Re: [PATCH v2 4/5] drm/xe/xe_ras: Add helper to clear error counter

["Tauro, Riana" <riana.tauro@intel.com>]

On 4/13/2026 2:55 PM, Raag Jadav wrote:
> On Mon, Apr 06, 2026 at 08:24:43PM +0530, Riana Tauro wrote:
>> Add helper function to clear error counter value.
>>
>> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
>> ---
>> Note: This will be integrated with drm_ras implementation
>> once clear-error-counter patch is merged.
>> https://patchwork.freedesktop.org/series/163019/
>> ---
>>   drivers/gpu/drm/xe/xe_ras.c | 48 +++++++++++++++++++++++++++++++++++++
>>   drivers/gpu/drm/xe/xe_ras.h |  2 ++
>>   2 files changed, 50 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
>> index b5fdad2c801d..56abcb9783a4 100644
>> --- a/drivers/gpu/drm/xe/xe_ras.c
>> +++ b/drivers/gpu/drm/xe/xe_ras.c
>> @@ -121,3 +121,51 @@ int xe_ras_get_error_counter(struct xe_device *xe, const enum drm_xe_ras_error_s
>>   	guard(xe_pm_runtime)(xe);
>>   	return get_error_counter(xe, &error_class, value);
>>   }
>> +
>> +/**
>> + * xe_ras_clear_error_counter() - Clear error counter value
>> + * @xe: xe device instance
>> + * @severity: Error severity level to be cleared
>> + * @error_id: Error component to be cleared
>> + *
>> + * This function clears the value of a specific RAS error counter based on
>> + * the provided severity and component.
>> + *
>> + * Return: 0 on success, negative error code on failure.
>> + */
>> +int xe_ras_clear_error_counter(struct xe_device *xe, const enum drm_xe_ras_error_severity severity,
>> +			       u32 error_id)
>> +{
>> +	struct xe_ras_clear_counter_response response = {0};
>> +	struct xe_ras_clear_counter_request request = {0};
>> +	struct xe_sysctrl_mailbox_command command = {0};
>> +	struct xe_ras_error_class *error_class = &request.error_class;
>> +	size_t rlen;
>> +	int ret;
>> +
>> +	error_class->common.severity = drm_to_xe_ras_severity[severity];
>> +	error_class->common.component = drm_to_xe_ras_component[error_id];
>> +
>> +	prepare_sysctrl_command(&command, XE_SYSCTRL_CMD_CLEAR_COUNTER, &request, sizeof(request),
>> +				&response, sizeof(response));
> Nit: Probably worth having a set_error_counter(), we never know when might
> need it :D

I did think about this while working on the drm_ras command . Since this 
is a error counter which is incremented for an error,
userspace shouldn't be allowed to set the count to anything other than 
0. So retained the command as clear

Riana
>
> Raag
>
>> +
>> +	guard(xe_pm_runtime)(xe);
>> +	ret = xe_sysctrl_send_command(&xe->sc, &command, &rlen);
>> +	if (ret) {
>> +		xe_err(xe, "[RAS]: Sysctrl error ret %d\n", ret);
>> +		return ret;
>> +	}
>> +
>> +	if (rlen != sizeof(response)) {
>> +		xe_err(xe, "[RAS]: Sysctrl response size mismatch. Expected %zu, got %zu\n",
>> +		       sizeof(response), rlen);
>> +		return -EINVAL;
>> +	}
>> +
>> +	if (response.status) {
>> +		xe_err(xe, "[RAS]: Sysctrl Failed to clear counter %u\n", response.status);
>> +		return -EIO;
>> +	}
>> +
>> +	return 0;
>> +}
>> diff --git a/drivers/gpu/drm/xe/xe_ras.h b/drivers/gpu/drm/xe/xe_ras.h
>> index e468c414148e..19e0e649d55f 100644
>> --- a/drivers/gpu/drm/xe/xe_ras.h
>> +++ b/drivers/gpu/drm/xe/xe_ras.h
>> @@ -12,5 +12,7 @@ struct xe_device;
>>   
>>   int xe_ras_get_error_counter(struct xe_device *xe, const enum drm_xe_ras_error_severity severity,
>>   			     u32 error_id, u32 *value);
>> +int xe_ras_clear_error_counter(struct xe_device *xe, const enum drm_xe_ras_error_severity severity,
>> +			       u32 error_id);
>>   
>>   #endif
>> -- 
>> 2.47.1
>>