[RFC PATCH 0/9] drm/i915/display: DC3CO support

[RFC PATCH 0/9] drm/i915/display: DC3CO support

[Dibin Moolakadan Subrahmanian]

Hi all,

This series introduces initial DC3CO DC state support,
replacing the existing PSR2-based TGL DC3CO design
(currently disabled).

The goal of this work is to move DC3CO handling out of PSR2-specific
code paths and into the core atomic display state flow, making the
behaviour consistent across PSR, ALPM and LOBF in line with the new
DC3CO design.

This series is posted as RFC to gather early feedback on the approach
before full integration.

Dibin Moolakadan Subrahmanian (9):
  drm/i915/display: Remove TGL DC3CO support
  drm/i915/display: Replace DC_STATE_EN_DC3CO with
    DC_STATE_EN_UPTO_DC3CO
  drm/i915/display: Add DC3CO enable/disable support
  drm/i915/display: Add DC3CO eligibility logic
  drm/i915/display: Track DC3CO enable source
  drm/i915/display: alpm enable DC3CO support
  drm/i915/display: psr enable DC3CO support
  drm/i915/display: Add intel_dc3co_can_enable() helper
  drm/i915/display: Add DC3CO disable handling for psr2

 drivers/gpu/drm/i915/display/intel_alpm.c     |   4 +
 drivers/gpu/drm/i915/display/intel_display.c  |  95 +++++++++
 drivers/gpu/drm/i915/display/intel_display.h  |   6 +-
 .../gpu/drm/i915/display/intel_display_core.h |   4 +
 .../drm/i915/display/intel_display_power.c    |  10 +-
 .../drm/i915/display/intel_display_power.h    |  10 +
 .../i915/display/intel_display_power_well.c   |  35 ++--
 .../gpu/drm/i915/display/intel_display_regs.h |   2 +-
 drivers/gpu/drm/i915/display/intel_dmc_wl.c   |   2 +-
 drivers/gpu/drm/i915/display/intel_psr.c      | 180 +++++-------------
 drivers/gpu/drm/i915/display/intel_psr_regs.h |   1 +
 11 files changed, 187 insertions(+), 162 deletions(-)

-- 
2.43.0

[PATCH 1/9] drm/i915/display: Remove TGL DC3CO support

[Dibin Moolakadan Subrahmanian]

Remove all Tiger Lake DC3CO-related functions, as the feature is no
longer used. The existing structure members are intentionally left in
place and will be cleaned up in subsequent patches.

Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
---
 .../i915/display/intel_display_power_well.c   |  25 ---
 .../drm/i915/display/intel_display_types.h    |   1 -
 drivers/gpu/drm/i915/display/intel_psr.c      | 163 ------------------
 3 files changed, 189 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index db185a859133..2dce622eb5d8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -821,23 +821,6 @@ void gen9_set_dc_state(struct intel_display *display, u32 state)
 	power_domains->dc_state = val & mask;
 }
 
-static void tgl_enable_dc3co(struct intel_display *display)
-{
-	drm_dbg_kms(display->drm, "Enabling DC3CO\n");
-	gen9_set_dc_state(display, DC_STATE_EN_DC3CO);
-}
-
-static void tgl_disable_dc3co(struct intel_display *display)
-{
-	drm_dbg_kms(display->drm, "Disabling DC3CO\n");
-	intel_de_rmw(display, DC_STATE_EN, DC_STATE_DC3CO_STATUS, 0);
-	gen9_set_dc_state(display, DC_STATE_DISABLE);
-	/*
-	 * Delay of 200us DC3CO Exit time B.Spec 49196
-	 */
-	usleep_range(200, 210);
-}
-
 static void assert_can_enable_dc5(struct intel_display *display)
 {
 	enum i915_power_well_id high_pg;
@@ -1016,11 +999,6 @@ void gen9_disable_dc_states(struct intel_display *display)
 	struct intel_cdclk_config cdclk_config = {};
 	u32 old_state = power_domains->dc_state;
 
-	if (power_domains->target_dc_state == DC_STATE_EN_DC3CO) {
-		tgl_disable_dc3co(display);
-		return;
-	}
-
 	if (HAS_DISPLAY(display)) {
 		intel_dmc_wl_get_noreg(display);
 		gen9_set_dc_state(display, DC_STATE_DISABLE);
@@ -1069,9 +1047,6 @@ static void gen9_dc_off_power_well_disable(struct intel_display *display,
 		return;
 
 	switch (power_domains->target_dc_state) {
-	case DC_STATE_EN_DC3CO:
-		tgl_enable_dc3co(display);
-		break;
 	case DC_STATE_EN_UPTO_DC6:
 		skl_enable_dc6(display);
 		break;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 6ff53cd58052..27f69df7ee9c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1759,7 +1759,6 @@ struct intel_psr {
 	bool panel_replay_enabled;
 	u32 dc3co_exitline;
 	u32 dc3co_exit_delay;
-	struct delayed_work dc3co_work;
 	u8 entry_setup_frames;
 
 	u8 io_wake_lines;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 2a378a5adc59..753359069044 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -85,22 +85,6 @@
  * issues the self-refresh re-enable code is done from a work queue, which
  * must be correctly synchronized/cancelled when shutting down the pipe."
  *
- * DC3CO (DC3 clock off)
- *
- * On top of PSR2, GEN12 adds a intermediate power savings state that turns
- * clock off automatically during PSR2 idle state.
- * The smaller overhead of DC3co entry/exit vs. the overhead of PSR2 deep sleep
- * entry/exit allows the HW to enter a low-power state even when page flipping
- * periodically (for instance a 30fps video playback scenario).
- *
- * Every time a flips occurs PSR2 will get out of deep sleep state(if it was),
- * so DC3CO is enabled and tgl_dc3co_disable_work is schedule to run after 6
- * frames, if no other flip occurs and the function above is executed, DC3CO is
- * disabled and PSR2 is configured to enter deep sleep, resetting again in case
- * of another flip.
- * Front buffer modifications do not trigger DC3CO activation on purpose as it
- * would bring a lot of complexity and most of the moderns systems will only
- * use page flips.
  */
 
 /*
@@ -1173,108 +1157,6 @@ static void psr2_program_idle_frames(struct intel_dp *intel_dp,
 		     EDP_PSR2_IDLE_FRAMES(idle_frames));
 }
 
-static void tgl_psr2_enable_dc3co(struct intel_dp *intel_dp)
-{
-	struct intel_display *display = to_intel_display(intel_dp);
-
-	psr2_program_idle_frames(intel_dp, 0);
-	intel_display_power_set_target_dc_state(display, DC_STATE_EN_DC3CO);
-}
-
-static void tgl_psr2_disable_dc3co(struct intel_dp *intel_dp)
-{
-	struct intel_display *display = to_intel_display(intel_dp);
-
-	intel_display_power_set_target_dc_state(display, DC_STATE_EN_UPTO_DC6);
-	psr2_program_idle_frames(intel_dp, psr_compute_idle_frames(intel_dp));
-}
-
-static void tgl_dc3co_disable_work(struct work_struct *work)
-{
-	struct intel_dp *intel_dp =
-		container_of(work, typeof(*intel_dp), psr.dc3co_work.work);
-
-	mutex_lock(&intel_dp->psr.lock);
-	/* If delayed work is pending, it is not idle */
-	if (delayed_work_pending(&intel_dp->psr.dc3co_work))
-		goto unlock;
-
-	tgl_psr2_disable_dc3co(intel_dp);
-unlock:
-	mutex_unlock(&intel_dp->psr.lock);
-}
-
-static void tgl_disallow_dc3co_on_psr2_exit(struct intel_dp *intel_dp)
-{
-	if (!intel_dp->psr.dc3co_exitline)
-		return;
-
-	cancel_delayed_work(&intel_dp->psr.dc3co_work);
-	/* Before PSR2 exit disallow dc3co*/
-	tgl_psr2_disable_dc3co(intel_dp);
-}
-
-static bool
-dc3co_is_pipe_port_compatible(struct intel_dp *intel_dp,
-			      struct intel_crtc_state *crtc_state)
-{
-	struct intel_display *display = to_intel_display(intel_dp);
-	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
-	enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
-	enum port port = dig_port->base.port;
-
-	if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14)
-		return pipe <= PIPE_B && port <= PORT_B;
-	else
-		return pipe == PIPE_A && port == PORT_A;
-}
-
-static void
-tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
-				  struct intel_crtc_state *crtc_state)
-{
-	struct intel_display *display = to_intel_display(intel_dp);
-	const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay;
-	struct i915_power_domains *power_domains = &display->power.domains;
-	u32 exit_scanlines;
-
-	/*
-	 * FIXME: Due to the changed sequence of activating/deactivating DC3CO,
-	 * disable DC3CO until the changed dc3co activating/deactivating sequence
-	 * is applied. B.Specs:49196
-	 */
-	return;
-
-	/*
-	 * DMC's DC3CO exit mechanism has an issue with Selective Fecth
-	 * TODO: when the issue is addressed, this restriction should be removed.
-	 */
-	if (crtc_state->enable_psr2_sel_fetch)
-		return;
-
-	if (!(power_domains->allowed_dc_mask & DC_STATE_EN_DC3CO))
-		return;
-
-	if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state))
-		return;
-
-	/* Wa_16011303918:adl-p */
-	if (display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0))
-		return;
-
-	/*
-	 * DC3CO Exit time 200us B.Spec 49196
-	 * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1
-	 */
-	exit_scanlines =
-		intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1;
-
-	if (drm_WARN_ON(display->drm, exit_scanlines > crtc_vdisplay))
-		return;
-
-	crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines;
-}
-
 static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
 					      struct intel_crtc_state *crtc_state)
 {
@@ -1613,8 +1495,6 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 		return false;
 	}
 
-	tgl_dc3co_exitline_compute_config(intel_dp, crtc_state);
-
 	return true;
 }
 
@@ -2063,16 +1943,6 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
 
 	psr_irq_control(intel_dp);
 
-	/*
-	 * TODO: if future platforms supports DC3CO in more than one
-	 * transcoder, EXITLINE will need to be unset when disabling PSR
-	 */
-	if (intel_dp->psr.dc3co_exitline)
-		intel_de_rmw(display,
-			     TRANS_EXITLINE(display, cpu_transcoder),
-			     EXITLINE_MASK,
-			     intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT | EXITLINE_ENABLE);
-
 	if (HAS_PSR_HW_TRACKING(display) && HAS_PSR2_SEL_FETCH(display))
 		intel_de_rmw(display, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING,
 			     intel_dp->psr.psr2_sel_fetch_enabled ?
@@ -2247,7 +2117,6 @@ static void intel_psr_exit(struct intel_dp *intel_dp)
 		intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder),
 			     TRANS_DP2_PANEL_REPLAY_ENABLE, 0);
 	} else if (intel_dp->psr.sel_update_enabled) {
-		tgl_disallow_dc3co_on_psr2_exit(intel_dp);
 
 		val = intel_de_rmw(display,
 				   EDP_PSR2_CTL(display, cpu_transcoder),
@@ -2390,7 +2259,6 @@ void intel_psr_disable(struct intel_dp *intel_dp,
 
 	mutex_unlock(&intel_dp->psr.lock);
 	cancel_work_sync(&intel_dp->psr.work);
-	cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);
 }
 
 /**
@@ -2421,7 +2289,6 @@ void intel_psr_pause(struct intel_dp *intel_dp)
 	mutex_unlock(&psr->lock);
 
 	cancel_work_sync(&psr->work);
-	cancel_delayed_work_sync(&psr->dc3co_work);
 }
 
 /**
@@ -3518,34 +3385,6 @@ void intel_psr_invalidate(struct intel_display *display,
 		mutex_unlock(&intel_dp->psr.lock);
 	}
 }
-/*
- * When we will be completely rely on PSR2 S/W tracking in future,
- * intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP
- * event also therefore tgl_dc3co_flush_locked() require to be changed
- * accordingly in future.
- */
-static void
-tgl_dc3co_flush_locked(struct intel_dp *intel_dp, unsigned int frontbuffer_bits,
-		       enum fb_op_origin origin)
-{
-	struct intel_display *display = to_intel_display(intel_dp);
-
-	if (!intel_dp->psr.dc3co_exitline || !intel_dp->psr.sel_update_enabled ||
-	    !intel_dp->psr.active)
-		return;
-
-	/*
-	 * At every frontbuffer flush flip event modified delay of delayed work,
-	 * when delayed work schedules that means display has been idle.
-	 */
-	if (!(frontbuffer_bits &
-	    INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe)))
-		return;
-
-	tgl_psr2_enable_dc3co(intel_dp);
-	mod_delayed_work(display->wq.unordered, &intel_dp->psr.dc3co_work,
-			 intel_dp->psr.dc3co_exit_delay);
-}
 
 static void _psr_flush_handle(struct intel_dp *intel_dp)
 {
@@ -3630,7 +3469,6 @@ void intel_psr_flush(struct intel_display *display,
 		if (origin == ORIGIN_FLIP ||
 		    (origin == ORIGIN_CURSOR_UPDATE &&
 		     !intel_dp->psr.psr2_sel_fetch_enabled)) {
-			tgl_dc3co_flush_locked(intel_dp, frontbuffer_bits, origin);
 			goto unlock;
 		}
 
@@ -3689,7 +3527,6 @@ void intel_psr_init(struct intel_dp *intel_dp)
 		intel_dp->psr.link_standby = connector->panel.vbt.psr.full_link;
 
 	INIT_WORK(&intel_dp->psr.work, intel_psr_work);
-	INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work);
 	mutex_init(&intel_dp->psr.lock);
 }
 
-- 
2.43.0

[PATCH 2/9] drm/i915/display: Replace DC_STATE_EN_DC3CO with DC_STATE_EN_UPTO_DC3CO

[Dibin Moolakadan Subrahmanian]

DC3CO no longer uses a standalone enable bit but part of existing
UPTO_DC* enable bits.

Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power.c      | 6 +++---
 drivers/gpu/drm/i915/display/intel_display_power_well.c | 4 ++--
 drivers/gpu/drm/i915/display/intel_display_regs.h       | 2 +-
 drivers/gpu/drm/i915/display/intel_dmc_wl.c             | 2 +-
 4 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 9f323c39d798..0961b194554c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -267,7 +267,7 @@ sanitize_target_dc_state(struct intel_display *display,
 	static const u32 states[] = {
 		DC_STATE_EN_UPTO_DC6,
 		DC_STATE_EN_UPTO_DC5,
-		DC_STATE_EN_DC3CO,
+		DC_STATE_EN_UPTO_DC3CO,
 		DC_STATE_DISABLE,
 	};
 	int i;
@@ -999,10 +999,10 @@ static u32 get_allowed_dc_mask(struct intel_display *display, int enable_dc)
 
 	switch (requested_dc) {
 	case 4:
-		mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6;
+		mask |= DC_STATE_EN_UPTO_DC3CO | DC_STATE_EN_UPTO_DC6;
 		break;
 	case 3:
-		mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC5;
+		mask |= DC_STATE_EN_UPTO_DC3CO | DC_STATE_EN_UPTO_DC5;
 		break;
 	case 2:
 		mask |= DC_STATE_EN_UPTO_DC6;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 2dce622eb5d8..6f62a4420f6e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -727,7 +727,7 @@ static u32 gen9_dc_mask(struct intel_display *display)
 	mask = DC_STATE_EN_UPTO_DC5;
 
 	if (DISPLAY_VER(display) >= 12)
-		mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6
+		mask |= DC_STATE_EN_UPTO_DC3CO | DC_STATE_EN_UPTO_DC6
 					  | DC_STATE_EN_DC9;
 	else if (DISPLAY_VER(display) == 11)
 		mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
@@ -977,7 +977,7 @@ static void bxt_verify_dpio_phy_power_wells(struct intel_display *display)
 static bool gen9_dc_off_power_well_enabled(struct intel_display *display,
 					   struct i915_power_well *power_well)
 {
-	return ((intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&
+	return ((intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_UPTO_DC3CO) == 0 &&
 		(intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 9e0d853f4b61..7e620e22718b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -2819,13 +2819,13 @@ enum skl_power_gate {
 /* GEN9 DC */
 #define DC_STATE_EN			_MMIO(0x45504)
 #define  DC_STATE_DISABLE		0
-#define  DC_STATE_EN_DC3CO		REG_BIT(30)
 #define  DC_STATE_DC3CO_STATUS		REG_BIT(29)
 #define  HOLD_PHY_CLKREQ_PG1_LATCH	REG_BIT(21)
 #define  HOLD_PHY_PG1_LATCH		REG_BIT(20)
 #define  DC_STATE_EN_UPTO_DC5		(1 << 0)
 #define  DC_STATE_EN_DC9		(1 << 3)
 #define  DC_STATE_EN_UPTO_DC6		(2 << 0)
+#define  DC_STATE_EN_UPTO_DC3CO		(3 << 0)
 #define  DC_STATE_EN_UPTO_DC5_DC6_MASK   0x3
 
 #define  DC_STATE_DEBUG                  _MMIO(0x45520)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
index 73a3101514f3..9f403b7820ab 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
@@ -260,7 +260,7 @@ static bool intel_dmc_wl_check_range(struct intel_display *display,
 	 * the DMC and requires a DC exit for proper access.
 	 */
 	switch (dc_state) {
-	case DC_STATE_EN_DC3CO:
+	case DC_STATE_EN_UPTO_DC3CO:
 		ranges = xe3lpd_dc3co_dmc_ranges;
 		break;
 	case DC_STATE_EN_UPTO_DC5:
-- 
2.43.0

Re: [PATCH 2/9] drm/i915/display: Replace DC_STATE_EN_DC3CO with DC_STATE_EN_UPTO_DC3CO

[Jani Nikula]

On Tue, 09 Dec 2025, Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com> wrote:
> DC3CO no longer uses a standalone enable bit but part of existing
> UPTO_DC* enable bits.

"no longer" for register contents absolutely requires references to the
platforms.

>
> Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_power.c      | 6 +++---
>  drivers/gpu/drm/i915/display/intel_display_power_well.c | 4 ++--
>  drivers/gpu/drm/i915/display/intel_display_regs.h       | 2 +-
>  drivers/gpu/drm/i915/display/intel_dmc_wl.c             | 2 +-
>  4 files changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 9f323c39d798..0961b194554c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -267,7 +267,7 @@ sanitize_target_dc_state(struct intel_display *display,
>  	static const u32 states[] = {
>  		DC_STATE_EN_UPTO_DC6,
>  		DC_STATE_EN_UPTO_DC5,
> -		DC_STATE_EN_DC3CO,
> +		DC_STATE_EN_UPTO_DC3CO,
>  		DC_STATE_DISABLE,
>  	};
>  	int i;
> @@ -999,10 +999,10 @@ static u32 get_allowed_dc_mask(struct intel_display *display, int enable_dc)
>  
>  	switch (requested_dc) {
>  	case 4:
> -		mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6;
> +		mask |= DC_STATE_EN_UPTO_DC3CO | DC_STATE_EN_UPTO_DC6;
>  		break;
>  	case 3:
> -		mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC5;
> +		mask |= DC_STATE_EN_UPTO_DC3CO | DC_STATE_EN_UPTO_DC5;
>  		break;
>  	case 2:
>  		mask |= DC_STATE_EN_UPTO_DC6;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 2dce622eb5d8..6f62a4420f6e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -727,7 +727,7 @@ static u32 gen9_dc_mask(struct intel_display *display)
>  	mask = DC_STATE_EN_UPTO_DC5;
>  
>  	if (DISPLAY_VER(display) >= 12)
> -		mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6
> +		mask |= DC_STATE_EN_UPTO_DC3CO | DC_STATE_EN_UPTO_DC6
>  					  | DC_STATE_EN_DC9;
>  	else if (DISPLAY_VER(display) == 11)
>  		mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
> @@ -977,7 +977,7 @@ static void bxt_verify_dpio_phy_power_wells(struct intel_display *display)
>  static bool gen9_dc_off_power_well_enabled(struct intel_display *display,
>  					   struct i915_power_well *power_well)
>  {
> -	return ((intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&
> +	return ((intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_UPTO_DC3CO) == 0 &&
>  		(intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 9e0d853f4b61..7e620e22718b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -2819,13 +2819,13 @@ enum skl_power_gate {
>  /* GEN9 DC */
>  #define DC_STATE_EN			_MMIO(0x45504)
>  #define  DC_STATE_DISABLE		0
> -#define  DC_STATE_EN_DC3CO		REG_BIT(30)
>  #define  DC_STATE_DC3CO_STATUS		REG_BIT(29)
>  #define  HOLD_PHY_CLKREQ_PG1_LATCH	REG_BIT(21)
>  #define  HOLD_PHY_PG1_LATCH		REG_BIT(20)
>  #define  DC_STATE_EN_UPTO_DC5		(1 << 0)
>  #define  DC_STATE_EN_DC9		(1 << 3)
>  #define  DC_STATE_EN_UPTO_DC6		(2 << 0)
> +#define  DC_STATE_EN_UPTO_DC3CO		(3 << 0)

This could use a conversion to REG_FIELD_MASK and REG_FIELD_PREP.

>  #define  DC_STATE_EN_UPTO_DC5_DC6_MASK   0x3
>  
>  #define  DC_STATE_DEBUG                  _MMIO(0x45520)
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> index 73a3101514f3..9f403b7820ab 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> @@ -260,7 +260,7 @@ static bool intel_dmc_wl_check_range(struct intel_display *display,
>  	 * the DMC and requires a DC exit for proper access.
>  	 */
>  	switch (dc_state) {
> -	case DC_STATE_EN_DC3CO:
> +	case DC_STATE_EN_UPTO_DC3CO:
>  		ranges = xe3lpd_dc3co_dmc_ranges;
>  		break;
>  	case DC_STATE_EN_UPTO_DC5:

-- 
Jani Nikula, Intel

Re: [PATCH 2/9] drm/i915/display: Replace DC_STATE_EN_DC3CO with DC_STATE_EN_UPTO_DC3CO

[Dibin Moolakadan Subrahmanian]

[-- Attachment #1: Type: text/plain, Size: 4608 bytes --]


On 05-01-2026 18:15, Jani Nikula wrote:
> On Tue, 09 Dec 2025, Dibin Moolakadan Subrahmanian<dibin.moolakadan.subrahmanian@intel.com> wrote:
>> DC3CO no longer uses a standalone enable bit but part of existing
>> UPTO_DC* enable bits.
> "no longer" for register contents absolutely requires references to the
> platforms.

I will add platform details here.

Regards,
Dibin

>> Signed-off-by: Dibin Moolakadan Subrahmanian<dibin.moolakadan.subrahmanian@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_display_power.c      | 6 +++---
>>   drivers/gpu/drm/i915/display/intel_display_power_well.c | 4 ++--
>>   drivers/gpu/drm/i915/display/intel_display_regs.h       | 2 +-
>>   drivers/gpu/drm/i915/display/intel_dmc_wl.c             | 2 +-
>>   4 files changed, 7 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>> index 9f323c39d798..0961b194554c 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>> @@ -267,7 +267,7 @@ sanitize_target_dc_state(struct intel_display *display,
>>   	static const u32 states[] = {
>>   		DC_STATE_EN_UPTO_DC6,
>>   		DC_STATE_EN_UPTO_DC5,
>> -		DC_STATE_EN_DC3CO,
>> +		DC_STATE_EN_UPTO_DC3CO,
>>   		DC_STATE_DISABLE,
>>   	};
>>   	int i;
>> @@ -999,10 +999,10 @@ static u32 get_allowed_dc_mask(struct intel_display *display, int enable_dc)
>>   
>>   	switch (requested_dc) {
>>   	case 4:
>> -		mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6;
>> +		mask |= DC_STATE_EN_UPTO_DC3CO | DC_STATE_EN_UPTO_DC6;
>>   		break;
>>   	case 3:
>> -		mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC5;
>> +		mask |= DC_STATE_EN_UPTO_DC3CO | DC_STATE_EN_UPTO_DC5;
>>   		break;
>>   	case 2:
>>   		mask |= DC_STATE_EN_UPTO_DC6;
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
>> index 2dce622eb5d8..6f62a4420f6e 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
>> @@ -727,7 +727,7 @@ static u32 gen9_dc_mask(struct intel_display *display)
>>   	mask = DC_STATE_EN_UPTO_DC5;
>>   
>>   	if (DISPLAY_VER(display) >= 12)
>> -		mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6
>> +		mask |= DC_STATE_EN_UPTO_DC3CO | DC_STATE_EN_UPTO_DC6
>>   					  | DC_STATE_EN_DC9;
>>   	else if (DISPLAY_VER(display) == 11)
>>   		mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
>> @@ -977,7 +977,7 @@ static void bxt_verify_dpio_phy_power_wells(struct intel_display *display)
>>   static bool gen9_dc_off_power_well_enabled(struct intel_display *display,
>>   					   struct i915_power_well *power_well)
>>   {
>> -	return ((intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&
>> +	return ((intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_UPTO_DC3CO) == 0 &&
>>   		(intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
>>   }
>>   
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
>> index 9e0d853f4b61..7e620e22718b 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
>> @@ -2819,13 +2819,13 @@ enum skl_power_gate {
>>   /* GEN9 DC */
>>   #define DC_STATE_EN			_MMIO(0x45504)
>>   #define  DC_STATE_DISABLE		0
>> -#define  DC_STATE_EN_DC3CO		REG_BIT(30)
>>   #define  DC_STATE_DC3CO_STATUS		REG_BIT(29)
>>   #define  HOLD_PHY_CLKREQ_PG1_LATCH	REG_BIT(21)
>>   #define  HOLD_PHY_PG1_LATCH		REG_BIT(20)
>>   #define  DC_STATE_EN_UPTO_DC5		(1 << 0)
>>   #define  DC_STATE_EN_DC9		(1 << 3)
>>   #define  DC_STATE_EN_UPTO_DC6		(2 << 0)
>> +#define  DC_STATE_EN_UPTO_DC3CO		(3 << 0)
> This could use a conversion to REG_FIELD_MASK and REG_FIELD_PREP.
>
>>   #define  DC_STATE_EN_UPTO_DC5_DC6_MASK   0x3
>>   
>>   #define  DC_STATE_DEBUG                  _MMIO(0x45520)
>> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
>> index 73a3101514f3..9f403b7820ab 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
>> @@ -260,7 +260,7 @@ static bool intel_dmc_wl_check_range(struct intel_display *display,
>>   	 * the DMC and requires a DC exit for proper access.
>>   	 */
>>   	switch (dc_state) {
>> -	case DC_STATE_EN_DC3CO:
>> +	case DC_STATE_EN_UPTO_DC3CO:
>>   		ranges = xe3lpd_dc3co_dmc_ranges;
>>   		break;
>>   	case DC_STATE_EN_UPTO_DC5:

[-- Attachment #2: Type: text/html, Size: 5523 bytes --]

[PATCH 3/9] drm/i915/display: Add DC3CO enable/disable support

[Dibin Moolakadan Subrahmanian]

Add explicit handling for DC3CO in the dc_off power well sequencing.
Introduce xe3lpd_enable_dc3co() and wire it into the dc_off power
enable flow. gen9_disable_dc_states() is also updated to disable the
corresponding DMC wakelock when transitioning out of DC3CO.

Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
---
 .../drm/i915/display/intel_display_power_well.c  | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 6f62a4420f6e..6d8d9d7b7d0a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -821,6 +821,13 @@ void gen9_set_dc_state(struct intel_display *display, u32 state)
 	power_domains->dc_state = val & mask;
 }
 
+static void xe3lpd_enable_dc3co(struct intel_display *display)
+{
+	drm_dbg_kms(display->drm, "Enabling DC3CO\n");
+	intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC3CO);
+	gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC3CO);
+}
+
 static void assert_can_enable_dc5(struct intel_display *display)
 {
 	enum i915_power_well_id high_pg;
@@ -1009,9 +1016,13 @@ void gen9_disable_dc_states(struct intel_display *display)
 	}
 
 	if (old_state == DC_STATE_EN_UPTO_DC5 ||
-	    old_state == DC_STATE_EN_UPTO_DC6)
+	    old_state == DC_STATE_EN_UPTO_DC6 ||
+	    old_state == DC_STATE_EN_UPTO_DC3CO)
 		intel_dmc_wl_disable(display);
 
+	if (old_state == DC_STATE_EN_UPTO_DC3CO)
+		return;
+
 	intel_cdclk_get_cdclk(display, &cdclk_config);
 	/* Can't read out voltage_level so can't use intel_cdclk_changed() */
 	drm_WARN_ON(display->drm,
@@ -1047,6 +1058,9 @@ static void gen9_dc_off_power_well_disable(struct intel_display *display,
 		return;
 
 	switch (power_domains->target_dc_state) {
+	case DC_STATE_EN_UPTO_DC3CO:
+		xe3lpd_enable_dc3co(display);
+		break;
 	case DC_STATE_EN_UPTO_DC6:
 		skl_enable_dc6(display);
 		break;
-- 
2.43.0

[PATCH 4/9] drm/i915/display: Add DC3CO eligibility logic

[Dibin Moolakadan Subrahmanian]

Introduce dc3co_allow in struct intel_display and determine DC3CO
eligibility during atomic_check(). DC3CO is permitted only when:

  - the active pipe drives eDP,
  - the pipe is single-pipe (no joiner),
  - the pipe/port combination supports DC3CO.

When eligible, intel_atomic_commit_tail() programs the target DC state
as DC_STATE_EN_UPTO_DC3CO; otherwise we fall back to DC6. Update the
PSR vblank enable/disable path to follow the same policy.

Also extend get_allowed_dc_mask() to expose DC3CO support on
DISPLAY_VER >= 35.

Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  | 75 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_display.h  |  1 +
 .../gpu/drm/i915/display/intel_display_core.h |  3 +
 .../drm/i915/display/intel_display_power.c    |  4 +-
 drivers/gpu/drm/i915/display/intel_psr.c      | 13 ++--
 5 files changed, 87 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 9c6d3ecdb589..205f55a87736 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6295,6 +6295,75 @@ static int intel_joiner_add_affected_crtcs(struct intel_atomic_state *state)
 	return 0;
 }
 
+bool intel_dc3co_allowed(struct intel_display *display)
+{
+	return display->power.dc3co_allow;
+}
+
+static bool intel_dc3co_port_pipe_compatible(struct intel_dp *intel_dp,
+					     const struct intel_crtc_state *crtc_state)
+{
+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+	enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
+	enum port port = dig_port->base.port;
+	int num_pipes = intel_crtc_num_joined_pipes(crtc_state);
+
+	if (num_pipes != 1)
+		return false;
+
+	if (!(pipe <= PIPE_B && port <= PORT_B))
+		return false;
+
+	return true;
+}
+
+static void intel_dc3co_allow_check(struct intel_atomic_state *state)
+{
+	struct intel_display *display = to_intel_display(state);
+	struct intel_crtc *crtc;
+	struct intel_crtc_state *new_crtc_state;
+	struct intel_encoder *encoder;
+	struct intel_dp *intel_dp;
+	int i;
+	struct i915_power_domains *power_domains = &display->power.domains;
+	bool any_active = false;
+	bool allow = true;
+
+	display->power.dc3co_allow = 0;
+
+	if ((power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC3CO) != DC_STATE_EN_UPTO_DC3CO)
+		return;
+
+	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+		if (!new_crtc_state->hw.active)
+			continue;
+
+		any_active = true;
+
+		for_each_intel_encoder_mask(display->drm, encoder,
+					    new_crtc_state->uapi.encoder_mask) {
+			/* If any active pipe not eDP disable*/
+			if (!intel_encoder_is_dp(encoder) ||
+			    encoder->type != INTEL_OUTPUT_EDP) {
+				allow = false;
+				goto out;
+			}
+			intel_dp = enc_to_intel_dp(encoder);
+			/* Port, joiner, pipe placement checks */
+			if (!intel_dc3co_port_pipe_compatible(intel_dp, new_crtc_state)) {
+				allow = false;
+				goto out;
+			}
+		}
+	}
+
+	if (!any_active)
+		allow = false;
+
+out:
+	display->power.dc3co_allow = allow;
+}
+
 static int intel_atomic_check_config(struct intel_atomic_state *state,
 				     struct intel_link_bw_limits *limits,
 				     enum pipe *failed_pipe)
@@ -6565,6 +6634,8 @@ int intel_atomic_check(struct drm_device *dev,
 	if (ret)
 		goto fail;
 
+	intel_dc3co_allow_check(state);
+
 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
 					    new_crtc_state, i) {
 		intel_color_assert_luts(new_crtc_state);
@@ -7601,6 +7672,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 		 */
 		intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
 	}
+	if (intel_dc3co_allowed(display))
+		intel_display_power_set_target_dc_state(display, DC_STATE_EN_UPTO_DC3CO);
+	else
+		intel_display_power_set_target_dc_state(display, DC_STATE_EN_UPTO_DC6);
 	/*
 	 * Delay re-enabling DC states by 17 ms to avoid the off->on->off
 	 * toggling overhead at and above 60 FPS.
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index f8e6e4e82722..97987f082560 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -560,5 +560,6 @@ bool assert_port_valid(struct intel_display *display, enum port port);
 
 bool intel_scanout_needs_vtd_wa(struct intel_display *display);
 int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state);
+bool intel_dc3co_allowed(struct intel_display *display);
 
 #endif
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index d708d322aa85..fa567c95029c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -538,6 +538,9 @@ struct intel_display {
 
 		/* perform PHY state sanity checks? */
 		bool chv_phy_assert[2];
+
+		/* mark dc3co entry is allowed*/
+		bool dc3co_allow;
 	} power;
 
 	struct {
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 0961b194554c..e99552f18756 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -956,7 +956,9 @@ static u32 get_allowed_dc_mask(struct intel_display *display, int enable_dc)
 	if (!HAS_DISPLAY(display))
 		return 0;
 
-	if (DISPLAY_VER(display) >= 20)
+	if (DISPLAY_VER(display) >= 35)
+		max_dc = 3;
+	else if (DISPLAY_VER(display) >= 20)
 		max_dc = 2;
 	else if (display->platform.dg2)
 		max_dc = 1;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 753359069044..9c616f449ad6 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -3903,14 +3903,11 @@ void intel_psr_notify_vblank_enable_disable(struct intel_display *display,
 		return;
 	}
 
-	/*
-	 * NOTE: intel_display_power_set_target_dc_state is used
-	 * only by PSR * code for DC3CO handling. DC3CO target
-	 * state is currently disabled in * PSR code. If DC3CO
-	 * is taken into use we need take that into account here
-	 * as well.
-	 */
-	intel_display_power_set_target_dc_state(display, enable ? DC_STATE_DISABLE :
+	if (intel_dc3co_allowed(display))
+		intel_display_power_set_target_dc_state(display, enable ? DC_STATE_DISABLE :
+						DC_STATE_EN_UPTO_DC3CO);
+	else
+		intel_display_power_set_target_dc_state(display, enable ? DC_STATE_DISABLE :
 						DC_STATE_EN_UPTO_DC6);
 }
 
-- 
2.43.0

Re: [PATCH 4/9] drm/i915/display: Add DC3CO eligibility logic

[Jani Nikula]

On Tue, 09 Dec 2025, Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com> wrote:
> Introduce dc3co_allow in struct intel_display and determine DC3CO
> eligibility during atomic_check(). DC3CO is permitted only when:
>
>   - the active pipe drives eDP,
>   - the pipe is single-pipe (no joiner),
>   - the pipe/port combination supports DC3CO.
>
> When eligible, intel_atomic_commit_tail() programs the target DC state
> as DC_STATE_EN_UPTO_DC3CO; otherwise we fall back to DC6. Update the
> PSR vblank enable/disable path to follow the same policy.
>
> Also extend get_allowed_dc_mask() to expose DC3CO support on
> DISPLAY_VER >= 35.
>
> Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c  | 75 +++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_display.h  |  1 +
>  .../gpu/drm/i915/display/intel_display_core.h |  3 +
>  .../drm/i915/display/intel_display_power.c    |  4 +-
>  drivers/gpu/drm/i915/display/intel_psr.c      | 13 ++--
>  5 files changed, 87 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 9c6d3ecdb589..205f55a87736 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6295,6 +6295,75 @@ static int intel_joiner_add_affected_crtcs(struct intel_atomic_state *state)
>  	return 0;
>  }
>  
> +bool intel_dc3co_allowed(struct intel_display *display)
> +{
> +	return display->power.dc3co_allow;

Very few files should touch display->power, and this is not one of them.

'git grep "display->power" -- drivers/gpu/drm/i915/display'

When is it okay to call this function and expect to get sane results?

> +}
> +
> +static bool intel_dc3co_port_pipe_compatible(struct intel_dp *intel_dp,
> +					     const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> +	enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
> +	enum port port = dig_port->base.port;
> +	int num_pipes = intel_crtc_num_joined_pipes(crtc_state);
> +
> +	if (num_pipes != 1)
> +		return false;
> +
> +	if (!(pipe <= PIPE_B && port <= PORT_B))
> +		return false;
> +
> +	return true;

That's a really complicated way to say

	return num_pipes == 1 && pipe <= PIPEB && port <= PORT_B;

> +}
> +
> +static void intel_dc3co_allow_check(struct intel_atomic_state *state)

What does "check" mean here? Or in *any* function?

Check sounds like something that's a pure function that doesn't change
anything... but this does.

> +{
> +	struct intel_display *display = to_intel_display(state);
> +	struct intel_crtc *crtc;
> +	struct intel_crtc_state *new_crtc_state;
> +	struct intel_encoder *encoder;
> +	struct intel_dp *intel_dp;
> +	int i;
> +	struct i915_power_domains *power_domains = &display->power.domains;
> +	bool any_active = false;
> +	bool allow = true;
> +
> +	display->power.dc3co_allow = 0;

That's now cached state with no stated rules on when it's valid and when
it's not.

> +
> +	if ((power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC3CO) != DC_STATE_EN_UPTO_DC3CO)
> +		return;
> +
> +	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> +		if (!new_crtc_state->hw.active)
> +			continue;
> +
> +		any_active = true;
> +
> +		for_each_intel_encoder_mask(display->drm, encoder,
> +					    new_crtc_state->uapi.encoder_mask) {
> +			/* If any active pipe not eDP disable*/

What?

> +			if (!intel_encoder_is_dp(encoder) ||
> +			    encoder->type != INTEL_OUTPUT_EDP) {
> +				allow = false;
> +				goto out;
> +			}
> +			intel_dp = enc_to_intel_dp(encoder);
> +			/* Port, joiner, pipe placement checks */

Is that a helpful comment?

> +			if (!intel_dc3co_port_pipe_compatible(intel_dp, new_crtc_state)) {
> +				allow = false;
> +				goto out;
> +			}
> +		}
> +	}
> +
> +	if (!any_active)
> +		allow = false;
> +
> +out:
> +	display->power.dc3co_allow = allow;
> +}
> +

intel_display.[ch] is not the dumping ground for random new code. The
goal is to *reduce* the size of it, not increase.

>  static int intel_atomic_check_config(struct intel_atomic_state *state,
>  				     struct intel_link_bw_limits *limits,
>  				     enum pipe *failed_pipe)
> @@ -6565,6 +6634,8 @@ int intel_atomic_check(struct drm_device *dev,
>  	if (ret)
>  		goto fail;
>  
> +	intel_dc3co_allow_check(state);
> +
>  	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
>  					    new_crtc_state, i) {
>  		intel_color_assert_luts(new_crtc_state);
> @@ -7601,6 +7672,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  		 */
>  		intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
>  	}
> +	if (intel_dc3co_allowed(display))
> +		intel_display_power_set_target_dc_state(display, DC_STATE_EN_UPTO_DC3CO);
> +	else
> +		intel_display_power_set_target_dc_state(display, DC_STATE_EN_UPTO_DC6);
>  	/*
>  	 * Delay re-enabling DC states by 17 ms to avoid the off->on->off
>  	 * toggling overhead at and above 60 FPS.
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index f8e6e4e82722..97987f082560 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -560,5 +560,6 @@ bool assert_port_valid(struct intel_display *display, enum port port);
>  
>  bool intel_scanout_needs_vtd_wa(struct intel_display *display);
>  int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state);
> +bool intel_dc3co_allowed(struct intel_display *display);
>  
>  #endif
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> index d708d322aa85..fa567c95029c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -538,6 +538,9 @@ struct intel_display {
>  
>  		/* perform PHY state sanity checks? */
>  		bool chv_phy_assert[2];
> +
> +		/* mark dc3co entry is allowed*/

		                              ^- space missing

> +		bool dc3co_allow;

Still unclear when this is valid.

>  	} power;
>  
>  	struct {
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 0961b194554c..e99552f18756 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -956,7 +956,9 @@ static u32 get_allowed_dc_mask(struct intel_display *display, int enable_dc)
>  	if (!HAS_DISPLAY(display))
>  		return 0;
>  
> -	if (DISPLAY_VER(display) >= 20)
> +	if (DISPLAY_VER(display) >= 35)
> +		max_dc = 3;
> +	else if (DISPLAY_VER(display) >= 20)
>  		max_dc = 2;
>  	else if (display->platform.dg2)
>  		max_dc = 1;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 753359069044..9c616f449ad6 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -3903,14 +3903,11 @@ void intel_psr_notify_vblank_enable_disable(struct intel_display *display,
>  		return;
>  	}
>  
> -	/*
> -	 * NOTE: intel_display_power_set_target_dc_state is used
> -	 * only by PSR * code for DC3CO handling. DC3CO target
> -	 * state is currently disabled in * PSR code. If DC3CO
> -	 * is taken into use we need take that into account here
> -	 * as well.
> -	 */
> -	intel_display_power_set_target_dc_state(display, enable ? DC_STATE_DISABLE :
> +	if (intel_dc3co_allowed(display))
> +		intel_display_power_set_target_dc_state(display, enable ? DC_STATE_DISABLE :
> +						DC_STATE_EN_UPTO_DC3CO);
> +	else
> +		intel_display_power_set_target_dc_state(display, enable ? DC_STATE_DISABLE :
>  						DC_STATE_EN_UPTO_DC6);
>  }

-- 
Jani Nikula, Intel

Re: [PATCH 4/9] drm/i915/display: Add DC3CO eligibility logic

[Dibin Moolakadan Subrahmanian]

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On 05-01-2026 18:25, Jani Nikula wrote:
> On Tue, 09 Dec 2025, Dibin Moolakadan Subrahmanian<dibin.moolakadan.subrahmanian@intel.com> wrote:
>> Introduce dc3co_allow in struct intel_display and determine DC3CO
>> eligibility during atomic_check(). DC3CO is permitted only when:
>>
>>    - the active pipe drives eDP,
>>    - the pipe is single-pipe (no joiner),
>>    - the pipe/port combination supports DC3CO.
>>
>> When eligible, intel_atomic_commit_tail() programs the target DC state
>> as DC_STATE_EN_UPTO_DC3CO; otherwise we fall back to DC6. Update the
>> PSR vblank enable/disable path to follow the same policy.
>>
>> Also extend get_allowed_dc_mask() to expose DC3CO support on
>> DISPLAY_VER >= 35.
>>
>> Signed-off-by: Dibin Moolakadan Subrahmanian<dibin.moolakadan.subrahmanian@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_display.c  | 75 +++++++++++++++++++
>>   drivers/gpu/drm/i915/display/intel_display.h  |  1 +
>>   .../gpu/drm/i915/display/intel_display_core.h |  3 +
>>   .../drm/i915/display/intel_display_power.c    |  4 +-
>>   drivers/gpu/drm/i915/display/intel_psr.c      | 13 ++--
>>   5 files changed, 87 insertions(+), 9 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index 9c6d3ecdb589..205f55a87736 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -6295,6 +6295,75 @@ static int intel_joiner_add_affected_crtcs(struct intel_atomic_state *state)
>>   	return 0;
>>   }
>>   
>> +bool intel_dc3co_allowed(struct intel_display *display)
>> +{
>> +	return display->power.dc3co_allow;
> Very few files should touch display->power, and this is not one of them.
>
> 'git grep "display->power" -- drivers/gpu/drm/i915/display'

Yes, git grep shows few files , I will try to move all dc3co functions to
drivers/gpu/drm/i915/display/intel_display_power.c.

>
> When is it okay to call this function and expect to get sane results?

display->power.dc3co_allow is only updated in intel_dc3co_allow_check() which is called from
intel_atomic_commit_tail().intel_dc3co_allowed() only intended to be called from intel_post_plane_update()
path(ALPM/PSR), which executes as part of intel_atomic_commit_tail().

>
>> +}
>> +
>> +static bool intel_dc3co_port_pipe_compatible(struct intel_dp *intel_dp,
>> +					     const struct intel_crtc_state *crtc_state)
>> +{
>> +	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>> +	enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
>> +	enum port port = dig_port->base.port;
>> +	int num_pipes = intel_crtc_num_joined_pipes(crtc_state);
>> +
>> +	if (num_pipes != 1)
>> +		return false;
>> +
>> +	if (!(pipe <= PIPE_B && port <= PORT_B))
>> +		return false;
>> +
>> +	return true;
> That's a really complicated way to say
>
> 	return num_pipes == 1 && pipe <= PIPEB && port <= PORT_B;

I will update this.

>
>> +}
>> +
>> +static void intel_dc3co_allow_check(struct intel_atomic_state *state)
> What does "check" mean here? Or in *any* function?
>
> Check sounds like something that's a pure function that doesn't change
> anything... but this does.

I will split this function to two , one for check and one for initialization

>> +{
>> +	struct intel_display *display = to_intel_display(state);
>> +	struct intel_crtc *crtc;
>> +	struct intel_crtc_state *new_crtc_state;
>> +	struct intel_encoder *encoder;
>> +	struct intel_dp *intel_dp;
>> +	int i;
>> +	struct i915_power_domains *power_domains = &display->power.domains;
>> +	bool any_active = false;
>> +	bool allow = true;
>> +
>> +	display->power.dc3co_allow = 0;
> That's now cached state with no stated rules on when it's valid and when
> it's not.
>
>> +
>> +	if ((power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC3CO) != DC_STATE_EN_UPTO_DC3CO)
>> +		return;
>> +
>> +	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
>> +		if (!new_crtc_state->hw.active)
>> +			continue;
>> +
>> +		any_active = true;
>> +
>> +		for_each_intel_encoder_mask(display->drm, encoder,
>> +					    new_crtc_state->uapi.encoder_mask) {
>> +			/* If any active pipe not eDP disable*/
> What?

I will correct comment /* Disallow DC3CO if any active pipe is not eDP */

>
>> +			if (!intel_encoder_is_dp(encoder) ||
>> +			    encoder->type != INTEL_OUTPUT_EDP) {
>> +				allow = false;
>> +				goto out;
>> +			}
>> +			intel_dp = enc_to_intel_dp(encoder);
>> +			/* Port, joiner, pipe placement checks */
> Is that a helpful comment?
>
>> +			if (!intel_dc3co_port_pipe_compatible(intel_dp, new_crtc_state)) {
>> +				allow = false;
>> +				goto out;
>> +			}
>> +		}
>> +	}
>> +
>> +	if (!any_active)
>> +		allow = false;
>> +
>> +out:
>> +	display->power.dc3co_allow = allow;
>> +}
>> +
> intel_display.[ch] is not the dumping ground for random new code. The
> goal is to *reduce* the size of it, not increase.

This function needs encoder,port and pipe information, which is why I added
it in intel_display.c.However,I agree it is updating dc3co_allow . I will check if
it can be moved to intel_display_power.c.

>
>>   static int intel_atomic_check_config(struct intel_atomic_state *state,
>>   				     struct intel_link_bw_limits *limits,
>>   				     enum pipe *failed_pipe)
>> @@ -6565,6 +6634,8 @@ int intel_atomic_check(struct drm_device *dev,
>>   	if (ret)
>>   		goto fail;
>>   
>> +	intel_dc3co_allow_check(state);
>> +
>>   	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
>>   					    new_crtc_state, i) {
>>   		intel_color_assert_luts(new_crtc_state);
>> @@ -7601,6 +7672,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>>   		 */
>>   		intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
>>   	}
>> +	if (intel_dc3co_allowed(display))
>> +		intel_display_power_set_target_dc_state(display, DC_STATE_EN_UPTO_DC3CO);
>> +	else
>> +		intel_display_power_set_target_dc_state(display, DC_STATE_EN_UPTO_DC6);
>>   	/*
>>   	 * Delay re-enabling DC states by 17 ms to avoid the off->on->off
>>   	 * toggling overhead at and above 60 FPS.
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
>> index f8e6e4e82722..97987f082560 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display.h
>> @@ -560,5 +560,6 @@ bool assert_port_valid(struct intel_display *display, enum port port);
>>   
>>   bool intel_scanout_needs_vtd_wa(struct intel_display *display);
>>   int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state);
>> +bool intel_dc3co_allowed(struct intel_display *display);
>>   
>>   #endif
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
>> index d708d322aa85..fa567c95029c 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>> @@ -538,6 +538,9 @@ struct intel_display {
>>   
>>   		/* perform PHY state sanity checks? */
>>   		bool chv_phy_assert[2];
>> +
>> +		/* mark dc3co entry is allowed*/
> 		                              ^- space missing
will add space.
>
>> +		bool dc3co_allow;
> Still unclear when this is valid.
>
>>   	} power;
>>   
>>   	struct {
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>> index 0961b194554c..e99552f18756 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>> @@ -956,7 +956,9 @@ static u32 get_allowed_dc_mask(struct intel_display *display, int enable_dc)
>>   	if (!HAS_DISPLAY(display))
>>   		return 0;
>>   
>> -	if (DISPLAY_VER(display) >= 20)
>> +	if (DISPLAY_VER(display) >= 35)
>> +		max_dc = 3;
>> +	else if (DISPLAY_VER(display) >= 20)
>>   		max_dc = 2;
>>   	else if (display->platform.dg2)
>>   		max_dc = 1;
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>> index 753359069044..9c616f449ad6 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>> @@ -3903,14 +3903,11 @@ void intel_psr_notify_vblank_enable_disable(struct intel_display *display,
>>   		return;
>>   	}
>>   
>> -	/*
>> -	 * NOTE: intel_display_power_set_target_dc_state is used
>> -	 * only by PSR * code for DC3CO handling. DC3CO target
>> -	 * state is currently disabled in * PSR code. If DC3CO
>> -	 * is taken into use we need take that into account here
>> -	 * as well.
>> -	 */
>> -	intel_display_power_set_target_dc_state(display, enable ? DC_STATE_DISABLE :
>> +	if (intel_dc3co_allowed(display))
>> +		intel_display_power_set_target_dc_state(display, enable ? DC_STATE_DISABLE :
>> +						DC_STATE_EN_UPTO_DC3CO);
>> +	else
>> +		intel_display_power_set_target_dc_state(display, enable ? DC_STATE_DISABLE :
>>   						DC_STATE_EN_UPTO_DC6);
>>   }

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Re: [PATCH 4/9] drm/i915/display: Add DC3CO eligibility logic

[Jani Nikula]

On Tue, 06 Jan 2026, Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com> wrote:
> On 05-01-2026 18:25, Jani Nikula wrote:
>> On Tue, 09 Dec 2025, Dibin Moolakadan Subrahmanian<dibin.moolakadan.subrahmanian@intel.com> wrote:
>>> Introduce dc3co_allow in struct intel_display and determine DC3CO
>>> eligibility during atomic_check(). DC3CO is permitted only when:
>>>
>>>    - the active pipe drives eDP,
>>>    - the pipe is single-pipe (no joiner),
>>>    - the pipe/port combination supports DC3CO.
>>>
>>> When eligible, intel_atomic_commit_tail() programs the target DC state
>>> as DC_STATE_EN_UPTO_DC3CO; otherwise we fall back to DC6. Update the
>>> PSR vblank enable/disable path to follow the same policy.
>>>
>>> Also extend get_allowed_dc_mask() to expose DC3CO support on
>>> DISPLAY_VER >= 35.
>>>
>>> Signed-off-by: Dibin Moolakadan Subrahmanian<dibin.moolakadan.subrahmanian@intel.com>
>>> ---
>>>   drivers/gpu/drm/i915/display/intel_display.c  | 75 +++++++++++++++++++
>>>   drivers/gpu/drm/i915/display/intel_display.h  |  1 +
>>>   .../gpu/drm/i915/display/intel_display_core.h |  3 +
>>>   .../drm/i915/display/intel_display_power.c    |  4 +-
>>>   drivers/gpu/drm/i915/display/intel_psr.c      | 13 ++--
>>>   5 files changed, 87 insertions(+), 9 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>>> index 9c6d3ecdb589..205f55a87736 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>>> @@ -6295,6 +6295,75 @@ static int intel_joiner_add_affected_crtcs(struct intel_atomic_state *state)
>>>   	return 0;
>>>   }
>>>   
>>> +bool intel_dc3co_allowed(struct intel_display *display)
>>> +{
>>> +	return display->power.dc3co_allow;
>> Very few files should touch display->power, and this is not one of them.
>>
>> 'git grep "display->power" -- drivers/gpu/drm/i915/display'
>
> Yes, git grep shows few files , I will try to move all dc3co functions to
> drivers/gpu/drm/i915/display/intel_display_power.c.
>
>>
>> When is it okay to call this function and expect to get sane results?
>
> display->power.dc3co_allow is only updated in intel_dc3co_allow_check() which is called from
> intel_atomic_commit_tail().intel_dc3co_allowed() only intended to be called from intel_post_plane_update()
> path(ALPM/PSR), which executes as part of intel_atomic_commit_tail().

The point being, you have a complicated set of rules, and who's going to
know them and how when reading the code?

BR,
Jani.

>
>>
>>> +}
>>> +
>>> +static bool intel_dc3co_port_pipe_compatible(struct intel_dp *intel_dp,
>>> +					     const struct intel_crtc_state *crtc_state)
>>> +{
>>> +	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>>> +	enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
>>> +	enum port port = dig_port->base.port;
>>> +	int num_pipes = intel_crtc_num_joined_pipes(crtc_state);
>>> +
>>> +	if (num_pipes != 1)
>>> +		return false;
>>> +
>>> +	if (!(pipe <= PIPE_B && port <= PORT_B))
>>> +		return false;
>>> +
>>> +	return true;
>> That's a really complicated way to say
>>
>> 	return num_pipes == 1 && pipe <= PIPEB && port <= PORT_B;
>
> I will update this.
>
>>
>>> +}
>>> +
>>> +static void intel_dc3co_allow_check(struct intel_atomic_state *state)
>> What does "check" mean here? Or in *any* function?
>>
>> Check sounds like something that's a pure function that doesn't change
>> anything... but this does.
>
> I will split this function to two , one for check and one for initialization
>
>>> +{
>>> +	struct intel_display *display = to_intel_display(state);
>>> +	struct intel_crtc *crtc;
>>> +	struct intel_crtc_state *new_crtc_state;
>>> +	struct intel_encoder *encoder;
>>> +	struct intel_dp *intel_dp;
>>> +	int i;
>>> +	struct i915_power_domains *power_domains = &display->power.domains;
>>> +	bool any_active = false;
>>> +	bool allow = true;
>>> +
>>> +	display->power.dc3co_allow = 0;
>> That's now cached state with no stated rules on when it's valid and when
>> it's not.
>>
>>> +
>>> +	if ((power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC3CO) != DC_STATE_EN_UPTO_DC3CO)
>>> +		return;
>>> +
>>> +	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
>>> +		if (!new_crtc_state->hw.active)
>>> +			continue;
>>> +
>>> +		any_active = true;
>>> +
>>> +		for_each_intel_encoder_mask(display->drm, encoder,
>>> +					    new_crtc_state->uapi.encoder_mask) {
>>> +			/* If any active pipe not eDP disable*/
>> What?
>
> I will correct comment /* Disallow DC3CO if any active pipe is not eDP */
>
>>
>>> +			if (!intel_encoder_is_dp(encoder) ||
>>> +			    encoder->type != INTEL_OUTPUT_EDP) {
>>> +				allow = false;
>>> +				goto out;
>>> +			}
>>> +			intel_dp = enc_to_intel_dp(encoder);
>>> +			/* Port, joiner, pipe placement checks */
>> Is that a helpful comment?
>>
>>> +			if (!intel_dc3co_port_pipe_compatible(intel_dp, new_crtc_state)) {
>>> +				allow = false;
>>> +				goto out;
>>> +			}
>>> +		}
>>> +	}
>>> +
>>> +	if (!any_active)
>>> +		allow = false;
>>> +
>>> +out:
>>> +	display->power.dc3co_allow = allow;
>>> +}
>>> +
>> intel_display.[ch] is not the dumping ground for random new code. The
>> goal is to *reduce* the size of it, not increase.
>
> This function needs encoder,port and pipe information, which is why I added
> it in intel_display.c.However,I agree it is updating dc3co_allow . I will check if
> it can be moved to intel_display_power.c.
>
>>
>>>   static int intel_atomic_check_config(struct intel_atomic_state *state,
>>>   				     struct intel_link_bw_limits *limits,
>>>   				     enum pipe *failed_pipe)
>>> @@ -6565,6 +6634,8 @@ int intel_atomic_check(struct drm_device *dev,
>>>   	if (ret)
>>>   		goto fail;
>>>   
>>> +	intel_dc3co_allow_check(state);
>>> +
>>>   	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
>>>   					    new_crtc_state, i) {
>>>   		intel_color_assert_luts(new_crtc_state);
>>> @@ -7601,6 +7672,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>>>   		 */
>>>   		intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
>>>   	}
>>> +	if (intel_dc3co_allowed(display))
>>> +		intel_display_power_set_target_dc_state(display, DC_STATE_EN_UPTO_DC3CO);
>>> +	else
>>> +		intel_display_power_set_target_dc_state(display, DC_STATE_EN_UPTO_DC6);
>>>   	/*
>>>   	 * Delay re-enabling DC states by 17 ms to avoid the off->on->off
>>>   	 * toggling overhead at and above 60 FPS.
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
>>> index f8e6e4e82722..97987f082560 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display.h
>>> +++ b/drivers/gpu/drm/i915/display/intel_display.h
>>> @@ -560,5 +560,6 @@ bool assert_port_valid(struct intel_display *display, enum port port);
>>>   
>>>   bool intel_scanout_needs_vtd_wa(struct intel_display *display);
>>>   int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state);
>>> +bool intel_dc3co_allowed(struct intel_display *display);
>>>   
>>>   #endif
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
>>> index d708d322aa85..fa567c95029c 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
>>> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>>> @@ -538,6 +538,9 @@ struct intel_display {
>>>   
>>>   		/* perform PHY state sanity checks? */
>>>   		bool chv_phy_assert[2];
>>> +
>>> +		/* mark dc3co entry is allowed*/
>> 		                              ^- space missing
> will add space.
>>
>>> +		bool dc3co_allow;
>> Still unclear when this is valid.
>>
>>>   	} power;
>>>   
>>>   	struct {
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>>> index 0961b194554c..e99552f18756 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>>> @@ -956,7 +956,9 @@ static u32 get_allowed_dc_mask(struct intel_display *display, int enable_dc)
>>>   	if (!HAS_DISPLAY(display))
>>>   		return 0;
>>>   
>>> -	if (DISPLAY_VER(display) >= 20)
>>> +	if (DISPLAY_VER(display) >= 35)
>>> +		max_dc = 3;
>>> +	else if (DISPLAY_VER(display) >= 20)
>>>   		max_dc = 2;
>>>   	else if (display->platform.dg2)
>>>   		max_dc = 1;
>>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>>> index 753359069044..9c616f449ad6 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>>> @@ -3903,14 +3903,11 @@ void intel_psr_notify_vblank_enable_disable(struct intel_display *display,
>>>   		return;
>>>   	}
>>>   
>>> -	/*
>>> -	 * NOTE: intel_display_power_set_target_dc_state is used
>>> -	 * only by PSR * code for DC3CO handling. DC3CO target
>>> -	 * state is currently disabled in * PSR code. If DC3CO
>>> -	 * is taken into use we need take that into account here
>>> -	 * as well.
>>> -	 */
>>> -	intel_display_power_set_target_dc_state(display, enable ? DC_STATE_DISABLE :
>>> +	if (intel_dc3co_allowed(display))
>>> +		intel_display_power_set_target_dc_state(display, enable ? DC_STATE_DISABLE :
>>> +						DC_STATE_EN_UPTO_DC3CO);
>>> +	else
>>> +		intel_display_power_set_target_dc_state(display, enable ? DC_STATE_DISABLE :
>>>   						DC_STATE_EN_UPTO_DC6);
>>>   }

-- 
Jani Nikula, Intel

[PATCH 5/9] drm/i915/display: Track DC3CO enable source

[Dibin Moolakadan Subrahmanian]

Introduce a bitmask enum intel_dc3co_source to record which display
features (PSR2, ALPM, LOBF) contribute to allowing DC3CO entry.
The source tracking is added here and will be integrated into the DC3CO
allow logic in follow-up commits.
Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c       | 11 +++++++++++
 drivers/gpu/drm/i915/display/intel_display.h       |  4 +++-
 drivers/gpu/drm/i915/display/intel_display_core.h  |  1 +
 drivers/gpu/drm/i915/display/intel_display_power.h | 10 ++++++++++
 4 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 205f55a87736..b14a1c9f80bd 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6300,6 +6300,16 @@ bool intel_dc3co_allowed(struct intel_display *display)
 	return display->power.dc3co_allow;
 }
 
+void intel_dc3co_source_set(struct intel_display *display, enum intel_dc3co_source source)
+{
+	display->power.dc3co_source |= source;
+}
+
+void intel_dc3co_source_unset(struct intel_display *display, enum intel_dc3co_source source)
+{
+	display->power.dc3co_source &= ~source;
+}
+
 static bool intel_dc3co_port_pipe_compatible(struct intel_dp *intel_dp,
 					     const struct intel_crtc_state *crtc_state)
 {
@@ -6330,6 +6340,7 @@ static void intel_dc3co_allow_check(struct intel_atomic_state *state)
 	bool allow = true;
 
 	display->power.dc3co_allow = 0;
+	intel_dc3co_source_unset(display, DC3CO_SOURCE_ALL);
 
 	if ((power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC3CO) != DC_STATE_EN_UPTO_DC3CO)
 		return;
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 97987f082560..87bbf1f66209 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -46,6 +46,7 @@ struct intel_link_m_n;
 struct intel_plane;
 struct intel_plane_state;
 struct intel_power_domain_mask;
+enum intel_dc3co_source;
 
 #define pipe_name(p) ((p) + 'A')
 
@@ -561,5 +562,6 @@ bool assert_port_valid(struct intel_display *display, enum port port);
 bool intel_scanout_needs_vtd_wa(struct intel_display *display);
 int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state);
 bool intel_dc3co_allowed(struct intel_display *display);
-
+void intel_dc3co_source_set(struct intel_display *display, enum intel_dc3co_source source);
+void intel_dc3co_source_unset(struct intel_display *display, enum intel_dc3co_source source);
 #endif
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index fa567c95029c..4ce34c567dbd 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -541,6 +541,7 @@ struct intel_display {
 
 		/* mark dc3co entry is allowed*/
 		bool dc3co_allow;
+		u32 dc3co_source;
 	} power;
 
 	struct {
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index d616d5d09cbe..dde07f931963 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -131,6 +131,16 @@ struct intel_power_domain_mask {
 	DECLARE_BITMAP(bits, POWER_DOMAIN_NUM);
 };
 
+enum intel_dc3co_source {
+	DC3CO_SOURCE_NONE = 0,
+	DC3CO_SOURCE_PSR2 = BIT(0),
+	DC3CO_SOURCE_ALPM = BIT(1),
+	DC3CO_SOURCE_LOBF = BIT(2),
+	DC3CO_SOURCE_ALL  = DC3CO_SOURCE_PSR2 |
+			    DC3CO_SOURCE_ALPM |
+			    DC3CO_SOURCE_LOBF,
+};
+
 struct i915_power_domains {
 	/*
 	 * Power wells needed for initialization at driver init and suspend
-- 
2.43.0

Re: [PATCH 5/9] drm/i915/display: Track DC3CO enable source

[Jani Nikula]

On Tue, 09 Dec 2025, Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com> wrote:
> Introduce a bitmask enum intel_dc3co_source to record which display
> features (PSR2, ALPM, LOBF) contribute to allowing DC3CO entry.
> The source tracking is added here and will be integrated into the DC3CO
> allow logic in follow-up commits.
> Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c       | 11 +++++++++++
>  drivers/gpu/drm/i915/display/intel_display.h       |  4 +++-
>  drivers/gpu/drm/i915/display/intel_display_core.h  |  1 +
>  drivers/gpu/drm/i915/display/intel_display_power.h | 10 ++++++++++
>  4 files changed, 25 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 205f55a87736..b14a1c9f80bd 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6300,6 +6300,16 @@ bool intel_dc3co_allowed(struct intel_display *display)
>  	return display->power.dc3co_allow;
>  }
>  
> +void intel_dc3co_source_set(struct intel_display *display, enum intel_dc3co_source source)
> +{
> +	display->power.dc3co_source |= source;
> +}
> +
> +void intel_dc3co_source_unset(struct intel_display *display, enum intel_dc3co_source source)
> +{
> +	display->power.dc3co_source &= ~source;
> +}
> +

These don't belong in intel_display.[ch].

>  static bool intel_dc3co_port_pipe_compatible(struct intel_dp *intel_dp,
>  					     const struct intel_crtc_state *crtc_state)
>  {
> @@ -6330,6 +6340,7 @@ static void intel_dc3co_allow_check(struct intel_atomic_state *state)
>  	bool allow = true;
>  
>  	display->power.dc3co_allow = 0;
> +	intel_dc3co_source_unset(display, DC3CO_SOURCE_ALL);
>  
>  	if ((power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC3CO) != DC_STATE_EN_UPTO_DC3CO)
>  		return;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index 97987f082560..87bbf1f66209 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -46,6 +46,7 @@ struct intel_link_m_n;
>  struct intel_plane;
>  struct intel_plane_state;
>  struct intel_power_domain_mask;
> +enum intel_dc3co_source;
>  
>  #define pipe_name(p) ((p) + 'A')
>  
> @@ -561,5 +562,6 @@ bool assert_port_valid(struct intel_display *display, enum port port);
>  bool intel_scanout_needs_vtd_wa(struct intel_display *display);
>  int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state);
>  bool intel_dc3co_allowed(struct intel_display *display);
> -
> +void intel_dc3co_source_set(struct intel_display *display, enum intel_dc3co_source source);
> +void intel_dc3co_source_unset(struct intel_display *display, enum intel_dc3co_source source);
>  #endif
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> index fa567c95029c..4ce34c567dbd 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -541,6 +541,7 @@ struct intel_display {
>  
>  		/* mark dc3co entry is allowed*/
>  		bool dc3co_allow;
> +		u32 dc3co_source;
>  	} power;
>  
>  	struct {
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
> index d616d5d09cbe..dde07f931963 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -131,6 +131,16 @@ struct intel_power_domain_mask {
>  	DECLARE_BITMAP(bits, POWER_DOMAIN_NUM);
>  };
>  
> +enum intel_dc3co_source {
> +	DC3CO_SOURCE_NONE = 0,
> +	DC3CO_SOURCE_PSR2 = BIT(0),
> +	DC3CO_SOURCE_ALPM = BIT(1),
> +	DC3CO_SOURCE_LOBF = BIT(2),
> +	DC3CO_SOURCE_ALL  = DC3CO_SOURCE_PSR2 |
> +			    DC3CO_SOURCE_ALPM |
> +			    DC3CO_SOURCE_LOBF,
> +};
> +
>  struct i915_power_domains {
>  	/*
>  	 * Power wells needed for initialization at driver init and suspend

-- 
Jani Nikula, Intel

[PATCH 6/9] drm/i915/display: alpm enable DC3CO support

[Dibin Moolakadan Subrahmanian]

if DC3CO allowed set PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL
in ALPM_CTL and update dc3co_source

Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c     | 4 ++++
 drivers/gpu/drm/i915/display/intel_psr_regs.h | 1 +
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 7ce8c674bb03..28a95f6ddfab 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -347,6 +347,10 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
 
 	alpm_ctl |= ALPM_CTL_ALPM_ENTRY_CHECK(crtc_state->alpm_state.check_entry_lines);
 
+	if (intel_dc3co_allowed(display)) {
+		alpm_ctl |= (PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL);
+		intel_dc3co_source_set(display, DC3CO_SOURCE_ALPM);
+	}
 	intel_de_write(display, ALPM_CTL(display, cpu_transcoder), alpm_ctl);
 	mutex_unlock(&intel_dp->alpm.lock);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index 8afbf5a38335..16a9e3af198d 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -268,6 +268,7 @@
 
 #define _PR_ALPM_CTL_A	0x60948
 #define PR_ALPM_CTL(dev_priv, tran)	_MMIO_TRANS2(dev_priv, tran, _PR_ALPM_CTL_A)
+#define  PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL			BIT(7)
 #define  PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU	BIT(6)
 #define  PR_ALPM_CTL_RFB_UPDATE_CONTROL				BIT(5)
 #define  PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE	BIT(4)
-- 
2.43.0

Re: [PATCH 6/9] drm/i915/display: alpm enable DC3CO support

[Hogander, Jouni]

On Tue, 2025-12-09 at 17:03 +0530, Dibin Moolakadan Subrahmanian wrote:
> if DC3CO allowed set PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL
> in ALPM_CTL and update dc3co_source
> 
> Signed-off-by: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_alpm.c     | 4 ++++
>  drivers/gpu/drm/i915/display/intel_psr_regs.h | 1 +
>  2 files changed, 5 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 7ce8c674bb03..28a95f6ddfab 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -347,6 +347,10 @@ static void lnl_alpm_configure(struct intel_dp
> *intel_dp,
>  
>  	alpm_ctl |= ALPM_CTL_ALPM_ENTRY_CHECK(crtc_state-
> >alpm_state.check_entry_lines);
>  
> +	if (intel_dc3co_allowed(display)) {
> +		alpm_ctl |= (PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL);
> +		intel_dc3co_source_set(display, DC3CO_SOURCE_ALPM);

This source concept is generally confusing. More specifically
DC3CO_SOURCE_ALPM I don't understand:

PSR and LOBF are methods to allow switching link off. ALPM is a method
to switch the link off. DC3CO and DC6 are Display power saving states
which are possible as the link is switched off.

BR,

Jouni Högander

> +	}
>  	intel_de_write(display, ALPM_CTL(display, cpu_transcoder),
> alpm_ctl);
>  	mutex_unlock(&intel_dp->alpm.lock);
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> index 8afbf5a38335..16a9e3af198d 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> @@ -268,6 +268,7 @@
>  
>  #define _PR_ALPM_CTL_A	0x60948
>  #define PR_ALPM_CTL(dev_priv, tran)	_MMIO_TRANS2(dev_priv, tran,
> _PR_ALPM_CTL_A)
> +#define 
> PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL			BIT(7)
>  #define 
> PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU	BIT(6)
>  #define 
> PR_ALPM_CTL_RFB_UPDATE_CONTROL				BIT(5)
>  #define 
> PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE	BIT(4)

Re: [PATCH 6/9] drm/i915/display: alpm enable DC3CO support

[Dibin Moolakadan Subrahmanian]

[-- Attachment #1: Type: text/plain, Size: 2415 bytes --]


On 12-12-2025 13:07, Hogander, Jouni wrote:
> On Tue, 2025-12-09 at 17:03 +0530, Dibin Moolakadan Subrahmanian wrote:
>> if DC3CO allowed set PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL
>> in ALPM_CTL and update dc3co_source
>>
>> Signed-off-by: Dibin Moolakadan Subrahmanian
>> <dibin.moolakadan.subrahmanian@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_alpm.c     | 4 ++++
>>   drivers/gpu/drm/i915/display/intel_psr_regs.h | 1 +
>>   2 files changed, 5 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
>> b/drivers/gpu/drm/i915/display/intel_alpm.c
>> index 7ce8c674bb03..28a95f6ddfab 100644
>> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
>> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
>> @@ -347,6 +347,10 @@ static void lnl_alpm_configure(struct intel_dp
>> *intel_dp,
>>   
>>   	alpm_ctl |= ALPM_CTL_ALPM_ENTRY_CHECK(crtc_state-
>>> alpm_state.check_entry_lines);
>>   
>> +	if (intel_dc3co_allowed(display)) {
>> +		alpm_ctl |= (PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL);
>> +		intel_dc3co_source_set(display, DC3CO_SOURCE_ALPM);
> This source concept is generally confusing. More specifically
> DC3CO_SOURCE_ALPM I don't understand:
>
> PSR and LOBF are methods to allow switching link off. ALPM is a method
> to switch the link off. DC3CO and DC6 are Display power saving states
> which are possible as the link is switched off.

Thank you for comments , I want to track the reason for enabling DC3CO.
I will remove DC3CO_SOURCE_ALPM as you pointed, but want to keep
DC3CO_REASON_PSR2 and DC3CO_REASON_LOBF .

> BR,
>
> Jouni Högander
>
>> +	}
>>   	intel_de_write(display, ALPM_CTL(display, cpu_transcoder),
>> alpm_ctl);
>>   	mutex_unlock(&intel_dp->alpm.lock);
>>   }
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h
>> b/drivers/gpu/drm/i915/display/intel_psr_regs.h
>> index 8afbf5a38335..16a9e3af198d 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
>> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
>> @@ -268,6 +268,7 @@
>>   
>>   #define _PR_ALPM_CTL_A	0x60948
>>   #define PR_ALPM_CTL(dev_priv, tran)	_MMIO_TRANS2(dev_priv, tran,
>> _PR_ALPM_CTL_A)
>> +#define
>> PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL			BIT(7)
>>   #define
>> PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU	BIT(6)
>>   #define
>> PR_ALPM_CTL_RFB_UPDATE_CONTROL				BIT(5)
>>   #define
>> PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE	BIT(4)

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[PATCH 7/9] drm/i915/display: psr enable DC3CO support

[Dibin Moolakadan Subrahmanian]

if DC3CO allowed and psr2 is enabled, update dc3co_source

Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 9c616f449ad6..d4c5dc6dcc82 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -3007,6 +3007,12 @@ void intel_psr_post_plane_update(struct intel_atomic_state *state,
 		if (crtc_state->crc_enabled && psr->enabled)
 			intel_psr_force_update(intel_dp);
 
+		if (psr->enabled &&
+		    psr->sel_update_enabled &&
+		    intel_dc3co_allowed(display)) {
+			intel_dc3co_source_set(display, DC3CO_SOURCE_PSR2);
+		}
+
 		/*
 		 * Clear possible busy bits in case we have
 		 * invalidate -> flip -> flush sequence.
-- 
2.43.0

Re: [PATCH 7/9] drm/i915/display: psr enable DC3CO support

[Jani Nikula]

On Tue, 09 Dec 2025, Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com> wrote:
> if DC3CO allowed and psr2 is enabled, update dc3co_source

Yeah, I can read the code, but what does it mean? Why?

>
> Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 9c616f449ad6..d4c5dc6dcc82 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -3007,6 +3007,12 @@ void intel_psr_post_plane_update(struct intel_atomic_state *state,
>  		if (crtc_state->crc_enabled && psr->enabled)
>  			intel_psr_force_update(intel_dp);
>  
> +		if (psr->enabled &&
> +		    psr->sel_update_enabled &&
> +		    intel_dc3co_allowed(display)) {
> +			intel_dc3co_source_set(display, DC3CO_SOURCE_PSR2);
> +		}
> +
>  		/*
>  		 * Clear possible busy bits in case we have
>  		 * invalidate -> flip -> flush sequence.

-- 
Jani Nikula, Intel

Re: [PATCH 7/9] drm/i915/display: psr enable DC3CO support

[Dibin Moolakadan Subrahmanian]

[-- Attachment #1: Type: text/plain, Size: 1379 bytes --]

On 05-01-2026 18:32, Jani Nikula wrote:
> On Tue, 09 Dec 2025, Dibin Moolakadan Subrahmanian<dibin.moolakadan.subrahmanian@intel.com> wrote:
>> if DC3CO allowed and psr2 is enabled, update dc3co_source
> Yeah, I can read the code, but what does it mean? Why?

I will add more details.
The intent is to record PSR2 as the source enabling DC3CO.
DC3CO can be entered when either PSR2 or LOBF is enabled, and
dc3co_source is used to track which feature triggered it.

>> Signed-off-by: Dibin Moolakadan Subrahmanian<dibin.moolakadan.subrahmanian@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_psr.c | 6 ++++++
>>   1 file changed, 6 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>> index 9c616f449ad6..d4c5dc6dcc82 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>> @@ -3007,6 +3007,12 @@ void intel_psr_post_plane_update(struct intel_atomic_state *state,
>>   		if (crtc_state->crc_enabled && psr->enabled)
>>   			intel_psr_force_update(intel_dp);
>>   
>> +		if (psr->enabled &&
>> +		    psr->sel_update_enabled &&
>> +		    intel_dc3co_allowed(display)) {
>> +			intel_dc3co_source_set(display, DC3CO_SOURCE_PSR2);
>> +		}
>> +
>>   		/*
>>   		 * Clear possible busy bits in case we have
>>   		 * invalidate -> flip -> flush sequence.

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[PATCH 8/9] drm/i915/display: Add intel_dc3co_can_enable() helper

[Dibin Moolakadan Subrahmanian]

Introduce a new helper that validates whether DC3CO can be enabled
based on both allow  and source.

Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 11 ++++++++++-
 drivers/gpu/drm/i915/display/intel_display.h |  1 +
 drivers/gpu/drm/i915/display/intel_psr.c     |  2 +-
 3 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index b14a1c9f80bd..9f9ba58371ab 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6295,6 +6295,15 @@ static int intel_joiner_add_affected_crtcs(struct intel_atomic_state *state)
 	return 0;
 }
 
+bool intel_dc3co_can_enable(struct intel_display *display)
+{
+	/*
+	 * ToDo - Check CMTG enabled
+	 * ToDo - Check flipq enabled
+	 */
+	return (display->power.dc3co_allow && display->power.dc3co_source);
+}
+
 bool intel_dc3co_allowed(struct intel_display *display)
 {
 	return display->power.dc3co_allow;
@@ -7683,7 +7692,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 		 */
 		intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
 	}
-	if (intel_dc3co_allowed(display))
+	if (intel_dc3co_can_enable(display))
 		intel_display_power_set_target_dc_state(display, DC_STATE_EN_UPTO_DC3CO);
 	else
 		intel_display_power_set_target_dc_state(display, DC_STATE_EN_UPTO_DC6);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 87bbf1f66209..f704cce4f1d8 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -564,4 +564,5 @@ int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state);
 bool intel_dc3co_allowed(struct intel_display *display);
 void intel_dc3co_source_set(struct intel_display *display, enum intel_dc3co_source source);
 void intel_dc3co_source_unset(struct intel_display *display, enum intel_dc3co_source source);
+bool intel_dc3co_can_enable(struct intel_display *display);
 #endif
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index d4c5dc6dcc82..18bf45455ea2 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -3909,7 +3909,7 @@ void intel_psr_notify_vblank_enable_disable(struct intel_display *display,
 		return;
 	}
 
-	if (intel_dc3co_allowed(display))
+	if (intel_dc3co_can_enable(display))
 		intel_display_power_set_target_dc_state(display, enable ? DC_STATE_DISABLE :
 						DC_STATE_EN_UPTO_DC3CO);
 	else
-- 
2.43.0

Re: [PATCH 8/9] drm/i915/display: Add intel_dc3co_can_enable() helper

[Jani Nikula]

On Tue, 09 Dec 2025, Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com> wrote:
> Introduce a new helper that validates whether DC3CO can be enabled
> based on both allow  and source.
>
> Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 11 ++++++++++-
>  drivers/gpu/drm/i915/display/intel_display.h |  1 +
>  drivers/gpu/drm/i915/display/intel_psr.c     |  2 +-
>  3 files changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index b14a1c9f80bd..9f9ba58371ab 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6295,6 +6295,15 @@ static int intel_joiner_add_affected_crtcs(struct intel_atomic_state *state)
>  	return 0;
>  }
>  
> +bool intel_dc3co_can_enable(struct intel_display *display)
> +{
> +	/*
> +	 * ToDo - Check CMTG enabled
> +	 * ToDo - Check flipq enabled
> +	 */
> +	return (display->power.dc3co_allow && display->power.dc3co_source);
> +}
> +

This doesn't belong in intel_display.[ch].

>  bool intel_dc3co_allowed(struct intel_display *display)
>  {
>  	return display->power.dc3co_allow;
> @@ -7683,7 +7692,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  		 */
>  		intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
>  	}
> -	if (intel_dc3co_allowed(display))
> +	if (intel_dc3co_can_enable(display))
>  		intel_display_power_set_target_dc_state(display, DC_STATE_EN_UPTO_DC3CO);
>  	else
>  		intel_display_power_set_target_dc_state(display, DC_STATE_EN_UPTO_DC6);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index 87bbf1f66209..f704cce4f1d8 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -564,4 +564,5 @@ int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state);
>  bool intel_dc3co_allowed(struct intel_display *display);
>  void intel_dc3co_source_set(struct intel_display *display, enum intel_dc3co_source source);
>  void intel_dc3co_source_unset(struct intel_display *display, enum intel_dc3co_source source);
> +bool intel_dc3co_can_enable(struct intel_display *display);
>  #endif
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index d4c5dc6dcc82..18bf45455ea2 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -3909,7 +3909,7 @@ void intel_psr_notify_vblank_enable_disable(struct intel_display *display,
>  		return;
>  	}
>  
> -	if (intel_dc3co_allowed(display))
> +	if (intel_dc3co_can_enable(display))
>  		intel_display_power_set_target_dc_state(display, enable ? DC_STATE_DISABLE :
>  						DC_STATE_EN_UPTO_DC3CO);
>  	else

-- 
Jani Nikula, Intel

[PATCH 9/9] drm/i915/display: Add DC3CO disable handling for psr2

[Dibin Moolakadan Subrahmanian]

dc6 should be enabled instead of dc3co after  6 idle frames
while in psr2.(re enable part of tgl dc3co handling)

Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_psr.c      | 78 ++++++++++++++++++-
 2 files changed, 78 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 27f69df7ee9c..6ff53cd58052 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1759,6 +1759,7 @@ struct intel_psr {
 	bool panel_replay_enabled;
 	u32 dc3co_exitline;
 	u32 dc3co_exit_delay;
+	struct delayed_work dc3co_work;
 	u8 entry_setup_frames;
 
 	u8 io_wake_lines;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 18bf45455ea2..4be709d1d324 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1157,6 +1157,78 @@ static void psr2_program_idle_frames(struct intel_dp *intel_dp,
 		     EDP_PSR2_IDLE_FRAMES(idle_frames));
 }
 
+static void psr2_dc3co_disable(struct intel_dp *intel_dp)
+{
+	struct intel_display *display = to_intel_display(intel_dp);
+	struct i915_power_domains *power_domains = &display->power.domains;
+
+	if ((power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC3CO) != DC_STATE_EN_UPTO_DC3CO)
+		return;
+
+	intel_display_power_set_target_dc_state(display, DC_STATE_EN_UPTO_DC6);
+	/* Todo restore PSR2 idle frames , ALPM control*/
+}
+
+static void psr2_dc3co_disable_on_exit(struct intel_dp *intel_dp)
+{
+	struct intel_display *display = to_intel_display(intel_dp);
+	struct i915_power_domains *power_domains = &display->power.domains;
+
+	if ((power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC3CO) != DC_STATE_EN_UPTO_DC3CO)
+		return;
+
+	cancel_delayed_work(&intel_dp->psr.dc3co_work);
+	intel_dc3co_source_unset(display, DC3CO_SOURCE_PSR2);
+}
+
+static void psr2_dc3co_disable_work(struct work_struct *work)
+{
+	struct intel_dp *intel_dp =
+		container_of(work, typeof(*intel_dp), psr.dc3co_work.work);
+
+	mutex_lock(&intel_dp->psr.lock);
+	/* If delayed work is pending, it is not idle */
+	if (delayed_work_pending(&intel_dp->psr.dc3co_work))
+		goto unlock;
+	/* enable DC6 after idle frames*/
+	psr2_dc3co_disable(intel_dp);
+
+unlock:
+	mutex_unlock(&intel_dp->psr.lock);
+}
+
+/*
+ * When we will be completely rely on PSR2 S/W tracking in future,
+ * intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP
+ * event also therefore psr2_dc3co_flush_locked() require to be changed
+ * accordingly in future.
+ */
+
+static void
+psr2_dc3co_flush_locked(struct intel_dp *intel_dp, unsigned int frontbuffer_bits,
+			enum fb_op_origin origin)
+{
+	struct intel_display *display = to_intel_display(intel_dp);
+	struct i915_power_domains *power_domains = &display->power.domains;
+
+	if (!(power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC3CO))
+		return;
+
+	if (!intel_dp->psr.sel_update_enabled ||
+	    !intel_dp->psr.active)
+		return;
+	/*
+	 * At every frontbuffer flush flip event modified delay of delayed work,
+	 * when delayed work schedules that means display has been idle.
+	 */
+	if (!(frontbuffer_bits &
+	    INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe)))
+		return;
+
+	mod_delayed_work(display->wq.unordered, &intel_dp->psr.dc3co_work,
+			 intel_dp->psr.dc3co_exit_delay);
+}
+
 static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
 					      struct intel_crtc_state *crtc_state)
 {
@@ -2117,7 +2189,7 @@ static void intel_psr_exit(struct intel_dp *intel_dp)
 		intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder),
 			     TRANS_DP2_PANEL_REPLAY_ENABLE, 0);
 	} else if (intel_dp->psr.sel_update_enabled) {
-
+		psr2_dc3co_disable_on_exit(intel_dp);
 		val = intel_de_rmw(display,
 				   EDP_PSR2_CTL(display, cpu_transcoder),
 				   EDP_PSR2_ENABLE, 0);
@@ -2259,6 +2331,7 @@ void intel_psr_disable(struct intel_dp *intel_dp,
 
 	mutex_unlock(&intel_dp->psr.lock);
 	cancel_work_sync(&intel_dp->psr.work);
+	cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);
 }
 
 /**
@@ -2289,6 +2362,7 @@ void intel_psr_pause(struct intel_dp *intel_dp)
 	mutex_unlock(&psr->lock);
 
 	cancel_work_sync(&psr->work);
+	cancel_delayed_work_sync(&psr->dc3co_work);
 }
 
 /**
@@ -3475,6 +3549,7 @@ void intel_psr_flush(struct intel_display *display,
 		if (origin == ORIGIN_FLIP ||
 		    (origin == ORIGIN_CURSOR_UPDATE &&
 		     !intel_dp->psr.psr2_sel_fetch_enabled)) {
+			psr2_dc3co_flush_locked(intel_dp, frontbuffer_bits, origin);
 			goto unlock;
 		}
 
@@ -3533,6 +3608,7 @@ void intel_psr_init(struct intel_dp *intel_dp)
 		intel_dp->psr.link_standby = connector->panel.vbt.psr.full_link;
 
 	INIT_WORK(&intel_dp->psr.work, intel_psr_work);
+	INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, psr2_dc3co_disable_work);
 	mutex_init(&intel_dp->psr.lock);
 }
 
-- 
2.43.0

Re: [PATCH 9/9] drm/i915/display: Add DC3CO disable handling for psr2

[Hogander, Jouni]

On Tue, 2025-12-09 at 17:03 +0530, Dibin Moolakadan Subrahmanian wrote:
> dc6 should be enabled instead of dc3co after  6 idle frames
> while in psr2.(re enable part of tgl dc3co handling)

This is for PSR and pretty much following existing (disabled) TGL DC3CO
control. What is your idea how selection between DC6 and DC3CO will be
done in case of LOBF?

BR,

Jouni Högander

> 
> Signed-off-by: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> ---
>  .../drm/i915/display/intel_display_types.h    |  1 +
>  drivers/gpu/drm/i915/display/intel_psr.c      | 78
> ++++++++++++++++++-
>  2 files changed, 78 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 27f69df7ee9c..6ff53cd58052 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1759,6 +1759,7 @@ struct intel_psr {
>  	bool panel_replay_enabled;
>  	u32 dc3co_exitline;
>  	u32 dc3co_exit_delay;
> +	struct delayed_work dc3co_work;
>  	u8 entry_setup_frames;
>  
>  	u8 io_wake_lines;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 18bf45455ea2..4be709d1d324 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1157,6 +1157,78 @@ static void psr2_program_idle_frames(struct
> intel_dp *intel_dp,
>  		     EDP_PSR2_IDLE_FRAMES(idle_frames));
>  }
>  
> +static void psr2_dc3co_disable(struct intel_dp *intel_dp)
> +{
> +	struct intel_display *display = to_intel_display(intel_dp);
> +	struct i915_power_domains *power_domains = &display-
> >power.domains;
> +
> +	if ((power_domains->allowed_dc_mask &
> DC_STATE_EN_UPTO_DC3CO) != DC_STATE_EN_UPTO_DC3CO)
> +		return;
> +
> +	intel_display_power_set_target_dc_state(display,
> DC_STATE_EN_UPTO_DC6);
> +	/* Todo restore PSR2 idle frames , ALPM control*/
> +}
> +
> +static void psr2_dc3co_disable_on_exit(struct intel_dp *intel_dp)
> +{
> +	struct intel_display *display = to_intel_display(intel_dp);
> +	struct i915_power_domains *power_domains = &display-
> >power.domains;
> +
> +	if ((power_domains->allowed_dc_mask &
> DC_STATE_EN_UPTO_DC3CO) != DC_STATE_EN_UPTO_DC3CO)
> +		return;
> +
> +	cancel_delayed_work(&intel_dp->psr.dc3co_work);
> +	intel_dc3co_source_unset(display, DC3CO_SOURCE_PSR2);
> +}
> +
> +static void psr2_dc3co_disable_work(struct work_struct *work)
> +{
> +	struct intel_dp *intel_dp =
> +		container_of(work, typeof(*intel_dp),
> psr.dc3co_work.work);
> +
> +	mutex_lock(&intel_dp->psr.lock);
> +	/* If delayed work is pending, it is not idle */
> +	if (delayed_work_pending(&intel_dp->psr.dc3co_work))
> +		goto unlock;
> +	/* enable DC6 after idle frames*/
> +	psr2_dc3co_disable(intel_dp);
> +
> +unlock:
> +	mutex_unlock(&intel_dp->psr.lock);
> +}
> +
> +/*
> + * When we will be completely rely on PSR2 S/W tracking in future,
> + * intel_psr_flush() will invalidate and flush the PSR for
> ORIGIN_FLIP
> + * event also therefore psr2_dc3co_flush_locked() require to be
> changed
> + * accordingly in future.
> + */
> +
> +static void
> +psr2_dc3co_flush_locked(struct intel_dp *intel_dp, unsigned int
> frontbuffer_bits,
> +			enum fb_op_origin origin)
> +{
> +	struct intel_display *display = to_intel_display(intel_dp);
> +	struct i915_power_domains *power_domains = &display-
> >power.domains;
> +
> +	if (!(power_domains->allowed_dc_mask &
> DC_STATE_EN_UPTO_DC3CO))
> +		return;
> +
> +	if (!intel_dp->psr.sel_update_enabled ||
> +	    !intel_dp->psr.active)
> +		return;
> +	/*
> +	 * At every frontbuffer flush flip event modified delay of
> delayed work,
> +	 * when delayed work schedules that means display has been
> idle.
> +	 */
> +	if (!(frontbuffer_bits &
> +	    INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe)))
> +		return;
> +
> +	mod_delayed_work(display->wq.unordered, &intel_dp-
> >psr.dc3co_work,
> +			 intel_dp->psr.dc3co_exit_delay);
> +}
> +
>  static bool intel_psr2_sel_fetch_config_valid(struct intel_dp
> *intel_dp,
>  					      struct
> intel_crtc_state *crtc_state)
>  {
> @@ -2117,7 +2189,7 @@ static void intel_psr_exit(struct intel_dp
> *intel_dp)
>  		intel_de_rmw(display, TRANS_DP2_CTL(intel_dp-
> >psr.transcoder),
>  			     TRANS_DP2_PANEL_REPLAY_ENABLE, 0);
>  	} else if (intel_dp->psr.sel_update_enabled) {
> -
> +		psr2_dc3co_disable_on_exit(intel_dp);
>  		val = intel_de_rmw(display,
>  				   EDP_PSR2_CTL(display,
> cpu_transcoder),
>  				   EDP_PSR2_ENABLE, 0);
> @@ -2259,6 +2331,7 @@ void intel_psr_disable(struct intel_dp
> *intel_dp,
>  
>  	mutex_unlock(&intel_dp->psr.lock);
>  	cancel_work_sync(&intel_dp->psr.work);
> +	cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);
>  }
>  
>  /**
> @@ -2289,6 +2362,7 @@ void intel_psr_pause(struct intel_dp *intel_dp)
>  	mutex_unlock(&psr->lock);
>  
>  	cancel_work_sync(&psr->work);
> +	cancel_delayed_work_sync(&psr->dc3co_work);
>  }
>  
>  /**
> @@ -3475,6 +3549,7 @@ void intel_psr_flush(struct intel_display
> *display,
>  		if (origin == ORIGIN_FLIP ||
>  		    (origin == ORIGIN_CURSOR_UPDATE &&
>  		     !intel_dp->psr.psr2_sel_fetch_enabled)) {
> +			psr2_dc3co_flush_locked(intel_dp,
> frontbuffer_bits, origin);
>  			goto unlock;
>  		}
>  
> @@ -3533,6 +3608,7 @@ void intel_psr_init(struct intel_dp *intel_dp)
>  		intel_dp->psr.link_standby = connector-
> >panel.vbt.psr.full_link;
>  
>  	INIT_WORK(&intel_dp->psr.work, intel_psr_work);
> +	INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work,
> psr2_dc3co_disable_work);
>  	mutex_init(&intel_dp->psr.lock);
>  }
>  

Re: [PATCH 9/9] drm/i915/display: Add DC3CO disable handling for psr2

[Dibin Moolakadan Subrahmanian]

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On 12-12-2025 12:41, Hogander, Jouni wrote:
> On Tue, 2025-12-09 at 17:03 +0530, Dibin Moolakadan Subrahmanian wrote:
>> dc6 should be enabled instead of dc3co after  6 idle frames
>> while in psr2.(re enable part of tgl dc3co handling)
> This is for PSR and pretty much following existing (disabled) TGL DC3CO
> control. What is your idea how selection between DC6 and DC3CO will be
> done in case of LOBF?

For both LOBF and PSR dc3co will be enabled from intel_atomic_commit_tail() it self.
This patch selects DC6 after 6 idle frames for PSR.

> BR,
>
> Jouni Högander
>
>> Signed-off-by: Dibin Moolakadan Subrahmanian
>> <dibin.moolakadan.subrahmanian@intel.com>
>> ---
>>   .../drm/i915/display/intel_display_types.h    |  1 +
>>   drivers/gpu/drm/i915/display/intel_psr.c      | 78
>> ++++++++++++++++++-
>>   2 files changed, 78 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
>> b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index 27f69df7ee9c..6ff53cd58052 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -1759,6 +1759,7 @@ struct intel_psr {
>>   	bool panel_replay_enabled;
>>   	u32 dc3co_exitline;
>>   	u32 dc3co_exit_delay;
>> +	struct delayed_work dc3co_work;
>>   	u8 entry_setup_frames;
>>   
>>   	u8 io_wake_lines;
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
>> b/drivers/gpu/drm/i915/display/intel_psr.c
>> index 18bf45455ea2..4be709d1d324 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>> @@ -1157,6 +1157,78 @@ static void psr2_program_idle_frames(struct
>> intel_dp *intel_dp,
>>   		     EDP_PSR2_IDLE_FRAMES(idle_frames));
>>   }
>>   
>> +static void psr2_dc3co_disable(struct intel_dp *intel_dp)
>> +{
>> +	struct intel_display *display = to_intel_display(intel_dp);
>> +	struct i915_power_domains *power_domains = &display-
>>> power.domains;
>> +
>> +	if ((power_domains->allowed_dc_mask &
>> DC_STATE_EN_UPTO_DC3CO) != DC_STATE_EN_UPTO_DC3CO)
>> +		return;
>> +
>> +	intel_display_power_set_target_dc_state(display,
>> DC_STATE_EN_UPTO_DC6);
>> +	/* Todo restore PSR2 idle frames , ALPM control*/
>> +}
>> +
>> +static void psr2_dc3co_disable_on_exit(struct intel_dp *intel_dp)
>> +{
>> +	struct intel_display *display = to_intel_display(intel_dp);
>> +	struct i915_power_domains *power_domains = &display-
>>> power.domains;
>> +
>> +	if ((power_domains->allowed_dc_mask &
>> DC_STATE_EN_UPTO_DC3CO) != DC_STATE_EN_UPTO_DC3CO)
>> +		return;
>> +
>> +	cancel_delayed_work(&intel_dp->psr.dc3co_work);
>> +	intel_dc3co_source_unset(display, DC3CO_SOURCE_PSR2);
>> +}
>> +
>> +static void psr2_dc3co_disable_work(struct work_struct *work)
>> +{
>> +	struct intel_dp *intel_dp =
>> +		container_of(work, typeof(*intel_dp),
>> psr.dc3co_work.work);
>> +
>> +	mutex_lock(&intel_dp->psr.lock);
>> +	/* If delayed work is pending, it is not idle */
>> +	if (delayed_work_pending(&intel_dp->psr.dc3co_work))
>> +		goto unlock;
>> +	/* enable DC6 after idle frames*/
>> +	psr2_dc3co_disable(intel_dp);
>> +
>> +unlock:
>> +	mutex_unlock(&intel_dp->psr.lock);
>> +}
>> +
>> +/*
>> + * When we will be completely rely on PSR2 S/W tracking in future,
>> + * intel_psr_flush() will invalidate and flush the PSR for
>> ORIGIN_FLIP
>> + * event also therefore psr2_dc3co_flush_locked() require to be
>> changed
>> + * accordingly in future.
>> + */
>> +
>> +static void
>> +psr2_dc3co_flush_locked(struct intel_dp *intel_dp, unsigned int
>> frontbuffer_bits,
>> +			enum fb_op_origin origin)
>> +{
>> +	struct intel_display *display = to_intel_display(intel_dp);
>> +	struct i915_power_domains *power_domains = &display-
>>> power.domains;
>> +
>> +	if (!(power_domains->allowed_dc_mask &
>> DC_STATE_EN_UPTO_DC3CO))
>> +		return;
>> +
>> +	if (!intel_dp->psr.sel_update_enabled ||
>> +	    !intel_dp->psr.active)
>> +		return;
>> +	/*
>> +	 * At every frontbuffer flush flip event modified delay of
>> delayed work,
>> +	 * when delayed work schedules that means display has been
>> idle.
>> +	 */
>> +	if (!(frontbuffer_bits &
>> +	    INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe)))
>> +		return;
>> +
>> +	mod_delayed_work(display->wq.unordered, &intel_dp-
>>> psr.dc3co_work,
>> +			 intel_dp->psr.dc3co_exit_delay);
>> +}
>> +
>>   static bool intel_psr2_sel_fetch_config_valid(struct intel_dp
>> *intel_dp,
>>   					      struct
>> intel_crtc_state *crtc_state)
>>   {
>> @@ -2117,7 +2189,7 @@ static void intel_psr_exit(struct intel_dp
>> *intel_dp)
>>   		intel_de_rmw(display, TRANS_DP2_CTL(intel_dp-
>>> psr.transcoder),
>>   			     TRANS_DP2_PANEL_REPLAY_ENABLE, 0);
>>   	} else if (intel_dp->psr.sel_update_enabled) {
>> -
>> +		psr2_dc3co_disable_on_exit(intel_dp);
>>   		val = intel_de_rmw(display,
>>   				   EDP_PSR2_CTL(display,
>> cpu_transcoder),
>>   				   EDP_PSR2_ENABLE, 0);
>> @@ -2259,6 +2331,7 @@ void intel_psr_disable(struct intel_dp
>> *intel_dp,
>>   
>>   	mutex_unlock(&intel_dp->psr.lock);
>>   	cancel_work_sync(&intel_dp->psr.work);
>> +	cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);
>>   }
>>   
>>   /**
>> @@ -2289,6 +2362,7 @@ void intel_psr_pause(struct intel_dp *intel_dp)
>>   	mutex_unlock(&psr->lock);
>>   
>>   	cancel_work_sync(&psr->work);
>> +	cancel_delayed_work_sync(&psr->dc3co_work);
>>   }
>>   
>>   /**
>> @@ -3475,6 +3549,7 @@ void intel_psr_flush(struct intel_display
>> *display,
>>   		if (origin == ORIGIN_FLIP ||
>>   		    (origin == ORIGIN_CURSOR_UPDATE &&
>>   		     !intel_dp->psr.psr2_sel_fetch_enabled)) {
>> +			psr2_dc3co_flush_locked(intel_dp,
>> frontbuffer_bits, origin);
>>   			goto unlock;
>>   		}
>>   
>> @@ -3533,6 +3608,7 @@ void intel_psr_init(struct intel_dp *intel_dp)
>>   		intel_dp->psr.link_standby = connector-
>>> panel.vbt.psr.full_link;
>>   
>>   	INIT_WORK(&intel_dp->psr.work, intel_psr_work);
>> +	INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work,
>> psr2_dc3co_disable_work);
>>   	mutex_init(&intel_dp->psr.lock);
>>   }
>>   

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Re: [PATCH 9/9] drm/i915/display: Add DC3CO disable handling for psr2

[Hogander, Jouni]

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On Tue, 2025-12-16 at 13:54 +0530, Dibin Moolakadan Subrahmanian wrote:


On 12-12-2025 12:41, Hogander, Jouni wrote:


On Tue, 2025-12-09 at 17:03 +0530, Dibin Moolakadan Subrahmanian wrote:


dc6 should be enabled instead of dc3co after  6 idle frames

while in psr2.(re enable part of tgl dc3co handling)

This is for PSR and pretty much following existing (disabled) TGL DC3CO

control. What is your idea how selection between DC6 and DC3CO will be

done in case of LOBF?

For both LOBF and PSR dc3co will be enabled from intel_atomic_commit_tail() it self.

This patch selects DC6 after 6 idle frames for PSR.

But how you are planning to do the same for LOBF? I think they should have common control.

BR,
Jouni Högander



BR,


Jouni Högander



Signed-off-by: Dibin Moolakadan Subrahmanian

<dibin.moolakadan.subrahmanian@intel.com><mailto:dibin.moolakadan.subrahmanian@intel.com>

---

 .../drm/i915/display/intel_display_types.h    |  1 +

 drivers/gpu/drm/i915/display/intel_psr.c      | 78

++++++++++++++++++-

 2 files changed, 78 insertions(+), 1 deletion(-)


diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h

b/drivers/gpu/drm/i915/display/intel_display_types.h

index 27f69df7ee9c..6ff53cd58052 100644

--- a/drivers/gpu/drm/i915/display/intel_display_types.h

+++ b/drivers/gpu/drm/i915/display/intel_display_types.h

@@ -1759,6 +1759,7 @@ struct intel_psr {

        bool panel_replay_enabled;

        u32 dc3co_exitline;

        u32 dc3co_exit_delay;

+       struct delayed_work dc3co_work;

        u8 entry_setup_frames;



        u8 io_wake_lines;

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c

b/drivers/gpu/drm/i915/display/intel_psr.c

index 18bf45455ea2..4be709d1d324 100644

--- a/drivers/gpu/drm/i915/display/intel_psr.c

+++ b/drivers/gpu/drm/i915/display/intel_psr.c

@@ -1157,6 +1157,78 @@ static void psr2_program_idle_frames(struct

intel_dp *intel_dp,

                     EDP_PSR2_IDLE_FRAMES(idle_frames));

 }



+static void psr2_dc3co_disable(struct intel_dp *intel_dp)

+{

+       struct intel_display *display = to_intel_display(intel_dp);

+       struct i915_power_domains *power_domains = &display-


power.domains;

+

+       if ((power_domains->allowed_dc_mask &

DC_STATE_EN_UPTO_DC3CO) != DC_STATE_EN_UPTO_DC3CO)

+               return;

+

+       intel_display_power_set_target_dc_state(display,

DC_STATE_EN_UPTO_DC6);

+       /* Todo restore PSR2 idle frames , ALPM control*/

+}

+

+static void psr2_dc3co_disable_on_exit(struct intel_dp *intel_dp)

+{

+       struct intel_display *display = to_intel_display(intel_dp);

+       struct i915_power_domains *power_domains = &display-


power.domains;

+

+       if ((power_domains->allowed_dc_mask &

DC_STATE_EN_UPTO_DC3CO) != DC_STATE_EN_UPTO_DC3CO)

+               return;

+

+       cancel_delayed_work(&intel_dp->psr.dc3co_work);

+       intel_dc3co_source_unset(display, DC3CO_SOURCE_PSR2);

+}

+

+static void psr2_dc3co_disable_work(struct work_struct *work)

+{

+       struct intel_dp *intel_dp =

+               container_of(work, typeof(*intel_dp),

psr.dc3co_work.work);

+

+       mutex_lock(&intel_dp->psr.lock);

+       /* If delayed work is pending, it is not idle */

+       if (delayed_work_pending(&intel_dp->psr.dc3co_work))

+               goto unlock;

+       /* enable DC6 after idle frames*/

+       psr2_dc3co_disable(intel_dp);

+

+unlock:

+       mutex_unlock(&intel_dp->psr.lock);

+}

+

+/*

+ * When we will be completely rely on PSR2 S/W tracking in future,

+ * intel_psr_flush() will invalidate and flush the PSR for

ORIGIN_FLIP

+ * event also therefore psr2_dc3co_flush_locked() require to be

changed

+ * accordingly in future.

+ */

+

+static void

+psr2_dc3co_flush_locked(struct intel_dp *intel_dp, unsigned int

frontbuffer_bits,

+                       enum fb_op_origin origin)

+{

+       struct intel_display *display = to_intel_display(intel_dp);

+       struct i915_power_domains *power_domains = &display-


power.domains;

+

+       if (!(power_domains->allowed_dc_mask &

DC_STATE_EN_UPTO_DC3CO))

+               return;

+

+       if (!intel_dp->psr.sel_update_enabled ||

+           !intel_dp->psr.active)

+               return;

+       /*

+        * At every frontbuffer flush flip event modified delay of

delayed work,

+        * when delayed work schedules that means display has been

idle.

+        */

+       if (!(frontbuffer_bits &

+           INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe)))

+               return;

+

+       mod_delayed_work(display->wq.unordered, &intel_dp-


psr.dc3co_work,

+                        intel_dp->psr.dc3co_exit_delay);

+}

+

 static bool intel_psr2_sel_fetch_config_valid(struct intel_dp

*intel_dp,

                                              struct

intel_crtc_state *crtc_state)

 {

@@ -2117,7 +2189,7 @@ static void intel_psr_exit(struct intel_dp

*intel_dp)

                intel_de_rmw(display, TRANS_DP2_CTL(intel_dp-


psr.transcoder),

                             TRANS_DP2_PANEL_REPLAY_ENABLE, 0);

        } else if (intel_dp->psr.sel_update_enabled) {

-

+               psr2_dc3co_disable_on_exit(intel_dp);

                val = intel_de_rmw(display,

                                   EDP_PSR2_CTL(display,

cpu_transcoder),

                                   EDP_PSR2_ENABLE, 0);

@@ -2259,6 +2331,7 @@ void intel_psr_disable(struct intel_dp

*intel_dp,



        mutex_unlock(&intel_dp->psr.lock);

        cancel_work_sync(&intel_dp->psr.work);

+       cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);

 }



 /**

@@ -2289,6 +2362,7 @@ void intel_psr_pause(struct intel_dp *intel_dp)

        mutex_unlock(&psr->lock);



        cancel_work_sync(&psr->work);

+       cancel_delayed_work_sync(&psr->dc3co_work);

 }



 /**

@@ -3475,6 +3549,7 @@ void intel_psr_flush(struct intel_display

*display,

                if (origin == ORIGIN_FLIP ||

                    (origin == ORIGIN_CURSOR_UPDATE &&

                     !intel_dp->psr.psr2_sel_fetch_enabled)) {

+                       psr2_dc3co_flush_locked(intel_dp,

frontbuffer_bits, origin);

                        goto unlock;

                }



@@ -3533,6 +3608,7 @@ void intel_psr_init(struct intel_dp *intel_dp)

                intel_dp->psr.link_standby = connector-


panel.vbt.psr.full_link;



        INIT_WORK(&intel_dp->psr.work, intel_psr_work);

+       INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work,

psr2_dc3co_disable_work);

        mutex_init(&intel_dp->psr.lock);

 }




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Re: [PATCH 9/9] drm/i915/display: Add DC3CO disable handling for psr2

[Dibin Moolakadan Subrahmanian]

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On 16-12-2025 14:00, Hogander, Jouni wrote:
> On Tue, 2025-12-16 at 13:54 +0530, Dibin Moolakadan Subrahmanian wrote:
> >
> >
> > On 12-12-2025 12:41, Hogander, Jouni wrote:
> >
> >> On Tue, 2025-12-09 at 17:03 +0530, Dibin Moolakadan Subrahmanian wrote:
> >>
> >>> dc6 should be enabled instead of dc3co after  6 idle frames
> >>> while in psr2.(re enable part of tgl dc3co handling)
> >> This is for PSR and pretty much following existing (disabled) TGL DC3CO
> >> control. What is your idea how selection between DC6 and DC3CO will be
> >> done in case of LOBF?
> > For both LOBF and PSR dc3co will be enabled from intel_atomic_commit_tail() it self.
> > This patch selects DC6 after 6 idle frames for PSR.
>
> But how you are planning to do the same for LOBF? I think they should have
> common control.

Planning not to enable DC6 for LOBF, only DC3CO will be enabled in LOBF.

> BR,
> Jouni Högander
>
> >
> >> BR,
> >>
> >> Jouni Högander
> >>
> >>
> >>> Signed-off-by: Dibin Moolakadan Subrahmanian
> >>> <dibin.moolakadan.subrahmanian@intel.com>
> >>> ---
> >>>   .../drm/i915/display/intel_display_types.h    |  1 +
> >>>   drivers/gpu/drm/i915/display/intel_psr.c      | 78
> >>> ++++++++++++++++++-
> >>>   2 files changed, 78 insertions(+), 1 deletion(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> >>> b/drivers/gpu/drm/i915/display/intel_display_types.h
> >>> index 27f69df7ee9c..6ff53cd58052 100644
> >>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> >>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> >>> @@ -1759,6 +1759,7 @@ struct intel_psr {
> >>>   	bool panel_replay_enabled;
> >>>   	u32 dc3co_exitline;
> >>>   	u32 dc3co_exit_delay;
> >>> +	struct delayed_work dc3co_work;
> >>>   	u8 entry_setup_frames;
> >>>   
> >>>   	u8 io_wake_lines;
> >>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> >>> b/drivers/gpu/drm/i915/display/intel_psr.c
> >>> index 18bf45455ea2..4be709d1d324 100644
> >>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> >>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> >>> @@ -1157,6 +1157,78 @@ static void psr2_program_idle_frames(struct
> >>> intel_dp *intel_dp,
> >>>   		     EDP_PSR2_IDLE_FRAMES(idle_frames));
> >>>   }
> >>>   
> >>> +static void psr2_dc3co_disable(struct intel_dp *intel_dp)
> >>> +{
> >>> +	struct intel_display *display = to_intel_display(intel_dp);
> >>> +	struct i915_power_domains *power_domains = &display-
> >>>
> >>>> power.domains;
> >>> +
> >>> +	if ((power_domains->allowed_dc_mask &
> >>> DC_STATE_EN_UPTO_DC3CO) != DC_STATE_EN_UPTO_DC3CO)
> >>> +		return;
> >>> +
> >>> +	intel_display_power_set_target_dc_state(display,
> >>> DC_STATE_EN_UPTO_DC6);
> >>> +	/* Todo restore PSR2 idle frames , ALPM control*/
> >>> +}
> >>> +
> >>> +static void psr2_dc3co_disable_on_exit(struct intel_dp *intel_dp)
> >>> +{
> >>> +	struct intel_display *display = to_intel_display(intel_dp);
> >>> +	struct i915_power_domains *power_domains = &display-
> >>>
> >>>> power.domains;
> >>> +
> >>> +	if ((power_domains->allowed_dc_mask &
> >>> DC_STATE_EN_UPTO_DC3CO) != DC_STATE_EN_UPTO_DC3CO)
> >>> +		return;
> >>> +
> >>> +	cancel_delayed_work(&intel_dp->psr.dc3co_work);
> >>> +	intel_dc3co_source_unset(display, DC3CO_SOURCE_PSR2);
> >>> +}
> >>> +
> >>> +static void psr2_dc3co_disable_work(struct work_struct *work)
> >>> +{
> >>> +	struct intel_dp *intel_dp =
> >>> +		container_of(work, typeof(*intel_dp),
> >>> psr.dc3co_work.work);
> >>> +
> >>> +	mutex_lock(&intel_dp->psr.lock);
> >>> +	/* If delayed work is pending, it is not idle */
> >>> +	if (delayed_work_pending(&intel_dp->psr.dc3co_work))
> >>> +		goto unlock;
> >>> +	/* enable DC6 after idle frames*/
> >>> +	psr2_dc3co_disable(intel_dp);
> >>> +
> >>> +unlock:
> >>> +	mutex_unlock(&intel_dp->psr.lock);
> >>> +}
> >>> +
> >>> +/*
> >>> + * When we will be completely rely on PSR2 S/W tracking in future,
> >>> + * intel_psr_flush() will invalidate and flush the PSR for
> >>> ORIGIN_FLIP
> >>> + * event also therefore psr2_dc3co_flush_locked() require to be
> >>> changed
> >>> + * accordingly in future.
> >>> + */
> >>> +
> >>> +static void
> >>> +psr2_dc3co_flush_locked(struct intel_dp *intel_dp, unsigned int
> >>> frontbuffer_bits,
> >>> +			enum fb_op_origin origin)
> >>> +{
> >>> +	struct intel_display *display = to_intel_display(intel_dp);
> >>> +	struct i915_power_domains *power_domains = &display-
> >>>
> >>>> power.domains;
> >>> +
> >>> +	if (!(power_domains->allowed_dc_mask &
> >>> DC_STATE_EN_UPTO_DC3CO))
> >>> +		return;
> >>> +
> >>> +	if (!intel_dp->psr.sel_update_enabled ||
> >>> +	    !intel_dp->psr.active)
> >>> +		return;
> >>> +	/*
> >>> +	 * At every frontbuffer flush flip event modified delay of
> >>> delayed work,
> >>> +	 * when delayed work schedules that means display has been
> >>> idle.
> >>> +	 */
> >>> +	if (!(frontbuffer_bits &
> >>> +	    INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe)))
> >>> +		return;
> >>> +
> >>> +	mod_delayed_work(display->wq.unordered, &intel_dp-
> >>>
> >>>> psr.dc3co_work,
> >>> +			 intel_dp->psr.dc3co_exit_delay);
> >>> +}
> >>> +
> >>>   static bool intel_psr2_sel_fetch_config_valid(struct intel_dp
> >>> *intel_dp,
> >>>   					      struct
> >>> intel_crtc_state *crtc_state)
> >>>   {
> >>> @@ -2117,7 +2189,7 @@ static void intel_psr_exit(struct intel_dp
> >>> *intel_dp)
> >>>   		intel_de_rmw(display, TRANS_DP2_CTL(intel_dp-
> >>>
> >>>> psr.transcoder),
> >>>   			     TRANS_DP2_PANEL_REPLAY_ENABLE, 0);
> >>>   	} else if (intel_dp->psr.sel_update_enabled) {
> >>> -
> >>> +		psr2_dc3co_disable_on_exit(intel_dp);
> >>>   		val = intel_de_rmw(display,
> >>>   				   EDP_PSR2_CTL(display,
> >>> cpu_transcoder),
> >>>   				   EDP_PSR2_ENABLE, 0);
> >>> @@ -2259,6 +2331,7 @@ void intel_psr_disable(struct intel_dp
> >>> *intel_dp,
> >>>   
> >>>   	mutex_unlock(&intel_dp->psr.lock);
> >>>   	cancel_work_sync(&intel_dp->psr.work);
> >>> +	cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);
> >>>   }
> >>>   
> >>>   /**
> >>> @@ -2289,6 +2362,7 @@ void intel_psr_pause(struct intel_dp *intel_dp)
> >>>   	mutex_unlock(&psr->lock);
> >>>   
> >>>   	cancel_work_sync(&psr->work);
> >>> +	cancel_delayed_work_sync(&psr->dc3co_work);
> >>>   }
> >>>   
> >>>   /**
> >>> @@ -3475,6 +3549,7 @@ void intel_psr_flush(struct intel_display
> >>> *display,
> >>>   		if (origin == ORIGIN_FLIP ||
> >>>   		    (origin == ORIGIN_CURSOR_UPDATE &&
> >>>   		     !intel_dp->psr.psr2_sel_fetch_enabled)) {
> >>> +			psr2_dc3co_flush_locked(intel_dp,
> >>> frontbuffer_bits, origin);
> >>>   			goto unlock;
> >>>   		}
> >>>   
> >>> @@ -3533,6 +3608,7 @@ void intel_psr_init(struct intel_dp *intel_dp)
> >>>   		intel_dp->psr.link_standby = connector-
> >>>
> >>>> panel.vbt.psr.full_link;
> >>>   
> >>>   	INIT_WORK(&intel_dp->psr.work, intel_psr_work);
> >>> +	INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work,
> >>> psr2_dc3co_disable_work);
> >>>   	mutex_init(&intel_dp->psr.lock);
> >>>   }
> >>>   
>

[-- Attachment #2: Type: text/html, Size: 9119 bytes --]

Re: [PATCH 9/9] drm/i915/display: Add DC3CO disable handling for psr2

[Jani Nikula]

On Tue, 09 Dec 2025, Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com> wrote:
> dc6 should be enabled instead of dc3co after  6 idle frames
> while in psr2.(re enable part of tgl dc3co handling)

Please write proper commit messages. I don't understand what this patch
is supposed to do based on this.

> Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
> ---
>  .../drm/i915/display/intel_display_types.h    |  1 +
>  drivers/gpu/drm/i915/display/intel_psr.c      | 78 ++++++++++++++++++-
>  2 files changed, 78 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 27f69df7ee9c..6ff53cd58052 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1759,6 +1759,7 @@ struct intel_psr {
>  	bool panel_replay_enabled;
>  	u32 dc3co_exitline;
>  	u32 dc3co_exit_delay;
> +	struct delayed_work dc3co_work;
>  	u8 entry_setup_frames;
>  
>  	u8 io_wake_lines;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 18bf45455ea2..4be709d1d324 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1157,6 +1157,78 @@ static void psr2_program_idle_frames(struct intel_dp *intel_dp,
>  		     EDP_PSR2_IDLE_FRAMES(idle_frames));
>  }
>  
> +static void psr2_dc3co_disable(struct intel_dp *intel_dp)
> +{
> +	struct intel_display *display = to_intel_display(intel_dp);
> +	struct i915_power_domains *power_domains = &display->power.domains;

There's currently one place in intel_psr.c that checks
power_domains->allowed_dc_mask, and I think even that is too much.

display->power belongs to intel_display_power*.c, and nobody else.

I think you probably need a helper function to ask for this stuff from
power modules.

> +
> +	if ((power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC3CO) != DC_STATE_EN_UPTO_DC3CO)
> +		return;
> +
> +	intel_display_power_set_target_dc_state(display, DC_STATE_EN_UPTO_DC6);
> +	/* Todo restore PSR2 idle frames , ALPM control*/

	/* TODO: restore PSR2 idle frames, ALPM control */

> +}
> +
> +static void psr2_dc3co_disable_on_exit(struct intel_dp *intel_dp)
> +{
> +	struct intel_display *display = to_intel_display(intel_dp);
> +	struct i915_power_domains *power_domains = &display->power.domains;
> +
> +	if ((power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC3CO) != DC_STATE_EN_UPTO_DC3CO)
> +		return;
> +
> +	cancel_delayed_work(&intel_dp->psr.dc3co_work);
> +	intel_dc3co_source_unset(display, DC3CO_SOURCE_PSR2);
> +}
> +
> +static void psr2_dc3co_disable_work(struct work_struct *work)
> +{
> +	struct intel_dp *intel_dp =
> +		container_of(work, typeof(*intel_dp), psr.dc3co_work.work);
> +
> +	mutex_lock(&intel_dp->psr.lock);
> +	/* If delayed work is pending, it is not idle */
> +	if (delayed_work_pending(&intel_dp->psr.dc3co_work))
> +		goto unlock;
> +	/* enable DC6 after idle frames*/
> +	psr2_dc3co_disable(intel_dp);
> +
> +unlock:
> +	mutex_unlock(&intel_dp->psr.lock);
> +}
> +
> +/*
> + * When we will be completely rely on PSR2 S/W tracking in future,
> + * intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP
> + * event also therefore psr2_dc3co_flush_locked() require to be changed
> + * accordingly in future.
> + */
> +
> +static void
> +psr2_dc3co_flush_locked(struct intel_dp *intel_dp, unsigned int frontbuffer_bits,
> +			enum fb_op_origin origin)
> +{
> +	struct intel_display *display = to_intel_display(intel_dp);
> +	struct i915_power_domains *power_domains = &display->power.domains;
> +
> +	if (!(power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC3CO))
> +		return;
> +
> +	if (!intel_dp->psr.sel_update_enabled ||
> +	    !intel_dp->psr.active)
> +		return;
> +	/*
> +	 * At every frontbuffer flush flip event modified delay of delayed work,
> +	 * when delayed work schedules that means display has been idle.
> +	 */
> +	if (!(frontbuffer_bits &
> +	    INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe)))
> +		return;
> +
> +	mod_delayed_work(display->wq.unordered, &intel_dp->psr.dc3co_work,
> +			 intel_dp->psr.dc3co_exit_delay);
> +}
> +
>  static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
>  					      struct intel_crtc_state *crtc_state)
>  {
> @@ -2117,7 +2189,7 @@ static void intel_psr_exit(struct intel_dp *intel_dp)
>  		intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder),
>  			     TRANS_DP2_PANEL_REPLAY_ENABLE, 0);
>  	} else if (intel_dp->psr.sel_update_enabled) {
> -
> +		psr2_dc3co_disable_on_exit(intel_dp);
>  		val = intel_de_rmw(display,
>  				   EDP_PSR2_CTL(display, cpu_transcoder),
>  				   EDP_PSR2_ENABLE, 0);
> @@ -2259,6 +2331,7 @@ void intel_psr_disable(struct intel_dp *intel_dp,
>  
>  	mutex_unlock(&intel_dp->psr.lock);
>  	cancel_work_sync(&intel_dp->psr.work);
> +	cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);
>  }
>  
>  /**
> @@ -2289,6 +2362,7 @@ void intel_psr_pause(struct intel_dp *intel_dp)
>  	mutex_unlock(&psr->lock);
>  
>  	cancel_work_sync(&psr->work);
> +	cancel_delayed_work_sync(&psr->dc3co_work);
>  }
>  
>  /**
> @@ -3475,6 +3549,7 @@ void intel_psr_flush(struct intel_display *display,
>  		if (origin == ORIGIN_FLIP ||
>  		    (origin == ORIGIN_CURSOR_UPDATE &&
>  		     !intel_dp->psr.psr2_sel_fetch_enabled)) {
> +			psr2_dc3co_flush_locked(intel_dp, frontbuffer_bits, origin);
>  			goto unlock;
>  		}
>  
> @@ -3533,6 +3608,7 @@ void intel_psr_init(struct intel_dp *intel_dp)
>  		intel_dp->psr.link_standby = connector->panel.vbt.psr.full_link;
>  
>  	INIT_WORK(&intel_dp->psr.work, intel_psr_work);
> +	INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, psr2_dc3co_disable_work);
>  	mutex_init(&intel_dp->psr.lock);
>  }

-- 
Jani Nikula, Intel

Re: [PATCH 9/9] drm/i915/display: Add DC3CO disable handling for psr2

[Dibin Moolakadan Subrahmanian]

[-- Attachment #1: Type: text/plain, Size: 6570 bytes --]


On 05-01-2026 18:31, Jani Nikula wrote:
> On Tue, 09 Dec 2025, Dibin Moolakadan Subrahmanian<dibin.moolakadan.subrahmanian@intel.com> wrote:
>> dc6 should be enabled instead of dc3co after  6 idle frames
>> while in psr2.(re enable part of tgl dc3co handling)
> Please write proper commit messages. I don't understand what this patch
> is supposed to do based on this.

I will add more details to commit message .
On TGL, original code disabled DC3CO after 6 consecutive idle frames and
re-enabled DC6. That logic was removed for the new DC3CO design. This patch
restores the behavior in PSR2, switching from DC3CO to DC6 after 6 idle
frames to maintain correct power management.

>
>> Signed-off-by: Dibin Moolakadan Subrahmanian<dibin.moolakadan.subrahmanian@intel.com>
>> ---
>>   .../drm/i915/display/intel_display_types.h    |  1 +
>>   drivers/gpu/drm/i915/display/intel_psr.c      | 78 ++++++++++++++++++-
>>   2 files changed, 78 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index 27f69df7ee9c..6ff53cd58052 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -1759,6 +1759,7 @@ struct intel_psr {
>>   	bool panel_replay_enabled;
>>   	u32 dc3co_exitline;
>>   	u32 dc3co_exit_delay;
>> +	struct delayed_work dc3co_work;
>>   	u8 entry_setup_frames;
>>   
>>   	u8 io_wake_lines;
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>> index 18bf45455ea2..4be709d1d324 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>> @@ -1157,6 +1157,78 @@ static void psr2_program_idle_frames(struct intel_dp *intel_dp,
>>   		     EDP_PSR2_IDLE_FRAMES(idle_frames));
>>   }
>>   
>> +static void psr2_dc3co_disable(struct intel_dp *intel_dp)
>> +{
>> +	struct intel_display *display = to_intel_display(intel_dp);
>> +	struct i915_power_domains *power_domains = &display->power.domains;
> There's currently one place in intel_psr.c that checks
> power_domains->allowed_dc_mask, and I think even that is too much.
>
> display->power belongs to intel_display_power*.c, and nobody else.
>
> I think you probably need a helper function to ask for this stuff from
> power modules.

Thanks for pointing this out.
I will add a helper function in intel_display_power.c to query this
instead of accessing display->power directly.

>> +
>> +	if ((power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC3CO) != DC_STATE_EN_UPTO_DC3CO)
>> +		return;
>> +
>> +	intel_display_power_set_target_dc_state(display, DC_STATE_EN_UPTO_DC6);
>> +	/* Todo restore PSR2 idle frames , ALPM control*/
> 	/* TODO: restore PSR2 idle frames, ALPM control */
>
>> +}
>> +
>> +static void psr2_dc3co_disable_on_exit(struct intel_dp *intel_dp)
>> +{
>> +	struct intel_display *display = to_intel_display(intel_dp);
>> +	struct i915_power_domains *power_domains = &display->power.domains;
>> +
>> +	if ((power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC3CO) != DC_STATE_EN_UPTO_DC3CO)
>> +		return;
>> +
>> +	cancel_delayed_work(&intel_dp->psr.dc3co_work);
>> +	intel_dc3co_source_unset(display, DC3CO_SOURCE_PSR2);
>> +}
>> +
>> +static void psr2_dc3co_disable_work(struct work_struct *work)
>> +{
>> +	struct intel_dp *intel_dp =
>> +		container_of(work, typeof(*intel_dp), psr.dc3co_work.work);
>> +
>> +	mutex_lock(&intel_dp->psr.lock);
>> +	/* If delayed work is pending, it is not idle */
>> +	if (delayed_work_pending(&intel_dp->psr.dc3co_work))
>> +		goto unlock;
>> +	/* enable DC6 after idle frames*/
>> +	psr2_dc3co_disable(intel_dp);
>> +
>> +unlock:
>> +	mutex_unlock(&intel_dp->psr.lock);
>> +}
>> +
>> +/*
>> + * When we will be completely rely on PSR2 S/W tracking in future,
>> + * intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP
>> + * event also therefore psr2_dc3co_flush_locked() require to be changed
>> + * accordingly in future.
>> + */
>> +
>> +static void
>> +psr2_dc3co_flush_locked(struct intel_dp *intel_dp, unsigned int frontbuffer_bits,
>> +			enum fb_op_origin origin)
>> +{
>> +	struct intel_display *display = to_intel_display(intel_dp);
>> +	struct i915_power_domains *power_domains = &display->power.domains;
>> +
>> +	if (!(power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC3CO))
>> +		return;
>> +
>> +	if (!intel_dp->psr.sel_update_enabled ||
>> +	    !intel_dp->psr.active)
>> +		return;
>> +	/*
>> +	 * At every frontbuffer flush flip event modified delay of delayed work,
>> +	 * when delayed work schedules that means display has been idle.
>> +	 */
>> +	if (!(frontbuffer_bits &
>> +	    INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe)))
>> +		return;
>> +
>> +	mod_delayed_work(display->wq.unordered, &intel_dp->psr.dc3co_work,
>> +			 intel_dp->psr.dc3co_exit_delay);
>> +}
>> +
>>   static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
>>   					      struct intel_crtc_state *crtc_state)
>>   {
>> @@ -2117,7 +2189,7 @@ static void intel_psr_exit(struct intel_dp *intel_dp)
>>   		intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder),
>>   			     TRANS_DP2_PANEL_REPLAY_ENABLE, 0);
>>   	} else if (intel_dp->psr.sel_update_enabled) {
>> -
>> +		psr2_dc3co_disable_on_exit(intel_dp);
>>   		val = intel_de_rmw(display,
>>   				   EDP_PSR2_CTL(display, cpu_transcoder),
>>   				   EDP_PSR2_ENABLE, 0);
>> @@ -2259,6 +2331,7 @@ void intel_psr_disable(struct intel_dp *intel_dp,
>>   
>>   	mutex_unlock(&intel_dp->psr.lock);
>>   	cancel_work_sync(&intel_dp->psr.work);
>> +	cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);
>>   }
>>   
>>   /**
>> @@ -2289,6 +2362,7 @@ void intel_psr_pause(struct intel_dp *intel_dp)
>>   	mutex_unlock(&psr->lock);
>>   
>>   	cancel_work_sync(&psr->work);
>> +	cancel_delayed_work_sync(&psr->dc3co_work);
>>   }
>>   
>>   /**
>> @@ -3475,6 +3549,7 @@ void intel_psr_flush(struct intel_display *display,
>>   		if (origin == ORIGIN_FLIP ||
>>   		    (origin == ORIGIN_CURSOR_UPDATE &&
>>   		     !intel_dp->psr.psr2_sel_fetch_enabled)) {
>> +			psr2_dc3co_flush_locked(intel_dp, frontbuffer_bits, origin);
>>   			goto unlock;
>>   		}
>>   
>> @@ -3533,6 +3608,7 @@ void intel_psr_init(struct intel_dp *intel_dp)
>>   		intel_dp->psr.link_standby = connector->panel.vbt.psr.full_link;
>>   
>>   	INIT_WORK(&intel_dp->psr.work, intel_psr_work);
>> +	INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, psr2_dc3co_disable_work);
>>   	mutex_init(&intel_dp->psr.lock);
>>   }

[-- Attachment #2: Type: text/html, Size: 7765 bytes --]

✓ CI.KUnit: success for drm/i915/display: DC3CO support

[Patchwork]

== Series Details ==

Series: drm/i915/display: DC3CO support
URL   : https://patchwork.freedesktop.org/series/158688/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[12:29:54] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[12:29:58] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[12:30:28] Starting KUnit Kernel (1/1)...
[12:30:28] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[12:30:29] ================== guc_buf (11 subtests) ===================
[12:30:29] [PASSED] test_smallest
[12:30:29] [PASSED] test_largest
[12:30:29] [PASSED] test_granular
[12:30:29] [PASSED] test_unique
[12:30:29] [PASSED] test_overlap
[12:30:29] [PASSED] test_reusable
[12:30:29] [PASSED] test_too_big
[12:30:29] [PASSED] test_flush
[12:30:29] [PASSED] test_lookup
[12:30:29] [PASSED] test_data
[12:30:29] [PASSED] test_class
[12:30:29] ===================== [PASSED] guc_buf =====================
[12:30:29] =================== guc_dbm (7 subtests) ===================
[12:30:29] [PASSED] test_empty
[12:30:29] [PASSED] test_default
[12:30:29] ======================== test_size  ========================
[12:30:29] [PASSED] 4
[12:30:29] [PASSED] 8
[12:30:29] [PASSED] 32
[12:30:29] [PASSED] 256
[12:30:29] ==================== [PASSED] test_size ====================
[12:30:29] ======================= test_reuse  ========================
[12:30:29] [PASSED] 4
[12:30:29] [PASSED] 8
[12:30:29] [PASSED] 32
[12:30:29] [PASSED] 256
[12:30:29] =================== [PASSED] test_reuse ====================
[12:30:29] =================== test_range_overlap  ====================
[12:30:29] [PASSED] 4
[12:30:29] [PASSED] 8
[12:30:29] [PASSED] 32
[12:30:29] [PASSED] 256
[12:30:29] =============== [PASSED] test_range_overlap ================
[12:30:29] =================== test_range_compact  ====================
[12:30:29] [PASSED] 4
[12:30:29] [PASSED] 8
[12:30:29] [PASSED] 32
[12:30:29] [PASSED] 256
[12:30:29] =============== [PASSED] test_range_compact ================
[12:30:29] ==================== test_range_spare  =====================
[12:30:29] [PASSED] 4
[12:30:29] [PASSED] 8
[12:30:29] [PASSED] 32
[12:30:29] [PASSED] 256
[12:30:29] ================ [PASSED] test_range_spare =================
[12:30:29] ===================== [PASSED] guc_dbm =====================
[12:30:29] =================== guc_idm (6 subtests) ===================
[12:30:29] [PASSED] bad_init
[12:30:29] [PASSED] no_init
[12:30:29] [PASSED] init_fini
[12:30:29] [PASSED] check_used
[12:30:29] [PASSED] check_quota
[12:30:29] [PASSED] check_all
[12:30:29] ===================== [PASSED] guc_idm =====================
[12:30:29] ================== no_relay (3 subtests) ===================
[12:30:29] [PASSED] xe_drops_guc2pf_if_not_ready
[12:30:29] [PASSED] xe_drops_guc2vf_if_not_ready
[12:30:29] [PASSED] xe_rejects_send_if_not_ready
[12:30:29] ==================== [PASSED] no_relay =====================
[12:30:29] ================== pf_relay (14 subtests) ==================
[12:30:29] [PASSED] pf_rejects_guc2pf_too_short
[12:30:29] [PASSED] pf_rejects_guc2pf_too_long
[12:30:29] [PASSED] pf_rejects_guc2pf_no_payload
[12:30:29] [PASSED] pf_fails_no_payload
[12:30:29] [PASSED] pf_fails_bad_origin
[12:30:29] [PASSED] pf_fails_bad_type
[12:30:29] [PASSED] pf_txn_reports_error
[12:30:29] [PASSED] pf_txn_sends_pf2guc
[12:30:29] [PASSED] pf_sends_pf2guc
[12:30:29] [SKIPPED] pf_loopback_nop
[12:30:29] [SKIPPED] pf_loopback_echo
[12:30:29] [SKIPPED] pf_loopback_fail
[12:30:29] [SKIPPED] pf_loopback_busy
[12:30:29] [SKIPPED] pf_loopback_retry
[12:30:29] ==================== [PASSED] pf_relay =====================
[12:30:29] ================== vf_relay (3 subtests) ===================
[12:30:29] [PASSED] vf_rejects_guc2vf_too_short
[12:30:29] [PASSED] vf_rejects_guc2vf_too_long
[12:30:29] [PASSED] vf_rejects_guc2vf_no_payload
[12:30:29] ==================== [PASSED] vf_relay =====================
[12:30:29] ================ pf_gt_config (6 subtests) =================
[12:30:29] [PASSED] fair_contexts_1vf
[12:30:29] [PASSED] fair_doorbells_1vf
[12:30:29] [PASSED] fair_ggtt_1vf
[12:30:29] ====================== fair_contexts  ======================
[12:30:29] [PASSED] 1 VF
[12:30:29] [PASSED] 2 VFs
[12:30:29] [PASSED] 3 VFs
[12:30:29] [PASSED] 4 VFs
[12:30:29] [PASSED] 5 VFs
[12:30:29] [PASSED] 6 VFs
[12:30:29] [PASSED] 7 VFs
[12:30:29] [PASSED] 8 VFs
[12:30:29] [PASSED] 9 VFs
[12:30:29] [PASSED] 10 VFs
[12:30:29] [PASSED] 11 VFs
[12:30:29] [PASSED] 12 VFs
[12:30:29] [PASSED] 13 VFs
[12:30:29] [PASSED] 14 VFs
[12:30:29] [PASSED] 15 VFs
[12:30:29] [PASSED] 16 VFs
[12:30:29] [PASSED] 17 VFs
[12:30:29] [PASSED] 18 VFs
[12:30:29] [PASSED] 19 VFs
[12:30:29] [PASSED] 20 VFs
[12:30:29] [PASSED] 21 VFs
[12:30:29] [PASSED] 22 VFs
[12:30:29] [PASSED] 23 VFs
[12:30:29] [PASSED] 24 VFs
[12:30:29] [PASSED] 25 VFs
[12:30:29] [PASSED] 26 VFs
[12:30:29] [PASSED] 27 VFs
[12:30:29] [PASSED] 28 VFs
[12:30:29] [PASSED] 29 VFs
[12:30:29] [PASSED] 30 VFs
[12:30:29] [PASSED] 31 VFs
[12:30:29] [PASSED] 32 VFs
[12:30:29] [PASSED] 33 VFs
[12:30:29] [PASSED] 34 VFs
[12:30:29] [PASSED] 35 VFs
[12:30:29] [PASSED] 36 VFs
[12:30:29] [PASSED] 37 VFs
[12:30:29] [PASSED] 38 VFs
[12:30:29] [PASSED] 39 VFs
[12:30:29] [PASSED] 40 VFs
[12:30:29] [PASSED] 41 VFs
[12:30:29] [PASSED] 42 VFs
[12:30:29] [PASSED] 43 VFs
[12:30:29] [PASSED] 44 VFs
[12:30:29] [PASSED] 45 VFs
[12:30:29] [PASSED] 46 VFs
[12:30:29] [PASSED] 47 VFs
[12:30:29] [PASSED] 48 VFs
[12:30:29] [PASSED] 49 VFs
[12:30:29] [PASSED] 50 VFs
[12:30:29] [PASSED] 51 VFs
[12:30:29] [PASSED] 52 VFs
[12:30:29] [PASSED] 53 VFs
[12:30:29] [PASSED] 54 VFs
[12:30:29] [PASSED] 55 VFs
[12:30:29] [PASSED] 56 VFs
[12:30:29] [PASSED] 57 VFs
[12:30:29] [PASSED] 58 VFs
[12:30:29] [PASSED] 59 VFs
[12:30:29] [PASSED] 60 VFs
[12:30:29] [PASSED] 61 VFs
[12:30:29] [PASSED] 62 VFs
[12:30:29] [PASSED] 63 VFs
[12:30:29] ================== [PASSED] fair_contexts ==================
[12:30:29] ===================== fair_doorbells  ======================
[12:30:29] [PASSED] 1 VF
[12:30:29] [PASSED] 2 VFs
[12:30:29] [PASSED] 3 VFs
[12:30:29] [PASSED] 4 VFs
[12:30:29] [PASSED] 5 VFs
[12:30:29] [PASSED] 6 VFs
[12:30:29] [PASSED] 7 VFs
[12:30:29] [PASSED] 8 VFs
[12:30:29] [PASSED] 9 VFs
[12:30:29] [PASSED] 10 VFs
[12:30:29] [PASSED] 11 VFs
[12:30:29] [PASSED] 12 VFs
[12:30:29] [PASSED] 13 VFs
[12:30:29] [PASSED] 14 VFs
[12:30:29] [PASSED] 15 VFs
[12:30:29] [PASSED] 16 VFs
[12:30:29] [PASSED] 17 VFs
[12:30:29] [PASSED] 18 VFs
[12:30:29] [PASSED] 19 VFs
[12:30:29] [PASSED] 20 VFs
[12:30:29] [PASSED] 21 VFs
[12:30:29] [PASSED] 22 VFs
[12:30:29] [PASSED] 23 VFs
[12:30:29] [PASSED] 24 VFs
[12:30:29] [PASSED] 25 VFs
[12:30:29] [PASSED] 26 VFs
[12:30:29] [PASSED] 27 VFs
[12:30:29] [PASSED] 28 VFs
[12:30:29] [PASSED] 29 VFs
[12:30:29] [PASSED] 30 VFs
[12:30:29] [PASSED] 31 VFs
[12:30:29] [PASSED] 32 VFs
[12:30:29] [PASSED] 33 VFs
[12:30:29] [PASSED] 34 VFs
[12:30:29] [PASSED] 35 VFs
[12:30:29] [PASSED] 36 VFs
[12:30:29] [PASSED] 37 VFs
[12:30:29] [PASSED] 38 VFs
[12:30:29] [PASSED] 39 VFs
[12:30:29] [PASSED] 40 VFs
[12:30:29] [PASSED] 41 VFs
[12:30:29] [PASSED] 42 VFs
[12:30:29] [PASSED] 43 VFs
[12:30:29] [PASSED] 44 VFs
[12:30:29] [PASSED] 45 VFs
[12:30:29] [PASSED] 46 VFs
[12:30:29] [PASSED] 47 VFs
[12:30:29] [PASSED] 48 VFs
[12:30:29] [PASSED] 49 VFs
[12:30:29] [PASSED] 50 VFs
[12:30:29] [PASSED] 51 VFs
[12:30:29] [PASSED] 52 VFs
[12:30:29] [PASSED] 53 VFs
[12:30:29] [PASSED] 54 VFs
[12:30:29] [PASSED] 55 VFs
[12:30:29] [PASSED] 56 VFs
[12:30:29] [PASSED] 57 VFs
[12:30:29] [PASSED] 58 VFs
[12:30:29] [PASSED] 59 VFs
[12:30:29] [PASSED] 60 VFs
[12:30:29] [PASSED] 61 VFs
[12:30:29] [PASSED] 62 VFs
[12:30:29] [PASSED] 63 VFs
[12:30:29] ================= [PASSED] fair_doorbells ==================
[12:30:29] ======================== fair_ggtt  ========================
[12:30:29] [PASSED] 1 VF
[12:30:29] [PASSED] 2 VFs
[12:30:29] [PASSED] 3 VFs
[12:30:29] [PASSED] 4 VFs
[12:30:29] [PASSED] 5 VFs
[12:30:29] [PASSED] 6 VFs
[12:30:29] [PASSED] 7 VFs
[12:30:29] [PASSED] 8 VFs
[12:30:29] [PASSED] 9 VFs
[12:30:29] [PASSED] 10 VFs
[12:30:29] [PASSED] 11 VFs
[12:30:29] [PASSED] 12 VFs
[12:30:29] [PASSED] 13 VFs
[12:30:29] [PASSED] 14 VFs
[12:30:29] [PASSED] 15 VFs
[12:30:29] [PASSED] 16 VFs
[12:30:29] [PASSED] 17 VFs
[12:30:29] [PASSED] 18 VFs
[12:30:29] [PASSED] 19 VFs
[12:30:29] [PASSED] 20 VFs
[12:30:29] [PASSED] 21 VFs
[12:30:29] [PASSED] 22 VFs
[12:30:29] [PASSED] 23 VFs
[12:30:29] [PASSED] 24 VFs
[12:30:29] [PASSED] 25 VFs
[12:30:29] [PASSED] 26 VFs
[12:30:29] [PASSED] 27 VFs
[12:30:29] [PASSED] 28 VFs
[12:30:29] [PASSED] 29 VFs
[12:30:29] [PASSED] 30 VFs
[12:30:29] [PASSED] 31 VFs
[12:30:29] [PASSED] 32 VFs
[12:30:29] [PASSED] 33 VFs
[12:30:29] [PASSED] 34 VFs
[12:30:29] [PASSED] 35 VFs
[12:30:29] [PASSED] 36 VFs
[12:30:29] [PASSED] 37 VFs
[12:30:29] [PASSED] 38 VFs
[12:30:29] [PASSED] 39 VFs
[12:30:29] [PASSED] 40 VFs
[12:30:29] [PASSED] 41 VFs
[12:30:29] [PASSED] 42 VFs
[12:30:29] [PASSED] 43 VFs
[12:30:29] [PASSED] 44 VFs
[12:30:29] [PASSED] 45 VFs
[12:30:29] [PASSED] 46 VFs
[12:30:29] [PASSED] 47 VFs
[12:30:29] [PASSED] 48 VFs
[12:30:29] [PASSED] 49 VFs
[12:30:29] [PASSED] 50 VFs
[12:30:29] [PASSED] 51 VFs
[12:30:29] [PASSED] 52 VFs
[12:30:29] [PASSED] 53 VFs
[12:30:29] [PASSED] 54 VFs
[12:30:29] [PASSED] 55 VFs
[12:30:29] [PASSED] 56 VFs
[12:30:29] [PASSED] 57 VFs
[12:30:29] [PASSED] 58 VFs
[12:30:29] [PASSED] 59 VFs
[12:30:29] [PASSED] 60 VFs
[12:30:29] [PASSED] 61 VFs
[12:30:29] [PASSED] 62 VFs
[12:30:29] [PASSED] 63 VFs
[12:30:29] ==================== [PASSED] fair_ggtt ====================
[12:30:29] ================== [PASSED] pf_gt_config ===================
[12:30:29] ===================== lmtt (1 subtest) =====================
[12:30:29] ======================== test_ops  =========================
[12:30:29] [PASSED] 2-level
[12:30:29] [PASSED] multi-level
[12:30:29] ==================== [PASSED] test_ops =====================
[12:30:29] ====================== [PASSED] lmtt =======================
[12:30:29] ================= pf_service (11 subtests) =================
[12:30:29] [PASSED] pf_negotiate_any
[12:30:29] [PASSED] pf_negotiate_base_match
[12:30:29] [PASSED] pf_negotiate_base_newer
[12:30:29] [PASSED] pf_negotiate_base_next
[12:30:29] [SKIPPED] pf_negotiate_base_older
[12:30:29] [PASSED] pf_negotiate_base_prev
[12:30:29] [PASSED] pf_negotiate_latest_match
[12:30:29] [PASSED] pf_negotiate_latest_newer
[12:30:29] [PASSED] pf_negotiate_latest_next
[12:30:29] [SKIPPED] pf_negotiate_latest_older
[12:30:29] [SKIPPED] pf_negotiate_latest_prev
[12:30:29] =================== [PASSED] pf_service ====================
[12:30:29] ================= xe_guc_g2g (2 subtests) ==================
[12:30:29] ============== xe_live_guc_g2g_kunit_default  ==============
[12:30:29] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[12:30:29] ============== xe_live_guc_g2g_kunit_allmem  ===============
[12:30:29] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[12:30:29] =================== [SKIPPED] xe_guc_g2g ===================
[12:30:29] =================== xe_mocs (2 subtests) ===================
[12:30:29] ================ xe_live_mocs_kernel_kunit  ================
[12:30:29] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[12:30:29] ================ xe_live_mocs_reset_kunit  =================
[12:30:29] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[12:30:29] ==================== [SKIPPED] xe_mocs =====================
[12:30:29] ================= xe_migrate (2 subtests) ==================
[12:30:29] ================= xe_migrate_sanity_kunit  =================
[12:30:29] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[12:30:29] ================== xe_validate_ccs_kunit  ==================
[12:30:29] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[12:30:29] =================== [SKIPPED] xe_migrate ===================
[12:30:29] ================== xe_dma_buf (1 subtest) ==================
[12:30:29] ==================== xe_dma_buf_kunit  =====================
[12:30:29] ================ [SKIPPED] xe_dma_buf_kunit ================
[12:30:29] =================== [SKIPPED] xe_dma_buf ===================
[12:30:29] ================= xe_bo_shrink (1 subtest) =================
[12:30:29] =================== xe_bo_shrink_kunit  ====================
[12:30:29] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[12:30:29] ================== [SKIPPED] xe_bo_shrink ==================
[12:30:29] ==================== xe_bo (2 subtests) ====================
[12:30:29] ================== xe_ccs_migrate_kunit  ===================
[12:30:29] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[12:30:29] ==================== xe_bo_evict_kunit  ====================
[12:30:29] =============== [SKIPPED] xe_bo_evict_kunit ================
[12:30:29] ===================== [SKIPPED] xe_bo ======================
[12:30:29] ==================== args (11 subtests) ====================
[12:30:29] [PASSED] count_args_test
[12:30:29] [PASSED] call_args_example
[12:30:29] [PASSED] call_args_test
[12:30:29] [PASSED] drop_first_arg_example
[12:30:29] [PASSED] drop_first_arg_test
[12:30:29] [PASSED] first_arg_example
[12:30:29] [PASSED] first_arg_test
[12:30:29] [PASSED] last_arg_example
[12:30:29] [PASSED] last_arg_test
[12:30:29] [PASSED] pick_arg_example
[12:30:29] [PASSED] sep_comma_example
[12:30:29] ====================== [PASSED] args =======================
[12:30:29] =================== xe_pci (3 subtests) ====================
[12:30:29] ==================== check_graphics_ip  ====================
[12:30:29] [PASSED] 12.00 Xe_LP
[12:30:29] [PASSED] 12.10 Xe_LP+
[12:30:29] [PASSED] 12.55 Xe_HPG
[12:30:29] [PASSED] 12.60 Xe_HPC
[12:30:29] [PASSED] 12.70 Xe_LPG
[12:30:29] [PASSED] 12.71 Xe_LPG
[12:30:29] [PASSED] 12.74 Xe_LPG+
[12:30:29] [PASSED] 20.01 Xe2_HPG
[12:30:29] [PASSED] 20.02 Xe2_HPG
[12:30:29] [PASSED] 20.04 Xe2_LPG
[12:30:29] [PASSED] 30.00 Xe3_LPG
[12:30:29] [PASSED] 30.01 Xe3_LPG
[12:30:29] [PASSED] 30.03 Xe3_LPG
[12:30:29] [PASSED] 30.04 Xe3_LPG
[12:30:29] [PASSED] 30.05 Xe3_LPG
[12:30:29] [PASSED] 35.11 Xe3p_XPC
[12:30:29] ================ [PASSED] check_graphics_ip ================
[12:30:29] ===================== check_media_ip  ======================
[12:30:29] [PASSED] 12.00 Xe_M
[12:30:29] [PASSED] 12.55 Xe_HPM
[12:30:29] [PASSED] 13.00 Xe_LPM+
[12:30:29] [PASSED] 13.01 Xe2_HPM
[12:30:29] [PASSED] 20.00 Xe2_LPM
[12:30:29] [PASSED] 30.00 Xe3_LPM
[12:30:29] [PASSED] 30.02 Xe3_LPM
[12:30:29] [PASSED] 35.00 Xe3p_LPM
[12:30:29] [PASSED] 35.03 Xe3p_HPM
[12:30:29] ================= [PASSED] check_media_ip ==================
[12:30:29] =================== check_platform_desc  ===================
[12:30:29] [PASSED] 0x9A60 (TIGERLAKE)
[12:30:29] [PASSED] 0x9A68 (TIGERLAKE)
[12:30:29] [PASSED] 0x9A70 (TIGERLAKE)
[12:30:29] [PASSED] 0x9A40 (TIGERLAKE)
[12:30:29] [PASSED] 0x9A49 (TIGERLAKE)
[12:30:29] [PASSED] 0x9A59 (TIGERLAKE)
[12:30:29] [PASSED] 0x9A78 (TIGERLAKE)
[12:30:29] [PASSED] 0x9AC0 (TIGERLAKE)
[12:30:29] [PASSED] 0x9AC9 (TIGERLAKE)
[12:30:29] [PASSED] 0x9AD9 (TIGERLAKE)
[12:30:29] [PASSED] 0x9AF8 (TIGERLAKE)
[12:30:29] [PASSED] 0x4C80 (ROCKETLAKE)
[12:30:29] [PASSED] 0x4C8A (ROCKETLAKE)
[12:30:29] [PASSED] 0x4C8B (ROCKETLAKE)
[12:30:29] [PASSED] 0x4C8C (ROCKETLAKE)
[12:30:29] [PASSED] 0x4C90 (ROCKETLAKE)
[12:30:29] [PASSED] 0x4C9A (ROCKETLAKE)
[12:30:29] [PASSED] 0x4680 (ALDERLAKE_S)
[12:30:29] [PASSED] 0x4682 (ALDERLAKE_S)
[12:30:29] [PASSED] 0x4688 (ALDERLAKE_S)
[12:30:29] [PASSED] 0x468A (ALDERLAKE_S)
[12:30:29] [PASSED] 0x468B (ALDERLAKE_S)
[12:30:29] [PASSED] 0x4690 (ALDERLAKE_S)
[12:30:29] [PASSED] 0x4692 (ALDERLAKE_S)
[12:30:29] [PASSED] 0x4693 (ALDERLAKE_S)
[12:30:29] [PASSED] 0x46A0 (ALDERLAKE_P)
[12:30:29] [PASSED] 0x46A1 (ALDERLAKE_P)
[12:30:29] [PASSED] 0x46A2 (ALDERLAKE_P)
[12:30:29] [PASSED] 0x46A3 (ALDERLAKE_P)
[12:30:29] [PASSED] 0x46A6 (ALDERLAKE_P)
[12:30:29] [PASSED] 0x46A8 (ALDERLAKE_P)
[12:30:29] [PASSED] 0x46AA (ALDERLAKE_P)
[12:30:29] [PASSED] 0x462A (ALDERLAKE_P)
[12:30:29] [PASSED] 0x4626 (ALDERLAKE_P)
[12:30:29] [PASSED] 0x4628 (ALDERLAKE_P)
[12:30:29] [PASSED] 0x46B0 (ALDERLAKE_P)
stty: 'standard input': Inappropriate ioctl for device
[12:30:29] [PASSED] 0x46B1 (ALDERLAKE_P)
[12:30:29] [PASSED] 0x46B2 (ALDERLAKE_P)
[12:30:29] [PASSED] 0x46B3 (ALDERLAKE_P)
[12:30:29] [PASSED] 0x46C0 (ALDERLAKE_P)
[12:30:29] [PASSED] 0x46C1 (ALDERLAKE_P)
[12:30:29] [PASSED] 0x46C2 (ALDERLAKE_P)
[12:30:29] [PASSED] 0x46C3 (ALDERLAKE_P)
[12:30:29] [PASSED] 0x46D0 (ALDERLAKE_N)
[12:30:29] [PASSED] 0x46D1 (ALDERLAKE_N)
[12:30:29] [PASSED] 0x46D2 (ALDERLAKE_N)
[12:30:29] [PASSED] 0x46D3 (ALDERLAKE_N)
[12:30:29] [PASSED] 0x46D4 (ALDERLAKE_N)
[12:30:29] [PASSED] 0xA721 (ALDERLAKE_P)
[12:30:29] [PASSED] 0xA7A1 (ALDERLAKE_P)
[12:30:29] [PASSED] 0xA7A9 (ALDERLAKE_P)
[12:30:29] [PASSED] 0xA7AC (ALDERLAKE_P)
[12:30:29] [PASSED] 0xA7AD (ALDERLAKE_P)
[12:30:29] [PASSED] 0xA720 (ALDERLAKE_P)
[12:30:29] [PASSED] 0xA7A0 (ALDERLAKE_P)
[12:30:29] [PASSED] 0xA7A8 (ALDERLAKE_P)
[12:30:29] [PASSED] 0xA7AA (ALDERLAKE_P)
[12:30:29] [PASSED] 0xA7AB (ALDERLAKE_P)
[12:30:29] [PASSED] 0xA780 (ALDERLAKE_S)
[12:30:29] [PASSED] 0xA781 (ALDERLAKE_S)
[12:30:29] [PASSED] 0xA782 (ALDERLAKE_S)
[12:30:29] [PASSED] 0xA783 (ALDERLAKE_S)
[12:30:29] [PASSED] 0xA788 (ALDERLAKE_S)
[12:30:29] [PASSED] 0xA789 (ALDERLAKE_S)
[12:30:29] [PASSED] 0xA78A (ALDERLAKE_S)
[12:30:29] [PASSED] 0xA78B (ALDERLAKE_S)
[12:30:29] [PASSED] 0x4905 (DG1)
[12:30:29] [PASSED] 0x4906 (DG1)
[12:30:29] [PASSED] 0x4907 (DG1)
[12:30:29] [PASSED] 0x4908 (DG1)
[12:30:29] [PASSED] 0x4909 (DG1)
[12:30:29] [PASSED] 0x56C0 (DG2)
[12:30:29] [PASSED] 0x56C2 (DG2)
[12:30:29] [PASSED] 0x56C1 (DG2)
[12:30:29] [PASSED] 0x7D51 (METEORLAKE)
[12:30:29] [PASSED] 0x7DD1 (METEORLAKE)
[12:30:29] [PASSED] 0x7D41 (METEORLAKE)
[12:30:29] [PASSED] 0x7D67 (METEORLAKE)
[12:30:29] [PASSED] 0xB640 (METEORLAKE)
[12:30:29] [PASSED] 0x56A0 (DG2)
[12:30:29] [PASSED] 0x56A1 (DG2)
[12:30:29] [PASSED] 0x56A2 (DG2)
[12:30:29] [PASSED] 0x56BE (DG2)
[12:30:29] [PASSED] 0x56BF (DG2)
[12:30:29] [PASSED] 0x5690 (DG2)
[12:30:29] [PASSED] 0x5691 (DG2)
[12:30:29] [PASSED] 0x5692 (DG2)
[12:30:29] [PASSED] 0x56A5 (DG2)
[12:30:29] [PASSED] 0x56A6 (DG2)
[12:30:29] [PASSED] 0x56B0 (DG2)
[12:30:29] [PASSED] 0x56B1 (DG2)
[12:30:29] [PASSED] 0x56BA (DG2)
[12:30:29] [PASSED] 0x56BB (DG2)
[12:30:29] [PASSED] 0x56BC (DG2)
[12:30:29] [PASSED] 0x56BD (DG2)
[12:30:29] [PASSED] 0x5693 (DG2)
[12:30:29] [PASSED] 0x5694 (DG2)
[12:30:29] [PASSED] 0x5695 (DG2)
[12:30:29] [PASSED] 0x56A3 (DG2)
[12:30:29] [PASSED] 0x56A4 (DG2)
[12:30:29] [PASSED] 0x56B2 (DG2)
[12:30:29] [PASSED] 0x56B3 (DG2)
[12:30:29] [PASSED] 0x5696 (DG2)
[12:30:29] [PASSED] 0x5697 (DG2)
[12:30:29] [PASSED] 0xB69 (PVC)
[12:30:29] [PASSED] 0xB6E (PVC)
[12:30:29] [PASSED] 0xBD4 (PVC)
[12:30:29] [PASSED] 0xBD5 (PVC)
[12:30:29] [PASSED] 0xBD6 (PVC)
[12:30:29] [PASSED] 0xBD7 (PVC)
[12:30:29] [PASSED] 0xBD8 (PVC)
[12:30:29] [PASSED] 0xBD9 (PVC)
[12:30:29] [PASSED] 0xBDA (PVC)
[12:30:29] [PASSED] 0xBDB (PVC)
[12:30:29] [PASSED] 0xBE0 (PVC)
[12:30:29] [PASSED] 0xBE1 (PVC)
[12:30:29] [PASSED] 0xBE5 (PVC)
[12:30:29] [PASSED] 0x7D40 (METEORLAKE)
[12:30:29] [PASSED] 0x7D45 (METEORLAKE)
[12:30:29] [PASSED] 0x7D55 (METEORLAKE)
[12:30:29] [PASSED] 0x7D60 (METEORLAKE)
[12:30:29] [PASSED] 0x7DD5 (METEORLAKE)
[12:30:29] [PASSED] 0x6420 (LUNARLAKE)
[12:30:29] [PASSED] 0x64A0 (LUNARLAKE)
[12:30:29] [PASSED] 0x64B0 (LUNARLAKE)
[12:30:29] [PASSED] 0xE202 (BATTLEMAGE)
[12:30:29] [PASSED] 0xE209 (BATTLEMAGE)
[12:30:29] [PASSED] 0xE20B (BATTLEMAGE)
[12:30:29] [PASSED] 0xE20C (BATTLEMAGE)
[12:30:29] [PASSED] 0xE20D (BATTLEMAGE)
[12:30:29] [PASSED] 0xE210 (BATTLEMAGE)
[12:30:29] [PASSED] 0xE211 (BATTLEMAGE)
[12:30:29] [PASSED] 0xE212 (BATTLEMAGE)
[12:30:29] [PASSED] 0xE216 (BATTLEMAGE)
[12:30:29] [PASSED] 0xE220 (BATTLEMAGE)
[12:30:29] [PASSED] 0xE221 (BATTLEMAGE)
[12:30:29] [PASSED] 0xE222 (BATTLEMAGE)
[12:30:29] [PASSED] 0xE223 (BATTLEMAGE)
[12:30:29] [PASSED] 0xB080 (PANTHERLAKE)
[12:30:29] [PASSED] 0xB081 (PANTHERLAKE)
[12:30:29] [PASSED] 0xB082 (PANTHERLAKE)
[12:30:29] [PASSED] 0xB083 (PANTHERLAKE)
[12:30:29] [PASSED] 0xB084 (PANTHERLAKE)
[12:30:29] [PASSED] 0xB085 (PANTHERLAKE)
[12:30:29] [PASSED] 0xB086 (PANTHERLAKE)
[12:30:29] [PASSED] 0xB087 (PANTHERLAKE)
[12:30:29] [PASSED] 0xB08F (PANTHERLAKE)
[12:30:29] [PASSED] 0xB090 (PANTHERLAKE)
[12:30:29] [PASSED] 0xB0A0 (PANTHERLAKE)
[12:30:29] [PASSED] 0xB0B0 (PANTHERLAKE)
[12:30:29] [PASSED] 0xD740 (NOVALAKE_S)
[12:30:29] [PASSED] 0xD741 (NOVALAKE_S)
[12:30:29] [PASSED] 0xD742 (NOVALAKE_S)
[12:30:29] [PASSED] 0xD743 (NOVALAKE_S)
[12:30:29] [PASSED] 0xD744 (NOVALAKE_S)
[12:30:29] [PASSED] 0xD745 (NOVALAKE_S)
[12:30:29] [PASSED] 0x674C (CRESCENTISLAND)
[12:30:29] [PASSED] 0xFD80 (PANTHERLAKE)
[12:30:29] [PASSED] 0xFD81 (PANTHERLAKE)
[12:30:29] =============== [PASSED] check_platform_desc ===============
[12:30:29] ===================== [PASSED] xe_pci ======================
[12:30:29] =================== xe_rtp (2 subtests) ====================
[12:30:29] =============== xe_rtp_process_to_sr_tests  ================
[12:30:29] [PASSED] coalesce-same-reg
[12:30:29] [PASSED] no-match-no-add
[12:30:29] [PASSED] match-or
[12:30:29] [PASSED] match-or-xfail
[12:30:29] [PASSED] no-match-no-add-multiple-rules
[12:30:29] [PASSED] two-regs-two-entries
[12:30:29] [PASSED] clr-one-set-other
[12:30:29] [PASSED] set-field
[12:30:29] [PASSED] conflict-duplicate
[12:30:29] [PASSED] conflict-not-disjoint
[12:30:29] [PASSED] conflict-reg-type
[12:30:29] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[12:30:29] ================== xe_rtp_process_tests  ===================
[12:30:29] [PASSED] active1
[12:30:29] [PASSED] active2
[12:30:29] [PASSED] active-inactive
[12:30:29] [PASSED] inactive-active
[12:30:29] [PASSED] inactive-1st_or_active-inactive
[12:30:29] [PASSED] inactive-2nd_or_active-inactive
[12:30:29] [PASSED] inactive-last_or_active-inactive
[12:30:29] [PASSED] inactive-no_or_active-inactive
[12:30:29] ============== [PASSED] xe_rtp_process_tests ===============
[12:30:29] ===================== [PASSED] xe_rtp ======================
[12:30:29] ==================== xe_wa (1 subtest) =====================
[12:30:29] ======================== xe_wa_gt  =========================
[12:30:29] [PASSED] TIGERLAKE B0
[12:30:29] [PASSED] DG1 A0
[12:30:29] [PASSED] DG1 B0
[12:30:29] [PASSED] ALDERLAKE_S A0
[12:30:29] [PASSED] ALDERLAKE_S B0
[12:30:29] [PASSED] ALDERLAKE_S C0
[12:30:29] [PASSED] ALDERLAKE_S D0
[12:30:29] [PASSED] ALDERLAKE_P A0
[12:30:29] [PASSED] ALDERLAKE_P B0
[12:30:29] [PASSED] ALDERLAKE_P C0
[12:30:29] [PASSED] ALDERLAKE_S RPLS D0
[12:30:29] [PASSED] ALDERLAKE_P RPLU E0
[12:30:29] [PASSED] DG2 G10 C0
[12:30:29] [PASSED] DG2 G11 B1
[12:30:29] [PASSED] DG2 G12 A1
[12:30:29] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[12:30:29] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[12:30:29] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[12:30:29] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[12:30:29] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[12:30:29] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[12:30:29] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[12:30:29] ==================== [PASSED] xe_wa_gt =====================
[12:30:29] ====================== [PASSED] xe_wa ======================
[12:30:29] ============================================================
[12:30:29] Testing complete. Ran 510 tests: passed: 492, skipped: 18
[12:30:29] Elapsed time: 35.204s total, 4.193s configuring, 30.545s building, 0.458s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[12:30:29] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[12:30:31] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[12:30:56] Starting KUnit Kernel (1/1)...
[12:30:56] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[12:30:56] ============ drm_test_pick_cmdline (2 subtests) ============
[12:30:56] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[12:30:56] =============== drm_test_pick_cmdline_named  ===============
[12:30:56] [PASSED] NTSC
[12:30:56] [PASSED] NTSC-J
[12:30:56] [PASSED] PAL
[12:30:56] [PASSED] PAL-M
[12:30:56] =========== [PASSED] drm_test_pick_cmdline_named ===========
[12:30:56] ============== [PASSED] drm_test_pick_cmdline ==============
[12:30:56] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[12:30:56] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[12:30:56] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[12:30:56] =========== drm_validate_clone_mode (2 subtests) ===========
[12:30:56] ============== drm_test_check_in_clone_mode  ===============
[12:30:56] [PASSED] in_clone_mode
[12:30:56] [PASSED] not_in_clone_mode
[12:30:56] ========== [PASSED] drm_test_check_in_clone_mode ===========
[12:30:56] =============== drm_test_check_valid_clones  ===============
[12:30:56] [PASSED] not_in_clone_mode
[12:30:56] [PASSED] valid_clone
[12:30:56] [PASSED] invalid_clone
[12:30:56] =========== [PASSED] drm_test_check_valid_clones ===========
[12:30:56] ============= [PASSED] drm_validate_clone_mode =============
[12:30:56] ============= drm_validate_modeset (1 subtest) =============
[12:30:56] [PASSED] drm_test_check_connector_changed_modeset
[12:30:56] ============== [PASSED] drm_validate_modeset ===============
[12:30:56] ====== drm_test_bridge_get_current_state (2 subtests) ======
[12:30:56] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[12:30:56] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[12:30:56] ======== [PASSED] drm_test_bridge_get_current_state ========
[12:30:56] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[12:30:56] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[12:30:56] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[12:30:56] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[12:30:56] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[12:30:56] ============== drm_bridge_alloc (2 subtests) ===============
[12:30:56] [PASSED] drm_test_drm_bridge_alloc_basic
[12:30:56] [PASSED] drm_test_drm_bridge_alloc_get_put
[12:30:56] ================ [PASSED] drm_bridge_alloc =================
[12:30:56] ================== drm_buddy (8 subtests) ==================
[12:30:56] [PASSED] drm_test_buddy_alloc_limit
[12:30:56] [PASSED] drm_test_buddy_alloc_optimistic
[12:30:56] [PASSED] drm_test_buddy_alloc_pessimistic
[12:30:56] [PASSED] drm_test_buddy_alloc_pathological
[12:30:56] [PASSED] drm_test_buddy_alloc_contiguous
[12:30:56] [PASSED] drm_test_buddy_alloc_clear
[12:30:56] [PASSED] drm_test_buddy_alloc_range_bias
[12:30:56] [PASSED] drm_test_buddy_fragmentation_performance
[12:30:56] ==================== [PASSED] drm_buddy ====================
[12:30:56] ============= drm_cmdline_parser (40 subtests) =============
[12:30:56] [PASSED] drm_test_cmdline_force_d_only
[12:30:56] [PASSED] drm_test_cmdline_force_D_only_dvi
[12:30:56] [PASSED] drm_test_cmdline_force_D_only_hdmi
[12:30:56] [PASSED] drm_test_cmdline_force_D_only_not_digital
[12:30:56] [PASSED] drm_test_cmdline_force_e_only
[12:30:56] [PASSED] drm_test_cmdline_res
[12:30:56] [PASSED] drm_test_cmdline_res_vesa
[12:30:56] [PASSED] drm_test_cmdline_res_vesa_rblank
[12:30:56] [PASSED] drm_test_cmdline_res_rblank
[12:30:56] [PASSED] drm_test_cmdline_res_bpp
[12:30:56] [PASSED] drm_test_cmdline_res_refresh
[12:30:56] [PASSED] drm_test_cmdline_res_bpp_refresh
[12:30:56] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[12:30:56] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[12:30:56] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[12:30:56] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[12:30:56] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[12:30:56] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[12:30:56] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[12:30:56] [PASSED] drm_test_cmdline_res_margins_force_on
[12:30:56] [PASSED] drm_test_cmdline_res_vesa_margins
[12:30:56] [PASSED] drm_test_cmdline_name
[12:30:56] [PASSED] drm_test_cmdline_name_bpp
[12:30:56] [PASSED] drm_test_cmdline_name_option
[12:30:56] [PASSED] drm_test_cmdline_name_bpp_option
[12:30:56] [PASSED] drm_test_cmdline_rotate_0
[12:30:56] [PASSED] drm_test_cmdline_rotate_90
[12:30:56] [PASSED] drm_test_cmdline_rotate_180
[12:30:56] [PASSED] drm_test_cmdline_rotate_270
[12:30:56] [PASSED] drm_test_cmdline_hmirror
[12:30:56] [PASSED] drm_test_cmdline_vmirror
[12:30:56] [PASSED] drm_test_cmdline_margin_options
[12:30:56] [PASSED] drm_test_cmdline_multiple_options
[12:30:56] [PASSED] drm_test_cmdline_bpp_extra_and_option
[12:30:56] [PASSED] drm_test_cmdline_extra_and_option
[12:30:56] [PASSED] drm_test_cmdline_freestanding_options
[12:30:56] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[12:30:56] [PASSED] drm_test_cmdline_panel_orientation
[12:30:56] ================ drm_test_cmdline_invalid  =================
[12:30:56] [PASSED] margin_only
[12:30:56] [PASSED] interlace_only
[12:30:56] [PASSED] res_missing_x
[12:30:56] [PASSED] res_missing_y
[12:30:56] [PASSED] res_bad_y
[12:30:56] [PASSED] res_missing_y_bpp
[12:30:56] [PASSED] res_bad_bpp
[12:30:56] [PASSED] res_bad_refresh
[12:30:56] [PASSED] res_bpp_refresh_force_on_off
[12:30:56] [PASSED] res_invalid_mode
[12:30:56] [PASSED] res_bpp_wrong_place_mode
[12:30:56] [PASSED] name_bpp_refresh
[12:30:56] [PASSED] name_refresh
[12:30:56] [PASSED] name_refresh_wrong_mode
[12:30:56] [PASSED] name_refresh_invalid_mode
[12:30:56] [PASSED] rotate_multiple
[12:30:56] [PASSED] rotate_invalid_val
[12:30:56] [PASSED] rotate_truncated
[12:30:56] [PASSED] invalid_option
[12:30:56] [PASSED] invalid_tv_option
[12:30:56] [PASSED] truncated_tv_option
[12:30:56] ============ [PASSED] drm_test_cmdline_invalid =============
[12:30:56] =============== drm_test_cmdline_tv_options  ===============
[12:30:56] [PASSED] NTSC
[12:30:56] [PASSED] NTSC_443
[12:30:56] [PASSED] NTSC_J
[12:30:56] [PASSED] PAL
[12:30:56] [PASSED] PAL_M
[12:30:56] [PASSED] PAL_N
[12:30:56] [PASSED] SECAM
[12:30:56] [PASSED] MONO_525
[12:30:56] [PASSED] MONO_625
[12:30:56] =========== [PASSED] drm_test_cmdline_tv_options ===========
[12:30:56] =============== [PASSED] drm_cmdline_parser ================
[12:30:56] ========== drmm_connector_hdmi_init (20 subtests) ==========
[12:30:56] [PASSED] drm_test_connector_hdmi_init_valid
[12:30:56] [PASSED] drm_test_connector_hdmi_init_bpc_8
[12:30:56] [PASSED] drm_test_connector_hdmi_init_bpc_10
[12:30:56] [PASSED] drm_test_connector_hdmi_init_bpc_12
[12:30:56] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[12:30:56] [PASSED] drm_test_connector_hdmi_init_bpc_null
[12:30:56] [PASSED] drm_test_connector_hdmi_init_formats_empty
[12:30:56] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[12:30:56] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[12:30:56] [PASSED] supported_formats=0x9 yuv420_allowed=1
[12:30:56] [PASSED] supported_formats=0x9 yuv420_allowed=0
[12:30:56] [PASSED] supported_formats=0x3 yuv420_allowed=1
[12:30:56] [PASSED] supported_formats=0x3 yuv420_allowed=0
[12:30:56] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[12:30:56] [PASSED] drm_test_connector_hdmi_init_null_ddc
[12:30:56] [PASSED] drm_test_connector_hdmi_init_null_product
[12:30:56] [PASSED] drm_test_connector_hdmi_init_null_vendor
[12:30:56] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[12:30:56] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[12:30:56] [PASSED] drm_test_connector_hdmi_init_product_valid
[12:30:56] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[12:30:56] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[12:30:56] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[12:30:56] ========= drm_test_connector_hdmi_init_type_valid  =========
[12:30:56] [PASSED] HDMI-A
[12:30:56] [PASSED] HDMI-B
[12:30:56] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[12:30:56] ======== drm_test_connector_hdmi_init_type_invalid  ========
[12:30:56] [PASSED] Unknown
[12:30:56] [PASSED] VGA
[12:30:56] [PASSED] DVI-I
[12:30:56] [PASSED] DVI-D
[12:30:56] [PASSED] DVI-A
[12:30:56] [PASSED] Composite
[12:30:56] [PASSED] SVIDEO
[12:30:56] [PASSED] LVDS
[12:30:56] [PASSED] Component
[12:30:56] [PASSED] DIN
[12:30:56] [PASSED] DP
[12:30:56] [PASSED] TV
[12:30:56] [PASSED] eDP
[12:30:56] [PASSED] Virtual
[12:30:56] [PASSED] DSI
[12:30:56] [PASSED] DPI
[12:30:56] [PASSED] Writeback
[12:30:56] [PASSED] SPI
[12:30:56] [PASSED] USB
[12:30:56] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[12:30:56] ============ [PASSED] drmm_connector_hdmi_init =============
[12:30:56] ============= drmm_connector_init (3 subtests) =============
[12:30:56] [PASSED] drm_test_drmm_connector_init
[12:30:56] [PASSED] drm_test_drmm_connector_init_null_ddc
[12:30:56] ========= drm_test_drmm_connector_init_type_valid  =========
[12:30:56] [PASSED] Unknown
[12:30:56] [PASSED] VGA
[12:30:56] [PASSED] DVI-I
[12:30:56] [PASSED] DVI-D
[12:30:56] [PASSED] DVI-A
[12:30:56] [PASSED] Composite
[12:30:56] [PASSED] SVIDEO
[12:30:56] [PASSED] LVDS
[12:30:56] [PASSED] Component
[12:30:56] [PASSED] DIN
[12:30:56] [PASSED] DP
[12:30:56] [PASSED] HDMI-A
[12:30:56] [PASSED] HDMI-B
[12:30:56] [PASSED] TV
[12:30:56] [PASSED] eDP
[12:30:56] [PASSED] Virtual
[12:30:56] [PASSED] DSI
[12:30:56] [PASSED] DPI
[12:30:56] [PASSED] Writeback
[12:30:56] [PASSED] SPI
[12:30:56] [PASSED] USB
[12:30:56] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[12:30:56] =============== [PASSED] drmm_connector_init ===============
[12:30:56] ========= drm_connector_dynamic_init (6 subtests) ==========
[12:30:56] [PASSED] drm_test_drm_connector_dynamic_init
[12:30:56] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[12:30:56] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[12:30:56] [PASSED] drm_test_drm_connector_dynamic_init_properties
[12:30:56] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[12:30:56] [PASSED] Unknown
[12:30:56] [PASSED] VGA
[12:30:56] [PASSED] DVI-I
[12:30:56] [PASSED] DVI-D
[12:30:56] [PASSED] DVI-A
[12:30:56] [PASSED] Composite
[12:30:56] [PASSED] SVIDEO
[12:30:56] [PASSED] LVDS
[12:30:56] [PASSED] Component
[12:30:56] [PASSED] DIN
[12:30:56] [PASSED] DP
[12:30:56] [PASSED] HDMI-A
[12:30:56] [PASSED] HDMI-B
[12:30:56] [PASSED] TV
[12:30:56] [PASSED] eDP
[12:30:56] [PASSED] Virtual
[12:30:56] [PASSED] DSI
[12:30:56] [PASSED] DPI
[12:30:56] [PASSED] Writeback
[12:30:56] [PASSED] SPI
[12:30:56] [PASSED] USB
[12:30:56] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[12:30:56] ======== drm_test_drm_connector_dynamic_init_name  =========
[12:30:56] [PASSED] Unknown
[12:30:56] [PASSED] VGA
[12:30:56] [PASSED] DVI-I
[12:30:56] [PASSED] DVI-D
[12:30:56] [PASSED] DVI-A
[12:30:56] [PASSED] Composite
[12:30:56] [PASSED] SVIDEO
[12:30:56] [PASSED] LVDS
[12:30:56] [PASSED] Component
[12:30:56] [PASSED] DIN
[12:30:56] [PASSED] DP
[12:30:56] [PASSED] HDMI-A
[12:30:56] [PASSED] HDMI-B
[12:30:56] [PASSED] TV
[12:30:56] [PASSED] eDP
[12:30:56] [PASSED] Virtual
[12:30:56] [PASSED] DSI
[12:30:56] [PASSED] DPI
[12:30:56] [PASSED] Writeback
[12:30:56] [PASSED] SPI
[12:30:56] [PASSED] USB
[12:30:56] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[12:30:56] =========== [PASSED] drm_connector_dynamic_init ============
[12:30:56] ==== drm_connector_dynamic_register_early (4 subtests) =====
[12:30:56] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[12:30:56] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[12:30:56] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[12:30:56] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[12:30:56] ====== [PASSED] drm_connector_dynamic_register_early =======
[12:30:56] ======= drm_connector_dynamic_register (7 subtests) ========
[12:30:56] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[12:30:56] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[12:30:56] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[12:30:56] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[12:30:56] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[12:30:56] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[12:30:56] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[12:30:56] ========= [PASSED] drm_connector_dynamic_register ==========
[12:30:56] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[12:30:56] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[12:30:56] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[12:30:56] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[12:30:56] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[12:30:56] ========== drm_test_get_tv_mode_from_name_valid  ===========
[12:30:56] [PASSED] NTSC
[12:30:56] [PASSED] NTSC-443
[12:30:56] [PASSED] NTSC-J
[12:30:56] [PASSED] PAL
[12:30:56] [PASSED] PAL-M
[12:30:56] [PASSED] PAL-N
[12:30:56] [PASSED] SECAM
[12:30:56] [PASSED] Mono
[12:30:56] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[12:30:56] [PASSED] drm_test_get_tv_mode_from_name_truncated
[12:30:56] ============ [PASSED] drm_get_tv_mode_from_name ============
[12:30:56] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[12:30:56] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[12:30:56] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[12:30:56] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[12:30:56] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[12:30:56] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[12:30:56] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[12:30:56] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[12:30:56] [PASSED] VIC 96
[12:30:56] [PASSED] VIC 97
[12:30:56] [PASSED] VIC 101
[12:30:56] [PASSED] VIC 102
[12:30:56] [PASSED] VIC 106
[12:30:56] [PASSED] VIC 107
[12:30:56] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[12:30:56] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[12:30:56] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[12:30:56] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[12:30:56] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[12:30:56] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[12:30:56] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[12:30:56] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[12:30:56] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[12:30:56] [PASSED] Automatic
[12:30:56] [PASSED] Full
[12:30:56] [PASSED] Limited 16:235
[12:30:56] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[12:30:56] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[12:30:56] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[12:30:56] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[12:30:56] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[12:30:56] [PASSED] RGB
[12:30:56] [PASSED] YUV 4:2:0
[12:30:56] [PASSED] YUV 4:2:2
[12:30:56] [PASSED] YUV 4:4:4
[12:30:56] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[12:30:56] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[12:30:56] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[12:30:56] ============= drm_damage_helper (21 subtests) ==============
[12:30:56] [PASSED] drm_test_damage_iter_no_damage
[12:30:56] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[12:30:56] [PASSED] drm_test_damage_iter_no_damage_src_moved
[12:30:56] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[12:30:56] [PASSED] drm_test_damage_iter_no_damage_not_visible
[12:30:56] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[12:30:56] [PASSED] drm_test_damage_iter_no_damage_no_fb
[12:30:56] [PASSED] drm_test_damage_iter_simple_damage
[12:30:56] [PASSED] drm_test_damage_iter_single_damage
[12:30:56] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[12:30:56] [PASSED] drm_test_damage_iter_single_damage_outside_src
[12:30:56] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[12:30:56] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[12:30:56] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[12:30:56] [PASSED] drm_test_damage_iter_single_damage_src_moved
[12:30:56] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[12:30:56] [PASSED] drm_test_damage_iter_damage
[12:30:56] [PASSED] drm_test_damage_iter_damage_one_intersect
[12:30:56] [PASSED] drm_test_damage_iter_damage_one_outside
[12:30:56] [PASSED] drm_test_damage_iter_damage_src_moved
[12:30:56] [PASSED] drm_test_damage_iter_damage_not_visible
[12:30:56] ================ [PASSED] drm_damage_helper ================
[12:30:56] ============== drm_dp_mst_helper (3 subtests) ==============
[12:30:56] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[12:30:56] [PASSED] Clock 154000 BPP 30 DSC disabled
[12:30:56] [PASSED] Clock 234000 BPP 30 DSC disabled
[12:30:56] [PASSED] Clock 297000 BPP 24 DSC disabled
[12:30:56] [PASSED] Clock 332880 BPP 24 DSC enabled
[12:30:56] [PASSED] Clock 324540 BPP 24 DSC enabled
[12:30:56] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[12:30:56] ============== drm_test_dp_mst_calc_pbn_div  ===============
[12:30:56] [PASSED] Link rate 2000000 lane count 4
[12:30:56] [PASSED] Link rate 2000000 lane count 2
[12:30:56] [PASSED] Link rate 2000000 lane count 1
[12:30:56] [PASSED] Link rate 1350000 lane count 4
[12:30:56] [PASSED] Link rate 1350000 lane count 2
[12:30:56] [PASSED] Link rate 1350000 lane count 1
[12:30:56] [PASSED] Link rate 1000000 lane count 4
[12:30:56] [PASSED] Link rate 1000000 lane count 2
[12:30:56] [PASSED] Link rate 1000000 lane count 1
[12:30:56] [PASSED] Link rate 810000 lane count 4
[12:30:56] [PASSED] Link rate 810000 lane count 2
[12:30:56] [PASSED] Link rate 810000 lane count 1
[12:30:56] [PASSED] Link rate 540000 lane count 4
[12:30:56] [PASSED] Link rate 540000 lane count 2
[12:30:56] [PASSED] Link rate 540000 lane count 1
[12:30:56] [PASSED] Link rate 270000 lane count 4
[12:30:56] [PASSED] Link rate 270000 lane count 2
[12:30:56] [PASSED] Link rate 270000 lane count 1
[12:30:56] [PASSED] Link rate 162000 lane count 4
[12:30:56] [PASSED] Link rate 162000 lane count 2
[12:30:56] [PASSED] Link rate 162000 lane count 1
[12:30:56] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[12:30:56] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[12:30:56] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[12:30:56] [PASSED] DP_POWER_UP_PHY with port number
[12:30:56] [PASSED] DP_POWER_DOWN_PHY with port number
[12:30:56] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[12:30:56] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[12:30:56] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[12:30:56] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[12:30:56] [PASSED] DP_QUERY_PAYLOAD with port number
[12:30:56] [PASSED] DP_QUERY_PAYLOAD with VCPI
[12:30:56] [PASSED] DP_REMOTE_DPCD_READ with port number
[12:30:56] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[12:30:56] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[12:30:56] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[12:30:56] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[12:30:56] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[12:30:56] [PASSED] DP_REMOTE_I2C_READ with port number
[12:30:56] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[12:30:56] [PASSED] DP_REMOTE_I2C_READ with transactions array
[12:30:56] [PASSED] DP_REMOTE_I2C_WRITE with port number
[12:30:56] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[12:30:56] [PASSED] DP_REMOTE_I2C_WRITE with data array
[12:30:56] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[12:30:56] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[12:30:56] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[12:30:56] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[12:30:56] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[12:30:56] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[12:30:56] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[12:30:56] ================ [PASSED] drm_dp_mst_helper ================
[12:30:56] ================== drm_exec (7 subtests) ===================
[12:30:56] [PASSED] sanitycheck
[12:30:56] [PASSED] test_lock
[12:30:56] [PASSED] test_lock_unlock
[12:30:56] [PASSED] test_duplicates
[12:30:56] [PASSED] test_prepare
[12:30:56] [PASSED] test_prepare_array
[12:30:56] [PASSED] test_multiple_loops
[12:30:56] ==================== [PASSED] drm_exec =====================
[12:30:56] =========== drm_format_helper_test (17 subtests) ===========
[12:30:56] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[12:30:56] [PASSED] single_pixel_source_buffer
[12:30:56] [PASSED] single_pixel_clip_rectangle
[12:30:56] [PASSED] well_known_colors
[12:30:56] [PASSED] destination_pitch
[12:30:56] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[12:30:56] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[12:30:56] [PASSED] single_pixel_source_buffer
[12:30:56] [PASSED] single_pixel_clip_rectangle
[12:30:56] [PASSED] well_known_colors
[12:30:56] [PASSED] destination_pitch
[12:30:56] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[12:30:56] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[12:30:56] [PASSED] single_pixel_source_buffer
[12:30:56] [PASSED] single_pixel_clip_rectangle
[12:30:56] [PASSED] well_known_colors
[12:30:56] [PASSED] destination_pitch
[12:30:56] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[12:30:56] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[12:30:56] [PASSED] single_pixel_source_buffer
[12:30:56] [PASSED] single_pixel_clip_rectangle
[12:30:56] [PASSED] well_known_colors
[12:30:56] [PASSED] destination_pitch
[12:30:56] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[12:30:56] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[12:30:56] [PASSED] single_pixel_source_buffer
[12:30:56] [PASSED] single_pixel_clip_rectangle
[12:30:56] [PASSED] well_known_colors
[12:30:56] [PASSED] destination_pitch
[12:30:56] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[12:30:56] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[12:30:56] [PASSED] single_pixel_source_buffer
[12:30:56] [PASSED] single_pixel_clip_rectangle
[12:30:56] [PASSED] well_known_colors
[12:30:56] [PASSED] destination_pitch
[12:30:56] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[12:30:56] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[12:30:56] [PASSED] single_pixel_source_buffer
[12:30:56] [PASSED] single_pixel_clip_rectangle
[12:30:56] [PASSED] well_known_colors
[12:30:56] [PASSED] destination_pitch
[12:30:56] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[12:30:56] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[12:30:56] [PASSED] single_pixel_source_buffer
[12:30:56] [PASSED] single_pixel_clip_rectangle
[12:30:56] [PASSED] well_known_colors
[12:30:56] [PASSED] destination_pitch
[12:30:56] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[12:30:56] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[12:30:56] [PASSED] single_pixel_source_buffer
[12:30:56] [PASSED] single_pixel_clip_rectangle
[12:30:56] [PASSED] well_known_colors
[12:30:56] [PASSED] destination_pitch
[12:30:56] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[12:30:56] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[12:30:56] [PASSED] single_pixel_source_buffer
[12:30:56] [PASSED] single_pixel_clip_rectangle
[12:30:56] [PASSED] well_known_colors
[12:30:56] [PASSED] destination_pitch
[12:30:56] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[12:30:56] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[12:30:56] [PASSED] single_pixel_source_buffer
[12:30:56] [PASSED] single_pixel_clip_rectangle
[12:30:56] [PASSED] well_known_colors
[12:30:56] [PASSED] destination_pitch
[12:30:56] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[12:30:56] ============== drm_test_fb_xrgb8888_to_mono  ===============
[12:30:56] [PASSED] single_pixel_source_buffer
[12:30:56] [PASSED] single_pixel_clip_rectangle
[12:30:56] [PASSED] well_known_colors
[12:30:56] [PASSED] destination_pitch
[12:30:56] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[12:30:56] ==================== drm_test_fb_swab  =====================
[12:30:56] [PASSED] single_pixel_source_buffer
[12:30:56] [PASSED] single_pixel_clip_rectangle
[12:30:56] [PASSED] well_known_colors
[12:30:56] [PASSED] destination_pitch
[12:30:56] ================ [PASSED] drm_test_fb_swab =================
[12:30:56] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[12:30:56] [PASSED] single_pixel_source_buffer
[12:30:56] [PASSED] single_pixel_clip_rectangle
[12:30:56] [PASSED] well_known_colors
[12:30:56] [PASSED] destination_pitch
[12:30:56] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[12:30:56] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[12:30:56] [PASSED] single_pixel_source_buffer
[12:30:56] [PASSED] single_pixel_clip_rectangle
[12:30:56] [PASSED] well_known_colors
[12:30:56] [PASSED] destination_pitch
[12:30:56] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[12:30:56] ================= drm_test_fb_clip_offset  =================
[12:30:56] [PASSED] pass through
[12:30:56] [PASSED] horizontal offset
[12:30:56] [PASSED] vertical offset
[12:30:56] [PASSED] horizontal and vertical offset
[12:30:56] [PASSED] horizontal offset (custom pitch)
[12:30:56] [PASSED] vertical offset (custom pitch)
[12:30:56] [PASSED] horizontal and vertical offset (custom pitch)
[12:30:56] ============= [PASSED] drm_test_fb_clip_offset =============
[12:30:56] =================== drm_test_fb_memcpy  ====================
[12:30:56] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[12:30:56] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[12:30:56] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[12:30:56] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[12:30:56] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[12:30:56] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[12:30:56] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[12:30:56] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[12:30:56] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[12:30:56] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[12:30:56] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[12:30:56] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[12:30:56] =============== [PASSED] drm_test_fb_memcpy ================
[12:30:56] ============= [PASSED] drm_format_helper_test ==============
[12:30:56] ================= drm_format (18 subtests) =================
[12:30:56] [PASSED] drm_test_format_block_width_invalid
[12:30:56] [PASSED] drm_test_format_block_width_one_plane
[12:30:56] [PASSED] drm_test_format_block_width_two_plane
[12:30:56] [PASSED] drm_test_format_block_width_three_plane
[12:30:56] [PASSED] drm_test_format_block_width_tiled
[12:30:56] [PASSED] drm_test_format_block_height_invalid
[12:30:56] [PASSED] drm_test_format_block_height_one_plane
[12:30:56] [PASSED] drm_test_format_block_height_two_plane
[12:30:56] [PASSED] drm_test_format_block_height_three_plane
[12:30:56] [PASSED] drm_test_format_block_height_tiled
[12:30:56] [PASSED] drm_test_format_min_pitch_invalid
[12:30:56] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[12:30:56] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[12:30:56] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[12:30:56] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[12:30:56] [PASSED] drm_test_format_min_pitch_two_plane
[12:30:56] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[12:30:56] [PASSED] drm_test_format_min_pitch_tiled
[12:30:56] =================== [PASSED] drm_format ====================
[12:30:56] ============== drm_framebuffer (10 subtests) ===============
[12:30:56] ========== drm_test_framebuffer_check_src_coords  ==========
[12:30:56] [PASSED] Success: source fits into fb
[12:30:56] [PASSED] Fail: overflowing fb with x-axis coordinate
[12:30:56] [PASSED] Fail: overflowing fb with y-axis coordinate
[12:30:56] [PASSED] Fail: overflowing fb with source width
[12:30:56] [PASSED] Fail: overflowing fb with source height
[12:30:56] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[12:30:56] [PASSED] drm_test_framebuffer_cleanup
[12:30:56] =============== drm_test_framebuffer_create  ===============
[12:30:56] [PASSED] ABGR8888 normal sizes
[12:30:56] [PASSED] ABGR8888 max sizes
[12:30:56] [PASSED] ABGR8888 pitch greater than min required
[12:30:56] [PASSED] ABGR8888 pitch less than min required
[12:30:56] [PASSED] ABGR8888 Invalid width
[12:30:56] [PASSED] ABGR8888 Invalid buffer handle
[12:30:56] [PASSED] No pixel format
[12:30:56] [PASSED] ABGR8888 Width 0
[12:30:56] [PASSED] ABGR8888 Height 0
[12:30:56] [PASSED] ABGR8888 Out of bound height * pitch combination
[12:30:56] [PASSED] ABGR8888 Large buffer offset
[12:30:56] [PASSED] ABGR8888 Buffer offset for inexistent plane
[12:30:56] [PASSED] ABGR8888 Invalid flag
[12:30:56] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[12:30:56] [PASSED] ABGR8888 Valid buffer modifier
[12:30:56] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[12:30:56] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[12:30:56] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[12:30:56] [PASSED] NV12 Normal sizes
[12:30:56] [PASSED] NV12 Max sizes
[12:30:56] [PASSED] NV12 Invalid pitch
[12:30:56] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[12:30:56] [PASSED] NV12 different  modifier per-plane
[12:30:56] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[12:30:56] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[12:30:56] [PASSED] NV12 Modifier for inexistent plane
[12:30:56] [PASSED] NV12 Handle for inexistent plane
[12:30:56] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[12:30:56] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[12:30:56] [PASSED] YVU420 Normal sizes
[12:30:56] [PASSED] YVU420 Max sizes
[12:30:56] [PASSED] YVU420 Invalid pitch
[12:30:56] [PASSED] YVU420 Different pitches
[12:30:56] [PASSED] YVU420 Different buffer offsets/pitches
[12:30:56] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[12:30:56] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[12:30:56] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[12:30:56] [PASSED] YVU420 Valid modifier
[12:30:56] [PASSED] YVU420 Different modifiers per plane
[12:30:56] [PASSED] YVU420 Modifier for inexistent plane
[12:30:56] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[12:30:56] [PASSED] X0L2 Normal sizes
[12:30:56] [PASSED] X0L2 Max sizes
[12:30:56] [PASSED] X0L2 Invalid pitch
[12:30:56] [PASSED] X0L2 Pitch greater than minimum required
[12:30:56] [PASSED] X0L2 Handle for inexistent plane
[12:30:56] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[12:30:56] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[12:30:56] [PASSED] X0L2 Valid modifier
[12:30:56] [PASSED] X0L2 Modifier for inexistent plane
[12:30:56] =========== [PASSED] drm_test_framebuffer_create ===========
[12:30:56] [PASSED] drm_test_framebuffer_free
[12:30:56] [PASSED] drm_test_framebuffer_init
[12:30:56] [PASSED] drm_test_framebuffer_init_bad_format
[12:30:56] [PASSED] drm_test_framebuffer_init_dev_mismatch
[12:30:56] [PASSED] drm_test_framebuffer_lookup
[12:30:56] [PASSED] drm_test_framebuffer_lookup_inexistent
[12:30:56] [PASSED] drm_test_framebuffer_modifiers_not_supported
[12:30:56] ================= [PASSED] drm_framebuffer =================
[12:30:56] ================ drm_gem_shmem (8 subtests) ================
[12:30:56] [PASSED] drm_gem_shmem_test_obj_create
[12:30:56] [PASSED] drm_gem_shmem_test_obj_create_private
[12:30:56] [PASSED] drm_gem_shmem_test_pin_pages
[12:30:56] [PASSED] drm_gem_shmem_test_vmap
[12:30:56] [PASSED] drm_gem_shmem_test_get_pages_sgt
[12:30:56] [PASSED] drm_gem_shmem_test_get_sg_table
[12:30:56] [PASSED] drm_gem_shmem_test_madvise
[12:30:56] [PASSED] drm_gem_shmem_test_purge
[12:30:56] ================== [PASSED] drm_gem_shmem ==================
[12:30:56] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[12:30:56] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[12:30:56] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[12:30:56] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[12:30:56] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[12:30:56] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[12:30:56] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[12:30:56] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[12:30:56] [PASSED] Automatic
[12:30:56] [PASSED] Full
[12:30:56] [PASSED] Limited 16:235
[12:30:56] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[12:30:56] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[12:30:56] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[12:30:56] [PASSED] drm_test_check_disable_connector
[12:30:56] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[12:30:56] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[12:30:56] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[12:30:56] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[12:30:56] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[12:30:56] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[12:30:56] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[12:30:56] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[12:30:56] [PASSED] drm_test_check_output_bpc_dvi
[12:30:56] [PASSED] drm_test_check_output_bpc_format_vic_1
[12:30:56] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[12:30:56] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[12:30:56] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[12:30:56] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[12:30:56] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[12:30:56] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[12:30:56] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[12:30:56] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[12:30:56] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[12:30:56] [PASSED] drm_test_check_broadcast_rgb_value
[12:30:56] [PASSED] drm_test_check_bpc_8_value
[12:30:56] [PASSED] drm_test_check_bpc_10_value
[12:30:56] [PASSED] drm_test_check_bpc_12_value
[12:30:56] [PASSED] drm_test_check_format_value
[12:30:56] [PASSED] drm_test_check_tmds_char_value
[12:30:56] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[12:30:56] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[12:30:56] [PASSED] drm_test_check_mode_valid
[12:30:56] [PASSED] drm_test_check_mode_valid_reject
[12:30:56] [PASSED] drm_test_check_mode_valid_reject_rate
[12:30:56] [PASSED] drm_test_check_mode_valid_reject_max_clock
[12:30:56] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[12:30:56] ================= drm_managed (2 subtests) =================
[12:30:56] [PASSED] drm_test_managed_release_action
[12:30:56] [PASSED] drm_test_managed_run_action
[12:30:56] =================== [PASSED] drm_managed ===================
[12:30:56] =================== drm_mm (6 subtests) ====================
[12:30:56] [PASSED] drm_test_mm_init
[12:30:56] [PASSED] drm_test_mm_debug
[12:30:56] [PASSED] drm_test_mm_align32
[12:30:56] [PASSED] drm_test_mm_align64
[12:30:56] [PASSED] drm_test_mm_lowest
[12:30:56] [PASSED] drm_test_mm_highest
[12:30:56] ===================== [PASSED] drm_mm ======================
[12:30:56] ============= drm_modes_analog_tv (5 subtests) =============
[12:30:56] [PASSED] drm_test_modes_analog_tv_mono_576i
[12:30:56] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[12:30:56] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[12:30:56] [PASSED] drm_test_modes_analog_tv_pal_576i
[12:30:56] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[12:30:56] =============== [PASSED] drm_modes_analog_tv ===============
[12:30:56] ============== drm_plane_helper (2 subtests) ===============
[12:30:56] =============== drm_test_check_plane_state  ================
[12:30:56] [PASSED] clipping_simple
[12:30:56] [PASSED] clipping_rotate_reflect
[12:30:56] [PASSED] positioning_simple
[12:30:56] [PASSED] upscaling
[12:30:56] [PASSED] downscaling
[12:30:56] [PASSED] rounding1
[12:30:56] [PASSED] rounding2
[12:30:56] [PASSED] rounding3
[12:30:56] [PASSED] rounding4
[12:30:56] =========== [PASSED] drm_test_check_plane_state ============
[12:30:56] =========== drm_test_check_invalid_plane_state  ============
[12:30:56] [PASSED] positioning_invalid
[12:30:56] [PASSED] upscaling_invalid
[12:30:56] [PASSED] downscaling_invalid
[12:30:56] ======= [PASSED] drm_test_check_invalid_plane_state ========
[12:30:56] ================ [PASSED] drm_plane_helper =================
[12:30:56] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[12:30:56] ====== drm_test_connector_helper_tv_get_modes_check  =======
[12:30:56] [PASSED] None
[12:30:56] [PASSED] PAL
[12:30:56] [PASSED] NTSC
[12:30:56] [PASSED] Both, NTSC Default
[12:30:56] [PASSED] Both, PAL Default
[12:30:56] [PASSED] Both, NTSC Default, with PAL on command-line
[12:30:56] [PASSED] Both, PAL Default, with NTSC on command-line
[12:30:56] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[12:30:56] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[12:30:56] ================== drm_rect (9 subtests) ===================
[12:30:56] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[12:30:56] [PASSED] drm_test_rect_clip_scaled_not_clipped
[12:30:56] [PASSED] drm_test_rect_clip_scaled_clipped
[12:30:56] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[12:30:56] ================= drm_test_rect_intersect  =================
[12:30:56] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[12:30:56] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[12:30:56] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[12:30:56] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[12:30:56] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[12:30:56] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[12:30:56] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[12:30:56] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[12:30:56] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[12:30:56] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[12:30:56] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[12:30:56] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[12:30:56] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[12:30:56] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[12:30:56] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[12:30:56] ============= [PASSED] drm_test_rect_intersect =============
[12:30:56] ================ drm_test_rect_calc_hscale  ================
[12:30:56] [PASSED] normal use
[12:30:56] [PASSED] out of max range
[12:30:56] [PASSED] out of min range
[12:30:56] [PASSED] zero dst
[12:30:56] [PASSED] negative src
[12:30:56] [PASSED] negative dst
[12:30:56] ============ [PASSED] drm_test_rect_calc_hscale ============
[12:30:56] ================ drm_test_rect_calc_vscale  ================
[12:30:56] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[12:30:56] [PASSED] out of max range
[12:30:56] [PASSED] out of min range
[12:30:56] [PASSED] zero dst
[12:30:56] [PASSED] negative src
[12:30:56] [PASSED] negative dst
[12:30:56] ============ [PASSED] drm_test_rect_calc_vscale ============
[12:30:56] ================== drm_test_rect_rotate  ===================
[12:30:56] [PASSED] reflect-x
[12:30:56] [PASSED] reflect-y
[12:30:56] [PASSED] rotate-0
[12:30:56] [PASSED] rotate-90
[12:30:56] [PASSED] rotate-180
[12:30:56] [PASSED] rotate-270
[12:30:56] ============== [PASSED] drm_test_rect_rotate ===============
[12:30:56] ================ drm_test_rect_rotate_inv  =================
[12:30:56] [PASSED] reflect-x
[12:30:56] [PASSED] reflect-y
[12:30:56] [PASSED] rotate-0
[12:30:56] [PASSED] rotate-90
[12:30:56] [PASSED] rotate-180
[12:30:56] [PASSED] rotate-270
[12:30:56] ============ [PASSED] drm_test_rect_rotate_inv =============
[12:30:56] ==================== [PASSED] drm_rect =====================
[12:30:56] ============ drm_sysfb_modeset_test (1 subtest) ============
[12:30:56] ============ drm_test_sysfb_build_fourcc_list  =============
[12:30:56] [PASSED] no native formats
[12:30:56] [PASSED] XRGB8888 as native format
[12:30:56] [PASSED] remove duplicates
[12:30:56] [PASSED] convert alpha formats
[12:30:56] [PASSED] random formats
[12:30:56] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[12:30:56] ============= [PASSED] drm_sysfb_modeset_test ==============
[12:30:56] ================== drm_fixp (2 subtests) ===================
[12:30:56] [PASSED] drm_test_int2fixp
[12:30:56] [PASSED] drm_test_sm2fixp
[12:30:56] ==================== [PASSED] drm_fixp =====================
[12:30:56] ============================================================
[12:30:56] Testing complete. Ran 624 tests: passed: 624
[12:30:56] Elapsed time: 27.048s total, 1.674s configuring, 24.906s building, 0.437s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[12:30:56] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[12:30:58] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[12:31:07] Starting KUnit Kernel (1/1)...
[12:31:07] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[12:31:07] ================= ttm_device (5 subtests) ==================
[12:31:07] [PASSED] ttm_device_init_basic
[12:31:07] [PASSED] ttm_device_init_multiple
[12:31:07] [PASSED] ttm_device_fini_basic
[12:31:07] [PASSED] ttm_device_init_no_vma_man
[12:31:07] ================== ttm_device_init_pools  ==================
[12:31:07] [PASSED] No DMA allocations, no DMA32 required
[12:31:07] [PASSED] DMA allocations, DMA32 required
[12:31:07] [PASSED] No DMA allocations, DMA32 required
[12:31:07] [PASSED] DMA allocations, no DMA32 required
[12:31:07] ============== [PASSED] ttm_device_init_pools ==============
[12:31:07] =================== [PASSED] ttm_device ====================
[12:31:07] ================== ttm_pool (8 subtests) ===================
[12:31:07] ================== ttm_pool_alloc_basic  ===================
[12:31:07] [PASSED] One page
[12:31:07] [PASSED] More than one page
[12:31:07] [PASSED] Above the allocation limit
[12:31:07] [PASSED] One page, with coherent DMA mappings enabled
[12:31:07] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[12:31:07] ============== [PASSED] ttm_pool_alloc_basic ===============
[12:31:07] ============== ttm_pool_alloc_basic_dma_addr  ==============
[12:31:07] [PASSED] One page
[12:31:07] [PASSED] More than one page
[12:31:07] [PASSED] Above the allocation limit
[12:31:07] [PASSED] One page, with coherent DMA mappings enabled
[12:31:07] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[12:31:07] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[12:31:07] [PASSED] ttm_pool_alloc_order_caching_match
[12:31:07] [PASSED] ttm_pool_alloc_caching_mismatch
[12:31:07] [PASSED] ttm_pool_alloc_order_mismatch
[12:31:07] [PASSED] ttm_pool_free_dma_alloc
[12:31:07] [PASSED] ttm_pool_free_no_dma_alloc
[12:31:07] [PASSED] ttm_pool_fini_basic
[12:31:07] ==================== [PASSED] ttm_pool =====================
[12:31:07] ================ ttm_resource (8 subtests) =================
[12:31:07] ================= ttm_resource_init_basic  =================
[12:31:07] [PASSED] Init resource in TTM_PL_SYSTEM
[12:31:07] [PASSED] Init resource in TTM_PL_VRAM
[12:31:07] [PASSED] Init resource in a private placement
[12:31:07] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[12:31:07] ============= [PASSED] ttm_resource_init_basic =============
[12:31:07] [PASSED] ttm_resource_init_pinned
[12:31:07] [PASSED] ttm_resource_fini_basic
[12:31:07] [PASSED] ttm_resource_manager_init_basic
[12:31:07] [PASSED] ttm_resource_manager_usage_basic
[12:31:07] [PASSED] ttm_resource_manager_set_used_basic
[12:31:07] [PASSED] ttm_sys_man_alloc_basic
[12:31:07] [PASSED] ttm_sys_man_free_basic
[12:31:07] ================== [PASSED] ttm_resource ===================
[12:31:07] =================== ttm_tt (15 subtests) ===================
[12:31:07] ==================== ttm_tt_init_basic  ====================
[12:31:07] [PASSED] Page-aligned size
[12:31:07] [PASSED] Extra pages requested
[12:31:07] ================ [PASSED] ttm_tt_init_basic ================
[12:31:07] [PASSED] ttm_tt_init_misaligned
[12:31:07] [PASSED] ttm_tt_fini_basic
[12:31:07] [PASSED] ttm_tt_fini_sg
[12:31:07] [PASSED] ttm_tt_fini_shmem
[12:31:07] [PASSED] ttm_tt_create_basic
[12:31:07] [PASSED] ttm_tt_create_invalid_bo_type
[12:31:07] [PASSED] ttm_tt_create_ttm_exists
[12:31:07] [PASSED] ttm_tt_create_failed
[12:31:07] [PASSED] ttm_tt_destroy_basic
[12:31:07] [PASSED] ttm_tt_populate_null_ttm
[12:31:07] [PASSED] ttm_tt_populate_populated_ttm
[12:31:07] [PASSED] ttm_tt_unpopulate_basic
[12:31:07] [PASSED] ttm_tt_unpopulate_empty_ttm
[12:31:07] [PASSED] ttm_tt_swapin_basic
[12:31:07] ===================== [PASSED] ttm_tt ======================
[12:31:07] =================== ttm_bo (14 subtests) ===================
[12:31:07] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[12:31:07] [PASSED] Cannot be interrupted and sleeps
[12:31:07] [PASSED] Cannot be interrupted, locks straight away
[12:31:07] [PASSED] Can be interrupted, sleeps
[12:31:07] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[12:31:07] [PASSED] ttm_bo_reserve_locked_no_sleep
[12:31:07] [PASSED] ttm_bo_reserve_no_wait_ticket
[12:31:07] [PASSED] ttm_bo_reserve_double_resv
[12:31:07] [PASSED] ttm_bo_reserve_interrupted
[12:31:07] [PASSED] ttm_bo_reserve_deadlock
[12:31:07] [PASSED] ttm_bo_unreserve_basic
[12:31:07] [PASSED] ttm_bo_unreserve_pinned
[12:31:07] [PASSED] ttm_bo_unreserve_bulk
[12:31:07] [PASSED] ttm_bo_fini_basic
[12:31:07] [PASSED] ttm_bo_fini_shared_resv
[12:31:07] [PASSED] ttm_bo_pin_basic
[12:31:07] [PASSED] ttm_bo_pin_unpin_resource
[12:31:07] [PASSED] ttm_bo_multiple_pin_one_unpin
[12:31:07] ===================== [PASSED] ttm_bo ======================
[12:31:07] ============== ttm_bo_validate (21 subtests) ===============
[12:31:07] ============== ttm_bo_init_reserved_sys_man  ===============
[12:31:07] [PASSED] Buffer object for userspace
[12:31:07] [PASSED] Kernel buffer object
[12:31:07] [PASSED] Shared buffer object
[12:31:07] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[12:31:07] ============== ttm_bo_init_reserved_mock_man  ==============
[12:31:07] [PASSED] Buffer object for userspace
[12:31:07] [PASSED] Kernel buffer object
[12:31:07] [PASSED] Shared buffer object
[12:31:07] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[12:31:07] [PASSED] ttm_bo_init_reserved_resv
[12:31:07] ================== ttm_bo_validate_basic  ==================
[12:31:07] [PASSED] Buffer object for userspace
[12:31:07] [PASSED] Kernel buffer object
[12:31:07] [PASSED] Shared buffer object
[12:31:07] ============== [PASSED] ttm_bo_validate_basic ==============
[12:31:07] [PASSED] ttm_bo_validate_invalid_placement
[12:31:07] ============= ttm_bo_validate_same_placement  ==============
[12:31:07] [PASSED] System manager
[12:31:07] [PASSED] VRAM manager
[12:31:07] ========= [PASSED] ttm_bo_validate_same_placement ==========
[12:31:07] [PASSED] ttm_bo_validate_failed_alloc
[12:31:07] [PASSED] ttm_bo_validate_pinned
[12:31:07] [PASSED] ttm_bo_validate_busy_placement
[12:31:07] ================ ttm_bo_validate_multihop  =================
[12:31:07] [PASSED] Buffer object for userspace
[12:31:07] [PASSED] Kernel buffer object
[12:31:07] [PASSED] Shared buffer object
[12:31:07] ============ [PASSED] ttm_bo_validate_multihop =============
[12:31:07] ========== ttm_bo_validate_no_placement_signaled  ==========
[12:31:07] [PASSED] Buffer object in system domain, no page vector
[12:31:07] [PASSED] Buffer object in system domain with an existing page vector
[12:31:07] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[12:31:07] ======== ttm_bo_validate_no_placement_not_signaled  ========
[12:31:07] [PASSED] Buffer object for userspace
[12:31:07] [PASSED] Kernel buffer object
[12:31:07] [PASSED] Shared buffer object
[12:31:07] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[12:31:07] [PASSED] ttm_bo_validate_move_fence_signaled
[12:31:07] ========= ttm_bo_validate_move_fence_not_signaled  =========
[12:31:07] [PASSED] Waits for GPU
[12:31:07] [PASSED] Tries to lock straight away
[12:31:07] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[12:31:07] [PASSED] ttm_bo_validate_happy_evict
[12:31:07] [PASSED] ttm_bo_validate_all_pinned_evict
[12:31:07] [PASSED] ttm_bo_validate_allowed_only_evict
[12:31:07] [PASSED] ttm_bo_validate_deleted_evict
[12:31:07] [PASSED] ttm_bo_validate_busy_domain_evict
[12:31:07] [PASSED] ttm_bo_validate_evict_gutting
[12:31:07] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[12:31:07] ================= [PASSED] ttm_bo_validate =================
[12:31:07] ============================================================
[12:31:07] Testing complete. Ran 101 tests: passed: 101
[12:31:07] Elapsed time: 11.318s total, 1.674s configuring, 9.377s building, 0.226s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✗ CI.checksparse: warning for drm/i915/display: DC3CO support

[Patchwork]

== Series Details ==

Series: drm/i915/display: DC3CO support
URL   : https://patchwork.freedesktop.org/series/158688/
State : warning

== Summary ==

+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast b47b04d41eda468db50bea8957bea3fa941a51d7
Sparse version: 0.6.4 (Ubuntu: 0.6.4-4ubuntu3)
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm/i915/display/intel_display.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_display_types.h:2101:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/intel_uncore.c:1930:1: warning: context imbalance in 'fwtable_read8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1931:1: warning: context imbalance in 'fwtable_read16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1932:1: warning: context imbalance in 'fwtable_read32' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1933:1: warning: context imbalance in 'fwtable_read64' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1998:1: warning: context imbalance in 'gen6_write8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1999:1: warning: context imbalance in 'gen6_write16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2000:1: warning: context imbalance in 'gen6_write32' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2020:1: warning: context imbalance in 'fwtable_write8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2021:1: warning: context imbalance in 'fwtable_write16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2022:1: warning: context imbalance in 'fwtable_write32' - unexpected unlock

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✗ Xe.CI.BAT: failure for drm/i915/display: DC3CO support

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 3455 bytes --]

== Series Details ==

Series: drm/i915/display: DC3CO support
URL   : https://patchwork.freedesktop.org/series/158688/
State : failure

== Summary ==

CI Bug Log - changes from xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f_BAT -> xe-pw-158688v1_BAT
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-158688v1_BAT absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-158688v1_BAT, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (12 -> 12)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-158688v1_BAT:

### IGT changes ###

#### Possible regressions ####

  * igt@xe_dma_buf_sync@export-dma-buf-once-read-write-sync:
    - bat-adlp-7:         [PASS][1] -> [DMESG-WARN][2] +53 other tests dmesg-warn
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/bat-adlp-7/igt@xe_dma_buf_sync@export-dma-buf-once-read-write-sync.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/bat-adlp-7/igt@xe_dma_buf_sync@export-dma-buf-once-read-write-sync.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@xe_debugfs@info-read}:
    - bat-adlp-7:         [PASS][3] -> [DMESG-WARN][4]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/bat-adlp-7/igt@xe_debugfs@info-read.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/bat-adlp-7/igt@xe_debugfs@info-read.html

  
Known issues
------------

  Here are the changes found in xe-pw-158688v1_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@xe_waitfence@reltime:
    - bat-dg2-oem2:       [PASS][5] -> [FAIL][6] ([Intel XE#6520])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/bat-dg2-oem2/igt@xe_waitfence@reltime.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/bat-dg2-oem2/igt@xe_waitfence@reltime.html

  
#### Possible fixes ####

  * igt@xe_waitfence@abstime:
    - bat-dg2-oem2:       [TIMEOUT][7] ([Intel XE#6506]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/bat-dg2-oem2/igt@xe_waitfence@abstime.html
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/bat-dg2-oem2/igt@xe_waitfence@abstime.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#6506]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6506
  [Intel XE#6520]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6520


Build changes
-------------

  * Linux: xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f -> xe-pw-158688v1

  IGT_8659: 8659
  xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f: 48deab361d3b570e2210875fdc8ffb29627d054f
  xe-pw-158688v1: 158688v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/index.html

[-- Attachment #2: Type: text/html, Size: 4132 bytes --]

✗ Xe.CI.Full: failure for drm/i915/display: DC3CO support

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 54596 bytes --]

== Series Details ==

Series: drm/i915/display: DC3CO support
URL   : https://patchwork.freedesktop.org/series/158688/
State : failure

== Summary ==

CI Bug Log - changes from xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f_FULL -> xe-pw-158688v1_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-158688v1_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-158688v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-158688v1_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@xe_exec_system_allocator@many-stride-new-madvise:
    - shard-bmg:          [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-3/igt@xe_exec_system_allocator@many-stride-new-madvise.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-2/igt@xe_exec_system_allocator@many-stride-new-madvise.html

  
Known issues
------------

  Here are the changes found in xe-pw-158688v1_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_hotunplug@hotrebind:
    - shard-bmg:          [PASS][3] -> [SKIP][4] ([Intel XE#6779])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-3/igt@core_hotunplug@hotrebind.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-2/igt@core_hotunplug@hotrebind.html

  * igt@device_reset@unbind-reset-rebind:
    - shard-bmg:          [PASS][5] -> [SKIP][6] ([Intel XE#6815])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-3/igt@device_reset@unbind-reset-rebind.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-2/igt@device_reset@unbind-reset-rebind.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
    - shard-adlp:         [PASS][7] -> [FAIL][8] ([Intel XE#1231])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-adlp-6/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-adlp-4/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@yf-tiled-32bpp-rotate-270:
    - shard-bmg:          NOTRUN -> [SKIP][9] ([Intel XE#1124]) +1 other test skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-3/igt@kms_big_fb@yf-tiled-32bpp-rotate-270.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc:
    - shard-bmg:          NOTRUN -> [SKIP][10] ([Intel XE#2887])
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-3/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs:
    - shard-dg2-set2:     [PASS][11] -> [INCOMPLETE][12] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4345] / [Intel XE#6168])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     [PASS][13] -> [INCOMPLETE][14] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#6168])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-6.html
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-6.html

  * igt@kms_chamelium_edid@hdmi-edid-stress-resolution-non-4k:
    - shard-bmg:          NOTRUN -> [SKIP][15] ([Intel XE#2252])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-3/igt@kms_chamelium_edid@hdmi-edid-stress-resolution-non-4k.html

  * igt@kms_colorop@plane-xr30-xr30-ctm_3x4_overdrive:
    - shard-bmg:          NOTRUN -> [SKIP][16] ([Intel XE#6704])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-6/igt@kms_colorop@plane-xr30-xr30-ctm_3x4_overdrive.html

  * igt@kms_cursor_crc@cursor-sliding-64x21:
    - shard-bmg:          NOTRUN -> [SKIP][17] ([Intel XE#2320])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-6/igt@kms_cursor_crc@cursor-sliding-64x21.html

  * igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size:
    - shard-bmg:          [PASS][18] -> [DMESG-WARN][19] ([Intel XE#5354])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-4/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-8/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html

  * igt@kms_flip@2x-flip-vs-suspend-interruptible:
    - shard-bmg:          [PASS][20] -> [INCOMPLETE][21] ([Intel XE#2049] / [Intel XE#2597]) +1 other test incomplete
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-8/igt@kms_flip@2x-flip-vs-suspend-interruptible.html
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-6/igt@kms_flip@2x-flip-vs-suspend-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
    - shard-lnl:          [PASS][22] -> [FAIL][23] ([Intel XE#301] / [Intel XE#3149])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-valid-mode:
    - shard-bmg:          NOTRUN -> [SKIP][24] ([Intel XE#2293])
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-1/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][25] ([Intel XE#2311]) +2 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-linear:
    - shard-bmg:          NOTRUN -> [SKIP][26] ([Intel XE#4141]) +3 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-tiling-linear.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-move:
    - shard-bmg:          NOTRUN -> [SKIP][27] ([Intel XE#2313])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-3/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-move.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-bmg:          [PASS][28] -> [ABORT][29] ([Intel XE#6740]) +1 other test abort
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-4/igt@kms_hdr@bpc-switch-dpms.html
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-8/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-75-upscale-factor-0-25@pipe-d:
    - shard-adlp:         [PASS][30] -> [DMESG-WARN][31] ([Intel XE#2953] / [Intel XE#4173]) +5 other tests dmesg-warn
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-adlp-9/igt@kms_plane_scaling@planes-downscale-factor-0-75-upscale-factor-0-25@pipe-d.html
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-adlp-2/igt@kms_plane_scaling@planes-downscale-factor-0-75-upscale-factor-0-25@pipe-d.html

  * igt@kms_pm_rpm@modeset-lpsp:
    - shard-bmg:          NOTRUN -> [SKIP][32] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#836])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-6/igt@kms_pm_rpm@modeset-lpsp.html

  * igt@kms_psr@psr2-sprite-plane-move:
    - shard-bmg:          NOTRUN -> [SKIP][33] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850])
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-6/igt@kms_psr@psr2-sprite-plane-move.html

  * igt@kms_vblank@ts-continuation-dpms-rpm@pipe-d-hdmi-a-3:
    - shard-bmg:          [PASS][34] -> [INCOMPLETE][35] ([Intel XE#4488]) +1 other test incomplete
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-5/igt@kms_vblank@ts-continuation-dpms-rpm@pipe-d-hdmi-a-3.html
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-2/igt@kms_vblank@ts-continuation-dpms-rpm@pipe-d-hdmi-a-3.html

  * igt@xe_create@multigpu-create-massive-size:
    - shard-bmg:          NOTRUN -> [SKIP][36] ([Intel XE#2504])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-6/igt@xe_create@multigpu-create-massive-size.html

  * igt@xe_exec_system_allocator@many-64k-mmap-new-huge-nomemset:
    - shard-bmg:          NOTRUN -> [SKIP][37] ([Intel XE#5007]) +1 other test skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-3/igt@xe_exec_system_allocator@many-64k-mmap-new-huge-nomemset.html

  * igt@xe_exec_system_allocator@process-many-mmap-shared-nomemset:
    - shard-bmg:          [PASS][38] -> [SKIP][39] ([Intel XE#6557] / [Intel XE#6703]) +6 other tests skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-3/igt@xe_exec_system_allocator@process-many-mmap-shared-nomemset.html
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-2/igt@xe_exec_system_allocator@process-many-mmap-shared-nomemset.html

  * igt@xe_exec_system_allocator@twice-mmap-free-madvise:
    - shard-bmg:          [PASS][40] -> [SKIP][41] ([Intel XE#6703]) +119 other tests skip
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-3/igt@xe_exec_system_allocator@twice-mmap-free-madvise.html
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-2/igt@xe_exec_system_allocator@twice-mmap-free-madvise.html

  * igt@xe_exec_system_allocator@twice-mmap-huge:
    - shard-bmg:          NOTRUN -> [SKIP][42] ([Intel XE#4943]) +3 other tests skip
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-3/igt@xe_exec_system_allocator@twice-mmap-huge.html

  * igt@xe_fault_injection@exec-queue-create-fail-xe_pxp_exec_queue_add:
    - shard-bmg:          NOTRUN -> [SKIP][43] ([Intel XE#6281])
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-6/igt@xe_fault_injection@exec-queue-create-fail-xe_pxp_exec_queue_add.html

  * igt@xe_pm@s2idle-multiple-execs:
    - shard-adlp:         [PASS][44] -> [DMESG-WARN][45] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#4504])
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-adlp-4/igt@xe_pm@s2idle-multiple-execs.html
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-adlp-9/igt@xe_pm@s2idle-multiple-execs.html

  
#### Possible fixes ####

  * igt@core_getversion@all-cards:
    - shard-bmg:          [FAIL][46] -> [PASS][47]
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-2/igt@core_getversion@all-cards.html
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-1/igt@core_getversion@all-cards.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
    - shard-bmg:          [DMESG-FAIL][48] ([Intel XE#5545]) -> [PASS][49] +1 other test pass
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-2/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-1/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html

  * igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1:
    - shard-adlp:         [FAIL][50] ([Intel XE#3908]) -> [PASS][51] +1 other test pass
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-adlp-3/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1.html
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-adlp-4/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
    - shard-adlp:         [FAIL][52] ([Intel XE#1231]) -> [PASS][53]
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-adlp-2/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-adlp-1/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html

  * igt@kms_bw@connected-linear-tiling-1-displays-2560x1440p:
    - shard-bmg:          [SKIP][54] ([Intel XE#367]) -> [PASS][55]
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-6/igt@kms_bw@connected-linear-tiling-1-displays-2560x1440p.html
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-4/igt@kms_bw@connected-linear-tiling-1-displays-2560x1440p.html

  * igt@kms_color@invalid-gamma-lut-sizes:
    - shard-adlp:         [DMESG-WARN][56] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][57] +1 other test pass
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-adlp-6/igt@kms_color@invalid-gamma-lut-sizes.html
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-adlp-4/igt@kms_color@invalid-gamma-lut-sizes.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-bmg:          [FAIL][58] ([Intel XE#5299]) -> [PASS][59]
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
    - shard-bmg:          [FAIL][60] ([Intel XE#4633]) -> [PASS][61]
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-6/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-4/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
    - shard-lnl:          [FAIL][62] ([Intel XE#301]) -> [PASS][63]
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html

  * igt@kms_flip@flip-vs-suspend-interruptible@b-hdmi-a1:
    - shard-adlp:         [DMESG-WARN][64] ([Intel XE#6766]) -> [PASS][65]
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-adlp-1/igt@kms_flip@flip-vs-suspend-interruptible@b-hdmi-a1.html
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-adlp-2/igt@kms_flip@flip-vs-suspend-interruptible@b-hdmi-a1.html

  * igt@kms_flip_tiling@flip-change-tiling:
    - shard-adlp:         [FAIL][66] ([Intel XE#1874]) -> [PASS][67] +2 other tests pass
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-adlp-6/igt@kms_flip_tiling@flip-change-tiling.html
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-adlp-2/igt@kms_flip_tiling@flip-change-tiling.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-bmg:          [ABORT][68] ([Intel XE#6740]) -> [PASS][69] +1 other test pass
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-5/igt@kms_hdr@bpc-switch-suspend.html
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-6/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_pm_rpm@basic-pci-d3-state:
    - shard-dg2-set2:     [FAIL][70] ([Intel XE#4741]) -> [PASS][71]
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-dg2-435/igt@kms_pm_rpm@basic-pci-d3-state.html
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-dg2-464/igt@kms_pm_rpm@basic-pci-d3-state.html

  * igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1:
    - shard-lnl:          [FAIL][72] ([Intel XE#2142]) -> [PASS][73] +1 other test pass
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-lnl-5/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-lnl-4/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html

  * igt@xe_exec_system_allocator@many-64k-mmap-file-nomemset:
    - shard-bmg:          [SKIP][74] ([Intel XE#6703]) -> [PASS][75] +44 other tests pass
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-2/igt@xe_exec_system_allocator@many-64k-mmap-file-nomemset.html
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-1/igt@xe_exec_system_allocator@many-64k-mmap-file-nomemset.html

  * igt@xe_exec_system_allocator@partial-atomic-munmap-cpu-fault:
    - shard-bmg:          [SKIP][76] ([Intel XE#6557] / [Intel XE#6703]) -> [PASS][77]
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-2/igt@xe_exec_system_allocator@partial-atomic-munmap-cpu-fault.html
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-1/igt@xe_exec_system_allocator@partial-atomic-munmap-cpu-fault.html

  * igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma:
    - shard-lnl:          [FAIL][78] ([Intel XE#5625]) -> [PASS][79]
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-lnl-2/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma.html
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-lnl-3/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma.html

  * igt@xe_module_load@load:
    - shard-dg2-set2:     ([PASS][80], [PASS][81], [PASS][82], [PASS][83], [PASS][84], [PASS][85], [PASS][86], [PASS][87], [PASS][88], [PASS][89], [PASS][90], [PASS][91], [PASS][92], [PASS][93], [PASS][94], [PASS][95], [PASS][96], [PASS][97], [PASS][98], [PASS][99], [PASS][100], [PASS][101], [PASS][102], [PASS][103], [PASS][104], [SKIP][105]) ([Intel XE#378]) -> ([PASS][106], [PASS][107], [PASS][108], [PASS][109], [PASS][110], [PASS][111], [PASS][112], [PASS][113], [PASS][114], [PASS][115], [PASS][116], [PASS][117], [PASS][118], [PASS][119], [PASS][120], [PASS][121], [PASS][122], [PASS][123], [PASS][124], [PASS][125], [PASS][126], [PASS][127], [PASS][128], [PASS][129], [PASS][130])
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-dg2-434/igt@xe_module_load@load.html
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-dg2-433/igt@xe_module_load@load.html
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-dg2-464/igt@xe_module_load@load.html
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-dg2-464/igt@xe_module_load@load.html
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-dg2-463/igt@xe_module_load@load.html
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-dg2-463/igt@xe_module_load@load.html
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-dg2-463/igt@xe_module_load@load.html
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-dg2-432/igt@xe_module_load@load.html
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-dg2-432/igt@xe_module_load@load.html
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-dg2-434/igt@xe_module_load@load.html
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-dg2-434/igt@xe_module_load@load.html
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-dg2-434/igt@xe_module_load@load.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-dg2-432/igt@xe_module_load@load.html
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-dg2-432/igt@xe_module_load@load.html
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-dg2-435/igt@xe_module_load@load.html
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-dg2-433/igt@xe_module_load@load.html
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-dg2-433/igt@xe_module_load@load.html
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-dg2-435/igt@xe_module_load@load.html
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-dg2-435/igt@xe_module_load@load.html
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-dg2-436/igt@xe_module_load@load.html
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-dg2-435/igt@xe_module_load@load.html
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-dg2-436/igt@xe_module_load@load.html
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-dg2-436/igt@xe_module_load@load.html
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-dg2-464/igt@xe_module_load@load.html
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-dg2-464/igt@xe_module_load@load.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-dg2-436/igt@xe_module_load@load.html
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-dg2-432/igt@xe_module_load@load.html
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-dg2-433/igt@xe_module_load@load.html
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-dg2-432/igt@xe_module_load@load.html
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-dg2-436/igt@xe_module_load@load.html
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-dg2-434/igt@xe_module_load@load.html
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-dg2-434/igt@xe_module_load@load.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-dg2-433/igt@xe_module_load@load.html
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-dg2-436/igt@xe_module_load@load.html
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-dg2-436/igt@xe_module_load@load.html
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-dg2-436/igt@xe_module_load@load.html
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-dg2-464/igt@xe_module_load@load.html
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-dg2-464/igt@xe_module_load@load.html
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-dg2-432/igt@xe_module_load@load.html
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-dg2-432/igt@xe_module_load@load.html
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-dg2-464/igt@xe_module_load@load.html
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-dg2-433/igt@xe_module_load@load.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-dg2-463/igt@xe_module_load@load.html
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-dg2-435/igt@xe_module_load@load.html
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-dg2-435/igt@xe_module_load@load.html
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-dg2-435/igt@xe_module_load@load.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-dg2-434/igt@xe_module_load@load.html
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-dg2-434/igt@xe_module_load@load.html
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-dg2-463/igt@xe_module_load@load.html
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-dg2-463/igt@xe_module_load@load.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-dg2-463/igt@xe_module_load@load.html

  * igt@xe_pmu@engine-activity-single-load-idle:
    - shard-dg2-set2:     [FAIL][131] ([Intel XE#6812]) -> [PASS][132] +1 other test pass
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-dg2-433/igt@xe_pmu@engine-activity-single-load-idle.html
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-dg2-433/igt@xe_pmu@engine-activity-single-load-idle.html

  * igt@xe_vm@bind-array-enobufs:
    - shard-dg2-set2:     [FAIL][133] ([Intel XE#6774]) -> [PASS][134]
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-dg2-434/igt@xe_vm@bind-array-enobufs.html
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-dg2-432/igt@xe_vm@bind-array-enobufs.html

  
#### Warnings ####

  * igt@kms_big_fb@x-tiled-32bpp-rotate-270:
    - shard-bmg:          [SKIP][135] ([Intel XE#2327]) -> [SKIP][136] ([Intel XE#6703])
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-3/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-2/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
    - shard-bmg:          [SKIP][137] ([Intel XE#1124]) -> [SKIP][138] ([Intel XE#6703]) +1 other test skip
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-3/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-2/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@yf-tiled-addfb-size-overflow:
    - shard-bmg:          [SKIP][139] ([Intel XE#610]) -> [SKIP][140] ([Intel XE#6703])
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-3/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-2/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html

  * igt@kms_bw@linear-tiling-4-displays-1920x1080p:
    - shard-bmg:          [SKIP][141] ([Intel XE#367]) -> [SKIP][142] ([Intel XE#6703])
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-3/igt@kms_bw@linear-tiling-4-displays-1920x1080p.html
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-2/igt@kms_bw@linear-tiling-4-displays-1920x1080p.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs:
    - shard-bmg:          [SKIP][143] ([Intel XE#6703]) -> [SKIP][144] ([Intel XE#2887]) +1 other test skip
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-2/igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs.html
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-1/igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs-cc:
    - shard-bmg:          [SKIP][145] ([Intel XE#2887]) -> [SKIP][146] ([Intel XE#6703]) +4 other tests skip
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-3/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs-cc.html
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-2/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs-cc.html

  * igt@kms_chamelium_frames@hdmi-frame-dump:
    - shard-bmg:          [SKIP][147] ([Intel XE#2252]) -> [SKIP][148] ([Intel XE#6703]) +1 other test skip
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-3/igt@kms_chamelium_frames@hdmi-frame-dump.html
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-2/igt@kms_chamelium_frames@hdmi-frame-dump.html

  * igt@kms_colorop@plane-xr30-xr30-ctm_3x4_bt709_enc_dec:
    - shard-bmg:          [SKIP][149] ([Intel XE#6704]) -> [SKIP][150] ([Intel XE#6703]) +1 other test skip
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-3/igt@kms_colorop@plane-xr30-xr30-ctm_3x4_bt709_enc_dec.html
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-2/igt@kms_colorop@plane-xr30-xr30-ctm_3x4_bt709_enc_dec.html

  * igt@kms_content_protection@dp-mst-type-1:
    - shard-bmg:          [SKIP][151] ([Intel XE#2390]) -> [SKIP][152] ([Intel XE#6703])
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-3/igt@kms_content_protection@dp-mst-type-1.html
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-2/igt@kms_content_protection@dp-mst-type-1.html

  * igt@kms_content_protection@mei-interface:
    - shard-bmg:          [SKIP][153] ([Intel XE#2341]) -> [SKIP][154] ([Intel XE#6703])
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-3/igt@kms_content_protection@mei-interface.html
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-2/igt@kms_content_protection@mei-interface.html

  * igt@kms_cursor_crc@cursor-onscreen-256x85:
    - shard-bmg:          [SKIP][155] ([Intel XE#2320]) -> [SKIP][156] ([Intel XE#6703])
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-3/igt@kms_cursor_crc@cursor-onscreen-256x85.html
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-2/igt@kms_cursor_crc@cursor-onscreen-256x85.html

  * igt@kms_cursor_crc@cursor-rapid-movement-512x170:
    - shard-bmg:          [SKIP][157] ([Intel XE#6703]) -> [SKIP][158] ([Intel XE#2321])
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-2/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-1/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html

  * igt@kms_dirtyfb@fbc-dirtyfb-ioctl:
    - shard-bmg:          [SKIP][159] ([Intel XE#4210]) -> [SKIP][160] ([Intel XE#6703])
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-3/igt@kms_dirtyfb@fbc-dirtyfb-ioctl.html
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-2/igt@kms_dirtyfb@fbc-dirtyfb-ioctl.html

  * igt@kms_dp_link_training@non-uhbr-mst:
    - shard-bmg:          [SKIP][161] ([Intel XE#4354]) -> [SKIP][162] ([Intel XE#6703])
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-3/igt@kms_dp_link_training@non-uhbr-mst.html
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-2/igt@kms_dp_link_training@non-uhbr-mst.html

  * igt@kms_dp_link_training@uhbr-sst:
    - shard-bmg:          [FAIL][163] ([Intel XE#6793]) -> [SKIP][164] ([Intel XE#4354])
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-6/igt@kms_dp_link_training@uhbr-sst.html
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-4/igt@kms_dp_link_training@uhbr-sst.html

  * igt@kms_feature_discovery@psr1:
    - shard-bmg:          [SKIP][165] ([Intel XE#2374]) -> [SKIP][166] ([Intel XE#6557] / [Intel XE#6703])
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-3/igt@kms_feature_discovery@psr1.html
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-2/igt@kms_feature_discovery@psr1.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-lnl:          [FAIL][167] ([Intel XE#301]) -> [FAIL][168] ([Intel XE#301] / [Intel XE#3149])
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-adlp:         [DMESG-WARN][169] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#6766]) -> [DMESG-WARN][170] ([Intel XE#6766]) +1 other test dmesg-warn
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-adlp-1/igt@kms_flip@flip-vs-suspend-interruptible.html
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-adlp-2/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
    - shard-bmg:          [SKIP][171] ([Intel XE#2293] / [Intel XE#2380]) -> [SKIP][172] ([Intel XE#6703])
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling:
    - shard-bmg:          [SKIP][173] ([Intel XE#6703]) -> [SKIP][174] ([Intel XE#2293] / [Intel XE#2380])
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-1/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-blt:
    - shard-bmg:          [SKIP][175] ([Intel XE#2311]) -> [SKIP][176] ([Intel XE#6557] / [Intel XE#6703])
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-3/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-blt.html
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@drrs-rgb565-draw-render:
    - shard-bmg:          [SKIP][177] ([Intel XE#6703]) -> [SKIP][178] ([Intel XE#2311]) +2 other tests skip
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-rgb565-draw-render.html
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-1/igt@kms_frontbuffer_tracking@drrs-rgb565-draw-render.html

  * igt@kms_frontbuffer_tracking@drrs-slowdraw:
    - shard-bmg:          [SKIP][179] ([Intel XE#6557] / [Intel XE#6703]) -> [SKIP][180] ([Intel XE#2311])
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-slowdraw.html
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-1/igt@kms_frontbuffer_tracking@drrs-slowdraw.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move:
    - shard-bmg:          [SKIP][181] ([Intel XE#6703]) -> [SKIP][182] ([Intel XE#4141]) +1 other test skip
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbc-stridechange:
    - shard-bmg:          [SKIP][183] ([Intel XE#4141]) -> [SKIP][184] ([Intel XE#6703]) +3 other tests skip
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-stridechange.html
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-stridechange.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-render:
    - shard-bmg:          [SKIP][185] ([Intel XE#2311]) -> [SKIP][186] ([Intel XE#6703]) +3 other tests skip
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-render.html
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][187] ([Intel XE#6703]) -> [SKIP][188] ([Intel XE#2313]) +2 other tests skip
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc.html
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff:
    - shard-bmg:          [SKIP][189] ([Intel XE#2313]) -> [SKIP][190] ([Intel XE#6703]) +4 other tests skip
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff.html
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-y:
    - shard-bmg:          [SKIP][191] ([Intel XE#2352]) -> [SKIP][192] ([Intel XE#6703])
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html

  * igt@kms_plane_multiple@2x-tiling-y:
    - shard-bmg:          [SKIP][193] ([Intel XE#5021]) -> [SKIP][194] ([Intel XE#6557] / [Intel XE#6703])
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-3/igt@kms_plane_multiple@2x-tiling-y.html
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-2/igt@kms_plane_multiple@2x-tiling-y.html

  * igt@kms_pm_dc@dc6-psr:
    - shard-bmg:          [SKIP][195] ([Intel XE#2392]) -> [SKIP][196] ([Intel XE#6703])
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-3/igt@kms_pm_dc@dc6-psr.html
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-2/igt@kms_pm_dc@dc6-psr.html

  * igt@kms_psr2_sf@psr2-overlay-plane-update-continuous-sf:
    - shard-bmg:          [SKIP][197] ([Intel XE#1406] / [Intel XE#1489]) -> [SKIP][198] ([Intel XE#1406] / [Intel XE#6703]) +1 other test skip
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-3/igt@kms_psr2_sf@psr2-overlay-plane-update-continuous-sf.html
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-2/igt@kms_psr2_sf@psr2-overlay-plane-update-continuous-sf.html

  * igt@kms_psr@fbc-psr-primary-render:
    - shard-bmg:          [SKIP][199] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) -> [SKIP][200] ([Intel XE#1406] / [Intel XE#6703]) +2 other tests skip
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-3/igt@kms_psr@fbc-psr-primary-render.html
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-2/igt@kms_psr@fbc-psr-primary-render.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-dg2-set2:     [SKIP][201] ([Intel XE#1500]) -> [SKIP][202] ([Intel XE#362])
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-dg2-464/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-dg2-463/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@kms_vrr@flip-dpms:
    - shard-bmg:          [SKIP][203] ([Intel XE#1499]) -> [SKIP][204] ([Intel XE#6703])
   [203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-3/igt@kms_vrr@flip-dpms.html
   [204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-2/igt@kms_vrr@flip-dpms.html

  * igt@xe_eudebug@basic-vm-bind-extended-discovery:
    - shard-bmg:          [SKIP][205] ([Intel XE#4837]) -> [SKIP][206] ([Intel XE#6703]) +1 other test skip
   [205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-3/igt@xe_eudebug@basic-vm-bind-extended-discovery.html
   [206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-2/igt@xe_eudebug@basic-vm-bind-extended-discovery.html

  * igt@xe_eudebug_online@pagefault-read:
    - shard-bmg:          [SKIP][207] ([Intel XE#4837] / [Intel XE#6665]) -> [SKIP][208] ([Intel XE#6703])
   [207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-3/igt@xe_eudebug_online@pagefault-read.html
   [208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-2/igt@xe_eudebug_online@pagefault-read.html

  * igt@xe_eudebug_online@reset-with-attention:
    - shard-bmg:          [SKIP][209] ([Intel XE#6703]) -> [SKIP][210] ([Intel XE#4837] / [Intel XE#6665])
   [209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-2/igt@xe_eudebug_online@reset-with-attention.html
   [210]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-1/igt@xe_eudebug_online@reset-with-attention.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-rebind:
    - shard-bmg:          [SKIP][211] ([Intel XE#2322]) -> [SKIP][212] ([Intel XE#6703]) +1 other test skip
   [211]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-3/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-rebind.html
   [212]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-2/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-rebind.html

  * igt@xe_exec_system_allocator@threads-many-mmap-new-huge-nomemset:
    - shard-bmg:          [SKIP][213] ([Intel XE#4943]) -> [SKIP][214] ([Intel XE#6703]) +4 other tests skip
   [213]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-3/igt@xe_exec_system_allocator@threads-many-mmap-new-huge-nomemset.html
   [214]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-2/igt@xe_exec_system_allocator@threads-many-mmap-new-huge-nomemset.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-new-huge-nomemset:
    - shard-bmg:          [SKIP][215] ([Intel XE#6703]) -> [SKIP][216] ([Intel XE#4943])
   [215]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-2/igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-new-huge-nomemset.html
   [216]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-1/igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-new-huge-nomemset.html

  * igt@xe_oa@oa-tlb-invalidate:
    - shard-bmg:          [SKIP][217] ([Intel XE#6703]) -> [SKIP][218] ([Intel XE#2248])
   [217]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-2/igt@xe_oa@oa-tlb-invalidate.html
   [218]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-1/igt@xe_oa@oa-tlb-invalidate.html

  * igt@xe_pm@d3cold-multiple-execs:
    - shard-bmg:          [SKIP][219] ([Intel XE#6703]) -> [SKIP][220] ([Intel XE#2284])
   [219]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-2/igt@xe_pm@d3cold-multiple-execs.html
   [220]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-1/igt@xe_pm@d3cold-multiple-execs.html

  * igt@xe_pxp@pxp-stale-bo-bind-post-termination-irq:
    - shard-bmg:          [SKIP][221] ([Intel XE#4733]) -> [SKIP][222] ([Intel XE#6703])
   [221]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-3/igt@xe_pxp@pxp-stale-bo-bind-post-termination-irq.html
   [222]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-2/igt@xe_pxp@pxp-stale-bo-bind-post-termination-irq.html

  * igt@xe_query@multigpu-query-invalid-uc-fw-version-mbz:
    - shard-bmg:          [SKIP][223] ([Intel XE#6703]) -> [SKIP][224] ([Intel XE#944])
   [223]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-2/igt@xe_query@multigpu-query-invalid-uc-fw-version-mbz.html
   [224]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-1/igt@xe_query@multigpu-query-invalid-uc-fw-version-mbz.html

  * igt@xe_query@multigpu-query-uc-fw-version-huc:
    - shard-bmg:          [SKIP][225] ([Intel XE#944]) -> [SKIP][226] ([Intel XE#6703])
   [225]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f/shard-bmg-3/igt@xe_query@multigpu-query-uc-fw-version-huc.html
   [226]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/shard-bmg-2/igt@xe_query@multigpu-query-uc-fw-version-huc.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1231]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1231
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1500]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1500
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#1874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1874
  [Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
  [Intel XE#2142]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2142
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2248]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2248
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
  [Intel XE#2352]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2352
  [Intel XE#2374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2374
  [Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
  [Intel XE#2390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2390
  [Intel XE#2392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2392
  [Intel XE#2504]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2504
  [Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
  [Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/362
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
  [Intel XE#3908]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3908
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
  [Intel XE#4210]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4210
  [Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
  [Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
  [Intel XE#4488]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4488
  [Intel XE#4504]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4504
  [Intel XE#4633]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4633
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4741]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4741
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
  [Intel XE#5007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5007
  [Intel XE#5021]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5021
  [Intel XE#5299]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5299
  [Intel XE#5354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5354
  [Intel XE#5545]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5545
  [Intel XE#5625]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5625
  [Intel XE#610]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/610
  [Intel XE#6168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6168
  [Intel XE#6281]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6281
  [Intel XE#6557]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6557
  [Intel XE#6665]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6665
  [Intel XE#6703]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6703
  [Intel XE#6704]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6704
  [Intel XE#6740]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6740
  [Intel XE#6766]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6766
  [Intel XE#6774]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6774
  [Intel XE#6779]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6779
  [Intel XE#6793]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6793
  [Intel XE#6812]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6812
  [Intel XE#6815]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6815
  [Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f -> xe-pw-158688v1

  IGT_8659: 8659
  xe-4208-48deab361d3b570e2210875fdc8ffb29627d054f: 48deab361d3b570e2210875fdc8ffb29627d054f
  xe-pw-158688v1: 158688v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158688v1/index.html

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