* [PATCH v3 1/2] drm/i915/ltphy: Implement HDMI Algo for Pll state
@ 2025-11-10 6:19 Suraj Kandpal
2025-11-10 6:19 ` [PATCH v3 2/2] drm/i915/ltphy: Return lowest portclock for HDMI from reverse algorithm Suraj Kandpal
` (7 more replies)
0 siblings, 8 replies; 10+ messages in thread
From: Suraj Kandpal @ 2025-11-10 6:19 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, Suraj Kandpal
Implement the HDMI Algorithm to dynamically create LT PHY state
based on the port clock provided.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
v1 -> v2:
-Add new macro functions and definitions for address assignment(Ankit)
-Introduce a structure lt_phy_param for code readability (Ankit)
v2 ->v3:
-Seprate out param calulation wherever possible (Ankit)
-Modify Macro to accept pll_reg (Ankit)
drivers/gpu/drm/i915/display/intel_lt_phy.c | 345 +++++++++++++++++-
drivers/gpu/drm/i915/display/intel_lt_phy.h | 3 +
.../gpu/drm/i915/display/intel_lt_phy_regs.h | 16 +
3 files changed, 362 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index af48d6cde226..d88dbfbe97b1 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -31,6 +31,32 @@
#define INTEL_LT_PHY_BOTH_LANES (INTEL_LT_PHY_LANE1 |\
INTEL_LT_PHY_LANE0)
#define MODE_DP 3
+#define Q32_TO_INT(x) ((x) >> 32)
+#define Q32_TO_FRAC(x) ((x) & 0xFFFFFFFF)
+#define DCO_MIN_FREQ_MHZ 11850
+#define REF_CLK_KHZ 38400
+#define TDC_RES_MULTIPLIER 10000000ULL
+
+struct phy_param_t {
+ u32 val;
+ u32 addr;
+};
+
+struct lt_phy_params {
+ struct phy_param_t pll_reg4;
+ struct phy_param_t pll_reg3;
+ struct phy_param_t pll_reg5;
+ struct phy_param_t pll_reg57;
+ struct phy_param_t lf;
+ struct phy_param_t tdc;
+ struct phy_param_t ssc;
+ struct phy_param_t bias2;
+ struct phy_param_t bias_trim;
+ struct phy_param_t dco_med;
+ struct phy_param_t dco_fine;
+ struct phy_param_t ssc_inj;
+ struct phy_param_t surv_bonus;
+};
static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_rbr = {
.clock = 162000,
@@ -1356,10 +1382,322 @@ intel_lt_phy_pll_is_ssc_enabled(struct intel_crtc_state *crtc_state,
return false;
}
+static u64 mul_q32_u32(u64 a_q32, u32 b)
+{
+ u64 p0, p1, carry, result;
+ u64 x_hi = a_q32 >> 32;
+ u64 x_lo = a_q32 & 0xFFFFFFFFULL;
+
+ p0 = x_lo * (u64)b;
+ p1 = x_hi * (u64)b;
+ carry = p0 >> 32;
+ result = (p1 << 32) + (carry << 32) + (p0 & 0xFFFFFFFFULL);
+
+ return result;
+}
+
+static bool
+calculate_target_dco_and_loop_cnt(u32 frequency_khz, u64 *target_dco_mhz, u32 *loop_cnt)
+{
+ u32 ppm_value = 1;
+ u32 dco_min_freq = DCO_MIN_FREQ_MHZ;
+ u32 dco_max_freq = 16200;
+ u32 dco_min_freq_low = 10000;
+ u32 dco_max_freq_low = 12000;
+ u64 val = 0;
+ u64 refclk_khz = REF_CLK_KHZ;
+ u64 m2div = 0;
+ u64 val_with_frac = 0;
+ u64 ppm = 0;
+ u64 temp0 = 0, temp1, scale;
+ int ppm_cnt, dco_count, y;
+
+ for (ppm_cnt = 0; ppm_cnt < 5; ppm_cnt++) {
+ ppm_value = ppm_cnt == 2 ? 2 : 1;
+ for (dco_count = 0; dco_count < 2; dco_count++) {
+ if (dco_count == 1) {
+ dco_min_freq = dco_min_freq_low;
+ dco_max_freq = dco_max_freq_low;
+ }
+ for (y = 2; y <= 255; y += 2) {
+ val = div64_u64((u64)y * frequency_khz, 200);
+ m2div = div64_u64(((u64)(val) << 32), refclk_khz);
+ m2div = mul_q32_u32(m2div, 500);
+ val_with_frac = mul_q32_u32(m2div, refclk_khz);
+ val_with_frac = div64_u64(val_with_frac, 500);
+ temp1 = Q32_TO_INT(val_with_frac);
+ temp0 = (temp1 > val) ? (temp1 - val) :
+ (val - temp1);
+ ppm = div64_u64(temp0, val);
+ if (temp1 >= dco_min_freq &&
+ temp1 <= dco_max_freq &&
+ ppm < ppm_value) {
+ /* Round to two places */
+ scale = (1ULL << 32) / 100;
+ temp0 = DIV_ROUND_UP_ULL(val_with_frac,
+ scale);
+ *target_dco_mhz = temp0 * scale;
+ *loop_cnt = y;
+ return true;
+ }
+ }
+ }
+ }
+
+ return false;
+}
+
+static void set_phy_vdr_addresses(struct lt_phy_params *p, int pll_type)
+{
+ p->pll_reg4.addr = PLL_REG_ADDR(PLL_REG4_ADDR, pll_type);
+ p->pll_reg3.addr = PLL_REG_ADDR(PLL_REG3_ADDR, pll_type);
+ p->pll_reg5.addr = PLL_REG_ADDR(PLL_REG5_ADDR, pll_type);
+ p->pll_reg57.addr = PLL_REG_ADDR(PLL_REG57_ADDR, pll_type);
+ p->lf.addr = PLL_REG_ADDR(PLL_LF_ADDR, pll_type);
+ p->tdc.addr = PLL_REG_ADDR(PLL_TDC_ADDR, pll_type);
+ p->ssc.addr = PLL_REG_ADDR(PLL_SSC_ADDR, pll_type);
+ p->bias2.addr = PLL_REG_ADDR(PLL_BIAS2_ADDR, pll_type);
+ p->bias_trim.addr = PLL_REG_ADDR(PLL_BIAS_TRIM_ADDR, pll_type);
+ p->dco_med.addr = PLL_REG_ADDR(PLL_DCO_MED_ADDR, pll_type);
+ p->dco_fine.addr = PLL_REG_ADDR(PLL_DCO_FINE_ADDR, pll_type);
+ p->ssc_inj.addr = PLL_REG_ADDR(PLL_SSC_INJ_ADDR, pll_type);
+ p->surv_bonus.addr = PLL_REG_ADDR(PLL_SURV_BONUS_ADDR, pll_type);
+}
+
+static void compute_ssc(struct lt_phy_params *p, u32 ana_cfg)
+{
+ int ssc_stepsize = 0;
+ int ssc_steplen = 0;
+ int ssc_steplog = 0;
+
+ p->ssc.val = (1 << 31) | (ana_cfg << 24) | (ssc_steplog << 16) |
+ (ssc_stepsize << 8) | ssc_steplen;
+}
+
+static void compute_bias2(struct lt_phy_params *p)
+{
+ u32 ssc_en_local = 0;
+ u64 dynctrl_ovrd_en = 0;
+
+ p->bias2.val = (dynctrl_ovrd_en << 31) | (ssc_en_local << 30) |
+ (1 << 23) | (1 << 24) | (32 << 16) | (1 << 8);
+}
+
+static void compute_tdc(struct lt_phy_params *p, u64 tdc_fine)
+{
+ u32 settling_time = 15;
+ u32 bias_ovr_en = 1;
+ u32 coldstart = 1;
+ u32 true_lock = 2;
+ u32 early_lock = 1;
+ u32 lock_ovr_en = 1;
+ u32 lock_thr = tdc_fine ? 3 : 5;
+ u32 unlock_thr = tdc_fine ? 5 : 11;
+
+ p->tdc.val = (u32)((2 << 30) + (settling_time << 16) + (bias_ovr_en << 15) +
+ (lock_ovr_en << 14) + (coldstart << 12) + (true_lock << 10) +
+ (early_lock << 8) + (unlock_thr << 4) + lock_thr);
+}
+
+static void compute_dco_med(struct lt_phy_params *p)
+{
+ u32 cselmed_en = 0;
+ u32 cselmed_dyn_adj = 0;
+ u32 cselmed_ratio = 39;
+ u32 cselmed_thr = 8;
+
+ p->dco_med.val = (cselmed_en << 31) + (cselmed_dyn_adj << 30) +
+ (cselmed_ratio << 24) + (cselmed_thr << 21);
+}
+
+static void compute_dco_fine(struct lt_phy_params *p, u32 dco_12g)
+{
+ u32 dco_fine0_tune_2_0 = 0;
+ u32 dco_fine1_tune_2_0 = 0;
+ u32 dco_fine2_tune_2_0 = 0;
+ u32 dco_fine3_tune_2_0 = 0;
+ u32 dco_dith0_tune_2_0 = 0;
+ u32 dco_dith1_tune_2_0 = 0;
+
+ dco_fine0_tune_2_0 = dco_12g ? 4 : 3;
+ dco_fine1_tune_2_0 = 2;
+ dco_fine2_tune_2_0 = dco_12g ? 2 : 1;
+ dco_fine3_tune_2_0 = 5;
+ dco_dith0_tune_2_0 = dco_12g ? 4 : 3;
+ dco_dith1_tune_2_0 = 2;
+
+ p->dco_fine.val = (dco_dith1_tune_2_0 << 19)
+ + (dco_dith0_tune_2_0 << 16)
+ + (dco_fine3_tune_2_0 << 11)
+ + (dco_fine2_tune_2_0 << 8)
+ + (dco_fine1_tune_2_0 << 3)
+ + dco_fine0_tune_2_0;
+}
+
+int
+intel_lt_phy_calculate_hdmi_state(struct intel_lt_phy_pll_state *lt_state,
+ u32 frequency_khz)
+{
+#define DATA_ASSIGN(i, pll_reg) \
+ do { \
+ lt_state->data[i][0] = (u8)((((pll_reg).val) & 0xFF000000) >> 24); \
+ lt_state->data[i][1] = (u8)((((pll_reg).val) & 0x00FF0000) >> 16); \
+ lt_state->data[i][2] = (u8)((((pll_reg).val) & 0x0000FF00) >> 8); \
+ lt_state->data[i][3] = (u8)((((pll_reg).val) & 0x000000FF)); \
+ } while (0)
+#define ADDR_ASSIGN(i, pll_reg) \
+ do { \
+ lt_state->addr_msb[i] = ((pll_reg).addr >> 8) & 0xFF; \
+ lt_state->addr_lsb[i] = (pll_reg).addr & 0xFF; \
+ } while (0)
+
+ bool found = false;
+ struct lt_phy_params p;
+ u32 dco_fmin = DCO_MIN_FREQ_MHZ;
+ u64 refclk_khz = REF_CLK_KHZ;
+ u64 m2div = 0;
+ u64 target_dco_mhz = 0;
+ u64 tdc_fine;
+ u64 tdc_targetcnt;
+ u64 feedfwd_gain;
+ u64 feedfwd_cal_en;
+ u64 tdc_res = 30;
+ u32 prop_coeff;
+ u32 int_coeff;
+ u32 ndiv = 1;
+ u32 m1div = 1;
+ u32 m2div_int;
+ u32 m2div_frac;
+ u32 frac_en;
+ u32 ana_cfg;
+ u32 loop_cnt = 0;
+ u32 gain_ctrl = 2;
+ u32 refclk_mhz_int = 38;
+ u32 postdiv = 0;
+ u32 d6_new = 0;
+ u32 dco_12g = 0;
+ u32 pll_type = 0;
+ u32 d1 = 2;
+ u32 d3 = 5;
+ u32 d5 = 0;
+ u32 d6 = 0;
+ u32 d7;
+ u32 d8 = 0;
+ u32 d4 = 0;
+ u32 bonus_7_0 = 0;
+ u32 csel2fo = 11;
+ u32 csel2fo_ovrd_en = 1;
+ u64 temp0, temp1, temp2, temp3;
+
+ p.surv_bonus.val = (bonus_7_0 << 16);
+ p.pll_reg4.val = (refclk_mhz_int << 17) +
+ (ndiv << 9) + (1 << 4);
+ p.bias_trim.val = (csel2fo_ovrd_en << 30) + (csel2fo << 24);
+ p.ssc_inj.val = 0;
+ found = calculate_target_dco_and_loop_cnt(frequency_khz, &target_dco_mhz, &loop_cnt);
+ if (!found)
+ return -EINVAL;
+
+ m2div = div64_u64(target_dco_mhz, (refclk_khz * ndiv * m1div));
+ m2div = mul_q32_u32(m2div, 1000);
+ if (Q32_TO_INT(m2div) > 511)
+ return -EINVAL;
+
+ m2div_int = (u32)Q32_TO_INT(m2div);
+ m2div_frac = (u32)(Q32_TO_FRAC(m2div));
+ frac_en = (m2div_frac > 0) ? 1 : 0;
+
+ if (frac_en > 0)
+ tdc_res = 70;
+ else
+ tdc_res = 36;
+ tdc_fine = tdc_res > 50 ? 1 : 0;
+ temp0 = tdc_res * 40 * 11;
+ temp1 = div64_u64(((4 * TDC_RES_MULTIPLIER) + temp0) * 500, temp0 * refclk_khz);
+ temp2 = div64_u64(temp0 * refclk_khz, 1000);
+ temp3 = div64_u64(((8 * TDC_RES_MULTIPLIER) + temp2), temp2);
+ tdc_targetcnt = tdc_res < 50 ? (int)(temp1) : (int)(temp3);
+ tdc_targetcnt = (int)(tdc_targetcnt / 2);
+ temp0 = mul_q32_u32(target_dco_mhz, tdc_res);
+ temp0 >>= 32;
+ feedfwd_gain = (m2div_frac > 0) ? div64_u64(m1div * TDC_RES_MULTIPLIER, temp0) : 0;
+ feedfwd_cal_en = frac_en;
+
+ temp0 = (u32)Q32_TO_INT(target_dco_mhz);
+ prop_coeff = (temp0 >= dco_fmin) ? 3 : 4;
+ int_coeff = (temp0 >= dco_fmin) ? 7 : 8;
+ ana_cfg = (temp0 >= dco_fmin) ? 8 : 6;
+ dco_12g = (temp0 >= dco_fmin) ? 0 : 1;
+
+ if (temp0 > 12960)
+ d7 = 10;
+ else
+ d7 = 8;
+
+ d8 = loop_cnt / 2;
+ d4 = d8 * 2;
+
+ /* Compute pll_reg3,5,57 & lf */
+ p.pll_reg3.val = (u32)((d4 << 21) + (d3 << 18) + (d1 << 15) + (m2div_int << 5));
+ p.pll_reg5.val = m2div_frac;
+ postdiv = (d5 == 0) ? 9 : d5;
+ d6_new = (d6 == 0) ? 40 : d6;
+ p.pll_reg57.val = (d7 << 24) + (postdiv << 15) + (d8 << 7) + d6_new;
+ p.lf.val = (u32)((frac_en << 31) + (1 << 30) + (frac_en << 29) +
+ (feedfwd_cal_en << 28) + (tdc_fine << 27) +
+ (gain_ctrl << 24) + (feedfwd_gain << 16) +
+ (int_coeff << 12) + (prop_coeff << 8) + tdc_targetcnt);
+
+ /* Compute ssc / bias2 */
+ compute_ssc(&p, ana_cfg);
+ compute_bias2(&p);
+
+ /* Compute tdc/dco_med */
+ compute_tdc(&p, tdc_fine);
+ compute_dco_med(&p);
+
+ /* Compute dcofine */
+ compute_dco_fine(&p, dco_12g);
+
+ pll_type = ((frequency_khz == 10000) || (frequency_khz == 20000) ||
+ (frequency_khz == 2500) || (dco_12g == 1)) ? 0 : 1;
+ set_phy_vdr_addresses(&p, pll_type);
+
+ lt_state->config[0] = 0x84;
+ lt_state->config[1] = 0x2d;
+ ADDR_ASSIGN(0, p.pll_reg4);
+ ADDR_ASSIGN(1, p.pll_reg3);
+ ADDR_ASSIGN(2, p.pll_reg5);
+ ADDR_ASSIGN(3, p.pll_reg57);
+ ADDR_ASSIGN(4, p.lf);
+ ADDR_ASSIGN(5, p.tdc);
+ ADDR_ASSIGN(6, p.ssc);
+ ADDR_ASSIGN(7, p.bias2);
+ ADDR_ASSIGN(8, p.bias_trim);
+ ADDR_ASSIGN(9, p.dco_med);
+ ADDR_ASSIGN(10, p.dco_fine);
+ ADDR_ASSIGN(11, p.ssc_inj);
+ ADDR_ASSIGN(12, p.surv_bonus);
+ DATA_ASSIGN(0, p.pll_reg4);
+ DATA_ASSIGN(1, p.pll_reg3);
+ DATA_ASSIGN(2, p.pll_reg5);
+ DATA_ASSIGN(3, p.pll_reg57);
+ DATA_ASSIGN(4, p.lf);
+ DATA_ASSIGN(5, p.tdc);
+ DATA_ASSIGN(6, p.ssc);
+ DATA_ASSIGN(7, p.bias2);
+ DATA_ASSIGN(8, p.bias_trim);
+ DATA_ASSIGN(9, p.dco_med);
+ DATA_ASSIGN(10, p.dco_fine);
+ DATA_ASSIGN(11, p.ssc_inj);
+ DATA_ASSIGN(12, p.surv_bonus);
+
+ return 0;
+}
+
static int
intel_lt_phy_calc_hdmi_port_clock(const struct intel_lt_phy_pll_state *lt_state)
{
-#define REF_CLK_KHZ 38400
#define REGVAL(i) ( \
(lt_state->data[i][3]) | \
(lt_state->data[i][2] << 8) | \
@@ -1472,7 +1810,10 @@ intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
}
}
- /* TODO: Add a function to compute the data for HDMI TMDS*/
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
+ return intel_lt_phy_calculate_hdmi_state(&crtc_state->dpll_hw_state.ltpll,
+ crtc_state->port_clock);
+ }
return -EINVAL;
}
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
index a538d4c69210..b7911acd7dcd 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
@@ -35,6 +35,9 @@ void intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
struct intel_lt_phy_pll_state *pll_state);
void intel_lt_phy_pll_state_verify(struct intel_atomic_state *state,
struct intel_crtc *crtc);
+int
+intel_lt_phy_calculate_hdmi_state(struct intel_lt_phy_pll_state *lt_state,
+ u32 frequency_khz);
void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
index 9223487d764e..dc7b7679cd06 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
@@ -72,4 +72,20 @@
#define XE3PLPD_PORT_P2M_MSGBUS_STATUS_P2P(port, lane) _XE3PLPD_PORT_P2M_MSGBUS_STATUS_P2P(__xe2lpd_port_idx(port), \
lane)
#define XE3LPD_PORT_P2M_ADDR_MASK REG_GENMASK(11, 0)
+
+#define PLL_REG4_ADDR 0x8510
+#define PLL_REG3_ADDR 0x850C
+#define PLL_REG5_ADDR 0x8514
+#define PLL_REG57_ADDR 0x85E4
+#define PLL_LF_ADDR 0x860C
+#define PLL_TDC_ADDR 0x8610
+#define PLL_SSC_ADDR 0x8614
+#define PLL_BIAS2_ADDR 0x8618
+#define PLL_BIAS_TRIM_ADDR 0x8648
+#define PLL_DCO_MED_ADDR 0x8640
+#define PLL_DCO_FINE_ADDR 0x864C
+#define PLL_SSC_INJ_ADDR 0x8624
+#define PLL_SURV_BONUS_ADDR 0x8644
+#define PLL_TYPE_OFFSET 0x200
+#define PLL_REG_ADDR(base, pll_type) ((pll_type) ? (base) + PLL_TYPE_OFFSET : (base))
#endif /* __INTEL_LT_PHY_REGS_H__ */
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v3 2/2] drm/i915/ltphy: Return lowest portclock for HDMI from reverse algorithm
2025-11-10 6:19 [PATCH v3 1/2] drm/i915/ltphy: Implement HDMI Algo for Pll state Suraj Kandpal
@ 2025-11-10 6:19 ` Suraj Kandpal
2025-11-10 6:26 ` ✗ CI.checkpatch: warning for series starting with [v3,1/2] drm/i915/ltphy: Implement HDMI Algo for Pll state Patchwork
` (6 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Suraj Kandpal @ 2025-11-10 6:19 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, Suraj Kandpal
Return the lowest port clock for HDMI when the reverse algorithm
calculates it to be 0 to avoid errors later but throw a warn.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
v1 -> v2:
-Derive intel_display in first line (Ankit)
-Use the actual lowest clock from table (Ankit)
drivers/gpu/drm/i915/display/intel_lt_phy.c | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index d88dbfbe97b1..10b82171b114 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -1696,7 +1696,7 @@ intel_lt_phy_calculate_hdmi_state(struct intel_lt_phy_pll_state *lt_state,
}
static int
-intel_lt_phy_calc_hdmi_port_clock(const struct intel_lt_phy_pll_state *lt_state)
+intel_lt_phy_calc_hdmi_port_clock(const struct intel_crtc_state *crtc_state)
{
#define REGVAL(i) ( \
(lt_state->data[i][3]) | \
@@ -1705,6 +1705,9 @@ intel_lt_phy_calc_hdmi_port_clock(const struct intel_lt_phy_pll_state *lt_state)
(lt_state->data[i][0] << 24) \
)
+ struct intel_display *display = to_intel_display(crtc_state);
+ const struct intel_lt_phy_pll_state *lt_state =
+ &crtc_state->dpll_hw_state.ltpll;
int clk = 0;
u32 d8, pll_reg_5, pll_reg_3, pll_reg_57, m2div_frac, m2div_int;
u64 temp0, temp1;
@@ -1747,11 +1750,14 @@ intel_lt_phy_calc_hdmi_port_clock(const struct intel_lt_phy_pll_state *lt_state)
* frequency = (m2div * refclk_khz / (d8 * 10))
*/
d8 = (pll_reg_57 & REG_GENMASK(14, 7)) >> 7;
+ if (d8 == 0) {
+ drm_WARN_ON(display->drm,
+ "Invalid port clock using lowest HDMI portclock\n");
+ return xe3plpd_lt_hdmi_252.clock;
+ }
m2div_int = (pll_reg_3 & REG_GENMASK(14, 5)) >> 5;
temp0 = ((u64)m2div_frac * REF_CLK_KHZ) >> 32;
temp1 = (u64)m2div_int * REF_CLK_KHZ;
- if (d8 == 0)
- return 0;
clk = div_u64((temp1 + temp0), d8 * 10);
@@ -1780,7 +1786,7 @@ intel_lt_phy_calc_port_clock(struct intel_encoder *encoder,
lt_state->config[0]);
clk = intel_lt_phy_get_dp_clock(rate);
} else {
- clk = intel_lt_phy_calc_hdmi_port_clock(lt_state);
+ clk = intel_lt_phy_calc_hdmi_port_clock(crtc_state);
}
return clk;
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* ✗ CI.checkpatch: warning for series starting with [v3,1/2] drm/i915/ltphy: Implement HDMI Algo for Pll state
2025-11-10 6:19 [PATCH v3 1/2] drm/i915/ltphy: Implement HDMI Algo for Pll state Suraj Kandpal
2025-11-10 6:19 ` [PATCH v3 2/2] drm/i915/ltphy: Return lowest portclock for HDMI from reverse algorithm Suraj Kandpal
@ 2025-11-10 6:26 ` Patchwork
2025-11-10 6:27 ` ✓ CI.KUnit: success " Patchwork
` (5 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2025-11-10 6:26 UTC (permalink / raw)
To: Suraj Kandpal; +Cc: intel-xe
== Series Details ==
Series: series starting with [v3,1/2] drm/i915/ltphy: Implement HDMI Algo for Pll state
URL : https://patchwork.freedesktop.org/series/157300/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
d9120d4d84745cf011b4b3efb338747e69179dfb
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 7c5750ac60363403b7b1a8258b752f20b3144d0a
Author: Suraj Kandpal <suraj.kandpal@intel.com>
Date: Mon Nov 10 11:49:41 2025 +0530
drm/i915/ltphy: Return lowest portclock for HDMI from reverse algorithm
Return the lowest port clock for HDMI when the reverse algorithm
calculates it to be 0 to avoid errors later but throw a warn.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
+ /mt/dim checkpatch 568f0845675b0c21185a5441e36c017e2bc095b4 drm-intel
2fe8df1b7d3c drm/i915/ltphy: Implement HDMI Algo for Pll state
-:208: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i' - possible side-effects?
#208: FILE: drivers/gpu/drm/i915/display/intel_lt_phy.c:1539:
+#define DATA_ASSIGN(i, pll_reg) \
+ do { \
+ lt_state->data[i][0] = (u8)((((pll_reg).val) & 0xFF000000) >> 24); \
+ lt_state->data[i][1] = (u8)((((pll_reg).val) & 0x00FF0000) >> 16); \
+ lt_state->data[i][2] = (u8)((((pll_reg).val) & 0x0000FF00) >> 8); \
+ lt_state->data[i][3] = (u8)((((pll_reg).val) & 0x000000FF)); \
+ } while (0)
-:208: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pll_reg' - possible side-effects?
#208: FILE: drivers/gpu/drm/i915/display/intel_lt_phy.c:1539:
+#define DATA_ASSIGN(i, pll_reg) \
+ do { \
+ lt_state->data[i][0] = (u8)((((pll_reg).val) & 0xFF000000) >> 24); \
+ lt_state->data[i][1] = (u8)((((pll_reg).val) & 0x00FF0000) >> 16); \
+ lt_state->data[i][2] = (u8)((((pll_reg).val) & 0x0000FF00) >> 8); \
+ lt_state->data[i][3] = (u8)((((pll_reg).val) & 0x000000FF)); \
+ } while (0)
-:215: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i' - possible side-effects?
#215: FILE: drivers/gpu/drm/i915/display/intel_lt_phy.c:1546:
+#define ADDR_ASSIGN(i, pll_reg) \
+ do { \
+ lt_state->addr_msb[i] = ((pll_reg).addr >> 8) & 0xFF; \
+ lt_state->addr_lsb[i] = (pll_reg).addr & 0xFF; \
+ } while (0)
-:215: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pll_reg' - possible side-effects?
#215: FILE: drivers/gpu/drm/i915/display/intel_lt_phy.c:1546:
+#define ADDR_ASSIGN(i, pll_reg) \
+ do { \
+ lt_state->addr_msb[i] = ((pll_reg).addr >> 8) & 0xFF; \
+ lt_state->addr_lsb[i] = (pll_reg).addr & 0xFF; \
+ } while (0)
-:421: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'base' - possible side-effects?
#421: FILE: drivers/gpu/drm/i915/display/intel_lt_phy_regs.h:89:
+#define PLL_REG_ADDR(base, pll_type) ((pll_type) ? (base) + PLL_TYPE_OFFSET : (base))
total: 0 errors, 0 warnings, 5 checks, 395 lines checked
7c5750ac6036 drm/i915/ltphy: Return lowest portclock for HDMI from reverse algorithm
^ permalink raw reply [flat|nested] 10+ messages in thread
* ✓ CI.KUnit: success for series starting with [v3,1/2] drm/i915/ltphy: Implement HDMI Algo for Pll state
2025-11-10 6:19 [PATCH v3 1/2] drm/i915/ltphy: Implement HDMI Algo for Pll state Suraj Kandpal
2025-11-10 6:19 ` [PATCH v3 2/2] drm/i915/ltphy: Return lowest portclock for HDMI from reverse algorithm Suraj Kandpal
2025-11-10 6:26 ` ✗ CI.checkpatch: warning for series starting with [v3,1/2] drm/i915/ltphy: Implement HDMI Algo for Pll state Patchwork
@ 2025-11-10 6:27 ` Patchwork
2025-11-10 6:42 ` ✗ CI.checksparse: warning " Patchwork
` (4 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2025-11-10 6:27 UTC (permalink / raw)
To: Suraj Kandpal; +Cc: intel-xe
== Series Details ==
Series: series starting with [v3,1/2] drm/i915/ltphy: Implement HDMI Algo for Pll state
URL : https://patchwork.freedesktop.org/series/157300/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[06:26:18] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[06:26:23] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[06:26:53] Starting KUnit Kernel (1/1)...
[06:26:53] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[06:26:53] ================== guc_buf (11 subtests) ===================
[06:26:53] [PASSED] test_smallest
[06:26:53] [PASSED] test_largest
[06:26:53] [PASSED] test_granular
[06:26:53] [PASSED] test_unique
[06:26:53] [PASSED] test_overlap
[06:26:53] [PASSED] test_reusable
[06:26:53] [PASSED] test_too_big
[06:26:53] [PASSED] test_flush
[06:26:53] [PASSED] test_lookup
[06:26:53] [PASSED] test_data
[06:26:53] [PASSED] test_class
[06:26:53] ===================== [PASSED] guc_buf =====================
[06:26:53] =================== guc_dbm (7 subtests) ===================
[06:26:53] [PASSED] test_empty
[06:26:53] [PASSED] test_default
[06:26:53] ======================== test_size ========================
[06:26:53] [PASSED] 4
[06:26:53] [PASSED] 8
[06:26:53] [PASSED] 32
[06:26:53] [PASSED] 256
[06:26:53] ==================== [PASSED] test_size ====================
[06:26:53] ======================= test_reuse ========================
[06:26:53] [PASSED] 4
[06:26:53] [PASSED] 8
[06:26:53] [PASSED] 32
[06:26:53] [PASSED] 256
[06:26:53] =================== [PASSED] test_reuse ====================
[06:26:53] =================== test_range_overlap ====================
[06:26:53] [PASSED] 4
[06:26:53] [PASSED] 8
[06:26:53] [PASSED] 32
[06:26:53] [PASSED] 256
[06:26:53] =============== [PASSED] test_range_overlap ================
[06:26:53] =================== test_range_compact ====================
[06:26:53] [PASSED] 4
[06:26:53] [PASSED] 8
[06:26:53] [PASSED] 32
[06:26:53] [PASSED] 256
[06:26:53] =============== [PASSED] test_range_compact ================
[06:26:53] ==================== test_range_spare =====================
[06:26:53] [PASSED] 4
[06:26:53] [PASSED] 8
[06:26:53] [PASSED] 32
[06:26:53] [PASSED] 256
[06:26:53] ================ [PASSED] test_range_spare =================
[06:26:53] ===================== [PASSED] guc_dbm =====================
[06:26:53] =================== guc_idm (6 subtests) ===================
[06:26:53] [PASSED] bad_init
[06:26:53] [PASSED] no_init
[06:26:53] [PASSED] init_fini
[06:26:53] [PASSED] check_used
[06:26:53] [PASSED] check_quota
[06:26:53] [PASSED] check_all
[06:26:53] ===================== [PASSED] guc_idm =====================
[06:26:53] ================== no_relay (3 subtests) ===================
[06:26:53] [PASSED] xe_drops_guc2pf_if_not_ready
[06:26:53] [PASSED] xe_drops_guc2vf_if_not_ready
[06:26:53] [PASSED] xe_rejects_send_if_not_ready
[06:26:53] ==================== [PASSED] no_relay =====================
[06:26:53] ================== pf_relay (14 subtests) ==================
[06:26:53] [PASSED] pf_rejects_guc2pf_too_short
[06:26:53] [PASSED] pf_rejects_guc2pf_too_long
[06:26:53] [PASSED] pf_rejects_guc2pf_no_payload
[06:26:53] [PASSED] pf_fails_no_payload
[06:26:53] [PASSED] pf_fails_bad_origin
[06:26:53] [PASSED] pf_fails_bad_type
[06:26:53] [PASSED] pf_txn_reports_error
[06:26:53] [PASSED] pf_txn_sends_pf2guc
[06:26:53] [PASSED] pf_sends_pf2guc
[06:26:53] [SKIPPED] pf_loopback_nop
[06:26:53] [SKIPPED] pf_loopback_echo
[06:26:53] [SKIPPED] pf_loopback_fail
[06:26:53] [SKIPPED] pf_loopback_busy
[06:26:53] [SKIPPED] pf_loopback_retry
[06:26:53] ==================== [PASSED] pf_relay =====================
[06:26:53] ================== vf_relay (3 subtests) ===================
[06:26:53] [PASSED] vf_rejects_guc2vf_too_short
[06:26:53] [PASSED] vf_rejects_guc2vf_too_long
[06:26:53] [PASSED] vf_rejects_guc2vf_no_payload
[06:26:53] ==================== [PASSED] vf_relay =====================
[06:26:53] ================ pf_gt_config (4 subtests) =================
[06:26:53] [PASSED] fair_contexts_1vf
[06:26:53] [PASSED] fair_doorbells_1vf
[06:26:53] ====================== fair_contexts ======================
[06:26:53] [PASSED] 1 VF
[06:26:53] [PASSED] 2 VFs
[06:26:53] [PASSED] 3 VFs
[06:26:53] [PASSED] 4 VFs
[06:26:53] [PASSED] 5 VFs
[06:26:53] [PASSED] 6 VFs
[06:26:53] [PASSED] 7 VFs
[06:26:53] [PASSED] 8 VFs
[06:26:53] [PASSED] 9 VFs
[06:26:53] [PASSED] 10 VFs
[06:26:53] [PASSED] 11 VFs
[06:26:53] [PASSED] 12 VFs
[06:26:53] [PASSED] 13 VFs
[06:26:53] [PASSED] 14 VFs
[06:26:53] [PASSED] 15 VFs
[06:26:53] [PASSED] 16 VFs
[06:26:53] [PASSED] 17 VFs
[06:26:53] [PASSED] 18 VFs
[06:26:53] [PASSED] 19 VFs
[06:26:53] [PASSED] 20 VFs
[06:26:53] [PASSED] 21 VFs
[06:26:53] [PASSED] 22 VFs
[06:26:53] [PASSED] 23 VFs
[06:26:53] [PASSED] 24 VFs
[06:26:53] [PASSED] 25 VFs
[06:26:53] [PASSED] 26 VFs
[06:26:53] [PASSED] 27 VFs
[06:26:53] [PASSED] 28 VFs
[06:26:53] [PASSED] 29 VFs
[06:26:53] [PASSED] 30 VFs
[06:26:53] [PASSED] 31 VFs
[06:26:53] [PASSED] 32 VFs
[06:26:53] [PASSED] 33 VFs
[06:26:53] [PASSED] 34 VFs
[06:26:53] [PASSED] 35 VFs
[06:26:53] [PASSED] 36 VFs
[06:26:53] [PASSED] 37 VFs
[06:26:53] [PASSED] 38 VFs
[06:26:53] [PASSED] 39 VFs
[06:26:53] [PASSED] 40 VFs
[06:26:53] [PASSED] 41 VFs
[06:26:53] [PASSED] 42 VFs
[06:26:53] [PASSED] 43 VFs
[06:26:53] [PASSED] 44 VFs
[06:26:53] [PASSED] 45 VFs
[06:26:53] [PASSED] 46 VFs
[06:26:53] [PASSED] 47 VFs
[06:26:53] [PASSED] 48 VFs
[06:26:53] [PASSED] 49 VFs
[06:26:53] [PASSED] 50 VFs
[06:26:53] [PASSED] 51 VFs
[06:26:53] [PASSED] 52 VFs
[06:26:53] [PASSED] 53 VFs
[06:26:53] [PASSED] 54 VFs
[06:26:53] [PASSED] 55 VFs
[06:26:53] [PASSED] 56 VFs
[06:26:53] [PASSED] 57 VFs
[06:26:53] [PASSED] 58 VFs
[06:26:53] [PASSED] 59 VFs
[06:26:53] [PASSED] 60 VFs
[06:26:53] [PASSED] 61 VFs
[06:26:53] [PASSED] 62 VFs
[06:26:53] [PASSED] 63 VFs
[06:26:53] ================== [PASSED] fair_contexts ==================
[06:26:53] ===================== fair_doorbells ======================
[06:26:53] [PASSED] 1 VF
[06:26:53] [PASSED] 2 VFs
[06:26:53] [PASSED] 3 VFs
[06:26:53] [PASSED] 4 VFs
[06:26:53] [PASSED] 5 VFs
[06:26:53] [PASSED] 6 VFs
[06:26:53] [PASSED] 7 VFs
[06:26:53] [PASSED] 8 VFs
[06:26:53] [PASSED] 9 VFs
[06:26:53] [PASSED] 10 VFs
[06:26:53] [PASSED] 11 VFs
[06:26:53] [PASSED] 12 VFs
[06:26:53] [PASSED] 13 VFs
[06:26:53] [PASSED] 14 VFs
[06:26:53] [PASSED] 15 VFs
[06:26:53] [PASSED] 16 VFs
[06:26:53] [PASSED] 17 VFs
[06:26:53] [PASSED] 18 VFs
[06:26:53] [PASSED] 19 VFs
[06:26:53] [PASSED] 20 VFs
[06:26:53] [PASSED] 21 VFs
[06:26:53] [PASSED] 22 VFs
[06:26:53] [PASSED] 23 VFs
[06:26:53] [PASSED] 24 VFs
[06:26:53] [PASSED] 25 VFs
[06:26:53] [PASSED] 26 VFs
[06:26:53] [PASSED] 27 VFs
[06:26:53] [PASSED] 28 VFs
[06:26:53] [PASSED] 29 VFs
[06:26:53] [PASSED] 30 VFs
[06:26:53] [PASSED] 31 VFs
[06:26:53] [PASSED] 32 VFs
[06:26:53] [PASSED] 33 VFs
[06:26:53] [PASSED] 34 VFs
[06:26:53] [PASSED] 35 VFs
[06:26:53] [PASSED] 36 VFs
[06:26:53] [PASSED] 37 VFs
[06:26:53] [PASSED] 38 VFs
[06:26:53] [PASSED] 39 VFs
[06:26:53] [PASSED] 40 VFs
[06:26:53] [PASSED] 41 VFs
[06:26:53] [PASSED] 42 VFs
[06:26:53] [PASSED] 43 VFs
[06:26:53] [PASSED] 44 VFs
[06:26:53] [PASSED] 45 VFs
[06:26:53] [PASSED] 46 VFs
[06:26:53] [PASSED] 47 VFs
[06:26:53] [PASSED] 48 VFs
[06:26:53] [PASSED] 49 VFs
[06:26:53] [PASSED] 50 VFs
[06:26:53] [PASSED] 51 VFs
[06:26:53] [PASSED] 52 VFs
[06:26:53] [PASSED] 53 VFs
[06:26:53] [PASSED] 54 VFs
[06:26:53] [PASSED] 55 VFs
[06:26:53] [PASSED] 56 VFs
[06:26:53] [PASSED] 57 VFs
[06:26:53] [PASSED] 58 VFs
[06:26:53] [PASSED] 59 VFs
[06:26:53] [PASSED] 60 VFs
[06:26:53] [PASSED] 61 VFs
[06:26:53] [PASSED] 62 VFs
[06:26:53] [PASSED] 63 VFs
[06:26:53] ================= [PASSED] fair_doorbells ==================
[06:26:53] ================== [PASSED] pf_gt_config ===================
[06:26:53] ===================== lmtt (1 subtest) =====================
[06:26:53] ======================== test_ops =========================
[06:26:53] [PASSED] 2-level
[06:26:53] [PASSED] multi-level
[06:26:53] ==================== [PASSED] test_ops =====================
[06:26:53] ====================== [PASSED] lmtt =======================
[06:26:53] ================= pf_service (11 subtests) =================
[06:26:53] [PASSED] pf_negotiate_any
[06:26:53] [PASSED] pf_negotiate_base_match
[06:26:53] [PASSED] pf_negotiate_base_newer
[06:26:53] [PASSED] pf_negotiate_base_next
[06:26:53] [SKIPPED] pf_negotiate_base_older
[06:26:53] [PASSED] pf_negotiate_base_prev
[06:26:53] [PASSED] pf_negotiate_latest_match
[06:26:53] [PASSED] pf_negotiate_latest_newer
[06:26:53] [PASSED] pf_negotiate_latest_next
[06:26:53] [SKIPPED] pf_negotiate_latest_older
[06:26:53] [SKIPPED] pf_negotiate_latest_prev
[06:26:53] =================== [PASSED] pf_service ====================
[06:26:53] ================= xe_guc_g2g (2 subtests) ==================
[06:26:53] ============== xe_live_guc_g2g_kunit_default ==============
[06:26:53] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[06:26:53] ============== xe_live_guc_g2g_kunit_allmem ===============
[06:26:53] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[06:26:53] =================== [SKIPPED] xe_guc_g2g ===================
[06:26:53] =================== xe_mocs (2 subtests) ===================
[06:26:53] ================ xe_live_mocs_kernel_kunit ================
[06:26:53] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[06:26:53] ================ xe_live_mocs_reset_kunit =================
[06:26:53] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[06:26:53] ==================== [SKIPPED] xe_mocs =====================
[06:26:53] ================= xe_migrate (2 subtests) ==================
[06:26:53] ================= xe_migrate_sanity_kunit =================
[06:26:53] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[06:26:53] ================== xe_validate_ccs_kunit ==================
[06:26:53] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[06:26:53] =================== [SKIPPED] xe_migrate ===================
[06:26:53] ================== xe_dma_buf (1 subtest) ==================
[06:26:53] ==================== xe_dma_buf_kunit =====================
[06:26:53] ================ [SKIPPED] xe_dma_buf_kunit ================
[06:26:53] =================== [SKIPPED] xe_dma_buf ===================
[06:26:53] ================= xe_bo_shrink (1 subtest) =================
[06:26:53] =================== xe_bo_shrink_kunit ====================
[06:26:53] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[06:26:53] ================== [SKIPPED] xe_bo_shrink ==================
[06:26:53] ==================== xe_bo (2 subtests) ====================
[06:26:53] ================== xe_ccs_migrate_kunit ===================
[06:26:53] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[06:26:53] ==================== xe_bo_evict_kunit ====================
[06:26:53] =============== [SKIPPED] xe_bo_evict_kunit ================
[06:26:53] ===================== [SKIPPED] xe_bo ======================
[06:26:53] ==================== args (11 subtests) ====================
[06:26:53] [PASSED] count_args_test
[06:26:53] [PASSED] call_args_example
[06:26:53] [PASSED] call_args_test
[06:26:53] [PASSED] drop_first_arg_example
[06:26:53] [PASSED] drop_first_arg_test
[06:26:53] [PASSED] first_arg_example
[06:26:53] [PASSED] first_arg_test
[06:26:53] [PASSED] last_arg_example
[06:26:53] [PASSED] last_arg_test
[06:26:53] [PASSED] pick_arg_example
[06:26:53] [PASSED] sep_comma_example
[06:26:53] ====================== [PASSED] args =======================
[06:26:53] =================== xe_pci (3 subtests) ====================
[06:26:53] ==================== check_graphics_ip ====================
[06:26:53] [PASSED] 12.00 Xe_LP
[06:26:53] [PASSED] 12.10 Xe_LP+
[06:26:53] [PASSED] 12.55 Xe_HPG
[06:26:53] [PASSED] 12.60 Xe_HPC
[06:26:53] [PASSED] 12.70 Xe_LPG
[06:26:53] [PASSED] 12.71 Xe_LPG
[06:26:53] [PASSED] 12.74 Xe_LPG+
[06:26:53] [PASSED] 20.01 Xe2_HPG
[06:26:53] [PASSED] 20.02 Xe2_HPG
[06:26:53] [PASSED] 20.04 Xe2_LPG
[06:26:53] [PASSED] 30.00 Xe3_LPG
[06:26:53] [PASSED] 30.01 Xe3_LPG
[06:26:53] [PASSED] 30.03 Xe3_LPG
[06:26:53] [PASSED] 30.04 Xe3_LPG
[06:26:53] [PASSED] 30.05 Xe3_LPG
[06:26:53] [PASSED] 35.11 Xe3p_XPC
[06:26:53] ================ [PASSED] check_graphics_ip ================
[06:26:53] ===================== check_media_ip ======================
[06:26:53] [PASSED] 12.00 Xe_M
[06:26:53] [PASSED] 12.55 Xe_HPM
[06:26:53] [PASSED] 13.00 Xe_LPM+
[06:26:53] [PASSED] 13.01 Xe2_HPM
[06:26:53] [PASSED] 20.00 Xe2_LPM
[06:26:53] [PASSED] 30.00 Xe3_LPM
[06:26:53] [PASSED] 30.02 Xe3_LPM
[06:26:53] [PASSED] 35.00 Xe3p_LPM
[06:26:53] [PASSED] 35.03 Xe3p_HPM
[06:26:53] ================= [PASSED] check_media_ip ==================
[06:26:53] =================== check_platform_desc ===================
[06:26:53] [PASSED] 0x9A60 (TIGERLAKE)
[06:26:53] [PASSED] 0x9A68 (TIGERLAKE)
[06:26:53] [PASSED] 0x9A70 (TIGERLAKE)
[06:26:53] [PASSED] 0x9A40 (TIGERLAKE)
[06:26:53] [PASSED] 0x9A49 (TIGERLAKE)
[06:26:53] [PASSED] 0x9A59 (TIGERLAKE)
[06:26:53] [PASSED] 0x9A78 (TIGERLAKE)
[06:26:53] [PASSED] 0x9AC0 (TIGERLAKE)
[06:26:53] [PASSED] 0x9AC9 (TIGERLAKE)
[06:26:53] [PASSED] 0x9AD9 (TIGERLAKE)
[06:26:53] [PASSED] 0x9AF8 (TIGERLAKE)
[06:26:53] [PASSED] 0x4C80 (ROCKETLAKE)
[06:26:53] [PASSED] 0x4C8A (ROCKETLAKE)
[06:26:53] [PASSED] 0x4C8B (ROCKETLAKE)
[06:26:53] [PASSED] 0x4C8C (ROCKETLAKE)
[06:26:53] [PASSED] 0x4C90 (ROCKETLAKE)
[06:26:53] [PASSED] 0x4C9A (ROCKETLAKE)
[06:26:53] [PASSED] 0x4680 (ALDERLAKE_S)
[06:26:53] [PASSED] 0x4682 (ALDERLAKE_S)
[06:26:53] [PASSED] 0x4688 (ALDERLAKE_S)
[06:26:53] [PASSED] 0x468A (ALDERLAKE_S)
[06:26:53] [PASSED] 0x468B (ALDERLAKE_S)
[06:26:53] [PASSED] 0x4690 (ALDERLAKE_S)
[06:26:53] [PASSED] 0x4692 (ALDERLAKE_S)
[06:26:53] [PASSED] 0x4693 (ALDERLAKE_S)
[06:26:53] [PASSED] 0x46A0 (ALDERLAKE_P)
[06:26:53] [PASSED] 0x46A1 (ALDERLAKE_P)
[06:26:53] [PASSED] 0x46A2 (ALDERLAKE_P)
[06:26:53] [PASSED] 0x46A3 (ALDERLAKE_P)
[06:26:53] [PASSED] 0x46A6 (ALDERLAKE_P)
[06:26:53] [PASSED] 0x46A8 (ALDERLAKE_P)
[06:26:53] [PASSED] 0x46AA (ALDERLAKE_P)
[06:26:53] [PASSED] 0x462A (ALDERLAKE_P)
[06:26:53] [PASSED] 0x4626 (ALDERLAKE_P)
[06:26:53] [PASSED] 0x4628 (ALDERLAKE_P)
[06:26:53] [PASSED] 0x46B0 (ALDERLAKE_P)
[06:26:53] [PASSED] 0x46B1 (ALDERLAKE_P)
[06:26:53] [PASSED] 0x46B2 (ALDERLAKE_P)
[06:26:53] [PASSED] 0x46B3 (ALDERLAKE_P)
[06:26:53] [PASSED] 0x46C0 (ALDERLAKE_P)
[06:26:53] [PASSED] 0x46C1 (ALDERLAKE_P)
[06:26:53] [PASSED] 0x46C2 (ALDERLAKE_P)
[06:26:53] [PASSED] 0x46C3 (ALDERLAKE_P)
[06:26:53] [PASSED] 0x46D0 (ALDERLAKE_N)
[06:26:53] [PASSED] 0x46D1 (ALDERLAKE_N)
[06:26:53] [PASSED] 0x46D2 (ALDERLAKE_N)
[06:26:53] [PASSED] 0x46D3 (ALDERLAKE_N)
[06:26:53] [PASSED] 0x46D4 (ALDERLAKE_N)
[06:26:53] [PASSED] 0xA721 (ALDERLAKE_P)
[06:26:53] [PASSED] 0xA7A1 (ALDERLAKE_P)
[06:26:53] [PASSED] 0xA7A9 (ALDERLAKE_P)
[06:26:53] [PASSED] 0xA7AC (ALDERLAKE_P)
[06:26:53] [PASSED] 0xA7AD (ALDERLAKE_P)
[06:26:53] [PASSED] 0xA720 (ALDERLAKE_P)
[06:26:53] [PASSED] 0xA7A0 (ALDERLAKE_P)
[06:26:53] [PASSED] 0xA7A8 (ALDERLAKE_P)
[06:26:53] [PASSED] 0xA7AA (ALDERLAKE_P)
[06:26:53] [PASSED] 0xA7AB (ALDERLAKE_P)
[06:26:53] [PASSED] 0xA780 (ALDERLAKE_S)
[06:26:53] [PASSED] 0xA781 (ALDERLAKE_S)
[06:26:53] [PASSED] 0xA782 (ALDERLAKE_S)
[06:26:53] [PASSED] 0xA783 (ALDERLAKE_S)
[06:26:53] [PASSED] 0xA788 (ALDERLAKE_S)
[06:26:53] [PASSED] 0xA789 (ALDERLAKE_S)
[06:26:53] [PASSED] 0xA78A (ALDERLAKE_S)
[06:26:53] [PASSED] 0xA78B (ALDERLAKE_S)
[06:26:53] [PASSED] 0x4905 (DG1)
[06:26:53] [PASSED] 0x4906 (DG1)
[06:26:53] [PASSED] 0x4907 (DG1)
[06:26:53] [PASSED] 0x4908 (DG1)
[06:26:53] [PASSED] 0x4909 (DG1)
[06:26:53] [PASSED] 0x56C0 (DG2)
[06:26:53] [PASSED] 0x56C2 (DG2)
[06:26:53] [PASSED] 0x56C1 (DG2)
[06:26:53] [PASSED] 0x7D51 (METEORLAKE)
[06:26:53] [PASSED] 0x7DD1 (METEORLAKE)
[06:26:53] [PASSED] 0x7D41 (METEORLAKE)
[06:26:53] [PASSED] 0x7D67 (METEORLAKE)
[06:26:53] [PASSED] 0xB640 (METEORLAKE)
[06:26:53] [PASSED] 0x56A0 (DG2)
[06:26:53] [PASSED] 0x56A1 (DG2)
[06:26:53] [PASSED] 0x56A2 (DG2)
[06:26:53] [PASSED] 0x56BE (DG2)
[06:26:53] [PASSED] 0x56BF (DG2)
[06:26:53] [PASSED] 0x5690 (DG2)
stty: 'standard input': Inappropriate ioctl for device
[06:26:53] [PASSED] 0x5691 (DG2)
[06:26:53] [PASSED] 0x5692 (DG2)
[06:26:53] [PASSED] 0x56A5 (DG2)
[06:26:53] [PASSED] 0x56A6 (DG2)
[06:26:53] [PASSED] 0x56B0 (DG2)
[06:26:53] [PASSED] 0x56B1 (DG2)
[06:26:53] [PASSED] 0x56BA (DG2)
[06:26:53] [PASSED] 0x56BB (DG2)
[06:26:53] [PASSED] 0x56BC (DG2)
[06:26:53] [PASSED] 0x56BD (DG2)
[06:26:53] [PASSED] 0x5693 (DG2)
[06:26:53] [PASSED] 0x5694 (DG2)
[06:26:53] [PASSED] 0x5695 (DG2)
[06:26:53] [PASSED] 0x56A3 (DG2)
[06:26:53] [PASSED] 0x56A4 (DG2)
[06:26:53] [PASSED] 0x56B2 (DG2)
[06:26:53] [PASSED] 0x56B3 (DG2)
[06:26:53] [PASSED] 0x5696 (DG2)
[06:26:53] [PASSED] 0x5697 (DG2)
[06:26:53] [PASSED] 0xB69 (PVC)
[06:26:53] [PASSED] 0xB6E (PVC)
[06:26:53] [PASSED] 0xBD4 (PVC)
[06:26:53] [PASSED] 0xBD5 (PVC)
[06:26:53] [PASSED] 0xBD6 (PVC)
[06:26:53] [PASSED] 0xBD7 (PVC)
[06:26:53] [PASSED] 0xBD8 (PVC)
[06:26:53] [PASSED] 0xBD9 (PVC)
[06:26:53] [PASSED] 0xBDA (PVC)
[06:26:53] [PASSED] 0xBDB (PVC)
[06:26:53] [PASSED] 0xBE0 (PVC)
[06:26:53] [PASSED] 0xBE1 (PVC)
[06:26:53] [PASSED] 0xBE5 (PVC)
[06:26:53] [PASSED] 0x7D40 (METEORLAKE)
[06:26:53] [PASSED] 0x7D45 (METEORLAKE)
[06:26:53] [PASSED] 0x7D55 (METEORLAKE)
[06:26:53] [PASSED] 0x7D60 (METEORLAKE)
[06:26:53] [PASSED] 0x7DD5 (METEORLAKE)
[06:26:53] [PASSED] 0x6420 (LUNARLAKE)
[06:26:53] [PASSED] 0x64A0 (LUNARLAKE)
[06:26:53] [PASSED] 0x64B0 (LUNARLAKE)
[06:26:53] [PASSED] 0xE202 (BATTLEMAGE)
[06:26:53] [PASSED] 0xE209 (BATTLEMAGE)
[06:26:53] [PASSED] 0xE20B (BATTLEMAGE)
[06:26:53] [PASSED] 0xE20C (BATTLEMAGE)
[06:26:53] [PASSED] 0xE20D (BATTLEMAGE)
[06:26:53] [PASSED] 0xE210 (BATTLEMAGE)
[06:26:53] [PASSED] 0xE211 (BATTLEMAGE)
[06:26:53] [PASSED] 0xE212 (BATTLEMAGE)
[06:26:53] [PASSED] 0xE216 (BATTLEMAGE)
[06:26:53] [PASSED] 0xE220 (BATTLEMAGE)
[06:26:53] [PASSED] 0xE221 (BATTLEMAGE)
[06:26:53] [PASSED] 0xE222 (BATTLEMAGE)
[06:26:53] [PASSED] 0xE223 (BATTLEMAGE)
[06:26:53] [PASSED] 0xB080 (PANTHERLAKE)
[06:26:53] [PASSED] 0xB081 (PANTHERLAKE)
[06:26:53] [PASSED] 0xB082 (PANTHERLAKE)
[06:26:53] [PASSED] 0xB083 (PANTHERLAKE)
[06:26:53] [PASSED] 0xB084 (PANTHERLAKE)
[06:26:53] [PASSED] 0xB085 (PANTHERLAKE)
[06:26:53] [PASSED] 0xB086 (PANTHERLAKE)
[06:26:53] [PASSED] 0xB087 (PANTHERLAKE)
[06:26:53] [PASSED] 0xB08F (PANTHERLAKE)
[06:26:53] [PASSED] 0xB090 (PANTHERLAKE)
[06:26:53] [PASSED] 0xB0A0 (PANTHERLAKE)
[06:26:53] [PASSED] 0xB0B0 (PANTHERLAKE)
[06:26:53] [PASSED] 0xD740 (NOVALAKE_S)
[06:26:53] [PASSED] 0xD741 (NOVALAKE_S)
[06:26:53] [PASSED] 0xD742 (NOVALAKE_S)
[06:26:53] [PASSED] 0xD743 (NOVALAKE_S)
[06:26:53] [PASSED] 0xD744 (NOVALAKE_S)
[06:26:53] [PASSED] 0xD745 (NOVALAKE_S)
[06:26:53] [PASSED] 0x674C (CRESCENTISLAND)
[06:26:53] [PASSED] 0xFD80 (PANTHERLAKE)
[06:26:53] [PASSED] 0xFD81 (PANTHERLAKE)
[06:26:53] =============== [PASSED] check_platform_desc ===============
[06:26:53] ===================== [PASSED] xe_pci ======================
[06:26:53] =================== xe_rtp (2 subtests) ====================
[06:26:53] =============== xe_rtp_process_to_sr_tests ================
[06:26:53] [PASSED] coalesce-same-reg
[06:26:53] [PASSED] no-match-no-add
[06:26:53] [PASSED] match-or
[06:26:53] [PASSED] match-or-xfail
[06:26:53] [PASSED] no-match-no-add-multiple-rules
[06:26:53] [PASSED] two-regs-two-entries
[06:26:53] [PASSED] clr-one-set-other
[06:26:53] [PASSED] set-field
[06:26:53] [PASSED] conflict-duplicate
[06:26:53] [PASSED] conflict-not-disjoint
[06:26:53] [PASSED] conflict-reg-type
[06:26:53] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[06:26:53] ================== xe_rtp_process_tests ===================
[06:26:53] [PASSED] active1
[06:26:53] [PASSED] active2
[06:26:53] [PASSED] active-inactive
[06:26:53] [PASSED] inactive-active
[06:26:53] [PASSED] inactive-1st_or_active-inactive
[06:26:53] [PASSED] inactive-2nd_or_active-inactive
[06:26:53] [PASSED] inactive-last_or_active-inactive
[06:26:53] [PASSED] inactive-no_or_active-inactive
[06:26:53] ============== [PASSED] xe_rtp_process_tests ===============
[06:26:53] ===================== [PASSED] xe_rtp ======================
[06:26:53] ==================== xe_wa (1 subtest) =====================
[06:26:53] ======================== xe_wa_gt =========================
[06:26:53] [PASSED] TIGERLAKE B0
[06:26:53] [PASSED] DG1 A0
[06:26:53] [PASSED] DG1 B0
[06:26:53] [PASSED] ALDERLAKE_S A0
[06:26:53] [PASSED] ALDERLAKE_S B0
[06:26:53] [PASSED] ALDERLAKE_S C0
[06:26:53] [PASSED] ALDERLAKE_S D0
[06:26:53] [PASSED] ALDERLAKE_P A0
[06:26:53] [PASSED] ALDERLAKE_P B0
[06:26:53] [PASSED] ALDERLAKE_P C0
[06:26:53] [PASSED] ALDERLAKE_S RPLS D0
[06:26:53] [PASSED] ALDERLAKE_P RPLU E0
[06:26:53] [PASSED] DG2 G10 C0
[06:26:53] [PASSED] DG2 G11 B1
[06:26:53] [PASSED] DG2 G12 A1
[06:26:53] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[06:26:53] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[06:26:53] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[06:26:53] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[06:26:53] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[06:26:53] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[06:26:53] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[06:26:53] ==================== [PASSED] xe_wa_gt =====================
[06:26:53] ====================== [PASSED] xe_wa ======================
[06:26:53] ============================================================
[06:26:53] Testing complete. Ran 446 tests: passed: 428, skipped: 18
[06:26:53] Elapsed time: 35.168s total, 4.222s configuring, 30.480s building, 0.430s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[06:26:54] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[06:26:55] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[06:27:20] Starting KUnit Kernel (1/1)...
[06:27:20] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[06:27:21] ============ drm_test_pick_cmdline (2 subtests) ============
[06:27:21] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[06:27:21] =============== drm_test_pick_cmdline_named ===============
[06:27:21] [PASSED] NTSC
[06:27:21] [PASSED] NTSC-J
[06:27:21] [PASSED] PAL
[06:27:21] [PASSED] PAL-M
[06:27:21] =========== [PASSED] drm_test_pick_cmdline_named ===========
[06:27:21] ============== [PASSED] drm_test_pick_cmdline ==============
[06:27:21] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[06:27:21] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[06:27:21] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[06:27:21] =========== drm_validate_clone_mode (2 subtests) ===========
[06:27:21] ============== drm_test_check_in_clone_mode ===============
[06:27:21] [PASSED] in_clone_mode
[06:27:21] [PASSED] not_in_clone_mode
[06:27:21] ========== [PASSED] drm_test_check_in_clone_mode ===========
[06:27:21] =============== drm_test_check_valid_clones ===============
[06:27:21] [PASSED] not_in_clone_mode
[06:27:21] [PASSED] valid_clone
[06:27:21] [PASSED] invalid_clone
[06:27:21] =========== [PASSED] drm_test_check_valid_clones ===========
[06:27:21] ============= [PASSED] drm_validate_clone_mode =============
[06:27:21] ============= drm_validate_modeset (1 subtest) =============
[06:27:21] [PASSED] drm_test_check_connector_changed_modeset
[06:27:21] ============== [PASSED] drm_validate_modeset ===============
[06:27:21] ====== drm_test_bridge_get_current_state (2 subtests) ======
[06:27:21] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[06:27:21] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[06:27:21] ======== [PASSED] drm_test_bridge_get_current_state ========
[06:27:21] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[06:27:21] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[06:27:21] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[06:27:21] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[06:27:21] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[06:27:21] ============== drm_bridge_alloc (2 subtests) ===============
[06:27:21] [PASSED] drm_test_drm_bridge_alloc_basic
[06:27:21] [PASSED] drm_test_drm_bridge_alloc_get_put
[06:27:21] ================ [PASSED] drm_bridge_alloc =================
[06:27:21] ================== drm_buddy (8 subtests) ==================
[06:27:21] [PASSED] drm_test_buddy_alloc_limit
[06:27:21] [PASSED] drm_test_buddy_alloc_optimistic
[06:27:21] [PASSED] drm_test_buddy_alloc_pessimistic
[06:27:21] [PASSED] drm_test_buddy_alloc_pathological
[06:27:21] [PASSED] drm_test_buddy_alloc_contiguous
[06:27:21] [PASSED] drm_test_buddy_alloc_clear
[06:27:21] [PASSED] drm_test_buddy_alloc_range_bias
[06:27:21] [PASSED] drm_test_buddy_fragmentation_performance
[06:27:21] ==================== [PASSED] drm_buddy ====================
[06:27:21] ============= drm_cmdline_parser (40 subtests) =============
[06:27:21] [PASSED] drm_test_cmdline_force_d_only
[06:27:21] [PASSED] drm_test_cmdline_force_D_only_dvi
[06:27:21] [PASSED] drm_test_cmdline_force_D_only_hdmi
[06:27:21] [PASSED] drm_test_cmdline_force_D_only_not_digital
[06:27:21] [PASSED] drm_test_cmdline_force_e_only
[06:27:21] [PASSED] drm_test_cmdline_res
[06:27:21] [PASSED] drm_test_cmdline_res_vesa
[06:27:21] [PASSED] drm_test_cmdline_res_vesa_rblank
[06:27:21] [PASSED] drm_test_cmdline_res_rblank
[06:27:21] [PASSED] drm_test_cmdline_res_bpp
[06:27:21] [PASSED] drm_test_cmdline_res_refresh
[06:27:21] [PASSED] drm_test_cmdline_res_bpp_refresh
[06:27:21] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[06:27:21] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[06:27:21] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[06:27:21] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[06:27:21] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[06:27:21] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[06:27:21] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[06:27:21] [PASSED] drm_test_cmdline_res_margins_force_on
[06:27:21] [PASSED] drm_test_cmdline_res_vesa_margins
[06:27:21] [PASSED] drm_test_cmdline_name
[06:27:21] [PASSED] drm_test_cmdline_name_bpp
[06:27:21] [PASSED] drm_test_cmdline_name_option
[06:27:21] [PASSED] drm_test_cmdline_name_bpp_option
[06:27:21] [PASSED] drm_test_cmdline_rotate_0
[06:27:21] [PASSED] drm_test_cmdline_rotate_90
[06:27:21] [PASSED] drm_test_cmdline_rotate_180
[06:27:21] [PASSED] drm_test_cmdline_rotate_270
[06:27:21] [PASSED] drm_test_cmdline_hmirror
[06:27:21] [PASSED] drm_test_cmdline_vmirror
[06:27:21] [PASSED] drm_test_cmdline_margin_options
[06:27:21] [PASSED] drm_test_cmdline_multiple_options
[06:27:21] [PASSED] drm_test_cmdline_bpp_extra_and_option
[06:27:21] [PASSED] drm_test_cmdline_extra_and_option
[06:27:21] [PASSED] drm_test_cmdline_freestanding_options
[06:27:21] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[06:27:21] [PASSED] drm_test_cmdline_panel_orientation
[06:27:21] ================ drm_test_cmdline_invalid =================
[06:27:21] [PASSED] margin_only
[06:27:21] [PASSED] interlace_only
[06:27:21] [PASSED] res_missing_x
[06:27:21] [PASSED] res_missing_y
[06:27:21] [PASSED] res_bad_y
[06:27:21] [PASSED] res_missing_y_bpp
[06:27:21] [PASSED] res_bad_bpp
[06:27:21] [PASSED] res_bad_refresh
[06:27:21] [PASSED] res_bpp_refresh_force_on_off
[06:27:21] [PASSED] res_invalid_mode
[06:27:21] [PASSED] res_bpp_wrong_place_mode
[06:27:21] [PASSED] name_bpp_refresh
[06:27:21] [PASSED] name_refresh
[06:27:21] [PASSED] name_refresh_wrong_mode
[06:27:21] [PASSED] name_refresh_invalid_mode
[06:27:21] [PASSED] rotate_multiple
[06:27:21] [PASSED] rotate_invalid_val
[06:27:21] [PASSED] rotate_truncated
[06:27:21] [PASSED] invalid_option
[06:27:21] [PASSED] invalid_tv_option
[06:27:21] [PASSED] truncated_tv_option
[06:27:21] ============ [PASSED] drm_test_cmdline_invalid =============
[06:27:21] =============== drm_test_cmdline_tv_options ===============
[06:27:21] [PASSED] NTSC
[06:27:21] [PASSED] NTSC_443
[06:27:21] [PASSED] NTSC_J
[06:27:21] [PASSED] PAL
[06:27:21] [PASSED] PAL_M
[06:27:21] [PASSED] PAL_N
[06:27:21] [PASSED] SECAM
[06:27:21] [PASSED] MONO_525
[06:27:21] [PASSED] MONO_625
[06:27:21] =========== [PASSED] drm_test_cmdline_tv_options ===========
[06:27:21] =============== [PASSED] drm_cmdline_parser ================
[06:27:21] ========== drmm_connector_hdmi_init (20 subtests) ==========
[06:27:21] [PASSED] drm_test_connector_hdmi_init_valid
[06:27:21] [PASSED] drm_test_connector_hdmi_init_bpc_8
[06:27:21] [PASSED] drm_test_connector_hdmi_init_bpc_10
[06:27:21] [PASSED] drm_test_connector_hdmi_init_bpc_12
[06:27:21] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[06:27:21] [PASSED] drm_test_connector_hdmi_init_bpc_null
[06:27:21] [PASSED] drm_test_connector_hdmi_init_formats_empty
[06:27:21] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[06:27:21] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[06:27:21] [PASSED] supported_formats=0x9 yuv420_allowed=1
[06:27:21] [PASSED] supported_formats=0x9 yuv420_allowed=0
[06:27:21] [PASSED] supported_formats=0x3 yuv420_allowed=1
[06:27:21] [PASSED] supported_formats=0x3 yuv420_allowed=0
[06:27:21] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[06:27:21] [PASSED] drm_test_connector_hdmi_init_null_ddc
[06:27:21] [PASSED] drm_test_connector_hdmi_init_null_product
[06:27:21] [PASSED] drm_test_connector_hdmi_init_null_vendor
[06:27:21] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[06:27:21] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[06:27:21] [PASSED] drm_test_connector_hdmi_init_product_valid
[06:27:21] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[06:27:21] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[06:27:21] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[06:27:21] ========= drm_test_connector_hdmi_init_type_valid =========
[06:27:21] [PASSED] HDMI-A
[06:27:21] [PASSED] HDMI-B
[06:27:21] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[06:27:21] ======== drm_test_connector_hdmi_init_type_invalid ========
[06:27:21] [PASSED] Unknown
[06:27:21] [PASSED] VGA
[06:27:21] [PASSED] DVI-I
[06:27:21] [PASSED] DVI-D
[06:27:21] [PASSED] DVI-A
[06:27:21] [PASSED] Composite
[06:27:21] [PASSED] SVIDEO
[06:27:21] [PASSED] LVDS
[06:27:21] [PASSED] Component
[06:27:21] [PASSED] DIN
[06:27:21] [PASSED] DP
[06:27:21] [PASSED] TV
[06:27:21] [PASSED] eDP
[06:27:21] [PASSED] Virtual
[06:27:21] [PASSED] DSI
[06:27:21] [PASSED] DPI
[06:27:21] [PASSED] Writeback
[06:27:21] [PASSED] SPI
[06:27:21] [PASSED] USB
[06:27:21] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[06:27:21] ============ [PASSED] drmm_connector_hdmi_init =============
[06:27:21] ============= drmm_connector_init (3 subtests) =============
[06:27:21] [PASSED] drm_test_drmm_connector_init
[06:27:21] [PASSED] drm_test_drmm_connector_init_null_ddc
[06:27:21] ========= drm_test_drmm_connector_init_type_valid =========
[06:27:21] [PASSED] Unknown
[06:27:21] [PASSED] VGA
[06:27:21] [PASSED] DVI-I
[06:27:21] [PASSED] DVI-D
[06:27:21] [PASSED] DVI-A
[06:27:21] [PASSED] Composite
[06:27:21] [PASSED] SVIDEO
[06:27:21] [PASSED] LVDS
[06:27:21] [PASSED] Component
[06:27:21] [PASSED] DIN
[06:27:21] [PASSED] DP
[06:27:21] [PASSED] HDMI-A
[06:27:21] [PASSED] HDMI-B
[06:27:21] [PASSED] TV
[06:27:21] [PASSED] eDP
[06:27:21] [PASSED] Virtual
[06:27:21] [PASSED] DSI
[06:27:21] [PASSED] DPI
[06:27:21] [PASSED] Writeback
[06:27:21] [PASSED] SPI
[06:27:21] [PASSED] USB
[06:27:21] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[06:27:21] =============== [PASSED] drmm_connector_init ===============
[06:27:21] ========= drm_connector_dynamic_init (6 subtests) ==========
[06:27:21] [PASSED] drm_test_drm_connector_dynamic_init
[06:27:21] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[06:27:21] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[06:27:21] [PASSED] drm_test_drm_connector_dynamic_init_properties
[06:27:21] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[06:27:21] [PASSED] Unknown
[06:27:21] [PASSED] VGA
[06:27:21] [PASSED] DVI-I
[06:27:21] [PASSED] DVI-D
[06:27:21] [PASSED] DVI-A
[06:27:21] [PASSED] Composite
[06:27:21] [PASSED] SVIDEO
[06:27:21] [PASSED] LVDS
[06:27:21] [PASSED] Component
[06:27:21] [PASSED] DIN
[06:27:21] [PASSED] DP
[06:27:21] [PASSED] HDMI-A
[06:27:21] [PASSED] HDMI-B
[06:27:21] [PASSED] TV
[06:27:21] [PASSED] eDP
[06:27:21] [PASSED] Virtual
[06:27:21] [PASSED] DSI
[06:27:21] [PASSED] DPI
[06:27:21] [PASSED] Writeback
[06:27:21] [PASSED] SPI
[06:27:21] [PASSED] USB
[06:27:21] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[06:27:21] ======== drm_test_drm_connector_dynamic_init_name =========
[06:27:21] [PASSED] Unknown
[06:27:21] [PASSED] VGA
[06:27:21] [PASSED] DVI-I
[06:27:21] [PASSED] DVI-D
[06:27:21] [PASSED] DVI-A
[06:27:21] [PASSED] Composite
[06:27:21] [PASSED] SVIDEO
[06:27:21] [PASSED] LVDS
[06:27:21] [PASSED] Component
[06:27:21] [PASSED] DIN
[06:27:21] [PASSED] DP
[06:27:21] [PASSED] HDMI-A
[06:27:21] [PASSED] HDMI-B
[06:27:21] [PASSED] TV
[06:27:21] [PASSED] eDP
[06:27:21] [PASSED] Virtual
[06:27:21] [PASSED] DSI
[06:27:21] [PASSED] DPI
[06:27:21] [PASSED] Writeback
[06:27:21] [PASSED] SPI
[06:27:21] [PASSED] USB
[06:27:21] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[06:27:21] =========== [PASSED] drm_connector_dynamic_init ============
[06:27:21] ==== drm_connector_dynamic_register_early (4 subtests) =====
[06:27:21] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[06:27:21] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[06:27:21] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[06:27:21] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[06:27:21] ====== [PASSED] drm_connector_dynamic_register_early =======
[06:27:21] ======= drm_connector_dynamic_register (7 subtests) ========
[06:27:21] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[06:27:21] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[06:27:21] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[06:27:21] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[06:27:21] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[06:27:21] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[06:27:21] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[06:27:21] ========= [PASSED] drm_connector_dynamic_register ==========
[06:27:21] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[06:27:21] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[06:27:21] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[06:27:21] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[06:27:21] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[06:27:21] ========== drm_test_get_tv_mode_from_name_valid ===========
[06:27:21] [PASSED] NTSC
[06:27:21] [PASSED] NTSC-443
[06:27:21] [PASSED] NTSC-J
[06:27:21] [PASSED] PAL
[06:27:21] [PASSED] PAL-M
[06:27:21] [PASSED] PAL-N
[06:27:21] [PASSED] SECAM
[06:27:21] [PASSED] Mono
[06:27:21] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[06:27:21] [PASSED] drm_test_get_tv_mode_from_name_truncated
[06:27:21] ============ [PASSED] drm_get_tv_mode_from_name ============
[06:27:21] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[06:27:21] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[06:27:21] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[06:27:21] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[06:27:21] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[06:27:21] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[06:27:21] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[06:27:21] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[06:27:21] [PASSED] VIC 96
[06:27:21] [PASSED] VIC 97
[06:27:21] [PASSED] VIC 101
[06:27:21] [PASSED] VIC 102
[06:27:21] [PASSED] VIC 106
[06:27:21] [PASSED] VIC 107
[06:27:21] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[06:27:21] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[06:27:21] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[06:27:21] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[06:27:21] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[06:27:21] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[06:27:21] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[06:27:21] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[06:27:21] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[06:27:21] [PASSED] Automatic
[06:27:21] [PASSED] Full
[06:27:21] [PASSED] Limited 16:235
[06:27:21] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[06:27:21] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[06:27:21] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[06:27:21] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[06:27:21] === drm_test_drm_hdmi_connector_get_output_format_name ====
[06:27:21] [PASSED] RGB
[06:27:21] [PASSED] YUV 4:2:0
[06:27:21] [PASSED] YUV 4:2:2
[06:27:21] [PASSED] YUV 4:4:4
[06:27:21] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[06:27:21] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[06:27:21] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[06:27:21] ============= drm_damage_helper (21 subtests) ==============
[06:27:21] [PASSED] drm_test_damage_iter_no_damage
[06:27:21] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[06:27:21] [PASSED] drm_test_damage_iter_no_damage_src_moved
[06:27:21] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[06:27:21] [PASSED] drm_test_damage_iter_no_damage_not_visible
[06:27:21] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[06:27:21] [PASSED] drm_test_damage_iter_no_damage_no_fb
[06:27:21] [PASSED] drm_test_damage_iter_simple_damage
[06:27:21] [PASSED] drm_test_damage_iter_single_damage
[06:27:21] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[06:27:21] [PASSED] drm_test_damage_iter_single_damage_outside_src
[06:27:21] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[06:27:21] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[06:27:21] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[06:27:21] [PASSED] drm_test_damage_iter_single_damage_src_moved
[06:27:21] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[06:27:21] [PASSED] drm_test_damage_iter_damage
[06:27:21] [PASSED] drm_test_damage_iter_damage_one_intersect
[06:27:21] [PASSED] drm_test_damage_iter_damage_one_outside
[06:27:21] [PASSED] drm_test_damage_iter_damage_src_moved
[06:27:21] [PASSED] drm_test_damage_iter_damage_not_visible
[06:27:21] ================ [PASSED] drm_damage_helper ================
[06:27:21] ============== drm_dp_mst_helper (3 subtests) ==============
[06:27:21] ============== drm_test_dp_mst_calc_pbn_mode ==============
[06:27:21] [PASSED] Clock 154000 BPP 30 DSC disabled
[06:27:21] [PASSED] Clock 234000 BPP 30 DSC disabled
[06:27:21] [PASSED] Clock 297000 BPP 24 DSC disabled
[06:27:21] [PASSED] Clock 332880 BPP 24 DSC enabled
[06:27:21] [PASSED] Clock 324540 BPP 24 DSC enabled
[06:27:21] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[06:27:21] ============== drm_test_dp_mst_calc_pbn_div ===============
[06:27:21] [PASSED] Link rate 2000000 lane count 4
[06:27:21] [PASSED] Link rate 2000000 lane count 2
[06:27:21] [PASSED] Link rate 2000000 lane count 1
[06:27:21] [PASSED] Link rate 1350000 lane count 4
[06:27:21] [PASSED] Link rate 1350000 lane count 2
[06:27:21] [PASSED] Link rate 1350000 lane count 1
[06:27:21] [PASSED] Link rate 1000000 lane count 4
[06:27:21] [PASSED] Link rate 1000000 lane count 2
[06:27:21] [PASSED] Link rate 1000000 lane count 1
[06:27:21] [PASSED] Link rate 810000 lane count 4
[06:27:21] [PASSED] Link rate 810000 lane count 2
[06:27:21] [PASSED] Link rate 810000 lane count 1
[06:27:21] [PASSED] Link rate 540000 lane count 4
[06:27:21] [PASSED] Link rate 540000 lane count 2
[06:27:21] [PASSED] Link rate 540000 lane count 1
[06:27:21] [PASSED] Link rate 270000 lane count 4
[06:27:21] [PASSED] Link rate 270000 lane count 2
[06:27:21] [PASSED] Link rate 270000 lane count 1
[06:27:21] [PASSED] Link rate 162000 lane count 4
[06:27:21] [PASSED] Link rate 162000 lane count 2
[06:27:21] [PASSED] Link rate 162000 lane count 1
[06:27:21] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[06:27:21] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[06:27:21] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[06:27:21] [PASSED] DP_POWER_UP_PHY with port number
[06:27:21] [PASSED] DP_POWER_DOWN_PHY with port number
[06:27:21] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[06:27:21] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[06:27:21] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[06:27:21] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[06:27:21] [PASSED] DP_QUERY_PAYLOAD with port number
[06:27:21] [PASSED] DP_QUERY_PAYLOAD with VCPI
[06:27:21] [PASSED] DP_REMOTE_DPCD_READ with port number
[06:27:21] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[06:27:21] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[06:27:21] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[06:27:21] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[06:27:21] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[06:27:21] [PASSED] DP_REMOTE_I2C_READ with port number
[06:27:21] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[06:27:21] [PASSED] DP_REMOTE_I2C_READ with transactions array
[06:27:21] [PASSED] DP_REMOTE_I2C_WRITE with port number
[06:27:21] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[06:27:21] [PASSED] DP_REMOTE_I2C_WRITE with data array
[06:27:21] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[06:27:21] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[06:27:21] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[06:27:21] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[06:27:21] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[06:27:21] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[06:27:21] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[06:27:21] ================ [PASSED] drm_dp_mst_helper ================
[06:27:21] ================== drm_exec (7 subtests) ===================
[06:27:21] [PASSED] sanitycheck
[06:27:21] [PASSED] test_lock
[06:27:21] [PASSED] test_lock_unlock
[06:27:21] [PASSED] test_duplicates
[06:27:21] [PASSED] test_prepare
[06:27:21] [PASSED] test_prepare_array
[06:27:21] [PASSED] test_multiple_loops
[06:27:21] ==================== [PASSED] drm_exec =====================
[06:27:21] =========== drm_format_helper_test (17 subtests) ===========
[06:27:21] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[06:27:21] [PASSED] single_pixel_source_buffer
[06:27:21] [PASSED] single_pixel_clip_rectangle
[06:27:21] [PASSED] well_known_colors
[06:27:21] [PASSED] destination_pitch
[06:27:21] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[06:27:21] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[06:27:21] [PASSED] single_pixel_source_buffer
[06:27:21] [PASSED] single_pixel_clip_rectangle
[06:27:21] [PASSED] well_known_colors
[06:27:21] [PASSED] destination_pitch
[06:27:21] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[06:27:21] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[06:27:21] [PASSED] single_pixel_source_buffer
[06:27:21] [PASSED] single_pixel_clip_rectangle
[06:27:21] [PASSED] well_known_colors
[06:27:21] [PASSED] destination_pitch
[06:27:21] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[06:27:21] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[06:27:21] [PASSED] single_pixel_source_buffer
[06:27:21] [PASSED] single_pixel_clip_rectangle
[06:27:21] [PASSED] well_known_colors
[06:27:21] [PASSED] destination_pitch
[06:27:21] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[06:27:21] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[06:27:21] [PASSED] single_pixel_source_buffer
[06:27:21] [PASSED] single_pixel_clip_rectangle
[06:27:21] [PASSED] well_known_colors
[06:27:21] [PASSED] destination_pitch
[06:27:21] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[06:27:21] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[06:27:21] [PASSED] single_pixel_source_buffer
[06:27:21] [PASSED] single_pixel_clip_rectangle
[06:27:21] [PASSED] well_known_colors
[06:27:21] [PASSED] destination_pitch
[06:27:21] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[06:27:21] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[06:27:21] [PASSED] single_pixel_source_buffer
[06:27:21] [PASSED] single_pixel_clip_rectangle
[06:27:21] [PASSED] well_known_colors
[06:27:21] [PASSED] destination_pitch
[06:27:21] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[06:27:21] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[06:27:21] [PASSED] single_pixel_source_buffer
[06:27:21] [PASSED] single_pixel_clip_rectangle
[06:27:21] [PASSED] well_known_colors
[06:27:21] [PASSED] destination_pitch
[06:27:21] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[06:27:21] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[06:27:21] [PASSED] single_pixel_source_buffer
[06:27:21] [PASSED] single_pixel_clip_rectangle
[06:27:21] [PASSED] well_known_colors
[06:27:21] [PASSED] destination_pitch
[06:27:21] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[06:27:21] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[06:27:21] [PASSED] single_pixel_source_buffer
[06:27:21] [PASSED] single_pixel_clip_rectangle
[06:27:21] [PASSED] well_known_colors
[06:27:21] [PASSED] destination_pitch
[06:27:21] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[06:27:21] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[06:27:21] [PASSED] single_pixel_source_buffer
[06:27:21] [PASSED] single_pixel_clip_rectangle
[06:27:21] [PASSED] well_known_colors
[06:27:21] [PASSED] destination_pitch
[06:27:21] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[06:27:21] ============== drm_test_fb_xrgb8888_to_mono ===============
[06:27:21] [PASSED] single_pixel_source_buffer
[06:27:21] [PASSED] single_pixel_clip_rectangle
[06:27:21] [PASSED] well_known_colors
[06:27:21] [PASSED] destination_pitch
[06:27:21] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[06:27:21] ==================== drm_test_fb_swab =====================
[06:27:21] [PASSED] single_pixel_source_buffer
[06:27:21] [PASSED] single_pixel_clip_rectangle
[06:27:21] [PASSED] well_known_colors
[06:27:21] [PASSED] destination_pitch
[06:27:21] ================ [PASSED] drm_test_fb_swab =================
[06:27:21] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[06:27:21] [PASSED] single_pixel_source_buffer
[06:27:21] [PASSED] single_pixel_clip_rectangle
[06:27:21] [PASSED] well_known_colors
[06:27:21] [PASSED] destination_pitch
[06:27:21] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[06:27:21] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[06:27:21] [PASSED] single_pixel_source_buffer
[06:27:21] [PASSED] single_pixel_clip_rectangle
[06:27:21] [PASSED] well_known_colors
[06:27:21] [PASSED] destination_pitch
[06:27:21] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[06:27:21] ================= drm_test_fb_clip_offset =================
[06:27:21] [PASSED] pass through
[06:27:21] [PASSED] horizontal offset
[06:27:21] [PASSED] vertical offset
[06:27:21] [PASSED] horizontal and vertical offset
[06:27:21] [PASSED] horizontal offset (custom pitch)
[06:27:21] [PASSED] vertical offset (custom pitch)
[06:27:21] [PASSED] horizontal and vertical offset (custom pitch)
[06:27:21] ============= [PASSED] drm_test_fb_clip_offset =============
[06:27:21] =================== drm_test_fb_memcpy ====================
[06:27:21] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[06:27:21] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[06:27:21] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[06:27:21] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[06:27:21] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[06:27:21] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[06:27:21] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[06:27:21] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[06:27:21] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[06:27:21] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[06:27:21] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[06:27:21] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[06:27:21] =============== [PASSED] drm_test_fb_memcpy ================
[06:27:21] ============= [PASSED] drm_format_helper_test ==============
[06:27:21] ================= drm_format (18 subtests) =================
[06:27:21] [PASSED] drm_test_format_block_width_invalid
[06:27:21] [PASSED] drm_test_format_block_width_one_plane
[06:27:21] [PASSED] drm_test_format_block_width_two_plane
[06:27:21] [PASSED] drm_test_format_block_width_three_plane
[06:27:21] [PASSED] drm_test_format_block_width_tiled
[06:27:21] [PASSED] drm_test_format_block_height_invalid
[06:27:21] [PASSED] drm_test_format_block_height_one_plane
[06:27:21] [PASSED] drm_test_format_block_height_two_plane
[06:27:21] [PASSED] drm_test_format_block_height_three_plane
[06:27:21] [PASSED] drm_test_format_block_height_tiled
[06:27:21] [PASSED] drm_test_format_min_pitch_invalid
[06:27:21] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[06:27:21] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[06:27:21] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[06:27:21] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[06:27:21] [PASSED] drm_test_format_min_pitch_two_plane
[06:27:21] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[06:27:21] [PASSED] drm_test_format_min_pitch_tiled
[06:27:21] =================== [PASSED] drm_format ====================
[06:27:21] ============== drm_framebuffer (10 subtests) ===============
[06:27:21] ========== drm_test_framebuffer_check_src_coords ==========
[06:27:21] [PASSED] Success: source fits into fb
[06:27:21] [PASSED] Fail: overflowing fb with x-axis coordinate
[06:27:21] [PASSED] Fail: overflowing fb with y-axis coordinate
[06:27:21] [PASSED] Fail: overflowing fb with source width
[06:27:21] [PASSED] Fail: overflowing fb with source height
[06:27:21] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[06:27:21] [PASSED] drm_test_framebuffer_cleanup
[06:27:21] =============== drm_test_framebuffer_create ===============
[06:27:21] [PASSED] ABGR8888 normal sizes
[06:27:21] [PASSED] ABGR8888 max sizes
[06:27:21] [PASSED] ABGR8888 pitch greater than min required
[06:27:21] [PASSED] ABGR8888 pitch less than min required
[06:27:21] [PASSED] ABGR8888 Invalid width
[06:27:21] [PASSED] ABGR8888 Invalid buffer handle
[06:27:21] [PASSED] No pixel format
[06:27:21] [PASSED] ABGR8888 Width 0
[06:27:21] [PASSED] ABGR8888 Height 0
[06:27:21] [PASSED] ABGR8888 Out of bound height * pitch combination
[06:27:21] [PASSED] ABGR8888 Large buffer offset
[06:27:21] [PASSED] ABGR8888 Buffer offset for inexistent plane
[06:27:21] [PASSED] ABGR8888 Invalid flag
[06:27:21] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[06:27:21] [PASSED] ABGR8888 Valid buffer modifier
[06:27:21] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[06:27:21] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[06:27:21] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[06:27:21] [PASSED] NV12 Normal sizes
[06:27:21] [PASSED] NV12 Max sizes
[06:27:21] [PASSED] NV12 Invalid pitch
[06:27:21] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[06:27:21] [PASSED] NV12 different modifier per-plane
[06:27:21] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[06:27:21] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[06:27:21] [PASSED] NV12 Modifier for inexistent plane
[06:27:21] [PASSED] NV12 Handle for inexistent plane
[06:27:21] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[06:27:21] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[06:27:21] [PASSED] YVU420 Normal sizes
[06:27:21] [PASSED] YVU420 Max sizes
[06:27:21] [PASSED] YVU420 Invalid pitch
[06:27:21] [PASSED] YVU420 Different pitches
[06:27:21] [PASSED] YVU420 Different buffer offsets/pitches
[06:27:21] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[06:27:21] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[06:27:21] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[06:27:21] [PASSED] YVU420 Valid modifier
[06:27:21] [PASSED] YVU420 Different modifiers per plane
[06:27:21] [PASSED] YVU420 Modifier for inexistent plane
[06:27:21] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[06:27:21] [PASSED] X0L2 Normal sizes
[06:27:21] [PASSED] X0L2 Max sizes
[06:27:21] [PASSED] X0L2 Invalid pitch
[06:27:21] [PASSED] X0L2 Pitch greater than minimum required
[06:27:21] [PASSED] X0L2 Handle for inexistent plane
[06:27:21] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[06:27:21] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[06:27:21] [PASSED] X0L2 Valid modifier
[06:27:21] [PASSED] X0L2 Modifier for inexistent plane
[06:27:21] =========== [PASSED] drm_test_framebuffer_create ===========
[06:27:21] [PASSED] drm_test_framebuffer_free
[06:27:21] [PASSED] drm_test_framebuffer_init
[06:27:21] [PASSED] drm_test_framebuffer_init_bad_format
[06:27:21] [PASSED] drm_test_framebuffer_init_dev_mismatch
[06:27:21] [PASSED] drm_test_framebuffer_lookup
[06:27:21] [PASSED] drm_test_framebuffer_lookup_inexistent
[06:27:21] [PASSED] drm_test_framebuffer_modifiers_not_supported
[06:27:21] ================= [PASSED] drm_framebuffer =================
[06:27:21] ================ drm_gem_shmem (8 subtests) ================
[06:27:21] [PASSED] drm_gem_shmem_test_obj_create
[06:27:21] [PASSED] drm_gem_shmem_test_obj_create_private
[06:27:21] [PASSED] drm_gem_shmem_test_pin_pages
[06:27:21] [PASSED] drm_gem_shmem_test_vmap
[06:27:21] [PASSED] drm_gem_shmem_test_get_pages_sgt
[06:27:21] [PASSED] drm_gem_shmem_test_get_sg_table
[06:27:21] [PASSED] drm_gem_shmem_test_madvise
[06:27:21] [PASSED] drm_gem_shmem_test_purge
[06:27:21] ================== [PASSED] drm_gem_shmem ==================
[06:27:21] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[06:27:21] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[06:27:21] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[06:27:21] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[06:27:21] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[06:27:21] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[06:27:21] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[06:27:21] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[06:27:21] [PASSED] Automatic
[06:27:21] [PASSED] Full
[06:27:21] [PASSED] Limited 16:235
[06:27:21] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[06:27:21] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[06:27:21] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[06:27:21] [PASSED] drm_test_check_disable_connector
[06:27:21] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[06:27:21] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[06:27:21] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[06:27:21] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[06:27:21] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[06:27:21] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[06:27:21] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[06:27:21] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[06:27:21] [PASSED] drm_test_check_output_bpc_dvi
[06:27:21] [PASSED] drm_test_check_output_bpc_format_vic_1
[06:27:21] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[06:27:21] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[06:27:21] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[06:27:21] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[06:27:21] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[06:27:21] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[06:27:21] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[06:27:21] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[06:27:21] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[06:27:21] [PASSED] drm_test_check_broadcast_rgb_value
[06:27:21] [PASSED] drm_test_check_bpc_8_value
[06:27:21] [PASSED] drm_test_check_bpc_10_value
[06:27:21] [PASSED] drm_test_check_bpc_12_value
[06:27:21] [PASSED] drm_test_check_format_value
[06:27:21] [PASSED] drm_test_check_tmds_char_value
[06:27:21] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[06:27:21] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[06:27:21] [PASSED] drm_test_check_mode_valid
[06:27:21] [PASSED] drm_test_check_mode_valid_reject
[06:27:21] [PASSED] drm_test_check_mode_valid_reject_rate
[06:27:21] [PASSED] drm_test_check_mode_valid_reject_max_clock
[06:27:21] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[06:27:21] ================= drm_managed (2 subtests) =================
[06:27:21] [PASSED] drm_test_managed_release_action
[06:27:21] [PASSED] drm_test_managed_run_action
[06:27:21] =================== [PASSED] drm_managed ===================
[06:27:21] =================== drm_mm (6 subtests) ====================
[06:27:21] [PASSED] drm_test_mm_init
[06:27:21] [PASSED] drm_test_mm_debug
[06:27:21] [PASSED] drm_test_mm_align32
[06:27:21] [PASSED] drm_test_mm_align64
[06:27:21] [PASSED] drm_test_mm_lowest
[06:27:21] [PASSED] drm_test_mm_highest
[06:27:21] ===================== [PASSED] drm_mm ======================
[06:27:21] ============= drm_modes_analog_tv (5 subtests) =============
[06:27:21] [PASSED] drm_test_modes_analog_tv_mono_576i
[06:27:21] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[06:27:21] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[06:27:21] [PASSED] drm_test_modes_analog_tv_pal_576i
[06:27:21] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[06:27:21] =============== [PASSED] drm_modes_analog_tv ===============
[06:27:21] ============== drm_plane_helper (2 subtests) ===============
[06:27:21] =============== drm_test_check_plane_state ================
[06:27:21] [PASSED] clipping_simple
[06:27:21] [PASSED] clipping_rotate_reflect
[06:27:21] [PASSED] positioning_simple
[06:27:21] [PASSED] upscaling
[06:27:21] [PASSED] downscaling
[06:27:21] [PASSED] rounding1
[06:27:21] [PASSED] rounding2
[06:27:21] [PASSED] rounding3
[06:27:21] [PASSED] rounding4
[06:27:21] =========== [PASSED] drm_test_check_plane_state ============
[06:27:21] =========== drm_test_check_invalid_plane_state ============
[06:27:21] [PASSED] positioning_invalid
[06:27:21] [PASSED] upscaling_invalid
[06:27:21] [PASSED] downscaling_invalid
[06:27:21] ======= [PASSED] drm_test_check_invalid_plane_state ========
[06:27:21] ================ [PASSED] drm_plane_helper =================
[06:27:21] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[06:27:21] ====== drm_test_connector_helper_tv_get_modes_check =======
[06:27:21] [PASSED] None
[06:27:21] [PASSED] PAL
[06:27:21] [PASSED] NTSC
[06:27:21] [PASSED] Both, NTSC Default
[06:27:21] [PASSED] Both, PAL Default
[06:27:21] [PASSED] Both, NTSC Default, with PAL on command-line
[06:27:21] [PASSED] Both, PAL Default, with NTSC on command-line
[06:27:21] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[06:27:21] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[06:27:21] ================== drm_rect (9 subtests) ===================
[06:27:21] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[06:27:21] [PASSED] drm_test_rect_clip_scaled_not_clipped
[06:27:21] [PASSED] drm_test_rect_clip_scaled_clipped
[06:27:21] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[06:27:21] ================= drm_test_rect_intersect =================
[06:27:21] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[06:27:21] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[06:27:21] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[06:27:21] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[06:27:21] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[06:27:21] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[06:27:21] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[06:27:21] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[06:27:21] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[06:27:21] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[06:27:21] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[06:27:21] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[06:27:21] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[06:27:21] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[06:27:21] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[06:27:21] ============= [PASSED] drm_test_rect_intersect =============
[06:27:21] ================ drm_test_rect_calc_hscale ================
[06:27:21] [PASSED] normal use
[06:27:21] [PASSED] out of max range
[06:27:21] [PASSED] out of min range
[06:27:21] [PASSED] zero dst
[06:27:21] [PASSED] negative src
[06:27:21] [PASSED] negative dst
[06:27:21] ============ [PASSED] drm_test_rect_calc_hscale ============
[06:27:21] ================ drm_test_rect_calc_vscale ================
[06:27:21] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[06:27:21] [PASSED] out of max range
[06:27:21] [PASSED] out of min range
[06:27:21] [PASSED] zero dst
[06:27:21] [PASSED] negative src
[06:27:21] [PASSED] negative dst
[06:27:21] ============ [PASSED] drm_test_rect_calc_vscale ============
[06:27:21] ================== drm_test_rect_rotate ===================
[06:27:21] [PASSED] reflect-x
[06:27:21] [PASSED] reflect-y
[06:27:21] [PASSED] rotate-0
[06:27:21] [PASSED] rotate-90
[06:27:21] [PASSED] rotate-180
[06:27:21] [PASSED] rotate-270
[06:27:21] ============== [PASSED] drm_test_rect_rotate ===============
[06:27:21] ================ drm_test_rect_rotate_inv =================
[06:27:21] [PASSED] reflect-x
[06:27:21] [PASSED] reflect-y
[06:27:21] [PASSED] rotate-0
[06:27:21] [PASSED] rotate-90
[06:27:21] [PASSED] rotate-180
[06:27:21] [PASSED] rotate-270
[06:27:21] ============ [PASSED] drm_test_rect_rotate_inv =============
[06:27:21] ==================== [PASSED] drm_rect =====================
[06:27:21] ============ drm_sysfb_modeset_test (1 subtest) ============
[06:27:21] ============ drm_test_sysfb_build_fourcc_list =============
[06:27:21] [PASSED] no native formats
[06:27:21] [PASSED] XRGB8888 as native format
[06:27:21] [PASSED] remove duplicates
[06:27:21] [PASSED] convert alpha formats
[06:27:21] [PASSED] random formats
[06:27:21] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[06:27:21] ============= [PASSED] drm_sysfb_modeset_test ==============
[06:27:21] ============================================================
[06:27:21] Testing complete. Ran 622 tests: passed: 622
[06:27:21] Elapsed time: 27.290s total, 1.735s configuring, 25.138s building, 0.387s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[06:27:21] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[06:27:23] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[06:27:32] Starting KUnit Kernel (1/1)...
[06:27:32] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[06:27:32] ================= ttm_device (5 subtests) ==================
[06:27:32] [PASSED] ttm_device_init_basic
[06:27:32] [PASSED] ttm_device_init_multiple
[06:27:32] [PASSED] ttm_device_fini_basic
[06:27:32] [PASSED] ttm_device_init_no_vma_man
[06:27:32] ================== ttm_device_init_pools ==================
[06:27:32] [PASSED] No DMA allocations, no DMA32 required
[06:27:32] [PASSED] DMA allocations, DMA32 required
[06:27:32] [PASSED] No DMA allocations, DMA32 required
[06:27:32] [PASSED] DMA allocations, no DMA32 required
[06:27:32] ============== [PASSED] ttm_device_init_pools ==============
[06:27:32] =================== [PASSED] ttm_device ====================
[06:27:32] ================== ttm_pool (8 subtests) ===================
[06:27:32] ================== ttm_pool_alloc_basic ===================
[06:27:32] [PASSED] One page
[06:27:32] [PASSED] More than one page
[06:27:32] [PASSED] Above the allocation limit
[06:27:32] [PASSED] One page, with coherent DMA mappings enabled
[06:27:32] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[06:27:32] ============== [PASSED] ttm_pool_alloc_basic ===============
[06:27:32] ============== ttm_pool_alloc_basic_dma_addr ==============
[06:27:32] [PASSED] One page
[06:27:32] [PASSED] More than one page
[06:27:32] [PASSED] Above the allocation limit
[06:27:32] [PASSED] One page, with coherent DMA mappings enabled
[06:27:32] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[06:27:32] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[06:27:32] [PASSED] ttm_pool_alloc_order_caching_match
[06:27:32] [PASSED] ttm_pool_alloc_caching_mismatch
[06:27:32] [PASSED] ttm_pool_alloc_order_mismatch
[06:27:32] [PASSED] ttm_pool_free_dma_alloc
[06:27:32] [PASSED] ttm_pool_free_no_dma_alloc
[06:27:32] [PASSED] ttm_pool_fini_basic
[06:27:32] ==================== [PASSED] ttm_pool =====================
[06:27:32] ================ ttm_resource (8 subtests) =================
[06:27:32] ================= ttm_resource_init_basic =================
[06:27:32] [PASSED] Init resource in TTM_PL_SYSTEM
[06:27:32] [PASSED] Init resource in TTM_PL_VRAM
[06:27:32] [PASSED] Init resource in a private placement
[06:27:32] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[06:27:32] ============= [PASSED] ttm_resource_init_basic =============
[06:27:32] [PASSED] ttm_resource_init_pinned
[06:27:32] [PASSED] ttm_resource_fini_basic
[06:27:32] [PASSED] ttm_resource_manager_init_basic
[06:27:32] [PASSED] ttm_resource_manager_usage_basic
[06:27:32] [PASSED] ttm_resource_manager_set_used_basic
[06:27:32] [PASSED] ttm_sys_man_alloc_basic
[06:27:32] [PASSED] ttm_sys_man_free_basic
[06:27:32] ================== [PASSED] ttm_resource ===================
[06:27:32] =================== ttm_tt (15 subtests) ===================
[06:27:32] ==================== ttm_tt_init_basic ====================
[06:27:32] [PASSED] Page-aligned size
[06:27:32] [PASSED] Extra pages requested
[06:27:32] ================ [PASSED] ttm_tt_init_basic ================
[06:27:32] [PASSED] ttm_tt_init_misaligned
[06:27:32] [PASSED] ttm_tt_fini_basic
[06:27:32] [PASSED] ttm_tt_fini_sg
[06:27:32] [PASSED] ttm_tt_fini_shmem
[06:27:32] [PASSED] ttm_tt_create_basic
[06:27:32] [PASSED] ttm_tt_create_invalid_bo_type
[06:27:32] [PASSED] ttm_tt_create_ttm_exists
[06:27:32] [PASSED] ttm_tt_create_failed
[06:27:32] [PASSED] ttm_tt_destroy_basic
[06:27:32] [PASSED] ttm_tt_populate_null_ttm
[06:27:32] [PASSED] ttm_tt_populate_populated_ttm
[06:27:32] [PASSED] ttm_tt_unpopulate_basic
[06:27:32] [PASSED] ttm_tt_unpopulate_empty_ttm
[06:27:32] [PASSED] ttm_tt_swapin_basic
[06:27:32] ===================== [PASSED] ttm_tt ======================
[06:27:32] =================== ttm_bo (14 subtests) ===================
[06:27:32] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[06:27:32] [PASSED] Cannot be interrupted and sleeps
[06:27:32] [PASSED] Cannot be interrupted, locks straight away
[06:27:32] [PASSED] Can be interrupted, sleeps
[06:27:32] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[06:27:32] [PASSED] ttm_bo_reserve_locked_no_sleep
[06:27:32] [PASSED] ttm_bo_reserve_no_wait_ticket
[06:27:32] [PASSED] ttm_bo_reserve_double_resv
[06:27:32] [PASSED] ttm_bo_reserve_interrupted
[06:27:32] [PASSED] ttm_bo_reserve_deadlock
[06:27:32] [PASSED] ttm_bo_unreserve_basic
[06:27:32] [PASSED] ttm_bo_unreserve_pinned
[06:27:32] [PASSED] ttm_bo_unreserve_bulk
[06:27:32] [PASSED] ttm_bo_fini_basic
[06:27:32] [PASSED] ttm_bo_fini_shared_resv
[06:27:32] [PASSED] ttm_bo_pin_basic
[06:27:32] [PASSED] ttm_bo_pin_unpin_resource
[06:27:32] [PASSED] ttm_bo_multiple_pin_one_unpin
[06:27:32] ===================== [PASSED] ttm_bo ======================
[06:27:32] ============== ttm_bo_validate (21 subtests) ===============
[06:27:32] ============== ttm_bo_init_reserved_sys_man ===============
[06:27:32] [PASSED] Buffer object for userspace
[06:27:32] [PASSED] Kernel buffer object
[06:27:32] [PASSED] Shared buffer object
[06:27:32] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[06:27:32] ============== ttm_bo_init_reserved_mock_man ==============
[06:27:32] [PASSED] Buffer object for userspace
[06:27:32] [PASSED] Kernel buffer object
[06:27:32] [PASSED] Shared buffer object
[06:27:32] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[06:27:32] [PASSED] ttm_bo_init_reserved_resv
[06:27:32] ================== ttm_bo_validate_basic ==================
[06:27:32] [PASSED] Buffer object for userspace
[06:27:32] [PASSED] Kernel buffer object
[06:27:32] [PASSED] Shared buffer object
[06:27:32] ============== [PASSED] ttm_bo_validate_basic ==============
[06:27:32] [PASSED] ttm_bo_validate_invalid_placement
[06:27:32] ============= ttm_bo_validate_same_placement ==============
[06:27:32] [PASSED] System manager
[06:27:32] [PASSED] VRAM manager
[06:27:32] ========= [PASSED] ttm_bo_validate_same_placement ==========
[06:27:32] [PASSED] ttm_bo_validate_failed_alloc
[06:27:32] [PASSED] ttm_bo_validate_pinned
[06:27:32] [PASSED] ttm_bo_validate_busy_placement
[06:27:32] ================ ttm_bo_validate_multihop =================
[06:27:32] [PASSED] Buffer object for userspace
[06:27:32] [PASSED] Kernel buffer object
[06:27:32] [PASSED] Shared buffer object
[06:27:32] ============ [PASSED] ttm_bo_validate_multihop =============
[06:27:32] ========== ttm_bo_validate_no_placement_signaled ==========
[06:27:32] [PASSED] Buffer object in system domain, no page vector
[06:27:32] [PASSED] Buffer object in system domain with an existing page vector
[06:27:32] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[06:27:32] ======== ttm_bo_validate_no_placement_not_signaled ========
[06:27:32] [PASSED] Buffer object for userspace
[06:27:32] [PASSED] Kernel buffer object
[06:27:32] [PASSED] Shared buffer object
[06:27:32] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[06:27:32] [PASSED] ttm_bo_validate_move_fence_signaled
[06:27:32] ========= ttm_bo_validate_move_fence_not_signaled =========
[06:27:32] [PASSED] Waits for GPU
[06:27:32] [PASSED] Tries to lock straight away
[06:27:32] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[06:27:32] [PASSED] ttm_bo_validate_happy_evict
[06:27:32] [PASSED] ttm_bo_validate_all_pinned_evict
[06:27:32] [PASSED] ttm_bo_validate_allowed_only_evict
[06:27:32] [PASSED] ttm_bo_validate_deleted_evict
[06:27:32] [PASSED] ttm_bo_validate_busy_domain_evict
[06:27:32] [PASSED] ttm_bo_validate_evict_gutting
[06:27:32] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[06:27:32] ================= [PASSED] ttm_bo_validate =================
[06:27:32] ============================================================
[06:27:32] Testing complete. Ran 101 tests: passed: 101
[06:27:32] Elapsed time: 11.276s total, 1.633s configuring, 9.426s building, 0.186s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 10+ messages in thread
* ✗ CI.checksparse: warning for series starting with [v3,1/2] drm/i915/ltphy: Implement HDMI Algo for Pll state
2025-11-10 6:19 [PATCH v3 1/2] drm/i915/ltphy: Implement HDMI Algo for Pll state Suraj Kandpal
` (2 preceding siblings ...)
2025-11-10 6:27 ` ✓ CI.KUnit: success " Patchwork
@ 2025-11-10 6:42 ` Patchwork
2025-11-10 7:06 ` ✓ Xe.CI.BAT: success " Patchwork
` (3 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2025-11-10 6:42 UTC (permalink / raw)
To: Kandpal, Suraj; +Cc: intel-xe
== Series Details ==
Series: series starting with [v3,1/2] drm/i915/ltphy: Implement HDMI Algo for Pll state
URL : https://patchwork.freedesktop.org/series/157300/
State : warning
== Summary ==
+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast 568f0845675b0c21185a5441e36c017e2bc095b4
Sparse version: 0.6.4 (Ubuntu: 0.6.4-4ubuntu3)
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm/i915/display/intel_ddi.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_display_types.h:2073:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2073:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2073:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2073:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2086:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2086:24: warning: unreplaced symbol '<noident>'
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 10+ messages in thread
* ✓ Xe.CI.BAT: success for series starting with [v3,1/2] drm/i915/ltphy: Implement HDMI Algo for Pll state
2025-11-10 6:19 [PATCH v3 1/2] drm/i915/ltphy: Implement HDMI Algo for Pll state Suraj Kandpal
` (3 preceding siblings ...)
2025-11-10 6:42 ` ✗ CI.checksparse: warning " Patchwork
@ 2025-11-10 7:06 ` Patchwork
2025-11-10 8:43 ` ✗ Xe.CI.Full: failure " Patchwork
` (2 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2025-11-10 7:06 UTC (permalink / raw)
To: Kandpal, Suraj; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 2037 bytes --]
== Series Details ==
Series: series starting with [v3,1/2] drm/i915/ltphy: Implement HDMI Algo for Pll state
URL : https://patchwork.freedesktop.org/series/157300/
State : success
== Summary ==
CI Bug Log - changes from xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4_BAT -> xe-pw-157300v1_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (13 -> 13)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in xe-pw-157300v1_BAT that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@xe_waitfence@reltime:
- bat-dg2-oem2: [PASS][1] -> [FAIL][2] ([Intel XE#6520])
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/bat-dg2-oem2/igt@xe_waitfence@reltime.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/bat-dg2-oem2/igt@xe_waitfence@reltime.html
#### Possible fixes ####
* igt@xe_waitfence@abstime:
- bat-dg2-oem2: [TIMEOUT][3] ([Intel XE#6506]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/bat-dg2-oem2/igt@xe_waitfence@abstime.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/bat-dg2-oem2/igt@xe_waitfence@abstime.html
[Intel XE#6506]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6506
[Intel XE#6520]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6520
Build changes
-------------
* IGT: IGT_8615 -> IGT_8616
* Linux: xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4 -> xe-pw-157300v1
IGT_8615: 8615
IGT_8616: 862eb176244feac8ee711f381fe1be1fdc6a7ede @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4: 568f0845675b0c21185a5441e36c017e2bc095b4
xe-pw-157300v1: 157300v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/index.html
[-- Attachment #2: Type: text/html, Size: 2638 bytes --]
^ permalink raw reply [flat|nested] 10+ messages in thread
* ✗ Xe.CI.Full: failure for series starting with [v3,1/2] drm/i915/ltphy: Implement HDMI Algo for Pll state
2025-11-10 6:19 [PATCH v3 1/2] drm/i915/ltphy: Implement HDMI Algo for Pll state Suraj Kandpal
` (4 preceding siblings ...)
2025-11-10 7:06 ` ✓ Xe.CI.BAT: success " Patchwork
@ 2025-11-10 8:43 ` Patchwork
2025-11-10 9:53 ` [PATCH v3 1/2] " Nautiyal, Ankit K
2025-11-14 14:45 ` Jani Nikula
7 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2025-11-10 8:43 UTC (permalink / raw)
To: Kandpal, Suraj; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 71783 bytes --]
== Series Details ==
Series: series starting with [v3,1/2] drm/i915/ltphy: Implement HDMI Algo for Pll state
URL : https://patchwork.freedesktop.org/series/157300/
State : failure
== Summary ==
CI Bug Log - changes from xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4_FULL -> xe-pw-157300v1_FULL
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-157300v1_FULL absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-157300v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (4 -> 4)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-157300v1_FULL:
### IGT changes ###
#### Possible regressions ####
* igt@kms_cursor_legacy@cursora-vs-flipb-atomic:
- shard-dg2-set2: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-dg2-433/igt@kms_cursor_legacy@cursora-vs-flipb-atomic.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-dg2-463/igt@kms_cursor_legacy@cursora-vs-flipb-atomic.html
* igt@xe_pmu@engine-activity-accuracy-50:
- shard-lnl: [PASS][3] -> [FAIL][4] +1 other test fail
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-lnl-1/igt@xe_pmu@engine-activity-accuracy-50.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-lnl-3/igt@xe_pmu@engine-activity-accuracy-50.html
Known issues
------------
Here are the changes found in xe-pw-157300v1_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- shard-lnl: NOTRUN -> [SKIP][5] ([Intel XE#1466])
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-lnl-8/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
* igt@kms_async_flips@async-flip-with-page-flip-events-linear-atomic@pipe-c-edp-1:
- shard-lnl: [PASS][6] -> [FAIL][7] ([Intel XE#6054]) +3 other tests fail
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-lnl-3/igt@kms_async_flips@async-flip-with-page-flip-events-linear-atomic@pipe-c-edp-1.html
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-lnl-3/igt@kms_async_flips@async-flip-with-page-flip-events-linear-atomic@pipe-c-edp-1.html
* igt@kms_async_flips@async-flip-with-page-flip-events-linear@pipe-c-edp-1:
- shard-lnl: [PASS][8] -> [FAIL][9] ([Intel XE#5993]) +3 other tests fail
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-lnl-4/igt@kms_async_flips@async-flip-with-page-flip-events-linear@pipe-c-edp-1.html
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-lnl-4/igt@kms_async_flips@async-flip-with-page-flip-events-linear@pipe-c-edp-1.html
* igt@kms_big_fb@4-tiled-32bpp-rotate-90:
- shard-bmg: NOTRUN -> [SKIP][10] ([Intel XE#2327])
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-5/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html
* igt@kms_big_fb@linear-64bpp-rotate-90:
- shard-lnl: NOTRUN -> [SKIP][11] ([Intel XE#1407]) +1 other test skip
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-lnl-5/igt@kms_big_fb@linear-64bpp-rotate-90.html
* igt@kms_big_fb@x-tiled-16bpp-rotate-270:
- shard-dg2-set2: NOTRUN -> [SKIP][12] ([Intel XE#316]) +1 other test skip
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-dg2-432/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-16bpp-rotate-270:
- shard-bmg: NOTRUN -> [SKIP][13] ([Intel XE#1124]) +1 other test skip
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-8/igt@kms_big_fb@y-tiled-16bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0:
- shard-dg2-set2: NOTRUN -> [SKIP][14] ([Intel XE#1124]) +6 other tests skip
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-dg2-435/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-adlp: [PASS][15] -> [DMESG-FAIL][16] ([Intel XE#4543]) +13 other tests dmesg-fail
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-adlp-8/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-8/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-0:
- shard-adlp: NOTRUN -> [SKIP][17] ([Intel XE#1124])
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-8/igt@kms_big_fb@yf-tiled-32bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-0:
- shard-lnl: NOTRUN -> [SKIP][18] ([Intel XE#1124]) +3 other tests skip
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-lnl-1/igt@kms_big_fb@yf-tiled-8bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-addfb-size-overflow:
- shard-bmg: NOTRUN -> [SKIP][19] ([Intel XE#610])
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-2/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html
* igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p:
- shard-bmg: NOTRUN -> [SKIP][20] ([Intel XE#2314] / [Intel XE#2894])
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-6/igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p.html
- shard-lnl: NOTRUN -> [SKIP][21] ([Intel XE#2191])
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-lnl-5/igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p.html
* igt@kms_bw@connected-linear-tiling-3-displays-2160x1440p:
- shard-dg2-set2: NOTRUN -> [SKIP][22] ([Intel XE#2191]) +1 other test skip
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-dg2-432/igt@kms_bw@connected-linear-tiling-3-displays-2160x1440p.html
* igt@kms_bw@connected-linear-tiling-4-displays-2560x1440p:
- shard-adlp: NOTRUN -> [SKIP][23] ([Intel XE#2191]) +1 other test skip
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-1/igt@kms_bw@connected-linear-tiling-4-displays-2560x1440p.html
* igt@kms_bw@linear-tiling-1-displays-1920x1080p:
- shard-bmg: NOTRUN -> [SKIP][24] ([Intel XE#367])
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-4/igt@kms_bw@linear-tiling-1-displays-1920x1080p.html
* igt@kms_bw@linear-tiling-2-displays-2160x1440p:
- shard-lnl: NOTRUN -> [SKIP][25] ([Intel XE#367])
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-lnl-4/igt@kms_bw@linear-tiling-2-displays-2160x1440p.html
* igt@kms_bw@linear-tiling-2-displays-2560x1440p:
- shard-dg2-set2: NOTRUN -> [SKIP][26] ([Intel XE#367])
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-dg2-435/igt@kms_bw@linear-tiling-2-displays-2560x1440p.html
* igt@kms_ccs@bad-aux-stride-4-tiled-mtl-mc-ccs:
- shard-bmg: NOTRUN -> [SKIP][27] ([Intel XE#2887]) +1 other test skip
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-1/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-mc-ccs.html
* igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs@pipe-d-hdmi-a-1:
- shard-adlp: NOTRUN -> [SKIP][28] ([Intel XE#455] / [Intel XE#787]) +3 other tests skip
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-9/igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs@pipe-c-dp-2:
- shard-bmg: NOTRUN -> [SKIP][29] ([Intel XE#2652] / [Intel XE#787]) +3 other tests skip
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-7/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs@pipe-c-dp-2.html
* igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs:
- shard-dg2-set2: NOTRUN -> [SKIP][30] ([Intel XE#455] / [Intel XE#787]) +3 other tests skip
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-dg2-435/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs.html
* igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-6:
- shard-dg2-set2: NOTRUN -> [SKIP][31] ([Intel XE#787]) +13 other tests skip
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-dg2-435/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-6.html
* igt@kms_ccs@ccs-on-another-bo-yf-tiled-ccs:
- shard-lnl: NOTRUN -> [SKIP][32] ([Intel XE#2887]) +2 other tests skip
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-lnl-2/igt@kms_ccs@ccs-on-another-bo-yf-tiled-ccs.html
* igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs:
- shard-lnl: NOTRUN -> [SKIP][33] ([Intel XE#3432])
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-lnl-3/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-1:
- shard-adlp: NOTRUN -> [SKIP][34] ([Intel XE#787]) +5 other tests skip
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-9/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-1.html
* igt@kms_chamelium_audio@dp-audio-edid:
- shard-bmg: NOTRUN -> [SKIP][35] ([Intel XE#2252]) +1 other test skip
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-6/igt@kms_chamelium_audio@dp-audio-edid.html
* igt@kms_chamelium_color@degamma:
- shard-bmg: NOTRUN -> [SKIP][36] ([Intel XE#2325]) +1 other test skip
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-4/igt@kms_chamelium_color@degamma.html
- shard-adlp: NOTRUN -> [SKIP][37] ([Intel XE#306]) +1 other test skip
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-2/igt@kms_chamelium_color@degamma.html
- shard-dg2-set2: NOTRUN -> [SKIP][38] ([Intel XE#306])
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-dg2-433/igt@kms_chamelium_color@degamma.html
- shard-lnl: NOTRUN -> [SKIP][39] ([Intel XE#306])
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-lnl-1/igt@kms_chamelium_color@degamma.html
* igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats:
- shard-adlp: NOTRUN -> [SKIP][40] ([Intel XE#373]) +1 other test skip
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-2/igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats.html
* igt@kms_chamelium_hpd@dp-hpd:
- shard-dg2-set2: NOTRUN -> [SKIP][41] ([Intel XE#373]) +3 other tests skip
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-dg2-433/igt@kms_chamelium_hpd@dp-hpd.html
* igt@kms_chamelium_hpd@dp-hpd-after-suspend:
- shard-lnl: NOTRUN -> [SKIP][42] ([Intel XE#373]) +1 other test skip
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-lnl-3/igt@kms_chamelium_hpd@dp-hpd-after-suspend.html
* igt@kms_content_protection@dp-mst-lic-type-0:
- shard-lnl: NOTRUN -> [SKIP][43] ([Intel XE#307])
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-lnl-3/igt@kms_content_protection@dp-mst-lic-type-0.html
* igt@kms_content_protection@srm@pipe-a-dp-2:
- shard-bmg: NOTRUN -> [FAIL][44] ([Intel XE#1178])
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-8/igt@kms_content_protection@srm@pipe-a-dp-2.html
* igt@kms_content_protection@srm@pipe-a-dp-4:
- shard-dg2-set2: NOTRUN -> [FAIL][45] ([Intel XE#1178]) +1 other test fail
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-dg2-433/igt@kms_content_protection@srm@pipe-a-dp-4.html
* igt@kms_cursor_crc@cursor-offscreen-512x512:
- shard-dg2-set2: NOTRUN -> [SKIP][46] ([Intel XE#308])
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-dg2-466/igt@kms_cursor_crc@cursor-offscreen-512x512.html
* igt@kms_cursor_crc@cursor-random-32x32:
- shard-adlp: NOTRUN -> [SKIP][47] ([Intel XE#455]) +8 other tests skip
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-1/igt@kms_cursor_crc@cursor-random-32x32.html
* igt@kms_cursor_crc@cursor-rapid-movement-32x10:
- shard-bmg: NOTRUN -> [SKIP][48] ([Intel XE#2320]) +1 other test skip
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-6/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html
* igt@kms_cursor_crc@cursor-sliding-max-size:
- shard-dg2-set2: NOTRUN -> [SKIP][49] ([Intel XE#455]) +7 other tests skip
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-dg2-432/igt@kms_cursor_crc@cursor-sliding-max-size.html
- shard-lnl: NOTRUN -> [SKIP][50] ([Intel XE#1424]) +1 other test skip
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-lnl-5/igt@kms_cursor_crc@cursor-sliding-max-size.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-bmg: [PASS][51] -> [SKIP][52] ([Intel XE#2291]) +6 other tests skip
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-bmg-7/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-6/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size:
- shard-adlp: NOTRUN -> [SKIP][53] ([Intel XE#309])
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-8/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
- shard-lnl: NOTRUN -> [SKIP][54] ([Intel XE#309])
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-lnl-4/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html
* igt@kms_cursor_legacy@flip-vs-cursor-legacy:
- shard-bmg: [PASS][55] -> [FAIL][56] ([Intel XE#4633])
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-bmg-5/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-6/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
- shard-bmg: NOTRUN -> [SKIP][57] ([Intel XE#2286])
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-1/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
* igt@kms_dp_link_training@uhbr-mst:
- shard-adlp: NOTRUN -> [SKIP][58] ([Intel XE#4356])
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-6/igt@kms_dp_link_training@uhbr-mst.html
* igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-dirtyfb-tests:
- shard-lnl: NOTRUN -> [SKIP][59] ([Intel XE#4422]) +1 other test skip
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-lnl-8/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-dirtyfb-tests.html
* igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area:
- shard-adlp: NOTRUN -> [SKIP][60] ([Intel XE#4422])
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-2/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area.html
- shard-bmg: NOTRUN -> [SKIP][61] ([Intel XE#4422])
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-4/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area.html
- shard-dg2-set2: NOTRUN -> [SKIP][62] ([Intel XE#4422])
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-dg2-433/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area.html
* igt@kms_feature_discovery@chamelium:
- shard-dg2-set2: NOTRUN -> [SKIP][63] ([Intel XE#701])
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-dg2-432/igt@kms_feature_discovery@chamelium.html
* igt@kms_flip@2x-absolute-wf_vblank:
- shard-adlp: NOTRUN -> [SKIP][64] ([Intel XE#310]) +1 other test skip
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-6/igt@kms_flip@2x-absolute-wf_vblank.html
* igt@kms_flip@2x-blocking-absolute-wf_vblank:
- shard-bmg: [PASS][65] -> [SKIP][66] ([Intel XE#2316])
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-bmg-4/igt@kms_flip@2x-blocking-absolute-wf_vblank.html
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-6/igt@kms_flip@2x-blocking-absolute-wf_vblank.html
* igt@kms_flip@2x-nonexisting-fb-interruptible:
- shard-lnl: NOTRUN -> [SKIP][67] ([Intel XE#1421]) +1 other test skip
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-lnl-8/igt@kms_flip@2x-nonexisting-fb-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
- shard-lnl: [PASS][68] -> [FAIL][69] ([Intel XE#301] / [Intel XE#3149]) +1 other test fail
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-lnl-7/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
* igt@kms_flip@flip-vs-rmfb-interruptible:
- shard-adlp: [PASS][70] -> [DMESG-WARN][71] ([Intel XE#4543] / [Intel XE#5208])
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-adlp-1/igt@kms_flip@flip-vs-rmfb-interruptible.html
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-9/igt@kms_flip@flip-vs-rmfb-interruptible.html
* igt@kms_flip@flip-vs-rmfb-interruptible@b-hdmi-a1:
- shard-adlp: [PASS][72] -> [DMESG-WARN][73] ([Intel XE#4543])
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-adlp-1/igt@kms_flip@flip-vs-rmfb-interruptible@b-hdmi-a1.html
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-9/igt@kms_flip@flip-vs-rmfb-interruptible@b-hdmi-a1.html
* igt@kms_flip@flip-vs-suspend@d-dp4:
- shard-dg2-set2: [PASS][74] -> [INCOMPLETE][75] ([Intel XE#2049] / [Intel XE#2597]) +1 other test incomplete
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-dg2-433/igt@kms_flip@flip-vs-suspend@d-dp4.html
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-dg2-466/igt@kms_flip@flip-vs-suspend@d-dp4.html
* igt@kms_flip@plain-flip-ts-check-interruptible@c-hdmi-a1:
- shard-adlp: NOTRUN -> [DMESG-WARN][76] ([Intel XE#4543]) +2 other tests dmesg-warn
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-1/igt@kms_flip@plain-flip-ts-check-interruptible@c-hdmi-a1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling:
- shard-bmg: NOTRUN -> [SKIP][77] ([Intel XE#2293] / [Intel XE#2380])
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode:
- shard-bmg: NOTRUN -> [SKIP][78] ([Intel XE#2293])
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@drrs-1p-offscreen-pri-indfb-draw-blt:
- shard-dg2-set2: NOTRUN -> [SKIP][79] ([Intel XE#6312]) +1 other test skip
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-dg2-435/igt@kms_frontbuffer_tracking@drrs-1p-offscreen-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@drrs-1p-primscrn-indfb-pgflip-blt:
- shard-adlp: NOTRUN -> [SKIP][80] ([Intel XE#651]) +2 other tests skip
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-3/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@drrs-suspend:
- shard-lnl: NOTRUN -> [SKIP][81] ([Intel XE#651]) +2 other tests skip
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-lnl-3/igt@kms_frontbuffer_tracking@drrs-suspend.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-blt:
- shard-adlp: NOTRUN -> [DMESG-FAIL][82] ([Intel XE#4543])
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-wc:
- shard-bmg: NOTRUN -> [SKIP][83] ([Intel XE#5390]) +1 other test skip
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-onoff:
- shard-bmg: NOTRUN -> [SKIP][84] ([Intel XE#2312])
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-indfb-msflip-blt:
- shard-bmg: NOTRUN -> [SKIP][85] ([Intel XE#2311]) +3 other tests skip
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-indfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-plflip-blt:
- shard-dg2-set2: NOTRUN -> [SKIP][86] ([Intel XE#651]) +9 other tests skip
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-dg2-432/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
- shard-adlp: NOTRUN -> [SKIP][87] ([Intel XE#653]) +2 other tests skip
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt:
- shard-bmg: NOTRUN -> [SKIP][88] ([Intel XE#2313]) +8 other tests skip
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-wc:
- shard-lnl: NOTRUN -> [SKIP][89] ([Intel XE#656]) +10 other tests skip
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-lnl-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt:
- shard-dg2-set2: NOTRUN -> [SKIP][90] ([Intel XE#653]) +15 other tests skip
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-dg2-436/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-blt:
- shard-adlp: NOTRUN -> [SKIP][91] ([Intel XE#656]) +11 other tests skip
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-1/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-blt.html
* igt@kms_hdr@invalid-metadata-sizes:
- shard-lnl: NOTRUN -> [SKIP][92] ([Intel XE#1503])
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-lnl-5/igt@kms_hdr@invalid-metadata-sizes.html
* igt@kms_joiner@invalid-modeset-force-big-joiner:
- shard-adlp: NOTRUN -> [SKIP][93] ([Intel XE#3012])
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-6/igt@kms_joiner@invalid-modeset-force-big-joiner.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-dg2-set2: NOTRUN -> [SKIP][94] ([Intel XE#356])
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-dg2-434/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_pipe_stress@stress-xrgb8888-yftiled:
- shard-adlp: NOTRUN -> [SKIP][95] ([Intel XE#5624])
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-3/igt@kms_pipe_stress@stress-xrgb8888-yftiled.html
* igt@kms_plane_multiple@2x-tiling-none:
- shard-bmg: [PASS][96] -> [SKIP][97] ([Intel XE#4596])
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-bmg-4/igt@kms_plane_multiple@2x-tiling-none.html
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-6/igt@kms_plane_multiple@2x-tiling-none.html
* igt@kms_plane_multiple@tiling-y:
- shard-lnl: NOTRUN -> [SKIP][98] ([Intel XE#5020])
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-lnl-1/igt@kms_plane_multiple@tiling-y.html
* igt@kms_pm_backlight@bad-brightness:
- shard-dg2-set2: NOTRUN -> [SKIP][99] ([Intel XE#870])
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-dg2-464/igt@kms_pm_backlight@bad-brightness.html
* igt@kms_pm_rpm@dpms-mode-unset-lpsp:
- shard-bmg: NOTRUN -> [SKIP][100] ([Intel XE#1439] / [Intel XE#836])
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-1/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html
* igt@kms_pm_rpm@modeset-lpsp-stress:
- shard-bmg: NOTRUN -> [SKIP][101] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#836])
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-8/igt@kms_pm_rpm@modeset-lpsp-stress.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress:
- shard-lnl: NOTRUN -> [SKIP][102] ([Intel XE#1439] / [Intel XE#3141])
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-lnl-8/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
* igt@kms_psr2_sf@pr-overlay-plane-update-sf-dmg-area:
- shard-adlp: NOTRUN -> [SKIP][103] ([Intel XE#1406] / [Intel XE#1489]) +2 other tests skip
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-2/igt@kms_psr2_sf@pr-overlay-plane-update-sf-dmg-area.html
- shard-bmg: NOTRUN -> [SKIP][104] ([Intel XE#1406] / [Intel XE#1489]) +1 other test skip
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-1/igt@kms_psr2_sf@pr-overlay-plane-update-sf-dmg-area.html
- shard-dg2-set2: NOTRUN -> [SKIP][105] ([Intel XE#1406] / [Intel XE#1489]) +3 other tests skip
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-dg2-464/igt@kms_psr2_sf@pr-overlay-plane-update-sf-dmg-area.html
- shard-lnl: NOTRUN -> [SKIP][106] ([Intel XE#1406] / [Intel XE#2893])
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-lnl-1/igt@kms_psr2_sf@pr-overlay-plane-update-sf-dmg-area.html
* igt@kms_psr@fbc-pr-sprite-render:
- shard-dg2-set2: NOTRUN -> [SKIP][107] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) +5 other tests skip
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-dg2-464/igt@kms_psr@fbc-pr-sprite-render.html
* igt@kms_psr@fbc-psr2-suspend:
- shard-adlp: NOTRUN -> [SKIP][108] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) +1 other test skip
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-3/igt@kms_psr@fbc-psr2-suspend.html
- shard-bmg: NOTRUN -> [SKIP][109] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +2 other tests skip
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-2/igt@kms_psr@fbc-psr2-suspend.html
- shard-lnl: NOTRUN -> [SKIP][110] ([Intel XE#1406]) +1 other test skip
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-lnl-3/igt@kms_psr@fbc-psr2-suspend.html
* igt@kms_psr@fbc-psr2-suspend@edp-1:
- shard-lnl: NOTRUN -> [SKIP][111] ([Intel XE#1406] / [Intel XE#4609])
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-lnl-3/igt@kms_psr@fbc-psr2-suspend@edp-1.html
* igt@kms_rotation_crc@bad-tiling:
- shard-dg2-set2: NOTRUN -> [SKIP][112] ([Intel XE#3414]) +2 other tests skip
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-dg2-435/igt@kms_rotation_crc@bad-tiling.html
* igt@kms_rotation_crc@primary-rotation-90:
- shard-bmg: NOTRUN -> [SKIP][113] ([Intel XE#3414] / [Intel XE#3904]) +1 other test skip
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-1/igt@kms_rotation_crc@primary-rotation-90.html
* igt@kms_rotation_crc@sprite-rotation-270:
- shard-adlp: NOTRUN -> [SKIP][114] ([Intel XE#3414])
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-4/igt@kms_rotation_crc@sprite-rotation-270.html
- shard-lnl: NOTRUN -> [SKIP][115] ([Intel XE#3414] / [Intel XE#3904]) +1 other test skip
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-lnl-8/igt@kms_rotation_crc@sprite-rotation-270.html
* igt@kms_setmode@clone-exclusive-crtc:
- shard-bmg: [PASS][116] -> [SKIP][117] ([Intel XE#1435])
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-bmg-8/igt@kms_setmode@clone-exclusive-crtc.html
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-6/igt@kms_setmode@clone-exclusive-crtc.html
* igt@kms_sharpness_filter@filter-scaler-upscale:
- shard-bmg: NOTRUN -> [SKIP][118] ([Intel XE#6503])
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-2/igt@kms_sharpness_filter@filter-scaler-upscale.html
* igt@xe_compute_preempt@compute-preempt-many-vram-evict:
- shard-dg2-set2: NOTRUN -> [SKIP][119] ([Intel XE#6360]) +1 other test skip
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-dg2-463/igt@xe_compute_preempt@compute-preempt-many-vram-evict.html
* igt@xe_eu_stall@invalid-sampling-rate:
- shard-dg2-set2: NOTRUN -> [SKIP][120] ([Intel XE#5626])
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-dg2-466/igt@xe_eu_stall@invalid-sampling-rate.html
* igt@xe_eudebug@basic-vm-bind-discovery:
- shard-dg2-set2: NOTRUN -> [SKIP][121] ([Intel XE#4837]) +2 other tests skip
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-dg2-436/igt@xe_eudebug@basic-vm-bind-discovery.html
* igt@xe_eudebug@basic-vm-bind-ufence:
- shard-lnl: NOTRUN -> [SKIP][122] ([Intel XE#4837]) +1 other test skip
[122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-lnl-4/igt@xe_eudebug@basic-vm-bind-ufence.html
* igt@xe_eudebug_online@reset-with-attention:
- shard-adlp: NOTRUN -> [SKIP][123] ([Intel XE#4837] / [Intel XE#5565]) +2 other tests skip
[123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-2/igt@xe_eudebug_online@reset-with-attention.html
* igt@xe_eudebug_online@writes-caching-sram-bb-vram-target-vram:
- shard-bmg: NOTRUN -> [SKIP][124] ([Intel XE#4837])
[124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-5/igt@xe_eudebug_online@writes-caching-sram-bb-vram-target-vram.html
* igt@xe_evict@evict-beng-large-multi-vm:
- shard-adlp: NOTRUN -> [SKIP][125] ([Intel XE#261] / [Intel XE#5564]) +1 other test skip
[125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-8/igt@xe_evict@evict-beng-large-multi-vm.html
* igt@xe_evict@evict-beng-mixed-threads-large-multi-vm:
- shard-lnl: NOTRUN -> [SKIP][126] ([Intel XE#688]) +3 other tests skip
[126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-lnl-3/igt@xe_evict@evict-beng-mixed-threads-large-multi-vm.html
* igt@xe_evict_ccs@evict-overcommit-parallel-instantfree-samefd:
- shard-adlp: NOTRUN -> [SKIP][127] ([Intel XE#688])
[127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-6/igt@xe_evict_ccs@evict-overcommit-parallel-instantfree-samefd.html
* igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-invalidate:
- shard-dg2-set2: [PASS][128] -> [INCOMPLETE][129] ([Intel XE#4842])
[128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-dg2-463/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-invalidate.html
[129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-dg2-436/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-invalidate.html
* igt@xe_exec_basic@multigpu-once-basic-defer-bind:
- shard-adlp: NOTRUN -> [SKIP][130] ([Intel XE#1392] / [Intel XE#5575]) +1 other test skip
[130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-2/igt@xe_exec_basic@multigpu-once-basic-defer-bind.html
- shard-bmg: NOTRUN -> [SKIP][131] ([Intel XE#2322]) +1 other test skip
[131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-1/igt@xe_exec_basic@multigpu-once-basic-defer-bind.html
- shard-lnl: NOTRUN -> [SKIP][132] ([Intel XE#1392]) +2 other tests skip
[132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-lnl-1/igt@xe_exec_basic@multigpu-once-basic-defer-bind.html
* igt@xe_exec_fault_mode@invalid-va-scratch-nopagefault:
- shard-adlp: NOTRUN -> [SKIP][133] ([Intel XE#288] / [Intel XE#5561]) +7 other tests skip
[133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-4/igt@xe_exec_fault_mode@invalid-va-scratch-nopagefault.html
* igt@xe_exec_fault_mode@once-bindexecqueue-imm:
- shard-dg2-set2: NOTRUN -> [SKIP][134] ([Intel XE#288]) +11 other tests skip
[134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-dg2-466/igt@xe_exec_fault_mode@once-bindexecqueue-imm.html
* igt@xe_exec_mix_modes@exec-spinner-interrupted-dma-fence:
- shard-adlp: NOTRUN -> [SKIP][135] ([Intel XE#2360])
[135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-9/igt@xe_exec_mix_modes@exec-spinner-interrupted-dma-fence.html
* igt@xe_exec_system_allocator@many-large-execqueues-mmap-file-nomemset:
- shard-adlp: NOTRUN -> [SKIP][136] ([Intel XE#4915]) +82 other tests skip
[136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-1/igt@xe_exec_system_allocator@many-large-execqueues-mmap-file-nomemset.html
* igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma:
- shard-lnl: [PASS][137] -> [FAIL][138] ([Intel XE#5625])
[137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-lnl-1/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma.html
[138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-lnl-7/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma.html
* igt@xe_exec_system_allocator@threads-many-large-mmap-shared-remap-dontunmap-eocheck:
- shard-dg2-set2: NOTRUN -> [SKIP][139] ([Intel XE#4915]) +131 other tests skip
[139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-dg2-432/igt@xe_exec_system_allocator@threads-many-large-mmap-shared-remap-dontunmap-eocheck.html
* igt@xe_exec_system_allocator@threads-shared-vm-many-large-mmap-new-huge:
- shard-lnl: NOTRUN -> [SKIP][140] ([Intel XE#4943]) +7 other tests skip
[140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-lnl-1/igt@xe_exec_system_allocator@threads-shared-vm-many-large-mmap-new-huge.html
* igt@xe_exec_system_allocator@threads-shared-vm-many-mmap-new-huge:
- shard-bmg: NOTRUN -> [SKIP][141] ([Intel XE#4943]) +3 other tests skip
[141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-1/igt@xe_exec_system_allocator@threads-shared-vm-many-mmap-new-huge.html
* igt@xe_exec_system_allocator@twice-large-malloc-prefetch-madvise:
- shard-lnl: NOTRUN -> [WARN][142] ([Intel XE#5786])
[142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-lnl-1/igt@xe_exec_system_allocator@twice-large-malloc-prefetch-madvise.html
* igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv:
- shard-dg2-set2: [PASS][143] -> [DMESG-WARN][144] ([Intel XE#5893])
[143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-dg2-433/igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv.html
[144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-dg2-436/igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv.html
* igt@xe_live_ktest@xe_migrate@xe_validate_ccs_kunit:
- shard-adlp: NOTRUN -> [SKIP][145] ([Intel XE#2229] / [Intel XE#5488])
[145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-9/igt@xe_live_ktest@xe_migrate@xe_validate_ccs_kunit.html
* igt@xe_oa@mmio-triggered-reports:
- shard-dg2-set2: NOTRUN -> [SKIP][146] ([Intel XE#3573]) +2 other tests skip
[146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-dg2-436/igt@xe_oa@mmio-triggered-reports.html
* igt@xe_oa@short-reads:
- shard-adlp: NOTRUN -> [SKIP][147] ([Intel XE#3573]) +2 other tests skip
[147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-9/igt@xe_oa@short-reads.html
* igt@xe_pat@pat-index-xelpg:
- shard-dg2-set2: NOTRUN -> [SKIP][148] ([Intel XE#979])
[148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-dg2-463/igt@xe_pat@pat-index-xelpg.html
* igt@xe_peer2peer@write@write-gpua-system-gpub-system-p2p:
- shard-adlp: NOTRUN -> [DMESG-FAIL][149] ([Intel XE#5213])
[149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-1/igt@xe_peer2peer@write@write-gpua-system-gpub-system-p2p.html
* igt@xe_pm@d3cold-i2c:
- shard-dg2-set2: NOTRUN -> [SKIP][150] ([Intel XE#5694])
[150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-dg2-466/igt@xe_pm@d3cold-i2c.html
* igt@xe_pm@d3cold-mmap-system:
- shard-dg2-set2: NOTRUN -> [SKIP][151] ([Intel XE#2284] / [Intel XE#366])
[151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-dg2-436/igt@xe_pm@d3cold-mmap-system.html
* igt@xe_pm@s2idle-d3cold-basic-exec:
- shard-bmg: NOTRUN -> [SKIP][152] ([Intel XE#2284])
[152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-5/igt@xe_pm@s2idle-d3cold-basic-exec.html
* igt@xe_pm_residency@cpg-basic:
- shard-lnl: NOTRUN -> [SKIP][153] ([Intel XE#584]) +1 other test skip
[153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-lnl-8/igt@xe_pm_residency@cpg-basic.html
* igt@xe_pmu@fn-engine-activity-load:
- shard-lnl: NOTRUN -> [SKIP][154] ([Intel XE#4650])
[154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-lnl-7/igt@xe_pmu@fn-engine-activity-load.html
* igt@xe_pmu@gt-c6-idle:
- shard-dg2-set2: [PASS][155] -> [FAIL][156] ([Intel XE#6366])
[155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-dg2-464/igt@xe_pmu@gt-c6-idle.html
[156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-dg2-464/igt@xe_pmu@gt-c6-idle.html
* igt@xe_pxp@pxp-src-to-pxp-dest-rendercopy:
- shard-dg2-set2: NOTRUN -> [SKIP][157] ([Intel XE#4733])
[157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-dg2-434/igt@xe_pxp@pxp-src-to-pxp-dest-rendercopy.html
* igt@xe_query@multigpu-query-invalid-cs-cycles:
- shard-lnl: NOTRUN -> [SKIP][158] ([Intel XE#944])
[158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-lnl-3/igt@xe_query@multigpu-query-invalid-cs-cycles.html
* igt@xe_query@multigpu-query-topology:
- shard-bmg: NOTRUN -> [SKIP][159] ([Intel XE#944])
[159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-4/igt@xe_query@multigpu-query-topology.html
* igt@xe_render_copy@render-stress-4-copies:
- shard-dg2-set2: NOTRUN -> [SKIP][160] ([Intel XE#4814])
[160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-dg2-463/igt@xe_render_copy@render-stress-4-copies.html
* igt@xe_sriov_scheduling@nonpreempt-engine-resets@numvfs-random:
- shard-adlp: [PASS][161] -> [DMESG-FAIL][162] ([Intel XE#3868] / [Intel XE#5213]) +1 other test dmesg-fail
[161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-adlp-4/igt@xe_sriov_scheduling@nonpreempt-engine-resets@numvfs-random.html
[162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-9/igt@xe_sriov_scheduling@nonpreempt-engine-resets@numvfs-random.html
* igt@xe_sriov_vram@vf-access-after-resize-up:
- shard-dg2-set2: NOTRUN -> [SKIP][163] ([Intel XE#6318])
[163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-dg2-432/igt@xe_sriov_vram@vf-access-after-resize-up.html
#### Possible fixes ####
* igt@intel_hwmon@hwmon-write:
- shard-bmg: [FAIL][164] ([Intel XE#4665]) -> [PASS][165]
[164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-bmg-1/igt@intel_hwmon@hwmon-write.html
[165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-6/igt@intel_hwmon@hwmon-write.html
* igt@kms_async_flips@async-flip-with-page-flip-events-tiled@pipe-b-hdmi-a-1-y:
- shard-adlp: [DMESG-WARN][166] ([Intel XE#4543]) -> [PASS][167] +16 other tests pass
[166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-adlp-6/igt@kms_async_flips@async-flip-with-page-flip-events-tiled@pipe-b-hdmi-a-1-y.html
[167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-1/igt@kms_async_flips@async-flip-with-page-flip-events-tiled@pipe-b-hdmi-a-1-y.html
* igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1:
- shard-adlp: [FAIL][168] ([Intel XE#3908]) -> [PASS][169] +1 other test pass
[168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-adlp-1/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1.html
[169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-6/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs:
- shard-dg2-set2: [INCOMPLETE][170] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4345] / [Intel XE#6168]) -> [PASS][171]
[170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
[171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-c-dp-4:
- shard-dg2-set2: [INCOMPLETE][172] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#6168]) -> [PASS][173]
[172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-c-dp-4.html
[173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-c-dp-4.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
- shard-dg2-set2: [INCOMPLETE][174] ([Intel XE#2705] / [Intel XE#4212] / [Intel XE#4345]) -> [PASS][175]
[174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
[175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-dp-4:
- shard-dg2-set2: [INCOMPLETE][176] ([Intel XE#2705] / [Intel XE#4212]) -> [PASS][177]
[176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-dp-4.html
[177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-dp-4.html
* igt@kms_cursor_legacy@cursora-vs-flipb-varying-size:
- shard-bmg: [SKIP][178] ([Intel XE#2291]) -> [PASS][179] +2 other tests pass
[178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-bmg-6/igt@kms_cursor_legacy@cursora-vs-flipb-varying-size.html
[179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-5/igt@kms_cursor_legacy@cursora-vs-flipb-varying-size.html
* igt@kms_display_modes@extended-mode-basic:
- shard-bmg: [SKIP][180] ([Intel XE#4302]) -> [PASS][181]
[180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-bmg-6/igt@kms_display_modes@extended-mode-basic.html
[181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-1/igt@kms_display_modes@extended-mode-basic.html
* igt@kms_feature_discovery@display-2x:
- shard-bmg: [SKIP][182] ([Intel XE#2373]) -> [PASS][183]
[182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-bmg-6/igt@kms_feature_discovery@display-2x.html
[183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-7/igt@kms_feature_discovery@display-2x.html
* igt@kms_flip@2x-nonexisting-fb:
- shard-bmg: [SKIP][184] ([Intel XE#2316]) -> [PASS][185] +6 other tests pass
[184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-bmg-6/igt@kms_flip@2x-nonexisting-fb.html
[185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-8/igt@kms_flip@2x-nonexisting-fb.html
* igt@kms_flip@flip-vs-expired-vblank@b-edp1:
- shard-lnl: [FAIL][186] ([Intel XE#301]) -> [PASS][187] +1 other test pass
[186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
[187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
* igt@kms_flip@flip-vs-panning-interruptible:
- shard-adlp: [DMESG-WARN][188] ([Intel XE#4543] / [Intel XE#5208]) -> [PASS][189]
[188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-adlp-1/igt@kms_flip@flip-vs-panning-interruptible.html
[189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-2/igt@kms_flip@flip-vs-panning-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render:
- shard-adlp: [DMESG-FAIL][190] ([Intel XE#4543]) -> [PASS][191] +5 other tests pass
[190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-adlp-1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render.html
[191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-adlp: [DMESG-WARN][192] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][193] +2 other tests pass
[192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-adlp-3/igt@kms_frontbuffer_tracking@fbc-suspend.html
[193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-9/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_pm_dc@dc5-dpms:
- shard-lnl: [FAIL][194] ([Intel XE#718]) -> [PASS][195]
[194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-lnl-5/igt@kms_pm_dc@dc5-dpms.html
[195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-lnl-5/igt@kms_pm_dc@dc5-dpms.html
* igt@kms_vblank@ts-continuation-suspend:
- shard-adlp: [INCOMPLETE][196] ([Intel XE#4488] / [Intel XE#5545]) -> [PASS][197]
[196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-adlp-6/igt@kms_vblank@ts-continuation-suspend.html
[197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-3/igt@kms_vblank@ts-continuation-suspend.html
* igt@kms_vblank@ts-continuation-suspend@pipe-a-hdmi-a-1:
- shard-adlp: [DMESG-FAIL][198] ([Intel XE#5545]) -> [PASS][199]
[198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-adlp-6/igt@kms_vblank@ts-continuation-suspend@pipe-a-hdmi-a-1.html
[199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-3/igt@kms_vblank@ts-continuation-suspend@pipe-a-hdmi-a-1.html
* igt@kms_vblank@ts-continuation-suspend@pipe-d-hdmi-a-1:
- shard-adlp: [INCOMPLETE][200] ([Intel XE#4488]) -> [PASS][201]
[200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-adlp-6/igt@kms_vblank@ts-continuation-suspend@pipe-d-hdmi-a-1.html
[201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-3/igt@kms_vblank@ts-continuation-suspend@pipe-d-hdmi-a-1.html
* igt@xe_evict@evict-beng-mixed-many-threads-small:
- shard-bmg: [INCOMPLETE][202] ([Intel XE#6321]) -> [PASS][203]
[202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-bmg-1/igt@xe_evict@evict-beng-mixed-many-threads-small.html
[203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-2/igt@xe_evict@evict-beng-mixed-many-threads-small.html
* igt@xe_exec_basic@multigpu-no-exec-basic:
- shard-adlp: [SKIP][204] ([Intel XE#1392] / [Intel XE#5575]) -> [PASS][205]
[204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-adlp-3/igt@xe_exec_basic@multigpu-no-exec-basic.html
[205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-1/igt@xe_exec_basic@multigpu-no-exec-basic.html
* igt@xe_pm@s2idle-vm-bind-userptr:
- shard-adlp: [DMESG-WARN][206] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#4504]) -> [PASS][207] +1 other test pass
[206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-adlp-8/igt@xe_pm@s2idle-vm-bind-userptr.html
[207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-2/igt@xe_pm@s2idle-vm-bind-userptr.html
* igt@xe_pm_residency@idle-residency:
- shard-dg2-set2: [FAIL][208] ([Intel XE#6362]) -> [PASS][209] +1 other test pass
[208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-dg2-466/igt@xe_pm_residency@idle-residency.html
[209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-dg2-435/igt@xe_pm_residency@idle-residency.html
* igt@xe_pmu@engine-activity-accuracy-90:
- shard-lnl: [FAIL][210] ([Intel XE#6251]) -> [PASS][211] +2 other tests pass
[210]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-lnl-3/igt@xe_pmu@engine-activity-accuracy-90.html
[211]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-lnl-1/igt@xe_pmu@engine-activity-accuracy-90.html
* igt@xe_sriov_flr@flr-twice:
- shard-bmg: [FAIL][212] -> [PASS][213]
[212]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-bmg-2/igt@xe_sriov_flr@flr-twice.html
[213]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-8/igt@xe_sriov_flr@flr-twice.html
* igt@xe_sriov_vram@vf-access-after-resize-down:
- shard-bmg: [FAIL][214] ([Intel XE#5937]) -> [PASS][215]
[214]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-bmg-5/igt@xe_sriov_vram@vf-access-after-resize-down.html
[215]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-4/igt@xe_sriov_vram@vf-access-after-resize-down.html
#### Warnings ####
* igt@kms_content_protection@srm:
- shard-bmg: [SKIP][216] ([Intel XE#2341]) -> [FAIL][217] ([Intel XE#1178])
[216]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-bmg-6/igt@kms_content_protection@srm.html
[217]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-8/igt@kms_content_protection@srm.html
* igt@kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-pgflip-blt:
- shard-bmg: [SKIP][218] ([Intel XE#2311]) -> [SKIP][219] ([Intel XE#2312]) +13 other tests skip
[218]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-pgflip-blt.html
[219]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt:
- shard-bmg: [SKIP][220] ([Intel XE#2312]) -> [SKIP][221] ([Intel XE#2311]) +14 other tests skip
[220]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt.html
[221]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-pri-indfb-multidraw:
- shard-bmg: [SKIP][222] ([Intel XE#2312]) -> [SKIP][223] ([Intel XE#5390]) +3 other tests skip
[222]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-pri-indfb-multidraw.html
[223]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt:
- shard-bmg: [SKIP][224] ([Intel XE#5390]) -> [SKIP][225] ([Intel XE#2312]) +3 other tests skip
[224]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt.html
[225]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-blt:
- shard-bmg: [SKIP][226] ([Intel XE#2312]) -> [SKIP][227] ([Intel XE#2313]) +14 other tests skip
[226]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-blt.html
[227]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt:
- shard-bmg: [SKIP][228] ([Intel XE#2313]) -> [SKIP][229] ([Intel XE#2312]) +12 other tests skip
[228]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-bmg-8/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
[229]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
* igt@kms_hdr@brightness-with-hdr:
- shard-bmg: [SKIP][230] ([Intel XE#3544]) -> [SKIP][231] ([Intel XE#3374] / [Intel XE#3544])
[230]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-bmg-1/igt@kms_hdr@brightness-with-hdr.html
[231]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-6/igt@kms_hdr@brightness-with-hdr.html
* igt@kms_tiled_display@basic-test-pattern:
- shard-dg2-set2: [FAIL][232] ([Intel XE#1729]) -> [SKIP][233] ([Intel XE#362])
[232]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-dg2-433/igt@kms_tiled_display@basic-test-pattern.html
[233]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-dg2-463/igt@kms_tiled_display@basic-test-pattern.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-bmg: [SKIP][234] ([Intel XE#2426]) -> [SKIP][235] ([Intel XE#2509])
[234]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-bmg-7/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
[235]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-5/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1:
- shard-lnl: [FAIL][236] ([Intel XE#5862] / [Intel XE#6554]) -> [FAIL][237] ([Intel XE#2142]) +1 other test fail
[236]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-lnl-3/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html
[237]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-lnl-7/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html
* igt@panthor/panthor_gem@bo_mmap_offset_invalid_handle:
- shard-bmg: [SKIP][238] ([Intel XE#6530]) -> [SKIP][239] ([Intel XE#6530] / [Intel XE#6557]) +11 other tests skip
[238]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-bmg-5/igt@panthor/panthor_gem@bo_mmap_offset_invalid_handle.html
[239]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-bmg-5/igt@panthor/panthor_gem@bo_mmap_offset_invalid_handle.html
* igt@xe_exec_reset@cm-cat-error:
- shard-adlp: [DMESG-FAIL][240] ([Intel XE#3868]) -> [DMESG-WARN][241] ([Intel XE#3868])
[240]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-adlp-6/igt@xe_exec_reset@cm-cat-error.html
[241]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-2/igt@xe_exec_reset@cm-cat-error.html
* igt@xe_peer2peer@write:
- shard-adlp: [SKIP][242] ([Intel XE#1061] / [Intel XE#5568]) -> [DMESG-FAIL][243] ([Intel XE#5213])
[242]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-adlp-4/igt@xe_peer2peer@write.html
[243]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-1/igt@xe_peer2peer@write.html
* igt@xe_query@multigpu-query-invalid-query:
- shard-adlp: [SKIP][244] ([Intel XE#944]) -> [FAIL][245] ([Intel XE#6249])
[244]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4/shard-adlp-9/igt@xe_query@multigpu-query-invalid-query.html
[245]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/shard-adlp-1/igt@xe_query@multigpu-query-invalid-query.html
[Intel XE#1061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1061
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
[Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
[Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
[Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
[Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
[Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
[Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
[Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
[Intel XE#1466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1466
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
[Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
[Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
[Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
[Intel XE#2142]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2142
[Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
[Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
[Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
[Intel XE#2286]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2286
[Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
[Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
[Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
[Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
[Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
[Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
[Intel XE#2360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2360
[Intel XE#2373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2373
[Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
[Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
[Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
[Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
[Intel XE#261]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/261
[Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
[Intel XE#2705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2705
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
[Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
[Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#3012]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3012
[Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
[Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
[Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
[Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
[Intel XE#310]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/310
[Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
[Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
[Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
[Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
[Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
[Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
[Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
[Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
[Intel XE#356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/356
[Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
[Intel XE#362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/362
[Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
[Intel XE#3868]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3868
[Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
[Intel XE#3908]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3908
[Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
[Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
[Intel XE#4302]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4302
[Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
[Intel XE#4356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4356
[Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
[Intel XE#4488]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4488
[Intel XE#4504]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4504
[Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
[Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
[Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
[Intel XE#4609]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4609
[Intel XE#4633]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4633
[Intel XE#4650]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4650
[Intel XE#4665]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4665
[Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
[Intel XE#4814]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4814
[Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
[Intel XE#4842]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4842
[Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
[Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
[Intel XE#5020]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5020
[Intel XE#5208]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5208
[Intel XE#5213]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5213
[Intel XE#5390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5390
[Intel XE#5488]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5488
[Intel XE#5545]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5545
[Intel XE#5561]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5561
[Intel XE#5564]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5564
[Intel XE#5565]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5565
[Intel XE#5568]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5568
[Intel XE#5575]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5575
[Intel XE#5624]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5624
[Intel XE#5625]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5625
[Intel XE#5626]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5626
[Intel XE#5694]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5694
[Intel XE#5786]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5786
[Intel XE#584]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/584
[Intel XE#5862]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5862
[Intel XE#5893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5893
[Intel XE#5937]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5937
[Intel XE#5993]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5993
[Intel XE#6054]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6054
[Intel XE#610]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/610
[Intel XE#6168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6168
[Intel XE#6249]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6249
[Intel XE#6251]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6251
[Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
[Intel XE#6318]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6318
[Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
[Intel XE#6360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6360
[Intel XE#6362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6362
[Intel XE#6366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6366
[Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
[Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
[Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
[Intel XE#6530]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6530
[Intel XE#6554]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6554
[Intel XE#6557]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6557
[Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
[Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
[Intel XE#701]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/701
[Intel XE#718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/718
[Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
[Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
[Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
[Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
[Intel XE#979]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/979
Build changes
-------------
* IGT: IGT_8615 -> IGT_8616
* Linux: xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4 -> xe-pw-157300v1
IGT_8615: 8615
IGT_8616: 862eb176244feac8ee711f381fe1be1fdc6a7ede @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-4076-568f0845675b0c21185a5441e36c017e2bc095b4: 568f0845675b0c21185a5441e36c017e2bc095b4
xe-pw-157300v1: 157300v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157300v1/index.html
[-- Attachment #2: Type: text/html, Size: 83226 bytes --]
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v3 1/2] drm/i915/ltphy: Implement HDMI Algo for Pll state
2025-11-10 6:19 [PATCH v3 1/2] drm/i915/ltphy: Implement HDMI Algo for Pll state Suraj Kandpal
` (5 preceding siblings ...)
2025-11-10 8:43 ` ✗ Xe.CI.Full: failure " Patchwork
@ 2025-11-10 9:53 ` Nautiyal, Ankit K
2025-11-14 14:45 ` Jani Nikula
7 siblings, 0 replies; 10+ messages in thread
From: Nautiyal, Ankit K @ 2025-11-10 9:53 UTC (permalink / raw)
To: Suraj Kandpal, intel-xe, intel-gfx
On 11/10/2025 11:49 AM, Suraj Kandpal wrote:
> Implement the HDMI Algorithm to dynamically create LT PHY state
> based on the port clock provided.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>
> v1 -> v2:
> -Add new macro functions and definitions for address assignment(Ankit)
> -Introduce a structure lt_phy_param for code readability (Ankit)
>
> v2 ->v3:
> -Seprate out param calulation wherever possible (Ankit)
> -Modify Macro to accept pll_reg (Ankit)
>
> drivers/gpu/drm/i915/display/intel_lt_phy.c | 345 +++++++++++++++++-
> drivers/gpu/drm/i915/display/intel_lt_phy.h | 3 +
> .../gpu/drm/i915/display/intel_lt_phy_regs.h | 16 +
> 3 files changed, 362 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index af48d6cde226..d88dbfbe97b1 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -31,6 +31,32 @@
> #define INTEL_LT_PHY_BOTH_LANES (INTEL_LT_PHY_LANE1 |\
> INTEL_LT_PHY_LANE0)
> #define MODE_DP 3
> +#define Q32_TO_INT(x) ((x) >> 32)
> +#define Q32_TO_FRAC(x) ((x) & 0xFFFFFFFF)
> +#define DCO_MIN_FREQ_MHZ 11850
> +#define REF_CLK_KHZ 38400
> +#define TDC_RES_MULTIPLIER 10000000ULL
> +
> +struct phy_param_t {
> + u32 val;
> + u32 addr;
> +};
> +
> +struct lt_phy_params {
> + struct phy_param_t pll_reg4;
> + struct phy_param_t pll_reg3;
> + struct phy_param_t pll_reg5;
> + struct phy_param_t pll_reg57;
> + struct phy_param_t lf;
> + struct phy_param_t tdc;
> + struct phy_param_t ssc;
> + struct phy_param_t bias2;
> + struct phy_param_t bias_trim;
> + struct phy_param_t dco_med;
> + struct phy_param_t dco_fine;
> + struct phy_param_t ssc_inj;
> + struct phy_param_t surv_bonus;
> +};
>
> static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_rbr = {
> .clock = 162000,
> @@ -1356,10 +1382,322 @@ intel_lt_phy_pll_is_ssc_enabled(struct intel_crtc_state *crtc_state,
> return false;
> }
>
> +static u64 mul_q32_u32(u64 a_q32, u32 b)
> +{
> + u64 p0, p1, carry, result;
> + u64 x_hi = a_q32 >> 32;
> + u64 x_lo = a_q32 & 0xFFFFFFFFULL;
> +
> + p0 = x_lo * (u64)b;
> + p1 = x_hi * (u64)b;
> + carry = p0 >> 32;
> + result = (p1 << 32) + (carry << 32) + (p0 & 0xFFFFFFFFULL);
> +
> + return result;
> +}
> +
> +static bool
> +calculate_target_dco_and_loop_cnt(u32 frequency_khz, u64 *target_dco_mhz, u32 *loop_cnt)
> +{
> + u32 ppm_value = 1;
> + u32 dco_min_freq = DCO_MIN_FREQ_MHZ;
> + u32 dco_max_freq = 16200;
> + u32 dco_min_freq_low = 10000;
> + u32 dco_max_freq_low = 12000;
> + u64 val = 0;
> + u64 refclk_khz = REF_CLK_KHZ;
> + u64 m2div = 0;
> + u64 val_with_frac = 0;
> + u64 ppm = 0;
> + u64 temp0 = 0, temp1, scale;
> + int ppm_cnt, dco_count, y;
> +
> + for (ppm_cnt = 0; ppm_cnt < 5; ppm_cnt++) {
> + ppm_value = ppm_cnt == 2 ? 2 : 1;
> + for (dco_count = 0; dco_count < 2; dco_count++) {
> + if (dco_count == 1) {
> + dco_min_freq = dco_min_freq_low;
> + dco_max_freq = dco_max_freq_low;
> + }
> + for (y = 2; y <= 255; y += 2) {
> + val = div64_u64((u64)y * frequency_khz, 200);
> + m2div = div64_u64(((u64)(val) << 32), refclk_khz);
> + m2div = mul_q32_u32(m2div, 500);
> + val_with_frac = mul_q32_u32(m2div, refclk_khz);
> + val_with_frac = div64_u64(val_with_frac, 500);
> + temp1 = Q32_TO_INT(val_with_frac);
> + temp0 = (temp1 > val) ? (temp1 - val) :
> + (val - temp1);
> + ppm = div64_u64(temp0, val);
> + if (temp1 >= dco_min_freq &&
> + temp1 <= dco_max_freq &&
> + ppm < ppm_value) {
> + /* Round to two places */
> + scale = (1ULL << 32) / 100;
> + temp0 = DIV_ROUND_UP_ULL(val_with_frac,
> + scale);
> + *target_dco_mhz = temp0 * scale;
> + *loop_cnt = y;
> + return true;
> + }
> + }
> + }
> + }
> +
> + return false;
> +}
> +
> +static void set_phy_vdr_addresses(struct lt_phy_params *p, int pll_type)
> +{
> + p->pll_reg4.addr = PLL_REG_ADDR(PLL_REG4_ADDR, pll_type);
> + p->pll_reg3.addr = PLL_REG_ADDR(PLL_REG3_ADDR, pll_type);
> + p->pll_reg5.addr = PLL_REG_ADDR(PLL_REG5_ADDR, pll_type);
> + p->pll_reg57.addr = PLL_REG_ADDR(PLL_REG57_ADDR, pll_type);
> + p->lf.addr = PLL_REG_ADDR(PLL_LF_ADDR, pll_type);
> + p->tdc.addr = PLL_REG_ADDR(PLL_TDC_ADDR, pll_type);
> + p->ssc.addr = PLL_REG_ADDR(PLL_SSC_ADDR, pll_type);
> + p->bias2.addr = PLL_REG_ADDR(PLL_BIAS2_ADDR, pll_type);
> + p->bias_trim.addr = PLL_REG_ADDR(PLL_BIAS_TRIM_ADDR, pll_type);
> + p->dco_med.addr = PLL_REG_ADDR(PLL_DCO_MED_ADDR, pll_type);
> + p->dco_fine.addr = PLL_REG_ADDR(PLL_DCO_FINE_ADDR, pll_type);
> + p->ssc_inj.addr = PLL_REG_ADDR(PLL_SSC_INJ_ADDR, pll_type);
> + p->surv_bonus.addr = PLL_REG_ADDR(PLL_SURV_BONUS_ADDR, pll_type);
> +}
> +
> +static void compute_ssc(struct lt_phy_params *p, u32 ana_cfg)
> +{
> + int ssc_stepsize = 0;
> + int ssc_steplen = 0;
> + int ssc_steplog = 0;
> +
> + p->ssc.val = (1 << 31) | (ana_cfg << 24) | (ssc_steplog << 16) |
> + (ssc_stepsize << 8) | ssc_steplen;
> +}
> +
> +static void compute_bias2(struct lt_phy_params *p)
> +{
> + u32 ssc_en_local = 0;
> + u64 dynctrl_ovrd_en = 0;
> +
> + p->bias2.val = (dynctrl_ovrd_en << 31) | (ssc_en_local << 30) |
> + (1 << 23) | (1 << 24) | (32 << 16) | (1 << 8);
> +}
> +
> +static void compute_tdc(struct lt_phy_params *p, u64 tdc_fine)
> +{
> + u32 settling_time = 15;
> + u32 bias_ovr_en = 1;
> + u32 coldstart = 1;
> + u32 true_lock = 2;
> + u32 early_lock = 1;
> + u32 lock_ovr_en = 1;
> + u32 lock_thr = tdc_fine ? 3 : 5;
> + u32 unlock_thr = tdc_fine ? 5 : 11;
> +
> + p->tdc.val = (u32)((2 << 30) + (settling_time << 16) + (bias_ovr_en << 15) +
> + (lock_ovr_en << 14) + (coldstart << 12) + (true_lock << 10) +
> + (early_lock << 8) + (unlock_thr << 4) + lock_thr);
> +}
> +
> +static void compute_dco_med(struct lt_phy_params *p)
> +{
> + u32 cselmed_en = 0;
> + u32 cselmed_dyn_adj = 0;
> + u32 cselmed_ratio = 39;
> + u32 cselmed_thr = 8;
> +
> + p->dco_med.val = (cselmed_en << 31) + (cselmed_dyn_adj << 30) +
> + (cselmed_ratio << 24) + (cselmed_thr << 21);
> +}
> +
> +static void compute_dco_fine(struct lt_phy_params *p, u32 dco_12g)
> +{
> + u32 dco_fine0_tune_2_0 = 0;
> + u32 dco_fine1_tune_2_0 = 0;
> + u32 dco_fine2_tune_2_0 = 0;
> + u32 dco_fine3_tune_2_0 = 0;
> + u32 dco_dith0_tune_2_0 = 0;
> + u32 dco_dith1_tune_2_0 = 0;
> +
> + dco_fine0_tune_2_0 = dco_12g ? 4 : 3;
> + dco_fine1_tune_2_0 = 2;
> + dco_fine2_tune_2_0 = dco_12g ? 2 : 1;
> + dco_fine3_tune_2_0 = 5;
> + dco_dith0_tune_2_0 = dco_12g ? 4 : 3;
> + dco_dith1_tune_2_0 = 2;
> +
> + p->dco_fine.val = (dco_dith1_tune_2_0 << 19)
> + + (dco_dith0_tune_2_0 << 16)
> + + (dco_fine3_tune_2_0 << 11)
> + + (dco_fine2_tune_2_0 << 8)
> + + (dco_fine1_tune_2_0 << 3)
> + + dco_fine0_tune_2_0;
I think this should have operator at the end:
p.dco_fine.val = (dco_dith1_tune_2_0 << 19) +
(dco_dith0_tune_2_0 << 16) +
(dco_fine3_tune_2_0 << 11) +
(dco_fine2_tune_2_0 << 8) +
(dco_fine1_tune_2_0 << 3) +
dco_fine0_tune_2_0;
> +}
> +
> +int
> +intel_lt_phy_calculate_hdmi_state(struct intel_lt_phy_pll_state *lt_state,
> + u32 frequency_khz)
> +{
> +#define DATA_ASSIGN(i, pll_reg) \
> + do { \
> + lt_state->data[i][0] = (u8)((((pll_reg).val) & 0xFF000000) >> 24); \
> + lt_state->data[i][1] = (u8)((((pll_reg).val) & 0x00FF0000) >> 16); \
> + lt_state->data[i][2] = (u8)((((pll_reg).val) & 0x0000FF00) >> 8); \
> + lt_state->data[i][3] = (u8)((((pll_reg).val) & 0x000000FF)); \
> + } while (0)
> +#define ADDR_ASSIGN(i, pll_reg) \
> + do { \
> + lt_state->addr_msb[i] = ((pll_reg).addr >> 8) & 0xFF; \
> + lt_state->addr_lsb[i] = (pll_reg).addr & 0xFF; \
> + } while (0)
> +
> + bool found = false;
> + struct lt_phy_params p;
> + u32 dco_fmin = DCO_MIN_FREQ_MHZ;
> + u64 refclk_khz = REF_CLK_KHZ;
> + u64 m2div = 0;
> + u64 target_dco_mhz = 0;
> + u64 tdc_fine;
> + u64 tdc_targetcnt;
I think the variables which have same context can be grouped together
like below:
u64 tdc_fine, tdc_targetcnt;
> + u64 feedfwd_gain;
> + u64 feedfwd_cal_en;
u64 feedfwd_gain, feedfwd_cal_en;
> + u64 tdc_res = 30;
> + u32 prop_coeff;
> + u32 int_coeff;
> + u32 ndiv = 1;
> + u32 m1div = 1;
> + u32 m2div_int;
> + u32 m2div_frac;
These 3 can come in same line:
> + u32 frac_en;
> + u32 ana_cfg;
> + u32 loop_cnt = 0;
> + u32 gain_ctrl = 2;
> + u32 refclk_mhz_int = 38;
u32 refclk_mhz_int = REF_CLK_KHZ / 1000;
Can be moved near to u64 refclk_khz above.
> + u32 postdiv = 0;
> + u32 d6_new = 0;
> + u32 dco_12g = 0;
> + u32 pll_type = 0;
> + u32 d1 = 2;
> + u32 d3 = 5;
> + u32 d5 = 0;
> + u32 d6 = 0;
> + u32 d7;
> + u32 d8 = 0;
> + u32 d4 = 0;
All of these can be be grouped together including the d6_new above:
u32 d1 = 2, d3 = 5, d4 = 0, d5 = 0;
u32 d6 = 0, d6_new = 0;
u32 d7, d8 = 0;
> + u32 bonus_7_0 = 0;
> + u32 csel2fo = 11;
> + u32 csel2fo_ovrd_en = 1;
> + u64 temp0, temp1, temp2, temp3;
> +
> + p.surv_bonus.val = (bonus_7_0 << 16);
> + p.pll_reg4.val = (refclk_mhz_int << 17) +
> + (ndiv << 9) + (1 << 4);
> + p.bias_trim.val = (csel2fo_ovrd_en << 30) + (csel2fo << 24);
> + p.ssc_inj.val = 0;
> + found = calculate_target_dco_and_loop_cnt(frequency_khz, &target_dco_mhz, &loop_cnt);
> + if (!found)
> + return -EINVAL;
> +
> + m2div = div64_u64(target_dco_mhz, (refclk_khz * ndiv * m1div));
> + m2div = mul_q32_u32(m2div, 1000);
> + if (Q32_TO_INT(m2div) > 511)
> + return -EINVAL;
> +
> + m2div_int = (u32)Q32_TO_INT(m2div);
> + m2div_frac = (u32)(Q32_TO_FRAC(m2div));
> + frac_en = (m2div_frac > 0) ? 1 : 0;
> +
> + if (frac_en > 0)
> + tdc_res = 70;
> + else
> + tdc_res = 36;
> + tdc_fine = tdc_res > 50 ? 1 : 0;
> + temp0 = tdc_res * 40 * 11;
> + temp1 = div64_u64(((4 * TDC_RES_MULTIPLIER) + temp0) * 500, temp0 * refclk_khz);
> + temp2 = div64_u64(temp0 * refclk_khz, 1000);
> + temp3 = div64_u64(((8 * TDC_RES_MULTIPLIER) + temp2), temp2);
> + tdc_targetcnt = tdc_res < 50 ? (int)(temp1) : (int)(temp3);
> + tdc_targetcnt = (int)(tdc_targetcnt / 2);
> + temp0 = mul_q32_u32(target_dco_mhz, tdc_res);
> + temp0 >>= 32;
> + feedfwd_gain = (m2div_frac > 0) ? div64_u64(m1div * TDC_RES_MULTIPLIER, temp0) : 0;
> + feedfwd_cal_en = frac_en;
> +
> + temp0 = (u32)Q32_TO_INT(target_dco_mhz);
> + prop_coeff = (temp0 >= dco_fmin) ? 3 : 4;
> + int_coeff = (temp0 >= dco_fmin) ? 7 : 8;
> + ana_cfg = (temp0 >= dco_fmin) ? 8 : 6;
> + dco_12g = (temp0 >= dco_fmin) ? 0 : 1;
> +
> + if (temp0 > 12960)
> + d7 = 10;
> + else
> + d7 = 8;
> +
> + d8 = loop_cnt / 2;
> + d4 = d8 * 2;
> +
> + /* Compute pll_reg3,5,57 & lf */
> + p.pll_reg3.val = (u32)((d4 << 21) + (d3 << 18) + (d1 << 15) + (m2div_int << 5));
> + p.pll_reg5.val = m2div_frac;
> + postdiv = (d5 == 0) ? 9 : d5;
> + d6_new = (d6 == 0) ? 40 : d6;
> + p.pll_reg57.val = (d7 << 24) + (postdiv << 15) + (d8 << 7) + d6_new;
> + p.lf.val = (u32)((frac_en << 31) + (1 << 30) + (frac_en << 29) +
> + (feedfwd_cal_en << 28) + (tdc_fine << 27) +
> + (gain_ctrl << 24) + (feedfwd_gain << 16) +
> + (int_coeff << 12) + (prop_coeff << 8) + tdc_targetcnt);
> +
> + /* Compute ssc / bias2 */
> + compute_ssc(&p, ana_cfg);
> + compute_bias2(&p);
> +
> + /* Compute tdc/dco_med */
> + compute_tdc(&p, tdc_fine);
> + compute_dco_med(&p);
> +
> + /* Compute dcofine */
Now I think we can do away with the comments above.
With the minor changes suggested above the patch looks good to me.
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
I was thinking if we should have a separate file for this, similar to
one for snps phy hdmi plls, but in that case we were using it for snps
PHY and C10 phy which have similar algorithm.
In the present LT PHY case it might be not a be a good idea for now.
Regards,
Ankit
> + compute_dco_fine(&p, dco_12g);
> +
> + pll_type = ((frequency_khz == 10000) || (frequency_khz == 20000) ||
> + (frequency_khz == 2500) || (dco_12g == 1)) ? 0 : 1;
> + set_phy_vdr_addresses(&p, pll_type);
> +
> + lt_state->config[0] = 0x84;
> + lt_state->config[1] = 0x2d;
> + ADDR_ASSIGN(0, p.pll_reg4);
> + ADDR_ASSIGN(1, p.pll_reg3);
> + ADDR_ASSIGN(2, p.pll_reg5);
> + ADDR_ASSIGN(3, p.pll_reg57);
> + ADDR_ASSIGN(4, p.lf);
> + ADDR_ASSIGN(5, p.tdc);
> + ADDR_ASSIGN(6, p.ssc);
> + ADDR_ASSIGN(7, p.bias2);
> + ADDR_ASSIGN(8, p.bias_trim);
> + ADDR_ASSIGN(9, p.dco_med);
> + ADDR_ASSIGN(10, p.dco_fine);
> + ADDR_ASSIGN(11, p.ssc_inj);
> + ADDR_ASSIGN(12, p.surv_bonus);
> + DATA_ASSIGN(0, p.pll_reg4);
> + DATA_ASSIGN(1, p.pll_reg3);
> + DATA_ASSIGN(2, p.pll_reg5);
> + DATA_ASSIGN(3, p.pll_reg57);
> + DATA_ASSIGN(4, p.lf);
> + DATA_ASSIGN(5, p.tdc);
> + DATA_ASSIGN(6, p.ssc);
> + DATA_ASSIGN(7, p.bias2);
> + DATA_ASSIGN(8, p.bias_trim);
> + DATA_ASSIGN(9, p.dco_med);
> + DATA_ASSIGN(10, p.dco_fine);
> + DATA_ASSIGN(11, p.ssc_inj);
> + DATA_ASSIGN(12, p.surv_bonus);
> +
> + return 0;
> +}
> +
> static int
> intel_lt_phy_calc_hdmi_port_clock(const struct intel_lt_phy_pll_state *lt_state)
> {
> -#define REF_CLK_KHZ 38400
> #define REGVAL(i) ( \
> (lt_state->data[i][3]) | \
> (lt_state->data[i][2] << 8) | \
> @@ -1472,7 +1810,10 @@ intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
> }
> }
>
> - /* TODO: Add a function to compute the data for HDMI TMDS*/
> + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
> + return intel_lt_phy_calculate_hdmi_state(&crtc_state->dpll_hw_state.ltpll,
> + crtc_state->port_clock);
> + }
>
> return -EINVAL;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> index a538d4c69210..b7911acd7dcd 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> @@ -35,6 +35,9 @@ void intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
> struct intel_lt_phy_pll_state *pll_state);
> void intel_lt_phy_pll_state_verify(struct intel_atomic_state *state,
> struct intel_crtc *crtc);
> +int
> +intel_lt_phy_calculate_hdmi_state(struct intel_lt_phy_pll_state *lt_state,
> + u32 frequency_khz);
> void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state);
> void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> index 9223487d764e..dc7b7679cd06 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> @@ -72,4 +72,20 @@
> #define XE3PLPD_PORT_P2M_MSGBUS_STATUS_P2P(port, lane) _XE3PLPD_PORT_P2M_MSGBUS_STATUS_P2P(__xe2lpd_port_idx(port), \
> lane)
> #define XE3LPD_PORT_P2M_ADDR_MASK REG_GENMASK(11, 0)
> +
> +#define PLL_REG4_ADDR 0x8510
> +#define PLL_REG3_ADDR 0x850C
> +#define PLL_REG5_ADDR 0x8514
> +#define PLL_REG57_ADDR 0x85E4
> +#define PLL_LF_ADDR 0x860C
> +#define PLL_TDC_ADDR 0x8610
> +#define PLL_SSC_ADDR 0x8614
> +#define PLL_BIAS2_ADDR 0x8618
> +#define PLL_BIAS_TRIM_ADDR 0x8648
> +#define PLL_DCO_MED_ADDR 0x8640
> +#define PLL_DCO_FINE_ADDR 0x864C
> +#define PLL_SSC_INJ_ADDR 0x8624
> +#define PLL_SURV_BONUS_ADDR 0x8644
> +#define PLL_TYPE_OFFSET 0x200
> +#define PLL_REG_ADDR(base, pll_type) ((pll_type) ? (base) + PLL_TYPE_OFFSET : (base))
> #endif /* __INTEL_LT_PHY_REGS_H__ */
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v3 1/2] drm/i915/ltphy: Implement HDMI Algo for Pll state
2025-11-10 6:19 [PATCH v3 1/2] drm/i915/ltphy: Implement HDMI Algo for Pll state Suraj Kandpal
` (6 preceding siblings ...)
2025-11-10 9:53 ` [PATCH v3 1/2] " Nautiyal, Ankit K
@ 2025-11-14 14:45 ` Jani Nikula
2025-11-17 4:59 ` Kandpal, Suraj
7 siblings, 1 reply; 10+ messages in thread
From: Jani Nikula @ 2025-11-14 14:45 UTC (permalink / raw)
To: Suraj Kandpal, intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, Suraj Kandpal
On Mon, 10 Nov 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Implement the HDMI Algorithm to dynamically create LT PHY state
> based on the port clock provided.
I know this has been merged already... because I encountered it while
trying to write a pull request changelog.
I have no idea what the commit is supposed to do based on the commit
message alone. Yes, I can (and now have) looked at the code, but please
be more elaborate in the commit messages.
For patch 2, I read the code and I still don't know what it's doing, and
what the fallback is, or why.
BR,
Jani.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>
> v1 -> v2:
> -Add new macro functions and definitions for address assignment(Ankit)
> -Introduce a structure lt_phy_param for code readability (Ankit)
>
> v2 ->v3:
> -Seprate out param calulation wherever possible (Ankit)
> -Modify Macro to accept pll_reg (Ankit)
>
> drivers/gpu/drm/i915/display/intel_lt_phy.c | 345 +++++++++++++++++-
> drivers/gpu/drm/i915/display/intel_lt_phy.h | 3 +
> .../gpu/drm/i915/display/intel_lt_phy_regs.h | 16 +
> 3 files changed, 362 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index af48d6cde226..d88dbfbe97b1 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -31,6 +31,32 @@
> #define INTEL_LT_PHY_BOTH_LANES (INTEL_LT_PHY_LANE1 |\
> INTEL_LT_PHY_LANE0)
> #define MODE_DP 3
> +#define Q32_TO_INT(x) ((x) >> 32)
> +#define Q32_TO_FRAC(x) ((x) & 0xFFFFFFFF)
> +#define DCO_MIN_FREQ_MHZ 11850
> +#define REF_CLK_KHZ 38400
> +#define TDC_RES_MULTIPLIER 10000000ULL
> +
> +struct phy_param_t {
> + u32 val;
> + u32 addr;
> +};
> +
> +struct lt_phy_params {
> + struct phy_param_t pll_reg4;
> + struct phy_param_t pll_reg3;
> + struct phy_param_t pll_reg5;
> + struct phy_param_t pll_reg57;
> + struct phy_param_t lf;
> + struct phy_param_t tdc;
> + struct phy_param_t ssc;
> + struct phy_param_t bias2;
> + struct phy_param_t bias_trim;
> + struct phy_param_t dco_med;
> + struct phy_param_t dco_fine;
> + struct phy_param_t ssc_inj;
> + struct phy_param_t surv_bonus;
> +};
>
> static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_rbr = {
> .clock = 162000,
> @@ -1356,10 +1382,322 @@ intel_lt_phy_pll_is_ssc_enabled(struct intel_crtc_state *crtc_state,
> return false;
> }
>
> +static u64 mul_q32_u32(u64 a_q32, u32 b)
> +{
> + u64 p0, p1, carry, result;
> + u64 x_hi = a_q32 >> 32;
> + u64 x_lo = a_q32 & 0xFFFFFFFFULL;
> +
> + p0 = x_lo * (u64)b;
> + p1 = x_hi * (u64)b;
> + carry = p0 >> 32;
> + result = (p1 << 32) + (carry << 32) + (p0 & 0xFFFFFFFFULL);
> +
> + return result;
> +}
> +
> +static bool
> +calculate_target_dco_and_loop_cnt(u32 frequency_khz, u64 *target_dco_mhz, u32 *loop_cnt)
> +{
> + u32 ppm_value = 1;
> + u32 dco_min_freq = DCO_MIN_FREQ_MHZ;
> + u32 dco_max_freq = 16200;
> + u32 dco_min_freq_low = 10000;
> + u32 dco_max_freq_low = 12000;
> + u64 val = 0;
> + u64 refclk_khz = REF_CLK_KHZ;
> + u64 m2div = 0;
> + u64 val_with_frac = 0;
> + u64 ppm = 0;
> + u64 temp0 = 0, temp1, scale;
> + int ppm_cnt, dco_count, y;
> +
> + for (ppm_cnt = 0; ppm_cnt < 5; ppm_cnt++) {
> + ppm_value = ppm_cnt == 2 ? 2 : 1;
> + for (dco_count = 0; dco_count < 2; dco_count++) {
> + if (dco_count == 1) {
> + dco_min_freq = dco_min_freq_low;
> + dco_max_freq = dco_max_freq_low;
> + }
> + for (y = 2; y <= 255; y += 2) {
> + val = div64_u64((u64)y * frequency_khz, 200);
> + m2div = div64_u64(((u64)(val) << 32), refclk_khz);
> + m2div = mul_q32_u32(m2div, 500);
> + val_with_frac = mul_q32_u32(m2div, refclk_khz);
> + val_with_frac = div64_u64(val_with_frac, 500);
> + temp1 = Q32_TO_INT(val_with_frac);
> + temp0 = (temp1 > val) ? (temp1 - val) :
> + (val - temp1);
> + ppm = div64_u64(temp0, val);
> + if (temp1 >= dco_min_freq &&
> + temp1 <= dco_max_freq &&
> + ppm < ppm_value) {
> + /* Round to two places */
> + scale = (1ULL << 32) / 100;
> + temp0 = DIV_ROUND_UP_ULL(val_with_frac,
> + scale);
> + *target_dco_mhz = temp0 * scale;
> + *loop_cnt = y;
> + return true;
> + }
> + }
> + }
> + }
> +
> + return false;
> +}
> +
> +static void set_phy_vdr_addresses(struct lt_phy_params *p, int pll_type)
> +{
> + p->pll_reg4.addr = PLL_REG_ADDR(PLL_REG4_ADDR, pll_type);
> + p->pll_reg3.addr = PLL_REG_ADDR(PLL_REG3_ADDR, pll_type);
> + p->pll_reg5.addr = PLL_REG_ADDR(PLL_REG5_ADDR, pll_type);
> + p->pll_reg57.addr = PLL_REG_ADDR(PLL_REG57_ADDR, pll_type);
> + p->lf.addr = PLL_REG_ADDR(PLL_LF_ADDR, pll_type);
> + p->tdc.addr = PLL_REG_ADDR(PLL_TDC_ADDR, pll_type);
> + p->ssc.addr = PLL_REG_ADDR(PLL_SSC_ADDR, pll_type);
> + p->bias2.addr = PLL_REG_ADDR(PLL_BIAS2_ADDR, pll_type);
> + p->bias_trim.addr = PLL_REG_ADDR(PLL_BIAS_TRIM_ADDR, pll_type);
> + p->dco_med.addr = PLL_REG_ADDR(PLL_DCO_MED_ADDR, pll_type);
> + p->dco_fine.addr = PLL_REG_ADDR(PLL_DCO_FINE_ADDR, pll_type);
> + p->ssc_inj.addr = PLL_REG_ADDR(PLL_SSC_INJ_ADDR, pll_type);
> + p->surv_bonus.addr = PLL_REG_ADDR(PLL_SURV_BONUS_ADDR, pll_type);
> +}
> +
> +static void compute_ssc(struct lt_phy_params *p, u32 ana_cfg)
> +{
> + int ssc_stepsize = 0;
> + int ssc_steplen = 0;
> + int ssc_steplog = 0;
> +
> + p->ssc.val = (1 << 31) | (ana_cfg << 24) | (ssc_steplog << 16) |
> + (ssc_stepsize << 8) | ssc_steplen;
> +}
> +
> +static void compute_bias2(struct lt_phy_params *p)
> +{
> + u32 ssc_en_local = 0;
> + u64 dynctrl_ovrd_en = 0;
> +
> + p->bias2.val = (dynctrl_ovrd_en << 31) | (ssc_en_local << 30) |
> + (1 << 23) | (1 << 24) | (32 << 16) | (1 << 8);
> +}
> +
> +static void compute_tdc(struct lt_phy_params *p, u64 tdc_fine)
> +{
> + u32 settling_time = 15;
> + u32 bias_ovr_en = 1;
> + u32 coldstart = 1;
> + u32 true_lock = 2;
> + u32 early_lock = 1;
> + u32 lock_ovr_en = 1;
> + u32 lock_thr = tdc_fine ? 3 : 5;
> + u32 unlock_thr = tdc_fine ? 5 : 11;
> +
> + p->tdc.val = (u32)((2 << 30) + (settling_time << 16) + (bias_ovr_en << 15) +
> + (lock_ovr_en << 14) + (coldstart << 12) + (true_lock << 10) +
> + (early_lock << 8) + (unlock_thr << 4) + lock_thr);
> +}
> +
> +static void compute_dco_med(struct lt_phy_params *p)
> +{
> + u32 cselmed_en = 0;
> + u32 cselmed_dyn_adj = 0;
> + u32 cselmed_ratio = 39;
> + u32 cselmed_thr = 8;
> +
> + p->dco_med.val = (cselmed_en << 31) + (cselmed_dyn_adj << 30) +
> + (cselmed_ratio << 24) + (cselmed_thr << 21);
> +}
> +
> +static void compute_dco_fine(struct lt_phy_params *p, u32 dco_12g)
> +{
> + u32 dco_fine0_tune_2_0 = 0;
> + u32 dco_fine1_tune_2_0 = 0;
> + u32 dco_fine2_tune_2_0 = 0;
> + u32 dco_fine3_tune_2_0 = 0;
> + u32 dco_dith0_tune_2_0 = 0;
> + u32 dco_dith1_tune_2_0 = 0;
> +
> + dco_fine0_tune_2_0 = dco_12g ? 4 : 3;
> + dco_fine1_tune_2_0 = 2;
> + dco_fine2_tune_2_0 = dco_12g ? 2 : 1;
> + dco_fine3_tune_2_0 = 5;
> + dco_dith0_tune_2_0 = dco_12g ? 4 : 3;
> + dco_dith1_tune_2_0 = 2;
> +
> + p->dco_fine.val = (dco_dith1_tune_2_0 << 19)
> + + (dco_dith0_tune_2_0 << 16)
> + + (dco_fine3_tune_2_0 << 11)
> + + (dco_fine2_tune_2_0 << 8)
> + + (dco_fine1_tune_2_0 << 3)
> + + dco_fine0_tune_2_0;
> +}
> +
> +int
> +intel_lt_phy_calculate_hdmi_state(struct intel_lt_phy_pll_state *lt_state,
> + u32 frequency_khz)
> +{
> +#define DATA_ASSIGN(i, pll_reg) \
> + do { \
> + lt_state->data[i][0] = (u8)((((pll_reg).val) & 0xFF000000) >> 24); \
> + lt_state->data[i][1] = (u8)((((pll_reg).val) & 0x00FF0000) >> 16); \
> + lt_state->data[i][2] = (u8)((((pll_reg).val) & 0x0000FF00) >> 8); \
> + lt_state->data[i][3] = (u8)((((pll_reg).val) & 0x000000FF)); \
> + } while (0)
> +#define ADDR_ASSIGN(i, pll_reg) \
> + do { \
> + lt_state->addr_msb[i] = ((pll_reg).addr >> 8) & 0xFF; \
> + lt_state->addr_lsb[i] = (pll_reg).addr & 0xFF; \
> + } while (0)
> +
> + bool found = false;
> + struct lt_phy_params p;
> + u32 dco_fmin = DCO_MIN_FREQ_MHZ;
> + u64 refclk_khz = REF_CLK_KHZ;
> + u64 m2div = 0;
> + u64 target_dco_mhz = 0;
> + u64 tdc_fine;
> + u64 tdc_targetcnt;
> + u64 feedfwd_gain;
> + u64 feedfwd_cal_en;
> + u64 tdc_res = 30;
> + u32 prop_coeff;
> + u32 int_coeff;
> + u32 ndiv = 1;
> + u32 m1div = 1;
> + u32 m2div_int;
> + u32 m2div_frac;
> + u32 frac_en;
> + u32 ana_cfg;
> + u32 loop_cnt = 0;
> + u32 gain_ctrl = 2;
> + u32 refclk_mhz_int = 38;
> + u32 postdiv = 0;
> + u32 d6_new = 0;
> + u32 dco_12g = 0;
> + u32 pll_type = 0;
> + u32 d1 = 2;
> + u32 d3 = 5;
> + u32 d5 = 0;
> + u32 d6 = 0;
> + u32 d7;
> + u32 d8 = 0;
> + u32 d4 = 0;
> + u32 bonus_7_0 = 0;
> + u32 csel2fo = 11;
> + u32 csel2fo_ovrd_en = 1;
> + u64 temp0, temp1, temp2, temp3;
> +
> + p.surv_bonus.val = (bonus_7_0 << 16);
> + p.pll_reg4.val = (refclk_mhz_int << 17) +
> + (ndiv << 9) + (1 << 4);
> + p.bias_trim.val = (csel2fo_ovrd_en << 30) + (csel2fo << 24);
> + p.ssc_inj.val = 0;
> + found = calculate_target_dco_and_loop_cnt(frequency_khz, &target_dco_mhz, &loop_cnt);
> + if (!found)
> + return -EINVAL;
> +
> + m2div = div64_u64(target_dco_mhz, (refclk_khz * ndiv * m1div));
> + m2div = mul_q32_u32(m2div, 1000);
> + if (Q32_TO_INT(m2div) > 511)
> + return -EINVAL;
> +
> + m2div_int = (u32)Q32_TO_INT(m2div);
> + m2div_frac = (u32)(Q32_TO_FRAC(m2div));
> + frac_en = (m2div_frac > 0) ? 1 : 0;
> +
> + if (frac_en > 0)
> + tdc_res = 70;
> + else
> + tdc_res = 36;
> + tdc_fine = tdc_res > 50 ? 1 : 0;
> + temp0 = tdc_res * 40 * 11;
> + temp1 = div64_u64(((4 * TDC_RES_MULTIPLIER) + temp0) * 500, temp0 * refclk_khz);
> + temp2 = div64_u64(temp0 * refclk_khz, 1000);
> + temp3 = div64_u64(((8 * TDC_RES_MULTIPLIER) + temp2), temp2);
> + tdc_targetcnt = tdc_res < 50 ? (int)(temp1) : (int)(temp3);
> + tdc_targetcnt = (int)(tdc_targetcnt / 2);
> + temp0 = mul_q32_u32(target_dco_mhz, tdc_res);
> + temp0 >>= 32;
> + feedfwd_gain = (m2div_frac > 0) ? div64_u64(m1div * TDC_RES_MULTIPLIER, temp0) : 0;
> + feedfwd_cal_en = frac_en;
> +
> + temp0 = (u32)Q32_TO_INT(target_dco_mhz);
> + prop_coeff = (temp0 >= dco_fmin) ? 3 : 4;
> + int_coeff = (temp0 >= dco_fmin) ? 7 : 8;
> + ana_cfg = (temp0 >= dco_fmin) ? 8 : 6;
> + dco_12g = (temp0 >= dco_fmin) ? 0 : 1;
> +
> + if (temp0 > 12960)
> + d7 = 10;
> + else
> + d7 = 8;
> +
> + d8 = loop_cnt / 2;
> + d4 = d8 * 2;
> +
> + /* Compute pll_reg3,5,57 & lf */
> + p.pll_reg3.val = (u32)((d4 << 21) + (d3 << 18) + (d1 << 15) + (m2div_int << 5));
> + p.pll_reg5.val = m2div_frac;
> + postdiv = (d5 == 0) ? 9 : d5;
> + d6_new = (d6 == 0) ? 40 : d6;
> + p.pll_reg57.val = (d7 << 24) + (postdiv << 15) + (d8 << 7) + d6_new;
> + p.lf.val = (u32)((frac_en << 31) + (1 << 30) + (frac_en << 29) +
> + (feedfwd_cal_en << 28) + (tdc_fine << 27) +
> + (gain_ctrl << 24) + (feedfwd_gain << 16) +
> + (int_coeff << 12) + (prop_coeff << 8) + tdc_targetcnt);
> +
> + /* Compute ssc / bias2 */
> + compute_ssc(&p, ana_cfg);
> + compute_bias2(&p);
> +
> + /* Compute tdc/dco_med */
> + compute_tdc(&p, tdc_fine);
> + compute_dco_med(&p);
> +
> + /* Compute dcofine */
> + compute_dco_fine(&p, dco_12g);
> +
> + pll_type = ((frequency_khz == 10000) || (frequency_khz == 20000) ||
> + (frequency_khz == 2500) || (dco_12g == 1)) ? 0 : 1;
> + set_phy_vdr_addresses(&p, pll_type);
> +
> + lt_state->config[0] = 0x84;
> + lt_state->config[1] = 0x2d;
> + ADDR_ASSIGN(0, p.pll_reg4);
> + ADDR_ASSIGN(1, p.pll_reg3);
> + ADDR_ASSIGN(2, p.pll_reg5);
> + ADDR_ASSIGN(3, p.pll_reg57);
> + ADDR_ASSIGN(4, p.lf);
> + ADDR_ASSIGN(5, p.tdc);
> + ADDR_ASSIGN(6, p.ssc);
> + ADDR_ASSIGN(7, p.bias2);
> + ADDR_ASSIGN(8, p.bias_trim);
> + ADDR_ASSIGN(9, p.dco_med);
> + ADDR_ASSIGN(10, p.dco_fine);
> + ADDR_ASSIGN(11, p.ssc_inj);
> + ADDR_ASSIGN(12, p.surv_bonus);
> + DATA_ASSIGN(0, p.pll_reg4);
> + DATA_ASSIGN(1, p.pll_reg3);
> + DATA_ASSIGN(2, p.pll_reg5);
> + DATA_ASSIGN(3, p.pll_reg57);
> + DATA_ASSIGN(4, p.lf);
> + DATA_ASSIGN(5, p.tdc);
> + DATA_ASSIGN(6, p.ssc);
> + DATA_ASSIGN(7, p.bias2);
> + DATA_ASSIGN(8, p.bias_trim);
> + DATA_ASSIGN(9, p.dco_med);
> + DATA_ASSIGN(10, p.dco_fine);
> + DATA_ASSIGN(11, p.ssc_inj);
> + DATA_ASSIGN(12, p.surv_bonus);
> +
> + return 0;
> +}
> +
> static int
> intel_lt_phy_calc_hdmi_port_clock(const struct intel_lt_phy_pll_state *lt_state)
> {
> -#define REF_CLK_KHZ 38400
> #define REGVAL(i) ( \
> (lt_state->data[i][3]) | \
> (lt_state->data[i][2] << 8) | \
> @@ -1472,7 +1810,10 @@ intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
> }
> }
>
> - /* TODO: Add a function to compute the data for HDMI TMDS*/
> + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
> + return intel_lt_phy_calculate_hdmi_state(&crtc_state->dpll_hw_state.ltpll,
> + crtc_state->port_clock);
> + }
>
> return -EINVAL;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> index a538d4c69210..b7911acd7dcd 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> @@ -35,6 +35,9 @@ void intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
> struct intel_lt_phy_pll_state *pll_state);
> void intel_lt_phy_pll_state_verify(struct intel_atomic_state *state,
> struct intel_crtc *crtc);
> +int
> +intel_lt_phy_calculate_hdmi_state(struct intel_lt_phy_pll_state *lt_state,
> + u32 frequency_khz);
> void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state);
> void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> index 9223487d764e..dc7b7679cd06 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> @@ -72,4 +72,20 @@
> #define XE3PLPD_PORT_P2M_MSGBUS_STATUS_P2P(port, lane) _XE3PLPD_PORT_P2M_MSGBUS_STATUS_P2P(__xe2lpd_port_idx(port), \
> lane)
> #define XE3LPD_PORT_P2M_ADDR_MASK REG_GENMASK(11, 0)
> +
> +#define PLL_REG4_ADDR 0x8510
> +#define PLL_REG3_ADDR 0x850C
> +#define PLL_REG5_ADDR 0x8514
> +#define PLL_REG57_ADDR 0x85E4
> +#define PLL_LF_ADDR 0x860C
> +#define PLL_TDC_ADDR 0x8610
> +#define PLL_SSC_ADDR 0x8614
> +#define PLL_BIAS2_ADDR 0x8618
> +#define PLL_BIAS_TRIM_ADDR 0x8648
> +#define PLL_DCO_MED_ADDR 0x8640
> +#define PLL_DCO_FINE_ADDR 0x864C
> +#define PLL_SSC_INJ_ADDR 0x8624
> +#define PLL_SURV_BONUS_ADDR 0x8644
> +#define PLL_TYPE_OFFSET 0x200
> +#define PLL_REG_ADDR(base, pll_type) ((pll_type) ? (base) + PLL_TYPE_OFFSET : (base))
> #endif /* __INTEL_LT_PHY_REGS_H__ */
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 10+ messages in thread
* RE: [PATCH v3 1/2] drm/i915/ltphy: Implement HDMI Algo for Pll state
2025-11-14 14:45 ` Jani Nikula
@ 2025-11-17 4:59 ` Kandpal, Suraj
0 siblings, 0 replies; 10+ messages in thread
From: Kandpal, Suraj @ 2025-11-17 4:59 UTC (permalink / raw)
To: Jani Nikula, intel-xe@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org
Cc: Nautiyal, Ankit K
> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Friday, November 14, 2025 8:15 PM
> To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-
> xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Kandpal, Suraj
> <suraj.kandpal@intel.com>
> Subject: Re: [PATCH v3 1/2] drm/i915/ltphy: Implement HDMI Algo for Pll
> state
>
> On Mon, 10 Nov 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> > Implement the HDMI Algorithm to dynamically create LT PHY state based
> > on the port clock provided.
>
> I know this has been merged already... because I encountered it while trying
> to write a pull request changelog.
>
> I have no idea what the commit is supposed to do based on the commit
> message alone. Yes, I can (and now have) looked at the code, but please be
> more elaborate in the commit messages.
>
> For patch 2, I read the code and I still don't know what it's doing, and what
> the fallback is, or why.
Sure will be more descriptive with the commit messages going forward.
For the second patch the idea was to not have a hang because of divide by 0 error when
port clock is returned as 0. Hence we return the lowest HDMI clock. We anyways have warning in
place which will tell us something has gone wrong.
Regards,
Suraj Kandpal
>
>
> BR,
> Jani.
>
>
>
>
> >
> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > ---
> >
> > v1 -> v2:
> > -Add new macro functions and definitions for address assignment(Ankit)
> > -Introduce a structure lt_phy_param for code readability (Ankit)
> >
> > v2 ->v3:
> > -Seprate out param calulation wherever possible (Ankit) -Modify Macro
> > to accept pll_reg (Ankit)
> >
> > drivers/gpu/drm/i915/display/intel_lt_phy.c | 345 +++++++++++++++++-
> > drivers/gpu/drm/i915/display/intel_lt_phy.h | 3 +
> > .../gpu/drm/i915/display/intel_lt_phy_regs.h | 16 +
> > 3 files changed, 362 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > index af48d6cde226..d88dbfbe97b1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > @@ -31,6 +31,32 @@
> > #define INTEL_LT_PHY_BOTH_LANES (INTEL_LT_PHY_LANE1 |\
> > INTEL_LT_PHY_LANE0)
> > #define MODE_DP 3
> > +#define Q32_TO_INT(x) ((x) >> 32)
> > +#define Q32_TO_FRAC(x) ((x) & 0xFFFFFFFF)
> > +#define DCO_MIN_FREQ_MHZ 11850
> > +#define REF_CLK_KHZ 38400
> > +#define TDC_RES_MULTIPLIER 10000000ULL
> > +
> > +struct phy_param_t {
> > + u32 val;
> > + u32 addr;
> > +};
> > +
> > +struct lt_phy_params {
> > + struct phy_param_t pll_reg4;
> > + struct phy_param_t pll_reg3;
> > + struct phy_param_t pll_reg5;
> > + struct phy_param_t pll_reg57;
> > + struct phy_param_t lf;
> > + struct phy_param_t tdc;
> > + struct phy_param_t ssc;
> > + struct phy_param_t bias2;
> > + struct phy_param_t bias_trim;
> > + struct phy_param_t dco_med;
> > + struct phy_param_t dco_fine;
> > + struct phy_param_t ssc_inj;
> > + struct phy_param_t surv_bonus;
> > +};
> >
> > static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_rbr = {
> > .clock = 162000,
> > @@ -1356,10 +1382,322 @@ intel_lt_phy_pll_is_ssc_enabled(struct
> intel_crtc_state *crtc_state,
> > return false;
> > }
> >
> > +static u64 mul_q32_u32(u64 a_q32, u32 b) {
> > + u64 p0, p1, carry, result;
> > + u64 x_hi = a_q32 >> 32;
> > + u64 x_lo = a_q32 & 0xFFFFFFFFULL;
> > +
> > + p0 = x_lo * (u64)b;
> > + p1 = x_hi * (u64)b;
> > + carry = p0 >> 32;
> > + result = (p1 << 32) + (carry << 32) + (p0 & 0xFFFFFFFFULL);
> > +
> > + return result;
> > +}
> > +
> > +static bool
> > +calculate_target_dco_and_loop_cnt(u32 frequency_khz, u64
> > +*target_dco_mhz, u32 *loop_cnt) {
> > + u32 ppm_value = 1;
> > + u32 dco_min_freq = DCO_MIN_FREQ_MHZ;
> > + u32 dco_max_freq = 16200;
> > + u32 dco_min_freq_low = 10000;
> > + u32 dco_max_freq_low = 12000;
> > + u64 val = 0;
> > + u64 refclk_khz = REF_CLK_KHZ;
> > + u64 m2div = 0;
> > + u64 val_with_frac = 0;
> > + u64 ppm = 0;
> > + u64 temp0 = 0, temp1, scale;
> > + int ppm_cnt, dco_count, y;
> > +
> > + for (ppm_cnt = 0; ppm_cnt < 5; ppm_cnt++) {
> > + ppm_value = ppm_cnt == 2 ? 2 : 1;
> > + for (dco_count = 0; dco_count < 2; dco_count++) {
> > + if (dco_count == 1) {
> > + dco_min_freq = dco_min_freq_low;
> > + dco_max_freq = dco_max_freq_low;
> > + }
> > + for (y = 2; y <= 255; y += 2) {
> > + val = div64_u64((u64)y * frequency_khz,
> 200);
> > + m2div = div64_u64(((u64)(val) << 32),
> refclk_khz);
> > + m2div = mul_q32_u32(m2div, 500);
> > + val_with_frac = mul_q32_u32(m2div,
> refclk_khz);
> > + val_with_frac = div64_u64(val_with_frac,
> 500);
> > + temp1 = Q32_TO_INT(val_with_frac);
> > + temp0 = (temp1 > val) ? (temp1 - val) :
> > + (val - temp1);
> > + ppm = div64_u64(temp0, val);
> > + if (temp1 >= dco_min_freq &&
> > + temp1 <= dco_max_freq &&
> > + ppm < ppm_value) {
> > + /* Round to two places */
> > + scale = (1ULL << 32) / 100;
> > + temp0 =
> DIV_ROUND_UP_ULL(val_with_frac,
> > + scale);
> > + *target_dco_mhz = temp0 * scale;
> > + *loop_cnt = y;
> > + return true;
> > + }
> > + }
> > + }
> > + }
> > +
> > + return false;
> > +}
> > +
> > +static void set_phy_vdr_addresses(struct lt_phy_params *p, int
> > +pll_type) {
> > + p->pll_reg4.addr = PLL_REG_ADDR(PLL_REG4_ADDR, pll_type);
> > + p->pll_reg3.addr = PLL_REG_ADDR(PLL_REG3_ADDR, pll_type);
> > + p->pll_reg5.addr = PLL_REG_ADDR(PLL_REG5_ADDR, pll_type);
> > + p->pll_reg57.addr = PLL_REG_ADDR(PLL_REG57_ADDR, pll_type);
> > + p->lf.addr = PLL_REG_ADDR(PLL_LF_ADDR, pll_type);
> > + p->tdc.addr = PLL_REG_ADDR(PLL_TDC_ADDR, pll_type);
> > + p->ssc.addr = PLL_REG_ADDR(PLL_SSC_ADDR, pll_type);
> > + p->bias2.addr = PLL_REG_ADDR(PLL_BIAS2_ADDR, pll_type);
> > + p->bias_trim.addr = PLL_REG_ADDR(PLL_BIAS_TRIM_ADDR,
> pll_type);
> > + p->dco_med.addr = PLL_REG_ADDR(PLL_DCO_MED_ADDR, pll_type);
> > + p->dco_fine.addr = PLL_REG_ADDR(PLL_DCO_FINE_ADDR, pll_type);
> > + p->ssc_inj.addr = PLL_REG_ADDR(PLL_SSC_INJ_ADDR, pll_type);
> > + p->surv_bonus.addr = PLL_REG_ADDR(PLL_SURV_BONUS_ADDR,
> pll_type); }
> > +
> > +static void compute_ssc(struct lt_phy_params *p, u32 ana_cfg) {
> > + int ssc_stepsize = 0;
> > + int ssc_steplen = 0;
> > + int ssc_steplog = 0;
> > +
> > + p->ssc.val = (1 << 31) | (ana_cfg << 24) | (ssc_steplog << 16) |
> > + (ssc_stepsize << 8) | ssc_steplen;
> > +}
> > +
> > +static void compute_bias2(struct lt_phy_params *p) {
> > + u32 ssc_en_local = 0;
> > + u64 dynctrl_ovrd_en = 0;
> > +
> > + p->bias2.val = (dynctrl_ovrd_en << 31) | (ssc_en_local << 30) |
> > + (1 << 23) | (1 << 24) | (32 << 16) | (1 << 8); }
> > +
> > +static void compute_tdc(struct lt_phy_params *p, u64 tdc_fine) {
> > + u32 settling_time = 15;
> > + u32 bias_ovr_en = 1;
> > + u32 coldstart = 1;
> > + u32 true_lock = 2;
> > + u32 early_lock = 1;
> > + u32 lock_ovr_en = 1;
> > + u32 lock_thr = tdc_fine ? 3 : 5;
> > + u32 unlock_thr = tdc_fine ? 5 : 11;
> > +
> > + p->tdc.val = (u32)((2 << 30) + (settling_time << 16) + (bias_ovr_en <<
> 15) +
> > + (lock_ovr_en << 14) + (coldstart << 12) + (true_lock << 10)
> +
> > + (early_lock << 8) + (unlock_thr << 4) + lock_thr); }
> > +
> > +static void compute_dco_med(struct lt_phy_params *p) {
> > + u32 cselmed_en = 0;
> > + u32 cselmed_dyn_adj = 0;
> > + u32 cselmed_ratio = 39;
> > + u32 cselmed_thr = 8;
> > +
> > + p->dco_med.val = (cselmed_en << 31) + (cselmed_dyn_adj << 30) +
> > + (cselmed_ratio << 24) + (cselmed_thr << 21); }
> > +
> > +static void compute_dco_fine(struct lt_phy_params *p, u32 dco_12g) {
> > + u32 dco_fine0_tune_2_0 = 0;
> > + u32 dco_fine1_tune_2_0 = 0;
> > + u32 dco_fine2_tune_2_0 = 0;
> > + u32 dco_fine3_tune_2_0 = 0;
> > + u32 dco_dith0_tune_2_0 = 0;
> > + u32 dco_dith1_tune_2_0 = 0;
> > +
> > + dco_fine0_tune_2_0 = dco_12g ? 4 : 3;
> > + dco_fine1_tune_2_0 = 2;
> > + dco_fine2_tune_2_0 = dco_12g ? 2 : 1;
> > + dco_fine3_tune_2_0 = 5;
> > + dco_dith0_tune_2_0 = dco_12g ? 4 : 3;
> > + dco_dith1_tune_2_0 = 2;
> > +
> > + p->dco_fine.val = (dco_dith1_tune_2_0 << 19)
> > + + (dco_dith0_tune_2_0 << 16)
> > + + (dco_fine3_tune_2_0 << 11)
> > + + (dco_fine2_tune_2_0 << 8)
> > + + (dco_fine1_tune_2_0 << 3)
> > + + dco_fine0_tune_2_0;
> > +}
> > +
> > +int
> > +intel_lt_phy_calculate_hdmi_state(struct intel_lt_phy_pll_state *lt_state,
> > + u32 frequency_khz)
> > +{
> > +#define DATA_ASSIGN(i, pll_reg) \
> > + do { \
> > + lt_state->data[i][0] = (u8)((((pll_reg).val) & 0xFF000000) >>
> 24); \
> > + lt_state->data[i][1] = (u8)((((pll_reg).val) & 0x00FF0000) >>
> 16); \
> > + lt_state->data[i][2] = (u8)((((pll_reg).val) & 0x0000FF00) >> 8);
> \
> > + lt_state->data[i][3] = (u8)((((pll_reg).val) & 0x000000FF));
> \
> > + } while (0)
> > +#define ADDR_ASSIGN(i, pll_reg) \
> > + do { \
> > + lt_state->addr_msb[i] = ((pll_reg).addr >> 8) & 0xFF; \
> > + lt_state->addr_lsb[i] = (pll_reg).addr & 0xFF; \
> > + } while (0)
> > +
> > + bool found = false;
> > + struct lt_phy_params p;
> > + u32 dco_fmin = DCO_MIN_FREQ_MHZ;
> > + u64 refclk_khz = REF_CLK_KHZ;
> > + u64 m2div = 0;
> > + u64 target_dco_mhz = 0;
> > + u64 tdc_fine;
> > + u64 tdc_targetcnt;
> > + u64 feedfwd_gain;
> > + u64 feedfwd_cal_en;
> > + u64 tdc_res = 30;
> > + u32 prop_coeff;
> > + u32 int_coeff;
> > + u32 ndiv = 1;
> > + u32 m1div = 1;
> > + u32 m2div_int;
> > + u32 m2div_frac;
> > + u32 frac_en;
> > + u32 ana_cfg;
> > + u32 loop_cnt = 0;
> > + u32 gain_ctrl = 2;
> > + u32 refclk_mhz_int = 38;
> > + u32 postdiv = 0;
> > + u32 d6_new = 0;
> > + u32 dco_12g = 0;
> > + u32 pll_type = 0;
> > + u32 d1 = 2;
> > + u32 d3 = 5;
> > + u32 d5 = 0;
> > + u32 d6 = 0;
> > + u32 d7;
> > + u32 d8 = 0;
> > + u32 d4 = 0;
> > + u32 bonus_7_0 = 0;
> > + u32 csel2fo = 11;
> > + u32 csel2fo_ovrd_en = 1;
> > + u64 temp0, temp1, temp2, temp3;
> > +
> > + p.surv_bonus.val = (bonus_7_0 << 16);
> > + p.pll_reg4.val = (refclk_mhz_int << 17) +
> > + (ndiv << 9) + (1 << 4);
> > + p.bias_trim.val = (csel2fo_ovrd_en << 30) + (csel2fo << 24);
> > + p.ssc_inj.val = 0;
> > + found = calculate_target_dco_and_loop_cnt(frequency_khz,
> &target_dco_mhz, &loop_cnt);
> > + if (!found)
> > + return -EINVAL;
> > +
> > + m2div = div64_u64(target_dco_mhz, (refclk_khz * ndiv * m1div));
> > + m2div = mul_q32_u32(m2div, 1000);
> > + if (Q32_TO_INT(m2div) > 511)
> > + return -EINVAL;
> > +
> > + m2div_int = (u32)Q32_TO_INT(m2div);
> > + m2div_frac = (u32)(Q32_TO_FRAC(m2div));
> > + frac_en = (m2div_frac > 0) ? 1 : 0;
> > +
> > + if (frac_en > 0)
> > + tdc_res = 70;
> > + else
> > + tdc_res = 36;
> > + tdc_fine = tdc_res > 50 ? 1 : 0;
> > + temp0 = tdc_res * 40 * 11;
> > + temp1 = div64_u64(((4 * TDC_RES_MULTIPLIER) + temp0) * 500,
> temp0 * refclk_khz);
> > + temp2 = div64_u64(temp0 * refclk_khz, 1000);
> > + temp3 = div64_u64(((8 * TDC_RES_MULTIPLIER) + temp2), temp2);
> > + tdc_targetcnt = tdc_res < 50 ? (int)(temp1) : (int)(temp3);
> > + tdc_targetcnt = (int)(tdc_targetcnt / 2);
> > + temp0 = mul_q32_u32(target_dco_mhz, tdc_res);
> > + temp0 >>= 32;
> > + feedfwd_gain = (m2div_frac > 0) ? div64_u64(m1div *
> TDC_RES_MULTIPLIER, temp0) : 0;
> > + feedfwd_cal_en = frac_en;
> > +
> > + temp0 = (u32)Q32_TO_INT(target_dco_mhz);
> > + prop_coeff = (temp0 >= dco_fmin) ? 3 : 4;
> > + int_coeff = (temp0 >= dco_fmin) ? 7 : 8;
> > + ana_cfg = (temp0 >= dco_fmin) ? 8 : 6;
> > + dco_12g = (temp0 >= dco_fmin) ? 0 : 1;
> > +
> > + if (temp0 > 12960)
> > + d7 = 10;
> > + else
> > + d7 = 8;
> > +
> > + d8 = loop_cnt / 2;
> > + d4 = d8 * 2;
> > +
> > + /* Compute pll_reg3,5,57 & lf */
> > + p.pll_reg3.val = (u32)((d4 << 21) + (d3 << 18) + (d1 << 15) +
> (m2div_int << 5));
> > + p.pll_reg5.val = m2div_frac;
> > + postdiv = (d5 == 0) ? 9 : d5;
> > + d6_new = (d6 == 0) ? 40 : d6;
> > + p.pll_reg57.val = (d7 << 24) + (postdiv << 15) + (d8 << 7) + d6_new;
> > + p.lf.val = (u32)((frac_en << 31) + (1 << 30) + (frac_en << 29) +
> > + (feedfwd_cal_en << 28) + (tdc_fine << 27) +
> > + (gain_ctrl << 24) + (feedfwd_gain << 16) +
> > + (int_coeff << 12) + (prop_coeff << 8) + tdc_targetcnt);
> > +
> > + /* Compute ssc / bias2 */
> > + compute_ssc(&p, ana_cfg);
> > + compute_bias2(&p);
> > +
> > + /* Compute tdc/dco_med */
> > + compute_tdc(&p, tdc_fine);
> > + compute_dco_med(&p);
> > +
> > + /* Compute dcofine */
> > + compute_dco_fine(&p, dco_12g);
> > +
> > + pll_type = ((frequency_khz == 10000) || (frequency_khz == 20000) ||
> > + (frequency_khz == 2500) || (dco_12g == 1)) ? 0 : 1;
> > + set_phy_vdr_addresses(&p, pll_type);
> > +
> > + lt_state->config[0] = 0x84;
> > + lt_state->config[1] = 0x2d;
> > + ADDR_ASSIGN(0, p.pll_reg4);
> > + ADDR_ASSIGN(1, p.pll_reg3);
> > + ADDR_ASSIGN(2, p.pll_reg5);
> > + ADDR_ASSIGN(3, p.pll_reg57);
> > + ADDR_ASSIGN(4, p.lf);
> > + ADDR_ASSIGN(5, p.tdc);
> > + ADDR_ASSIGN(6, p.ssc);
> > + ADDR_ASSIGN(7, p.bias2);
> > + ADDR_ASSIGN(8, p.bias_trim);
> > + ADDR_ASSIGN(9, p.dco_med);
> > + ADDR_ASSIGN(10, p.dco_fine);
> > + ADDR_ASSIGN(11, p.ssc_inj);
> > + ADDR_ASSIGN(12, p.surv_bonus);
> > + DATA_ASSIGN(0, p.pll_reg4);
> > + DATA_ASSIGN(1, p.pll_reg3);
> > + DATA_ASSIGN(2, p.pll_reg5);
> > + DATA_ASSIGN(3, p.pll_reg57);
> > + DATA_ASSIGN(4, p.lf);
> > + DATA_ASSIGN(5, p.tdc);
> > + DATA_ASSIGN(6, p.ssc);
> > + DATA_ASSIGN(7, p.bias2);
> > + DATA_ASSIGN(8, p.bias_trim);
> > + DATA_ASSIGN(9, p.dco_med);
> > + DATA_ASSIGN(10, p.dco_fine);
> > + DATA_ASSIGN(11, p.ssc_inj);
> > + DATA_ASSIGN(12, p.surv_bonus);
> > +
> > + return 0;
> > +}
> > +
> > static int
> > intel_lt_phy_calc_hdmi_port_clock(const struct intel_lt_phy_pll_state
> > *lt_state) { -#define REF_CLK_KHZ 38400
> > #define REGVAL(i) ( \
> > (lt_state->data[i][3]) | \
> > (lt_state->data[i][2] << 8) | \
> > @@ -1472,7 +1810,10 @@ intel_lt_phy_pll_calc_state(struct
> intel_crtc_state *crtc_state,
> > }
> > }
> >
> > - /* TODO: Add a function to compute the data for HDMI TMDS*/
> > + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
> > + return intel_lt_phy_calculate_hdmi_state(&crtc_state-
> >dpll_hw_state.ltpll,
> > + crtc_state-
> >port_clock);
> > + }
> >
> > return -EINVAL;
> > }
> > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h
> > b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> > index a538d4c69210..b7911acd7dcd 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
> > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> > @@ -35,6 +35,9 @@ void intel_lt_phy_pll_readout_hw_state(struct
> intel_encoder *encoder,
> > struct intel_lt_phy_pll_state *pll_state);
> void
> > intel_lt_phy_pll_state_verify(struct intel_atomic_state *state,
> > struct intel_crtc *crtc);
> > +int
> > +intel_lt_phy_calculate_hdmi_state(struct intel_lt_phy_pll_state *lt_state,
> > + u32 frequency_khz);
> > void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
> > const struct intel_crtc_state *crtc_state); void
> > intel_xe3plpd_pll_disable(struct intel_encoder *encoder); diff --git
> > a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> > b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> > index 9223487d764e..dc7b7679cd06 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> > @@ -72,4 +72,20 @@
> > #define XE3PLPD_PORT_P2M_MSGBUS_STATUS_P2P(port, lane)
> _XE3PLPD_PORT_P2M_MSGBUS_STATUS_P2P(__xe2lpd_port_idx(port), \
> >
> lane)
> > #define XE3LPD_PORT_P2M_ADDR_MASK
> REG_GENMASK(11, 0)
> > +
> > +#define PLL_REG4_ADDR 0x8510
> > +#define PLL_REG3_ADDR 0x850C
> > +#define PLL_REG5_ADDR 0x8514
> > +#define PLL_REG57_ADDR 0x85E4
> > +#define PLL_LF_ADDR 0x860C
> > +#define PLL_TDC_ADDR 0x8610
> > +#define PLL_SSC_ADDR 0x8614
> > +#define PLL_BIAS2_ADDR 0x8618
> > +#define PLL_BIAS_TRIM_ADDR 0x8648
> > +#define PLL_DCO_MED_ADDR 0x8640
> > +#define PLL_DCO_FINE_ADDR 0x864C
> > +#define PLL_SSC_INJ_ADDR 0x8624
> > +#define PLL_SURV_BONUS_ADDR 0x8644
> > +#define PLL_TYPE_OFFSET 0x200
> > +#define PLL_REG_ADDR(base, pll_type) ((pll_type) ? (base) +
> PLL_TYPE_OFFSET : (base))
> > #endif /* __INTEL_LT_PHY_REGS_H__ */
>
> --
> Jani Nikula, Intel
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2025-11-17 4:59 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
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2025-11-10 6:19 [PATCH v3 1/2] drm/i915/ltphy: Implement HDMI Algo for Pll state Suraj Kandpal
2025-11-10 6:19 ` [PATCH v3 2/2] drm/i915/ltphy: Return lowest portclock for HDMI from reverse algorithm Suraj Kandpal
2025-11-10 6:26 ` ✗ CI.checkpatch: warning for series starting with [v3,1/2] drm/i915/ltphy: Implement HDMI Algo for Pll state Patchwork
2025-11-10 6:27 ` ✓ CI.KUnit: success " Patchwork
2025-11-10 6:42 ` ✗ CI.checksparse: warning " Patchwork
2025-11-10 7:06 ` ✓ Xe.CI.BAT: success " Patchwork
2025-11-10 8:43 ` ✗ Xe.CI.Full: failure " Patchwork
2025-11-10 9:53 ` [PATCH v3 1/2] " Nautiyal, Ankit K
2025-11-14 14:45 ` Jani Nikula
2025-11-17 4:59 ` Kandpal, Suraj
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