[PATCH v2 0/2] drm/xe/guc: Add Wa_14025883347 for GuC DMA failure on reset

[PATCH v2 0/2] drm/xe/guc: Add Wa_14025883347 for GuC DMA failure on reset

[Sk Anirban]

Prevent GuC firmware DMA failures during GuC-only reset by disabling
idle flow and verifying SRAM handling completion. Without this, reset
can be issued while SRAM handler is copying WOPCM to SRAM,
causing GuC HW to get stuck.

Signed-off-by: Sk Anirban <sk.anirban@intel.com>

Sk Anirban (2):
  drm/xe/rtp: Extend support for max rules/actions per entry
  drm/xe/guc: Add Wa_14025883347 for GuC DMA failure on reset

 drivers/gpu/drm/xe/regs/xe_guc_regs.h |  8 +++++++
 drivers/gpu/drm/xe/xe_guc.c           | 30 +++++++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_rtp.h           |  4 ++--
 drivers/gpu/drm/xe/xe_rtp_helpers.h   |  3 +++
 drivers/gpu/drm/xe/xe_wa_oob.rules    |  9 ++++++++
 5 files changed, 52 insertions(+), 2 deletions(-)

-- 
2.43.0

[PATCH v2 1/2] drm/xe/rtp: Extend support for max rules/actions per entry

[Sk Anirban]

Increase XE_RTP_PASTE macro coverage to 15 arguments
to support workarounds with many platform-specific conditions.

Signed-off-by: Sk Anirban <sk.anirban@intel.com>
---
 drivers/gpu/drm/xe/xe_rtp.h         | 4 ++--
 drivers/gpu/drm/xe/xe_rtp_helpers.h | 3 +++
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_rtp.h b/drivers/gpu/drm/xe/xe_rtp.h
index ba5f940c0a96..072dedc4ebf2 100644
--- a/drivers/gpu/drm/xe/xe_rtp.h
+++ b/drivers/gpu/drm/xe/xe_rtp.h
@@ -374,7 +374,7 @@ struct xe_reg_sr;
  * XE_RTP_RULES - Helper to set multiple rules to a struct xe_rtp_entry_sr entry
  * @...: Rules
  *
- * At least one rule is needed and up to 12 are supported. Multiple rules are
+ * At least one rule is needed and up to 15 are supported. Multiple rules are
  * AND'ed together, i.e. all the rules must evaluate to true for the entry to
  * be processed. See XE_RTP_MATCH_* for the possible match rules. Example:
  *
@@ -399,7 +399,7 @@ struct xe_reg_sr;
  * XE_RTP_ACTIONS - Helper to set multiple actions to a struct xe_rtp_entry_sr
  * @...: Actions to be taken
  *
- * At least one action is needed and up to 12 are supported. See XE_RTP_ACTION_*
+ * At least one action is needed and up to 15 are supported. See XE_RTP_ACTION_*
  * for the possible actions. Example:
  *
  * .. code-block:: c
diff --git a/drivers/gpu/drm/xe/xe_rtp_helpers.h b/drivers/gpu/drm/xe/xe_rtp_helpers.h
index a33b0ae98bbc..2de0274bac04 100644
--- a/drivers/gpu/drm/xe/xe_rtp_helpers.h
+++ b/drivers/gpu/drm/xe/xe_rtp_helpers.h
@@ -66,6 +66,9 @@
 #define XE_RTP_PASTE_10(prefix_, sep_, args_) _XE_RTP_CONCAT(prefix_, FIRST_ARG args_) __XE_RTP_PASTE_SEP_ ## sep_ XE_RTP_PASTE_9(prefix_, sep_, _XE_TUPLE_TAIL args_)
 #define XE_RTP_PASTE_11(prefix_, sep_, args_) _XE_RTP_CONCAT(prefix_, FIRST_ARG args_) __XE_RTP_PASTE_SEP_ ## sep_ XE_RTP_PASTE_10(prefix_, sep_, _XE_TUPLE_TAIL args_)
 #define XE_RTP_PASTE_12(prefix_, sep_, args_) _XE_RTP_CONCAT(prefix_, FIRST_ARG args_) __XE_RTP_PASTE_SEP_ ## sep_ XE_RTP_PASTE_11(prefix_, sep_, _XE_TUPLE_TAIL args_)
+#define XE_RTP_PASTE_13(prefix_, sep_, args_) _XE_RTP_CONCAT(prefix_, FIRST_ARG args_) __XE_RTP_PASTE_SEP_ ## sep_ XE_RTP_PASTE_12(prefix_, sep_, _XE_TUPLE_TAIL args_)
+#define XE_RTP_PASTE_14(prefix_, sep_, args_) _XE_RTP_CONCAT(prefix_, FIRST_ARG args_) __XE_RTP_PASTE_SEP_ ## sep_ XE_RTP_PASTE_13(prefix_, sep_, _XE_TUPLE_TAIL args_)
+#define XE_RTP_PASTE_15(prefix_, sep_, args_) _XE_RTP_CONCAT(prefix_, FIRST_ARG args_) __XE_RTP_PASTE_SEP_ ## sep_ XE_RTP_PASTE_14(prefix_, sep_, _XE_TUPLE_TAIL args_)
 
 /*
  * XE_RTP_DROP_CAST - Drop cast to convert a compound statement to a initializer
-- 
2.43.0

[PATCH v2 2/2] drm/xe/guc: Add Wa_14025883347 for GuC DMA failure on reset

[Sk Anirban]

Prevent GuC firmware DMA failures during GuC-only reset by disabling
idle flow and verifying SRAM handling completion. Without this, reset
can be issued while SRAM handler is copying WOPCM to SRAM,
causing GuC HW to get stuck.

v2: Modify error message (Badal)
    Rename reg bit name (Daniele)
    Update WA skip condition (Daniele)
    Update SRAM handling logic (Daniele)

Signed-off-by: Sk Anirban <sk.anirban@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_guc_regs.h |  8 +++++++
 drivers/gpu/drm/xe/xe_guc.c           | 30 +++++++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_wa_oob.rules    |  9 ++++++++
 3 files changed, 47 insertions(+)

diff --git a/drivers/gpu/drm/xe/regs/xe_guc_regs.h b/drivers/gpu/drm/xe/regs/xe_guc_regs.h
index 87984713dd12..c9cb02f32f5a 100644
--- a/drivers/gpu/drm/xe/regs/xe_guc_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_guc_regs.h
@@ -40,6 +40,9 @@
 #define   GS_BOOTROM_JUMP_PASSED		REG_FIELD_PREP(GS_BOOTROM_MASK, 0x76)
 #define   GS_MIA_IN_RESET			REG_BIT(0)
 
+#define GUC_HASH_BOOT_CHECK			XE_REG(0xc010)
+#define   GUC_BOOT_UKERNEL_VALID		REG_BIT(31)
+
 #define GUC_HEADER_INFO				XE_REG(0xc014)
 
 #define GUC_WOPCM_SIZE				XE_REG(0xc050)
@@ -83,7 +86,12 @@
 #define   GUC_WOPCM_OFFSET_MASK			REG_GENMASK(31, GUC_WOPCM_OFFSET_SHIFT)
 #define   HUC_LOADING_AGENT_GUC			REG_BIT(1)
 #define   GUC_WOPCM_OFFSET_VALID		REG_BIT(0)
+
+#define GUC_SRAM_STATUS				XE_REG(0xc398)
+#define   GUC_SRAM_HANDLING_MASK		REG_GENMASK(8, 7)
+
 #define GUC_MAX_IDLE_COUNT			XE_REG(0xc3e4)
+#define   GUC_IDLE_FLOW_DISABLE			REG_BIT(31)
 #define GUC_PMTIMESTAMP_LO			XE_REG(0xc3e8)
 #define GUC_PMTIMESTAMP_HI			XE_REG(0xc3ec)
 
diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index 44360437beeb..42658a409556 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -900,6 +900,33 @@ int xe_guc_post_load_init(struct xe_guc *guc)
 	return xe_guc_submit_enable(guc);
 }
 
+/*
+ * Wa_14025883347: Prevent GuC firmware DMA failures during GuC-only reset by ensuring
+ * SRAM save/restore operations are complete before reset.
+ */
+static void guc_prevent_fw_dma_failure_on_reset(struct xe_guc *guc)
+{
+	struct xe_gt *gt = guc_to_gt(guc);
+	u32 boot_hash_chk, guc_status, sram_status;
+	int ret;
+
+	guc_status = xe_mmio_read32(&gt->mmio, GUC_STATUS);
+	if (guc_status & GS_MIA_IN_RESET)
+		return;
+
+	boot_hash_chk = xe_mmio_read32(&gt->mmio, GUC_HASH_BOOT_CHECK);
+	if (!(boot_hash_chk & GUC_BOOT_UKERNEL_VALID))
+		return;
+
+	xe_mmio_rmw32(&gt->mmio, GUC_MAX_IDLE_COUNT, 0, GUC_IDLE_FLOW_DISABLE);
+
+	ret = xe_mmio_wait32(&gt->mmio, GUC_SRAM_STATUS, GUC_SRAM_HANDLING_MASK,
+			     0, 5000, &sram_status, false);
+	if (ret)
+		xe_gt_warn(gt, "SRAM handling not complete (GUC_SRAM_STATUS: 0x%x)\n",
+			   sram_status);
+}
+
 int xe_guc_reset(struct xe_guc *guc)
 {
 	struct xe_gt *gt = guc_to_gt(guc);
@@ -909,6 +936,9 @@ int xe_guc_reset(struct xe_guc *guc)
 
 	xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
 
+	if (XE_GT_WA(gt, 14025883347))
+		guc_prevent_fw_dma_failure_on_reset(guc);
+
 	if (IS_SRIOV_VF(gt_to_xe(gt)))
 		return xe_gt_sriov_vf_bootstrap(gt);
 
diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
index 5cd7fa6d2a5c..ff2efc7a68cc 100644
--- a/drivers/gpu/drm/xe/xe_wa_oob.rules
+++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
@@ -73,3 +73,12 @@
 15015404425_disable	PLATFORM(PANTHERLAKE), MEDIA_STEP(B0, FOREVER)
 16026007364    MEDIA_VERSION(3000)
 14020316580    MEDIA_VERSION(1301)
+
+14025883347	MEDIA_VERSION(1301)
+		MEDIA_VERSION(2000)
+		MEDIA_VERSION(3000)
+		MEDIA_VERSION(3002)
+		MEDIA_VERSION(3500)
+		MEDIA_VERSION(3503)
+		GRAPHICS_VERSION_RANGE(3000, 3001)
+		GRAPHICS_VERSION_RANGE(3003, 3005)
-- 
2.43.0

✗ CI.checkpatch: warning for drm/xe/guc: Add Wa_14025883347 for GuC DMA failure on reset (rev2)

[Patchwork]

== Series Details ==

Series: drm/xe/guc: Add Wa_14025883347 for GuC DMA failure on reset (rev2)
URL   : https://patchwork.freedesktop.org/series/160091/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
ee83616c430ce70bd254bd2774d143a5733c8666
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 93af31847da02cc8ff8105d46d5258941f9d2fdd
Author: Sk Anirban <sk.anirban@intel.com>
Date:   Fri Jan 16 16:04:54 2026 +0530

    drm/xe/guc: Add Wa_14025883347 for GuC DMA failure on reset
    
    Prevent GuC firmware DMA failures during GuC-only reset by disabling
    idle flow and verifying SRAM handling completion. Without this, reset
    can be issued while SRAM handler is copying WOPCM to SRAM,
    causing GuC HW to get stuck.
    
    v2: Modify error message (Badal)
        Rename reg bit name (Daniele)
        Update WA skip condition (Daniele)
        Update SRAM handling logic (Daniele)
    
    Signed-off-by: Sk Anirban <sk.anirban@intel.com>
+ /mt/dim checkpatch fc80c6efbab24db4bd766a58b2f56c61f7491817 drm-intel
16769d997b05 drm/xe/rtp: Extend support for max rules/actions per entry
-:41: WARNING:LONG_LINE: line length of 167 exceeds 100 columns
#41: FILE: drivers/gpu/drm/xe/xe_rtp_helpers.h:69:
+#define XE_RTP_PASTE_13(prefix_, sep_, args_) _XE_RTP_CONCAT(prefix_, FIRST_ARG args_) __XE_RTP_PASTE_SEP_ ## sep_ XE_RTP_PASTE_12(prefix_, sep_, _XE_TUPLE_TAIL args_)

-:41: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#41: FILE: drivers/gpu/drm/xe/xe_rtp_helpers.h:69:
+#define XE_RTP_PASTE_13(prefix_, sep_, args_) _XE_RTP_CONCAT(prefix_, FIRST_ARG args_) __XE_RTP_PASTE_SEP_ ## sep_ XE_RTP_PASTE_12(prefix_, sep_, _XE_TUPLE_TAIL args_)

BUT SEE:

   do {} while (0) advice is over-stated in a few situations:

   The more obvious case is macros, like MODULE_PARM_DESC, invoked at
   file-scope, where C disallows code (it must be in functions).  See
   $exceptions if you have one to add by name.

   More troublesome is declarative macros used at top of new scope,
   like DECLARE_PER_CPU.  These might just compile with a do-while-0
   wrapper, but would be incorrect.  Most of these are handled by
   detecting struct,union,etc declaration primitives in $exceptions.

   Theres also macros called inside an if (block), which "return" an
   expression.  These cannot do-while, and need a ({}) wrapper.

   Enjoy this qualification while we work to improve our heuristics.

-:41: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'prefix_' - possible side-effects?
#41: FILE: drivers/gpu/drm/xe/xe_rtp_helpers.h:69:
+#define XE_RTP_PASTE_13(prefix_, sep_, args_) _XE_RTP_CONCAT(prefix_, FIRST_ARG args_) __XE_RTP_PASTE_SEP_ ## sep_ XE_RTP_PASTE_12(prefix_, sep_, _XE_TUPLE_TAIL args_)

-:41: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'args_' - possible side-effects?
#41: FILE: drivers/gpu/drm/xe/xe_rtp_helpers.h:69:
+#define XE_RTP_PASTE_13(prefix_, sep_, args_) _XE_RTP_CONCAT(prefix_, FIRST_ARG args_) __XE_RTP_PASTE_SEP_ ## sep_ XE_RTP_PASTE_12(prefix_, sep_, _XE_TUPLE_TAIL args_)

-:42: WARNING:LONG_LINE: line length of 167 exceeds 100 columns
#42: FILE: drivers/gpu/drm/xe/xe_rtp_helpers.h:70:
+#define XE_RTP_PASTE_14(prefix_, sep_, args_) _XE_RTP_CONCAT(prefix_, FIRST_ARG args_) __XE_RTP_PASTE_SEP_ ## sep_ XE_RTP_PASTE_13(prefix_, sep_, _XE_TUPLE_TAIL args_)

-:42: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#42: FILE: drivers/gpu/drm/xe/xe_rtp_helpers.h:70:
+#define XE_RTP_PASTE_14(prefix_, sep_, args_) _XE_RTP_CONCAT(prefix_, FIRST_ARG args_) __XE_RTP_PASTE_SEP_ ## sep_ XE_RTP_PASTE_13(prefix_, sep_, _XE_TUPLE_TAIL args_)

BUT SEE:

   do {} while (0) advice is over-stated in a few situations:

   The more obvious case is macros, like MODULE_PARM_DESC, invoked at
   file-scope, where C disallows code (it must be in functions).  See
   $exceptions if you have one to add by name.

   More troublesome is declarative macros used at top of new scope,
   like DECLARE_PER_CPU.  These might just compile with a do-while-0
   wrapper, but would be incorrect.  Most of these are handled by
   detecting struct,union,etc declaration primitives in $exceptions.

   Theres also macros called inside an if (block), which "return" an
   expression.  These cannot do-while, and need a ({}) wrapper.

   Enjoy this qualification while we work to improve our heuristics.

-:42: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'prefix_' - possible side-effects?
#42: FILE: drivers/gpu/drm/xe/xe_rtp_helpers.h:70:
+#define XE_RTP_PASTE_14(prefix_, sep_, args_) _XE_RTP_CONCAT(prefix_, FIRST_ARG args_) __XE_RTP_PASTE_SEP_ ## sep_ XE_RTP_PASTE_13(prefix_, sep_, _XE_TUPLE_TAIL args_)

-:42: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'args_' - possible side-effects?
#42: FILE: drivers/gpu/drm/xe/xe_rtp_helpers.h:70:
+#define XE_RTP_PASTE_14(prefix_, sep_, args_) _XE_RTP_CONCAT(prefix_, FIRST_ARG args_) __XE_RTP_PASTE_SEP_ ## sep_ XE_RTP_PASTE_13(prefix_, sep_, _XE_TUPLE_TAIL args_)

-:43: WARNING:LONG_LINE: line length of 167 exceeds 100 columns
#43: FILE: drivers/gpu/drm/xe/xe_rtp_helpers.h:71:
+#define XE_RTP_PASTE_15(prefix_, sep_, args_) _XE_RTP_CONCAT(prefix_, FIRST_ARG args_) __XE_RTP_PASTE_SEP_ ## sep_ XE_RTP_PASTE_14(prefix_, sep_, _XE_TUPLE_TAIL args_)

-:43: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#43: FILE: drivers/gpu/drm/xe/xe_rtp_helpers.h:71:
+#define XE_RTP_PASTE_15(prefix_, sep_, args_) _XE_RTP_CONCAT(prefix_, FIRST_ARG args_) __XE_RTP_PASTE_SEP_ ## sep_ XE_RTP_PASTE_14(prefix_, sep_, _XE_TUPLE_TAIL args_)

BUT SEE:

   do {} while (0) advice is over-stated in a few situations:

   The more obvious case is macros, like MODULE_PARM_DESC, invoked at
   file-scope, where C disallows code (it must be in functions).  See
   $exceptions if you have one to add by name.

   More troublesome is declarative macros used at top of new scope,
   like DECLARE_PER_CPU.  These might just compile with a do-while-0
   wrapper, but would be incorrect.  Most of these are handled by
   detecting struct,union,etc declaration primitives in $exceptions.

   Theres also macros called inside an if (block), which "return" an
   expression.  These cannot do-while, and need a ({}) wrapper.

   Enjoy this qualification while we work to improve our heuristics.

-:43: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'prefix_' - possible side-effects?
#43: FILE: drivers/gpu/drm/xe/xe_rtp_helpers.h:71:
+#define XE_RTP_PASTE_15(prefix_, sep_, args_) _XE_RTP_CONCAT(prefix_, FIRST_ARG args_) __XE_RTP_PASTE_SEP_ ## sep_ XE_RTP_PASTE_14(prefix_, sep_, _XE_TUPLE_TAIL args_)

-:43: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'args_' - possible side-effects?
#43: FILE: drivers/gpu/drm/xe/xe_rtp_helpers.h:71:
+#define XE_RTP_PASTE_15(prefix_, sep_, args_) _XE_RTP_CONCAT(prefix_, FIRST_ARG args_) __XE_RTP_PASTE_SEP_ ## sep_ XE_RTP_PASTE_14(prefix_, sep_, _XE_TUPLE_TAIL args_)

total: 3 errors, 3 warnings, 6 checks, 25 lines checked
93af31847da0 drm/xe/guc: Add Wa_14025883347 for GuC DMA failure on reset

✓ CI.KUnit: success for drm/xe/guc: Add Wa_14025883347 for GuC DMA failure on reset (rev2)

[Patchwork]

== Series Details ==

Series: drm/xe/guc: Add Wa_14025883347 for GuC DMA failure on reset (rev2)
URL   : https://patchwork.freedesktop.org/series/160091/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[11:55:54] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:55:58] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[11:56:30] Starting KUnit Kernel (1/1)...
[11:56:30] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:56:30] ================== guc_buf (11 subtests) ===================
[11:56:30] [PASSED] test_smallest
[11:56:30] [PASSED] test_largest
[11:56:30] [PASSED] test_granular
[11:56:30] [PASSED] test_unique
[11:56:30] [PASSED] test_overlap
[11:56:30] [PASSED] test_reusable
[11:56:30] [PASSED] test_too_big
[11:56:30] [PASSED] test_flush
[11:56:30] [PASSED] test_lookup
[11:56:30] [PASSED] test_data
[11:56:30] [PASSED] test_class
[11:56:30] ===================== [PASSED] guc_buf =====================
[11:56:30] =================== guc_dbm (7 subtests) ===================
[11:56:30] [PASSED] test_empty
[11:56:30] [PASSED] test_default
[11:56:30] ======================== test_size  ========================
[11:56:30] [PASSED] 4
[11:56:30] [PASSED] 8
[11:56:30] [PASSED] 32
[11:56:30] [PASSED] 256
[11:56:30] ==================== [PASSED] test_size ====================
[11:56:30] ======================= test_reuse  ========================
[11:56:30] [PASSED] 4
[11:56:30] [PASSED] 8
[11:56:30] [PASSED] 32
[11:56:30] [PASSED] 256
[11:56:30] =================== [PASSED] test_reuse ====================
[11:56:30] =================== test_range_overlap  ====================
[11:56:30] [PASSED] 4
[11:56:30] [PASSED] 8
[11:56:30] [PASSED] 32
[11:56:30] [PASSED] 256
[11:56:30] =============== [PASSED] test_range_overlap ================
[11:56:30] =================== test_range_compact  ====================
[11:56:30] [PASSED] 4
[11:56:30] [PASSED] 8
[11:56:30] [PASSED] 32
[11:56:30] [PASSED] 256
[11:56:30] =============== [PASSED] test_range_compact ================
[11:56:30] ==================== test_range_spare  =====================
[11:56:30] [PASSED] 4
[11:56:30] [PASSED] 8
[11:56:30] [PASSED] 32
[11:56:30] [PASSED] 256
[11:56:30] ================ [PASSED] test_range_spare =================
[11:56:30] ===================== [PASSED] guc_dbm =====================
[11:56:30] =================== guc_idm (6 subtests) ===================
[11:56:30] [PASSED] bad_init
[11:56:30] [PASSED] no_init
[11:56:30] [PASSED] init_fini
[11:56:30] [PASSED] check_used
[11:56:30] [PASSED] check_quota
[11:56:30] [PASSED] check_all
[11:56:30] ===================== [PASSED] guc_idm =====================
[11:56:30] ================== no_relay (3 subtests) ===================
[11:56:30] [PASSED] xe_drops_guc2pf_if_not_ready
[11:56:30] [PASSED] xe_drops_guc2vf_if_not_ready
[11:56:30] [PASSED] xe_rejects_send_if_not_ready
[11:56:30] ==================== [PASSED] no_relay =====================
[11:56:30] ================== pf_relay (14 subtests) ==================
[11:56:30] [PASSED] pf_rejects_guc2pf_too_short
[11:56:30] [PASSED] pf_rejects_guc2pf_too_long
[11:56:30] [PASSED] pf_rejects_guc2pf_no_payload
[11:56:30] [PASSED] pf_fails_no_payload
[11:56:30] [PASSED] pf_fails_bad_origin
[11:56:30] [PASSED] pf_fails_bad_type
[11:56:30] [PASSED] pf_txn_reports_error
[11:56:30] [PASSED] pf_txn_sends_pf2guc
[11:56:30] [PASSED] pf_sends_pf2guc
[11:56:30] [SKIPPED] pf_loopback_nop
[11:56:30] [SKIPPED] pf_loopback_echo
[11:56:30] [SKIPPED] pf_loopback_fail
[11:56:30] [SKIPPED] pf_loopback_busy
[11:56:30] [SKIPPED] pf_loopback_retry
[11:56:30] ==================== [PASSED] pf_relay =====================
[11:56:30] ================== vf_relay (3 subtests) ===================
[11:56:30] [PASSED] vf_rejects_guc2vf_too_short
[11:56:30] [PASSED] vf_rejects_guc2vf_too_long
[11:56:30] [PASSED] vf_rejects_guc2vf_no_payload
[11:56:30] ==================== [PASSED] vf_relay =====================
[11:56:30] ================ pf_gt_config (6 subtests) =================
[11:56:30] [PASSED] fair_contexts_1vf
[11:56:30] [PASSED] fair_doorbells_1vf
[11:56:30] [PASSED] fair_ggtt_1vf
[11:56:30] ====================== fair_contexts  ======================
[11:56:30] [PASSED] 1 VF
[11:56:30] [PASSED] 2 VFs
[11:56:30] [PASSED] 3 VFs
[11:56:30] [PASSED] 4 VFs
[11:56:30] [PASSED] 5 VFs
[11:56:30] [PASSED] 6 VFs
[11:56:30] [PASSED] 7 VFs
[11:56:30] [PASSED] 8 VFs
[11:56:30] [PASSED] 9 VFs
[11:56:30] [PASSED] 10 VFs
[11:56:30] [PASSED] 11 VFs
[11:56:30] [PASSED] 12 VFs
[11:56:30] [PASSED] 13 VFs
[11:56:30] [PASSED] 14 VFs
[11:56:30] [PASSED] 15 VFs
[11:56:30] [PASSED] 16 VFs
[11:56:30] [PASSED] 17 VFs
[11:56:30] [PASSED] 18 VFs
[11:56:30] [PASSED] 19 VFs
[11:56:30] [PASSED] 20 VFs
[11:56:30] [PASSED] 21 VFs
[11:56:30] [PASSED] 22 VFs
[11:56:30] [PASSED] 23 VFs
[11:56:30] [PASSED] 24 VFs
[11:56:30] [PASSED] 25 VFs
[11:56:30] [PASSED] 26 VFs
[11:56:30] [PASSED] 27 VFs
[11:56:30] [PASSED] 28 VFs
[11:56:30] [PASSED] 29 VFs
[11:56:30] [PASSED] 30 VFs
[11:56:30] [PASSED] 31 VFs
[11:56:30] [PASSED] 32 VFs
[11:56:30] [PASSED] 33 VFs
[11:56:30] [PASSED] 34 VFs
[11:56:30] [PASSED] 35 VFs
[11:56:30] [PASSED] 36 VFs
[11:56:30] [PASSED] 37 VFs
[11:56:30] [PASSED] 38 VFs
[11:56:30] [PASSED] 39 VFs
[11:56:30] [PASSED] 40 VFs
[11:56:30] [PASSED] 41 VFs
[11:56:30] [PASSED] 42 VFs
[11:56:30] [PASSED] 43 VFs
[11:56:30] [PASSED] 44 VFs
[11:56:30] [PASSED] 45 VFs
[11:56:30] [PASSED] 46 VFs
[11:56:30] [PASSED] 47 VFs
[11:56:30] [PASSED] 48 VFs
[11:56:30] [PASSED] 49 VFs
[11:56:30] [PASSED] 50 VFs
[11:56:30] [PASSED] 51 VFs
[11:56:30] [PASSED] 52 VFs
[11:56:30] [PASSED] 53 VFs
[11:56:30] [PASSED] 54 VFs
[11:56:30] [PASSED] 55 VFs
[11:56:30] [PASSED] 56 VFs
[11:56:30] [PASSED] 57 VFs
[11:56:30] [PASSED] 58 VFs
[11:56:30] [PASSED] 59 VFs
[11:56:30] [PASSED] 60 VFs
[11:56:30] [PASSED] 61 VFs
[11:56:30] [PASSED] 62 VFs
[11:56:30] [PASSED] 63 VFs
[11:56:30] ================== [PASSED] fair_contexts ==================
[11:56:30] ===================== fair_doorbells  ======================
[11:56:30] [PASSED] 1 VF
[11:56:30] [PASSED] 2 VFs
[11:56:30] [PASSED] 3 VFs
[11:56:30] [PASSED] 4 VFs
[11:56:30] [PASSED] 5 VFs
[11:56:30] [PASSED] 6 VFs
[11:56:30] [PASSED] 7 VFs
[11:56:30] [PASSED] 8 VFs
[11:56:30] [PASSED] 9 VFs
[11:56:30] [PASSED] 10 VFs
[11:56:30] [PASSED] 11 VFs
[11:56:30] [PASSED] 12 VFs
[11:56:30] [PASSED] 13 VFs
[11:56:30] [PASSED] 14 VFs
[11:56:30] [PASSED] 15 VFs
[11:56:30] [PASSED] 16 VFs
[11:56:30] [PASSED] 17 VFs
[11:56:30] [PASSED] 18 VFs
[11:56:30] [PASSED] 19 VFs
[11:56:30] [PASSED] 20 VFs
[11:56:30] [PASSED] 21 VFs
[11:56:30] [PASSED] 22 VFs
[11:56:30] [PASSED] 23 VFs
[11:56:30] [PASSED] 24 VFs
[11:56:30] [PASSED] 25 VFs
[11:56:30] [PASSED] 26 VFs
[11:56:30] [PASSED] 27 VFs
[11:56:30] [PASSED] 28 VFs
[11:56:30] [PASSED] 29 VFs
[11:56:30] [PASSED] 30 VFs
[11:56:30] [PASSED] 31 VFs
[11:56:30] [PASSED] 32 VFs
[11:56:30] [PASSED] 33 VFs
[11:56:30] [PASSED] 34 VFs
[11:56:30] [PASSED] 35 VFs
[11:56:30] [PASSED] 36 VFs
[11:56:30] [PASSED] 37 VFs
[11:56:30] [PASSED] 38 VFs
[11:56:30] [PASSED] 39 VFs
[11:56:30] [PASSED] 40 VFs
[11:56:30] [PASSED] 41 VFs
[11:56:30] [PASSED] 42 VFs
[11:56:30] [PASSED] 43 VFs
[11:56:30] [PASSED] 44 VFs
[11:56:30] [PASSED] 45 VFs
[11:56:30] [PASSED] 46 VFs
[11:56:30] [PASSED] 47 VFs
[11:56:30] [PASSED] 48 VFs
[11:56:30] [PASSED] 49 VFs
[11:56:30] [PASSED] 50 VFs
[11:56:30] [PASSED] 51 VFs
[11:56:30] [PASSED] 52 VFs
[11:56:30] [PASSED] 53 VFs
[11:56:30] [PASSED] 54 VFs
[11:56:30] [PASSED] 55 VFs
[11:56:30] [PASSED] 56 VFs
[11:56:30] [PASSED] 57 VFs
[11:56:30] [PASSED] 58 VFs
[11:56:30] [PASSED] 59 VFs
[11:56:30] [PASSED] 60 VFs
[11:56:30] [PASSED] 61 VFs
[11:56:30] [PASSED] 62 VFs
[11:56:30] [PASSED] 63 VFs
[11:56:30] ================= [PASSED] fair_doorbells ==================
[11:56:30] ======================== fair_ggtt  ========================
[11:56:30] [PASSED] 1 VF
[11:56:30] [PASSED] 2 VFs
[11:56:30] [PASSED] 3 VFs
[11:56:30] [PASSED] 4 VFs
[11:56:30] [PASSED] 5 VFs
[11:56:30] [PASSED] 6 VFs
[11:56:30] [PASSED] 7 VFs
[11:56:30] [PASSED] 8 VFs
[11:56:30] [PASSED] 9 VFs
[11:56:30] [PASSED] 10 VFs
[11:56:30] [PASSED] 11 VFs
[11:56:30] [PASSED] 12 VFs
[11:56:30] [PASSED] 13 VFs
[11:56:30] [PASSED] 14 VFs
[11:56:30] [PASSED] 15 VFs
[11:56:30] [PASSED] 16 VFs
[11:56:30] [PASSED] 17 VFs
[11:56:30] [PASSED] 18 VFs
[11:56:30] [PASSED] 19 VFs
[11:56:30] [PASSED] 20 VFs
[11:56:30] [PASSED] 21 VFs
[11:56:30] [PASSED] 22 VFs
[11:56:30] [PASSED] 23 VFs
[11:56:30] [PASSED] 24 VFs
[11:56:30] [PASSED] 25 VFs
[11:56:30] [PASSED] 26 VFs
[11:56:30] [PASSED] 27 VFs
[11:56:30] [PASSED] 28 VFs
[11:56:30] [PASSED] 29 VFs
[11:56:30] [PASSED] 30 VFs
[11:56:30] [PASSED] 31 VFs
[11:56:30] [PASSED] 32 VFs
[11:56:30] [PASSED] 33 VFs
[11:56:30] [PASSED] 34 VFs
[11:56:30] [PASSED] 35 VFs
[11:56:30] [PASSED] 36 VFs
[11:56:30] [PASSED] 37 VFs
[11:56:30] [PASSED] 38 VFs
[11:56:30] [PASSED] 39 VFs
[11:56:30] [PASSED] 40 VFs
[11:56:30] [PASSED] 41 VFs
[11:56:30] [PASSED] 42 VFs
[11:56:30] [PASSED] 43 VFs
[11:56:30] [PASSED] 44 VFs
[11:56:30] [PASSED] 45 VFs
[11:56:30] [PASSED] 46 VFs
[11:56:30] [PASSED] 47 VFs
[11:56:30] [PASSED] 48 VFs
[11:56:30] [PASSED] 49 VFs
[11:56:30] [PASSED] 50 VFs
[11:56:30] [PASSED] 51 VFs
[11:56:30] [PASSED] 52 VFs
[11:56:30] [PASSED] 53 VFs
[11:56:30] [PASSED] 54 VFs
[11:56:30] [PASSED] 55 VFs
[11:56:30] [PASSED] 56 VFs
[11:56:30] [PASSED] 57 VFs
[11:56:30] [PASSED] 58 VFs
[11:56:30] [PASSED] 59 VFs
[11:56:30] [PASSED] 60 VFs
[11:56:30] [PASSED] 61 VFs
[11:56:30] [PASSED] 62 VFs
[11:56:30] [PASSED] 63 VFs
[11:56:30] ==================== [PASSED] fair_ggtt ====================
[11:56:30] ================== [PASSED] pf_gt_config ===================
[11:56:30] ===================== lmtt (1 subtest) =====================
[11:56:30] ======================== test_ops  =========================
[11:56:30] [PASSED] 2-level
[11:56:30] [PASSED] multi-level
[11:56:30] ==================== [PASSED] test_ops =====================
[11:56:30] ====================== [PASSED] lmtt =======================
[11:56:30] ================= pf_service (11 subtests) =================
[11:56:30] [PASSED] pf_negotiate_any
[11:56:30] [PASSED] pf_negotiate_base_match
[11:56:30] [PASSED] pf_negotiate_base_newer
[11:56:30] [PASSED] pf_negotiate_base_next
[11:56:30] [SKIPPED] pf_negotiate_base_older
[11:56:30] [PASSED] pf_negotiate_base_prev
[11:56:30] [PASSED] pf_negotiate_latest_match
[11:56:30] [PASSED] pf_negotiate_latest_newer
[11:56:30] [PASSED] pf_negotiate_latest_next
[11:56:30] [SKIPPED] pf_negotiate_latest_older
[11:56:30] [SKIPPED] pf_negotiate_latest_prev
[11:56:30] =================== [PASSED] pf_service ====================
[11:56:30] ================= xe_guc_g2g (2 subtests) ==================
[11:56:30] ============== xe_live_guc_g2g_kunit_default  ==============
[11:56:30] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[11:56:30] ============== xe_live_guc_g2g_kunit_allmem  ===============
[11:56:30] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[11:56:30] =================== [SKIPPED] xe_guc_g2g ===================
[11:56:30] =================== xe_mocs (2 subtests) ===================
[11:56:30] ================ xe_live_mocs_kernel_kunit  ================
[11:56:30] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[11:56:30] ================ xe_live_mocs_reset_kunit  =================
[11:56:30] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[11:56:30] ==================== [SKIPPED] xe_mocs =====================
[11:56:30] ================= xe_migrate (2 subtests) ==================
[11:56:30] ================= xe_migrate_sanity_kunit  =================
[11:56:30] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[11:56:30] ================== xe_validate_ccs_kunit  ==================
[11:56:30] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[11:56:30] =================== [SKIPPED] xe_migrate ===================
[11:56:30] ================== xe_dma_buf (1 subtest) ==================
[11:56:30] ==================== xe_dma_buf_kunit  =====================
[11:56:30] ================ [SKIPPED] xe_dma_buf_kunit ================
[11:56:30] =================== [SKIPPED] xe_dma_buf ===================
[11:56:30] ================= xe_bo_shrink (1 subtest) =================
[11:56:30] =================== xe_bo_shrink_kunit  ====================
[11:56:30] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[11:56:30] ================== [SKIPPED] xe_bo_shrink ==================
[11:56:30] ==================== xe_bo (2 subtests) ====================
[11:56:30] ================== xe_ccs_migrate_kunit  ===================
[11:56:30] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[11:56:30] ==================== xe_bo_evict_kunit  ====================
[11:56:30] =============== [SKIPPED] xe_bo_evict_kunit ================
[11:56:30] ===================== [SKIPPED] xe_bo ======================
[11:56:30] ==================== args (13 subtests) ====================
[11:56:30] [PASSED] count_args_test
[11:56:30] [PASSED] call_args_example
[11:56:30] [PASSED] call_args_test
[11:56:30] [PASSED] drop_first_arg_example
[11:56:30] [PASSED] drop_first_arg_test
[11:56:30] [PASSED] first_arg_example
[11:56:30] [PASSED] first_arg_test
[11:56:30] [PASSED] last_arg_example
[11:56:30] [PASSED] last_arg_test
[11:56:30] [PASSED] pick_arg_example
[11:56:30] [PASSED] if_args_example
[11:56:30] [PASSED] if_args_test
[11:56:30] [PASSED] sep_comma_example
[11:56:30] ====================== [PASSED] args =======================
[11:56:30] =================== xe_pci (3 subtests) ====================
[11:56:30] ==================== check_graphics_ip  ====================
[11:56:30] [PASSED] 12.00 Xe_LP
[11:56:30] [PASSED] 12.10 Xe_LP+
[11:56:30] [PASSED] 12.55 Xe_HPG
[11:56:30] [PASSED] 12.60 Xe_HPC
[11:56:30] [PASSED] 12.70 Xe_LPG
[11:56:30] [PASSED] 12.71 Xe_LPG
[11:56:30] [PASSED] 12.74 Xe_LPG+
[11:56:30] [PASSED] 20.01 Xe2_HPG
[11:56:30] [PASSED] 20.02 Xe2_HPG
[11:56:30] [PASSED] 20.04 Xe2_LPG
[11:56:30] [PASSED] 30.00 Xe3_LPG
[11:56:30] [PASSED] 30.01 Xe3_LPG
[11:56:30] [PASSED] 30.03 Xe3_LPG
[11:56:30] [PASSED] 30.04 Xe3_LPG
[11:56:30] [PASSED] 30.05 Xe3_LPG
[11:56:30] [PASSED] 35.11 Xe3p_XPC
[11:56:30] ================ [PASSED] check_graphics_ip ================
[11:56:30] ===================== check_media_ip  ======================
[11:56:30] [PASSED] 12.00 Xe_M
[11:56:30] [PASSED] 12.55 Xe_HPM
[11:56:30] [PASSED] 13.00 Xe_LPM+
[11:56:30] [PASSED] 13.01 Xe2_HPM
[11:56:30] [PASSED] 20.00 Xe2_LPM
[11:56:30] [PASSED] 30.00 Xe3_LPM
[11:56:30] [PASSED] 30.02 Xe3_LPM
[11:56:30] [PASSED] 35.00 Xe3p_LPM
[11:56:30] [PASSED] 35.03 Xe3p_HPM
[11:56:30] ================= [PASSED] check_media_ip ==================
[11:56:30] =================== check_platform_desc  ===================
[11:56:30] [PASSED] 0x9A60 (TIGERLAKE)
[11:56:30] [PASSED] 0x9A68 (TIGERLAKE)
[11:56:30] [PASSED] 0x9A70 (TIGERLAKE)
[11:56:30] [PASSED] 0x9A40 (TIGERLAKE)
[11:56:30] [PASSED] 0x9A49 (TIGERLAKE)
[11:56:30] [PASSED] 0x9A59 (TIGERLAKE)
[11:56:30] [PASSED] 0x9A78 (TIGERLAKE)
[11:56:30] [PASSED] 0x9AC0 (TIGERLAKE)
[11:56:30] [PASSED] 0x9AC9 (TIGERLAKE)
[11:56:30] [PASSED] 0x9AD9 (TIGERLAKE)
[11:56:30] [PASSED] 0x9AF8 (TIGERLAKE)
[11:56:30] [PASSED] 0x4C80 (ROCKETLAKE)
[11:56:30] [PASSED] 0x4C8A (ROCKETLAKE)
[11:56:30] [PASSED] 0x4C8B (ROCKETLAKE)
[11:56:30] [PASSED] 0x4C8C (ROCKETLAKE)
[11:56:30] [PASSED] 0x4C90 (ROCKETLAKE)
[11:56:30] [PASSED] 0x4C9A (ROCKETLAKE)
[11:56:30] [PASSED] 0x4680 (ALDERLAKE_S)
[11:56:30] [PASSED] 0x4682 (ALDERLAKE_S)
[11:56:30] [PASSED] 0x4688 (ALDERLAKE_S)
[11:56:30] [PASSED] 0x468A (ALDERLAKE_S)
[11:56:30] [PASSED] 0x468B (ALDERLAKE_S)
[11:56:30] [PASSED] 0x4690 (ALDERLAKE_S)
[11:56:30] [PASSED] 0x4692 (ALDERLAKE_S)
[11:56:30] [PASSED] 0x4693 (ALDERLAKE_S)
[11:56:30] [PASSED] 0x46A0 (ALDERLAKE_P)
[11:56:30] [PASSED] 0x46A1 (ALDERLAKE_P)
[11:56:30] [PASSED] 0x46A2 (ALDERLAKE_P)
[11:56:30] [PASSED] 0x46A3 (ALDERLAKE_P)
[11:56:30] [PASSED] 0x46A6 (ALDERLAKE_P)
[11:56:30] [PASSED] 0x46A8 (ALDERLAKE_P)
[11:56:30] [PASSED] 0x46AA (ALDERLAKE_P)
[11:56:30] [PASSED] 0x462A (ALDERLAKE_P)
[11:56:30] [PASSED] 0x4626 (ALDERLAKE_P)
[11:56:30] [PASSED] 0x4628 (ALDERLAKE_P)
stty: 'standard input': Inappropriate ioctl for device
[11:56:30] [PASSED] 0x46B0 (ALDERLAKE_P)
[11:56:30] [PASSED] 0x46B1 (ALDERLAKE_P)
[11:56:30] [PASSED] 0x46B2 (ALDERLAKE_P)
[11:56:30] [PASSED] 0x46B3 (ALDERLAKE_P)
[11:56:30] [PASSED] 0x46C0 (ALDERLAKE_P)
[11:56:30] [PASSED] 0x46C1 (ALDERLAKE_P)
[11:56:30] [PASSED] 0x46C2 (ALDERLAKE_P)
[11:56:30] [PASSED] 0x46C3 (ALDERLAKE_P)
[11:56:30] [PASSED] 0x46D0 (ALDERLAKE_N)
[11:56:30] [PASSED] 0x46D1 (ALDERLAKE_N)
[11:56:30] [PASSED] 0x46D2 (ALDERLAKE_N)
[11:56:30] [PASSED] 0x46D3 (ALDERLAKE_N)
[11:56:30] [PASSED] 0x46D4 (ALDERLAKE_N)
[11:56:30] [PASSED] 0xA721 (ALDERLAKE_P)
[11:56:30] [PASSED] 0xA7A1 (ALDERLAKE_P)
[11:56:30] [PASSED] 0xA7A9 (ALDERLAKE_P)
[11:56:30] [PASSED] 0xA7AC (ALDERLAKE_P)
[11:56:30] [PASSED] 0xA7AD (ALDERLAKE_P)
[11:56:30] [PASSED] 0xA720 (ALDERLAKE_P)
[11:56:30] [PASSED] 0xA7A0 (ALDERLAKE_P)
[11:56:30] [PASSED] 0xA7A8 (ALDERLAKE_P)
[11:56:30] [PASSED] 0xA7AA (ALDERLAKE_P)
[11:56:30] [PASSED] 0xA7AB (ALDERLAKE_P)
[11:56:30] [PASSED] 0xA780 (ALDERLAKE_S)
[11:56:30] [PASSED] 0xA781 (ALDERLAKE_S)
[11:56:30] [PASSED] 0xA782 (ALDERLAKE_S)
[11:56:30] [PASSED] 0xA783 (ALDERLAKE_S)
[11:56:30] [PASSED] 0xA788 (ALDERLAKE_S)
[11:56:30] [PASSED] 0xA789 (ALDERLAKE_S)
[11:56:30] [PASSED] 0xA78A (ALDERLAKE_S)
[11:56:30] [PASSED] 0xA78B (ALDERLAKE_S)
[11:56:30] [PASSED] 0x4905 (DG1)
[11:56:30] [PASSED] 0x4906 (DG1)
[11:56:30] [PASSED] 0x4907 (DG1)
[11:56:30] [PASSED] 0x4908 (DG1)
[11:56:30] [PASSED] 0x4909 (DG1)
[11:56:30] [PASSED] 0x56C0 (DG2)
[11:56:30] [PASSED] 0x56C2 (DG2)
[11:56:30] [PASSED] 0x56C1 (DG2)
[11:56:30] [PASSED] 0x7D51 (METEORLAKE)
[11:56:30] [PASSED] 0x7DD1 (METEORLAKE)
[11:56:30] [PASSED] 0x7D41 (METEORLAKE)
[11:56:30] [PASSED] 0x7D67 (METEORLAKE)
[11:56:30] [PASSED] 0xB640 (METEORLAKE)
[11:56:30] [PASSED] 0x56A0 (DG2)
[11:56:30] [PASSED] 0x56A1 (DG2)
[11:56:30] [PASSED] 0x56A2 (DG2)
[11:56:30] [PASSED] 0x56BE (DG2)
[11:56:30] [PASSED] 0x56BF (DG2)
[11:56:30] [PASSED] 0x5690 (DG2)
[11:56:30] [PASSED] 0x5691 (DG2)
[11:56:30] [PASSED] 0x5692 (DG2)
[11:56:30] [PASSED] 0x56A5 (DG2)
[11:56:30] [PASSED] 0x56A6 (DG2)
[11:56:30] [PASSED] 0x56B0 (DG2)
[11:56:30] [PASSED] 0x56B1 (DG2)
[11:56:30] [PASSED] 0x56BA (DG2)
[11:56:30] [PASSED] 0x56BB (DG2)
[11:56:30] [PASSED] 0x56BC (DG2)
[11:56:30] [PASSED] 0x56BD (DG2)
[11:56:30] [PASSED] 0x5693 (DG2)
[11:56:30] [PASSED] 0x5694 (DG2)
[11:56:30] [PASSED] 0x5695 (DG2)
[11:56:30] [PASSED] 0x56A3 (DG2)
[11:56:30] [PASSED] 0x56A4 (DG2)
[11:56:30] [PASSED] 0x56B2 (DG2)
[11:56:30] [PASSED] 0x56B3 (DG2)
[11:56:30] [PASSED] 0x5696 (DG2)
[11:56:30] [PASSED] 0x5697 (DG2)
[11:56:30] [PASSED] 0xB69 (PVC)
[11:56:30] [PASSED] 0xB6E (PVC)
[11:56:30] [PASSED] 0xBD4 (PVC)
[11:56:30] [PASSED] 0xBD5 (PVC)
[11:56:30] [PASSED] 0xBD6 (PVC)
[11:56:30] [PASSED] 0xBD7 (PVC)
[11:56:30] [PASSED] 0xBD8 (PVC)
[11:56:30] [PASSED] 0xBD9 (PVC)
[11:56:30] [PASSED] 0xBDA (PVC)
[11:56:30] [PASSED] 0xBDB (PVC)
[11:56:30] [PASSED] 0xBE0 (PVC)
[11:56:30] [PASSED] 0xBE1 (PVC)
[11:56:30] [PASSED] 0xBE5 (PVC)
[11:56:30] [PASSED] 0x7D40 (METEORLAKE)
[11:56:30] [PASSED] 0x7D45 (METEORLAKE)
[11:56:30] [PASSED] 0x7D55 (METEORLAKE)
[11:56:30] [PASSED] 0x7D60 (METEORLAKE)
[11:56:30] [PASSED] 0x7DD5 (METEORLAKE)
[11:56:30] [PASSED] 0x6420 (LUNARLAKE)
[11:56:30] [PASSED] 0x64A0 (LUNARLAKE)
[11:56:30] [PASSED] 0x64B0 (LUNARLAKE)
[11:56:30] [PASSED] 0xE202 (BATTLEMAGE)
[11:56:30] [PASSED] 0xE209 (BATTLEMAGE)
[11:56:30] [PASSED] 0xE20B (BATTLEMAGE)
[11:56:30] [PASSED] 0xE20C (BATTLEMAGE)
[11:56:30] [PASSED] 0xE20D (BATTLEMAGE)
[11:56:30] [PASSED] 0xE210 (BATTLEMAGE)
[11:56:30] [PASSED] 0xE211 (BATTLEMAGE)
[11:56:30] [PASSED] 0xE212 (BATTLEMAGE)
[11:56:30] [PASSED] 0xE216 (BATTLEMAGE)
[11:56:30] [PASSED] 0xE220 (BATTLEMAGE)
[11:56:30] [PASSED] 0xE221 (BATTLEMAGE)
[11:56:30] [PASSED] 0xE222 (BATTLEMAGE)
[11:56:30] [PASSED] 0xE223 (BATTLEMAGE)
[11:56:30] [PASSED] 0xB080 (PANTHERLAKE)
[11:56:30] [PASSED] 0xB081 (PANTHERLAKE)
[11:56:30] [PASSED] 0xB082 (PANTHERLAKE)
[11:56:30] [PASSED] 0xB083 (PANTHERLAKE)
[11:56:30] [PASSED] 0xB084 (PANTHERLAKE)
[11:56:30] [PASSED] 0xB085 (PANTHERLAKE)
[11:56:30] [PASSED] 0xB086 (PANTHERLAKE)
[11:56:30] [PASSED] 0xB087 (PANTHERLAKE)
[11:56:30] [PASSED] 0xB08F (PANTHERLAKE)
[11:56:30] [PASSED] 0xB090 (PANTHERLAKE)
[11:56:30] [PASSED] 0xB0A0 (PANTHERLAKE)
[11:56:30] [PASSED] 0xB0B0 (PANTHERLAKE)
[11:56:30] [PASSED] 0xFD80 (PANTHERLAKE)
[11:56:30] [PASSED] 0xFD81 (PANTHERLAKE)
[11:56:30] [PASSED] 0xD740 (NOVALAKE_S)
[11:56:30] [PASSED] 0xD741 (NOVALAKE_S)
[11:56:30] [PASSED] 0xD742 (NOVALAKE_S)
[11:56:30] [PASSED] 0xD743 (NOVALAKE_S)
[11:56:30] [PASSED] 0xD744 (NOVALAKE_S)
[11:56:30] [PASSED] 0xD745 (NOVALAKE_S)
[11:56:30] [PASSED] 0x674C (CRESCENTISLAND)
[11:56:30] =============== [PASSED] check_platform_desc ===============
[11:56:30] ===================== [PASSED] xe_pci ======================
[11:56:30] =================== xe_rtp (2 subtests) ====================
[11:56:30] =============== xe_rtp_process_to_sr_tests  ================
[11:56:30] [PASSED] coalesce-same-reg
[11:56:30] [PASSED] no-match-no-add
[11:56:30] [PASSED] match-or
[11:56:30] [PASSED] match-or-xfail
[11:56:30] [PASSED] no-match-no-add-multiple-rules
[11:56:30] [PASSED] two-regs-two-entries
[11:56:30] [PASSED] clr-one-set-other
[11:56:30] [PASSED] set-field
[11:56:30] [PASSED] conflict-duplicate
[11:56:30] [PASSED] conflict-not-disjoint
[11:56:30] [PASSED] conflict-reg-type
[11:56:30] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[11:56:30] ================== xe_rtp_process_tests  ===================
[11:56:30] [PASSED] active1
[11:56:30] [PASSED] active2
[11:56:30] [PASSED] active-inactive
[11:56:30] [PASSED] inactive-active
[11:56:30] [PASSED] inactive-1st_or_active-inactive
[11:56:30] [PASSED] inactive-2nd_or_active-inactive
[11:56:30] [PASSED] inactive-last_or_active-inactive
[11:56:30] [PASSED] inactive-no_or_active-inactive
[11:56:30] ============== [PASSED] xe_rtp_process_tests ===============
[11:56:30] ===================== [PASSED] xe_rtp ======================
[11:56:30] ==================== xe_wa (1 subtest) =====================
[11:56:30] ======================== xe_wa_gt  =========================
[11:56:30] [PASSED] TIGERLAKE B0
[11:56:30] [PASSED] DG1 A0
[11:56:30] [PASSED] DG1 B0
[11:56:30] [PASSED] ALDERLAKE_S A0
[11:56:30] [PASSED] ALDERLAKE_S B0
[11:56:30] [PASSED] ALDERLAKE_S C0
[11:56:30] [PASSED] ALDERLAKE_S D0
[11:56:30] [PASSED] ALDERLAKE_P A0
[11:56:30] [PASSED] ALDERLAKE_P B0
[11:56:30] [PASSED] ALDERLAKE_P C0
[11:56:30] [PASSED] ALDERLAKE_S RPLS D0
[11:56:30] [PASSED] ALDERLAKE_P RPLU E0
[11:56:30] [PASSED] DG2 G10 C0
[11:56:30] [PASSED] DG2 G11 B1
[11:56:30] [PASSED] DG2 G12 A1
[11:56:30] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[11:56:30] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[11:56:30] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[11:56:30] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[11:56:30] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[11:56:30] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[11:56:30] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[11:56:30] ==================== [PASSED] xe_wa_gt =====================
[11:56:30] ====================== [PASSED] xe_wa ======================
[11:56:30] ============================================================
[11:56:30] Testing complete. Ran 512 tests: passed: 494, skipped: 18
[11:56:30] Elapsed time: 36.200s total, 4.211s configuring, 31.472s building, 0.471s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[11:56:30] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:56:32] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[11:56:57] Starting KUnit Kernel (1/1)...
[11:56:57] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:56:57] ============ drm_test_pick_cmdline (2 subtests) ============
[11:56:57] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[11:56:57] =============== drm_test_pick_cmdline_named  ===============
[11:56:57] [PASSED] NTSC
[11:56:57] [PASSED] NTSC-J
[11:56:57] [PASSED] PAL
[11:56:57] [PASSED] PAL-M
[11:56:57] =========== [PASSED] drm_test_pick_cmdline_named ===========
[11:56:57] ============== [PASSED] drm_test_pick_cmdline ==============
[11:56:57] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[11:56:57] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[11:56:57] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[11:56:57] =========== drm_validate_clone_mode (2 subtests) ===========
[11:56:57] ============== drm_test_check_in_clone_mode  ===============
[11:56:57] [PASSED] in_clone_mode
[11:56:57] [PASSED] not_in_clone_mode
[11:56:57] ========== [PASSED] drm_test_check_in_clone_mode ===========
[11:56:57] =============== drm_test_check_valid_clones  ===============
[11:56:57] [PASSED] not_in_clone_mode
[11:56:57] [PASSED] valid_clone
[11:56:57] [PASSED] invalid_clone
[11:56:57] =========== [PASSED] drm_test_check_valid_clones ===========
[11:56:57] ============= [PASSED] drm_validate_clone_mode =============
[11:56:57] ============= drm_validate_modeset (1 subtest) =============
[11:56:57] [PASSED] drm_test_check_connector_changed_modeset
[11:56:57] ============== [PASSED] drm_validate_modeset ===============
[11:56:57] ====== drm_test_bridge_get_current_state (2 subtests) ======
[11:56:57] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[11:56:57] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[11:56:57] ======== [PASSED] drm_test_bridge_get_current_state ========
[11:56:57] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[11:56:57] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[11:56:57] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[11:56:57] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[11:56:57] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[11:56:57] ============== drm_bridge_alloc (2 subtests) ===============
[11:56:57] [PASSED] drm_test_drm_bridge_alloc_basic
[11:56:57] [PASSED] drm_test_drm_bridge_alloc_get_put
[11:56:57] ================ [PASSED] drm_bridge_alloc =================
[11:56:57] ================== drm_buddy (8 subtests) ==================
[11:56:57] [PASSED] drm_test_buddy_alloc_limit
[11:56:57] [PASSED] drm_test_buddy_alloc_optimistic
[11:56:57] [PASSED] drm_test_buddy_alloc_pessimistic
[11:56:57] [PASSED] drm_test_buddy_alloc_pathological
[11:56:57] [PASSED] drm_test_buddy_alloc_contiguous
[11:56:57] [PASSED] drm_test_buddy_alloc_clear
[11:56:57] [PASSED] drm_test_buddy_alloc_range_bias
[11:56:58] [PASSED] drm_test_buddy_fragmentation_performance
[11:56:58] ==================== [PASSED] drm_buddy ====================
[11:56:58] ============= drm_cmdline_parser (40 subtests) =============
[11:56:58] [PASSED] drm_test_cmdline_force_d_only
[11:56:58] [PASSED] drm_test_cmdline_force_D_only_dvi
[11:56:58] [PASSED] drm_test_cmdline_force_D_only_hdmi
[11:56:58] [PASSED] drm_test_cmdline_force_D_only_not_digital
[11:56:58] [PASSED] drm_test_cmdline_force_e_only
[11:56:58] [PASSED] drm_test_cmdline_res
[11:56:58] [PASSED] drm_test_cmdline_res_vesa
[11:56:58] [PASSED] drm_test_cmdline_res_vesa_rblank
[11:56:58] [PASSED] drm_test_cmdline_res_rblank
[11:56:58] [PASSED] drm_test_cmdline_res_bpp
[11:56:58] [PASSED] drm_test_cmdline_res_refresh
[11:56:58] [PASSED] drm_test_cmdline_res_bpp_refresh
[11:56:58] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[11:56:58] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[11:56:58] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[11:56:58] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[11:56:58] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[11:56:58] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[11:56:58] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[11:56:58] [PASSED] drm_test_cmdline_res_margins_force_on
[11:56:58] [PASSED] drm_test_cmdline_res_vesa_margins
[11:56:58] [PASSED] drm_test_cmdline_name
[11:56:58] [PASSED] drm_test_cmdline_name_bpp
[11:56:58] [PASSED] drm_test_cmdline_name_option
[11:56:58] [PASSED] drm_test_cmdline_name_bpp_option
[11:56:58] [PASSED] drm_test_cmdline_rotate_0
[11:56:58] [PASSED] drm_test_cmdline_rotate_90
[11:56:58] [PASSED] drm_test_cmdline_rotate_180
[11:56:58] [PASSED] drm_test_cmdline_rotate_270
[11:56:58] [PASSED] drm_test_cmdline_hmirror
[11:56:58] [PASSED] drm_test_cmdline_vmirror
[11:56:58] [PASSED] drm_test_cmdline_margin_options
[11:56:58] [PASSED] drm_test_cmdline_multiple_options
[11:56:58] [PASSED] drm_test_cmdline_bpp_extra_and_option
[11:56:58] [PASSED] drm_test_cmdline_extra_and_option
[11:56:58] [PASSED] drm_test_cmdline_freestanding_options
[11:56:58] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[11:56:58] [PASSED] drm_test_cmdline_panel_orientation
[11:56:58] ================ drm_test_cmdline_invalid  =================
[11:56:58] [PASSED] margin_only
[11:56:58] [PASSED] interlace_only
[11:56:58] [PASSED] res_missing_x
[11:56:58] [PASSED] res_missing_y
[11:56:58] [PASSED] res_bad_y
[11:56:58] [PASSED] res_missing_y_bpp
[11:56:58] [PASSED] res_bad_bpp
[11:56:58] [PASSED] res_bad_refresh
[11:56:58] [PASSED] res_bpp_refresh_force_on_off
[11:56:58] [PASSED] res_invalid_mode
[11:56:58] [PASSED] res_bpp_wrong_place_mode
[11:56:58] [PASSED] name_bpp_refresh
[11:56:58] [PASSED] name_refresh
[11:56:58] [PASSED] name_refresh_wrong_mode
[11:56:58] [PASSED] name_refresh_invalid_mode
[11:56:58] [PASSED] rotate_multiple
[11:56:58] [PASSED] rotate_invalid_val
[11:56:58] [PASSED] rotate_truncated
[11:56:58] [PASSED] invalid_option
[11:56:58] [PASSED] invalid_tv_option
[11:56:58] [PASSED] truncated_tv_option
[11:56:58] ============ [PASSED] drm_test_cmdline_invalid =============
[11:56:58] =============== drm_test_cmdline_tv_options  ===============
[11:56:58] [PASSED] NTSC
[11:56:58] [PASSED] NTSC_443
[11:56:58] [PASSED] NTSC_J
[11:56:58] [PASSED] PAL
[11:56:58] [PASSED] PAL_M
[11:56:58] [PASSED] PAL_N
[11:56:58] [PASSED] SECAM
[11:56:58] [PASSED] MONO_525
[11:56:58] [PASSED] MONO_625
[11:56:58] =========== [PASSED] drm_test_cmdline_tv_options ===========
[11:56:58] =============== [PASSED] drm_cmdline_parser ================
[11:56:58] ========== drmm_connector_hdmi_init (20 subtests) ==========
[11:56:58] [PASSED] drm_test_connector_hdmi_init_valid
[11:56:58] [PASSED] drm_test_connector_hdmi_init_bpc_8
[11:56:58] [PASSED] drm_test_connector_hdmi_init_bpc_10
[11:56:58] [PASSED] drm_test_connector_hdmi_init_bpc_12
[11:56:58] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[11:56:58] [PASSED] drm_test_connector_hdmi_init_bpc_null
[11:56:58] [PASSED] drm_test_connector_hdmi_init_formats_empty
[11:56:58] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[11:56:58] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[11:56:58] [PASSED] supported_formats=0x9 yuv420_allowed=1
[11:56:58] [PASSED] supported_formats=0x9 yuv420_allowed=0
[11:56:58] [PASSED] supported_formats=0x3 yuv420_allowed=1
[11:56:58] [PASSED] supported_formats=0x3 yuv420_allowed=0
[11:56:58] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[11:56:58] [PASSED] drm_test_connector_hdmi_init_null_ddc
[11:56:58] [PASSED] drm_test_connector_hdmi_init_null_product
[11:56:58] [PASSED] drm_test_connector_hdmi_init_null_vendor
[11:56:58] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[11:56:58] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[11:56:58] [PASSED] drm_test_connector_hdmi_init_product_valid
[11:56:58] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[11:56:58] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[11:56:58] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[11:56:58] ========= drm_test_connector_hdmi_init_type_valid  =========
[11:56:58] [PASSED] HDMI-A
[11:56:58] [PASSED] HDMI-B
[11:56:58] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[11:56:58] ======== drm_test_connector_hdmi_init_type_invalid  ========
[11:56:58] [PASSED] Unknown
[11:56:58] [PASSED] VGA
[11:56:58] [PASSED] DVI-I
[11:56:58] [PASSED] DVI-D
[11:56:58] [PASSED] DVI-A
[11:56:58] [PASSED] Composite
[11:56:58] [PASSED] SVIDEO
[11:56:58] [PASSED] LVDS
[11:56:58] [PASSED] Component
[11:56:58] [PASSED] DIN
[11:56:58] [PASSED] DP
[11:56:58] [PASSED] TV
[11:56:58] [PASSED] eDP
[11:56:58] [PASSED] Virtual
[11:56:58] [PASSED] DSI
[11:56:58] [PASSED] DPI
[11:56:58] [PASSED] Writeback
[11:56:58] [PASSED] SPI
[11:56:58] [PASSED] USB
[11:56:58] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[11:56:58] ============ [PASSED] drmm_connector_hdmi_init =============
[11:56:58] ============= drmm_connector_init (3 subtests) =============
[11:56:58] [PASSED] drm_test_drmm_connector_init
[11:56:58] [PASSED] drm_test_drmm_connector_init_null_ddc
[11:56:58] ========= drm_test_drmm_connector_init_type_valid  =========
[11:56:58] [PASSED] Unknown
[11:56:58] [PASSED] VGA
[11:56:58] [PASSED] DVI-I
[11:56:58] [PASSED] DVI-D
[11:56:58] [PASSED] DVI-A
[11:56:58] [PASSED] Composite
[11:56:58] [PASSED] SVIDEO
[11:56:58] [PASSED] LVDS
[11:56:58] [PASSED] Component
[11:56:58] [PASSED] DIN
[11:56:58] [PASSED] DP
[11:56:58] [PASSED] HDMI-A
[11:56:58] [PASSED] HDMI-B
[11:56:58] [PASSED] TV
[11:56:58] [PASSED] eDP
[11:56:58] [PASSED] Virtual
[11:56:58] [PASSED] DSI
[11:56:58] [PASSED] DPI
[11:56:58] [PASSED] Writeback
[11:56:58] [PASSED] SPI
[11:56:58] [PASSED] USB
[11:56:58] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[11:56:58] =============== [PASSED] drmm_connector_init ===============
[11:56:58] ========= drm_connector_dynamic_init (6 subtests) ==========
[11:56:58] [PASSED] drm_test_drm_connector_dynamic_init
[11:56:58] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[11:56:58] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[11:56:58] [PASSED] drm_test_drm_connector_dynamic_init_properties
[11:56:58] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[11:56:58] [PASSED] Unknown
[11:56:58] [PASSED] VGA
[11:56:58] [PASSED] DVI-I
[11:56:58] [PASSED] DVI-D
[11:56:58] [PASSED] DVI-A
[11:56:58] [PASSED] Composite
[11:56:58] [PASSED] SVIDEO
[11:56:58] [PASSED] LVDS
[11:56:58] [PASSED] Component
[11:56:58] [PASSED] DIN
[11:56:58] [PASSED] DP
[11:56:58] [PASSED] HDMI-A
[11:56:58] [PASSED] HDMI-B
[11:56:58] [PASSED] TV
[11:56:58] [PASSED] eDP
[11:56:58] [PASSED] Virtual
[11:56:58] [PASSED] DSI
[11:56:58] [PASSED] DPI
[11:56:58] [PASSED] Writeback
[11:56:58] [PASSED] SPI
[11:56:58] [PASSED] USB
[11:56:58] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[11:56:58] ======== drm_test_drm_connector_dynamic_init_name  =========
[11:56:58] [PASSED] Unknown
[11:56:58] [PASSED] VGA
[11:56:58] [PASSED] DVI-I
[11:56:58] [PASSED] DVI-D
[11:56:58] [PASSED] DVI-A
[11:56:58] [PASSED] Composite
[11:56:58] [PASSED] SVIDEO
[11:56:58] [PASSED] LVDS
[11:56:58] [PASSED] Component
[11:56:58] [PASSED] DIN
[11:56:58] [PASSED] DP
[11:56:58] [PASSED] HDMI-A
[11:56:58] [PASSED] HDMI-B
[11:56:58] [PASSED] TV
[11:56:58] [PASSED] eDP
[11:56:58] [PASSED] Virtual
[11:56:58] [PASSED] DSI
[11:56:58] [PASSED] DPI
[11:56:58] [PASSED] Writeback
[11:56:58] [PASSED] SPI
[11:56:58] [PASSED] USB
[11:56:58] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[11:56:58] =========== [PASSED] drm_connector_dynamic_init ============
[11:56:58] ==== drm_connector_dynamic_register_early (4 subtests) =====
[11:56:58] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[11:56:58] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[11:56:58] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[11:56:58] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[11:56:58] ====== [PASSED] drm_connector_dynamic_register_early =======
[11:56:58] ======= drm_connector_dynamic_register (7 subtests) ========
[11:56:58] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[11:56:58] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[11:56:58] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[11:56:58] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[11:56:58] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[11:56:58] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[11:56:58] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[11:56:58] ========= [PASSED] drm_connector_dynamic_register ==========
[11:56:58] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[11:56:58] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[11:56:58] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[11:56:58] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[11:56:58] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[11:56:58] ========== drm_test_get_tv_mode_from_name_valid  ===========
[11:56:58] [PASSED] NTSC
[11:56:58] [PASSED] NTSC-443
[11:56:58] [PASSED] NTSC-J
[11:56:58] [PASSED] PAL
[11:56:58] [PASSED] PAL-M
[11:56:58] [PASSED] PAL-N
[11:56:58] [PASSED] SECAM
[11:56:58] [PASSED] Mono
[11:56:58] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[11:56:58] [PASSED] drm_test_get_tv_mode_from_name_truncated
[11:56:58] ============ [PASSED] drm_get_tv_mode_from_name ============
[11:56:58] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[11:56:58] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[11:56:58] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[11:56:58] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[11:56:58] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[11:56:58] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[11:56:58] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[11:56:58] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[11:56:58] [PASSED] VIC 96
[11:56:58] [PASSED] VIC 97
[11:56:58] [PASSED] VIC 101
[11:56:58] [PASSED] VIC 102
[11:56:58] [PASSED] VIC 106
[11:56:58] [PASSED] VIC 107
[11:56:58] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[11:56:58] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[11:56:58] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[11:56:58] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[11:56:58] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[11:56:58] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[11:56:58] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[11:56:58] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[11:56:58] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[11:56:58] [PASSED] Automatic
[11:56:58] [PASSED] Full
[11:56:58] [PASSED] Limited 16:235
[11:56:58] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[11:56:58] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[11:56:58] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[11:56:58] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[11:56:58] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[11:56:58] [PASSED] RGB
[11:56:58] [PASSED] YUV 4:2:0
[11:56:58] [PASSED] YUV 4:2:2
[11:56:58] [PASSED] YUV 4:4:4
[11:56:58] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[11:56:58] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[11:56:58] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[11:56:58] ============= drm_damage_helper (21 subtests) ==============
[11:56:58] [PASSED] drm_test_damage_iter_no_damage
[11:56:58] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[11:56:58] [PASSED] drm_test_damage_iter_no_damage_src_moved
[11:56:58] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[11:56:58] [PASSED] drm_test_damage_iter_no_damage_not_visible
[11:56:58] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[11:56:58] [PASSED] drm_test_damage_iter_no_damage_no_fb
[11:56:58] [PASSED] drm_test_damage_iter_simple_damage
[11:56:58] [PASSED] drm_test_damage_iter_single_damage
[11:56:58] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[11:56:58] [PASSED] drm_test_damage_iter_single_damage_outside_src
[11:56:58] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[11:56:58] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[11:56:58] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[11:56:58] [PASSED] drm_test_damage_iter_single_damage_src_moved
[11:56:58] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[11:56:58] [PASSED] drm_test_damage_iter_damage
[11:56:58] [PASSED] drm_test_damage_iter_damage_one_intersect
[11:56:58] [PASSED] drm_test_damage_iter_damage_one_outside
[11:56:58] [PASSED] drm_test_damage_iter_damage_src_moved
[11:56:58] [PASSED] drm_test_damage_iter_damage_not_visible
[11:56:58] ================ [PASSED] drm_damage_helper ================
[11:56:58] ============== drm_dp_mst_helper (3 subtests) ==============
[11:56:58] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[11:56:58] [PASSED] Clock 154000 BPP 30 DSC disabled
[11:56:58] [PASSED] Clock 234000 BPP 30 DSC disabled
[11:56:58] [PASSED] Clock 297000 BPP 24 DSC disabled
[11:56:58] [PASSED] Clock 332880 BPP 24 DSC enabled
[11:56:58] [PASSED] Clock 324540 BPP 24 DSC enabled
[11:56:58] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[11:56:58] ============== drm_test_dp_mst_calc_pbn_div  ===============
[11:56:58] [PASSED] Link rate 2000000 lane count 4
[11:56:58] [PASSED] Link rate 2000000 lane count 2
[11:56:58] [PASSED] Link rate 2000000 lane count 1
[11:56:58] [PASSED] Link rate 1350000 lane count 4
[11:56:58] [PASSED] Link rate 1350000 lane count 2
[11:56:58] [PASSED] Link rate 1350000 lane count 1
[11:56:58] [PASSED] Link rate 1000000 lane count 4
[11:56:58] [PASSED] Link rate 1000000 lane count 2
[11:56:58] [PASSED] Link rate 1000000 lane count 1
[11:56:58] [PASSED] Link rate 810000 lane count 4
[11:56:58] [PASSED] Link rate 810000 lane count 2
[11:56:58] [PASSED] Link rate 810000 lane count 1
[11:56:58] [PASSED] Link rate 540000 lane count 4
[11:56:58] [PASSED] Link rate 540000 lane count 2
[11:56:58] [PASSED] Link rate 540000 lane count 1
[11:56:58] [PASSED] Link rate 270000 lane count 4
[11:56:58] [PASSED] Link rate 270000 lane count 2
[11:56:58] [PASSED] Link rate 270000 lane count 1
[11:56:58] [PASSED] Link rate 162000 lane count 4
[11:56:58] [PASSED] Link rate 162000 lane count 2
[11:56:58] [PASSED] Link rate 162000 lane count 1
[11:56:58] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[11:56:58] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[11:56:58] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[11:56:58] [PASSED] DP_POWER_UP_PHY with port number
[11:56:58] [PASSED] DP_POWER_DOWN_PHY with port number
[11:56:58] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[11:56:58] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[11:56:58] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[11:56:58] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[11:56:58] [PASSED] DP_QUERY_PAYLOAD with port number
[11:56:58] [PASSED] DP_QUERY_PAYLOAD with VCPI
[11:56:58] [PASSED] DP_REMOTE_DPCD_READ with port number
[11:56:58] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[11:56:58] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[11:56:58] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[11:56:58] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[11:56:58] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[11:56:58] [PASSED] DP_REMOTE_I2C_READ with port number
[11:56:58] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[11:56:58] [PASSED] DP_REMOTE_I2C_READ with transactions array
[11:56:58] [PASSED] DP_REMOTE_I2C_WRITE with port number
[11:56:58] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[11:56:58] [PASSED] DP_REMOTE_I2C_WRITE with data array
[11:56:58] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[11:56:58] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[11:56:58] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[11:56:58] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[11:56:58] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[11:56:58] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[11:56:58] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[11:56:58] ================ [PASSED] drm_dp_mst_helper ================
[11:56:58] ================== drm_exec (7 subtests) ===================
[11:56:58] [PASSED] sanitycheck
[11:56:58] [PASSED] test_lock
[11:56:58] [PASSED] test_lock_unlock
[11:56:58] [PASSED] test_duplicates
[11:56:58] [PASSED] test_prepare
[11:56:58] [PASSED] test_prepare_array
[11:56:58] [PASSED] test_multiple_loops
[11:56:58] ==================== [PASSED] drm_exec =====================
[11:56:58] =========== drm_format_helper_test (17 subtests) ===========
[11:56:58] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[11:56:58] [PASSED] single_pixel_source_buffer
[11:56:58] [PASSED] single_pixel_clip_rectangle
[11:56:58] [PASSED] well_known_colors
[11:56:58] [PASSED] destination_pitch
[11:56:58] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[11:56:58] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[11:56:58] [PASSED] single_pixel_source_buffer
[11:56:58] [PASSED] single_pixel_clip_rectangle
[11:56:58] [PASSED] well_known_colors
[11:56:58] [PASSED] destination_pitch
[11:56:58] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[11:56:58] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[11:56:58] [PASSED] single_pixel_source_buffer
[11:56:58] [PASSED] single_pixel_clip_rectangle
[11:56:58] [PASSED] well_known_colors
[11:56:58] [PASSED] destination_pitch
[11:56:58] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[11:56:58] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[11:56:58] [PASSED] single_pixel_source_buffer
[11:56:58] [PASSED] single_pixel_clip_rectangle
[11:56:58] [PASSED] well_known_colors
[11:56:58] [PASSED] destination_pitch
[11:56:58] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[11:56:58] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[11:56:58] [PASSED] single_pixel_source_buffer
[11:56:58] [PASSED] single_pixel_clip_rectangle
[11:56:58] [PASSED] well_known_colors
[11:56:58] [PASSED] destination_pitch
[11:56:58] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[11:56:58] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[11:56:58] [PASSED] single_pixel_source_buffer
[11:56:58] [PASSED] single_pixel_clip_rectangle
[11:56:58] [PASSED] well_known_colors
[11:56:58] [PASSED] destination_pitch
[11:56:58] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[11:56:58] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[11:56:58] [PASSED] single_pixel_source_buffer
[11:56:58] [PASSED] single_pixel_clip_rectangle
[11:56:58] [PASSED] well_known_colors
[11:56:58] [PASSED] destination_pitch
[11:56:58] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[11:56:58] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[11:56:58] [PASSED] single_pixel_source_buffer
[11:56:58] [PASSED] single_pixel_clip_rectangle
[11:56:58] [PASSED] well_known_colors
[11:56:58] [PASSED] destination_pitch
[11:56:58] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[11:56:58] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[11:56:58] [PASSED] single_pixel_source_buffer
[11:56:58] [PASSED] single_pixel_clip_rectangle
[11:56:58] [PASSED] well_known_colors
[11:56:58] [PASSED] destination_pitch
[11:56:58] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[11:56:58] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[11:56:58] [PASSED] single_pixel_source_buffer
[11:56:58] [PASSED] single_pixel_clip_rectangle
[11:56:58] [PASSED] well_known_colors
[11:56:58] [PASSED] destination_pitch
[11:56:58] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[11:56:58] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[11:56:58] [PASSED] single_pixel_source_buffer
[11:56:58] [PASSED] single_pixel_clip_rectangle
[11:56:58] [PASSED] well_known_colors
[11:56:58] [PASSED] destination_pitch
[11:56:58] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[11:56:58] ============== drm_test_fb_xrgb8888_to_mono  ===============
[11:56:58] [PASSED] single_pixel_source_buffer
[11:56:58] [PASSED] single_pixel_clip_rectangle
[11:56:58] [PASSED] well_known_colors
[11:56:58] [PASSED] destination_pitch
[11:56:58] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[11:56:58] ==================== drm_test_fb_swab  =====================
[11:56:58] [PASSED] single_pixel_source_buffer
[11:56:58] [PASSED] single_pixel_clip_rectangle
[11:56:58] [PASSED] well_known_colors
[11:56:58] [PASSED] destination_pitch
[11:56:58] ================ [PASSED] drm_test_fb_swab =================
[11:56:58] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[11:56:58] [PASSED] single_pixel_source_buffer
[11:56:58] [PASSED] single_pixel_clip_rectangle
[11:56:58] [PASSED] well_known_colors
[11:56:58] [PASSED] destination_pitch
[11:56:58] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[11:56:58] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[11:56:58] [PASSED] single_pixel_source_buffer
[11:56:58] [PASSED] single_pixel_clip_rectangle
[11:56:58] [PASSED] well_known_colors
[11:56:58] [PASSED] destination_pitch
[11:56:58] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[11:56:58] ================= drm_test_fb_clip_offset  =================
[11:56:58] [PASSED] pass through
[11:56:58] [PASSED] horizontal offset
[11:56:58] [PASSED] vertical offset
[11:56:58] [PASSED] horizontal and vertical offset
[11:56:58] [PASSED] horizontal offset (custom pitch)
[11:56:58] [PASSED] vertical offset (custom pitch)
[11:56:58] [PASSED] horizontal and vertical offset (custom pitch)
[11:56:58] ============= [PASSED] drm_test_fb_clip_offset =============
[11:56:58] =================== drm_test_fb_memcpy  ====================
[11:56:58] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[11:56:58] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[11:56:58] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[11:56:58] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[11:56:58] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[11:56:58] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[11:56:58] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[11:56:58] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[11:56:58] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[11:56:58] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[11:56:58] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[11:56:58] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[11:56:58] =============== [PASSED] drm_test_fb_memcpy ================
[11:56:58] ============= [PASSED] drm_format_helper_test ==============
[11:56:58] ================= drm_format (18 subtests) =================
[11:56:58] [PASSED] drm_test_format_block_width_invalid
[11:56:58] [PASSED] drm_test_format_block_width_one_plane
[11:56:58] [PASSED] drm_test_format_block_width_two_plane
[11:56:58] [PASSED] drm_test_format_block_width_three_plane
[11:56:58] [PASSED] drm_test_format_block_width_tiled
[11:56:58] [PASSED] drm_test_format_block_height_invalid
[11:56:58] [PASSED] drm_test_format_block_height_one_plane
[11:56:58] [PASSED] drm_test_format_block_height_two_plane
[11:56:58] [PASSED] drm_test_format_block_height_three_plane
[11:56:58] [PASSED] drm_test_format_block_height_tiled
[11:56:58] [PASSED] drm_test_format_min_pitch_invalid
[11:56:58] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[11:56:58] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[11:56:58] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[11:56:58] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[11:56:58] [PASSED] drm_test_format_min_pitch_two_plane
[11:56:58] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[11:56:58] [PASSED] drm_test_format_min_pitch_tiled
[11:56:58] =================== [PASSED] drm_format ====================
[11:56:58] ============== drm_framebuffer (10 subtests) ===============
[11:56:58] ========== drm_test_framebuffer_check_src_coords  ==========
[11:56:58] [PASSED] Success: source fits into fb
[11:56:58] [PASSED] Fail: overflowing fb with x-axis coordinate
[11:56:58] [PASSED] Fail: overflowing fb with y-axis coordinate
[11:56:58] [PASSED] Fail: overflowing fb with source width
[11:56:58] [PASSED] Fail: overflowing fb with source height
[11:56:58] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[11:56:58] [PASSED] drm_test_framebuffer_cleanup
[11:56:58] =============== drm_test_framebuffer_create  ===============
[11:56:58] [PASSED] ABGR8888 normal sizes
[11:56:58] [PASSED] ABGR8888 max sizes
[11:56:58] [PASSED] ABGR8888 pitch greater than min required
[11:56:58] [PASSED] ABGR8888 pitch less than min required
[11:56:58] [PASSED] ABGR8888 Invalid width
[11:56:58] [PASSED] ABGR8888 Invalid buffer handle
[11:56:58] [PASSED] No pixel format
[11:56:58] [PASSED] ABGR8888 Width 0
[11:56:58] [PASSED] ABGR8888 Height 0
[11:56:58] [PASSED] ABGR8888 Out of bound height * pitch combination
[11:56:58] [PASSED] ABGR8888 Large buffer offset
[11:56:58] [PASSED] ABGR8888 Buffer offset for inexistent plane
[11:56:58] [PASSED] ABGR8888 Invalid flag
[11:56:58] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[11:56:58] [PASSED] ABGR8888 Valid buffer modifier
[11:56:58] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[11:56:58] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[11:56:58] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[11:56:58] [PASSED] NV12 Normal sizes
[11:56:58] [PASSED] NV12 Max sizes
[11:56:58] [PASSED] NV12 Invalid pitch
[11:56:58] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[11:56:58] [PASSED] NV12 different  modifier per-plane
[11:56:58] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[11:56:58] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[11:56:58] [PASSED] NV12 Modifier for inexistent plane
[11:56:58] [PASSED] NV12 Handle for inexistent plane
[11:56:58] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[11:56:58] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[11:56:58] [PASSED] YVU420 Normal sizes
[11:56:58] [PASSED] YVU420 Max sizes
[11:56:58] [PASSED] YVU420 Invalid pitch
[11:56:58] [PASSED] YVU420 Different pitches
[11:56:58] [PASSED] YVU420 Different buffer offsets/pitches
[11:56:58] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[11:56:58] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[11:56:58] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[11:56:58] [PASSED] YVU420 Valid modifier
[11:56:58] [PASSED] YVU420 Different modifiers per plane
[11:56:58] [PASSED] YVU420 Modifier for inexistent plane
[11:56:58] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[11:56:58] [PASSED] X0L2 Normal sizes
[11:56:58] [PASSED] X0L2 Max sizes
[11:56:58] [PASSED] X0L2 Invalid pitch
[11:56:58] [PASSED] X0L2 Pitch greater than minimum required
[11:56:58] [PASSED] X0L2 Handle for inexistent plane
[11:56:58] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[11:56:58] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[11:56:58] [PASSED] X0L2 Valid modifier
[11:56:58] [PASSED] X0L2 Modifier for inexistent plane
[11:56:58] =========== [PASSED] drm_test_framebuffer_create ===========
[11:56:58] [PASSED] drm_test_framebuffer_free
[11:56:58] [PASSED] drm_test_framebuffer_init
[11:56:58] [PASSED] drm_test_framebuffer_init_bad_format
[11:56:58] [PASSED] drm_test_framebuffer_init_dev_mismatch
[11:56:58] [PASSED] drm_test_framebuffer_lookup
[11:56:58] [PASSED] drm_test_framebuffer_lookup_inexistent
[11:56:58] [PASSED] drm_test_framebuffer_modifiers_not_supported
[11:56:58] ================= [PASSED] drm_framebuffer =================
[11:56:58] ================ drm_gem_shmem (8 subtests) ================
[11:56:58] [PASSED] drm_gem_shmem_test_obj_create
[11:56:58] [PASSED] drm_gem_shmem_test_obj_create_private
[11:56:58] [PASSED] drm_gem_shmem_test_pin_pages
[11:56:58] [PASSED] drm_gem_shmem_test_vmap
[11:56:58] [PASSED] drm_gem_shmem_test_get_sg_table
[11:56:58] [PASSED] drm_gem_shmem_test_get_pages_sgt
[11:56:58] [PASSED] drm_gem_shmem_test_madvise
[11:56:58] [PASSED] drm_gem_shmem_test_purge
[11:56:58] ================== [PASSED] drm_gem_shmem ==================
[11:56:58] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[11:56:58] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[11:56:58] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[11:56:58] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[11:56:58] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[11:56:58] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[11:56:58] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[11:56:58] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[11:56:58] [PASSED] Automatic
[11:56:58] [PASSED] Full
[11:56:58] [PASSED] Limited 16:235
[11:56:58] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[11:56:58] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[11:56:58] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[11:56:58] [PASSED] drm_test_check_disable_connector
[11:56:58] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[11:56:58] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[11:56:58] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[11:56:58] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[11:56:58] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[11:56:58] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[11:56:58] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[11:56:58] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[11:56:58] [PASSED] drm_test_check_output_bpc_dvi
[11:56:58] [PASSED] drm_test_check_output_bpc_format_vic_1
[11:56:58] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[11:56:58] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[11:56:58] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[11:56:58] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[11:56:58] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[11:56:58] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[11:56:58] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[11:56:58] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[11:56:58] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[11:56:58] [PASSED] drm_test_check_broadcast_rgb_value
[11:56:58] [PASSED] drm_test_check_bpc_8_value
[11:56:58] [PASSED] drm_test_check_bpc_10_value
[11:56:58] [PASSED] drm_test_check_bpc_12_value
[11:56:58] [PASSED] drm_test_check_format_value
[11:56:58] [PASSED] drm_test_check_tmds_char_value
[11:56:58] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[11:56:58] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[11:56:58] [PASSED] drm_test_check_mode_valid
[11:56:58] [PASSED] drm_test_check_mode_valid_reject
[11:56:58] [PASSED] drm_test_check_mode_valid_reject_rate
[11:56:58] [PASSED] drm_test_check_mode_valid_reject_max_clock
[11:56:58] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[11:56:58] ================= drm_managed (2 subtests) =================
[11:56:58] [PASSED] drm_test_managed_release_action
[11:56:58] [PASSED] drm_test_managed_run_action
[11:56:58] =================== [PASSED] drm_managed ===================
[11:56:58] =================== drm_mm (6 subtests) ====================
[11:56:58] [PASSED] drm_test_mm_init
[11:56:58] [PASSED] drm_test_mm_debug
[11:56:58] [PASSED] drm_test_mm_align32
[11:56:58] [PASSED] drm_test_mm_align64
[11:56:58] [PASSED] drm_test_mm_lowest
[11:56:58] [PASSED] drm_test_mm_highest
[11:56:58] ===================== [PASSED] drm_mm ======================
[11:56:58] ============= drm_modes_analog_tv (5 subtests) =============
[11:56:58] [PASSED] drm_test_modes_analog_tv_mono_576i
[11:56:58] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[11:56:58] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[11:56:58] [PASSED] drm_test_modes_analog_tv_pal_576i
[11:56:58] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[11:56:58] =============== [PASSED] drm_modes_analog_tv ===============
[11:56:58] ============== drm_plane_helper (2 subtests) ===============
[11:56:58] =============== drm_test_check_plane_state  ================
[11:56:58] [PASSED] clipping_simple
[11:56:58] [PASSED] clipping_rotate_reflect
[11:56:58] [PASSED] positioning_simple
[11:56:58] [PASSED] upscaling
[11:56:58] [PASSED] downscaling
[11:56:58] [PASSED] rounding1
[11:56:58] [PASSED] rounding2
[11:56:58] [PASSED] rounding3
[11:56:58] [PASSED] rounding4
[11:56:58] =========== [PASSED] drm_test_check_plane_state ============
[11:56:58] =========== drm_test_check_invalid_plane_state  ============
[11:56:58] [PASSED] positioning_invalid
[11:56:58] [PASSED] upscaling_invalid
[11:56:58] [PASSED] downscaling_invalid
[11:56:58] ======= [PASSED] drm_test_check_invalid_plane_state ========
[11:56:58] ================ [PASSED] drm_plane_helper =================
[11:56:58] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[11:56:58] ====== drm_test_connector_helper_tv_get_modes_check  =======
[11:56:58] [PASSED] None
[11:56:58] [PASSED] PAL
[11:56:58] [PASSED] NTSC
[11:56:58] [PASSED] Both, NTSC Default
[11:56:58] [PASSED] Both, PAL Default
[11:56:58] [PASSED] Both, NTSC Default, with PAL on command-line
[11:56:58] [PASSED] Both, PAL Default, with NTSC on command-line
[11:56:58] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[11:56:58] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[11:56:58] ================== drm_rect (9 subtests) ===================
[11:56:58] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[11:56:58] [PASSED] drm_test_rect_clip_scaled_not_clipped
[11:56:58] [PASSED] drm_test_rect_clip_scaled_clipped
[11:56:58] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[11:56:58] ================= drm_test_rect_intersect  =================
[11:56:58] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[11:56:58] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[11:56:58] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[11:56:58] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[11:56:58] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[11:56:58] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[11:56:58] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[11:56:58] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[11:56:58] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[11:56:58] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[11:56:58] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[11:56:58] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[11:56:58] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[11:56:58] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[11:56:58] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[11:56:58] ============= [PASSED] drm_test_rect_intersect =============
[11:56:58] ================ drm_test_rect_calc_hscale  ================
[11:56:58] [PASSED] normal use
[11:56:58] [PASSED] out of max range
[11:56:58] [PASSED] out of min range
[11:56:58] [PASSED] zero dst
[11:56:58] [PASSED] negative src
[11:56:58] [PASSED] negative dst
[11:56:58] ============ [PASSED] drm_test_rect_calc_hscale ============
[11:56:58] ================ drm_test_rect_calc_vscale  ================
[11:56:58] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[11:56:58] [PASSED] out of max range
[11:56:58] [PASSED] out of min range
[11:56:58] [PASSED] zero dst
[11:56:58] [PASSED] negative src
[11:56:58] [PASSED] negative dst
[11:56:58] ============ [PASSED] drm_test_rect_calc_vscale ============
[11:56:58] ================== drm_test_rect_rotate  ===================
[11:56:58] [PASSED] reflect-x
[11:56:58] [PASSED] reflect-y
[11:56:58] [PASSED] rotate-0
[11:56:58] [PASSED] rotate-90
[11:56:58] [PASSED] rotate-180
[11:56:58] [PASSED] rotate-270
[11:56:58] ============== [PASSED] drm_test_rect_rotate ===============
[11:56:58] ================ drm_test_rect_rotate_inv  =================
[11:56:58] [PASSED] reflect-x
[11:56:58] [PASSED] reflect-y
[11:56:58] [PASSED] rotate-0
[11:56:58] [PASSED] rotate-90
[11:56:58] [PASSED] rotate-180
[11:56:58] [PASSED] rotate-270
[11:56:58] ============ [PASSED] drm_test_rect_rotate_inv =============
[11:56:58] ==================== [PASSED] drm_rect =====================
[11:56:58] ============ drm_sysfb_modeset_test (1 subtest) ============
[11:56:58] ============ drm_test_sysfb_build_fourcc_list  =============
[11:56:58] [PASSED] no native formats
[11:56:58] [PASSED] XRGB8888 as native format
[11:56:58] [PASSED] remove duplicates
[11:56:58] [PASSED] convert alpha formats
[11:56:58] [PASSED] random formats
[11:56:58] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[11:56:58] ============= [PASSED] drm_sysfb_modeset_test ==============
[11:56:58] ================== drm_fixp (2 subtests) ===================
[11:56:58] [PASSED] drm_test_int2fixp
[11:56:58] [PASSED] drm_test_sm2fixp
[11:56:58] ==================== [PASSED] drm_fixp =====================
[11:56:58] ============================================================
[11:56:58] Testing complete. Ran 624 tests: passed: 624
[11:56:58] Elapsed time: 27.358s total, 1.708s configuring, 25.229s building, 0.411s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[11:56:58] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:56:59] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[11:57:09] Starting KUnit Kernel (1/1)...
[11:57:09] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:57:09] ================= ttm_device (5 subtests) ==================
[11:57:09] [PASSED] ttm_device_init_basic
[11:57:09] [PASSED] ttm_device_init_multiple
[11:57:09] [PASSED] ttm_device_fini_basic
[11:57:09] [PASSED] ttm_device_init_no_vma_man
[11:57:09] ================== ttm_device_init_pools  ==================
[11:57:09] [PASSED] No DMA allocations, no DMA32 required
[11:57:09] [PASSED] DMA allocations, DMA32 required
[11:57:09] [PASSED] No DMA allocations, DMA32 required
[11:57:09] [PASSED] DMA allocations, no DMA32 required
[11:57:09] ============== [PASSED] ttm_device_init_pools ==============
[11:57:09] =================== [PASSED] ttm_device ====================
[11:57:09] ================== ttm_pool (8 subtests) ===================
[11:57:09] ================== ttm_pool_alloc_basic  ===================
[11:57:09] [PASSED] One page
[11:57:09] [PASSED] More than one page
[11:57:09] [PASSED] Above the allocation limit
[11:57:09] [PASSED] One page, with coherent DMA mappings enabled
[11:57:09] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[11:57:09] ============== [PASSED] ttm_pool_alloc_basic ===============
[11:57:09] ============== ttm_pool_alloc_basic_dma_addr  ==============
[11:57:09] [PASSED] One page
[11:57:09] [PASSED] More than one page
[11:57:09] [PASSED] Above the allocation limit
[11:57:09] [PASSED] One page, with coherent DMA mappings enabled
[11:57:09] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[11:57:09] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[11:57:09] [PASSED] ttm_pool_alloc_order_caching_match
[11:57:09] [PASSED] ttm_pool_alloc_caching_mismatch
[11:57:09] [PASSED] ttm_pool_alloc_order_mismatch
[11:57:09] [PASSED] ttm_pool_free_dma_alloc
[11:57:09] [PASSED] ttm_pool_free_no_dma_alloc
[11:57:09] [PASSED] ttm_pool_fini_basic
[11:57:09] ==================== [PASSED] ttm_pool =====================
[11:57:09] ================ ttm_resource (8 subtests) =================
[11:57:09] ================= ttm_resource_init_basic  =================
[11:57:09] [PASSED] Init resource in TTM_PL_SYSTEM
[11:57:09] [PASSED] Init resource in TTM_PL_VRAM
[11:57:09] [PASSED] Init resource in a private placement
[11:57:09] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[11:57:09] ============= [PASSED] ttm_resource_init_basic =============
[11:57:09] [PASSED] ttm_resource_init_pinned
[11:57:09] [PASSED] ttm_resource_fini_basic
[11:57:09] [PASSED] ttm_resource_manager_init_basic
[11:57:09] [PASSED] ttm_resource_manager_usage_basic
[11:57:09] [PASSED] ttm_resource_manager_set_used_basic
[11:57:09] [PASSED] ttm_sys_man_alloc_basic
[11:57:09] [PASSED] ttm_sys_man_free_basic
[11:57:09] ================== [PASSED] ttm_resource ===================
[11:57:09] =================== ttm_tt (15 subtests) ===================
[11:57:09] ==================== ttm_tt_init_basic  ====================
[11:57:09] [PASSED] Page-aligned size
[11:57:09] [PASSED] Extra pages requested
[11:57:09] ================ [PASSED] ttm_tt_init_basic ================
[11:57:09] [PASSED] ttm_tt_init_misaligned
[11:57:09] [PASSED] ttm_tt_fini_basic
[11:57:09] [PASSED] ttm_tt_fini_sg
[11:57:09] [PASSED] ttm_tt_fini_shmem
[11:57:09] [PASSED] ttm_tt_create_basic
[11:57:09] [PASSED] ttm_tt_create_invalid_bo_type
[11:57:09] [PASSED] ttm_tt_create_ttm_exists
[11:57:09] [PASSED] ttm_tt_create_failed
[11:57:09] [PASSED] ttm_tt_destroy_basic
[11:57:09] [PASSED] ttm_tt_populate_null_ttm
[11:57:09] [PASSED] ttm_tt_populate_populated_ttm
[11:57:09] [PASSED] ttm_tt_unpopulate_basic
[11:57:09] [PASSED] ttm_tt_unpopulate_empty_ttm
[11:57:09] [PASSED] ttm_tt_swapin_basic
[11:57:09] ===================== [PASSED] ttm_tt ======================
[11:57:09] =================== ttm_bo (14 subtests) ===================
[11:57:09] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[11:57:09] [PASSED] Cannot be interrupted and sleeps
[11:57:09] [PASSED] Cannot be interrupted, locks straight away
[11:57:09] [PASSED] Can be interrupted, sleeps
[11:57:09] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[11:57:09] [PASSED] ttm_bo_reserve_locked_no_sleep
[11:57:09] [PASSED] ttm_bo_reserve_no_wait_ticket
[11:57:09] [PASSED] ttm_bo_reserve_double_resv
[11:57:09] [PASSED] ttm_bo_reserve_interrupted
[11:57:09] [PASSED] ttm_bo_reserve_deadlock
[11:57:09] [PASSED] ttm_bo_unreserve_basic
[11:57:09] [PASSED] ttm_bo_unreserve_pinned
[11:57:09] [PASSED] ttm_bo_unreserve_bulk
[11:57:09] [PASSED] ttm_bo_fini_basic
[11:57:09] [PASSED] ttm_bo_fini_shared_resv
[11:57:09] [PASSED] ttm_bo_pin_basic
[11:57:09] [PASSED] ttm_bo_pin_unpin_resource
[11:57:09] [PASSED] ttm_bo_multiple_pin_one_unpin
[11:57:09] ===================== [PASSED] ttm_bo ======================
[11:57:09] ============== ttm_bo_validate (21 subtests) ===============
[11:57:09] ============== ttm_bo_init_reserved_sys_man  ===============
[11:57:09] [PASSED] Buffer object for userspace
[11:57:09] [PASSED] Kernel buffer object
[11:57:09] [PASSED] Shared buffer object
[11:57:09] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[11:57:09] ============== ttm_bo_init_reserved_mock_man  ==============
[11:57:09] [PASSED] Buffer object for userspace
[11:57:09] [PASSED] Kernel buffer object
[11:57:09] [PASSED] Shared buffer object
[11:57:09] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[11:57:09] [PASSED] ttm_bo_init_reserved_resv
[11:57:09] ================== ttm_bo_validate_basic  ==================
[11:57:09] [PASSED] Buffer object for userspace
[11:57:09] [PASSED] Kernel buffer object
[11:57:09] [PASSED] Shared buffer object
[11:57:09] ============== [PASSED] ttm_bo_validate_basic ==============
[11:57:09] [PASSED] ttm_bo_validate_invalid_placement
[11:57:09] ============= ttm_bo_validate_same_placement  ==============
[11:57:09] [PASSED] System manager
[11:57:09] [PASSED] VRAM manager
[11:57:09] ========= [PASSED] ttm_bo_validate_same_placement ==========
[11:57:09] [PASSED] ttm_bo_validate_failed_alloc
[11:57:09] [PASSED] ttm_bo_validate_pinned
[11:57:09] [PASSED] ttm_bo_validate_busy_placement
[11:57:09] ================ ttm_bo_validate_multihop  =================
[11:57:09] [PASSED] Buffer object for userspace
[11:57:09] [PASSED] Kernel buffer object
[11:57:09] [PASSED] Shared buffer object
[11:57:09] ============ [PASSED] ttm_bo_validate_multihop =============
[11:57:09] ========== ttm_bo_validate_no_placement_signaled  ==========
[11:57:09] [PASSED] Buffer object in system domain, no page vector
[11:57:09] [PASSED] Buffer object in system domain with an existing page vector
[11:57:09] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[11:57:09] ======== ttm_bo_validate_no_placement_not_signaled  ========
[11:57:09] [PASSED] Buffer object for userspace
[11:57:09] [PASSED] Kernel buffer object
[11:57:09] [PASSED] Shared buffer object
[11:57:09] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[11:57:09] [PASSED] ttm_bo_validate_move_fence_signaled
[11:57:09] ========= ttm_bo_validate_move_fence_not_signaled  =========
[11:57:09] [PASSED] Waits for GPU
[11:57:09] [PASSED] Tries to lock straight away
[11:57:09] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[11:57:09] [PASSED] ttm_bo_validate_happy_evict
[11:57:09] [PASSED] ttm_bo_validate_all_pinned_evict
[11:57:09] [PASSED] ttm_bo_validate_allowed_only_evict
[11:57:09] [PASSED] ttm_bo_validate_deleted_evict
[11:57:09] [PASSED] ttm_bo_validate_busy_domain_evict
[11:57:09] [PASSED] ttm_bo_validate_evict_gutting
[11:57:09] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[11:57:09] ================= [PASSED] ttm_bo_validate =================
[11:57:09] ============================================================
[11:57:09] Testing complete. Ran 101 tests: passed: 101
[11:57:09] Elapsed time: 11.526s total, 1.695s configuring, 9.565s building, 0.217s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✗ Xe.CI.BAT: failure for drm/xe/guc: Add Wa_14025883347 for GuC DMA failure on reset (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 3218 bytes --]

== Series Details ==

Series: drm/xe/guc: Add Wa_14025883347 for GuC DMA failure on reset (rev2)
URL   : https://patchwork.freedesktop.org/series/160091/
State : failure

== Summary ==

CI Bug Log - changes from xe-4395-278a33d3977124821c19b51fb88d9d651b4fe40a_BAT -> xe-pw-160091v2_BAT
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-160091v2_BAT absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-160091v2_BAT, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (12 -> 12)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-160091v2_BAT:

### IGT changes ###

#### Possible regressions ####

  * igt@sriov_basic@enable-vfs-autoprobe-on:
    - bat-ptl-1:          [PASS][1] -> [ABORT][2] +1 other test abort
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4395-278a33d3977124821c19b51fb88d9d651b4fe40a/bat-ptl-1/igt@sriov_basic@enable-vfs-autoprobe-on.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/bat-ptl-1/igt@sriov_basic@enable-vfs-autoprobe-on.html
    - bat-bmg-2:          [PASS][3] -> [ABORT][4] +1 other test abort
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4395-278a33d3977124821c19b51fb88d9d651b4fe40a/bat-bmg-2/igt@sriov_basic@enable-vfs-autoprobe-on.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/bat-bmg-2/igt@sriov_basic@enable-vfs-autoprobe-on.html

  * igt@sriov_basic@enable-vfs-autoprobe-on@numvfs-1:
    - bat-bmg-1:          [PASS][5] -> [ABORT][6] +1 other test abort
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4395-278a33d3977124821c19b51fb88d9d651b4fe40a/bat-bmg-1/igt@sriov_basic@enable-vfs-autoprobe-on@numvfs-1.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/bat-bmg-1/igt@sriov_basic@enable-vfs-autoprobe-on@numvfs-1.html
    - bat-ptl-2:          [PASS][7] -> [ABORT][8] +1 other test abort
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4395-278a33d3977124821c19b51fb88d9d651b4fe40a/bat-ptl-2/igt@sriov_basic@enable-vfs-autoprobe-on@numvfs-1.html
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/bat-ptl-2/igt@sriov_basic@enable-vfs-autoprobe-on@numvfs-1.html

  * igt@xe_module_load@load:
    - bat-ptl-vm:         [PASS][9] -> [ABORT][10]
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4395-278a33d3977124821c19b51fb88d9d651b4fe40a/bat-ptl-vm/igt@xe_module_load@load.html
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/bat-ptl-vm/igt@xe_module_load@load.html

  


Build changes
-------------

  * Linux: xe-4395-278a33d3977124821c19b51fb88d9d651b4fe40a -> xe-pw-160091v2

  IGT_8704: 8704
  xe-4395-278a33d3977124821c19b51fb88d9d651b4fe40a: 278a33d3977124821c19b51fb88d9d651b4fe40a
  xe-pw-160091v2: 160091v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/index.html

[-- Attachment #2: Type: text/html, Size: 3890 bytes --]

✗ Xe.CI.Full: failure for drm/xe/guc: Add Wa_14025883347 for GuC DMA failure on reset (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 30165 bytes --]

== Series Details ==

Series: drm/xe/guc: Add Wa_14025883347 for GuC DMA failure on reset (rev2)
URL   : https://patchwork.freedesktop.org/series/160091/
State : failure

== Summary ==

CI Bug Log - changes from xe-4395-278a33d3977124821c19b51fb88d9d651b4fe40a_FULL -> xe-pw-160091v2_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-160091v2_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-160091v2_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-160091v2_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@xe_pmu@engine-activity-render-node-idle:
    - shard-bmg:          NOTRUN -> [ABORT][1] +9 other tests abort
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-3/igt@xe_pmu@engine-activity-render-node-idle.html

  * igt@xe_pmu@engine-activity-render-node-load:
    - shard-bmg:          [PASS][2] -> [ABORT][3] +31 other tests abort
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4395-278a33d3977124821c19b51fb88d9d651b4fe40a/shard-bmg-10/igt@xe_pmu@engine-activity-render-node-load.html
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-3/igt@xe_pmu@engine-activity-render-node-load.html

  
Known issues
------------

  Here are the changes found in xe-pw-160091v2_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_big_fb@x-tiled-8bpp-rotate-270:
    - shard-bmg:          NOTRUN -> [SKIP][4] ([Intel XE#2327]) +1 other test skip
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-3/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-addfb:
    - shard-bmg:          NOTRUN -> [SKIP][5] ([Intel XE#2328])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-10/igt@kms_big_fb@y-tiled-addfb.html

  * igt@kms_big_fb@yf-tiled-32bpp-rotate-0:
    - shard-bmg:          NOTRUN -> [SKIP][6] ([Intel XE#1124]) +5 other tests skip
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-3/igt@kms_big_fb@yf-tiled-32bpp-rotate-0.html

  * igt@kms_bw@connected-linear-tiling-3-displays-2560x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][7] ([Intel XE#2314] / [Intel XE#2894]) +1 other test skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-3/igt@kms_bw@connected-linear-tiling-3-displays-2560x1440p.html

  * igt@kms_bw@linear-tiling-2-displays-2560x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#367]) +1 other test skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-9/igt@kms_bw@linear-tiling-2-displays-2560x1440p.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs@pipe-c-dp-2:
    - shard-bmg:          NOTRUN -> [SKIP][9] ([Intel XE#2652] / [Intel XE#787]) +17 other tests skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-10/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs@pipe-c-dp-2.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc:
    - shard-bmg:          NOTRUN -> [SKIP][10] ([Intel XE#3432])
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-10/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][11] ([Intel XE#2887]) +8 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-3/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs.html

  * igt@kms_chamelium_color@ctm-0-50:
    - shard-bmg:          NOTRUN -> [SKIP][12] ([Intel XE#2325]) +1 other test skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-10/igt@kms_chamelium_color@ctm-0-50.html

  * igt@kms_chamelium_frames@hdmi-cmp-planar-formats:
    - shard-bmg:          NOTRUN -> [SKIP][13] ([Intel XE#2252]) +4 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-3/igt@kms_chamelium_frames@hdmi-cmp-planar-formats.html

  * igt@kms_content_protection@atomic-dpms-hdcp14@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][14] ([Intel XE#3304]) +1 other test fail
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-8/igt@kms_content_protection@atomic-dpms-hdcp14@pipe-a-dp-2.html

  * igt@kms_content_protection@dp-mst-type-0:
    - shard-bmg:          NOTRUN -> [SKIP][15] ([Intel XE#2390] / [Intel XE#6974]) +1 other test skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-9/igt@kms_content_protection@dp-mst-type-0.html

  * igt@kms_cursor_crc@cursor-offscreen-512x170:
    - shard-bmg:          NOTRUN -> [SKIP][16] ([Intel XE#2321]) +1 other test skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-9/igt@kms_cursor_crc@cursor-offscreen-512x170.html

  * igt@kms_cursor_crc@cursor-onscreen-64x21:
    - shard-bmg:          NOTRUN -> [SKIP][17] ([Intel XE#2320]) +2 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-9/igt@kms_cursor_crc@cursor-onscreen-64x21.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
    - shard-bmg:          NOTRUN -> [SKIP][18] ([Intel XE#2286])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-3/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html

  * igt@kms_dp_link_training@uhbr-sst:
    - shard-bmg:          NOTRUN -> [SKIP][19] ([Intel XE#4354])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-3/igt@kms_dp_link_training@uhbr-sst.html

  * igt@kms_dsc@dsc-with-output-formats:
    - shard-bmg:          NOTRUN -> [SKIP][20] ([Intel XE#2244])
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-9/igt@kms_dsc@dsc-with-output-formats.html

  * igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area:
    - shard-bmg:          NOTRUN -> [SKIP][21] ([Intel XE#4422])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-8/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area.html

  * igt@kms_feature_discovery@dp-mst:
    - shard-bmg:          NOTRUN -> [SKIP][22] ([Intel XE#2375])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-10/igt@kms_feature_discovery@dp-mst.html

  * igt@kms_feature_discovery@psr2:
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#2374])
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-3/igt@kms_feature_discovery@psr2.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling:
    - shard-bmg:          NOTRUN -> [SKIP][24] ([Intel XE#2293] / [Intel XE#2380]) +3 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-10/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling@pipe-a-valid-mode:
    - shard-bmg:          NOTRUN -> [SKIP][25] ([Intel XE#2293]) +3 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-10/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][26] ([Intel XE#4141]) +7 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-argb161616f-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][27] ([Intel XE#7061]) +5 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-9/igt@kms_frontbuffer_tracking@fbc-argb161616f-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-indfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][28] ([Intel XE#2311]) +14 other tests skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][29] ([Intel XE#2313]) +18 other tests skip
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-9/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_joiner@basic-big-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][30] ([Intel XE#6901]) +1 other test skip
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-10/igt@kms_joiner@basic-big-joiner.html

  * igt@kms_pipe_stress@stress-xrgb8888-yftiled:
    - shard-bmg:          NOTRUN -> [SKIP][31] ([Intel XE#6912])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-10/igt@kms_pipe_stress@stress-xrgb8888-yftiled.html

  * igt@kms_plane_multiple@2x-tiling-yf:
    - shard-bmg:          NOTRUN -> [SKIP][32] ([Intel XE#5021])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-3/igt@kms_plane_multiple@2x-tiling-yf.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-b:
    - shard-bmg:          NOTRUN -> [SKIP][33] ([Intel XE#6886]) +4 other tests skip
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-3/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-b.html

  * igt@kms_pm_backlight@fade-with-dpms:
    - shard-bmg:          NOTRUN -> [SKIP][34] ([Intel XE#870])
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-9/igt@kms_pm_backlight@fade-with-dpms.html

  * igt@kms_pm_rpm@dpms-mode-unset-lpsp:
    - shard-bmg:          NOTRUN -> [SKIP][35] ([Intel XE#1439] / [Intel XE#836])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-3/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html

  * igt@kms_pm_rpm@modeset-lpsp-stress:
    - shard-bmg:          NOTRUN -> [SKIP][36] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#836])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-10/igt@kms_pm_rpm@modeset-lpsp-stress.html

  * igt@kms_pm_rpm@package-g7:
    - shard-bmg:          NOTRUN -> [SKIP][37] ([Intel XE#6814])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-3/igt@kms_pm_rpm@package-g7.html

  * igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-fully-sf:
    - shard-bmg:          NOTRUN -> [SKIP][38] ([Intel XE#1406] / [Intel XE#1489]) +6 other tests skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-9/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_su@page_flip-p010:
    - shard-bmg:          NOTRUN -> [SKIP][39] ([Intel XE#1406] / [Intel XE#2387])
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-8/igt@kms_psr2_su@page_flip-p010.html

  * igt@kms_psr@psr-sprite-render:
    - shard-bmg:          NOTRUN -> [SKIP][40] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +5 other tests skip
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-10/igt@kms_psr@psr-sprite-render.html

  * igt@kms_rotation_crc@primary-rotation-90:
    - shard-bmg:          NOTRUN -> [SKIP][41] ([Intel XE#3414] / [Intel XE#3904])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-10/igt@kms_rotation_crc@primary-rotation-90.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-0:
    - shard-bmg:          NOTRUN -> [SKIP][42] ([Intel XE#2330])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-3/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html

  * igt@kms_sharpness_filter@filter-rotations:
    - shard-bmg:          NOTRUN -> [SKIP][43] ([Intel XE#6503]) +1 other test skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-10/igt@kms_sharpness_filter@filter-rotations.html

  * igt@kms_vrr@flipline:
    - shard-bmg:          NOTRUN -> [SKIP][44] ([Intel XE#1499])
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-3/igt@kms_vrr@flipline.html

  * igt@xe_eudebug@basic-exec-queues:
    - shard-bmg:          NOTRUN -> [SKIP][45] ([Intel XE#4837]) +4 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-9/igt@xe_eudebug@basic-exec-queues.html

  * igt@xe_eudebug_online@stopped-thread:
    - shard-bmg:          NOTRUN -> [SKIP][46] ([Intel XE#4837] / [Intel XE#6665]) +6 other tests skip
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-3/igt@xe_eudebug_online@stopped-thread.html

  * igt@xe_exec_basic@multigpu-once-null-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][47] ([Intel XE#2322]) +5 other tests skip
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-9/igt@xe_exec_basic@multigpu-once-null-rebind.html

  * igt@xe_exec_multi_queue@one-queue-preempt-mode-close-fd-smem:
    - shard-bmg:          NOTRUN -> [SKIP][48] ([Intel XE#6874]) +17 other tests skip
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-10/igt@xe_exec_multi_queue@one-queue-preempt-mode-close-fd-smem.html

  * igt@xe_exec_store@basic-all@engine-drm_xe_engine_class_compute-instance-0-tile-0:
    - shard-lnl:          [PASS][49] -> [DMESG-WARN][50] ([Intel XE#7063])
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4395-278a33d3977124821c19b51fb88d9d651b4fe40a/shard-lnl-8/igt@xe_exec_store@basic-all@engine-drm_xe_engine_class_compute-instance-0-tile-0.html
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-lnl-5/igt@xe_exec_store@basic-all@engine-drm_xe_engine_class_compute-instance-0-tile-0.html

  * igt@xe_exec_system_allocator@many-64k-mmap-new-huge:
    - shard-bmg:          NOTRUN -> [SKIP][51] ([Intel XE#5007]) +1 other test skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-3/igt@xe_exec_system_allocator@many-64k-mmap-new-huge.html

  * igt@xe_exec_system_allocator@many-stride-new-prefetch:
    - shard-bmg:          NOTRUN -> [INCOMPLETE][52] ([Intel XE#7098])
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-10/igt@xe_exec_system_allocator@many-stride-new-prefetch.html

  * igt@xe_exec_system_allocator@process-many-large-execqueues-mmap-new-huge:
    - shard-bmg:          NOTRUN -> [SKIP][53] ([Intel XE#4943]) +12 other tests skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-3/igt@xe_exec_system_allocator@process-many-large-execqueues-mmap-new-huge.html

  * igt@xe_multigpu_svm@mgpu-migration-prefetch:
    - shard-bmg:          NOTRUN -> [SKIP][54] ([Intel XE#6964]) +1 other test skip
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-10/igt@xe_multigpu_svm@mgpu-migration-prefetch.html

  * igt@xe_pat@pat-index-xehpc:
    - shard-bmg:          NOTRUN -> [SKIP][55] ([Intel XE#1420])
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-8/igt@xe_pat@pat-index-xehpc.html

  * igt@xe_pm@s2idle-d3cold-basic-exec:
    - shard-bmg:          NOTRUN -> [SKIP][56] ([Intel XE#2284]) +1 other test skip
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-3/igt@xe_pm@s2idle-d3cold-basic-exec.html

  * igt@xe_pxp@pxp-stale-bo-bind-post-termination-irq:
    - shard-bmg:          NOTRUN -> [SKIP][57] ([Intel XE#4733]) +2 other tests skip
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-9/igt@xe_pxp@pxp-stale-bo-bind-post-termination-irq.html

  * igt@xe_query@multigpu-query-invalid-cs-cycles:
    - shard-bmg:          NOTRUN -> [SKIP][58] ([Intel XE#944]) +1 other test skip
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-10/igt@xe_query@multigpu-query-invalid-cs-cycles.html

  
#### Possible fixes ####

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
    - shard-lnl:          [FAIL][59] ([Intel XE#301]) -> [PASS][60] +2 other tests pass
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4395-278a33d3977124821c19b51fb88d9d651b4fe40a/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html

  * igt@xe_exec_reset@gt-reset-stress:
    - shard-lnl:          [DMESG-WARN][61] ([Intel XE#7023]) -> [PASS][62]
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4395-278a33d3977124821c19b51fb88d9d651b4fe40a/shard-lnl-2/igt@xe_exec_reset@gt-reset-stress.html
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-lnl-2/igt@xe_exec_reset@gt-reset-stress.html

  * igt@xe_exec_store@basic-all@engine-drm_xe_engine_class_render-instance-0-tile-0:
    - shard-lnl:          [DMESG-WARN][63] ([Intel XE#7063]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4395-278a33d3977124821c19b51fb88d9d651b4fe40a/shard-lnl-8/igt@xe_exec_store@basic-all@engine-drm_xe_engine_class_render-instance-0-tile-0.html
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-lnl-5/igt@xe_exec_store@basic-all@engine-drm_xe_engine_class_render-instance-0-tile-0.html

  * igt@xe_module_load@load:
    - shard-bmg:          ([ABORT][65], [PASS][66], [PASS][67], [PASS][68], [PASS][69], [PASS][70], [PASS][71], [PASS][72], [PASS][73], [PASS][74], [PASS][75], [PASS][76], [PASS][77], [PASS][78], [PASS][79], [PASS][80], [PASS][81], [PASS][82], [PASS][83], [ABORT][84], [ABORT][85], [PASS][86], [PASS][87]) ([Intel XE#7083]) -> ([PASS][88], [PASS][89], [PASS][90], [PASS][91], [PASS][92], [PASS][93], [PASS][94], [PASS][95], [PASS][96], [PASS][97], [PASS][98], [PASS][99], [PASS][100], [PASS][101], [PASS][102], [PASS][103], [PASS][104], [PASS][105], [PASS][106], [PASS][107], [PASS][108], [PASS][109], [PASS][110], [PASS][111], [PASS][112])
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4395-278a33d3977124821c19b51fb88d9d651b4fe40a/shard-bmg-6/igt@xe_module_load@load.html
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4395-278a33d3977124821c19b51fb88d9d651b4fe40a/shard-bmg-3/igt@xe_module_load@load.html
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4395-278a33d3977124821c19b51fb88d9d651b4fe40a/shard-bmg-2/igt@xe_module_load@load.html
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4395-278a33d3977124821c19b51fb88d9d651b4fe40a/shard-bmg-3/igt@xe_module_load@load.html
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4395-278a33d3977124821c19b51fb88d9d651b4fe40a/shard-bmg-1/igt@xe_module_load@load.html
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4395-278a33d3977124821c19b51fb88d9d651b4fe40a/shard-bmg-1/igt@xe_module_load@load.html
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4395-278a33d3977124821c19b51fb88d9d651b4fe40a/shard-bmg-1/igt@xe_module_load@load.html
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4395-278a33d3977124821c19b51fb88d9d651b4fe40a/shard-bmg-10/igt@xe_module_load@load.html
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4395-278a33d3977124821c19b51fb88d9d651b4fe40a/shard-bmg-9/igt@xe_module_load@load.html
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4395-278a33d3977124821c19b51fb88d9d651b4fe40a/shard-bmg-9/igt@xe_module_load@load.html
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4395-278a33d3977124821c19b51fb88d9d651b4fe40a/shard-bmg-9/igt@xe_module_load@load.html
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4395-278a33d3977124821c19b51fb88d9d651b4fe40a/shard-bmg-1/igt@xe_module_load@load.html
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4395-278a33d3977124821c19b51fb88d9d651b4fe40a/shard-bmg-10/igt@xe_module_load@load.html
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4395-278a33d3977124821c19b51fb88d9d651b4fe40a/shard-bmg-2/igt@xe_module_load@load.html
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4395-278a33d3977124821c19b51fb88d9d651b4fe40a/shard-bmg-8/igt@xe_module_load@load.html
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4395-278a33d3977124821c19b51fb88d9d651b4fe40a/shard-bmg-8/igt@xe_module_load@load.html
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4395-278a33d3977124821c19b51fb88d9d651b4fe40a/shard-bmg-7/igt@xe_module_load@load.html
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4395-278a33d3977124821c19b51fb88d9d651b4fe40a/shard-bmg-8/igt@xe_module_load@load.html
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4395-278a33d3977124821c19b51fb88d9d651b4fe40a/shard-bmg-7/igt@xe_module_load@load.html
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4395-278a33d3977124821c19b51fb88d9d651b4fe40a/shard-bmg-6/igt@xe_module_load@load.html
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4395-278a33d3977124821c19b51fb88d9d651b4fe40a/shard-bmg-6/igt@xe_module_load@load.html
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4395-278a33d3977124821c19b51fb88d9d651b4fe40a/shard-bmg-10/igt@xe_module_load@load.html
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4395-278a33d3977124821c19b51fb88d9d651b4fe40a/shard-bmg-7/igt@xe_module_load@load.html
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-3/igt@xe_module_load@load.html
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-7/igt@xe_module_load@load.html
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-9/igt@xe_module_load@load.html
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-8/igt@xe_module_load@load.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-9/igt@xe_module_load@load.html
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-9/igt@xe_module_load@load.html
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-8/igt@xe_module_load@load.html
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-8/igt@xe_module_load@load.html
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-7/igt@xe_module_load@load.html
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-1/igt@xe_module_load@load.html
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-2/igt@xe_module_load@load.html
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-2/igt@xe_module_load@load.html
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-2/igt@xe_module_load@load.html
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-2/igt@xe_module_load@load.html
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-8/igt@xe_module_load@load.html
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-10/igt@xe_module_load@load.html
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-2/igt@xe_module_load@load.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-10/igt@xe_module_load@load.html
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-3/igt@xe_module_load@load.html
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-1/igt@xe_module_load@load.html
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-1/igt@xe_module_load@load.html
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-1/igt@xe_module_load@load.html
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-10/igt@xe_module_load@load.html
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-3/igt@xe_module_load@load.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-10/igt@xe_module_load@load.html

  
#### Warnings ####

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [ABORT][113] ([Intel XE#6740]) -> [SKIP][114] ([Intel XE#1503])
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4395-278a33d3977124821c19b51fb88d9d651b4fe40a/shard-bmg-1/igt@kms_hdr@invalid-hdr.html
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/shard-bmg-9/igt@kms_hdr@invalid-hdr.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1420]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1420
  [Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2286]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2286
  [Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2328]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2328
  [Intel XE#2330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2330
  [Intel XE#2374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2374
  [Intel XE#2375]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2375
  [Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
  [Intel XE#2387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2387
  [Intel XE#2390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2390
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
  [Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
  [Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
  [Intel XE#5007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5007
  [Intel XE#5021]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5021
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#6665]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6665
  [Intel XE#6740]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6740
  [Intel XE#6814]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6814
  [Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
  [Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
  [Intel XE#6901]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6901
  [Intel XE#6912]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6912
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#6974]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6974
  [Intel XE#7023]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7023
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7063]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7063
  [Intel XE#7083]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7083
  [Intel XE#7098]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7098
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-4395-278a33d3977124821c19b51fb88d9d651b4fe40a -> xe-pw-160091v2

  IGT_8704: 8704
  xe-4395-278a33d3977124821c19b51fb88d9d651b4fe40a: 278a33d3977124821c19b51fb88d9d651b4fe40a
  xe-pw-160091v2: 160091v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160091v2/index.html

[-- Attachment #2: Type: text/html, Size: 32891 bytes --]

Re: [PATCH v2 2/2] drm/xe/guc: Add Wa_14025883347 for GuC DMA failure on reset

[Nilawar, Badal]

On 16-01-2026 16:04, Sk Anirban wrote:
> Prevent GuC firmware DMA failures during GuC-only reset by disabling
> idle flow and verifying SRAM handling completion. Without this, reset
> can be issued while SRAM handler is copying WOPCM to SRAM,
> causing GuC HW to get stuck.
>
> v2: Modify error message (Badal)
>      Rename reg bit name (Daniele)
>      Update WA skip condition (Daniele)
>      Update SRAM handling logic (Daniele)
>
> Signed-off-by: Sk Anirban <sk.anirban@intel.com>
> ---
>   drivers/gpu/drm/xe/regs/xe_guc_regs.h |  8 +++++++
>   drivers/gpu/drm/xe/xe_guc.c           | 30 +++++++++++++++++++++++++++
>   drivers/gpu/drm/xe/xe_wa_oob.rules    |  9 ++++++++
>   3 files changed, 47 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_guc_regs.h b/drivers/gpu/drm/xe/regs/xe_guc_regs.h
> index 87984713dd12..c9cb02f32f5a 100644
> --- a/drivers/gpu/drm/xe/regs/xe_guc_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_guc_regs.h
> @@ -40,6 +40,9 @@
>   #define   GS_BOOTROM_JUMP_PASSED		REG_FIELD_PREP(GS_BOOTROM_MASK, 0x76)
>   #define   GS_MIA_IN_RESET			REG_BIT(0)
>   
> +#define GUC_HASH_BOOT_CHECK			XE_REG(0xc010)
%s/_HASH_BOOT_CHECK/_BOOT_HASH_CHECK/ the way its defined in Bspecs
> +#define   GUC_BOOT_UKERNEL_VALID		REG_BIT(31)
> +
>   #define GUC_HEADER_INFO				XE_REG(0xc014)
>   
>   #define GUC_WOPCM_SIZE				XE_REG(0xc050)
> @@ -83,7 +86,12 @@
>   #define   GUC_WOPCM_OFFSET_MASK			REG_GENMASK(31, GUC_WOPCM_OFFSET_SHIFT)
>   #define   HUC_LOADING_AGENT_GUC			REG_BIT(1)
>   #define   GUC_WOPCM_OFFSET_VALID		REG_BIT(0)
> +
> +#define GUC_SRAM_STATUS				XE_REG(0xc398)
> +#define   GUC_SRAM_HANDLING_MASK		REG_GENMASK(8, 7)
> +
>   #define GUC_MAX_IDLE_COUNT			XE_REG(0xc3e4)
> +#define   GUC_IDLE_FLOW_DISABLE			REG_BIT(31)
>   #define GUC_PMTIMESTAMP_LO			XE_REG(0xc3e8)
>   #define GUC_PMTIMESTAMP_HI			XE_REG(0xc3ec)
>   
> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> index 44360437beeb..42658a409556 100644
> --- a/drivers/gpu/drm/xe/xe_guc.c
> +++ b/drivers/gpu/drm/xe/xe_guc.c
> @@ -900,6 +900,33 @@ int xe_guc_post_load_init(struct xe_guc *guc)
>   	return xe_guc_submit_enable(guc);
>   }
>   
> +/*
> + * Wa_14025883347: Prevent GuC firmware DMA failures during GuC-only reset by ensuring
> + * SRAM save/restore operations are complete before reset.
> + */
> +static void guc_prevent_fw_dma_failure_on_reset(struct xe_guc *guc)
> +{
> +	struct xe_gt *gt = guc_to_gt(guc);
> +	u32 boot_hash_chk, guc_status, sram_status;
> +	int ret;
> +
> +	guc_status = xe_mmio_read32(&gt->mmio, GUC_STATUS);
> +	if (guc_status & GS_MIA_IN_RESET)
> +		return;
> +
> +	boot_hash_chk = xe_mmio_read32(&gt->mmio, GUC_HASH_BOOT_CHECK);
> +	if (!(boot_hash_chk & GUC_BOOT_UKERNEL_VALID))
> +		return;
> +
> +	xe_mmio_rmw32(&gt->mmio, GUC_MAX_IDLE_COUNT, 0, GUC_IDLE_FLOW_DISABLE);
> +
> +	ret = xe_mmio_wait32(&gt->mmio, GUC_SRAM_STATUS, GUC_SRAM_HANDLING_MASK,
> +			     0, 5000, &sram_status, false);
> +	if (ret)
> +		xe_gt_warn(gt, "SRAM handling not complete (GUC_SRAM_STATUS: 0x%x)\n",
> +			   sram_status);
> +}
> +
>   int xe_guc_reset(struct xe_guc *guc)
>   {
>   	struct xe_gt *gt = guc_to_gt(guc);
> @@ -909,6 +936,9 @@ int xe_guc_reset(struct xe_guc *guc)
>   
>   	xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
>   
> +	if (XE_GT_WA(gt, 14025883347))
> +		guc_prevent_fw_dma_failure_on_reset(guc);
> +
>   	if (IS_SRIOV_VF(gt_to_xe(gt)))
>   		return xe_gt_sriov_vf_bootstrap(gt);

Place WA code after IS_SRIOV_VF check to avoid applying it for VFs.

Thanks,
Badal

>   
> diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
> index 5cd7fa6d2a5c..ff2efc7a68cc 100644
> --- a/drivers/gpu/drm/xe/xe_wa_oob.rules
> +++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
> @@ -73,3 +73,12 @@
>   15015404425_disable	PLATFORM(PANTHERLAKE), MEDIA_STEP(B0, FOREVER)
>   16026007364    MEDIA_VERSION(3000)
>   14020316580    MEDIA_VERSION(1301)
> +
> +14025883347	MEDIA_VERSION(1301)
> +		MEDIA_VERSION(2000)
> +		MEDIA_VERSION(3000)
> +		MEDIA_VERSION(3002)
> +		MEDIA_VERSION(3500)
> +		MEDIA_VERSION(3503)
> +		GRAPHICS_VERSION_RANGE(3000, 3001)
> +		GRAPHICS_VERSION_RANGE(3003, 3005)

Re: [PATCH v2 2/2] drm/xe/guc: Add Wa_14025883347 for GuC DMA failure on reset

[Daniele Ceraolo Spurio]

On 1/16/2026 2:34 AM, Sk Anirban wrote:
> Prevent GuC firmware DMA failures during GuC-only reset by disabling
> idle flow and verifying SRAM handling completion. Without this, reset
> can be issued while SRAM handler is copying WOPCM to SRAM,
> causing GuC HW to get stuck.
>
> v2: Modify error message (Badal)
>      Rename reg bit name (Daniele)
>      Update WA skip condition (Daniele)
>      Update SRAM handling logic (Daniele)
>
> Signed-off-by: Sk Anirban <sk.anirban@intel.com>
> ---
>   drivers/gpu/drm/xe/regs/xe_guc_regs.h |  8 +++++++
>   drivers/gpu/drm/xe/xe_guc.c           | 30 +++++++++++++++++++++++++++
>   drivers/gpu/drm/xe/xe_wa_oob.rules    |  9 ++++++++
>   3 files changed, 47 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_guc_regs.h b/drivers/gpu/drm/xe/regs/xe_guc_regs.h
> index 87984713dd12..c9cb02f32f5a 100644
> --- a/drivers/gpu/drm/xe/regs/xe_guc_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_guc_regs.h
> @@ -40,6 +40,9 @@
>   #define   GS_BOOTROM_JUMP_PASSED		REG_FIELD_PREP(GS_BOOTROM_MASK, 0x76)
>   #define   GS_MIA_IN_RESET			REG_BIT(0)
>   
> +#define GUC_HASH_BOOT_CHECK			XE_REG(0xc010)
> +#define   GUC_BOOT_UKERNEL_VALID		REG_BIT(31)
> +
>   #define GUC_HEADER_INFO				XE_REG(0xc014)
>   
>   #define GUC_WOPCM_SIZE				XE_REG(0xc050)
> @@ -83,7 +86,12 @@
>   #define   GUC_WOPCM_OFFSET_MASK			REG_GENMASK(31, GUC_WOPCM_OFFSET_SHIFT)
>   #define   HUC_LOADING_AGENT_GUC			REG_BIT(1)
>   #define   GUC_WOPCM_OFFSET_VALID		REG_BIT(0)
> +
> +#define GUC_SRAM_STATUS				XE_REG(0xc398)
> +#define   GUC_SRAM_HANDLING_MASK		REG_GENMASK(8, 7)
> +
>   #define GUC_MAX_IDLE_COUNT			XE_REG(0xc3e4)
> +#define   GUC_IDLE_FLOW_DISABLE			REG_BIT(31)
>   #define GUC_PMTIMESTAMP_LO			XE_REG(0xc3e8)
>   #define GUC_PMTIMESTAMP_HI			XE_REG(0xc3ec)
>   
> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> index 44360437beeb..42658a409556 100644
> --- a/drivers/gpu/drm/xe/xe_guc.c
> +++ b/drivers/gpu/drm/xe/xe_guc.c
> @@ -900,6 +900,33 @@ int xe_guc_post_load_init(struct xe_guc *guc)
>   	return xe_guc_submit_enable(guc);
>   }
>   
> +/*
> + * Wa_14025883347: Prevent GuC firmware DMA failures during GuC-only reset by ensuring
> + * SRAM save/restore operations are complete before reset.
> + */
> +static void guc_prevent_fw_dma_failure_on_reset(struct xe_guc *guc)
> +{
> +	struct xe_gt *gt = guc_to_gt(guc);
> +	u32 boot_hash_chk, guc_status, sram_status;
> +	int ret;
> +
> +	guc_status = xe_mmio_read32(&gt->mmio, GUC_STATUS);
> +	if (guc_status & GS_MIA_IN_RESET)
> +		return;
> +
> +	boot_hash_chk = xe_mmio_read32(&gt->mmio, GUC_HASH_BOOT_CHECK);
> +	if (!(boot_hash_chk & GUC_BOOT_UKERNEL_VALID))
> +		return;
> +
> +	xe_mmio_rmw32(&gt->mmio, GUC_MAX_IDLE_COUNT, 0, GUC_IDLE_FLOW_DISABLE);
> +

The WA says that we also need to wait for the status to be "ready" after 
setting GUC_IDLE_FLOW_DISABLE.

Daniele

> +	ret = xe_mmio_wait32(&gt->mmio, GUC_SRAM_STATUS, GUC_SRAM_HANDLING_MASK,
> +			     0, 5000, &sram_status, false);
> +	if (ret)
> +		xe_gt_warn(gt, "SRAM handling not complete (GUC_SRAM_STATUS: 0x%x)\n",
> +			   sram_status);
> +}
> +
>   int xe_guc_reset(struct xe_guc *guc)
>   {
>   	struct xe_gt *gt = guc_to_gt(guc);
> @@ -909,6 +936,9 @@ int xe_guc_reset(struct xe_guc *guc)
>   
>   	xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
>   
> +	if (XE_GT_WA(gt, 14025883347))
> +		guc_prevent_fw_dma_failure_on_reset(guc);
> +
>   	if (IS_SRIOV_VF(gt_to_xe(gt)))
>   		return xe_gt_sriov_vf_bootstrap(gt);
>   
> diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
> index 5cd7fa6d2a5c..ff2efc7a68cc 100644
> --- a/drivers/gpu/drm/xe/xe_wa_oob.rules
> +++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
> @@ -73,3 +73,12 @@
>   15015404425_disable	PLATFORM(PANTHERLAKE), MEDIA_STEP(B0, FOREVER)
>   16026007364    MEDIA_VERSION(3000)
>   14020316580    MEDIA_VERSION(1301)
> +
> +14025883347	MEDIA_VERSION(1301)
> +		MEDIA_VERSION(2000)
> +		MEDIA_VERSION(3000)
> +		MEDIA_VERSION(3002)
> +		MEDIA_VERSION(3500)
> +		MEDIA_VERSION(3503)
> +		GRAPHICS_VERSION_RANGE(3000, 3001)
> +		GRAPHICS_VERSION_RANGE(3003, 3005)

Re: [PATCH v2 2/2] drm/xe/guc: Add Wa_14025883347 for GuC DMA failure on reset

[Anirban, Sk]

Hi,

On 23-01-2026 03:12 am, Daniele Ceraolo Spurio wrote:
>
>
> On 1/16/2026 2:34 AM, Sk Anirban wrote:
>> Prevent GuC firmware DMA failures during GuC-only reset by disabling
>> idle flow and verifying SRAM handling completion. Without this, reset
>> can be issued while SRAM handler is copying WOPCM to SRAM,
>> causing GuC HW to get stuck.
>>
>> v2: Modify error message (Badal)
>>      Rename reg bit name (Daniele)
>>      Update WA skip condition (Daniele)
>>      Update SRAM handling logic (Daniele)
>>
>> Signed-off-by: Sk Anirban <sk.anirban@intel.com>
>> ---
>>   drivers/gpu/drm/xe/regs/xe_guc_regs.h |  8 +++++++
>>   drivers/gpu/drm/xe/xe_guc.c           | 30 +++++++++++++++++++++++++++
>>   drivers/gpu/drm/xe/xe_wa_oob.rules    |  9 ++++++++
>>   3 files changed, 47 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/xe/regs/xe_guc_regs.h 
>> b/drivers/gpu/drm/xe/regs/xe_guc_regs.h
>> index 87984713dd12..c9cb02f32f5a 100644
>> --- a/drivers/gpu/drm/xe/regs/xe_guc_regs.h
>> +++ b/drivers/gpu/drm/xe/regs/xe_guc_regs.h
>> @@ -40,6 +40,9 @@
>>   #define   GS_BOOTROM_JUMP_PASSED REG_FIELD_PREP(GS_BOOTROM_MASK, 0x76)
>>   #define   GS_MIA_IN_RESET            REG_BIT(0)
>>   +#define GUC_HASH_BOOT_CHECK            XE_REG(0xc010)
>> +#define   GUC_BOOT_UKERNEL_VALID        REG_BIT(31)
>> +
>>   #define GUC_HEADER_INFO                XE_REG(0xc014)
>>     #define GUC_WOPCM_SIZE                XE_REG(0xc050)
>> @@ -83,7 +86,12 @@
>>   #define   GUC_WOPCM_OFFSET_MASK            REG_GENMASK(31, 
>> GUC_WOPCM_OFFSET_SHIFT)
>>   #define   HUC_LOADING_AGENT_GUC            REG_BIT(1)
>>   #define   GUC_WOPCM_OFFSET_VALID        REG_BIT(0)
>> +
>> +#define GUC_SRAM_STATUS                XE_REG(0xc398)
>> +#define   GUC_SRAM_HANDLING_MASK        REG_GENMASK(8, 7)
>> +
>>   #define GUC_MAX_IDLE_COUNT            XE_REG(0xc3e4)
>> +#define   GUC_IDLE_FLOW_DISABLE            REG_BIT(31)
>>   #define GUC_PMTIMESTAMP_LO            XE_REG(0xc3e8)
>>   #define GUC_PMTIMESTAMP_HI            XE_REG(0xc3ec)
>>   diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
>> index 44360437beeb..42658a409556 100644
>> --- a/drivers/gpu/drm/xe/xe_guc.c
>> +++ b/drivers/gpu/drm/xe/xe_guc.c
>> @@ -900,6 +900,33 @@ int xe_guc_post_load_init(struct xe_guc *guc)
>>       return xe_guc_submit_enable(guc);
>>   }
>>   +/*
>> + * Wa_14025883347: Prevent GuC firmware DMA failures during GuC-only 
>> reset by ensuring
>> + * SRAM save/restore operations are complete before reset.
>> + */
>> +static void guc_prevent_fw_dma_failure_on_reset(struct xe_guc *guc)
>> +{
>> +    struct xe_gt *gt = guc_to_gt(guc);
>> +    u32 boot_hash_chk, guc_status, sram_status;
>> +    int ret;
>> +
>> +    guc_status = xe_mmio_read32(&gt->mmio, GUC_STATUS);
>> +    if (guc_status & GS_MIA_IN_RESET)
>> +        return;
>> +
>> +    boot_hash_chk = xe_mmio_read32(&gt->mmio, GUC_HASH_BOOT_CHECK);
>> +    if (!(boot_hash_chk & GUC_BOOT_UKERNEL_VALID))
>> +        return;
>> +
>> +    xe_mmio_rmw32(&gt->mmio, GUC_MAX_IDLE_COUNT, 0, 
>> GUC_IDLE_FLOW_DISABLE);
>> +
>
> The WA says that we also need to wait for the status to be "ready" 
> after setting GUC_IDLE_FLOW_DISABLE.
>
> Daniele
>
As discussed, a GuC reset can occur without firmware interaction, and 
during RC6 exit the GuC load status may transition, meaning it will not 
always be INTEL_GUC_LOAD_STATUS_READY.

So we’re checking GS_MIA_IN_RESET instead. I just want to confirm that 
this is enough to ensure FW is present before applying the WA.

Thanks,

Anirban

>> +    ret = xe_mmio_wait32(&gt->mmio, GUC_SRAM_STATUS, 
>> GUC_SRAM_HANDLING_MASK,
>> +                 0, 5000, &sram_status, false);
>> +    if (ret)
>> +        xe_gt_warn(gt, "SRAM handling not complete (GUC_SRAM_STATUS: 
>> 0x%x)\n",
>> +               sram_status);
>> +}
>> +
>>   int xe_guc_reset(struct xe_guc *guc)
>>   {
>>       struct xe_gt *gt = guc_to_gt(guc);
>> @@ -909,6 +936,9 @@ int xe_guc_reset(struct xe_guc *guc)
>>         xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
>>   +    if (XE_GT_WA(gt, 14025883347))
>> +        guc_prevent_fw_dma_failure_on_reset(guc);
>> +
>>       if (IS_SRIOV_VF(gt_to_xe(gt)))
>>           return xe_gt_sriov_vf_bootstrap(gt);
>>   diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules 
>> b/drivers/gpu/drm/xe/xe_wa_oob.rules
>> index 5cd7fa6d2a5c..ff2efc7a68cc 100644
>> --- a/drivers/gpu/drm/xe/xe_wa_oob.rules
>> +++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
>> @@ -73,3 +73,12 @@
>>   15015404425_disable    PLATFORM(PANTHERLAKE), MEDIA_STEP(B0, FOREVER)
>>   16026007364    MEDIA_VERSION(3000)
>>   14020316580    MEDIA_VERSION(1301)
>> +
>> +14025883347    MEDIA_VERSION(1301)
>> +        MEDIA_VERSION(2000)
>> +        MEDIA_VERSION(3000)
>> +        MEDIA_VERSION(3002)
>> +        MEDIA_VERSION(3500)
>> +        MEDIA_VERSION(3503)
>> +        GRAPHICS_VERSION_RANGE(3000, 3001)
>> +        GRAPHICS_VERSION_RANGE(3003, 3005)
>

Re: [PATCH v2 2/2] drm/xe/guc: Add Wa_14025883347 for GuC DMA failure on reset

[Daniele Ceraolo Spurio]

On 1/23/2026 9:12 AM, Anirban, Sk wrote:
> Hi,
>
> On 23-01-2026 03:12 am, Daniele Ceraolo Spurio wrote:
>>
>>
>> On 1/16/2026 2:34 AM, Sk Anirban wrote:
>>> Prevent GuC firmware DMA failures during GuC-only reset by disabling
>>> idle flow and verifying SRAM handling completion. Without this, reset
>>> can be issued while SRAM handler is copying WOPCM to SRAM,
>>> causing GuC HW to get stuck.
>>>
>>> v2: Modify error message (Badal)
>>>      Rename reg bit name (Daniele)
>>>      Update WA skip condition (Daniele)
>>>      Update SRAM handling logic (Daniele)
>>>
>>> Signed-off-by: Sk Anirban <sk.anirban@intel.com>
>>> ---
>>>   drivers/gpu/drm/xe/regs/xe_guc_regs.h |  8 +++++++
>>>   drivers/gpu/drm/xe/xe_guc.c           | 30 
>>> +++++++++++++++++++++++++++
>>>   drivers/gpu/drm/xe/xe_wa_oob.rules    |  9 ++++++++
>>>   3 files changed, 47 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/xe/regs/xe_guc_regs.h 
>>> b/drivers/gpu/drm/xe/regs/xe_guc_regs.h
>>> index 87984713dd12..c9cb02f32f5a 100644
>>> --- a/drivers/gpu/drm/xe/regs/xe_guc_regs.h
>>> +++ b/drivers/gpu/drm/xe/regs/xe_guc_regs.h
>>> @@ -40,6 +40,9 @@
>>>   #define   GS_BOOTROM_JUMP_PASSED REG_FIELD_PREP(GS_BOOTROM_MASK, 
>>> 0x76)
>>>   #define   GS_MIA_IN_RESET            REG_BIT(0)
>>>   +#define GUC_HASH_BOOT_CHECK            XE_REG(0xc010)
>>> +#define   GUC_BOOT_UKERNEL_VALID        REG_BIT(31)
>>> +
>>>   #define GUC_HEADER_INFO                XE_REG(0xc014)
>>>     #define GUC_WOPCM_SIZE                XE_REG(0xc050)
>>> @@ -83,7 +86,12 @@
>>>   #define   GUC_WOPCM_OFFSET_MASK            REG_GENMASK(31, 
>>> GUC_WOPCM_OFFSET_SHIFT)
>>>   #define   HUC_LOADING_AGENT_GUC            REG_BIT(1)
>>>   #define   GUC_WOPCM_OFFSET_VALID        REG_BIT(0)
>>> +
>>> +#define GUC_SRAM_STATUS                XE_REG(0xc398)
>>> +#define   GUC_SRAM_HANDLING_MASK        REG_GENMASK(8, 7)
>>> +
>>>   #define GUC_MAX_IDLE_COUNT            XE_REG(0xc3e4)
>>> +#define   GUC_IDLE_FLOW_DISABLE            REG_BIT(31)
>>>   #define GUC_PMTIMESTAMP_LO            XE_REG(0xc3e8)
>>>   #define GUC_PMTIMESTAMP_HI            XE_REG(0xc3ec)
>>>   diff --git a/drivers/gpu/drm/xe/xe_guc.c 
>>> b/drivers/gpu/drm/xe/xe_guc.c
>>> index 44360437beeb..42658a409556 100644
>>> --- a/drivers/gpu/drm/xe/xe_guc.c
>>> +++ b/drivers/gpu/drm/xe/xe_guc.c
>>> @@ -900,6 +900,33 @@ int xe_guc_post_load_init(struct xe_guc *guc)
>>>       return xe_guc_submit_enable(guc);
>>>   }
>>>   +/*
>>> + * Wa_14025883347: Prevent GuC firmware DMA failures during 
>>> GuC-only reset by ensuring
>>> + * SRAM save/restore operations are complete before reset.
>>> + */
>>> +static void guc_prevent_fw_dma_failure_on_reset(struct xe_guc *guc)
>>> +{
>>> +    struct xe_gt *gt = guc_to_gt(guc);
>>> +    u32 boot_hash_chk, guc_status, sram_status;
>>> +    int ret;
>>> +
>>> +    guc_status = xe_mmio_read32(&gt->mmio, GUC_STATUS);
>>> +    if (guc_status & GS_MIA_IN_RESET)
>>> +        return;
>>> +
>>> +    boot_hash_chk = xe_mmio_read32(&gt->mmio, GUC_HASH_BOOT_CHECK);
>>> +    if (!(boot_hash_chk & GUC_BOOT_UKERNEL_VALID))
>>> +        return;
>>> +
>>> +    xe_mmio_rmw32(&gt->mmio, GUC_MAX_IDLE_COUNT, 0, 
>>> GUC_IDLE_FLOW_DISABLE);
>>> +
>>
>> The WA says that we also need to wait for the status to be "ready" 
>> after setting GUC_IDLE_FLOW_DISABLE.
>>
>> Daniele
>>
> As discussed, a GuC reset can occur without firmware interaction, and 
> during RC6 exit the GuC load status may transition, meaning it will 
> not always be INTEL_GUC_LOAD_STATUS_READY.
>
> So we’re checking GS_MIA_IN_RESET instead. I just want to confirm that 
> this is enough to ensure FW is present before applying the WA.

The GS_MIA_IN_RESET check + boot_hash_chk are enough to determine if the 
FW is present. However, waiting for the ready state is not about 
confirming if it is present, it is about waiting for the FW 
initialization to complete after we've confirmed that it is indeed 
present. Basically the WA is saying that we can't do a GuC reset while 
GuC init is still in progress.

Daniele

>
> Thanks,
>
> Anirban
>
>>> +    ret = xe_mmio_wait32(&gt->mmio, GUC_SRAM_STATUS, 
>>> GUC_SRAM_HANDLING_MASK,
>>> +                 0, 5000, &sram_status, false);
>>> +    if (ret)
>>> +        xe_gt_warn(gt, "SRAM handling not complete 
>>> (GUC_SRAM_STATUS: 0x%x)\n",
>>> +               sram_status);
>>> +}
>>> +
>>>   int xe_guc_reset(struct xe_guc *guc)
>>>   {
>>>       struct xe_gt *gt = guc_to_gt(guc);
>>> @@ -909,6 +936,9 @@ int xe_guc_reset(struct xe_guc *guc)
>>>         xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
>>>   +    if (XE_GT_WA(gt, 14025883347))
>>> +        guc_prevent_fw_dma_failure_on_reset(guc);
>>> +
>>>       if (IS_SRIOV_VF(gt_to_xe(gt)))
>>>           return xe_gt_sriov_vf_bootstrap(gt);
>>>   diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules 
>>> b/drivers/gpu/drm/xe/xe_wa_oob.rules
>>> index 5cd7fa6d2a5c..ff2efc7a68cc 100644
>>> --- a/drivers/gpu/drm/xe/xe_wa_oob.rules
>>> +++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
>>> @@ -73,3 +73,12 @@
>>>   15015404425_disable    PLATFORM(PANTHERLAKE), MEDIA_STEP(B0, FOREVER)
>>>   16026007364    MEDIA_VERSION(3000)
>>>   14020316580    MEDIA_VERSION(1301)
>>> +
>>> +14025883347    MEDIA_VERSION(1301)
>>> +        MEDIA_VERSION(2000)
>>> +        MEDIA_VERSION(3000)
>>> +        MEDIA_VERSION(3002)
>>> +        MEDIA_VERSION(3500)
>>> +        MEDIA_VERSION(3503)
>>> +        GRAPHICS_VERSION_RANGE(3000, 3001)
>>> +        GRAPHICS_VERSION_RANGE(3003, 3005)
>>

Re: [PATCH v2 2/2] drm/xe/guc: Add Wa_14025883347 for GuC DMA failure on reset

[Anirban, Sk]

Hi,

On 23-01-2026 10:58 pm, Daniele Ceraolo Spurio wrote:
>
>
> On 1/23/2026 9:12 AM, Anirban, Sk wrote:
>> Hi,
>>
>> On 23-01-2026 03:12 am, Daniele Ceraolo Spurio wrote:
>>>
>>>
>>> On 1/16/2026 2:34 AM, Sk Anirban wrote:
>>>> Prevent GuC firmware DMA failures during GuC-only reset by disabling
>>>> idle flow and verifying SRAM handling completion. Without this, reset
>>>> can be issued while SRAM handler is copying WOPCM to SRAM,
>>>> causing GuC HW to get stuck.
>>>>
>>>> v2: Modify error message (Badal)
>>>>      Rename reg bit name (Daniele)
>>>>      Update WA skip condition (Daniele)
>>>>      Update SRAM handling logic (Daniele)
>>>>
>>>> Signed-off-by: Sk Anirban <sk.anirban@intel.com>
>>>> ---
>>>>   drivers/gpu/drm/xe/regs/xe_guc_regs.h |  8 +++++++
>>>>   drivers/gpu/drm/xe/xe_guc.c           | 30 
>>>> +++++++++++++++++++++++++++
>>>>   drivers/gpu/drm/xe/xe_wa_oob.rules    |  9 ++++++++
>>>>   3 files changed, 47 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/xe/regs/xe_guc_regs.h 
>>>> b/drivers/gpu/drm/xe/regs/xe_guc_regs.h
>>>> index 87984713dd12..c9cb02f32f5a 100644
>>>> --- a/drivers/gpu/drm/xe/regs/xe_guc_regs.h
>>>> +++ b/drivers/gpu/drm/xe/regs/xe_guc_regs.h
>>>> @@ -40,6 +40,9 @@
>>>>   #define   GS_BOOTROM_JUMP_PASSED REG_FIELD_PREP(GS_BOOTROM_MASK, 
>>>> 0x76)
>>>>   #define   GS_MIA_IN_RESET            REG_BIT(0)
>>>>   +#define GUC_HASH_BOOT_CHECK            XE_REG(0xc010)
>>>> +#define   GUC_BOOT_UKERNEL_VALID        REG_BIT(31)
>>>> +
>>>>   #define GUC_HEADER_INFO                XE_REG(0xc014)
>>>>     #define GUC_WOPCM_SIZE                XE_REG(0xc050)
>>>> @@ -83,7 +86,12 @@
>>>>   #define   GUC_WOPCM_OFFSET_MASK            REG_GENMASK(31, 
>>>> GUC_WOPCM_OFFSET_SHIFT)
>>>>   #define   HUC_LOADING_AGENT_GUC            REG_BIT(1)
>>>>   #define   GUC_WOPCM_OFFSET_VALID        REG_BIT(0)
>>>> +
>>>> +#define GUC_SRAM_STATUS                XE_REG(0xc398)
>>>> +#define   GUC_SRAM_HANDLING_MASK        REG_GENMASK(8, 7)
>>>> +
>>>>   #define GUC_MAX_IDLE_COUNT            XE_REG(0xc3e4)
>>>> +#define   GUC_IDLE_FLOW_DISABLE            REG_BIT(31)
>>>>   #define GUC_PMTIMESTAMP_LO            XE_REG(0xc3e8)
>>>>   #define GUC_PMTIMESTAMP_HI            XE_REG(0xc3ec)
>>>>   diff --git a/drivers/gpu/drm/xe/xe_guc.c 
>>>> b/drivers/gpu/drm/xe/xe_guc.c
>>>> index 44360437beeb..42658a409556 100644
>>>> --- a/drivers/gpu/drm/xe/xe_guc.c
>>>> +++ b/drivers/gpu/drm/xe/xe_guc.c
>>>> @@ -900,6 +900,33 @@ int xe_guc_post_load_init(struct xe_guc *guc)
>>>>       return xe_guc_submit_enable(guc);
>>>>   }
>>>>   +/*
>>>> + * Wa_14025883347: Prevent GuC firmware DMA failures during 
>>>> GuC-only reset by ensuring
>>>> + * SRAM save/restore operations are complete before reset.
>>>> + */
>>>> +static void guc_prevent_fw_dma_failure_on_reset(struct xe_guc *guc)
>>>> +{
>>>> +    struct xe_gt *gt = guc_to_gt(guc);
>>>> +    u32 boot_hash_chk, guc_status, sram_status;
>>>> +    int ret;
>>>> +
>>>> +    guc_status = xe_mmio_read32(&gt->mmio, GUC_STATUS);
>>>> +    if (guc_status & GS_MIA_IN_RESET)
>>>> +        return;
>>>> +
>>>> +    boot_hash_chk = xe_mmio_read32(&gt->mmio, GUC_HASH_BOOT_CHECK);
>>>> +    if (!(boot_hash_chk & GUC_BOOT_UKERNEL_VALID))
>>>> +        return;
>>>> +
>>>> +    xe_mmio_rmw32(&gt->mmio, GUC_MAX_IDLE_COUNT, 0, 
>>>> GUC_IDLE_FLOW_DISABLE);
>>>> +
>>>
>>> The WA says that we also need to wait for the status to be "ready" 
>>> after setting GUC_IDLE_FLOW_DISABLE.
>>>
>>> Daniele
>>>
>> As discussed, a GuC reset can occur without firmware interaction, and 
>> during RC6 exit the GuC load status may transition, meaning it will 
>> not always be INTEL_GUC_LOAD_STATUS_READY.
>>
>> So we’re checking GS_MIA_IN_RESET instead. I just want to confirm 
>> that this is enough to ensure FW is present before applying the WA.
>
> The GS_MIA_IN_RESET check + boot_hash_chk are enough to determine if 
> the FW is present. However, waiting for the ready state is not about 
> confirming if it is present, it is about waiting for the FW 
> initialization to complete after we've confirmed that it is indeed 
> present. Basically the WA is saying that we can't do a GuC reset while 
> GuC init is still in progress.
>
> Daniele

Understood. In that scenario, a timeout check on GUC_STATUS[15:8] = 0xF0 
should be adequate to verify that the status is ready. I will add the 
code block for this.

Thanks,

Anirban

>
>>
>> Thanks,
>>
>> Anirban
>>
>>>> +    ret = xe_mmio_wait32(&gt->mmio, GUC_SRAM_STATUS, 
>>>> GUC_SRAM_HANDLING_MASK,
>>>> +                 0, 5000, &sram_status, false);
>>>> +    if (ret)
>>>> +        xe_gt_warn(gt, "SRAM handling not complete 
>>>> (GUC_SRAM_STATUS: 0x%x)\n",
>>>> +               sram_status);
>>>> +}
>>>> +
>>>>   int xe_guc_reset(struct xe_guc *guc)
>>>>   {
>>>>       struct xe_gt *gt = guc_to_gt(guc);
>>>> @@ -909,6 +936,9 @@ int xe_guc_reset(struct xe_guc *guc)
>>>>         xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
>>>>   +    if (XE_GT_WA(gt, 14025883347))
>>>> +        guc_prevent_fw_dma_failure_on_reset(guc);
>>>> +
>>>>       if (IS_SRIOV_VF(gt_to_xe(gt)))
>>>>           return xe_gt_sriov_vf_bootstrap(gt);
>>>>   diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules 
>>>> b/drivers/gpu/drm/xe/xe_wa_oob.rules
>>>> index 5cd7fa6d2a5c..ff2efc7a68cc 100644
>>>> --- a/drivers/gpu/drm/xe/xe_wa_oob.rules
>>>> +++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
>>>> @@ -73,3 +73,12 @@
>>>>   15015404425_disable    PLATFORM(PANTHERLAKE), MEDIA_STEP(B0, 
>>>> FOREVER)
>>>>   16026007364    MEDIA_VERSION(3000)
>>>>   14020316580    MEDIA_VERSION(1301)
>>>> +
>>>> +14025883347    MEDIA_VERSION(1301)
>>>> +        MEDIA_VERSION(2000)
>>>> +        MEDIA_VERSION(3000)
>>>> +        MEDIA_VERSION(3002)
>>>> +        MEDIA_VERSION(3500)
>>>> +        MEDIA_VERSION(3503)
>>>> +        GRAPHICS_VERSION_RANGE(3000, 3001)
>>>> +        GRAPHICS_VERSION_RANGE(3003, 3005)
>>>
>

Re: [PATCH v2 2/2] drm/xe/guc: Add Wa_14025883347 for GuC DMA failure on reset

[Daniele Ceraolo Spurio]

On 1/23/2026 9:54 AM, Anirban, Sk wrote:
> Hi,
>
> On 23-01-2026 10:58 pm, Daniele Ceraolo Spurio wrote:
>>
>>
>> On 1/23/2026 9:12 AM, Anirban, Sk wrote:
>>> Hi,
>>>
>>> On 23-01-2026 03:12 am, Daniele Ceraolo Spurio wrote:
>>>>
>>>>
>>>> On 1/16/2026 2:34 AM, Sk Anirban wrote:
>>>>> Prevent GuC firmware DMA failures during GuC-only reset by disabling
>>>>> idle flow and verifying SRAM handling completion. Without this, reset
>>>>> can be issued while SRAM handler is copying WOPCM to SRAM,
>>>>> causing GuC HW to get stuck.
>>>>>
>>>>> v2: Modify error message (Badal)
>>>>>      Rename reg bit name (Daniele)
>>>>>      Update WA skip condition (Daniele)
>>>>>      Update SRAM handling logic (Daniele)
>>>>>
>>>>> Signed-off-by: Sk Anirban <sk.anirban@intel.com>
>>>>> ---
>>>>>   drivers/gpu/drm/xe/regs/xe_guc_regs.h |  8 +++++++
>>>>>   drivers/gpu/drm/xe/xe_guc.c           | 30 
>>>>> +++++++++++++++++++++++++++
>>>>>   drivers/gpu/drm/xe/xe_wa_oob.rules    |  9 ++++++++
>>>>>   3 files changed, 47 insertions(+)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/xe/regs/xe_guc_regs.h 
>>>>> b/drivers/gpu/drm/xe/regs/xe_guc_regs.h
>>>>> index 87984713dd12..c9cb02f32f5a 100644
>>>>> --- a/drivers/gpu/drm/xe/regs/xe_guc_regs.h
>>>>> +++ b/drivers/gpu/drm/xe/regs/xe_guc_regs.h
>>>>> @@ -40,6 +40,9 @@
>>>>>   #define   GS_BOOTROM_JUMP_PASSED REG_FIELD_PREP(GS_BOOTROM_MASK, 
>>>>> 0x76)
>>>>>   #define   GS_MIA_IN_RESET            REG_BIT(0)
>>>>>   +#define GUC_HASH_BOOT_CHECK            XE_REG(0xc010)
>>>>> +#define   GUC_BOOT_UKERNEL_VALID        REG_BIT(31)
>>>>> +
>>>>>   #define GUC_HEADER_INFO                XE_REG(0xc014)
>>>>>     #define GUC_WOPCM_SIZE                XE_REG(0xc050)
>>>>> @@ -83,7 +86,12 @@
>>>>>   #define   GUC_WOPCM_OFFSET_MASK REG_GENMASK(31, 
>>>>> GUC_WOPCM_OFFSET_SHIFT)
>>>>>   #define   HUC_LOADING_AGENT_GUC            REG_BIT(1)
>>>>>   #define   GUC_WOPCM_OFFSET_VALID        REG_BIT(0)
>>>>> +
>>>>> +#define GUC_SRAM_STATUS                XE_REG(0xc398)
>>>>> +#define   GUC_SRAM_HANDLING_MASK        REG_GENMASK(8, 7)
>>>>> +
>>>>>   #define GUC_MAX_IDLE_COUNT            XE_REG(0xc3e4)
>>>>> +#define   GUC_IDLE_FLOW_DISABLE            REG_BIT(31)
>>>>>   #define GUC_PMTIMESTAMP_LO            XE_REG(0xc3e8)
>>>>>   #define GUC_PMTIMESTAMP_HI            XE_REG(0xc3ec)
>>>>>   diff --git a/drivers/gpu/drm/xe/xe_guc.c 
>>>>> b/drivers/gpu/drm/xe/xe_guc.c
>>>>> index 44360437beeb..42658a409556 100644
>>>>> --- a/drivers/gpu/drm/xe/xe_guc.c
>>>>> +++ b/drivers/gpu/drm/xe/xe_guc.c
>>>>> @@ -900,6 +900,33 @@ int xe_guc_post_load_init(struct xe_guc *guc)
>>>>>       return xe_guc_submit_enable(guc);
>>>>>   }
>>>>>   +/*
>>>>> + * Wa_14025883347: Prevent GuC firmware DMA failures during 
>>>>> GuC-only reset by ensuring
>>>>> + * SRAM save/restore operations are complete before reset.
>>>>> + */
>>>>> +static void guc_prevent_fw_dma_failure_on_reset(struct xe_guc *guc)
>>>>> +{
>>>>> +    struct xe_gt *gt = guc_to_gt(guc);
>>>>> +    u32 boot_hash_chk, guc_status, sram_status;
>>>>> +    int ret;
>>>>> +
>>>>> +    guc_status = xe_mmio_read32(&gt->mmio, GUC_STATUS);
>>>>> +    if (guc_status & GS_MIA_IN_RESET)
>>>>> +        return;
>>>>> +
>>>>> +    boot_hash_chk = xe_mmio_read32(&gt->mmio, GUC_HASH_BOOT_CHECK);
>>>>> +    if (!(boot_hash_chk & GUC_BOOT_UKERNEL_VALID))
>>>>> +        return;
>>>>> +
>>>>> +    xe_mmio_rmw32(&gt->mmio, GUC_MAX_IDLE_COUNT, 0, 
>>>>> GUC_IDLE_FLOW_DISABLE);
>>>>> +
>>>>
>>>> The WA says that we also need to wait for the status to be "ready" 
>>>> after setting GUC_IDLE_FLOW_DISABLE.
>>>>
>>>> Daniele
>>>>
>>> As discussed, a GuC reset can occur without firmware interaction, 
>>> and during RC6 exit the GuC load status may transition, meaning it 
>>> will not always be INTEL_GUC_LOAD_STATUS_READY.
>>>
>>> So we’re checking GS_MIA_IN_RESET instead. I just want to confirm 
>>> that this is enough to ensure FW is present before applying the WA.
>>
>> The GS_MIA_IN_RESET check + boot_hash_chk are enough to determine if 
>> the FW is present. However, waiting for the ready state is not about 
>> confirming if it is present, it is about waiting for the FW 
>> initialization to complete after we've confirmed that it is indeed 
>> present. Basically the WA is saying that we can't do a GuC reset 
>> while GuC init is still in progress.
>>
>> Daniele
>
> Understood. In that scenario, a timeout check on GUC_STATUS[15:8] = 
> 0xF0 should be adequate to verify that the status is ready. I will add 
> the code block for this.

Note that the GuC init can take a while if we're throttling due to 
excessive heat, so use a big timeout (100ms should do).

Daniele

>
> Thanks,
>
> Anirban
>
>>
>>>
>>> Thanks,
>>>
>>> Anirban
>>>
>>>>> +    ret = xe_mmio_wait32(&gt->mmio, GUC_SRAM_STATUS, 
>>>>> GUC_SRAM_HANDLING_MASK,
>>>>> +                 0, 5000, &sram_status, false);
>>>>> +    if (ret)
>>>>> +        xe_gt_warn(gt, "SRAM handling not complete 
>>>>> (GUC_SRAM_STATUS: 0x%x)\n",
>>>>> +               sram_status);
>>>>> +}
>>>>> +
>>>>>   int xe_guc_reset(struct xe_guc *guc)
>>>>>   {
>>>>>       struct xe_gt *gt = guc_to_gt(guc);
>>>>> @@ -909,6 +936,9 @@ int xe_guc_reset(struct xe_guc *guc)
>>>>>         xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
>>>>>   +    if (XE_GT_WA(gt, 14025883347))
>>>>> +        guc_prevent_fw_dma_failure_on_reset(guc);
>>>>> +
>>>>>       if (IS_SRIOV_VF(gt_to_xe(gt)))
>>>>>           return xe_gt_sriov_vf_bootstrap(gt);
>>>>>   diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules 
>>>>> b/drivers/gpu/drm/xe/xe_wa_oob.rules
>>>>> index 5cd7fa6d2a5c..ff2efc7a68cc 100644
>>>>> --- a/drivers/gpu/drm/xe/xe_wa_oob.rules
>>>>> +++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
>>>>> @@ -73,3 +73,12 @@
>>>>>   15015404425_disable    PLATFORM(PANTHERLAKE), MEDIA_STEP(B0, 
>>>>> FOREVER)
>>>>>   16026007364    MEDIA_VERSION(3000)
>>>>>   14020316580    MEDIA_VERSION(1301)
>>>>> +
>>>>> +14025883347    MEDIA_VERSION(1301)
>>>>> +        MEDIA_VERSION(2000)
>>>>> +        MEDIA_VERSION(3000)
>>>>> +        MEDIA_VERSION(3002)
>>>>> +        MEDIA_VERSION(3500)
>>>>> +        MEDIA_VERSION(3503)
>>>>> +        GRAPHICS_VERSION_RANGE(3000, 3001)
>>>>> +        GRAPHICS_VERSION_RANGE(3003, 3005)
>>>>
>>

Re: [PATCH v2 2/2] drm/xe/guc: Add Wa_14025883347 for GuC DMA failure on reset

[Anirban, Sk]

Hi,

On 23-01-2026 11:28 pm, Daniele Ceraolo Spurio wrote:
>
>
> On 1/23/2026 9:54 AM, Anirban, Sk wrote:
>> Hi,
>>
>> On 23-01-2026 10:58 pm, Daniele Ceraolo Spurio wrote:
>>>
>>>
>>> On 1/23/2026 9:12 AM, Anirban, Sk wrote:
>>>> Hi,
>>>>
>>>> On 23-01-2026 03:12 am, Daniele Ceraolo Spurio wrote:
>>>>>
>>>>>
>>>>> On 1/16/2026 2:34 AM, Sk Anirban wrote:
>>>>>> Prevent GuC firmware DMA failures during GuC-only reset by disabling
>>>>>> idle flow and verifying SRAM handling completion. Without this, 
>>>>>> reset
>>>>>> can be issued while SRAM handler is copying WOPCM to SRAM,
>>>>>> causing GuC HW to get stuck.
>>>>>>
>>>>>> v2: Modify error message (Badal)
>>>>>>      Rename reg bit name (Daniele)
>>>>>>      Update WA skip condition (Daniele)
>>>>>>      Update SRAM handling logic (Daniele)
>>>>>>
>>>>>> Signed-off-by: Sk Anirban <sk.anirban@intel.com>
>>>>>> ---
>>>>>>   drivers/gpu/drm/xe/regs/xe_guc_regs.h |  8 +++++++
>>>>>>   drivers/gpu/drm/xe/xe_guc.c           | 30 
>>>>>> +++++++++++++++++++++++++++
>>>>>>   drivers/gpu/drm/xe/xe_wa_oob.rules    |  9 ++++++++
>>>>>>   3 files changed, 47 insertions(+)
>>>>>>
>>>>>> diff --git a/drivers/gpu/drm/xe/regs/xe_guc_regs.h 
>>>>>> b/drivers/gpu/drm/xe/regs/xe_guc_regs.h
>>>>>> index 87984713dd12..c9cb02f32f5a 100644
>>>>>> --- a/drivers/gpu/drm/xe/regs/xe_guc_regs.h
>>>>>> +++ b/drivers/gpu/drm/xe/regs/xe_guc_regs.h
>>>>>> @@ -40,6 +40,9 @@
>>>>>>   #define   GS_BOOTROM_JUMP_PASSED 
>>>>>> REG_FIELD_PREP(GS_BOOTROM_MASK, 0x76)
>>>>>>   #define   GS_MIA_IN_RESET            REG_BIT(0)
>>>>>>   +#define GUC_HASH_BOOT_CHECK            XE_REG(0xc010)
>>>>>> +#define   GUC_BOOT_UKERNEL_VALID        REG_BIT(31)
>>>>>> +
>>>>>>   #define GUC_HEADER_INFO                XE_REG(0xc014)
>>>>>>     #define GUC_WOPCM_SIZE                XE_REG(0xc050)
>>>>>> @@ -83,7 +86,12 @@
>>>>>>   #define   GUC_WOPCM_OFFSET_MASK REG_GENMASK(31, 
>>>>>> GUC_WOPCM_OFFSET_SHIFT)
>>>>>>   #define   HUC_LOADING_AGENT_GUC            REG_BIT(1)
>>>>>>   #define   GUC_WOPCM_OFFSET_VALID        REG_BIT(0)
>>>>>> +
>>>>>> +#define GUC_SRAM_STATUS                XE_REG(0xc398)
>>>>>> +#define   GUC_SRAM_HANDLING_MASK        REG_GENMASK(8, 7)
>>>>>> +
>>>>>>   #define GUC_MAX_IDLE_COUNT            XE_REG(0xc3e4)
>>>>>> +#define   GUC_IDLE_FLOW_DISABLE            REG_BIT(31)
>>>>>>   #define GUC_PMTIMESTAMP_LO            XE_REG(0xc3e8)
>>>>>>   #define GUC_PMTIMESTAMP_HI            XE_REG(0xc3ec)
>>>>>>   diff --git a/drivers/gpu/drm/xe/xe_guc.c 
>>>>>> b/drivers/gpu/drm/xe/xe_guc.c
>>>>>> index 44360437beeb..42658a409556 100644
>>>>>> --- a/drivers/gpu/drm/xe/xe_guc.c
>>>>>> +++ b/drivers/gpu/drm/xe/xe_guc.c
>>>>>> @@ -900,6 +900,33 @@ int xe_guc_post_load_init(struct xe_guc *guc)
>>>>>>       return xe_guc_submit_enable(guc);
>>>>>>   }
>>>>>>   +/*
>>>>>> + * Wa_14025883347: Prevent GuC firmware DMA failures during 
>>>>>> GuC-only reset by ensuring
>>>>>> + * SRAM save/restore operations are complete before reset.
>>>>>> + */
>>>>>> +static void guc_prevent_fw_dma_failure_on_reset(struct xe_guc *guc)
>>>>>> +{
>>>>>> +    struct xe_gt *gt = guc_to_gt(guc);
>>>>>> +    u32 boot_hash_chk, guc_status, sram_status;
>>>>>> +    int ret;
>>>>>> +
>>>>>> +    guc_status = xe_mmio_read32(&gt->mmio, GUC_STATUS);
>>>>>> +    if (guc_status & GS_MIA_IN_RESET)
>>>>>> +        return;
>>>>>> +
>>>>>> +    boot_hash_chk = xe_mmio_read32(&gt->mmio, GUC_HASH_BOOT_CHECK);
>>>>>> +    if (!(boot_hash_chk & GUC_BOOT_UKERNEL_VALID))
>>>>>> +        return;
>>>>>> +
>>>>>> +    xe_mmio_rmw32(&gt->mmio, GUC_MAX_IDLE_COUNT, 0, 
>>>>>> GUC_IDLE_FLOW_DISABLE);
>>>>>> +
>>>>>
>>>>> The WA says that we also need to wait for the status to be "ready" 
>>>>> after setting GUC_IDLE_FLOW_DISABLE.
>>>>>
>>>>> Daniele
>>>>>
>>>> As discussed, a GuC reset can occur without firmware interaction, 
>>>> and during RC6 exit the GuC load status may transition, meaning it 
>>>> will not always be INTEL_GUC_LOAD_STATUS_READY.
>>>>
>>>> So we’re checking GS_MIA_IN_RESET instead. I just want to confirm 
>>>> that this is enough to ensure FW is present before applying the WA.
>>>
>>> The GS_MIA_IN_RESET check + boot_hash_chk are enough to determine if 
>>> the FW is present. However, waiting for the ready state is not about 
>>> confirming if it is present, it is about waiting for the FW 
>>> initialization to complete after we've confirmed that it is indeed 
>>> present. Basically the WA is saying that we can't do a GuC reset 
>>> while GuC init is still in progress.
>>>
>>> Daniele
>>
>> Understood. In that scenario, a timeout check on GUC_STATUS[15:8] = 
>> 0xF0 should be adequate to verify that the status is ready. I will 
>> add the code block for this.
>
> Note that the GuC init can take a while if we're throttling due to 
> excessive heat, so use a big timeout (100ms should do).
>
> Daniele

Sure, I will use that.

Thanks,

Anirban

>
>>
>> Thanks,
>>
>> Anirban
>>
>>>
>>>>
>>>> Thanks,
>>>>
>>>> Anirban
>>>>
>>>>>> +    ret = xe_mmio_wait32(&gt->mmio, GUC_SRAM_STATUS, 
>>>>>> GUC_SRAM_HANDLING_MASK,
>>>>>> +                 0, 5000, &sram_status, false);
>>>>>> +    if (ret)
>>>>>> +        xe_gt_warn(gt, "SRAM handling not complete 
>>>>>> (GUC_SRAM_STATUS: 0x%x)\n",
>>>>>> +               sram_status);
>>>>>> +}
>>>>>> +
>>>>>>   int xe_guc_reset(struct xe_guc *guc)
>>>>>>   {
>>>>>>       struct xe_gt *gt = guc_to_gt(guc);
>>>>>> @@ -909,6 +936,9 @@ int xe_guc_reset(struct xe_guc *guc)
>>>>>>         xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
>>>>>>   +    if (XE_GT_WA(gt, 14025883347))
>>>>>> +        guc_prevent_fw_dma_failure_on_reset(guc);
>>>>>> +
>>>>>>       if (IS_SRIOV_VF(gt_to_xe(gt)))
>>>>>>           return xe_gt_sriov_vf_bootstrap(gt);
>>>>>>   diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules 
>>>>>> b/drivers/gpu/drm/xe/xe_wa_oob.rules
>>>>>> index 5cd7fa6d2a5c..ff2efc7a68cc 100644
>>>>>> --- a/drivers/gpu/drm/xe/xe_wa_oob.rules
>>>>>> +++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
>>>>>> @@ -73,3 +73,12 @@
>>>>>>   15015404425_disable    PLATFORM(PANTHERLAKE), MEDIA_STEP(B0, 
>>>>>> FOREVER)
>>>>>>   16026007364    MEDIA_VERSION(3000)
>>>>>>   14020316580    MEDIA_VERSION(1301)
>>>>>> +
>>>>>> +14025883347    MEDIA_VERSION(1301)
>>>>>> +        MEDIA_VERSION(2000)
>>>>>> +        MEDIA_VERSION(3000)
>>>>>> +        MEDIA_VERSION(3002)
>>>>>> +        MEDIA_VERSION(3500)
>>>>>> +        MEDIA_VERSION(3503)
>>>>>> +        GRAPHICS_VERSION_RANGE(3000, 3001)
>>>>>> +        GRAPHICS_VERSION_RANGE(3003, 3005)
>>>>>
>>>
>