Re: [PATCH v3] drm/xe/xe_guc_ads: Add nonpriv registers to write list

["Dixit, Ashutosh" <ashutosh.dixit@intel.com>]

On Mon, 02 Dec 2024 13:11:21 -0800, Cavitt, Jonathan wrote:
>
> -----Original Message-----
> From: Dixit, Ashutosh <ashutosh.dixit@intel.com>
> Sent: Monday, December 2, 2024 12:33 PM
> To: Cavitt, Jonathan <jonathan.cavitt@intel.com>
> Cc: intel-xe@lists.freedesktop.org; Gupta, saurabhg <saurabhg.gupta@intel.com>; Zuo, Alex <alex.zuo@intel.com>; Nerlige Ramappa, Umesh <umesh.nerlige.ramappa@intel.com>; Harrison, John C <john.c.harrison@intel.com>; Roper, Matthew D <matthew.d.roper@intel.com>; De Marchi, Lucas <lucas.demarchi@intel.com>
> Subject: Re: [PATCH v3] drm/xe/xe_guc_ads: Add nonpriv registers to write list
> >
> > On Fri, 22 Nov 2024 10:08:26 -0800, Jonathan Cavitt wrote:
> > >
> > > When performing a guc_mmio_regset_write, we add all the registers in the
> > > reg_sr list to the save/restore list, but do not do the same for the
> > > nonpriv registers.  Add them in.
> > >
> > > v2:
> > > - Add all NONPRIV registers to avoid undefined behavior (Harrison)
> > > - s/whitelist/nonpriv
> > >
> > > v3:
> > > - Rebase
> > >
> > > Closes: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2249
> > > Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
> > > CC: Lucas de Marchi <lucas.demarchi@intel.com>
> > > CC: Matt Roper <matthew.d.roper@intel.com>
> > > CC: John Harrison <john.c.harrison@intel.com>
> > > CC: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> > > CC: Ashutosh Dixit <ashutosh.dixit@intel.com>
> > > Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > ---
> > >  drivers/gpu/drm/xe/xe_guc_ads.c | 7 +++++++
> > >  1 file changed, 7 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
> > > index 943146e5b460..b0afb89d9d90 100644
> > > --- a/drivers/gpu/drm/xe/xe_guc_ads.c
> > > +++ b/drivers/gpu/drm/xe/xe_guc_ads.c
> > > @@ -243,6 +243,8 @@ static size_t calculate_regset_size(struct xe_gt *gt)
> > >		xa_for_each(&hwe->reg_sr.xa, sr_idx, sr_entry)
> > >			count++;
> > >
> > > +	count += RING_MAX_NONPRIV_SLOTS * XE_NUM_HW_ENGINES;
> > > +
> > >	count += ADS_REGSET_EXTRA_MAX * XE_NUM_HW_ENGINES;
> > >
> > >	if (XE_WA(gt, 1607983814))
> > > @@ -727,6 +729,11 @@ static unsigned int guc_mmio_regset_write(struct xe_guc_ads *ads,
> > >	xa_for_each(&hwe->reg_sr.xa, idx, entry)
> > >		guc_mmio_regset_write_one(ads, regset_map, entry->reg, count++);
> > >
> > > +	for (i = 0; i < RING_MAX_NONPRIV_SLOTS; i++)
> > > +		guc_mmio_regset_write_one(ads, regset_map,
> > > +					  RING_FORCE_TO_NONPRIV(hwe->mmio_base, i),
> > > +					  count++);
> > > +
> >
> > What about the EU_PERF_CNTL registers which were there in the original
> > patch? Those are not needed?
>
> It turned out they weren't.  At least not for this use case.
> They might be needed later for a different issue, but right now we aren't
> observing any issues caused by their absence.

Ok, let's keep this patch restricted to the nonprov registers.


>
> >
> > >	for (e = extra_regs; e < extra_regs + ARRAY_SIZE(extra_regs); e++) {
> > >		if (e->skip)
> > >			continue;
> > > --
> > > 2.43.0
> > >
> >