Re: [Intel-xe] [PATCH 0/4] RFC: drm/xe/ras: Supporting RAS on XE.

[Jani Nikula <jani.nikula@linux.intel.com>]

On Thu, 06 Apr 2023, Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com> wrote:
> These patches in series are for adding Reliability, 
> Availability and Serviceability support on xe.
> Patches provide the infra for various hardware error
> counting and logging. These error counters will be exposed to 
> userspace in subsequent patches.
> In current patches:
> 1) We are adding support to handle new interrupts bits.
> 2) Counting of GT errors.
> 3) Soc/SGunit error counting.
> 4) CSC HW and FW error counting and sending uvent.
>
> Akeem G Abodunrin (1):
>   drm/xe/ras: Add support for reporting CSC HW and FW errors.
>
> Aravind Iddamsetty (2):
>   drm/xe/ras: Log the GT hw errors.
>   drm/xe/ras: Count SOC and SGUNIT errors
>
> Himal Prasad Ghimiray (1):
>   drm/xe: Handle GRF/IC ECC error irq
>
>  drivers/gpu/drm/xe/regs/xe_regs.h    | 244 ++++++++

Please don't recreate i915_reg.h in xe. Please add separate regs files
like we've been doing in i915. It's pain to split a monster register
file later.

BR,
Jani.


>  drivers/gpu/drm/xe/xe_device.c       |   6 +
>  drivers/gpu/drm/xe/xe_device_types.h |   4 +
>  drivers/gpu/drm/xe/xe_gt.c           |  30 +
>  drivers/gpu/drm/xe/xe_gt_types.h     | 105 ++++
>  drivers/gpu/drm/xe/xe_irq.c          | 824 +++++++++++++++++++++++++++
>  drivers/gpu/drm/xe/xe_pci.c          |   6 +
>  7 files changed, 1219 insertions(+)

-- 
Jani Nikula, Intel Open Source Graphics Center