From: Jani Nikula <jani.nikula@linux.intel.com>
To: "Ghimiray, Himal Prasad" <himal.prasad.ghimiray@intel.com>,
"intel-xe@lists.freedesktop.org" <intel-xe@lists.freedesktop.org>
Cc: Matt Roper <matthew.d.roper@intel.com>,
Lucas De Marchi <lucas.demarchi@intel.com>,
Rodrigo Vivi <rodrigo.vivi@intel.com>
Subject: Re: [Intel-xe] [PATCH 0/4] RFC: drm/xe/ras: Supporting RAS on XE.
Date: Tue, 02 May 2023 12:38:21 +0300 [thread overview]
Message-ID: <87y1m713aq.fsf@intel.com> (raw)
In-Reply-To: <SA1PR11MB70389B5E7E0207B638A90228B3659@SA1PR11MB7038.namprd11.prod.outlook.com>
On Wed, 26 Apr 2023, "Ghimiray, Himal Prasad" <himal.prasad.ghimiray@intel.com> wrote:
> Hi Jani,
>
> Is recommendation to create new .h file for error related registers ?
> Can I go ahead with adding file xe_gt_error_regs.h (GT, SOC, GSC) which explicitly mentions registers related to error handling ?
I don't know what the best grouping for this stuff would be. Maybe I'd
go for grouping by hardware blocks rather than functionality like
errors. Cc: Lucas, Matt, Rodrigo, just to pick a few names who might
have a better idea.
Just don't dump register macros to a single file that will bloat to
become unmanageable.
BR,
Jani.
PS. Please also don't top-post on mailing lists.
>
> BR
> Himal Ghimiray
>
>
>> -----Original Message-----
>> From: Jani Nikula <jani.nikula@linux.intel.com>
>> Sent: 06 April 2023 17:56
>> To: Ghimiray, Himal Prasad <himal.prasad.ghimiray@intel.com>; intel-
>> xe@lists.freedesktop.org
>> Cc: Ghimiray, Himal Prasad <himal.prasad.ghimiray@intel.com>
>> Subject: Re: [Intel-xe] [PATCH 0/4] RFC: drm/xe/ras: Supporting RAS on XE.
>>
>> On Thu, 06 Apr 2023, Himal Prasad Ghimiray
>> <himal.prasad.ghimiray@intel.com> wrote:
>> > These patches in series are for adding Reliability, Availability and
>> > Serviceability support on xe.
>> > Patches provide the infra for various hardware error counting and
>> > logging. These error counters will be exposed to userspace in
>> > subsequent patches.
>> > In current patches:
>> > 1) We are adding support to handle new interrupts bits.
>> > 2) Counting of GT errors.
>> > 3) Soc/SGunit error counting.
>> > 4) CSC HW and FW error counting and sending uvent.
>> >
>> > Akeem G Abodunrin (1):
>> > drm/xe/ras: Add support for reporting CSC HW and FW errors.
>> >
>> > Aravind Iddamsetty (2):
>> > drm/xe/ras: Log the GT hw errors.
>> > drm/xe/ras: Count SOC and SGUNIT errors
>> >
>> > Himal Prasad Ghimiray (1):
>> > drm/xe: Handle GRF/IC ECC error irq
>> >
>> > drivers/gpu/drm/xe/regs/xe_regs.h | 244 ++++++++
>>
>> Please don't recreate i915_reg.h in xe. Please add separate regs files like
>> we've been doing in i915. It's pain to split a monster register file later.
>>
>> BR,
>> Jani.
>>
>>
>> > drivers/gpu/drm/xe/xe_device.c | 6 +
>> > drivers/gpu/drm/xe/xe_device_types.h | 4 +
>> > drivers/gpu/drm/xe/xe_gt.c | 30 +
>> > drivers/gpu/drm/xe/xe_gt_types.h | 105 ++++
>> > drivers/gpu/drm/xe/xe_irq.c | 824
>> +++++++++++++++++++++++++++
>> > drivers/gpu/drm/xe/xe_pci.c | 6 +
>> > 7 files changed, 1219 insertions(+)
>>
>> --
>> Jani Nikula, Intel Open Source Graphics Center
--
Jani Nikula, Intel Open Source Graphics Center
next prev parent reply other threads:[~2023-05-02 9:38 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-06 9:26 [Intel-xe] [PATCH 0/4] RFC: drm/xe/ras: Supporting RAS on XE Himal Prasad Ghimiray
2023-04-06 9:26 ` [Intel-xe] ✗ CI.Patch_applied: failure for " Patchwork
2023-04-06 9:26 ` [Intel-xe] [PATCH 1/4] drm/xe: Handle GRF/IC ECC error irq Himal Prasad Ghimiray
2023-04-24 23:51 ` Matt Roper
2023-04-27 7:18 ` Ghimiray, Himal Prasad
2023-05-02 19:56 ` Rodrigo Vivi
2023-04-06 9:26 ` [Intel-xe] [PATCH 2/4] drm/xe/ras: Log the GT hw errors Himal Prasad Ghimiray
2023-04-24 13:37 ` Dafna Hirschfeld
2023-04-25 0:22 ` Matt Roper
2023-04-28 8:00 ` Ghimiray, Himal Prasad
2023-05-04 0:02 ` Matt Roper
2023-05-05 7:24 ` Iddamsetty, Aravind
2023-05-05 15:10 ` Matt Roper
2023-04-25 4:26 ` Iddamsetty, Aravind
2023-04-06 9:26 ` [Intel-xe] [PATCH 3/4] drm/xe/ras: Count SOC and SGUNIT errors Himal Prasad Ghimiray
2023-04-06 9:26 ` [Intel-xe] [PATCH 4/4] drm/xe/ras: Add support for reporting CSC HW and FW errors Himal Prasad Ghimiray
2023-04-06 12:25 ` [Intel-xe] [PATCH 0/4] RFC: drm/xe/ras: Supporting RAS on XE Jani Nikula
2023-04-26 12:14 ` Ghimiray, Himal Prasad
2023-05-02 9:38 ` Jani Nikula [this message]
2023-05-02 19:58 ` Rodrigo Vivi
2023-05-02 20:41 ` Lucas De Marchi
-- strict thread matches above, loose matches on Subject: below --
2023-04-06 9:22 [Intel-xe] [PATCH 0/4] [RFC] " Himal Prasad Ghimiray
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=87y1m713aq.fsf@intel.com \
--to=jani.nikula@linux.intel.com \
--cc=himal.prasad.ghimiray@intel.com \
--cc=intel-xe@lists.freedesktop.org \
--cc=lucas.demarchi@intel.com \
--cc=matthew.d.roper@intel.com \
--cc=rodrigo.vivi@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox