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From: Gustavo Sousa <gustavo.sousa@intel.com>
To: <intel-xe@lists.freedesktop.org>
Cc: Matt Roper <matthew.d.roper@intel.com>,
	Michal Wajdeczko <michal.wajdeczko@intel.com>
Subject: Re: [PATCH v3 0/7] Fix MCR inconsistencies in RTP tables
Date: Fri, 15 May 2026 18:19:01 -0300	[thread overview]
Message-ID: <874ik82wxm.fsf@intel.com> (raw)
In-Reply-To: <20260514-rtp-mcr-check-v3-0-30dd47855fee@intel.com>

Gustavo Sousa <gustavo.sousa@intel.com> writes:

> The Xe driver uses struct xe_reg as base type to represent a register
> definition, and defines struct xe_reg_mcr as a sort of subtype to
> represent multicast replicated (MCR) registers.  It uses this subtyping
> to "force" the use of the correct MCR-based API for MMIO operations on
> MCR registers.
>
> In regular driver code, usage of those MCR registers usually need some
> reasoning about whether the access will need to be steered or a
> multicast; and the correct MCR API will be selected.
>
> For RTP tables, on the other hand, that's not the case.  The developer
> when defining an action the developer can either select a regular or a
> MCR register and the register save/restore logic will make the selection
> between regular vs MCR MMIO access depending on the register instance
> defined in the RTP action.
>
> That allows some mistakes to go unnoticed: a non-MCR register instance
> could be used for an RTP action against a platform where such a register
> is actually MCR; and vice-versa.
>
> This series fixes those mistakes.
>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>

Pushed to drm-xe-next.

Thanks Matt and Michal for the reviews!

--
Gustavo Sousa

> ---
> Changes in v3:
> - Dropped patch "drm/xe/kunit: Add xe_kunit_helper_is_live_test()",
>   which became unnecessary in v2.
> - This version is being sent mainly to get fresh CI results before
>   applying, just in case any new inconsistencies were introduced in the
>   meantime.
> - Link to v2: https://patch.msgid.link/20260508-rtp-mcr-check-v2-0-9897b147a5d2@intel.com
>
> Changes in v2:
> - Incorporated review feedback. Please see individual patches for the
>   respective changelogs.
> - Dropped inclusion of hw_engines in xe_wa test.  We will implement a more
>   focused test to check for MCR inconsistencies in the future, which will
>   iterate over all applicable RTP tables.
> - As a result of the above, dropped MMIO interception patches, as they became
>   unnecessary.
> - Link to v1: https://patch.msgid.link/20260116-rtp-mcr-check-v1-0-d420b9c1a327@intel.com
>
> ---
> Gustavo Sousa (7):
>       drm/xe: Define CACHE_MODE_1 as MCR register
>       drm/xe: Define and use MCR version of COMMON_SLICE_CHICKEN1
>       drm/xe: Define and use MCR version of COMMON_SLICE_CHICKEN4
>       drm/xe: Extract xe_hw_engine_setup_reg_lrc()
>       drm/xe/kunit: Use KUNIT_EXPECT_EQ() in xe_wa_gt()
>       drm/xe/mcr: Extract reg_in_steering_type_ranges()
>       drm/xe/reg_sr: Do sanity check for MCR vs non-MCR
>
>  drivers/gpu/drm/xe/regs/xe_gt_regs.h   |  4 +-
>  drivers/gpu/drm/xe/tests/xe_rtp_test.c | 71 ++++++++++++++++++++++++++++++----
>  drivers/gpu/drm/xe/tests/xe_wa_test.c  | 14 ++++++-
>  drivers/gpu/drm/xe/xe_gt.c             |  8 ++--
>  drivers/gpu/drm/xe/xe_gt_mcr.c         | 67 +++++++++++++++++++++++---------
>  drivers/gpu/drm/xe/xe_gt_mcr.h         |  1 +
>  drivers/gpu/drm/xe/xe_hw_engine.c      | 15 ++++++-
>  drivers/gpu/drm/xe/xe_hw_engine.h      |  2 +-
>  drivers/gpu/drm/xe/xe_reg_sr.c         | 36 +++++++++++++++++
>  drivers/gpu/drm/xe/xe_tuning.c         |  2 +-
>  drivers/gpu/drm/xe/xe_wa.c             |  6 +--
>  11 files changed, 186 insertions(+), 40 deletions(-)
> ---
> base-commit: 2edbd77a2045d12d30c95dbb5842b831e3da0035
> change-id: 20260112-rtp-mcr-check-f976cb1adf94
>
> Best regards,
> --  
> Gustavo Sousa <gustavo.sousa@intel.com>

      parent reply	other threads:[~2026-05-15 21:19 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-14 21:44 [PATCH v3 0/7] Fix MCR inconsistencies in RTP tables Gustavo Sousa
2026-05-14 21:44 ` [PATCH v3 1/7] drm/xe: Define CACHE_MODE_1 as MCR register Gustavo Sousa
2026-05-14 21:44 ` [PATCH v3 2/7] drm/xe: Define and use MCR version of COMMON_SLICE_CHICKEN1 Gustavo Sousa
2026-05-14 21:44 ` [PATCH v3 3/7] drm/xe: Define and use MCR version of COMMON_SLICE_CHICKEN4 Gustavo Sousa
2026-05-14 21:44 ` [PATCH v3 4/7] drm/xe: Extract xe_hw_engine_setup_reg_lrc() Gustavo Sousa
2026-05-14 21:44 ` [PATCH v3 5/7] drm/xe/kunit: Use KUNIT_EXPECT_EQ() in xe_wa_gt() Gustavo Sousa
2026-05-14 21:44 ` [PATCH v3 6/7] drm/xe/mcr: Extract reg_in_steering_type_ranges() Gustavo Sousa
2026-05-14 21:44 ` [PATCH v3 7/7] drm/xe/reg_sr: Do sanity check for MCR vs non-MCR Gustavo Sousa
2026-05-14 23:03 ` ✓ CI.KUnit: success for Fix MCR inconsistencies in RTP tables (rev3) Patchwork
2026-05-14 23:55 ` ✓ Xe.CI.BAT: " Patchwork
2026-05-15 17:30 ` ✓ Xe.CI.FULL: " Patchwork
2026-05-15 21:19 ` Gustavo Sousa [this message]

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