* [PATCH 00/16] DPLL framework redesign
@ 2025-04-02 8:31 Suraj Kandpal
2025-04-02 8:31 ` [PATCH 01/16] drm/i915/dpll: Rename intel_shared_dpll_state Suraj Kandpal
` (23 more replies)
0 siblings, 24 replies; 31+ messages in thread
From: Suraj Kandpal @ 2025-04-02 8:31 UTC (permalink / raw)
To: intel-xe, intel-gfx
Cc: ankit.k.nautiyal, uma.shankar, jani.nikula, mika.kahola,
ville.syrjala, Suraj Kandpal
Since MTL we moved away from using our existing DPLL framework this
was done since the existing API didnt really work for us.
This Redesing is a first part of two part series which will
redesign the current framework so that it can be used for
PLL/PHY enablement going forward.
Here we move away from the shared_dpll naming and also
change arguments for some functions which are needed for PLL
which have individual PHY keeping in mind that we don't break
any of the legacy stuff. When this gets approved and merged a
second series hooking up the SNPS PHY PLL API to this framework
will be posted. This is done to reduce the rework in case the
current design floated ends up getting changed during the review
process.
We also rename some functions in intel_dpll_mgr to start with
intel_dpll_* in an effort to make sure all exported functions
have the filename at the start.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Suraj Kandpal (16):
drm/i915/dpll: Rename intel_shared_dpll_state
drm/i915/dpll: Rename macro for_each_shared_dpll
drm/i915/dpll: Rename intel_shared_dpll_funcs
drm/i915/dpll: Rename intel_shared_dpll
drm/i915/dpll: Move away from using shared dpll
drm/i915/dpll: Rename crtc_get_shared_dpll
drm/i915/dpll: Change argument for enable hook in
intel_global_dpll_funcs
drm/i915/drm: Rename disable hook in intel_dpll_global_func
drm/i915/dpll: Introduce new hook in intel_dpll_global_func
drm/i915/dpll: Add intel_encoder argument to get_hw_state hook
drm/i915/dpll: Change arguments for get_freq hook
drm/i915/dpll: Rename intel_[enable/disable]_global_dpll
drm/i915/dpll: Rename intel_unreference_dpll_global_crtc
drm/i915/dpll: Rename intel_<release/reserve>_dpll_globals
drm/i915/dpll: Rename intel_compute_dpll_globals
drm/i915/dpll: Rename intel_update_active_dpll
drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 70 +-
drivers/gpu/drm/i915/display/intel_ddi.h | 6 +-
drivers/gpu/drm/i915/display/intel_display.c | 22 +-
.../gpu/drm/i915/display/intel_display_core.h | 4 +-
.../drm/i915/display/intel_display_debugfs.c | 4 +-
.../drm/i915/display/intel_display_driver.c | 2 +-
.../drm/i915/display/intel_display_types.h | 8 +-
drivers/gpu/drm/i915/display/intel_dpll.c | 30 +-
drivers/gpu/drm/i915/display/intel_dpll.h | 2 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 707 +++++++++---------
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 79 +-
drivers/gpu/drm/i915/display/intel_fdi.c | 2 +-
drivers/gpu/drm/i915/display/intel_lvds.c | 2 +-
.../drm/i915/display/intel_modeset_setup.c | 10 +-
.../drm/i915/display/intel_modeset_verify.c | 4 +-
.../gpu/drm/i915/display/intel_pch_display.c | 20 +-
.../gpu/drm/i915/display/intel_pch_refclk.c | 4 +-
18 files changed, 500 insertions(+), 478 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 01/16] drm/i915/dpll: Rename intel_shared_dpll_state
2025-04-02 8:31 [PATCH 00/16] DPLL framework redesign Suraj Kandpal
@ 2025-04-02 8:31 ` Suraj Kandpal
2025-04-02 8:31 ` [PATCH 02/16] drm/i915/dpll: Rename macro for_each_shared_dpll Suraj Kandpal
` (22 subsequent siblings)
23 siblings, 0 replies; 31+ messages in thread
From: Suraj Kandpal @ 2025-04-02 8:31 UTC (permalink / raw)
To: intel-xe, intel-gfx
Cc: ankit.k.nautiyal, uma.shankar, jani.nikula, mika.kahola,
ville.syrjala, Suraj Kandpal
Rename intel_shared_dpll_state to just intel_dpll_state since it may
not necessarily store share dpll state info specially since
DISPLAY_VER >= 14 PLL's are not shared.
Also change the name of variables which may have been assoiciated as
a shared_dpll.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
.../drm/i915/display/intel_display_types.h | 2 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 56 +++++++++----------
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 8 +--
3 files changed, 33 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 367b53a9eae2..7d1c64f7b405 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -591,7 +591,7 @@ struct intel_atomic_state {
bool dpll_set, modeset;
- struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
+ struct intel_dpll_state dpll_state[I915_NUM_PLLS];
struct intel_dp_tunnel_inherited_state *inherited_dp_tunnels;
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index ec7feef1ef59..6edb4570d764 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -119,17 +119,17 @@ struct intel_dpll_mgr {
static void
intel_atomic_duplicate_dpll_state(struct intel_display *display,
- struct intel_shared_dpll_state *shared_dpll)
+ struct intel_dpll_state *dpll_state)
{
struct intel_shared_dpll *pll;
int i;
/* Copy shared dpll state */
for_each_shared_dpll(display, pll, i)
- shared_dpll[pll->index] = pll->state;
+ dpll_state[pll->index] = pll->state;
}
-static struct intel_shared_dpll_state *
+static struct intel_dpll_state *
intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
{
struct intel_atomic_state *state = to_intel_atomic_state(s);
@@ -141,10 +141,10 @@ intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
state->dpll_set = true;
intel_atomic_duplicate_dpll_state(display,
- state->shared_dpll);
+ state->dpll_state);
}
- return state->shared_dpll;
+ return state->dpll_state;
}
/**
@@ -362,11 +362,11 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
{
struct intel_display *display = to_intel_display(crtc);
unsigned long dpll_mask_all = intel_dpll_mask_all(display);
- struct intel_shared_dpll_state *shared_dpll;
+ struct intel_dpll_state *dpll_state;
struct intel_shared_dpll *unused_pll = NULL;
enum intel_dpll_id id;
- shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
+ dpll_state = intel_atomic_get_shared_dpll_state(&state->base);
drm_WARN_ON(display->drm, dpll_mask & ~dpll_mask_all);
@@ -378,20 +378,20 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
continue;
/* Only want to check enabled timings first */
- if (shared_dpll[pll->index].pipe_mask == 0) {
+ if (dpll_state[pll->index].pipe_mask == 0) {
if (!unused_pll)
unused_pll = pll;
continue;
}
if (memcmp(dpll_hw_state,
- &shared_dpll[pll->index].hw_state,
+ &dpll_state[pll->index].hw_state,
sizeof(*dpll_hw_state)) == 0) {
drm_dbg_kms(display->drm,
"[CRTC:%d:%s] sharing existing %s (pipe mask 0x%x, active 0x%x)\n",
crtc->base.base.id, crtc->base.name,
pll->info->name,
- shared_dpll[pll->index].pipe_mask,
+ dpll_state[pll->index].pipe_mask,
pll->active_mask);
return pll;
}
@@ -412,20 +412,20 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
* intel_reference_shared_dpll_crtc - Get a DPLL reference for a CRTC
* @crtc: CRTC on which behalf the reference is taken
* @pll: DPLL for which the reference is taken
- * @shared_dpll_state: the DPLL atomic state in which the reference is tracked
+ * @dpll_state: the DPLL atomic state in which the reference is tracked
*
* Take a reference for @pll tracking the use of it by @crtc.
*/
static void
intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc,
const struct intel_shared_dpll *pll,
- struct intel_shared_dpll_state *shared_dpll_state)
+ struct intel_dpll_state *dpll_state)
{
struct intel_display *display = to_intel_display(crtc);
- drm_WARN_ON(display->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) != 0);
+ drm_WARN_ON(display->drm, (dpll_state->pipe_mask & BIT(crtc->pipe)) != 0);
- shared_dpll_state->pipe_mask |= BIT(crtc->pipe);
+ dpll_state->pipe_mask |= BIT(crtc->pipe);
drm_dbg_kms(display->drm, "[CRTC:%d:%s] reserving %s\n",
crtc->base.base.id, crtc->base.name, pll->info->name);
@@ -437,34 +437,34 @@ intel_reference_shared_dpll(struct intel_atomic_state *state,
const struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
- struct intel_shared_dpll_state *shared_dpll;
+ struct intel_dpll_state *dpll_state;
- shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
+ dpll_state = intel_atomic_get_shared_dpll_state(&state->base);
- if (shared_dpll[pll->index].pipe_mask == 0)
- shared_dpll[pll->index].hw_state = *dpll_hw_state;
+ if (dpll_state[pll->index].pipe_mask == 0)
+ dpll_state[pll->index].hw_state = *dpll_hw_state;
- intel_reference_shared_dpll_crtc(crtc, pll, &shared_dpll[pll->index]);
+ intel_reference_shared_dpll_crtc(crtc, pll, &dpll_state[pll->index]);
}
/**
* intel_unreference_shared_dpll_crtc - Drop a DPLL reference for a CRTC
* @crtc: CRTC on which behalf the reference is dropped
* @pll: DPLL for which the reference is dropped
- * @shared_dpll_state: the DPLL atomic state in which the reference is tracked
+ * @dpll_state: the DPLL atomic state in which the reference is tracked
*
* Drop a reference for @pll tracking the end of use of it by @crtc.
*/
void
intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
const struct intel_shared_dpll *pll,
- struct intel_shared_dpll_state *shared_dpll_state)
+ struct intel_dpll_state *dpll_state)
{
struct intel_display *display = to_intel_display(crtc);
- drm_WARN_ON(display->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) == 0);
+ drm_WARN_ON(display->drm, (dpll_state->pipe_mask & BIT(crtc->pipe)) == 0);
- shared_dpll_state->pipe_mask &= ~BIT(crtc->pipe);
+ dpll_state->pipe_mask &= ~BIT(crtc->pipe);
drm_dbg_kms(display->drm, "[CRTC:%d:%s] releasing %s\n",
crtc->base.base.id, crtc->base.name, pll->info->name);
@@ -474,11 +474,11 @@ static void intel_unreference_shared_dpll(struct intel_atomic_state *state,
const struct intel_crtc *crtc,
const struct intel_shared_dpll *pll)
{
- struct intel_shared_dpll_state *shared_dpll;
+ struct intel_dpll_state *dpll_state;
- shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
+ dpll_state = intel_atomic_get_shared_dpll_state(&state->base);
- intel_unreference_shared_dpll_crtc(crtc, pll, &shared_dpll[pll->index]);
+ intel_unreference_shared_dpll_crtc(crtc, pll, &dpll_state[pll->index]);
}
static void intel_put_dpll(struct intel_atomic_state *state,
@@ -511,7 +511,7 @@ static void intel_put_dpll(struct intel_atomic_state *state,
void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
{
struct intel_display *display = to_intel_display(state);
- struct intel_shared_dpll_state *shared_dpll = state->shared_dpll;
+ struct intel_dpll_state *dpll_state = state->dpll_state;
struct intel_shared_dpll *pll;
int i;
@@ -519,7 +519,7 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
return;
for_each_shared_dpll(display, pll, i)
- swap(pll->state, shared_dpll[pll->index]);
+ swap(pll->state, dpll_state[pll->index]);
}
static bool ibx_pch_dpll_get_hw_state(struct intel_display *display,
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index caffb084830c..fe6c676737bb 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -280,7 +280,7 @@ struct intel_dpll_hw_state {
};
/**
- * struct intel_shared_dpll_state - hold the DPLL atomic state
+ * struct intel_dpll_state - hold the DPLL atomic state
*
* This structure holds an atomic state for the DPLL, that can represent
* either its current state (in struct &intel_shared_dpll) or a desired
@@ -289,7 +289,7 @@ struct intel_dpll_hw_state {
*
* See also intel_reserve_shared_dplls() and intel_release_shared_dplls().
*/
-struct intel_shared_dpll_state {
+struct intel_dpll_state {
/**
* @pipe_mask: mask of pipes using this DPLL, active or not
*/
@@ -353,7 +353,7 @@ struct intel_shared_dpll {
* Store the state for the pll, including its hw state
* and CRTCs using it.
*/
- struct intel_shared_dpll_state state;
+ struct intel_dpll_state state;
/**
* @index: index for atomic state
@@ -406,7 +406,7 @@ void intel_release_shared_dplls(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
const struct intel_shared_dpll *pll,
- struct intel_shared_dpll_state *shared_dpll_state);
+ struct intel_dpll_state *shared_dpll_state);
void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
enum icl_port_dpll_id port_dpll_id);
void intel_update_active_dpll(struct intel_atomic_state *state,
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 02/16] drm/i915/dpll: Rename macro for_each_shared_dpll
2025-04-02 8:31 [PATCH 00/16] DPLL framework redesign Suraj Kandpal
2025-04-02 8:31 ` [PATCH 01/16] drm/i915/dpll: Rename intel_shared_dpll_state Suraj Kandpal
@ 2025-04-02 8:31 ` Suraj Kandpal
2025-04-02 8:31 ` [PATCH 03/16] drm/i915/dpll: Rename intel_shared_dpll_funcs Suraj Kandpal
` (21 subsequent siblings)
23 siblings, 0 replies; 31+ messages in thread
From: Suraj Kandpal @ 2025-04-02 8:31 UTC (permalink / raw)
To: intel-xe, intel-gfx
Cc: ankit.k.nautiyal, uma.shankar, jani.nikula, mika.kahola,
ville.syrjala, Suraj Kandpal
Rename the macro for_each_shared_dpll to for_each_dpll since
this loop will not necessarily be used for only shared
dpll in future.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
.../gpu/drm/i915/display/intel_display_debugfs.c | 2 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 16 ++++++++--------
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 2 +-
drivers/gpu/drm/i915/display/intel_pch_refclk.c | 2 +-
4 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 4c784bb7e14b..a317c6646382 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -634,7 +634,7 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
display->dpll.ref_clks.nssc,
display->dpll.ref_clks.ssc);
- for_each_shared_dpll(display, pll, i) {
+ for_each_dpll(display, pll, i) {
drm_printf(&p, "DPLL%i: %s, id: %i\n", pll->index,
pll->info->name, pll->info->id);
drm_printf(&p, " pipe_mask: 0x%x, active: 0x%x, on: %s\n",
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 6edb4570d764..bbb51119ef5b 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -124,8 +124,8 @@ intel_atomic_duplicate_dpll_state(struct intel_display *display,
struct intel_shared_dpll *pll;
int i;
- /* Copy shared dpll state */
- for_each_shared_dpll(display, pll, i)
+ /* Copy dpll state */
+ for_each_dpll(display, pll, i)
dpll_state[pll->index] = pll->state;
}
@@ -162,7 +162,7 @@ intel_get_shared_dpll_by_id(struct intel_display *display,
struct intel_shared_dpll *pll;
int i;
- for_each_shared_dpll(display, pll, i) {
+ for_each_dpll(display, pll, i) {
if (pll->info->id == id)
return pll;
}
@@ -345,7 +345,7 @@ intel_dpll_mask_all(struct intel_display *display)
unsigned long dpll_mask = 0;
int i;
- for_each_shared_dpll(display, pll, i) {
+ for_each_dpll(display, pll, i) {
drm_WARN_ON(display->drm, dpll_mask & BIT(pll->info->id));
dpll_mask |= BIT(pll->info->id);
@@ -518,7 +518,7 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
if (!state->dpll_set)
return;
- for_each_shared_dpll(display, pll, i)
+ for_each_dpll(display, pll, i)
swap(pll->state, dpll_state[pll->index]);
}
@@ -4543,7 +4543,7 @@ void intel_dpll_readout_hw_state(struct intel_display *display)
struct intel_shared_dpll *pll;
int i;
- for_each_shared_dpll(display, pll, i)
+ for_each_dpll(display, pll, i)
readout_dpll_hw_state(display, pll);
}
@@ -4572,7 +4572,7 @@ void intel_dpll_sanitize_state(struct intel_display *display)
intel_cx0_pll_power_save_wa(display);
- for_each_shared_dpll(display, pll, i)
+ for_each_dpll(display, pll, i)
sanitize_dpll_state(display, pll);
}
@@ -4721,6 +4721,6 @@ void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state)
struct intel_shared_dpll *pll;
int i;
- for_each_shared_dpll(display, pll, i)
+ for_each_dpll(display, pll, i)
verify_single_dpll_state(display, pll, NULL, NULL);
}
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index fe6c676737bb..d93072486831 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -30,7 +30,7 @@
#include "intel_display_power.h"
#include "intel_wakeref.h"
-#define for_each_shared_dpll(__display, __pll, __i) \
+#define for_each_dpll(__display, __pll, __i) \
for ((__i) = 0; (__i) < (__display)->dpll.num_shared_dpll && \
((__pll) = &(__display)->dpll.shared_dplls[(__i)]) ; (__i)++)
diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
index 1307a478861a..611f3b8dffef 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
@@ -536,7 +536,7 @@ static void ilk_init_pch_refclk(struct intel_display *display)
}
/* Check if any DPLLs are using the SSC source */
- for_each_shared_dpll(display, pll, i) {
+ for_each_dpll(display, pll, i) {
u32 temp;
temp = intel_de_read(display, PCH_DPLL(pll->info->id));
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 03/16] drm/i915/dpll: Rename intel_shared_dpll_funcs
2025-04-02 8:31 [PATCH 00/16] DPLL framework redesign Suraj Kandpal
2025-04-02 8:31 ` [PATCH 01/16] drm/i915/dpll: Rename intel_shared_dpll_state Suraj Kandpal
2025-04-02 8:31 ` [PATCH 02/16] drm/i915/dpll: Rename macro for_each_shared_dpll Suraj Kandpal
@ 2025-04-02 8:31 ` Suraj Kandpal
2025-04-03 14:59 ` Jani Nikula
2025-04-02 8:31 ` [PATCH 04/16] drm/i915/dpll: Rename intel_shared_dpll Suraj Kandpal
` (20 subsequent siblings)
23 siblings, 1 reply; 31+ messages in thread
From: Suraj Kandpal @ 2025-04-02 8:31 UTC (permalink / raw)
To: intel-xe, intel-gfx
Cc: ankit.k.nautiyal, uma.shankar, jani.nikula, mika.kahola,
ville.syrjala, Suraj Kandpal
Rename intel_shared_dpll_funcs to intel_global_dpll_funcs
since it needs to represent both shared and individual
dplls.
--v2
-Change intel_global_dpll to intel_dpll_global to be more
in line with the naming standard where the name should
start with the file name [Jani]
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 24 +++++++++----------
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 4 ++--
2 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index bbb51119ef5b..92ca2a544e2f 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -61,7 +61,7 @@
*/
/* platform specific hooks for managing DPLLs */
-struct intel_shared_dpll_funcs {
+struct intel_dpll_global_funcs {
/*
* Hook for enabling the pll, called from intel_enable_shared_dpll() if
* the pll is not already enabled.
@@ -668,7 +668,7 @@ static bool ibx_compare_hw_state(const struct intel_dpll_hw_state *_a,
a->fp1 == b->fp1;
}
-static const struct intel_shared_dpll_funcs ibx_pch_dpll_funcs = {
+static const struct intel_dpll_global_funcs ibx_pch_dpll_funcs = {
.enable = ibx_pch_dpll_enable,
.disable = ibx_pch_dpll_disable,
.get_hw_state = ibx_pch_dpll_get_hw_state,
@@ -1268,14 +1268,14 @@ static bool hsw_compare_hw_state(const struct intel_dpll_hw_state *_a,
a->spll == b->spll;
}
-static const struct intel_shared_dpll_funcs hsw_ddi_wrpll_funcs = {
+static const struct intel_dpll_global_funcs hsw_ddi_wrpll_funcs = {
.enable = hsw_ddi_wrpll_enable,
.disable = hsw_ddi_wrpll_disable,
.get_hw_state = hsw_ddi_wrpll_get_hw_state,
.get_freq = hsw_ddi_wrpll_get_freq,
};
-static const struct intel_shared_dpll_funcs hsw_ddi_spll_funcs = {
+static const struct intel_dpll_global_funcs hsw_ddi_spll_funcs = {
.enable = hsw_ddi_spll_enable,
.disable = hsw_ddi_spll_disable,
.get_hw_state = hsw_ddi_spll_get_hw_state,
@@ -1300,7 +1300,7 @@ static bool hsw_ddi_lcpll_get_hw_state(struct intel_display *display,
return true;
}
-static const struct intel_shared_dpll_funcs hsw_ddi_lcpll_funcs = {
+static const struct intel_dpll_global_funcs hsw_ddi_lcpll_funcs = {
.enable = hsw_ddi_lcpll_enable,
.disable = hsw_ddi_lcpll_disable,
.get_hw_state = hsw_ddi_lcpll_get_hw_state,
@@ -2002,14 +2002,14 @@ static bool skl_compare_hw_state(const struct intel_dpll_hw_state *_a,
a->cfgcr2 == b->cfgcr2;
}
-static const struct intel_shared_dpll_funcs skl_ddi_pll_funcs = {
+static const struct intel_dpll_global_funcs skl_ddi_pll_funcs = {
.enable = skl_ddi_pll_enable,
.disable = skl_ddi_pll_disable,
.get_hw_state = skl_ddi_pll_get_hw_state,
.get_freq = skl_ddi_pll_get_freq,
};
-static const struct intel_shared_dpll_funcs skl_ddi_dpll0_funcs = {
+static const struct intel_dpll_global_funcs skl_ddi_dpll0_funcs = {
.enable = skl_ddi_dpll0_enable,
.disable = skl_ddi_dpll0_disable,
.get_hw_state = skl_ddi_dpll0_get_hw_state,
@@ -2484,7 +2484,7 @@ static bool bxt_compare_hw_state(const struct intel_dpll_hw_state *_a,
a->pcsdw12 == b->pcsdw12;
}
-static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = {
+static const struct intel_dpll_global_funcs bxt_ddi_pll_funcs = {
.enable = bxt_ddi_pll_enable,
.disable = bxt_ddi_pll_disable,
.get_hw_state = bxt_ddi_pll_get_hw_state,
@@ -4129,21 +4129,21 @@ static bool icl_compare_hw_state(const struct intel_dpll_hw_state *_a,
a->mg_pll_tdc_coldst_bias == b->mg_pll_tdc_coldst_bias;
}
-static const struct intel_shared_dpll_funcs combo_pll_funcs = {
+static const struct intel_dpll_global_funcs combo_pll_funcs = {
.enable = combo_pll_enable,
.disable = combo_pll_disable,
.get_hw_state = combo_pll_get_hw_state,
.get_freq = icl_ddi_combo_pll_get_freq,
};
-static const struct intel_shared_dpll_funcs tbt_pll_funcs = {
+static const struct intel_dpll_global_funcs tbt_pll_funcs = {
.enable = tbt_pll_enable,
.disable = tbt_pll_disable,
.get_hw_state = tbt_pll_get_hw_state,
.get_freq = icl_ddi_tbt_pll_get_freq,
};
-static const struct intel_shared_dpll_funcs mg_pll_funcs = {
+static const struct intel_dpll_global_funcs mg_pll_funcs = {
.enable = mg_pll_enable,
.disable = mg_pll_disable,
.get_hw_state = mg_pll_get_hw_state,
@@ -4191,7 +4191,7 @@ static const struct intel_dpll_mgr ehl_pll_mgr = {
.compare_hw_state = icl_compare_hw_state,
};
-static const struct intel_shared_dpll_funcs dkl_pll_funcs = {
+static const struct intel_dpll_global_funcs dkl_pll_funcs = {
.enable = mg_pll_enable,
.disable = mg_pll_disable,
.get_hw_state = dkl_pll_get_hw_state,
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index d93072486831..2080118be523 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -41,7 +41,7 @@ struct intel_crtc;
struct intel_crtc_state;
struct intel_encoder;
struct intel_shared_dpll;
-struct intel_shared_dpll_funcs;
+struct intel_dpll_global_funcs;
/**
* enum intel_dpll_id - possible DPLL ids
@@ -314,7 +314,7 @@ struct dpll_info {
/**
* @funcs: platform specific hooks
*/
- const struct intel_shared_dpll_funcs *funcs;
+ const struct intel_dpll_global_funcs *funcs;
/**
* @id: unique identifier for this DPLL
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 04/16] drm/i915/dpll: Rename intel_shared_dpll
2025-04-02 8:31 [PATCH 00/16] DPLL framework redesign Suraj Kandpal
` (2 preceding siblings ...)
2025-04-02 8:31 ` [PATCH 03/16] drm/i915/dpll: Rename intel_shared_dpll_funcs Suraj Kandpal
@ 2025-04-02 8:31 ` Suraj Kandpal
2025-04-03 15:01 ` Jani Nikula
2025-04-02 8:31 ` [PATCH 05/16] drm/i915/dpll: Move away from using shared dpll Suraj Kandpal
` (19 subsequent siblings)
23 siblings, 1 reply; 31+ messages in thread
From: Suraj Kandpal @ 2025-04-02 8:31 UTC (permalink / raw)
To: intel-xe, intel-gfx
Cc: ankit.k.nautiyal, uma.shankar, jani.nikula, mika.kahola,
ville.syrjala, Suraj Kandpal
Rename intel_shared_dpll to intel_dpll_global to represent both
shared and individual dplls. Since from MTL each PHY has it's
own PLL making the shared PLL naming a little outdated. In an
effort to make this framework accepting of future changes this
needs to be done.
--v2
-Use intel_dpll_global to make sure names start with the filename
[Jani/Ville]
-Explain the need of this rename [Jani]
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 52 ++--
drivers/gpu/drm/i915/display/intel_ddi.h | 6 +-
drivers/gpu/drm/i915/display/intel_display.c | 12 +-
.../gpu/drm/i915/display/intel_display_core.h | 4 +-
.../drm/i915/display/intel_display_debugfs.c | 2 +-
.../drm/i915/display/intel_display_types.h | 6 +-
drivers/gpu/drm/i915/display/intel_dpll.c | 4 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 228 +++++++++---------
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 18 +-
drivers/gpu/drm/i915/display/intel_fdi.c | 2 +-
drivers/gpu/drm/i915/display/intel_lvds.c | 2 +-
.../drm/i915/display/intel_modeset_setup.c | 8 +-
.../gpu/drm/i915/display/intel_pch_display.c | 10 +-
.../gpu/drm/i915/display/intel_pch_refclk.c | 2 +-
15 files changed, 179 insertions(+), 179 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index b69c713fb79a..97c20c493e4d 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -658,7 +658,7 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder,
{
struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
- struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ struct intel_dpll_global *pll = crtc_state->dpll_global;
enum phy phy;
u32 val;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 56068b2ef964..a8934ea5077d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -234,7 +234,7 @@ static void intel_wait_ddi_buf_active(struct intel_encoder *encoder)
port_name(port));
}
-static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
+static u32 hsw_pll_to_ddi_pll_sel(const struct intel_dpll_global *pll)
{
switch (pll->info->id) {
case DPLL_ID_WRPLL1:
@@ -258,7 +258,7 @@ static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
- const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ const struct intel_dpll_global *pll = crtc_state->dpll_global;
int clock = crtc_state->port_clock;
const enum intel_dpll_id id = pll->info->id;
@@ -1559,7 +1559,7 @@ static bool _icl_ddi_is_clock_enabled(struct intel_display *display, i915_reg_t
return !(intel_de_read(display, reg) & clk_off);
}
-static struct intel_shared_dpll *
+static struct intel_dpll_global *
_icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg,
u32 clk_sel_mask, u32 clk_sel_shift)
{
@@ -1574,7 +1574,7 @@ static void adls_ddi_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(encoder);
- const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ const struct intel_dpll_global *pll = crtc_state->dpll_global;
enum phy phy = intel_encoder_to_phy(encoder);
if (drm_WARN_ON(display->drm, !pll))
@@ -1604,7 +1604,7 @@ static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder)
ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
}
-static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder)
+static struct intel_dpll_global *adls_ddi_get_pll(struct intel_encoder *encoder)
{
struct intel_display *display = to_intel_display(encoder);
enum phy phy = intel_encoder_to_phy(encoder);
@@ -1618,7 +1618,7 @@ static void rkl_ddi_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(encoder);
- const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ const struct intel_dpll_global *pll = crtc_state->dpll_global;
enum phy phy = intel_encoder_to_phy(encoder);
if (drm_WARN_ON(display->drm, !pll))
@@ -1648,7 +1648,7 @@ static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder)
RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
}
-static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder)
+static struct intel_dpll_global *rkl_ddi_get_pll(struct intel_encoder *encoder)
{
struct intel_display *display = to_intel_display(encoder);
enum phy phy = intel_encoder_to_phy(encoder);
@@ -1662,7 +1662,7 @@ static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(encoder);
- const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ const struct intel_dpll_global *pll = crtc_state->dpll_global;
enum phy phy = intel_encoder_to_phy(encoder);
if (drm_WARN_ON(display->drm, !pll))
@@ -1701,7 +1701,7 @@ static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder)
DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
}
-static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder)
+static struct intel_dpll_global *dg1_ddi_get_pll(struct intel_encoder *encoder)
{
struct intel_display *display = to_intel_display(encoder);
enum phy phy = intel_encoder_to_phy(encoder);
@@ -1728,7 +1728,7 @@ static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(encoder);
- const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ const struct intel_dpll_global *pll = crtc_state->dpll_global;
enum phy phy = intel_encoder_to_phy(encoder);
if (drm_WARN_ON(display->drm, !pll))
@@ -1758,7 +1758,7 @@ static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder)
ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
}
-struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder)
+struct intel_dpll_global *icl_ddi_combo_get_pll(struct intel_encoder *encoder)
{
struct intel_display *display = to_intel_display(encoder);
enum phy phy = intel_encoder_to_phy(encoder);
@@ -1772,7 +1772,7 @@ static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(encoder);
- const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ const struct intel_dpll_global *pll = crtc_state->dpll_global;
enum port port = encoder->port;
if (drm_WARN_ON(display->drm, !pll))
@@ -1815,7 +1815,7 @@ static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(encoder);
- const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ const struct intel_dpll_global *pll = crtc_state->dpll_global;
enum tc_port tc_port = intel_encoder_to_tc(encoder);
enum port port = encoder->port;
@@ -1866,7 +1866,7 @@ static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));
}
-static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder)
+static struct intel_dpll_global *icl_ddi_tc_get_pll(struct intel_encoder *encoder)
{
struct intel_display *display = to_intel_display(encoder);
enum tc_port tc_port = intel_encoder_to_tc(encoder);
@@ -1896,7 +1896,7 @@ static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encode
return intel_get_shared_dpll_by_id(display, id);
}
-static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
+static struct intel_dpll_global *bxt_ddi_get_pll(struct intel_encoder *encoder)
{
struct intel_display *display = to_intel_display(encoder->base.dev);
enum intel_dpll_id id;
@@ -1923,7 +1923,7 @@ static void skl_ddi_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(encoder);
- const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ const struct intel_dpll_global *pll = crtc_state->dpll_global;
enum port port = encoder->port;
if (drm_WARN_ON(display->drm, !pll))
@@ -1965,7 +1965,7 @@ static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder)
return !(intel_de_read(display, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port));
}
-static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder)
+static struct intel_dpll_global *skl_ddi_get_pll(struct intel_encoder *encoder)
{
struct intel_display *display = to_intel_display(encoder);
enum port port = encoder->port;
@@ -1991,7 +1991,7 @@ void hsw_ddi_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(encoder);
- const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ const struct intel_dpll_global *pll = crtc_state->dpll_global;
enum port port = encoder->port;
if (drm_WARN_ON(display->drm, !pll))
@@ -2016,7 +2016,7 @@ bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder)
return intel_de_read(display, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE;
}
-static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder)
+static struct intel_dpll_global *hsw_ddi_get_pll(struct intel_encoder *encoder)
{
struct intel_display *display = to_intel_display(encoder);
enum port port = encoder->port;
@@ -4184,7 +4184,7 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
void intel_ddi_get_clock(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
- struct intel_shared_dpll *pll)
+ struct intel_dpll_global *pll)
{
struct intel_display *display = to_intel_display(encoder);
enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
@@ -4200,7 +4200,7 @@ void intel_ddi_get_clock(struct intel_encoder *encoder,
icl_set_active_port_dpll(crtc_state, port_dpll_id);
- crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->shared_dpll,
+ crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->dpll_global,
&crtc_state->dpll_hw_state);
}
@@ -4254,7 +4254,7 @@ static void icl_ddi_combo_get_config(struct intel_encoder *encoder,
intel_ddi_get_config(encoder, crtc_state);
}
-static bool icl_ddi_tc_pll_is_tbt(const struct intel_shared_dpll *pll)
+static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll_global *pll)
{
return pll->info->id == DPLL_ID_ICL_TBTPLL;
}
@@ -4264,7 +4264,7 @@ icl_ddi_tc_port_pll_type(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(encoder);
- const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ const struct intel_dpll_global *pll = crtc_state->dpll_global;
if (drm_WARN_ON(display->drm, !pll))
return ICL_PORT_DPLL_DEFAULT;
@@ -4287,7 +4287,7 @@ intel_ddi_port_pll_type(struct intel_encoder *encoder,
static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
- struct intel_shared_dpll *pll)
+ struct intel_dpll_global *pll)
{
struct intel_display *display = to_intel_display(encoder);
enum icl_port_dpll_id port_dpll_id;
@@ -4310,10 +4310,10 @@ static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
icl_set_active_port_dpll(crtc_state, port_dpll_id);
- if (icl_ddi_tc_pll_is_tbt(crtc_state->shared_dpll))
+ if (icl_ddi_tc_pll_is_tbt(crtc_state->dpll_global))
crtc_state->port_clock = icl_calc_tbt_pll_link(display, encoder->port);
else
- crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->shared_dpll,
+ crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->dpll_global,
&crtc_state->dpll_hw_state);
}
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h
index 353eb04079e9..c41341b7e5cf 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi.h
@@ -18,7 +18,7 @@ struct intel_display;
struct intel_dp;
struct intel_dpll_hw_state;
struct intel_encoder;
-struct intel_shared_dpll;
+struct intel_dpll_global;
enum pipe;
enum port;
enum transcoder;
@@ -40,7 +40,7 @@ void intel_ddi_enable_clock(struct intel_encoder *encoder,
void intel_ddi_disable_clock(struct intel_encoder *encoder);
void intel_ddi_get_clock(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
- struct intel_shared_dpll *pll);
+ struct intel_dpll_global *pll);
void hsw_ddi_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void hsw_ddi_disable_clock(struct intel_encoder *encoder);
@@ -50,7 +50,7 @@ intel_ddi_port_pll_type(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void hsw_ddi_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state);
-struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder);
+struct intel_dpll_global *icl_ddi_combo_get_pll(struct intel_encoder *encoder);
void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void intel_wait_ddi_buf_idle(struct intel_display *display, enum port port);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c540e2cae1f0..5b808bad61e0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1322,7 +1322,7 @@ static void intel_encoders_update_prepare(struct intel_atomic_state *state)
if (intel_crtc_needs_modeset(new_crtc_state))
continue;
- new_crtc_state->shared_dpll = old_crtc_state->shared_dpll;
+ new_crtc_state->dpll_global = old_crtc_state->dpll_global;
new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state;
}
}
@@ -1661,7 +1661,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
intel_encoders_pre_pll_enable(state, crtc);
- if (new_crtc_state->shared_dpll)
+ if (new_crtc_state->dpll_global)
intel_enable_shared_dpll(new_crtc_state);
intel_encoders_pre_enable(state, crtc);
@@ -1957,7 +1957,7 @@ static void get_crtc_power_domains(struct intel_crtc_state *crtc_state,
if (HAS_DDI(display) && crtc_state->has_audio)
set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits);
- if (crtc_state->shared_dpll)
+ if (crtc_state->dpll_global)
set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits);
if (crtc_state->dsc.compression_enable)
@@ -4498,7 +4498,7 @@ copy_joiner_crtc_state_modeset(struct intel_atomic_state *state,
/* preserve some things from the slave's original crtc state */
saved_state->uapi = secondary_crtc_state->uapi;
saved_state->scaler_state = secondary_crtc_state->scaler_state;
- saved_state->shared_dpll = secondary_crtc_state->shared_dpll;
+ saved_state->dpll_global = secondary_crtc_state->dpll_global;
saved_state->crc_enabled = secondary_crtc_state->crc_enabled;
intel_crtc_free_hw_state(secondary_crtc_state);
@@ -4561,7 +4561,7 @@ intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
saved_state->uapi = crtc_state->uapi;
saved_state->inherited = crtc_state->inherited;
saved_state->scaler_state = crtc_state->scaler_state;
- saved_state->shared_dpll = crtc_state->shared_dpll;
+ saved_state->dpll_global = crtc_state->dpll_global;
saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
sizeof(saved_state->icl_port_dplls));
@@ -5313,7 +5313,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_BOOL(double_wide);
if (display->dpll.mgr)
- PIPE_CONF_CHECK_P(shared_dpll);
+ PIPE_CONF_CHECK_P(dpll_global);
/* FIXME convert everything over the dpll_mgr */
if (display->dpll.mgr || HAS_GMCH(display))
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 3673275f9061..b23ff1c34bdf 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -126,8 +126,8 @@ struct intel_audio {
struct intel_dpll {
struct mutex lock;
- int num_shared_dpll;
- struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
+ int num_dpll_global;
+ struct intel_dpll_global dpll_globals[I915_NUM_PLLS];
const struct intel_dpll_mgr *mgr;
struct {
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index a317c6646382..db26998e0baa 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -625,7 +625,7 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
{
struct intel_display *display = node_to_intel_display(m->private);
struct drm_printer p = drm_seq_file_printer(m);
- struct intel_shared_dpll *pll;
+ struct intel_dpll_global *pll;
int i;
drm_modeset_lock_all(display->drm);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 7d1c64f7b405..e080ffb32546 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1075,8 +1075,8 @@ struct intel_crtc_state {
* haswell. */
struct dpll dpll;
- /* Selected dpll when shared or NULL. */
- struct intel_shared_dpll *shared_dpll;
+ /* Selected dpll. */
+ struct intel_dpll_global *dpll_global;
/* Actual register state of the dpll, for shared dpll cross-checking. */
struct intel_dpll_hw_state dpll_hw_state;
@@ -1086,7 +1086,7 @@ struct intel_crtc_state {
* setting shared_dpll and dpll_hw_state to one of these reserved ones.
*/
struct icl_port_dpll {
- struct intel_shared_dpll *pll;
+ struct intel_dpll_global *pll;
struct intel_dpll_hw_state hw_state;
} icl_port_dplls[ICL_PORT_DPLL_COUNT];
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 0481b1365b85..c6d29382378b 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1770,9 +1770,9 @@ int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
int ret;
drm_WARN_ON(display->drm, !intel_crtc_needs_modeset(crtc_state));
- drm_WARN_ON(display->drm, !crtc_state->hw.enable && crtc_state->shared_dpll);
+ drm_WARN_ON(display->drm, !crtc_state->hw.enable && crtc_state->dpll_global);
- if (!crtc_state->hw.enable || crtc_state->shared_dpll)
+ if (!crtc_state->hw.enable || crtc_state->dpll_global)
return 0;
if (!display->funcs.dpll->crtc_get_shared_dpll)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 92ca2a544e2f..833c90f3f0f1 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -67,7 +67,7 @@ struct intel_dpll_global_funcs {
* the pll is not already enabled.
*/
void (*enable)(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll_global *pll,
const struct intel_dpll_hw_state *dpll_hw_state);
/*
@@ -76,7 +76,7 @@ struct intel_dpll_global_funcs {
* tracked users for it.
*/
void (*disable)(struct intel_display *display,
- struct intel_shared_dpll *pll);
+ struct intel_dpll_global *pll);
/*
* Hook for reading the values currently programmed to the DPLL
@@ -84,7 +84,7 @@ struct intel_dpll_global_funcs {
* verification after a mode set.
*/
bool (*get_hw_state)(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll_global *pll,
struct intel_dpll_hw_state *dpll_hw_state);
/*
@@ -92,7 +92,7 @@ struct intel_dpll_global_funcs {
* in state.
*/
int (*get_freq)(struct intel_display *i915,
- const struct intel_shared_dpll *pll,
+ const struct intel_dpll_global *pll,
const struct intel_dpll_hw_state *dpll_hw_state);
};
@@ -121,7 +121,7 @@ static void
intel_atomic_duplicate_dpll_state(struct intel_display *display,
struct intel_dpll_state *dpll_state)
{
- struct intel_shared_dpll *pll;
+ struct intel_dpll_global *pll;
int i;
/* Copy dpll state */
@@ -155,11 +155,11 @@ intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
* Returns:
* A pointer to the DPLL with @id
*/
-struct intel_shared_dpll *
+struct intel_dpll_global *
intel_get_shared_dpll_by_id(struct intel_display *display,
enum intel_dpll_id id)
{
- struct intel_shared_dpll *pll;
+ struct intel_dpll_global *pll;
int i;
for_each_dpll(display, pll, i) {
@@ -173,7 +173,7 @@ intel_get_shared_dpll_by_id(struct intel_display *display,
/* For ILK+ */
void assert_shared_dpll(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll_global *pll,
bool state)
{
bool cur_state;
@@ -202,7 +202,7 @@ enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port)
static i915_reg_t
intel_combo_pll_enable_reg(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_dpll_global *pll)
{
if (display->platform.dg1)
return DG1_DPLL_ENABLE(pll->info->id);
@@ -215,7 +215,7 @@ intel_combo_pll_enable_reg(struct intel_display *display,
static i915_reg_t
intel_tc_pll_enable_reg(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_dpll_global *pll)
{
const enum intel_dpll_id id = pll->info->id;
enum tc_port tc_port = icl_pll_id_to_tc_port(id);
@@ -227,7 +227,7 @@ intel_tc_pll_enable_reg(struct intel_display *display,
}
static void _intel_enable_shared_dpll(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_dpll_global *pll)
{
if (pll->info->power_domain)
pll->wakeref = intel_display_power_get(display, pll->info->power_domain);
@@ -237,7 +237,7 @@ static void _intel_enable_shared_dpll(struct intel_display *display,
}
static void _intel_disable_shared_dpll(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_dpll_global *pll)
{
pll->info->funcs->disable(display, pll);
pll->on = false;
@@ -256,7 +256,7 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ struct intel_dpll_global *pll = crtc_state->dpll_global;
unsigned int pipe_mask = intel_crtc_joined_pipe_mask(crtc_state);
unsigned int old_mask;
@@ -302,7 +302,7 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ struct intel_dpll_global *pll = crtc_state->dpll_global;
unsigned int pipe_mask = intel_crtc_joined_pipe_mask(crtc_state);
/* PCH only available on ILK+ */
@@ -341,7 +341,7 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
static unsigned long
intel_dpll_mask_all(struct intel_display *display)
{
- struct intel_shared_dpll *pll;
+ struct intel_dpll_global *pll;
unsigned long dpll_mask = 0;
int i;
@@ -354,7 +354,7 @@ intel_dpll_mask_all(struct intel_display *display)
return dpll_mask;
}
-static struct intel_shared_dpll *
+static struct intel_dpll_global *
intel_find_shared_dpll(struct intel_atomic_state *state,
const struct intel_crtc *crtc,
const struct intel_dpll_hw_state *dpll_hw_state,
@@ -363,7 +363,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
struct intel_display *display = to_intel_display(crtc);
unsigned long dpll_mask_all = intel_dpll_mask_all(display);
struct intel_dpll_state *dpll_state;
- struct intel_shared_dpll *unused_pll = NULL;
+ struct intel_dpll_global *unused_pll = NULL;
enum intel_dpll_id id;
dpll_state = intel_atomic_get_shared_dpll_state(&state->base);
@@ -371,7 +371,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
drm_WARN_ON(display->drm, dpll_mask & ~dpll_mask_all);
for_each_set_bit(id, &dpll_mask, fls(dpll_mask_all)) {
- struct intel_shared_dpll *pll;
+ struct intel_dpll_global *pll;
pll = intel_get_shared_dpll_by_id(display, id);
if (!pll)
@@ -418,7 +418,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
*/
static void
intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc,
- const struct intel_shared_dpll *pll,
+ const struct intel_dpll_global *pll,
struct intel_dpll_state *dpll_state)
{
struct intel_display *display = to_intel_display(crtc);
@@ -434,7 +434,7 @@ intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc,
static void
intel_reference_shared_dpll(struct intel_atomic_state *state,
const struct intel_crtc *crtc,
- const struct intel_shared_dpll *pll,
+ const struct intel_dpll_global *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
struct intel_dpll_state *dpll_state;
@@ -457,7 +457,7 @@ intel_reference_shared_dpll(struct intel_atomic_state *state,
*/
void
intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
- const struct intel_shared_dpll *pll,
+ const struct intel_dpll_global *pll,
struct intel_dpll_state *dpll_state)
{
struct intel_display *display = to_intel_display(crtc);
@@ -472,7 +472,7 @@ intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
static void intel_unreference_shared_dpll(struct intel_atomic_state *state,
const struct intel_crtc *crtc,
- const struct intel_shared_dpll *pll)
+ const struct intel_dpll_global *pll)
{
struct intel_dpll_state *dpll_state;
@@ -489,12 +489,12 @@ static void intel_put_dpll(struct intel_atomic_state *state,
struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- new_crtc_state->shared_dpll = NULL;
+ new_crtc_state->dpll_global = NULL;
- if (!old_crtc_state->shared_dpll)
+ if (!old_crtc_state->dpll_global)
return;
- intel_unreference_shared_dpll(state, crtc, old_crtc_state->shared_dpll);
+ intel_unreference_shared_dpll(state, crtc, old_crtc_state->dpll_global);
}
/**
@@ -512,7 +512,7 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
{
struct intel_display *display = to_intel_display(state);
struct intel_dpll_state *dpll_state = state->dpll_state;
- struct intel_shared_dpll *pll;
+ struct intel_dpll_global *pll;
int i;
if (!state->dpll_set)
@@ -523,7 +523,7 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
}
static bool ibx_pch_dpll_get_hw_state(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll_global *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx;
@@ -559,7 +559,7 @@ static void ibx_assert_pch_refclk_enabled(struct intel_display *display)
}
static void ibx_pch_dpll_enable(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll_global *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx;
@@ -588,7 +588,7 @@ static void ibx_pch_dpll_enable(struct intel_display *display,
}
static void ibx_pch_dpll_disable(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_dpll_global *pll)
{
const enum intel_dpll_id id = pll->info->id;
@@ -612,7 +612,7 @@ static int ibx_get_dpll(struct intel_atomic_state *state,
struct drm_i915_private *i915 = to_i915(display->drm);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- struct intel_shared_dpll *pll;
+ struct intel_dpll_global *pll;
enum intel_dpll_id id;
if (HAS_PCH_IBX(i915)) {
@@ -638,7 +638,7 @@ static int ibx_get_dpll(struct intel_atomic_state *state,
intel_reference_shared_dpll(state, crtc,
pll, &crtc_state->dpll_hw_state);
- crtc_state->shared_dpll = pll;
+ crtc_state->dpll_global = pll;
return 0;
}
@@ -690,7 +690,7 @@ static const struct intel_dpll_mgr pch_pll_mgr = {
};
static void hsw_ddi_wrpll_enable(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll_global *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
@@ -702,7 +702,7 @@ static void hsw_ddi_wrpll_enable(struct intel_display *display,
}
static void hsw_ddi_spll_enable(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll_global *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
@@ -713,7 +713,7 @@ static void hsw_ddi_spll_enable(struct intel_display *display,
}
static void hsw_ddi_wrpll_disable(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_dpll_global *pll)
{
const enum intel_dpll_id id = pll->info->id;
@@ -729,7 +729,7 @@ static void hsw_ddi_wrpll_disable(struct intel_display *display,
}
static void hsw_ddi_spll_disable(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_dpll_global *pll)
{
enum intel_dpll_id id = pll->info->id;
@@ -745,7 +745,7 @@ static void hsw_ddi_spll_disable(struct intel_display *display,
}
static bool hsw_ddi_wrpll_get_hw_state(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll_global *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
@@ -767,7 +767,7 @@ static bool hsw_ddi_wrpll_get_hw_state(struct intel_display *display,
}
static bool hsw_ddi_spll_get_hw_state(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll_global *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
@@ -994,7 +994,7 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */,
}
static int hsw_ddi_wrpll_get_freq(struct intel_display *display,
- const struct intel_shared_dpll *pll,
+ const struct intel_dpll_global *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
@@ -1057,7 +1057,7 @@ hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state,
return 0;
}
-static struct intel_shared_dpll *
+static struct intel_dpll_global *
hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
@@ -1088,11 +1088,11 @@ hsw_ddi_lcpll_compute_dpll(struct intel_crtc_state *crtc_state)
}
}
-static struct intel_shared_dpll *
+static struct intel_dpll_global *
hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
- struct intel_shared_dpll *pll;
+ struct intel_dpll_global *pll;
enum intel_dpll_id pll_id;
int clock = crtc_state->port_clock;
@@ -1120,7 +1120,7 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
}
static int hsw_ddi_lcpll_get_freq(struct intel_display *display,
- const struct intel_shared_dpll *pll,
+ const struct intel_dpll_global *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
int link_clock = 0;
@@ -1160,7 +1160,7 @@ hsw_ddi_spll_compute_dpll(struct intel_atomic_state *state,
return 0;
}
-static struct intel_shared_dpll *
+static struct intel_dpll_global *
hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
@@ -1172,7 +1172,7 @@ hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
}
static int hsw_ddi_spll_get_freq(struct intel_display *display,
- const struct intel_shared_dpll *pll,
+ const struct intel_dpll_global *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
@@ -1219,7 +1219,7 @@ static int hsw_get_dpll(struct intel_atomic_state *state,
{
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- struct intel_shared_dpll *pll = NULL;
+ struct intel_dpll_global *pll = NULL;
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
pll = hsw_ddi_wrpll_get_dpll(state, crtc);
@@ -1234,7 +1234,7 @@ static int hsw_get_dpll(struct intel_atomic_state *state,
intel_reference_shared_dpll(state, crtc,
pll, &crtc_state->dpll_hw_state);
- crtc_state->shared_dpll = pll;
+ crtc_state->dpll_global = pll;
return 0;
}
@@ -1283,18 +1283,18 @@ static const struct intel_dpll_global_funcs hsw_ddi_spll_funcs = {
};
static void hsw_ddi_lcpll_enable(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll_global *pll,
const struct intel_dpll_hw_state *hw_state)
{
}
static void hsw_ddi_lcpll_disable(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_dpll_global *pll)
{
}
static bool hsw_ddi_lcpll_get_hw_state(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll_global *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
return true;
@@ -1362,7 +1362,7 @@ static const struct skl_dpll_regs skl_dpll_regs[4] = {
};
static void skl_ddi_pll_write_ctrl1(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll_global *pll,
const struct skl_dpll_hw_state *hw_state)
{
const enum intel_dpll_id id = pll->info->id;
@@ -1376,7 +1376,7 @@ static void skl_ddi_pll_write_ctrl1(struct intel_display *display,
}
static void skl_ddi_pll_enable(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll_global *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
@@ -1398,7 +1398,7 @@ static void skl_ddi_pll_enable(struct intel_display *display,
}
static void skl_ddi_dpll0_enable(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll_global *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
@@ -1407,7 +1407,7 @@ static void skl_ddi_dpll0_enable(struct intel_display *display,
}
static void skl_ddi_pll_disable(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_dpll_global *pll)
{
const struct skl_dpll_regs *regs = skl_dpll_regs;
const enum intel_dpll_id id = pll->info->id;
@@ -1418,12 +1418,12 @@ static void skl_ddi_pll_disable(struct intel_display *display,
}
static void skl_ddi_dpll0_disable(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_dpll_global *pll)
{
}
static bool skl_ddi_pll_get_hw_state(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll_global *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
@@ -1461,7 +1461,7 @@ static bool skl_ddi_pll_get_hw_state(struct intel_display *display,
}
static bool skl_ddi_dpll0_get_hw_state(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll_global *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
@@ -1734,7 +1734,7 @@ skl_ddi_calculate_wrpll(int clock,
}
static int skl_ddi_wrpll_get_freq(struct intel_display *display,
- const struct intel_shared_dpll *pll,
+ const struct intel_dpll_global *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
@@ -1882,7 +1882,7 @@ skl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
}
static int skl_ddi_lcpll_get_freq(struct intel_display *display,
- const struct intel_shared_dpll *pll,
+ const struct intel_dpll_global *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
@@ -1937,7 +1937,7 @@ static int skl_get_dpll(struct intel_atomic_state *state,
{
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- struct intel_shared_dpll *pll;
+ struct intel_dpll_global *pll;
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
pll = intel_find_shared_dpll(state, crtc,
@@ -1955,13 +1955,13 @@ static int skl_get_dpll(struct intel_atomic_state *state,
intel_reference_shared_dpll(state, crtc,
pll, &crtc_state->dpll_hw_state);
- crtc_state->shared_dpll = pll;
+ crtc_state->dpll_global = pll;
return 0;
}
static int skl_ddi_pll_get_freq(struct intel_display *display,
- const struct intel_shared_dpll *pll,
+ const struct intel_dpll_global *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
@@ -2036,7 +2036,7 @@ static const struct intel_dpll_mgr skl_pll_mgr = {
};
static void bxt_ddi_pll_enable(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll_global *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
@@ -2139,7 +2139,7 @@ static void bxt_ddi_pll_enable(struct intel_display *display,
}
static void bxt_ddi_pll_disable(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_dpll_global *pll)
{
enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
@@ -2158,7 +2158,7 @@ static void bxt_ddi_pll_disable(struct intel_display *display,
}
static bool bxt_ddi_pll_get_hw_state(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll_global *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
@@ -2358,7 +2358,7 @@ static int bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
}
static int bxt_ddi_pll_get_freq(struct intel_display *display,
- const struct intel_shared_dpll *pll,
+ const struct intel_dpll_global *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
@@ -2427,7 +2427,7 @@ static int bxt_get_dpll(struct intel_atomic_state *state,
struct intel_display *display = to_intel_display(state);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- struct intel_shared_dpll *pll;
+ struct intel_dpll_global *pll;
enum intel_dpll_id id;
/* 1:1 mapping between ports and PLLs */
@@ -2440,7 +2440,7 @@ static int bxt_get_dpll(struct intel_atomic_state *state,
intel_reference_shared_dpll(state, crtc,
pll, &crtc_state->dpll_hw_state);
- crtc_state->shared_dpll = pll;
+ crtc_state->dpll_global = pll;
return 0;
}
@@ -2755,7 +2755,7 @@ static int icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
}
static int icl_ddi_tbt_pll_get_freq(struct intel_display *display,
- const struct intel_shared_dpll *pll,
+ const struct intel_dpll_global *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
/*
@@ -2826,7 +2826,7 @@ icl_calc_wrpll(struct intel_crtc_state *crtc_state,
}
static int icl_ddi_combo_pll_get_freq(struct intel_display *display,
- const struct intel_shared_dpll *pll,
+ const struct intel_dpll_global *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
@@ -3199,7 +3199,7 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
}
static int icl_ddi_mg_pll_get_freq(struct intel_display *display,
- const struct intel_shared_dpll *pll,
+ const struct intel_dpll_global *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
@@ -3285,7 +3285,7 @@ void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
struct icl_port_dpll *port_dpll =
&crtc_state->icl_port_dplls[port_dpll_id];
- crtc_state->shared_dpll = port_dpll->pll;
+ crtc_state->dpll_global = port_dpll->pll;
crtc_state->dpll_hw_state = port_dpll->hw_state;
}
@@ -3428,8 +3428,8 @@ static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state,
return ret;
/* this is mainly for the fastset check */
- if (old_crtc_state->shared_dpll &&
- old_crtc_state->shared_dpll->info->id == DPLL_ID_ICL_TBTPLL)
+ if (old_crtc_state->dpll_global &&
+ old_crtc_state->dpll_global->info->id == DPLL_ID_ICL_TBTPLL)
icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);
else
icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_MG_PHY);
@@ -3521,7 +3521,7 @@ static void icl_put_dplls(struct intel_atomic_state *state,
intel_atomic_get_new_crtc_state(state, crtc);
enum icl_port_dpll_id id;
- new_crtc_state->shared_dpll = NULL;
+ new_crtc_state->dpll_global = NULL;
for (id = ICL_PORT_DPLL_DEFAULT; id < ICL_PORT_DPLL_COUNT; id++) {
const struct icl_port_dpll *old_port_dpll =
@@ -3539,7 +3539,7 @@ static void icl_put_dplls(struct intel_atomic_state *state,
}
static bool mg_pll_get_hw_state(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll_global *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
@@ -3606,7 +3606,7 @@ static bool mg_pll_get_hw_state(struct intel_display *display,
}
static bool dkl_pll_get_hw_state(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll_global *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
@@ -3678,7 +3678,7 @@ static bool dkl_pll_get_hw_state(struct intel_display *display,
}
static bool icl_pll_get_hw_state(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll_global *pll,
struct intel_dpll_hw_state *dpll_hw_state,
i915_reg_t enable_reg)
{
@@ -3739,7 +3739,7 @@ static bool icl_pll_get_hw_state(struct intel_display *display,
}
static bool combo_pll_get_hw_state(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll_global *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
@@ -3748,14 +3748,14 @@ static bool combo_pll_get_hw_state(struct intel_display *display,
}
static bool tbt_pll_get_hw_state(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll_global *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
return icl_pll_get_hw_state(display, pll, dpll_hw_state, TBT_PLL_ENABLE);
}
static void icl_dpll_write(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll_global *pll,
const struct icl_dpll_hw_state *hw_state)
{
const enum intel_dpll_id id = pll->info->id;
@@ -3797,7 +3797,7 @@ static void icl_dpll_write(struct intel_display *display,
}
static void icl_mg_pll_write(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll_global *pll,
const struct icl_dpll_hw_state *hw_state)
{
enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);
@@ -3840,7 +3840,7 @@ static void icl_mg_pll_write(struct intel_display *display,
}
static void dkl_pll_write(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll_global *pll,
const struct icl_dpll_hw_state *hw_state)
{
enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);
@@ -3905,7 +3905,7 @@ static void dkl_pll_write(struct intel_display *display,
}
static void icl_pll_power_enable(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll_global *pll,
i915_reg_t enable_reg)
{
intel_de_rmw(display, enable_reg, 0, PLL_POWER_ENABLE);
@@ -3920,7 +3920,7 @@ static void icl_pll_power_enable(struct intel_display *display,
}
static void icl_pll_enable(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll_global *pll,
i915_reg_t enable_reg)
{
intel_de_rmw(display, enable_reg, 0, PLL_ENABLE);
@@ -3930,7 +3930,7 @@ static void icl_pll_enable(struct intel_display *display,
drm_err(display->drm, "PLL %d not locked\n", pll->info->id);
}
-static void adlp_cmtg_clock_gating_wa(struct intel_display *display, struct intel_shared_dpll *pll)
+static void adlp_cmtg_clock_gating_wa(struct intel_display *display, struct intel_dpll_global *pll)
{
u32 val;
@@ -3955,7 +3955,7 @@ static void adlp_cmtg_clock_gating_wa(struct intel_display *display, struct inte
}
static void combo_pll_enable(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll_global *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
@@ -3979,7 +3979,7 @@ static void combo_pll_enable(struct intel_display *display,
}
static void tbt_pll_enable(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll_global *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
@@ -4000,7 +4000,7 @@ static void tbt_pll_enable(struct intel_display *display,
}
static void mg_pll_enable(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll_global *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
@@ -4025,7 +4025,7 @@ static void mg_pll_enable(struct intel_display *display,
}
static void icl_pll_disable(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll_global *pll,
i915_reg_t enable_reg)
{
/* The first steps are done by intel_ddi_post_disable(). */
@@ -4056,7 +4056,7 @@ static void icl_pll_disable(struct intel_display *display,
}
static void combo_pll_disable(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_dpll_global *pll)
{
i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
@@ -4064,13 +4064,13 @@ static void combo_pll_disable(struct intel_display *display,
}
static void tbt_pll_disable(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_dpll_global *pll)
{
icl_pll_disable(display, pll, TBT_PLL_ENABLE);
}
static void mg_pll_disable(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_dpll_global *pll)
{
i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
@@ -4347,19 +4347,19 @@ void intel_shared_dpll_init(struct intel_display *display)
for (i = 0; dpll_info[i].name; i++) {
if (drm_WARN_ON(display->drm,
- i >= ARRAY_SIZE(display->dpll.shared_dplls)))
+ i >= ARRAY_SIZE(display->dpll.dpll_globals)))
break;
/* must fit into unsigned long bitmask on 32bit */
if (drm_WARN_ON(display->drm, dpll_info[i].id >= 32))
break;
- display->dpll.shared_dplls[i].info = &dpll_info[i];
- display->dpll.shared_dplls[i].index = i;
+ display->dpll.dpll_globals[i].info = &dpll_info[i];
+ display->dpll.dpll_globals[i].index = i;
}
display->dpll.mgr = dpll_mgr;
- display->dpll.num_shared_dpll = i;
+ display->dpll.num_dpll_global = i;
}
/**
@@ -4483,7 +4483,7 @@ void intel_update_active_dpll(struct intel_atomic_state *state,
* Return the output frequency corresponding to @pll's passed in @dpll_hw_state.
*/
int intel_dpll_get_freq(struct intel_display *display,
- const struct intel_shared_dpll *pll,
+ const struct intel_dpll_global *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
if (drm_WARN_ON(display->drm, !pll->info->funcs->get_freq))
@@ -4501,14 +4501,14 @@ int intel_dpll_get_freq(struct intel_display *display,
* Read out @pll's hardware state into @dpll_hw_state.
*/
bool intel_dpll_get_hw_state(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll_global *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
return pll->info->funcs->get_hw_state(display, pll, dpll_hw_state);
}
static void readout_dpll_hw_state(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_dpll_global *pll)
{
struct intel_crtc *crtc;
@@ -4522,7 +4522,7 @@ static void readout_dpll_hw_state(struct intel_display *display,
struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
- if (crtc_state->hw.active && crtc_state->shared_dpll == pll)
+ if (crtc_state->hw.active && crtc_state->dpll_global == pll)
intel_reference_shared_dpll_crtc(crtc, pll, &pll->state);
}
pll->active_mask = pll->state.pipe_mask;
@@ -4540,7 +4540,7 @@ void intel_dpll_update_ref_clks(struct intel_display *display)
void intel_dpll_readout_hw_state(struct intel_display *display)
{
- struct intel_shared_dpll *pll;
+ struct intel_dpll_global *pll;
int i;
for_each_dpll(display, pll, i)
@@ -4548,7 +4548,7 @@ void intel_dpll_readout_hw_state(struct intel_display *display)
}
static void sanitize_dpll_state(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_dpll_global *pll)
{
if (!pll->on)
return;
@@ -4567,7 +4567,7 @@ static void sanitize_dpll_state(struct intel_display *display,
void intel_dpll_sanitize_state(struct intel_display *display)
{
- struct intel_shared_dpll *pll;
+ struct intel_dpll_global *pll;
int i;
intel_cx0_pll_power_save_wa(display);
@@ -4624,7 +4624,7 @@ bool intel_dpll_compare_hw_state(struct intel_display *display,
static void
verify_single_dpll_state(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll_global *pll,
struct intel_crtc *crtc,
const struct intel_crtc_state *new_crtc_state)
{
@@ -4677,8 +4677,8 @@ verify_single_dpll_state(struct intel_display *display,
pll->info->name);
}
-static bool has_alt_port_dpll(const struct intel_shared_dpll *old_pll,
- const struct intel_shared_dpll *new_pll)
+static bool has_alt_port_dpll(const struct intel_dpll_global *old_pll,
+ const struct intel_dpll_global *new_pll)
{
return old_pll && new_pll && old_pll != new_pll &&
(old_pll->info->is_alt_port_dpll || new_pll->info->is_alt_port_dpll);
@@ -4693,22 +4693,22 @@ void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
const struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- if (new_crtc_state->shared_dpll)
- verify_single_dpll_state(display, new_crtc_state->shared_dpll,
+ if (new_crtc_state->dpll_global)
+ verify_single_dpll_state(display, new_crtc_state->dpll_global,
crtc, new_crtc_state);
- if (old_crtc_state->shared_dpll &&
- old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {
+ if (old_crtc_state->dpll_global &&
+ old_crtc_state->dpll_global != new_crtc_state->dpll_global) {
u8 pipe_mask = BIT(crtc->pipe);
- struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
+ struct intel_dpll_global *pll = old_crtc_state->dpll_global;
INTEL_DISPLAY_STATE_WARN(display, pll->active_mask & pipe_mask,
"%s: pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n",
pll->info->name, pipe_name(crtc->pipe), pll->active_mask);
/* TC ports have both MG/TC and TBT PLL referenced simultaneously */
- INTEL_DISPLAY_STATE_WARN(display, !has_alt_port_dpll(old_crtc_state->shared_dpll,
- new_crtc_state->shared_dpll) &&
+ INTEL_DISPLAY_STATE_WARN(display, !has_alt_port_dpll(old_crtc_state->dpll_global,
+ new_crtc_state->dpll_global) &&
pll->state.pipe_mask & pipe_mask,
"%s: pll enabled crtcs mismatch (found pipe %c in enabled mask (0x%x))\n",
pll->info->name, pipe_name(crtc->pipe), pll->state.pipe_mask);
@@ -4718,7 +4718,7 @@ void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state)
{
struct intel_display *display = to_intel_display(state);
- struct intel_shared_dpll *pll;
+ struct intel_dpll_global *pll;
int i;
for_each_dpll(display, pll, i)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 2080118be523..bd52e30d83bd 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -31,8 +31,8 @@
#include "intel_wakeref.h"
#define for_each_dpll(__display, __pll, __i) \
- for ((__i) = 0; (__i) < (__display)->dpll.num_shared_dpll && \
- ((__pll) = &(__display)->dpll.shared_dplls[(__i)]) ; (__i)++)
+ for ((__i) = 0; (__i) < (__display)->dpll.num_dpll_global && \
+ ((__pll) = &(__display)->dpll.dpll_globals[(__i)]) ; (__i)++)
enum tc_port;
struct drm_printer;
@@ -344,9 +344,9 @@ struct dpll_info {
};
/**
- * struct intel_shared_dpll - display PLL with tracked state and users
+ * struct intel_dpll_global - display PLL with tracked state and users
*/
-struct intel_shared_dpll {
+struct intel_dpll_global {
/**
* @state:
*
@@ -388,11 +388,11 @@ struct intel_shared_dpll {
#define SKL_DPLL3 3
/* shared dpll functions */
-struct intel_shared_dpll *
+struct intel_dpll_global *
intel_get_shared_dpll_by_id(struct intel_display *display,
enum intel_dpll_id id);
void assert_shared_dpll(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll_global *pll,
bool state);
#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
@@ -405,7 +405,7 @@ int intel_reserve_shared_dplls(struct intel_atomic_state *state,
void intel_release_shared_dplls(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
- const struct intel_shared_dpll *pll,
+ const struct intel_dpll_global *pll,
struct intel_dpll_state *shared_dpll_state);
void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
enum icl_port_dpll_id port_dpll_id);
@@ -413,10 +413,10 @@ void intel_update_active_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder);
int intel_dpll_get_freq(struct intel_display *display,
- const struct intel_shared_dpll *pll,
+ const struct intel_dpll_global *pll,
const struct intel_dpll_hw_state *dpll_hw_state);
bool intel_dpll_get_hw_state(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll_global *pll,
struct intel_dpll_hw_state *dpll_hw_state);
void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index 40deee0769ae..acc0b45eced0 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -911,7 +911,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
intel_de_write(display, FDI_RX_CTL(PIPE_A), rx_ctl_val);
/* Configure Port Clock Select */
- drm_WARN_ON(display->drm, crtc_state->shared_dpll->info->id != DPLL_ID_SPLL);
+ drm_WARN_ON(display->drm, crtc_state->dpll_global->info->id != DPLL_ID_SPLL);
intel_ddi_enable_clock(encoder, crtc_state);
/* Start the training iterating through available voltages and emphasis,
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
index 89d26913e253..bc8725aa99da 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -251,7 +251,7 @@ static void intel_pre_enable_lvds(struct intel_atomic_state *state,
if (HAS_PCH_SPLIT(i915)) {
assert_fdi_rx_pll_disabled(display, pipe);
- assert_shared_dpll_disabled(display, crtc_state->shared_dpll);
+ assert_shared_dpll_disabled(display, crtc_state->dpll_global);
} else {
assert_pll_disabled(display, pipe);
}
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index 3cc915739677..427eff400b53 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -91,10 +91,10 @@ static void intel_crtc_disable_noatomic_begin(struct intel_crtc *crtc,
crtc->active = false;
crtc->base.enabled = false;
- if (crtc_state->shared_dpll)
+ if (crtc_state->dpll_global)
intel_unreference_shared_dpll_crtc(crtc,
- crtc_state->shared_dpll,
- &crtc_state->shared_dpll->state);
+ crtc_state->dpll_global,
+ &crtc_state->dpll_global->state);
}
static void set_encoder_for_connector(struct intel_connector *connector,
@@ -568,7 +568,7 @@ static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
*/
return IS_SANDYBRIDGE(i915) &&
crtc_state->hw.active &&
- crtc_state->shared_dpll &&
+ crtc_state->dpll_global &&
crtc_state->port_clock == 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index b909ed18a5b2..57303ecb77ad 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -255,7 +255,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
u32 val, pipeconf_val;
/* Make sure PCH DPLL is enabled */
- assert_shared_dpll_enabled(display, crtc_state->shared_dpll);
+ assert_shared_dpll_enabled(display, crtc_state->dpll_global);
/* FDI must be feeding us bits for PCH ports */
assert_fdi_tx_enabled(display, pipe);
@@ -387,7 +387,7 @@ void ilk_pch_enable(struct intel_atomic_state *state,
temp = intel_de_read(display, PCH_DPLL_SEL);
temp |= TRANS_DPLL_ENABLE(pipe);
sel = TRANS_DPLLB_SEL(pipe);
- if (crtc_state->shared_dpll ==
+ if (crtc_state->dpll_global ==
intel_get_shared_dpll_by_id(display, DPLL_ID_PCH_PLL_B))
temp |= sel;
else
@@ -504,7 +504,7 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- struct intel_shared_dpll *pll;
+ struct intel_dpll_global *pll;
enum pipe pipe = crtc->pipe;
enum intel_dpll_id pll_id;
bool pll_active;
@@ -536,8 +536,8 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
pll_id = DPLL_ID_PCH_PLL_A;
}
- crtc_state->shared_dpll = intel_get_shared_dpll_by_id(display, pll_id);
- pll = crtc_state->shared_dpll;
+ crtc_state->dpll_global = intel_get_shared_dpll_by_id(display, pll_id);
+ pll = crtc_state->dpll_global;
pll_active = intel_dpll_get_hw_state(display, pll,
&crtc_state->dpll_hw_state);
diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
index 611f3b8dffef..24e050d00db9 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
@@ -500,7 +500,7 @@ static void ilk_init_pch_refclk(struct intel_display *display)
{
struct drm_i915_private *dev_priv = to_i915(display->drm);
struct intel_encoder *encoder;
- struct intel_shared_dpll *pll;
+ struct intel_dpll_global *pll;
int i;
u32 val, final;
bool has_lvds = false;
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 05/16] drm/i915/dpll: Move away from using shared dpll
2025-04-02 8:31 [PATCH 00/16] DPLL framework redesign Suraj Kandpal
` (3 preceding siblings ...)
2025-04-02 8:31 ` [PATCH 04/16] drm/i915/dpll: Rename intel_shared_dpll Suraj Kandpal
@ 2025-04-02 8:31 ` Suraj Kandpal
2025-04-03 15:03 ` Jani Nikula
2025-04-02 8:31 ` [PATCH 06/16] drm/i915/dpll: Rename crtc_get_shared_dpll Suraj Kandpal
` (18 subsequent siblings)
23 siblings, 1 reply; 31+ messages in thread
From: Suraj Kandpal @ 2025-04-02 8:31 UTC (permalink / raw)
To: intel-xe, intel-gfx
Cc: ankit.k.nautiyal, uma.shankar, jani.nikula, mika.kahola,
ville.syrjala, Suraj Kandpal
Rename functions to move away from using shared dpll in the dpll
framework as much as possible since dpll may not always be shared.
--v2
-Use intel_dpll_global instead of global_dpll [Jani]
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 14 +-
drivers/gpu/drm/i915/display/intel_display.c | 8 +-
.../drm/i915/display/intel_display_driver.c | 2 +-
drivers/gpu/drm/i915/display/intel_dpll.c | 10 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 150 +++++++++---------
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 32 ++--
drivers/gpu/drm/i915/display/intel_lvds.c | 2 +-
.../drm/i915/display/intel_modeset_setup.c | 2 +-
.../drm/i915/display/intel_modeset_verify.c | 4 +-
.../gpu/drm/i915/display/intel_pch_display.c | 14 +-
10 files changed, 119 insertions(+), 119 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index a8934ea5077d..3fe330bf2636 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1567,7 +1567,7 @@ _icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg,
id = (intel_de_read(display, reg) & clk_sel_mask) >> clk_sel_shift;
- return intel_get_shared_dpll_by_id(display, id);
+ return intel_get_dpll_global_by_id(display, id);
}
static void adls_ddi_enable_clock(struct intel_encoder *encoder,
@@ -1721,7 +1721,7 @@ static struct intel_dpll_global *dg1_ddi_get_pll(struct intel_encoder *encoder)
if (phy >= PHY_C)
id += DPLL_ID_DG1_DPLL2;
- return intel_get_shared_dpll_by_id(display, id);
+ return intel_get_dpll_global_by_id(display, id);
}
static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
@@ -1893,7 +1893,7 @@ static struct intel_dpll_global *icl_ddi_tc_get_pll(struct intel_encoder *encode
return NULL;
}
- return intel_get_shared_dpll_by_id(display, id);
+ return intel_get_dpll_global_by_id(display, id);
}
static struct intel_dpll_global *bxt_ddi_get_pll(struct intel_encoder *encoder)
@@ -1916,7 +1916,7 @@ static struct intel_dpll_global *bxt_ddi_get_pll(struct intel_encoder *encoder)
return NULL;
}
- return intel_get_shared_dpll_by_id(display, id);
+ return intel_get_dpll_global_by_id(display, id);
}
static void skl_ddi_enable_clock(struct intel_encoder *encoder,
@@ -1984,7 +1984,7 @@ static struct intel_dpll_global *skl_ddi_get_pll(struct intel_encoder *encoder)
id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >>
DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port);
- return intel_get_shared_dpll_by_id(display, id);
+ return intel_get_dpll_global_by_id(display, id);
}
void hsw_ddi_enable_clock(struct intel_encoder *encoder,
@@ -2051,7 +2051,7 @@ static struct intel_dpll_global *hsw_ddi_get_pll(struct intel_encoder *encoder)
return NULL;
}
- return intel_get_shared_dpll_by_id(display, id);
+ return intel_get_dpll_global_by_id(display, id);
}
void intel_ddi_enable_clock(struct intel_encoder *encoder,
@@ -2758,7 +2758,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
* 4. Enable the port PLL.
*
* The PLL enabling itself was already done before this function by
- * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only
+ * hsw_crtc_enable()->intel_enable_dpll_global(). We need only
* configure the PLL to port mapping here.
*/
intel_ddi_enable_clock(encoder, crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 5b808bad61e0..904b9544515b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1662,7 +1662,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
intel_encoders_pre_pll_enable(state, crtc);
if (new_crtc_state->dpll_global)
- intel_enable_shared_dpll(new_crtc_state);
+ intel_enable_dpll_global(new_crtc_state);
intel_encoders_pre_enable(state, crtc);
@@ -1791,7 +1791,7 @@ static void hsw_crtc_disable(struct intel_atomic_state *state,
intel_encoders_disable(state, crtc);
intel_encoders_post_disable(state, crtc);
- intel_disable_shared_dpll(old_crtc_state);
+ intel_disable_dpll_global(old_crtc_state);
intel_encoders_post_pll_disable(state, crtc);
@@ -6429,7 +6429,7 @@ int intel_atomic_check(struct drm_device *dev,
any_ms = true;
- intel_release_shared_dplls(state, crtc);
+ intel_release_dpll_globals(state, crtc);
}
if (any_ms && !check_digital_port_conflicts(state)) {
@@ -7523,7 +7523,7 @@ static int intel_atomic_swap_state(struct intel_atomic_state *state)
intel_atomic_swap_global_state(state);
- intel_shared_dpll_swap_state(state);
+ intel_dpll_swap_state(state);
intel_atomic_track_fbs(state);
diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
index 4edadebad13b..b6c670c54eb1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_driver.c
+++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
@@ -441,7 +441,7 @@ int intel_display_driver_probe_nogem(struct intel_display *display)
}
intel_plane_possible_crtcs_init(display);
- intel_shared_dpll_init(display);
+ intel_dpll_global_init(display);
intel_fdi_pll_freq_update(display);
intel_update_czclk(display);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index c6d29382378b..04fb76a399ab 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1162,7 +1162,7 @@ static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
return 0;
- ret = intel_compute_shared_dplls(state, crtc, encoder);
+ ret = intel_compute_dpll_globals(state, crtc, encoder);
if (ret)
return ret;
@@ -1190,7 +1190,7 @@ static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state,
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
return 0;
- return intel_reserve_shared_dplls(state, crtc, encoder);
+ return intel_reserve_dpll_globals(state, crtc, encoder);
}
static int dg2_crtc_compute_clock(struct intel_atomic_state *state,
@@ -1224,7 +1224,7 @@ static int mtl_crtc_compute_clock(struct intel_atomic_state *state,
if (ret)
return ret;
- /* TODO: Do the readback via intel_compute_shared_dplls() */
+ /* TODO: Do the readback via intel_compute_dpll_globals() */
crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll);
crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
@@ -1397,7 +1397,7 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
ilk_compute_dpll(crtc_state, &crtc_state->dpll,
&crtc_state->dpll);
- ret = intel_compute_shared_dplls(state, crtc, NULL);
+ ret = intel_compute_dpll_globals(state, crtc, NULL);
if (ret)
return ret;
@@ -1417,7 +1417,7 @@ static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state,
if (!crtc_state->has_pch_encoder)
return 0;
- return intel_reserve_shared_dplls(state, crtc, NULL);
+ return intel_reserve_dpll_globals(state, crtc, NULL);
}
static u32 vlv_dpll(const struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 833c90f3f0f1..e6546d735799 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -49,21 +49,21 @@
* share a PLL if their configurations match.
*
* This file provides an abstraction over display PLLs. The function
- * intel_shared_dpll_init() initializes the PLLs for the given platform. The
+ * intel_dpll_global_init() initializes the PLLs for the given platform. The
* users of a PLL are tracked and that tracking is integrated with the atomic
* modset interface. During an atomic operation, required PLLs can be reserved
* for a given CRTC and encoder configuration by calling
- * intel_reserve_shared_dplls() and previously reserved PLLs can be released
- * with intel_release_shared_dplls().
+ * intel_reserve_dpll_globals() and previously reserved PLLs can be released
+ * with intel_release_dpll_globals().
* Changes to the users are first staged in the atomic state, and then made
- * effective by calling intel_shared_dpll_swap_state() during the atomic
+ * effective by calling intel_dpll_swap_state() during the atomic
* commit phase.
*/
/* platform specific hooks for managing DPLLs */
struct intel_dpll_global_funcs {
/*
- * Hook for enabling the pll, called from intel_enable_shared_dpll() if
+ * Hook for enabling the pll, called from intel_enable_dpll_global() if
* the pll is not already enabled.
*/
void (*enable)(struct intel_display *display,
@@ -71,7 +71,7 @@ struct intel_dpll_global_funcs {
const struct intel_dpll_hw_state *dpll_hw_state);
/*
- * Hook for disabling the pll, called from intel_disable_shared_dpll()
+ * Hook for disabling the pll, called from intel_disable_dpll_global()
* only when it is safe to disable the pll, i.e., there are no more
* tracked users for it.
*/
@@ -130,7 +130,7 @@ intel_atomic_duplicate_dpll_state(struct intel_display *display,
}
static struct intel_dpll_state *
-intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
+intel_atomic_get_dpll_global_state(struct drm_atomic_state *s)
{
struct intel_atomic_state *state = to_intel_atomic_state(s);
struct intel_display *display = to_intel_display(state);
@@ -148,7 +148,7 @@ intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
}
/**
- * intel_get_shared_dpll_by_id - get a DPLL given its id
+ * intel_get_dpll_global_by_id - get a DPLL given its id
* @display: intel_display device instance
* @id: pll id
*
@@ -156,7 +156,7 @@ intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
* A pointer to the DPLL with @id
*/
struct intel_dpll_global *
-intel_get_shared_dpll_by_id(struct intel_display *display,
+intel_get_dpll_global_by_id(struct intel_display *display,
enum intel_dpll_id id)
{
struct intel_dpll_global *pll;
@@ -172,7 +172,7 @@ intel_get_shared_dpll_by_id(struct intel_display *display,
}
/* For ILK+ */
-void assert_shared_dpll(struct intel_display *display,
+void assert_dpll_global(struct intel_display *display,
struct intel_dpll_global *pll,
bool state)
{
@@ -247,12 +247,12 @@ static void _intel_disable_shared_dpll(struct intel_display *display,
}
/**
- * intel_enable_shared_dpll - enable a CRTC's shared DPLL
- * @crtc_state: CRTC, and its state, which has a shared DPLL
+ * intel_enable_dpll_global - enable a CRTC's global DPLL
+ * @crtc_state: CRTC, and its state, which has a DPLL
*
- * Enable the shared DPLL used by @crtc.
+ * Enable DPLL used by @crtc.
*/
-void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
+void intel_enable_dpll_global(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -279,7 +279,7 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
if (old_mask) {
drm_WARN_ON(display->drm, !pll->on);
- assert_shared_dpll_enabled(display, pll);
+ assert_dpll_global_enabled(display, pll);
goto out;
}
drm_WARN_ON(display->drm, pll->on);
@@ -293,12 +293,12 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
}
/**
- * intel_disable_shared_dpll - disable a CRTC's shared DPLL
+ * intel_disable_dpll_global - disable a CRTC's shared DPLL
* @crtc_state: CRTC, and its state, which has a shared DPLL
*
- * Disable the shared DPLL used by @crtc.
+ * Disable DPLL used by @crtc.
*/
-void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
+void intel_disable_dpll_global(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -323,7 +323,7 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
pll->info->name, pll->active_mask, pll->on,
crtc->base.base.id, crtc->base.name);
- assert_shared_dpll_enabled(display, pll);
+ assert_dpll_global_enabled(display, pll);
drm_WARN_ON(display->drm, !pll->on);
pll->active_mask &= ~pipe_mask;
@@ -355,7 +355,7 @@ intel_dpll_mask_all(struct intel_display *display)
}
static struct intel_dpll_global *
-intel_find_shared_dpll(struct intel_atomic_state *state,
+intel_find_dpll_global(struct intel_atomic_state *state,
const struct intel_crtc *crtc,
const struct intel_dpll_hw_state *dpll_hw_state,
unsigned long dpll_mask)
@@ -366,14 +366,14 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
struct intel_dpll_global *unused_pll = NULL;
enum intel_dpll_id id;
- dpll_state = intel_atomic_get_shared_dpll_state(&state->base);
+ dpll_state = intel_atomic_get_dpll_global_state(&state->base);
drm_WARN_ON(display->drm, dpll_mask & ~dpll_mask_all);
for_each_set_bit(id, &dpll_mask, fls(dpll_mask_all)) {
struct intel_dpll_global *pll;
- pll = intel_get_shared_dpll_by_id(display, id);
+ pll = intel_get_dpll_global_by_id(display, id);
if (!pll)
continue;
@@ -409,7 +409,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
}
/**
- * intel_reference_shared_dpll_crtc - Get a DPLL reference for a CRTC
+ * intel_reference_dpll_global_crtc - Get a DPLL reference for a CRTC
* @crtc: CRTC on which behalf the reference is taken
* @pll: DPLL for which the reference is taken
* @dpll_state: the DPLL atomic state in which the reference is tracked
@@ -417,7 +417,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
* Take a reference for @pll tracking the use of it by @crtc.
*/
static void
-intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc,
+intel_reference_dpll_global_crtc(const struct intel_crtc *crtc,
const struct intel_dpll_global *pll,
struct intel_dpll_state *dpll_state)
{
@@ -432,23 +432,23 @@ intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc,
}
static void
-intel_reference_shared_dpll(struct intel_atomic_state *state,
+intel_reference_dpll_global(struct intel_atomic_state *state,
const struct intel_crtc *crtc,
const struct intel_dpll_global *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
struct intel_dpll_state *dpll_state;
- dpll_state = intel_atomic_get_shared_dpll_state(&state->base);
+ dpll_state = intel_atomic_get_dpll_global_state(&state->base);
if (dpll_state[pll->index].pipe_mask == 0)
dpll_state[pll->index].hw_state = *dpll_hw_state;
- intel_reference_shared_dpll_crtc(crtc, pll, &dpll_state[pll->index]);
+ intel_reference_dpll_global_crtc(crtc, pll, &dpll_state[pll->index]);
}
/**
- * intel_unreference_shared_dpll_crtc - Drop a DPLL reference for a CRTC
+ * intel_unreference_dpll_global_crtc - Drop a DPLL reference for a CRTC
* @crtc: CRTC on which behalf the reference is dropped
* @pll: DPLL for which the reference is dropped
* @dpll_state: the DPLL atomic state in which the reference is tracked
@@ -456,7 +456,7 @@ intel_reference_shared_dpll(struct intel_atomic_state *state,
* Drop a reference for @pll tracking the end of use of it by @crtc.
*/
void
-intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
+intel_unreference_dpll_global_crtc(const struct intel_crtc *crtc,
const struct intel_dpll_global *pll,
struct intel_dpll_state *dpll_state)
{
@@ -470,15 +470,15 @@ intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
crtc->base.base.id, crtc->base.name, pll->info->name);
}
-static void intel_unreference_shared_dpll(struct intel_atomic_state *state,
+static void intel_unreference_dpll_global(struct intel_atomic_state *state,
const struct intel_crtc *crtc,
const struct intel_dpll_global *pll)
{
struct intel_dpll_state *dpll_state;
- dpll_state = intel_atomic_get_shared_dpll_state(&state->base);
+ dpll_state = intel_atomic_get_dpll_global_state(&state->base);
- intel_unreference_shared_dpll_crtc(crtc, pll, &dpll_state[pll->index]);
+ intel_unreference_dpll_global_crtc(crtc, pll, &dpll_state[pll->index]);
}
static void intel_put_dpll(struct intel_atomic_state *state,
@@ -494,11 +494,11 @@ static void intel_put_dpll(struct intel_atomic_state *state,
if (!old_crtc_state->dpll_global)
return;
- intel_unreference_shared_dpll(state, crtc, old_crtc_state->dpll_global);
+ intel_unreference_dpll_global(state, crtc, old_crtc_state->dpll_global);
}
/**
- * intel_shared_dpll_swap_state - make atomic DPLL configuration effective
+ * intel_dpll_swap_state - make atomic DPLL configuration effective
* @state: atomic state
*
* This is the dpll version of drm_atomic_helper_swap_state() since the
@@ -508,7 +508,7 @@ static void intel_put_dpll(struct intel_atomic_state *state,
* i.e. it also puts the current state into @state, even though there is no
* need for that at this moment.
*/
-void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
+void intel_dpll_swap_state(struct intel_atomic_state *state)
{
struct intel_display *display = to_intel_display(state);
struct intel_dpll_state *dpll_state = state->dpll_state;
@@ -618,14 +618,14 @@ static int ibx_get_dpll(struct intel_atomic_state *state,
if (HAS_PCH_IBX(i915)) {
/* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
id = (enum intel_dpll_id) crtc->pipe;
- pll = intel_get_shared_dpll_by_id(display, id);
+ pll = intel_get_dpll_global_by_id(display, id);
drm_dbg_kms(display->drm,
"[CRTC:%d:%s] using pre-allocated %s\n",
crtc->base.base.id, crtc->base.name,
pll->info->name);
} else {
- pll = intel_find_shared_dpll(state, crtc,
+ pll = intel_find_dpll_global(state, crtc,
&crtc_state->dpll_hw_state,
BIT(DPLL_ID_PCH_PLL_B) |
BIT(DPLL_ID_PCH_PLL_A));
@@ -635,7 +635,7 @@ static int ibx_get_dpll(struct intel_atomic_state *state,
return -EINVAL;
/* reference the pll */
- intel_reference_shared_dpll(state, crtc,
+ intel_reference_dpll_global(state, crtc,
pll, &crtc_state->dpll_hw_state);
crtc_state->dpll_global = pll;
@@ -1064,7 +1064,7 @@ hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state,
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- return intel_find_shared_dpll(state, crtc,
+ return intel_find_dpll_global(state, crtc,
&crtc_state->dpll_hw_state,
BIT(DPLL_ID_WRPLL2) |
BIT(DPLL_ID_WRPLL1));
@@ -1111,7 +1111,7 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
return NULL;
}
- pll = intel_get_shared_dpll_by_id(display, pll_id);
+ pll = intel_get_dpll_global_by_id(display, pll_id);
if (!pll)
return NULL;
@@ -1167,7 +1167,7 @@ hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- return intel_find_shared_dpll(state, crtc, &crtc_state->dpll_hw_state,
+ return intel_find_dpll_global(state, crtc, &crtc_state->dpll_hw_state,
BIT(DPLL_ID_SPLL));
}
@@ -1231,7 +1231,7 @@ static int hsw_get_dpll(struct intel_atomic_state *state,
if (!pll)
return -EINVAL;
- intel_reference_shared_dpll(state, crtc,
+ intel_reference_dpll_global(state, crtc,
pll, &crtc_state->dpll_hw_state);
crtc_state->dpll_global = pll;
@@ -1940,11 +1940,11 @@ static int skl_get_dpll(struct intel_atomic_state *state,
struct intel_dpll_global *pll;
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
- pll = intel_find_shared_dpll(state, crtc,
+ pll = intel_find_dpll_global(state, crtc,
&crtc_state->dpll_hw_state,
BIT(DPLL_ID_SKL_DPLL0));
else
- pll = intel_find_shared_dpll(state, crtc,
+ pll = intel_find_dpll_global(state, crtc,
&crtc_state->dpll_hw_state,
BIT(DPLL_ID_SKL_DPLL3) |
BIT(DPLL_ID_SKL_DPLL2) |
@@ -1952,7 +1952,7 @@ static int skl_get_dpll(struct intel_atomic_state *state,
if (!pll)
return -EINVAL;
- intel_reference_shared_dpll(state, crtc,
+ intel_reference_dpll_global(state, crtc,
pll, &crtc_state->dpll_hw_state);
crtc_state->dpll_global = pll;
@@ -2432,12 +2432,12 @@ static int bxt_get_dpll(struct intel_atomic_state *state,
/* 1:1 mapping between ports and PLLs */
id = (enum intel_dpll_id) encoder->port;
- pll = intel_get_shared_dpll_by_id(display, id);
+ pll = intel_get_dpll_global_by_id(display, id);
drm_dbg_kms(display->drm, "[CRTC:%d:%s] using pre-allocated %s\n",
crtc->base.base.id, crtc->base.name, pll->info->name);
- intel_reference_shared_dpll(state, crtc,
+ intel_reference_dpll_global(state, crtc,
pll, &crtc_state->dpll_hw_state);
crtc_state->dpll_global = pll;
@@ -3388,13 +3388,13 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
/* Eliminate DPLLs from consideration if reserved by HTI */
dpll_mask &= ~intel_hti_dpll_mask(display);
- port_dpll->pll = intel_find_shared_dpll(state, crtc,
+ port_dpll->pll = intel_find_dpll_global(state, crtc,
&port_dpll->hw_state,
dpll_mask);
if (!port_dpll->pll)
return -EINVAL;
- intel_reference_shared_dpll(state, crtc,
+ intel_reference_dpll_global(state, crtc,
port_dpll->pll, &port_dpll->hw_state);
icl_update_active_dpll(state, crtc, encoder);
@@ -3452,25 +3452,25 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
int ret;
port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
- port_dpll->pll = intel_find_shared_dpll(state, crtc,
+ port_dpll->pll = intel_find_dpll_global(state, crtc,
&port_dpll->hw_state,
BIT(DPLL_ID_ICL_TBTPLL));
if (!port_dpll->pll)
return -EINVAL;
- intel_reference_shared_dpll(state, crtc,
+ intel_reference_dpll_global(state, crtc,
port_dpll->pll, &port_dpll->hw_state);
port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
dpll_id = icl_tc_port_to_pll_id(intel_encoder_to_tc(encoder));
- port_dpll->pll = intel_find_shared_dpll(state, crtc,
+ port_dpll->pll = intel_find_dpll_global(state, crtc,
&port_dpll->hw_state,
BIT(dpll_id));
if (!port_dpll->pll) {
ret = -EINVAL;
goto err_unreference_tbt_pll;
}
- intel_reference_shared_dpll(state, crtc,
+ intel_reference_dpll_global(state, crtc,
port_dpll->pll, &port_dpll->hw_state);
icl_update_active_dpll(state, crtc, encoder);
@@ -3479,7 +3479,7 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
err_unreference_tbt_pll:
port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
- intel_unreference_shared_dpll(state, crtc, port_dpll->pll);
+ intel_unreference_dpll_global(state, crtc, port_dpll->pll);
return ret;
}
@@ -3534,7 +3534,7 @@ static void icl_put_dplls(struct intel_atomic_state *state,
if (!old_port_dpll->pll)
continue;
- intel_unreference_shared_dpll(state, crtc, old_port_dpll->pll);
+ intel_unreference_dpll_global(state, crtc, old_port_dpll->pll);
}
}
@@ -4300,12 +4300,12 @@ static const struct intel_dpll_mgr adlp_pll_mgr = {
};
/**
- * intel_shared_dpll_init - Initialize shared DPLLs
+ * intel_dpll_global_init - Initialize DPLLs
* @display: intel_display device
*
- * Initialize shared DPLLs for @display.
+ * Initialize DPLLs for @display.
*/
-void intel_shared_dpll_init(struct intel_display *display)
+void intel_dpll_global_init(struct intel_display *display)
{
struct drm_i915_private *i915 = to_i915(display->drm);
const struct intel_dpll_mgr *dpll_mgr = NULL;
@@ -4363,7 +4363,7 @@ void intel_shared_dpll_init(struct intel_display *display)
}
/**
- * intel_compute_shared_dplls - compute DPLL state CRTC and encoder combination
+ * intel_compute_dpll_globals - compute DPLL state CRTC and encoder combination
* @state: atomic state
* @crtc: CRTC to compute DPLLs for
* @encoder: encoder
@@ -4371,12 +4371,12 @@ void intel_shared_dpll_init(struct intel_display *display)
* This function computes the DPLL state for the given CRTC and encoder.
*
* The new configuration in the atomic commit @state is made effective by
- * calling intel_shared_dpll_swap_state().
+ * calling intel_dpll_swap_state().
*
* Returns:
* 0 on success, negative error code on failure.
*/
-int intel_compute_shared_dplls(struct intel_atomic_state *state,
+int intel_compute_dpll_globals(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder)
{
@@ -4390,7 +4390,7 @@ int intel_compute_shared_dplls(struct intel_atomic_state *state,
}
/**
- * intel_reserve_shared_dplls - reserve DPLLs for CRTC and encoder combination
+ * intel_reserve_dpll_globals - reserve DPLLs for CRTC and encoder combination
* @state: atomic state
* @crtc: CRTC to reserve DPLLs for
* @encoder: encoder
@@ -4400,16 +4400,16 @@ int intel_compute_shared_dplls(struct intel_atomic_state *state,
* state.
*
* The new configuration in the atomic commit @state is made effective by
- * calling intel_shared_dpll_swap_state().
+ * calling intel_dpll_swap_state().
*
* The reserved DPLLs should be released by calling
- * intel_release_shared_dplls().
+ * intel_release_dpll_globals().
*
* Returns:
* 0 if all required DPLLs were successfully reserved,
* negative error code otherwise.
*/
-int intel_reserve_shared_dplls(struct intel_atomic_state *state,
+int intel_reserve_dpll_globals(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder)
{
@@ -4423,17 +4423,17 @@ int intel_reserve_shared_dplls(struct intel_atomic_state *state,
}
/**
- * intel_release_shared_dplls - end use of DPLLs by CRTC in atomic state
+ * intel_release_dpll_globals - end use of DPLLs by CRTC in atomic state
* @state: atomic state
* @crtc: crtc from which the DPLLs are to be released
*
- * This function releases all DPLLs reserved by intel_reserve_shared_dplls()
+ * This function releases all DPLLs reserved by intel_reserve_dpll_globals()
* from the current atomic commit @state and the old @crtc atomic state.
*
* The new configuration in the atomic commit @state is made effective by
- * calling intel_shared_dpll_swap_state().
+ * calling intel_dpll_swap_state().
*/
-void intel_release_shared_dplls(struct intel_atomic_state *state,
+void intel_release_dpll_globals(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct intel_display *display = to_intel_display(state);
@@ -4442,7 +4442,7 @@ void intel_release_shared_dplls(struct intel_atomic_state *state,
/*
* FIXME: this function is called for every platform having a
* compute_clock hook, even though the platform doesn't yet support
- * the shared DPLL framework and intel_reserve_shared_dplls() is not
+ * the global DPLL framework and intel_reserve_dpll_globals() is not
* called on those.
*/
if (!dpll_mgr)
@@ -4458,7 +4458,7 @@ void intel_release_shared_dplls(struct intel_atomic_state *state,
* @encoder: encoder determining the type of port DPLL
*
* Update the active DPLL for the given @crtc/@encoder in @crtc's atomic state,
- * from the port DPLLs reserved previously by intel_reserve_shared_dplls(). The
+ * from the port DPLLs reserved previously by intel_reserve_dpll_globals(). The
* DPLL selected will be based on the current mode of the encoder's port.
*/
void intel_update_active_dpll(struct intel_atomic_state *state,
@@ -4523,7 +4523,7 @@ static void readout_dpll_hw_state(struct intel_display *display,
to_intel_crtc_state(crtc->base.state);
if (crtc_state->hw.active && crtc_state->dpll_global == pll)
- intel_reference_shared_dpll_crtc(crtc, pll, &pll->state);
+ intel_reference_dpll_global_crtc(crtc, pll, &pll->state);
}
pll->active_mask = pll->state.pipe_mask;
@@ -4684,8 +4684,8 @@ static bool has_alt_port_dpll(const struct intel_dpll_global *old_pll,
(old_pll->info->is_alt_port_dpll || new_pll->info->is_alt_port_dpll);
}
-void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
- struct intel_crtc *crtc)
+void intel_dpll_state_verify(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
struct intel_display *display = to_intel_display(state);
const struct intel_crtc_state *old_crtc_state =
@@ -4715,7 +4715,7 @@ void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
}
}
-void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state)
+void intel_dpll_global_verify_disabled(struct intel_atomic_state *state)
{
struct intel_display *display = to_intel_display(state);
struct intel_dpll_global *pll;
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index bd52e30d83bd..6215da164ffc 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -387,24 +387,24 @@ struct intel_dpll_global {
#define SKL_DPLL2 2
#define SKL_DPLL3 3
-/* shared dpll functions */
+/* global dpll functions */
struct intel_dpll_global *
-intel_get_shared_dpll_by_id(struct intel_display *display,
+intel_get_dpll_global_by_id(struct intel_display *display,
enum intel_dpll_id id);
-void assert_shared_dpll(struct intel_display *display,
+void assert_dpll_global(struct intel_display *display,
struct intel_dpll_global *pll,
bool state);
-#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
-#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
-int intel_compute_shared_dplls(struct intel_atomic_state *state,
+#define assert_dpll_global_enabled(d, p) assert_dpll_global(d, p, true)
+#define assert_dpll_global_disabled(d, p) assert_dpll_global(d, p, false)
+int intel_compute_dpll_globals(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder);
-int intel_reserve_shared_dplls(struct intel_atomic_state *state,
+int intel_reserve_dpll_globals(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder);
-void intel_release_shared_dplls(struct intel_atomic_state *state,
+void intel_release_dpll_globals(struct intel_atomic_state *state,
struct intel_crtc *crtc);
-void intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
+void intel_unreference_dpll_global_crtc(const struct intel_crtc *crtc,
const struct intel_dpll_global *pll,
struct intel_dpll_state *shared_dpll_state);
void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
@@ -418,10 +418,10 @@ int intel_dpll_get_freq(struct intel_display *display,
bool intel_dpll_get_hw_state(struct intel_display *display,
struct intel_dpll_global *pll,
struct intel_dpll_hw_state *dpll_hw_state);
-void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
-void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
-void intel_shared_dpll_swap_state(struct intel_atomic_state *state);
-void intel_shared_dpll_init(struct intel_display *display);
+void intel_enable_dpll_global(const struct intel_crtc_state *crtc_state);
+void intel_disable_dpll_global(const struct intel_crtc_state *crtc_state);
+void intel_dpll_swap_state(struct intel_atomic_state *state);
+void intel_dpll_global_init(struct intel_display *display);
void intel_dpll_update_ref_clks(struct intel_display *display);
void intel_dpll_readout_hw_state(struct intel_display *display);
void intel_dpll_sanitize_state(struct intel_display *display);
@@ -435,8 +435,8 @@ bool intel_dpll_compare_hw_state(struct intel_display *display,
enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);
bool intel_dpll_is_combophy(enum intel_dpll_id id);
-void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
- struct intel_crtc *crtc);
-void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state);
+void intel_dpll_state_verify(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
+void intel_dpll_global_verify_disabled(struct intel_atomic_state *state);
#endif /* _INTEL_DPLL_MGR_H_ */
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
index bc8725aa99da..52f61a120b70 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -251,7 +251,7 @@ static void intel_pre_enable_lvds(struct intel_atomic_state *state,
if (HAS_PCH_SPLIT(i915)) {
assert_fdi_rx_pll_disabled(display, pipe);
- assert_shared_dpll_disabled(display, crtc_state->dpll_global);
+ assert_dpll_global_disabled(display, crtc_state->dpll_global);
} else {
assert_pll_disabled(display, pipe);
}
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index 427eff400b53..4221d1566c8a 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -92,7 +92,7 @@ static void intel_crtc_disable_noatomic_begin(struct intel_crtc *crtc,
crtc->base.enabled = false;
if (crtc_state->dpll_global)
- intel_unreference_shared_dpll_crtc(crtc,
+ intel_unreference_dpll_global_crtc(crtc,
crtc_state->dpll_global,
&crtc_state->dpll_global->state);
}
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
index a008412fdd04..eb080a1d8a42 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
@@ -246,7 +246,7 @@ void intel_modeset_verify_crtc(struct intel_atomic_state *state,
intel_wm_state_verify(state, crtc);
verify_connector_state(state, crtc);
verify_crtc_state(state, crtc);
- intel_shared_dpll_state_verify(state, crtc);
+ intel_dpll_state_verify(state, crtc);
intel_mpllb_state_verify(state, crtc);
intel_cx0pll_state_verify(state, crtc);
}
@@ -255,5 +255,5 @@ void intel_modeset_verify_disabled(struct intel_atomic_state *state)
{
verify_encoder_state(state);
verify_connector_state(state, NULL);
- intel_shared_dpll_verify_disabled(state);
+ intel_dpll_global_verify_disabled(state);
}
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 57303ecb77ad..aa39d0fb1e23 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -255,7 +255,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
u32 val, pipeconf_val;
/* Make sure PCH DPLL is enabled */
- assert_shared_dpll_enabled(display, crtc_state->dpll_global);
+ assert_dpll_global_enabled(display, crtc_state->dpll_global);
/* FDI must be feeding us bits for PCH ports */
assert_fdi_tx_enabled(display, pipe);
@@ -388,7 +388,7 @@ void ilk_pch_enable(struct intel_atomic_state *state,
temp |= TRANS_DPLL_ENABLE(pipe);
sel = TRANS_DPLLB_SEL(pipe);
if (crtc_state->dpll_global ==
- intel_get_shared_dpll_by_id(display, DPLL_ID_PCH_PLL_B))
+ intel_get_dpll_global_by_id(display, DPLL_ID_PCH_PLL_B))
temp |= sel;
else
temp &= ~sel;
@@ -400,11 +400,11 @@ void ilk_pch_enable(struct intel_atomic_state *state,
* transcoder, and we actually should do this to not upset any PCH
* transcoder that already use the clock when we share it.
*
- * Note that enable_shared_dpll tries to do the right thing, but
- * get_shared_dpll unconditionally resets the pll - we need that
+ * Note that enable_dpll_global tries to do the right thing, but
+ * get_dpll_global unconditionally resets the pll - we need that
* to have the right LVDS enable sequence.
*/
- intel_enable_shared_dpll(crtc_state);
+ intel_enable_dpll_global(crtc_state);
/* set transcoder timing, panel must allow it */
assert_pps_unlocked(display, pipe);
@@ -479,7 +479,7 @@ void ilk_pch_post_disable(struct intel_atomic_state *state,
ilk_fdi_pll_disable(crtc);
- intel_disable_shared_dpll(old_crtc_state);
+ intel_disable_dpll_global(old_crtc_state);
}
static void ilk_pch_clock_get(struct intel_crtc_state *crtc_state)
@@ -536,7 +536,7 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
pll_id = DPLL_ID_PCH_PLL_A;
}
- crtc_state->dpll_global = intel_get_shared_dpll_by_id(display, pll_id);
+ crtc_state->dpll_global = intel_get_dpll_global_by_id(display, pll_id);
pll = crtc_state->dpll_global;
pll_active = intel_dpll_get_hw_state(display, pll,
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 06/16] drm/i915/dpll: Rename crtc_get_shared_dpll
2025-04-02 8:31 [PATCH 00/16] DPLL framework redesign Suraj Kandpal
` (4 preceding siblings ...)
2025-04-02 8:31 ` [PATCH 05/16] drm/i915/dpll: Move away from using shared dpll Suraj Kandpal
@ 2025-04-02 8:31 ` Suraj Kandpal
2025-04-02 8:31 ` [PATCH 07/16] drm/i915/dpll: Change argument for enable hook in intel_global_dpll_funcs Suraj Kandpal
` (17 subsequent siblings)
23 siblings, 0 replies; 31+ messages in thread
From: Suraj Kandpal @ 2025-04-02 8:31 UTC (permalink / raw)
To: intel-xe, intel-gfx
Cc: ankit.k.nautiyal, uma.shankar, jani.nikula, mika.kahola,
ville.syrjala, Suraj Kandpal
Rename crtc_get_shared_dpll to take into the individual PLL framework
which came in at DISPLAY_VER >= 14.
--v2
-Change naming to dpll_global to keep consistency with rest of the
naming
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_dpll.c | 16 ++++++++--------
drivers/gpu/drm/i915/display/intel_dpll.h | 2 +-
3 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 904b9544515b..0c77fb02c565 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4222,7 +4222,7 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
crtc_state->update_wm_post = true;
if (intel_crtc_needs_modeset(crtc_state)) {
- ret = intel_dpll_crtc_get_shared_dpll(state, crtc);
+ ret = intel_dpll_crtc_get_dpll_global(state, crtc);
if (ret)
return ret;
}
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 04fb76a399ab..eac588566d7c 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -27,7 +27,7 @@
struct intel_dpll_funcs {
int (*crtc_compute_clock)(struct intel_atomic_state *state,
struct intel_crtc *crtc);
- int (*crtc_get_shared_dpll)(struct intel_atomic_state *state,
+ int (*crtc_get_dpll_global)(struct intel_atomic_state *state,
struct intel_crtc *crtc);
};
@@ -1177,7 +1177,7 @@ static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
return 0;
}
-static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state,
+static int hsw_crtc_get_dpll_global(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct intel_display *display = to_intel_display(state);
@@ -1407,7 +1407,7 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
return ret;
}
-static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state,
+static int ilk_crtc_get_dpll_global(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct intel_crtc_state *crtc_state =
@@ -1703,12 +1703,12 @@ static const struct intel_dpll_funcs dg2_dpll_funcs = {
static const struct intel_dpll_funcs hsw_dpll_funcs = {
.crtc_compute_clock = hsw_crtc_compute_clock,
- .crtc_get_shared_dpll = hsw_crtc_get_shared_dpll,
+ .crtc_get_dpll_global = hsw_crtc_get_dpll_global,
};
static const struct intel_dpll_funcs ilk_dpll_funcs = {
.crtc_compute_clock = ilk_crtc_compute_clock,
- .crtc_get_shared_dpll = ilk_crtc_get_shared_dpll,
+ .crtc_get_dpll_global = ilk_crtc_get_dpll_global,
};
static const struct intel_dpll_funcs chv_dpll_funcs = {
@@ -1761,7 +1761,7 @@ int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
return 0;
}
-int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
+int intel_dpll_crtc_get_dpll_global(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct intel_display *display = to_intel_display(state);
@@ -1775,10 +1775,10 @@ int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
if (!crtc_state->hw.enable || crtc_state->dpll_global)
return 0;
- if (!display->funcs.dpll->crtc_get_shared_dpll)
+ if (!display->funcs.dpll->crtc_get_dpll_global)
return 0;
- ret = display->funcs.dpll->crtc_get_shared_dpll(state, crtc);
+ ret = display->funcs.dpll->crtc_get_dpll_global(state, crtc);
if (ret) {
drm_dbg_kms(display->drm, "[CRTC:%d:%s] Couldn't get a shared DPLL\n",
crtc->base.base.id, crtc->base.name);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.h b/drivers/gpu/drm/i915/display/intel_dpll.h
index 280e90a57c87..81c9249f293b 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll.h
@@ -19,7 +19,7 @@ struct intel_dpll_hw_state;
void intel_dpll_init_clock_hook(struct intel_display *display);
int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
struct intel_crtc *crtc);
-int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
+int intel_dpll_crtc_get_dpll_global(struct intel_atomic_state *state,
struct intel_crtc *crtc);
int i9xx_calc_dpll_params(int refclk, struct dpll *clock);
u32 i9xx_dpll_compute_fp(const struct dpll *dpll);
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 07/16] drm/i915/dpll: Change argument for enable hook in intel_global_dpll_funcs
2025-04-02 8:31 [PATCH 00/16] DPLL framework redesign Suraj Kandpal
` (5 preceding siblings ...)
2025-04-02 8:31 ` [PATCH 06/16] drm/i915/dpll: Rename crtc_get_shared_dpll Suraj Kandpal
@ 2025-04-02 8:31 ` Suraj Kandpal
2025-04-02 8:31 ` [PATCH 08/16] drm/i915/drm: Rename disable hook in intel_dpll_global_func Suraj Kandpal
` (16 subsequent siblings)
23 siblings, 0 replies; 31+ messages in thread
From: Suraj Kandpal @ 2025-04-02 8:31 UTC (permalink / raw)
To: intel-xe, intel-gfx
Cc: ankit.k.nautiyal, uma.shankar, jani.nikula, mika.kahola,
ville.syrjala, Suraj Kandpal
Change the arguments for enable hook in intel_global_dpll_funcs to only
accept crtc_state. This is because we really don't need those extra
arguments everything can be derived from crtc_state and we need both
intel_encoder and crtc_state for PLL enablement when DISPLAY_VER() >= 14
which requires us to pass this crtc state if we want the future
PLL framework to fit into the existing one and not use the intel_ddi
hooks
--v2
-Rename global_dpll to dpll_global to keep consistency with filename
[Jani/Ville]
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 100 ++++++++++--------
1 file changed, 54 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index e6546d735799..869118f868f6 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -66,9 +66,8 @@ struct intel_dpll_global_funcs {
* Hook for enabling the pll, called from intel_enable_dpll_global() if
* the pll is not already enabled.
*/
- void (*enable)(struct intel_display *display,
- struct intel_dpll_global *pll,
- const struct intel_dpll_hw_state *dpll_hw_state);
+ void (*enable)(const struct intel_crtc_state *state,
+ struct intel_encoder *encoder);
/*
* Hook for disabling the pll, called from intel_disable_dpll_global()
@@ -226,13 +225,15 @@ intel_tc_pll_enable_reg(struct intel_display *display,
return MG_PLL_ENABLE(tc_port);
}
-static void _intel_enable_shared_dpll(struct intel_display *display,
- struct intel_dpll_global *pll)
+static void _intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
{
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_dpll_global *pll = crtc_state->dpll_global;
+
if (pll->info->power_domain)
pll->wakeref = intel_display_power_get(display, pll->info->power_domain);
- pll->info->funcs->enable(display, pll, &pll->state.hw_state);
+ pll->info->funcs->enable(crtc_state, NULL);
pll->on = true;
}
@@ -286,7 +287,7 @@ void intel_enable_dpll_global(const struct intel_crtc_state *crtc_state)
drm_dbg_kms(display->drm, "enabling %s\n", pll->info->name);
- _intel_enable_shared_dpll(display, pll);
+ _intel_enable_shared_dpll(crtc_state);
out:
mutex_unlock(&display->dpll.lock);
@@ -558,11 +559,12 @@ static void ibx_assert_pch_refclk_enabled(struct intel_display *display)
"PCH refclk assertion failure, should be active but is disabled\n");
}
-static void ibx_pch_dpll_enable(struct intel_display *display,
- struct intel_dpll_global *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static void ibx_pch_dpll_enable(const struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
- const struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx;
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_dpll_global *pll = crtc_state->dpll_global;
+ const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
const enum intel_dpll_id id = pll->info->id;
/* PCH refclock must be enabled first */
@@ -689,11 +691,12 @@ static const struct intel_dpll_mgr pch_pll_mgr = {
.compare_hw_state = ibx_compare_hw_state,
};
-static void hsw_ddi_wrpll_enable(struct intel_display *display,
- struct intel_dpll_global *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static void hsw_ddi_wrpll_enable(const struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
- const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_dpll_global *pll = crtc_state->dpll_global;
+ const struct hsw_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.hsw;
const enum intel_dpll_id id = pll->info->id;
intel_de_write(display, WRPLL_CTL(id), hw_state->wrpll);
@@ -701,11 +704,11 @@ static void hsw_ddi_wrpll_enable(struct intel_display *display,
udelay(20);
}
-static void hsw_ddi_spll_enable(struct intel_display *display,
- struct intel_dpll_global *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static void hsw_ddi_spll_enable(const struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
- const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
+ struct intel_display *display = to_intel_display(crtc_state);
+ const struct hsw_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.hsw;
intel_de_write(display, SPLL_CTL, hw_state->spll);
intel_de_posting_read(display, SPLL_CTL);
@@ -1282,9 +1285,8 @@ static const struct intel_dpll_global_funcs hsw_ddi_spll_funcs = {
.get_freq = hsw_ddi_spll_get_freq,
};
-static void hsw_ddi_lcpll_enable(struct intel_display *display,
- struct intel_dpll_global *pll,
- const struct intel_dpll_hw_state *hw_state)
+static void hsw_ddi_lcpll_enable(const struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
}
@@ -1375,11 +1377,12 @@ static void skl_ddi_pll_write_ctrl1(struct intel_display *display,
intel_de_posting_read(display, DPLL_CTRL1);
}
-static void skl_ddi_pll_enable(struct intel_display *display,
- struct intel_dpll_global *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static void skl_ddi_pll_enable(const struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
- const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_dpll_global *pll = crtc_state->dpll_global;
+ const struct skl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.skl;
const struct skl_dpll_regs *regs = skl_dpll_regs;
const enum intel_dpll_id id = pll->info->id;
@@ -1397,11 +1400,12 @@ static void skl_ddi_pll_enable(struct intel_display *display,
drm_err(display->drm, "DPLL %d not locked\n", id);
}
-static void skl_ddi_dpll0_enable(struct intel_display *display,
- struct intel_dpll_global *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static void skl_ddi_dpll0_enable(const struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
- const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_dpll_global *pll = crtc_state->dpll_global;
+ const struct skl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.skl;
skl_ddi_pll_write_ctrl1(display, pll, hw_state);
}
@@ -2035,11 +2039,12 @@ static const struct intel_dpll_mgr skl_pll_mgr = {
.compare_hw_state = skl_compare_hw_state,
};
-static void bxt_ddi_pll_enable(struct intel_display *display,
- struct intel_dpll_global *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static void bxt_ddi_pll_enable(const struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
- const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_dpll_global *pll = crtc_state->dpll_global;
+ const struct bxt_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.bxt;
enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
enum dpio_phy phy = DPIO_PHY0;
enum dpio_channel ch = DPIO_CH0;
@@ -3954,11 +3959,12 @@ static void adlp_cmtg_clock_gating_wa(struct intel_display *display, struct inte
drm_dbg_kms(display->drm, "Unexpected flags in TRANS_CMTG_CHICKEN: %08x\n", val);
}
-static void combo_pll_enable(struct intel_display *display,
- struct intel_dpll_global *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static void combo_pll_enable(const struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
- const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_dpll_global *pll = crtc_state->dpll_global;
+ const struct icl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.icl;
i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
icl_pll_power_enable(display, pll, enable_reg);
@@ -3978,11 +3984,12 @@ static void combo_pll_enable(struct intel_display *display,
/* DVFS post sequence would be here. See the comment above. */
}
-static void tbt_pll_enable(struct intel_display *display,
- struct intel_dpll_global *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static void tbt_pll_enable(const struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
- const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_dpll_global *pll = crtc_state->dpll_global;
+ const struct icl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.icl;
icl_pll_power_enable(display, pll, TBT_PLL_ENABLE);
@@ -3999,11 +4006,12 @@ static void tbt_pll_enable(struct intel_display *display,
/* DVFS post sequence would be here. See the comment above. */
}
-static void mg_pll_enable(struct intel_display *display,
- struct intel_dpll_global *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static void mg_pll_enable(const struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
- const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_dpll_global *pll = crtc_state->dpll_global;
+ const struct icl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.icl;
i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
icl_pll_power_enable(display, pll, enable_reg);
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 08/16] drm/i915/drm: Rename disable hook in intel_dpll_global_func
2025-04-02 8:31 [PATCH 00/16] DPLL framework redesign Suraj Kandpal
` (6 preceding siblings ...)
2025-04-02 8:31 ` [PATCH 07/16] drm/i915/dpll: Change argument for enable hook in intel_global_dpll_funcs Suraj Kandpal
@ 2025-04-02 8:31 ` Suraj Kandpal
2025-04-02 8:31 ` [PATCH 09/16] drm/i915/dpll: Introduce new " Suraj Kandpal
` (15 subsequent siblings)
23 siblings, 0 replies; 31+ messages in thread
From: Suraj Kandpal @ 2025-04-02 8:31 UTC (permalink / raw)
To: intel-xe, intel-gfx
Cc: ankit.k.nautiyal, uma.shankar, jani.nikula, mika.kahola,
ville.syrjala, Suraj Kandpal
Rename the disable hook to disable_shared_dpll since it will be used
only to disable shared dpll and not individual PLL going forward.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 30 +++++++++----------
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 869118f868f6..48efc25e18dc 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -70,12 +70,12 @@ struct intel_dpll_global_funcs {
struct intel_encoder *encoder);
/*
- * Hook for disabling the pll, called from intel_disable_dpll_global()
+ * Hook for disabling the shared pll, called from intel_disable_global_dpll()
* only when it is safe to disable the pll, i.e., there are no more
* tracked users for it.
*/
- void (*disable)(struct intel_display *display,
- struct intel_dpll_global *pll);
+ void (*shared_dpll_disable)(struct intel_display *display,
+ struct intel_dpll_global *pll);
/*
* Hook for reading the values currently programmed to the DPLL
@@ -240,7 +240,7 @@ static void _intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
static void _intel_disable_shared_dpll(struct intel_display *display,
struct intel_dpll_global *pll)
{
- pll->info->funcs->disable(display, pll);
+ pll->info->funcs->shared_dpll_disable(display, pll);
pll->on = false;
if (pll->info->power_domain)
@@ -672,7 +672,7 @@ static bool ibx_compare_hw_state(const struct intel_dpll_hw_state *_a,
static const struct intel_dpll_global_funcs ibx_pch_dpll_funcs = {
.enable = ibx_pch_dpll_enable,
- .disable = ibx_pch_dpll_disable,
+ .shared_dpll_disable = ibx_pch_dpll_disable,
.get_hw_state = ibx_pch_dpll_get_hw_state,
};
@@ -1273,14 +1273,14 @@ static bool hsw_compare_hw_state(const struct intel_dpll_hw_state *_a,
static const struct intel_dpll_global_funcs hsw_ddi_wrpll_funcs = {
.enable = hsw_ddi_wrpll_enable,
- .disable = hsw_ddi_wrpll_disable,
+ .shared_dpll_disable = hsw_ddi_wrpll_disable,
.get_hw_state = hsw_ddi_wrpll_get_hw_state,
.get_freq = hsw_ddi_wrpll_get_freq,
};
static const struct intel_dpll_global_funcs hsw_ddi_spll_funcs = {
.enable = hsw_ddi_spll_enable,
- .disable = hsw_ddi_spll_disable,
+ .shared_dpll_disable = hsw_ddi_spll_disable,
.get_hw_state = hsw_ddi_spll_get_hw_state,
.get_freq = hsw_ddi_spll_get_freq,
};
@@ -1304,7 +1304,7 @@ static bool hsw_ddi_lcpll_get_hw_state(struct intel_display *display,
static const struct intel_dpll_global_funcs hsw_ddi_lcpll_funcs = {
.enable = hsw_ddi_lcpll_enable,
- .disable = hsw_ddi_lcpll_disable,
+ .shared_dpll_disable = hsw_ddi_lcpll_disable,
.get_hw_state = hsw_ddi_lcpll_get_hw_state,
.get_freq = hsw_ddi_lcpll_get_freq,
};
@@ -2008,14 +2008,14 @@ static bool skl_compare_hw_state(const struct intel_dpll_hw_state *_a,
static const struct intel_dpll_global_funcs skl_ddi_pll_funcs = {
.enable = skl_ddi_pll_enable,
- .disable = skl_ddi_pll_disable,
+ .shared_dpll_disable = skl_ddi_pll_disable,
.get_hw_state = skl_ddi_pll_get_hw_state,
.get_freq = skl_ddi_pll_get_freq,
};
static const struct intel_dpll_global_funcs skl_ddi_dpll0_funcs = {
.enable = skl_ddi_dpll0_enable,
- .disable = skl_ddi_dpll0_disable,
+ .shared_dpll_disable = skl_ddi_dpll0_disable,
.get_hw_state = skl_ddi_dpll0_get_hw_state,
.get_freq = skl_ddi_pll_get_freq,
};
@@ -2491,7 +2491,7 @@ static bool bxt_compare_hw_state(const struct intel_dpll_hw_state *_a,
static const struct intel_dpll_global_funcs bxt_ddi_pll_funcs = {
.enable = bxt_ddi_pll_enable,
- .disable = bxt_ddi_pll_disable,
+ .shared_dpll_disable = bxt_ddi_pll_disable,
.get_hw_state = bxt_ddi_pll_get_hw_state,
.get_freq = bxt_ddi_pll_get_freq,
};
@@ -4139,21 +4139,21 @@ static bool icl_compare_hw_state(const struct intel_dpll_hw_state *_a,
static const struct intel_dpll_global_funcs combo_pll_funcs = {
.enable = combo_pll_enable,
- .disable = combo_pll_disable,
+ .shared_dpll_disable = combo_pll_disable,
.get_hw_state = combo_pll_get_hw_state,
.get_freq = icl_ddi_combo_pll_get_freq,
};
static const struct intel_dpll_global_funcs tbt_pll_funcs = {
.enable = tbt_pll_enable,
- .disable = tbt_pll_disable,
+ .shared_dpll_disable = tbt_pll_disable,
.get_hw_state = tbt_pll_get_hw_state,
.get_freq = icl_ddi_tbt_pll_get_freq,
};
static const struct intel_dpll_global_funcs mg_pll_funcs = {
.enable = mg_pll_enable,
- .disable = mg_pll_disable,
+ .shared_dpll_disable = mg_pll_disable,
.get_hw_state = mg_pll_get_hw_state,
.get_freq = icl_ddi_mg_pll_get_freq,
};
@@ -4201,7 +4201,7 @@ static const struct intel_dpll_mgr ehl_pll_mgr = {
static const struct intel_dpll_global_funcs dkl_pll_funcs = {
.enable = mg_pll_enable,
- .disable = mg_pll_disable,
+ .shared_dpll_disable = mg_pll_disable,
.get_hw_state = dkl_pll_get_hw_state,
.get_freq = icl_ddi_mg_pll_get_freq,
};
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 09/16] drm/i915/dpll: Introduce new hook in intel_dpll_global_func
2025-04-02 8:31 [PATCH 00/16] DPLL framework redesign Suraj Kandpal
` (7 preceding siblings ...)
2025-04-02 8:31 ` [PATCH 08/16] drm/i915/drm: Rename disable hook in intel_dpll_global_func Suraj Kandpal
@ 2025-04-02 8:31 ` Suraj Kandpal
2025-04-02 8:31 ` [PATCH 10/16] drm/i915/dpll: Add intel_encoder argument to get_hw_state hook Suraj Kandpal
` (14 subsequent siblings)
23 siblings, 0 replies; 31+ messages in thread
From: Suraj Kandpal @ 2025-04-02 8:31 UTC (permalink / raw)
To: intel-xe, intel-gfx
Cc: ankit.k.nautiyal, uma.shankar, jani.nikula, mika.kahola,
ville.syrjala, Suraj Kandpal
Introduce disable hook to disable individual dpll which is to
be used by DISPLAY_VER() >= 14.
--v2
-Rename intel_global_dpll to intel_dpll_global [Jani/Ville]
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 48efc25e18dc..27181ddc4e0f 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -69,6 +69,12 @@ struct intel_dpll_global_funcs {
void (*enable)(const struct intel_crtc_state *state,
struct intel_encoder *encoder);
+ /*
+ * Hook for disabling the individual pll, used from DISPLAY_VER() >= 14
+ */
+ void (*disable)(struct intel_display *display,
+ struct intel_dpll_global *pll);
+
/*
* Hook for disabling the shared pll, called from intel_disable_global_dpll()
* only when it is safe to disable the pll, i.e., there are no more
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 10/16] drm/i915/dpll: Add intel_encoder argument to get_hw_state hook
2025-04-02 8:31 [PATCH 00/16] DPLL framework redesign Suraj Kandpal
` (8 preceding siblings ...)
2025-04-02 8:31 ` [PATCH 09/16] drm/i915/dpll: Introduce new " Suraj Kandpal
@ 2025-04-02 8:31 ` Suraj Kandpal
2025-04-02 8:31 ` [PATCH 11/16] drm/i915/dpll: Change arguments for get_freq hook Suraj Kandpal
` (13 subsequent siblings)
23 siblings, 0 replies; 31+ messages in thread
From: Suraj Kandpal @ 2025-04-02 8:31 UTC (permalink / raw)
To: intel-xe, intel-gfx
Cc: ankit.k.nautiyal, uma.shankar, jani.nikula, mika.kahola,
ville.syrjala, Suraj Kandpal
Add intel_encoder argument in the get_hw_state hook as encoders
and the data stored within them are essential to read the hw state
starting DISPLAY_VER() >= 14.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 38 ++++++++++++-------
1 file changed, 25 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 27181ddc4e0f..287ad58dc95c 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -90,7 +90,8 @@ struct intel_dpll_global_funcs {
*/
bool (*get_hw_state)(struct intel_display *display,
struct intel_dpll_global *pll,
- struct intel_dpll_hw_state *dpll_hw_state);
+ struct intel_dpll_hw_state *dpll_hw_state,
+ struct intel_encoder *encoder);
/*
* Hook for calculating the pll's output frequency based on its passed
@@ -531,7 +532,8 @@ void intel_dpll_swap_state(struct intel_atomic_state *state)
static bool ibx_pch_dpll_get_hw_state(struct intel_display *display,
struct intel_dpll_global *pll,
- struct intel_dpll_hw_state *dpll_hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state,
+ struct intel_encoder *encoder)
{
struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx;
const enum intel_dpll_id id = pll->info->id;
@@ -755,7 +757,8 @@ static void hsw_ddi_spll_disable(struct intel_display *display,
static bool hsw_ddi_wrpll_get_hw_state(struct intel_display *display,
struct intel_dpll_global *pll,
- struct intel_dpll_hw_state *dpll_hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state,
+ struct intel_encoder *encoder)
{
struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
const enum intel_dpll_id id = pll->info->id;
@@ -777,7 +780,8 @@ static bool hsw_ddi_wrpll_get_hw_state(struct intel_display *display,
static bool hsw_ddi_spll_get_hw_state(struct intel_display *display,
struct intel_dpll_global *pll,
- struct intel_dpll_hw_state *dpll_hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state,
+ struct intel_encoder *encoder)
{
struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
intel_wakeref_t wakeref;
@@ -1303,7 +1307,8 @@ static void hsw_ddi_lcpll_disable(struct intel_display *display,
static bool hsw_ddi_lcpll_get_hw_state(struct intel_display *display,
struct intel_dpll_global *pll,
- struct intel_dpll_hw_state *dpll_hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state,
+ struct intel_encoder *encoder)
{
return true;
}
@@ -1434,7 +1439,8 @@ static void skl_ddi_dpll0_disable(struct intel_display *display,
static bool skl_ddi_pll_get_hw_state(struct intel_display *display,
struct intel_dpll_global *pll,
- struct intel_dpll_hw_state *dpll_hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state,
+ struct intel_encoder *encoder)
{
struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
const struct skl_dpll_regs *regs = skl_dpll_regs;
@@ -1472,7 +1478,8 @@ static bool skl_ddi_pll_get_hw_state(struct intel_display *display,
static bool skl_ddi_dpll0_get_hw_state(struct intel_display *display,
struct intel_dpll_global *pll,
- struct intel_dpll_hw_state *dpll_hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state,
+ struct intel_encoder *encoder)
{
struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
const struct skl_dpll_regs *regs = skl_dpll_regs;
@@ -2170,7 +2177,8 @@ static void bxt_ddi_pll_disable(struct intel_display *display,
static bool bxt_ddi_pll_get_hw_state(struct intel_display *display,
struct intel_dpll_global *pll,
- struct intel_dpll_hw_state *dpll_hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state,
+ struct intel_encoder *encoder)
{
struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
@@ -3551,7 +3559,8 @@ static void icl_put_dplls(struct intel_atomic_state *state,
static bool mg_pll_get_hw_state(struct intel_display *display,
struct intel_dpll_global *pll,
- struct intel_dpll_hw_state *dpll_hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state,
+ struct intel_encoder *encoder)
{
struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
const enum intel_dpll_id id = pll->info->id;
@@ -3618,7 +3627,8 @@ static bool mg_pll_get_hw_state(struct intel_display *display,
static bool dkl_pll_get_hw_state(struct intel_display *display,
struct intel_dpll_global *pll,
- struct intel_dpll_hw_state *dpll_hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state,
+ struct intel_encoder *encoder)
{
struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
const enum intel_dpll_id id = pll->info->id;
@@ -3751,7 +3761,8 @@ static bool icl_pll_get_hw_state(struct intel_display *display,
static bool combo_pll_get_hw_state(struct intel_display *display,
struct intel_dpll_global *pll,
- struct intel_dpll_hw_state *dpll_hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state,
+ struct intel_encoder *encoder)
{
i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
@@ -3760,7 +3771,8 @@ static bool combo_pll_get_hw_state(struct intel_display *display,
static bool tbt_pll_get_hw_state(struct intel_display *display,
struct intel_dpll_global *pll,
- struct intel_dpll_hw_state *dpll_hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state,
+ struct intel_encoder *encoder)
{
return icl_pll_get_hw_state(display, pll, dpll_hw_state, TBT_PLL_ENABLE);
}
@@ -4518,7 +4530,7 @@ bool intel_dpll_get_hw_state(struct intel_display *display,
struct intel_dpll_global *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
- return pll->info->funcs->get_hw_state(display, pll, dpll_hw_state);
+ return pll->info->funcs->get_hw_state(display, pll, dpll_hw_state, NULL);
}
static void readout_dpll_hw_state(struct intel_display *display,
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 11/16] drm/i915/dpll: Change arguments for get_freq hook
2025-04-02 8:31 [PATCH 00/16] DPLL framework redesign Suraj Kandpal
` (9 preceding siblings ...)
2025-04-02 8:31 ` [PATCH 10/16] drm/i915/dpll: Add intel_encoder argument to get_hw_state hook Suraj Kandpal
@ 2025-04-02 8:31 ` Suraj Kandpal
2025-04-02 8:32 ` [PATCH 12/16] drm/i915/dpll: Rename intel_[enable/disable]_global_dpll Suraj Kandpal
` (12 subsequent siblings)
23 siblings, 0 replies; 31+ messages in thread
From: Suraj Kandpal @ 2025-04-02 8:31 UTC (permalink / raw)
To: intel-xe, intel-gfx
Cc: ankit.k.nautiyal, uma.shankar, jani.nikula, mika.kahola,
ville.syrjala, Suraj Kandpal
Change the arguments for get_freq hook in intel_dpll_global_funcs
to use only intel_crtc_state and intel_encoder since that all we need
and the rest can be derived from the above two.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 6 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 107 +++++++++---------
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 5 +-
3 files changed, 57 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 3fe330bf2636..2f1f7dd20e80 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4200,8 +4200,7 @@ void intel_ddi_get_clock(struct intel_encoder *encoder,
icl_set_active_port_dpll(crtc_state, port_dpll_id);
- crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->dpll_global,
- &crtc_state->dpll_hw_state);
+ crtc_state->port_clock = intel_dpll_get_freq(crtc_state, encoder);
}
static void mtl_ddi_get_config(struct intel_encoder *encoder,
@@ -4313,8 +4312,7 @@ static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
if (icl_ddi_tc_pll_is_tbt(crtc_state->dpll_global))
crtc_state->port_clock = icl_calc_tbt_pll_link(display, encoder->port);
else
- crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->dpll_global,
- &crtc_state->dpll_hw_state);
+ crtc_state->port_clock = intel_dpll_get_freq(crtc_state, encoder);
}
static void icl_ddi_tc_get_config(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 287ad58dc95c..8b4c35245190 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -76,7 +76,7 @@ struct intel_dpll_global_funcs {
struct intel_dpll_global *pll);
/*
- * Hook for disabling the shared pll, called from intel_disable_global_dpll()
+ * Hook for disabling the shared pll, called from intel_disable_dpll_global()
* only when it is safe to disable the pll, i.e., there are no more
* tracked users for it.
*/
@@ -97,9 +97,8 @@ struct intel_dpll_global_funcs {
* Hook for calculating the pll's output frequency based on its passed
* in state.
*/
- int (*get_freq)(struct intel_display *i915,
- const struct intel_dpll_global *pll,
- const struct intel_dpll_hw_state *dpll_hw_state);
+ int (*get_freq)(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder);
};
struct intel_dpll_mgr {
@@ -1006,11 +1005,11 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */,
*r2_out = best.r2;
}
-static int hsw_ddi_wrpll_get_freq(struct intel_display *display,
- const struct intel_dpll_global *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static int hsw_ddi_wrpll_get_freq(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
- const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
+ struct intel_display *display = to_intel_display(crtc_state);
+ const struct hsw_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.hsw;
int refclk;
int n, p, r;
u32 wrpll = hw_state->wrpll;
@@ -1051,7 +1050,6 @@ static int
hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
- struct intel_display *display = to_intel_display(state);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
struct hsw_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.hsw;
@@ -1064,8 +1062,7 @@ hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state,
WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
WRPLL_DIVIDER_POST(p);
- crtc_state->port_clock = hsw_ddi_wrpll_get_freq(display, NULL,
- &crtc_state->dpll_hw_state);
+ crtc_state->port_clock = hsw_ddi_wrpll_get_freq(crtc_state, NULL);
return 0;
}
@@ -1132,10 +1129,11 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
return pll;
}
-static int hsw_ddi_lcpll_get_freq(struct intel_display *display,
- const struct intel_dpll_global *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static int hsw_ddi_lcpll_get_freq(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_dpll_global *pll = crtc_state->dpll_global;
int link_clock = 0;
switch (pll->info->id) {
@@ -1184,11 +1182,11 @@ hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
BIT(DPLL_ID_SPLL));
}
-static int hsw_ddi_spll_get_freq(struct intel_display *display,
- const struct intel_dpll_global *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static int hsw_ddi_spll_get_freq(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
- const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
+ struct intel_display *display = to_intel_display(crtc_state);
+ const struct hsw_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.hsw;
int link_clock = 0;
switch (hw_state->spll & SPLL_FREQ_MASK) {
@@ -1977,20 +1975,21 @@ static int skl_get_dpll(struct intel_atomic_state *state,
return 0;
}
-static int skl_ddi_pll_get_freq(struct intel_display *display,
- const struct intel_dpll_global *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static int skl_ddi_pll_get_freq(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
- const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_dpll_global *pll = crtc_state->dpll_global;
+ const struct skl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.skl;
/*
* ctrl1 register is already shifted for each pll, just use 0 to get
* the internal shift for each field
*/
if (hw_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0))
- return skl_ddi_wrpll_get_freq(display, pll, dpll_hw_state);
+ return skl_ddi_wrpll_get_freq(display, pll, &crtc_state->dpll_hw_state);
else
- return skl_ddi_lcpll_get_freq(display, pll, dpll_hw_state);
+ return skl_ddi_lcpll_get_freq(display, pll, &crtc_state->dpll_hw_state);
}
static void skl_update_dpll_ref_clks(struct intel_display *display)
@@ -2376,11 +2375,11 @@ static int bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
return 0;
}
-static int bxt_ddi_pll_get_freq(struct intel_display *display,
- const struct intel_dpll_global *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static int bxt_ddi_pll_get_freq(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
- const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
+ struct intel_display *display = to_intel_display(crtc_state);
+ const struct bxt_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.bxt;
struct dpll clock;
clock.m1 = 2;
@@ -2408,7 +2407,6 @@ bxt_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
static int
bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
{
- struct intel_display *display = to_intel_display(crtc_state);
struct dpll clk_div = {};
int ret;
@@ -2418,8 +2416,7 @@ bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
if (ret)
return ret;
- crtc_state->port_clock = bxt_ddi_pll_get_freq(display, NULL,
- &crtc_state->dpll_hw_state);
+ crtc_state->port_clock = bxt_ddi_pll_get_freq(crtc_state, NULL);
return 0;
}
@@ -2773,10 +2770,11 @@ static int icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
return 0;
}
-static int icl_ddi_tbt_pll_get_freq(struct intel_display *display,
- const struct intel_dpll_global *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static int icl_ddi_tbt_pll_get_freq(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
+ struct intel_display *display = to_intel_display(crtc_state);
+
/*
* The PLL outputs multiple frequencies at the same time, selection is
* made at DDI clock mux level.
@@ -2844,11 +2842,11 @@ icl_calc_wrpll(struct intel_crtc_state *crtc_state,
return 0;
}
-static int icl_ddi_combo_pll_get_freq(struct intel_display *display,
- const struct intel_dpll_global *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static int icl_ddi_combo_pll_get_freq(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
- const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
+ struct intel_display *display = to_intel_display(crtc_state);
+ const struct icl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.icl;
int ref_clock = icl_wrpll_ref_clock(display);
u32 dco_fraction;
u32 p0, p1, p2, dco_freq;
@@ -3217,11 +3215,11 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
return 0;
}
-static int icl_ddi_mg_pll_get_freq(struct intel_display *display,
- const struct intel_dpll_global *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static int icl_ddi_mg_pll_get_freq(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
- const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
+ struct intel_display *display = to_intel_display(crtc_state);
+ const struct icl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.icl;
u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
u64 tmp;
@@ -3354,8 +3352,7 @@ static int icl_compute_combo_phy_dpll(struct intel_atomic_state *state,
/* this is mainly for the fastset check */
icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);
- crtc_state->port_clock = icl_ddi_combo_pll_get_freq(display, NULL,
- &port_dpll->hw_state);
+ crtc_state->port_clock = icl_ddi_combo_pll_get_freq(crtc_state, NULL);
return 0;
}
@@ -3453,8 +3450,7 @@ static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state,
else
icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_MG_PHY);
- crtc_state->port_clock = icl_ddi_mg_pll_get_freq(display, NULL,
- &port_dpll->hw_state);
+ crtc_state->port_clock = icl_ddi_mg_pll_get_freq(crtc_state, NULL);
return 0;
}
@@ -4502,20 +4498,23 @@ void intel_update_active_dpll(struct intel_atomic_state *state,
/**
* intel_dpll_get_freq - calculate the DPLL's output frequency
- * @display: intel_display device
- * @pll: DPLL for which to calculate the output frequency
- * @dpll_hw_state: DPLL state from which to calculate the output frequency
+ * @crtc_state: crtc_state which contains the DPLL state from which we
+ * calculate frequency
+ * @encoder: Encoder for which the freq is calculated
*
- * Return the output frequency corresponding to @pll's passed in @dpll_hw_state.
+ * Return the output frequency corresponding to @pll's passed in
+ * @crtc_state->dpll_hw_state.
*/
-int intel_dpll_get_freq(struct intel_display *display,
- const struct intel_dpll_global *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+int intel_dpll_get_freq(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_dpll_global *pll = crtc_state->dpll_global;
+
if (drm_WARN_ON(display->drm, !pll->info->funcs->get_freq))
return 0;
- return pll->info->funcs->get_freq(display, pll, dpll_hw_state);
+ return pll->info->funcs->get_freq(crtc_state, encoder);
}
/**
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 6215da164ffc..d039056efbbc 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -412,9 +412,8 @@ void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
void intel_update_active_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder);
-int intel_dpll_get_freq(struct intel_display *display,
- const struct intel_dpll_global *pll,
- const struct intel_dpll_hw_state *dpll_hw_state);
+int intel_dpll_get_freq(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder);
bool intel_dpll_get_hw_state(struct intel_display *display,
struct intel_dpll_global *pll,
struct intel_dpll_hw_state *dpll_hw_state);
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 12/16] drm/i915/dpll: Rename intel_[enable/disable]_global_dpll
2025-04-02 8:31 [PATCH 00/16] DPLL framework redesign Suraj Kandpal
` (10 preceding siblings ...)
2025-04-02 8:31 ` [PATCH 11/16] drm/i915/dpll: Change arguments for get_freq hook Suraj Kandpal
@ 2025-04-02 8:32 ` Suraj Kandpal
2025-04-02 8:32 ` [PATCH 13/16] drm/i915/dpll: Rename intel_unreference_dpll_global_crtc Suraj Kandpal
` (11 subsequent siblings)
23 siblings, 0 replies; 31+ messages in thread
From: Suraj Kandpal @ 2025-04-02 8:32 UTC (permalink / raw)
To: intel-xe, intel-gfx
Cc: ankit.k.nautiyal, uma.shankar, jani.nikula, mika.kahola,
ville.syrjala, Suraj Kandpal
Rename intel_[enable/disable]_global_dpll to intel_dpll_[enable/disable]
in an effort to make sure all functions that are exported
start with the filename.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 8 ++++----
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 4 ++--
drivers/gpu/drm/i915/display/intel_pch_display.c | 6 +++---
4 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 0c77fb02c565..759479f576d8 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1662,7 +1662,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
intel_encoders_pre_pll_enable(state, crtc);
if (new_crtc_state->dpll_global)
- intel_enable_dpll_global(new_crtc_state);
+ intel_dpll_enable(new_crtc_state);
intel_encoders_pre_enable(state, crtc);
@@ -1791,7 +1791,7 @@ static void hsw_crtc_disable(struct intel_atomic_state *state,
intel_encoders_disable(state, crtc);
intel_encoders_post_disable(state, crtc);
- intel_disable_dpll_global(old_crtc_state);
+ intel_dpll_disable(old_crtc_state);
intel_encoders_post_pll_disable(state, crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 8b4c35245190..97447ac0fcdf 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -254,12 +254,12 @@ static void _intel_disable_shared_dpll(struct intel_display *display,
}
/**
- * intel_enable_dpll_global - enable a CRTC's global DPLL
+ * intel_dpll_enable - enable a CRTC's global DPLL
* @crtc_state: CRTC, and its state, which has a DPLL
*
* Enable DPLL used by @crtc.
*/
-void intel_enable_dpll_global(const struct intel_crtc_state *crtc_state)
+void intel_dpll_enable(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -300,12 +300,12 @@ void intel_enable_dpll_global(const struct intel_crtc_state *crtc_state)
}
/**
- * intel_disable_dpll_global - disable a CRTC's shared DPLL
+ * intel_dpll_disable - disable a CRTC's shared DPLL
* @crtc_state: CRTC, and its state, which has a shared DPLL
*
* Disable DPLL used by @crtc.
*/
-void intel_disable_dpll_global(const struct intel_crtc_state *crtc_state)
+void intel_dpll_disable(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index d039056efbbc..bc93cb36b737 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -417,8 +417,8 @@ int intel_dpll_get_freq(struct intel_crtc_state *crtc_state,
bool intel_dpll_get_hw_state(struct intel_display *display,
struct intel_dpll_global *pll,
struct intel_dpll_hw_state *dpll_hw_state);
-void intel_enable_dpll_global(const struct intel_crtc_state *crtc_state);
-void intel_disable_dpll_global(const struct intel_crtc_state *crtc_state);
+void intel_dpll_enable(const struct intel_crtc_state *crtc_state);
+void intel_dpll_disable(const struct intel_crtc_state *crtc_state);
void intel_dpll_swap_state(struct intel_atomic_state *state);
void intel_dpll_global_init(struct intel_display *display);
void intel_dpll_update_ref_clks(struct intel_display *display);
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index aa39d0fb1e23..4297afd5a37f 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -400,11 +400,11 @@ void ilk_pch_enable(struct intel_atomic_state *state,
* transcoder, and we actually should do this to not upset any PCH
* transcoder that already use the clock when we share it.
*
- * Note that enable_dpll_global tries to do the right thing, but
+ * Note that dpll_enable tries to do the right thing, but
* get_dpll_global unconditionally resets the pll - we need that
* to have the right LVDS enable sequence.
*/
- intel_enable_dpll_global(crtc_state);
+ intel_dpll_enable(crtc_state);
/* set transcoder timing, panel must allow it */
assert_pps_unlocked(display, pipe);
@@ -479,7 +479,7 @@ void ilk_pch_post_disable(struct intel_atomic_state *state,
ilk_fdi_pll_disable(crtc);
- intel_disable_dpll_global(old_crtc_state);
+ intel_dpll_disable(old_crtc_state);
}
static void ilk_pch_clock_get(struct intel_crtc_state *crtc_state)
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 13/16] drm/i915/dpll: Rename intel_unreference_dpll_global_crtc
2025-04-02 8:31 [PATCH 00/16] DPLL framework redesign Suraj Kandpal
` (11 preceding siblings ...)
2025-04-02 8:32 ` [PATCH 12/16] drm/i915/dpll: Rename intel_[enable/disable]_global_dpll Suraj Kandpal
@ 2025-04-02 8:32 ` Suraj Kandpal
2025-04-02 8:32 ` [PATCH 14/16] drm/i915/dpll: Rename intel_<release/reserve>_dpll_globals Suraj Kandpal
` (10 subsequent siblings)
23 siblings, 0 replies; 31+ messages in thread
From: Suraj Kandpal @ 2025-04-02 8:32 UTC (permalink / raw)
To: intel-xe, intel-gfx
Cc: ankit.k.nautiyal, uma.shankar, jani.nikula, mika.kahola,
ville.syrjala, Suraj Kandpal
Rename intel_unreference_dpll_global_crtc to intel_dpll_unreference_crtc
in an effort to keep names of exported functions start with the filename.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 10 +++++-----
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 6 +++---
drivers/gpu/drm/i915/display/intel_modeset_setup.c | 6 +++---
3 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 97447ac0fcdf..dd1f2104d5b1 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -455,7 +455,7 @@ intel_reference_dpll_global(struct intel_atomic_state *state,
}
/**
- * intel_unreference_dpll_global_crtc - Drop a DPLL reference for a CRTC
+ * intel_dpll_unreference_crtc - Drop a DPLL reference for a CRTC
* @crtc: CRTC on which behalf the reference is dropped
* @pll: DPLL for which the reference is dropped
* @dpll_state: the DPLL atomic state in which the reference is tracked
@@ -463,9 +463,9 @@ intel_reference_dpll_global(struct intel_atomic_state *state,
* Drop a reference for @pll tracking the end of use of it by @crtc.
*/
void
-intel_unreference_dpll_global_crtc(const struct intel_crtc *crtc,
- const struct intel_dpll_global *pll,
- struct intel_dpll_state *dpll_state)
+intel_dpll_unreference_crtc(const struct intel_crtc *crtc,
+ const struct intel_dpll_global *pll,
+ struct intel_dpll_state *dpll_state)
{
struct intel_display *display = to_intel_display(crtc);
@@ -485,7 +485,7 @@ static void intel_unreference_dpll_global(struct intel_atomic_state *state,
dpll_state = intel_atomic_get_dpll_global_state(&state->base);
- intel_unreference_dpll_global_crtc(crtc, pll, &dpll_state[pll->index]);
+ intel_dpll_unreference_crtc(crtc, pll, &dpll_state[pll->index]);
}
static void intel_put_dpll(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index bc93cb36b737..f240018416c7 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -404,9 +404,9 @@ int intel_reserve_dpll_globals(struct intel_atomic_state *state,
struct intel_encoder *encoder);
void intel_release_dpll_globals(struct intel_atomic_state *state,
struct intel_crtc *crtc);
-void intel_unreference_dpll_global_crtc(const struct intel_crtc *crtc,
- const struct intel_dpll_global *pll,
- struct intel_dpll_state *shared_dpll_state);
+void intel_dpll_unreference_crtc(const struct intel_crtc *crtc,
+ const struct intel_dpll_global *pll,
+ struct intel_dpll_state *shared_dpll_state);
void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
enum icl_port_dpll_id port_dpll_id);
void intel_update_active_dpll(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index 4221d1566c8a..191027c9bd4f 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -92,9 +92,9 @@ static void intel_crtc_disable_noatomic_begin(struct intel_crtc *crtc,
crtc->base.enabled = false;
if (crtc_state->dpll_global)
- intel_unreference_dpll_global_crtc(crtc,
- crtc_state->dpll_global,
- &crtc_state->dpll_global->state);
+ intel_dpll_unreference_crtc(crtc,
+ crtc_state->dpll_global,
+ &crtc_state->dpll_global->state);
}
static void set_encoder_for_connector(struct intel_connector *connector,
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 14/16] drm/i915/dpll: Rename intel_<release/reserve>_dpll_globals
2025-04-02 8:31 [PATCH 00/16] DPLL framework redesign Suraj Kandpal
` (12 preceding siblings ...)
2025-04-02 8:32 ` [PATCH 13/16] drm/i915/dpll: Rename intel_unreference_dpll_global_crtc Suraj Kandpal
@ 2025-04-02 8:32 ` Suraj Kandpal
2025-04-02 8:32 ` [PATCH 15/16] drm/i915/dpll: Rename intel_compute_dpll_globals Suraj Kandpal
` (9 subsequent siblings)
23 siblings, 0 replies; 31+ messages in thread
From: Suraj Kandpal @ 2025-04-02 8:32 UTC (permalink / raw)
To: intel-xe, intel-gfx
Cc: ankit.k.nautiyal, uma.shankar, jani.nikula, mika.kahola,
ville.syrjala, Suraj Kandpal
Rename intel_<release/reserve>_dpll_globals to
intel_dpll_<release/reserve> in an effort to keep names of
exported functions start with the filename.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_dpll.c | 4 +--
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 26 +++++++++----------
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 10 +++----
4 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 759479f576d8..5afc5e678844 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6429,7 +6429,7 @@ int intel_atomic_check(struct drm_device *dev,
any_ms = true;
- intel_release_dpll_globals(state, crtc);
+ intel_dpll_release(state, crtc);
}
if (any_ms && !check_digital_port_conflicts(state)) {
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index eac588566d7c..13a70ef95804 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1190,7 +1190,7 @@ static int hsw_crtc_get_dpll_global(struct intel_atomic_state *state,
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
return 0;
- return intel_reserve_dpll_globals(state, crtc, encoder);
+ return intel_dpll_reserve(state, crtc, encoder);
}
static int dg2_crtc_compute_clock(struct intel_atomic_state *state,
@@ -1417,7 +1417,7 @@ static int ilk_crtc_get_dpll_global(struct intel_atomic_state *state,
if (!crtc_state->has_pch_encoder)
return 0;
- return intel_reserve_dpll_globals(state, crtc, NULL);
+ return intel_dpll_reserve(state, crtc, NULL);
}
static u32 vlv_dpll(const struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index dd1f2104d5b1..7faf1b2e6399 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -53,8 +53,8 @@
* users of a PLL are tracked and that tracking is integrated with the atomic
* modset interface. During an atomic operation, required PLLs can be reserved
* for a given CRTC and encoder configuration by calling
- * intel_reserve_dpll_globals() and previously reserved PLLs can be released
- * with intel_release_dpll_globals().
+ * intel_dpll_reserve() and previously reserved PLLs can be released
+ * with intel_dpll_release().
* Changes to the users are first staged in the atomic state, and then made
* effective by calling intel_dpll_swap_state() during the atomic
* commit phase.
@@ -4412,7 +4412,7 @@ int intel_compute_dpll_globals(struct intel_atomic_state *state,
}
/**
- * intel_reserve_dpll_globals - reserve DPLLs for CRTC and encoder combination
+ * intel_dpll_reserve - reserve DPLLs for CRTC and encoder combination
* @state: atomic state
* @crtc: CRTC to reserve DPLLs for
* @encoder: encoder
@@ -4425,15 +4425,15 @@ int intel_compute_dpll_globals(struct intel_atomic_state *state,
* calling intel_dpll_swap_state().
*
* The reserved DPLLs should be released by calling
- * intel_release_dpll_globals().
+ * intel_dpll_release().
*
* Returns:
* 0 if all required DPLLs were successfully reserved,
* negative error code otherwise.
*/
-int intel_reserve_dpll_globals(struct intel_atomic_state *state,
- struct intel_crtc *crtc,
- struct intel_encoder *encoder)
+int intel_dpll_reserve(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_encoder *encoder)
{
struct intel_display *display = to_intel_display(state);
const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
@@ -4445,18 +4445,18 @@ int intel_reserve_dpll_globals(struct intel_atomic_state *state,
}
/**
- * intel_release_dpll_globals - end use of DPLLs by CRTC in atomic state
+ * intel_dpll_release - end use of DPLLs by CRTC in atomic state
* @state: atomic state
* @crtc: crtc from which the DPLLs are to be released
*
- * This function releases all DPLLs reserved by intel_reserve_dpll_globals()
+ * This function releases all DPLLs reserved by intel_dpll_reserve()
* from the current atomic commit @state and the old @crtc atomic state.
*
* The new configuration in the atomic commit @state is made effective by
* calling intel_dpll_swap_state().
*/
-void intel_release_dpll_globals(struct intel_atomic_state *state,
- struct intel_crtc *crtc)
+void intel_dpll_release(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
struct intel_display *display = to_intel_display(state);
const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
@@ -4464,7 +4464,7 @@ void intel_release_dpll_globals(struct intel_atomic_state *state,
/*
* FIXME: this function is called for every platform having a
* compute_clock hook, even though the platform doesn't yet support
- * the global DPLL framework and intel_reserve_dpll_globals() is not
+ * the global DPLL framework and intel_dpll_reserve() is not
* called on those.
*/
if (!dpll_mgr)
@@ -4480,7 +4480,7 @@ void intel_release_dpll_globals(struct intel_atomic_state *state,
* @encoder: encoder determining the type of port DPLL
*
* Update the active DPLL for the given @crtc/@encoder in @crtc's atomic state,
- * from the port DPLLs reserved previously by intel_reserve_dpll_globals(). The
+ * from the port DPLLs reserved previously by intel_dpll_reserve(). The
* DPLL selected will be based on the current mode of the encoder's port.
*/
void intel_update_active_dpll(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index f240018416c7..b6d5a15b8103 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -399,11 +399,11 @@ void assert_dpll_global(struct intel_display *display,
int intel_compute_dpll_globals(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder);
-int intel_reserve_dpll_globals(struct intel_atomic_state *state,
- struct intel_crtc *crtc,
- struct intel_encoder *encoder);
-void intel_release_dpll_globals(struct intel_atomic_state *state,
- struct intel_crtc *crtc);
+int intel_dpll_reserve(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_encoder *encoder);
+void intel_dpll_release(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
void intel_dpll_unreference_crtc(const struct intel_crtc *crtc,
const struct intel_dpll_global *pll,
struct intel_dpll_state *shared_dpll_state);
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 15/16] drm/i915/dpll: Rename intel_compute_dpll_globals
2025-04-02 8:31 [PATCH 00/16] DPLL framework redesign Suraj Kandpal
` (13 preceding siblings ...)
2025-04-02 8:32 ` [PATCH 14/16] drm/i915/dpll: Rename intel_<release/reserve>_dpll_globals Suraj Kandpal
@ 2025-04-02 8:32 ` Suraj Kandpal
2025-04-02 8:32 ` [PATCH 16/16] drm/i915/dpll: Rename intel_update_active_dpll Suraj Kandpal
` (8 subsequent siblings)
23 siblings, 0 replies; 31+ messages in thread
From: Suraj Kandpal @ 2025-04-02 8:32 UTC (permalink / raw)
To: intel-xe, intel-gfx
Cc: ankit.k.nautiyal, uma.shankar, jani.nikula, mika.kahola,
ville.syrjala, Suraj Kandpal
Rename intel_compute_dpll_globals to intel_dpll_compute in an
effort to make sure all function names that are exported have
the filename at start.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll.c | 6 +++---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 8 ++++----
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 6 +++---
3 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 13a70ef95804..1cdd54e5beaf 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1162,7 +1162,7 @@ static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
return 0;
- ret = intel_compute_dpll_globals(state, crtc, encoder);
+ ret = intel_dpll_compute(state, crtc, encoder);
if (ret)
return ret;
@@ -1224,7 +1224,7 @@ static int mtl_crtc_compute_clock(struct intel_atomic_state *state,
if (ret)
return ret;
- /* TODO: Do the readback via intel_compute_dpll_globals() */
+ /* TODO: Do the readback via intel_dpll_compute() */
crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll);
crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
@@ -1397,7 +1397,7 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
ilk_compute_dpll(crtc_state, &crtc_state->dpll,
&crtc_state->dpll);
- ret = intel_compute_dpll_globals(state, crtc, NULL);
+ ret = intel_dpll_compute(state, crtc, NULL);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 7faf1b2e6399..03c08ada0261 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4385,7 +4385,7 @@ void intel_dpll_global_init(struct intel_display *display)
}
/**
- * intel_compute_dpll_globals - compute DPLL state CRTC and encoder combination
+ * intel_dpll_compute - compute DPLL state CRTC and encoder combination
* @state: atomic state
* @crtc: CRTC to compute DPLLs for
* @encoder: encoder
@@ -4398,9 +4398,9 @@ void intel_dpll_global_init(struct intel_display *display)
* Returns:
* 0 on success, negative error code on failure.
*/
-int intel_compute_dpll_globals(struct intel_atomic_state *state,
- struct intel_crtc *crtc,
- struct intel_encoder *encoder)
+int intel_dpll_compute(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_encoder *encoder)
{
struct intel_display *display = to_intel_display(state);
const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index b6d5a15b8103..9bd71aba6c6a 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -396,9 +396,9 @@ void assert_dpll_global(struct intel_display *display,
bool state);
#define assert_dpll_global_enabled(d, p) assert_dpll_global(d, p, true)
#define assert_dpll_global_disabled(d, p) assert_dpll_global(d, p, false)
-int intel_compute_dpll_globals(struct intel_atomic_state *state,
- struct intel_crtc *crtc,
- struct intel_encoder *encoder);
+int intel_dpll_compute(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_encoder *encoder);
int intel_dpll_reserve(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder);
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 16/16] drm/i915/dpll: Rename intel_update_active_dpll
2025-04-02 8:31 [PATCH 00/16] DPLL framework redesign Suraj Kandpal
` (14 preceding siblings ...)
2025-04-02 8:32 ` [PATCH 15/16] drm/i915/dpll: Rename intel_compute_dpll_globals Suraj Kandpal
@ 2025-04-02 8:32 ` Suraj Kandpal
2025-04-02 8:39 ` ✓ CI.Patch_applied: success for DPLL framework redesign (rev2) Patchwork
` (7 subsequent siblings)
23 siblings, 0 replies; 31+ messages in thread
From: Suraj Kandpal @ 2025-04-02 8:32 UTC (permalink / raw)
To: intel-xe, intel-gfx
Cc: ankit.k.nautiyal, uma.shankar, jani.nikula, mika.kahola,
ville.syrjala, Suraj Kandpal
Rename intel_update_active_dpll to intel_dpll_update_active in an
effort to have function names which are exported to start with
filenames they are exported from.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 4 ++--
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 2f1f7dd20e80..1253fa35a5d0 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3647,7 +3647,7 @@ void intel_ddi_update_active_dpll(struct intel_atomic_state *state,
for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc,
intel_crtc_joined_pipe_mask(crtc_state))
- intel_update_active_dpll(state, pipe_crtc, encoder);
+ intel_dpll_update_active(state, pipe_crtc, encoder);
}
/*
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 03c08ada0261..2b86775c464e 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4474,7 +4474,7 @@ void intel_dpll_release(struct intel_atomic_state *state,
}
/**
- * intel_update_active_dpll - update the active DPLL for a CRTC/encoder
+ * intel_dpll_update_active - update the active DPLL for a CRTC/encoder
* @state: atomic state
* @crtc: the CRTC for which to update the active DPLL
* @encoder: encoder determining the type of port DPLL
@@ -4483,7 +4483,7 @@ void intel_dpll_release(struct intel_atomic_state *state,
* from the port DPLLs reserved previously by intel_dpll_reserve(). The
* DPLL selected will be based on the current mode of the encoder's port.
*/
-void intel_update_active_dpll(struct intel_atomic_state *state,
+void intel_dpll_update_active(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder)
{
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 9bd71aba6c6a..b6d985e4e3ec 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -409,7 +409,7 @@ void intel_dpll_unreference_crtc(const struct intel_crtc *crtc,
struct intel_dpll_state *shared_dpll_state);
void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
enum icl_port_dpll_id port_dpll_id);
-void intel_update_active_dpll(struct intel_atomic_state *state,
+void intel_dpll_update_active(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder);
int intel_dpll_get_freq(struct intel_crtc_state *crtc_state,
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* ✓ CI.Patch_applied: success for DPLL framework redesign (rev2)
2025-04-02 8:31 [PATCH 00/16] DPLL framework redesign Suraj Kandpal
` (15 preceding siblings ...)
2025-04-02 8:32 ` [PATCH 16/16] drm/i915/dpll: Rename intel_update_active_dpll Suraj Kandpal
@ 2025-04-02 8:39 ` Patchwork
2025-04-02 8:40 ` ✗ CI.checkpatch: warning " Patchwork
` (6 subsequent siblings)
23 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2025-04-02 8:39 UTC (permalink / raw)
To: Suraj Kandpal; +Cc: intel-xe
== Series Details ==
Series: DPLL framework redesign (rev2)
URL : https://patchwork.freedesktop.org/series/145380/
State : success
== Summary ==
=== Applying kernel patches on branch 'drm-tip' with base: ===
Base commit: f0fd77956987 drm-tip: 2025y-04m-02d-05h-39m-01s UTC integration manifest
=== git am output follows ===
Applying: drm/i915/dpll: Rename intel_shared_dpll_state
Applying: drm/i915/dpll: Rename macro for_each_shared_dpll
Applying: drm/i915/dpll: Rename intel_shared_dpll_funcs
Applying: drm/i915/dpll: Rename intel_shared_dpll
Applying: drm/i915/dpll: Move away from using shared dpll
Applying: drm/i915/dpll: Rename crtc_get_shared_dpll
Applying: drm/i915/dpll: Change argument for enable hook in intel_global_dpll_funcs
Applying: drm/i915/drm: Rename disable hook in intel_dpll_global_func
Applying: drm/i915/dpll: Introduce new hook in intel_dpll_global_func
Applying: drm/i915/dpll: Add intel_encoder argument to get_hw_state hook
Applying: drm/i915/dpll: Change arguments for get_freq hook
Applying: drm/i915/dpll: Rename intel_[enable/disable]_global_dpll
Applying: drm/i915/dpll: Rename intel_unreference_dpll_global_crtc
Applying: drm/i915/dpll: Rename intel_<release/reserve>_dpll_globals
Applying: drm/i915/dpll: Rename intel_compute_dpll_globals
Applying: drm/i915/dpll: Rename intel_update_active_dpll
^ permalink raw reply [flat|nested] 31+ messages in thread
* ✗ CI.checkpatch: warning for DPLL framework redesign (rev2)
2025-04-02 8:31 [PATCH 00/16] DPLL framework redesign Suraj Kandpal
` (16 preceding siblings ...)
2025-04-02 8:39 ` ✓ CI.Patch_applied: success for DPLL framework redesign (rev2) Patchwork
@ 2025-04-02 8:40 ` Patchwork
2025-04-02 8:41 ` ✓ CI.KUnit: success " Patchwork
` (5 subsequent siblings)
23 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2025-04-02 8:40 UTC (permalink / raw)
To: Suraj Kandpal; +Cc: intel-xe
== Series Details ==
Series: DPLL framework redesign (rev2)
URL : https://patchwork.freedesktop.org/series/145380/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
99e5a866b5e13f134e606a3e29d9508d97826fb3
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 15868762c8a0acfbd506f0385c9caf431e99ded7
Author: Suraj Kandpal <suraj.kandpal@intel.com>
Date: Wed Apr 2 14:02:04 2025 +0530
drm/i915/dpll: Rename intel_update_active_dpll
Rename intel_update_active_dpll to intel_dpll_update_active in an
effort to have function names which are exported to start with
filenames they are exported from.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
+ /mt/dim checkpatch f0fd77956987f035c79d08c812343a27a655a57b drm-intel
6d389dc3b7a2 drm/i915/dpll: Rename intel_shared_dpll_state
7d821180c8e9 drm/i915/dpll: Rename macro for_each_shared_dpll
-:102: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__display' - possible side-effects?
#102: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.h:33:
+#define for_each_dpll(__display, __pll, __i) \
for ((__i) = 0; (__i) < (__display)->dpll.num_shared_dpll && \
((__pll) = &(__display)->dpll.shared_dplls[(__i)]) ; (__i)++)
-:102: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i' - possible side-effects?
#102: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.h:33:
+#define for_each_dpll(__display, __pll, __i) \
for ((__i) = 0; (__i) < (__display)->dpll.num_shared_dpll && \
((__pll) = &(__display)->dpll.shared_dplls[(__i)]) ; (__i)++)
total: 0 errors, 0 warnings, 2 checks, 81 lines checked
118b57db0a78 drm/i915/dpll: Rename intel_shared_dpll_funcs
c54777679a04 drm/i915/dpll: Rename intel_shared_dpll
35a75716f77c drm/i915/dpll: Move away from using shared dpll
4bbc0d5f6251 drm/i915/dpll: Rename crtc_get_shared_dpll
c046d7908512 drm/i915/dpll: Change argument for enable hook in intel_global_dpll_funcs
1877a99c9263 drm/i915/drm: Rename disable hook in intel_dpll_global_func
16e7b9fa1ebe drm/i915/dpll: Introduce new hook in intel_dpll_global_func
014809e753d9 drm/i915/dpll: Add intel_encoder argument to get_hw_state hook
257612d424b8 drm/i915/dpll: Change arguments for get_freq hook
7a1d1026788d drm/i915/dpll: Rename intel_[enable/disable]_global_dpll
d675005552ca drm/i915/dpll: Rename intel_unreference_dpll_global_crtc
28f28a463697 drm/i915/dpll: Rename intel_<release/reserve>_dpll_globals
0ad1c0f06a81 drm/i915/dpll: Rename intel_compute_dpll_globals
15868762c8a0 drm/i915/dpll: Rename intel_update_active_dpll
^ permalink raw reply [flat|nested] 31+ messages in thread
* ✓ CI.KUnit: success for DPLL framework redesign (rev2)
2025-04-02 8:31 [PATCH 00/16] DPLL framework redesign Suraj Kandpal
` (17 preceding siblings ...)
2025-04-02 8:40 ` ✗ CI.checkpatch: warning " Patchwork
@ 2025-04-02 8:41 ` Patchwork
2025-04-02 8:58 ` ✓ CI.Build: " Patchwork
` (4 subsequent siblings)
23 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2025-04-02 8:41 UTC (permalink / raw)
To: Suraj Kandpal; +Cc: intel-xe
== Series Details ==
Series: DPLL framework redesign (rev2)
URL : https://patchwork.freedesktop.org/series/145380/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[08:40:25] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[08:40:29] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json ARCH=um O=.kunit --jobs=48
../lib/iomap.c:156:5: warning: no previous prototype for ‘ioread64_lo_hi’ [-Wmissing-prototypes]
156 | u64 ioread64_lo_hi(const void __iomem *addr)
| ^~~~~~~~~~~~~~
../lib/iomap.c:163:5: warning: no previous prototype for ‘ioread64_hi_lo’ [-Wmissing-prototypes]
163 | u64 ioread64_hi_lo(const void __iomem *addr)
| ^~~~~~~~~~~~~~
../lib/iomap.c:170:5: warning: no previous prototype for ‘ioread64be_lo_hi’ [-Wmissing-prototypes]
170 | u64 ioread64be_lo_hi(const void __iomem *addr)
| ^~~~~~~~~~~~~~~~
../lib/iomap.c:178:5: warning: no previous prototype for ‘ioread64be_hi_lo’ [-Wmissing-prototypes]
178 | u64 ioread64be_hi_lo(const void __iomem *addr)
| ^~~~~~~~~~~~~~~~
../lib/iomap.c:264:6: warning: no previous prototype for ‘iowrite64_lo_hi’ [-Wmissing-prototypes]
264 | void iowrite64_lo_hi(u64 val, void __iomem *addr)
| ^~~~~~~~~~~~~~~
../lib/iomap.c:272:6: warning: no previous prototype for ‘iowrite64_hi_lo’ [-Wmissing-prototypes]
272 | void iowrite64_hi_lo(u64 val, void __iomem *addr)
| ^~~~~~~~~~~~~~~
../lib/iomap.c:280:6: warning: no previous prototype for ‘iowrite64be_lo_hi’ [-Wmissing-prototypes]
280 | void iowrite64be_lo_hi(u64 val, void __iomem *addr)
| ^~~~~~~~~~~~~~~~~
../lib/iomap.c:288:6: warning: no previous prototype for ‘iowrite64be_hi_lo’ [-Wmissing-prototypes]
288 | void iowrite64be_hi_lo(u64 val, void __iomem *addr)
| ^~~~~~~~~~~~~~~~~
[08:40:56] Starting KUnit Kernel (1/1)...
[08:40:56] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[08:40:56] ================== guc_buf (11 subtests) ===================
[08:40:56] [PASSED] test_smallest
[08:40:56] [PASSED] test_largest
[08:40:56] [PASSED] test_granular
[08:40:56] [PASSED] test_unique
[08:40:56] [PASSED] test_overlap
[08:40:56] [PASSED] test_reusable
[08:40:56] [PASSED] test_too_big
[08:40:56] [PASSED] test_flush
[08:40:56] [PASSED] test_lookup
[08:40:56] [PASSED] test_data
[08:40:56] [PASSED] test_class
[08:40:56] ===================== [PASSED] guc_buf =====================
[08:40:56] =================== guc_dbm (7 subtests) ===================
[08:40:56] [PASSED] test_empty
[08:40:56] [PASSED] test_default
[08:40:56] ======================== test_size ========================
[08:40:56] [PASSED] 4
[08:40:56] [PASSED] 8
[08:40:56] [PASSED] 32
[08:40:56] [PASSED] 256
[08:40:56] ==================== [PASSED] test_size ====================
[08:40:56] ======================= test_reuse ========================
[08:40:56] [PASSED] 4
[08:40:56] [PASSED] 8
[08:40:56] [PASSED] 32
[08:40:56] [PASSED] 256
[08:40:56] =================== [PASSED] test_reuse ====================
[08:40:56] =================== test_range_overlap ====================
[08:40:56] [PASSED] 4
[08:40:56] [PASSED] 8
[08:40:56] [PASSED] 32
[08:40:56] [PASSED] 256
[08:40:56] =============== [PASSED] test_range_overlap ================
[08:40:56] =================== test_range_compact ====================
[08:40:56] [PASSED] 4
[08:40:56] [PASSED] 8
[08:40:56] [PASSED] 32
[08:40:56] [PASSED] 256
[08:40:56] =============== [PASSED] test_range_compact ================
[08:40:56] ==================== test_range_spare =====================
[08:40:56] [PASSED] 4
[08:40:56] [PASSED] 8
[08:40:56] [PASSED] 32
[08:40:56] [PASSED] 256
[08:40:56] ================ [PASSED] test_range_spare =================
[08:40:56] ===================== [PASSED] guc_dbm =====================
[08:40:56] =================== guc_idm (6 subtests) ===================
[08:40:56] [PASSED] bad_init
[08:40:56] [PASSED] no_init
[08:40:56] [PASSED] init_fini
[08:40:56] [PASSED] check_used
[08:40:56] [PASSED] check_quota
[08:40:56] [PASSED] check_all
[08:40:56] ===================== [PASSED] guc_idm =====================
[08:40:56] ================== no_relay (3 subtests) ===================
[08:40:56] [PASSED] xe_drops_guc2pf_if_not_ready
[08:40:56] [PASSED] xe_drops_guc2vf_if_not_ready
[08:40:56] [PASSED] xe_rejects_send_if_not_ready
[08:40:56] ==================== [PASSED] no_relay =====================
[08:40:56] ================== pf_relay (14 subtests) ==================
[08:40:56] [PASSED] pf_rejects_guc2pf_too_short
[08:40:56] [PASSED] pf_rejects_guc2pf_too_long
[08:40:56] [PASSED] pf_rejects_guc2pf_no_payload
[08:40:56] [PASSED] pf_fails_no_payload
[08:40:56] [PASSED] pf_fails_bad_origin
[08:40:56] [PASSED] pf_fails_bad_type
[08:40:56] [PASSED] pf_txn_reports_error
[08:40:56] [PASSED] pf_txn_sends_pf2guc
[08:40:56] [PASSED] pf_sends_pf2guc
[08:40:56] [SKIPPED] pf_loopback_nop
[08:40:56] [SKIPPED] pf_loopback_echo
[08:40:56] [SKIPPED] pf_loopback_fail
[08:40:56] [SKIPPED] pf_loopback_busy
[08:40:56] [SKIPPED] pf_loopback_retry
[08:40:56] ==================== [PASSED] pf_relay =====================
[08:40:56] ================== vf_relay (3 subtests) ===================
[08:40:56] [PASSED] vf_rejects_guc2vf_too_short
[08:40:56] [PASSED] vf_rejects_guc2vf_too_long
[08:40:56] [PASSED] vf_rejects_guc2vf_no_payload
[08:40:56] ==================== [PASSED] vf_relay =====================
[08:40:56] ================= pf_service (11 subtests) =================
[08:40:56] [PASSED] pf_negotiate_any
[08:40:56] [PASSED] pf_negotiate_base_match
[08:40:56] [PASSED] pf_negotiate_base_newer
[08:40:56] [PASSED] pf_negotiate_base_next
[08:40:56] [SKIPPED] pf_negotiate_base_older
[08:40:56] [PASSED] pf_negotiate_base_prev
[08:40:56] [PASSED] pf_negotiate_latest_match
[08:40:56] [PASSED] pf_negotiate_latest_newer
[08:40:56] [PASSED] pf_negotiate_latest_next
[08:40:56] [SKIPPED] pf_negotiate_latest_older
[08:40:56] [SKIPPED] pf_negotiate_latest_prev
[08:40:56] =================== [PASSED] pf_service ====================
[08:40:56] ===================== lmtt (1 subtest) =====================
[08:40:56] ======================== test_ops =========================
[08:40:56] [PASSED] 2-level
[08:40:56] [PASSED] multi-level
[08:40:56] ==================== [PASSED] test_ops =====================
[08:40:56] ====================== [PASSED] lmtt =======================
[08:40:56] =================== xe_mocs (2 subtests) ===================
[08:40:56] ================ xe_live_mocs_kernel_kunit ================
[08:40:56] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[08:40:56] ================ xe_live_mocs_reset_kunit =================
[08:40:56] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[08:40:56] ==================== [SKIPPED] xe_mocs =====================
[08:40:56] ================= xe_migrate (2 subtests) ==================
[08:40:56] ================= xe_migrate_sanity_kunit =================
[08:40:56] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[08:40:56] ================== xe_validate_ccs_kunit ==================
[08:40:56] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[08:40:56] =================== [SKIPPED] xe_migrate ===================
[08:40:56] ================== xe_dma_buf (1 subtest) ==================
[08:40:56] ==================== xe_dma_buf_kunit =====================
[08:40:56] ================ [SKIPPED] xe_dma_buf_kunit ================
[08:40:56] =================== [SKIPPED] xe_dma_buf ===================
[08:40:56] ================= xe_bo_shrink (1 subtest) =================
[08:40:56] =================== xe_bo_shrink_kunit ====================
[08:40:56] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[08:40:56] ================== [SKIPPED] xe_bo_shrink ==================
[08:40:56] ==================== xe_bo (2 subtests) ====================
[08:40:56] ================== xe_ccs_migrate_kunit ===================
[08:40:56] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
stty: 'standard input': Inappropriate ioctl for device
[08:40:56] ==================== xe_bo_evict_kunit ====================
[08:40:56] =============== [SKIPPED] xe_bo_evict_kunit ================
[08:40:56] ===================== [SKIPPED] xe_bo ======================
[08:40:56] ==================== args (11 subtests) ====================
[08:40:56] [PASSED] count_args_test
[08:40:56] [PASSED] call_args_example
[08:40:56] [PASSED] call_args_test
[08:40:56] [PASSED] drop_first_arg_example
[08:40:56] [PASSED] drop_first_arg_test
[08:40:56] [PASSED] first_arg_example
[08:40:56] [PASSED] first_arg_test
[08:40:56] [PASSED] last_arg_example
[08:40:56] [PASSED] last_arg_test
[08:40:56] [PASSED] pick_arg_example
[08:40:56] [PASSED] sep_comma_example
[08:40:56] ====================== [PASSED] args =======================
[08:40:56] =================== xe_pci (2 subtests) ====================
[08:40:56] [PASSED] xe_gmdid_graphics_ip
[08:40:56] [PASSED] xe_gmdid_media_ip
[08:40:56] ===================== [PASSED] xe_pci ======================
[08:40:56] =================== xe_rtp (2 subtests) ====================
[08:40:56] =============== xe_rtp_process_to_sr_tests ================
[08:40:56] [PASSED] coalesce-same-reg
[08:40:56] [PASSED] no-match-no-add
[08:40:56] [PASSED] match-or
[08:40:56] [PASSED] match-or-xfail
[08:40:56] [PASSED] no-match-no-add-multiple-rules
[08:40:56] [PASSED] two-regs-two-entries
[08:40:56] [PASSED] clr-one-set-other
[08:40:56] [PASSED] set-field
[08:40:56] [PASSED] conflict-duplicate
[08:40:56] [PASSED] conflict-not-disjoint
[08:40:56] [PASSED] conflict-reg-type
[08:40:56] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[08:40:56] ================== xe_rtp_process_tests ===================
[08:40:56] [PASSED] active1
[08:40:56] [PASSED] active2
[08:40:56] [PASSED] active-inactive
[08:40:56] [PASSED] inactive-active
[08:40:56] [PASSED] inactive-1st_or_active-inactive
[08:40:56] [PASSED] inactive-2nd_or_active-inactive
[08:40:56] [PASSED] inactive-last_or_active-inactive
[08:40:56] [PASSED] inactive-no_or_active-inactive
[08:40:56] ============== [PASSED] xe_rtp_process_tests ===============
[08:40:56] ===================== [PASSED] xe_rtp ======================
[08:40:56] ==================== xe_wa (1 subtest) =====================
[08:40:56] ======================== xe_wa_gt =========================
[08:40:56] [PASSED] TIGERLAKE (B0)
[08:40:56] [PASSED] DG1 (A0)
[08:40:56] [PASSED] DG1 (B0)
[08:40:56] [PASSED] ALDERLAKE_S (A0)
[08:40:56] [PASSED] ALDERLAKE_S (B0)
[08:40:56] [PASSED] ALDERLAKE_S (C0)
[08:40:56] [PASSED] ALDERLAKE_S (D0)
[08:40:56] [PASSED] ALDERLAKE_P (A0)
[08:40:56] [PASSED] ALDERLAKE_P (B0)
[08:40:56] [PASSED] ALDERLAKE_P (C0)
[08:40:56] [PASSED] ALDERLAKE_S_RPLS (D0)
[08:40:56] [PASSED] ALDERLAKE_P_RPLU (E0)
[08:40:56] [PASSED] DG2_G10 (C0)
[08:40:56] [PASSED] DG2_G11 (B1)
[08:40:56] [PASSED] DG2_G12 (A1)
[08:40:56] [PASSED] METEORLAKE (g:A0, m:A0)
[08:40:56] [PASSED] METEORLAKE (g:A0, m:A0)
[08:40:56] [PASSED] METEORLAKE (g:A0, m:A0)
[08:40:56] [PASSED] LUNARLAKE (g:A0, m:A0)
[08:40:56] [PASSED] LUNARLAKE (g:B0, m:A0)
[08:40:56] [PASSED] BATTLEMAGE (g:A0, m:A1)
[08:40:56] ==================== [PASSED] xe_wa_gt =====================
[08:40:56] ====================== [PASSED] xe_wa ======================
[08:40:56] ============================================================
[08:40:56] Testing complete. Ran 133 tests: passed: 117, skipped: 16
[08:40:56] Elapsed time: 30.964s total, 4.245s configuring, 26.453s building, 0.248s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[08:40:56] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[08:40:58] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json ARCH=um O=.kunit --jobs=48
../lib/iomap.c:156:5: warning: no previous prototype for ‘ioread64_lo_hi’ [-Wmissing-prototypes]
156 | u64 ioread64_lo_hi(const void __iomem *addr)
| ^~~~~~~~~~~~~~
../lib/iomap.c:163:5: warning: no previous prototype for ‘ioread64_hi_lo’ [-Wmissing-prototypes]
163 | u64 ioread64_hi_lo(const void __iomem *addr)
| ^~~~~~~~~~~~~~
../lib/iomap.c:170:5: warning: no previous prototype for ‘ioread64be_lo_hi’ [-Wmissing-prototypes]
170 | u64 ioread64be_lo_hi(const void __iomem *addr)
| ^~~~~~~~~~~~~~~~
../lib/iomap.c:178:5: warning: no previous prototype for ‘ioread64be_hi_lo’ [-Wmissing-prototypes]
178 | u64 ioread64be_hi_lo(const void __iomem *addr)
| ^~~~~~~~~~~~~~~~
../lib/iomap.c:264:6: warning: no previous prototype for ‘iowrite64_lo_hi’ [-Wmissing-prototypes]
264 | void iowrite64_lo_hi(u64 val, void __iomem *addr)
| ^~~~~~~~~~~~~~~
../lib/iomap.c:272:6: warning: no previous prototype for ‘iowrite64_hi_lo’ [-Wmissing-prototypes]
272 | void iowrite64_hi_lo(u64 val, void __iomem *addr)
| ^~~~~~~~~~~~~~~
../lib/iomap.c:280:6: warning: no previous prototype for ‘iowrite64be_lo_hi’ [-Wmissing-prototypes]
280 | void iowrite64be_lo_hi(u64 val, void __iomem *addr)
| ^~~~~~~~~~~~~~~~~
../lib/iomap.c:288:6: warning: no previous prototype for ‘iowrite64be_hi_lo’ [-Wmissing-prototypes]
288 | void iowrite64be_hi_lo(u64 val, void __iomem *addr)
| ^~~~~~~~~~~~~~~~~
[08:41:19] Starting KUnit Kernel (1/1)...
[08:41:19] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[08:41:19] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[08:41:19] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[08:41:19] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[08:41:19] =========== drm_validate_clone_mode (2 subtests) ===========
[08:41:19] ============== drm_test_check_in_clone_mode ===============
[08:41:19] [PASSED] in_clone_mode
[08:41:19] [PASSED] not_in_clone_mode
[08:41:19] ========== [PASSED] drm_test_check_in_clone_mode ===========
[08:41:19] =============== drm_test_check_valid_clones ===============
[08:41:19] [PASSED] not_in_clone_mode
[08:41:19] [PASSED] valid_clone
[08:41:19] [PASSED] invalid_clone
[08:41:19] =========== [PASSED] drm_test_check_valid_clones ===========
[08:41:19] ============= [PASSED] drm_validate_clone_mode =============
[08:41:19] ============= drm_validate_modeset (1 subtest) =============
[08:41:19] [PASSED] drm_test_check_connector_changed_modeset
[08:41:19] ============== [PASSED] drm_validate_modeset ===============
[08:41:19] ====== drm_test_bridge_get_current_state (2 subtests) ======
[08:41:19] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[08:41:19] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[08:41:19] ======== [PASSED] drm_test_bridge_get_current_state ========
[08:41:19] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[08:41:19] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[08:41:19] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[08:41:19] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[08:41:19] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[08:41:19] ================== drm_buddy (7 subtests) ==================
[08:41:19] [PASSED] drm_test_buddy_alloc_limit
[08:41:19] [PASSED] drm_test_buddy_alloc_optimistic
[08:41:19] [PASSED] drm_test_buddy_alloc_pessimistic
[08:41:19] [PASSED] drm_test_buddy_alloc_pathological
[08:41:19] [PASSED] drm_test_buddy_alloc_contiguous
[08:41:19] [PASSED] drm_test_buddy_alloc_clear
[08:41:19] [PASSED] drm_test_buddy_alloc_range_bias
[08:41:19] ==================== [PASSED] drm_buddy ====================
[08:41:19] ============= drm_cmdline_parser (40 subtests) =============
[08:41:19] [PASSED] drm_test_cmdline_force_d_only
[08:41:19] [PASSED] drm_test_cmdline_force_D_only_dvi
[08:41:19] [PASSED] drm_test_cmdline_force_D_only_hdmi
[08:41:19] [PASSED] drm_test_cmdline_force_D_only_not_digital
[08:41:19] [PASSED] drm_test_cmdline_force_e_only
[08:41:19] [PASSED] drm_test_cmdline_res
[08:41:19] [PASSED] drm_test_cmdline_res_vesa
[08:41:19] [PASSED] drm_test_cmdline_res_vesa_rblank
[08:41:19] [PASSED] drm_test_cmdline_res_rblank
[08:41:19] [PASSED] drm_test_cmdline_res_bpp
[08:41:19] [PASSED] drm_test_cmdline_res_refresh
[08:41:19] [PASSED] drm_test_cmdline_res_bpp_refresh
[08:41:19] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[08:41:19] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[08:41:19] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[08:41:19] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[08:41:19] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[08:41:19] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[08:41:19] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[08:41:19] [PASSED] drm_test_cmdline_res_margins_force_on
[08:41:19] [PASSED] drm_test_cmdline_res_vesa_margins
[08:41:19] [PASSED] drm_test_cmdline_name
[08:41:19] [PASSED] drm_test_cmdline_name_bpp
[08:41:19] [PASSED] drm_test_cmdline_name_option
[08:41:19] [PASSED] drm_test_cmdline_name_bpp_option
[08:41:19] [PASSED] drm_test_cmdline_rotate_0
[08:41:19] [PASSED] drm_test_cmdline_rotate_90
[08:41:19] [PASSED] drm_test_cmdline_rotate_180
[08:41:19] [PASSED] drm_test_cmdline_rotate_270
[08:41:19] [PASSED] drm_test_cmdline_hmirror
[08:41:19] [PASSED] drm_test_cmdline_vmirror
[08:41:19] [PASSED] drm_test_cmdline_margin_options
[08:41:19] [PASSED] drm_test_cmdline_multiple_options
[08:41:19] [PASSED] drm_test_cmdline_bpp_extra_and_option
[08:41:19] [PASSED] drm_test_cmdline_extra_and_option
[08:41:19] [PASSED] drm_test_cmdline_freestanding_options
[08:41:19] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[08:41:19] [PASSED] drm_test_cmdline_panel_orientation
[08:41:19] ================ drm_test_cmdline_invalid =================
[08:41:19] [PASSED] margin_only
[08:41:19] [PASSED] interlace_only
[08:41:19] [PASSED] res_missing_x
[08:41:19] [PASSED] res_missing_y
[08:41:19] [PASSED] res_bad_y
[08:41:19] [PASSED] res_missing_y_bpp
[08:41:19] [PASSED] res_bad_bpp
[08:41:19] [PASSED] res_bad_refresh
[08:41:19] [PASSED] res_bpp_refresh_force_on_off
[08:41:19] [PASSED] res_invalid_mode
[08:41:19] [PASSED] res_bpp_wrong_place_mode
[08:41:19] [PASSED] name_bpp_refresh
[08:41:19] [PASSED] name_refresh
[08:41:19] [PASSED] name_refresh_wrong_mode
[08:41:19] [PASSED] name_refresh_invalid_mode
[08:41:19] [PASSED] rotate_multiple
[08:41:19] [PASSED] rotate_invalid_val
[08:41:19] [PASSED] rotate_truncated
[08:41:19] [PASSED] invalid_option
[08:41:19] [PASSED] invalid_tv_option
[08:41:19] [PASSED] truncated_tv_option
[08:41:19] ============ [PASSED] drm_test_cmdline_invalid =============
[08:41:19] =============== drm_test_cmdline_tv_options ===============
[08:41:19] [PASSED] NTSC
[08:41:19] [PASSED] NTSC_443
[08:41:19] [PASSED] NTSC_J
[08:41:19] [PASSED] PAL
[08:41:19] [PASSED] PAL_M
[08:41:19] [PASSED] PAL_N
[08:41:19] [PASSED] SECAM
[08:41:19] [PASSED] MONO_525
[08:41:19] [PASSED] MONO_625
[08:41:19] =========== [PASSED] drm_test_cmdline_tv_options ===========
[08:41:19] =============== [PASSED] drm_cmdline_parser ================
[08:41:19] ========== drmm_connector_hdmi_init (20 subtests) ==========
[08:41:19] [PASSED] drm_test_connector_hdmi_init_valid
[08:41:19] [PASSED] drm_test_connector_hdmi_init_bpc_8
[08:41:19] [PASSED] drm_test_connector_hdmi_init_bpc_10
[08:41:19] [PASSED] drm_test_connector_hdmi_init_bpc_12
[08:41:19] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[08:41:19] [PASSED] drm_test_connector_hdmi_init_bpc_null
[08:41:19] [PASSED] drm_test_connector_hdmi_init_formats_empty
[08:41:19] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[08:41:19] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[08:41:19] [PASSED] supported_formats=0x9 yuv420_allowed=1
[08:41:19] [PASSED] supported_formats=0x9 yuv420_allowed=0
[08:41:19] [PASSED] supported_formats=0x3 yuv420_allowed=1
[08:41:19] [PASSED] supported_formats=0x3 yuv420_allowed=0
[08:41:19] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[08:41:19] [PASSED] drm_test_connector_hdmi_init_null_ddc
[08:41:19] [PASSED] drm_test_connector_hdmi_init_null_product
[08:41:19] [PASSED] drm_test_connector_hdmi_init_null_vendor
[08:41:19] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[08:41:19] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[08:41:19] [PASSED] drm_test_connector_hdmi_init_product_valid
[08:41:19] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[08:41:19] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[08:41:19] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[08:41:19] ========= drm_test_connector_hdmi_init_type_valid =========
[08:41:19] [PASSED] HDMI-A
[08:41:19] [PASSED] HDMI-B
[08:41:19] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[08:41:19] ======== drm_test_connector_hdmi_init_type_invalid ========
[08:41:19] [PASSED] Unknown
[08:41:19] [PASSED] VGA
[08:41:19] [PASSED] DVI-I
[08:41:19] [PASSED] DVI-D
[08:41:19] [PASSED] DVI-A
[08:41:19] [PASSED] Composite
[08:41:19] [PASSED] SVIDEO
[08:41:19] [PASSED] LVDS
[08:41:19] [PASSED] Component
[08:41:19] [PASSED] DIN
[08:41:19] [PASSED] DP
[08:41:19] [PASSED] TV
[08:41:19] [PASSED] eDP
[08:41:19] [PASSED] Virtual
[08:41:19] [PASSED] DSI
[08:41:19] [PASSED] DPI
[08:41:19] [PASSED] Writeback
[08:41:19] [PASSED] SPI
[08:41:19] [PASSED] USB
[08:41:19] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[08:41:19] ============ [PASSED] drmm_connector_hdmi_init =============
[08:41:19] ============= drmm_connector_init (3 subtests) =============
[08:41:19] [PASSED] drm_test_drmm_connector_init
[08:41:19] [PASSED] drm_test_drmm_connector_init_null_ddc
[08:41:19] ========= drm_test_drmm_connector_init_type_valid =========
[08:41:19] [PASSED] Unknown
[08:41:19] [PASSED] VGA
[08:41:19] [PASSED] DVI-I
[08:41:19] [PASSED] DVI-D
[08:41:19] [PASSED] DVI-A
[08:41:19] [PASSED] Composite
[08:41:19] [PASSED] SVIDEO
[08:41:19] [PASSED] LVDS
[08:41:19] [PASSED] Component
[08:41:19] [PASSED] DIN
[08:41:19] [PASSED] DP
[08:41:19] [PASSED] HDMI-A
[08:41:19] [PASSED] HDMI-B
[08:41:19] [PASSED] TV
[08:41:19] [PASSED] eDP
[08:41:19] [PASSED] Virtual
[08:41:19] [PASSED] DSI
[08:41:19] [PASSED] DPI
[08:41:19] [PASSED] Writeback
[08:41:19] [PASSED] SPI
[08:41:19] [PASSED] USB
[08:41:19] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[08:41:19] =============== [PASSED] drmm_connector_init ===============
[08:41:19] ========= drm_connector_dynamic_init (6 subtests) ==========
[08:41:19] [PASSED] drm_test_drm_connector_dynamic_init
[08:41:19] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[08:41:19] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[08:41:19] [PASSED] drm_test_drm_connector_dynamic_init_properties
[08:41:19] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[08:41:19] [PASSED] Unknown
[08:41:19] [PASSED] VGA
[08:41:19] [PASSED] DVI-I
[08:41:19] [PASSED] DVI-D
[08:41:19] [PASSED] DVI-A
[08:41:19] [PASSED] Composite
[08:41:19] [PASSED] SVIDEO
[08:41:19] [PASSED] LVDS
[08:41:19] [PASSED] Component
[08:41:19] [PASSED] DIN
[08:41:19] [PASSED] DP
[08:41:19] [PASSED] HDMI-A
[08:41:19] [PASSED] HDMI-B
[08:41:19] [PASSED] TV
[08:41:19] [PASSED] eDP
[08:41:19] [PASSED] Virtual
[08:41:19] [PASSED] DSI
[08:41:19] [PASSED] DPI
[08:41:19] [PASSED] Writeback
[08:41:19] [PASSED] SPI
[08:41:19] [PASSED] USB
[08:41:19] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[08:41:19] ======== drm_test_drm_connector_dynamic_init_name =========
[08:41:19] [PASSED] Unknown
[08:41:19] [PASSED] VGA
[08:41:19] [PASSED] DVI-I
[08:41:19] [PASSED] DVI-D
[08:41:19] [PASSED] DVI-A
[08:41:19] [PASSED] Composite
[08:41:19] [PASSED] SVIDEO
[08:41:19] [PASSED] LVDS
[08:41:19] [PASSED] Component
[08:41:19] [PASSED] DIN
[08:41:19] [PASSED] DP
[08:41:19] [PASSED] HDMI-A
[08:41:19] [PASSED] HDMI-B
[08:41:19] [PASSED] TV
[08:41:19] [PASSED] eDP
[08:41:19] [PASSED] Virtual
[08:41:19] [PASSED] DSI
[08:41:19] [PASSED] DPI
[08:41:19] [PASSED] Writeback
[08:41:19] [PASSED] SPI
[08:41:19] [PASSED] USB
[08:41:19] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[08:41:19] =========== [PASSED] drm_connector_dynamic_init ============
[08:41:19] ==== drm_connector_dynamic_register_early (4 subtests) =====
[08:41:19] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[08:41:19] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[08:41:19] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[08:41:19] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[08:41:19] ====== [PASSED] drm_connector_dynamic_register_early =======
[08:41:19] ======= drm_connector_dynamic_register (7 subtests) ========
[08:41:19] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[08:41:19] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[08:41:19] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[08:41:19] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[08:41:19] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[08:41:19] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[08:41:19] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[08:41:19] ========= [PASSED] drm_connector_dynamic_register ==========
[08:41:19] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[08:41:19] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[08:41:19] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[08:41:19] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[08:41:19] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[08:41:19] ========== drm_test_get_tv_mode_from_name_valid ===========
[08:41:19] [PASSED] NTSC
[08:41:19] [PASSED] NTSC-443
[08:41:19] [PASSED] NTSC-J
[08:41:19] [PASSED] PAL
[08:41:19] [PASSED] PAL-M
[08:41:19] [PASSED] PAL-N
[08:41:19] [PASSED] SECAM
[08:41:19] [PASSED] Mono
[08:41:19] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[08:41:19] [PASSED] drm_test_get_tv_mode_from_name_truncated
[08:41:19] ============ [PASSED] drm_get_tv_mode_from_name ============
[08:41:19] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[08:41:19] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[08:41:19] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[08:41:19] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[08:41:19] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[08:41:19] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[08:41:19] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[08:41:19] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[08:41:19] [PASSED] VIC 96
[08:41:19] [PASSED] VIC 97
[08:41:19] [PASSED] VIC 101
[08:41:19] [PASSED] VIC 102
[08:41:19] [PASSED] VIC 106
[08:41:19] [PASSED] VIC 107
[08:41:19] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[08:41:19] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[08:41:19] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[08:41:19] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[08:41:19] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[08:41:19] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[08:41:19] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[08:41:19] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[08:41:19] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[08:41:19] [PASSED] Automatic
[08:41:19] [PASSED] Full
[08:41:19] [PASSED] Limited 16:235
[08:41:19] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[08:41:19] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[08:41:19] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[08:41:19] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[08:41:19] === drm_test_drm_hdmi_connector_get_output_format_name ====
[08:41:19] [PASSED] RGB
[08:41:19] [PASSED] YUV 4:2:0
[08:41:19] [PASSED] YUV 4:2:2
[08:41:19] [PASSED] YUV 4:4:4
[08:41:19] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[08:41:19] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[08:41:19] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[08:41:19] ============= drm_damage_helper (21 subtests) ==============
[08:41:19] [PASSED] drm_test_damage_iter_no_damage
[08:41:19] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[08:41:19] [PASSED] drm_test_damage_iter_no_damage_src_moved
[08:41:19] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[08:41:19] [PASSED] drm_test_damage_iter_no_damage_not_visible
[08:41:19] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[08:41:19] [PASSED] drm_test_damage_iter_no_damage_no_fb
[08:41:19] [PASSED] drm_test_damage_iter_simple_damage
[08:41:19] [PASSED] drm_test_damage_iter_single_damage
[08:41:19] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[08:41:19] [PASSED] drm_test_damage_iter_single_damage_outside_src
[08:41:19] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[08:41:19] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[08:41:19] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[08:41:19] [PASSED] drm_test_damage_iter_single_damage_src_moved
[08:41:19] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[08:41:19] [PASSED] drm_test_damage_iter_damage
[08:41:19] [PASSED] drm_test_damage_iter_damage_one_intersect
[08:41:19] [PASSED] drm_test_damage_iter_damage_one_outside
[08:41:19] [PASSED] drm_test_damage_iter_damage_src_moved
[08:41:19] [PASSED] drm_test_damage_iter_damage_not_visible
[08:41:19] ================ [PASSED] drm_damage_helper ================
[08:41:19] ============== drm_dp_mst_helper (3 subtests) ==============
[08:41:19] ============== drm_test_dp_mst_calc_pbn_mode ==============
[08:41:19] [PASSED] Clock 154000 BPP 30 DSC disabled
[08:41:19] [PASSED] Clock 234000 BPP 30 DSC disabled
[08:41:19] [PASSED] Clock 297000 BPP 24 DSC disabled
[08:41:19] [PASSED] Clock 332880 BPP 24 DSC enabled
[08:41:19] [PASSED] Clock 324540 BPP 24 DSC enabled
[08:41:19] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[08:41:19] ============== drm_test_dp_mst_calc_pbn_div ===============
[08:41:19] [PASSED] Link rate 2000000 lane count 4
[08:41:19] [PASSED] Link rate 2000000 lane count 2
[08:41:19] [PASSED] Link rate 2000000 lane count 1
[08:41:19] [PASSED] Link rate 1350000 lane count 4
[08:41:19] [PASSED] Link rate 1350000 lane count 2
[08:41:19] [PASSED] Link rate 1350000 lane count 1
[08:41:19] [PASSED] Link rate 1000000 lane count 4
[08:41:19] [PASSED] Link rate 1000000 lane count 2
[08:41:19] [PASSED] Link rate 1000000 lane count 1
[08:41:19] [PASSED] Link rate 810000 lane count 4
[08:41:19] [PASSED] Link rate 810000 lane count 2
[08:41:19] [PASSED] Link rate 810000 lane count 1
[08:41:19] [PASSED] Link rate 540000 lane count 4
[08:41:19] [PASSED] Link rate 540000 lane count 2
[08:41:19] [PASSED] Link rate 540000 lane count 1
[08:41:19] [PASSED] Link rate 270000 lane count 4
[08:41:19] [PASSED] Link rate 270000 lane count 2
[08:41:19] [PASSED] Link rate 270000 lane count 1
[08:41:19] [PASSED] Link rate 162000 lane count 4
[08:41:19] [PASSED] Link rate 162000 lane count 2
[08:41:19] [PASSED] Link rate 162000 lane count 1
[08:41:19] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[08:41:19] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[08:41:19] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[08:41:19] [PASSED] DP_POWER_UP_PHY with port number
[08:41:19] [PASSED] DP_POWER_DOWN_PHY with port number
[08:41:19] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[08:41:19] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[08:41:19] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[08:41:19] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[08:41:19] [PASSED] DP_QUERY_PAYLOAD with port number
[08:41:19] [PASSED] DP_QUERY_PAYLOAD with VCPI
[08:41:19] [PASSED] DP_REMOTE_DPCD_READ with port number
[08:41:19] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[08:41:19] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[08:41:19] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[08:41:19] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[08:41:19] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[08:41:19] [PASSED] DP_REMOTE_I2C_READ with port number
[08:41:19] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[08:41:19] [PASSED] DP_REMOTE_I2C_READ with transactions array
[08:41:19] [PASSED] DP_REMOTE_I2C_WRITE with port number
[08:41:19] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[08:41:19] [PASSED] DP_REMOTE_I2C_WRITE with data array
[08:41:19] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[08:41:19] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[08:41:19] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[08:41:19] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[08:41:19] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[08:41:19] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[08:41:19] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[08:41:19] ================ [PASSED] drm_dp_mst_helper ================
[08:41:19] ================== drm_exec (7 subtests) ===================
[08:41:19] [PASSED] sanitycheck
[08:41:19] [PASSED] test_lock
[08:41:19] [PASSED] test_lock_unlock
[08:41:19] [PASSED] test_duplicates
[08:41:19] [PASSED] test_prepare
[08:41:19] [PASSED] test_prepare_array
[08:41:19] [PASSED] test_multiple_loops
[08:41:19] ==================== [PASSED] drm_exec =====================
[08:41:19] =========== drm_format_helper_test (18 subtests) ===========
[08:41:19] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[08:41:19] [PASSED] single_pixel_source_buffer
[08:41:19] [PASSED] single_pixel_clip_rectangle
[08:41:19] [PASSED] well_known_colors
[08:41:19] [PASSED] destination_pitch
[08:41:19] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[08:41:19] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[08:41:19] [PASSED] single_pixel_source_buffer
[08:41:19] [PASSED] single_pixel_clip_rectangle
[08:41:19] [PASSED] well_known_colors
[08:41:19] [PASSED] destination_pitch
[08:41:19] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[08:41:19] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[08:41:19] [PASSED] single_pixel_source_buffer
[08:41:19] [PASSED] single_pixel_clip_rectangle
[08:41:19] [PASSED] well_known_colors
[08:41:19] [PASSED] destination_pitch
[08:41:19] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[08:41:19] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[08:41:19] [PASSED] single_pixel_source_buffer
[08:41:19] [PASSED] single_pixel_clip_rectangle
[08:41:19] [PASSED] well_known_colors
[08:41:19] [PASSED] destination_pitch
[08:41:19] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[08:41:19] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[08:41:19] [PASSED] single_pixel_source_buffer
[08:41:19] [PASSED] single_pixel_clip_rectangle
[08:41:19] [PASSED] well_known_colors
[08:41:19] [PASSED] destination_pitch
[08:41:19] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[08:41:19] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[08:41:19] [PASSED] single_pixel_source_buffer
[08:41:19] [PASSED] single_pixel_clip_rectangle
[08:41:19] [PASSED] well_known_colors
[08:41:19] [PASSED] destination_pitch
[08:41:19] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[08:41:19] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[08:41:19] [PASSED] single_pixel_source_buffer
[08:41:19] [PASSED] single_pixel_clip_rectangle
[08:41:19] [PASSED] well_known_colors
[08:41:19] [PASSED] destination_pitch
[08:41:19] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[08:41:19] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[08:41:19] [PASSED] single_pixel_source_buffer
[08:41:19] [PASSED] single_pixel_clip_rectangle
[08:41:19] [PASSED] well_known_colors
[08:41:19] [PASSED] destination_pitch
[08:41:19] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[08:41:19] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[08:41:19] [PASSED] single_pixel_source_buffer
[08:41:19] [PASSED] single_pixel_clip_rectangle
[08:41:19] [PASSED] well_known_colors
[08:41:19] [PASSED] destination_pitch
[08:41:19] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[08:41:19] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[08:41:19] [PASSED] single_pixel_source_buffer
[08:41:19] [PASSED] single_pixel_clip_rectangle
[08:41:19] [PASSED] well_known_colors
[08:41:19] [PASSED] destination_pitch
[08:41:19] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[08:41:19] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[08:41:19] [PASSED] single_pixel_source_buffer
[08:41:19] [PASSED] single_pixel_clip_rectangle
[08:41:19] [PASSED] well_known_colors
[08:41:19] [PASSED] destination_pitch
[08:41:19] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[08:41:19] ============== drm_test_fb_xrgb8888_to_mono ===============
[08:41:19] [PASSED] single_pixel_source_buffer
[08:41:19] [PASSED] single_pixel_clip_rectangle
[08:41:19] [PASSED] well_known_colors
[08:41:19] [PASSED] destination_pitch
[08:41:19] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[08:41:19] ==================== drm_test_fb_swab =====================
[08:41:19] [PASSED] single_pixel_source_buffer
[08:41:19] [PASSED] single_pixel_clip_rectangle
[08:41:19] [PASSED] well_known_colors
[08:41:19] [PASSED] destination_pitch
[08:41:19] ================ [PASSED] drm_test_fb_swab =================
[08:41:19] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[08:41:19] [PASSED] single_pixel_source_buffer
[08:41:19] [PASSED] single_pixel_clip_rectangle
[08:41:19] [PASSED] well_known_colors
[08:41:19] [PASSED] destination_pitch
[08:41:19] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[08:41:19] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[08:41:19] [PASSED] single_pixel_source_buffer
[08:41:19] [PASSED] single_pixel_clip_rectangle
[08:41:19] [PASSED] well_known_colors
[08:41:19] [PASSED] destination_pitch
[08:41:19] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[08:41:19] ================= drm_test_fb_clip_offset =================
[08:41:19] [PASSED] pass through
[08:41:19] [PASSED] horizontal offset
[08:41:19] [PASSED] vertical offset
[08:41:19] [PASSED] horizontal and vertical offset
[08:41:19] [PASSED] horizontal offset (custom pitch)
[08:41:19] [PASSED] vertical offset (custom pitch)
[08:41:19] [PASSED] horizontal and vertical offset (custom pitch)
[08:41:19] ============= [PASSED] drm_test_fb_clip_offset =============
[08:41:19] ============== drm_test_fb_build_fourcc_list ==============
[08:41:19] [PASSED] no native formats
[08:41:19] [PASSED] XRGB8888 as native format
[08:41:19] [PASSED] remove duplicates
[08:41:19] [PASSED] convert alpha formats
[08:41:19] [PASSED] random formats
[08:41:19] ========== [PASSED] drm_test_fb_build_fourcc_list ==========
[08:41:19] =================== drm_test_fb_memcpy ====================
[08:41:19] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[08:41:19] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[08:41:19] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[08:41:19] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[08:41:19] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[08:41:19] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[08:41:19] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[08:41:19] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[08:41:19] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[08:41:19] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[08:41:19] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[08:41:19] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[08:41:19] =============== [PASSED] drm_test_fb_memcpy ================
[08:41:19] ============= [PASSED] drm_format_helper_test ==============
[08:41:19] ================= drm_format (18 subtests) =================
[08:41:19] [PASSED] drm_test_format_block_width_invalid
[08:41:19] [PASSED] drm_test_format_block_width_one_plane
[08:41:19] [PASSED] drm_test_format_block_width_two_plane
[08:41:19] [PASSED] drm_test_format_block_width_three_plane
[08:41:19] [PASSED] drm_test_format_block_width_tiled
[08:41:19] [PASSED] drm_test_format_block_height_invalid
[08:41:19] [PASSED] drm_test_format_block_height_one_plane
[08:41:19] [PASSED] drm_test_format_block_height_two_plane
[08:41:19] [PASSED] drm_test_format_block_height_three_plane
[08:41:19] [PASSED] drm_test_format_block_height_tiled
[08:41:19] [PASSED] drm_test_format_min_pitch_invalid
[08:41:19] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[08:41:19] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[08:41:19] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[08:41:19] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[08:41:19] [PASSED] drm_test_format_min_pitch_two_plane
[08:41:19] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[08:41:19] [PASSED] drm_test_format_min_pitch_tiled
[08:41:19] =================== [PASSED] drm_format ====================
[08:41:19] ============== drm_framebuffer (10 subtests) ===============
[08:41:19] ========== drm_test_framebuffer_check_src_coords ==========
[08:41:19] [PASSED] Success: source fits into fb
[08:41:19] [PASSED] Fail: overflowing fb with x-axis coordinate
[08:41:19] [PASSED] Fail: overflowing fb with y-axis coordinate
[08:41:19] [PASSED] Fail: overflowing fb with source width
[08:41:19] [PASSED] Fail: overflowing fb with source height
[08:41:19] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[08:41:19] [PASSED] drm_test_framebuffer_cleanup
[08:41:19] =============== drm_test_framebuffer_create ===============
[08:41:19] [PASSED] ABGR8888 normal sizes
[08:41:19] [PASSED] ABGR8888 max sizes
[08:41:19] [PASSED] ABGR8888 pitch greater than min required
[08:41:19] [PASSED] ABGR8888 pitch less than min required
[08:41:19] [PASSED] ABGR8888 Invalid width
[08:41:19] [PASSED] ABGR8888 Invalid buffer handle
[08:41:19] [PASSED] No pixel format
[08:41:19] [PASSED] ABGR8888 Width 0
[08:41:19] [PASSED] ABGR8888 Height 0
[08:41:19] [PASSED] ABGR8888 Out of bound height * pitch combination
[08:41:19] [PASSED] ABGR8888 Large buffer offset
[08:41:19] [PASSED] ABGR8888 Buffer offset for inexistent plane
[08:41:19] [PASSED] ABGR8888 Invalid flag
[08:41:19] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[08:41:19] [PASSED] ABGR8888 Valid buffer modifier
[08:41:19] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[08:41:19] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[08:41:19] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[08:41:19] [PASSED] NV12 Normal sizes
[08:41:19] [PASSED] NV12 Max sizes
[08:41:19] [PASSED] NV12 Invalid pitch
[08:41:19] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[08:41:19] [PASSED] NV12 different modifier per-plane
[08:41:19] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[08:41:19] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[08:41:19] [PASSED] NV12 Modifier for inexistent plane
[08:41:19] [PASSED] NV12 Handle for inexistent plane
[08:41:19] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[08:41:19] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[08:41:19] [PASSED] YVU420 Normal sizes
[08:41:19] [PASSED] YVU420 Max sizes
[08:41:19] [PASSED] YVU420 Invalid pitch
[08:41:19] [PASSED] YVU420 Different pitches
[08:41:19] [PASSED] YVU420 Different buffer offsets/pitches
[08:41:19] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[08:41:19] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[08:41:19] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[08:41:19] [PASSED] YVU420 Valid modifier
[08:41:19] [PASSED] YVU420 Different modifiers per plane
[08:41:19] [PASSED] YVU420 Modifier for inexistent plane
[08:41:19] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[08:41:19] [PASSED] X0L2 Normal sizes
[08:41:19] [PASSED] X0L2 Max sizes
[08:41:19] [PASSED] X0L2 Invalid pitch
[08:41:19] [PASSED] X0L2 Pitch greater than minimum required
[08:41:19] [PASSED] X0L2 Handle for inexistent plane
[08:41:19] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[08:41:19] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[08:41:19] [PASSED] X0L2 Valid modifier
[08:41:19] [PASSED] X0L2 Modifier for inexistent plane
[08:41:19] =========== [PASSED] drm_test_framebuffer_create ===========
[08:41:19] [PASSED] drm_test_framebuffer_free
[08:41:19] [PASSED] drm_test_framebuffer_init
[08:41:19] [PASSED] drm_test_framebuffer_init_bad_format
[08:41:19] [PASSED] drm_test_framebuffer_init_dev_mismatch
[08:41:19] [PASSED] drm_test_framebuffer_lookup
[08:41:19] [PASSED] drm_test_framebuffer_lookup_inexistent
[08:41:19] [PASSED] drm_test_framebuffer_modifiers_not_supported
[08:41:19] ================= [PASSED] drm_framebuffer =================
[08:41:19] ================ drm_gem_shmem (8 subtests) ================
[08:41:19] [PASSED] drm_gem_shmem_test_obj_create
[08:41:19] [PASSED] drm_gem_shmem_test_obj_create_private
[08:41:19] [PASSED] drm_gem_shmem_test_pin_pages
[08:41:19] [PASSED] drm_gem_shmem_test_vmap
[08:41:19] [PASSED] drm_gem_shmem_test_get_pages_sgt
[08:41:19] [PASSED] drm_gem_shmem_test_get_sg_table
[08:41:19] [PASSED] drm_gem_shmem_test_madvise
[08:41:19] [PASSED] drm_gem_shmem_test_purge
[08:41:19] ================== [PASSED] drm_gem_shmem ==================
[08:41:19] === drm_atomic_helper_connector_hdmi_check (23 subtests) ===
[08:41:19] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[08:41:19] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[08:41:19] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[08:41:19] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[08:41:19] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[08:41:19] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[08:41:19] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[08:41:19] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[08:41:19] [PASSED] drm_test_check_disable_connector
[08:41:19] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[08:41:19] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback
[08:41:19] [PASSED] drm_test_check_max_tmds_rate_format_fallback
[08:41:19] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[08:41:19] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[08:41:19] [PASSED] drm_test_check_output_bpc_dvi
[08:41:19] [PASSED] drm_test_check_output_bpc_format_vic_1
[08:41:19] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[08:41:19] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[08:41:19] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[08:41:19] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[08:41:19] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[08:41:19] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[08:41:19] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[08:41:19] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[08:41:19] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[08:41:19] [PASSED] drm_test_check_broadcast_rgb_value
[08:41:19] [PASSED] drm_test_check_bpc_8_value
[08:41:19] [PASSED] drm_test_check_bpc_10_value
[08:41:19] [PASSED] drm_test_check_bpc_12_value
[08:41:19] [PASSED] drm_test_check_format_value
[08:41:19] [PASSED] drm_test_check_tmds_char_value
[08:41:19] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[08:41:19] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[08:41:19] [PASSED] drm_test_check_mode_valid
[08:41:19] [PASSED] drm_test_check_mode_valid_reject
[08:41:19] [PASSED] drm_test_check_mode_valid_reject_rate
[08:41:19] [PASSED] drm_test_check_mode_valid_reject_max_clock
[08:41:19] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[08:41:19] ================= drm_managed (2 subtests) =================
[08:41:19] [PASSED] drm_test_managed_release_action
[08:41:19] [PASSED] drm_test_managed_run_action
[08:41:19] =================== [PASSED] drm_managed ===================
[08:41:19] =================== drm_mm (6 subtests) ====================
[08:41:19] [PASSED] drm_test_mm_init
[08:41:19] [PASSED] drm_test_mm_debug
[08:41:19] [PASSED] drm_test_mm_align32
[08:41:19] [PASSED] drm_test_mm_align64
[08:41:19] [PASSED] drm_test_mm_lowest
[08:41:19] [PASSED] drm_test_mm_highest
[08:41:19] ===================== [PASSED] drm_mm ======================
[08:41:19] ============= drm_modes_analog_tv (5 subtests) =============
[08:41:19] [PASSED] drm_test_modes_analog_tv_mono_576i
[08:41:19] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[08:41:19] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[08:41:19] [PASSED] drm_test_modes_analog_tv_pal_576i
[08:41:19] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[08:41:19] =============== [PASSED] drm_modes_analog_tv ===============
[08:41:19] ============== drm_plane_helper (2 subtests) ===============
[08:41:19] =============== drm_test_check_plane_state ================
[08:41:19] [PASSED] clipping_simple
[08:41:19] [PASSED] clipping_rotate_reflect
[08:41:19] [PASSED] positioning_simple
[08:41:19] [PASSED] upscaling
[08:41:19] [PASSED] downscaling
[08:41:19] [PASSED] rounding1
[08:41:19] [PASSED] rounding2
[08:41:19] [PASSED] rounding3
[08:41:19] [PASSED] rounding4
[08:41:19] =========== [PASSED] drm_test_check_plane_state ============
[08:41:19] =========== drm_test_check_invalid_plane_state ============
[08:41:19] [PASSED] positioning_invalid
[08:41:19] [PASSED] upscaling_invalid
[08:41:19] [PASSED] downscaling_invalid
[08:41:19] ======= [PASSED] drm_test_check_invalid_plane_state ========
[08:41:19] ================ [PASSED] drm_plane_helper =================
[08:41:19] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[08:41:19] ====== drm_test_connector_helper_tv_get_modes_check =======
[08:41:19] [PASSED] None
[08:41:19] [PASSED] PAL
[08:41:19] [PASSED] NTSC
[08:41:19] [PASSED] Both, NTSC Default
[08:41:19] [PASSED] Both, PAL Default
[08:41:19] [PASSED] Both, NTSC Default, with PAL on command-line
[08:41:19] [PASSED] Both, PAL Default, with NTSC on command-line
[08:41:19] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[08:41:19] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[08:41:19] ================== drm_rect (9 subtests) ===================
[08:41:19] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[08:41:19] [PASSED] drm_test_rect_clip_scaled_not_clipped
[08:41:19] [PASSED] drm_test_rect_clip_scaled_clipped
[08:41:19] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[08:41:19] ================= drm_test_rect_intersect =================
[08:41:19] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[08:41:19] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[08:41:19] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[08:41:19] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[08:41:19] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[08:41:19] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[08:41:19] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[08:41:19] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[08:41:19] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[08:41:19] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[08:41:19] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[08:41:19] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[08:41:19] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[08:41:19] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
stty: 'standard input': Inappropriate ioctl for device
[08:41:19] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[08:41:19] ============= [PASSED] drm_test_rect_intersect =============
[08:41:19] ================ drm_test_rect_calc_hscale ================
[08:41:19] [PASSED] normal use
[08:41:19] [PASSED] out of max range
[08:41:19] [PASSED] out of min range
[08:41:19] [PASSED] zero dst
[08:41:19] [PASSED] negative src
[08:41:19] [PASSED] negative dst
[08:41:19] ============ [PASSED] drm_test_rect_calc_hscale ============
[08:41:19] ================ drm_test_rect_calc_vscale ================
[08:41:19] [PASSED] normal use
[08:41:19] [PASSED] out of max range
[08:41:19] [PASSED] out of min range
[08:41:19] [PASSED] zero dst
[08:41:19] [PASSED] negative src
[08:41:19] [PASSED] negative dst
[08:41:19] ============ [PASSED] drm_test_rect_calc_vscale ============
[08:41:19] ================== drm_test_rect_rotate ===================
[08:41:19] [PASSED] reflect-x
[08:41:19] [PASSED] reflect-y
[08:41:19] [PASSED] rotate-0
[08:41:19] [PASSED] rotate-90
[08:41:19] [PASSED] rotate-180
[08:41:19] [PASSED] rotate-270
[08:41:19] ============== [PASSED] drm_test_rect_rotate ===============
[08:41:19] ================ drm_test_rect_rotate_inv =================
[08:41:19] [PASSED] reflect-x
[08:41:19] [PASSED] reflect-y
[08:41:19] [PASSED] rotate-0
[08:41:19] [PASSED] rotate-90
[08:41:19] [PASSED] rotate-180
[08:41:19] [PASSED] rotate-270
[08:41:19] ============ [PASSED] drm_test_rect_rotate_inv =============
[08:41:19] ==================== [PASSED] drm_rect =====================
[08:41:19] ============================================================
[08:41:19] Testing complete. Ran 608 tests: passed: 608
[08:41:19] Elapsed time: 22.893s total, 1.667s configuring, 21.050s building, 0.174s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[08:41:19] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[08:41:21] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json ARCH=um O=.kunit --jobs=48
[08:41:28] Starting KUnit Kernel (1/1)...
[08:41:28] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[08:41:29] ================= ttm_device (5 subtests) ==================
[08:41:29] [PASSED] ttm_device_init_basic
[08:41:29] [PASSED] ttm_device_init_multiple
[08:41:29] [PASSED] ttm_device_fini_basic
[08:41:29] [PASSED] ttm_device_init_no_vma_man
[08:41:29] ================== ttm_device_init_pools ==================
[08:41:29] [PASSED] No DMA allocations, no DMA32 required
[08:41:29] [PASSED] DMA allocations, DMA32 required
[08:41:29] [PASSED] No DMA allocations, DMA32 required
[08:41:29] [PASSED] DMA allocations, no DMA32 required
[08:41:29] ============== [PASSED] ttm_device_init_pools ==============
[08:41:29] =================== [PASSED] ttm_device ====================
[08:41:29] ================== ttm_pool (8 subtests) ===================
[08:41:29] ================== ttm_pool_alloc_basic ===================
[08:41:29] [PASSED] One page
[08:41:29] [PASSED] More than one page
[08:41:29] [PASSED] Above the allocation limit
[08:41:29] [PASSED] One page, with coherent DMA mappings enabled
[08:41:29] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[08:41:29] ============== [PASSED] ttm_pool_alloc_basic ===============
[08:41:29] ============== ttm_pool_alloc_basic_dma_addr ==============
[08:41:29] [PASSED] One page
[08:41:29] [PASSED] More than one page
[08:41:29] [PASSED] Above the allocation limit
[08:41:29] [PASSED] One page, with coherent DMA mappings enabled
[08:41:29] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[08:41:29] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[08:41:29] [PASSED] ttm_pool_alloc_order_caching_match
[08:41:29] [PASSED] ttm_pool_alloc_caching_mismatch
[08:41:29] [PASSED] ttm_pool_alloc_order_mismatch
[08:41:29] [PASSED] ttm_pool_free_dma_alloc
[08:41:29] [PASSED] ttm_pool_free_no_dma_alloc
[08:41:29] [PASSED] ttm_pool_fini_basic
[08:41:29] ==================== [PASSED] ttm_pool =====================
[08:41:29] ================ ttm_resource (8 subtests) =================
[08:41:29] ================= ttm_resource_init_basic =================
[08:41:29] [PASSED] Init resource in TTM_PL_SYSTEM
[08:41:29] [PASSED] Init resource in TTM_PL_VRAM
[08:41:29] [PASSED] Init resource in a private placement
[08:41:29] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[08:41:29] ============= [PASSED] ttm_resource_init_basic =============
[08:41:29] [PASSED] ttm_resource_init_pinned
[08:41:29] [PASSED] ttm_resource_fini_basic
[08:41:29] [PASSED] ttm_resource_manager_init_basic
[08:41:29] [PASSED] ttm_resource_manager_usage_basic
[08:41:29] [PASSED] ttm_resource_manager_set_used_basic
[08:41:29] [PASSED] ttm_sys_man_alloc_basic
[08:41:29] [PASSED] ttm_sys_man_free_basic
[08:41:29] ================== [PASSED] ttm_resource ===================
[08:41:29] =================== ttm_tt (15 subtests) ===================
[08:41:29] ==================== ttm_tt_init_basic ====================
[08:41:29] [PASSED] Page-aligned size
[08:41:29] [PASSED] Extra pages requested
[08:41:29] ================ [PASSED] ttm_tt_init_basic ================
[08:41:29] [PASSED] ttm_tt_init_misaligned
[08:41:29] [PASSED] ttm_tt_fini_basic
[08:41:29] [PASSED] ttm_tt_fini_sg
[08:41:29] [PASSED] ttm_tt_fini_shmem
[08:41:29] [PASSED] ttm_tt_create_basic
[08:41:29] [PASSED] ttm_tt_create_invalid_bo_type
[08:41:29] [PASSED] ttm_tt_create_ttm_exists
[08:41:29] [PASSED] ttm_tt_create_failed
[08:41:29] [PASSED] ttm_tt_destroy_basic
[08:41:29] [PASSED] ttm_tt_populate_null_ttm
[08:41:29] [PASSED] ttm_tt_populate_populated_ttm
[08:41:29] [PASSED] ttm_tt_unpopulate_basic
[08:41:29] [PASSED] ttm_tt_unpopulate_empty_ttm
[08:41:29] [PASSED] ttm_tt_swapin_basic
[08:41:29] ===================== [PASSED] ttm_tt ======================
[08:41:29] =================== ttm_bo (14 subtests) ===================
[08:41:29] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[08:41:29] [PASSED] Cannot be interrupted and sleeps
[08:41:29] [PASSED] Cannot be interrupted, locks straight away
[08:41:29] [PASSED] Can be interrupted, sleeps
[08:41:29] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[08:41:29] [PASSED] ttm_bo_reserve_locked_no_sleep
[08:41:29] [PASSED] ttm_bo_reserve_no_wait_ticket
[08:41:29] [PASSED] ttm_bo_reserve_double_resv
[08:41:29] [PASSED] ttm_bo_reserve_interrupted
[08:41:29] [PASSED] ttm_bo_reserve_deadlock
[08:41:29] [PASSED] ttm_bo_unreserve_basic
[08:41:29] [PASSED] ttm_bo_unreserve_pinned
[08:41:29] [PASSED] ttm_bo_unreserve_bulk
[08:41:29] [PASSED] ttm_bo_put_basic
[08:41:29] [PASSED] ttm_bo_put_shared_resv
[08:41:29] [PASSED] ttm_bo_pin_basic
[08:41:29] [PASSED] ttm_bo_pin_unpin_resource
[08:41:29] [PASSED] ttm_bo_multiple_pin_one_unpin
[08:41:29] ===================== [PASSED] ttm_bo ======================
[08:41:29] ============== ttm_bo_validate (22 subtests) ===============
[08:41:29] ============== ttm_bo_init_reserved_sys_man ===============
[08:41:29] [PASSED] Buffer object for userspace
[08:41:29] [PASSED] Kernel buffer object
[08:41:29] [PASSED] Shared buffer object
[08:41:29] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[08:41:29] ============== ttm_bo_init_reserved_mock_man ==============
[08:41:29] [PASSED] Buffer object for userspace
[08:41:29] [PASSED] Kernel buffer object
[08:41:29] [PASSED] Shared buffer object
[08:41:29] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[08:41:29] [PASSED] ttm_bo_init_reserved_resv
[08:41:29] ================== ttm_bo_validate_basic ==================
[08:41:29] [PASSED] Buffer object for userspace
[08:41:29] [PASSED] Kernel buffer object
[08:41:29] [PASSED] Shared buffer object
[08:41:29] ============== [PASSED] ttm_bo_validate_basic ==============
[08:41:29] [PASSED] ttm_bo_validate_invalid_placement
[08:41:29] ============= ttm_bo_validate_same_placement ==============
[08:41:29] [PASSED] System manager
[08:41:29] [PASSED] VRAM manager
[08:41:29] ========= [PASSED] ttm_bo_validate_same_placement ==========
[08:41:29] [PASSED] ttm_bo_validate_failed_alloc
[08:41:29] [PASSED] ttm_bo_validate_pinned
[08:41:29] [PASSED] ttm_bo_validate_busy_placement
[08:41:29] ================ ttm_bo_validate_multihop =================
[08:41:29] [PASSED] Buffer object for userspace
[08:41:29] [PASSED] Kernel buffer object
[08:41:29] [PASSED] Shared buffer object
[08:41:29] ============ [PASSED] ttm_bo_validate_multihop =============
[08:41:29] ========== ttm_bo_validate_no_placement_signaled ==========
[08:41:29] [PASSED] Buffer object in system domain, no page vector
[08:41:29] [PASSED] Buffer object in system domain with an existing page vector
[08:41:29] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[08:41:29] ======== ttm_bo_validate_no_placement_not_signaled ========
[08:41:29] [PASSED] Buffer object for userspace
[08:41:29] [PASSED] Kernel buffer object
[08:41:29] [PASSED] Shared buffer object
[08:41:29] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[08:41:29] [PASSED] ttm_bo_validate_move_fence_signaled
[08:41:29] ========= ttm_bo_validate_move_fence_not_signaled =========
[08:41:29] [PASSED] Waits for GPU
[08:41:29] [PASSED] Tries to lock straight away
[08:41:29] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[08:41:29] [PASSED] ttm_bo_validate_swapout
[08:41:29] [PASSED] ttm_bo_validate_happy_evict
[08:41:29] [PASSED] ttm_bo_validate_all_pinned_evict
[08:41:29] [PASSED] ttm_bo_validate_allowed_only_evict
[08:41:29] [PASSED] ttm_bo_validate_deleted_evict
[08:41:29] [PASSED] ttm_bo_validate_busy_domain_evict
[08:41:29] [PASSED] ttm_bo_validate_evict_gutting
[08:41:29] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[08:41:29] ================= [PASSED] ttm_bo_validate =================
[08:41:29] ============================================================
[08:41:29] Testing complete. Ran 102 tests: passed: 102
[08:41:29] Elapsed time: 10.077s total, 1.622s configuring, 7.787s building, 0.569s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 31+ messages in thread
* ✓ CI.Build: success for DPLL framework redesign (rev2)
2025-04-02 8:31 [PATCH 00/16] DPLL framework redesign Suraj Kandpal
` (18 preceding siblings ...)
2025-04-02 8:41 ` ✓ CI.KUnit: success " Patchwork
@ 2025-04-02 8:58 ` Patchwork
2025-04-02 9:00 ` ✓ CI.Hooks: " Patchwork
` (3 subsequent siblings)
23 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2025-04-02 8:58 UTC (permalink / raw)
To: Suraj Kandpal; +Cc: intel-xe
== Series Details ==
Series: DPLL framework redesign (rev2)
URL : https://patchwork.freedesktop.org/series/145380/
State : success
== Summary ==
lib/modules/6.14.0-xe+/kernel/arch/x86/events/amd/
lib/modules/6.14.0-xe+/kernel/arch/x86/events/amd/amd-uncore.ko
lib/modules/6.14.0-xe+/kernel/arch/x86/events/rapl.ko
lib/modules/6.14.0-xe+/kernel/arch/x86/kvm/
lib/modules/6.14.0-xe+/kernel/arch/x86/kvm/kvm.ko
lib/modules/6.14.0-xe+/kernel/arch/x86/kvm/kvm-intel.ko
lib/modules/6.14.0-xe+/kernel/arch/x86/kvm/kvm-amd.ko
lib/modules/6.14.0-xe+/kernel/kernel/
lib/modules/6.14.0-xe+/kernel/kernel/kheaders.ko
lib/modules/6.14.0-xe+/kernel/crypto/
lib/modules/6.14.0-xe+/kernel/crypto/ecrdsa_generic.ko
lib/modules/6.14.0-xe+/kernel/crypto/xcbc.ko
lib/modules/6.14.0-xe+/kernel/crypto/serpent_generic.ko
lib/modules/6.14.0-xe+/kernel/crypto/aria_generic.ko
lib/modules/6.14.0-xe+/kernel/crypto/crypto_simd.ko
lib/modules/6.14.0-xe+/kernel/crypto/adiantum.ko
lib/modules/6.14.0-xe+/kernel/crypto/tcrypt.ko
lib/modules/6.14.0-xe+/kernel/crypto/crypto_engine.ko
lib/modules/6.14.0-xe+/kernel/crypto/zstd.ko
lib/modules/6.14.0-xe+/kernel/crypto/asymmetric_keys/
lib/modules/6.14.0-xe+/kernel/crypto/asymmetric_keys/pkcs7_test_key.ko
lib/modules/6.14.0-xe+/kernel/crypto/asymmetric_keys/pkcs8_key_parser.ko
lib/modules/6.14.0-xe+/kernel/crypto/des_generic.ko
lib/modules/6.14.0-xe+/kernel/crypto/xctr.ko
lib/modules/6.14.0-xe+/kernel/crypto/authenc.ko
lib/modules/6.14.0-xe+/kernel/crypto/sm4_generic.ko
lib/modules/6.14.0-xe+/kernel/crypto/camellia_generic.ko
lib/modules/6.14.0-xe+/kernel/crypto/sm3.ko
lib/modules/6.14.0-xe+/kernel/crypto/pcrypt.ko
lib/modules/6.14.0-xe+/kernel/crypto/aegis128.ko
lib/modules/6.14.0-xe+/kernel/crypto/af_alg.ko
lib/modules/6.14.0-xe+/kernel/crypto/algif_aead.ko
lib/modules/6.14.0-xe+/kernel/crypto/cmac.ko
lib/modules/6.14.0-xe+/kernel/crypto/sm3_generic.ko
lib/modules/6.14.0-xe+/kernel/crypto/aes_ti.ko
lib/modules/6.14.0-xe+/kernel/crypto/chacha_generic.ko
lib/modules/6.14.0-xe+/kernel/crypto/poly1305_generic.ko
lib/modules/6.14.0-xe+/kernel/crypto/nhpoly1305.ko
lib/modules/6.14.0-xe+/kernel/crypto/crc32_generic.ko
lib/modules/6.14.0-xe+/kernel/crypto/essiv.ko
lib/modules/6.14.0-xe+/kernel/crypto/ccm.ko
lib/modules/6.14.0-xe+/kernel/crypto/wp512.ko
lib/modules/6.14.0-xe+/kernel/crypto/streebog_generic.ko
lib/modules/6.14.0-xe+/kernel/crypto/authencesn.ko
lib/modules/6.14.0-xe+/kernel/crypto/echainiv.ko
lib/modules/6.14.0-xe+/kernel/crypto/lrw.ko
lib/modules/6.14.0-xe+/kernel/crypto/cryptd.ko
lib/modules/6.14.0-xe+/kernel/crypto/crypto_user.ko
lib/modules/6.14.0-xe+/kernel/crypto/algif_hash.ko
lib/modules/6.14.0-xe+/kernel/crypto/polyval-generic.ko
lib/modules/6.14.0-xe+/kernel/crypto/hctr2.ko
lib/modules/6.14.0-xe+/kernel/crypto/842.ko
lib/modules/6.14.0-xe+/kernel/crypto/pcbc.ko
lib/modules/6.14.0-xe+/kernel/crypto/ansi_cprng.ko
lib/modules/6.14.0-xe+/kernel/crypto/cast6_generic.ko
lib/modules/6.14.0-xe+/kernel/crypto/twofish_common.ko
lib/modules/6.14.0-xe+/kernel/crypto/twofish_generic.ko
lib/modules/6.14.0-xe+/kernel/crypto/lz4hc.ko
lib/modules/6.14.0-xe+/kernel/crypto/blowfish_generic.ko
lib/modules/6.14.0-xe+/kernel/crypto/md4.ko
lib/modules/6.14.0-xe+/kernel/crypto/chacha20poly1305.ko
lib/modules/6.14.0-xe+/kernel/crypto/curve25519-generic.ko
lib/modules/6.14.0-xe+/kernel/crypto/lz4.ko
lib/modules/6.14.0-xe+/kernel/crypto/rmd160.ko
lib/modules/6.14.0-xe+/kernel/crypto/algif_skcipher.ko
lib/modules/6.14.0-xe+/kernel/crypto/cast5_generic.ko
lib/modules/6.14.0-xe+/kernel/crypto/fcrypt.ko
lib/modules/6.14.0-xe+/kernel/crypto/ecdsa_generic.ko
lib/modules/6.14.0-xe+/kernel/crypto/sm4.ko
lib/modules/6.14.0-xe+/kernel/crypto/cast_common.ko
lib/modules/6.14.0-xe+/kernel/crypto/blowfish_common.ko
lib/modules/6.14.0-xe+/kernel/crypto/michael_mic.ko
lib/modules/6.14.0-xe+/kernel/crypto/async_tx/
lib/modules/6.14.0-xe+/kernel/crypto/async_tx/async_xor.ko
lib/modules/6.14.0-xe+/kernel/crypto/async_tx/async_tx.ko
lib/modules/6.14.0-xe+/kernel/crypto/async_tx/async_memcpy.ko
lib/modules/6.14.0-xe+/kernel/crypto/async_tx/async_pq.ko
lib/modules/6.14.0-xe+/kernel/crypto/async_tx/async_raid6_recov.ko
lib/modules/6.14.0-xe+/kernel/crypto/algif_rng.ko
lib/modules/6.14.0-xe+/kernel/block/
lib/modules/6.14.0-xe+/kernel/block/bfq.ko
lib/modules/6.14.0-xe+/kernel/block/kyber-iosched.ko
lib/modules/6.14.0-xe+/build
lib/modules/6.14.0-xe+/modules.alias.bin
lib/modules/6.14.0-xe+/modules.builtin
lib/modules/6.14.0-xe+/modules.softdep
lib/modules/6.14.0-xe+/modules.alias
lib/modules/6.14.0-xe+/modules.order
lib/modules/6.14.0-xe+/modules.symbols
lib/modules/6.14.0-xe+/modules.dep.bin
+ mv kernel-nodebug.tar.gz ..
+ cd ..
+ rm -rf archive
++ date +%s
+ echo -e '\e[0Ksection_end:1743584278:package_x86_64_nodebug\r\e[0K'
+ sync
^[[0Ksection_end:1743584278:package_x86_64_nodebug
^[[0K
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 31+ messages in thread
* ✓ CI.Hooks: success for DPLL framework redesign (rev2)
2025-04-02 8:31 [PATCH 00/16] DPLL framework redesign Suraj Kandpal
` (19 preceding siblings ...)
2025-04-02 8:58 ` ✓ CI.Build: " Patchwork
@ 2025-04-02 9:00 ` Patchwork
2025-04-02 9:02 ` ✓ CI.checksparse: " Patchwork
` (2 subsequent siblings)
23 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2025-04-02 9:00 UTC (permalink / raw)
To: Suraj Kandpal; +Cc: intel-xe
== Series Details ==
Series: DPLL framework redesign (rev2)
URL : https://patchwork.freedesktop.org/series/145380/
State : success
== Summary ==
run-parts: executing /workspace/ci/hooks/00-showenv
+ export
+ grep -Ei '(^|\W)CI_'
declare -x CI_KERNEL_BUILD_DIR="/workspace/kernel/build64-default"
declare -x CI_KERNEL_SRC_DIR="/workspace/kernel"
declare -x CI_TOOLS_SRC_DIR="/workspace/ci"
declare -x CI_WORKSPACE_DIR="/workspace"
run-parts: executing /workspace/ci/hooks/10-build-W1
+ SRC_DIR=/workspace/kernel
+ RESTORE_DISPLAY_CONFIG=0
+ '[' -n /workspace/kernel/build64-default ']'
+ BUILD_DIR=/workspace/kernel/build64-default
+ cd /workspace/kernel
++ nproc
+ make -j48 O=/workspace/kernel/build64-default modules_prepare
make[1]: Entering directory '/workspace/kernel/build64-default'
GEN Makefile
DESCEND objtool
CALL ../scripts/checksyscalls.sh
INSTALL libsubcmd_headers
CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/exec-cmd.o
CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/help.o
CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/pager.o
CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/parse-options.o
CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/run-command.o
CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/sigchain.o
CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/subcmd-config.o
LD /workspace/kernel/build64-default/tools/objtool/libsubcmd/libsubcmd-in.o
AR /workspace/kernel/build64-default/tools/objtool/libsubcmd/libsubcmd.a
CC /workspace/kernel/build64-default/tools/objtool/weak.o
CC /workspace/kernel/build64-default/tools/objtool/check.o
CC /workspace/kernel/build64-default/tools/objtool/special.o
CC /workspace/kernel/build64-default/tools/objtool/builtin-check.o
CC /workspace/kernel/build64-default/tools/objtool/arch/x86/special.o
CC /workspace/kernel/build64-default/tools/objtool/elf.o
CC /workspace/kernel/build64-default/tools/objtool/objtool.o
CC /workspace/kernel/build64-default/tools/objtool/arch/x86/decode.o
CC /workspace/kernel/build64-default/tools/objtool/arch/x86/orc.o
CC /workspace/kernel/build64-default/tools/objtool/orc_gen.o
CC /workspace/kernel/build64-default/tools/objtool/orc_dump.o
CC /workspace/kernel/build64-default/tools/objtool/libstring.o
CC /workspace/kernel/build64-default/tools/objtool/libctype.o
CC /workspace/kernel/build64-default/tools/objtool/str_error_r.o
CC /workspace/kernel/build64-default/tools/objtool/librbtree.o
LD /workspace/kernel/build64-default/tools/objtool/arch/x86/objtool-in.o
LD /workspace/kernel/build64-default/tools/objtool/objtool-in.o
LINK /workspace/kernel/build64-default/tools/objtool/objtool
make[1]: Leaving directory '/workspace/kernel/build64-default'
++ nproc
+ make -j48 O=/workspace/kernel/build64-default W=1 drivers/gpu/drm/xe
make[1]: Entering directory '/workspace/kernel/build64-default'
make[2]: Nothing to be done for 'drivers/gpu/drm/xe'.
make[1]: Leaving directory '/workspace/kernel/build64-default'
run-parts: executing /workspace/ci/hooks/11-build-32b
+++ realpath /workspace/ci/hooks/11-build-32b
++ dirname /workspace/ci/hooks/11-build-32b
+ THIS_SCRIPT_DIR=/workspace/ci/hooks
+ SRC_DIR=/workspace/kernel
+ TOOLS_SRC_DIR=/workspace/ci
+ '[' -n /workspace/kernel/build64-default ']'
+ BUILD_DIR=/workspace/kernel/build64-default
+ BUILD_DIR=/workspace/kernel/build64-default/build32
+ cd /workspace/kernel
+ mkdir -p /workspace/kernel/build64-default/build32
++ nproc
+ make -j48 ARCH=i386 O=/workspace/kernel/build64-default/build32 defconfig
make[1]: Entering directory '/workspace/kernel/build64-default/build32'
GEN Makefile
HOSTCC scripts/basic/fixdep
HOSTCC scripts/kconfig/conf.o
HOSTCC scripts/kconfig/confdata.o
HOSTCC scripts/kconfig/expr.o
LEX scripts/kconfig/lexer.lex.c
YACC scripts/kconfig/parser.tab.[ch]
HOSTCC scripts/kconfig/menu.o
HOSTCC scripts/kconfig/preprocess.o
HOSTCC scripts/kconfig/symbol.o
HOSTCC scripts/kconfig/util.o
HOSTCC scripts/kconfig/lexer.lex.o
HOSTCC scripts/kconfig/parser.tab.o
HOSTLD scripts/kconfig/conf
*** Default configuration is based on 'i386_defconfig'
#
# configuration written to .config
#
make[1]: Leaving directory '/workspace/kernel/build64-default/build32'
+ cd /workspace/kernel/build64-default/build32
+ /workspace/kernel/scripts/kconfig/merge_config.sh .config /workspace/ci/kernel/fragments/10-xe.fragment
Using .config as base
Merging /workspace/ci/kernel/fragments/10-xe.fragment
Value of CONFIG_DRM_XE is redefined by fragment /workspace/ci/kernel/fragments/10-xe.fragment:
Previous value: # CONFIG_DRM_XE is not set
New value: CONFIG_DRM_XE=m
GEN Makefile
#
# configuration written to .config
#
Value requested for CONFIG_HAVE_UID16 not in final .config
Requested value: CONFIG_HAVE_UID16=y
Actual value:
Value requested for CONFIG_UID16 not in final .config
Requested value: CONFIG_UID16=y
Actual value:
Value requested for CONFIG_X86_32 not in final .config
Requested value: CONFIG_X86_32=y
Actual value:
Value requested for CONFIG_OUTPUT_FORMAT not in final .config
Requested value: CONFIG_OUTPUT_FORMAT="elf32-i386"
Actual value: CONFIG_OUTPUT_FORMAT="elf64-x86-64"
Value requested for CONFIG_ARCH_MMAP_RND_BITS_MIN not in final .config
Requested value: CONFIG_ARCH_MMAP_RND_BITS_MIN=8
Actual value: CONFIG_ARCH_MMAP_RND_BITS_MIN=28
Value requested for CONFIG_ARCH_MMAP_RND_BITS_MAX not in final .config
Requested value: CONFIG_ARCH_MMAP_RND_BITS_MAX=16
Actual value: CONFIG_ARCH_MMAP_RND_BITS_MAX=32
Value requested for CONFIG_PGTABLE_LEVELS not in final .config
Requested value: CONFIG_PGTABLE_LEVELS=2
Actual value: CONFIG_PGTABLE_LEVELS=5
Value requested for CONFIG_X86_BIGSMP not in final .config
Requested value: # CONFIG_X86_BIGSMP is not set
Actual value:
Value requested for CONFIG_X86_INTEL_QUARK not in final .config
Requested value: # CONFIG_X86_INTEL_QUARK is not set
Actual value:
Value requested for CONFIG_X86_RDC321X not in final .config
Requested value: # CONFIG_X86_RDC321X is not set
Actual value:
Value requested for CONFIG_X86_32_NON_STANDARD not in final .config
Requested value: # CONFIG_X86_32_NON_STANDARD is not set
Actual value:
Value requested for CONFIG_X86_32_IRIS not in final .config
Requested value: # CONFIG_X86_32_IRIS is not set
Actual value:
Value requested for CONFIG_M486SX not in final .config
Requested value: # CONFIG_M486SX is not set
Actual value:
Value requested for CONFIG_M486 not in final .config
Requested value: # CONFIG_M486 is not set
Actual value:
Value requested for CONFIG_M586 not in final .config
Requested value: # CONFIG_M586 is not set
Actual value:
Value requested for CONFIG_M586TSC not in final .config
Requested value: # CONFIG_M586TSC is not set
Actual value:
Value requested for CONFIG_M586MMX not in final .config
Requested value: # CONFIG_M586MMX is not set
Actual value:
Value requested for CONFIG_M686 not in final .config
Requested value: CONFIG_M686=y
Actual value:
Value requested for CONFIG_MPENTIUMII not in final .config
Requested value: # CONFIG_MPENTIUMII is not set
Actual value:
Value requested for CONFIG_MPENTIUMIII not in final .config
Requested value: # CONFIG_MPENTIUMIII is not set
Actual value:
Value requested for CONFIG_MPENTIUMM not in final .config
Requested value: # CONFIG_MPENTIUMM is not set
Actual value:
Value requested for CONFIG_MPENTIUM4 not in final .config
Requested value: # CONFIG_MPENTIUM4 is not set
Actual value:
Value requested for CONFIG_MK6 not in final .config
Requested value: # CONFIG_MK6 is not set
Actual value:
Value requested for CONFIG_MK7 not in final .config
Requested value: # CONFIG_MK7 is not set
Actual value:
Value requested for CONFIG_MCRUSOE not in final .config
Requested value: # CONFIG_MCRUSOE is not set
Actual value:
Value requested for CONFIG_MEFFICEON not in final .config
Requested value: # CONFIG_MEFFICEON is not set
Actual value:
Value requested for CONFIG_MWINCHIPC6 not in final .config
Requested value: # CONFIG_MWINCHIPC6 is not set
Actual value:
Value requested for CONFIG_MWINCHIP3D not in final .config
Requested value: # CONFIG_MWINCHIP3D is not set
Actual value:
Value requested for CONFIG_MELAN not in final .config
Requested value: # CONFIG_MELAN is not set
Actual value:
Value requested for CONFIG_MGEODEGX1 not in final .config
Requested value: # CONFIG_MGEODEGX1 is not set
Actual value:
Value requested for CONFIG_MGEODE_LX not in final .config
Requested value: # CONFIG_MGEODE_LX is not set
Actual value:
Value requested for CONFIG_MCYRIXIII not in final .config
Requested value: # CONFIG_MCYRIXIII is not set
Actual value:
Value requested for CONFIG_MVIAC3_2 not in final .config
Requested value: # CONFIG_MVIAC3_2 is not set
Actual value:
Value requested for CONFIG_MVIAC7 not in final .config
Requested value: # CONFIG_MVIAC7 is not set
Actual value:
Value requested for CONFIG_X86_GENERIC not in final .config
Requested value: # CONFIG_X86_GENERIC is not set
Actual value:
Value requested for CONFIG_X86_INTERNODE_CACHE_SHIFT not in final .config
Requested value: CONFIG_X86_INTERNODE_CACHE_SHIFT=5
Actual value: CONFIG_X86_INTERNODE_CACHE_SHIFT=6
Value requested for CONFIG_X86_L1_CACHE_SHIFT not in final .config
Requested value: CONFIG_X86_L1_CACHE_SHIFT=5
Actual value: CONFIG_X86_L1_CACHE_SHIFT=6
Value requested for CONFIG_X86_USE_PPRO_CHECKSUM not in final .config
Requested value: CONFIG_X86_USE_PPRO_CHECKSUM=y
Actual value:
Value requested for CONFIG_X86_MINIMUM_CPU_FAMILY not in final .config
Requested value: CONFIG_X86_MINIMUM_CPU_FAMILY=6
Actual value: CONFIG_X86_MINIMUM_CPU_FAMILY=64
Value requested for CONFIG_CPU_SUP_TRANSMETA_32 not in final .config
Requested value: CONFIG_CPU_SUP_TRANSMETA_32=y
Actual value:
Value requested for CONFIG_CPU_SUP_VORTEX_32 not in final .config
Requested value: CONFIG_CPU_SUP_VORTEX_32=y
Actual value:
Value requested for CONFIG_HPET_TIMER not in final .config
Requested value: # CONFIG_HPET_TIMER is not set
Actual value: CONFIG_HPET_TIMER=y
Value requested for CONFIG_NR_CPUS_RANGE_END not in final .config
Requested value: CONFIG_NR_CPUS_RANGE_END=8
Actual value: CONFIG_NR_CPUS_RANGE_END=512
Value requested for CONFIG_NR_CPUS_DEFAULT not in final .config
Requested value: CONFIG_NR_CPUS_DEFAULT=8
Actual value: CONFIG_NR_CPUS_DEFAULT=64
Value requested for CONFIG_X86_ANCIENT_MCE not in final .config
Requested value: # CONFIG_X86_ANCIENT_MCE is not set
Actual value:
Value requested for CONFIG_X86_LEGACY_VM86 not in final .config
Requested value: # CONFIG_X86_LEGACY_VM86 is not set
Actual value:
Value requested for CONFIG_X86_ESPFIX32 not in final .config
Requested value: CONFIG_X86_ESPFIX32=y
Actual value:
Value requested for CONFIG_TOSHIBA not in final .config
Requested value: # CONFIG_TOSHIBA is not set
Actual value:
Value requested for CONFIG_X86_REBOOTFIXUPS not in final .config
Requested value: # CONFIG_X86_REBOOTFIXUPS is not set
Actual value:
Value requested for CONFIG_MICROCODE_INITRD32 not in final .config
Requested value: CONFIG_MICROCODE_INITRD32=y
Actual value:
Value requested for CONFIG_NOHIGHMEM not in final .config
Requested value: # CONFIG_NOHIGHMEM is not set
Actual value:
Value requested for CONFIG_HIGHMEM4G not in final .config
Requested value: CONFIG_HIGHMEM4G=y
Actual value:
Value requested for CONFIG_HIGHMEM64G not in final .config
Requested value: # CONFIG_HIGHMEM64G is not set
Actual value:
Value requested for CONFIG_VMSPLIT_3G not in final .config
Requested value: CONFIG_VMSPLIT_3G=y
Actual value:
Value requested for CONFIG_VMSPLIT_3G_OPT not in final .config
Requested value: # CONFIG_VMSPLIT_3G_OPT is not set
Actual value:
Value requested for CONFIG_VMSPLIT_2G not in final .config
Requested value: # CONFIG_VMSPLIT_2G is not set
Actual value:
Value requested for CONFIG_VMSPLIT_2G_OPT not in final .config
Requested value: # CONFIG_VMSPLIT_2G_OPT is not set
Actual value:
Value requested for CONFIG_VMSPLIT_1G not in final .config
Requested value: # CONFIG_VMSPLIT_1G is not set
Actual value:
Value requested for CONFIG_PAGE_OFFSET not in final .config
Requested value: CONFIG_PAGE_OFFSET=0xC0000000
Actual value:
Value requested for CONFIG_HIGHMEM not in final .config
Requested value: CONFIG_HIGHMEM=y
Actual value:
Value requested for CONFIG_X86_PAE not in final .config
Requested value: # CONFIG_X86_PAE is not set
Actual value:
Value requested for CONFIG_ARCH_FLATMEM_ENABLE not in final .config
Requested value: CONFIG_ARCH_FLATMEM_ENABLE=y
Actual value:
Value requested for CONFIG_ARCH_SELECT_MEMORY_MODEL not in final .config
Requested value: CONFIG_ARCH_SELECT_MEMORY_MODEL=y
Actual value:
Value requested for CONFIG_ILLEGAL_POINTER_VALUE not in final .config
Requested value: CONFIG_ILLEGAL_POINTER_VALUE=0
Actual value: CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
Value requested for CONFIG_HIGHPTE not in final .config
Requested value: # CONFIG_HIGHPTE is not set
Actual value:
Value requested for CONFIG_COMPAT_VDSO not in final .config
Requested value: # CONFIG_COMPAT_VDSO is not set
Actual value:
Value requested for CONFIG_FUNCTION_PADDING_CFI not in final .config
Requested value: CONFIG_FUNCTION_PADDING_CFI=0
Actual value: CONFIG_FUNCTION_PADDING_CFI=11
Value requested for CONFIG_FUNCTION_PADDING_BYTES not in final .config
Requested value: CONFIG_FUNCTION_PADDING_BYTES=4
Actual value: CONFIG_FUNCTION_PADDING_BYTES=16
Value requested for CONFIG_APM not in final .config
Requested value: # CONFIG_APM is not set
Actual value:
Value requested for CONFIG_X86_POWERNOW_K6 not in final .config
Requested value: # CONFIG_X86_POWERNOW_K6 is not set
Actual value:
Value requested for CONFIG_X86_POWERNOW_K7 not in final .config
Requested value: # CONFIG_X86_POWERNOW_K7 is not set
Actual value:
Value requested for CONFIG_X86_GX_SUSPMOD not in final .config
Requested value: # CONFIG_X86_GX_SUSPMOD is not set
Actual value:
Value requested for CONFIG_X86_SPEEDSTEP_ICH not in final .config
Requested value: # CONFIG_X86_SPEEDSTEP_ICH is not set
Actual value:
Value requested for CONFIG_X86_SPEEDSTEP_SMI not in final .config
Requested value: # CONFIG_X86_SPEEDSTEP_SMI is not set
Actual value:
Value requested for CONFIG_X86_CPUFREQ_NFORCE2 not in final .config
Requested value: # CONFIG_X86_CPUFREQ_NFORCE2 is not set
Actual value:
Value requested for CONFIG_X86_LONGRUN not in final .config
Requested value: # CONFIG_X86_LONGRUN is not set
Actual value:
Value requested for CONFIG_X86_LONGHAUL not in final .config
Requested value: # CONFIG_X86_LONGHAUL is not set
Actual value:
Value requested for CONFIG_X86_E_POWERSAVER not in final .config
Requested value: # CONFIG_X86_E_POWERSAVER is not set
Actual value:
Value requested for CONFIG_PCI_GOBIOS not in final .config
Requested value: # CONFIG_PCI_GOBIOS is not set
Actual value:
Value requested for CONFIG_PCI_GOMMCONFIG not in final .config
Requested value: # CONFIG_PCI_GOMMCONFIG is not set
Actual value:
Value requested for CONFIG_PCI_GODIRECT not in final .config
Requested value: # CONFIG_PCI_GODIRECT is not set
Actual value:
Value requested for CONFIG_PCI_GOANY not in final .config
Requested value: CONFIG_PCI_GOANY=y
Actual value:
Value requested for CONFIG_PCI_BIOS not in final .config
Requested value: CONFIG_PCI_BIOS=y
Actual value:
Value requested for CONFIG_ISA not in final .config
Requested value: # CONFIG_ISA is not set
Actual value:
Value requested for CONFIG_SCx200 not in final .config
Requested value: # CONFIG_SCx200 is not set
Actual value:
Value requested for CONFIG_OLPC not in final .config
Requested value: # CONFIG_OLPC is not set
Actual value:
Value requested for CONFIG_ALIX not in final .config
Requested value: # CONFIG_ALIX is not set
Actual value:
Value requested for CONFIG_NET5501 not in final .config
Requested value: # CONFIG_NET5501 is not set
Actual value:
Value requested for CONFIG_GEOS not in final .config
Requested value: # CONFIG_GEOS is not set
Actual value:
Value requested for CONFIG_COMPAT_32 not in final .config
Requested value: CONFIG_COMPAT_32=y
Actual value:
Value requested for CONFIG_HAVE_ATOMIC_IOMAP not in final .config
Requested value: CONFIG_HAVE_ATOMIC_IOMAP=y
Actual value:
Value requested for CONFIG_ARCH_32BIT_OFF_T not in final .config
Requested value: CONFIG_ARCH_32BIT_OFF_T=y
Actual value:
Value requested for CONFIG_ARCH_WANT_IPC_PARSE_VERSION not in final .config
Requested value: CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
Actual value:
Value requested for CONFIG_MODULES_USE_ELF_REL not in final .config
Requested value: CONFIG_MODULES_USE_ELF_REL=y
Actual value:
Value requested for CONFIG_ARCH_MMAP_RND_BITS not in final .config
Requested value: CONFIG_ARCH_MMAP_RND_BITS=8
Actual value: CONFIG_ARCH_MMAP_RND_BITS=28
Value requested for CONFIG_CLONE_BACKWARDS not in final .config
Requested value: CONFIG_CLONE_BACKWARDS=y
Actual value:
Value requested for CONFIG_OLD_SIGSUSPEND3 not in final .config
Requested value: CONFIG_OLD_SIGSUSPEND3=y
Actual value:
Value requested for CONFIG_OLD_SIGACTION not in final .config
Requested value: CONFIG_OLD_SIGACTION=y
Actual value:
Value requested for CONFIG_ARCH_SPLIT_ARG64 not in final .config
Requested value: CONFIG_ARCH_SPLIT_ARG64=y
Actual value:
Value requested for CONFIG_FUNCTION_ALIGNMENT not in final .config
Requested value: CONFIG_FUNCTION_ALIGNMENT=4
Actual value: CONFIG_FUNCTION_ALIGNMENT=16
Value requested for CONFIG_SELECT_MEMORY_MODEL not in final .config
Requested value: CONFIG_SELECT_MEMORY_MODEL=y
Actual value:
Value requested for CONFIG_FLATMEM_MANUAL not in final .config
Requested value: CONFIG_FLATMEM_MANUAL=y
Actual value:
Value requested for CONFIG_SPARSEMEM_MANUAL not in final .config
Requested value: # CONFIG_SPARSEMEM_MANUAL is not set
Actual value:
Value requested for CONFIG_FLATMEM not in final .config
Requested value: CONFIG_FLATMEM=y
Actual value:
Value requested for CONFIG_SPARSEMEM_STATIC not in final .config
Requested value: CONFIG_SPARSEMEM_STATIC=y
Actual value:
Value requested for CONFIG_BOUNCE not in final .config
Requested value: CONFIG_BOUNCE=y
Actual value:
Value requested for CONFIG_KMAP_LOCAL not in final .config
Requested value: CONFIG_KMAP_LOCAL=y
Actual value:
Value requested for CONFIG_HOTPLUG_PCI_COMPAQ not in final .config
Requested value: # CONFIG_HOTPLUG_PCI_COMPAQ is not set
Actual value:
Value requested for CONFIG_HOTPLUG_PCI_IBM not in final .config
Requested value: # CONFIG_HOTPLUG_PCI_IBM is not set
Actual value:
Value requested for CONFIG_EFI_CAPSULE_QUIRK_QUARK_CSH not in final .config
Requested value: CONFIG_EFI_CAPSULE_QUIRK_QUARK_CSH=y
Actual value:
Value requested for CONFIG_PCH_PHUB not in final .config
Requested value: # CONFIG_PCH_PHUB is not set
Actual value:
Value requested for CONFIG_SCSI_NSP32 not in final .config
Requested value: # CONFIG_SCSI_NSP32 is not set
Actual value:
Value requested for CONFIG_PATA_CS5520 not in final .config
Requested value: # CONFIG_PATA_CS5520 is not set
Actual value:
Value requested for CONFIG_PATA_CS5530 not in final .config
Requested value: # CONFIG_PATA_CS5530 is not set
Actual value:
Value requested for CONFIG_PATA_CS5535 not in final .config
Requested value: # CONFIG_PATA_CS5535 is not set
Actual value:
Value requested for CONFIG_PATA_CS5536 not in final .config
Requested value: # CONFIG_PATA_CS5536 is not set
Actual value:
Value requested for CONFIG_PATA_SC1200 not in final .config
Requested value: # CONFIG_PATA_SC1200 is not set
Actual value:
Value requested for CONFIG_PCH_GBE not in final .config
Requested value: # CONFIG_PCH_GBE is not set
Actual value:
Value requested for CONFIG_INPUT_WISTRON_BTNS not in final .config
Requested value: # CONFIG_INPUT_WISTRON_BTNS is not set
Actual value:
Value requested for CONFIG_SERIAL_TIMBERDALE not in final .config
Requested value: # CONFIG_SERIAL_TIMBERDALE is not set
Actual value:
Value requested for CONFIG_SERIAL_PCH_UART not in final .config
Requested value: # CONFIG_SERIAL_PCH_UART is not set
Actual value:
Value requested for CONFIG_HW_RANDOM_GEODE not in final .config
Requested value: CONFIG_HW_RANDOM_GEODE=y
Actual value:
Value requested for CONFIG_SONYPI not in final .config
Requested value: # CONFIG_SONYPI is not set
Actual value:
Value requested for CONFIG_PC8736x_GPIO not in final .config
Requested value: # CONFIG_PC8736x_GPIO is not set
Actual value:
Value requested for CONFIG_NSC_GPIO not in final .config
Requested value: # CONFIG_NSC_GPIO is not set
Actual value:
Value requested for CONFIG_I2C_EG20T not in final .config
Requested value: # CONFIG_I2C_EG20T is not set
Actual value:
Value requested for CONFIG_SCx200_ACB not in final .config
Requested value: # CONFIG_SCx200_ACB is not set
Actual value:
Value requested for CONFIG_PTP_1588_CLOCK_PCH not in final .config
Requested value: # CONFIG_PTP_1588_CLOCK_PCH is not set
Actual value:
Value requested for CONFIG_SBC8360_WDT not in final .config
Requested value: # CONFIG_SBC8360_WDT is not set
Actual value:
Value requested for CONFIG_SBC7240_WDT not in final .config
Requested value: # CONFIG_SBC7240_WDT is not set
Actual value:
Value requested for CONFIG_MFD_CS5535 not in final .config
Requested value: # CONFIG_MFD_CS5535 is not set
Actual value:
Value requested for CONFIG_AGP_ALI not in final .config
Requested value: # CONFIG_AGP_ALI is not set
Actual value:
Value requested for CONFIG_AGP_ATI not in final .config
Requested value: # CONFIG_AGP_ATI is not set
Actual value:
Value requested for CONFIG_AGP_AMD not in final .config
Requested value: # CONFIG_AGP_AMD is not set
Actual value:
Value requested for CONFIG_AGP_NVIDIA not in final .config
Requested value: # CONFIG_AGP_NVIDIA is not set
Actual value:
Value requested for CONFIG_AGP_SWORKS not in final .config
Requested value: # CONFIG_AGP_SWORKS is not set
Actual value:
Value requested for CONFIG_AGP_EFFICEON not in final .config
Requested value: # CONFIG_AGP_EFFICEON is not set
Actual value:
Value requested for CONFIG_SND_CS5530 not in final .config
Requested value: # CONFIG_SND_CS5530 is not set
Actual value:
Value requested for CONFIG_SND_CS5535AUDIO not in final .config
Requested value: # CONFIG_SND_CS5535AUDIO is not set
Actual value:
Value requested for CONFIG_SND_SIS7019 not in final .config
Requested value: # CONFIG_SND_SIS7019 is not set
Actual value:
Value requested for CONFIG_LEDS_OT200 not in final .config
Requested value: # CONFIG_LEDS_OT200 is not set
Actual value:
Value requested for CONFIG_PCH_DMA not in final .config
Requested value: # CONFIG_PCH_DMA is not set
Actual value:
Value requested for CONFIG_CLKSRC_I8253 not in final .config
Requested value: CONFIG_CLKSRC_I8253=y
Actual value:
Value requested for CONFIG_MAILBOX not in final .config
Requested value: # CONFIG_MAILBOX is not set
Actual value: CONFIG_MAILBOX=y
Value requested for CONFIG_CRYPTO_SERPENT_SSE2_586 not in final .config
Requested value: # CONFIG_CRYPTO_SERPENT_SSE2_586 is not set
Actual value:
Value requested for CONFIG_CRYPTO_TWOFISH_586 not in final .config
Requested value: # CONFIG_CRYPTO_TWOFISH_586 is not set
Actual value:
Value requested for CONFIG_CRYPTO_DEV_GEODE not in final .config
Requested value: # CONFIG_CRYPTO_DEV_GEODE is not set
Actual value:
Value requested for CONFIG_CRYPTO_DEV_HIFN_795X not in final .config
Requested value: # CONFIG_CRYPTO_DEV_HIFN_795X is not set
Actual value:
Value requested for CONFIG_CRYPTO_LIB_POLY1305_RSIZE not in final .config
Requested value: CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1
Actual value: CONFIG_CRYPTO_LIB_POLY1305_RSIZE=11
Value requested for CONFIG_AUDIT_GENERIC not in final .config
Requested value: CONFIG_AUDIT_GENERIC=y
Actual value:
Value requested for CONFIG_GENERIC_VDSO_32 not in final .config
Requested value: CONFIG_GENERIC_VDSO_32=y
Actual value:
Value requested for CONFIG_DEBUG_KMAP_LOCAL not in final .config
Requested value: # CONFIG_DEBUG_KMAP_LOCAL is not set
Actual value:
Value requested for CONFIG_DEBUG_HIGHMEM not in final .config
Requested value: # CONFIG_DEBUG_HIGHMEM is not set
Actual value:
Value requested for CONFIG_HAVE_DEBUG_STACKOVERFLOW not in final .config
Requested value: CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
Actual value:
Value requested for CONFIG_DEBUG_STACKOVERFLOW not in final .config
Requested value: # CONFIG_DEBUG_STACKOVERFLOW is not set
Actual value:
Value requested for CONFIG_HAVE_FUNCTION_GRAPH_TRACER not in final .config
Requested value: CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
Actual value:
Value requested for CONFIG_HAVE_FUNCTION_GRAPH_FREGS not in final .config
Requested value: CONFIG_HAVE_FUNCTION_GRAPH_FREGS=y
Actual value:
Value requested for CONFIG_HAVE_FTRACE_GRAPH_FUNC not in final .config
Requested value: CONFIG_HAVE_FTRACE_GRAPH_FUNC=y
Actual value:
Value requested for CONFIG_DRM_KUNIT_TEST not in final .config
Requested value: CONFIG_DRM_KUNIT_TEST=m
Actual value:
Value requested for CONFIG_DRM_XE_WERROR not in final .config
Requested value: CONFIG_DRM_XE_WERROR=y
Actual value:
Value requested for CONFIG_DRM_XE_DEBUG not in final .config
Requested value: CONFIG_DRM_XE_DEBUG=y
Actual value:
Value requested for CONFIG_DRM_XE_DEBUG_MEM not in final .config
Requested value: CONFIG_DRM_XE_DEBUG_MEM=y
Actual value:
Value requested for CONFIG_DRM_XE_KUNIT_TEST not in final .config
Requested value: CONFIG_DRM_XE_KUNIT_TEST=m
Actual value:
++ nproc
+ make -j48 ARCH=i386 olddefconfig
GEN Makefile
#
# configuration written to .config
#
++ nproc
+ make -j48 ARCH=i386
SYNC include/config/auto.conf.cmd
GEN Makefile
GEN Makefile
WRAP arch/x86/include/generated/uapi/asm/bpf_perf_event.h
WRAP arch/x86/include/generated/uapi/asm/fcntl.h
WRAP arch/x86/include/generated/uapi/asm/errno.h
WRAP arch/x86/include/generated/uapi/asm/ioctl.h
SYSHDR arch/x86/include/generated/uapi/asm/unistd_32.h
WRAP arch/x86/include/generated/uapi/asm/ioctls.h
WRAP arch/x86/include/generated/uapi/asm/ipcbuf.h
SYSHDR arch/x86/include/generated/uapi/asm/unistd_64.h
WRAP arch/x86/include/generated/uapi/asm/param.h
WRAP arch/x86/include/generated/uapi/asm/poll.h
SYSHDR arch/x86/include/generated/uapi/asm/unistd_x32.h
UPD include/generated/uapi/linux/version.h
SYSTBL arch/x86/include/generated/asm/syscalls_32.h
WRAP arch/x86/include/generated/uapi/asm/socket.h
WRAP arch/x86/include/generated/uapi/asm/resource.h
WRAP arch/x86/include/generated/uapi/asm/sockios.h
WRAP arch/x86/include/generated/uapi/asm/termbits.h
WRAP arch/x86/include/generated/uapi/asm/termios.h
WRAP arch/x86/include/generated/uapi/asm/types.h
UPD include/generated/compile.h
HOSTCC arch/x86/tools/relocs_32.o
HOSTCC arch/x86/tools/relocs_64.o
HOSTCC arch/x86/tools/relocs_common.o
WRAP arch/x86/include/generated/asm/early_ioremap.h
WRAP arch/x86/include/generated/asm/fprobe.h
WRAP arch/x86/include/generated/asm/mcs_spinlock.h
WRAP arch/x86/include/generated/asm/mmzone.h
WRAP arch/x86/include/generated/asm/irq_regs.h
WRAP arch/x86/include/generated/asm/kmap_size.h
WRAP arch/x86/include/generated/asm/local64.h
WRAP arch/x86/include/generated/asm/mmiowb.h
WRAP arch/x86/include/generated/asm/module.lds.h
HOSTCC scripts/kallsyms
WRAP arch/x86/include/generated/asm/rwonce.h
HOSTCC scripts/sorttable
HOSTCC scripts/asn1_compiler
HOSTCC scripts/selinux/mdp/mdp
HOSTLD arch/x86/tools/relocs
UPD include/config/kernel.release
UPD include/generated/utsrelease.h
CC scripts/mod/empty.o
HOSTCC scripts/mod/mk_elfconfig
CC scripts/mod/devicetable-offsets.s
UPD scripts/mod/devicetable-offsets.h
MKELF scripts/mod/elfconfig.h
HOSTCC scripts/mod/modpost.o
HOSTCC scripts/mod/file2alias.o
HOSTCC scripts/mod/sumversion.o
HOSTCC scripts/mod/symsearch.o
HOSTLD scripts/mod/modpost
CC kernel/bounds.s
CHKSHA1 /workspace/kernel/include/linux/atomic/atomic-arch-fallback.h
CHKSHA1 /workspace/kernel/include/linux/atomic/atomic-instrumented.h
CHKSHA1 /workspace/kernel/include/linux/atomic/atomic-long.h
UPD include/generated/timeconst.h
UPD include/generated/bounds.h
CC arch/x86/kernel/asm-offsets.s
UPD include/generated/asm-offsets.h
CALL /workspace/kernel/scripts/checksyscalls.sh
LDS scripts/module.lds
CC init/main.o
HOSTCC usr/gen_init_cpio
CC init/do_mounts.o
CC certs/system_keyring.o
CC ipc/util.o
CC init/do_mounts_initrd.o
UPD init/utsversion-tmp.h
CC ipc/msgutil.o
CC init/initramfs.o
CC mm/filemap.o
CC init/calibrate.o
CC ipc/msg.o
CC mm/mempool.o
CC security/commoncap.o
CC ipc/sem.o
CC init/init_task.o
CC block/bdev.o
CC io_uring/io_uring.o
CC mm/oom_kill.o
AS arch/x86/lib/atomic64_cx8_32.o
CC security/lsm_syscalls.o
AS arch/x86/entry/entry.o
CC ipc/shm.o
AR arch/x86/crypto/built-in.a
CC arch/x86/realmode/init.o
AS arch/x86/entry/entry_32.o
CC arch/x86/video/video-common.o
CC arch/x86/pci/i386.o
AR arch/x86/net/built-in.a
CC arch/x86/power/cpu.o
CC security/keys/gc.o
HOSTCC security/selinux/genheaders
AR virt/lib/built-in.a
CC block/partitions/core.o
CC security/integrity/iint.o
AR arch/x86/entry/vsyscall/built-in.a
CC arch/x86/events/amd/core.o
CC arch/x86/mm/pat/set_memory.o
AR arch/x86/platform/atom/built-in.a
AR virt/built-in.a
AR drivers/cache/built-in.a
CC fs/notify/dnotify/dnotify.o
CC lib/math/div64.o
CC net/core/sock.o
CC arch/x86/virt/svm/cmdline.o
CC ipc/syscall.o
CC arch/x86/kernel/fpu/init.o
AR arch/x86/virt/vmx/built-in.a
CC sound/core/seq/seq.o
AR arch/x86/platform/ce4100/built-in.a
AR drivers/irqchip/built-in.a
AS arch/x86/lib/checksum_32.o
CC block/fops.o
CC arch/x86/entry/vdso/vma.o
CC fs/notify/inotify/inotify_fsnotify.o
CC arch/x86/pci/init.o
CC fs/notify/inotify/inotify_user.o
CC arch/x86/platform/efi/memmap.o
AR drivers/bus/mhi/built-in.a
CC arch/x86/platform/efi/quirks.o
AR drivers/bus/built-in.a
CC kernel/sched/core.o
CC arch/x86/lib/cmdline.o
AR drivers/pwm/built-in.a
CC crypto/asymmetric_keys/asymmetric_type.o
AR drivers/leds/trigger/built-in.a
AR drivers/leds/blink/built-in.a
AR drivers/leds/simple/built-in.a
AR arch/x86/virt/svm/built-in.a
CC drivers/leds/led-core.o
AR arch/x86/virt/built-in.a
CC arch/x86/mm/init.o
AS arch/x86/lib/cmpxchg8b_emu.o
CC lib/math/gcd.o
GEN security/selinux/flask.h security/selinux/av_permissions.h
CC arch/x86/lib/cpu.o
CC security/selinux/avc.o
CC lib/math/lcm.o
CC lib/math/int_log.o
AR arch/x86/platform/geode/built-in.a
CC net/core/request_sock.o
GEN usr/initramfs_data.cpio
COPY usr/initramfs_inc_data
AS usr/initramfs_data.o
HOSTCC certs/extract-cert
AR usr/built-in.a
CC lib/math/int_pow.o
CC arch/x86/kernel/fpu/bugs.o
AR arch/x86/platform/iris/built-in.a
CC arch/x86/platform/efi/efi.o
CC lib/math/int_sqrt.o
CC arch/x86/kernel/fpu/core.o
CC lib/math/reciprocal_div.o
AS arch/x86/realmode/rm/header.o
CC sound/core/seq/seq_lock.o
CC arch/x86/lib/delay.o
AS arch/x86/realmode/rm/trampoline_32.o
CC arch/x86/events/intel/core.o
CC lib/math/rational.o
AS arch/x86/realmode/rm/stack.o
AS arch/x86/realmode/rm/reboot.o
AS arch/x86/realmode/rm/wakeup_asm.o
AR arch/x86/video/built-in.a
CC arch/x86/platform/intel/iosf_mbi.o
AR arch/x86/platform/intel-mid/built-in.a
CERT certs/x509_certificate_list
CERT certs/signing_key.x509
CC arch/x86/realmode/rm/wakemain.o
CC mm/fadvise.o
AS certs/system_certificates.o
CC security/integrity/integrity_audit.o
AR certs/built-in.a
CC block/partitions/msdos.o
CC mm/maccess.o
CC arch/x86/events/zhaoxin/core.o
CC arch/x86/events/intel/bts.o
CC arch/x86/pci/pcbios.o
CC drivers/leds/led-class.o
CC arch/x86/realmode/rm/video-mode.o
CC drivers/leds/led-triggers.o
CC crypto/asymmetric_keys/restrict.o
CC arch/x86/events/core.o
CC init/version.o
CC security/keys/key.o
AR fs/notify/dnotify/built-in.a
CC security/keys/keyring.o
CC arch/x86/entry/vdso/extable.o
CC io_uring/opdef.o
CC arch/x86/power/hibernate_32.o
AS arch/x86/realmode/rm/copy.o
AS arch/x86/lib/getuser.o
GEN arch/x86/lib/inat-tables.c
LDS arch/x86/entry/vdso/vdso32/vdso32.lds
AS arch/x86/realmode/rm/bioscall.o
CC arch/x86/lib/insn-eval.o
CC arch/x86/realmode/rm/regs.o
CC drivers/pci/msi/pcidev_msi.o
CC sound/core/seq/seq_clientmgr.o
CC arch/x86/realmode/rm/video-vga.o
CC drivers/video/console/dummycon.o
CC drivers/pci/pcie/portdrv.o
AR lib/math/built-in.a
CC sound/core/seq/seq_memory.o
CC lib/crypto/mpi/generic_mpih-lshift.o
AR fs/notify/inotify/built-in.a
AR fs/notify/fanotify/built-in.a
AR arch/x86/platform/intel-quark/built-in.a
CC fs/notify/fsnotify.o
CC kernel/sched/fair.o
CC arch/x86/realmode/rm/video-vesa.o
CC kernel/locking/mutex.o
AS arch/x86/power/hibernate_asm_32.o
CC net/core/skbuff.o
CC kernel/sched/build_policy.o
CC arch/x86/realmode/rm/video-bios.o
CC security/selinux/hooks.o
CC crypto/asymmetric_keys/signature.o
CC arch/x86/events/amd/lbr.o
PASYMS arch/x86/realmode/rm/pasyms.h
CC arch/x86/mm/pat/memtype.o
CC lib/crypto/memneq.o
LDS arch/x86/realmode/rm/realmode.lds
AR arch/x86/platform/olpc/built-in.a
CC lib/crypto/mpi/generic_mpih-mul1.o
LD arch/x86/realmode/rm/realmode.elf
CC sound/core/sound.o
CC lib/crypto/utils.o
RELOCS arch/x86/realmode/rm/realmode.relocs
OBJCOPY arch/x86/realmode/rm/realmode.bin
AS arch/x86/realmode/rmpiggy.o
AR arch/x86/realmode/built-in.a
CC arch/x86/mm/pat/memtype_interval.o
CC ipc/ipc_sysctl.o
CC arch/x86/platform/efi/efi_32.o
CC arch/x86/events/amd/ibs.o
AR arch/x86/platform/intel/built-in.a
CC arch/x86/pci/mmconfig_32.o
CC security/selinux/selinuxfs.o
AR security/integrity/built-in.a
CC net/core/datagram.o
CC net/ethernet/eth.o
AR init/built-in.a
CC arch/x86/events/amd/uncore.o
AR drivers/leds/built-in.a
AS arch/x86/platform/efi/efi_stub_32.o
CC arch/x86/platform/efi/runtime-map.o
CC arch/x86/power/hibernate.o
CC block/partitions/efi.o
AS arch/x86/entry/vdso/vdso32/note.o
CC drivers/video/console/vgacon.o
CC drivers/pci/msi/api.o
CC mm/page-writeback.o
AS arch/x86/entry/vdso/vdso32/system_call.o
AR sound/i2c/other/built-in.a
CC kernel/power/qos.o
AR sound/i2c/built-in.a
AR arch/x86/events/zhaoxin/built-in.a
AS arch/x86/entry/vdso/vdso32/sigreturn.o
CC lib/crypto/chacha.o
AR arch/x86/platform/scx200/built-in.a
CC ipc/mqueue.o
CC arch/x86/kernel/cpu/mce/core.o
CC arch/x86/entry/vdso/vdso32/vclock_gettime.o
CC security/keys/keyctl.o
CC crypto/api.o
CC crypto/asymmetric_keys/public_key.o
CC drivers/pci/pcie/rcec.o
CC arch/x86/kernel/fpu/regset.o
CC drivers/pci/pcie/bwctrl.o
CC arch/x86/lib/insn.o
AR net/802/built-in.a
CC arch/x86/lib/kaslr.o
CC sound/core/seq/seq_queue.o
CC arch/x86/lib/memcpy_32.o
AS arch/x86/lib/memmove_32.o
CC lib/crypto/mpi/generic_mpih-mul2.o
AR arch/x86/platform/ts5500/built-in.a
CC arch/x86/mm/init_32.o
AR arch/x86/platform/uv/built-in.a
CC net/core/stream.o
CC arch/x86/entry/vdso/vdso32/vgetcpu.o
AR drivers/idle/built-in.a
CC arch/x86/mm/fault.o
CC arch/x86/kernel/cpu/mtrr/mtrr.o
CC fs/notify/notification.o
CC kernel/sched/build_utility.o
CC arch/x86/events/probe.o
CC sound/core/init.o
CC arch/x86/pci/direct.o
CC drivers/pci/msi/msi.o
CC fs/nfs_common/nfsacl.o
CC arch/x86/lib/misc.o
AR arch/x86/mm/pat/built-in.a
CC block/bio.o
CC arch/x86/lib/pc-conf-reg.o
AR arch/x86/power/built-in.a
CC sound/core/memory.o
CC lib/crypto/mpi/generic_mpih-mul3.o
AR arch/x86/platform/efi/built-in.a
AR arch/x86/platform/built-in.a
CC security/keys/permission.o
HOSTCC arch/x86/entry/vdso/vdso2c
CC net/sched/sch_generic.o
ASN.1 crypto/asymmetric_keys/x509.asn1.[ch]
AS arch/x86/lib/putuser.o
ASN.1 crypto/asymmetric_keys/x509_akid.asn1.[ch]
CC crypto/asymmetric_keys/x509_loader.o
CC kernel/locking/semaphore.o
AS arch/x86/lib/retpoline.o
AR drivers/char/ipmi/built-in.a
CC net/netlink/af_netlink.o
CC arch/x86/lib/string_32.o
CC drivers/acpi/acpica/dsargs.o
CC arch/x86/kernel/acpi/boot.o
CC arch/x86/lib/strstr_32.o
CC drivers/pci/pcie/aspm.o
CC arch/x86/kernel/apic/apic.o
AR block/partitions/built-in.a
CC arch/x86/kernel/fpu/signal.o
CC arch/x86/mm/ioremap.o
CC arch/x86/lib/usercopy.o
CC crypto/asymmetric_keys/x509_public_key.o
CC sound/core/seq/seq_fifo.o
CC fs/notify/group.o
CC arch/x86/kernel/acpi/sleep.o
AR arch/x86/events/amd/built-in.a
AR drivers/video/console/built-in.a
CC fs/iomap/trace.o
CC drivers/video/backlight/backlight.o
CC kernel/power/main.o
CC arch/x86/kernel/cpu/mtrr/if.o
CC arch/x86/entry/vdso/vdso32-setup.o
CC arch/x86/kernel/apic/apic_common.o
CC arch/x86/pci/mmconfig-shared.o
CC fs/nfs_common/grace.o
CC arch/x86/lib/usercopy_32.o
CC drivers/acpi/acpica/dscontrol.o
CC security/keys/process_keys.o
CC lib/crypto/mpi/generic_mpih-rshift.o
CC arch/x86/events/intel/ds.o
AR net/ethernet/built-in.a
CC fs/nfs_common/common.o
CC security/keys/request_key.o
AR drivers/pci/pwrctrl/built-in.a
CC net/sched/sch_mq.o
CC lib/zlib_inflate/inffast.o
CC ipc/namespace.o
VDSO arch/x86/entry/vdso/vdso32.so.dbg
CC net/sched/sch_frag.o
OBJCOPY arch/x86/entry/vdso/vdso32.so
VDSO2C arch/x86/entry/vdso/vdso-image-32.c
CC arch/x86/entry/vdso/vdso-image-32.o
CC block/elevator.o
CC drivers/pci/msi/irqdomain.o
CC kernel/locking/rwsem.o
CC arch/x86/lib/msr-smp.o
CC drivers/acpi/acpica/dsdebug.o
ASN.1 crypto/asymmetric_keys/pkcs7.asn1.[ch]
CC crypto/asymmetric_keys/pkcs7_trust.o
CC arch/x86/kernel/apic/apic_noop.o
CC lib/zlib_inflate/inflate.o
CC lib/zlib_deflate/deflate.o
CC arch/x86/kernel/fpu/xstate.o
CC drivers/pnp/pnpacpi/core.o
CC kernel/printk/printk.o
CC sound/core/seq/seq_prioq.o
CC fs/notify/mark.o
CC arch/x86/kernel/cpu/mtrr/generic.o
CC fs/notify/fdinfo.o
CC arch/x86/mm/extable.o
AR arch/x86/entry/vdso/built-in.a
CC arch/x86/entry/syscall_32.o
CC sound/core/seq/seq_timer.o
CC arch/x86/lib/cache-smp.o
CC mm/folio-compat.o
CC lib/crypto/mpi/generic_mpih-sub1.o
CC drivers/acpi/acpica/dsfield.o
CC crypto/asymmetric_keys/pkcs7_verify.o
AR drivers/video/backlight/built-in.a
CC arch/x86/kernel/cpu/mce/severity.o
AR drivers/video/fbdev/core/built-in.a
CC drivers/pnp/pnpacpi/rsparser.o
AR drivers/video/fbdev/omap/built-in.a
CC arch/x86/lib/crc32-glue.o
AS arch/x86/kernel/acpi/wakeup_32.o
CC drivers/video/aperture.o
CC ipc/mq_sysctl.o
AR drivers/video/fbdev/omap2/omapfb/dss/built-in.a
CC arch/x86/kernel/acpi/cstate.o
AR fs/nfs_common/built-in.a
CC drivers/video/cmdline.o
AR drivers/video/fbdev/omap2/omapfb/displays/built-in.a
AR drivers/video/fbdev/omap2/omapfb/built-in.a
AR drivers/video/fbdev/omap2/built-in.a
AR drivers/video/fbdev/built-in.a
CC lib/zlib_deflate/deftree.o
CC kernel/power/console.o
CC arch/x86/pci/fixup.o
CC drivers/pci/pcie/pme.o
CC arch/x86/kernel/kprobes/core.o
CC io_uring/kbuf.o
CC arch/x86/kernel/cpu/mce/genpool.o
CC net/core/scm.o
CC lib/zlib_inflate/infutil.o
CC fs/iomap/iter.o
AR drivers/pci/msi/built-in.a
CC security/keys/request_key_auth.o
CC lib/crypto/mpi/generic_mpih-add1.o
AR net/bpf/built-in.a
CC io_uring/rsrc.o
CC kernel/locking/percpu-rwsem.o
CC arch/x86/kernel/apic/ipi.o
CC lib/zlib_deflate/deflate_syms.o
CC crypto/asymmetric_keys/x509.asn1.o
CC drivers/acpi/acpica/dsinit.o
AR ipc/built-in.a
AS arch/x86/lib/crc32-pclmul.o
CC crypto/asymmetric_keys/x509_akid.asn1.o
CC lib/crypto/aes.o
CC arch/x86/lib/msr.o
CC crypto/asymmetric_keys/x509_cert_parser.o
CC sound/core/seq/seq_system.o
CC kernel/power/process.o
CC crypto/cipher.o
AR arch/x86/kernel/acpi/built-in.a
CC arch/x86/kernel/cpu/microcode/core.o
CC mm/readahead.o
CC net/core/gen_stats.o
CC lib/zlib_inflate/inftrees.o
CC block/blk-core.o
CC lib/crypto/arc4.o
AR fs/notify/built-in.a
CC arch/x86/mm/mmap.o
AR drivers/amba/built-in.a
CC security/selinux/netlink.o
CC kernel/locking/spinlock.o
CC drivers/pci/hotplug/pci_hotplug_core.o
AR lib/zlib_deflate/built-in.a
AS arch/x86/lib/msr-reg.o
CC net/sched/sch_api.o
CC arch/x86/kernel/cpu/mtrr/cleanup.o
CC drivers/acpi/acpica/dsmethod.o
CC lib/zlib_inflate/inflate_syms.o
CC lib/crypto/mpi/mpicoder.o
CC io_uring/notif.o
CC arch/x86/entry/common.o
AR arch/x86/kernel/fpu/built-in.a
CC drivers/video/nomodeset.o
CC arch/x86/mm/pgtable.o
CC arch/x86/events/intel/knc.o
CC arch/x86/kernel/cpu/mce/intel.o
CC crypto/asymmetric_keys/pkcs7.asn1.o
CC arch/x86/kernel/cpu/mce/amd.o
CC kernel/printk/printk_safe.o
AR drivers/pnp/pnpacpi/built-in.a
CC drivers/pnp/core.o
CC arch/x86/kernel/apic/vector.o
CC arch/x86/events/utils.o
CC security/keys/user_defined.o
CC crypto/asymmetric_keys/pkcs7_parser.o
CC fs/iomap/buffered-io.o
CC net/sched/sch_blackhole.o
AR drivers/pci/pcie/built-in.a
CC sound/core/seq/seq_ports.o
CC sound/core/seq/seq_info.o
CC arch/x86/lib/msr-reg-export.o
CC kernel/locking/osq_lock.o
CC arch/x86/pci/acpi.o
CC mm/swap.o
AR lib/zlib_inflate/built-in.a
CC fs/quota/dquot.o
CC arch/x86/kernel/kprobes/opt.o
CC drivers/video/hdmi.o
CC mm/truncate.o
CC net/sched/cls_api.o
CC net/netlink/genetlink.o
CC drivers/acpi/acpica/dsmthdat.o
AS arch/x86/lib/hweight.o
CC arch/x86/kernel/cpu/microcode/intel.o
CC arch/x86/lib/iomem.o
CC mm/vmscan.o
CC kernel/locking/qspinlock.o
CC fs/proc/task_mmu.o
CC kernel/printk/nbcon.o
CC fs/iomap/direct-io.o
CC arch/x86/lib/atomic64_32.o
CC arch/x86/kernel/cpu/mtrr/amd.o
CC lib/crypto/mpi/mpi-add.o
CC security/selinux/nlmsgtab.o
CC security/selinux/netif.o
CC net/core/gen_estimator.o
CC kernel/power/suspend.o
CC arch/x86/mm/physaddr.o
AR crypto/asymmetric_keys/built-in.a
CC crypto/compress.o
CC drivers/pci/hotplug/acpi_pcihp.o
CC security/keys/proc.o
CC kernel/irq/irqdesc.o
CC drivers/pnp/card.o
CC sound/core/control.o
CC net/netlink/policy.o
AS arch/x86/entry/thunk.o
CC kernel/irq/handle.o
CC fs/proc/inode.o
CC drivers/acpi/acpica/dsobject.o
CC arch/x86/events/intel/lbr.o
AR arch/x86/entry/built-in.a
CC arch/x86/lib/inat.o
AR drivers/clk/actions/built-in.a
AR drivers/clk/analogbits/built-in.a
AR drivers/clk/bcm/built-in.a
CC block/blk-sysfs.o
AR drivers/clk/imgtec/built-in.a
AR drivers/clk/imx/built-in.a
AR drivers/clk/ingenic/built-in.a
AR drivers/clk/mediatek/built-in.a
CC kernel/locking/rtmutex_api.o
AR drivers/clk/microchip/built-in.a
CC arch/x86/kernel/apic/init.o
AR arch/x86/lib/built-in.a
AR drivers/clk/mstar/built-in.a
AR arch/x86/lib/lib.a
AR drivers/clk/mvebu/built-in.a
AR drivers/clk/ralink/built-in.a
AR drivers/clk/renesas/built-in.a
CC security/keys/sysctl.o
AR drivers/clk/socfpga/built-in.a
CC sound/core/seq/seq_dummy.o
CC io_uring/tctx.o
AR drivers/clk/sophgo/built-in.a
CC arch/x86/pci/legacy.o
AR drivers/clk/sprd/built-in.a
CC security/keys/keyctl_pkey.o
CC arch/x86/mm/tlb.o
AR drivers/clk/starfive/built-in.a
AR drivers/clk/sunxi-ng/built-in.a
AR drivers/clk/ti/built-in.a
AR drivers/clk/versatile/built-in.a
AR drivers/video/built-in.a
AR drivers/clk/xilinx/built-in.a
CC net/core/net_namespace.o
AR drivers/clk/built-in.a
AR arch/x86/kernel/kprobes/built-in.a
CC lib/lzo/lzo1x_compress.o
CC arch/x86/kernel/apic/hw_nmi.o
AR kernel/sched/built-in.a
CC net/ethtool/ioctl.o
CC arch/x86/kernel/cpu/mtrr/cyrix.o
CC arch/x86/kernel/cpu/cacheinfo.o
CC net/netfilter/core.o
CC drivers/acpi/acpica/dsopcode.o
CC arch/x86/kernel/cpu/microcode/amd.o
CC crypto/algapi.o
CC lib/crypto/mpi/mpi-bit.o
CC kernel/printk/printk_ringbuffer.o
CC drivers/pnp/driver.o
CC kernel/locking/qrwlock.o
CC drivers/acpi/acpica/dspkginit.o
AR drivers/pci/hotplug/built-in.a
CC arch/x86/kernel/cpu/mce/threshold.o
AR drivers/pci/controller/dwc/built-in.a
AR drivers/pci/controller/mobiveil/built-in.a
CC kernel/irq/manage.o
AR drivers/pci/controller/plda/built-in.a
AR drivers/pci/controller/built-in.a
CC arch/x86/kernel/cpu/scattered.o
CC arch/x86/kernel/cpu/mtrr/centaur.o
AR drivers/pci/switch/built-in.a
CC drivers/pci/access.o
CC net/netfilter/nf_log.o
CC sound/core/misc.o
CC arch/x86/events/intel/p4.o
CC fs/kernfs/mount.o
LDS arch/x86/kernel/vmlinux.lds
CC arch/x86/kernel/cpu/topology_common.o
CC crypto/scatterwalk.o
CC lib/lzo/lzo1x_decompress_safe.o
AR sound/core/seq/built-in.a
CC net/sched/act_api.o
CC io_uring/filetable.o
CC security/selinux/netnode.o
CC fs/proc/root.o
CC fs/iomap/fiemap.o
AR security/keys/built-in.a
CC kernel/rcu/update.o
CC arch/x86/pci/irq.o
CC io_uring/rw.o
CC arch/x86/kernel/apic/io_apic.o
CC drivers/acpi/acpica/dsutils.o
CC kernel/printk/sysctl.o
CC kernel/power/hibernate.o
CC arch/x86/events/rapl.o
CC fs/sysfs/file.o
CC block/blk-flush.o
CC drivers/acpi/acpica/dswexec.o
CC drivers/pnp/resource.o
AR kernel/locking/built-in.a
CC net/ethtool/common.o
CC lib/crypto/mpi/mpi-cmp.o
CC lib/crypto/gf128mul.o
CC arch/x86/kernel/cpu/mtrr/legacy.o
AR net/netlink/built-in.a
CC arch/x86/mm/cpu_entry_area.o
CC block/blk-settings.o
CC fs/proc/base.o
CC net/core/secure_seq.o
CC net/netfilter/nf_queue.o
AR kernel/printk/built-in.a
CC kernel/power/snapshot.o
AR drivers/acpi/pmic/built-in.a
AR lib/lzo/built-in.a
CC kernel/rcu/sync.o
CC fs/iomap/seek.o
CC arch/x86/pci/common.o
CC security/min_addr.o
CC kernel/rcu/srcutree.o
AR arch/x86/kernel/cpu/microcode/built-in.a
CC net/ethtool/netlink.o
CC net/netfilter/nf_sockopt.o
CC sound/core/device.o
CC net/ipv4/netfilter/nf_defrag_ipv4.o
CC block/blk-ioc.o
CC drivers/acpi/acpica/dswload.o
CC drivers/pci/bus.o
CC net/ipv4/route.o
CC fs/quota/quota_v2.o
CC lib/crypto/blake2s.o
AR arch/x86/kernel/cpu/mtrr/built-in.a
CC fs/kernfs/inode.o
CC sound/core/info.o
CC crypto/proc.o
CC net/ethtool/bitset.o
AR arch/x86/kernel/cpu/mce/built-in.a
CC arch/x86/kernel/cpu/topology_ext.o
CC lib/crypto/mpi/mpi-sub-ui.o
CC net/sched/sch_fifo.o
AR kernel/livepatch/built-in.a
CC mm/shrinker.o
CC arch/x86/events/intel/p6.o
CC security/security.o
CC fs/quota/quota_tree.o
CC fs/sysfs/dir.o
CC drivers/pnp/manager.o
CC security/lsm_audit.o
CC arch/x86/mm/maccess.o
CC lib/crypto/blake2s-generic.o
CC drivers/acpi/acpica/dswload2.o
CC net/xfrm/xfrm_policy.o
CC security/selinux/netport.o
CC drivers/pci/probe.o
CC kernel/irq/spurious.o
CC fs/iomap/swapfile.o
CC arch/x86/pci/early.o
CC arch/x86/kernel/cpu/topology_amd.o
CC mm/shmem.o
CC arch/x86/mm/pgprot.o
CC fs/quota/quota.o
AR sound/drivers/opl3/built-in.a
CC block/blk-map.o
CC kernel/power/swap.o
AR sound/drivers/opl4/built-in.a
AR sound/drivers/mpu401/built-in.a
AR sound/drivers/vx/built-in.a
AR sound/drivers/pcsp/built-in.a
AR sound/drivers/built-in.a
CC kernel/irq/resend.o
CC crypto/aead.o
CC net/ethtool/strset.o
CC io_uring/net.o
CC net/unix/af_unix.o
CC lib/crypto/mpi/mpi-div.o
CC net/ipv6/netfilter/ip6_tables.o
CC fs/sysfs/symlink.o
CC net/packet/af_packet.o
CC fs/kernfs/dir.o
CC drivers/acpi/acpica/dswscope.o
CC arch/x86/kernel/apic/msi.o
CC fs/quota/kqid.o
CC kernel/dma/mapping.o
CC drivers/pnp/support.o
CC lib/crypto/mpi/mpi-mod.o
CC net/core/flow_dissector.o
CC sound/core/isadma.o
CC arch/x86/kernel/cpu/common.o
CC io_uring/poll.o
CC net/ipv4/netfilter/nf_reject_ipv4.o
CC net/ipv4/netfilter/ip_tables.o
CC arch/x86/events/intel/pt.o
CC net/netfilter/utils.o
CC arch/x86/mm/pgtable_32.o
AR net/dsa/built-in.a
CC io_uring/eventfd.o
CC arch/x86/pci/bus_numa.o
CC net/ipv4/inetpeer.o
CC lib/lz4/lz4_decompress.o
CC lib/zstd/zstd_decompress_module.o
CC kernel/irq/chip.o
CC net/sched/cls_cgroup.o
CC drivers/acpi/acpica/dswstate.o
AR fs/iomap/built-in.a
CC security/selinux/status.o
CC lib/crypto/sha1.o
CC net/netfilter/nfnetlink.o
AR sound/isa/ad1816a/built-in.a
AR sound/isa/ad1848/built-in.a
CC sound/core/vmaster.o
AR sound/isa/cs423x/built-in.a
CC drivers/dma/dw/core.o
AR sound/isa/es1688/built-in.a
AR sound/isa/galaxy/built-in.a
CC drivers/pnp/interface.o
AR sound/isa/gus/built-in.a
AR sound/isa/msnd/built-in.a
CC drivers/pnp/quirks.o
AR sound/isa/opti9xx/built-in.a
AR sound/isa/sb/built-in.a
CC lib/crypto/mpi/mpi-mul.o
CC fs/sysfs/mount.o
AR sound/isa/wavefront/built-in.a
AR sound/isa/wss/built-in.a
AR sound/isa/built-in.a
CC drivers/dma/dw/dw.o
CC lib/zstd/decompress/huf_decompress.o
CC kernel/dma/direct.o
CC drivers/dma/dw/idma32.o
CC block/blk-merge.o
CC arch/x86/kernel/apic/probe_32.o
CC crypto/geniv.o
CC drivers/acpi/acpica/evevent.o
CC drivers/acpi/acpica/evgpe.o
CC sound/core/ctljack.o
CC fs/proc/generic.o
CC arch/x86/mm/iomap_32.o
CC arch/x86/pci/amd_bus.o
CC arch/x86/kernel/cpu/rdrand.o
CC fs/quota/netlink.o
CC net/ethtool/linkinfo.o
CC drivers/pci/host-bridge.o
CC kernel/power/user.o
CC kernel/rcu/tree.o
CC mm/util.o
CC drivers/acpi/dptf/int340x_thermal.o
AR arch/x86/kernel/apic/built-in.a
CC kernel/entry/common.o
CC kernel/irq/dummychip.o
CC sound/core/jack.o
CC security/device_cgroup.o
CC fs/kernfs/file.o
CC lib/crypto/mpi/mpih-cmp.o
CC drivers/acpi/x86/apple.o
CC drivers/acpi/acpica/evgpeblk.o
CC drivers/pnp/system.o
CC net/ipv6/netfilter/ip6table_filter.o
CC arch/x86/events/msr.o
CC mm/mmzone.o
CC security/selinux/ss/ebitmap.o
CC net/sched/ematch.o
CC fs/sysfs/group.o
CC arch/x86/mm/hugetlbpage.o
CC security/selinux/ss/hashtab.o
CC arch/x86/events/intel/uncore.o
CC kernel/entry/syscall_user_dispatch.o
CC net/sunrpc/auth_gss/auth_gss.o
CC arch/x86/kernel/cpu/match.o
AR lib/lz4/built-in.a
AR drivers/acpi/dptf/built-in.a
CC net/sunrpc/clnt.o
CC fs/devpts/inode.o
CC drivers/dma/dw/acpi.o
CC kernel/irq/devres.o
CC crypto/lskcipher.o
CC drivers/pci/remove.o
CC fs/netfs/buffered_read.o
CC net/netfilter/nfnetlink_log.o
CC lib/crypto/mpi/mpih-div.o
AR arch/x86/pci/built-in.a
CC drivers/pci/pci.o
CC net/ipv4/netfilter/iptable_filter.o
CC fs/proc/array.o
CC io_uring/uring_cmd.o
CC drivers/acpi/acpica/evgpeinit.o
AR fs/quota/built-in.a
CC drivers/acpi/x86/cmos_rtc.o
CC kernel/power/poweroff.o
CC fs/netfs/buffered_write.o
CC net/sunrpc/auth_gss/gss_mech_switch.o
AR drivers/pnp/built-in.a
CC drivers/dma/hsu/hsu.o
CC lib/xz/xz_dec_syms.o
CC sound/core/hwdep.o
CC drivers/pci/pci-driver.o
CC crypto/skcipher.o
CC lib/zstd/decompress/zstd_ddict.o
CC net/ethtool/linkmodes.o
CC arch/x86/kernel/cpu/bugs.o
AR kernel/power/built-in.a
CC net/ipv4/protocol.o
CC net/core/sysctl_net_core.o
CC arch/x86/mm/dump_pagetables.o
CC lib/zstd/decompress/zstd_decompress.o
CC net/ipv6/netfilter/ip6table_mangle.o
AR fs/sysfs/built-in.a
AS arch/x86/kernel/head_32.o
CC kernel/irq/kexec.o
CC kernel/dma/ops_helpers.o
CC drivers/acpi/acpica/evgpeutil.o
CC net/ipv4/netfilter/iptable_mangle.o
CC net/ipv6/af_inet6.o
CC drivers/acpi/tables.o
CC sound/core/timer.o
CC net/unix/garbage.o
CC block/blk-timeout.o
CC fs/kernfs/symlink.o
AR kernel/entry/built-in.a
CC fs/ext4/balloc.o
CC mm/vmstat.o
CC lib/xz/xz_dec_stream.o
AR drivers/dma/dw/built-in.a
CC fs/jbd2/transaction.o
CC net/unix/sysctl_net_unix.o
CC net/sunrpc/auth_gss/svcauth_gss.o
AR fs/devpts/built-in.a
CC fs/ext4/bitmap.o
CC drivers/acpi/x86/lpss.o
AR net/sched/built-in.a
CC mm/backing-dev.o
CC drivers/acpi/acpica/evglock.o
CC lib/crypto/mpi/mpih-mul.o
CC kernel/irq/autoprobe.o
CC mm/mm_init.o
CC security/selinux/ss/symtab.o
CC mm/percpu.o
CC net/ipv4/ip_input.o
AR drivers/dma/hsu/built-in.a
AR drivers/dma/idxd/built-in.a
AR drivers/dma/amd/built-in.a
AR drivers/dma/mediatek/built-in.a
AR drivers/dma/qcom/built-in.a
AR drivers/dma/stm32/built-in.a
CC mm/slab_common.o
AR drivers/dma/ti/built-in.a
CC fs/proc/fd.o
AR drivers/dma/xilinx/built-in.a
CC kernel/dma/remap.o
CC drivers/dma/dmaengine.o
CC drivers/dma/virt-dma.o
CC lib/xz/xz_dec_lzma2.o
CC security/selinux/ss/sidtab.o
CC fs/netfs/direct_read.o
CC arch/x86/mm/highmem_32.o
CC block/blk-lib.o
CC net/xfrm/xfrm_state.o
CC io_uring/openclose.o
AR fs/kernfs/built-in.a
CC fs/proc/proc_tty.o
CC drivers/acpi/acpica/evhandler.o
CC lib/zstd/decompress/zstd_decompress_block.o
CC net/ethtool/rss.o
CC lib/xz/xz_dec_bcj.o
CC kernel/irq/irqdomain.o
CC crypto/seqiv.o
CC arch/x86/events/intel/uncore_nhmex.o
AR net/packet/built-in.a
CC sound/core/hrtimer.o
CC kernel/module/main.o
CC kernel/module/strict_rwx.o
CC block/blk-mq.o
CC net/netfilter/nf_conntrack_core.o
CC drivers/acpi/x86/s2idle.o
CC net/ipv4/netfilter/ipt_REJECT.o
CC kernel/module/kmod.o
CC fs/proc/cmdline.o
CC net/ipv6/netfilter/nf_defrag_ipv6_hooks.o
CC drivers/acpi/acpica/evmisc.o
CC net/core/dev.o
AR net/unix/built-in.a
CC lib/crypto/mpi/mpi-pow.o
AR kernel/dma/built-in.a
CC net/ipv4/ip_fragment.o
CC fs/jbd2/commit.o
CC lib/dim/dim.o
AR arch/x86/mm/built-in.a
CC mm/compaction.o
CC fs/netfs/direct_write.o
CC arch/x86/events/intel/uncore_snb.o
CC net/sunrpc/auth_gss/gss_rpc_upcall.o
CC lib/fonts/fonts.o
AR lib/xz/built-in.a
CC arch/x86/kernel/cpu/aperfmperf.o
CC net/ipv6/anycast.o
CC sound/core/pcm.o
CC sound/core/pcm_native.o
CC kernel/irq/proc.o
CC [M] net/ipv4/netfilter/iptable_nat.o
AR net/wireless/tests/built-in.a
CC net/wireless/core.o
CC kernel/time/time.o
CC kernel/futex/core.o
CC crypto/echainiv.o
CC drivers/acpi/acpica/evregion.o
CC net/ipv6/netfilter/nf_conntrack_reasm.o
CC fs/proc/consoles.o
CC io_uring/sqpoll.o
CC net/netfilter/nf_conntrack_standalone.o
CC lib/dim/net_dim.o
CC lib/fonts/font_8x16.o
CC fs/ext4/block_validity.o
CC sound/core/pcm_lib.o
CC drivers/dma/acpi-dma.o
CC arch/x86/events/intel/uncore_snbep.o
CC kernel/rcu/rcu_segcblist.o
CC drivers/acpi/x86/utils.o
CC net/ethtool/linkstate.o
CC security/selinux/ss/avtab.o
CC lib/crypto/mpi/mpiutil.o
CC drivers/acpi/acpica/evrgnini.o
AR lib/fonts/built-in.a
CC security/selinux/ss/policydb.o
AR sound/pci/ac97/built-in.a
CC lib/zstd/zstd_common_module.o
CC security/selinux/ss/services.o
AR sound/pci/ali5451/built-in.a
AR sound/pci/asihpi/built-in.a
AR sound/pci/au88x0/built-in.a
CC arch/x86/kernel/cpu/cpuid-deps.o
CC net/ethtool/debug.o
AR sound/pci/aw2/built-in.a
AR sound/pci/ctxfi/built-in.a
AR sound/pci/ca0106/built-in.a
AR sound/pci/cs46xx/built-in.a
AR sound/pci/cs5535audio/built-in.a
CC crypto/ahash.o
AR sound/pci/lola/built-in.a
CC fs/proc/cpuinfo.o
CC net/ethtool/wol.o
AR sound/pci/lx6464es/built-in.a
AR sound/pci/echoaudio/built-in.a
CC fs/netfs/iterator.o
CC kernel/irq/migration.o
AR sound/pci/emu10k1/built-in.a
CC sound/pci/hda/hda_bind.o
CC drivers/pci/search.o
AR sound/pci/ice1712/built-in.a
CC drivers/pci/rom.o
CC crypto/shash.o
CC kernel/futex/syscalls.o
CC net/core/dev_addr_lists.o
CC sound/pci/hda/hda_codec.o
CC net/core/dst.o
CC drivers/acpi/acpica/evsci.o
CC fs/jbd2/recovery.o
CC net/sunrpc/auth_gss/gss_rpc_xdr.o
CC arch/x86/kernel/cpu/umwait.o
CC kernel/time/timer.o
AR drivers/dma/built-in.a
CC drivers/acpi/x86/blacklist.o
AR kernel/rcu/built-in.a
CC net/sunrpc/auth_gss/trace.o
CC net/netfilter/nf_conntrack_expect.o
AR lib/crypto/mpi/built-in.a
CC fs/ext4/dir.o
CC lib/dim/rdma_dim.o
AR net/ipv4/netfilter/built-in.a
AR drivers/soc/apple/built-in.a
CC lib/crypto/sha256.o
CC net/ipv4/ip_forward.o
AR drivers/soc/aspeed/built-in.a
AR sound/ppc/built-in.a
CC fs/proc/devices.o
AR drivers/soc/bcm/built-in.a
AR drivers/soc/fsl/built-in.a
CC kernel/irq/cpuhotplug.o
AR drivers/soc/fujitsu/built-in.a
AR drivers/soc/hisilicon/built-in.a
AR drivers/soc/imx/built-in.a
AR drivers/soc/ixp4xx/built-in.a
AR drivers/soc/loongson/built-in.a
CC arch/x86/events/intel/uncore_discovery.o
CC drivers/acpi/acpica/evxface.o
AR drivers/soc/mediatek/built-in.a
AR drivers/soc/microchip/built-in.a
CC kernel/futex/pi.o
CC block/blk-mq-tag.o
AR drivers/soc/nuvoton/built-in.a
AR drivers/soc/pxa/built-in.a
AR drivers/soc/amlogic/built-in.a
AR drivers/soc/qcom/built-in.a
CC fs/ramfs/inode.o
AR drivers/soc/renesas/built-in.a
AR drivers/soc/rockchip/built-in.a
AR drivers/soc/sunxi/built-in.a
AR drivers/soc/ti/built-in.a
AR drivers/soc/versatile/built-in.a
AR drivers/soc/xilinx/built-in.a
AR drivers/soc/built-in.a
CC sound/pci/hda/hda_jack.o
CC net/ipv6/netfilter/nf_reject_ipv6.o
CC drivers/pci/setup-res.o
AR lib/dim/built-in.a
CC security/selinux/ss/conditional.o
CC kernel/time/hrtimer.o
CC fs/ext4/ext4_jbd2.o
AR drivers/acpi/x86/built-in.a
AR sound/arm/built-in.a
CC net/ipv6/ip6_output.o
MKCAP arch/x86/kernel/cpu/capflags.c
CC kernel/irq/pm.o
CC lib/zstd/common/debug.o
CC crypto/akcipher.o
CC lib/zstd/common/entropy_common.o
CC fs/netfs/locking.o
CC kernel/module/tree_lookup.o
CC io_uring/xattr.o
CC net/ethtool/features.o
CC net/xfrm/xfrm_hash.o
CC fs/netfs/main.o
CC arch/x86/kernel/head32.o
AR lib/crypto/built-in.a
CC drivers/acpi/acpica/evxfevnt.o
AR sound/sh/built-in.a
CC net/sunrpc/auth_gss/gss_krb5_mech.o
CC lib/zstd/common/error_private.o
CC lib/zstd/common/fse_decompress.o
CC fs/proc/interrupts.o
CC net/ipv4/ip_options.o
CC lib/zstd/common/zstd_common.o
CC fs/jbd2/checkpoint.o
CC net/ipv6/ip6_input.o
CC fs/hugetlbfs/inode.o
CC kernel/module/kallsyms.o
CC kernel/futex/requeue.o
CC kernel/module/procfs.o
CC net/netfilter/nf_conntrack_helper.o
CC fs/ramfs/file-mmu.o
CC drivers/acpi/acpica/evxfgpe.o
CC security/selinux/ss/mls.o
CC net/ethtool/privflags.o
CC mm/show_mem.o
AR sound/pci/korg1212/built-in.a
CC arch/x86/kernel/ebda.o
CC block/blk-stat.o
CC sound/core/pcm_misc.o
CC net/xfrm/xfrm_input.o
CC drivers/pci/irq.o
CC drivers/pci/vpd.o
CC fs/proc/loadavg.o
CC kernel/irq/msi.o
CC arch/x86/events/intel/cstate.o
AR lib/zstd/built-in.a
CC lib/argv_split.o
CC net/sunrpc/xprt.o
CC fs/fat/cache.o
CC crypto/sig.o
CC net/ipv4/ip_output.o
CC net/ipv6/addrconf.o
CC io_uring/nop.o
CC net/ipv6/addrlabel.o
CC fs/isofs/namei.o
CC drivers/acpi/acpica/evxfregn.o
CC fs/isofs/inode.o
CC fs/jbd2/revoke.o
CC kernel/module/sysfs.o
AR sound/synth/emux/built-in.a
AR sound/synth/built-in.a
CC kernel/futex/waitwake.o
CC net/ipv6/route.o
CC lib/bug.o
AR fs/ramfs/built-in.a
CC net/wireless/sysfs.o
CC fs/fat/dir.o
CC kernel/irq/affinity.o
CC fs/netfs/misc.o
CC kernel/cgroup/cgroup.o
CC net/ipv6/netfilter/ip6t_ipv6header.o
CC kernel/trace/trace_clock.o
CC kernel/cgroup/rstat.o
CC fs/proc/meminfo.o
CC block/blk-mq-sysfs.o
CC kernel/time/sleep_timeout.o
CC fs/ext4/extents.o
CC drivers/acpi/acpica/exconcat.o
CC sound/core/pcm_memory.o
CC drivers/acpi/acpica/exconfig.o
CC net/sunrpc/socklib.o
CC sound/pci/hda/hda_auto_parser.o
CC mm/interval_tree.o
CC net/netfilter/nf_conntrack_proto.o
CC drivers/pci/setup-bus.o
AR arch/x86/events/intel/built-in.a
CC fs/isofs/dir.o
AR arch/x86/events/built-in.a
CC net/ipv4/ip_sockglue.o
CC net/ethtool/rings.o
CC net/sunrpc/auth_gss/gss_krb5_seal.o
CC crypto/kpp.o
ASN.1 crypto/rsapubkey.asn1.[ch]
CC fs/proc/stat.o
CC io_uring/fs.o
CC kernel/trace/ring_buffer.o
CC net/ethtool/channels.o
CC io_uring/splice.o
CC drivers/pci/vc.o
CC lib/buildid.o
AR sound/usb/misc/built-in.a
CC net/ipv4/inet_hashtables.o
CC security/selinux/ss/context.o
AR sound/usb/usx2y/built-in.a
AR fs/hugetlbfs/built-in.a
AR kernel/module/built-in.a
AR sound/usb/caiaq/built-in.a
CC drivers/acpi/acpica/exconvrt.o
AR sound/usb/6fire/built-in.a
CC drivers/virtio/virtio.o
CC kernel/time/timekeeping.o
CC drivers/tty/vt/vt_ioctl.o
AR sound/usb/hiface/built-in.a
CC drivers/virtio/virtio_ring.o
AR kernel/futex/built-in.a
CC kernel/irq/matrix.o
AR sound/usb/bcd2000/built-in.a
CC net/wireless/radiotap.o
AR sound/usb/built-in.a
CC net/core/netevent.o
CC fs/jbd2/journal.o
CC drivers/tty/vt/vc_screen.o
CC block/blk-mq-cpumap.o
CC fs/nfs/client.o
CC sound/core/memalloc.o
CC fs/netfs/objects.o
CC net/xfrm/xfrm_output.o
CC fs/proc/uptime.o
CC drivers/acpi/acpica/excreate.o
CC net/netfilter/nf_conntrack_proto_generic.o
CC block/blk-mq-sched.o
CC fs/isofs/util.o
CC mm/list_lru.o
ASN.1 crypto/rsaprivkey.asn1.[ch]
CC crypto/rsa.o
CC net/ipv6/netfilter/ip6t_REJECT.o
CC fs/exportfs/expfs.o
CC lib/clz_tab.o
CC sound/pci/hda/hda_sysfs.o
CC io_uring/sync.o
CC lib/cmdline.o
CC net/sunrpc/auth_gss/gss_krb5_unseal.o
CC sound/pci/hda/hda_controller.o
CC net/wireless/util.o
CC drivers/acpi/osi.o
CC net/xfrm/xfrm_sysctl.o
CC fs/fat/fatent.o
CC lib/cpumask.o
CC drivers/acpi/acpica/exdebug.o
CC drivers/tty/vt/selection.o
CC net/ethtool/coalesce.o
CC security/selinux/netlabel.o
CC arch/x86/kernel/cpu/powerflags.o
CC drivers/pci/mmap.o
AR net/mac80211/tests/built-in.a
CC fs/proc/util.o
CC net/mac80211/main.o
CC net/netlabel/netlabel_user.o
CC drivers/char/hw_random/core.o
CC net/rfkill/core.o
CC net/9p/mod.o
CC fs/isofs/rock.o
CC fs/isofs/export.o
CC drivers/acpi/acpica/exdump.o
CC sound/core/pcm_timer.o
AR kernel/irq/built-in.a
CC fs/netfs/read_collect.o
CC crypto/rsa_helper.o
CC net/dns_resolver/dns_key.o
CC mm/workingset.o
AR fs/exportfs/built-in.a
CC fs/proc/version.o
CC net/handshake/alert.o
AR drivers/iommu/amd/built-in.a
CC sound/core/seq_device.o
AR drivers/iommu/intel/built-in.a
AR drivers/iommu/arm/arm-smmu/built-in.a
AR drivers/iommu/arm/arm-smmu-v3/built-in.a
AR drivers/iommu/arm/built-in.a
CC arch/x86/kernel/cpu/topology.o
CC drivers/acpi/acpica/exfield.o
CC lib/ctype.o
AR drivers/iommu/iommufd/built-in.a
AR drivers/iommu/riscv/built-in.a
CC drivers/iommu/iommu.o
CC lib/dec_and_lock.o
CC io_uring/msg_ring.o
CC block/ioctl.o
CC kernel/time/ntp.o
CC drivers/char/hw_random/intel-rng.o
CC net/xfrm/xfrm_replay.o
CC net/netfilter/nf_conntrack_proto_tcp.o
CC crypto/rsa-pkcs1pad.o
CC drivers/pci/devres.o
CC drivers/tty/vt/keyboard.o
CC drivers/tty/hvc/hvc_console.o
CC net/9p/client.o
CC lib/decompress.o
CC net/sunrpc/auth_gss/gss_krb5_wrap.o
CC lib/decompress_bunzip2.o
CC drivers/virtio/virtio_anchor.o
CC sound/pci/hda/hda_proc.o
AR net/ipv6/netfilter/built-in.a
CC net/core/neighbour.o
CC drivers/acpi/acpica/exfldio.o
CC net/dns_resolver/dns_query.o
CC net/ipv4/inet_timewait_sock.o
CC fs/proc/softirqs.o
CC net/sunrpc/auth_gss/gss_krb5_crypto.o
CC fs/nfs/dir.o
CC lib/decompress_inflate.o
CC fs/isofs/joliet.o
CC net/ipv6/ip6_fib.o
CC fs/fat/file.o
AR sound/core/built-in.a
CC arch/x86/kernel/platform-quirks.o
CC net/rfkill/input.o
CC net/netlabel/netlabel_kapi.o
CC net/ethtool/pause.o
CC net/ethtool/eee.o
CC mm/debug.o
CC drivers/virtio/virtio_pci_modern_dev.o
CC net/devres.o
AR security/selinux/built-in.a
CC drivers/char/hw_random/amd-rng.o
AR security/built-in.a
CC drivers/char/hw_random/geode-rng.o
CC drivers/acpi/acpica/exmisc.o
CC drivers/char/hw_random/via-rng.o
CC kernel/time/clocksource.o
CC crypto/rsassa-pkcs1.o
CC io_uring/advise.o
CC crypto/acompress.o
CC drivers/pci/proc.o
CC fs/proc/namespaces.o
CC net/wireless/reg.o
CC lib/decompress_unlz4.o
AR drivers/tty/hvc/built-in.a
CC block/genhd.o
CC drivers/acpi/acpica/exmutex.o
CC fs/netfs/read_pgpriv2.o
AR fs/jbd2/built-in.a
CC net/socket.o
CC fs/isofs/compress.o
CC kernel/trace/trace.o
CC net/handshake/genl.o
AR net/rfkill/built-in.a
CC net/ipv4/inet_connection_sock.o
AR net/dns_resolver/built-in.a
CC net/ipv4/tcp.o
CC net/ethtool/tsinfo.o
CC block/ioprio.o
CC fs/nfs/file.o
CC arch/x86/kernel/cpu/proc.o
CC net/xfrm/xfrm_device.o
CC drivers/virtio/virtio_pci_legacy_dev.o
CC drivers/acpi/acpica/exnames.o
CC drivers/virtio/virtio_pci_modern.o
CC mm/gup.o
AR drivers/char/hw_random/built-in.a
CC sound/pci/hda/hda_hwdep.o
CC drivers/char/agp/backend.o
CC drivers/tty/vt/vt.o
CC lib/decompress_unlzma.o
CC fs/fat/inode.o
CC drivers/char/mem.o
CC drivers/char/agp/generic.o
CC drivers/virtio/virtio_pci_common.o
AR drivers/gpu/host1x/built-in.a
CC mm/mmap_lock.o
CC io_uring/epoll.o
CC net/sunrpc/auth_gss/gss_krb5_keys.o
CC drivers/iommu/iommu-traces.o
CC fs/proc/self.o
CC crypto/scompress.o
AR drivers/gpu/drm/tests/built-in.a
AR drivers/gpu/drm/arm/built-in.a
AR drivers/gpu/drm/clients/built-in.a
CC drivers/gpu/drm/display/drm_display_helper_mod.o
CC kernel/time/jiffies.o
CC drivers/acpi/acpica/exoparg1.o
CC fs/ext4/extents_status.o
CC net/netlabel/netlabel_domainhash.o
CC drivers/pci/pci-sysfs.o
CC fs/netfs/read_retry.o
CC net/core/rtnetlink.o
CC net/netfilter/nf_conntrack_proto_udp.o
AR drivers/gpu/vga/built-in.a
AR fs/isofs/built-in.a
CC net/handshake/netlink.o
CC block/badblocks.o
CC block/blk-rq-qos.o
CC net/9p/error.o
CC drivers/tty/serial/8250/8250_core.o
CC arch/x86/kernel/cpu/feat_ctl.o
CC kernel/cgroup/namespace.o
CC kernel/cgroup/cgroup-v1.o
CC sound/pci/hda/hda_intel.o
CC drivers/gpu/drm/display/drm_dp_dual_mode_helper.o
CC net/netlabel/netlabel_addrlist.o
CC net/ipv4/tcp_input.o
CC kernel/time/timer_list.o
CC net/mac80211/status.o
CC net/netlabel/netlabel_mgmt.o
CC fs/proc/thread_self.o
CC drivers/acpi/acpica/exoparg2.o
CC lib/decompress_unlzo.o
CC net/9p/protocol.o
CC kernel/cgroup/freezer.o
CC net/ipv6/ipv6_sockglue.o
CC net/xfrm/xfrm_nat_keepalive.o
CC net/ethtool/cabletest.o
CC io_uring/statx.o
CC arch/x86/kernel/cpu/intel.o
CC net/netlabel/netlabel_unlabeled.o
COPY drivers/tty/vt/defkeymap.c
CC arch/x86/kernel/process_32.o
CC drivers/virtio/virtio_pci_legacy.o
CC drivers/char/agp/isoch.o
CC crypto/algboss.o
CC kernel/trace/trace_output.o
CC drivers/iommu/iommu-sysfs.o
CC drivers/acpi/acpica/exoparg3.o
CC drivers/iommu/dma-iommu.o
CC block/disk-events.o
CC kernel/bpf/core.o
CC fs/netfs/read_single.o
CC fs/proc/proc_sysctl.o
AR net/sunrpc/auth_gss/built-in.a
CC net/sunrpc/xprtsock.o
CC lib/decompress_unxz.o
CC fs/fat/misc.o
CC kernel/time/timeconv.o
CC drivers/gpu/drm/display/drm_dp_helper.o
CC drivers/tty/serial/8250/8250_platform.o
CC net/handshake/request.o
CC net/netfilter/nf_conntrack_proto_icmp.o
CC drivers/pci/slot.o
CC arch/x86/kernel/cpu/tsx.o
CC net/9p/trans_common.o
CC drivers/acpi/acpica/exoparg6.o
CC net/handshake/tlshd.o
CC net/ipv4/tcp_output.o
CC net/sysctl_net.o
CC io_uring/timeout.o
CC net/mac80211/driver-ops.o
CC drivers/virtio/virtio_pci_admin_legacy_io.o
CC drivers/acpi/osl.o
CC fs/nfs/getroot.o
CC net/ethtool/tunnels.o
CC fs/proc/proc_net.o
CC kernel/time/timecounter.o
CC kernel/cgroup/legacy_freezer.o
CC drivers/virtio/virtio_input.o
CC drivers/tty/vt/consolemap.o
CC drivers/char/agp/amd64-agp.o
CC kernel/time/alarmtimer.o
CC mm/highmem.o
CC kernel/trace/trace_seq.o
CC lib/decompress_unzstd.o
CC net/xfrm/xfrm_algo.o
CC io_uring/fdinfo.o
CC drivers/acpi/acpica/exprep.o
CC block/blk-ia-ranges.o
CC arch/x86/kernel/cpu/intel_epb.o
CC crypto/testmgr.o
AR sound/pci/hda/built-in.a
AR sound/pci/mixart/built-in.a
AR sound/pci/nm256/built-in.a
CC fs/netfs/rolling_buffer.o
CC net/9p/trans_fd.o
AR sound/pci/oxygen/built-in.a
AR sound/pci/pcxhr/built-in.a
AR sound/pci/riptide/built-in.a
AR sound/pci/rme9652/built-in.a
AR sound/pci/trident/built-in.a
AR sound/pci/ymfpci/built-in.a
CC drivers/tty/serial/8250/8250_pnp.o
AR sound/pci/vx222/built-in.a
AR sound/pci/built-in.a
CC fs/fat/nfs.o
AR sound/firewire/built-in.a
AR sound/sparc/built-in.a
AR sound/spi/built-in.a
CC fs/ext4/file.o
AR sound/parisc/built-in.a
CC net/netlabel/netlabel_cipso_v4.o
AR sound/pcmcia/vx/built-in.a
AR sound/pcmcia/pdaudiocf/built-in.a
CC drivers/acpi/acpica/exregion.o
CC net/9p/trans_virtio.o
AR sound/pcmcia/built-in.a
CC drivers/pci/pci-acpi.o
CC drivers/tty/serial/8250/8250_rsa.o
AR sound/mips/built-in.a
AR sound/soc/built-in.a
AR sound/atmel/built-in.a
CC sound/hda/hda_bus_type.o
CC sound/hda/hdac_bus.o
CC arch/x86/kernel/cpu/amd.o
CC kernel/cgroup/pids.o
CC lib/dump_stack.o
CC drivers/virtio/virtio_dma_buf.o
CC sound/hda/hdac_device.o
CC drivers/char/agp/intel-agp.o
CC drivers/char/agp/intel-gtt.o
CC crypto/cmac.o
CC drivers/iommu/iova.o
CC fs/netfs/write_collect.o
CC net/ipv6/ndisc.o
CC fs/ext4/fsmap.o
HOSTCC drivers/tty/vt/conmakehash
CC mm/memory.o
CC net/netfilter/nf_conntrack_extend.o
CC drivers/acpi/acpica/exresnte.o
CC block/early-lookup.o
AR drivers/tty/ipwireless/built-in.a
CC net/handshake/trace.o
CC kernel/cgroup/rdma.o
CC io_uring/cancel.o
CC sound/hda/hdac_sysfs.o
CC fs/nfs/inode.o
CC fs/proc/kcore.o
CC net/wireless/scan.o
CC net/ethtool/fec.o
CC drivers/tty/vt/defkeymap.o
CC crypto/hmac.o
CC fs/proc/vmcore.o
CC kernel/time/posix-timers.o
CC fs/fat/namei_vfat.o
CC net/core/utils.o
CC drivers/tty/serial/8250/8250_port.o
CC net/core/link_watch.o
CONMK drivers/tty/vt/consolemap_deftbl.c
CC net/core/filter.o
CC net/xfrm/xfrm_user.o
CC drivers/tty/vt/consolemap_deftbl.o
CC mm/mincore.o
AR drivers/tty/vt/built-in.a
CC lib/earlycpio.o
CC fs/ext4/fsync.o
CC drivers/acpi/acpica/exresolv.o
AR drivers/virtio/built-in.a
CC mm/mlock.o
CC lib/extable.o
CC mm/mmap.o
CC net/sunrpc/sched.o
CC drivers/gpu/drm/display/drm_dp_mst_topology.o
CC arch/x86/kernel/signal.o
CC kernel/trace/trace_stat.o
CC crypto/crypto_null.o
CC arch/x86/kernel/cpu/hygon.o
CC drivers/pci/iomap.o
CC arch/x86/kernel/cpu/centaur.o
CC block/bounce.o
AR drivers/iommu/built-in.a
CC kernel/cgroup/cpuset.o
CC arch/x86/kernel/cpu/transmeta.o
CC net/netlabel/netlabel_calipso.o
CC drivers/acpi/acpica/exresop.o
CC arch/x86/kernel/cpu/zhaoxin.o
CC arch/x86/kernel/signal_32.o
AR drivers/char/agp/built-in.a
CC drivers/char/random.o
CC lib/flex_proportions.o
AR net/9p/built-in.a
CC sound/hda/hdac_regmap.o
CC kernel/cgroup/misc.o
CC io_uring/waitid.o
CC fs/netfs/write_issue.o
AR sound/x86/built-in.a
CC net/ipv6/udp.o
CC net/netfilter/nf_conntrack_acct.o
CC drivers/pci/quirks.o
AR kernel/bpf/built-in.a
CC crypto/md5.o
CC net/ethtool/eeprom.o
CC drivers/tty/serial/8250/8250_dma.o
CC drivers/acpi/acpica/exserial.o
CC fs/proc/kmsg.o
CC drivers/tty/tty_io.o
CC net/mac80211/sta_info.o
CC net/core/sock_diag.o
CC lib/idr.o
CC fs/proc/page.o
CC drivers/gpu/drm/ttm/ttm_tt.o
CC arch/x86/kernel/cpu/vortex.o
CC drivers/connector/cn_queue.o
CC kernel/trace/trace_printk.o
CC drivers/base/power/sysfs.o
CC drivers/block/loop.o
CC kernel/time/posix-cpu-timers.o
AR net/handshake/built-in.a
CC drivers/base/firmware_loader/builtin/main.o
CC drivers/misc/eeprom/eeprom_93cx6.o
CC drivers/base/firmware_loader/main.o
CC drivers/block/virtio_blk.o
CC fs/fat/namei_msdos.o
CC drivers/acpi/acpica/exstore.o
AR drivers/mfd/built-in.a
CC kernel/time/posix-clock.o
AR drivers/misc/cb710/built-in.a
CC lib/iomem_copy.o
CC crypto/sha256_generic.o
CC fs/ext4/hash.o
CC drivers/base/regmap/regmap.o
CC sound/hda/hdac_controller.o
CC block/bsg.o
CC kernel/time/itimer.o
CC arch/x86/kernel/cpu/perfctr-watchdog.o
CC drivers/base/regmap/regcache.o
CC lib/irq_regs.o
AR drivers/base/firmware_loader/builtin/built-in.a
CC sound/hda/hdac_stream.o
CC io_uring/register.o
AR net/netlabel/built-in.a
CC net/ipv4/tcp_timer.o
AR drivers/misc/eeprom/built-in.a
AR drivers/misc/lis3lv02d/built-in.a
AR drivers/misc/cardreader/built-in.a
AR drivers/misc/keba/built-in.a
CC drivers/tty/n_tty.o
AR drivers/misc/built-in.a
CC drivers/acpi/acpica/exstoren.o
CC lib/is_single_threaded.o
CC drivers/base/power/generic_ops.o
AR fs/proc/built-in.a
CC mm/mmu_gather.o
CC fs/nfs/super.o
CC drivers/gpu/drm/ttm/ttm_bo.o
CC arch/x86/kernel/traps.o
CC net/netfilter/nf_conntrack_seqadj.o
CC mm/mprotect.o
CC drivers/tty/serial/8250/8250_dwlib.o
CC kernel/events/core.o
CC fs/netfs/write_retry.o
CC net/ethtool/stats.o
CC crypto/sha512_generic.o
CC kernel/trace/pid_list.o
CC drivers/char/misc.o
CC block/blk-cgroup.o
CC drivers/acpi/acpica/exstorob.o
CC fs/ext4/ialloc.o
CC lib/klist.o
CC arch/x86/kernel/cpu/vmware.o
CC drivers/connector/connector.o
CC net/mac80211/wep.o
CC fs/ext4/indirect.o
CC drivers/base/power/common.o
CC mm/mremap.o
AR fs/fat/built-in.a
CC net/netfilter/nf_conntrack_proto_icmpv6.o
AR drivers/base/firmware_loader/built-in.a
CC lib/kobject.o
CC drivers/acpi/acpica/exsystem.o
CC net/sunrpc/auth.o
CC arch/x86/kernel/idt.o
CC kernel/time/clockevents.o
CC arch/x86/kernel/cpu/hypervisor.o
CC net/wireless/nl80211.o
CC drivers/char/virtio_console.o
CC net/sunrpc/auth_null.o
CC kernel/cgroup/debug.o
CC sound/hda/array.o
CC drivers/tty/serial/serial_core.o
AR net/xfrm/built-in.a
CC io_uring/truncate.o
CC drivers/char/hpet.o
AR sound/xen/built-in.a
CC sound/hda/hdmi_chmap.o
CC drivers/acpi/acpica/extrace.o
AR drivers/block/built-in.a
CC drivers/pci/pci-label.o
CC net/ipv6/udplite.o
CC drivers/tty/serial/8250/8250_pcilib.o
CC crypto/sha3_generic.o
CC drivers/base/power/qos.o
CC drivers/gpu/drm/ttm/ttm_bo_util.o
CC net/sunrpc/auth_tls.o
CC lib/kobject_uevent.o
AR fs/netfs/built-in.a
CC kernel/trace/trace_sched_switch.o
AR drivers/base/test/built-in.a
CC kernel/time/tick-common.o
AR sound/virtio/built-in.a
CC fs/ext4/inline.o
CC arch/x86/kernel/cpu/mshyperv.o
CC net/ipv6/raw.o
CC drivers/acpi/acpica/exutils.o
CC fs/nfs/io.o
CC drivers/base/power/runtime.o
CC net/ipv4/tcp_ipv4.o
CC drivers/connector/cn_proc.o
CC drivers/base/regmap/regcache-rbtree.o
CC net/ipv4/tcp_minisocks.o
CC net/ipv4/tcp_cong.o
CC drivers/base/regmap/regcache-flat.o
CC net/ethtool/phc_vclocks.o
CC drivers/gpu/drm/display/drm_dsc_helper.o
CC crypto/ecb.o
CC kernel/fork.o
CC lib/logic_pio.o
CC mm/msync.o
AR kernel/cgroup/built-in.a
CC mm/page_vma_mapped.o
CC arch/x86/kernel/cpu/debugfs.o
CC kernel/time/tick-broadcast.o
CC drivers/tty/serial/8250/8250_early.o
CC io_uring/memmap.o
CC drivers/pci/vgaarb.o
CC drivers/acpi/acpica/hwacpi.o
CC sound/sound_core.o
CC block/blk-ioprio.o
CC drivers/char/nvram.o
CC net/netfilter/nf_conntrack_netlink.o
CC kernel/events/ring_buffer.o
CC sound/hda/trace.o
CC crypto/cbc.o
CC drivers/base/regmap/regcache-maple.o
CC drivers/tty/tty_ioctl.o
CC drivers/gpu/drm/ttm/ttm_bo_vm.o
CC drivers/acpi/acpica/hwesleep.o
CC kernel/time/tick-broadcast-hrtimer.o
CC net/core/dev_ioctl.o
CC drivers/tty/serial/serial_base_bus.o
CC drivers/gpu/drm/display/drm_hdcp_helper.o
CC drivers/tty/serial/8250/8250_exar.o
CC net/wireless/mlme.o
CC arch/x86/kernel/cpu/bus_lock.o
CC drivers/gpu/drm/i915/i915_config.o
CC drivers/gpu/drm/i915/i915_driver.o
CC net/netfilter/nf_conntrack_ftp.o
CC lib/maple_tree.o
CC kernel/trace/trace_nop.o
CC net/ethtool/mm.o
CC io_uring/alloc_cache.o
CC kernel/events/callchain.o
CC drivers/acpi/utils.o
CC mm/pagewalk.o
CC fs/nfs/direct.o
CC crypto/ctr.o
CC fs/ext4/inode.o
CC drivers/base/power/wakeirq.o
CC net/core/tso.o
CC sound/last.o
CC drivers/acpi/acpica/hwgpe.o
CC net/mac80211/aead_api.o
CC block/blk-iolatency.o
AR drivers/connector/built-in.a
CC mm/pgtable-generic.o
CC net/core/sock_reuseport.o
CC kernel/time/tick-oneshot.o
AR drivers/char/built-in.a
CC kernel/exec_domain.o
CC drivers/base/regmap/regmap-debugfs.o
AR drivers/gpu/drm/renesas/rcar-du/built-in.a
AR drivers/gpu/drm/renesas/rz-du/built-in.a
CC net/ipv4/tcp_metrics.o
AR drivers/gpu/drm/renesas/built-in.a
CC drivers/acpi/acpica/hwregs.o
CC fs/lockd/clntlock.o
CC sound/hda/hdac_component.o
CC fs/nfs/pagelist.o
AR drivers/pci/built-in.a
CC drivers/gpu/drm/ttm/ttm_module.o
CC drivers/tty/serial/serial_ctrl.o
CC net/wireless/ibss.o
CC crypto/gcm.o
CC drivers/gpu/drm/display/drm_hdmi_helper.o
CC kernel/panic.o
CC drivers/base/power/main.o
CC drivers/gpu/drm/i915/i915_drm_client.o
CC io_uring/io-wq.o
CC fs/lockd/clntproc.o
CC arch/x86/kernel/cpu/capflags.o
CC net/core/fib_notifier.o
CC kernel/time/tick-sched.o
CC lib/memcat_p.o
CC kernel/trace/blktrace.o
CC net/mac80211/wpa.o
CC kernel/trace/trace_events.o
CC net/ipv6/icmp.o
AR arch/x86/kernel/cpu/built-in.a
CC arch/x86/kernel/irq.o
CC kernel/cpu.o
CC drivers/base/component.o
CC drivers/tty/serial/8250/8250_lpss.o
CC net/sunrpc/auth_unix.o
CC drivers/acpi/acpica/hwsleep.o
CC mm/rmap.o
CC net/ethtool/module.o
CC drivers/tty/serial/8250/8250_mid.o
CC drivers/gpu/drm/ttm/ttm_execbuf_util.o
CC drivers/gpu/drm/ttm/ttm_range_manager.o
CC drivers/acpi/acpica/hwvalid.o
CC io_uring/futex.o
AR drivers/base/regmap/built-in.a
CC drivers/base/core.o
CC sound/hda/hdac_i915.o
CC drivers/base/bus.o
CC drivers/gpu/drm/display/drm_scdc_helper.o
CC crypto/ccm.o
CC drivers/gpu/drm/i915/i915_getparam.o
CC block/blk-iocost.o
CC net/wireless/sme.o
CC io_uring/napi.o
CC drivers/acpi/acpica/hwxface.o
CC fs/lockd/clntxdr.o
CC net/ethtool/cmis_fw_update.o
CC net/sunrpc/svc.o
CC kernel/time/timer_migration.o
AR drivers/nfc/built-in.a
CC drivers/tty/serial/serial_port.o
CC net/wireless/chan.o
CC net/netfilter/nf_conntrack_irc.o
CC net/wireless/ethtool.o
CC drivers/tty/tty_ldisc.o
CC drivers/gpu/drm/ttm/ttm_resource.o
CC net/netfilter/nf_conntrack_sip.o
CC sound/hda/intel-dsp-config.o
CC drivers/tty/serial/8250/8250_pci.o
CC mm/vmalloc.o
CC drivers/acpi/acpica/hwxfsleep.o
CC kernel/events/hw_breakpoint.o
CC drivers/tty/serial/earlycon.o
CC fs/nfs/read.o
CC net/core/xdp.o
AR drivers/gpu/drm/display/built-in.a
CC arch/x86/kernel/irq_32.o
CC net/ipv4/tcp_fastopen.o
CC drivers/base/power/wakeup.o
AR drivers/dax/hmem/built-in.a
AR drivers/dax/built-in.a
CC block/mq-deadline.o
CC fs/nfs/symlink.o
CC crypto/aes_generic.o
CC drivers/tty/tty_buffer.o
CC drivers/acpi/acpica/hwpci.o
CC sound/hda/intel-nhlt.o
CC kernel/time/vsyscall.o
CC net/mac80211/scan.o
CC sound/hda/intel-sdw-acpi.o
CC drivers/gpu/drm/i915/i915_ioctl.o
CC net/ipv6/mcast.o
CC fs/nfs/unlink.o
CC net/core/flow_offload.o
CC lib/nmi_backtrace.o
CC drivers/base/dd.o
CC net/ethtool/cmis_cdb.o
CC fs/lockd/host.o
CC drivers/base/syscore.o
CC fs/nls/nls_base.o
CC drivers/acpi/acpica/nsaccess.o
CC fs/lockd/svc.o
CC kernel/exit.o
CC drivers/gpu/drm/ttm/ttm_pool.o
CC arch/x86/kernel/dumpstack_32.o
CC drivers/tty/serial/8250/8250_pericom.o
CC drivers/gpu/drm/i915/i915_irq.o
CC net/sunrpc/svcsock.o
CC drivers/gpu/drm/ttm/ttm_device.o
AR drivers/gpu/drm/omapdrm/built-in.a
AR sound/hda/built-in.a
CC net/ipv4/tcp_rate.o
AR sound/built-in.a
CC lib/objpool.o
CC crypto/authenc.o
AR io_uring/built-in.a
CC net/mac80211/offchannel.o
CC net/ethtool/pse-pd.o
CC kernel/trace/trace_export.o
CC drivers/acpi/acpica/nsalloc.o
CC fs/lockd/svclock.o
CC fs/nls/nls_cp437.o
CC net/wireless/mesh.o
CC drivers/base/power/wakeup_stats.o
CC lib/plist.o
CC crypto/authencesn.o
CC mm/vma.o
CC kernel/time/timekeeping_debug.o
CC fs/nfs/write.o
CC arch/x86/kernel/time.o
CC arch/x86/kernel/ioport.o
AR drivers/gpu/drm/tilcdc/built-in.a
CC crypto/lzo.o
CC crypto/lzo-rle.o
AR drivers/tty/serial/8250/built-in.a
AR drivers/tty/serial/built-in.a
CC drivers/tty/tty_port.o
CC fs/nls/nls_ascii.o
CC kernel/softirq.o
CC net/ipv6/reassembly.o
CC drivers/acpi/acpica/nsarguments.o
CC kernel/time/namespace.o
CC net/sunrpc/svcauth.o
AR fs/unicode/built-in.a
CC crypto/rng.o
CC net/ethtool/plca.o
CC drivers/base/power/trace.o
CC kernel/trace/trace_event_perf.o
CC kernel/events/uprobes.o
CC net/netfilter/nf_nat_core.o
CC net/core/gro.o
CC drivers/tty/tty_mutex.o
CC drivers/dma-buf/dma-buf.o
CC drivers/acpi/reboot.o
CC fs/nls/nls_iso8859-1.o
CC mm/process_vm_access.o
CC drivers/gpu/drm/ttm/ttm_sys_manager.o
CC net/mac80211/ht.o
CC drivers/acpi/acpica/nsconvert.o
CC drivers/gpu/drm/i915/i915_mitigations.o
CC lib/radix-tree.o
CC arch/x86/kernel/dumpstack.o
CC net/sunrpc/svcauth_unix.o
CC block/kyber-iosched.o
CC net/mac80211/agg-tx.o
CC drivers/acpi/nvs.o
CC drivers/gpu/drm/i915/i915_module.o
CC net/ipv4/tcp_recovery.o
CC drivers/gpu/drm/virtio/virtgpu_drv.o
AR drivers/gpu/drm/imx/built-in.a
CC fs/ext4/ioctl.o
CC drivers/dma-buf/dma-fence.o
AR drivers/cxl/core/built-in.a
CC fs/nls/nls_utf8.o
AR drivers/cxl/built-in.a
CC net/netfilter/nf_nat_proto.o
CC mm/page_alloc.o
CC fs/autofs/init.o
CC fs/9p/vfs_super.o
CC drivers/acpi/acpica/nsdump.o
CC drivers/gpu/drm/ttm/ttm_backup.o
CC drivers/tty/tty_ldsem.o
AR kernel/time/built-in.a
CC net/ipv6/tcp_ipv6.o
CC crypto/drbg.o
AR drivers/base/power/built-in.a
CC fs/lockd/svcshare.o
CC drivers/base/driver.o
CC fs/autofs/inode.o
AR fs/hostfs/built-in.a
CC net/ipv6/ping.o
CC kernel/trace/trace_events_filter.o
AR drivers/gpu/drm/panel/built-in.a
CC drivers/acpi/wakeup.o
AR fs/nls/built-in.a
CC fs/ext4/mballoc.o
CC drivers/acpi/acpica/nseval.o
CC net/ipv4/tcp_ulp.o
CC net/ethtool/phy.o
CC drivers/gpu/drm/i915/i915_params.o
CC arch/x86/kernel/nmi.o
CC net/core/netdev-genl.o
CC net/wireless/ap.o
CC drivers/base/class.o
AR drivers/gpu/drm/bridge/analogix/built-in.a
CC net/sunrpc/addr.o
CC drivers/acpi/acpica/nsinit.o
AR drivers/gpu/drm/bridge/cadence/built-in.a
AR drivers/gpu/drm/bridge/imx/built-in.a
CC drivers/gpu/drm/virtio/virtgpu_kms.o
AR drivers/gpu/drm/bridge/synopsys/built-in.a
AR drivers/gpu/drm/hisilicon/built-in.a
AR drivers/gpu/drm/bridge/built-in.a
CC drivers/base/platform.o
CC drivers/macintosh/mac_hid.o
CC kernel/resource.o
CC fs/ext4/migrate.o
AR drivers/scsi/pcmcia/built-in.a
CC drivers/scsi/scsi.o
CC fs/9p/vfs_inode.o
CC drivers/tty/tty_baudrate.o
CC drivers/gpu/drm/ttm/ttm_agp_backend.o
CC lib/ratelimit.o
CC fs/debugfs/inode.o
CC lib/rbtree.o
CC fs/tracefs/inode.o
CC drivers/gpu/drm/virtio/virtgpu_gem.o
CC [M] fs/efivarfs/inode.o
CC fs/autofs/root.o
CC fs/open.o
CC drivers/acpi/sleep.o
CC drivers/acpi/acpica/nsload.o
CC crypto/jitterentropy.o
CC net/netfilter/nf_nat_helper.o
CC drivers/dma-buf/dma-fence-array.o
CC net/core/netdev-genl-gen.o
CC block/blk-mq-debugfs.o
CC drivers/gpu/drm/i915/i915_pci.o
CC drivers/scsi/hosts.o
CC crypto/jitterentropy-kcapi.o
CC lib/seq_buf.o
CC arch/x86/kernel/ldt.o
CC fs/lockd/svcproc.o
AR drivers/macintosh/built-in.a
CC lib/siphash.o
AR kernel/events/built-in.a
CC mm/page_frag_cache.o
CC drivers/tty/tty_jobctrl.o
AR drivers/gpu/drm/mxsfb/built-in.a
CC fs/debugfs/file.o
AR drivers/gpu/drm/ttm/built-in.a
CC drivers/acpi/acpica/nsnames.o
CC fs/read_write.o
CC net/ethtool/tsconfig.o
CC crypto/ghash-generic.o
CC arch/x86/kernel/setup.o
CC fs/nfs/namespace.o
CC net/netfilter/nf_nat_masquerade.o
CC fs/lockd/svcsubs.o
CC [M] fs/efivarfs/file.o
CC net/sunrpc/rpcb_clnt.o
CC fs/9p/vfs_inode_dotl.o
CC net/mac80211/agg-rx.o
CC net/ipv4/tcp_offload.o
CC drivers/dma-buf/dma-fence-chain.o
CC kernel/trace/trace_events_trigger.o
CC drivers/gpu/drm/virtio/virtgpu_vram.o
CC block/blk-pm.o
CC fs/tracefs/event_inode.o
CC drivers/base/cpu.o
CC drivers/acpi/acpica/nsobject.o
CC drivers/tty/n_null.o
CC crypto/hash_info.o
AR drivers/nvme/common/built-in.a
AR drivers/nvme/host/built-in.a
CC arch/x86/kernel/x86_init.o
CC net/ipv4/tcp_plb.o
CC kernel/trace/trace_eprobe.o
CC lib/string.o
AR drivers/nvme/target/built-in.a
CC crypto/rsapubkey.asn1.o
AR drivers/nvme/built-in.a
CC block/holder.o
CC fs/ext4/mmp.o
CC [M] fs/efivarfs/super.o
CC crypto/rsaprivkey.asn1.o
CC fs/file_table.o
CC fs/autofs/symlink.o
AR crypto/built-in.a
CC net/wireless/trace.o
CC fs/9p/vfs_addr.o
CC drivers/base/firmware.o
CC net/netfilter/nf_nat_ftp.o
CC fs/nfs/mount_clnt.o
CC drivers/scsi/scsi_ioctl.o
CC net/core/gso.o
CC net/ipv4/datagram.o
CC lib/timerqueue.o
CC drivers/gpu/drm/i915/i915_scatterlist.o
CC fs/lockd/mon.o
CC drivers/acpi/device_sysfs.o
CC drivers/dma-buf/dma-fence-unwrap.o
CC drivers/acpi/acpica/nsparse.o
CC drivers/tty/pty.o
CC lib/union_find.o
CC lib/vsprintf.o
CC net/ipv6/exthdrs.o
CC drivers/gpu/drm/virtio/virtgpu_display.o
CC fs/autofs/waitq.o
CC net/wireless/ocb.o
CC fs/lockd/trace.o
CC net/mac80211/vht.o
AR net/ethtool/built-in.a
CC drivers/gpu/drm/i915/i915_switcheroo.o
CC net/wireless/pmsr.o
AR fs/debugfs/built-in.a
CC drivers/scsi/scsicam.o
AR block/built-in.a
CC drivers/ata/libata-core.o
CC drivers/acpi/device_pm.o
AR drivers/gpu/drm/tiny/built-in.a
CC arch/x86/kernel/i8259.o
CC drivers/acpi/proc.o
CC drivers/acpi/acpica/nspredef.o
CC drivers/base/init.o
CC drivers/ata/libata-scsi.o
CC net/netfilter/nf_nat_irc.o
AR fs/tracefs/built-in.a
CC mm/init-mm.o
CC drivers/gpu/drm/virtio/virtgpu_vq.o
CC [M] fs/efivarfs/vars.o
CC drivers/dma-buf/dma-resv.o
GEN net/wireless/shipped-certs.c
CC arch/x86/kernel/irqinit.o
CC drivers/gpu/drm/virtio/virtgpu_fence.o
CC fs/9p/vfs_file.o
CC net/sunrpc/timer.o
CC net/ipv4/raw.o
CC drivers/ata/libata-eh.o
CC drivers/scsi/scsi_error.o
CC drivers/base/map.o
CC fs/ext4/move_extent.o
CC lib/win_minmax.o
CC drivers/acpi/acpica/nsprepkg.o
CC drivers/tty/tty_audit.o
CC fs/autofs/expire.o
CC kernel/sysctl.o
CC fs/lockd/xdr.o
CC fs/nfs/nfstrace.o
CC net/core/net-sysfs.o
CC kernel/trace/trace_kprobe.o
CC drivers/dma-buf/sync_file.o
CC net/netfilter/nf_nat_sip.o
AR drivers/net/phy/mediatek/built-in.a
CC fs/ext4/namei.o
AR drivers/net/phy/qcom/built-in.a
AR drivers/net/pse-pd/built-in.a
CC fs/9p/vfs_dir.o
CC drivers/net/phy/realtek/realtek_main.o
CC drivers/net/phy/realtek/realtek_hwmon.o
CC net/mac80211/he.o
CC drivers/net/phy/mdio-boardinfo.o
CC net/sunrpc/xdr.o
CC drivers/base/devres.o
CC mm/memblock.o
CC arch/x86/kernel/jump_label.o
CC net/wireless/shipped-certs.o
CC net/mac80211/s1g.o
LD [M] fs/efivarfs/efivarfs.o
CC fs/ext4/page-io.o
CC drivers/acpi/acpica/nsrepair.o
CC drivers/gpu/drm/i915/i915_sysfs.o
CC arch/x86/kernel/irq_work.o
CC drivers/net/mdio/acpi_mdio.o
CC net/ipv4/udp.o
CC kernel/capability.o
CC drivers/net/mdio/fwnode_mdio.o
CC drivers/net/phy/stubs.o
CC fs/autofs/dev-ioctl.o
CC drivers/tty/sysrq.o
AR drivers/net/pcs/built-in.a
CC drivers/base/attribute_container.o
CC mm/slub.o
AR drivers/dma-buf/built-in.a
CC drivers/scsi/scsi_lib.o
CC drivers/acpi/acpica/nsrepair2.o
CC kernel/trace/error_report-traces.o
CC fs/9p/vfs_dentry.o
CC drivers/gpu/drm/virtio/virtgpu_object.o
CC lib/xarray.o
CC drivers/acpi/bus.o
CC net/core/hotdata.o
CC net/ipv6/datagram.o
CC drivers/gpu/drm/i915/i915_utils.o
CC fs/lockd/clnt4xdr.o
CC drivers/base/transport_class.o
CC drivers/gpu/drm/i915/intel_clock_gating.o
CC net/sunrpc/sunrpc_syms.o
CC net/netfilter/x_tables.o
CC mm/madvise.o
CC drivers/acpi/acpica/nssearch.o
CC drivers/acpi/glue.o
AR drivers/net/phy/realtek/built-in.a
CC drivers/gpu/drm/virtio/virtgpu_debugfs.o
AR drivers/net/ethernet/3com/built-in.a
CC fs/9p/v9fs.o
CC drivers/net/ethernet/8390/ne2k-pci.o
AR drivers/gpu/drm/xlnx/built-in.a
CC drivers/acpi/acpica/nsutils.o
CC fs/nfs/export.o
CC arch/x86/kernel/probe_roms.o
AR drivers/net/mdio/built-in.a
CC drivers/net/phy/mdio_devres.o
CC drivers/base/topology.o
AR drivers/net/ethernet/adaptec/built-in.a
CC drivers/ata/libata-transport.o
AR fs/autofs/built-in.a
CC net/core/netdev_rx_queue.o
AR drivers/gpu/drm/gud/built-in.a
CC drivers/net/ethernet/8390/8390.o
AR drivers/gpu/drm/solomon/built-in.a
CC drivers/acpi/scan.o
AR drivers/net/wireless/admtek/built-in.a
AR drivers/net/wireless/ath/built-in.a
AR drivers/net/wireless/atmel/built-in.a
CC [M] drivers/gpu/drm/scheduler/sched_main.o
CC fs/nfs/sysfs.o
AR drivers/net/wireless/broadcom/built-in.a
AR drivers/tty/built-in.a
AR drivers/net/wireless/intel/built-in.a
AR drivers/net/wireless/intersil/built-in.a
CC fs/nfs/fs_context.o
HOSTCC drivers/gpu/drm/xe/xe_gen_wa_oob
CC mm/page_io.o
AR drivers/net/wireless/marvell/built-in.a
CC net/sunrpc/cache.o
AR drivers/net/wireless/mediatek/built-in.a
CC drivers/gpu/drm/i915/intel_cpu_info.o
AR drivers/net/wireless/microchip/built-in.a
AR drivers/net/wireless/purelifi/built-in.a
CC drivers/ata/libata-trace.o
AR drivers/net/wireless/quantenna/built-in.a
CC drivers/gpu/drm/i915/intel_device_info.o
AR drivers/net/wireless/ralink/built-in.a
AR drivers/net/wireless/realtek/built-in.a
GEN xe_wa_oob.c xe_wa_oob.h
AR drivers/net/wireless/rsi/built-in.a
CC [M] drivers/gpu/drm/xe/xe_bb.o
AR drivers/net/wireless/silabs/built-in.a
CC drivers/net/phy/phy.o
AR drivers/net/wireless/st/built-in.a
AR drivers/net/wireless/ti/built-in.a
AR drivers/net/wireless/zydas/built-in.a
AR drivers/net/wireless/virtual/built-in.a
AR drivers/net/wireless/built-in.a
CC fs/lockd/xdr4.o
CC drivers/acpi/acpica/nswalk.o
CC drivers/net/phy/phy-c45.o
CC drivers/acpi/mipi-disco-img.o
CC kernel/ptrace.o
CC fs/9p/fid.o
CC kernel/trace/power-traces.o
CC [M] drivers/gpu/drm/scheduler/sched_fence.o
CC drivers/gpu/drm/virtio/virtgpu_plane.o
CC fs/nfs/nfsroot.o
CC drivers/base/container.o
CC net/netfilter/xt_tcpudp.o
CC arch/x86/kernel/sys_ia32.o
CC kernel/user.o
CC drivers/net/phy/phy-core.o
CC lib/lockref.o
CC drivers/acpi/resource.o
CC [M] drivers/gpu/drm/xe/xe_bo.o
CC drivers/acpi/acpica/nsxfeval.o
CC net/mac80211/ibss.o
CC kernel/trace/rpm-traces.o
CC [M] drivers/gpu/drm/scheduler/sched_entity.o
CC kernel/trace/trace_dynevent.o
CC fs/super.o
CC lib/bcd.o
CC net/sunrpc/rpc_pipe.o
CC net/core/net-procfs.o
CC lib/sort.o
CC drivers/scsi/constants.o
CC net/ipv6/ip6_flowlabel.o
CC drivers/base/property.o
CC net/ipv4/udplite.o
CC lib/parser.o
AR drivers/net/ethernet/8390/built-in.a
AR drivers/net/ethernet/agere/built-in.a
AR drivers/net/ethernet/alacritech/built-in.a
AR drivers/net/ethernet/alteon/built-in.a
CC fs/ext4/readpage.o
AR drivers/net/ethernet/amazon/built-in.a
CC drivers/firewire/init_ohci1394_dma.o
AR drivers/net/ethernet/amd/built-in.a
AR drivers/net/ethernet/aquantia/built-in.a
CC fs/9p/xattr.o
CC drivers/cdrom/cdrom.o
CC fs/ext4/resize.o
AR drivers/net/ethernet/arc/built-in.a
CC drivers/acpi/acpica/nsxfname.o
AR drivers/net/ethernet/asix/built-in.a
AR drivers/net/ethernet/atheros/built-in.a
AR drivers/net/ethernet/cadence/built-in.a
CC drivers/net/ethernet/broadcom/bnx2.o
AR drivers/net/usb/built-in.a
CC drivers/net/mii.o
CC kernel/signal.o
AR drivers/net/ethernet/brocade/built-in.a
CC drivers/gpu/drm/virtio/virtgpu_ioctl.o
CC drivers/acpi/acpica/nsxfobj.o
CC drivers/gpu/drm/i915/intel_memory_region.o
CC lib/debug_locks.o
CC arch/x86/kernel/ksysfs.o
CC lib/random32.o
CC drivers/gpu/drm/virtio/virtgpu_prime.o
CC kernel/trace/trace_probe.o
CC [M] drivers/gpu/drm/xe/xe_bo_evict.o
CC fs/lockd/svc4proc.o
CC drivers/acpi/acpica/psargs.o
CC kernel/sys.o
CC drivers/net/phy/phy_device.o
LD [M] drivers/gpu/drm/scheduler/gpu-sched.o
CC net/mac80211/iface.o
CC arch/x86/kernel/bootflag.o
CC drivers/scsi/scsi_lib_dma.o
CC net/ipv4/udp_offload.o
CC kernel/trace/trace_uprobe.o
CC fs/char_dev.o
AR drivers/net/ethernet/cavium/common/built-in.a
AR drivers/net/ethernet/cavium/thunder/built-in.a
CC net/mac80211/link.o
AR drivers/net/ethernet/cavium/liquidio/built-in.a
CC mm/swap_state.o
CC lib/bust_spinlocks.o
CC net/ipv6/inet6_connection_sock.o
AR drivers/net/ethernet/cavium/octeon/built-in.a
AR drivers/net/ethernet/cavium/built-in.a
CC [M] drivers/gpu/drm/xe/xe_devcoredump.o
CC arch/x86/kernel/e820.o
AR drivers/firewire/built-in.a
CC fs/stat.o
AR fs/9p/built-in.a
CC drivers/scsi/scsi_scan.o
CC net/netfilter/xt_CONNSECMARK.o
CC drivers/ata/libata-sata.o
CC drivers/acpi/acpica/psloop.o
CC fs/nfs/sysctl.o
CC drivers/base/cacheinfo.o
CC net/core/netpoll.o
CC kernel/umh.o
AR drivers/auxdisplay/built-in.a
CC net/netfilter/xt_NFLOG.o
CC drivers/ata/libata-sff.o
AR drivers/net/ethernet/chelsio/built-in.a
CC drivers/pcmcia/cs.o
CC drivers/net/phy/linkmode.o
CC drivers/gpu/drm/virtio/virtgpu_trace_points.o
CC kernel/workqueue.o
CC drivers/acpi/acpi_processor.o
CC net/ipv4/arp.o
CC drivers/ata/libata-pmp.o
CC net/sunrpc/sysfs.o
CC lib/kasprintf.o
CC drivers/gpu/drm/i915/intel_pcode.o
CC drivers/gpu/drm/i915/intel_region_ttm.o
CC net/ipv4/icmp.o
CC net/ipv4/devinet.o
CC drivers/acpi/acpica/psobject.o
CC drivers/acpi/processor_core.o
CC fs/ext4/super.o
CC fs/exec.o
GEN drivers/scsi/scsi_devinfo_tbl.c
CC kernel/pid.o
CC drivers/net/loopback.o
CC lib/bitmap.o
CC fs/lockd/procfs.o
CC drivers/gpu/drm/drm_atomic.o
CC drivers/base/swnode.o
CC mm/swapfile.o
CC drivers/acpi/acpica/psopcode.o
CC mm/swap_slots.o
CC drivers/acpi/acpica/psopinfo.o
AR drivers/cdrom/built-in.a
CC [M] drivers/gpu/drm/xe/xe_device.o
CC drivers/acpi/processor_pdc.o
CC drivers/pcmcia/socket_sysfs.o
CC arch/x86/kernel/pci-dma.o
CC net/ipv6/udp_offload.o
CC drivers/acpi/ec.o
CC net/netfilter/xt_SECMARK.o
CC lib/scatterlist.o
CC net/ipv4/af_inet.o
CC fs/nfs/nfs3super.o
AR drivers/net/ethernet/cisco/built-in.a
CC net/netfilter/xt_TCPMSS.o
CC drivers/net/phy/phy_link_topology.o
CC drivers/net/phy/mdio_bus.o
CC drivers/gpu/drm/virtio/virtgpu_submit.o
CC net/netfilter/xt_conntrack.o
CC drivers/scsi/scsi_devinfo.o
CC drivers/base/faux.o
CC [M] drivers/gpu/drm/xe/xe_device_sysfs.o
CC net/netfilter/xt_policy.o
CC drivers/acpi/acpica/psparse.o
CC net/netfilter/xt_state.o
CC drivers/gpu/drm/drm_atomic_uapi.o
CC net/ipv4/igmp.o
AR fs/lockd/built-in.a
CC drivers/gpu/drm/i915/intel_runtime_pm.o
CC arch/x86/kernel/quirks.o
CC [M] drivers/gpu/drm/xe/xe_dma_buf.o
CC drivers/pcmcia/cardbus.o
CC net/sunrpc/svc_xprt.o
CC net/ipv6/seg6.o
CC kernel/trace/rethook.o
CC drivers/acpi/acpica/psscope.o
CC net/ipv6/fib6_notifier.o
CC net/core/fib_rules.o
CC drivers/gpu/drm/i915/intel_sbi.o
CC net/ipv4/fib_frontend.o
CC drivers/gpu/drm/drm_auth.o
CC drivers/base/auxiliary.o
CC drivers/usb/common/common.o
CC net/core/net-traces.o
CC mm/dmapool.o
CC drivers/scsi/scsi_sysctl.o
CC net/ipv6/rpl.o
AR drivers/gpu/drm/virtio/built-in.a
AR drivers/net/ethernet/cortina/built-in.a
CC drivers/ata/libata-acpi.o
CC drivers/pcmcia/ds.o
CC drivers/net/phy/mdio_device.o
CC drivers/acpi/acpica/pstree.o
CC drivers/net/ethernet/broadcom/tg3.o
CC [M] drivers/gpu/drm/xe/xe_drm_client.o
CC fs/nfs/nfs3client.o
CC drivers/usb/core/usb.o
CC drivers/net/netconsole.o
CC drivers/usb/core/hub.o
CC arch/x86/kernel/kdebugfs.o
CC drivers/net/phy/swphy.o
CC net/mac80211/rate.o
CC lib/list_sort.o
CC drivers/base/devtmpfs.o
CC drivers/base/module.o
AR kernel/trace/built-in.a
CC drivers/base/auxiliary_sysfs.o
CC drivers/input/serio/serio.o
CC lib/uuid.o
CC drivers/input/keyboard/atkbd.o
CC net/core/selftests.o
CC drivers/acpi/acpica/psutils.o
CC drivers/input/mouse/psmouse-base.o
CC lib/iov_iter.o
AR drivers/input/joystick/built-in.a
CC net/sunrpc/xprtmultipath.o
CC drivers/gpu/drm/drm_blend.o
AR drivers/input/tablet/built-in.a
CC drivers/pcmcia/pcmcia_resource.o
CC [M] net/netfilter/nf_log_syslog.o
CC [M] drivers/gpu/drm/xe/xe_eu_stall.o
CC drivers/usb/common/debug.o
CC drivers/scsi/scsi_proc.o
CC lib/clz_ctz.o
CC lib/bsearch.o
CC drivers/rtc/lib.o
CC drivers/acpi/acpica/pswalk.o
CC drivers/rtc/class.o
CC drivers/input/serio/i8042.o
AR drivers/usb/common/built-in.a
CC drivers/input/mouse/synaptics.o
CC drivers/gpu/drm/i915/intel_step.o
CC fs/nfs/nfs3proc.o
CC [M] net/netfilter/xt_mark.o
CC drivers/i2c/algos/i2c-algo-bit.o
AR drivers/net/ethernet/dec/tulip/built-in.a
AR drivers/net/ethernet/dec/built-in.a
CC kernel/task_work.o
CC arch/x86/kernel/alternative.o
CC drivers/gpu/drm/i915/intel_uncore.o
CC net/ipv6/ioam6.o
CC drivers/acpi/acpica/psxface.o
CC drivers/gpu/drm/drm_bridge.o
CC drivers/net/phy/fixed_phy.o
CC net/ipv4/fib_semantics.o
CC drivers/ata/libata-pata-timings.o
CC [M] net/netfilter/xt_nat.o
CC drivers/rtc/interface.o
CC mm/hugetlb.o
CC drivers/input/mouse/focaltech.o
CC net/ipv4/fib_trie.o
CC drivers/acpi/acpica/rsaddr.o
CC drivers/base/devcoredump.o
AR drivers/i3c/built-in.a
CC drivers/net/virtio_net.o
AR drivers/media/i2c/built-in.a
AR drivers/media/tuners/built-in.a
CC drivers/ata/ahci.o
AR drivers/media/rc/keymaps/built-in.a
AR drivers/media/rc/built-in.a
AR drivers/media/common/b2c2/built-in.a
CC lib/find_bit.o
CC drivers/base/platform-msi.o
AR drivers/media/common/saa7146/built-in.a
AR drivers/media/platform/allegro-dvt/built-in.a
AR drivers/media/common/siano/built-in.a
AR drivers/media/platform/amlogic/meson-ge2d/built-in.a
AR drivers/media/common/v4l2-tpg/built-in.a
AR drivers/media/platform/amlogic/built-in.a
CC drivers/scsi/scsi_debugfs.o
AR drivers/media/common/videobuf2/built-in.a
AR drivers/media/platform/amphion/built-in.a
AR drivers/media/common/built-in.a
AR drivers/media/platform/aspeed/built-in.a
CC drivers/base/physical_location.o
CC fs/ext4/symlink.o
AR drivers/media/platform/atmel/built-in.a
AR drivers/media/platform/broadcom/built-in.a
AR drivers/media/platform/cadence/built-in.a
AR drivers/media/platform/chips-media/coda/built-in.a
AR drivers/media/platform/chips-media/wave5/built-in.a
AR drivers/media/platform/chips-media/built-in.a
AR drivers/input/keyboard/built-in.a
CC drivers/input/serio/serport.o
CC drivers/gpu/drm/drm_cache.o
AR drivers/media/platform/imagination/built-in.a
AR drivers/media/platform/intel/built-in.a
AR drivers/media/platform/marvell/built-in.a
AR drivers/media/platform/microchip/built-in.a
AR drivers/media/platform/mediatek/jpeg/built-in.a
CC kernel/extable.o
AR drivers/media/platform/mediatek/mdp/built-in.a
AR drivers/media/platform/mediatek/vcodec/common/built-in.a
CC drivers/acpi/acpica/rscalc.o
CC drivers/gpu/drm/drm_color_mgmt.o
AR drivers/media/platform/mediatek/vcodec/encoder/built-in.a
AR drivers/media/platform/mediatek/vcodec/decoder/built-in.a
AR drivers/media/platform/mediatek/vcodec/built-in.a
AR drivers/input/touchscreen/built-in.a
AR drivers/media/platform/mediatek/vpu/built-in.a
CC kernel/params.o
AR drivers/media/platform/mediatek/mdp3/built-in.a
AR drivers/media/platform/mediatek/built-in.a
CC drivers/net/net_failover.o
CC drivers/pcmcia/cistpl.o
AR drivers/media/platform/nuvoton/built-in.a
AR drivers/i2c/algos/built-in.a
CC [M] net/netfilter/xt_LOG.o
AR drivers/media/platform/nvidia/tegra-vde/built-in.a
AR drivers/media/platform/nxp/dw100/built-in.a
CC drivers/i2c/busses/i2c-i801.o
AR drivers/media/platform/nvidia/built-in.a
AR drivers/media/platform/nxp/imx-jpeg/built-in.a
CC fs/ext4/sysfs.o
CC drivers/acpi/dock.o
CC drivers/acpi/pci_root.o
AR drivers/media/platform/nxp/imx8-isi/built-in.a
AR drivers/media/platform/nxp/built-in.a
AR drivers/media/platform/qcom/camss/built-in.a
AR drivers/media/platform/qcom/venus/built-in.a
AR drivers/media/platform/qcom/built-in.a
CC drivers/acpi/pci_link.o
AR drivers/media/platform/raspberrypi/pisp_be/built-in.a
CC fs/ext4/xattr.o
AR drivers/media/platform/raspberrypi/rp1-cfe/built-in.a
AR drivers/media/platform/raspberrypi/built-in.a
CC lib/llist.o
AR drivers/media/platform/renesas/rcar-vin/built-in.a
AR drivers/media/platform/renesas/rzg2l-cru/built-in.a
CC [M] net/netfilter/xt_MASQUERADE.o
AR drivers/media/platform/renesas/vsp1/built-in.a
AR drivers/media/platform/renesas/built-in.a
CC drivers/input/serio/libps2.o
CC drivers/base/trace.o
AR drivers/media/platform/rockchip/rga/built-in.a
AR drivers/media/platform/samsung/exynos-gsc/built-in.a
AR drivers/media/platform/rockchip/rkisp1/built-in.a
AR drivers/media/platform/samsung/exynos4-is/built-in.a
CC net/sunrpc/stats.o
AR drivers/media/platform/rockchip/built-in.a
AR drivers/media/platform/samsung/s3c-camif/built-in.a
CC arch/x86/kernel/i8253.o
AR drivers/net/ethernet/dlink/built-in.a
CC fs/ext4/xattr_hurd.o
CC net/sunrpc/sysctl.o
AR drivers/media/platform/samsung/s5p-g2d/built-in.a
CC drivers/input/mouse/alps.o
AR drivers/media/platform/samsung/s5p-jpeg/built-in.a
AR drivers/media/platform/samsung/s5p-mfc/built-in.a
AR drivers/media/platform/samsung/built-in.a
CC net/core/ptp_classifier.o
CC drivers/acpi/acpica/rscreate.o
CC [M] drivers/gpu/drm/xe/xe_exec.o
AR drivers/media/platform/st/sti/bdisp/built-in.a
CC drivers/scsi/scsi_trace.o
AR drivers/media/platform/st/sti/c8sectpfe/built-in.a
AR drivers/net/phy/built-in.a
AR drivers/media/platform/st/sti/delta/built-in.a
CC drivers/ata/libahci.o
AR drivers/media/platform/st/sti/hva/built-in.a
AR drivers/media/platform/st/stm32/built-in.a
CC fs/nfs/nfs3xdr.o
AR drivers/media/platform/st/built-in.a
AR drivers/media/platform/sunxi/sun4i-csi/built-in.a
AR drivers/media/pci/ttpci/built-in.a
AR drivers/media/pci/b2c2/built-in.a
CC drivers/usb/core/hcd.o
AR drivers/media/platform/sunxi/sun6i-csi/built-in.a
AR drivers/media/platform/sunxi/sun6i-mipi-csi2/built-in.a
AR drivers/media/pci/pluto2/built-in.a
CC drivers/acpi/acpica/rsdumpinfo.o
AR drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/built-in.a
CC fs/pipe.o
AR drivers/media/pci/dm1105/built-in.a
CC fs/namei.o
AR drivers/media/platform/sunxi/sun8i-di/built-in.a
AR drivers/media/pci/pt1/built-in.a
AR drivers/media/platform/sunxi/sun8i-rotate/built-in.a
AR drivers/media/pci/pt3/built-in.a
AR drivers/media/platform/sunxi/built-in.a
AR drivers/media/pci/mantis/built-in.a
AR drivers/media/pci/ngene/built-in.a
AR drivers/media/platform/ti/am437x/built-in.a
AR drivers/media/platform/verisilicon/built-in.a
AR drivers/media/pci/ddbridge/built-in.a
CC drivers/ata/ata_piix.o
AR drivers/media/platform/ti/cal/built-in.a
AR drivers/media/pci/saa7146/built-in.a
AR drivers/media/platform/ti/vpe/built-in.a
AR drivers/media/pci/smipcie/built-in.a
AR drivers/media/platform/ti/davinci/built-in.a
AR drivers/media/pci/netup_unidvb/built-in.a
AR drivers/media/platform/ti/j721e-csi2rx/built-in.a
AR drivers/media/pci/intel/ipu3/built-in.a
AR drivers/media/platform/ti/omap/built-in.a
AR drivers/media/pci/intel/ivsc/built-in.a
AR drivers/media/platform/ti/omap3isp/built-in.a
AR drivers/media/pci/intel/built-in.a
AR drivers/media/platform/ti/built-in.a
AR drivers/media/pci/built-in.a
CC [M] drivers/gpu/drm/xe/xe_exec_queue.o
AR drivers/media/platform/via/built-in.a
CC drivers/ata/pata_amd.o
AR drivers/media/platform/xilinx/built-in.a
AR drivers/media/platform/built-in.a
AR drivers/pps/clients/built-in.a
CC drivers/pps/pps.o
CC drivers/pps/kapi.o
AR drivers/media/usb/b2c2/built-in.a
CC arch/x86/kernel/hw_breakpoint.o
AR drivers/media/usb/dvb-usb/built-in.a
CC drivers/ptp/ptp_clock.o
AR drivers/media/usb/dvb-usb-v2/built-in.a
AR drivers/media/usb/s2255/built-in.a
AR drivers/media/usb/siano/built-in.a
AR drivers/media/usb/ttusb-budget/built-in.a
CC drivers/acpi/acpica/rsinfo.o
AR drivers/media/usb/ttusb-dec/built-in.a
AR drivers/media/usb/built-in.a
CC drivers/rtc/nvmem.o
CC net/mac80211/michael.o
AR drivers/media/mmc/siano/built-in.a
AR drivers/media/mmc/built-in.a
CC drivers/pps/sysfs.o
AR drivers/media/firewire/built-in.a
CC net/ipv6/sysctl_net_ipv6.o
CC fs/nfs/nfs3acl.o
AR drivers/media/spi/built-in.a
AR drivers/input/serio/built-in.a
AR drivers/media/test-drivers/built-in.a
AR drivers/media/built-in.a
CC drivers/gpu/drm/i915/intel_uncore_trace.o
CC [M] drivers/gpu/drm/xe/xe_execlist.o
AR drivers/net/ethernet/emulex/built-in.a
AR drivers/i2c/muxes/built-in.a
CC kernel/kthread.o
CC drivers/gpu/drm/drm_connector.o
CC drivers/rtc/dev.o
CC lib/lwq.o
CC fs/nfs/nfs4proc.o
AR drivers/base/built-in.a
CC net/ipv6/xfrm6_policy.o
CC drivers/scsi/scsi_logging.o
CC drivers/acpi/acpica/rsio.o
CC drivers/gpu/drm/i915/intel_wakeref.o
CC mm/mmu_notifier.o
CC lib/memweight.o
AR drivers/i2c/busses/built-in.a
CC drivers/i2c/i2c-boardinfo.o
CC [M] net/netfilter/xt_addrtype.o
CC mm/migrate.o
CC lib/kfifo.o
CC net/ipv6/xfrm6_state.o
CC drivers/rtc/proc.o
CC fs/nfs/nfs4xdr.o
CC drivers/pcmcia/pcmcia_cis.o
CC drivers/ata/pata_oldpiix.o
AR drivers/pps/built-in.a
CC drivers/acpi/acpica/rsirq.o
CC drivers/ptp/ptp_chardev.o
CC drivers/i2c/i2c-core-base.o
CC fs/fcntl.o
AR drivers/usb/phy/built-in.a
AR drivers/net/ethernet/engleder/built-in.a
CC kernel/sys_ni.o
CC drivers/gpu/drm/drm_crtc.o
CC lib/percpu-refcount.o
CC arch/x86/kernel/tsc.o
CC net/mac80211/tkip.o
CC drivers/acpi/pci_irq.o
CC drivers/acpi/acpica/rslist.o
CC drivers/input/mouse/byd.o
CC fs/ext4/xattr_trusted.o
CC net/ipv6/xfrm6_input.o
CC net/ipv4/fib_notifier.o
AR drivers/net/ethernet/ezchip/built-in.a
CC drivers/gpu/drm/i915/vlv_sideband.o
CC drivers/scsi/scsi_pm.o
CC drivers/rtc/sysfs.o
AR drivers/net/ethernet/fujitsu/built-in.a
CC kernel/nsproxy.o
CC fs/nfs/nfs4state.o
CC drivers/usb/core/urb.o
AR drivers/input/misc/built-in.a
CC drivers/ptp/ptp_sysfs.o
CC drivers/gpu/drm/i915/vlv_suspend.o
CC drivers/input/mouse/logips2pp.o
AR net/sunrpc/built-in.a
CC drivers/i2c/i2c-core-smbus.o
CC net/core/netprio_cgroup.o
CC drivers/pcmcia/rsrc_mgr.o
CC kernel/notifier.o
CC drivers/acpi/acpica/rsmemory.o
CC drivers/power/supply/power_supply_core.o
CC drivers/ata/pata_sch.o
CC [M] drivers/gpu/drm/xe/xe_force_wake.o
CC drivers/usb/core/message.o
AR drivers/net/ethernet/fungible/built-in.a
CC drivers/input/input.o
CC net/ipv4/inet_fragment.o
CC lib/rhashtable.o
CC drivers/power/supply/power_supply_sysfs.o
CC mm/page_counter.o
CC net/ipv6/xfrm6_output.o
CC kernel/ksysfs.o
CC net/ipv4/ping.o
CC drivers/rtc/rtc-mc146818-lib.o
CC drivers/power/supply/power_supply_leds.o
AR net/wireless/built-in.a
CC drivers/input/input-compat.o
CC lib/base64.o
CC drivers/i2c/i2c-core-acpi.o
CC drivers/acpi/acpica/rsmisc.o
CC arch/x86/kernel/tsc_msr.o
CC drivers/ptp/ptp_vclock.o
AR drivers/net/ethernet/google/built-in.a
CC fs/nfs/nfs4renewd.o
AR net/netfilter/built-in.a
CC drivers/usb/mon/mon_main.o
CC drivers/acpi/acpi_apd.o
CC drivers/input/input-mt.o
CC [M] drivers/gpu/drm/xe/xe_ggtt.o
CC drivers/scsi/scsi_bsg.o
CC drivers/input/mouse/lifebook.o
CC fs/nfs/nfs4super.o
CC drivers/pcmcia/rsrc_nonstatic.o
CC drivers/ptp/ptp_kvm_x86.o
CC mm/hugetlb_cgroup.o
CC drivers/gpu/drm/i915/soc/intel_dram.o
CC drivers/acpi/acpi_platform.o
CC drivers/hwmon/hwmon.o
CC drivers/scsi/scsi_common.o
CC fs/ext4/xattr_user.o
CC drivers/ata/pata_mpiix.o
AR drivers/thermal/broadcom/built-in.a
CC net/ipv4/ip_tunnel_core.o
CC arch/x86/kernel/io_delay.o
AR drivers/thermal/renesas/built-in.a
AR drivers/thermal/samsung/built-in.a
CC drivers/thermal/intel/intel_tcc.o
CC drivers/acpi/acpica/rsserial.o
CC drivers/acpi/acpi_pnp.o
CC drivers/i2c/i2c-smbus.o
CC net/core/netclassid_cgroup.o
CC kernel/cred.o
CC drivers/rtc/rtc-cmos.o
CC drivers/power/supply/power_supply_hwmon.o
AR drivers/thermal/st/built-in.a
CC drivers/thermal/intel/therm_throt.o
CC mm/early_ioremap.o
CC drivers/input/mouse/trackpoint.o
CC drivers/usb/mon/mon_stat.o
CC fs/nfs/nfs4file.o
CC drivers/ptp/ptp_kvm_common.o
CC lib/once.o
CC arch/x86/kernel/rtc.o
CC drivers/acpi/power.o
AR drivers/watchdog/built-in.a
CC drivers/acpi/acpica/rsutils.o
CC net/ipv4/gre_offload.o
CC net/ipv4/metrics.o
CC drivers/scsi/scsi_transport_spi.o
CC net/ipv6/xfrm6_protocol.o
CC drivers/usb/core/driver.o
CC kernel/reboot.o
CC mm/secretmem.o
CC drivers/gpu/drm/drm_displayid.o
AR drivers/power/supply/built-in.a
AR drivers/thermal/qcom/built-in.a
AR drivers/power/built-in.a
CC drivers/usb/mon/mon_text.o
CC fs/ext4/fast_commit.o
CC net/mac80211/aes_cmac.o
CC drivers/usb/host/pci-quirks.o
CC drivers/input/input-poller.o
CC arch/x86/kernel/resource.o
CC mm/hmm.o
CC lib/refcount.o
CC drivers/pcmcia/yenta_socket.o
CC net/mac80211/aes_gmac.o
CC drivers/ata/ata_generic.o
CC [M] drivers/gpu/drm/xe/xe_gpu_scheduler.o
CC drivers/usb/class/usblp.o
CC [M] drivers/thermal/intel/x86_pkg_temp_thermal.o
CC drivers/acpi/acpica/rsxface.o
CC net/core/dst_cache.o
CC drivers/gpu/drm/drm_drv.o
AR drivers/i2c/built-in.a
AR drivers/thermal/tegra/built-in.a
CC drivers/input/mouse/cypress_ps2.o
CC drivers/input/ff-core.o
CC fs/nfs/delegation.o
CC drivers/usb/storage/scsiglue.o
CC net/core/gro_cells.o
CC fs/nfs/nfs4idmap.o
CC lib/rcuref.o
AR drivers/net/ethernet/hisilicon/built-in.a
AS arch/x86/kernel/irqflags.o
CC drivers/md/md.o
CC arch/x86/kernel/static_call.o
AR drivers/thermal/mediatek/built-in.a
CC drivers/usb/host/ehci-hcd.o
AR drivers/ptp/built-in.a
CC fs/ioctl.o
CC drivers/usb/core/config.o
CC net/mac80211/fils_aead.o
CC drivers/acpi/event.o
CC drivers/gpu/drm/i915/soc/intel_gmch.o
CC drivers/gpu/drm/i915/soc/intel_pch.o
AR drivers/rtc/built-in.a
CC lib/usercopy.o
CC lib/errseq.o
CC [M] drivers/gpu/drm/xe/xe_gsc.o
CC drivers/scsi/virtio_scsi.o
AR drivers/hwmon/built-in.a
AR drivers/net/ethernet/huawei/built-in.a
CC fs/ext4/orphan.o
CC fs/nfs/callback.o
CC kernel/async.o
CC drivers/acpi/acpica/tbdata.o
CC mm/memfd.o
CC arch/x86/kernel/process.o
CC fs/readdir.o
CC lib/bucket_locks.o
CC drivers/usb/host/ehci-pci.o
CC drivers/usb/mon/mon_bin.o
CC [M] drivers/gpu/drm/xe/xe_gsc_debugfs.o
AR drivers/thermal/intel/built-in.a
CC drivers/thermal/thermal_core.o
AR drivers/ata/built-in.a
CC drivers/input/touchscreen.o
CC fs/nfs/callback_xdr.o
CC drivers/input/mouse/psmouse-smbus.o
CC net/ipv6/netfilter.o
CC net/mac80211/cfg.o
CC drivers/net/ethernet/intel/e1000/e1000_main.o
CC net/ipv4/netlink.o
CC net/mac80211/ethtool.o
CC drivers/net/ethernet/intel/e1000e/82571.o
CC drivers/input/ff-memless.o
AR drivers/usb/class/built-in.a
CC fs/ext4/acl.o
CC drivers/net/ethernet/intel/e100.o
CC drivers/usb/storage/protocol.o
CC kernel/range.o
CC drivers/gpu/drm/i915/soc/intel_rom.o
CC net/ipv6/proc.o
CC [M] drivers/gpu/drm/xe/xe_gsc_proxy.o
CC drivers/acpi/acpica/tbfadt.o
CC drivers/acpi/evged.o
CC kernel/smpboot.o
CC drivers/net/ethernet/intel/e1000/e1000_hw.o
AR drivers/usb/misc/built-in.a
CC drivers/thermal/thermal_sysfs.o
CC drivers/usb/early/ehci-dbgp.o
CC net/core/failover.o
CC lib/generic-radix-tree.o
CC lib/bitmap-str.o
CC fs/ext4/xattr_security.o
AR drivers/pcmcia/built-in.a
CC drivers/input/sparse-keymap.o
CC drivers/usb/core/file.o
CC drivers/cpufreq/cpufreq.o
CC drivers/usb/storage/transport.o
CC drivers/usb/core/buffer.o
CC mm/ptdump.o
CC lib/string_helpers.o
CC [M] drivers/gpu/drm/xe/xe_gsc_submit.o
CC drivers/scsi/sd.o
CC drivers/thermal/thermal_trip.o
CC drivers/cpufreq/freq_table.o
CC drivers/acpi/acpica/tbfind.o
CC drivers/net/ethernet/intel/e1000e/ich8lan.o
AR drivers/input/mouse/built-in.a
AR drivers/net/ethernet/i825xx/built-in.a
CC lib/hexdump.o
CC net/mac80211/rx.o
CC drivers/usb/core/sysfs.o
CC drivers/thermal/thermal_helpers.o
CC arch/x86/kernel/ptrace.o
CC fs/select.o
CC drivers/net/ethernet/intel/e1000/e1000_ethtool.o
CC kernel/ucount.o
CC drivers/gpu/drm/i915/i915_memcpy.o
AR drivers/usb/mon/built-in.a
CC drivers/net/ethernet/intel/e1000e/80003es2lan.o
CC drivers/input/vivaldi-fmap.o
CC drivers/net/ethernet/intel/e1000/e1000_param.o
CC net/ipv4/nexthop.o
CC fs/dcache.o
CC mm/execmem.o
AR drivers/net/ethernet/microsoft/built-in.a
CC kernel/regset.o
CC drivers/acpi/acpica/tbinstal.o
CC drivers/gpu/drm/drm_dumb_buffers.o
CC drivers/usb/storage/usb.o
CC drivers/gpu/drm/i915/i915_mm.o
CC drivers/cpufreq/cpufreq_performance.o
CC net/mac80211/spectmgmt.o
CC net/ipv6/syncookies.o
CC drivers/md/md-bitmap.o
CC fs/inode.o
AR fs/ext4/built-in.a
CC drivers/thermal/thermal_thresholds.o
CC net/ipv4/udp_tunnel_stub.o
CC drivers/usb/core/endpoint.o
CC drivers/acpi/acpica/tbprint.o
CC drivers/input/input-leds.o
AR drivers/usb/early/built-in.a
CC drivers/gpu/drm/i915/i915_sw_fence.o
AR drivers/net/ethernet/litex/built-in.a
CC drivers/cpuidle/governors/menu.o
CC drivers/cpuidle/cpuidle.o
AR net/core/built-in.a
CC drivers/cpufreq/cpufreq_userspace.o
CC fs/attr.o
CC drivers/cpuidle/governors/haltpoll.o
CC fs/nfs/callback_proc.o
CC drivers/cpufreq/cpufreq_ondemand.o
AR drivers/net/ethernet/marvell/octeon_ep/built-in.a
CC kernel/ksyms_common.o
AR drivers/net/ethernet/marvell/octeon_ep_vf/built-in.a
AR drivers/net/ethernet/marvell/octeontx2/built-in.a
CC kernel/groups.o
AR drivers/net/ethernet/marvell/prestera/built-in.a
CC drivers/net/ethernet/marvell/sky2.o
CC [M] drivers/gpu/drm/xe/xe_gt.o
CC lib/kstrtox.o
CC kernel/kcmp.o
CC drivers/acpi/sysfs.o
CC drivers/acpi/acpica/tbutils.o
CC drivers/thermal/thermal_netlink.o
CC kernel/freezer.o
AR mm/built-in.a
CC drivers/md/md-autodetect.o
CC arch/x86/kernel/tls.o
CC drivers/input/evdev.o
CC drivers/gpu/drm/i915/i915_sw_fence_work.o
CC [M] drivers/gpu/drm/xe/xe_gt_ccs_mode.o
CC drivers/usb/core/devio.o
CC lib/iomap.o
CC net/ipv4/ip_tunnel.o
CC drivers/net/ethernet/intel/e1000e/mac.o
CC drivers/cpuidle/driver.o
CC net/ipv6/calipso.o
CC drivers/acpi/acpica/tbxface.o
CC fs/bad_inode.o
CC drivers/usb/storage/initializers.o
CC drivers/acpi/property.o
CC kernel/profile.o
CC drivers/gpu/drm/i915/i915_syncmap.o
CC [M] drivers/gpu/drm/xe/xe_gt_clock.o
CC fs/nfs/nfs4namespace.o
AR drivers/mmc/built-in.a
CC net/ipv4/sysctl_net_ipv4.o
AR drivers/cpuidle/governors/built-in.a
CC drivers/gpu/drm/drm_edid.o
CC drivers/usb/storage/sierra_ms.o
CC net/mac80211/tx.o
CC drivers/md/dm.o
CC drivers/usb/host/ohci-hcd.o
CC drivers/usb/core/notify.o
CC drivers/cpufreq/cpufreq_governor.o
CC arch/x86/kernel/step.o
CC drivers/net/ethernet/intel/e1000e/manage.o
CC [M] drivers/gpu/drm/xe/xe_gt_freq.o
CC drivers/md/dm-table.o
CC drivers/acpi/acpica/tbxfload.o
CC drivers/cpuidle/governor.o
CC drivers/md/dm-target.o
CC fs/nfs/nfs4getroot.o
CC fs/file.o
CC drivers/acpi/acpica/tbxfroot.o
AR drivers/net/ethernet/mellanox/built-in.a
CC fs/filesystems.o
CC lib/iomap_copy.o
CC drivers/gpu/drm/i915/i915_user_extensions.o
CC drivers/usb/host/ohci-pci.o
CC drivers/thermal/thermal_hwmon.o
CC drivers/acpi/debugfs.o
CC drivers/scsi/sr.o
CC drivers/cpuidle/sysfs.o
CC lib/devres.o
CC arch/x86/kernel/i8237.o
AR drivers/net/ethernet/broadcom/built-in.a
AR drivers/input/built-in.a
CC kernel/stacktrace.o
CC drivers/gpu/drm/i915/i915_debugfs.o
CC net/ipv4/proc.o
CC drivers/cpufreq/cpufreq_governor_attr_set.o
CC drivers/scsi/sr_ioctl.o
CC net/mac80211/key.o
CC drivers/usb/storage/option_ms.o
CC lib/check_signature.o
AR drivers/net/ethernet/intel/e1000/built-in.a
CC net/ipv6/ah6.o
CC drivers/acpi/acpica/utaddress.o
AR drivers/ufs/built-in.a
CC kernel/dma.o
CC drivers/cpuidle/poll_state.o
CC drivers/usb/core/generic.o
CC drivers/thermal/gov_step_wise.o
CC drivers/usb/storage/usual-tables.o
AR drivers/net/ethernet/meta/built-in.a
CC fs/nfs/nfs4client.o
CC fs/namespace.o
CC drivers/gpu/drm/drm_eld.o
CC net/ipv6/esp6.o
CC arch/x86/kernel/stacktrace.o
CC fs/nfs/nfs4session.o
CC net/mac80211/util.o
CC lib/interval_tree.o
CC drivers/net/ethernet/intel/e1000e/nvm.o
CC drivers/usb/core/quirks.o
CC [M] drivers/gpu/drm/xe/xe_gt_idle.o
CC arch/x86/kernel/reboot.o
CC drivers/scsi/sr_vendor.o
CC drivers/cpuidle/cpuidle-haltpoll.o
CC arch/x86/kernel/msr.o
CC drivers/acpi/acpica/utalloc.o
CC drivers/scsi/sg.o
CC drivers/cpufreq/acpi-cpufreq.o
CC net/ipv6/sit.o
CC net/mac80211/parse.o
CC drivers/gpu/drm/i915/i915_debugfs_params.o
CC net/ipv4/fib_rules.o
CC kernel/smp.o
CC lib/assoc_array.o
AR drivers/thermal/built-in.a
CC [M] drivers/gpu/drm/xe/xe_gt_mcr.o
AR drivers/net/ethernet/micrel/built-in.a
AR drivers/net/ethernet/microchip/built-in.a
CC net/ipv4/ipmr.o
CC drivers/cpufreq/amd-pstate.o
CC drivers/md/dm-linear.o
AR drivers/usb/storage/built-in.a
CC drivers/md/dm-stripe.o
CC drivers/net/ethernet/intel/e1000e/phy.o
CC drivers/net/ethernet/intel/e1000e/param.o
AR drivers/firmware/arm_ffa/built-in.a
AR drivers/firmware/arm_scmi/built-in.a
AR drivers/firmware/broadcom/built-in.a
CC lib/bitrev.o
AR drivers/firmware/cirrus/test/built-in.a
CC drivers/usb/host/uhci-hcd.o
AR drivers/firmware/cirrus/built-in.a
CC arch/x86/kernel/cpuid.o
CC drivers/acpi/acpica/utascii.o
AR drivers/firmware/meson/built-in.a
AR drivers/cpuidle/built-in.a
AR drivers/firmware/microchip/built-in.a
CC drivers/acpi/acpi_lpat.o
CC net/ipv6/addrconf_core.o
CC drivers/firmware/efi/efi-bgrt.o
CC drivers/firmware/efi/efi.o
CC drivers/firmware/efi/libstub/efi-stub-helper.o
CC drivers/acpi/acpi_pcc.o
CC drivers/usb/core/devices.o
CC drivers/net/ethernet/intel/e1000e/ethtool.o
CC drivers/gpu/drm/drm_encoder.o
AR drivers/crypto/stm32/built-in.a
CC drivers/scsi/scsi_sysfs.o
AR drivers/crypto/xilinx/built-in.a
AR drivers/crypto/hisilicon/built-in.a
CC drivers/acpi/acpica/utbuffer.o
AR drivers/crypto/intel/keembay/built-in.a
CC drivers/gpu/drm/i915/i915_pmu.o
CC drivers/acpi/acpica/utcksum.o
AR drivers/crypto/intel/ixp4xx/built-in.a
AR drivers/crypto/intel/built-in.a
CC drivers/clocksource/acpi_pm.o
AR drivers/crypto/starfive/built-in.a
AR drivers/crypto/built-in.a
CC fs/nfs/dns_resolve.o
CC drivers/usb/host/xhci.o
CC drivers/firmware/efi/vars.o
CC arch/x86/kernel/early-quirks.o
CC drivers/usb/core/phy.o
CC drivers/usb/core/port.o
AR drivers/net/ethernet/mscc/built-in.a
CC net/mac80211/wme.o
CC drivers/gpu/drm/drm_file.o
CC lib/crc-ccitt.o
CC drivers/hid/usbhid/hid-core.o
CC drivers/hid/hid-core.o
CC drivers/net/ethernet/intel/e1000e/netdev.o
CC drivers/usb/host/xhci-mem.o
CC drivers/cpufreq/amd-pstate-trace.o
CC drivers/hid/usbhid/hiddev.o
AR drivers/platform/x86/amd/built-in.a
AR drivers/platform/x86/intel/built-in.a
CC drivers/platform/x86/wmi.o
CC drivers/hid/usbhid/hid-pidff.o
AR drivers/net/ethernet/marvell/built-in.a
CC drivers/platform/x86/wmi-bmof.o
CC [M] drivers/gpu/drm/xe/xe_gt_pagefault.o
CC drivers/gpu/drm/drm_fourcc.o
CC drivers/acpi/acpica/utcopy.o
CC kernel/uid16.o
CC lib/crc16.o
CC drivers/firmware/efi/libstub/gop.o
CC drivers/usb/core/hcd-pci.o
CC drivers/md/dm-ioctl.o
CC drivers/gpu/drm/drm_framebuffer.o
CC net/ipv6/exthdrs_core.o
CC drivers/usb/host/xhci-ext-caps.o
CC drivers/clocksource/i8253.o
CC fs/seq_file.o
CC drivers/mailbox/mailbox.o
CC drivers/gpu/drm/drm_gem.o
CC drivers/usb/host/xhci-ring.o
CC kernel/kallsyms.o
CC net/ipv6/ip6_checksum.o
CC drivers/acpi/acpica/utexcep.o
HOSTCC lib/gen_crc32table
CC drivers/gpu/drm/i915/gt/gen2_engine_cs.o
CC fs/xattr.o
CC arch/x86/kernel/smp.o
CC kernel/acct.o
CC lib/xxhash.o
CC drivers/md/dm-io.o
CC fs/nfs/nfs4trace.o
CC drivers/cpufreq/intel_pstate.o
CC fs/nfs/nfs4sysctl.o
AR drivers/clocksource/built-in.a
CC drivers/hid/hid-input.o
AR drivers/firmware/imx/built-in.a
CC drivers/gpu/drm/drm_ioctl.o
CC drivers/net/ethernet/intel/e1000e/ptp.o
CC net/ipv4/ipmr_base.o
AR drivers/scsi/built-in.a
AR drivers/platform/surface/built-in.a
CC [M] drivers/gpu/drm/xe/xe_gt_sysfs.o
CC drivers/acpi/acpica/utdebug.o
CC drivers/platform/x86/eeepc-laptop.o
CC drivers/mailbox/pcc.o
CC drivers/acpi/ac.o
CC fs/libfs.o
CC drivers/firmware/efi/libstub/secureboot.o
CC drivers/gpu/drm/i915/gt/gen6_engine_cs.o
CC drivers/usb/core/usb-acpi.o
CC net/ipv6/ip6_icmp.o
AR drivers/firmware/psci/built-in.a
CC drivers/gpu/drm/drm_lease.o
CC net/mac80211/chan.o
CC arch/x86/kernel/smpboot.o
CC [M] drivers/gpu/drm/xe/xe_gt_throttle.o
CC drivers/acpi/acpica/utdecode.o
CC drivers/hid/hid-quirks.o
CC lib/genalloc.o
AR drivers/hid/usbhid/built-in.a
CC arch/x86/kernel/tsc_sync.o
CC kernel/vmcore_info.o
CC fs/fs-writeback.o
CC drivers/firmware/efi/libstub/tpm.o
CC drivers/acpi/button.o
CC drivers/acpi/fan_core.o
CC arch/x86/kernel/setup_percpu.o
CC drivers/gpu/drm/i915/gt/gen6_ppgtt.o
CC [M] drivers/gpu/drm/xe/xe_gt_tlb_invalidation.o
AR drivers/mailbox/built-in.a
CC drivers/firmware/efi/reboot.o
CC [M] drivers/gpu/drm/xe/xe_gt_topology.o
CC drivers/usb/host/xhci-hub.o
CC kernel/elfcorehdr.o
CC net/ipv6/output_core.o
CC drivers/acpi/acpica/utdelete.o
CC drivers/gpu/drm/drm_managed.o
CC net/mac80211/trace.o
CC drivers/acpi/fan_attr.o
AR drivers/net/ethernet/myricom/built-in.a
CC drivers/platform/x86/p2sb.o
CC net/ipv4/syncookies.o
CC drivers/firmware/efi/libstub/file.o
CC net/ipv6/protocol.o
CC drivers/acpi/acpica/uterror.o
AR drivers/usb/core/built-in.a
CC drivers/hid/hid-debug.o
CC net/ipv4/tunnel4.o
CC drivers/md/dm-kcopyd.o
AR drivers/net/ethernet/natsemi/built-in.a
CC net/ipv4/ipconfig.o
CC arch/x86/kernel/mpparse.o
CC lib/percpu_counter.o
CC drivers/firmware/efi/memattr.o
CC drivers/acpi/acpica/uteval.o
CC fs/pnode.o
CC drivers/md/dm-sysfs.o
CC net/mac80211/mlme.o
AR drivers/net/ethernet/neterion/built-in.a
CC net/ipv4/netfilter.o
CC drivers/firmware/efi/libstub/mem.o
CC drivers/gpu/drm/drm_mm.o
CC fs/splice.o
AR drivers/firmware/qcom/built-in.a
CC net/ipv6/ip6_offload.o
AR drivers/firmware/smccc/built-in.a
CC drivers/acpi/fan_hwmon.o
CC drivers/acpi/acpica/utglobal.o
CC kernel/crash_reserve.o
CC fs/sync.o
CC [M] drivers/gpu/drm/xe/xe_guc.o
CC net/mac80211/tdls.o
CC drivers/gpu/drm/i915/gt/gen7_renderclear.o
AR drivers/perf/built-in.a
CC drivers/hid/hidraw.o
CC net/ipv6/tcpv6_offload.o
CC arch/x86/kernel/trace_clock.o
CC net/ipv6/exthdrs_offload.o
AR drivers/net/ethernet/netronome/built-in.a
AR drivers/platform/x86/built-in.a
CC drivers/firmware/efi/tpm.o
AR drivers/platform/built-in.a
CC drivers/acpi/acpi_video.o
CC drivers/md/dm-stats.o
CC fs/utimes.o
CC drivers/acpi/acpica/uthex.o
CC lib/audit.o
CC net/mac80211/ocb.o
CC drivers/acpi/video_detect.o
CC [M] drivers/gpu/drm/xe/xe_guc_ads.o
CC drivers/firmware/efi/memmap.o
AR drivers/net/ethernet/ni/built-in.a
CC drivers/md/dm-rq.o
CC drivers/net/ethernet/nvidia/forcedeth.o
CC drivers/acpi/processor_driver.o
CC drivers/firmware/efi/libstub/random.o
CC drivers/acpi/acpica/utids.o
CC kernel/kexec_core.o
AR drivers/hwtracing/intel_th/built-in.a
AR drivers/android/built-in.a
AR drivers/cpufreq/built-in.a
CC net/ipv6/inet6_hashtables.o
CC drivers/gpu/drm/i915/gt/gen8_engine_cs.o
AR drivers/nvmem/layouts/built-in.a
CC drivers/acpi/processor_thermal.o
CC drivers/nvmem/core.o
CC drivers/firmware/efi/libstub/randomalloc.o
CC drivers/firmware/efi/capsule.o
CC [M] drivers/gpu/drm/xe/xe_guc_buf.o
CC arch/x86/kernel/trace.o
CC net/mac80211/airtime.o
CC net/ipv6/mcast_snoop.o
AR drivers/firmware/tegra/built-in.a
CC drivers/hid/hid-generic.o
AR drivers/firmware/xilinx/built-in.a
CC drivers/firmware/dmi_scan.o
CC drivers/acpi/acpica/utinit.o
CC drivers/acpi/acpica/utlock.o
CC lib/syscall.o
CC [M] drivers/gpu/drm/xe/xe_guc_capture.o
CC drivers/acpi/processor_idle.o
CC drivers/firmware/efi/esrt.o
CC drivers/firmware/efi/libstub/pci.o
CC drivers/hid/hid-a4tech.o
CC arch/x86/kernel/rethook.o
CC net/mac80211/eht.o
CC net/mac80211/led.o
CC drivers/gpu/drm/drm_mode_config.o
CC drivers/usb/host/xhci-dbg.o
CC drivers/firmware/dmi-id.o
CC lib/errname.o
CC drivers/firmware/efi/libstub/skip_spaces.o
CC drivers/hid/hid-apple.o
CC drivers/acpi/processor_throttling.o
CC drivers/firmware/efi/runtime-wrappers.o
CC drivers/acpi/acpica/utmath.o
CC drivers/acpi/acpica/utmisc.o
CC kernel/crash_core.o
CC drivers/md/dm-io-rewind.o
CC net/mac80211/pm.o
CC drivers/firmware/memmap.o
CC net/ipv4/tcp_cubic.o
CC drivers/firmware/efi/capsule-loader.o
CC lib/nlattr.o
CC drivers/hid/hid-belkin.o
CC drivers/md/dm-builtin.o
CC net/ipv4/tcp_sigpool.o
CC [M] drivers/gpu/drm/xe/xe_guc_ct.o
AR drivers/net/ethernet/oki-semi/built-in.a
CC fs/d_path.o
CC drivers/firmware/efi/earlycon.o
CC kernel/kexec.o
CC net/mac80211/rc80211_minstrel_ht.o
CC arch/x86/kernel/vmcore_info_32.o
CC net/ipv4/cipso_ipv4.o
CC drivers/acpi/acpica/utmutex.o
CC drivers/firmware/efi/libstub/lib-cmdline.o
CC drivers/hid/hid-cherry.o
CC arch/x86/kernel/machine_kexec_32.o
CC drivers/usb/host/xhci-trace.o
CC net/ipv4/xfrm4_policy.o
CC lib/cpu_rmap.o
CC kernel/utsname.o
CC drivers/firmware/efi/libstub/lib-ctype.o
CC drivers/firmware/efi/libstub/alignedmem.o
AR drivers/net/ethernet/packetengines/built-in.a
CC fs/stack.o
AR drivers/nvmem/built-in.a
CC drivers/usb/host/xhci-debugfs.o
CC drivers/acpi/processor_perflib.o
AR fs/nfs/built-in.a
CC [M] drivers/gpu/drm/xe/xe_guc_db_mgr.o
CC drivers/gpu/drm/drm_mode_object.o
AR drivers/net/ethernet/qlogic/built-in.a
CC net/mac80211/wbrf.o
CC drivers/gpu/drm/i915/gt/gen8_ppgtt.o
CC drivers/hid/hid-chicony.o
AS arch/x86/kernel/relocate_kernel_32.o
CC drivers/acpi/acpica/utnonansi.o
CC drivers/md/dm-raid1.o
CC drivers/acpi/acpica/utobject.o
CC lib/dynamic_queue_limits.o
CC drivers/firmware/efi/libstub/relocate.o
CC kernel/pid_namespace.o
AR net/ipv6/built-in.a
AR drivers/net/ethernet/qualcomm/emac/built-in.a
CC drivers/usb/host/xhci-pci.o
AR drivers/net/ethernet/qualcomm/built-in.a
CC lib/glob.o
CC drivers/gpu/drm/i915/gt/intel_breadcrumbs.o
CC drivers/gpu/drm/drm_modes.o
CC [M] drivers/gpu/drm/xe/xe_guc_engine_activity.o
CC net/ipv4/xfrm4_state.o
CC lib/strncpy_from_user.o
CC kernel/stop_machine.o
CC drivers/acpi/acpica/utosi.o
CC drivers/firmware/efi/libstub/printk.o
CC drivers/acpi/container.o
CC net/ipv4/xfrm4_input.o
CC drivers/net/ethernet/realtek/8139too.o
AR drivers/net/ethernet/intel/e1000e/built-in.a
AR drivers/net/ethernet/intel/built-in.a
CC drivers/gpu/drm/i915/gt/intel_context.o
CC drivers/gpu/drm/drm_modeset_lock.o
CC fs/fs_struct.o
CC drivers/md/dm-log.o
AR drivers/firmware/efi/built-in.a
AR drivers/net/ethernet/renesas/built-in.a
CC arch/x86/kernel/crash_dump_32.o
CC drivers/acpi/acpica/utownerid.o
CC net/ipv4/xfrm4_output.o
CC drivers/hid/hid-cypress.o
CC drivers/md/dm-region-hash.o
CC drivers/acpi/acpica/utpredef.o
CC net/ipv4/xfrm4_protocol.o
CC drivers/gpu/drm/drm_plane.o
CC drivers/net/ethernet/realtek/r8169_main.o
CC drivers/acpi/thermal_lib.o
AR drivers/net/ethernet/rdc/built-in.a
CC arch/x86/kernel/crash.o
CC fs/statfs.o
CC drivers/acpi/thermal.o
CC drivers/hid/hid-ezkey.o
CC drivers/acpi/acpica/utresdecode.o
CC drivers/firmware/efi/libstub/vsprintf.o
CC fs/fs_pin.o
CC drivers/gpu/drm/i915/gt/intel_context_sseu.o
CC drivers/net/ethernet/realtek/r8169_firmware.o
CC drivers/hid/hid-gyration.o
CC kernel/audit.o
CC drivers/hid/hid-ite.o
AR drivers/net/ethernet/rocker/built-in.a
CC [M] drivers/gpu/drm/xe/xe_guc_hwconfig.o
CC fs/nsfs.o
CC drivers/acpi/acpica/utresrc.o
CC [M] drivers/gpu/drm/xe/xe_guc_id_mgr.o
CC drivers/acpi/nhlt.o
CC drivers/net/ethernet/realtek/r8169_phy_config.o
CC drivers/firmware/efi/libstub/x86-stub.o
CC lib/strnlen_user.o
CC drivers/gpu/drm/drm_prime.o
CC drivers/acpi/acpica/utstate.o
CC kernel/auditfilter.o
AR drivers/net/ethernet/samsung/built-in.a
CC drivers/hid/hid-kensington.o
CC drivers/gpu/drm/i915/gt/intel_engine_cs.o
CC drivers/md/dm-zero.o
CC kernel/auditsc.o
CC arch/x86/kernel/module.o
CC [M] drivers/gpu/drm/xe/xe_guc_klv_helpers.o
CC fs/fs_types.o
CC drivers/hid/hid-lg.o
AR drivers/net/ethernet/seeq/built-in.a
CC [M] drivers/gpu/drm/xe/xe_guc_log.o
AR drivers/net/ethernet/silan/built-in.a
CC [M] drivers/gpu/drm/xe/xe_guc_pc.o
CC drivers/gpu/drm/i915/gt/intel_engine_heartbeat.o
CC fs/fs_context.o
CC lib/net_utils.o
CC drivers/gpu/drm/drm_print.o
CC kernel/audit_watch.o
CC drivers/hid/hid-lgff.o
CC lib/sg_pool.o
CC arch/x86/kernel/doublefault_32.o
CC drivers/acpi/acpica/utstring.o
AR drivers/net/ethernet/sis/built-in.a
CC drivers/gpu/drm/drm_property.o
AR drivers/net/ethernet/sfc/built-in.a
CC fs/fs_parser.o
CC drivers/acpi/acpica/utstrsuppt.o
CC drivers/gpu/drm/drm_rect.o
CC fs/fsopen.o
CC drivers/firmware/efi/libstub/smbios.o
CC [M] drivers/gpu/drm/xe/xe_guc_submit.o
CC drivers/gpu/drm/i915/gt/intel_engine_pm.o
CC kernel/audit_fsnotify.o
CC arch/x86/kernel/early_printk.o
AR net/ipv4/built-in.a
AR drivers/net/ethernet/smsc/built-in.a
CC drivers/acpi/acpica/utstrtoul64.o
CC drivers/acpi/acpi_memhotplug.o
AR drivers/net/ethernet/socionext/built-in.a
AR drivers/net/ethernet/nvidia/built-in.a
CC drivers/acpi/ioapic.o
CC drivers/gpu/drm/drm_syncobj.o
CC fs/init.o
CC [M] drivers/gpu/drm/xe/xe_heci_gsc.o
AR drivers/net/ethernet/stmicro/built-in.a
AR drivers/md/built-in.a
CC [M] drivers/gpu/drm/xe/xe_huc.o
CC arch/x86/kernel/hpet.o
CC drivers/gpu/drm/i915/gt/intel_engine_user.o
AR drivers/net/ethernet/sun/built-in.a
CC drivers/gpu/drm/i915/gt/intel_execlists_submission.o
CC lib/stackdepot.o
CC drivers/gpu/drm/drm_sysfs.o
CC arch/x86/kernel/amd_nb.o
CC drivers/acpi/battery.o
CC drivers/gpu/drm/i915/gt/intel_ggtt.o
AR drivers/usb/host/built-in.a
AR drivers/net/ethernet/tehuti/built-in.a
AR drivers/usb/built-in.a
AR drivers/net/ethernet/ti/built-in.a
CC [M] drivers/gpu/drm/xe/xe_hw_engine.o
CC kernel/audit_tree.o
CC lib/asn1_decoder.o
STUBCPY drivers/firmware/efi/libstub/alignedmem.stub.o
CC fs/kernel_read_file.o
CC drivers/hid/hid-lg4ff.o
CC drivers/gpu/drm/i915/gt/intel_ggtt_fencing.o
AR drivers/net/ethernet/vertexcom/built-in.a
CC [M] drivers/gpu/drm/xe/xe_hw_engine_class_sysfs.o
CC drivers/acpi/acpica/utxface.o
CC fs/mnt_idmapping.o
CC drivers/gpu/drm/i915/gt/intel_gt.o
GEN lib/oid_registry_data.c
STUBCPY drivers/firmware/efi/libstub/efi-stub-helper.stub.o
CC drivers/gpu/drm/drm_trace_points.o
CC [M] drivers/gpu/drm/xe/xe_hw_engine_group.o
STUBCPY drivers/firmware/efi/libstub/file.stub.o
STUBCPY drivers/firmware/efi/libstub/gop.stub.o
STUBCPY drivers/firmware/efi/libstub/lib-cmdline.stub.o
STUBCPY drivers/firmware/efi/libstub/lib-ctype.stub.o
STUBCPY drivers/firmware/efi/libstub/mem.stub.o
STUBCPY drivers/firmware/efi/libstub/pci.stub.o
STUBCPY drivers/firmware/efi/libstub/printk.stub.o
AR drivers/net/ethernet/via/built-in.a
STUBCPY drivers/firmware/efi/libstub/random.stub.o
CC drivers/hid/hid-lg-g15.o
STUBCPY drivers/firmware/efi/libstub/randomalloc.stub.o
CC fs/remap_range.o
STUBCPY drivers/firmware/efi/libstub/relocate.stub.o
STUBCPY drivers/firmware/efi/libstub/secureboot.stub.o
CC drivers/acpi/acpica/utxfinit.o
STUBCPY drivers/firmware/efi/libstub/skip_spaces.stub.o
CC arch/x86/kernel/amd_node.o
STUBCPY drivers/firmware/efi/libstub/smbios.stub.o
CC fs/pidfs.o
STUBCPY drivers/firmware/efi/libstub/tpm.stub.o
CC kernel/kprobes.o
STUBCPY drivers/firmware/efi/libstub/vsprintf.stub.o
STUBCPY drivers/firmware/efi/libstub/x86-stub.stub.o
CC drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.o
AR drivers/firmware/efi/libstub/lib.a
CC kernel/seccomp.o
AR drivers/net/ethernet/wangxun/built-in.a
CC drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.o
AR drivers/firmware/built-in.a
CC drivers/acpi/acpica/utxferror.o
CC fs/buffer.o
CC lib/ucs2_string.o
CC drivers/acpi/bgrt.o
CC fs/mpage.o
CC arch/x86/kernel/kvm.o
CC drivers/acpi/spcr.o
CC drivers/hid/hid-microsoft.o
CC [M] drivers/gpu/drm/xe/xe_hw_fence.o
CC drivers/hid/hid-monterey.o
CC drivers/gpu/drm/drm_vblank.o
CC drivers/gpu/drm/i915/gt/intel_gt_clock_utils.o
CC lib/sbitmap.o
CC [M] drivers/gpu/drm/xe/xe_irq.o
CC drivers/acpi/acpica/utxfmutex.o
CC lib/group_cpus.o
AR drivers/net/ethernet/wiznet/built-in.a
CC lib/fw_table.o
CC fs/proc_namespace.o
CC fs/direct-io.o
CC kernel/relay.o
AR drivers/net/ethernet/xilinx/built-in.a
AR drivers/net/ethernet/xircom/built-in.a
AR lib/lib.a
CC arch/x86/kernel/kvmclock.o
CC drivers/hid/hid-ntrig.o
CC drivers/gpu/drm/drm_vblank_work.o
CC [M] drivers/gpu/drm/xe/xe_lrc.o
CC kernel/utsname_sysctl.o
AR drivers/net/ethernet/synopsys/built-in.a
CC arch/x86/kernel/paravirt.o
CC drivers/gpu/drm/i915/gt/intel_gt_debugfs.o
CC fs/eventpoll.o
GEN lib/crc32table.h
CC drivers/hid/hid-pl.o
CC kernel/delayacct.o
AR drivers/acpi/acpica/built-in.a
CC drivers/gpu/drm/drm_vma_manager.o
AR drivers/net/ethernet/pensando/built-in.a
CC kernel/taskstats.o
CC arch/x86/kernel/pvclock.o
CC [M] drivers/gpu/drm/xe/xe_migrate.o
CC kernel/tsacct.o
CC arch/x86/kernel/pcspeaker.o
AR drivers/acpi/built-in.a
CC drivers/hid/hid-petalynx.o
CC drivers/gpu/drm/i915/gt/intel_gt_engines_debugfs.o
CC lib/oid_registry.o
CC fs/anon_inodes.o
CC drivers/gpu/drm/i915/gt/intel_gt_irq.o
CC drivers/hid/hid-redragon.o
CC kernel/tracepoint.o
CC fs/signalfd.o
CC kernel/irq_work.o
CC lib/crc32.o
CC [M] drivers/gpu/drm/xe/xe_mmio.o
CC arch/x86/kernel/check.o
CC drivers/gpu/drm/i915/gt/intel_gt_mcr.o
CC fs/timerfd.o
CC kernel/static_call.o
CC drivers/gpu/drm/drm_writeback.o
CC [M] drivers/gpu/drm/xe/xe_mocs.o
CC drivers/hid/hid-samsung.o
CC drivers/hid/hid-sony.o
CC fs/eventfd.o
AR drivers/net/ethernet/realtek/built-in.a
CC drivers/gpu/drm/drm_panel.o
AR drivers/net/ethernet/built-in.a
CC arch/x86/kernel/uprobes.o
CC kernel/padata.o
CC drivers/hid/hid-sunplus.o
CC [M] drivers/gpu/drm/xe/xe_module.o
CC fs/aio.o
AR drivers/net/built-in.a
CC arch/x86/kernel/perf_regs.o
AR lib/built-in.a
CC drivers/hid/hid-topseed.o
CC kernel/jump_label.o
CC drivers/gpu/drm/drm_pci.o
CC [M] drivers/gpu/drm/xe/xe_oa.o
CC drivers/gpu/drm/i915/gt/intel_gt_pm.o
CC fs/locks.o
CC arch/x86/kernel/tracepoint.o
CC kernel/context_tracking.o
CC drivers/gpu/drm/drm_debugfs.o
CC kernel/iomem.o
CC [M] drivers/gpu/drm/xe/xe_observation.o
CC kernel/rseq.o
CC drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.o
CC arch/x86/kernel/itmt.o
CC drivers/gpu/drm/drm_debugfs_crc.o
CC [M] drivers/gpu/drm/xe/xe_pat.o
CC arch/x86/kernel/umip.o
CC fs/binfmt_misc.o
CC fs/binfmt_script.o
CC drivers/gpu/drm/drm_panel_orientation_quirks.o
CC arch/x86/kernel/unwind_frame.o
CC [M] drivers/gpu/drm/xe/xe_pci.o
CC drivers/gpu/drm/i915/gt/intel_gt_pm_irq.o
CC fs/binfmt_elf.o
CC drivers/gpu/drm/drm_buddy.o
CC [M] drivers/gpu/drm/xe/xe_pcode.o
CC fs/mbcache.o
CC drivers/gpu/drm/i915/gt/intel_gt_requests.o
CC drivers/gpu/drm/drm_gem_shmem_helper.o
CC drivers/gpu/drm/i915/gt/intel_gt_sysfs.o
CC drivers/gpu/drm/drm_atomic_helper.o
CC drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.o
CC [M] drivers/gpu/drm/xe/xe_pm.o
CC fs/posix_acl.o
CC [M] drivers/gpu/drm/xe/xe_preempt_fence.o
CC [M] drivers/gpu/drm/xe/xe_pt.o
CC fs/coredump.o
CC drivers/gpu/drm/i915/gt/intel_gtt.o
CC drivers/gpu/drm/drm_atomic_state_helper.o
CC [M] drivers/gpu/drm/xe/xe_pt_walk.o
CC [M] drivers/gpu/drm/xe/xe_pxp.o
CC drivers/gpu/drm/drm_bridge_helper.o
CC [M] drivers/gpu/drm/xe/xe_pxp_debugfs.o
CC drivers/gpu/drm/drm_crtc_helper.o
CC drivers/gpu/drm/i915/gt/intel_llc.o
CC fs/drop_caches.o
CC drivers/gpu/drm/drm_damage_helper.o
CC drivers/gpu/drm/i915/gt/intel_lrc.o
CC fs/sysctls.o
CC [M] drivers/gpu/drm/xe/xe_pxp_submit.o
CC drivers/gpu/drm/i915/gt/intel_migrate.o
CC drivers/gpu/drm/drm_flip_work.o
CC drivers/gpu/drm/i915/gt/intel_mocs.o
CC drivers/gpu/drm/drm_format_helper.o
AR arch/x86/kernel/built-in.a
AR drivers/hid/built-in.a
CC fs/fhandle.o
CC [M] drivers/gpu/drm/xe/xe_query.o
AR arch/x86/built-in.a
CC drivers/gpu/drm/i915/gt/intel_ppgtt.o
AR kernel/built-in.a
CC [M] drivers/gpu/drm/xe/xe_range_fence.o
CC drivers/gpu/drm/drm_gem_atomic_helper.o
CC drivers/gpu/drm/i915/gt/intel_rc6.o
CC [M] drivers/gpu/drm/xe/xe_reg_sr.o
CC drivers/gpu/drm/i915/gt/intel_region_lmem.o
CC drivers/gpu/drm/drm_gem_framebuffer_helper.o
CC [M] drivers/gpu/drm/xe/xe_reg_whitelist.o
CC drivers/gpu/drm/i915/gt/intel_renderstate.o
CC [M] drivers/gpu/drm/xe/xe_ring_ops.o
CC drivers/gpu/drm/drm_kms_helper_common.o
CC [M] drivers/gpu/drm/xe/xe_rtp.o
CC drivers/gpu/drm/i915/gt/intel_reset.o
CC drivers/gpu/drm/drm_modeset_helper.o
CC [M] drivers/gpu/drm/xe/xe_sa.o
CC drivers/gpu/drm/i915/gt/intel_ring.o
CC drivers/gpu/drm/drm_plane_helper.o
CC [M] drivers/gpu/drm/xe/xe_sched_job.o
CC drivers/gpu/drm/drm_probe_helper.o
CC drivers/gpu/drm/drm_self_refresh_helper.o
CC drivers/gpu/drm/i915/gt/intel_ring_submission.o
CC [M] drivers/gpu/drm/xe/xe_shrinker.o
CC drivers/gpu/drm/i915/gt/intel_rps.o
CC [M] drivers/gpu/drm/xe/xe_step.o
CC drivers/gpu/drm/drm_simple_kms_helper.o
CC [M] drivers/gpu/drm/xe/xe_survivability_mode.o
CC drivers/gpu/drm/bridge/panel.o
CC drivers/gpu/drm/i915/gt/intel_sa_media.o
CC drivers/gpu/drm/drm_mipi_dsi.o
CC drivers/gpu/drm/i915/gt/intel_sseu.o
CC [M] drivers/gpu/drm/xe/xe_sync.o
CC [M] drivers/gpu/drm/drm_exec.o
CC drivers/gpu/drm/i915/gt/intel_sseu_debugfs.o
CC [M] drivers/gpu/drm/xe/xe_tile.o
CC [M] drivers/gpu/drm/drm_gpuvm.o
CC drivers/gpu/drm/i915/gt/intel_timeline.o
AR net/mac80211/built-in.a
AR net/built-in.a
CC [M] drivers/gpu/drm/xe/xe_tile_sysfs.o
CC [M] drivers/gpu/drm/xe/xe_trace.o
CC drivers/gpu/drm/i915/gt/intel_tlb.o
CC [M] drivers/gpu/drm/drm_suballoc.o
CC [M] drivers/gpu/drm/xe/xe_trace_bo.o
CC [M] drivers/gpu/drm/drm_gem_ttm_helper.o
CC drivers/gpu/drm/i915/gt/intel_wopcm.o
CC drivers/gpu/drm/i915/gt/intel_workarounds.o
CC [M] drivers/gpu/drm/xe/xe_trace_guc.o
CC [M] drivers/gpu/drm/xe/xe_trace_lrc.o
CC drivers/gpu/drm/i915/gt/shmem_utils.o
CC [M] drivers/gpu/drm/xe/xe_ttm_stolen_mgr.o
CC [M] drivers/gpu/drm/xe/xe_ttm_sys_mgr.o
CC drivers/gpu/drm/i915/gt/sysfs_engines.o
CC [M] drivers/gpu/drm/xe/xe_ttm_vram_mgr.o
CC [M] drivers/gpu/drm/xe/xe_tuning.o
CC drivers/gpu/drm/i915/gt/intel_ggtt_gmch.o
AR fs/built-in.a
CC [M] drivers/gpu/drm/xe/xe_uc.o
CC drivers/gpu/drm/i915/gt/gen6_renderstate.o
CC [M] drivers/gpu/drm/xe/xe_uc_fw.o
CC [M] drivers/gpu/drm/xe/xe_vm.o
CC drivers/gpu/drm/i915/gt/gen7_renderstate.o
CC drivers/gpu/drm/i915/gt/gen8_renderstate.o
CC [M] drivers/gpu/drm/xe/xe_vram.o
CC drivers/gpu/drm/i915/gt/gen9_renderstate.o
CC drivers/gpu/drm/i915/gem/i915_gem_busy.o
CC [M] drivers/gpu/drm/xe/xe_vram_freq.o
CC drivers/gpu/drm/i915/gem/i915_gem_clflush.o
CC [M] drivers/gpu/drm/xe/xe_vsec.o
CC [M] drivers/gpu/drm/xe/xe_wa.o
CC drivers/gpu/drm/i915/gem/i915_gem_context.o
CC [M] drivers/gpu/drm/xe/xe_wait_user_fence.o
CC drivers/gpu/drm/i915/gem/i915_gem_create.o
CC drivers/gpu/drm/i915/gem/i915_gem_dmabuf.o
CC [M] drivers/gpu/drm/xe/xe_wopcm.o
CC drivers/gpu/drm/i915/gem/i915_gem_domain.o
LD [M] drivers/gpu/drm/drm_suballoc_helper.o
CC drivers/gpu/drm/i915/gem/i915_gem_execbuffer.o
CC [M] drivers/gpu/drm/xe/xe_hmm.o
CC drivers/gpu/drm/i915/gem/i915_gem_internal.o
CC drivers/gpu/drm/i915/gem/i915_gem_lmem.o
CC [M] drivers/gpu/drm/xe/xe_hwmon.o
LD [M] drivers/gpu/drm/drm_ttm_helper.o
CC drivers/gpu/drm/i915/gem/i915_gem_mman.o
CC [M] drivers/gpu/drm/xe/xe_pmu.o
CC drivers/gpu/drm/i915/gem/i915_gem_object.o
CC [M] drivers/gpu/drm/xe/xe_gt_sriov_vf.o
CC [M] drivers/gpu/drm/xe/xe_guc_relay.o
CC drivers/gpu/drm/i915/gem/i915_gem_pages.o
CC drivers/gpu/drm/i915/gem/i915_gem_phys.o
CC drivers/gpu/drm/i915/gem/i915_gem_pm.o
CC [M] drivers/gpu/drm/xe/xe_memirq.o
CC drivers/gpu/drm/i915/gem/i915_gem_region.o
CC drivers/gpu/drm/i915/gem/i915_gem_shmem.o
CC [M] drivers/gpu/drm/xe/xe_sriov.o
CC drivers/gpu/drm/i915/gem/i915_gem_shrinker.o
CC drivers/gpu/drm/i915/gem/i915_gem_stolen.o
CC [M] drivers/gpu/drm/xe/xe_sriov_vf.o
CC drivers/gpu/drm/i915/gem/i915_gem_throttle.o
CC [M] drivers/gpu/drm/xe/display/ext/i915_irq.o
CC drivers/gpu/drm/i915/gem/i915_gem_tiling.o
CC drivers/gpu/drm/i915/gem/i915_gem_ttm.o
CC [M] drivers/gpu/drm/xe/display/ext/i915_utils.o
CC drivers/gpu/drm/i915/gem/i915_gem_ttm_move.o
CC drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.o
CC [M] drivers/gpu/drm/xe/display/intel_bo.o
CC drivers/gpu/drm/i915/gem/i915_gem_userptr.o
CC drivers/gpu/drm/i915/gem/i915_gem_wait.o
CC [M] drivers/gpu/drm/xe/display/intel_fb_bo.o
CC drivers/gpu/drm/i915/gem/i915_gemfs.o
CC [M] drivers/gpu/drm/xe/display/intel_fbdev_fb.o
CC drivers/gpu/drm/i915/i915_active.o
CC [M] drivers/gpu/drm/xe/display/xe_display.o
CC [M] drivers/gpu/drm/xe/display/xe_display_misc.o
CC drivers/gpu/drm/i915/i915_cmd_parser.o
CC [M] drivers/gpu/drm/xe/display/xe_display_rpm.o
CC drivers/gpu/drm/i915/i915_deps.o
CC drivers/gpu/drm/i915/i915_gem.o
CC [M] drivers/gpu/drm/xe/display/xe_display_rps.o
CC [M] drivers/gpu/drm/xe/display/xe_display_wa.o
CC drivers/gpu/drm/i915/i915_gem_evict.o
CC drivers/gpu/drm/i915/i915_gem_gtt.o
CC [M] drivers/gpu/drm/xe/display/xe_dsb_buffer.o
CC drivers/gpu/drm/i915/i915_gem_ww.o
CC [M] drivers/gpu/drm/xe/display/xe_fb_pin.o
CC drivers/gpu/drm/i915/i915_query.o
CC drivers/gpu/drm/i915/i915_request.o
CC [M] drivers/gpu/drm/xe/display/xe_hdcp_gsc.o
CC [M] drivers/gpu/drm/xe/display/xe_plane_initial.o
CC [M] drivers/gpu/drm/xe/display/xe_tdf.o
CC [M] drivers/gpu/drm/xe/i915-soc/intel_dram.o
CC drivers/gpu/drm/i915/i915_scheduler.o
CC [M] drivers/gpu/drm/xe/i915-soc/intel_pch.o
CC drivers/gpu/drm/i915/i915_trace_points.o
CC drivers/gpu/drm/i915/i915_ttm_buddy_manager.o
CC [M] drivers/gpu/drm/xe/i915-soc/intel_rom.o
CC [M] drivers/gpu/drm/xe/i915-display/icl_dsi.o
CC drivers/gpu/drm/i915/i915_vma.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_alpm.o
CC drivers/gpu/drm/i915/i915_vma_resource.o
CC drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.o
CC drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.o
CC drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_atomic.o
CC drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_debugfs.o
CC drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_atomic_plane.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_audio.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_ads.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_capture.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_backlight.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_ct.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_fw.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_bios.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_log.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_rc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_bw.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_submission.o
CC drivers/gpu/drm/i915/gt/uc/intel_huc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_cdclk.o
CC drivers/gpu/drm/i915/gt/uc/intel_huc_debugfs.o
CC drivers/gpu/drm/i915/gt/uc/intel_huc_fw.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_cmtg.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_color.o
CC drivers/gpu/drm/i915/gt/uc/intel_uc.o
CC drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_combo_phy.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_connector.o
CC drivers/gpu/drm/i915/gt/uc/intel_uc_fw.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_crtc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_crtc_state_dump.o
CC drivers/gpu/drm/i915/gt/intel_gsc.o
CC drivers/gpu/drm/i915/i915_hwmon.o
CC drivers/gpu/drm/i915/display/hsw_ips.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_cursor.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_cx0_phy.o
CC drivers/gpu/drm/i915/display/i9xx_plane.o
CC drivers/gpu/drm/i915/display/i9xx_display_sr.o
CC drivers/gpu/drm/i915/display/i9xx_wm.o
CC drivers/gpu/drm/i915/display/intel_alpm.o
CC drivers/gpu/drm/i915/display/intel_atomic.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_ddi.o
CC drivers/gpu/drm/i915/display/intel_atomic_plane.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_ddi_buf_trans.o
CC drivers/gpu/drm/i915/display/intel_audio.o
CC drivers/gpu/drm/i915/display/intel_bios.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display.o
CC drivers/gpu/drm/i915/display/intel_bo.o
CC drivers/gpu/drm/i915/display/intel_bw.o
CC drivers/gpu/drm/i915/display/intel_cdclk.o
CC drivers/gpu/drm/i915/display/intel_cmtg.o
CC drivers/gpu/drm/i915/display/intel_color.o
CC drivers/gpu/drm/i915/display/intel_combo_phy.o
CC drivers/gpu/drm/i915/display/intel_connector.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_conversion.o
CC drivers/gpu/drm/i915/display/intel_crtc.o
CC drivers/gpu/drm/i915/display/intel_crtc_state_dump.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_device.o
CC drivers/gpu/drm/i915/display/intel_cursor.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_driver.o
CC drivers/gpu/drm/i915/display/intel_display.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_irq.o
CC drivers/gpu/drm/i915/display/intel_display_conversion.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_params.o
CC drivers/gpu/drm/i915/display/intel_display_driver.o
CC drivers/gpu/drm/i915/display/intel_display_irq.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_power.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_power_map.o
CC drivers/gpu/drm/i915/display/intel_display_params.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_power_well.o
CC drivers/gpu/drm/i915/display/intel_display_power.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_trace.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_wa.o
CC drivers/gpu/drm/i915/display/intel_display_power_map.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dkl_phy.o
CC drivers/gpu/drm/i915/display/intel_display_power_well.o
CC drivers/gpu/drm/i915/display/intel_display_reset.o
CC drivers/gpu/drm/i915/display/intel_display_rpm.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dmc.o
CC drivers/gpu/drm/i915/display/intel_display_rps.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dmc_wl.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dp.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_aux.o
CC drivers/gpu/drm/i915/display/intel_display_snapshot.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_aux_backlight.o
CC drivers/gpu/drm/i915/display/intel_display_wa.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_hdcp.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_link_training.o
CC drivers/gpu/drm/i915/display/intel_dmc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_mst.o
CC drivers/gpu/drm/i915/display/intel_dmc_wl.o
CC drivers/gpu/drm/i915/display/intel_dpio_phy.o
CC drivers/gpu/drm/i915/display/intel_dpll.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_test.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dpll.o
CC drivers/gpu/drm/i915/display/intel_dpll_mgr.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dpll_mgr.o
CC drivers/gpu/drm/i915/display/intel_dpt.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dpt_common.o
CC drivers/gpu/drm/i915/display/intel_dpt_common.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_drrs.o
CC drivers/gpu/drm/i915/display/intel_drrs.o
CC drivers/gpu/drm/i915/display/intel_dsb.o
CC drivers/gpu/drm/i915/display/intel_dsb_buffer.o
CC drivers/gpu/drm/i915/display/intel_fb.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dsb.o
CC drivers/gpu/drm/i915/display/intel_fb_bo.o
CC drivers/gpu/drm/i915/display/intel_fb_pin.o
CC drivers/gpu/drm/i915/display/intel_fbc.o
CC drivers/gpu/drm/i915/display/intel_fdi.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dsi.o
CC drivers/gpu/drm/i915/display/intel_fifo_underrun.o
CC drivers/gpu/drm/i915/display/intel_frontbuffer.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dsi_dcs_backlight.o
CC drivers/gpu/drm/i915/display/intel_global_state.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dsi_vbt.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_encoder.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_fb.o
CC drivers/gpu/drm/i915/display/intel_hdcp.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_fbc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_fdi.o
CC drivers/gpu/drm/i915/display/intel_hdcp_gsc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_fifo_underrun.o
CC drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_frontbuffer.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_global_state.o
CC drivers/gpu/drm/i915/display/intel_hotplug.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_gmbus.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_hdcp.o
CC drivers/gpu/drm/i915/display/intel_hotplug_irq.o
CC drivers/gpu/drm/i915/display/intel_hti.o
CC drivers/gpu/drm/i915/display/intel_link_bw.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_hdcp_gsc_message.o
CC drivers/gpu/drm/i915/display/intel_load_detect.o
CC drivers/gpu/drm/i915/display/intel_lpe_audio.o
CC drivers/gpu/drm/i915/display/intel_modeset_lock.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_hdmi.o
CC drivers/gpu/drm/i915/display/intel_modeset_setup.o
CC drivers/gpu/drm/i915/display/intel_modeset_verify.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_hotplug.o
CC drivers/gpu/drm/i915/display/intel_overlay.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_hotplug_irq.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_hti.o
CC drivers/gpu/drm/i915/display/intel_pch_display.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_link_bw.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_lspcon.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_modeset_lock.o
CC drivers/gpu/drm/i915/display/intel_pch_refclk.o
CC drivers/gpu/drm/i915/display/intel_plane_initial.o
CC drivers/gpu/drm/i915/display/intel_pmdemand.o
CC drivers/gpu/drm/i915/display/intel_psr.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_modeset_setup.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_modeset_verify.o
CC drivers/gpu/drm/i915/display/intel_quirks.o
CC drivers/gpu/drm/i915/display/intel_sprite.o
CC drivers/gpu/drm/i915/display/intel_sprite_uapi.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_panel.o
CC drivers/gpu/drm/i915/display/intel_tc.o
CC drivers/gpu/drm/i915/display/intel_vblank.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_pfit.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_pmdemand.o
CC drivers/gpu/drm/i915/display/intel_vga.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_pps.o
CC drivers/gpu/drm/i915/display/intel_wm.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_psr.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_qp_tables.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_quirks.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_snps_hdmi_pll.o
CC drivers/gpu/drm/i915/display/skl_scaler.o
CC drivers/gpu/drm/i915/display/skl_universal_plane.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_snps_phy.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_tc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_vblank.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_vdsc.o
CC drivers/gpu/drm/i915/display/skl_watermark.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_vga.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_vrr.o
CC drivers/gpu/drm/i915/display/intel_acpi.o
CC drivers/gpu/drm/i915/display/intel_opregion.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_wm.o
CC [M] drivers/gpu/drm/xe/i915-display/skl_scaler.o
CC drivers/gpu/drm/i915/display/intel_display_debugfs.o
CC drivers/gpu/drm/i915/display/intel_display_debugfs_params.o
CC [M] drivers/gpu/drm/xe/i915-display/skl_universal_plane.o
CC drivers/gpu/drm/i915/display/intel_pipe_crc.o
CC drivers/gpu/drm/i915/display/dvo_ch7017.o
CC drivers/gpu/drm/i915/display/dvo_ch7xxx.o
CC [M] drivers/gpu/drm/xe/i915-display/skl_watermark.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_acpi.o
CC drivers/gpu/drm/i915/display/dvo_ivch.o
CC drivers/gpu/drm/i915/display/dvo_ns2501.o
CC drivers/gpu/drm/i915/display/dvo_sil164.o
CC drivers/gpu/drm/i915/display/dvo_tfp410.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_opregion.o
CC drivers/gpu/drm/i915/display/g4x_dp.o
CC drivers/gpu/drm/i915/display/g4x_hdmi.o
CC [M] drivers/gpu/drm/xe/xe_debugfs.o
CC drivers/gpu/drm/i915/display/icl_dsi.o
CC [M] drivers/gpu/drm/xe/xe_gt_debugfs.o
CC drivers/gpu/drm/i915/display/intel_backlight.o
CC [M] drivers/gpu/drm/xe/xe_gt_sriov_vf_debugfs.o
CC [M] drivers/gpu/drm/xe/xe_gt_stats.o
CC drivers/gpu/drm/i915/display/intel_crt.o
CC [M] drivers/gpu/drm/xe/xe_huc_debugfs.o
CC [M] drivers/gpu/drm/xe/xe_guc_debugfs.o
CC drivers/gpu/drm/i915/display/intel_cx0_phy.o
CC drivers/gpu/drm/i915/display/intel_ddi.o
CC [M] drivers/gpu/drm/xe/xe_uc_debugfs.o
CC drivers/gpu/drm/i915/display/intel_ddi_buf_trans.o
CC drivers/gpu/drm/i915/display/intel_display_device.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_debugfs.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_debugfs_params.o
CC drivers/gpu/drm/i915/display/intel_display_trace.o
CC drivers/gpu/drm/i915/display/intel_dkl_phy.o
CC drivers/gpu/drm/i915/display/intel_dp.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_pipe_crc.o
CC drivers/gpu/drm/i915/display/intel_dp_aux.o
CC drivers/gpu/drm/i915/display/intel_dp_aux_backlight.o
CC drivers/gpu/drm/i915/display/intel_dp_hdcp.o
CC drivers/gpu/drm/i915/display/intel_dp_link_training.o
CC drivers/gpu/drm/i915/display/intel_dp_mst.o
CC drivers/gpu/drm/i915/display/intel_dp_test.o
CC drivers/gpu/drm/i915/display/intel_dsi.o
CC drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.o
CC drivers/gpu/drm/i915/display/intel_dsi_vbt.o
CC drivers/gpu/drm/i915/display/intel_dvo.o
CC drivers/gpu/drm/i915/display/intel_encoder.o
CC drivers/gpu/drm/i915/display/intel_gmbus.o
CC drivers/gpu/drm/i915/display/intel_hdmi.o
CC drivers/gpu/drm/i915/display/intel_lspcon.o
CC drivers/gpu/drm/i915/display/intel_lvds.o
CC drivers/gpu/drm/i915/display/intel_panel.o
CC drivers/gpu/drm/i915/display/intel_pfit.o
CC drivers/gpu/drm/i915/display/intel_pps.o
CC drivers/gpu/drm/i915/display/intel_qp_tables.o
CC drivers/gpu/drm/i915/display/intel_sdvo.o
CC drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.o
CC drivers/gpu/drm/i915/display/intel_snps_phy.o
CC drivers/gpu/drm/i915/display/intel_tv.o
CC drivers/gpu/drm/i915/display/intel_vdsc.o
CC drivers/gpu/drm/i915/display/intel_vrr.o
CC drivers/gpu/drm/i915/display/vlv_dsi.o
CC drivers/gpu/drm/i915/display/vlv_dsi_pll.o
CC drivers/gpu/drm/i915/i915_perf.o
CC drivers/gpu/drm/i915/pxp/intel_pxp.o
CC drivers/gpu/drm/i915/pxp/intel_pxp_huc.o
CC drivers/gpu/drm/i915/pxp/intel_pxp_tee.o
CC drivers/gpu/drm/i915/i915_gpu_error.o
CC drivers/gpu/drm/i915/i915_vgpu.o
LD [M] drivers/gpu/drm/xe/xe.o
AR drivers/gpu/drm/i915/built-in.a
AR drivers/gpu/drm/built-in.a
AR drivers/gpu/built-in.a
AR drivers/built-in.a
AR built-in.a
AR vmlinux.a
LD vmlinux.o
OBJCOPY modules.builtin.modinfo
GEN modules.builtin
MODPOST Module.symvers
CC .vmlinux.export.o
CC [M] fs/efivarfs/efivarfs.mod.o
CC [M] .module-common.o
CC [M] drivers/gpu/drm/drm_exec.mod.o
CC [M] drivers/gpu/drm/drm_gpuvm.mod.o
CC [M] drivers/gpu/drm/drm_suballoc_helper.mod.o
CC [M] drivers/gpu/drm/drm_ttm_helper.mod.o
CC [M] drivers/gpu/drm/scheduler/gpu-sched.mod.o
CC [M] drivers/gpu/drm/xe/xe.mod.o
CC [M] drivers/thermal/intel/x86_pkg_temp_thermal.mod.o
CC [M] net/netfilter/nf_log_syslog.mod.o
CC [M] net/netfilter/xt_mark.mod.o
CC [M] net/netfilter/xt_nat.mod.o
CC [M] net/netfilter/xt_LOG.mod.o
CC [M] net/netfilter/xt_MASQUERADE.mod.o
CC [M] net/netfilter/xt_addrtype.mod.o
CC [M] net/ipv4/netfilter/iptable_nat.mod.o
LD [M] fs/efivarfs/efivarfs.ko
LD [M] drivers/gpu/drm/drm_suballoc_helper.ko
LD [M] drivers/gpu/drm/scheduler/gpu-sched.ko
LD [M] net/netfilter/nf_log_syslog.ko
LD [M] drivers/gpu/drm/drm_gpuvm.ko
LD [M] net/netfilter/xt_mark.ko
LD [M] net/netfilter/xt_nat.ko
LD [M] drivers/gpu/drm/drm_ttm_helper.ko
LD [M] drivers/gpu/drm/drm_exec.ko
LD [M] net/netfilter/xt_addrtype.ko
LD [M] net/ipv4/netfilter/iptable_nat.ko
LD [M] drivers/gpu/drm/xe/xe.ko
LD [M] drivers/thermal/intel/x86_pkg_temp_thermal.ko
LD [M] net/netfilter/xt_MASQUERADE.ko
LD [M] net/netfilter/xt_LOG.ko
UPD include/generated/utsversion.h
CC init/version-timestamp.o
KSYMS .tmp_vmlinux0.kallsyms.S
AS .tmp_vmlinux0.kallsyms.o
LD .tmp_vmlinux1
NM .tmp_vmlinux1.syms
KSYMS .tmp_vmlinux1.kallsyms.S
AS .tmp_vmlinux1.kallsyms.o
LD .tmp_vmlinux2
NM .tmp_vmlinux2.syms
KSYMS .tmp_vmlinux2.kallsyms.S
AS .tmp_vmlinux2.kallsyms.o
LD vmlinux
NM System.map
SORTTAB vmlinux
RELOCS arch/x86/boot/compressed/vmlinux.relocs
RSTRIP vmlinux
CC arch/x86/boot/a20.o
AS arch/x86/boot/bioscall.o
CC arch/x86/boot/cmdline.o
AS arch/x86/boot/copy.o
HOSTCC arch/x86/boot/mkcpustr
CC arch/x86/boot/cpuflags.o
CC arch/x86/boot/cpucheck.o
CC arch/x86/boot/early_serial_console.o
CC arch/x86/boot/edd.o
CC arch/x86/boot/main.o
CC arch/x86/boot/memory.o
CC arch/x86/boot/pm.o
AS arch/x86/boot/pmjump.o
CC arch/x86/boot/printf.o
CC arch/x86/boot/regs.o
CC arch/x86/boot/string.o
CC arch/x86/boot/tty.o
CC arch/x86/boot/video.o
CC arch/x86/boot/video-mode.o
CC arch/x86/boot/version.o
CC arch/x86/boot/video-vga.o
CC arch/x86/boot/video-vesa.o
CC arch/x86/boot/video-bios.o
HOSTCC arch/x86/boot/tools/build
CPUSTR arch/x86/boot/cpustr.h
CC arch/x86/boot/cpu.o
LDS arch/x86/boot/compressed/vmlinux.lds
AS arch/x86/boot/compressed/kernel_info.o
AS arch/x86/boot/compressed/head_32.o
VOFFSET arch/x86/boot/compressed/../voffset.h
CC arch/x86/boot/compressed/string.o
CC arch/x86/boot/compressed/cmdline.o
CC arch/x86/boot/compressed/error.o
OBJCOPY arch/x86/boot/compressed/vmlinux.bin
HOSTCC arch/x86/boot/compressed/mkpiggy
CC arch/x86/boot/compressed/cpuflags.o
CC arch/x86/boot/compressed/early_serial_console.o
CC arch/x86/boot/compressed/kaslr.o
CC arch/x86/boot/compressed/acpi.o
CC arch/x86/boot/compressed/efi.o
GZIP arch/x86/boot/compressed/vmlinux.bin.gz
CC arch/x86/boot/compressed/misc.o
MKPIGGY arch/x86/boot/compressed/piggy.S
AS arch/x86/boot/compressed/piggy.o
LD arch/x86/boot/compressed/vmlinux
ZOFFSET arch/x86/boot/zoffset.h
OBJCOPY arch/x86/boot/vmlinux.bin
AS arch/x86/boot/header.o
LD arch/x86/boot/setup.elf
OBJCOPY arch/x86/boot/setup.bin
BUILD arch/x86/boot/bzImage
Kernel: arch/x86/boot/bzImage is ready (#1)
run-parts: executing /workspace/ci/hooks/20-kernel-doc
+ SRC_DIR=/workspace/kernel
+ cd /workspace/kernel
+ find drivers/gpu/drm/xe/ -name '*.[ch]' -not -path 'drivers/gpu/drm/xe/display/*'
+ xargs ./scripts/kernel-doc -Werror -none include/uapi/drm/xe_drm.h
All hooks done
^ permalink raw reply [flat|nested] 31+ messages in thread
* ✓ CI.checksparse: success for DPLL framework redesign (rev2)
2025-04-02 8:31 [PATCH 00/16] DPLL framework redesign Suraj Kandpal
` (20 preceding siblings ...)
2025-04-02 9:00 ` ✓ CI.Hooks: " Patchwork
@ 2025-04-02 9:02 ` Patchwork
2025-04-02 9:47 ` ✓ Xe.CI.BAT: " Patchwork
2025-04-02 11:01 ` ✗ Xe.CI.Full: failure " Patchwork
23 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2025-04-02 9:02 UTC (permalink / raw)
To: Suraj Kandpal; +Cc: intel-xe
== Series Details ==
Series: DPLL framework redesign (rev2)
URL : https://patchwork.freedesktop.org/series/145380/
State : success
== Summary ==
+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast f0fd77956987f035c79d08c812343a27a655a57b
Sparse version: 0.6.4 (Ubuntu: 0.6.4-4ubuntu3)
Fast mode used, each commit won't be checked separately.
Okay!
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 31+ messages in thread
* ✓ Xe.CI.BAT: success for DPLL framework redesign (rev2)
2025-04-02 8:31 [PATCH 00/16] DPLL framework redesign Suraj Kandpal
` (21 preceding siblings ...)
2025-04-02 9:02 ` ✓ CI.checksparse: " Patchwork
@ 2025-04-02 9:47 ` Patchwork
2025-04-02 11:01 ` ✗ Xe.CI.Full: failure " Patchwork
23 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2025-04-02 9:47 UTC (permalink / raw)
To: Suraj Kandpal; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 984 bytes --]
== Series Details ==
Series: DPLL framework redesign (rev2)
URL : https://patchwork.freedesktop.org/series/145380/
State : success
== Summary ==
CI Bug Log - changes from xe-2896-f0fd77956987f035c79d08c812343a27a655a57b_BAT -> xe-pw-145380v2_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (9 -> 8)
------------------------------
Missing (1): bat-adlp-vm
Changes
-------
No changes found
Build changes
-------------
* IGT: IGT_8297 -> IGT_8298
* Linux: xe-2896-f0fd77956987f035c79d08c812343a27a655a57b -> xe-pw-145380v2
IGT_8297: 0a27244ed1972af84c78d68523d5791e596349e7 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
IGT_8298: 8298
xe-2896-f0fd77956987f035c79d08c812343a27a655a57b: f0fd77956987f035c79d08c812343a27a655a57b
xe-pw-145380v2: 145380v2
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/index.html
[-- Attachment #2: Type: text/html, Size: 1546 bytes --]
^ permalink raw reply [flat|nested] 31+ messages in thread
* ✗ Xe.CI.Full: failure for DPLL framework redesign (rev2)
2025-04-02 8:31 [PATCH 00/16] DPLL framework redesign Suraj Kandpal
` (22 preceding siblings ...)
2025-04-02 9:47 ` ✓ Xe.CI.BAT: " Patchwork
@ 2025-04-02 11:01 ` Patchwork
23 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2025-04-02 11:01 UTC (permalink / raw)
To: Suraj Kandpal; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 84544 bytes --]
== Series Details ==
Series: DPLL framework redesign (rev2)
URL : https://patchwork.freedesktop.org/series/145380/
State : failure
== Summary ==
CI Bug Log - changes from xe-2896-f0fd77956987f035c79d08c812343a27a655a57b_FULL -> xe-pw-145380v2_FULL
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-145380v2_FULL absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-145380v2_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (4 -> 4)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-145380v2_FULL:
### IGT changes ###
#### Possible regressions ####
* igt@kms_pm_dc@dc5-dpms:
- shard-bmg: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-bmg-2/igt@kms_pm_dc@dc5-dpms.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-4/igt@kms_pm_dc@dc5-dpms.html
* igt@kms_vblank@query-forked-hang@pipe-a-edp-1:
- shard-lnl: [PASS][3] -> [ABORT][4] +1 other test abort
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-lnl-3/igt@kms_vblank@query-forked-hang@pipe-a-edp-1.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-lnl-5/igt@kms_vblank@query-forked-hang@pipe-a-edp-1.html
* igt@xe_exec_threads@threads-shared-vm-rebind-bindexecqueue:
- shard-dg2-set2: [PASS][5] -> [INCOMPLETE][6]
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-dg2-432/igt@xe_exec_threads@threads-shared-vm-rebind-bindexecqueue.html
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-433/igt@xe_exec_threads@threads-shared-vm-rebind-bindexecqueue.html
* igt@xe_pmu@all-fn-engine-activity-load (NEW):
- shard-dg2-set2: NOTRUN -> [SKIP][7] +2 other tests skip
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-466/igt@xe_pmu@all-fn-engine-activity-load.html
* igt@xe_pmu@fn-engine-activity-load (NEW):
- shard-bmg: NOTRUN -> [SKIP][8] +2 other tests skip
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-8/igt@xe_pmu@fn-engine-activity-load.html
* igt@xe_pmu@fn-engine-activity-sched-if-idle (NEW):
- shard-lnl: NOTRUN -> [SKIP][9] +2 other tests skip
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-lnl-5/igt@xe_pmu@fn-engine-activity-sched-if-idle.html
* igt@xe_sriov_scheduling@nonpreempt-engine-resets:
- shard-adlp: [PASS][10] -> [SKIP][11]
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-adlp-6/igt@xe_sriov_scheduling@nonpreempt-engine-resets.html
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-4/igt@xe_sriov_scheduling@nonpreempt-engine-resets.html
#### Warnings ####
* igt@xe_evict@evict-small-cm:
- shard-lnl: [SKIP][12] ([Intel XE#688]) -> [ABORT][13]
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-lnl-7/igt@xe_evict@evict-small-cm.html
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-lnl-6/igt@xe_evict@evict-small-cm.html
New tests
---------
New tests have been introduced between xe-2896-f0fd77956987f035c79d08c812343a27a655a57b_FULL and xe-pw-145380v2_FULL:
### New IGT tests (8) ###
* igt@xe_pmu@all-fn-engine-activity-load:
- Statuses : 3 skip(s)
- Exec time: [0.0] s
* igt@xe_pmu@fn-engine-activity-load:
- Statuses : 1 pass(s) 3 skip(s)
- Exec time: [0.0, 30.23] s
* igt@xe_pmu@fn-engine-activity-load@engine-drm_xe_engine_class_copy0:
- Statuses : 1 pass(s)
- Exec time: [6.05] s
* igt@xe_pmu@fn-engine-activity-load@engine-drm_xe_engine_class_render0:
- Statuses : 1 pass(s)
- Exec time: [6.04] s
* igt@xe_pmu@fn-engine-activity-load@engine-drm_xe_engine_class_video_decode0:
- Statuses : 1 pass(s)
- Exec time: [6.04] s
* igt@xe_pmu@fn-engine-activity-load@engine-drm_xe_engine_class_video_decode1:
- Statuses : 1 pass(s)
- Exec time: [6.04] s
* igt@xe_pmu@fn-engine-activity-load@engine-drm_xe_engine_class_video_enhance0:
- Statuses : 1 pass(s)
- Exec time: [6.04] s
* igt@xe_pmu@fn-engine-activity-sched-if-idle:
- Statuses : 3 skip(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in xe-pw-145380v2_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_async_flips@async-flip-with-page-flip-events:
- shard-adlp: [PASS][14] -> [DMESG-WARN][15] ([Intel XE#4543]) +8 other tests dmesg-warn
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-adlp-6/igt@kms_async_flips@async-flip-with-page-flip-events.html
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-6/igt@kms_async_flips@async-flip-with-page-flip-events.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-270:
- shard-lnl: NOTRUN -> [SKIP][16] ([Intel XE#1407])
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-lnl-8/igt@kms_big_fb@4-tiled-64bpp-rotate-270.html
* igt@kms_big_fb@linear-32bpp-rotate-270:
- shard-dg2-set2: NOTRUN -> [SKIP][17] ([Intel XE#316])
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-435/igt@kms_big_fb@linear-32bpp-rotate-270.html
* igt@kms_big_fb@linear-64bpp-rotate-270:
- shard-bmg: NOTRUN -> [SKIP][18] ([Intel XE#2327])
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-6/igt@kms_big_fb@linear-64bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-180:
- shard-adlp: NOTRUN -> [DMESG-FAIL][19] ([Intel XE#4543]) +1 other test dmesg-fail
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-1/igt@kms_big_fb@x-tiled-64bpp-rotate-180.html
* igt@kms_big_fb@y-tiled-16bpp-rotate-180:
- shard-bmg: NOTRUN -> [SKIP][20] ([Intel XE#1124]) +5 other tests skip
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-4/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html
* igt@kms_big_fb@y-tiled-32bpp-rotate-270:
- shard-adlp: NOTRUN -> [SKIP][21] ([Intel XE#316]) +2 other tests skip
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-4/igt@kms_big_fb@y-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180:
- shard-dg2-set2: NOTRUN -> [SKIP][22] ([Intel XE#1124])
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-466/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-adlp: [PASS][23] -> [DMESG-FAIL][24] ([Intel XE#4543]) +15 other tests dmesg-fail
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-adlp-1/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-1/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-270:
- shard-adlp: NOTRUN -> [SKIP][25] ([Intel XE#1124]) +8 other tests skip
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-2/igt@kms_big_fb@yf-tiled-16bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-270:
- shard-lnl: NOTRUN -> [SKIP][26] ([Intel XE#1124])
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-lnl-8/igt@kms_big_fb@yf-tiled-64bpp-rotate-270.html
* igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p:
- shard-dg2-set2: [PASS][27] -> [SKIP][28] ([Intel XE#2191])
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-dg2-466/igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p.html
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-464/igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p.html
* igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p:
- shard-adlp: NOTRUN -> [SKIP][29] ([Intel XE#2191])
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-9/igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p.html
* igt@kms_bw@linear-tiling-2-displays-2160x1440p:
- shard-adlp: NOTRUN -> [SKIP][30] ([Intel XE#367]) +1 other test skip
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-4/igt@kms_bw@linear-tiling-2-displays-2160x1440p.html
* igt@kms_bw@linear-tiling-3-displays-3840x2160p:
- shard-bmg: NOTRUN -> [SKIP][31] ([Intel XE#367])
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-4/igt@kms_bw@linear-tiling-3-displays-3840x2160p.html
* igt@kms_ccs@bad-aux-stride-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-1:
- shard-adlp: NOTRUN -> [SKIP][32] ([Intel XE#455] / [Intel XE#787]) +27 other tests skip
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-1/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc:
- shard-bmg: NOTRUN -> [SKIP][33] ([Intel XE#2887]) +5 other tests skip
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-5/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc.html
* igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-mc-ccs:
- shard-lnl: NOTRUN -> [SKIP][34] ([Intel XE#2887]) +3 other tests skip
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-lnl-6/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-mc-ccs.html
* igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs@pipe-c-hdmi-a-1:
- shard-adlp: NOTRUN -> [SKIP][35] ([Intel XE#787]) +41 other tests skip
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-4/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs@pipe-c-hdmi-a-1.html
* igt@kms_ccs@crc-primary-basic-yf-tiled-ccs@pipe-d-dp-2:
- shard-dg2-set2: NOTRUN -> [SKIP][36] ([Intel XE#455] / [Intel XE#787]) +35 other tests skip
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-432/igt@kms_ccs@crc-primary-basic-yf-tiled-ccs@pipe-d-dp-2.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs:
- shard-adlp: NOTRUN -> [SKIP][37] ([Intel XE#2907]) +2 other tests skip
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-8/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs@pipe-b-dp-2:
- shard-bmg: NOTRUN -> [SKIP][38] ([Intel XE#2652] / [Intel XE#787]) +3 other tests skip
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-6/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs@pipe-b-dp-2.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-6:
- shard-dg2-set2: NOTRUN -> [SKIP][39] ([Intel XE#787]) +201 other tests skip
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-435/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-6.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
- shard-dg2-set2: [PASS][40] -> [INCOMPLETE][41] ([Intel XE#2705] / [Intel XE#4212] / [Intel XE#4345])
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-dp-4:
- shard-dg2-set2: NOTRUN -> [INCOMPLETE][42] ([Intel XE#2705] / [Intel XE#4212])
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-dp-4.html
* igt@kms_cdclk@mode-transition-all-outputs:
- shard-adlp: NOTRUN -> [SKIP][43] ([Intel XE#4418])
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-4/igt@kms_cdclk@mode-transition-all-outputs.html
* igt@kms_cdclk@mode-transition@pipe-d-dp-4:
- shard-dg2-set2: NOTRUN -> [SKIP][44] ([Intel XE#4417]) +3 other tests skip
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-466/igt@kms_cdclk@mode-transition@pipe-d-dp-4.html
* igt@kms_cdclk@plane-scaling@pipe-b-dp-2:
- shard-dg2-set2: NOTRUN -> [SKIP][45] ([Intel XE#4416]) +3 other tests skip
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-432/igt@kms_cdclk@plane-scaling@pipe-b-dp-2.html
* igt@kms_chamelium_color@ctm-max:
- shard-dg2-set2: NOTRUN -> [SKIP][46] ([Intel XE#306])
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-466/igt@kms_chamelium_color@ctm-max.html
* igt@kms_chamelium_color@ctm-red-to-blue:
- shard-adlp: NOTRUN -> [SKIP][47] ([Intel XE#306])
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-1/igt@kms_chamelium_color@ctm-red-to-blue.html
* igt@kms_chamelium_frames@dp-crc-single:
- shard-bmg: NOTRUN -> [SKIP][48] ([Intel XE#2252]) +3 other tests skip
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-8/igt@kms_chamelium_frames@dp-crc-single.html
* igt@kms_chamelium_hpd@hdmi-hpd-storm:
- shard-dg2-set2: NOTRUN -> [SKIP][49] ([Intel XE#373]) +2 other tests skip
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-432/igt@kms_chamelium_hpd@hdmi-hpd-storm.html
* igt@kms_chamelium_hpd@hdmi-hpd-storm-disable:
- shard-adlp: NOTRUN -> [SKIP][50] ([Intel XE#373]) +5 other tests skip
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-2/igt@kms_chamelium_hpd@hdmi-hpd-storm-disable.html
* igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode:
- shard-lnl: NOTRUN -> [SKIP][51] ([Intel XE#373]) +4 other tests skip
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-lnl-3/igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode.html
* igt@kms_content_protection@dp-mst-type-1:
- shard-bmg: NOTRUN -> [SKIP][52] ([Intel XE#2390])
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-1/igt@kms_content_protection@dp-mst-type-1.html
* igt@kms_content_protection@lic-type-0@pipe-a-dp-2:
- shard-bmg: NOTRUN -> [FAIL][53] ([Intel XE#1178])
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-5/igt@kms_content_protection@lic-type-0@pipe-a-dp-2.html
* igt@kms_content_protection@srm@pipe-a-dp-4:
- shard-dg2-set2: NOTRUN -> [FAIL][54] ([Intel XE#1178]) +1 other test fail
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-463/igt@kms_content_protection@srm@pipe-a-dp-4.html
* igt@kms_content_protection@uevent@pipe-a-dp-2:
- shard-bmg: NOTRUN -> [FAIL][55] ([Intel XE#1188])
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-2/igt@kms_content_protection@uevent@pipe-a-dp-2.html
* igt@kms_content_protection@uevent@pipe-a-dp-4:
- shard-dg2-set2: NOTRUN -> [FAIL][56] ([Intel XE#1188])
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-466/igt@kms_content_protection@uevent@pipe-a-dp-4.html
* igt@kms_cursor_crc@cursor-random-128x42:
- shard-lnl: NOTRUN -> [SKIP][57] ([Intel XE#1424]) +1 other test skip
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-lnl-7/igt@kms_cursor_crc@cursor-random-128x42.html
* igt@kms_cursor_crc@cursor-random-64x21:
- shard-bmg: NOTRUN -> [SKIP][58] ([Intel XE#2320])
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-8/igt@kms_cursor_crc@cursor-random-64x21.html
* igt@kms_cursor_legacy@cursora-vs-flipb-toggle:
- shard-lnl: NOTRUN -> [SKIP][59] ([Intel XE#309])
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-lnl-7/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-atomic:
- shard-adlp: NOTRUN -> [SKIP][60] ([Intel XE#309]) +2 other tests skip
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-8/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
- shard-adlp: NOTRUN -> [SKIP][61] ([Intel XE#323])
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-1/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
* igt@kms_display_modes@extended-mode-basic:
- shard-dg2-set2: [PASS][62] -> [SKIP][63] ([Intel XE#4302])
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-dg2-432/igt@kms_display_modes@extended-mode-basic.html
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-464/igt@kms_display_modes@extended-mode-basic.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2:
- shard-dg2-set2: NOTRUN -> [SKIP][64] ([Intel XE#4494])
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-432/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2.html
* igt@kms_dp_link_training@non-uhbr-sst:
- shard-bmg: [PASS][65] -> [SKIP][66] ([Intel XE#4354])
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-bmg-7/igt@kms_dp_link_training@non-uhbr-sst.html
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-4/igt@kms_dp_link_training@non-uhbr-sst.html
* igt@kms_dsc@dsc-fractional-bpp:
- shard-bmg: NOTRUN -> [SKIP][67] ([Intel XE#2244]) +1 other test skip
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-2/igt@kms_dsc@dsc-fractional-bpp.html
* igt@kms_dsc@dsc-with-bpc:
- shard-dg2-set2: NOTRUN -> [SKIP][68] ([Intel XE#455]) +3 other tests skip
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-463/igt@kms_dsc@dsc-with-bpc.html
* igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-different-formats:
- shard-dg2-set2: NOTRUN -> [SKIP][69] ([Intel XE#4422])
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-433/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-different-formats.html
* igt@kms_feature_discovery@display-2x:
- shard-bmg: [PASS][70] -> [SKIP][71] ([Intel XE#2373])
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-bmg-7/igt@kms_feature_discovery@display-2x.html
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-4/igt@kms_feature_discovery@display-2x.html
* igt@kms_feature_discovery@display-4x:
- shard-adlp: NOTRUN -> [SKIP][72] ([Intel XE#1138])
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-1/igt@kms_feature_discovery@display-4x.html
* igt@kms_feature_discovery@psr2:
- shard-adlp: NOTRUN -> [SKIP][73] ([Intel XE#1135])
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-4/igt@kms_feature_discovery@psr2.html
* igt@kms_flip@2x-busy-flip:
- shard-bmg: [PASS][74] -> [SKIP][75] ([Intel XE#2316])
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-bmg-1/igt@kms_flip@2x-busy-flip.html
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-4/igt@kms_flip@2x-busy-flip.html
* igt@kms_flip@2x-dpms-vs-vblank-race-interruptible:
- shard-dg2-set2: [PASS][76] -> [SKIP][77] ([Intel XE#310]) +4 other tests skip
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-dg2-432/igt@kms_flip@2x-dpms-vs-vblank-race-interruptible.html
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-464/igt@kms_flip@2x-dpms-vs-vblank-race-interruptible.html
* igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible:
- shard-adlp: NOTRUN -> [SKIP][78] ([Intel XE#310]) +6 other tests skip
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-1/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible.html
* igt@kms_flip@2x-flip-vs-expired-vblank@ab-dp2-hdmi-a3:
- shard-bmg: [PASS][79] -> [FAIL][80] ([Intel XE#3321]) +5 other tests fail
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-bmg-1/igt@kms_flip@2x-flip-vs-expired-vblank@ab-dp2-hdmi-a3.html
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-5/igt@kms_flip@2x-flip-vs-expired-vblank@ab-dp2-hdmi-a3.html
* igt@kms_flip@2x-flip-vs-suspend-interruptible:
- shard-lnl: NOTRUN -> [SKIP][81] ([Intel XE#1421])
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-lnl-1/igt@kms_flip@2x-flip-vs-suspend-interruptible.html
* igt@kms_flip@2x-wf_vblank-ts-check:
- shard-bmg: NOTRUN -> [SKIP][82] ([Intel XE#2316]) +1 other test skip
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-4/igt@kms_flip@2x-wf_vblank-ts-check.html
* igt@kms_flip@flip-vs-expired-vblank@a-dp4:
- shard-dg2-set2: [PASS][83] -> [FAIL][84] ([Intel XE#301] / [Intel XE#3321])
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-dg2-463/igt@kms_flip@flip-vs-expired-vblank@a-dp4.html
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-463/igt@kms_flip@flip-vs-expired-vblank@a-dp4.html
* igt@kms_flip@flip-vs-suspend:
- shard-adlp: NOTRUN -> [DMESG-WARN][85] ([Intel XE#2953] / [Intel XE#4173]) +1 other test dmesg-warn
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-9/igt@kms_flip@flip-vs-suspend.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-adlp: [PASS][86] -> [DMESG-WARN][87] ([Intel XE#2953] / [Intel XE#4173]) +2 other tests dmesg-warn
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-adlp-6/igt@kms_flip@flip-vs-suspend-interruptible.html
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-4/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_flip@flip-vs-suspend@a-hdmi-a1:
- shard-adlp: NOTRUN -> [DMESG-WARN][88] ([Intel XE#4173])
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-9/igt@kms_flip@flip-vs-suspend@a-hdmi-a1.html
* igt@kms_flip@plain-flip-fb-recreate:
- shard-bmg: [PASS][89] -> [FAIL][90] ([Intel XE#2882]) +2 other tests fail
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-bmg-3/igt@kms_flip@plain-flip-fb-recreate.html
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-2/igt@kms_flip@plain-flip-fb-recreate.html
* igt@kms_flip@wf_vblank-ts-check:
- shard-dg2-set2: [PASS][91] -> [FAIL][92] ([Intel XE#886])
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-dg2-466/igt@kms_flip@wf_vblank-ts-check.html
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-432/igt@kms_flip@wf_vblank-ts-check.html
* igt@kms_flip@wf_vblank-ts-check@a-edp1:
- shard-lnl: [PASS][93] -> [FAIL][94] ([Intel XE#886]) +1 other test fail
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-lnl-5/igt@kms_flip@wf_vblank-ts-check@a-edp1.html
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-lnl-6/igt@kms_flip@wf_vblank-ts-check@a-edp1.html
* igt@kms_flip@wf_vblank-ts-check@a-hdmi-a2:
- shard-dg2-set2: NOTRUN -> [FAIL][95] ([Intel XE#886]) +1 other test fail
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-432/igt@kms_flip@wf_vblank-ts-check@a-hdmi-a2.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode:
- shard-bmg: NOTRUN -> [SKIP][96] ([Intel XE#2293]) +2 other tests skip
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-1/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling:
- shard-adlp: NOTRUN -> [SKIP][97] ([Intel XE#455]) +24 other tests skip
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-8/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling:
- shard-bmg: NOTRUN -> [SKIP][98] ([Intel XE#2293] / [Intel XE#2380]) +2 other tests skip
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-1/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling.html
* igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-x-to-y:
- shard-adlp: [PASS][99] -> [FAIL][100] ([Intel XE#1874])
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-adlp-8/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-x-to-y.html
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-8/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-x-to-y.html
* igt@kms_force_connector_basic@force-edid:
- shard-lnl: NOTRUN -> [SKIP][101] ([Intel XE#352])
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-lnl-1/igt@kms_force_connector_basic@force-edid.html
* igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-blt:
- shard-adlp: NOTRUN -> [SKIP][102] ([Intel XE#651]) +10 other tests skip
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-2/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-move:
- shard-dg2-set2: NOTRUN -> [SKIP][103] ([Intel XE#651]) +4 other tests skip
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-463/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-move.html
* igt@kms_frontbuffer_tracking@drrs-2p-primscrn-shrfb-plflip-blt:
- shard-dg2-set2: NOTRUN -> [SKIP][104] ([Intel XE#656])
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-464/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-fullscreen:
- shard-bmg: NOTRUN -> [SKIP][105] ([Intel XE#2312])
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-fullscreen.html
* igt@kms_frontbuffer_tracking@drrs-indfb-scaledprimary:
- shard-lnl: NOTRUN -> [SKIP][106] ([Intel XE#651]) +4 other tests skip
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-lnl-3/igt@kms_frontbuffer_tracking@drrs-indfb-scaledprimary.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff:
- shard-bmg: NOTRUN -> [SKIP][107] ([Intel XE#4141]) +6 other tests skip
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-onoff:
- shard-dg2-set2: [PASS][108] -> [SKIP][109] ([Intel XE#656]) +5 other tests skip
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-dg2-433/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-onoff.html
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-464/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbc-tiling-4:
- shard-adlp: NOTRUN -> [SKIP][110] ([Intel XE#1151])
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-6/igt@kms_frontbuffer_tracking@fbc-tiling-4.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-move:
- shard-adlp: NOTRUN -> [SKIP][111] ([Intel XE#656]) +30 other tests skip
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-1/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-move.html
* igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-render:
- shard-bmg: NOTRUN -> [SKIP][112] ([Intel XE#2311]) +9 other tests skip
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-wc:
- shard-lnl: NOTRUN -> [SKIP][113] ([Intel XE#656]) +7 other tests skip
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-lnl-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt:
- shard-adlp: NOTRUN -> [SKIP][114] ([Intel XE#653]) +11 other tests skip
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc:
- shard-bmg: NOTRUN -> [SKIP][115] ([Intel XE#2313]) +11 other tests skip
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-slowdraw:
- shard-dg2-set2: NOTRUN -> [SKIP][116] ([Intel XE#653]) +6 other tests skip
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-463/igt@kms_frontbuffer_tracking@psr-slowdraw.html
* igt@kms_hdr@static-toggle:
- shard-lnl: NOTRUN -> [SKIP][117] ([Intel XE#1503])
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-lnl-1/igt@kms_hdr@static-toggle.html
* igt@kms_joiner@basic-force-ultra-joiner:
- shard-adlp: NOTRUN -> [SKIP][118] ([Intel XE#2925])
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-2/igt@kms_joiner@basic-force-ultra-joiner.html
* igt@kms_joiner@invalid-modeset-force-ultra-joiner:
- shard-lnl: NOTRUN -> [SKIP][119] ([Intel XE#2934])
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-lnl-6/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html
* igt@kms_joiner@invalid-modeset-ultra-joiner:
- shard-bmg: NOTRUN -> [SKIP][120] ([Intel XE#2927])
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-8/igt@kms_joiner@invalid-modeset-ultra-joiner.html
* igt@kms_plane_scaling@2x-scaler-multi-pipe:
- shard-dg2-set2: [PASS][121] -> [SKIP][122] ([Intel XE#309]) +2 other tests skip
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-dg2-463/igt@kms_plane_scaling@2x-scaler-multi-pipe.html
[122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-464/igt@kms_plane_scaling@2x-scaler-multi-pipe.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format:
- shard-bmg: NOTRUN -> [SKIP][123] ([Intel XE#2763]) +9 other tests skip
[123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-4/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format.html
* igt@kms_plane_scaling@plane-downscale-factor-0-5-with-modifiers:
- shard-lnl: NOTRUN -> [SKIP][124] ([Intel XE#2763]) +3 other tests skip
[124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-lnl-5/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-modifiers.html
* igt@kms_pm_backlight@basic-brightness:
- shard-bmg: NOTRUN -> [SKIP][125] ([Intel XE#870])
[125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-4/igt@kms_pm_backlight@basic-brightness.html
* igt@kms_pm_backlight@brightness-with-dpms:
- shard-adlp: NOTRUN -> [SKIP][126] ([Intel XE#2938])
[126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-8/igt@kms_pm_backlight@brightness-with-dpms.html
* igt@kms_pm_backlight@fade-with-dpms:
- shard-adlp: NOTRUN -> [SKIP][127] ([Intel XE#870])
[127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-8/igt@kms_pm_backlight@fade-with-dpms.html
- shard-dg2-set2: NOTRUN -> [SKIP][128] ([Intel XE#870]) +1 other test skip
[128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-464/igt@kms_pm_backlight@fade-with-dpms.html
* igt@kms_pm_dc@dc3co-vpb-simulation:
- shard-bmg: NOTRUN -> [SKIP][129] ([Intel XE#2391])
[129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-4/igt@kms_pm_dc@dc3co-vpb-simulation.html
* igt@kms_pm_dc@deep-pkgc:
- shard-dg2-set2: NOTRUN -> [SKIP][130] ([Intel XE#908])
[130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-435/igt@kms_pm_dc@deep-pkgc.html
* igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-lnl: NOTRUN -> [SKIP][131] ([Intel XE#1439] / [Intel XE#836])
[131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-lnl-7/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
* igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf:
- shard-adlp: NOTRUN -> [SKIP][132] ([Intel XE#1489]) +4 other tests skip
[132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-2/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf.html
* igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area:
- shard-bmg: NOTRUN -> [SKIP][133] ([Intel XE#1489]) +2 other tests skip
[133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-4/igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area.html
* igt@kms_psr2_sf@pr-overlay-plane-move-continuous-exceed-fully-sf:
- shard-lnl: NOTRUN -> [SKIP][134] ([Intel XE#2893]) +1 other test skip
[134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-lnl-7/igt@kms_psr2_sf@pr-overlay-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr@fbc-psr2-cursor-blt:
- shard-adlp: NOTRUN -> [SKIP][135] ([Intel XE#2850] / [Intel XE#929]) +12 other tests skip
[135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-2/igt@kms_psr@fbc-psr2-cursor-blt.html
* igt@kms_psr@fbc-psr2-dpms:
- shard-dg2-set2: NOTRUN -> [SKIP][136] ([Intel XE#2850] / [Intel XE#929]) +1 other test skip
[136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-432/igt@kms_psr@fbc-psr2-dpms.html
* igt@kms_psr@pr-no-drrs:
- shard-lnl: NOTRUN -> [SKIP][137] ([Intel XE#1406])
[137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-lnl-7/igt@kms_psr@pr-no-drrs.html
* igt@kms_psr@psr2-sprite-blt:
- shard-bmg: NOTRUN -> [SKIP][138] ([Intel XE#2234] / [Intel XE#2850]) +5 other tests skip
[138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-7/igt@kms_psr@psr2-sprite-blt.html
* igt@kms_rotation_crc@bad-tiling:
- shard-dg2-set2: NOTRUN -> [SKIP][139] ([Intel XE#3414])
[139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-464/igt@kms_rotation_crc@bad-tiling.html
* igt@kms_rotation_crc@primary-rotation-90:
- shard-adlp: NOTRUN -> [SKIP][140] ([Intel XE#3414]) +1 other test skip
[140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-1/igt@kms_rotation_crc@primary-rotation-90.html
* igt@kms_setmode@clone-exclusive-crtc:
- shard-bmg: [PASS][141] -> [SKIP][142] ([Intel XE#1435])
[141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-bmg-7/igt@kms_setmode@clone-exclusive-crtc.html
[142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-4/igt@kms_setmode@clone-exclusive-crtc.html
* igt@kms_setmode@invalid-clone-exclusive-crtc:
- shard-bmg: NOTRUN -> [SKIP][143] ([Intel XE#1435])
[143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-5/igt@kms_setmode@invalid-clone-exclusive-crtc.html
* igt@kms_tv_load_detect@load-detect:
- shard-adlp: NOTRUN -> [SKIP][144] ([Intel XE#330])
[144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-2/igt@kms_tv_load_detect@load-detect.html
* igt@kms_vrr@cmrr@pipe-a-edp-1:
- shard-lnl: [PASS][145] -> [FAIL][146] ([Intel XE#4459]) +1 other test fail
[145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-lnl-4/igt@kms_vrr@cmrr@pipe-a-edp-1.html
[146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-lnl-7/igt@kms_vrr@cmrr@pipe-a-edp-1.html
* igt@kms_vrr@seamless-rr-switch-drrs:
- shard-bmg: NOTRUN -> [SKIP][147] ([Intel XE#1499])
[147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-8/igt@kms_vrr@seamless-rr-switch-drrs.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-adlp: NOTRUN -> [SKIP][148] ([Intel XE#756])
[148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-4/igt@kms_writeback@writeback-invalid-parameters.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-bmg: NOTRUN -> [SKIP][149] ([Intel XE#756])
[149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-6/igt@kms_writeback@writeback-pixel-formats.html
* igt@xe_ccs@block-multicopy-inplace:
- shard-adlp: NOTRUN -> [SKIP][150] ([Intel XE#455] / [Intel XE#488])
[150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-4/igt@xe_ccs@block-multicopy-inplace.html
* igt@xe_ccs@large-ctrl-surf-copy:
- shard-adlp: NOTRUN -> [SKIP][151] ([Intel XE#3576])
[151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-6/igt@xe_ccs@large-ctrl-surf-copy.html
* igt@xe_compute_preempt@compute-preempt-many:
- shard-bmg: [PASS][152] -> [FAIL][153] ([Intel XE#4278]) +1 other test fail
[152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-bmg-6/igt@xe_compute_preempt@compute-preempt-many.html
[153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-1/igt@xe_compute_preempt@compute-preempt-many.html
* igt@xe_copy_basic@mem-set-linear-0x3fff:
- shard-adlp: NOTRUN -> [SKIP][154] ([Intel XE#1126])
[154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-2/igt@xe_copy_basic@mem-set-linear-0x3fff.html
- shard-dg2-set2: NOTRUN -> [SKIP][155] ([Intel XE#1126])
[155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-432/igt@xe_copy_basic@mem-set-linear-0x3fff.html
* igt@xe_eudebug@basic-exec-queues:
- shard-bmg: NOTRUN -> [SKIP][156] ([Intel XE#2905]) +2 other tests skip
[156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-2/igt@xe_eudebug@basic-exec-queues.html
* igt@xe_eudebug@basic-read-event:
- shard-adlp: NOTRUN -> [SKIP][157] ([Intel XE#2905]) +9 other tests skip
[157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-2/igt@xe_eudebug@basic-read-event.html
* igt@xe_eudebug@discovery-race-sigint:
- shard-lnl: NOTRUN -> [SKIP][158] ([Intel XE#2905] / [Intel XE#4259])
[158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-lnl-8/igt@xe_eudebug@discovery-race-sigint.html
* igt@xe_eudebug_online@set-breakpoint-sigint-debugger:
- shard-adlp: NOTRUN -> [SKIP][159] ([Intel XE#4577])
[159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-8/igt@xe_eudebug_online@set-breakpoint-sigint-debugger.html
- shard-lnl: NOTRUN -> [SKIP][160] ([Intel XE#4577])
[160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-lnl-5/igt@xe_eudebug_online@set-breakpoint-sigint-debugger.html
* igt@xe_eudebug_online@single-step-one:
- shard-lnl: NOTRUN -> [SKIP][161] ([Intel XE#2905]) +2 other tests skip
[161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-lnl-7/igt@xe_eudebug_online@single-step-one.html
* igt@xe_eudebug_online@writes-caching-vram-bb-vram-target-vram:
- shard-dg2-set2: NOTRUN -> [SKIP][162] ([Intel XE#2905])
[162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-433/igt@xe_eudebug_online@writes-caching-vram-bb-vram-target-vram.html
* igt@xe_eudebug_sriov@deny-sriov:
- shard-adlp: NOTRUN -> [SKIP][163] ([Intel XE#4519])
[163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-9/igt@xe_eudebug_sriov@deny-sriov.html
* igt@xe_evict@evict-large-multi-vm:
- shard-adlp: NOTRUN -> [SKIP][164] ([Intel XE#261] / [Intel XE#688]) +1 other test skip
[164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-1/igt@xe_evict@evict-large-multi-vm.html
* igt@xe_exec_basic@multigpu-many-execqueues-many-vm-basic-defer-bind:
- shard-dg2-set2: [PASS][165] -> [SKIP][166] ([Intel XE#1392]) +6 other tests skip
[165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-dg2-433/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-basic-defer-bind.html
[166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-432/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-basic-defer-bind.html
* igt@xe_exec_basic@multigpu-no-exec-userptr-invalidate-race:
- shard-lnl: NOTRUN -> [SKIP][167] ([Intel XE#1392]) +3 other tests skip
[167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-lnl-8/igt@xe_exec_basic@multigpu-no-exec-userptr-invalidate-race.html
* igt@xe_exec_basic@multigpu-once-basic-defer-bind:
- shard-bmg: NOTRUN -> [SKIP][168] ([Intel XE#2322]) +2 other tests skip
[168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-1/igt@xe_exec_basic@multigpu-once-basic-defer-bind.html
* igt@xe_exec_basic@multigpu-once-bindexecqueue-rebind:
- shard-adlp: NOTRUN -> [SKIP][169] ([Intel XE#1392]) +9 other tests skip
[169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-4/igt@xe_exec_basic@multigpu-once-bindexecqueue-rebind.html
- shard-dg2-set2: NOTRUN -> [SKIP][170] ([Intel XE#1392])
[170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-432/igt@xe_exec_basic@multigpu-once-bindexecqueue-rebind.html
* igt@xe_exec_fault_mode@once-bindexecqueue-rebind:
- shard-dg2-set2: NOTRUN -> [SKIP][171] ([Intel XE#288]) +3 other tests skip
[171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-432/igt@xe_exec_fault_mode@once-bindexecqueue-rebind.html
* igt@xe_exec_fault_mode@once-bindexecqueue-userptr:
- shard-adlp: NOTRUN -> [SKIP][172] ([Intel XE#288]) +22 other tests skip
[172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-6/igt@xe_exec_fault_mode@once-bindexecqueue-userptr.html
* igt@xe_exec_mix_modes@exec-spinner-interrupted-dma-fence:
- shard-adlp: NOTRUN -> [SKIP][173] ([Intel XE#2360])
[173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-1/igt@xe_exec_mix_modes@exec-spinner-interrupted-dma-fence.html
* igt@xe_exec_threads@threads-hang-fd-userptr-invalidate:
- shard-dg2-set2: [PASS][174] -> [DMESG-WARN][175] ([Intel XE#3876])
[174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-dg2-433/igt@xe_exec_threads@threads-hang-fd-userptr-invalidate.html
[175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-433/igt@xe_exec_threads@threads-hang-fd-userptr-invalidate.html
* igt@xe_live_ktest@xe_bo:
- shard-adlp: NOTRUN -> [SKIP][176] ([Intel XE#2229] / [Intel XE#455]) +1 other test skip
[176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-6/igt@xe_live_ktest@xe_bo.html
* igt@xe_live_ktest@xe_bo@xe_ccs_migrate_kunit:
- shard-adlp: NOTRUN -> [SKIP][177] ([Intel XE#2229])
[177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-6/igt@xe_live_ktest@xe_bo@xe_ccs_migrate_kunit.html
* igt@xe_mmap@pci-membarrier-bad-object:
- shard-lnl: NOTRUN -> [SKIP][178] ([Intel XE#4045])
[178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-lnl-8/igt@xe_mmap@pci-membarrier-bad-object.html
* igt@xe_mmap@vram:
- shard-adlp: NOTRUN -> [SKIP][179] ([Intel XE#1008])
[179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-4/igt@xe_mmap@vram.html
* igt@xe_noexec_ping_pong:
- shard-lnl: NOTRUN -> [SKIP][180] ([Intel XE#379])
[180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-lnl-8/igt@xe_noexec_ping_pong.html
* igt@xe_oa@create-destroy-userspace-config:
- shard-adlp: NOTRUN -> [SKIP][181] ([Intel XE#2541] / [Intel XE#3573]) +6 other tests skip
[181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-9/igt@xe_oa@create-destroy-userspace-config.html
* igt@xe_oa@oa-tlb-invalidate:
- shard-dg2-set2: NOTRUN -> [SKIP][182] ([Intel XE#2541] / [Intel XE#3573]) +1 other test skip
[182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-433/igt@xe_oa@oa-tlb-invalidate.html
* igt@xe_oa@syncs-userptr-wait-cfg:
- shard-dg2-set2: NOTRUN -> [SKIP][183] ([Intel XE#2541] / [Intel XE#3573] / [Intel XE#4501])
[183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-435/igt@xe_oa@syncs-userptr-wait-cfg.html
- shard-adlp: NOTRUN -> [SKIP][184] ([Intel XE#2541] / [Intel XE#3573] / [Intel XE#4501])
[184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-1/igt@xe_oa@syncs-userptr-wait-cfg.html
* igt@xe_peer2peer@read@read-gpua-vram01-gpub-system-p2p:
- shard-dg2-set2: NOTRUN -> [FAIL][185] ([Intel XE#1173])
[185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-433/igt@xe_peer2peer@read@read-gpua-vram01-gpub-system-p2p.html
* igt@xe_pm@d3cold-basic:
- shard-adlp: NOTRUN -> [SKIP][186] ([Intel XE#2284] / [Intel XE#366])
[186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-1/igt@xe_pm@d3cold-basic.html
* igt@xe_pm@d3cold-mmap-system:
- shard-dg2-set2: NOTRUN -> [SKIP][187] ([Intel XE#2284] / [Intel XE#366])
[187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-435/igt@xe_pm@d3cold-mmap-system.html
* igt@xe_pm@d3hot-mmap-vram:
- shard-adlp: NOTRUN -> [SKIP][188] ([Intel XE#1948])
[188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-4/igt@xe_pm@d3hot-mmap-vram.html
- shard-lnl: NOTRUN -> [SKIP][189] ([Intel XE#1948])
[189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-lnl-4/igt@xe_pm@d3hot-mmap-vram.html
* igt@xe_pm@s2idle-vm-bind-userptr:
- shard-adlp: [PASS][190] -> [DMESG-WARN][191] ([Intel XE#4173]) +2 other tests dmesg-warn
[190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-adlp-8/igt@xe_pm@s2idle-vm-bind-userptr.html
[191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-2/igt@xe_pm@s2idle-vm-bind-userptr.html
* igt@xe_pm@s4-vm-bind-unbind-all:
- shard-lnl: [PASS][192] -> [ABORT][193] ([Intel XE#1794])
[192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-lnl-6/igt@xe_pm@s4-vm-bind-unbind-all.html
[193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-lnl-2/igt@xe_pm@s4-vm-bind-unbind-all.html
* igt@xe_pm@s4-vm-bind-userptr:
- shard-adlp: [PASS][194] -> [ABORT][195] ([Intel XE#1794])
[194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-adlp-8/igt@xe_pm@s4-vm-bind-userptr.html
[195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-9/igt@xe_pm@s4-vm-bind-userptr.html
* igt@xe_query@multigpu-query-invalid-cs-cycles:
- shard-bmg: NOTRUN -> [SKIP][196] ([Intel XE#944]) +1 other test skip
[196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-1/igt@xe_query@multigpu-query-invalid-cs-cycles.html
* igt@xe_query@multigpu-query-invalid-extension:
- shard-adlp: NOTRUN -> [SKIP][197] ([Intel XE#944]) +1 other test skip
[197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-4/igt@xe_query@multigpu-query-invalid-extension.html
- shard-dg2-set2: NOTRUN -> [SKIP][198] ([Intel XE#944])
[198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-433/igt@xe_query@multigpu-query-invalid-extension.html
* igt@xe_query@multigpu-query-topology-l3-bank-mask:
- shard-lnl: NOTRUN -> [SKIP][199] ([Intel XE#944])
[199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-lnl-1/igt@xe_query@multigpu-query-topology-l3-bank-mask.html
* igt@xe_sriov_auto_provisioning@exclusive-ranges:
- shard-lnl: NOTRUN -> [SKIP][200] ([Intel XE#4130])
[200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-lnl-5/igt@xe_sriov_auto_provisioning@exclusive-ranges.html
* igt@xe_sriov_flr@flr-each-isolation:
- shard-bmg: NOTRUN -> [SKIP][201] ([Intel XE#3342])
[201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-3/igt@xe_sriov_flr@flr-each-isolation.html
#### Possible fixes ####
* {igt@intel_sysfs_debugfs@xe-debugfs-read-all-entries-display-off}:
- shard-lnl: [ABORT][202] ([Intel XE#4624]) -> [PASS][203] +1 other test pass
[202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-lnl-1/igt@intel_sysfs_debugfs@xe-debugfs-read-all-entries-display-off.html
[203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-lnl-5/igt@intel_sysfs_debugfs@xe-debugfs-read-all-entries-display-off.html
* igt@kms_async_flips@async-flip-with-page-flip-events-atomic:
- shard-lnl: [FAIL][204] ([Intel XE#3719] / [Intel XE#911]) -> [PASS][205] +3 other tests pass
[204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-lnl-8/igt@kms_async_flips@async-flip-with-page-flip-events-atomic.html
[205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-lnl-1/igt@kms_async_flips@async-flip-with-page-flip-events-atomic.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-edp-1-linear:
- shard-lnl: [FAIL][206] ([Intel XE#911]) -> [PASS][207] +3 other tests pass
[206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-lnl-1/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-edp-1-linear.html
[207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-lnl-2/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-edp-1-linear.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-adlp: [DMESG-FAIL][208] ([Intel XE#4543]) -> [PASS][209] +6 other tests pass
[208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-adlp-2/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
[209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-2/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p:
- shard-dg2-set2: [SKIP][210] ([Intel XE#2191]) -> [PASS][211]
[210]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-dg2-464/igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p.html
[211]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-433/igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p.html
* igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p:
- shard-bmg: [SKIP][212] ([Intel XE#2314] / [Intel XE#2894]) -> [PASS][213]
[212]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-bmg-4/igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p.html
[213]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-1/igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p.html
* igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy:
- shard-dg2-set2: [SKIP][214] ([Intel XE#309]) -> [PASS][215] +5 other tests pass
[214]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-dg2-464/igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy.html
[215]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-433/igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size:
- shard-bmg: [SKIP][216] ([Intel XE#2291]) -> [PASS][217] +6 other tests pass
[216]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-bmg-4/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html
[217]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-1/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html
* igt@kms_dp_aux_dev:
- shard-bmg: [SKIP][218] ([Intel XE#3009]) -> [PASS][219]
[218]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-bmg-4/igt@kms_dp_aux_dev.html
[219]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-8/igt@kms_dp_aux_dev.html
* igt@kms_dp_link_training@non-uhbr-sst:
- shard-dg2-set2: [SKIP][220] ([Intel XE#4354]) -> [PASS][221]
[220]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-dg2-464/igt@kms_dp_link_training@non-uhbr-sst.html
[221]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-432/igt@kms_dp_link_training@non-uhbr-sst.html
* igt@kms_flip@2x-absolute-wf_vblank:
- shard-bmg: [SKIP][222] ([Intel XE#2316]) -> [PASS][223] +3 other tests pass
[222]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-bmg-4/igt@kms_flip@2x-absolute-wf_vblank.html
[223]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-1/igt@kms_flip@2x-absolute-wf_vblank.html
* igt@kms_flip@2x-absolute-wf_vblank-interruptible:
- shard-dg2-set2: [SKIP][224] ([Intel XE#310]) -> [PASS][225] +5 other tests pass
[224]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-dg2-464/igt@kms_flip@2x-absolute-wf_vblank-interruptible.html
[225]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-432/igt@kms_flip@2x-absolute-wf_vblank-interruptible.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bd-dp2-hdmi-a3:
- shard-bmg: [FAIL][226] ([Intel XE#3321]) -> [PASS][227] +3 other tests pass
[226]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-bmg-6/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bd-dp2-hdmi-a3.html
[227]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-1/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bd-dp2-hdmi-a3.html
* igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a6-dp4:
- shard-dg2-set2: [FAIL][228] ([Intel XE#301]) -> [PASS][229] +4 other tests pass
[228]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-dg2-433/igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a6-dp4.html
[229]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-433/igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a6-dp4.html
* igt@kms_flip@flip-vs-blocking-wf-vblank@c-edp1:
- shard-lnl: [FAIL][230] ([Intel XE#886]) -> [PASS][231] +3 other tests pass
[230]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-lnl-1/igt@kms_flip@flip-vs-blocking-wf-vblank@c-edp1.html
[231]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-lnl-4/igt@kms_flip@flip-vs-blocking-wf-vblank@c-edp1.html
* igt@kms_flip@flip-vs-suspend@a-hdmi-a6:
- shard-dg2-set2: [INCOMPLETE][232] ([Intel XE#2049] / [Intel XE#2597]) -> [PASS][233] +1 other test pass
[232]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-dg2-433/igt@kms_flip@flip-vs-suspend@a-hdmi-a6.html
[233]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-463/igt@kms_flip@flip-vs-suspend@a-hdmi-a6.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt:
- shard-dg2-set2: [SKIP][234] ([Intel XE#656]) -> [PASS][235] +8 other tests pass
[234]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-dg2-464/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt.html
[235]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-433/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-1:
- shard-adlp: [DMESG-WARN][236] ([Intel XE#4173]) -> [PASS][237] +7 other tests pass
[236]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-adlp-6/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-1.html
[237]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-1/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-1.html
* igt@kms_plane_cursor@viewport:
- shard-adlp: [FAIL][238] ([Intel XE#1471]) -> [PASS][239] +1 other test pass
[238]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-adlp-1/igt@kms_plane_cursor@viewport.html
[239]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-4/igt@kms_plane_cursor@viewport.html
- shard-dg2-set2: [FAIL][240] ([Intel XE#616]) -> [PASS][241]
[240]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-dg2-464/igt@kms_plane_cursor@viewport.html
[241]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-432/igt@kms_plane_cursor@viewport.html
* igt@kms_plane_multiple@2x-tiling-x:
- shard-dg2-set2: [SKIP][242] ([Intel XE#4596]) -> [PASS][243] +1 other test pass
[242]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-dg2-464/igt@kms_plane_multiple@2x-tiling-x.html
[243]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-463/igt@kms_plane_multiple@2x-tiling-x.html
* igt@kms_plane_scaling@intel-max-src-size:
- shard-dg2-set2: [ABORT][244] ([Intel XE#4540]) -> [PASS][245]
[244]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-dg2-433/igt@kms_plane_scaling@intel-max-src-size.html
[245]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-432/igt@kms_plane_scaling@intel-max-src-size.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75:
- shard-adlp: [DMESG-WARN][246] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][247] +2 other tests pass
[246]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-adlp-8/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75.html
[247]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-1/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75.html
* igt@kms_pm_dc@dc5-psr:
- shard-lnl: [FAIL][248] ([Intel XE#718]) -> [PASS][249]
[248]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-lnl-3/igt@kms_pm_dc@dc5-psr.html
[249]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-lnl-8/igt@kms_pm_dc@dc5-psr.html
* igt@kms_setmode@clone-exclusive-crtc:
- shard-dg2-set2: [SKIP][250] ([Intel XE#455]) -> [PASS][251]
[250]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-dg2-464/igt@kms_setmode@clone-exclusive-crtc.html
[251]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-432/igt@kms_setmode@clone-exclusive-crtc.html
* igt@testdisplay:
- shard-dg2-set2: [ABORT][252] ([Intel XE#2705] / [Intel XE#4540]) -> [PASS][253]
[252]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-dg2-463/igt@testdisplay.html
[253]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-432/igt@testdisplay.html
* igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate-race:
- shard-dg2-set2: [SKIP][254] ([Intel XE#1392]) -> [PASS][255] +2 other tests pass
[254]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-dg2-432/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate-race.html
[255]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-464/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate-race.html
* igt@xe_pm@s4-basic-exec:
- shard-adlp: [ABORT][256] ([Intel XE#1794]) -> [PASS][257]
[256]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-adlp-9/igt@xe_pm@s4-basic-exec.html
[257]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-adlp-1/igt@xe_pm@s4-basic-exec.html
* igt@xe_pm@s4-multiple-execs:
- shard-lnl: [ABORT][258] ([Intel XE#1794]) -> [PASS][259]
[258]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-lnl-2/igt@xe_pm@s4-multiple-execs.html
[259]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-lnl-4/igt@xe_pm@s4-multiple-execs.html
#### Warnings ####
* igt@kms_ccs@bad-aux-stride-y-tiled-ccs@pipe-d-hdmi-a-6:
- shard-dg2-set2: [SKIP][260] ([Intel XE#455] / [Intel XE#787]) -> [SKIP][261] ([Intel XE#787]) +6 other tests skip
[260]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-dg2-464/igt@kms_ccs@bad-aux-stride-y-tiled-ccs@pipe-d-hdmi-a-6.html
[261]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-435/igt@kms_ccs@bad-aux-stride-y-tiled-ccs@pipe-d-hdmi-a-6.html
* igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-6:
- shard-dg2-set2: [SKIP][262] ([Intel XE#787]) -> [SKIP][263] ([Intel XE#455] / [Intel XE#787]) +6 other tests skip
[262]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-dg2-435/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-6.html
[263]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-464/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-6.html
* igt@kms_content_protection@atomic:
- shard-dg2-set2: [FAIL][264] ([Intel XE#1178]) -> [SKIP][265] ([Intel XE#455])
[264]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-dg2-433/igt@kms_content_protection@atomic.html
[265]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-464/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@atomic-dpms@pipe-a-dp-2:
- shard-bmg: [INCOMPLETE][266] ([Intel XE#4132]) -> [FAIL][267] ([Intel XE#1178]) +1 other test fail
[266]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-bmg-1/igt@kms_content_protection@atomic-dpms@pipe-a-dp-2.html
[267]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-8/igt@kms_content_protection@atomic-dpms@pipe-a-dp-2.html
* igt@kms_content_protection@lic-type-0:
- shard-bmg: [SKIP][268] ([Intel XE#2341]) -> [FAIL][269] ([Intel XE#1178])
[268]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-bmg-4/igt@kms_content_protection@lic-type-0.html
[269]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-5/igt@kms_content_protection@lic-type-0.html
* igt@kms_content_protection@srm:
- shard-dg2-set2: [SKIP][270] ([Intel XE#455]) -> [FAIL][271] ([Intel XE#1178])
[270]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-dg2-464/igt@kms_content_protection@srm.html
[271]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-463/igt@kms_content_protection@srm.html
* igt@kms_content_protection@uevent:
- shard-bmg: [SKIP][272] ([Intel XE#2341]) -> [FAIL][273] ([Intel XE#1188])
[272]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-bmg-4/igt@kms_content_protection@uevent.html
[273]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-2/igt@kms_content_protection@uevent.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-dg2-set2: [FAIL][274] ([Intel XE#301]) -> [SKIP][275] ([Intel XE#310])
[274]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-dg2-463/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
[275]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-464/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
* igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-blt:
- shard-bmg: [SKIP][276] ([Intel XE#2312]) -> [SKIP][277] ([Intel XE#2311]) +7 other tests skip
[276]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-blt.html
[277]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-1/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][278] ([Intel XE#2311]) -> [SKIP][279] ([Intel XE#2312]) +12 other tests skip
[278]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-bmg-1/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-mmap-wc.html
[279]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-onoff:
- shard-dg2-set2: [SKIP][280] ([Intel XE#651]) -> [SKIP][281] ([Intel XE#656]) +13 other tests skip
[280]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-dg2-463/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-onoff.html
[281]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-464/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-render:
- shard-bmg: [SKIP][282] ([Intel XE#2312]) -> [SKIP][283] ([Intel XE#4141]) +2 other tests skip
[282]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-render.html
[283]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff:
- shard-bmg: [SKIP][284] ([Intel XE#4141]) -> [SKIP][285] ([Intel XE#2312]) +5 other tests skip
[284]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html
[285]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-mmap-wc:
- shard-dg2-set2: [SKIP][286] ([Intel XE#656]) -> [SKIP][287] ([Intel XE#651]) +16 other tests skip
[286]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-dg2-464/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-mmap-wc.html
[287]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-432/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-onoff:
- shard-dg2-set2: [SKIP][288] ([Intel XE#656]) -> [SKIP][289] ([Intel XE#653]) +17 other tests skip
[288]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-dg2-464/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-onoff.html
[289]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-466/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-plflip-blt:
- shard-bmg: [SKIP][290] ([Intel XE#2312]) -> [SKIP][291] ([Intel XE#2313]) +14 other tests skip
[290]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-plflip-blt.html
[291]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-blt:
- shard-bmg: [SKIP][292] ([Intel XE#2313]) -> [SKIP][293] ([Intel XE#2312]) +12 other tests skip
[292]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-blt.html
[293]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt:
- shard-dg2-set2: [SKIP][294] ([Intel XE#653]) -> [SKIP][295] ([Intel XE#656]) +13 other tests skip
[294]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-dg2-466/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt.html
[295]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-464/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt.html
* igt@kms_plane_multiple@2x-tiling-yf:
- shard-dg2-set2: [SKIP][296] ([Intel XE#4596]) -> [SKIP][297] ([Intel XE#455])
[296]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-dg2-464/igt@kms_plane_multiple@2x-tiling-yf.html
[297]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-466/igt@kms_plane_multiple@2x-tiling-yf.html
* igt@kms_tiled_display@basic-test-pattern:
- shard-dg2-set2: [SKIP][298] ([Intel XE#362]) -> [FAIL][299] ([Intel XE#1729])
[298]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-dg2-464/igt@kms_tiled_display@basic-test-pattern.html
[299]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-433/igt@kms_tiled_display@basic-test-pattern.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-dg2-set2: [SKIP][300] ([Intel XE#1500]) -> [SKIP][301] ([Intel XE#362])
[300]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-dg2-433/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
[301]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-463/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@xe_peer2peer@read:
- shard-dg2-set2: [SKIP][302] ([Intel XE#1061]) -> [FAIL][303] ([Intel XE#1173])
[302]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2896-f0fd77956987f035c79d08c812343a27a655a57b/shard-dg2-432/igt@xe_peer2peer@read.html
[303]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/shard-dg2-433/igt@xe_peer2peer@read.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[Intel XE#1008]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1008
[Intel XE#1061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1061
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1126
[Intel XE#1135]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1135
[Intel XE#1138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1138
[Intel XE#1151]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1151
[Intel XE#1173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1173
[Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
[Intel XE#1188]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1188
[Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
[Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
[Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
[Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
[Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
[Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
[Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
[Intel XE#1471]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1471
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
[Intel XE#1500]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1500
[Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
[Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
[Intel XE#1794]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1794
[Intel XE#1874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1874
[Intel XE#1948]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1948
[Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
[Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
[Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
[Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
[Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
[Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
[Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
[Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
[Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
[Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
[Intel XE#2360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2360
[Intel XE#2373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2373
[Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
[Intel XE#2390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2390
[Intel XE#2391]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2391
[Intel XE#2541]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2541
[Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
[Intel XE#261]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/261
[Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
[Intel XE#2705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2705
[Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
[Intel XE#2882]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2882
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
[Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
[Intel XE#2905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2905
[Intel XE#2907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2907
[Intel XE#2925]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2925
[Intel XE#2927]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2927
[Intel XE#2934]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2934
[Intel XE#2938]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2938
[Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
[Intel XE#3009]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3009
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
[Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
[Intel XE#310]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/310
[Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
[Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
[Intel XE#330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/330
[Intel XE#3321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3321
[Intel XE#3342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3342
[Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
[Intel XE#352]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/352
[Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
[Intel XE#3576]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3576
[Intel XE#362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/362
[Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#3719]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3719
[Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
[Intel XE#379]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/379
[Intel XE#3876]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3876
[Intel XE#4045]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4045
[Intel XE#4130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4130
[Intel XE#4132]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4132
[Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
[Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
[Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
[Intel XE#4259]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4259
[Intel XE#4278]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4278
[Intel XE#4302]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4302
[Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
[Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
[Intel XE#4416]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4416
[Intel XE#4417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4417
[Intel XE#4418]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4418
[Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
[Intel XE#4459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4459
[Intel XE#4494]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4494
[Intel XE#4501]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4501
[Intel XE#4519]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4519
[Intel XE#4540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4540
[Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
[Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
[Intel XE#4577]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4577
[Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
[Intel XE#4624]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4624
[Intel XE#488]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/488
[Intel XE#616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/616
[Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
[Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
[Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
[Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
[Intel XE#718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/718
[Intel XE#756]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/756
[Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
[Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
[Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
[Intel XE#886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/886
[Intel XE#908]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/908
[Intel XE#911]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/911
[Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
Build changes
-------------
* IGT: IGT_8297 -> IGT_8298
* Linux: xe-2896-f0fd77956987f035c79d08c812343a27a655a57b -> xe-pw-145380v2
IGT_8297: 0a27244ed1972af84c78d68523d5791e596349e7 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
IGT_8298: 8298
xe-2896-f0fd77956987f035c79d08c812343a27a655a57b: f0fd77956987f035c79d08c812343a27a655a57b
xe-pw-145380v2: 145380v2
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-145380v2/index.html
[-- Attachment #2: Type: text/html, Size: 99789 bytes --]
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 03/16] drm/i915/dpll: Rename intel_shared_dpll_funcs
2025-04-02 8:31 ` [PATCH 03/16] drm/i915/dpll: Rename intel_shared_dpll_funcs Suraj Kandpal
@ 2025-04-03 14:59 ` Jani Nikula
2025-04-03 15:11 ` Kandpal, Suraj
0 siblings, 1 reply; 31+ messages in thread
From: Jani Nikula @ 2025-04-03 14:59 UTC (permalink / raw)
To: Suraj Kandpal, intel-xe, intel-gfx
Cc: ankit.k.nautiyal, uma.shankar, mika.kahola, ville.syrjala,
Suraj Kandpal
On Wed, 02 Apr 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Rename intel_shared_dpll_funcs to intel_global_dpll_funcs
> since it needs to represent both shared and individual
> dplls.
>
> --v2
> -Change intel_global_dpll to intel_dpll_global to be more
> in line with the naming standard where the name should
> start with the file name [Jani]
Though I'm not sure what we need the "global" for. Just
intel_dpll_funcs?
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 24 +++++++++----------
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 4 ++--
> 2 files changed, 14 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index bbb51119ef5b..92ca2a544e2f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -61,7 +61,7 @@
> */
>
> /* platform specific hooks for managing DPLLs */
> -struct intel_shared_dpll_funcs {
> +struct intel_dpll_global_funcs {
> /*
> * Hook for enabling the pll, called from intel_enable_shared_dpll() if
> * the pll is not already enabled.
> @@ -668,7 +668,7 @@ static bool ibx_compare_hw_state(const struct intel_dpll_hw_state *_a,
> a->fp1 == b->fp1;
> }
>
> -static const struct intel_shared_dpll_funcs ibx_pch_dpll_funcs = {
> +static const struct intel_dpll_global_funcs ibx_pch_dpll_funcs = {
> .enable = ibx_pch_dpll_enable,
> .disable = ibx_pch_dpll_disable,
> .get_hw_state = ibx_pch_dpll_get_hw_state,
> @@ -1268,14 +1268,14 @@ static bool hsw_compare_hw_state(const struct intel_dpll_hw_state *_a,
> a->spll == b->spll;
> }
>
> -static const struct intel_shared_dpll_funcs hsw_ddi_wrpll_funcs = {
> +static const struct intel_dpll_global_funcs hsw_ddi_wrpll_funcs = {
> .enable = hsw_ddi_wrpll_enable,
> .disable = hsw_ddi_wrpll_disable,
> .get_hw_state = hsw_ddi_wrpll_get_hw_state,
> .get_freq = hsw_ddi_wrpll_get_freq,
> };
>
> -static const struct intel_shared_dpll_funcs hsw_ddi_spll_funcs = {
> +static const struct intel_dpll_global_funcs hsw_ddi_spll_funcs = {
> .enable = hsw_ddi_spll_enable,
> .disable = hsw_ddi_spll_disable,
> .get_hw_state = hsw_ddi_spll_get_hw_state,
> @@ -1300,7 +1300,7 @@ static bool hsw_ddi_lcpll_get_hw_state(struct intel_display *display,
> return true;
> }
>
> -static const struct intel_shared_dpll_funcs hsw_ddi_lcpll_funcs = {
> +static const struct intel_dpll_global_funcs hsw_ddi_lcpll_funcs = {
> .enable = hsw_ddi_lcpll_enable,
> .disable = hsw_ddi_lcpll_disable,
> .get_hw_state = hsw_ddi_lcpll_get_hw_state,
> @@ -2002,14 +2002,14 @@ static bool skl_compare_hw_state(const struct intel_dpll_hw_state *_a,
> a->cfgcr2 == b->cfgcr2;
> }
>
> -static const struct intel_shared_dpll_funcs skl_ddi_pll_funcs = {
> +static const struct intel_dpll_global_funcs skl_ddi_pll_funcs = {
> .enable = skl_ddi_pll_enable,
> .disable = skl_ddi_pll_disable,
> .get_hw_state = skl_ddi_pll_get_hw_state,
> .get_freq = skl_ddi_pll_get_freq,
> };
>
> -static const struct intel_shared_dpll_funcs skl_ddi_dpll0_funcs = {
> +static const struct intel_dpll_global_funcs skl_ddi_dpll0_funcs = {
> .enable = skl_ddi_dpll0_enable,
> .disable = skl_ddi_dpll0_disable,
> .get_hw_state = skl_ddi_dpll0_get_hw_state,
> @@ -2484,7 +2484,7 @@ static bool bxt_compare_hw_state(const struct intel_dpll_hw_state *_a,
> a->pcsdw12 == b->pcsdw12;
> }
>
> -static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = {
> +static const struct intel_dpll_global_funcs bxt_ddi_pll_funcs = {
> .enable = bxt_ddi_pll_enable,
> .disable = bxt_ddi_pll_disable,
> .get_hw_state = bxt_ddi_pll_get_hw_state,
> @@ -4129,21 +4129,21 @@ static bool icl_compare_hw_state(const struct intel_dpll_hw_state *_a,
> a->mg_pll_tdc_coldst_bias == b->mg_pll_tdc_coldst_bias;
> }
>
> -static const struct intel_shared_dpll_funcs combo_pll_funcs = {
> +static const struct intel_dpll_global_funcs combo_pll_funcs = {
> .enable = combo_pll_enable,
> .disable = combo_pll_disable,
> .get_hw_state = combo_pll_get_hw_state,
> .get_freq = icl_ddi_combo_pll_get_freq,
> };
>
> -static const struct intel_shared_dpll_funcs tbt_pll_funcs = {
> +static const struct intel_dpll_global_funcs tbt_pll_funcs = {
> .enable = tbt_pll_enable,
> .disable = tbt_pll_disable,
> .get_hw_state = tbt_pll_get_hw_state,
> .get_freq = icl_ddi_tbt_pll_get_freq,
> };
>
> -static const struct intel_shared_dpll_funcs mg_pll_funcs = {
> +static const struct intel_dpll_global_funcs mg_pll_funcs = {
> .enable = mg_pll_enable,
> .disable = mg_pll_disable,
> .get_hw_state = mg_pll_get_hw_state,
> @@ -4191,7 +4191,7 @@ static const struct intel_dpll_mgr ehl_pll_mgr = {
> .compare_hw_state = icl_compare_hw_state,
> };
>
> -static const struct intel_shared_dpll_funcs dkl_pll_funcs = {
> +static const struct intel_dpll_global_funcs dkl_pll_funcs = {
> .enable = mg_pll_enable,
> .disable = mg_pll_disable,
> .get_hw_state = dkl_pll_get_hw_state,
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index d93072486831..2080118be523 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -41,7 +41,7 @@ struct intel_crtc;
> struct intel_crtc_state;
> struct intel_encoder;
> struct intel_shared_dpll;
> -struct intel_shared_dpll_funcs;
> +struct intel_dpll_global_funcs;
>
> /**
> * enum intel_dpll_id - possible DPLL ids
> @@ -314,7 +314,7 @@ struct dpll_info {
> /**
> * @funcs: platform specific hooks
> */
> - const struct intel_shared_dpll_funcs *funcs;
> + const struct intel_dpll_global_funcs *funcs;
>
> /**
> * @id: unique identifier for this DPLL
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 04/16] drm/i915/dpll: Rename intel_shared_dpll
2025-04-02 8:31 ` [PATCH 04/16] drm/i915/dpll: Rename intel_shared_dpll Suraj Kandpal
@ 2025-04-03 15:01 ` Jani Nikula
2025-04-03 15:15 ` Kandpal, Suraj
0 siblings, 1 reply; 31+ messages in thread
From: Jani Nikula @ 2025-04-03 15:01 UTC (permalink / raw)
To: Suraj Kandpal, intel-xe, intel-gfx
Cc: ankit.k.nautiyal, uma.shankar, mika.kahola, ville.syrjala,
Suraj Kandpal
On Wed, 02 Apr 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Rename intel_shared_dpll to intel_dpll_global to represent both
> shared and individual dplls. Since from MTL each PHY has it's
> own PLL making the shared PLL naming a little outdated. In an
> effort to make this framework accepting of future changes this
> needs to be done.
>
> --v2
> -Use intel_dpll_global to make sure names start with the filename
> [Jani/Ville]
> -Explain the need of this rename [Jani]
Here too, why not just struct intel_dpll?
I get that it's used in intel_display_core.h but it's a single user
that's less important and could be renamed there.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 52 ++--
> drivers/gpu/drm/i915/display/intel_ddi.h | 6 +-
> drivers/gpu/drm/i915/display/intel_display.c | 12 +-
> .../gpu/drm/i915/display/intel_display_core.h | 4 +-
> .../drm/i915/display/intel_display_debugfs.c | 2 +-
> .../drm/i915/display/intel_display_types.h | 6 +-
> drivers/gpu/drm/i915/display/intel_dpll.c | 4 +-
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 228 +++++++++---------
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 18 +-
> drivers/gpu/drm/i915/display/intel_fdi.c | 2 +-
> drivers/gpu/drm/i915/display/intel_lvds.c | 2 +-
> .../drm/i915/display/intel_modeset_setup.c | 8 +-
> .../gpu/drm/i915/display/intel_pch_display.c | 10 +-
> .../gpu/drm/i915/display/intel_pch_refclk.c | 2 +-
> 15 files changed, 179 insertions(+), 179 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index b69c713fb79a..97c20c493e4d 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -658,7 +658,7 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder,
> {
> struct intel_display *display = to_intel_display(encoder);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> - struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> + struct intel_dpll_global *pll = crtc_state->dpll_global;
> enum phy phy;
> u32 val;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 56068b2ef964..a8934ea5077d 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -234,7 +234,7 @@ static void intel_wait_ddi_buf_active(struct intel_encoder *encoder)
> port_name(port));
> }
>
> -static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
> +static u32 hsw_pll_to_ddi_pll_sel(const struct intel_dpll_global *pll)
> {
> switch (pll->info->id) {
> case DPLL_ID_WRPLL1:
> @@ -258,7 +258,7 @@ static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
> static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> - const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> + const struct intel_dpll_global *pll = crtc_state->dpll_global;
> int clock = crtc_state->port_clock;
> const enum intel_dpll_id id = pll->info->id;
>
> @@ -1559,7 +1559,7 @@ static bool _icl_ddi_is_clock_enabled(struct intel_display *display, i915_reg_t
> return !(intel_de_read(display, reg) & clk_off);
> }
>
> -static struct intel_shared_dpll *
> +static struct intel_dpll_global *
> _icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg,
> u32 clk_sel_mask, u32 clk_sel_shift)
> {
> @@ -1574,7 +1574,7 @@ static void adls_ddi_enable_clock(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(encoder);
> - const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> + const struct intel_dpll_global *pll = crtc_state->dpll_global;
> enum phy phy = intel_encoder_to_phy(encoder);
>
> if (drm_WARN_ON(display->drm, !pll))
> @@ -1604,7 +1604,7 @@ static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder)
> ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
> }
>
> -static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder)
> +static struct intel_dpll_global *adls_ddi_get_pll(struct intel_encoder *encoder)
> {
> struct intel_display *display = to_intel_display(encoder);
> enum phy phy = intel_encoder_to_phy(encoder);
> @@ -1618,7 +1618,7 @@ static void rkl_ddi_enable_clock(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(encoder);
> - const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> + const struct intel_dpll_global *pll = crtc_state->dpll_global;
> enum phy phy = intel_encoder_to_phy(encoder);
>
> if (drm_WARN_ON(display->drm, !pll))
> @@ -1648,7 +1648,7 @@ static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder)
> RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
> }
>
> -static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder)
> +static struct intel_dpll_global *rkl_ddi_get_pll(struct intel_encoder *encoder)
> {
> struct intel_display *display = to_intel_display(encoder);
> enum phy phy = intel_encoder_to_phy(encoder);
> @@ -1662,7 +1662,7 @@ static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(encoder);
> - const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> + const struct intel_dpll_global *pll = crtc_state->dpll_global;
> enum phy phy = intel_encoder_to_phy(encoder);
>
> if (drm_WARN_ON(display->drm, !pll))
> @@ -1701,7 +1701,7 @@ static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder)
> DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
> }
>
> -static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder)
> +static struct intel_dpll_global *dg1_ddi_get_pll(struct intel_encoder *encoder)
> {
> struct intel_display *display = to_intel_display(encoder);
> enum phy phy = intel_encoder_to_phy(encoder);
> @@ -1728,7 +1728,7 @@ static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(encoder);
> - const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> + const struct intel_dpll_global *pll = crtc_state->dpll_global;
> enum phy phy = intel_encoder_to_phy(encoder);
>
> if (drm_WARN_ON(display->drm, !pll))
> @@ -1758,7 +1758,7 @@ static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder)
> ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
> }
>
> -struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder)
> +struct intel_dpll_global *icl_ddi_combo_get_pll(struct intel_encoder *encoder)
> {
> struct intel_display *display = to_intel_display(encoder);
> enum phy phy = intel_encoder_to_phy(encoder);
> @@ -1772,7 +1772,7 @@ static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(encoder);
> - const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> + const struct intel_dpll_global *pll = crtc_state->dpll_global;
> enum port port = encoder->port;
>
> if (drm_WARN_ON(display->drm, !pll))
> @@ -1815,7 +1815,7 @@ static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(encoder);
> - const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> + const struct intel_dpll_global *pll = crtc_state->dpll_global;
> enum tc_port tc_port = intel_encoder_to_tc(encoder);
> enum port port = encoder->port;
>
> @@ -1866,7 +1866,7 @@ static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
> return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));
> }
>
> -static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder)
> +static struct intel_dpll_global *icl_ddi_tc_get_pll(struct intel_encoder *encoder)
> {
> struct intel_display *display = to_intel_display(encoder);
> enum tc_port tc_port = intel_encoder_to_tc(encoder);
> @@ -1896,7 +1896,7 @@ static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encode
> return intel_get_shared_dpll_by_id(display, id);
> }
>
> -static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
> +static struct intel_dpll_global *bxt_ddi_get_pll(struct intel_encoder *encoder)
> {
> struct intel_display *display = to_intel_display(encoder->base.dev);
> enum intel_dpll_id id;
> @@ -1923,7 +1923,7 @@ static void skl_ddi_enable_clock(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(encoder);
> - const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> + const struct intel_dpll_global *pll = crtc_state->dpll_global;
> enum port port = encoder->port;
>
> if (drm_WARN_ON(display->drm, !pll))
> @@ -1965,7 +1965,7 @@ static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder)
> return !(intel_de_read(display, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port));
> }
>
> -static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder)
> +static struct intel_dpll_global *skl_ddi_get_pll(struct intel_encoder *encoder)
> {
> struct intel_display *display = to_intel_display(encoder);
> enum port port = encoder->port;
> @@ -1991,7 +1991,7 @@ void hsw_ddi_enable_clock(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(encoder);
> - const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> + const struct intel_dpll_global *pll = crtc_state->dpll_global;
> enum port port = encoder->port;
>
> if (drm_WARN_ON(display->drm, !pll))
> @@ -2016,7 +2016,7 @@ bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder)
> return intel_de_read(display, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE;
> }
>
> -static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder)
> +static struct intel_dpll_global *hsw_ddi_get_pll(struct intel_encoder *encoder)
> {
> struct intel_display *display = to_intel_display(encoder);
> enum port port = encoder->port;
> @@ -4184,7 +4184,7 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
>
> void intel_ddi_get_clock(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state,
> - struct intel_shared_dpll *pll)
> + struct intel_dpll_global *pll)
> {
> struct intel_display *display = to_intel_display(encoder);
> enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
> @@ -4200,7 +4200,7 @@ void intel_ddi_get_clock(struct intel_encoder *encoder,
>
> icl_set_active_port_dpll(crtc_state, port_dpll_id);
>
> - crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->shared_dpll,
> + crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->dpll_global,
> &crtc_state->dpll_hw_state);
> }
>
> @@ -4254,7 +4254,7 @@ static void icl_ddi_combo_get_config(struct intel_encoder *encoder,
> intel_ddi_get_config(encoder, crtc_state);
> }
>
> -static bool icl_ddi_tc_pll_is_tbt(const struct intel_shared_dpll *pll)
> +static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll_global *pll)
> {
> return pll->info->id == DPLL_ID_ICL_TBTPLL;
> }
> @@ -4264,7 +4264,7 @@ icl_ddi_tc_port_pll_type(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(encoder);
> - const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> + const struct intel_dpll_global *pll = crtc_state->dpll_global;
>
> if (drm_WARN_ON(display->drm, !pll))
> return ICL_PORT_DPLL_DEFAULT;
> @@ -4287,7 +4287,7 @@ intel_ddi_port_pll_type(struct intel_encoder *encoder,
>
> static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state,
> - struct intel_shared_dpll *pll)
> + struct intel_dpll_global *pll)
> {
> struct intel_display *display = to_intel_display(encoder);
> enum icl_port_dpll_id port_dpll_id;
> @@ -4310,10 +4310,10 @@ static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
>
> icl_set_active_port_dpll(crtc_state, port_dpll_id);
>
> - if (icl_ddi_tc_pll_is_tbt(crtc_state->shared_dpll))
> + if (icl_ddi_tc_pll_is_tbt(crtc_state->dpll_global))
> crtc_state->port_clock = icl_calc_tbt_pll_link(display, encoder->port);
> else
> - crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->shared_dpll,
> + crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->dpll_global,
> &crtc_state->dpll_hw_state);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h
> index 353eb04079e9..c41341b7e5cf 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.h
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.h
> @@ -18,7 +18,7 @@ struct intel_display;
> struct intel_dp;
> struct intel_dpll_hw_state;
> struct intel_encoder;
> -struct intel_shared_dpll;
> +struct intel_dpll_global;
> enum pipe;
> enum port;
> enum transcoder;
> @@ -40,7 +40,7 @@ void intel_ddi_enable_clock(struct intel_encoder *encoder,
> void intel_ddi_disable_clock(struct intel_encoder *encoder);
> void intel_ddi_get_clock(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state,
> - struct intel_shared_dpll *pll);
> + struct intel_dpll_global *pll);
> void hsw_ddi_enable_clock(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state);
> void hsw_ddi_disable_clock(struct intel_encoder *encoder);
> @@ -50,7 +50,7 @@ intel_ddi_port_pll_type(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state);
> void hsw_ddi_get_config(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state);
> -struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder);
> +struct intel_dpll_global *icl_ddi_combo_get_pll(struct intel_encoder *encoder);
> void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state);
> void intel_wait_ddi_buf_idle(struct intel_display *display, enum port port);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index c540e2cae1f0..5b808bad61e0 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1322,7 +1322,7 @@ static void intel_encoders_update_prepare(struct intel_atomic_state *state)
> if (intel_crtc_needs_modeset(new_crtc_state))
> continue;
>
> - new_crtc_state->shared_dpll = old_crtc_state->shared_dpll;
> + new_crtc_state->dpll_global = old_crtc_state->dpll_global;
> new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state;
> }
> }
> @@ -1661,7 +1661,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
>
> intel_encoders_pre_pll_enable(state, crtc);
>
> - if (new_crtc_state->shared_dpll)
> + if (new_crtc_state->dpll_global)
> intel_enable_shared_dpll(new_crtc_state);
>
> intel_encoders_pre_enable(state, crtc);
> @@ -1957,7 +1957,7 @@ static void get_crtc_power_domains(struct intel_crtc_state *crtc_state,
> if (HAS_DDI(display) && crtc_state->has_audio)
> set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits);
>
> - if (crtc_state->shared_dpll)
> + if (crtc_state->dpll_global)
> set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits);
>
> if (crtc_state->dsc.compression_enable)
> @@ -4498,7 +4498,7 @@ copy_joiner_crtc_state_modeset(struct intel_atomic_state *state,
> /* preserve some things from the slave's original crtc state */
> saved_state->uapi = secondary_crtc_state->uapi;
> saved_state->scaler_state = secondary_crtc_state->scaler_state;
> - saved_state->shared_dpll = secondary_crtc_state->shared_dpll;
> + saved_state->dpll_global = secondary_crtc_state->dpll_global;
> saved_state->crc_enabled = secondary_crtc_state->crc_enabled;
>
> intel_crtc_free_hw_state(secondary_crtc_state);
> @@ -4561,7 +4561,7 @@ intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
> saved_state->uapi = crtc_state->uapi;
> saved_state->inherited = crtc_state->inherited;
> saved_state->scaler_state = crtc_state->scaler_state;
> - saved_state->shared_dpll = crtc_state->shared_dpll;
> + saved_state->dpll_global = crtc_state->dpll_global;
> saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
> memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
> sizeof(saved_state->icl_port_dplls));
> @@ -5313,7 +5313,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> PIPE_CONF_CHECK_BOOL(double_wide);
>
> if (display->dpll.mgr)
> - PIPE_CONF_CHECK_P(shared_dpll);
> + PIPE_CONF_CHECK_P(dpll_global);
>
> /* FIXME convert everything over the dpll_mgr */
> if (display->dpll.mgr || HAS_GMCH(display))
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> index 3673275f9061..b23ff1c34bdf 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -126,8 +126,8 @@ struct intel_audio {
> struct intel_dpll {
> struct mutex lock;
>
> - int num_shared_dpll;
> - struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
> + int num_dpll_global;
> + struct intel_dpll_global dpll_globals[I915_NUM_PLLS];
> const struct intel_dpll_mgr *mgr;
>
> struct {
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index a317c6646382..db26998e0baa 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -625,7 +625,7 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
> {
> struct intel_display *display = node_to_intel_display(m->private);
> struct drm_printer p = drm_seq_file_printer(m);
> - struct intel_shared_dpll *pll;
> + struct intel_dpll_global *pll;
> int i;
>
> drm_modeset_lock_all(display->drm);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 7d1c64f7b405..e080ffb32546 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1075,8 +1075,8 @@ struct intel_crtc_state {
> * haswell. */
> struct dpll dpll;
>
> - /* Selected dpll when shared or NULL. */
> - struct intel_shared_dpll *shared_dpll;
> + /* Selected dpll. */
> + struct intel_dpll_global *dpll_global;
>
> /* Actual register state of the dpll, for shared dpll cross-checking. */
> struct intel_dpll_hw_state dpll_hw_state;
> @@ -1086,7 +1086,7 @@ struct intel_crtc_state {
> * setting shared_dpll and dpll_hw_state to one of these reserved ones.
> */
> struct icl_port_dpll {
> - struct intel_shared_dpll *pll;
> + struct intel_dpll_global *pll;
> struct intel_dpll_hw_state hw_state;
> } icl_port_dplls[ICL_PORT_DPLL_COUNT];
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 0481b1365b85..c6d29382378b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -1770,9 +1770,9 @@ int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
> int ret;
>
> drm_WARN_ON(display->drm, !intel_crtc_needs_modeset(crtc_state));
> - drm_WARN_ON(display->drm, !crtc_state->hw.enable && crtc_state->shared_dpll);
> + drm_WARN_ON(display->drm, !crtc_state->hw.enable && crtc_state->dpll_global);
>
> - if (!crtc_state->hw.enable || crtc_state->shared_dpll)
> + if (!crtc_state->hw.enable || crtc_state->dpll_global)
> return 0;
>
> if (!display->funcs.dpll->crtc_get_shared_dpll)
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 92ca2a544e2f..833c90f3f0f1 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -67,7 +67,7 @@ struct intel_dpll_global_funcs {
> * the pll is not already enabled.
> */
> void (*enable)(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll_global *pll,
> const struct intel_dpll_hw_state *dpll_hw_state);
>
> /*
> @@ -76,7 +76,7 @@ struct intel_dpll_global_funcs {
> * tracked users for it.
> */
> void (*disable)(struct intel_display *display,
> - struct intel_shared_dpll *pll);
> + struct intel_dpll_global *pll);
>
> /*
> * Hook for reading the values currently programmed to the DPLL
> @@ -84,7 +84,7 @@ struct intel_dpll_global_funcs {
> * verification after a mode set.
> */
> bool (*get_hw_state)(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll_global *pll,
> struct intel_dpll_hw_state *dpll_hw_state);
>
> /*
> @@ -92,7 +92,7 @@ struct intel_dpll_global_funcs {
> * in state.
> */
> int (*get_freq)(struct intel_display *i915,
> - const struct intel_shared_dpll *pll,
> + const struct intel_dpll_global *pll,
> const struct intel_dpll_hw_state *dpll_hw_state);
> };
>
> @@ -121,7 +121,7 @@ static void
> intel_atomic_duplicate_dpll_state(struct intel_display *display,
> struct intel_dpll_state *dpll_state)
> {
> - struct intel_shared_dpll *pll;
> + struct intel_dpll_global *pll;
> int i;
>
> /* Copy dpll state */
> @@ -155,11 +155,11 @@ intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
> * Returns:
> * A pointer to the DPLL with @id
> */
> -struct intel_shared_dpll *
> +struct intel_dpll_global *
> intel_get_shared_dpll_by_id(struct intel_display *display,
> enum intel_dpll_id id)
> {
> - struct intel_shared_dpll *pll;
> + struct intel_dpll_global *pll;
> int i;
>
> for_each_dpll(display, pll, i) {
> @@ -173,7 +173,7 @@ intel_get_shared_dpll_by_id(struct intel_display *display,
>
> /* For ILK+ */
> void assert_shared_dpll(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll_global *pll,
> bool state)
> {
> bool cur_state;
> @@ -202,7 +202,7 @@ enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port)
>
> static i915_reg_t
> intel_combo_pll_enable_reg(struct intel_display *display,
> - struct intel_shared_dpll *pll)
> + struct intel_dpll_global *pll)
> {
> if (display->platform.dg1)
> return DG1_DPLL_ENABLE(pll->info->id);
> @@ -215,7 +215,7 @@ intel_combo_pll_enable_reg(struct intel_display *display,
>
> static i915_reg_t
> intel_tc_pll_enable_reg(struct intel_display *display,
> - struct intel_shared_dpll *pll)
> + struct intel_dpll_global *pll)
> {
> const enum intel_dpll_id id = pll->info->id;
> enum tc_port tc_port = icl_pll_id_to_tc_port(id);
> @@ -227,7 +227,7 @@ intel_tc_pll_enable_reg(struct intel_display *display,
> }
>
> static void _intel_enable_shared_dpll(struct intel_display *display,
> - struct intel_shared_dpll *pll)
> + struct intel_dpll_global *pll)
> {
> if (pll->info->power_domain)
> pll->wakeref = intel_display_power_get(display, pll->info->power_domain);
> @@ -237,7 +237,7 @@ static void _intel_enable_shared_dpll(struct intel_display *display,
> }
>
> static void _intel_disable_shared_dpll(struct intel_display *display,
> - struct intel_shared_dpll *pll)
> + struct intel_dpll_global *pll)
> {
> pll->info->funcs->disable(display, pll);
> pll->on = false;
> @@ -256,7 +256,7 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> + struct intel_dpll_global *pll = crtc_state->dpll_global;
> unsigned int pipe_mask = intel_crtc_joined_pipe_mask(crtc_state);
> unsigned int old_mask;
>
> @@ -302,7 +302,7 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> + struct intel_dpll_global *pll = crtc_state->dpll_global;
> unsigned int pipe_mask = intel_crtc_joined_pipe_mask(crtc_state);
>
> /* PCH only available on ILK+ */
> @@ -341,7 +341,7 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
> static unsigned long
> intel_dpll_mask_all(struct intel_display *display)
> {
> - struct intel_shared_dpll *pll;
> + struct intel_dpll_global *pll;
> unsigned long dpll_mask = 0;
> int i;
>
> @@ -354,7 +354,7 @@ intel_dpll_mask_all(struct intel_display *display)
> return dpll_mask;
> }
>
> -static struct intel_shared_dpll *
> +static struct intel_dpll_global *
> intel_find_shared_dpll(struct intel_atomic_state *state,
> const struct intel_crtc *crtc,
> const struct intel_dpll_hw_state *dpll_hw_state,
> @@ -363,7 +363,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
> struct intel_display *display = to_intel_display(crtc);
> unsigned long dpll_mask_all = intel_dpll_mask_all(display);
> struct intel_dpll_state *dpll_state;
> - struct intel_shared_dpll *unused_pll = NULL;
> + struct intel_dpll_global *unused_pll = NULL;
> enum intel_dpll_id id;
>
> dpll_state = intel_atomic_get_shared_dpll_state(&state->base);
> @@ -371,7 +371,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
> drm_WARN_ON(display->drm, dpll_mask & ~dpll_mask_all);
>
> for_each_set_bit(id, &dpll_mask, fls(dpll_mask_all)) {
> - struct intel_shared_dpll *pll;
> + struct intel_dpll_global *pll;
>
> pll = intel_get_shared_dpll_by_id(display, id);
> if (!pll)
> @@ -418,7 +418,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
> */
> static void
> intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc,
> - const struct intel_shared_dpll *pll,
> + const struct intel_dpll_global *pll,
> struct intel_dpll_state *dpll_state)
> {
> struct intel_display *display = to_intel_display(crtc);
> @@ -434,7 +434,7 @@ intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc,
> static void
> intel_reference_shared_dpll(struct intel_atomic_state *state,
> const struct intel_crtc *crtc,
> - const struct intel_shared_dpll *pll,
> + const struct intel_dpll_global *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> struct intel_dpll_state *dpll_state;
> @@ -457,7 +457,7 @@ intel_reference_shared_dpll(struct intel_atomic_state *state,
> */
> void
> intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
> - const struct intel_shared_dpll *pll,
> + const struct intel_dpll_global *pll,
> struct intel_dpll_state *dpll_state)
> {
> struct intel_display *display = to_intel_display(crtc);
> @@ -472,7 +472,7 @@ intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
>
> static void intel_unreference_shared_dpll(struct intel_atomic_state *state,
> const struct intel_crtc *crtc,
> - const struct intel_shared_dpll *pll)
> + const struct intel_dpll_global *pll)
> {
> struct intel_dpll_state *dpll_state;
>
> @@ -489,12 +489,12 @@ static void intel_put_dpll(struct intel_atomic_state *state,
> struct intel_crtc_state *new_crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
>
> - new_crtc_state->shared_dpll = NULL;
> + new_crtc_state->dpll_global = NULL;
>
> - if (!old_crtc_state->shared_dpll)
> + if (!old_crtc_state->dpll_global)
> return;
>
> - intel_unreference_shared_dpll(state, crtc, old_crtc_state->shared_dpll);
> + intel_unreference_shared_dpll(state, crtc, old_crtc_state->dpll_global);
> }
>
> /**
> @@ -512,7 +512,7 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
> {
> struct intel_display *display = to_intel_display(state);
> struct intel_dpll_state *dpll_state = state->dpll_state;
> - struct intel_shared_dpll *pll;
> + struct intel_dpll_global *pll;
> int i;
>
> if (!state->dpll_set)
> @@ -523,7 +523,7 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
> }
>
> static bool ibx_pch_dpll_get_hw_state(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll_global *pll,
> struct intel_dpll_hw_state *dpll_hw_state)
> {
> struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx;
> @@ -559,7 +559,7 @@ static void ibx_assert_pch_refclk_enabled(struct intel_display *display)
> }
>
> static void ibx_pch_dpll_enable(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll_global *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> const struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx;
> @@ -588,7 +588,7 @@ static void ibx_pch_dpll_enable(struct intel_display *display,
> }
>
> static void ibx_pch_dpll_disable(struct intel_display *display,
> - struct intel_shared_dpll *pll)
> + struct intel_dpll_global *pll)
> {
> const enum intel_dpll_id id = pll->info->id;
>
> @@ -612,7 +612,7 @@ static int ibx_get_dpll(struct intel_atomic_state *state,
> struct drm_i915_private *i915 = to_i915(display->drm);
> struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> - struct intel_shared_dpll *pll;
> + struct intel_dpll_global *pll;
> enum intel_dpll_id id;
>
> if (HAS_PCH_IBX(i915)) {
> @@ -638,7 +638,7 @@ static int ibx_get_dpll(struct intel_atomic_state *state,
> intel_reference_shared_dpll(state, crtc,
> pll, &crtc_state->dpll_hw_state);
>
> - crtc_state->shared_dpll = pll;
> + crtc_state->dpll_global = pll;
>
> return 0;
> }
> @@ -690,7 +690,7 @@ static const struct intel_dpll_mgr pch_pll_mgr = {
> };
>
> static void hsw_ddi_wrpll_enable(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll_global *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
> @@ -702,7 +702,7 @@ static void hsw_ddi_wrpll_enable(struct intel_display *display,
> }
>
> static void hsw_ddi_spll_enable(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll_global *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
> @@ -713,7 +713,7 @@ static void hsw_ddi_spll_enable(struct intel_display *display,
> }
>
> static void hsw_ddi_wrpll_disable(struct intel_display *display,
> - struct intel_shared_dpll *pll)
> + struct intel_dpll_global *pll)
> {
> const enum intel_dpll_id id = pll->info->id;
>
> @@ -729,7 +729,7 @@ static void hsw_ddi_wrpll_disable(struct intel_display *display,
> }
>
> static void hsw_ddi_spll_disable(struct intel_display *display,
> - struct intel_shared_dpll *pll)
> + struct intel_dpll_global *pll)
> {
> enum intel_dpll_id id = pll->info->id;
>
> @@ -745,7 +745,7 @@ static void hsw_ddi_spll_disable(struct intel_display *display,
> }
>
> static bool hsw_ddi_wrpll_get_hw_state(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll_global *pll,
> struct intel_dpll_hw_state *dpll_hw_state)
> {
> struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
> @@ -767,7 +767,7 @@ static bool hsw_ddi_wrpll_get_hw_state(struct intel_display *display,
> }
>
> static bool hsw_ddi_spll_get_hw_state(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll_global *pll,
> struct intel_dpll_hw_state *dpll_hw_state)
> {
> struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
> @@ -994,7 +994,7 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */,
> }
>
> static int hsw_ddi_wrpll_get_freq(struct intel_display *display,
> - const struct intel_shared_dpll *pll,
> + const struct intel_dpll_global *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
> @@ -1057,7 +1057,7 @@ hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state,
> return 0;
> }
>
> -static struct intel_shared_dpll *
> +static struct intel_dpll_global *
> hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> @@ -1088,11 +1088,11 @@ hsw_ddi_lcpll_compute_dpll(struct intel_crtc_state *crtc_state)
> }
> }
>
> -static struct intel_shared_dpll *
> +static struct intel_dpll_global *
> hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
> - struct intel_shared_dpll *pll;
> + struct intel_dpll_global *pll;
> enum intel_dpll_id pll_id;
> int clock = crtc_state->port_clock;
>
> @@ -1120,7 +1120,7 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
> }
>
> static int hsw_ddi_lcpll_get_freq(struct intel_display *display,
> - const struct intel_shared_dpll *pll,
> + const struct intel_dpll_global *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> int link_clock = 0;
> @@ -1160,7 +1160,7 @@ hsw_ddi_spll_compute_dpll(struct intel_atomic_state *state,
> return 0;
> }
>
> -static struct intel_shared_dpll *
> +static struct intel_dpll_global *
> hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> @@ -1172,7 +1172,7 @@ hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
> }
>
> static int hsw_ddi_spll_get_freq(struct intel_display *display,
> - const struct intel_shared_dpll *pll,
> + const struct intel_dpll_global *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
> @@ -1219,7 +1219,7 @@ static int hsw_get_dpll(struct intel_atomic_state *state,
> {
> struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> - struct intel_shared_dpll *pll = NULL;
> + struct intel_dpll_global *pll = NULL;
>
> if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> pll = hsw_ddi_wrpll_get_dpll(state, crtc);
> @@ -1234,7 +1234,7 @@ static int hsw_get_dpll(struct intel_atomic_state *state,
> intel_reference_shared_dpll(state, crtc,
> pll, &crtc_state->dpll_hw_state);
>
> - crtc_state->shared_dpll = pll;
> + crtc_state->dpll_global = pll;
>
> return 0;
> }
> @@ -1283,18 +1283,18 @@ static const struct intel_dpll_global_funcs hsw_ddi_spll_funcs = {
> };
>
> static void hsw_ddi_lcpll_enable(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll_global *pll,
> const struct intel_dpll_hw_state *hw_state)
> {
> }
>
> static void hsw_ddi_lcpll_disable(struct intel_display *display,
> - struct intel_shared_dpll *pll)
> + struct intel_dpll_global *pll)
> {
> }
>
> static bool hsw_ddi_lcpll_get_hw_state(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll_global *pll,
> struct intel_dpll_hw_state *dpll_hw_state)
> {
> return true;
> @@ -1362,7 +1362,7 @@ static const struct skl_dpll_regs skl_dpll_regs[4] = {
> };
>
> static void skl_ddi_pll_write_ctrl1(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll_global *pll,
> const struct skl_dpll_hw_state *hw_state)
> {
> const enum intel_dpll_id id = pll->info->id;
> @@ -1376,7 +1376,7 @@ static void skl_ddi_pll_write_ctrl1(struct intel_display *display,
> }
>
> static void skl_ddi_pll_enable(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll_global *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
> @@ -1398,7 +1398,7 @@ static void skl_ddi_pll_enable(struct intel_display *display,
> }
>
> static void skl_ddi_dpll0_enable(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll_global *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
> @@ -1407,7 +1407,7 @@ static void skl_ddi_dpll0_enable(struct intel_display *display,
> }
>
> static void skl_ddi_pll_disable(struct intel_display *display,
> - struct intel_shared_dpll *pll)
> + struct intel_dpll_global *pll)
> {
> const struct skl_dpll_regs *regs = skl_dpll_regs;
> const enum intel_dpll_id id = pll->info->id;
> @@ -1418,12 +1418,12 @@ static void skl_ddi_pll_disable(struct intel_display *display,
> }
>
> static void skl_ddi_dpll0_disable(struct intel_display *display,
> - struct intel_shared_dpll *pll)
> + struct intel_dpll_global *pll)
> {
> }
>
> static bool skl_ddi_pll_get_hw_state(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll_global *pll,
> struct intel_dpll_hw_state *dpll_hw_state)
> {
> struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
> @@ -1461,7 +1461,7 @@ static bool skl_ddi_pll_get_hw_state(struct intel_display *display,
> }
>
> static bool skl_ddi_dpll0_get_hw_state(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll_global *pll,
> struct intel_dpll_hw_state *dpll_hw_state)
> {
> struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
> @@ -1734,7 +1734,7 @@ skl_ddi_calculate_wrpll(int clock,
> }
>
> static int skl_ddi_wrpll_get_freq(struct intel_display *display,
> - const struct intel_shared_dpll *pll,
> + const struct intel_dpll_global *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
> @@ -1882,7 +1882,7 @@ skl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
> }
>
> static int skl_ddi_lcpll_get_freq(struct intel_display *display,
> - const struct intel_shared_dpll *pll,
> + const struct intel_dpll_global *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
> @@ -1937,7 +1937,7 @@ static int skl_get_dpll(struct intel_atomic_state *state,
> {
> struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> - struct intel_shared_dpll *pll;
> + struct intel_dpll_global *pll;
>
> if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> pll = intel_find_shared_dpll(state, crtc,
> @@ -1955,13 +1955,13 @@ static int skl_get_dpll(struct intel_atomic_state *state,
> intel_reference_shared_dpll(state, crtc,
> pll, &crtc_state->dpll_hw_state);
>
> - crtc_state->shared_dpll = pll;
> + crtc_state->dpll_global = pll;
>
> return 0;
> }
>
> static int skl_ddi_pll_get_freq(struct intel_display *display,
> - const struct intel_shared_dpll *pll,
> + const struct intel_dpll_global *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
> @@ -2036,7 +2036,7 @@ static const struct intel_dpll_mgr skl_pll_mgr = {
> };
>
> static void bxt_ddi_pll_enable(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll_global *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
> @@ -2139,7 +2139,7 @@ static void bxt_ddi_pll_enable(struct intel_display *display,
> }
>
> static void bxt_ddi_pll_disable(struct intel_display *display,
> - struct intel_shared_dpll *pll)
> + struct intel_dpll_global *pll)
> {
> enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
>
> @@ -2158,7 +2158,7 @@ static void bxt_ddi_pll_disable(struct intel_display *display,
> }
>
> static bool bxt_ddi_pll_get_hw_state(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll_global *pll,
> struct intel_dpll_hw_state *dpll_hw_state)
> {
> struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
> @@ -2358,7 +2358,7 @@ static int bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
> }
>
> static int bxt_ddi_pll_get_freq(struct intel_display *display,
> - const struct intel_shared_dpll *pll,
> + const struct intel_dpll_global *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
> @@ -2427,7 +2427,7 @@ static int bxt_get_dpll(struct intel_atomic_state *state,
> struct intel_display *display = to_intel_display(state);
> struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> - struct intel_shared_dpll *pll;
> + struct intel_dpll_global *pll;
> enum intel_dpll_id id;
>
> /* 1:1 mapping between ports and PLLs */
> @@ -2440,7 +2440,7 @@ static int bxt_get_dpll(struct intel_atomic_state *state,
> intel_reference_shared_dpll(state, crtc,
> pll, &crtc_state->dpll_hw_state);
>
> - crtc_state->shared_dpll = pll;
> + crtc_state->dpll_global = pll;
>
> return 0;
> }
> @@ -2755,7 +2755,7 @@ static int icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
> }
>
> static int icl_ddi_tbt_pll_get_freq(struct intel_display *display,
> - const struct intel_shared_dpll *pll,
> + const struct intel_dpll_global *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> /*
> @@ -2826,7 +2826,7 @@ icl_calc_wrpll(struct intel_crtc_state *crtc_state,
> }
>
> static int icl_ddi_combo_pll_get_freq(struct intel_display *display,
> - const struct intel_shared_dpll *pll,
> + const struct intel_dpll_global *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
> @@ -3199,7 +3199,7 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
> }
>
> static int icl_ddi_mg_pll_get_freq(struct intel_display *display,
> - const struct intel_shared_dpll *pll,
> + const struct intel_dpll_global *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
> @@ -3285,7 +3285,7 @@ void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
> struct icl_port_dpll *port_dpll =
> &crtc_state->icl_port_dplls[port_dpll_id];
>
> - crtc_state->shared_dpll = port_dpll->pll;
> + crtc_state->dpll_global = port_dpll->pll;
> crtc_state->dpll_hw_state = port_dpll->hw_state;
> }
>
> @@ -3428,8 +3428,8 @@ static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state,
> return ret;
>
> /* this is mainly for the fastset check */
> - if (old_crtc_state->shared_dpll &&
> - old_crtc_state->shared_dpll->info->id == DPLL_ID_ICL_TBTPLL)
> + if (old_crtc_state->dpll_global &&
> + old_crtc_state->dpll_global->info->id == DPLL_ID_ICL_TBTPLL)
> icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);
> else
> icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_MG_PHY);
> @@ -3521,7 +3521,7 @@ static void icl_put_dplls(struct intel_atomic_state *state,
> intel_atomic_get_new_crtc_state(state, crtc);
> enum icl_port_dpll_id id;
>
> - new_crtc_state->shared_dpll = NULL;
> + new_crtc_state->dpll_global = NULL;
>
> for (id = ICL_PORT_DPLL_DEFAULT; id < ICL_PORT_DPLL_COUNT; id++) {
> const struct icl_port_dpll *old_port_dpll =
> @@ -3539,7 +3539,7 @@ static void icl_put_dplls(struct intel_atomic_state *state,
> }
>
> static bool mg_pll_get_hw_state(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll_global *pll,
> struct intel_dpll_hw_state *dpll_hw_state)
> {
> struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
> @@ -3606,7 +3606,7 @@ static bool mg_pll_get_hw_state(struct intel_display *display,
> }
>
> static bool dkl_pll_get_hw_state(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll_global *pll,
> struct intel_dpll_hw_state *dpll_hw_state)
> {
> struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
> @@ -3678,7 +3678,7 @@ static bool dkl_pll_get_hw_state(struct intel_display *display,
> }
>
> static bool icl_pll_get_hw_state(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll_global *pll,
> struct intel_dpll_hw_state *dpll_hw_state,
> i915_reg_t enable_reg)
> {
> @@ -3739,7 +3739,7 @@ static bool icl_pll_get_hw_state(struct intel_display *display,
> }
>
> static bool combo_pll_get_hw_state(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll_global *pll,
> struct intel_dpll_hw_state *dpll_hw_state)
> {
> i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
> @@ -3748,14 +3748,14 @@ static bool combo_pll_get_hw_state(struct intel_display *display,
> }
>
> static bool tbt_pll_get_hw_state(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll_global *pll,
> struct intel_dpll_hw_state *dpll_hw_state)
> {
> return icl_pll_get_hw_state(display, pll, dpll_hw_state, TBT_PLL_ENABLE);
> }
>
> static void icl_dpll_write(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll_global *pll,
> const struct icl_dpll_hw_state *hw_state)
> {
> const enum intel_dpll_id id = pll->info->id;
> @@ -3797,7 +3797,7 @@ static void icl_dpll_write(struct intel_display *display,
> }
>
> static void icl_mg_pll_write(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll_global *pll,
> const struct icl_dpll_hw_state *hw_state)
> {
> enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);
> @@ -3840,7 +3840,7 @@ static void icl_mg_pll_write(struct intel_display *display,
> }
>
> static void dkl_pll_write(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll_global *pll,
> const struct icl_dpll_hw_state *hw_state)
> {
> enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);
> @@ -3905,7 +3905,7 @@ static void dkl_pll_write(struct intel_display *display,
> }
>
> static void icl_pll_power_enable(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll_global *pll,
> i915_reg_t enable_reg)
> {
> intel_de_rmw(display, enable_reg, 0, PLL_POWER_ENABLE);
> @@ -3920,7 +3920,7 @@ static void icl_pll_power_enable(struct intel_display *display,
> }
>
> static void icl_pll_enable(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll_global *pll,
> i915_reg_t enable_reg)
> {
> intel_de_rmw(display, enable_reg, 0, PLL_ENABLE);
> @@ -3930,7 +3930,7 @@ static void icl_pll_enable(struct intel_display *display,
> drm_err(display->drm, "PLL %d not locked\n", pll->info->id);
> }
>
> -static void adlp_cmtg_clock_gating_wa(struct intel_display *display, struct intel_shared_dpll *pll)
> +static void adlp_cmtg_clock_gating_wa(struct intel_display *display, struct intel_dpll_global *pll)
> {
> u32 val;
>
> @@ -3955,7 +3955,7 @@ static void adlp_cmtg_clock_gating_wa(struct intel_display *display, struct inte
> }
>
> static void combo_pll_enable(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll_global *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
> @@ -3979,7 +3979,7 @@ static void combo_pll_enable(struct intel_display *display,
> }
>
> static void tbt_pll_enable(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll_global *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
> @@ -4000,7 +4000,7 @@ static void tbt_pll_enable(struct intel_display *display,
> }
>
> static void mg_pll_enable(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll_global *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
> @@ -4025,7 +4025,7 @@ static void mg_pll_enable(struct intel_display *display,
> }
>
> static void icl_pll_disable(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll_global *pll,
> i915_reg_t enable_reg)
> {
> /* The first steps are done by intel_ddi_post_disable(). */
> @@ -4056,7 +4056,7 @@ static void icl_pll_disable(struct intel_display *display,
> }
>
> static void combo_pll_disable(struct intel_display *display,
> - struct intel_shared_dpll *pll)
> + struct intel_dpll_global *pll)
> {
> i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
>
> @@ -4064,13 +4064,13 @@ static void combo_pll_disable(struct intel_display *display,
> }
>
> static void tbt_pll_disable(struct intel_display *display,
> - struct intel_shared_dpll *pll)
> + struct intel_dpll_global *pll)
> {
> icl_pll_disable(display, pll, TBT_PLL_ENABLE);
> }
>
> static void mg_pll_disable(struct intel_display *display,
> - struct intel_shared_dpll *pll)
> + struct intel_dpll_global *pll)
> {
> i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
>
> @@ -4347,19 +4347,19 @@ void intel_shared_dpll_init(struct intel_display *display)
>
> for (i = 0; dpll_info[i].name; i++) {
> if (drm_WARN_ON(display->drm,
> - i >= ARRAY_SIZE(display->dpll.shared_dplls)))
> + i >= ARRAY_SIZE(display->dpll.dpll_globals)))
> break;
>
> /* must fit into unsigned long bitmask on 32bit */
> if (drm_WARN_ON(display->drm, dpll_info[i].id >= 32))
> break;
>
> - display->dpll.shared_dplls[i].info = &dpll_info[i];
> - display->dpll.shared_dplls[i].index = i;
> + display->dpll.dpll_globals[i].info = &dpll_info[i];
> + display->dpll.dpll_globals[i].index = i;
> }
>
> display->dpll.mgr = dpll_mgr;
> - display->dpll.num_shared_dpll = i;
> + display->dpll.num_dpll_global = i;
> }
>
> /**
> @@ -4483,7 +4483,7 @@ void intel_update_active_dpll(struct intel_atomic_state *state,
> * Return the output frequency corresponding to @pll's passed in @dpll_hw_state.
> */
> int intel_dpll_get_freq(struct intel_display *display,
> - const struct intel_shared_dpll *pll,
> + const struct intel_dpll_global *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> if (drm_WARN_ON(display->drm, !pll->info->funcs->get_freq))
> @@ -4501,14 +4501,14 @@ int intel_dpll_get_freq(struct intel_display *display,
> * Read out @pll's hardware state into @dpll_hw_state.
> */
> bool intel_dpll_get_hw_state(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll_global *pll,
> struct intel_dpll_hw_state *dpll_hw_state)
> {
> return pll->info->funcs->get_hw_state(display, pll, dpll_hw_state);
> }
>
> static void readout_dpll_hw_state(struct intel_display *display,
> - struct intel_shared_dpll *pll)
> + struct intel_dpll_global *pll)
> {
> struct intel_crtc *crtc;
>
> @@ -4522,7 +4522,7 @@ static void readout_dpll_hw_state(struct intel_display *display,
> struct intel_crtc_state *crtc_state =
> to_intel_crtc_state(crtc->base.state);
>
> - if (crtc_state->hw.active && crtc_state->shared_dpll == pll)
> + if (crtc_state->hw.active && crtc_state->dpll_global == pll)
> intel_reference_shared_dpll_crtc(crtc, pll, &pll->state);
> }
> pll->active_mask = pll->state.pipe_mask;
> @@ -4540,7 +4540,7 @@ void intel_dpll_update_ref_clks(struct intel_display *display)
>
> void intel_dpll_readout_hw_state(struct intel_display *display)
> {
> - struct intel_shared_dpll *pll;
> + struct intel_dpll_global *pll;
> int i;
>
> for_each_dpll(display, pll, i)
> @@ -4548,7 +4548,7 @@ void intel_dpll_readout_hw_state(struct intel_display *display)
> }
>
> static void sanitize_dpll_state(struct intel_display *display,
> - struct intel_shared_dpll *pll)
> + struct intel_dpll_global *pll)
> {
> if (!pll->on)
> return;
> @@ -4567,7 +4567,7 @@ static void sanitize_dpll_state(struct intel_display *display,
>
> void intel_dpll_sanitize_state(struct intel_display *display)
> {
> - struct intel_shared_dpll *pll;
> + struct intel_dpll_global *pll;
> int i;
>
> intel_cx0_pll_power_save_wa(display);
> @@ -4624,7 +4624,7 @@ bool intel_dpll_compare_hw_state(struct intel_display *display,
>
> static void
> verify_single_dpll_state(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll_global *pll,
> struct intel_crtc *crtc,
> const struct intel_crtc_state *new_crtc_state)
> {
> @@ -4677,8 +4677,8 @@ verify_single_dpll_state(struct intel_display *display,
> pll->info->name);
> }
>
> -static bool has_alt_port_dpll(const struct intel_shared_dpll *old_pll,
> - const struct intel_shared_dpll *new_pll)
> +static bool has_alt_port_dpll(const struct intel_dpll_global *old_pll,
> + const struct intel_dpll_global *new_pll)
> {
> return old_pll && new_pll && old_pll != new_pll &&
> (old_pll->info->is_alt_port_dpll || new_pll->info->is_alt_port_dpll);
> @@ -4693,22 +4693,22 @@ void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
> const struct intel_crtc_state *new_crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
>
> - if (new_crtc_state->shared_dpll)
> - verify_single_dpll_state(display, new_crtc_state->shared_dpll,
> + if (new_crtc_state->dpll_global)
> + verify_single_dpll_state(display, new_crtc_state->dpll_global,
> crtc, new_crtc_state);
>
> - if (old_crtc_state->shared_dpll &&
> - old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {
> + if (old_crtc_state->dpll_global &&
> + old_crtc_state->dpll_global != new_crtc_state->dpll_global) {
> u8 pipe_mask = BIT(crtc->pipe);
> - struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
> + struct intel_dpll_global *pll = old_crtc_state->dpll_global;
>
> INTEL_DISPLAY_STATE_WARN(display, pll->active_mask & pipe_mask,
> "%s: pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n",
> pll->info->name, pipe_name(crtc->pipe), pll->active_mask);
>
> /* TC ports have both MG/TC and TBT PLL referenced simultaneously */
> - INTEL_DISPLAY_STATE_WARN(display, !has_alt_port_dpll(old_crtc_state->shared_dpll,
> - new_crtc_state->shared_dpll) &&
> + INTEL_DISPLAY_STATE_WARN(display, !has_alt_port_dpll(old_crtc_state->dpll_global,
> + new_crtc_state->dpll_global) &&
> pll->state.pipe_mask & pipe_mask,
> "%s: pll enabled crtcs mismatch (found pipe %c in enabled mask (0x%x))\n",
> pll->info->name, pipe_name(crtc->pipe), pll->state.pipe_mask);
> @@ -4718,7 +4718,7 @@ void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
> void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state)
> {
> struct intel_display *display = to_intel_display(state);
> - struct intel_shared_dpll *pll;
> + struct intel_dpll_global *pll;
> int i;
>
> for_each_dpll(display, pll, i)
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index 2080118be523..bd52e30d83bd 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -31,8 +31,8 @@
> #include "intel_wakeref.h"
>
> #define for_each_dpll(__display, __pll, __i) \
> - for ((__i) = 0; (__i) < (__display)->dpll.num_shared_dpll && \
> - ((__pll) = &(__display)->dpll.shared_dplls[(__i)]) ; (__i)++)
> + for ((__i) = 0; (__i) < (__display)->dpll.num_dpll_global && \
> + ((__pll) = &(__display)->dpll.dpll_globals[(__i)]) ; (__i)++)
>
> enum tc_port;
> struct drm_printer;
> @@ -344,9 +344,9 @@ struct dpll_info {
> };
>
> /**
> - * struct intel_shared_dpll - display PLL with tracked state and users
> + * struct intel_dpll_global - display PLL with tracked state and users
> */
> -struct intel_shared_dpll {
> +struct intel_dpll_global {
> /**
> * @state:
> *
> @@ -388,11 +388,11 @@ struct intel_shared_dpll {
> #define SKL_DPLL3 3
>
> /* shared dpll functions */
> -struct intel_shared_dpll *
> +struct intel_dpll_global *
> intel_get_shared_dpll_by_id(struct intel_display *display,
> enum intel_dpll_id id);
> void assert_shared_dpll(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll_global *pll,
> bool state);
> #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
> #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
> @@ -405,7 +405,7 @@ int intel_reserve_shared_dplls(struct intel_atomic_state *state,
> void intel_release_shared_dplls(struct intel_atomic_state *state,
> struct intel_crtc *crtc);
> void intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
> - const struct intel_shared_dpll *pll,
> + const struct intel_dpll_global *pll,
> struct intel_dpll_state *shared_dpll_state);
> void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
> enum icl_port_dpll_id port_dpll_id);
> @@ -413,10 +413,10 @@ void intel_update_active_dpll(struct intel_atomic_state *state,
> struct intel_crtc *crtc,
> struct intel_encoder *encoder);
> int intel_dpll_get_freq(struct intel_display *display,
> - const struct intel_shared_dpll *pll,
> + const struct intel_dpll_global *pll,
> const struct intel_dpll_hw_state *dpll_hw_state);
> bool intel_dpll_get_hw_state(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll_global *pll,
> struct intel_dpll_hw_state *dpll_hw_state);
> void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
> void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
> index 40deee0769ae..acc0b45eced0 100644
> --- a/drivers/gpu/drm/i915/display/intel_fdi.c
> +++ b/drivers/gpu/drm/i915/display/intel_fdi.c
> @@ -911,7 +911,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
> intel_de_write(display, FDI_RX_CTL(PIPE_A), rx_ctl_val);
>
> /* Configure Port Clock Select */
> - drm_WARN_ON(display->drm, crtc_state->shared_dpll->info->id != DPLL_ID_SPLL);
> + drm_WARN_ON(display->drm, crtc_state->dpll_global->info->id != DPLL_ID_SPLL);
> intel_ddi_enable_clock(encoder, crtc_state);
>
> /* Start the training iterating through available voltages and emphasis,
> diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
> index 89d26913e253..bc8725aa99da 100644
> --- a/drivers/gpu/drm/i915/display/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/display/intel_lvds.c
> @@ -251,7 +251,7 @@ static void intel_pre_enable_lvds(struct intel_atomic_state *state,
>
> if (HAS_PCH_SPLIT(i915)) {
> assert_fdi_rx_pll_disabled(display, pipe);
> - assert_shared_dpll_disabled(display, crtc_state->shared_dpll);
> + assert_shared_dpll_disabled(display, crtc_state->dpll_global);
> } else {
> assert_pll_disabled(display, pipe);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> index 3cc915739677..427eff400b53 100644
> --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> @@ -91,10 +91,10 @@ static void intel_crtc_disable_noatomic_begin(struct intel_crtc *crtc,
> crtc->active = false;
> crtc->base.enabled = false;
>
> - if (crtc_state->shared_dpll)
> + if (crtc_state->dpll_global)
> intel_unreference_shared_dpll_crtc(crtc,
> - crtc_state->shared_dpll,
> - &crtc_state->shared_dpll->state);
> + crtc_state->dpll_global,
> + &crtc_state->dpll_global->state);
> }
>
> static void set_encoder_for_connector(struct intel_connector *connector,
> @@ -568,7 +568,7 @@ static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
> */
> return IS_SANDYBRIDGE(i915) &&
> crtc_state->hw.active &&
> - crtc_state->shared_dpll &&
> + crtc_state->dpll_global &&
> crtc_state->port_clock == 0;
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
> index b909ed18a5b2..57303ecb77ad 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
> @@ -255,7 +255,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
> u32 val, pipeconf_val;
>
> /* Make sure PCH DPLL is enabled */
> - assert_shared_dpll_enabled(display, crtc_state->shared_dpll);
> + assert_shared_dpll_enabled(display, crtc_state->dpll_global);
>
> /* FDI must be feeding us bits for PCH ports */
> assert_fdi_tx_enabled(display, pipe);
> @@ -387,7 +387,7 @@ void ilk_pch_enable(struct intel_atomic_state *state,
> temp = intel_de_read(display, PCH_DPLL_SEL);
> temp |= TRANS_DPLL_ENABLE(pipe);
> sel = TRANS_DPLLB_SEL(pipe);
> - if (crtc_state->shared_dpll ==
> + if (crtc_state->dpll_global ==
> intel_get_shared_dpll_by_id(display, DPLL_ID_PCH_PLL_B))
> temp |= sel;
> else
> @@ -504,7 +504,7 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
> struct intel_display *display = to_intel_display(crtc_state);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - struct intel_shared_dpll *pll;
> + struct intel_dpll_global *pll;
> enum pipe pipe = crtc->pipe;
> enum intel_dpll_id pll_id;
> bool pll_active;
> @@ -536,8 +536,8 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
> pll_id = DPLL_ID_PCH_PLL_A;
> }
>
> - crtc_state->shared_dpll = intel_get_shared_dpll_by_id(display, pll_id);
> - pll = crtc_state->shared_dpll;
> + crtc_state->dpll_global = intel_get_shared_dpll_by_id(display, pll_id);
> + pll = crtc_state->dpll_global;
>
> pll_active = intel_dpll_get_hw_state(display, pll,
> &crtc_state->dpll_hw_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> index 611f3b8dffef..24e050d00db9 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> @@ -500,7 +500,7 @@ static void ilk_init_pch_refclk(struct intel_display *display)
> {
> struct drm_i915_private *dev_priv = to_i915(display->drm);
> struct intel_encoder *encoder;
> - struct intel_shared_dpll *pll;
> + struct intel_dpll_global *pll;
> int i;
> u32 val, final;
> bool has_lvds = false;
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 05/16] drm/i915/dpll: Move away from using shared dpll
2025-04-02 8:31 ` [PATCH 05/16] drm/i915/dpll: Move away from using shared dpll Suraj Kandpal
@ 2025-04-03 15:03 ` Jani Nikula
2025-04-03 15:17 ` Kandpal, Suraj
0 siblings, 1 reply; 31+ messages in thread
From: Jani Nikula @ 2025-04-03 15:03 UTC (permalink / raw)
To: Suraj Kandpal, intel-xe, intel-gfx
Cc: ankit.k.nautiyal, uma.shankar, mika.kahola, ville.syrjala,
Suraj Kandpal
On Wed, 02 Apr 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Rename functions to move away from using shared dpll in the dpll
> framework as much as possible since dpll may not always be shared.
>
> --v2
> -Use intel_dpll_global instead of global_dpll [Jani]
I regret I didn't perhaps think this through in my earlier review, or
didn't get the message across, but... why not just drop both shared and
global? Just dpll.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 14 +-
> drivers/gpu/drm/i915/display/intel_display.c | 8 +-
> .../drm/i915/display/intel_display_driver.c | 2 +-
> drivers/gpu/drm/i915/display/intel_dpll.c | 10 +-
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 150 +++++++++---------
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 32 ++--
> drivers/gpu/drm/i915/display/intel_lvds.c | 2 +-
> .../drm/i915/display/intel_modeset_setup.c | 2 +-
> .../drm/i915/display/intel_modeset_verify.c | 4 +-
> .../gpu/drm/i915/display/intel_pch_display.c | 14 +-
> 10 files changed, 119 insertions(+), 119 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index a8934ea5077d..3fe330bf2636 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1567,7 +1567,7 @@ _icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg,
>
> id = (intel_de_read(display, reg) & clk_sel_mask) >> clk_sel_shift;
>
> - return intel_get_shared_dpll_by_id(display, id);
> + return intel_get_dpll_global_by_id(display, id);
> }
>
> static void adls_ddi_enable_clock(struct intel_encoder *encoder,
> @@ -1721,7 +1721,7 @@ static struct intel_dpll_global *dg1_ddi_get_pll(struct intel_encoder *encoder)
> if (phy >= PHY_C)
> id += DPLL_ID_DG1_DPLL2;
>
> - return intel_get_shared_dpll_by_id(display, id);
> + return intel_get_dpll_global_by_id(display, id);
> }
>
> static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
> @@ -1893,7 +1893,7 @@ static struct intel_dpll_global *icl_ddi_tc_get_pll(struct intel_encoder *encode
> return NULL;
> }
>
> - return intel_get_shared_dpll_by_id(display, id);
> + return intel_get_dpll_global_by_id(display, id);
> }
>
> static struct intel_dpll_global *bxt_ddi_get_pll(struct intel_encoder *encoder)
> @@ -1916,7 +1916,7 @@ static struct intel_dpll_global *bxt_ddi_get_pll(struct intel_encoder *encoder)
> return NULL;
> }
>
> - return intel_get_shared_dpll_by_id(display, id);
> + return intel_get_dpll_global_by_id(display, id);
> }
>
> static void skl_ddi_enable_clock(struct intel_encoder *encoder,
> @@ -1984,7 +1984,7 @@ static struct intel_dpll_global *skl_ddi_get_pll(struct intel_encoder *encoder)
> id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >>
> DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port);
>
> - return intel_get_shared_dpll_by_id(display, id);
> + return intel_get_dpll_global_by_id(display, id);
> }
>
> void hsw_ddi_enable_clock(struct intel_encoder *encoder,
> @@ -2051,7 +2051,7 @@ static struct intel_dpll_global *hsw_ddi_get_pll(struct intel_encoder *encoder)
> return NULL;
> }
>
> - return intel_get_shared_dpll_by_id(display, id);
> + return intel_get_dpll_global_by_id(display, id);
> }
>
> void intel_ddi_enable_clock(struct intel_encoder *encoder,
> @@ -2758,7 +2758,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
> * 4. Enable the port PLL.
> *
> * The PLL enabling itself was already done before this function by
> - * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only
> + * hsw_crtc_enable()->intel_enable_dpll_global(). We need only
> * configure the PLL to port mapping here.
> */
> intel_ddi_enable_clock(encoder, crtc_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 5b808bad61e0..904b9544515b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1662,7 +1662,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
> intel_encoders_pre_pll_enable(state, crtc);
>
> if (new_crtc_state->dpll_global)
> - intel_enable_shared_dpll(new_crtc_state);
> + intel_enable_dpll_global(new_crtc_state);
>
> intel_encoders_pre_enable(state, crtc);
>
> @@ -1791,7 +1791,7 @@ static void hsw_crtc_disable(struct intel_atomic_state *state,
> intel_encoders_disable(state, crtc);
> intel_encoders_post_disable(state, crtc);
>
> - intel_disable_shared_dpll(old_crtc_state);
> + intel_disable_dpll_global(old_crtc_state);
>
> intel_encoders_post_pll_disable(state, crtc);
>
> @@ -6429,7 +6429,7 @@ int intel_atomic_check(struct drm_device *dev,
>
> any_ms = true;
>
> - intel_release_shared_dplls(state, crtc);
> + intel_release_dpll_globals(state, crtc);
> }
>
> if (any_ms && !check_digital_port_conflicts(state)) {
> @@ -7523,7 +7523,7 @@ static int intel_atomic_swap_state(struct intel_atomic_state *state)
>
> intel_atomic_swap_global_state(state);
>
> - intel_shared_dpll_swap_state(state);
> + intel_dpll_swap_state(state);
>
> intel_atomic_track_fbs(state);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
> index 4edadebad13b..b6c670c54eb1 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> @@ -441,7 +441,7 @@ int intel_display_driver_probe_nogem(struct intel_display *display)
> }
>
> intel_plane_possible_crtcs_init(display);
> - intel_shared_dpll_init(display);
> + intel_dpll_global_init(display);
> intel_fdi_pll_freq_update(display);
>
> intel_update_czclk(display);
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index c6d29382378b..04fb76a399ab 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -1162,7 +1162,7 @@ static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
> intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
> return 0;
>
> - ret = intel_compute_shared_dplls(state, crtc, encoder);
> + ret = intel_compute_dpll_globals(state, crtc, encoder);
> if (ret)
> return ret;
>
> @@ -1190,7 +1190,7 @@ static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state,
> intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
> return 0;
>
> - return intel_reserve_shared_dplls(state, crtc, encoder);
> + return intel_reserve_dpll_globals(state, crtc, encoder);
> }
>
> static int dg2_crtc_compute_clock(struct intel_atomic_state *state,
> @@ -1224,7 +1224,7 @@ static int mtl_crtc_compute_clock(struct intel_atomic_state *state,
> if (ret)
> return ret;
>
> - /* TODO: Do the readback via intel_compute_shared_dplls() */
> + /* TODO: Do the readback via intel_compute_dpll_globals() */
> crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll);
>
> crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
> @@ -1397,7 +1397,7 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
> ilk_compute_dpll(crtc_state, &crtc_state->dpll,
> &crtc_state->dpll);
>
> - ret = intel_compute_shared_dplls(state, crtc, NULL);
> + ret = intel_compute_dpll_globals(state, crtc, NULL);
> if (ret)
> return ret;
>
> @@ -1417,7 +1417,7 @@ static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state,
> if (!crtc_state->has_pch_encoder)
> return 0;
>
> - return intel_reserve_shared_dplls(state, crtc, NULL);
> + return intel_reserve_dpll_globals(state, crtc, NULL);
> }
>
> static u32 vlv_dpll(const struct intel_crtc_state *crtc_state)
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 833c90f3f0f1..e6546d735799 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -49,21 +49,21 @@
> * share a PLL if their configurations match.
> *
> * This file provides an abstraction over display PLLs. The function
> - * intel_shared_dpll_init() initializes the PLLs for the given platform. The
> + * intel_dpll_global_init() initializes the PLLs for the given platform. The
> * users of a PLL are tracked and that tracking is integrated with the atomic
> * modset interface. During an atomic operation, required PLLs can be reserved
> * for a given CRTC and encoder configuration by calling
> - * intel_reserve_shared_dplls() and previously reserved PLLs can be released
> - * with intel_release_shared_dplls().
> + * intel_reserve_dpll_globals() and previously reserved PLLs can be released
> + * with intel_release_dpll_globals().
> * Changes to the users are first staged in the atomic state, and then made
> - * effective by calling intel_shared_dpll_swap_state() during the atomic
> + * effective by calling intel_dpll_swap_state() during the atomic
> * commit phase.
> */
>
> /* platform specific hooks for managing DPLLs */
> struct intel_dpll_global_funcs {
> /*
> - * Hook for enabling the pll, called from intel_enable_shared_dpll() if
> + * Hook for enabling the pll, called from intel_enable_dpll_global() if
> * the pll is not already enabled.
> */
> void (*enable)(struct intel_display *display,
> @@ -71,7 +71,7 @@ struct intel_dpll_global_funcs {
> const struct intel_dpll_hw_state *dpll_hw_state);
>
> /*
> - * Hook for disabling the pll, called from intel_disable_shared_dpll()
> + * Hook for disabling the pll, called from intel_disable_dpll_global()
> * only when it is safe to disable the pll, i.e., there are no more
> * tracked users for it.
> */
> @@ -130,7 +130,7 @@ intel_atomic_duplicate_dpll_state(struct intel_display *display,
> }
>
> static struct intel_dpll_state *
> -intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
> +intel_atomic_get_dpll_global_state(struct drm_atomic_state *s)
> {
> struct intel_atomic_state *state = to_intel_atomic_state(s);
> struct intel_display *display = to_intel_display(state);
> @@ -148,7 +148,7 @@ intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
> }
>
> /**
> - * intel_get_shared_dpll_by_id - get a DPLL given its id
> + * intel_get_dpll_global_by_id - get a DPLL given its id
> * @display: intel_display device instance
> * @id: pll id
> *
> @@ -156,7 +156,7 @@ intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
> * A pointer to the DPLL with @id
> */
> struct intel_dpll_global *
> -intel_get_shared_dpll_by_id(struct intel_display *display,
> +intel_get_dpll_global_by_id(struct intel_display *display,
> enum intel_dpll_id id)
> {
> struct intel_dpll_global *pll;
> @@ -172,7 +172,7 @@ intel_get_shared_dpll_by_id(struct intel_display *display,
> }
>
> /* For ILK+ */
> -void assert_shared_dpll(struct intel_display *display,
> +void assert_dpll_global(struct intel_display *display,
> struct intel_dpll_global *pll,
> bool state)
> {
> @@ -247,12 +247,12 @@ static void _intel_disable_shared_dpll(struct intel_display *display,
> }
>
> /**
> - * intel_enable_shared_dpll - enable a CRTC's shared DPLL
> - * @crtc_state: CRTC, and its state, which has a shared DPLL
> + * intel_enable_dpll_global - enable a CRTC's global DPLL
> + * @crtc_state: CRTC, and its state, which has a DPLL
> *
> - * Enable the shared DPLL used by @crtc.
> + * Enable DPLL used by @crtc.
> */
> -void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
> +void intel_enable_dpll_global(const struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -279,7 +279,7 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
>
> if (old_mask) {
> drm_WARN_ON(display->drm, !pll->on);
> - assert_shared_dpll_enabled(display, pll);
> + assert_dpll_global_enabled(display, pll);
> goto out;
> }
> drm_WARN_ON(display->drm, pll->on);
> @@ -293,12 +293,12 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
> }
>
> /**
> - * intel_disable_shared_dpll - disable a CRTC's shared DPLL
> + * intel_disable_dpll_global - disable a CRTC's shared DPLL
> * @crtc_state: CRTC, and its state, which has a shared DPLL
> *
> - * Disable the shared DPLL used by @crtc.
> + * Disable DPLL used by @crtc.
> */
> -void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
> +void intel_disable_dpll_global(const struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -323,7 +323,7 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
> pll->info->name, pll->active_mask, pll->on,
> crtc->base.base.id, crtc->base.name);
>
> - assert_shared_dpll_enabled(display, pll);
> + assert_dpll_global_enabled(display, pll);
> drm_WARN_ON(display->drm, !pll->on);
>
> pll->active_mask &= ~pipe_mask;
> @@ -355,7 +355,7 @@ intel_dpll_mask_all(struct intel_display *display)
> }
>
> static struct intel_dpll_global *
> -intel_find_shared_dpll(struct intel_atomic_state *state,
> +intel_find_dpll_global(struct intel_atomic_state *state,
> const struct intel_crtc *crtc,
> const struct intel_dpll_hw_state *dpll_hw_state,
> unsigned long dpll_mask)
> @@ -366,14 +366,14 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
> struct intel_dpll_global *unused_pll = NULL;
> enum intel_dpll_id id;
>
> - dpll_state = intel_atomic_get_shared_dpll_state(&state->base);
> + dpll_state = intel_atomic_get_dpll_global_state(&state->base);
>
> drm_WARN_ON(display->drm, dpll_mask & ~dpll_mask_all);
>
> for_each_set_bit(id, &dpll_mask, fls(dpll_mask_all)) {
> struct intel_dpll_global *pll;
>
> - pll = intel_get_shared_dpll_by_id(display, id);
> + pll = intel_get_dpll_global_by_id(display, id);
> if (!pll)
> continue;
>
> @@ -409,7 +409,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
> }
>
> /**
> - * intel_reference_shared_dpll_crtc - Get a DPLL reference for a CRTC
> + * intel_reference_dpll_global_crtc - Get a DPLL reference for a CRTC
> * @crtc: CRTC on which behalf the reference is taken
> * @pll: DPLL for which the reference is taken
> * @dpll_state: the DPLL atomic state in which the reference is tracked
> @@ -417,7 +417,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
> * Take a reference for @pll tracking the use of it by @crtc.
> */
> static void
> -intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc,
> +intel_reference_dpll_global_crtc(const struct intel_crtc *crtc,
> const struct intel_dpll_global *pll,
> struct intel_dpll_state *dpll_state)
> {
> @@ -432,23 +432,23 @@ intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc,
> }
>
> static void
> -intel_reference_shared_dpll(struct intel_atomic_state *state,
> +intel_reference_dpll_global(struct intel_atomic_state *state,
> const struct intel_crtc *crtc,
> const struct intel_dpll_global *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> struct intel_dpll_state *dpll_state;
>
> - dpll_state = intel_atomic_get_shared_dpll_state(&state->base);
> + dpll_state = intel_atomic_get_dpll_global_state(&state->base);
>
> if (dpll_state[pll->index].pipe_mask == 0)
> dpll_state[pll->index].hw_state = *dpll_hw_state;
>
> - intel_reference_shared_dpll_crtc(crtc, pll, &dpll_state[pll->index]);
> + intel_reference_dpll_global_crtc(crtc, pll, &dpll_state[pll->index]);
> }
>
> /**
> - * intel_unreference_shared_dpll_crtc - Drop a DPLL reference for a CRTC
> + * intel_unreference_dpll_global_crtc - Drop a DPLL reference for a CRTC
> * @crtc: CRTC on which behalf the reference is dropped
> * @pll: DPLL for which the reference is dropped
> * @dpll_state: the DPLL atomic state in which the reference is tracked
> @@ -456,7 +456,7 @@ intel_reference_shared_dpll(struct intel_atomic_state *state,
> * Drop a reference for @pll tracking the end of use of it by @crtc.
> */
> void
> -intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
> +intel_unreference_dpll_global_crtc(const struct intel_crtc *crtc,
> const struct intel_dpll_global *pll,
> struct intel_dpll_state *dpll_state)
> {
> @@ -470,15 +470,15 @@ intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
> crtc->base.base.id, crtc->base.name, pll->info->name);
> }
>
> -static void intel_unreference_shared_dpll(struct intel_atomic_state *state,
> +static void intel_unreference_dpll_global(struct intel_atomic_state *state,
> const struct intel_crtc *crtc,
> const struct intel_dpll_global *pll)
> {
> struct intel_dpll_state *dpll_state;
>
> - dpll_state = intel_atomic_get_shared_dpll_state(&state->base);
> + dpll_state = intel_atomic_get_dpll_global_state(&state->base);
>
> - intel_unreference_shared_dpll_crtc(crtc, pll, &dpll_state[pll->index]);
> + intel_unreference_dpll_global_crtc(crtc, pll, &dpll_state[pll->index]);
> }
>
> static void intel_put_dpll(struct intel_atomic_state *state,
> @@ -494,11 +494,11 @@ static void intel_put_dpll(struct intel_atomic_state *state,
> if (!old_crtc_state->dpll_global)
> return;
>
> - intel_unreference_shared_dpll(state, crtc, old_crtc_state->dpll_global);
> + intel_unreference_dpll_global(state, crtc, old_crtc_state->dpll_global);
> }
>
> /**
> - * intel_shared_dpll_swap_state - make atomic DPLL configuration effective
> + * intel_dpll_swap_state - make atomic DPLL configuration effective
> * @state: atomic state
> *
> * This is the dpll version of drm_atomic_helper_swap_state() since the
> @@ -508,7 +508,7 @@ static void intel_put_dpll(struct intel_atomic_state *state,
> * i.e. it also puts the current state into @state, even though there is no
> * need for that at this moment.
> */
> -void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
> +void intel_dpll_swap_state(struct intel_atomic_state *state)
> {
> struct intel_display *display = to_intel_display(state);
> struct intel_dpll_state *dpll_state = state->dpll_state;
> @@ -618,14 +618,14 @@ static int ibx_get_dpll(struct intel_atomic_state *state,
> if (HAS_PCH_IBX(i915)) {
> /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
> id = (enum intel_dpll_id) crtc->pipe;
> - pll = intel_get_shared_dpll_by_id(display, id);
> + pll = intel_get_dpll_global_by_id(display, id);
>
> drm_dbg_kms(display->drm,
> "[CRTC:%d:%s] using pre-allocated %s\n",
> crtc->base.base.id, crtc->base.name,
> pll->info->name);
> } else {
> - pll = intel_find_shared_dpll(state, crtc,
> + pll = intel_find_dpll_global(state, crtc,
> &crtc_state->dpll_hw_state,
> BIT(DPLL_ID_PCH_PLL_B) |
> BIT(DPLL_ID_PCH_PLL_A));
> @@ -635,7 +635,7 @@ static int ibx_get_dpll(struct intel_atomic_state *state,
> return -EINVAL;
>
> /* reference the pll */
> - intel_reference_shared_dpll(state, crtc,
> + intel_reference_dpll_global(state, crtc,
> pll, &crtc_state->dpll_hw_state);
>
> crtc_state->dpll_global = pll;
> @@ -1064,7 +1064,7 @@ hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state,
> struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
>
> - return intel_find_shared_dpll(state, crtc,
> + return intel_find_dpll_global(state, crtc,
> &crtc_state->dpll_hw_state,
> BIT(DPLL_ID_WRPLL2) |
> BIT(DPLL_ID_WRPLL1));
> @@ -1111,7 +1111,7 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
> return NULL;
> }
>
> - pll = intel_get_shared_dpll_by_id(display, pll_id);
> + pll = intel_get_dpll_global_by_id(display, pll_id);
>
> if (!pll)
> return NULL;
> @@ -1167,7 +1167,7 @@ hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
> struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
>
> - return intel_find_shared_dpll(state, crtc, &crtc_state->dpll_hw_state,
> + return intel_find_dpll_global(state, crtc, &crtc_state->dpll_hw_state,
> BIT(DPLL_ID_SPLL));
> }
>
> @@ -1231,7 +1231,7 @@ static int hsw_get_dpll(struct intel_atomic_state *state,
> if (!pll)
> return -EINVAL;
>
> - intel_reference_shared_dpll(state, crtc,
> + intel_reference_dpll_global(state, crtc,
> pll, &crtc_state->dpll_hw_state);
>
> crtc_state->dpll_global = pll;
> @@ -1940,11 +1940,11 @@ static int skl_get_dpll(struct intel_atomic_state *state,
> struct intel_dpll_global *pll;
>
> if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> - pll = intel_find_shared_dpll(state, crtc,
> + pll = intel_find_dpll_global(state, crtc,
> &crtc_state->dpll_hw_state,
> BIT(DPLL_ID_SKL_DPLL0));
> else
> - pll = intel_find_shared_dpll(state, crtc,
> + pll = intel_find_dpll_global(state, crtc,
> &crtc_state->dpll_hw_state,
> BIT(DPLL_ID_SKL_DPLL3) |
> BIT(DPLL_ID_SKL_DPLL2) |
> @@ -1952,7 +1952,7 @@ static int skl_get_dpll(struct intel_atomic_state *state,
> if (!pll)
> return -EINVAL;
>
> - intel_reference_shared_dpll(state, crtc,
> + intel_reference_dpll_global(state, crtc,
> pll, &crtc_state->dpll_hw_state);
>
> crtc_state->dpll_global = pll;
> @@ -2432,12 +2432,12 @@ static int bxt_get_dpll(struct intel_atomic_state *state,
>
> /* 1:1 mapping between ports and PLLs */
> id = (enum intel_dpll_id) encoder->port;
> - pll = intel_get_shared_dpll_by_id(display, id);
> + pll = intel_get_dpll_global_by_id(display, id);
>
> drm_dbg_kms(display->drm, "[CRTC:%d:%s] using pre-allocated %s\n",
> crtc->base.base.id, crtc->base.name, pll->info->name);
>
> - intel_reference_shared_dpll(state, crtc,
> + intel_reference_dpll_global(state, crtc,
> pll, &crtc_state->dpll_hw_state);
>
> crtc_state->dpll_global = pll;
> @@ -3388,13 +3388,13 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
> /* Eliminate DPLLs from consideration if reserved by HTI */
> dpll_mask &= ~intel_hti_dpll_mask(display);
>
> - port_dpll->pll = intel_find_shared_dpll(state, crtc,
> + port_dpll->pll = intel_find_dpll_global(state, crtc,
> &port_dpll->hw_state,
> dpll_mask);
> if (!port_dpll->pll)
> return -EINVAL;
>
> - intel_reference_shared_dpll(state, crtc,
> + intel_reference_dpll_global(state, crtc,
> port_dpll->pll, &port_dpll->hw_state);
>
> icl_update_active_dpll(state, crtc, encoder);
> @@ -3452,25 +3452,25 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
> int ret;
>
> port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
> - port_dpll->pll = intel_find_shared_dpll(state, crtc,
> + port_dpll->pll = intel_find_dpll_global(state, crtc,
> &port_dpll->hw_state,
> BIT(DPLL_ID_ICL_TBTPLL));
> if (!port_dpll->pll)
> return -EINVAL;
> - intel_reference_shared_dpll(state, crtc,
> + intel_reference_dpll_global(state, crtc,
> port_dpll->pll, &port_dpll->hw_state);
>
>
> port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
> dpll_id = icl_tc_port_to_pll_id(intel_encoder_to_tc(encoder));
> - port_dpll->pll = intel_find_shared_dpll(state, crtc,
> + port_dpll->pll = intel_find_dpll_global(state, crtc,
> &port_dpll->hw_state,
> BIT(dpll_id));
> if (!port_dpll->pll) {
> ret = -EINVAL;
> goto err_unreference_tbt_pll;
> }
> - intel_reference_shared_dpll(state, crtc,
> + intel_reference_dpll_global(state, crtc,
> port_dpll->pll, &port_dpll->hw_state);
>
> icl_update_active_dpll(state, crtc, encoder);
> @@ -3479,7 +3479,7 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
>
> err_unreference_tbt_pll:
> port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
> - intel_unreference_shared_dpll(state, crtc, port_dpll->pll);
> + intel_unreference_dpll_global(state, crtc, port_dpll->pll);
>
> return ret;
> }
> @@ -3534,7 +3534,7 @@ static void icl_put_dplls(struct intel_atomic_state *state,
> if (!old_port_dpll->pll)
> continue;
>
> - intel_unreference_shared_dpll(state, crtc, old_port_dpll->pll);
> + intel_unreference_dpll_global(state, crtc, old_port_dpll->pll);
> }
> }
>
> @@ -4300,12 +4300,12 @@ static const struct intel_dpll_mgr adlp_pll_mgr = {
> };
>
> /**
> - * intel_shared_dpll_init - Initialize shared DPLLs
> + * intel_dpll_global_init - Initialize DPLLs
> * @display: intel_display device
> *
> - * Initialize shared DPLLs for @display.
> + * Initialize DPLLs for @display.
> */
> -void intel_shared_dpll_init(struct intel_display *display)
> +void intel_dpll_global_init(struct intel_display *display)
> {
> struct drm_i915_private *i915 = to_i915(display->drm);
> const struct intel_dpll_mgr *dpll_mgr = NULL;
> @@ -4363,7 +4363,7 @@ void intel_shared_dpll_init(struct intel_display *display)
> }
>
> /**
> - * intel_compute_shared_dplls - compute DPLL state CRTC and encoder combination
> + * intel_compute_dpll_globals - compute DPLL state CRTC and encoder combination
> * @state: atomic state
> * @crtc: CRTC to compute DPLLs for
> * @encoder: encoder
> @@ -4371,12 +4371,12 @@ void intel_shared_dpll_init(struct intel_display *display)
> * This function computes the DPLL state for the given CRTC and encoder.
> *
> * The new configuration in the atomic commit @state is made effective by
> - * calling intel_shared_dpll_swap_state().
> + * calling intel_dpll_swap_state().
> *
> * Returns:
> * 0 on success, negative error code on failure.
> */
> -int intel_compute_shared_dplls(struct intel_atomic_state *state,
> +int intel_compute_dpll_globals(struct intel_atomic_state *state,
> struct intel_crtc *crtc,
> struct intel_encoder *encoder)
> {
> @@ -4390,7 +4390,7 @@ int intel_compute_shared_dplls(struct intel_atomic_state *state,
> }
>
> /**
> - * intel_reserve_shared_dplls - reserve DPLLs for CRTC and encoder combination
> + * intel_reserve_dpll_globals - reserve DPLLs for CRTC and encoder combination
> * @state: atomic state
> * @crtc: CRTC to reserve DPLLs for
> * @encoder: encoder
> @@ -4400,16 +4400,16 @@ int intel_compute_shared_dplls(struct intel_atomic_state *state,
> * state.
> *
> * The new configuration in the atomic commit @state is made effective by
> - * calling intel_shared_dpll_swap_state().
> + * calling intel_dpll_swap_state().
> *
> * The reserved DPLLs should be released by calling
> - * intel_release_shared_dplls().
> + * intel_release_dpll_globals().
> *
> * Returns:
> * 0 if all required DPLLs were successfully reserved,
> * negative error code otherwise.
> */
> -int intel_reserve_shared_dplls(struct intel_atomic_state *state,
> +int intel_reserve_dpll_globals(struct intel_atomic_state *state,
> struct intel_crtc *crtc,
> struct intel_encoder *encoder)
> {
> @@ -4423,17 +4423,17 @@ int intel_reserve_shared_dplls(struct intel_atomic_state *state,
> }
>
> /**
> - * intel_release_shared_dplls - end use of DPLLs by CRTC in atomic state
> + * intel_release_dpll_globals - end use of DPLLs by CRTC in atomic state
> * @state: atomic state
> * @crtc: crtc from which the DPLLs are to be released
> *
> - * This function releases all DPLLs reserved by intel_reserve_shared_dplls()
> + * This function releases all DPLLs reserved by intel_reserve_dpll_globals()
> * from the current atomic commit @state and the old @crtc atomic state.
> *
> * The new configuration in the atomic commit @state is made effective by
> - * calling intel_shared_dpll_swap_state().
> + * calling intel_dpll_swap_state().
> */
> -void intel_release_shared_dplls(struct intel_atomic_state *state,
> +void intel_release_dpll_globals(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> struct intel_display *display = to_intel_display(state);
> @@ -4442,7 +4442,7 @@ void intel_release_shared_dplls(struct intel_atomic_state *state,
> /*
> * FIXME: this function is called for every platform having a
> * compute_clock hook, even though the platform doesn't yet support
> - * the shared DPLL framework and intel_reserve_shared_dplls() is not
> + * the global DPLL framework and intel_reserve_dpll_globals() is not
> * called on those.
> */
> if (!dpll_mgr)
> @@ -4458,7 +4458,7 @@ void intel_release_shared_dplls(struct intel_atomic_state *state,
> * @encoder: encoder determining the type of port DPLL
> *
> * Update the active DPLL for the given @crtc/@encoder in @crtc's atomic state,
> - * from the port DPLLs reserved previously by intel_reserve_shared_dplls(). The
> + * from the port DPLLs reserved previously by intel_reserve_dpll_globals(). The
> * DPLL selected will be based on the current mode of the encoder's port.
> */
> void intel_update_active_dpll(struct intel_atomic_state *state,
> @@ -4523,7 +4523,7 @@ static void readout_dpll_hw_state(struct intel_display *display,
> to_intel_crtc_state(crtc->base.state);
>
> if (crtc_state->hw.active && crtc_state->dpll_global == pll)
> - intel_reference_shared_dpll_crtc(crtc, pll, &pll->state);
> + intel_reference_dpll_global_crtc(crtc, pll, &pll->state);
> }
> pll->active_mask = pll->state.pipe_mask;
>
> @@ -4684,8 +4684,8 @@ static bool has_alt_port_dpll(const struct intel_dpll_global *old_pll,
> (old_pll->info->is_alt_port_dpll || new_pll->info->is_alt_port_dpll);
> }
>
> -void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
> - struct intel_crtc *crtc)
> +void intel_dpll_state_verify(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> struct intel_display *display = to_intel_display(state);
> const struct intel_crtc_state *old_crtc_state =
> @@ -4715,7 +4715,7 @@ void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
> }
> }
>
> -void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state)
> +void intel_dpll_global_verify_disabled(struct intel_atomic_state *state)
> {
> struct intel_display *display = to_intel_display(state);
> struct intel_dpll_global *pll;
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index bd52e30d83bd..6215da164ffc 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -387,24 +387,24 @@ struct intel_dpll_global {
> #define SKL_DPLL2 2
> #define SKL_DPLL3 3
>
> -/* shared dpll functions */
> +/* global dpll functions */
> struct intel_dpll_global *
> -intel_get_shared_dpll_by_id(struct intel_display *display,
> +intel_get_dpll_global_by_id(struct intel_display *display,
> enum intel_dpll_id id);
> -void assert_shared_dpll(struct intel_display *display,
> +void assert_dpll_global(struct intel_display *display,
> struct intel_dpll_global *pll,
> bool state);
> -#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
> -#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
> -int intel_compute_shared_dplls(struct intel_atomic_state *state,
> +#define assert_dpll_global_enabled(d, p) assert_dpll_global(d, p, true)
> +#define assert_dpll_global_disabled(d, p) assert_dpll_global(d, p, false)
> +int intel_compute_dpll_globals(struct intel_atomic_state *state,
> struct intel_crtc *crtc,
> struct intel_encoder *encoder);
> -int intel_reserve_shared_dplls(struct intel_atomic_state *state,
> +int intel_reserve_dpll_globals(struct intel_atomic_state *state,
> struct intel_crtc *crtc,
> struct intel_encoder *encoder);
> -void intel_release_shared_dplls(struct intel_atomic_state *state,
> +void intel_release_dpll_globals(struct intel_atomic_state *state,
> struct intel_crtc *crtc);
> -void intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
> +void intel_unreference_dpll_global_crtc(const struct intel_crtc *crtc,
> const struct intel_dpll_global *pll,
> struct intel_dpll_state *shared_dpll_state);
> void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
> @@ -418,10 +418,10 @@ int intel_dpll_get_freq(struct intel_display *display,
> bool intel_dpll_get_hw_state(struct intel_display *display,
> struct intel_dpll_global *pll,
> struct intel_dpll_hw_state *dpll_hw_state);
> -void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
> -void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
> -void intel_shared_dpll_swap_state(struct intel_atomic_state *state);
> -void intel_shared_dpll_init(struct intel_display *display);
> +void intel_enable_dpll_global(const struct intel_crtc_state *crtc_state);
> +void intel_disable_dpll_global(const struct intel_crtc_state *crtc_state);
> +void intel_dpll_swap_state(struct intel_atomic_state *state);
> +void intel_dpll_global_init(struct intel_display *display);
> void intel_dpll_update_ref_clks(struct intel_display *display);
> void intel_dpll_readout_hw_state(struct intel_display *display);
> void intel_dpll_sanitize_state(struct intel_display *display);
> @@ -435,8 +435,8 @@ bool intel_dpll_compare_hw_state(struct intel_display *display,
> enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);
> bool intel_dpll_is_combophy(enum intel_dpll_id id);
>
> -void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
> - struct intel_crtc *crtc);
> -void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state);
> +void intel_dpll_state_verify(struct intel_atomic_state *state,
> + struct intel_crtc *crtc);
> +void intel_dpll_global_verify_disabled(struct intel_atomic_state *state);
>
> #endif /* _INTEL_DPLL_MGR_H_ */
> diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
> index bc8725aa99da..52f61a120b70 100644
> --- a/drivers/gpu/drm/i915/display/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/display/intel_lvds.c
> @@ -251,7 +251,7 @@ static void intel_pre_enable_lvds(struct intel_atomic_state *state,
>
> if (HAS_PCH_SPLIT(i915)) {
> assert_fdi_rx_pll_disabled(display, pipe);
> - assert_shared_dpll_disabled(display, crtc_state->dpll_global);
> + assert_dpll_global_disabled(display, crtc_state->dpll_global);
> } else {
> assert_pll_disabled(display, pipe);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> index 427eff400b53..4221d1566c8a 100644
> --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> @@ -92,7 +92,7 @@ static void intel_crtc_disable_noatomic_begin(struct intel_crtc *crtc,
> crtc->base.enabled = false;
>
> if (crtc_state->dpll_global)
> - intel_unreference_shared_dpll_crtc(crtc,
> + intel_unreference_dpll_global_crtc(crtc,
> crtc_state->dpll_global,
> &crtc_state->dpll_global->state);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> index a008412fdd04..eb080a1d8a42 100644
> --- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> +++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> @@ -246,7 +246,7 @@ void intel_modeset_verify_crtc(struct intel_atomic_state *state,
> intel_wm_state_verify(state, crtc);
> verify_connector_state(state, crtc);
> verify_crtc_state(state, crtc);
> - intel_shared_dpll_state_verify(state, crtc);
> + intel_dpll_state_verify(state, crtc);
> intel_mpllb_state_verify(state, crtc);
> intel_cx0pll_state_verify(state, crtc);
> }
> @@ -255,5 +255,5 @@ void intel_modeset_verify_disabled(struct intel_atomic_state *state)
> {
> verify_encoder_state(state);
> verify_connector_state(state, NULL);
> - intel_shared_dpll_verify_disabled(state);
> + intel_dpll_global_verify_disabled(state);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
> index 57303ecb77ad..aa39d0fb1e23 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
> @@ -255,7 +255,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
> u32 val, pipeconf_val;
>
> /* Make sure PCH DPLL is enabled */
> - assert_shared_dpll_enabled(display, crtc_state->dpll_global);
> + assert_dpll_global_enabled(display, crtc_state->dpll_global);
>
> /* FDI must be feeding us bits for PCH ports */
> assert_fdi_tx_enabled(display, pipe);
> @@ -388,7 +388,7 @@ void ilk_pch_enable(struct intel_atomic_state *state,
> temp |= TRANS_DPLL_ENABLE(pipe);
> sel = TRANS_DPLLB_SEL(pipe);
> if (crtc_state->dpll_global ==
> - intel_get_shared_dpll_by_id(display, DPLL_ID_PCH_PLL_B))
> + intel_get_dpll_global_by_id(display, DPLL_ID_PCH_PLL_B))
> temp |= sel;
> else
> temp &= ~sel;
> @@ -400,11 +400,11 @@ void ilk_pch_enable(struct intel_atomic_state *state,
> * transcoder, and we actually should do this to not upset any PCH
> * transcoder that already use the clock when we share it.
> *
> - * Note that enable_shared_dpll tries to do the right thing, but
> - * get_shared_dpll unconditionally resets the pll - we need that
> + * Note that enable_dpll_global tries to do the right thing, but
> + * get_dpll_global unconditionally resets the pll - we need that
> * to have the right LVDS enable sequence.
> */
> - intel_enable_shared_dpll(crtc_state);
> + intel_enable_dpll_global(crtc_state);
>
> /* set transcoder timing, panel must allow it */
> assert_pps_unlocked(display, pipe);
> @@ -479,7 +479,7 @@ void ilk_pch_post_disable(struct intel_atomic_state *state,
>
> ilk_fdi_pll_disable(crtc);
>
> - intel_disable_shared_dpll(old_crtc_state);
> + intel_disable_dpll_global(old_crtc_state);
> }
>
> static void ilk_pch_clock_get(struct intel_crtc_state *crtc_state)
> @@ -536,7 +536,7 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
> pll_id = DPLL_ID_PCH_PLL_A;
> }
>
> - crtc_state->dpll_global = intel_get_shared_dpll_by_id(display, pll_id);
> + crtc_state->dpll_global = intel_get_dpll_global_by_id(display, pll_id);
> pll = crtc_state->dpll_global;
>
> pll_active = intel_dpll_get_hw_state(display, pll,
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 31+ messages in thread
* RE: [PATCH 03/16] drm/i915/dpll: Rename intel_shared_dpll_funcs
2025-04-03 14:59 ` Jani Nikula
@ 2025-04-03 15:11 ` Kandpal, Suraj
0 siblings, 0 replies; 31+ messages in thread
From: Kandpal, Suraj @ 2025-04-03 15:11 UTC (permalink / raw)
To: Nikula, Jani, intel-xe@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org
Cc: Nautiyal, Ankit K, Shankar, Uma, Kahola, Mika, Syrjala, Ville
> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Thursday, April 3, 2025 8:29 PM
> To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-xe@lists.freedesktop.org;
> intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Shankar, Uma
> <uma.shankar@intel.com>; Kahola, Mika <mika.kahola@intel.com>; Syrjala,
> Ville <ville.syrjala@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>
> Subject: Re: [PATCH 03/16] drm/i915/dpll: Rename intel_shared_dpll_funcs
>
> On Wed, 02 Apr 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> > Rename intel_shared_dpll_funcs to intel_global_dpll_funcs since it
> > needs to represent both shared and individual dplls.
> >
> > --v2
> > -Change intel_global_dpll to intel_dpll_global to be more in line with
> > the naming standard where the name should start with the file name
> > [Jani]
>
> Though I'm not sure what we need the "global" for. Just intel_dpll_funcs?
Reason being intel_dpll_funcs already exist
Regards,
Suraj Kandpal
>
> >
> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 24
> > +++++++++---------- drivers/gpu/drm/i915/display/intel_dpll_mgr.h |
> > 4 ++--
> > 2 files changed, 14 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > index bbb51119ef5b..92ca2a544e2f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > @@ -61,7 +61,7 @@
> > */
> >
> > /* platform specific hooks for managing DPLLs */ -struct
> > intel_shared_dpll_funcs {
> > +struct intel_dpll_global_funcs {
> > /*
> > * Hook for enabling the pll, called from intel_enable_shared_dpll() if
> > * the pll is not already enabled.
> > @@ -668,7 +668,7 @@ static bool ibx_compare_hw_state(const struct
> intel_dpll_hw_state *_a,
> > a->fp1 == b->fp1;
> > }
> >
> > -static const struct intel_shared_dpll_funcs ibx_pch_dpll_funcs = {
> > +static const struct intel_dpll_global_funcs ibx_pch_dpll_funcs = {
> > .enable = ibx_pch_dpll_enable,
> > .disable = ibx_pch_dpll_disable,
> > .get_hw_state = ibx_pch_dpll_get_hw_state, @@ -1268,14 +1268,14
> @@
> > static bool hsw_compare_hw_state(const struct intel_dpll_hw_state *_a,
> > a->spll == b->spll;
> > }
> >
> > -static const struct intel_shared_dpll_funcs hsw_ddi_wrpll_funcs = {
> > +static const struct intel_dpll_global_funcs hsw_ddi_wrpll_funcs = {
> > .enable = hsw_ddi_wrpll_enable,
> > .disable = hsw_ddi_wrpll_disable,
> > .get_hw_state = hsw_ddi_wrpll_get_hw_state,
> > .get_freq = hsw_ddi_wrpll_get_freq,
> > };
> >
> > -static const struct intel_shared_dpll_funcs hsw_ddi_spll_funcs = {
> > +static const struct intel_dpll_global_funcs hsw_ddi_spll_funcs = {
> > .enable = hsw_ddi_spll_enable,
> > .disable = hsw_ddi_spll_disable,
> > .get_hw_state = hsw_ddi_spll_get_hw_state, @@ -1300,7 +1300,7 @@
> > static bool hsw_ddi_lcpll_get_hw_state(struct intel_display *display,
> > return true;
> > }
> >
> > -static const struct intel_shared_dpll_funcs hsw_ddi_lcpll_funcs = {
> > +static const struct intel_dpll_global_funcs hsw_ddi_lcpll_funcs = {
> > .enable = hsw_ddi_lcpll_enable,
> > .disable = hsw_ddi_lcpll_disable,
> > .get_hw_state = hsw_ddi_lcpll_get_hw_state, @@ -2002,14 +2002,14
> @@
> > static bool skl_compare_hw_state(const struct intel_dpll_hw_state *_a,
> > a->cfgcr2 == b->cfgcr2;
> > }
> >
> > -static const struct intel_shared_dpll_funcs skl_ddi_pll_funcs = {
> > +static const struct intel_dpll_global_funcs skl_ddi_pll_funcs = {
> > .enable = skl_ddi_pll_enable,
> > .disable = skl_ddi_pll_disable,
> > .get_hw_state = skl_ddi_pll_get_hw_state,
> > .get_freq = skl_ddi_pll_get_freq,
> > };
> >
> > -static const struct intel_shared_dpll_funcs skl_ddi_dpll0_funcs = {
> > +static const struct intel_dpll_global_funcs skl_ddi_dpll0_funcs = {
> > .enable = skl_ddi_dpll0_enable,
> > .disable = skl_ddi_dpll0_disable,
> > .get_hw_state = skl_ddi_dpll0_get_hw_state, @@ -2484,7 +2484,7
> @@
> > static bool bxt_compare_hw_state(const struct intel_dpll_hw_state *_a,
> > a->pcsdw12 == b->pcsdw12;
> > }
> >
> > -static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = {
> > +static const struct intel_dpll_global_funcs bxt_ddi_pll_funcs = {
> > .enable = bxt_ddi_pll_enable,
> > .disable = bxt_ddi_pll_disable,
> > .get_hw_state = bxt_ddi_pll_get_hw_state, @@ -4129,21 +4129,21
> @@
> > static bool icl_compare_hw_state(const struct intel_dpll_hw_state *_a,
> > a->mg_pll_tdc_coldst_bias == b->mg_pll_tdc_coldst_bias; }
> >
> > -static const struct intel_shared_dpll_funcs combo_pll_funcs = {
> > +static const struct intel_dpll_global_funcs combo_pll_funcs = {
> > .enable = combo_pll_enable,
> > .disable = combo_pll_disable,
> > .get_hw_state = combo_pll_get_hw_state,
> > .get_freq = icl_ddi_combo_pll_get_freq, };
> >
> > -static const struct intel_shared_dpll_funcs tbt_pll_funcs = {
> > +static const struct intel_dpll_global_funcs tbt_pll_funcs = {
> > .enable = tbt_pll_enable,
> > .disable = tbt_pll_disable,
> > .get_hw_state = tbt_pll_get_hw_state,
> > .get_freq = icl_ddi_tbt_pll_get_freq, };
> >
> > -static const struct intel_shared_dpll_funcs mg_pll_funcs = {
> > +static const struct intel_dpll_global_funcs mg_pll_funcs = {
> > .enable = mg_pll_enable,
> > .disable = mg_pll_disable,
> > .get_hw_state = mg_pll_get_hw_state, @@ -4191,7 +4191,7 @@ static
> > const struct intel_dpll_mgr ehl_pll_mgr = {
> > .compare_hw_state = icl_compare_hw_state, };
> >
> > -static const struct intel_shared_dpll_funcs dkl_pll_funcs = {
> > +static const struct intel_dpll_global_funcs dkl_pll_funcs = {
> > .enable = mg_pll_enable,
> > .disable = mg_pll_disable,
> > .get_hw_state = dkl_pll_get_hw_state, diff --git
> > a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > index d93072486831..2080118be523 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > @@ -41,7 +41,7 @@ struct intel_crtc;
> > struct intel_crtc_state;
> > struct intel_encoder;
> > struct intel_shared_dpll;
> > -struct intel_shared_dpll_funcs;
> > +struct intel_dpll_global_funcs;
> >
> > /**
> > * enum intel_dpll_id - possible DPLL ids @@ -314,7 +314,7 @@ struct
> > dpll_info {
> > /**
> > * @funcs: platform specific hooks
> > */
> > - const struct intel_shared_dpll_funcs *funcs;
> > + const struct intel_dpll_global_funcs *funcs;
> >
> > /**
> > * @id: unique identifier for this DPLL
>
> --
> Jani Nikula, Intel
^ permalink raw reply [flat|nested] 31+ messages in thread
* RE: [PATCH 04/16] drm/i915/dpll: Rename intel_shared_dpll
2025-04-03 15:01 ` Jani Nikula
@ 2025-04-03 15:15 ` Kandpal, Suraj
0 siblings, 0 replies; 31+ messages in thread
From: Kandpal, Suraj @ 2025-04-03 15:15 UTC (permalink / raw)
To: Nikula, Jani, intel-xe@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org
Cc: Nautiyal, Ankit K, Shankar, Uma, Kahola, Mika, Syrjala, Ville
> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Thursday, April 3, 2025 8:32 PM
> To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-xe@lists.freedesktop.org;
> intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Shankar, Uma
> <uma.shankar@intel.com>; Kahola, Mika <mika.kahola@intel.com>; Syrjala,
> Ville <ville.syrjala@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>
> Subject: Re: [PATCH 04/16] drm/i915/dpll: Rename intel_shared_dpll
>
> On Wed, 02 Apr 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> > Rename intel_shared_dpll to intel_dpll_global to represent both
> > shared and individual dplls. Since from MTL each PHY has it's
> > own PLL making the shared PLL naming a little outdated. In an
> > effort to make this framework accepting of future changes this
> > needs to be done.
> >
> > --v2
> > -Use intel_dpll_global to make sure names start with the filename
> > [Jani/Ville]
> > -Explain the need of this rename [Jani]
>
> Here too, why not just struct intel_dpll?
>
> I get that it's used in intel_display_core.h but it's a single user
> that's less important and could be renamed there.
So make intel_shared_dpll to intel_dpll and maybe intel_dpll to intel_dpll_global sounds better than
Also seeing the comment intel_dpll has it does seem like it tracks a global state of intel dpll
"
/*
* dpll and cdclk state is protected by connection_mutex dpll.lock serializes
* intel_{prepare,enable,disable}_shared_dpll. Must be global rather than per
* dpll, because on some platforms plls share registers.
*/
"
Regards,
Suraj Kandpal
>
>
> >
> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_ddi.c | 52 ++--
> > drivers/gpu/drm/i915/display/intel_ddi.h | 6 +-
> > drivers/gpu/drm/i915/display/intel_display.c | 12 +-
> > .../gpu/drm/i915/display/intel_display_core.h | 4 +-
> > .../drm/i915/display/intel_display_debugfs.c | 2 +-
> > .../drm/i915/display/intel_display_types.h | 6 +-
> > drivers/gpu/drm/i915/display/intel_dpll.c | 4 +-
> > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 228 +++++++++---------
> > drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 18 +-
> > drivers/gpu/drm/i915/display/intel_fdi.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_lvds.c | 2 +-
> > .../drm/i915/display/intel_modeset_setup.c | 8 +-
> > .../gpu/drm/i915/display/intel_pch_display.c | 10 +-
> > .../gpu/drm/i915/display/intel_pch_refclk.c | 2 +-
> > 15 files changed, 179 insertions(+), 179 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> > index b69c713fb79a..97c20c493e4d 100644
> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> > @@ -658,7 +658,7 @@ static void gen11_dsi_map_pll(struct intel_encoder
> *encoder,
> > {
> > struct intel_display *display = to_intel_display(encoder);
> > struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> > - struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> > + struct intel_dpll_global *pll = crtc_state->dpll_global;
> > enum phy phy;
> > u32 val;
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 56068b2ef964..a8934ea5077d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -234,7 +234,7 @@ static void intel_wait_ddi_buf_active(struct
> intel_encoder *encoder)
> > port_name(port));
> > }
> >
> > -static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
> > +static u32 hsw_pll_to_ddi_pll_sel(const struct intel_dpll_global *pll)
> > {
> > switch (pll->info->id) {
> > case DPLL_ID_WRPLL1:
> > @@ -258,7 +258,7 @@ static u32 hsw_pll_to_ddi_pll_sel(const struct
> intel_shared_dpll *pll)
> > static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
> > const struct intel_crtc_state *crtc_state)
> > {
> > - const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> > + const struct intel_dpll_global *pll = crtc_state->dpll_global;
> > int clock = crtc_state->port_clock;
> > const enum intel_dpll_id id = pll->info->id;
> >
> > @@ -1559,7 +1559,7 @@ static bool _icl_ddi_is_clock_enabled(struct
> intel_display *display, i915_reg_t
> > return !(intel_de_read(display, reg) & clk_off);
> > }
> >
> > -static struct intel_shared_dpll *
> > +static struct intel_dpll_global *
> > _icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg,
> > u32 clk_sel_mask, u32 clk_sel_shift)
> > {
> > @@ -1574,7 +1574,7 @@ static void adls_ddi_enable_clock(struct
> intel_encoder *encoder,
> > const struct intel_crtc_state *crtc_state)
> > {
> > struct intel_display *display = to_intel_display(encoder);
> > - const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> > + const struct intel_dpll_global *pll = crtc_state->dpll_global;
> > enum phy phy = intel_encoder_to_phy(encoder);
> >
> > if (drm_WARN_ON(display->drm, !pll))
> > @@ -1604,7 +1604,7 @@ static bool adls_ddi_is_clock_enabled(struct
> intel_encoder *encoder)
> >
> ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
> > }
> >
> > -static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder
> *encoder)
> > +static struct intel_dpll_global *adls_ddi_get_pll(struct intel_encoder
> *encoder)
> > {
> > struct intel_display *display = to_intel_display(encoder);
> > enum phy phy = intel_encoder_to_phy(encoder);
> > @@ -1618,7 +1618,7 @@ static void rkl_ddi_enable_clock(struct
> intel_encoder *encoder,
> > const struct intel_crtc_state *crtc_state)
> > {
> > struct intel_display *display = to_intel_display(encoder);
> > - const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> > + const struct intel_dpll_global *pll = crtc_state->dpll_global;
> > enum phy phy = intel_encoder_to_phy(encoder);
> >
> > if (drm_WARN_ON(display->drm, !pll))
> > @@ -1648,7 +1648,7 @@ static bool rkl_ddi_is_clock_enabled(struct
> intel_encoder *encoder)
> >
> RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
> > }
> >
> > -static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder
> *encoder)
> > +static struct intel_dpll_global *rkl_ddi_get_pll(struct intel_encoder
> *encoder)
> > {
> > struct intel_display *display = to_intel_display(encoder);
> > enum phy phy = intel_encoder_to_phy(encoder);
> > @@ -1662,7 +1662,7 @@ static void dg1_ddi_enable_clock(struct
> intel_encoder *encoder,
> > const struct intel_crtc_state *crtc_state)
> > {
> > struct intel_display *display = to_intel_display(encoder);
> > - const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> > + const struct intel_dpll_global *pll = crtc_state->dpll_global;
> > enum phy phy = intel_encoder_to_phy(encoder);
> >
> > if (drm_WARN_ON(display->drm, !pll))
> > @@ -1701,7 +1701,7 @@ static bool dg1_ddi_is_clock_enabled(struct
> intel_encoder *encoder)
> >
> DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
> > }
> >
> > -static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder
> *encoder)
> > +static struct intel_dpll_global *dg1_ddi_get_pll(struct intel_encoder
> *encoder)
> > {
> > struct intel_display *display = to_intel_display(encoder);
> > enum phy phy = intel_encoder_to_phy(encoder);
> > @@ -1728,7 +1728,7 @@ static void icl_ddi_combo_enable_clock(struct
> intel_encoder *encoder,
> > const struct intel_crtc_state *crtc_state)
> > {
> > struct intel_display *display = to_intel_display(encoder);
> > - const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> > + const struct intel_dpll_global *pll = crtc_state->dpll_global;
> > enum phy phy = intel_encoder_to_phy(encoder);
> >
> > if (drm_WARN_ON(display->drm, !pll))
> > @@ -1758,7 +1758,7 @@ static bool icl_ddi_combo_is_clock_enabled(struct
> intel_encoder *encoder)
> >
> ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
> > }
> >
> > -struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder
> *encoder)
> > +struct intel_dpll_global *icl_ddi_combo_get_pll(struct intel_encoder
> *encoder)
> > {
> > struct intel_display *display = to_intel_display(encoder);
> > enum phy phy = intel_encoder_to_phy(encoder);
> > @@ -1772,7 +1772,7 @@ static void jsl_ddi_tc_enable_clock(struct
> intel_encoder *encoder,
> > const struct intel_crtc_state *crtc_state)
> > {
> > struct intel_display *display = to_intel_display(encoder);
> > - const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> > + const struct intel_dpll_global *pll = crtc_state->dpll_global;
> > enum port port = encoder->port;
> >
> > if (drm_WARN_ON(display->drm, !pll))
> > @@ -1815,7 +1815,7 @@ static void icl_ddi_tc_enable_clock(struct
> intel_encoder *encoder,
> > const struct intel_crtc_state *crtc_state)
> > {
> > struct intel_display *display = to_intel_display(encoder);
> > - const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> > + const struct intel_dpll_global *pll = crtc_state->dpll_global;
> > enum tc_port tc_port = intel_encoder_to_tc(encoder);
> > enum port port = encoder->port;
> >
> > @@ -1866,7 +1866,7 @@ static bool icl_ddi_tc_is_clock_enabled(struct
> intel_encoder *encoder)
> > return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));
> > }
> >
> > -static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder
> *encoder)
> > +static struct intel_dpll_global *icl_ddi_tc_get_pll(struct intel_encoder
> *encoder)
> > {
> > struct intel_display *display = to_intel_display(encoder);
> > enum tc_port tc_port = intel_encoder_to_tc(encoder);
> > @@ -1896,7 +1896,7 @@ static struct intel_shared_dpll
> *icl_ddi_tc_get_pll(struct intel_encoder *encode
> > return intel_get_shared_dpll_by_id(display, id);
> > }
> >
> > -static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder
> *encoder)
> > +static struct intel_dpll_global *bxt_ddi_get_pll(struct intel_encoder
> *encoder)
> > {
> > struct intel_display *display = to_intel_display(encoder->base.dev);
> > enum intel_dpll_id id;
> > @@ -1923,7 +1923,7 @@ static void skl_ddi_enable_clock(struct
> intel_encoder *encoder,
> > const struct intel_crtc_state *crtc_state)
> > {
> > struct intel_display *display = to_intel_display(encoder);
> > - const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> > + const struct intel_dpll_global *pll = crtc_state->dpll_global;
> > enum port port = encoder->port;
> >
> > if (drm_WARN_ON(display->drm, !pll))
> > @@ -1965,7 +1965,7 @@ static bool skl_ddi_is_clock_enabled(struct
> intel_encoder *encoder)
> > return !(intel_de_read(display, DPLL_CTRL2) &
> DPLL_CTRL2_DDI_CLK_OFF(port));
> > }
> >
> > -static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder
> *encoder)
> > +static struct intel_dpll_global *skl_ddi_get_pll(struct intel_encoder
> *encoder)
> > {
> > struct intel_display *display = to_intel_display(encoder);
> > enum port port = encoder->port;
> > @@ -1991,7 +1991,7 @@ void hsw_ddi_enable_clock(struct intel_encoder
> *encoder,
> > const struct intel_crtc_state *crtc_state)
> > {
> > struct intel_display *display = to_intel_display(encoder);
> > - const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> > + const struct intel_dpll_global *pll = crtc_state->dpll_global;
> > enum port port = encoder->port;
> >
> > if (drm_WARN_ON(display->drm, !pll))
> > @@ -2016,7 +2016,7 @@ bool hsw_ddi_is_clock_enabled(struct
> intel_encoder *encoder)
> > return intel_de_read(display, PORT_CLK_SEL(port)) !=
> PORT_CLK_SEL_NONE;
> > }
> >
> > -static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder
> *encoder)
> > +static struct intel_dpll_global *hsw_ddi_get_pll(struct intel_encoder
> *encoder)
> > {
> > struct intel_display *display = to_intel_display(encoder);
> > enum port port = encoder->port;
> > @@ -4184,7 +4184,7 @@ static void intel_ddi_get_config(struct
> intel_encoder *encoder,
> >
> > void intel_ddi_get_clock(struct intel_encoder *encoder,
> > struct intel_crtc_state *crtc_state,
> > - struct intel_shared_dpll *pll)
> > + struct intel_dpll_global *pll)
> > {
> > struct intel_display *display = to_intel_display(encoder);
> > enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
> > @@ -4200,7 +4200,7 @@ void intel_ddi_get_clock(struct intel_encoder
> *encoder,
> >
> > icl_set_active_port_dpll(crtc_state, port_dpll_id);
> >
> > - crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state-
> >shared_dpll,
> > + crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state-
> >dpll_global,
> > &crtc_state-
> >dpll_hw_state);
> > }
> >
> > @@ -4254,7 +4254,7 @@ static void icl_ddi_combo_get_config(struct
> intel_encoder *encoder,
> > intel_ddi_get_config(encoder, crtc_state);
> > }
> >
> > -static bool icl_ddi_tc_pll_is_tbt(const struct intel_shared_dpll *pll)
> > +static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll_global *pll)
> > {
> > return pll->info->id == DPLL_ID_ICL_TBTPLL;
> > }
> > @@ -4264,7 +4264,7 @@ icl_ddi_tc_port_pll_type(struct intel_encoder
> *encoder,
> > const struct intel_crtc_state *crtc_state)
> > {
> > struct intel_display *display = to_intel_display(encoder);
> > - const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> > + const struct intel_dpll_global *pll = crtc_state->dpll_global;
> >
> > if (drm_WARN_ON(display->drm, !pll))
> > return ICL_PORT_DPLL_DEFAULT;
> > @@ -4287,7 +4287,7 @@ intel_ddi_port_pll_type(struct intel_encoder
> *encoder,
> >
> > static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
> > struct intel_crtc_state *crtc_state,
> > - struct intel_shared_dpll *pll)
> > + struct intel_dpll_global *pll)
> > {
> > struct intel_display *display = to_intel_display(encoder);
> > enum icl_port_dpll_id port_dpll_id;
> > @@ -4310,10 +4310,10 @@ static void icl_ddi_tc_get_clock(struct
> intel_encoder *encoder,
> >
> > icl_set_active_port_dpll(crtc_state, port_dpll_id);
> >
> > - if (icl_ddi_tc_pll_is_tbt(crtc_state->shared_dpll))
> > + if (icl_ddi_tc_pll_is_tbt(crtc_state->dpll_global))
> > crtc_state->port_clock = icl_calc_tbt_pll_link(display, encoder-
> >port);
> > else
> > - crtc_state->port_clock = intel_dpll_get_freq(display,
> crtc_state->shared_dpll,
> > + crtc_state->port_clock = intel_dpll_get_freq(display,
> crtc_state->dpll_global,
> > &crtc_state-
> >dpll_hw_state);
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h
> b/drivers/gpu/drm/i915/display/intel_ddi.h
> > index 353eb04079e9..c41341b7e5cf 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.h
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.h
> > @@ -18,7 +18,7 @@ struct intel_display;
> > struct intel_dp;
> > struct intel_dpll_hw_state;
> > struct intel_encoder;
> > -struct intel_shared_dpll;
> > +struct intel_dpll_global;
> > enum pipe;
> > enum port;
> > enum transcoder;
> > @@ -40,7 +40,7 @@ void intel_ddi_enable_clock(struct intel_encoder
> *encoder,
> > void intel_ddi_disable_clock(struct intel_encoder *encoder);
> > void intel_ddi_get_clock(struct intel_encoder *encoder,
> > struct intel_crtc_state *crtc_state,
> > - struct intel_shared_dpll *pll);
> > + struct intel_dpll_global *pll);
> > void hsw_ddi_enable_clock(struct intel_encoder *encoder,
> > const struct intel_crtc_state *crtc_state);
> > void hsw_ddi_disable_clock(struct intel_encoder *encoder);
> > @@ -50,7 +50,7 @@ intel_ddi_port_pll_type(struct intel_encoder *encoder,
> > const struct intel_crtc_state *crtc_state);
> > void hsw_ddi_get_config(struct intel_encoder *encoder,
> > struct intel_crtc_state *crtc_state);
> > -struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder
> *encoder);
> > +struct intel_dpll_global *icl_ddi_combo_get_pll(struct intel_encoder
> *encoder);
> > void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
> > const struct intel_crtc_state *crtc_state);
> > void intel_wait_ddi_buf_idle(struct intel_display *display, enum port port);
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> > index c540e2cae1f0..5b808bad61e0 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -1322,7 +1322,7 @@ static void intel_encoders_update_prepare(struct
> intel_atomic_state *state)
> > if (intel_crtc_needs_modeset(new_crtc_state))
> > continue;
> >
> > - new_crtc_state->shared_dpll = old_crtc_state-
> >shared_dpll;
> > + new_crtc_state->dpll_global = old_crtc_state-
> >dpll_global;
> > new_crtc_state->dpll_hw_state = old_crtc_state-
> >dpll_hw_state;
> > }
> > }
> > @@ -1661,7 +1661,7 @@ static void hsw_crtc_enable(struct
> intel_atomic_state *state,
> >
> > intel_encoders_pre_pll_enable(state, crtc);
> >
> > - if (new_crtc_state->shared_dpll)
> > + if (new_crtc_state->dpll_global)
> > intel_enable_shared_dpll(new_crtc_state);
> >
> > intel_encoders_pre_enable(state, crtc);
> > @@ -1957,7 +1957,7 @@ static void get_crtc_power_domains(struct
> intel_crtc_state *crtc_state,
> > if (HAS_DDI(display) && crtc_state->has_audio)
> > set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits);
> >
> > - if (crtc_state->shared_dpll)
> > + if (crtc_state->dpll_global)
> > set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits);
> >
> > if (crtc_state->dsc.compression_enable)
> > @@ -4498,7 +4498,7 @@ copy_joiner_crtc_state_modeset(struct
> intel_atomic_state *state,
> > /* preserve some things from the slave's original crtc state */
> > saved_state->uapi = secondary_crtc_state->uapi;
> > saved_state->scaler_state = secondary_crtc_state->scaler_state;
> > - saved_state->shared_dpll = secondary_crtc_state->shared_dpll;
> > + saved_state->dpll_global = secondary_crtc_state->dpll_global;
> > saved_state->crc_enabled = secondary_crtc_state->crc_enabled;
> >
> > intel_crtc_free_hw_state(secondary_crtc_state);
> > @@ -4561,7 +4561,7 @@ intel_crtc_prepare_cleared_state(struct
> intel_atomic_state *state,
> > saved_state->uapi = crtc_state->uapi;
> > saved_state->inherited = crtc_state->inherited;
> > saved_state->scaler_state = crtc_state->scaler_state;
> > - saved_state->shared_dpll = crtc_state->shared_dpll;
> > + saved_state->dpll_global = crtc_state->dpll_global;
> > saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
> > memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
> > sizeof(saved_state->icl_port_dplls));
> > @@ -5313,7 +5313,7 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
> > PIPE_CONF_CHECK_BOOL(double_wide);
> >
> > if (display->dpll.mgr)
> > - PIPE_CONF_CHECK_P(shared_dpll);
> > + PIPE_CONF_CHECK_P(dpll_global);
> >
> > /* FIXME convert everything over the dpll_mgr */
> > if (display->dpll.mgr || HAS_GMCH(display))
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
> b/drivers/gpu/drm/i915/display/intel_display_core.h
> > index 3673275f9061..b23ff1c34bdf 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> > @@ -126,8 +126,8 @@ struct intel_audio {
> > struct intel_dpll {
> > struct mutex lock;
> >
> > - int num_shared_dpll;
> > - struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
> > + int num_dpll_global;
> > + struct intel_dpll_global dpll_globals[I915_NUM_PLLS];
> > const struct intel_dpll_mgr *mgr;
> >
> > struct {
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > index a317c6646382..db26998e0baa 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > @@ -625,7 +625,7 @@ static int i915_shared_dplls_info(struct seq_file *m,
> void *unused)
> > {
> > struct intel_display *display = node_to_intel_display(m->private);
> > struct drm_printer p = drm_seq_file_printer(m);
> > - struct intel_shared_dpll *pll;
> > + struct intel_dpll_global *pll;
> > int i;
> >
> > drm_modeset_lock_all(display->drm);
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 7d1c64f7b405..e080ffb32546 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1075,8 +1075,8 @@ struct intel_crtc_state {
> > * haswell. */
> > struct dpll dpll;
> >
> > - /* Selected dpll when shared or NULL. */
> > - struct intel_shared_dpll *shared_dpll;
> > + /* Selected dpll. */
> > + struct intel_dpll_global *dpll_global;
> >
> > /* Actual register state of the dpll, for shared dpll cross-checking. */
> > struct intel_dpll_hw_state dpll_hw_state;
> > @@ -1086,7 +1086,7 @@ struct intel_crtc_state {
> > * setting shared_dpll and dpll_hw_state to one of these reserved
> ones.
> > */
> > struct icl_port_dpll {
> > - struct intel_shared_dpll *pll;
> > + struct intel_dpll_global *pll;
> > struct intel_dpll_hw_state hw_state;
> > } icl_port_dplls[ICL_PORT_DPLL_COUNT];
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c
> b/drivers/gpu/drm/i915/display/intel_dpll.c
> > index 0481b1365b85..c6d29382378b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> > @@ -1770,9 +1770,9 @@ int intel_dpll_crtc_get_shared_dpll(struct
> intel_atomic_state *state,
> > int ret;
> >
> > drm_WARN_ON(display->drm, !intel_crtc_needs_modeset(crtc_state));
> > - drm_WARN_ON(display->drm, !crtc_state->hw.enable && crtc_state-
> >shared_dpll);
> > + drm_WARN_ON(display->drm, !crtc_state->hw.enable && crtc_state-
> >dpll_global);
> >
> > - if (!crtc_state->hw.enable || crtc_state->shared_dpll)
> > + if (!crtc_state->hw.enable || crtc_state->dpll_global)
> > return 0;
> >
> > if (!display->funcs.dpll->crtc_get_shared_dpll)
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > index 92ca2a544e2f..833c90f3f0f1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > @@ -67,7 +67,7 @@ struct intel_dpll_global_funcs {
> > * the pll is not already enabled.
> > */
> > void (*enable)(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll_global *pll,
> > const struct intel_dpll_hw_state *dpll_hw_state);
> >
> > /*
> > @@ -76,7 +76,7 @@ struct intel_dpll_global_funcs {
> > * tracked users for it.
> > */
> > void (*disable)(struct intel_display *display,
> > - struct intel_shared_dpll *pll);
> > + struct intel_dpll_global *pll);
> >
> > /*
> > * Hook for reading the values currently programmed to the DPLL
> > @@ -84,7 +84,7 @@ struct intel_dpll_global_funcs {
> > * verification after a mode set.
> > */
> > bool (*get_hw_state)(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll_global *pll,
> > struct intel_dpll_hw_state *dpll_hw_state);
> >
> > /*
> > @@ -92,7 +92,7 @@ struct intel_dpll_global_funcs {
> > * in state.
> > */
> > int (*get_freq)(struct intel_display *i915,
> > - const struct intel_shared_dpll *pll,
> > + const struct intel_dpll_global *pll,
> > const struct intel_dpll_hw_state *dpll_hw_state);
> > };
> >
> > @@ -121,7 +121,7 @@ static void
> > intel_atomic_duplicate_dpll_state(struct intel_display *display,
> > struct intel_dpll_state *dpll_state)
> > {
> > - struct intel_shared_dpll *pll;
> > + struct intel_dpll_global *pll;
> > int i;
> >
> > /* Copy dpll state */
> > @@ -155,11 +155,11 @@ intel_atomic_get_shared_dpll_state(struct
> drm_atomic_state *s)
> > * Returns:
> > * A pointer to the DPLL with @id
> > */
> > -struct intel_shared_dpll *
> > +struct intel_dpll_global *
> > intel_get_shared_dpll_by_id(struct intel_display *display,
> > enum intel_dpll_id id)
> > {
> > - struct intel_shared_dpll *pll;
> > + struct intel_dpll_global *pll;
> > int i;
> >
> > for_each_dpll(display, pll, i) {
> > @@ -173,7 +173,7 @@ intel_get_shared_dpll_by_id(struct intel_display
> *display,
> >
> > /* For ILK+ */
> > void assert_shared_dpll(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll_global *pll,
> > bool state)
> > {
> > bool cur_state;
> > @@ -202,7 +202,7 @@ enum intel_dpll_id icl_tc_port_to_pll_id(enum
> tc_port tc_port)
> >
> > static i915_reg_t
> > intel_combo_pll_enable_reg(struct intel_display *display,
> > - struct intel_shared_dpll *pll)
> > + struct intel_dpll_global *pll)
> > {
> > if (display->platform.dg1)
> > return DG1_DPLL_ENABLE(pll->info->id);
> > @@ -215,7 +215,7 @@ intel_combo_pll_enable_reg(struct intel_display
> *display,
> >
> > static i915_reg_t
> > intel_tc_pll_enable_reg(struct intel_display *display,
> > - struct intel_shared_dpll *pll)
> > + struct intel_dpll_global *pll)
> > {
> > const enum intel_dpll_id id = pll->info->id;
> > enum tc_port tc_port = icl_pll_id_to_tc_port(id);
> > @@ -227,7 +227,7 @@ intel_tc_pll_enable_reg(struct intel_display *display,
> > }
> >
> > static void _intel_enable_shared_dpll(struct intel_display *display,
> > - struct intel_shared_dpll *pll)
> > + struct intel_dpll_global *pll)
> > {
> > if (pll->info->power_domain)
> > pll->wakeref = intel_display_power_get(display, pll->info-
> >power_domain);
> > @@ -237,7 +237,7 @@ static void _intel_enable_shared_dpll(struct
> intel_display *display,
> > }
> >
> > static void _intel_disable_shared_dpll(struct intel_display *display,
> > - struct intel_shared_dpll *pll)
> > + struct intel_dpll_global *pll)
> > {
> > pll->info->funcs->disable(display, pll);
> > pll->on = false;
> > @@ -256,7 +256,7 @@ void intel_enable_shared_dpll(const struct
> intel_crtc_state *crtc_state)
> > {
> > struct intel_display *display = to_intel_display(crtc_state);
> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > - struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> > + struct intel_dpll_global *pll = crtc_state->dpll_global;
> > unsigned int pipe_mask = intel_crtc_joined_pipe_mask(crtc_state);
> > unsigned int old_mask;
> >
> > @@ -302,7 +302,7 @@ void intel_disable_shared_dpll(const struct
> intel_crtc_state *crtc_state)
> > {
> > struct intel_display *display = to_intel_display(crtc_state);
> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > - struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> > + struct intel_dpll_global *pll = crtc_state->dpll_global;
> > unsigned int pipe_mask = intel_crtc_joined_pipe_mask(crtc_state);
> >
> > /* PCH only available on ILK+ */
> > @@ -341,7 +341,7 @@ void intel_disable_shared_dpll(const struct
> intel_crtc_state *crtc_state)
> > static unsigned long
> > intel_dpll_mask_all(struct intel_display *display)
> > {
> > - struct intel_shared_dpll *pll;
> > + struct intel_dpll_global *pll;
> > unsigned long dpll_mask = 0;
> > int i;
> >
> > @@ -354,7 +354,7 @@ intel_dpll_mask_all(struct intel_display *display)
> > return dpll_mask;
> > }
> >
> > -static struct intel_shared_dpll *
> > +static struct intel_dpll_global *
> > intel_find_shared_dpll(struct intel_atomic_state *state,
> > const struct intel_crtc *crtc,
> > const struct intel_dpll_hw_state *dpll_hw_state,
> > @@ -363,7 +363,7 @@ intel_find_shared_dpll(struct intel_atomic_state
> *state,
> > struct intel_display *display = to_intel_display(crtc);
> > unsigned long dpll_mask_all = intel_dpll_mask_all(display);
> > struct intel_dpll_state *dpll_state;
> > - struct intel_shared_dpll *unused_pll = NULL;
> > + struct intel_dpll_global *unused_pll = NULL;
> > enum intel_dpll_id id;
> >
> > dpll_state = intel_atomic_get_shared_dpll_state(&state->base);
> > @@ -371,7 +371,7 @@ intel_find_shared_dpll(struct intel_atomic_state
> *state,
> > drm_WARN_ON(display->drm, dpll_mask & ~dpll_mask_all);
> >
> > for_each_set_bit(id, &dpll_mask, fls(dpll_mask_all)) {
> > - struct intel_shared_dpll *pll;
> > + struct intel_dpll_global *pll;
> >
> > pll = intel_get_shared_dpll_by_id(display, id);
> > if (!pll)
> > @@ -418,7 +418,7 @@ intel_find_shared_dpll(struct intel_atomic_state
> *state,
> > */
> > static void
> > intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc,
> > - const struct intel_shared_dpll *pll,
> > + const struct intel_dpll_global *pll,
> > struct intel_dpll_state *dpll_state)
> > {
> > struct intel_display *display = to_intel_display(crtc);
> > @@ -434,7 +434,7 @@ intel_reference_shared_dpll_crtc(const struct
> intel_crtc *crtc,
> > static void
> > intel_reference_shared_dpll(struct intel_atomic_state *state,
> > const struct intel_crtc *crtc,
> > - const struct intel_shared_dpll *pll,
> > + const struct intel_dpll_global *pll,
> > const struct intel_dpll_hw_state *dpll_hw_state)
> > {
> > struct intel_dpll_state *dpll_state;
> > @@ -457,7 +457,7 @@ intel_reference_shared_dpll(struct
> intel_atomic_state *state,
> > */
> > void
> > intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
> > - const struct intel_shared_dpll *pll,
> > + const struct intel_dpll_global *pll,
> > struct intel_dpll_state *dpll_state)
> > {
> > struct intel_display *display = to_intel_display(crtc);
> > @@ -472,7 +472,7 @@ intel_unreference_shared_dpll_crtc(const struct
> intel_crtc *crtc,
> >
> > static void intel_unreference_shared_dpll(struct intel_atomic_state *state,
> > const struct intel_crtc *crtc,
> > - const struct intel_shared_dpll *pll)
> > + const struct intel_dpll_global *pll)
> > {
> > struct intel_dpll_state *dpll_state;
> >
> > @@ -489,12 +489,12 @@ static void intel_put_dpll(struct intel_atomic_state
> *state,
> > struct intel_crtc_state *new_crtc_state =
> > intel_atomic_get_new_crtc_state(state, crtc);
> >
> > - new_crtc_state->shared_dpll = NULL;
> > + new_crtc_state->dpll_global = NULL;
> >
> > - if (!old_crtc_state->shared_dpll)
> > + if (!old_crtc_state->dpll_global)
> > return;
> >
> > - intel_unreference_shared_dpll(state, crtc, old_crtc_state-
> >shared_dpll);
> > + intel_unreference_shared_dpll(state, crtc, old_crtc_state-
> >dpll_global);
> > }
> >
> > /**
> > @@ -512,7 +512,7 @@ void intel_shared_dpll_swap_state(struct
> intel_atomic_state *state)
> > {
> > struct intel_display *display = to_intel_display(state);
> > struct intel_dpll_state *dpll_state = state->dpll_state;
> > - struct intel_shared_dpll *pll;
> > + struct intel_dpll_global *pll;
> > int i;
> >
> > if (!state->dpll_set)
> > @@ -523,7 +523,7 @@ void intel_shared_dpll_swap_state(struct
> intel_atomic_state *state)
> > }
> >
> > static bool ibx_pch_dpll_get_hw_state(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll_global *pll,
> > struct intel_dpll_hw_state *dpll_hw_state)
> > {
> > struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx;
> > @@ -559,7 +559,7 @@ static void ibx_assert_pch_refclk_enabled(struct
> intel_display *display)
> > }
> >
> > static void ibx_pch_dpll_enable(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll_global *pll,
> > const struct intel_dpll_hw_state
> *dpll_hw_state)
> > {
> > const struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx;
> > @@ -588,7 +588,7 @@ static void ibx_pch_dpll_enable(struct intel_display
> *display,
> > }
> >
> > static void ibx_pch_dpll_disable(struct intel_display *display,
> > - struct intel_shared_dpll *pll)
> > + struct intel_dpll_global *pll)
> > {
> > const enum intel_dpll_id id = pll->info->id;
> >
> > @@ -612,7 +612,7 @@ static int ibx_get_dpll(struct intel_atomic_state
> *state,
> > struct drm_i915_private *i915 = to_i915(display->drm);
> > struct intel_crtc_state *crtc_state =
> > intel_atomic_get_new_crtc_state(state, crtc);
> > - struct intel_shared_dpll *pll;
> > + struct intel_dpll_global *pll;
> > enum intel_dpll_id id;
> >
> > if (HAS_PCH_IBX(i915)) {
> > @@ -638,7 +638,7 @@ static int ibx_get_dpll(struct intel_atomic_state
> *state,
> > intel_reference_shared_dpll(state, crtc,
> > pll, &crtc_state->dpll_hw_state);
> >
> > - crtc_state->shared_dpll = pll;
> > + crtc_state->dpll_global = pll;
> >
> > return 0;
> > }
> > @@ -690,7 +690,7 @@ static const struct intel_dpll_mgr pch_pll_mgr = {
> > };
> >
> > static void hsw_ddi_wrpll_enable(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll_global *pll,
> > const struct intel_dpll_hw_state
> *dpll_hw_state)
> > {
> > const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
> > @@ -702,7 +702,7 @@ static void hsw_ddi_wrpll_enable(struct intel_display
> *display,
> > }
> >
> > static void hsw_ddi_spll_enable(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll_global *pll,
> > const struct intel_dpll_hw_state
> *dpll_hw_state)
> > {
> > const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
> > @@ -713,7 +713,7 @@ static void hsw_ddi_spll_enable(struct intel_display
> *display,
> > }
> >
> > static void hsw_ddi_wrpll_disable(struct intel_display *display,
> > - struct intel_shared_dpll *pll)
> > + struct intel_dpll_global *pll)
> > {
> > const enum intel_dpll_id id = pll->info->id;
> >
> > @@ -729,7 +729,7 @@ static void hsw_ddi_wrpll_disable(struct intel_display
> *display,
> > }
> >
> > static void hsw_ddi_spll_disable(struct intel_display *display,
> > - struct intel_shared_dpll *pll)
> > + struct intel_dpll_global *pll)
> > {
> > enum intel_dpll_id id = pll->info->id;
> >
> > @@ -745,7 +745,7 @@ static void hsw_ddi_spll_disable(struct intel_display
> *display,
> > }
> >
> > static bool hsw_ddi_wrpll_get_hw_state(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll_global *pll,
> > struct intel_dpll_hw_state *dpll_hw_state)
> > {
> > struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
> > @@ -767,7 +767,7 @@ static bool hsw_ddi_wrpll_get_hw_state(struct
> intel_display *display,
> > }
> >
> > static bool hsw_ddi_spll_get_hw_state(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll_global *pll,
> > struct intel_dpll_hw_state *dpll_hw_state)
> > {
> > struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
> > @@ -994,7 +994,7 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */,
> > }
> >
> > static int hsw_ddi_wrpll_get_freq(struct intel_display *display,
> > - const struct intel_shared_dpll *pll,
> > + const struct intel_dpll_global *pll,
> > const struct intel_dpll_hw_state
> *dpll_hw_state)
> > {
> > const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
> > @@ -1057,7 +1057,7 @@ hsw_ddi_wrpll_compute_dpll(struct
> intel_atomic_state *state,
> > return 0;
> > }
> >
> > -static struct intel_shared_dpll *
> > +static struct intel_dpll_global *
> > hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state,
> > struct intel_crtc *crtc)
> > {
> > @@ -1088,11 +1088,11 @@ hsw_ddi_lcpll_compute_dpll(struct
> intel_crtc_state *crtc_state)
> > }
> > }
> >
> > -static struct intel_shared_dpll *
> > +static struct intel_dpll_global *
> > hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
> > {
> > struct intel_display *display = to_intel_display(crtc_state);
> > - struct intel_shared_dpll *pll;
> > + struct intel_dpll_global *pll;
> > enum intel_dpll_id pll_id;
> > int clock = crtc_state->port_clock;
> >
> > @@ -1120,7 +1120,7 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state
> *crtc_state)
> > }
> >
> > static int hsw_ddi_lcpll_get_freq(struct intel_display *display,
> > - const struct intel_shared_dpll *pll,
> > + const struct intel_dpll_global *pll,
> > const struct intel_dpll_hw_state
> *dpll_hw_state)
> > {
> > int link_clock = 0;
> > @@ -1160,7 +1160,7 @@ hsw_ddi_spll_compute_dpll(struct
> intel_atomic_state *state,
> > return 0;
> > }
> >
> > -static struct intel_shared_dpll *
> > +static struct intel_dpll_global *
> > hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
> > struct intel_crtc *crtc)
> > {
> > @@ -1172,7 +1172,7 @@ hsw_ddi_spll_get_dpll(struct intel_atomic_state
> *state,
> > }
> >
> > static int hsw_ddi_spll_get_freq(struct intel_display *display,
> > - const struct intel_shared_dpll *pll,
> > + const struct intel_dpll_global *pll,
> > const struct intel_dpll_hw_state
> *dpll_hw_state)
> > {
> > const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
> > @@ -1219,7 +1219,7 @@ static int hsw_get_dpll(struct intel_atomic_state
> *state,
> > {
> > struct intel_crtc_state *crtc_state =
> > intel_atomic_get_new_crtc_state(state, crtc);
> > - struct intel_shared_dpll *pll = NULL;
> > + struct intel_dpll_global *pll = NULL;
> >
> > if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> > pll = hsw_ddi_wrpll_get_dpll(state, crtc);
> > @@ -1234,7 +1234,7 @@ static int hsw_get_dpll(struct intel_atomic_state
> *state,
> > intel_reference_shared_dpll(state, crtc,
> > pll, &crtc_state->dpll_hw_state);
> >
> > - crtc_state->shared_dpll = pll;
> > + crtc_state->dpll_global = pll;
> >
> > return 0;
> > }
> > @@ -1283,18 +1283,18 @@ static const struct intel_dpll_global_funcs
> hsw_ddi_spll_funcs = {
> > };
> >
> > static void hsw_ddi_lcpll_enable(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll_global *pll,
> > const struct intel_dpll_hw_state *hw_state)
> > {
> > }
> >
> > static void hsw_ddi_lcpll_disable(struct intel_display *display,
> > - struct intel_shared_dpll *pll)
> > + struct intel_dpll_global *pll)
> > {
> > }
> >
> > static bool hsw_ddi_lcpll_get_hw_state(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll_global *pll,
> > struct intel_dpll_hw_state *dpll_hw_state)
> > {
> > return true;
> > @@ -1362,7 +1362,7 @@ static const struct skl_dpll_regs skl_dpll_regs[4] = {
> > };
> >
> > static void skl_ddi_pll_write_ctrl1(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll_global *pll,
> > const struct skl_dpll_hw_state *hw_state)
> > {
> > const enum intel_dpll_id id = pll->info->id;
> > @@ -1376,7 +1376,7 @@ static void skl_ddi_pll_write_ctrl1(struct
> intel_display *display,
> > }
> >
> > static void skl_ddi_pll_enable(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll_global *pll,
> > const struct intel_dpll_hw_state *dpll_hw_state)
> > {
> > const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
> > @@ -1398,7 +1398,7 @@ static void skl_ddi_pll_enable(struct intel_display
> *display,
> > }
> >
> > static void skl_ddi_dpll0_enable(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll_global *pll,
> > const struct intel_dpll_hw_state
> *dpll_hw_state)
> > {
> > const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
> > @@ -1407,7 +1407,7 @@ static void skl_ddi_dpll0_enable(struct
> intel_display *display,
> > }
> >
> > static void skl_ddi_pll_disable(struct intel_display *display,
> > - struct intel_shared_dpll *pll)
> > + struct intel_dpll_global *pll)
> > {
> > const struct skl_dpll_regs *regs = skl_dpll_regs;
> > const enum intel_dpll_id id = pll->info->id;
> > @@ -1418,12 +1418,12 @@ static void skl_ddi_pll_disable(struct
> intel_display *display,
> > }
> >
> > static void skl_ddi_dpll0_disable(struct intel_display *display,
> > - struct intel_shared_dpll *pll)
> > + struct intel_dpll_global *pll)
> > {
> > }
> >
> > static bool skl_ddi_pll_get_hw_state(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll_global *pll,
> > struct intel_dpll_hw_state *dpll_hw_state)
> > {
> > struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
> > @@ -1461,7 +1461,7 @@ static bool skl_ddi_pll_get_hw_state(struct
> intel_display *display,
> > }
> >
> > static bool skl_ddi_dpll0_get_hw_state(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll_global *pll,
> > struct intel_dpll_hw_state *dpll_hw_state)
> > {
> > struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
> > @@ -1734,7 +1734,7 @@ skl_ddi_calculate_wrpll(int clock,
> > }
> >
> > static int skl_ddi_wrpll_get_freq(struct intel_display *display,
> > - const struct intel_shared_dpll *pll,
> > + const struct intel_dpll_global *pll,
> > const struct intel_dpll_hw_state
> *dpll_hw_state)
> > {
> > const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
> > @@ -1882,7 +1882,7 @@ skl_ddi_dp_set_dpll_hw_state(struct
> intel_crtc_state *crtc_state)
> > }
> >
> > static int skl_ddi_lcpll_get_freq(struct intel_display *display,
> > - const struct intel_shared_dpll *pll,
> > + const struct intel_dpll_global *pll,
> > const struct intel_dpll_hw_state
> *dpll_hw_state)
> > {
> > const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
> > @@ -1937,7 +1937,7 @@ static int skl_get_dpll(struct intel_atomic_state
> *state,
> > {
> > struct intel_crtc_state *crtc_state =
> > intel_atomic_get_new_crtc_state(state, crtc);
> > - struct intel_shared_dpll *pll;
> > + struct intel_dpll_global *pll;
> >
> > if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> > pll = intel_find_shared_dpll(state, crtc,
> > @@ -1955,13 +1955,13 @@ static int skl_get_dpll(struct intel_atomic_state
> *state,
> > intel_reference_shared_dpll(state, crtc,
> > pll, &crtc_state->dpll_hw_state);
> >
> > - crtc_state->shared_dpll = pll;
> > + crtc_state->dpll_global = pll;
> >
> > return 0;
> > }
> >
> > static int skl_ddi_pll_get_freq(struct intel_display *display,
> > - const struct intel_shared_dpll *pll,
> > + const struct intel_dpll_global *pll,
> > const struct intel_dpll_hw_state
> *dpll_hw_state)
> > {
> > const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
> > @@ -2036,7 +2036,7 @@ static const struct intel_dpll_mgr skl_pll_mgr = {
> > };
> >
> > static void bxt_ddi_pll_enable(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll_global *pll,
> > const struct intel_dpll_hw_state *dpll_hw_state)
> > {
> > const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
> > @@ -2139,7 +2139,7 @@ static void bxt_ddi_pll_enable(struct intel_display
> *display,
> > }
> >
> > static void bxt_ddi_pll_disable(struct intel_display *display,
> > - struct intel_shared_dpll *pll)
> > + struct intel_dpll_global *pll)
> > {
> > enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
> >
> > @@ -2158,7 +2158,7 @@ static void bxt_ddi_pll_disable(struct intel_display
> *display,
> > }
> >
> > static bool bxt_ddi_pll_get_hw_state(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll_global *pll,
> > struct intel_dpll_hw_state *dpll_hw_state)
> > {
> > struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
> > @@ -2358,7 +2358,7 @@ static int bxt_ddi_set_dpll_hw_state(struct
> intel_crtc_state *crtc_state,
> > }
> >
> > static int bxt_ddi_pll_get_freq(struct intel_display *display,
> > - const struct intel_shared_dpll *pll,
> > + const struct intel_dpll_global *pll,
> > const struct intel_dpll_hw_state
> *dpll_hw_state)
> > {
> > const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
> > @@ -2427,7 +2427,7 @@ static int bxt_get_dpll(struct intel_atomic_state
> *state,
> > struct intel_display *display = to_intel_display(state);
> > struct intel_crtc_state *crtc_state =
> > intel_atomic_get_new_crtc_state(state, crtc);
> > - struct intel_shared_dpll *pll;
> > + struct intel_dpll_global *pll;
> > enum intel_dpll_id id;
> >
> > /* 1:1 mapping between ports and PLLs */
> > @@ -2440,7 +2440,7 @@ static int bxt_get_dpll(struct intel_atomic_state
> *state,
> > intel_reference_shared_dpll(state, crtc,
> > pll, &crtc_state->dpll_hw_state);
> >
> > - crtc_state->shared_dpll = pll;
> > + crtc_state->dpll_global = pll;
> >
> > return 0;
> > }
> > @@ -2755,7 +2755,7 @@ static int icl_calc_tbt_pll(struct intel_crtc_state
> *crtc_state,
> > }
> >
> > static int icl_ddi_tbt_pll_get_freq(struct intel_display *display,
> > - const struct intel_shared_dpll *pll,
> > + const struct intel_dpll_global *pll,
> > const struct intel_dpll_hw_state
> *dpll_hw_state)
> > {
> > /*
> > @@ -2826,7 +2826,7 @@ icl_calc_wrpll(struct intel_crtc_state *crtc_state,
> > }
> >
> > static int icl_ddi_combo_pll_get_freq(struct intel_display *display,
> > - const struct intel_shared_dpll *pll,
> > + const struct intel_dpll_global *pll,
> > const struct intel_dpll_hw_state
> *dpll_hw_state)
> > {
> > const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
> > @@ -3199,7 +3199,7 @@ static int icl_calc_mg_pll_state(struct
> intel_crtc_state *crtc_state,
> > }
> >
> > static int icl_ddi_mg_pll_get_freq(struct intel_display *display,
> > - const struct intel_shared_dpll *pll,
> > + const struct intel_dpll_global *pll,
> > const struct intel_dpll_hw_state
> *dpll_hw_state)
> > {
> > const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
> > @@ -3285,7 +3285,7 @@ void icl_set_active_port_dpll(struct
> intel_crtc_state *crtc_state,
> > struct icl_port_dpll *port_dpll =
> > &crtc_state->icl_port_dplls[port_dpll_id];
> >
> > - crtc_state->shared_dpll = port_dpll->pll;
> > + crtc_state->dpll_global = port_dpll->pll;
> > crtc_state->dpll_hw_state = port_dpll->hw_state;
> > }
> >
> > @@ -3428,8 +3428,8 @@ static int icl_compute_tc_phy_dplls(struct
> intel_atomic_state *state,
> > return ret;
> >
> > /* this is mainly for the fastset check */
> > - if (old_crtc_state->shared_dpll &&
> > - old_crtc_state->shared_dpll->info->id == DPLL_ID_ICL_TBTPLL)
> > + if (old_crtc_state->dpll_global &&
> > + old_crtc_state->dpll_global->info->id == DPLL_ID_ICL_TBTPLL)
> > icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);
> > else
> > icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_MG_PHY);
> > @@ -3521,7 +3521,7 @@ static void icl_put_dplls(struct intel_atomic_state
> *state,
> > intel_atomic_get_new_crtc_state(state, crtc);
> > enum icl_port_dpll_id id;
> >
> > - new_crtc_state->shared_dpll = NULL;
> > + new_crtc_state->dpll_global = NULL;
> >
> > for (id = ICL_PORT_DPLL_DEFAULT; id < ICL_PORT_DPLL_COUNT; id++) {
> > const struct icl_port_dpll *old_port_dpll =
> > @@ -3539,7 +3539,7 @@ static void icl_put_dplls(struct intel_atomic_state
> *state,
> > }
> >
> > static bool mg_pll_get_hw_state(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll_global *pll,
> > struct intel_dpll_hw_state *dpll_hw_state)
> > {
> > struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
> > @@ -3606,7 +3606,7 @@ static bool mg_pll_get_hw_state(struct
> intel_display *display,
> > }
> >
> > static bool dkl_pll_get_hw_state(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll_global *pll,
> > struct intel_dpll_hw_state *dpll_hw_state)
> > {
> > struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
> > @@ -3678,7 +3678,7 @@ static bool dkl_pll_get_hw_state(struct
> intel_display *display,
> > }
> >
> > static bool icl_pll_get_hw_state(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll_global *pll,
> > struct intel_dpll_hw_state *dpll_hw_state,
> > i915_reg_t enable_reg)
> > {
> > @@ -3739,7 +3739,7 @@ static bool icl_pll_get_hw_state(struct intel_display
> *display,
> > }
> >
> > static bool combo_pll_get_hw_state(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll_global *pll,
> > struct intel_dpll_hw_state *dpll_hw_state)
> > {
> > i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
> > @@ -3748,14 +3748,14 @@ static bool combo_pll_get_hw_state(struct
> intel_display *display,
> > }
> >
> > static bool tbt_pll_get_hw_state(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll_global *pll,
> > struct intel_dpll_hw_state *dpll_hw_state)
> > {
> > return icl_pll_get_hw_state(display, pll, dpll_hw_state,
> TBT_PLL_ENABLE);
> > }
> >
> > static void icl_dpll_write(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll_global *pll,
> > const struct icl_dpll_hw_state *hw_state)
> > {
> > const enum intel_dpll_id id = pll->info->id;
> > @@ -3797,7 +3797,7 @@ static void icl_dpll_write(struct intel_display
> *display,
> > }
> >
> > static void icl_mg_pll_write(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll_global *pll,
> > const struct icl_dpll_hw_state *hw_state)
> > {
> > enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);
> > @@ -3840,7 +3840,7 @@ static void icl_mg_pll_write(struct intel_display
> *display,
> > }
> >
> > static void dkl_pll_write(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll_global *pll,
> > const struct icl_dpll_hw_state *hw_state)
> > {
> > enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);
> > @@ -3905,7 +3905,7 @@ static void dkl_pll_write(struct intel_display
> *display,
> > }
> >
> > static void icl_pll_power_enable(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll_global *pll,
> > i915_reg_t enable_reg)
> > {
> > intel_de_rmw(display, enable_reg, 0, PLL_POWER_ENABLE);
> > @@ -3920,7 +3920,7 @@ static void icl_pll_power_enable(struct
> intel_display *display,
> > }
> >
> > static void icl_pll_enable(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll_global *pll,
> > i915_reg_t enable_reg)
> > {
> > intel_de_rmw(display, enable_reg, 0, PLL_ENABLE);
> > @@ -3930,7 +3930,7 @@ static void icl_pll_enable(struct intel_display
> *display,
> > drm_err(display->drm, "PLL %d not locked\n", pll->info->id);
> > }
> >
> > -static void adlp_cmtg_clock_gating_wa(struct intel_display *display, struct
> intel_shared_dpll *pll)
> > +static void adlp_cmtg_clock_gating_wa(struct intel_display *display, struct
> intel_dpll_global *pll)
> > {
> > u32 val;
> >
> > @@ -3955,7 +3955,7 @@ static void adlp_cmtg_clock_gating_wa(struct
> intel_display *display, struct inte
> > }
> >
> > static void combo_pll_enable(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll_global *pll,
> > const struct intel_dpll_hw_state *dpll_hw_state)
> > {
> > const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
> > @@ -3979,7 +3979,7 @@ static void combo_pll_enable(struct intel_display
> *display,
> > }
> >
> > static void tbt_pll_enable(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll_global *pll,
> > const struct intel_dpll_hw_state *dpll_hw_state)
> > {
> > const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
> > @@ -4000,7 +4000,7 @@ static void tbt_pll_enable(struct intel_display
> *display,
> > }
> >
> > static void mg_pll_enable(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll_global *pll,
> > const struct intel_dpll_hw_state *dpll_hw_state)
> > {
> > const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
> > @@ -4025,7 +4025,7 @@ static void mg_pll_enable(struct intel_display
> *display,
> > }
> >
> > static void icl_pll_disable(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll_global *pll,
> > i915_reg_t enable_reg)
> > {
> > /* The first steps are done by intel_ddi_post_disable(). */
> > @@ -4056,7 +4056,7 @@ static void icl_pll_disable(struct intel_display
> *display,
> > }
> >
> > static void combo_pll_disable(struct intel_display *display,
> > - struct intel_shared_dpll *pll)
> > + struct intel_dpll_global *pll)
> > {
> > i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
> >
> > @@ -4064,13 +4064,13 @@ static void combo_pll_disable(struct
> intel_display *display,
> > }
> >
> > static void tbt_pll_disable(struct intel_display *display,
> > - struct intel_shared_dpll *pll)
> > + struct intel_dpll_global *pll)
> > {
> > icl_pll_disable(display, pll, TBT_PLL_ENABLE);
> > }
> >
> > static void mg_pll_disable(struct intel_display *display,
> > - struct intel_shared_dpll *pll)
> > + struct intel_dpll_global *pll)
> > {
> > i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
> >
> > @@ -4347,19 +4347,19 @@ void intel_shared_dpll_init(struct intel_display
> *display)
> >
> > for (i = 0; dpll_info[i].name; i++) {
> > if (drm_WARN_ON(display->drm,
> > - i >= ARRAY_SIZE(display->dpll.shared_dplls)))
> > + i >= ARRAY_SIZE(display->dpll.dpll_globals)))
> > break;
> >
> > /* must fit into unsigned long bitmask on 32bit */
> > if (drm_WARN_ON(display->drm, dpll_info[i].id >= 32))
> > break;
> >
> > - display->dpll.shared_dplls[i].info = &dpll_info[i];
> > - display->dpll.shared_dplls[i].index = i;
> > + display->dpll.dpll_globals[i].info = &dpll_info[i];
> > + display->dpll.dpll_globals[i].index = i;
> > }
> >
> > display->dpll.mgr = dpll_mgr;
> > - display->dpll.num_shared_dpll = i;
> > + display->dpll.num_dpll_global = i;
> > }
> >
> > /**
> > @@ -4483,7 +4483,7 @@ void intel_update_active_dpll(struct
> intel_atomic_state *state,
> > * Return the output frequency corresponding to @pll's passed in
> @dpll_hw_state.
> > */
> > int intel_dpll_get_freq(struct intel_display *display,
> > - const struct intel_shared_dpll *pll,
> > + const struct intel_dpll_global *pll,
> > const struct intel_dpll_hw_state *dpll_hw_state)
> > {
> > if (drm_WARN_ON(display->drm, !pll->info->funcs->get_freq))
> > @@ -4501,14 +4501,14 @@ int intel_dpll_get_freq(struct intel_display
> *display,
> > * Read out @pll's hardware state into @dpll_hw_state.
> > */
> > bool intel_dpll_get_hw_state(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll_global *pll,
> > struct intel_dpll_hw_state *dpll_hw_state)
> > {
> > return pll->info->funcs->get_hw_state(display, pll, dpll_hw_state);
> > }
> >
> > static void readout_dpll_hw_state(struct intel_display *display,
> > - struct intel_shared_dpll *pll)
> > + struct intel_dpll_global *pll)
> > {
> > struct intel_crtc *crtc;
> >
> > @@ -4522,7 +4522,7 @@ static void readout_dpll_hw_state(struct
> intel_display *display,
> > struct intel_crtc_state *crtc_state =
> > to_intel_crtc_state(crtc->base.state);
> >
> > - if (crtc_state->hw.active && crtc_state->shared_dpll == pll)
> > + if (crtc_state->hw.active && crtc_state->dpll_global == pll)
> > intel_reference_shared_dpll_crtc(crtc, pll, &pll->state);
> > }
> > pll->active_mask = pll->state.pipe_mask;
> > @@ -4540,7 +4540,7 @@ void intel_dpll_update_ref_clks(struct
> intel_display *display)
> >
> > void intel_dpll_readout_hw_state(struct intel_display *display)
> > {
> > - struct intel_shared_dpll *pll;
> > + struct intel_dpll_global *pll;
> > int i;
> >
> > for_each_dpll(display, pll, i)
> > @@ -4548,7 +4548,7 @@ void intel_dpll_readout_hw_state(struct
> intel_display *display)
> > }
> >
> > static void sanitize_dpll_state(struct intel_display *display,
> > - struct intel_shared_dpll *pll)
> > + struct intel_dpll_global *pll)
> > {
> > if (!pll->on)
> > return;
> > @@ -4567,7 +4567,7 @@ static void sanitize_dpll_state(struct intel_display
> *display,
> >
> > void intel_dpll_sanitize_state(struct intel_display *display)
> > {
> > - struct intel_shared_dpll *pll;
> > + struct intel_dpll_global *pll;
> > int i;
> >
> > intel_cx0_pll_power_save_wa(display);
> > @@ -4624,7 +4624,7 @@ bool intel_dpll_compare_hw_state(struct
> intel_display *display,
> >
> > static void
> > verify_single_dpll_state(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll_global *pll,
> > struct intel_crtc *crtc,
> > const struct intel_crtc_state *new_crtc_state)
> > {
> > @@ -4677,8 +4677,8 @@ verify_single_dpll_state(struct intel_display
> *display,
> > pll->info->name);
> > }
> >
> > -static bool has_alt_port_dpll(const struct intel_shared_dpll *old_pll,
> > - const struct intel_shared_dpll *new_pll)
> > +static bool has_alt_port_dpll(const struct intel_dpll_global *old_pll,
> > + const struct intel_dpll_global *new_pll)
> > {
> > return old_pll && new_pll && old_pll != new_pll &&
> > (old_pll->info->is_alt_port_dpll || new_pll->info-
> >is_alt_port_dpll);
> > @@ -4693,22 +4693,22 @@ void intel_shared_dpll_state_verify(struct
> intel_atomic_state *state,
> > const struct intel_crtc_state *new_crtc_state =
> > intel_atomic_get_new_crtc_state(state, crtc);
> >
> > - if (new_crtc_state->shared_dpll)
> > - verify_single_dpll_state(display, new_crtc_state->shared_dpll,
> > + if (new_crtc_state->dpll_global)
> > + verify_single_dpll_state(display, new_crtc_state->dpll_global,
> > crtc, new_crtc_state);
> >
> > - if (old_crtc_state->shared_dpll &&
> > - old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {
> > + if (old_crtc_state->dpll_global &&
> > + old_crtc_state->dpll_global != new_crtc_state->dpll_global) {
> > u8 pipe_mask = BIT(crtc->pipe);
> > - struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
> > + struct intel_dpll_global *pll = old_crtc_state->dpll_global;
> >
> > INTEL_DISPLAY_STATE_WARN(display, pll->active_mask &
> pipe_mask,
> > "%s: pll active mismatch (didn't expect
> pipe %c in active mask (0x%x))\n",
> > pll->info->name, pipe_name(crtc-
> >pipe), pll->active_mask);
> >
> > /* TC ports have both MG/TC and TBT PLL referenced
> simultaneously */
> > - INTEL_DISPLAY_STATE_WARN(display,
> !has_alt_port_dpll(old_crtc_state->shared_dpll,
> > -
> new_crtc_state->shared_dpll) &&
> > + INTEL_DISPLAY_STATE_WARN(display,
> !has_alt_port_dpll(old_crtc_state->dpll_global,
> > +
> new_crtc_state->dpll_global) &&
> > pll->state.pipe_mask & pipe_mask,
> > "%s: pll enabled crtcs mismatch
> (found pipe %c in enabled mask (0x%x))\n",
> > pll->info->name, pipe_name(crtc-
> >pipe), pll->state.pipe_mask);
> > @@ -4718,7 +4718,7 @@ void intel_shared_dpll_state_verify(struct
> intel_atomic_state *state,
> > void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state)
> > {
> > struct intel_display *display = to_intel_display(state);
> > - struct intel_shared_dpll *pll;
> > + struct intel_dpll_global *pll;
> > int i;
> >
> > for_each_dpll(display, pll, i)
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > index 2080118be523..bd52e30d83bd 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > @@ -31,8 +31,8 @@
> > #include "intel_wakeref.h"
> >
> > #define for_each_dpll(__display, __pll, __i) \
> > - for ((__i) = 0; (__i) < (__display)->dpll.num_shared_dpll && \
> > - ((__pll) = &(__display)->dpll.shared_dplls[(__i)]) ; (__i)++)
> > + for ((__i) = 0; (__i) < (__display)->dpll.num_dpll_global && \
> > + ((__pll) = &(__display)->dpll.dpll_globals[(__i)]) ; (__i)++)
> >
> > enum tc_port;
> > struct drm_printer;
> > @@ -344,9 +344,9 @@ struct dpll_info {
> > };
> >
> > /**
> > - * struct intel_shared_dpll - display PLL with tracked state and users
> > + * struct intel_dpll_global - display PLL with tracked state and users
> > */
> > -struct intel_shared_dpll {
> > +struct intel_dpll_global {
> > /**
> > * @state:
> > *
> > @@ -388,11 +388,11 @@ struct intel_shared_dpll {
> > #define SKL_DPLL3 3
> >
> > /* shared dpll functions */
> > -struct intel_shared_dpll *
> > +struct intel_dpll_global *
> > intel_get_shared_dpll_by_id(struct intel_display *display,
> > enum intel_dpll_id id);
> > void assert_shared_dpll(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll_global *pll,
> > bool state);
> > #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
> > #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
> > @@ -405,7 +405,7 @@ int intel_reserve_shared_dplls(struct
> intel_atomic_state *state,
> > void intel_release_shared_dplls(struct intel_atomic_state *state,
> > struct intel_crtc *crtc);
> > void intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
> > - const struct intel_shared_dpll *pll,
> > + const struct intel_dpll_global *pll,
> > struct intel_dpll_state
> *shared_dpll_state);
> > void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
> > enum icl_port_dpll_id port_dpll_id);
> > @@ -413,10 +413,10 @@ void intel_update_active_dpll(struct
> intel_atomic_state *state,
> > struct intel_crtc *crtc,
> > struct intel_encoder *encoder);
> > int intel_dpll_get_freq(struct intel_display *display,
> > - const struct intel_shared_dpll *pll,
> > + const struct intel_dpll_global *pll,
> > const struct intel_dpll_hw_state *dpll_hw_state);
> > bool intel_dpll_get_hw_state(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll_global *pll,
> > struct intel_dpll_hw_state *dpll_hw_state);
> > void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
> > void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
> > diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c
> b/drivers/gpu/drm/i915/display/intel_fdi.c
> > index 40deee0769ae..acc0b45eced0 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fdi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fdi.c
> > @@ -911,7 +911,7 @@ void hsw_fdi_link_train(struct intel_encoder
> *encoder,
> > intel_de_write(display, FDI_RX_CTL(PIPE_A), rx_ctl_val);
> >
> > /* Configure Port Clock Select */
> > - drm_WARN_ON(display->drm, crtc_state->shared_dpll->info->id !=
> DPLL_ID_SPLL);
> > + drm_WARN_ON(display->drm, crtc_state->dpll_global->info->id !=
> DPLL_ID_SPLL);
> > intel_ddi_enable_clock(encoder, crtc_state);
> >
> > /* Start the training iterating through available voltages and emphasis,
> > diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c
> b/drivers/gpu/drm/i915/display/intel_lvds.c
> > index 89d26913e253..bc8725aa99da 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lvds.c
> > +++ b/drivers/gpu/drm/i915/display/intel_lvds.c
> > @@ -251,7 +251,7 @@ static void intel_pre_enable_lvds(struct
> intel_atomic_state *state,
> >
> > if (HAS_PCH_SPLIT(i915)) {
> > assert_fdi_rx_pll_disabled(display, pipe);
> > - assert_shared_dpll_disabled(display, crtc_state->shared_dpll);
> > + assert_shared_dpll_disabled(display, crtc_state->dpll_global);
> > } else {
> > assert_pll_disabled(display, pipe);
> > }
> > diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > index 3cc915739677..427eff400b53 100644
> > --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > @@ -91,10 +91,10 @@ static void intel_crtc_disable_noatomic_begin(struct
> intel_crtc *crtc,
> > crtc->active = false;
> > crtc->base.enabled = false;
> >
> > - if (crtc_state->shared_dpll)
> > + if (crtc_state->dpll_global)
> > intel_unreference_shared_dpll_crtc(crtc,
> > - crtc_state->shared_dpll,
> > - &crtc_state->shared_dpll-
> >state);
> > + crtc_state->dpll_global,
> > + &crtc_state->dpll_global-
> >state);
> > }
> >
> > static void set_encoder_for_connector(struct intel_connector *connector,
> > @@ -568,7 +568,7 @@ static bool has_bogus_dpll_config(const struct
> intel_crtc_state *crtc_state)
> > */
> > return IS_SANDYBRIDGE(i915) &&
> > crtc_state->hw.active &&
> > - crtc_state->shared_dpll &&
> > + crtc_state->dpll_global &&
> > crtc_state->port_clock == 0;
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c
> b/drivers/gpu/drm/i915/display/intel_pch_display.c
> > index b909ed18a5b2..57303ecb77ad 100644
> > --- a/drivers/gpu/drm/i915/display/intel_pch_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
> > @@ -255,7 +255,7 @@ static void ilk_enable_pch_transcoder(const struct
> intel_crtc_state *crtc_state)
> > u32 val, pipeconf_val;
> >
> > /* Make sure PCH DPLL is enabled */
> > - assert_shared_dpll_enabled(display, crtc_state->shared_dpll);
> > + assert_shared_dpll_enabled(display, crtc_state->dpll_global);
> >
> > /* FDI must be feeding us bits for PCH ports */
> > assert_fdi_tx_enabled(display, pipe);
> > @@ -387,7 +387,7 @@ void ilk_pch_enable(struct intel_atomic_state *state,
> > temp = intel_de_read(display, PCH_DPLL_SEL);
> > temp |= TRANS_DPLL_ENABLE(pipe);
> > sel = TRANS_DPLLB_SEL(pipe);
> > - if (crtc_state->shared_dpll ==
> > + if (crtc_state->dpll_global ==
> > intel_get_shared_dpll_by_id(display, DPLL_ID_PCH_PLL_B))
> > temp |= sel;
> > else
> > @@ -504,7 +504,7 @@ void ilk_pch_get_config(struct intel_crtc_state
> *crtc_state)
> > struct intel_display *display = to_intel_display(crtc_state);
> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > - struct intel_shared_dpll *pll;
> > + struct intel_dpll_global *pll;
> > enum pipe pipe = crtc->pipe;
> > enum intel_dpll_id pll_id;
> > bool pll_active;
> > @@ -536,8 +536,8 @@ void ilk_pch_get_config(struct intel_crtc_state
> *crtc_state)
> > pll_id = DPLL_ID_PCH_PLL_A;
> > }
> >
> > - crtc_state->shared_dpll = intel_get_shared_dpll_by_id(display, pll_id);
> > - pll = crtc_state->shared_dpll;
> > + crtc_state->dpll_global = intel_get_shared_dpll_by_id(display, pll_id);
> > + pll = crtc_state->dpll_global;
> >
> > pll_active = intel_dpll_get_hw_state(display, pll,
> > &crtc_state->dpll_hw_state);
> > diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> > index 611f3b8dffef..24e050d00db9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> > @@ -500,7 +500,7 @@ static void ilk_init_pch_refclk(struct intel_display
> *display)
> > {
> > struct drm_i915_private *dev_priv = to_i915(display->drm);
> > struct intel_encoder *encoder;
> > - struct intel_shared_dpll *pll;
> > + struct intel_dpll_global *pll;
> > int i;
> > u32 val, final;
> > bool has_lvds = false;
>
> --
> Jani Nikula, Intel
^ permalink raw reply [flat|nested] 31+ messages in thread
* RE: [PATCH 05/16] drm/i915/dpll: Move away from using shared dpll
2025-04-03 15:03 ` Jani Nikula
@ 2025-04-03 15:17 ` Kandpal, Suraj
0 siblings, 0 replies; 31+ messages in thread
From: Kandpal, Suraj @ 2025-04-03 15:17 UTC (permalink / raw)
To: Nikula, Jani, intel-xe@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org
Cc: Nautiyal, Ankit K, Shankar, Uma, Kahola, Mika, Syrjala, Ville
> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Thursday, April 3, 2025 8:33 PM
> To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-xe@lists.freedesktop.org;
> intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Shankar, Uma
> <uma.shankar@intel.com>; Kahola, Mika <mika.kahola@intel.com>; Syrjala,
> Ville <ville.syrjala@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>
> Subject: Re: [PATCH 05/16] drm/i915/dpll: Move away from using shared dpll
>
> On Wed, 02 Apr 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> > Rename functions to move away from using shared dpll in the dpll
> > framework as much as possible since dpll may not always be shared.
> >
> > --v2
> > -Use intel_dpll_global instead of global_dpll [Jani]
>
> I regret I didn't perhaps think this through in my earlier review, or didn't get the
> message across, but... why not just drop both shared and global? Just dpll.
>
I think that can be done if one of my previous comments in the previous patch makes sense and I can
Spin a new revision more towards this approach of dropping both global and shared
Regards,
Suraj Kandpal
>
> >
> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 14 +-
> > drivers/gpu/drm/i915/display/intel_display.c | 8 +-
> > .../drm/i915/display/intel_display_driver.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_dpll.c | 10 +-
> > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 150
> > +++++++++--------- drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 32 ++--
> > drivers/gpu/drm/i915/display/intel_lvds.c | 2 +-
> > .../drm/i915/display/intel_modeset_setup.c | 2 +-
> > .../drm/i915/display/intel_modeset_verify.c | 4 +-
> > .../gpu/drm/i915/display/intel_pch_display.c | 14 +-
> > 10 files changed, 119 insertions(+), 119 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index a8934ea5077d..3fe330bf2636 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -1567,7 +1567,7 @@ _icl_ddi_get_pll(struct intel_display *display,
> > i915_reg_t reg,
> >
> > id = (intel_de_read(display, reg) & clk_sel_mask) >> clk_sel_shift;
> >
> > - return intel_get_shared_dpll_by_id(display, id);
> > + return intel_get_dpll_global_by_id(display, id);
> > }
> >
> > static void adls_ddi_enable_clock(struct intel_encoder *encoder, @@
> > -1721,7 +1721,7 @@ static struct intel_dpll_global *dg1_ddi_get_pll(struct
> intel_encoder *encoder)
> > if (phy >= PHY_C)
> > id += DPLL_ID_DG1_DPLL2;
> >
> > - return intel_get_shared_dpll_by_id(display, id);
> > + return intel_get_dpll_global_by_id(display, id);
> > }
> >
> > static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
> > @@ -1893,7 +1893,7 @@ static struct intel_dpll_global
> *icl_ddi_tc_get_pll(struct intel_encoder *encode
> > return NULL;
> > }
> >
> > - return intel_get_shared_dpll_by_id(display, id);
> > + return intel_get_dpll_global_by_id(display, id);
> > }
> >
> > static struct intel_dpll_global *bxt_ddi_get_pll(struct intel_encoder
> > *encoder) @@ -1916,7 +1916,7 @@ static struct intel_dpll_global
> *bxt_ddi_get_pll(struct intel_encoder *encoder)
> > return NULL;
> > }
> >
> > - return intel_get_shared_dpll_by_id(display, id);
> > + return intel_get_dpll_global_by_id(display, id);
> > }
> >
> > static void skl_ddi_enable_clock(struct intel_encoder *encoder, @@
> > -1984,7 +1984,7 @@ static struct intel_dpll_global *skl_ddi_get_pll(struct
> intel_encoder *encoder)
> > id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >>
> > DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port);
> >
> > - return intel_get_shared_dpll_by_id(display, id);
> > + return intel_get_dpll_global_by_id(display, id);
> > }
> >
> > void hsw_ddi_enable_clock(struct intel_encoder *encoder, @@ -2051,7
> > +2051,7 @@ static struct intel_dpll_global *hsw_ddi_get_pll(struct
> intel_encoder *encoder)
> > return NULL;
> > }
> >
> > - return intel_get_shared_dpll_by_id(display, id);
> > + return intel_get_dpll_global_by_id(display, id);
> > }
> >
> > void intel_ddi_enable_clock(struct intel_encoder *encoder, @@ -2758,7
> > +2758,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state
> *state,
> > * 4. Enable the port PLL.
> > *
> > * The PLL enabling itself was already done before this function by
> > - * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only
> > + * hsw_crtc_enable()->intel_enable_dpll_global(). We need only
> > * configure the PLL to port mapping here.
> > */
> > intel_ddi_enable_clock(encoder, crtc_state); diff --git
> > a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 5b808bad61e0..904b9544515b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -1662,7 +1662,7 @@ static void hsw_crtc_enable(struct
> intel_atomic_state *state,
> > intel_encoders_pre_pll_enable(state, crtc);
> >
> > if (new_crtc_state->dpll_global)
> > - intel_enable_shared_dpll(new_crtc_state);
> > + intel_enable_dpll_global(new_crtc_state);
> >
> > intel_encoders_pre_enable(state, crtc);
> >
> > @@ -1791,7 +1791,7 @@ static void hsw_crtc_disable(struct
> intel_atomic_state *state,
> > intel_encoders_disable(state, crtc);
> > intel_encoders_post_disable(state, crtc);
> >
> > - intel_disable_shared_dpll(old_crtc_state);
> > + intel_disable_dpll_global(old_crtc_state);
> >
> > intel_encoders_post_pll_disable(state, crtc);
> >
> > @@ -6429,7 +6429,7 @@ int intel_atomic_check(struct drm_device *dev,
> >
> > any_ms = true;
> >
> > - intel_release_shared_dplls(state, crtc);
> > + intel_release_dpll_globals(state, crtc);
> > }
> >
> > if (any_ms && !check_digital_port_conflicts(state)) { @@ -7523,7
> > +7523,7 @@ static int intel_atomic_swap_state(struct
> > intel_atomic_state *state)
> >
> > intel_atomic_swap_global_state(state);
> >
> > - intel_shared_dpll_swap_state(state);
> > + intel_dpll_swap_state(state);
> >
> > intel_atomic_track_fbs(state);
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c
> > b/drivers/gpu/drm/i915/display/intel_display_driver.c
> > index 4edadebad13b..b6c670c54eb1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> > @@ -441,7 +441,7 @@ int intel_display_driver_probe_nogem(struct
> intel_display *display)
> > }
> >
> > intel_plane_possible_crtcs_init(display);
> > - intel_shared_dpll_init(display);
> > + intel_dpll_global_init(display);
> > intel_fdi_pll_freq_update(display);
> >
> > intel_update_czclk(display);
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c
> > b/drivers/gpu/drm/i915/display/intel_dpll.c
> > index c6d29382378b..04fb76a399ab 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> > @@ -1162,7 +1162,7 @@ static int hsw_crtc_compute_clock(struct
> intel_atomic_state *state,
> > intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
> > return 0;
> >
> > - ret = intel_compute_shared_dplls(state, crtc, encoder);
> > + ret = intel_compute_dpll_globals(state, crtc, encoder);
> > if (ret)
> > return ret;
> >
> > @@ -1190,7 +1190,7 @@ static int hsw_crtc_get_shared_dpll(struct
> intel_atomic_state *state,
> > intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
> > return 0;
> >
> > - return intel_reserve_shared_dplls(state, crtc, encoder);
> > + return intel_reserve_dpll_globals(state, crtc, encoder);
> > }
> >
> > static int dg2_crtc_compute_clock(struct intel_atomic_state *state,
> > @@ -1224,7 +1224,7 @@ static int mtl_crtc_compute_clock(struct
> intel_atomic_state *state,
> > if (ret)
> > return ret;
> >
> > - /* TODO: Do the readback via intel_compute_shared_dplls() */
> > + /* TODO: Do the readback via intel_compute_dpll_globals() */
> > crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder,
> > &crtc_state->dpll_hw_state.cx0pll);
> >
> > crtc_state->hw.adjusted_mode.crtc_clock =
> > intel_crtc_dotclock(crtc_state); @@ -1397,7 +1397,7 @@ static int
> ilk_crtc_compute_clock(struct intel_atomic_state *state,
> > ilk_compute_dpll(crtc_state, &crtc_state->dpll,
> > &crtc_state->dpll);
> >
> > - ret = intel_compute_shared_dplls(state, crtc, NULL);
> > + ret = intel_compute_dpll_globals(state, crtc, NULL);
> > if (ret)
> > return ret;
> >
> > @@ -1417,7 +1417,7 @@ static int ilk_crtc_get_shared_dpll(struct
> intel_atomic_state *state,
> > if (!crtc_state->has_pch_encoder)
> > return 0;
> >
> > - return intel_reserve_shared_dplls(state, crtc, NULL);
> > + return intel_reserve_dpll_globals(state, crtc, NULL);
> > }
> >
> > static u32 vlv_dpll(const struct intel_crtc_state *crtc_state) diff
> > --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > index 833c90f3f0f1..e6546d735799 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > @@ -49,21 +49,21 @@
> > * share a PLL if their configurations match.
> > *
> > * This file provides an abstraction over display PLLs. The function
> > - * intel_shared_dpll_init() initializes the PLLs for the given
> > platform. The
> > + * intel_dpll_global_init() initializes the PLLs for the given
> > + platform. The
> > * users of a PLL are tracked and that tracking is integrated with the atomic
> > * modset interface. During an atomic operation, required PLLs can be
> reserved
> > * for a given CRTC and encoder configuration by calling
> > - * intel_reserve_shared_dplls() and previously reserved PLLs can be
> > released
> > - * with intel_release_shared_dplls().
> > + * intel_reserve_dpll_globals() and previously reserved PLLs can be
> > + released
> > + * with intel_release_dpll_globals().
> > * Changes to the users are first staged in the atomic state, and
> > then made
> > - * effective by calling intel_shared_dpll_swap_state() during the
> > atomic
> > + * effective by calling intel_dpll_swap_state() during the atomic
> > * commit phase.
> > */
> >
> > /* platform specific hooks for managing DPLLs */ struct
> > intel_dpll_global_funcs {
> > /*
> > - * Hook for enabling the pll, called from intel_enable_shared_dpll() if
> > + * Hook for enabling the pll, called from intel_enable_dpll_global()
> > +if
> > * the pll is not already enabled.
> > */
> > void (*enable)(struct intel_display *display, @@ -71,7 +71,7 @@
> > struct intel_dpll_global_funcs {
> > const struct intel_dpll_hw_state *dpll_hw_state);
> >
> > /*
> > - * Hook for disabling the pll, called from intel_disable_shared_dpll()
> > + * Hook for disabling the pll, called from
> > +intel_disable_dpll_global()
> > * only when it is safe to disable the pll, i.e., there are no more
> > * tracked users for it.
> > */
> > @@ -130,7 +130,7 @@ intel_atomic_duplicate_dpll_state(struct
> > intel_display *display, }
> >
> > static struct intel_dpll_state *
> > -intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
> > +intel_atomic_get_dpll_global_state(struct drm_atomic_state *s)
> > {
> > struct intel_atomic_state *state = to_intel_atomic_state(s);
> > struct intel_display *display = to_intel_display(state); @@ -148,7
> > +148,7 @@ intel_atomic_get_shared_dpll_state(struct drm_atomic_state
> > *s) }
> >
> > /**
> > - * intel_get_shared_dpll_by_id - get a DPLL given its id
> > + * intel_get_dpll_global_by_id - get a DPLL given its id
> > * @display: intel_display device instance
> > * @id: pll id
> > *
> > @@ -156,7 +156,7 @@ intel_atomic_get_shared_dpll_state(struct
> drm_atomic_state *s)
> > * A pointer to the DPLL with @id
> > */
> > struct intel_dpll_global *
> > -intel_get_shared_dpll_by_id(struct intel_display *display,
> > +intel_get_dpll_global_by_id(struct intel_display *display,
> > enum intel_dpll_id id)
> > {
> > struct intel_dpll_global *pll;
> > @@ -172,7 +172,7 @@ intel_get_shared_dpll_by_id(struct intel_display
> > *display, }
> >
> > /* For ILK+ */
> > -void assert_shared_dpll(struct intel_display *display,
> > +void assert_dpll_global(struct intel_display *display,
> > struct intel_dpll_global *pll,
> > bool state)
> > {
> > @@ -247,12 +247,12 @@ static void _intel_disable_shared_dpll(struct
> > intel_display *display, }
> >
> > /**
> > - * intel_enable_shared_dpll - enable a CRTC's shared DPLL
> > - * @crtc_state: CRTC, and its state, which has a shared DPLL
> > + * intel_enable_dpll_global - enable a CRTC's global DPLL
> > + * @crtc_state: CRTC, and its state, which has a DPLL
> > *
> > - * Enable the shared DPLL used by @crtc.
> > + * Enable DPLL used by @crtc.
> > */
> > -void intel_enable_shared_dpll(const struct intel_crtc_state
> > *crtc_state)
> > +void intel_enable_dpll_global(const struct intel_crtc_state
> > +*crtc_state)
> > {
> > struct intel_display *display = to_intel_display(crtc_state);
> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > @@ -279,7 +279,7 @@ void intel_enable_shared_dpll(const struct
> > intel_crtc_state *crtc_state)
> >
> > if (old_mask) {
> > drm_WARN_ON(display->drm, !pll->on);
> > - assert_shared_dpll_enabled(display, pll);
> > + assert_dpll_global_enabled(display, pll);
> > goto out;
> > }
> > drm_WARN_ON(display->drm, pll->on);
> > @@ -293,12 +293,12 @@ void intel_enable_shared_dpll(const struct
> > intel_crtc_state *crtc_state) }
> >
> > /**
> > - * intel_disable_shared_dpll - disable a CRTC's shared DPLL
> > + * intel_disable_dpll_global - disable a CRTC's shared DPLL
> > * @crtc_state: CRTC, and its state, which has a shared DPLL
> > *
> > - * Disable the shared DPLL used by @crtc.
> > + * Disable DPLL used by @crtc.
> > */
> > -void intel_disable_shared_dpll(const struct intel_crtc_state
> > *crtc_state)
> > +void intel_disable_dpll_global(const struct intel_crtc_state
> > +*crtc_state)
> > {
> > struct intel_display *display = to_intel_display(crtc_state);
> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > @@ -323,7 +323,7 @@ void intel_disable_shared_dpll(const struct
> intel_crtc_state *crtc_state)
> > pll->info->name, pll->active_mask, pll->on,
> > crtc->base.base.id, crtc->base.name);
> >
> > - assert_shared_dpll_enabled(display, pll);
> > + assert_dpll_global_enabled(display, pll);
> > drm_WARN_ON(display->drm, !pll->on);
> >
> > pll->active_mask &= ~pipe_mask;
> > @@ -355,7 +355,7 @@ intel_dpll_mask_all(struct intel_display *display)
> > }
> >
> > static struct intel_dpll_global *
> > -intel_find_shared_dpll(struct intel_atomic_state *state,
> > +intel_find_dpll_global(struct intel_atomic_state *state,
> > const struct intel_crtc *crtc,
> > const struct intel_dpll_hw_state *dpll_hw_state,
> > unsigned long dpll_mask)
> > @@ -366,14 +366,14 @@ intel_find_shared_dpll(struct intel_atomic_state
> *state,
> > struct intel_dpll_global *unused_pll = NULL;
> > enum intel_dpll_id id;
> >
> > - dpll_state = intel_atomic_get_shared_dpll_state(&state->base);
> > + dpll_state = intel_atomic_get_dpll_global_state(&state->base);
> >
> > drm_WARN_ON(display->drm, dpll_mask & ~dpll_mask_all);
> >
> > for_each_set_bit(id, &dpll_mask, fls(dpll_mask_all)) {
> > struct intel_dpll_global *pll;
> >
> > - pll = intel_get_shared_dpll_by_id(display, id);
> > + pll = intel_get_dpll_global_by_id(display, id);
> > if (!pll)
> > continue;
> >
> > @@ -409,7 +409,7 @@ intel_find_shared_dpll(struct intel_atomic_state
> > *state, }
> >
> > /**
> > - * intel_reference_shared_dpll_crtc - Get a DPLL reference for a CRTC
> > + * intel_reference_dpll_global_crtc - Get a DPLL reference for a CRTC
> > * @crtc: CRTC on which behalf the reference is taken
> > * @pll: DPLL for which the reference is taken
> > * @dpll_state: the DPLL atomic state in which the reference is
> > tracked @@ -417,7 +417,7 @@ intel_find_shared_dpll(struct
> intel_atomic_state *state,
> > * Take a reference for @pll tracking the use of it by @crtc.
> > */
> > static void
> > -intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc,
> > +intel_reference_dpll_global_crtc(const struct intel_crtc *crtc,
> > const struct intel_dpll_global *pll,
> > struct intel_dpll_state *dpll_state) { @@ -
> 432,23 +432,23 @@
> > intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc, }
> >
> > static void
> > -intel_reference_shared_dpll(struct intel_atomic_state *state,
> > +intel_reference_dpll_global(struct intel_atomic_state *state,
> > const struct intel_crtc *crtc,
> > const struct intel_dpll_global *pll,
> > const struct intel_dpll_hw_state *dpll_hw_state) {
> > struct intel_dpll_state *dpll_state;
> >
> > - dpll_state = intel_atomic_get_shared_dpll_state(&state->base);
> > + dpll_state = intel_atomic_get_dpll_global_state(&state->base);
> >
> > if (dpll_state[pll->index].pipe_mask == 0)
> > dpll_state[pll->index].hw_state = *dpll_hw_state;
> >
> > - intel_reference_shared_dpll_crtc(crtc, pll, &dpll_state[pll->index]);
> > + intel_reference_dpll_global_crtc(crtc, pll,
> > +&dpll_state[pll->index]);
> > }
> >
> > /**
> > - * intel_unreference_shared_dpll_crtc - Drop a DPLL reference for a
> > CRTC
> > + * intel_unreference_dpll_global_crtc - Drop a DPLL reference for a
> > + CRTC
> > * @crtc: CRTC on which behalf the reference is dropped
> > * @pll: DPLL for which the reference is dropped
> > * @dpll_state: the DPLL atomic state in which the reference is
> > tracked @@ -456,7 +456,7 @@ intel_reference_shared_dpll(struct
> intel_atomic_state *state,
> > * Drop a reference for @pll tracking the end of use of it by @crtc.
> > */
> > void
> > -intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
> > +intel_unreference_dpll_global_crtc(const struct intel_crtc *crtc,
> > const struct intel_dpll_global *pll,
> > struct intel_dpll_state *dpll_state) { @@ -
> 470,15 +470,15 @@
> > intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
> > crtc->base.base.id, crtc->base.name, pll->info->name); }
> >
> > -static void intel_unreference_shared_dpll(struct intel_atomic_state
> > *state,
> > +static void intel_unreference_dpll_global(struct intel_atomic_state
> > +*state,
> > const struct intel_crtc *crtc,
> > const struct intel_dpll_global *pll) {
> > struct intel_dpll_state *dpll_state;
> >
> > - dpll_state = intel_atomic_get_shared_dpll_state(&state->base);
> > + dpll_state = intel_atomic_get_dpll_global_state(&state->base);
> >
> > - intel_unreference_shared_dpll_crtc(crtc, pll, &dpll_state[pll->index]);
> > + intel_unreference_dpll_global_crtc(crtc, pll,
> > +&dpll_state[pll->index]);
> > }
> >
> > static void intel_put_dpll(struct intel_atomic_state *state, @@
> > -494,11 +494,11 @@ static void intel_put_dpll(struct intel_atomic_state
> *state,
> > if (!old_crtc_state->dpll_global)
> > return;
> >
> > - intel_unreference_shared_dpll(state, crtc, old_crtc_state-
> >dpll_global);
> > + intel_unreference_dpll_global(state, crtc,
> > +old_crtc_state->dpll_global);
> > }
> >
> > /**
> > - * intel_shared_dpll_swap_state - make atomic DPLL configuration
> > effective
> > + * intel_dpll_swap_state - make atomic DPLL configuration effective
> > * @state: atomic state
> > *
> > * This is the dpll version of drm_atomic_helper_swap_state() since
> > the @@ -508,7 +508,7 @@ static void intel_put_dpll(struct
> intel_atomic_state *state,
> > * i.e. it also puts the current state into @state, even though there is no
> > * need for that at this moment.
> > */
> > -void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
> > +void intel_dpll_swap_state(struct intel_atomic_state *state)
> > {
> > struct intel_display *display = to_intel_display(state);
> > struct intel_dpll_state *dpll_state = state->dpll_state; @@ -618,14
> > +618,14 @@ static int ibx_get_dpll(struct intel_atomic_state *state,
> > if (HAS_PCH_IBX(i915)) {
> > /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
> > id = (enum intel_dpll_id) crtc->pipe;
> > - pll = intel_get_shared_dpll_by_id(display, id);
> > + pll = intel_get_dpll_global_by_id(display, id);
> >
> > drm_dbg_kms(display->drm,
> > "[CRTC:%d:%s] using pre-allocated %s\n",
> > crtc->base.base.id, crtc->base.name,
> > pll->info->name);
> > } else {
> > - pll = intel_find_shared_dpll(state, crtc,
> > + pll = intel_find_dpll_global(state, crtc,
> > &crtc_state->dpll_hw_state,
> > BIT(DPLL_ID_PCH_PLL_B) |
> > BIT(DPLL_ID_PCH_PLL_A));
> > @@ -635,7 +635,7 @@ static int ibx_get_dpll(struct intel_atomic_state
> *state,
> > return -EINVAL;
> >
> > /* reference the pll */
> > - intel_reference_shared_dpll(state, crtc,
> > + intel_reference_dpll_global(state, crtc,
> > pll, &crtc_state->dpll_hw_state);
> >
> > crtc_state->dpll_global = pll;
> > @@ -1064,7 +1064,7 @@ hsw_ddi_wrpll_get_dpll(struct intel_atomic_state
> *state,
> > struct intel_crtc_state *crtc_state =
> > intel_atomic_get_new_crtc_state(state, crtc);
> >
> > - return intel_find_shared_dpll(state, crtc,
> > + return intel_find_dpll_global(state, crtc,
> > &crtc_state->dpll_hw_state,
> > BIT(DPLL_ID_WRPLL2) |
> > BIT(DPLL_ID_WRPLL1));
> > @@ -1111,7 +1111,7 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state
> *crtc_state)
> > return NULL;
> > }
> >
> > - pll = intel_get_shared_dpll_by_id(display, pll_id);
> > + pll = intel_get_dpll_global_by_id(display, pll_id);
> >
> > if (!pll)
> > return NULL;
> > @@ -1167,7 +1167,7 @@ hsw_ddi_spll_get_dpll(struct intel_atomic_state
> *state,
> > struct intel_crtc_state *crtc_state =
> > intel_atomic_get_new_crtc_state(state, crtc);
> >
> > - return intel_find_shared_dpll(state, crtc, &crtc_state->dpll_hw_state,
> > + return intel_find_dpll_global(state, crtc,
> > +&crtc_state->dpll_hw_state,
> > BIT(DPLL_ID_SPLL));
> > }
> >
> > @@ -1231,7 +1231,7 @@ static int hsw_get_dpll(struct intel_atomic_state
> *state,
> > if (!pll)
> > return -EINVAL;
> >
> > - intel_reference_shared_dpll(state, crtc,
> > + intel_reference_dpll_global(state, crtc,
> > pll, &crtc_state->dpll_hw_state);
> >
> > crtc_state->dpll_global = pll;
> > @@ -1940,11 +1940,11 @@ static int skl_get_dpll(struct intel_atomic_state
> *state,
> > struct intel_dpll_global *pll;
> >
> > if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> > - pll = intel_find_shared_dpll(state, crtc,
> > + pll = intel_find_dpll_global(state, crtc,
> > &crtc_state->dpll_hw_state,
> > BIT(DPLL_ID_SKL_DPLL0));
> > else
> > - pll = intel_find_shared_dpll(state, crtc,
> > + pll = intel_find_dpll_global(state, crtc,
> > &crtc_state->dpll_hw_state,
> > BIT(DPLL_ID_SKL_DPLL3) |
> > BIT(DPLL_ID_SKL_DPLL2) |
> > @@ -1952,7 +1952,7 @@ static int skl_get_dpll(struct intel_atomic_state
> *state,
> > if (!pll)
> > return -EINVAL;
> >
> > - intel_reference_shared_dpll(state, crtc,
> > + intel_reference_dpll_global(state, crtc,
> > pll, &crtc_state->dpll_hw_state);
> >
> > crtc_state->dpll_global = pll;
> > @@ -2432,12 +2432,12 @@ static int bxt_get_dpll(struct
> > intel_atomic_state *state,
> >
> > /* 1:1 mapping between ports and PLLs */
> > id = (enum intel_dpll_id) encoder->port;
> > - pll = intel_get_shared_dpll_by_id(display, id);
> > + pll = intel_get_dpll_global_by_id(display, id);
> >
> > drm_dbg_kms(display->drm, "[CRTC:%d:%s] using pre-allocated %s\n",
> > crtc->base.base.id, crtc->base.name, pll->info->name);
> >
> > - intel_reference_shared_dpll(state, crtc,
> > + intel_reference_dpll_global(state, crtc,
> > pll, &crtc_state->dpll_hw_state);
> >
> > crtc_state->dpll_global = pll;
> > @@ -3388,13 +3388,13 @@ static int icl_get_combo_phy_dpll(struct
> intel_atomic_state *state,
> > /* Eliminate DPLLs from consideration if reserved by HTI */
> > dpll_mask &= ~intel_hti_dpll_mask(display);
> >
> > - port_dpll->pll = intel_find_shared_dpll(state, crtc,
> > + port_dpll->pll = intel_find_dpll_global(state, crtc,
> > &port_dpll->hw_state,
> > dpll_mask);
> > if (!port_dpll->pll)
> > return -EINVAL;
> >
> > - intel_reference_shared_dpll(state, crtc,
> > + intel_reference_dpll_global(state, crtc,
> > port_dpll->pll, &port_dpll->hw_state);
> >
> > icl_update_active_dpll(state, crtc, encoder); @@ -3452,25 +3452,25
> > @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
> > int ret;
> >
> > port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
> > - port_dpll->pll = intel_find_shared_dpll(state, crtc,
> > + port_dpll->pll = intel_find_dpll_global(state, crtc,
> > &port_dpll->hw_state,
> > BIT(DPLL_ID_ICL_TBTPLL));
> > if (!port_dpll->pll)
> > return -EINVAL;
> > - intel_reference_shared_dpll(state, crtc,
> > + intel_reference_dpll_global(state, crtc,
> > port_dpll->pll, &port_dpll->hw_state);
> >
> >
> > port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
> > dpll_id = icl_tc_port_to_pll_id(intel_encoder_to_tc(encoder));
> > - port_dpll->pll = intel_find_shared_dpll(state, crtc,
> > + port_dpll->pll = intel_find_dpll_global(state, crtc,
> > &port_dpll->hw_state,
> > BIT(dpll_id));
> > if (!port_dpll->pll) {
> > ret = -EINVAL;
> > goto err_unreference_tbt_pll;
> > }
> > - intel_reference_shared_dpll(state, crtc,
> > + intel_reference_dpll_global(state, crtc,
> > port_dpll->pll, &port_dpll->hw_state);
> >
> > icl_update_active_dpll(state, crtc, encoder); @@ -3479,7 +3479,7 @@
> > static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
> >
> > err_unreference_tbt_pll:
> > port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
> > - intel_unreference_shared_dpll(state, crtc, port_dpll->pll);
> > + intel_unreference_dpll_global(state, crtc, port_dpll->pll);
> >
> > return ret;
> > }
> > @@ -3534,7 +3534,7 @@ static void icl_put_dplls(struct intel_atomic_state
> *state,
> > if (!old_port_dpll->pll)
> > continue;
> >
> > - intel_unreference_shared_dpll(state, crtc, old_port_dpll->pll);
> > + intel_unreference_dpll_global(state, crtc, old_port_dpll->pll);
> > }
> > }
> >
> > @@ -4300,12 +4300,12 @@ static const struct intel_dpll_mgr
> > adlp_pll_mgr = { };
> >
> > /**
> > - * intel_shared_dpll_init - Initialize shared DPLLs
> > + * intel_dpll_global_init - Initialize DPLLs
> > * @display: intel_display device
> > *
> > - * Initialize shared DPLLs for @display.
> > + * Initialize DPLLs for @display.
> > */
> > -void intel_shared_dpll_init(struct intel_display *display)
> > +void intel_dpll_global_init(struct intel_display *display)
> > {
> > struct drm_i915_private *i915 = to_i915(display->drm);
> > const struct intel_dpll_mgr *dpll_mgr = NULL; @@ -4363,7 +4363,7
> @@
> > void intel_shared_dpll_init(struct intel_display *display) }
> >
> > /**
> > - * intel_compute_shared_dplls - compute DPLL state CRTC and encoder
> > combination
> > + * intel_compute_dpll_globals - compute DPLL state CRTC and encoder
> > + combination
> > * @state: atomic state
> > * @crtc: CRTC to compute DPLLs for
> > * @encoder: encoder
> > @@ -4371,12 +4371,12 @@ void intel_shared_dpll_init(struct intel_display
> *display)
> > * This function computes the DPLL state for the given CRTC and encoder.
> > *
> > * The new configuration in the atomic commit @state is made
> > effective by
> > - * calling intel_shared_dpll_swap_state().
> > + * calling intel_dpll_swap_state().
> > *
> > * Returns:
> > * 0 on success, negative error code on failure.
> > */
> > -int intel_compute_shared_dplls(struct intel_atomic_state *state,
> > +int intel_compute_dpll_globals(struct intel_atomic_state *state,
> > struct intel_crtc *crtc,
> > struct intel_encoder *encoder) { @@ -4390,7
> +4390,7 @@ int
> > intel_compute_shared_dplls(struct intel_atomic_state *state, }
> >
> > /**
> > - * intel_reserve_shared_dplls - reserve DPLLs for CRTC and encoder
> > combination
> > + * intel_reserve_dpll_globals - reserve DPLLs for CRTC and encoder
> > + combination
> > * @state: atomic state
> > * @crtc: CRTC to reserve DPLLs for
> > * @encoder: encoder
> > @@ -4400,16 +4400,16 @@ int intel_compute_shared_dplls(struct
> intel_atomic_state *state,
> > * state.
> > *
> > * The new configuration in the atomic commit @state is made
> > effective by
> > - * calling intel_shared_dpll_swap_state().
> > + * calling intel_dpll_swap_state().
> > *
> > * The reserved DPLLs should be released by calling
> > - * intel_release_shared_dplls().
> > + * intel_release_dpll_globals().
> > *
> > * Returns:
> > * 0 if all required DPLLs were successfully reserved,
> > * negative error code otherwise.
> > */
> > -int intel_reserve_shared_dplls(struct intel_atomic_state *state,
> > +int intel_reserve_dpll_globals(struct intel_atomic_state *state,
> > struct intel_crtc *crtc,
> > struct intel_encoder *encoder) { @@ -4423,17
> +4423,17 @@
> > int intel_reserve_shared_dplls(struct intel_atomic_state *state, }
> >
> > /**
> > - * intel_release_shared_dplls - end use of DPLLs by CRTC in atomic
> > state
> > + * intel_release_dpll_globals - end use of DPLLs by CRTC in atomic
> > + state
> > * @state: atomic state
> > * @crtc: crtc from which the DPLLs are to be released
> > *
> > - * This function releases all DPLLs reserved by
> > intel_reserve_shared_dplls()
> > + * This function releases all DPLLs reserved by
> > + intel_reserve_dpll_globals()
> > * from the current atomic commit @state and the old @crtc atomic state.
> > *
> > * The new configuration in the atomic commit @state is made
> > effective by
> > - * calling intel_shared_dpll_swap_state().
> > + * calling intel_dpll_swap_state().
> > */
> > -void intel_release_shared_dplls(struct intel_atomic_state *state,
> > +void intel_release_dpll_globals(struct intel_atomic_state *state,
> > struct intel_crtc *crtc)
> > {
> > struct intel_display *display = to_intel_display(state); @@ -4442,7
> > +4442,7 @@ void intel_release_shared_dplls(struct intel_atomic_state
> *state,
> > /*
> > * FIXME: this function is called for every platform having a
> > * compute_clock hook, even though the platform doesn't yet support
> > - * the shared DPLL framework and intel_reserve_shared_dplls() is not
> > + * the global DPLL framework and intel_reserve_dpll_globals() is not
> > * called on those.
> > */
> > if (!dpll_mgr)
> > @@ -4458,7 +4458,7 @@ void intel_release_shared_dplls(struct
> intel_atomic_state *state,
> > * @encoder: encoder determining the type of port DPLL
> > *
> > * Update the active DPLL for the given @crtc/@encoder in @crtc's
> > atomic state,
> > - * from the port DPLLs reserved previously by
> > intel_reserve_shared_dplls(). The
> > + * from the port DPLLs reserved previously by
> > + intel_reserve_dpll_globals(). The
> > * DPLL selected will be based on the current mode of the encoder's port.
> > */
> > void intel_update_active_dpll(struct intel_atomic_state *state, @@
> > -4523,7 +4523,7 @@ static void readout_dpll_hw_state(struct intel_display
> *display,
> > to_intel_crtc_state(crtc->base.state);
> >
> > if (crtc_state->hw.active && crtc_state->dpll_global == pll)
> > - intel_reference_shared_dpll_crtc(crtc, pll, &pll->state);
> > + intel_reference_dpll_global_crtc(crtc, pll, &pll->state);
> > }
> > pll->active_mask = pll->state.pipe_mask;
> >
> > @@ -4684,8 +4684,8 @@ static bool has_alt_port_dpll(const struct
> intel_dpll_global *old_pll,
> > (old_pll->info->is_alt_port_dpll ||
> > new_pll->info->is_alt_port_dpll); }
> >
> > -void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
> > - struct intel_crtc *crtc)
> > +void intel_dpll_state_verify(struct intel_atomic_state *state,
> > + struct intel_crtc *crtc)
> > {
> > struct intel_display *display = to_intel_display(state);
> > const struct intel_crtc_state *old_crtc_state = @@ -4715,7 +4715,7
> > @@ void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
> > }
> > }
> >
> > -void intel_shared_dpll_verify_disabled(struct intel_atomic_state
> > *state)
> > +void intel_dpll_global_verify_disabled(struct intel_atomic_state
> > +*state)
> > {
> > struct intel_display *display = to_intel_display(state);
> > struct intel_dpll_global *pll;
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > index bd52e30d83bd..6215da164ffc 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > @@ -387,24 +387,24 @@ struct intel_dpll_global { #define SKL_DPLL2 2
> > #define SKL_DPLL3 3
> >
> > -/* shared dpll functions */
> > +/* global dpll functions */
> > struct intel_dpll_global *
> > -intel_get_shared_dpll_by_id(struct intel_display *display,
> > +intel_get_dpll_global_by_id(struct intel_display *display,
> > enum intel_dpll_id id);
> > -void assert_shared_dpll(struct intel_display *display,
> > +void assert_dpll_global(struct intel_display *display,
> > struct intel_dpll_global *pll,
> > bool state);
> > -#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p,
> > true) -#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d,
> > p, false) -int intel_compute_shared_dplls(struct intel_atomic_state
> > *state,
> > +#define assert_dpll_global_enabled(d, p) assert_dpll_global(d, p,
> > +true) #define assert_dpll_global_disabled(d, p) assert_dpll_global(d,
> > +p, false) int intel_compute_dpll_globals(struct intel_atomic_state
> > +*state,
> > struct intel_crtc *crtc,
> > struct intel_encoder *encoder); -int
> > intel_reserve_shared_dplls(struct intel_atomic_state *state,
> > +int intel_reserve_dpll_globals(struct intel_atomic_state *state,
> > struct intel_crtc *crtc,
> > struct intel_encoder *encoder); -void
> > intel_release_shared_dplls(struct intel_atomic_state *state,
> > +void intel_release_dpll_globals(struct intel_atomic_state *state,
> > struct intel_crtc *crtc);
> > -void intel_unreference_shared_dpll_crtc(const struct intel_crtc
> > *crtc,
> > +void intel_unreference_dpll_global_crtc(const struct intel_crtc
> > +*crtc,
> > const struct intel_dpll_global *pll,
> > struct intel_dpll_state
> *shared_dpll_state); void
> > icl_set_active_port_dpll(struct intel_crtc_state *crtc_state, @@
> > -418,10 +418,10 @@ int intel_dpll_get_freq(struct intel_display
> > *display, bool intel_dpll_get_hw_state(struct intel_display *display,
> > struct intel_dpll_global *pll,
> > struct intel_dpll_hw_state *dpll_hw_state); -void
> > intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
> > -void intel_disable_shared_dpll(const struct intel_crtc_state
> > *crtc_state); -void intel_shared_dpll_swap_state(struct
> > intel_atomic_state *state); -void intel_shared_dpll_init(struct
> > intel_display *display);
> > +void intel_enable_dpll_global(const struct intel_crtc_state
> > +*crtc_state); void intel_disable_dpll_global(const struct
> > +intel_crtc_state *crtc_state); void intel_dpll_swap_state(struct
> > +intel_atomic_state *state); void intel_dpll_global_init(struct
> > +intel_display *display);
> > void intel_dpll_update_ref_clks(struct intel_display *display); void
> > intel_dpll_readout_hw_state(struct intel_display *display); void
> > intel_dpll_sanitize_state(struct intel_display *display); @@ -435,8
> > +435,8 @@ bool intel_dpll_compare_hw_state(struct intel_display
> > *display, enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port
> > tc_port); bool intel_dpll_is_combophy(enum intel_dpll_id id);
> >
> > -void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
> > - struct intel_crtc *crtc);
> > -void intel_shared_dpll_verify_disabled(struct intel_atomic_state
> > *state);
> > +void intel_dpll_state_verify(struct intel_atomic_state *state,
> > + struct intel_crtc *crtc);
> > +void intel_dpll_global_verify_disabled(struct intel_atomic_state
> > +*state);
> >
> > #endif /* _INTEL_DPLL_MGR_H_ */
> > diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c
> > b/drivers/gpu/drm/i915/display/intel_lvds.c
> > index bc8725aa99da..52f61a120b70 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lvds.c
> > +++ b/drivers/gpu/drm/i915/display/intel_lvds.c
> > @@ -251,7 +251,7 @@ static void intel_pre_enable_lvds(struct
> > intel_atomic_state *state,
> >
> > if (HAS_PCH_SPLIT(i915)) {
> > assert_fdi_rx_pll_disabled(display, pipe);
> > - assert_shared_dpll_disabled(display, crtc_state->dpll_global);
> > + assert_dpll_global_disabled(display, crtc_state->dpll_global);
> > } else {
> > assert_pll_disabled(display, pipe);
> > }
> > diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > index 427eff400b53..4221d1566c8a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > @@ -92,7 +92,7 @@ static void intel_crtc_disable_noatomic_begin(struct
> intel_crtc *crtc,
> > crtc->base.enabled = false;
> >
> > if (crtc_state->dpll_global)
> > - intel_unreference_shared_dpll_crtc(crtc,
> > + intel_unreference_dpll_global_crtc(crtc,
> > crtc_state->dpll_global,
> > &crtc_state->dpll_global-
> >state); } diff --git
> > a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> > b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> > index a008412fdd04..eb080a1d8a42 100644
> > --- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> > +++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> > @@ -246,7 +246,7 @@ void intel_modeset_verify_crtc(struct
> intel_atomic_state *state,
> > intel_wm_state_verify(state, crtc);
> > verify_connector_state(state, crtc);
> > verify_crtc_state(state, crtc);
> > - intel_shared_dpll_state_verify(state, crtc);
> > + intel_dpll_state_verify(state, crtc);
> > intel_mpllb_state_verify(state, crtc);
> > intel_cx0pll_state_verify(state, crtc); } @@ -255,5 +255,5 @@ void
> > intel_modeset_verify_disabled(struct intel_atomic_state *state) {
> > verify_encoder_state(state);
> > verify_connector_state(state, NULL);
> > - intel_shared_dpll_verify_disabled(state);
> > + intel_dpll_global_verify_disabled(state);
> > }
> > diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c
> > b/drivers/gpu/drm/i915/display/intel_pch_display.c
> > index 57303ecb77ad..aa39d0fb1e23 100644
> > --- a/drivers/gpu/drm/i915/display/intel_pch_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
> > @@ -255,7 +255,7 @@ static void ilk_enable_pch_transcoder(const struct
> intel_crtc_state *crtc_state)
> > u32 val, pipeconf_val;
> >
> > /* Make sure PCH DPLL is enabled */
> > - assert_shared_dpll_enabled(display, crtc_state->dpll_global);
> > + assert_dpll_global_enabled(display, crtc_state->dpll_global);
> >
> > /* FDI must be feeding us bits for PCH ports */
> > assert_fdi_tx_enabled(display, pipe); @@ -388,7 +388,7 @@ void
> > ilk_pch_enable(struct intel_atomic_state *state,
> > temp |= TRANS_DPLL_ENABLE(pipe);
> > sel = TRANS_DPLLB_SEL(pipe);
> > if (crtc_state->dpll_global ==
> > - intel_get_shared_dpll_by_id(display, DPLL_ID_PCH_PLL_B))
> > + intel_get_dpll_global_by_id(display, DPLL_ID_PCH_PLL_B))
> > temp |= sel;
> > else
> > temp &= ~sel;
> > @@ -400,11 +400,11 @@ void ilk_pch_enable(struct intel_atomic_state
> *state,
> > * transcoder, and we actually should do this to not upset any PCH
> > * transcoder that already use the clock when we share it.
> > *
> > - * Note that enable_shared_dpll tries to do the right thing, but
> > - * get_shared_dpll unconditionally resets the pll - we need that
> > + * Note that enable_dpll_global tries to do the right thing, but
> > + * get_dpll_global unconditionally resets the pll - we need that
> > * to have the right LVDS enable sequence.
> > */
> > - intel_enable_shared_dpll(crtc_state);
> > + intel_enable_dpll_global(crtc_state);
> >
> > /* set transcoder timing, panel must allow it */
> > assert_pps_unlocked(display, pipe);
> > @@ -479,7 +479,7 @@ void ilk_pch_post_disable(struct
> > intel_atomic_state *state,
> >
> > ilk_fdi_pll_disable(crtc);
> >
> > - intel_disable_shared_dpll(old_crtc_state);
> > + intel_disable_dpll_global(old_crtc_state);
> > }
> >
> > static void ilk_pch_clock_get(struct intel_crtc_state *crtc_state) @@
> > -536,7 +536,7 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
> > pll_id = DPLL_ID_PCH_PLL_A;
> > }
> >
> > - crtc_state->dpll_global = intel_get_shared_dpll_by_id(display, pll_id);
> > + crtc_state->dpll_global = intel_get_dpll_global_by_id(display,
> > +pll_id);
> > pll = crtc_state->dpll_global;
> >
> > pll_active = intel_dpll_get_hw_state(display, pll,
>
> --
> Jani Nikula, Intel
^ permalink raw reply [flat|nested] 31+ messages in thread
end of thread, other threads:[~2025-04-03 15:17 UTC | newest]
Thread overview: 31+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-04-02 8:31 [PATCH 00/16] DPLL framework redesign Suraj Kandpal
2025-04-02 8:31 ` [PATCH 01/16] drm/i915/dpll: Rename intel_shared_dpll_state Suraj Kandpal
2025-04-02 8:31 ` [PATCH 02/16] drm/i915/dpll: Rename macro for_each_shared_dpll Suraj Kandpal
2025-04-02 8:31 ` [PATCH 03/16] drm/i915/dpll: Rename intel_shared_dpll_funcs Suraj Kandpal
2025-04-03 14:59 ` Jani Nikula
2025-04-03 15:11 ` Kandpal, Suraj
2025-04-02 8:31 ` [PATCH 04/16] drm/i915/dpll: Rename intel_shared_dpll Suraj Kandpal
2025-04-03 15:01 ` Jani Nikula
2025-04-03 15:15 ` Kandpal, Suraj
2025-04-02 8:31 ` [PATCH 05/16] drm/i915/dpll: Move away from using shared dpll Suraj Kandpal
2025-04-03 15:03 ` Jani Nikula
2025-04-03 15:17 ` Kandpal, Suraj
2025-04-02 8:31 ` [PATCH 06/16] drm/i915/dpll: Rename crtc_get_shared_dpll Suraj Kandpal
2025-04-02 8:31 ` [PATCH 07/16] drm/i915/dpll: Change argument for enable hook in intel_global_dpll_funcs Suraj Kandpal
2025-04-02 8:31 ` [PATCH 08/16] drm/i915/drm: Rename disable hook in intel_dpll_global_func Suraj Kandpal
2025-04-02 8:31 ` [PATCH 09/16] drm/i915/dpll: Introduce new " Suraj Kandpal
2025-04-02 8:31 ` [PATCH 10/16] drm/i915/dpll: Add intel_encoder argument to get_hw_state hook Suraj Kandpal
2025-04-02 8:31 ` [PATCH 11/16] drm/i915/dpll: Change arguments for get_freq hook Suraj Kandpal
2025-04-02 8:32 ` [PATCH 12/16] drm/i915/dpll: Rename intel_[enable/disable]_global_dpll Suraj Kandpal
2025-04-02 8:32 ` [PATCH 13/16] drm/i915/dpll: Rename intel_unreference_dpll_global_crtc Suraj Kandpal
2025-04-02 8:32 ` [PATCH 14/16] drm/i915/dpll: Rename intel_<release/reserve>_dpll_globals Suraj Kandpal
2025-04-02 8:32 ` [PATCH 15/16] drm/i915/dpll: Rename intel_compute_dpll_globals Suraj Kandpal
2025-04-02 8:32 ` [PATCH 16/16] drm/i915/dpll: Rename intel_update_active_dpll Suraj Kandpal
2025-04-02 8:39 ` ✓ CI.Patch_applied: success for DPLL framework redesign (rev2) Patchwork
2025-04-02 8:40 ` ✗ CI.checkpatch: warning " Patchwork
2025-04-02 8:41 ` ✓ CI.KUnit: success " Patchwork
2025-04-02 8:58 ` ✓ CI.Build: " Patchwork
2025-04-02 9:00 ` ✓ CI.Hooks: " Patchwork
2025-04-02 9:02 ` ✓ CI.checksparse: " Patchwork
2025-04-02 9:47 ` ✓ Xe.CI.BAT: " Patchwork
2025-04-02 11:01 ` ✗ Xe.CI.Full: failure " Patchwork
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox