* [PATCH v2 0/3] drm/xe: Update Wa_14026539277
@ 2026-07-24 21:44 Gustavo Sousa
2026-07-24 21:44 ` [PATCH v2 1/3] drm/xe: Extract override_has_cached_pt() Gustavo Sousa
` (5 more replies)
0 siblings, 6 replies; 13+ messages in thread
From: Gustavo Sousa @ 2026-07-24 21:44 UTC (permalink / raw)
To: intel-xe; +Cc: Gustavo Sousa
The definition of Wa_14026539277 has been updated in the workaround
database and requires a different implementation. Let's revert the
existing one and then add the up-to-date implementation.
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
Changes in v2:
- Details of the changes are in the patch's changelog.
- Link to v1: https://patch.msgid.link/20260721-wa_14026539277-v1-0-09fa102f3084@intel.com
---
Gustavo Sousa (3):
drm/xe: Extract override_has_cached_pt()
Revert "drm/xe/nvlp: Implement Wa_14026539277"
drm/xe: Add up-to-date implementation for Wa_14026539277
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 4 --
drivers/gpu/drm/xe/xe_pat.h | 10 +++++
drivers/gpu/drm/xe/xe_device.c | 28 ++++++++++----
drivers/gpu/drm/xe/xe_gt.c | 39 --------------------
drivers/gpu/drm/xe/xe_pat.c | 61 ++++++++++++++++++++++++++++---
drivers/gpu/drm/xe/xe_vm.c | 5 +++
drivers/gpu/drm/xe/xe_vm_madvise.c | 3 ++
drivers/gpu/drm/xe/xe_device_wa_oob.rules | 1 -
drivers/gpu/drm/xe/xe_wa_oob.rules | 1 +
9 files changed, 94 insertions(+), 58 deletions(-)
---
base-commit: 03696c1dc9eabc0658baefcff8787dab48c89d93
change-id: 20260701-wa_14026539277-9d39ae09ab75
Best regards,
--
Gustavo Sousa <gustavo.sousa@intel.com>
^ permalink raw reply [flat|nested] 13+ messages in thread* [PATCH v2 1/3] drm/xe: Extract override_has_cached_pt() 2026-07-24 21:44 [PATCH v2 0/3] drm/xe: Update Wa_14026539277 Gustavo Sousa @ 2026-07-24 21:44 ` Gustavo Sousa 2026-07-28 12:42 ` Matthew Auld 2026-07-24 21:44 ` [PATCH v2 2/3] Revert "drm/xe/nvlp: Implement Wa_14026539277" Gustavo Sousa ` (4 subsequent siblings) 5 siblings, 1 reply; 13+ messages in thread From: Gustavo Sousa @ 2026-07-24 21:44 UTC (permalink / raw) To: intel-xe; +Cc: Gustavo Sousa Some platforms support cached page tables, but some workarounds might require disabling the cached access on the CPU side. One such example is Wa_16029380221, but there could be others as well. Extract the code responsible for overriding xe->info.has_cached_pt into a new function called override_has_cached_pt(), so that we have a common place to add the necessary runtime checks specific for has_cached_pt. Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> --- drivers/gpu/drm/xe/xe_device.c | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c index 4eed9a251e65..5189419a0593 100644 --- a/drivers/gpu/drm/xe/xe_device.c +++ b/drivers/gpu/drm/xe/xe_device.c @@ -831,6 +831,21 @@ int xe_device_probe_early(struct xe_device *xe) } ALLOW_ERROR_INJECTION(xe_device_probe_early, ERRNO); /* See xe_pci_probe() */ +static void override_has_cached_pt(struct xe_device *xe) +{ + struct xe_gt *gt; + u8 id; + + /* + * Wa_16029380221: The affected GT will always use non-coherent + * access to page tables, so we must do uncached writes from the + * CPU. + */ + for_each_gt(gt, xe, id) + if (XE_GT_WA(gt, 16029380221)) + xe->info.has_cached_pt = false; +} + static int probe_has_flat_ccs(struct xe_device *xe) { struct xe_gt *gt; @@ -950,14 +965,7 @@ int xe_device_probe(struct xe_device *xe) return err; } - /* - * Wa_16029380221: The affected GT will always use non-coherent - * access to page tables, so we must do uncached writes from the - * CPU. - */ - for_each_gt(gt, xe, id) - if (XE_GT_WA(gt, 16029380221)) - xe->info.has_cached_pt = false; + override_has_cached_pt(xe); for_each_tile(tile, xe, id) { err = xe_ggtt_init_early(tile->mem.ggtt); -- 2.55.0 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v2 1/3] drm/xe: Extract override_has_cached_pt() 2026-07-24 21:44 ` [PATCH v2 1/3] drm/xe: Extract override_has_cached_pt() Gustavo Sousa @ 2026-07-28 12:42 ` Matthew Auld 0 siblings, 0 replies; 13+ messages in thread From: Matthew Auld @ 2026-07-28 12:42 UTC (permalink / raw) To: Gustavo Sousa, intel-xe On 24/07/2026 22:44, Gustavo Sousa wrote: > Some platforms support cached page tables, but some workarounds might > require disabling the cached access on the CPU side. One such example > is Wa_16029380221, but there could be others as well. Extract the > code responsible for overriding xe->info.has_cached_pt into a new > function called override_has_cached_pt(), so that we have a common > place to add the necessary runtime checks specific for has_cached_pt. > > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> Reviewed-by: Matthew Auld <matthew.auld@intel.com> > --- > drivers/gpu/drm/xe/xe_device.c | 24 ++++++++++++++++-------- > 1 file changed, 16 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c > index 4eed9a251e65..5189419a0593 100644 > --- a/drivers/gpu/drm/xe/xe_device.c > +++ b/drivers/gpu/drm/xe/xe_device.c > @@ -831,6 +831,21 @@ int xe_device_probe_early(struct xe_device *xe) > } > ALLOW_ERROR_INJECTION(xe_device_probe_early, ERRNO); /* See xe_pci_probe() */ > > +static void override_has_cached_pt(struct xe_device *xe) > +{ > + struct xe_gt *gt; > + u8 id; > + > + /* > + * Wa_16029380221: The affected GT will always use non-coherent > + * access to page tables, so we must do uncached writes from the > + * CPU. > + */ > + for_each_gt(gt, xe, id) > + if (XE_GT_WA(gt, 16029380221)) > + xe->info.has_cached_pt = false; > +} > + > static int probe_has_flat_ccs(struct xe_device *xe) > { > struct xe_gt *gt; > @@ -950,14 +965,7 @@ int xe_device_probe(struct xe_device *xe) > return err; > } > > - /* > - * Wa_16029380221: The affected GT will always use non-coherent > - * access to page tables, so we must do uncached writes from the > - * CPU. > - */ > - for_each_gt(gt, xe, id) > - if (XE_GT_WA(gt, 16029380221)) > - xe->info.has_cached_pt = false; > + override_has_cached_pt(xe); > > for_each_tile(tile, xe, id) { > err = xe_ggtt_init_early(tile->mem.ggtt); > ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 2/3] Revert "drm/xe/nvlp: Implement Wa_14026539277" 2026-07-24 21:44 [PATCH v2 0/3] drm/xe: Update Wa_14026539277 Gustavo Sousa 2026-07-24 21:44 ` [PATCH v2 1/3] drm/xe: Extract override_has_cached_pt() Gustavo Sousa @ 2026-07-24 21:44 ` Gustavo Sousa 2026-08-19 13:23 ` Matthew Auld 2026-07-24 21:44 ` [PATCH v2 3/3] drm/xe: Add up-to-date implementation for Wa_14026539277 Gustavo Sousa ` (3 subsequent siblings) 5 siblings, 1 reply; 13+ messages in thread From: Gustavo Sousa @ 2026-07-24 21:44 UTC (permalink / raw) To: intel-xe; +Cc: Gustavo Sousa This reverts commit 0919b266456d81e71277c5963d4e806e85b65232. The definition of Wa_14026539277 has been updated in the workaround database and requires a different implementation. So let's revert the current implementation; a follow-up change will add the proper handling for this workaround. Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> --- drivers/gpu/drm/xe/regs/xe_gt_regs.h | 4 ---- drivers/gpu/drm/xe/xe_gt.c | 39 ------------------------------- drivers/gpu/drm/xe/xe_device_wa_oob.rules | 1 - 3 files changed, 44 deletions(-) diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h index 08251c7a1a4b..155cc19f097e 100644 --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h @@ -456,10 +456,6 @@ #define XEHPC_L3CLOS_MASK(i) XE_REG_MCR(0xb194 + (i) * 8) -#define L2COMPUTESIDECTRL XE_REG_MCR(0xb1c0) -#define CECTRL REG_GENMASK(2, 1) -#define CECTRL_CENODATA_ALWAYS REG_FIELD_PREP(CECTRL, 0x0) - #define XE2_GLOBAL_INVAL XE_REG(0xb404) #define XE2LPM_L3SQCREG2 XE_REG_MCR(0xb604) diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c index dfdacc0f6de9..2f14795e61f4 100644 --- a/drivers/gpu/drm/xe/xe_gt.c +++ b/drivers/gpu/drm/xe/xe_gt.c @@ -12,7 +12,6 @@ #include <drm/drm_managed.h> #include <uapi/drm/xe_drm.h> -#include <generated/xe_device_wa_oob.h> #include <generated/xe_wa_oob.h> #include "instructions/xe_alu_commands.h" @@ -455,35 +454,6 @@ int xe_gt_record_default_lrcs(struct xe_gt *gt) return err; } -static void wa_14026539277(struct xe_gt *gt) -{ - struct xe_device *xe = gt_to_xe(gt); - u32 val; - - /* - * FIXME: We currently can't use FUNC(xe_rtp_match_not_sriov_vf) in the - * rules for Wa_14026539277 due to xe_wa_process_device_oob() being - * called before xe_sriov_probe_early(); and we can't move the call to - * the former to happen after the latter because MMIO read functions - * already depend on a device OOB workaround. This needs to be fixed by - * allowing workaround checks to happen at different stages of driver - * initialization. - */ - if (IS_SRIOV_VF(xe)) - return; - - if (!XE_DEVICE_WA(xe, 14026539277)) - return; - - if (!xe_gt_is_main_type(gt)) - return; - - val = xe_gt_mcr_unicast_read_any(gt, L2COMPUTESIDECTRL); - val &= ~CECTRL; - val |= CECTRL_CENODATA_ALWAYS; - xe_gt_mcr_multicast_write(gt, L2COMPUTESIDECTRL, val); -} - int xe_gt_init_early(struct xe_gt *gt) { int err; @@ -609,15 +579,6 @@ static int gt_init_with_gt_forcewake(struct xe_gt *gt) */ gt->info.gmdid = xe_mmio_read32(>->mmio, GMD_ID); - /* - * Wa_14026539277 can't be implemented as a regular GT workaround (i.e. - * as an entry in gt_was[]) for two reasons: it is actually a device - * workaround that happens to involve programming a GT register; and it - * needs to be applied early to avoid getting the hardware in a bad - * state before we have a chance to do the necessary programming. - */ - wa_14026539277(gt); - return 0; } diff --git a/drivers/gpu/drm/xe/xe_device_wa_oob.rules b/drivers/gpu/drm/xe/xe_device_wa_oob.rules index d8dc41851425..356b4707dafe 100644 --- a/drivers/gpu/drm/xe/xe_device_wa_oob.rules +++ b/drivers/gpu/drm/xe/xe_device_wa_oob.rules @@ -3,7 +3,6 @@ PLATFORM(PANTHERLAKE) 22019338487_display PLATFORM(LUNARLAKE) 14022085890 SUBPLATFORM(BATTLEMAGE, G21) -14026539277 PLATFORM(NOVALAKE_P), PLATFORM_STEP(A0, B0) 14026633728 PLATFORM(CRESCENTISLAND) 14026746987 PLATFORM(CRESCENTISLAND) 14026779378 PLATFORM(CRESCENTISLAND) -- 2.55.0 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v2 2/3] Revert "drm/xe/nvlp: Implement Wa_14026539277" 2026-07-24 21:44 ` [PATCH v2 2/3] Revert "drm/xe/nvlp: Implement Wa_14026539277" Gustavo Sousa @ 2026-08-19 13:23 ` Matthew Auld 0 siblings, 0 replies; 13+ messages in thread From: Matthew Auld @ 2026-08-19 13:23 UTC (permalink / raw) To: Gustavo Sousa, intel-xe On 24/07/2026 22:44, Gustavo Sousa wrote: > This reverts commit 0919b266456d81e71277c5963d4e806e85b65232. > > The definition of Wa_14026539277 has been updated in the workaround > database and requires a different implementation. So let's revert the > current implementation; a follow-up change will add the proper > handling for this workaround. > > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> Reviewed-by: Matthew Auld <matthew.auld@intel.com> ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 3/3] drm/xe: Add up-to-date implementation for Wa_14026539277 2026-07-24 21:44 [PATCH v2 0/3] drm/xe: Update Wa_14026539277 Gustavo Sousa 2026-07-24 21:44 ` [PATCH v2 1/3] drm/xe: Extract override_has_cached_pt() Gustavo Sousa 2026-07-24 21:44 ` [PATCH v2 2/3] Revert "drm/xe/nvlp: Implement Wa_14026539277" Gustavo Sousa @ 2026-07-24 21:44 ` Gustavo Sousa 2026-07-28 12:40 ` Matthew Auld 2026-08-19 13:53 ` Matthew Auld 2026-07-24 22:22 ` ✗ CI.checkpatch: warning for drm/xe: Update Wa_14026539277 Patchwork ` (2 subsequent siblings) 5 siblings, 2 replies; 13+ messages in thread From: Gustavo Sousa @ 2026-07-24 21:44 UTC (permalink / raw) To: intel-xe; +Cc: Gustavo Sousa Wa_14026539277 is a temporary workaround that targets only A* steppings of graphics version 35.10 and requires that we avoid using 2-way coherency for device-cacheable memory accesses. For driver-internal usage, we convert those configurations to be device-uncached and 1-way-coherent; on the UAPI side, we reject VM_BIND/MADVISE calls that are 2-way-coherent and leave it up to userspace to select the alternative option that is most appropriate to their usage. v2: - Add missing bits to convert the PAT value to device-uncacheable in wa_14026539277_fixup_pat_value(). (Sashiko) - Also validate the PAT index in the DRM_XE_VM_MADVISE ioctl. (Sashiko) - Match against the graphics IP instead of the platform. Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> --- drivers/gpu/drm/xe/xe_pat.h | 10 +++++++ drivers/gpu/drm/xe/xe_device.c | 16 ++++++---- drivers/gpu/drm/xe/xe_pat.c | 61 ++++++++++++++++++++++++++++++++++---- drivers/gpu/drm/xe/xe_vm.c | 5 ++++ drivers/gpu/drm/xe/xe_vm_madvise.c | 3 ++ drivers/gpu/drm/xe/xe_wa_oob.rules | 1 + 6 files changed, 84 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_pat.h b/drivers/gpu/drm/xe/xe_pat.h index 7060f66e1d63..10374022f1d2 100644 --- a/drivers/gpu/drm/xe/xe_pat.h +++ b/drivers/gpu/drm/xe/xe_pat.h @@ -82,6 +82,16 @@ bool xe_pat_index_get_comp_en(struct xe_device *xe, u16 pat_index); */ u16 xe_pat_index_get_l3_policy(struct xe_device *xe, u16 pat_index); +/** + * xe_pat_wa_14026539277_reserved - Is this PAT index reserved from + * use due to Wa_14026539277? + * @xe: xe device + * @pat_index: The pat_index to query + * + * Return: a boolean indicating whether the PAT index is reserved or not. + */ +bool xe_pat_wa_14026539277_reserved(struct xe_device *xe, u16 pat_index); + #define xe_cache_pat_idx(xe, cache_mode) ({ \ const struct xe_device *__xedev = (xe); \ enum xe_cache_level __mode = (cache_mode); \ diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c index 5189419a0593..c4b8023cb8a2 100644 --- a/drivers/gpu/drm/xe/xe_device.c +++ b/drivers/gpu/drm/xe/xe_device.c @@ -836,14 +836,18 @@ static void override_has_cached_pt(struct xe_device *xe) struct xe_gt *gt; u8 id; - /* - * Wa_16029380221: The affected GT will always use non-coherent - * access to page tables, so we must do uncached writes from the - * CPU. - */ - for_each_gt(gt, xe, id) + for_each_gt(gt, xe, id) { + /* + * Wa_16029380221: The affected GT will always use + * non-coherent access to page tables, so we must do + * uncached writes from the CPU. + */ if (XE_GT_WA(gt, 16029380221)) xe->info.has_cached_pt = false; + + if (XE_GT_WA(gt, 14026539277)) + xe->info.has_cached_pt = false; + } } static int probe_has_flat_ccs(struct xe_device *xe) diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c index a5fe1beec652..a9cde12eba70 100644 --- a/drivers/gpu/drm/xe/xe_pat.c +++ b/drivers/gpu/drm/xe/xe_pat.c @@ -313,6 +313,37 @@ u16 xe_pat_index_get_l3_policy(struct xe_device *xe, u16 pat_index) return REG_FIELD_GET(XE2_L3_POLICY, xe->pat.table[pat_index].value); } +bool xe_pat_wa_14026539277_reserved(struct xe_device *xe, u16 pat_index) +{ + struct xe_gt *gt; + u8 id; + bool has_wa = false; + + for_each_gt(gt, xe, id) { + if (XE_GT_WA(gt, 14026539277)) { + has_wa = true; + break; + } + } + + return has_wa && xe_pat_index_get_l3_policy(xe, pat_index) != XE_L3_POLICY_UC && + xe_pat_index_get_coh_mode(xe, pat_index) == XE_COH_2WAY; +} + +static u32 wa_14026539277_fixup_pat_value(struct xe_gt *gt, u32 value) +{ + if (XE_GT_WA(gt, 14026539277)) { + if (REG_FIELD_GET(XE2_L3_POLICY, value) != XE_L3_POLICY_UC && + REG_FIELD_GET(XE2_COH_MODE, value) == XE_COH_2WAY) { + value &= ~(XE2_L3_POLICY | XE2_COH_MODE); + value |= REG_FIELD_PREP(XE2_L3_POLICY, XE_L3_POLICY_UC) | + REG_FIELD_PREP(XE2_COH_MODE, XE_COH_1WAY); + } + } + + return value; +} + static const struct xe_pat_table_entry *gt_pta_entry(struct xe_gt *gt) { struct xe_device *xe = gt_to_xe(gt); @@ -373,18 +404,22 @@ static void program_pat_mcr(struct xe_gt *gt, const struct xe_pat_table_entry ta for (int i = 0; i < n_entries; i++) { struct xe_reg_mcr reg_mcr = XE_REG_MCR(_PAT_INDEX(i)); + u32 pat = wa_14026539277_fixup_pat_value(gt, table[i].value); - xe_gt_mcr_multicast_write(gt, reg_mcr, table[i].value); + xe_gt_mcr_multicast_write(gt, reg_mcr, pat); } if (xe->pat.pat_ats) - xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_ATS), xe->pat.pat_ats->value); + xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_ATS), + wa_14026539277_fixup_pat_value(gt, xe->pat.pat_ats->value)); if (pta_entry) - xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_PTA), pta_entry->value); + xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_PTA), + wa_14026539277_fixup_pat_value(gt, pta_entry->value)); if (tr_pta_entry) - xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_TR_PTA), tr_pta_entry->value); + xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_TR_PTA), + wa_14026539277_fixup_pat_value(gt, tr_pta_entry->value)); } static int xelp_dump(struct xe_gt *gt, struct drm_printer *p) @@ -534,13 +569,16 @@ static int xe2_dump(struct xe_gt *gt, struct drm_printer *p) drm_printf(p, "PAT table: (* = reserved entry)\n"); for (i = 0; i < xe->pat.n_entries; i++) { + bool rsvd = !xe->pat.table[i].valid || + xe_pat_wa_14026539277_reserved(xe, i); + if (xe_gt_is_media_type(gt)) pat = xe_mmio_read32(>->mmio, XE_REG(_PAT_INDEX(i))); else pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i))); xe_pat_index_label(label, sizeof(label), i); - xe->pat.ops->entry_dump(p, label, pat, !xe->pat.table[i].valid); + xe->pat.ops->entry_dump(p, label, pat, rsvd); } /* @@ -747,9 +785,14 @@ int xe_pat_dump_sw_config(struct xe_gt *gt, struct drm_printer *p) for (u32 i = 0; i < xe->pat.n_entries; i++) { u32 pat = xe->pat.table[i].value; + pat = wa_14026539277_fixup_pat_value(gt, pat); + if (GRAPHICS_VER(xe) >= 20) { + bool rsvd = !xe->pat.table[i].valid || + xe_pat_wa_14026539277_reserved(xe, i); + xe_pat_index_label(label, sizeof(label), i); - xe->pat.ops->entry_dump(p, label, pat, !xe->pat.table[i].valid); + xe->pat.ops->entry_dump(p, label, pat, rsvd); } else if (xe->info.platform == XE_METEORLAKE) { xelpg_pat_entry_dump(p, i, pat); } else if (xe->info.platform == XE_PVC) { @@ -764,6 +807,8 @@ int xe_pat_dump_sw_config(struct xe_gt *gt, struct drm_printer *p) if (pta_entry) { u32 pat = pta_entry->value; + pat = wa_14026539277_fixup_pat_value(gt, pat); + drm_printf(p, "Page Table Access:\n"); xe->pat.ops->entry_dump(p, "PTA_MODE", pat, false); } @@ -771,6 +816,8 @@ int xe_pat_dump_sw_config(struct xe_gt *gt, struct drm_printer *p) if (tr_pta_entry) { u32 pat = tr_pta_entry->value; + pat = wa_14026539277_fixup_pat_value(gt, pat); + drm_printf(p, "TRTT Page Table Access:\n"); xe->pat.ops->entry_dump(p, "TR_PTA_MODE", pat, false); } @@ -778,6 +825,8 @@ int xe_pat_dump_sw_config(struct xe_gt *gt, struct drm_printer *p) if (xe->pat.pat_ats) { u32 pat = xe->pat.pat_ats->value; + pat = wa_14026539277_fixup_pat_value(gt, pat); + drm_printf(p, "PCIe ATS/PASID:\n"); xe->pat.ops->entry_dump(p, "PAT_ATS ", pat, false); } diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c index 9e0176861cb6..64c03c669630 100644 --- a/drivers/gpu/drm/xe/xe_vm.c +++ b/drivers/gpu/drm/xe/xe_vm.c @@ -3697,6 +3697,11 @@ static int vm_bind_ioctl_check_args(struct xe_device *xe, struct xe_vm *vm, goto free_bind_ops; } + if (XE_IOCTL_DBG(xe, xe_pat_wa_14026539277_reserved(xe, pat_index))) { + err = -EINVAL; + goto free_bind_ops; + } + if (XE_IOCTL_DBG(xe, op > DRM_XE_VM_BIND_OP_PREFETCH) || XE_IOCTL_DBG(xe, flags & ~SUPPORTED_FLAGS) || XE_IOCTL_DBG(xe, obj && (is_null || is_cpu_addr_mirror)) || diff --git a/drivers/gpu/drm/xe/xe_vm_madvise.c b/drivers/gpu/drm/xe/xe_vm_madvise.c index 0474768a38aa..265273294756 100644 --- a/drivers/gpu/drm/xe/xe_vm_madvise.c +++ b/drivers/gpu/drm/xe/xe_vm_madvise.c @@ -500,6 +500,9 @@ static bool check_pat_args_are_sane(struct xe_device *xe, u16 coh_mode = xe_pat_index_get_coh_mode(xe, pat_index); int i; + if (XE_IOCTL_DBG(xe, xe_pat_wa_14026539277_reserved(xe, pat_index))) + return false; + /* * Using coh_none with CPU cached buffers is not allowed on iGPU. * On iGPU the GPU shares the LLC with the CPU, so with coh_none diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules index f02ac9bf7424..d53e7f75814b 100644 --- a/drivers/gpu/drm/xe/xe_wa_oob.rules +++ b/drivers/gpu/drm/xe/xe_wa_oob.rules @@ -71,4 +71,5 @@ GRAPHICS_VERSION(3511) 16029897822 MEDIA_VERSION(3500) GRAPHICS_VERSION(3510) +14026539277 GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0) 14027054324 GRAPHICS_VERSION(3511) -- 2.55.0 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v2 3/3] drm/xe: Add up-to-date implementation for Wa_14026539277 2026-07-24 21:44 ` [PATCH v2 3/3] drm/xe: Add up-to-date implementation for Wa_14026539277 Gustavo Sousa @ 2026-07-28 12:40 ` Matthew Auld 2026-07-28 13:25 ` Souza, Jose 2026-08-19 13:53 ` Matthew Auld 1 sibling, 1 reply; 13+ messages in thread From: Matthew Auld @ 2026-07-28 12:40 UTC (permalink / raw) To: Gustavo Sousa, intel-xe, Souza, Jose, Mrozek, Michal, Zhang, Carl On 24/07/2026 22:44, Gustavo Sousa wrote: > Wa_14026539277 is a temporary workaround that targets only A* > steppings of graphics version 35.10 and requires that we avoid using > 2-way coherency for device-cacheable memory accesses. For > driver-internal usage, we convert those configurations to be > device-uncached and 1-way-coherent; on the UAPI side, we reject > VM_BIND/MADVISE calls that are 2-way-coherent and leave it up to > userspace to select the alternative option that is most appropriate to > their usage. > > v2: > - Add missing bits to convert the PAT value to device-uncacheable in > wa_14026539277_fixup_pat_value(). (Sashiko) > - Also validate the PAT index in the DRM_XE_VM_MADVISE > ioctl. (Sashiko) > - Match against the graphics IP instead of the platform. > > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> > --- > drivers/gpu/drm/xe/xe_pat.h | 10 +++++++ > drivers/gpu/drm/xe/xe_device.c | 16 ++++++---- > drivers/gpu/drm/xe/xe_pat.c | 61 ++++++++++++++++++++++++++++++++++---- > drivers/gpu/drm/xe/xe_vm.c | 5 ++++ > drivers/gpu/drm/xe/xe_vm_madvise.c | 3 ++ > drivers/gpu/drm/xe/xe_wa_oob.rules | 1 + > 6 files changed, 84 insertions(+), 12 deletions(-) > > diff --git a/drivers/gpu/drm/xe/xe_pat.h b/drivers/gpu/drm/xe/xe_pat.h > index 7060f66e1d63..10374022f1d2 100644 > --- a/drivers/gpu/drm/xe/xe_pat.h > +++ b/drivers/gpu/drm/xe/xe_pat.h > @@ -82,6 +82,16 @@ bool xe_pat_index_get_comp_en(struct xe_device *xe, u16 pat_index); > */ > u16 xe_pat_index_get_l3_policy(struct xe_device *xe, u16 pat_index); > > +/** > + * xe_pat_wa_14026539277_reserved - Is this PAT index reserved from > + * use due to Wa_14026539277? > + * @xe: xe device > + * @pat_index: The pat_index to query > + * > + * Return: a boolean indicating whether the PAT index is reserved or not. > + */ > +bool xe_pat_wa_14026539277_reserved(struct xe_device *xe, u16 pat_index); > + > #define xe_cache_pat_idx(xe, cache_mode) ({ \ > const struct xe_device *__xedev = (xe); \ > enum xe_cache_level __mode = (cache_mode); \ > diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c > index 5189419a0593..c4b8023cb8a2 100644 > --- a/drivers/gpu/drm/xe/xe_device.c > +++ b/drivers/gpu/drm/xe/xe_device.c > @@ -836,14 +836,18 @@ static void override_has_cached_pt(struct xe_device *xe) > struct xe_gt *gt; > u8 id; > > - /* > - * Wa_16029380221: The affected GT will always use non-coherent > - * access to page tables, so we must do uncached writes from the > - * CPU. > - */ > - for_each_gt(gt, xe, id) > + for_each_gt(gt, xe, id) { > + /* > + * Wa_16029380221: The affected GT will always use > + * non-coherent access to page tables, so we must do > + * uncached writes from the CPU. > + */ > if (XE_GT_WA(gt, 16029380221)) > xe->info.has_cached_pt = false; > + > + if (XE_GT_WA(gt, 14026539277)) > + xe->info.has_cached_pt = false; > + } > } > > static int probe_has_flat_ccs(struct xe_device *xe) > diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c > index a5fe1beec652..a9cde12eba70 100644 > --- a/drivers/gpu/drm/xe/xe_pat.c > +++ b/drivers/gpu/drm/xe/xe_pat.c > @@ -313,6 +313,37 @@ u16 xe_pat_index_get_l3_policy(struct xe_device *xe, u16 pat_index) > return REG_FIELD_GET(XE2_L3_POLICY, xe->pat.table[pat_index].value); > } > > +bool xe_pat_wa_14026539277_reserved(struct xe_device *xe, u16 pat_index) > +{ > + struct xe_gt *gt; > + u8 id; > + bool has_wa = false; > + > + for_each_gt(gt, xe, id) { > + if (XE_GT_WA(gt, 14026539277)) { > + has_wa = true; > + break; > + } > + } > + > + return has_wa && xe_pat_index_get_l3_policy(xe, pat_index) != XE_L3_POLICY_UC && > + xe_pat_index_get_coh_mode(xe, pat_index) == XE_COH_2WAY; > +} > + > +static u32 wa_14026539277_fixup_pat_value(struct xe_gt *gt, u32 value) > +{ > + if (XE_GT_WA(gt, 14026539277)) { > + if (REG_FIELD_GET(XE2_L3_POLICY, value) != XE_L3_POLICY_UC && > + REG_FIELD_GET(XE2_COH_MODE, value) == XE_COH_2WAY) { > + value &= ~(XE2_L3_POLICY | XE2_COH_MODE); > + value |= REG_FIELD_PREP(XE2_L3_POLICY, XE_L3_POLICY_UC) | > + REG_FIELD_PREP(XE2_COH_MODE, XE_COH_1WAY); > + } > + } > + > + return value; > +} > + > static const struct xe_pat_table_entry *gt_pta_entry(struct xe_gt *gt) > { > struct xe_device *xe = gt_to_xe(gt); > @@ -373,18 +404,22 @@ static void program_pat_mcr(struct xe_gt *gt, const struct xe_pat_table_entry ta > > for (int i = 0; i < n_entries; i++) { > struct xe_reg_mcr reg_mcr = XE_REG_MCR(_PAT_INDEX(i)); > + u32 pat = wa_14026539277_fixup_pat_value(gt, table[i].value); > > - xe_gt_mcr_multicast_write(gt, reg_mcr, table[i].value); > + xe_gt_mcr_multicast_write(gt, reg_mcr, pat); > } > > if (xe->pat.pat_ats) > - xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_ATS), xe->pat.pat_ats->value); > + xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_ATS), > + wa_14026539277_fixup_pat_value(gt, xe->pat.pat_ats->value)); > > if (pta_entry) > - xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_PTA), pta_entry->value); > + xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_PTA), > + wa_14026539277_fixup_pat_value(gt, pta_entry->value)); > > if (tr_pta_entry) > - xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_TR_PTA), tr_pta_entry->value); > + xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_TR_PTA), > + wa_14026539277_fixup_pat_value(gt, tr_pta_entry->value)); > } > > static int xelp_dump(struct xe_gt *gt, struct drm_printer *p) > @@ -534,13 +569,16 @@ static int xe2_dump(struct xe_gt *gt, struct drm_printer *p) > drm_printf(p, "PAT table: (* = reserved entry)\n"); > > for (i = 0; i < xe->pat.n_entries; i++) { > + bool rsvd = !xe->pat.table[i].valid || > + xe_pat_wa_14026539277_reserved(xe, i); > + > if (xe_gt_is_media_type(gt)) > pat = xe_mmio_read32(>->mmio, XE_REG(_PAT_INDEX(i))); > else > pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i))); > > xe_pat_index_label(label, sizeof(label), i); > - xe->pat.ops->entry_dump(p, label, pat, !xe->pat.table[i].valid); > + xe->pat.ops->entry_dump(p, label, pat, rsvd); > } > > /* > @@ -747,9 +785,14 @@ int xe_pat_dump_sw_config(struct xe_gt *gt, struct drm_printer *p) > for (u32 i = 0; i < xe->pat.n_entries; i++) { > u32 pat = xe->pat.table[i].value; > > + pat = wa_14026539277_fixup_pat_value(gt, pat); > + > if (GRAPHICS_VER(xe) >= 20) { > + bool rsvd = !xe->pat.table[i].valid || > + xe_pat_wa_14026539277_reserved(xe, i); > + > xe_pat_index_label(label, sizeof(label), i); > - xe->pat.ops->entry_dump(p, label, pat, !xe->pat.table[i].valid); > + xe->pat.ops->entry_dump(p, label, pat, rsvd); > } else if (xe->info.platform == XE_METEORLAKE) { > xelpg_pat_entry_dump(p, i, pat); > } else if (xe->info.platform == XE_PVC) { > @@ -764,6 +807,8 @@ int xe_pat_dump_sw_config(struct xe_gt *gt, struct drm_printer *p) > if (pta_entry) { > u32 pat = pta_entry->value; > > + pat = wa_14026539277_fixup_pat_value(gt, pat); > + > drm_printf(p, "Page Table Access:\n"); > xe->pat.ops->entry_dump(p, "PTA_MODE", pat, false); > } > @@ -771,6 +816,8 @@ int xe_pat_dump_sw_config(struct xe_gt *gt, struct drm_printer *p) > if (tr_pta_entry) { > u32 pat = tr_pta_entry->value; > > + pat = wa_14026539277_fixup_pat_value(gt, pat); > + > drm_printf(p, "TRTT Page Table Access:\n"); > xe->pat.ops->entry_dump(p, "TR_PTA_MODE", pat, false); > } > @@ -778,6 +825,8 @@ int xe_pat_dump_sw_config(struct xe_gt *gt, struct drm_printer *p) > if (xe->pat.pat_ats) { > u32 pat = xe->pat.pat_ats->value; > > + pat = wa_14026539277_fixup_pat_value(gt, pat); > + > drm_printf(p, "PCIe ATS/PASID:\n"); > xe->pat.ops->entry_dump(p, "PAT_ATS ", pat, false); > } > diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c > index 9e0176861cb6..64c03c669630 100644 > --- a/drivers/gpu/drm/xe/xe_vm.c > +++ b/drivers/gpu/drm/xe/xe_vm.c > @@ -3697,6 +3697,11 @@ static int vm_bind_ioctl_check_args(struct xe_device *xe, struct xe_vm *vm, > goto free_bind_ops; > } > > + if (XE_IOCTL_DBG(xe, xe_pat_wa_14026539277_reserved(xe, pat_index))) { > + err = -EINVAL; > + goto free_bind_ops; > + } > + > if (XE_IOCTL_DBG(xe, op > DRM_XE_VM_BIND_OP_PREFETCH) || > XE_IOCTL_DBG(xe, flags & ~SUPPORTED_FLAGS) || > XE_IOCTL_DBG(xe, obj && (is_null || is_cpu_addr_mirror)) || > diff --git a/drivers/gpu/drm/xe/xe_vm_madvise.c b/drivers/gpu/drm/xe/xe_vm_madvise.c > index 0474768a38aa..265273294756 100644 > --- a/drivers/gpu/drm/xe/xe_vm_madvise.c > +++ b/drivers/gpu/drm/xe/xe_vm_madvise.c > @@ -500,6 +500,9 @@ static bool check_pat_args_are_sane(struct xe_device *xe, > u16 coh_mode = xe_pat_index_get_coh_mode(xe, pat_index); > int i; > > + if (XE_IOCTL_DBG(xe, xe_pat_wa_14026539277_reserved(xe, pat_index))) > + return false; > + Jose, Michal, Carl, would this approach work for you guys? Essentially just don't use any 2WAY coherency PAT index on this platforms with the WA. If so, could you also give an ack from UMD pov? This impacts vm_bind + madvise uAPI. > /* > * Using coh_none with CPU cached buffers is not allowed on iGPU. > * On iGPU the GPU shares the LLC with the CPU, so with coh_none > diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules > index f02ac9bf7424..d53e7f75814b 100644 > --- a/drivers/gpu/drm/xe/xe_wa_oob.rules > +++ b/drivers/gpu/drm/xe/xe_wa_oob.rules > @@ -71,4 +71,5 @@ > GRAPHICS_VERSION(3511) > 16029897822 MEDIA_VERSION(3500) > GRAPHICS_VERSION(3510) > +14026539277 GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0) > 14027054324 GRAPHICS_VERSION(3511) > ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 3/3] drm/xe: Add up-to-date implementation for Wa_14026539277 2026-07-28 12:40 ` Matthew Auld @ 2026-07-28 13:25 ` Souza, Jose 0 siblings, 0 replies; 13+ messages in thread From: Souza, Jose @ 2026-07-28 13:25 UTC (permalink / raw) To: intel-xe@lists.freedesktop.org, Sousa, Gustavo, Zhang, Carl, Auld, Matthew, Mrozek, Michal On Tue, 2026-07-28 at 13:40 +0100, Matthew Auld wrote: > On 24/07/2026 22:44, Gustavo Sousa wrote: > > Wa_14026539277 is a temporary workaround that targets only A* > > steppings of graphics version 35.10 and requires that we avoid > > using > > 2-way coherency for device-cacheable memory accesses. For > > driver-internal usage, we convert those configurations to be > > device-uncached and 1-way-coherent; on the UAPI side, we reject > > VM_BIND/MADVISE calls that are 2-way-coherent and leave it up to > > userspace to select the alternative option that is most appropriate > > to > > their usage. > > > > v2: > > - Add missing bits to convert the PAT value to device- > > uncacheable in > > wa_14026539277_fixup_pat_value(). (Sashiko) > > - Also validate the PAT index in the DRM_XE_VM_MADVISE > > ioctl. (Sashiko) > > - Match against the graphics IP instead of the platform. > > > > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> > > --- > > drivers/gpu/drm/xe/xe_pat.h | 10 +++++++ > > drivers/gpu/drm/xe/xe_device.c | 16 ++++++---- > > drivers/gpu/drm/xe/xe_pat.c | 61 > > ++++++++++++++++++++++++++++++++++---- > > drivers/gpu/drm/xe/xe_vm.c | 5 ++++ > > drivers/gpu/drm/xe/xe_vm_madvise.c | 3 ++ > > drivers/gpu/drm/xe/xe_wa_oob.rules | 1 + > > 6 files changed, 84 insertions(+), 12 deletions(-) > > > > diff --git a/drivers/gpu/drm/xe/xe_pat.h > > b/drivers/gpu/drm/xe/xe_pat.h > > index 7060f66e1d63..10374022f1d2 100644 > > --- a/drivers/gpu/drm/xe/xe_pat.h > > +++ b/drivers/gpu/drm/xe/xe_pat.h > > @@ -82,6 +82,16 @@ bool xe_pat_index_get_comp_en(struct xe_device > > *xe, u16 pat_index); > > */ > > u16 xe_pat_index_get_l3_policy(struct xe_device *xe, u16 > > pat_index); > > > > +/** > > + * xe_pat_wa_14026539277_reserved - Is this PAT index reserved > > from > > + * use due to Wa_14026539277? > > + * @xe: xe device > > + * @pat_index: The pat_index to query > > + * > > + * Return: a boolean indicating whether the PAT index is reserved > > or not. > > + */ > > +bool xe_pat_wa_14026539277_reserved(struct xe_device *xe, u16 > > pat_index); > > + > > #define xe_cache_pat_idx(xe, cache_mode) > > ({ \ > > const struct xe_device *__xedev = > > (xe); \ > > enum xe_cache_level __mode = > > (cache_mode); \ > > diff --git a/drivers/gpu/drm/xe/xe_device.c > > b/drivers/gpu/drm/xe/xe_device.c > > index 5189419a0593..c4b8023cb8a2 100644 > > --- a/drivers/gpu/drm/xe/xe_device.c > > +++ b/drivers/gpu/drm/xe/xe_device.c > > @@ -836,14 +836,18 @@ static void override_has_cached_pt(struct > > xe_device *xe) > > struct xe_gt *gt; > > u8 id; > > > > - /* > > - * Wa_16029380221: The affected GT will always use non- > > coherent > > - * access to page tables, so we must do uncached writes > > from the > > - * CPU. > > - */ > > - for_each_gt(gt, xe, id) > > + for_each_gt(gt, xe, id) { > > + /* > > + * Wa_16029380221: The affected GT will always use > > + * non-coherent access to page tables, so we must > > do > > + * uncached writes from the CPU. > > + */ > > if (XE_GT_WA(gt, 16029380221)) > > xe->info.has_cached_pt = false; > > + > > + if (XE_GT_WA(gt, 14026539277)) > > + xe->info.has_cached_pt = false; > > + } > > } > > > > static int probe_has_flat_ccs(struct xe_device *xe) > > diff --git a/drivers/gpu/drm/xe/xe_pat.c > > b/drivers/gpu/drm/xe/xe_pat.c > > index a5fe1beec652..a9cde12eba70 100644 > > --- a/drivers/gpu/drm/xe/xe_pat.c > > +++ b/drivers/gpu/drm/xe/xe_pat.c > > @@ -313,6 +313,37 @@ u16 xe_pat_index_get_l3_policy(struct > > xe_device *xe, u16 pat_index) > > return REG_FIELD_GET(XE2_L3_POLICY, xe- > > >pat.table[pat_index].value); > > } > > > > +bool xe_pat_wa_14026539277_reserved(struct xe_device *xe, u16 > > pat_index) > > +{ > > + struct xe_gt *gt; > > + u8 id; > > + bool has_wa = false; > > + > > + for_each_gt(gt, xe, id) { > > + if (XE_GT_WA(gt, 14026539277)) { > > + has_wa = true; > > + break; > > + } > > + } > > + > > + return has_wa && xe_pat_index_get_l3_policy(xe, pat_index) > > != XE_L3_POLICY_UC && > > + xe_pat_index_get_coh_mode(xe, pat_index) == > > XE_COH_2WAY; > > +} > > + > > +static u32 wa_14026539277_fixup_pat_value(struct xe_gt *gt, u32 > > value) > > +{ > > + if (XE_GT_WA(gt, 14026539277)) { > > + if (REG_FIELD_GET(XE2_L3_POLICY, value) != > > XE_L3_POLICY_UC && > > + REG_FIELD_GET(XE2_COH_MODE, value) == > > XE_COH_2WAY) { > > + value &= ~(XE2_L3_POLICY | XE2_COH_MODE); > > + value |= REG_FIELD_PREP(XE2_L3_POLICY, > > XE_L3_POLICY_UC) | > > + REG_FIELD_PREP(XE2_COH_MODE, > > XE_COH_1WAY); > > + } > > + } > > + > > + return value; > > +} > > + > > static const struct xe_pat_table_entry *gt_pta_entry(struct xe_gt > > *gt) > > { > > struct xe_device *xe = gt_to_xe(gt); > > @@ -373,18 +404,22 @@ static void program_pat_mcr(struct xe_gt *gt, > > const struct xe_pat_table_entry ta > > > > for (int i = 0; i < n_entries; i++) { > > struct xe_reg_mcr reg_mcr = > > XE_REG_MCR(_PAT_INDEX(i)); > > + u32 pat = wa_14026539277_fixup_pat_value(gt, > > table[i].value); > > > > - xe_gt_mcr_multicast_write(gt, reg_mcr, > > table[i].value); > > + xe_gt_mcr_multicast_write(gt, reg_mcr, pat); > > } > > > > if (xe->pat.pat_ats) > > - xe_gt_mcr_multicast_write(gt, > > XE_REG_MCR(_PAT_ATS), xe->pat.pat_ats->value); > > + xe_gt_mcr_multicast_write(gt, > > XE_REG_MCR(_PAT_ATS), > > + > > wa_14026539277_fixup_pat_value(gt, xe->pat.pat_ats->value)); > > > > if (pta_entry) > > - xe_gt_mcr_multicast_write(gt, > > XE_REG_MCR(_PAT_PTA), pta_entry->value); > > + xe_gt_mcr_multicast_write(gt, > > XE_REG_MCR(_PAT_PTA), > > + > > wa_14026539277_fixup_pat_value(gt, pta_entry->value)); > > > > if (tr_pta_entry) > > - xe_gt_mcr_multicast_write(gt, > > XE_REG_MCR(_PAT_TR_PTA), tr_pta_entry->value); > > + xe_gt_mcr_multicast_write(gt, > > XE_REG_MCR(_PAT_TR_PTA), > > + > > wa_14026539277_fixup_pat_value(gt, tr_pta_entry->value)); > > } > > > > static int xelp_dump(struct xe_gt *gt, struct drm_printer *p) > > @@ -534,13 +569,16 @@ static int xe2_dump(struct xe_gt *gt, struct > > drm_printer *p) > > drm_printf(p, "PAT table: (* = reserved entry)\n"); > > > > for (i = 0; i < xe->pat.n_entries; i++) { > > + bool rsvd = !xe->pat.table[i].valid || > > + xe_pat_wa_14026539277_reserved(xe, i); > > + > > if (xe_gt_is_media_type(gt)) > > pat = xe_mmio_read32(>->mmio, > > XE_REG(_PAT_INDEX(i))); > > else > > pat = xe_gt_mcr_unicast_read_any(gt, > > XE_REG_MCR(_PAT_INDEX(i))); > > > > xe_pat_index_label(label, sizeof(label), i); > > - xe->pat.ops->entry_dump(p, label, pat, !xe- > > >pat.table[i].valid); > > + xe->pat.ops->entry_dump(p, label, pat, rsvd); > > } > > > > /* > > @@ -747,9 +785,14 @@ int xe_pat_dump_sw_config(struct xe_gt *gt, > > struct drm_printer *p) > > for (u32 i = 0; i < xe->pat.n_entries; i++) { > > u32 pat = xe->pat.table[i].value; > > > > + pat = wa_14026539277_fixup_pat_value(gt, pat); > > + > > if (GRAPHICS_VER(xe) >= 20) { > > + bool rsvd = !xe->pat.table[i].valid || > > + > > xe_pat_wa_14026539277_reserved(xe, i); > > + > > xe_pat_index_label(label, sizeof(label), > > i); > > - xe->pat.ops->entry_dump(p, label, pat, > > !xe->pat.table[i].valid); > > + xe->pat.ops->entry_dump(p, label, pat, > > rsvd); > > } else if (xe->info.platform == XE_METEORLAKE) { > > xelpg_pat_entry_dump(p, i, pat); > > } else if (xe->info.platform == XE_PVC) { > > @@ -764,6 +807,8 @@ int xe_pat_dump_sw_config(struct xe_gt *gt, > > struct drm_printer *p) > > if (pta_entry) { > > u32 pat = pta_entry->value; > > > > + pat = wa_14026539277_fixup_pat_value(gt, pat); > > + > > drm_printf(p, "Page Table Access:\n"); > > xe->pat.ops->entry_dump(p, "PTA_MODE", pat, > > false); > > } > > @@ -771,6 +816,8 @@ int xe_pat_dump_sw_config(struct xe_gt *gt, > > struct drm_printer *p) > > if (tr_pta_entry) { > > u32 pat = tr_pta_entry->value; > > > > + pat = wa_14026539277_fixup_pat_value(gt, pat); > > + > > drm_printf(p, "TRTT Page Table Access:\n"); > > xe->pat.ops->entry_dump(p, "TR_PTA_MODE", pat, > > false); > > } > > @@ -778,6 +825,8 @@ int xe_pat_dump_sw_config(struct xe_gt *gt, > > struct drm_printer *p) > > if (xe->pat.pat_ats) { > > u32 pat = xe->pat.pat_ats->value; > > > > + pat = wa_14026539277_fixup_pat_value(gt, pat); > > + > > drm_printf(p, "PCIe ATS/PASID:\n"); > > xe->pat.ops->entry_dump(p, "PAT_ATS ", pat, > > false); > > } > > diff --git a/drivers/gpu/drm/xe/xe_vm.c > > b/drivers/gpu/drm/xe/xe_vm.c > > index 9e0176861cb6..64c03c669630 100644 > > --- a/drivers/gpu/drm/xe/xe_vm.c > > +++ b/drivers/gpu/drm/xe/xe_vm.c > > @@ -3697,6 +3697,11 @@ static int vm_bind_ioctl_check_args(struct > > xe_device *xe, struct xe_vm *vm, > > goto free_bind_ops; > > } > > > > + if (XE_IOCTL_DBG(xe, > > xe_pat_wa_14026539277_reserved(xe, pat_index))) { > > + err = -EINVAL; > > + goto free_bind_ops; > > + } > > + > > if (XE_IOCTL_DBG(xe, op > > > DRM_XE_VM_BIND_OP_PREFETCH) || > > XE_IOCTL_DBG(xe, flags & ~SUPPORTED_FLAGS) || > > XE_IOCTL_DBG(xe, obj && (is_null || > > is_cpu_addr_mirror)) || > > diff --git a/drivers/gpu/drm/xe/xe_vm_madvise.c > > b/drivers/gpu/drm/xe/xe_vm_madvise.c > > index 0474768a38aa..265273294756 100644 > > --- a/drivers/gpu/drm/xe/xe_vm_madvise.c > > +++ b/drivers/gpu/drm/xe/xe_vm_madvise.c > > @@ -500,6 +500,9 @@ static bool check_pat_args_are_sane(struct > > xe_device *xe, > > u16 coh_mode = xe_pat_index_get_coh_mode(xe, pat_index); > > int i; > > > > + if (XE_IOCTL_DBG(xe, xe_pat_wa_14026539277_reserved(xe, > > pat_index))) > > + return false; > > + > > Jose, Michal, Carl, would this approach work for you guys? > Essentially > just don't use any 2WAY coherency PAT index on this platforms with > the > WA. If so, could you also give an ack from UMD pov? This impacts > vm_bind > + madvise uAPI. Mesa only uses 1-way coherancy so this is Acked-by: José Roberto de Souza <jose.souza@intel.com> > > > /* > > * Using coh_none with CPU cached buffers is not allowed > > on iGPU. > > * On iGPU the GPU shares the LLC with the CPU, so with > > coh_none > > diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules > > b/drivers/gpu/drm/xe/xe_wa_oob.rules > > index f02ac9bf7424..d53e7f75814b 100644 > > --- a/drivers/gpu/drm/xe/xe_wa_oob.rules > > +++ b/drivers/gpu/drm/xe/xe_wa_oob.rules > > @@ -71,4 +71,5 @@ > > GRAPHICS_VERSION(3511) > > 16029897822 MEDIA_VERSION(3500) > > GRAPHICS_VERSION(3510) > > +14026539277 GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0) > > 14027054324 GRAPHICS_VERSION(3511) > > ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 3/3] drm/xe: Add up-to-date implementation for Wa_14026539277 2026-07-24 21:44 ` [PATCH v2 3/3] drm/xe: Add up-to-date implementation for Wa_14026539277 Gustavo Sousa 2026-07-28 12:40 ` Matthew Auld @ 2026-08-19 13:53 ` Matthew Auld 2026-08-19 20:37 ` Gustavo Sousa 1 sibling, 1 reply; 13+ messages in thread From: Matthew Auld @ 2026-08-19 13:53 UTC (permalink / raw) To: Gustavo Sousa, intel-xe On 24/07/2026 22:44, Gustavo Sousa wrote: > Wa_14026539277 is a temporary workaround that targets only A* > steppings of graphics version 35.10 and requires that we avoid using > 2-way coherency for device-cacheable memory accesses. For > driver-internal usage, we convert those configurations to be > device-uncached and 1-way-coherent; on the UAPI side, we reject > VM_BIND/MADVISE calls that are 2-way-coherent and leave it up to > userspace to select the alternative option that is most appropriate to > their usage. > > v2: > - Add missing bits to convert the PAT value to device-uncacheable in > wa_14026539277_fixup_pat_value(). (Sashiko) > - Also validate the PAT index in the DRM_XE_VM_MADVISE > ioctl. (Sashiko) > - Match against the graphics IP instead of the platform. > > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> > --- > drivers/gpu/drm/xe/xe_pat.h | 10 +++++++ > drivers/gpu/drm/xe/xe_device.c | 16 ++++++---- > drivers/gpu/drm/xe/xe_pat.c | 61 ++++++++++++++++++++++++++++++++++---- > drivers/gpu/drm/xe/xe_vm.c | 5 ++++ > drivers/gpu/drm/xe/xe_vm_madvise.c | 3 ++ > drivers/gpu/drm/xe/xe_wa_oob.rules | 1 + > 6 files changed, 84 insertions(+), 12 deletions(-) > > diff --git a/drivers/gpu/drm/xe/xe_pat.h b/drivers/gpu/drm/xe/xe_pat.h > index 7060f66e1d63..10374022f1d2 100644 > --- a/drivers/gpu/drm/xe/xe_pat.h > +++ b/drivers/gpu/drm/xe/xe_pat.h > @@ -82,6 +82,16 @@ bool xe_pat_index_get_comp_en(struct xe_device *xe, u16 pat_index); > */ > u16 xe_pat_index_get_l3_policy(struct xe_device *xe, u16 pat_index); > > +/** > + * xe_pat_wa_14026539277_reserved - Is this PAT index reserved from > + * use due to Wa_14026539277? > + * @xe: xe device > + * @pat_index: The pat_index to query > + * > + * Return: a boolean indicating whether the PAT index is reserved or not. > + */ > +bool xe_pat_wa_14026539277_reserved(struct xe_device *xe, u16 pat_index); > + > #define xe_cache_pat_idx(xe, cache_mode) ({ \ > const struct xe_device *__xedev = (xe); \ > enum xe_cache_level __mode = (cache_mode); \ > diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c > index 5189419a0593..c4b8023cb8a2 100644 > --- a/drivers/gpu/drm/xe/xe_device.c > +++ b/drivers/gpu/drm/xe/xe_device.c > @@ -836,14 +836,18 @@ static void override_has_cached_pt(struct xe_device *xe) > struct xe_gt *gt; > u8 id; > > - /* > - * Wa_16029380221: The affected GT will always use non-coherent > - * access to page tables, so we must do uncached writes from the > - * CPU. > - */ > - for_each_gt(gt, xe, id) > + for_each_gt(gt, xe, id) { > + /* > + * Wa_16029380221: The affected GT will always use > + * non-coherent access to page tables, so we must do > + * uncached writes from the CPU. > + */ > if (XE_GT_WA(gt, 16029380221)) > xe->info.has_cached_pt = false; > + > + if (XE_GT_WA(gt, 14026539277)) > + xe->info.has_cached_pt = false; > + } > } > > static int probe_has_flat_ccs(struct xe_device *xe) > diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c > index a5fe1beec652..a9cde12eba70 100644 > --- a/drivers/gpu/drm/xe/xe_pat.c > +++ b/drivers/gpu/drm/xe/xe_pat.c > @@ -313,6 +313,37 @@ u16 xe_pat_index_get_l3_policy(struct xe_device *xe, u16 pat_index) > return REG_FIELD_GET(XE2_L3_POLICY, xe->pat.table[pat_index].value); > } > > +bool xe_pat_wa_14026539277_reserved(struct xe_device *xe, u16 pat_index) > +{ > + struct xe_gt *gt; > + u8 id; > + bool has_wa = false; > + > + for_each_gt(gt, xe, id) { > + if (XE_GT_WA(gt, 14026539277)) { > + has_wa = true; > + break; > + } > + } > + > + return has_wa && xe_pat_index_get_l3_policy(xe, pat_index) != XE_L3_POLICY_UC && Just to make sure I understand. Why do we bother to check the l3 policy here? Do we not just want to ban all 2WAY from uapi pov? The l3/l4 policy can often be promoted via the per MOCS setting, so even if UC here it can be made WB via MOCS. Is this OK? > + xe_pat_index_get_coh_mode(xe, pat_index) == XE_COH_2WAY; > +} > + > +static u32 wa_14026539277_fixup_pat_value(struct xe_gt *gt, u32 value) > +{ > + if (XE_GT_WA(gt, 14026539277)) { > + if (REG_FIELD_GET(XE2_L3_POLICY, value) != XE_L3_POLICY_UC && > + REG_FIELD_GET(XE2_COH_MODE, value) == XE_COH_2WAY) { > + value &= ~(XE2_L3_POLICY | XE2_COH_MODE); > + value |= REG_FIELD_PREP(XE2_L3_POLICY, XE_L3_POLICY_UC) | > + REG_FIELD_PREP(XE2_COH_MODE, XE_COH_1WAY); > + } > + } > + > + return value; > +} > + > static const struct xe_pat_table_entry *gt_pta_entry(struct xe_gt *gt) > { > struct xe_device *xe = gt_to_xe(gt); > @@ -373,18 +404,22 @@ static void program_pat_mcr(struct xe_gt *gt, const struct xe_pat_table_entry ta > > for (int i = 0; i < n_entries; i++) { > struct xe_reg_mcr reg_mcr = XE_REG_MCR(_PAT_INDEX(i)); > + u32 pat = wa_14026539277_fixup_pat_value(gt, table[i].value); > > - xe_gt_mcr_multicast_write(gt, reg_mcr, table[i].value); > + xe_gt_mcr_multicast_write(gt, reg_mcr, pat); > } > > if (xe->pat.pat_ats) > - xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_ATS), xe->pat.pat_ats->value); > + xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_ATS), > + wa_14026539277_fixup_pat_value(gt, xe->pat.pat_ats->value)); > > if (pta_entry) > - xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_PTA), pta_entry->value); > + xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_PTA), > + wa_14026539277_fixup_pat_value(gt, pta_entry->value)); > > if (tr_pta_entry) > - xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_TR_PTA), tr_pta_entry->value); > + xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_TR_PTA), > + wa_14026539277_fixup_pat_value(gt, tr_pta_entry->value)); > } > > static int xelp_dump(struct xe_gt *gt, struct drm_printer *p) > @@ -534,13 +569,16 @@ static int xe2_dump(struct xe_gt *gt, struct drm_printer *p) > drm_printf(p, "PAT table: (* = reserved entry)\n"); > > for (i = 0; i < xe->pat.n_entries; i++) { > + bool rsvd = !xe->pat.table[i].valid || > + xe_pat_wa_14026539277_reserved(xe, i); > + > if (xe_gt_is_media_type(gt)) > pat = xe_mmio_read32(>->mmio, XE_REG(_PAT_INDEX(i))); > else > pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i))); > > xe_pat_index_label(label, sizeof(label), i); > - xe->pat.ops->entry_dump(p, label, pat, !xe->pat.table[i].valid); > + xe->pat.ops->entry_dump(p, label, pat, rsvd); > } > > /* > @@ -747,9 +785,14 @@ int xe_pat_dump_sw_config(struct xe_gt *gt, struct drm_printer *p) > for (u32 i = 0; i < xe->pat.n_entries; i++) { > u32 pat = xe->pat.table[i].value; > > + pat = wa_14026539277_fixup_pat_value(gt, pat); > + > if (GRAPHICS_VER(xe) >= 20) { > + bool rsvd = !xe->pat.table[i].valid || > + xe_pat_wa_14026539277_reserved(xe, i); > + > xe_pat_index_label(label, sizeof(label), i); > - xe->pat.ops->entry_dump(p, label, pat, !xe->pat.table[i].valid); > + xe->pat.ops->entry_dump(p, label, pat, rsvd); > } else if (xe->info.platform == XE_METEORLAKE) { > xelpg_pat_entry_dump(p, i, pat); > } else if (xe->info.platform == XE_PVC) { > @@ -764,6 +807,8 @@ int xe_pat_dump_sw_config(struct xe_gt *gt, struct drm_printer *p) > if (pta_entry) { > u32 pat = pta_entry->value; > > + pat = wa_14026539277_fixup_pat_value(gt, pat); > + > drm_printf(p, "Page Table Access:\n"); > xe->pat.ops->entry_dump(p, "PTA_MODE", pat, false); > } > @@ -771,6 +816,8 @@ int xe_pat_dump_sw_config(struct xe_gt *gt, struct drm_printer *p) > if (tr_pta_entry) { > u32 pat = tr_pta_entry->value; > > + pat = wa_14026539277_fixup_pat_value(gt, pat); > + > drm_printf(p, "TRTT Page Table Access:\n"); > xe->pat.ops->entry_dump(p, "TR_PTA_MODE", pat, false); > } > @@ -778,6 +825,8 @@ int xe_pat_dump_sw_config(struct xe_gt *gt, struct drm_printer *p) > if (xe->pat.pat_ats) { > u32 pat = xe->pat.pat_ats->value; > > + pat = wa_14026539277_fixup_pat_value(gt, pat); > + > drm_printf(p, "PCIe ATS/PASID:\n"); > xe->pat.ops->entry_dump(p, "PAT_ATS ", pat, false); > } > diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c > index 9e0176861cb6..64c03c669630 100644 > --- a/drivers/gpu/drm/xe/xe_vm.c > +++ b/drivers/gpu/drm/xe/xe_vm.c > @@ -3697,6 +3697,11 @@ static int vm_bind_ioctl_check_args(struct xe_device *xe, struct xe_vm *vm, > goto free_bind_ops; > } > > + if (XE_IOCTL_DBG(xe, xe_pat_wa_14026539277_reserved(xe, pat_index))) { > + err = -EINVAL; > + goto free_bind_ops; > + } > + > if (XE_IOCTL_DBG(xe, op > DRM_XE_VM_BIND_OP_PREFETCH) || > XE_IOCTL_DBG(xe, flags & ~SUPPORTED_FLAGS) || > XE_IOCTL_DBG(xe, obj && (is_null || is_cpu_addr_mirror)) || > diff --git a/drivers/gpu/drm/xe/xe_vm_madvise.c b/drivers/gpu/drm/xe/xe_vm_madvise.c > index 0474768a38aa..265273294756 100644 > --- a/drivers/gpu/drm/xe/xe_vm_madvise.c > +++ b/drivers/gpu/drm/xe/xe_vm_madvise.c > @@ -500,6 +500,9 @@ static bool check_pat_args_are_sane(struct xe_device *xe, > u16 coh_mode = xe_pat_index_get_coh_mode(xe, pat_index); > int i; > > + if (XE_IOCTL_DBG(xe, xe_pat_wa_14026539277_reserved(xe, pat_index))) > + return false; > + > /* > * Using coh_none with CPU cached buffers is not allowed on iGPU. > * On iGPU the GPU shares the LLC with the CPU, so with coh_none > diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules > index f02ac9bf7424..d53e7f75814b 100644 > --- a/drivers/gpu/drm/xe/xe_wa_oob.rules > +++ b/drivers/gpu/drm/xe/xe_wa_oob.rules > @@ -71,4 +71,5 @@ > GRAPHICS_VERSION(3511) > 16029897822 MEDIA_VERSION(3500) > GRAPHICS_VERSION(3510) > +14026539277 GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0) > 14027054324 GRAPHICS_VERSION(3511) > ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 3/3] drm/xe: Add up-to-date implementation for Wa_14026539277 2026-08-19 13:53 ` Matthew Auld @ 2026-08-19 20:37 ` Gustavo Sousa 0 siblings, 0 replies; 13+ messages in thread From: Gustavo Sousa @ 2026-08-19 20:37 UTC (permalink / raw) To: Matthew Auld, intel-xe Matthew Auld <matthew.auld@intel.com> writes: > On 24/07/2026 22:44, Gustavo Sousa wrote: >> Wa_14026539277 is a temporary workaround that targets only A* >> steppings of graphics version 35.10 and requires that we avoid using >> 2-way coherency for device-cacheable memory accesses. For >> driver-internal usage, we convert those configurations to be >> device-uncached and 1-way-coherent; on the UAPI side, we reject >> VM_BIND/MADVISE calls that are 2-way-coherent and leave it up to >> userspace to select the alternative option that is most appropriate to >> their usage. >> >> v2: >> - Add missing bits to convert the PAT value to device-uncacheable in >> wa_14026539277_fixup_pat_value(). (Sashiko) >> - Also validate the PAT index in the DRM_XE_VM_MADVISE >> ioctl. (Sashiko) >> - Match against the graphics IP instead of the platform. >> >> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> >> --- >> drivers/gpu/drm/xe/xe_pat.h | 10 +++++++ >> drivers/gpu/drm/xe/xe_device.c | 16 ++++++---- >> drivers/gpu/drm/xe/xe_pat.c | 61 ++++++++++++++++++++++++++++++++++---- >> drivers/gpu/drm/xe/xe_vm.c | 5 ++++ >> drivers/gpu/drm/xe/xe_vm_madvise.c | 3 ++ >> drivers/gpu/drm/xe/xe_wa_oob.rules | 1 + >> 6 files changed, 84 insertions(+), 12 deletions(-) >> >> diff --git a/drivers/gpu/drm/xe/xe_pat.h b/drivers/gpu/drm/xe/xe_pat.h >> index 7060f66e1d63..10374022f1d2 100644 >> --- a/drivers/gpu/drm/xe/xe_pat.h >> +++ b/drivers/gpu/drm/xe/xe_pat.h >> @@ -82,6 +82,16 @@ bool xe_pat_index_get_comp_en(struct xe_device *xe, u16 pat_index); >> */ >> u16 xe_pat_index_get_l3_policy(struct xe_device *xe, u16 pat_index); >> >> +/** >> + * xe_pat_wa_14026539277_reserved - Is this PAT index reserved from >> + * use due to Wa_14026539277? >> + * @xe: xe device >> + * @pat_index: The pat_index to query >> + * >> + * Return: a boolean indicating whether the PAT index is reserved or not. >> + */ >> +bool xe_pat_wa_14026539277_reserved(struct xe_device *xe, u16 pat_index); >> + >> #define xe_cache_pat_idx(xe, cache_mode) ({ \ >> const struct xe_device *__xedev = (xe); \ >> enum xe_cache_level __mode = (cache_mode); \ >> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c >> index 5189419a0593..c4b8023cb8a2 100644 >> --- a/drivers/gpu/drm/xe/xe_device.c >> +++ b/drivers/gpu/drm/xe/xe_device.c >> @@ -836,14 +836,18 @@ static void override_has_cached_pt(struct xe_device *xe) >> struct xe_gt *gt; >> u8 id; >> >> - /* >> - * Wa_16029380221: The affected GT will always use non-coherent >> - * access to page tables, so we must do uncached writes from the >> - * CPU. >> - */ >> - for_each_gt(gt, xe, id) >> + for_each_gt(gt, xe, id) { >> + /* >> + * Wa_16029380221: The affected GT will always use >> + * non-coherent access to page tables, so we must do >> + * uncached writes from the CPU. >> + */ >> if (XE_GT_WA(gt, 16029380221)) >> xe->info.has_cached_pt = false; >> + >> + if (XE_GT_WA(gt, 14026539277)) >> + xe->info.has_cached_pt = false; >> + } >> } >> >> static int probe_has_flat_ccs(struct xe_device *xe) >> diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c >> index a5fe1beec652..a9cde12eba70 100644 >> --- a/drivers/gpu/drm/xe/xe_pat.c >> +++ b/drivers/gpu/drm/xe/xe_pat.c >> @@ -313,6 +313,37 @@ u16 xe_pat_index_get_l3_policy(struct xe_device *xe, u16 pat_index) >> return REG_FIELD_GET(XE2_L3_POLICY, xe->pat.table[pat_index].value); >> } >> >> +bool xe_pat_wa_14026539277_reserved(struct xe_device *xe, u16 pat_index) >> +{ >> + struct xe_gt *gt; >> + u8 id; >> + bool has_wa = false; >> + >> + for_each_gt(gt, xe, id) { >> + if (XE_GT_WA(gt, 14026539277)) { >> + has_wa = true; >> + break; >> + } >> + } >> + >> + return has_wa && xe_pat_index_get_l3_policy(xe, pat_index) != XE_L3_POLICY_UC && > > Just to make sure I understand. Why do we bother to check the l3 policy > here? Do we not just want to ban all 2WAY from uapi pov? The l3/l4 > policy can often be promoted via the per MOCS setting, so even if UC > here it can be made WB via MOCS. Is this OK? That's a good point. The workaround instructions were to avoid using GT-cacheable 2-way-coherent configurations, that's why I was allowing 2-way coherency for XE_L3_POLICY_UC, but I did not think of the scenario of the cache policy being overridden by MOCS. Thanks for pointing it out! Yeah, it seems we should use a bigger hammer and disallow any 2-way coherency then. I'll change this on the next version. -- Gustavo Sousa > >> + xe_pat_index_get_coh_mode(xe, pat_index) == XE_COH_2WAY; >> +} >> + >> +static u32 wa_14026539277_fixup_pat_value(struct xe_gt *gt, u32 value) >> +{ >> + if (XE_GT_WA(gt, 14026539277)) { >> + if (REG_FIELD_GET(XE2_L3_POLICY, value) != XE_L3_POLICY_UC && >> + REG_FIELD_GET(XE2_COH_MODE, value) == XE_COH_2WAY) { >> + value &= ~(XE2_L3_POLICY | XE2_COH_MODE); >> + value |= REG_FIELD_PREP(XE2_L3_POLICY, XE_L3_POLICY_UC) | >> + REG_FIELD_PREP(XE2_COH_MODE, XE_COH_1WAY); >> + } >> + } >> + >> + return value; >> +} >> + >> static const struct xe_pat_table_entry *gt_pta_entry(struct xe_gt *gt) >> { >> struct xe_device *xe = gt_to_xe(gt); >> @@ -373,18 +404,22 @@ static void program_pat_mcr(struct xe_gt *gt, const struct xe_pat_table_entry ta >> >> for (int i = 0; i < n_entries; i++) { >> struct xe_reg_mcr reg_mcr = XE_REG_MCR(_PAT_INDEX(i)); >> + u32 pat = wa_14026539277_fixup_pat_value(gt, table[i].value); >> >> - xe_gt_mcr_multicast_write(gt, reg_mcr, table[i].value); >> + xe_gt_mcr_multicast_write(gt, reg_mcr, pat); >> } >> >> if (xe->pat.pat_ats) >> - xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_ATS), xe->pat.pat_ats->value); >> + xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_ATS), >> + wa_14026539277_fixup_pat_value(gt, xe->pat.pat_ats->value)); >> >> if (pta_entry) >> - xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_PTA), pta_entry->value); >> + xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_PTA), >> + wa_14026539277_fixup_pat_value(gt, pta_entry->value)); >> >> if (tr_pta_entry) >> - xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_TR_PTA), tr_pta_entry->value); >> + xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_TR_PTA), >> + wa_14026539277_fixup_pat_value(gt, tr_pta_entry->value)); >> } >> >> static int xelp_dump(struct xe_gt *gt, struct drm_printer *p) >> @@ -534,13 +569,16 @@ static int xe2_dump(struct xe_gt *gt, struct drm_printer *p) >> drm_printf(p, "PAT table: (* = reserved entry)\n"); >> >> for (i = 0; i < xe->pat.n_entries; i++) { >> + bool rsvd = !xe->pat.table[i].valid || >> + xe_pat_wa_14026539277_reserved(xe, i); >> + >> if (xe_gt_is_media_type(gt)) >> pat = xe_mmio_read32(>->mmio, XE_REG(_PAT_INDEX(i))); >> else >> pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i))); >> >> xe_pat_index_label(label, sizeof(label), i); >> - xe->pat.ops->entry_dump(p, label, pat, !xe->pat.table[i].valid); >> + xe->pat.ops->entry_dump(p, label, pat, rsvd); >> } >> >> /* >> @@ -747,9 +785,14 @@ int xe_pat_dump_sw_config(struct xe_gt *gt, struct drm_printer *p) >> for (u32 i = 0; i < xe->pat.n_entries; i++) { >> u32 pat = xe->pat.table[i].value; >> >> + pat = wa_14026539277_fixup_pat_value(gt, pat); >> + >> if (GRAPHICS_VER(xe) >= 20) { >> + bool rsvd = !xe->pat.table[i].valid || >> + xe_pat_wa_14026539277_reserved(xe, i); >> + >> xe_pat_index_label(label, sizeof(label), i); >> - xe->pat.ops->entry_dump(p, label, pat, !xe->pat.table[i].valid); >> + xe->pat.ops->entry_dump(p, label, pat, rsvd); >> } else if (xe->info.platform == XE_METEORLAKE) { >> xelpg_pat_entry_dump(p, i, pat); >> } else if (xe->info.platform == XE_PVC) { >> @@ -764,6 +807,8 @@ int xe_pat_dump_sw_config(struct xe_gt *gt, struct drm_printer *p) >> if (pta_entry) { >> u32 pat = pta_entry->value; >> >> + pat = wa_14026539277_fixup_pat_value(gt, pat); >> + >> drm_printf(p, "Page Table Access:\n"); >> xe->pat.ops->entry_dump(p, "PTA_MODE", pat, false); >> } >> @@ -771,6 +816,8 @@ int xe_pat_dump_sw_config(struct xe_gt *gt, struct drm_printer *p) >> if (tr_pta_entry) { >> u32 pat = tr_pta_entry->value; >> >> + pat = wa_14026539277_fixup_pat_value(gt, pat); >> + >> drm_printf(p, "TRTT Page Table Access:\n"); >> xe->pat.ops->entry_dump(p, "TR_PTA_MODE", pat, false); >> } >> @@ -778,6 +825,8 @@ int xe_pat_dump_sw_config(struct xe_gt *gt, struct drm_printer *p) >> if (xe->pat.pat_ats) { >> u32 pat = xe->pat.pat_ats->value; >> >> + pat = wa_14026539277_fixup_pat_value(gt, pat); >> + >> drm_printf(p, "PCIe ATS/PASID:\n"); >> xe->pat.ops->entry_dump(p, "PAT_ATS ", pat, false); >> } >> diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c >> index 9e0176861cb6..64c03c669630 100644 >> --- a/drivers/gpu/drm/xe/xe_vm.c >> +++ b/drivers/gpu/drm/xe/xe_vm.c >> @@ -3697,6 +3697,11 @@ static int vm_bind_ioctl_check_args(struct xe_device *xe, struct xe_vm *vm, >> goto free_bind_ops; >> } >> >> + if (XE_IOCTL_DBG(xe, xe_pat_wa_14026539277_reserved(xe, pat_index))) { >> + err = -EINVAL; >> + goto free_bind_ops; >> + } >> + >> if (XE_IOCTL_DBG(xe, op > DRM_XE_VM_BIND_OP_PREFETCH) || >> XE_IOCTL_DBG(xe, flags & ~SUPPORTED_FLAGS) || >> XE_IOCTL_DBG(xe, obj && (is_null || is_cpu_addr_mirror)) || >> diff --git a/drivers/gpu/drm/xe/xe_vm_madvise.c b/drivers/gpu/drm/xe/xe_vm_madvise.c >> index 0474768a38aa..265273294756 100644 >> --- a/drivers/gpu/drm/xe/xe_vm_madvise.c >> +++ b/drivers/gpu/drm/xe/xe_vm_madvise.c >> @@ -500,6 +500,9 @@ static bool check_pat_args_are_sane(struct xe_device *xe, >> u16 coh_mode = xe_pat_index_get_coh_mode(xe, pat_index); >> int i; >> >> + if (XE_IOCTL_DBG(xe, xe_pat_wa_14026539277_reserved(xe, pat_index))) >> + return false; >> + >> /* >> * Using coh_none with CPU cached buffers is not allowed on iGPU. >> * On iGPU the GPU shares the LLC with the CPU, so with coh_none >> diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules >> index f02ac9bf7424..d53e7f75814b 100644 >> --- a/drivers/gpu/drm/xe/xe_wa_oob.rules >> +++ b/drivers/gpu/drm/xe/xe_wa_oob.rules >> @@ -71,4 +71,5 @@ >> GRAPHICS_VERSION(3511) >> 16029897822 MEDIA_VERSION(3500) >> GRAPHICS_VERSION(3510) >> +14026539277 GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0) >> 14027054324 GRAPHICS_VERSION(3511) >> ^ permalink raw reply [flat|nested] 13+ messages in thread
* ✗ CI.checkpatch: warning for drm/xe: Update Wa_14026539277 2026-07-24 21:44 [PATCH v2 0/3] drm/xe: Update Wa_14026539277 Gustavo Sousa ` (2 preceding siblings ...) 2026-07-24 21:44 ` [PATCH v2 3/3] drm/xe: Add up-to-date implementation for Wa_14026539277 Gustavo Sousa @ 2026-07-24 22:22 ` Patchwork 2026-07-24 22:23 ` ✓ CI.KUnit: success " Patchwork 2026-07-24 22:59 ` ✓ Xe.CI.BAT: " Patchwork 5 siblings, 0 replies; 13+ messages in thread From: Patchwork @ 2026-07-24 22:22 UTC (permalink / raw) To: Gustavo Sousa; +Cc: intel-xe == Series Details == Series: drm/xe: Update Wa_14026539277 URL : https://patchwork.freedesktop.org/series/171093/ State : warning == Summary == + KERNEL=/kernel + git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt Cloning into 'mt'... warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/ + git -C mt rev-list -n1 origin/master 061140b9bc586ae7f40abc1249c97e1cc72d1b9d + cd /kernel + git config --global --add safe.directory /kernel + git log -n1 commit 26de468102d3c6fdf460c47058ed27da4855cd30 Author: Gustavo Sousa <gustavo.sousa@intel.com> Date: Fri Jul 24 18:44:19 2026 -0300 drm/xe: Add up-to-date implementation for Wa_14026539277 Wa_14026539277 is a temporary workaround that targets only A* steppings of graphics version 35.10 and requires that we avoid using 2-way coherency for device-cacheable memory accesses. For driver-internal usage, we convert those configurations to be device-uncached and 1-way-coherent; on the UAPI side, we reject VM_BIND/MADVISE calls that are 2-way-coherent and leave it up to userspace to select the alternative option that is most appropriate to their usage. v2: - Add missing bits to convert the PAT value to device-uncacheable in wa_14026539277_fixup_pat_value(). (Sashiko) - Also validate the PAT index in the DRM_XE_VM_MADVISE ioctl. (Sashiko) - Match against the graphics IP instead of the platform. Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> + /mt/dim checkpatch 03696c1dc9eabc0658baefcff8787dab48c89d93 drm-intel 7a74ec71abc1 drm/xe: Extract override_has_cached_pt() 0c0cca170ffd Revert "drm/xe/nvlp: Implement Wa_14026539277" 26de468102d3 drm/xe: Add up-to-date implementation for Wa_14026539277 -:108: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #108: FILE: drivers/gpu/drm/xe/xe_pat.c:414: + wa_14026539277_fixup_pat_value(gt, xe->pat.pat_ats->value)); total: 0 errors, 1 warnings, 0 checks, 184 lines checked ^ permalink raw reply [flat|nested] 13+ messages in thread
* ✓ CI.KUnit: success for drm/xe: Update Wa_14026539277 2026-07-24 21:44 [PATCH v2 0/3] drm/xe: Update Wa_14026539277 Gustavo Sousa ` (3 preceding siblings ...) 2026-07-24 22:22 ` ✗ CI.checkpatch: warning for drm/xe: Update Wa_14026539277 Patchwork @ 2026-07-24 22:23 ` Patchwork 2026-07-24 22:59 ` ✓ Xe.CI.BAT: " Patchwork 5 siblings, 0 replies; 13+ messages in thread From: Patchwork @ 2026-07-24 22:23 UTC (permalink / raw) To: Gustavo Sousa; +Cc: intel-xe == Series Details == Series: drm/xe: Update Wa_14026539277 URL : https://patchwork.freedesktop.org/series/171093/ State : success == Summary == + trap cleanup EXIT + /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig [22:22:28] Configuring KUnit Kernel ... Generating .config ... Populating config with: $ make ARCH=um O=.kunit olddefconfig [22:22:32] Building KUnit Kernel ... Populating config with: $ make ARCH=um O=.kunit olddefconfig Building with: $ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48 [22:23:05] Starting KUnit Kernel (1/1)... [22:23:05] ============================================================ Running tests with: $ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt [22:23:05] ================== guc_buf (11 subtests) =================== [22:23:05] [PASSED] test_smallest [22:23:05] [PASSED] test_largest [22:23:05] [PASSED] test_granular [22:23:05] [PASSED] test_unique [22:23:05] [PASSED] test_overlap [22:23:05] [PASSED] test_reusable [22:23:05] [PASSED] test_too_big [22:23:05] [PASSED] test_flush [22:23:05] [PASSED] test_lookup [22:23:05] [PASSED] test_data [22:23:05] [PASSED] test_class [22:23:05] ===================== [PASSED] guc_buf ===================== [22:23:05] =================== guc_dbm (7 subtests) =================== [22:23:05] [PASSED] test_empty [22:23:05] [PASSED] test_default [22:23:05] ======================== test_size ======================== [22:23:05] [PASSED] 4 [22:23:05] [PASSED] 8 [22:23:05] [PASSED] 32 [22:23:05] [PASSED] 256 [22:23:05] ==================== [PASSED] test_size ==================== [22:23:05] ======================= test_reuse ======================== [22:23:05] [PASSED] 4 [22:23:05] [PASSED] 8 [22:23:05] [PASSED] 32 [22:23:05] [PASSED] 256 [22:23:05] =================== [PASSED] test_reuse ==================== [22:23:05] =================== test_range_overlap ==================== [22:23:05] [PASSED] 4 [22:23:05] [PASSED] 8 [22:23:05] [PASSED] 32 [22:23:05] [PASSED] 256 [22:23:05] =============== [PASSED] test_range_overlap ================ [22:23:05] =================== test_range_compact ==================== [22:23:05] [PASSED] 4 [22:23:05] [PASSED] 8 [22:23:05] [PASSED] 32 [22:23:05] [PASSED] 256 [22:23:05] =============== [PASSED] test_range_compact ================ [22:23:05] ==================== test_range_spare ===================== [22:23:05] [PASSED] 4 [22:23:05] [PASSED] 8 [22:23:05] [PASSED] 32 [22:23:05] [PASSED] 256 [22:23:05] ================ [PASSED] test_range_spare ================= [22:23:05] ===================== [PASSED] guc_dbm ===================== [22:23:05] =================== guc_idm (6 subtests) =================== [22:23:05] [PASSED] bad_init [22:23:05] [PASSED] no_init [22:23:05] [PASSED] init_fini [22:23:05] [PASSED] check_used [22:23:05] [PASSED] check_quota [22:23:05] [PASSED] check_all [22:23:05] ===================== [PASSED] guc_idm ===================== [22:23:05] =============== guc_klv_helpers (9 subtests) =============== [22:23:05] [PASSED] test_count [22:23:05] [PASSED] test_encode_u32 [22:23:05] [PASSED] test_encode_u64 [22:23:05] [PASSED] test_encode_string [22:23:05] [PASSED] test_encode_object_raw [22:23:05] [PASSED] test_encode_object_klv [22:23:05] [PASSED] test_encode_object_nested [22:23:05] [PASSED] test_encode_object_basic [22:23:05] [PASSED] test_print [22:23:05] ================= [PASSED] guc_klv_helpers ================= [22:23:05] ================== no_relay (3 subtests) =================== [22:23:05] [PASSED] xe_drops_guc2pf_if_not_ready [22:23:05] [PASSED] xe_drops_guc2vf_if_not_ready [22:23:05] [PASSED] xe_rejects_send_if_not_ready [22:23:05] ==================== [PASSED] no_relay ===================== [22:23:05] ================== pf_relay (14 subtests) ================== [22:23:05] [PASSED] pf_rejects_guc2pf_too_short [22:23:05] [PASSED] pf_rejects_guc2pf_too_long [22:23:05] [PASSED] pf_rejects_guc2pf_no_payload [22:23:05] [PASSED] pf_fails_no_payload [22:23:05] [PASSED] pf_fails_bad_origin [22:23:05] [PASSED] pf_fails_bad_type [22:23:05] [PASSED] pf_txn_reports_error [22:23:05] [PASSED] pf_txn_sends_pf2guc [22:23:05] [PASSED] pf_sends_pf2guc [22:23:05] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV) [22:23:05] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV) [22:23:05] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV) [22:23:05] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV) [22:23:05] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV) [22:23:05] ==================== [PASSED] pf_relay ===================== [22:23:05] ================== vf_relay (3 subtests) =================== [22:23:05] [PASSED] vf_rejects_guc2vf_too_short [22:23:05] [PASSED] vf_rejects_guc2vf_too_long [22:23:05] [PASSED] vf_rejects_guc2vf_no_payload [22:23:05] ==================== [PASSED] vf_relay ===================== [22:23:05] ================ pf_gt_config (9 subtests) ================= [22:23:05] [PASSED] fair_contexts_1vf [22:23:05] [PASSED] fair_doorbells_1vf [22:23:05] [PASSED] fair_ggtt_1vf [22:23:05] ====================== fair_vram_1vf ====================== [22:23:05] [PASSED] 3.50 GiB [22:23:05] [PASSED] 11.5 GiB [22:23:05] [PASSED] 15.5 GiB [22:23:05] [PASSED] 31.5 GiB [22:23:05] [PASSED] 63.5 GiB [22:23:05] [PASSED] 1.91 GiB [22:23:05] ================== [PASSED] fair_vram_1vf ================== [22:23:05] ================ fair_vram_1vf_admin_only ================= [22:23:05] [PASSED] 3.50 GiB [22:23:05] [PASSED] 11.5 GiB [22:23:05] [PASSED] 15.5 GiB [22:23:05] [PASSED] 31.5 GiB [22:23:05] [PASSED] 63.5 GiB [22:23:05] [PASSED] 1.91 GiB [22:23:05] ============ [PASSED] fair_vram_1vf_admin_only ============= [22:23:05] ====================== fair_contexts ====================== [22:23:05] [PASSED] 1 VF [22:23:05] [PASSED] 2 VFs [22:23:05] [PASSED] 3 VFs [22:23:05] [PASSED] 4 VFs [22:23:05] [PASSED] 5 VFs [22:23:05] [PASSED] 6 VFs [22:23:05] [PASSED] 7 VFs [22:23:05] [PASSED] 8 VFs [22:23:05] [PASSED] 9 VFs [22:23:05] [PASSED] 10 VFs [22:23:05] [PASSED] 11 VFs [22:23:05] [PASSED] 12 VFs [22:23:05] [PASSED] 13 VFs [22:23:05] [PASSED] 14 VFs [22:23:05] [PASSED] 15 VFs [22:23:05] [PASSED] 16 VFs [22:23:05] [PASSED] 17 VFs [22:23:05] [PASSED] 18 VFs [22:23:05] [PASSED] 19 VFs [22:23:05] [PASSED] 20 VFs [22:23:05] [PASSED] 21 VFs [22:23:05] [PASSED] 22 VFs [22:23:05] [PASSED] 23 VFs [22:23:05] [PASSED] 24 VFs [22:23:05] [PASSED] 25 VFs [22:23:05] [PASSED] 26 VFs [22:23:05] [PASSED] 27 VFs [22:23:05] [PASSED] 28 VFs [22:23:05] [PASSED] 29 VFs [22:23:05] [PASSED] 30 VFs [22:23:05] [PASSED] 31 VFs [22:23:05] [PASSED] 32 VFs [22:23:05] [PASSED] 33 VFs [22:23:05] [PASSED] 34 VFs [22:23:05] [PASSED] 35 VFs [22:23:05] [PASSED] 36 VFs [22:23:05] [PASSED] 37 VFs [22:23:05] [PASSED] 38 VFs [22:23:05] [PASSED] 39 VFs [22:23:05] [PASSED] 40 VFs [22:23:05] [PASSED] 41 VFs [22:23:05] [PASSED] 42 VFs [22:23:05] [PASSED] 43 VFs [22:23:05] [PASSED] 44 VFs [22:23:05] [PASSED] 45 VFs [22:23:05] [PASSED] 46 VFs [22:23:05] [PASSED] 47 VFs [22:23:05] [PASSED] 48 VFs [22:23:05] [PASSED] 49 VFs [22:23:05] [PASSED] 50 VFs [22:23:05] [PASSED] 51 VFs [22:23:05] [PASSED] 52 VFs [22:23:05] [PASSED] 53 VFs [22:23:05] [PASSED] 54 VFs [22:23:05] [PASSED] 55 VFs [22:23:05] [PASSED] 56 VFs [22:23:05] [PASSED] 57 VFs [22:23:05] [PASSED] 58 VFs [22:23:05] [PASSED] 59 VFs [22:23:05] [PASSED] 60 VFs [22:23:05] [PASSED] 61 VFs [22:23:05] [PASSED] 62 VFs [22:23:05] [PASSED] 63 VFs [22:23:05] ================== [PASSED] fair_contexts ================== [22:23:05] ===================== fair_doorbells ====================== [22:23:05] [PASSED] 1 VF [22:23:05] [PASSED] 2 VFs [22:23:05] [PASSED] 3 VFs [22:23:05] [PASSED] 4 VFs [22:23:05] [PASSED] 5 VFs [22:23:05] [PASSED] 6 VFs [22:23:05] [PASSED] 7 VFs [22:23:05] [PASSED] 8 VFs [22:23:05] [PASSED] 9 VFs [22:23:05] [PASSED] 10 VFs [22:23:05] [PASSED] 11 VFs [22:23:05] [PASSED] 12 VFs [22:23:05] [PASSED] 13 VFs [22:23:05] [PASSED] 14 VFs [22:23:05] [PASSED] 15 VFs [22:23:05] [PASSED] 16 VFs [22:23:05] [PASSED] 17 VFs [22:23:05] [PASSED] 18 VFs [22:23:05] [PASSED] 19 VFs [22:23:05] [PASSED] 20 VFs [22:23:05] [PASSED] 21 VFs [22:23:05] [PASSED] 22 VFs [22:23:05] [PASSED] 23 VFs [22:23:05] [PASSED] 24 VFs [22:23:05] [PASSED] 25 VFs [22:23:05] [PASSED] 26 VFs [22:23:05] [PASSED] 27 VFs [22:23:05] [PASSED] 28 VFs [22:23:05] [PASSED] 29 VFs [22:23:05] [PASSED] 30 VFs [22:23:05] [PASSED] 31 VFs [22:23:05] [PASSED] 32 VFs [22:23:05] [PASSED] 33 VFs [22:23:05] [PASSED] 34 VFs [22:23:05] [PASSED] 35 VFs [22:23:05] [PASSED] 36 VFs [22:23:05] [PASSED] 37 VFs [22:23:05] [PASSED] 38 VFs [22:23:05] [PASSED] 39 VFs [22:23:05] [PASSED] 40 VFs [22:23:05] [PASSED] 41 VFs [22:23:05] [PASSED] 42 VFs [22:23:05] [PASSED] 43 VFs [22:23:05] [PASSED] 44 VFs [22:23:05] [PASSED] 45 VFs [22:23:05] [PASSED] 46 VFs [22:23:05] [PASSED] 47 VFs [22:23:05] [PASSED] 48 VFs [22:23:05] [PASSED] 49 VFs [22:23:05] [PASSED] 50 VFs [22:23:05] [PASSED] 51 VFs [22:23:05] [PASSED] 52 VFs [22:23:05] [PASSED] 53 VFs [22:23:05] [PASSED] 54 VFs [22:23:05] [PASSED] 55 VFs [22:23:05] [PASSED] 56 VFs [22:23:05] [PASSED] 57 VFs [22:23:05] [PASSED] 58 VFs [22:23:05] [PASSED] 59 VFs [22:23:05] [PASSED] 60 VFs [22:23:05] [PASSED] 61 VFs [22:23:05] [PASSED] 62 VFs [22:23:05] [PASSED] 63 VFs [22:23:05] ================= [PASSED] fair_doorbells ================== [22:23:05] ======================== fair_ggtt ======================== [22:23:05] [PASSED] 1 VF [22:23:05] [PASSED] 2 VFs [22:23:05] [PASSED] 3 VFs [22:23:05] [PASSED] 4 VFs [22:23:05] [PASSED] 5 VFs [22:23:05] [PASSED] 6 VFs [22:23:05] [PASSED] 7 VFs [22:23:05] [PASSED] 8 VFs [22:23:05] [PASSED] 9 VFs [22:23:05] [PASSED] 10 VFs [22:23:05] [PASSED] 11 VFs [22:23:05] [PASSED] 12 VFs [22:23:05] [PASSED] 13 VFs [22:23:05] [PASSED] 14 VFs [22:23:05] [PASSED] 15 VFs [22:23:05] [PASSED] 16 VFs [22:23:05] [PASSED] 17 VFs [22:23:05] [PASSED] 18 VFs [22:23:05] [PASSED] 19 VFs [22:23:05] [PASSED] 20 VFs [22:23:05] [PASSED] 21 VFs [22:23:05] [PASSED] 22 VFs [22:23:05] [PASSED] 23 VFs [22:23:05] [PASSED] 24 VFs [22:23:05] [PASSED] 25 VFs [22:23:05] [PASSED] 26 VFs [22:23:05] [PASSED] 27 VFs [22:23:05] [PASSED] 28 VFs [22:23:05] [PASSED] 29 VFs [22:23:05] [PASSED] 30 VFs [22:23:05] [PASSED] 31 VFs [22:23:05] [PASSED] 32 VFs [22:23:05] [PASSED] 33 VFs [22:23:05] [PASSED] 34 VFs [22:23:05] [PASSED] 35 VFs [22:23:05] [PASSED] 36 VFs [22:23:05] [PASSED] 37 VFs [22:23:05] [PASSED] 38 VFs [22:23:05] [PASSED] 39 VFs [22:23:05] [PASSED] 40 VFs [22:23:05] [PASSED] 41 VFs [22:23:05] [PASSED] 42 VFs [22:23:05] [PASSED] 43 VFs [22:23:05] [PASSED] 44 VFs [22:23:05] [PASSED] 45 VFs [22:23:05] [PASSED] 46 VFs [22:23:05] [PASSED] 47 VFs [22:23:05] [PASSED] 48 VFs [22:23:05] [PASSED] 49 VFs [22:23:05] [PASSED] 50 VFs [22:23:05] [PASSED] 51 VFs [22:23:05] [PASSED] 52 VFs [22:23:05] [PASSED] 53 VFs [22:23:05] [PASSED] 54 VFs [22:23:05] [PASSED] 55 VFs [22:23:05] [PASSED] 56 VFs [22:23:05] [PASSED] 57 VFs [22:23:05] [PASSED] 58 VFs [22:23:05] [PASSED] 59 VFs [22:23:05] [PASSED] 60 VFs [22:23:05] [PASSED] 61 VFs [22:23:05] [PASSED] 62 VFs [22:23:05] [PASSED] 63 VFs [22:23:05] ==================== [PASSED] fair_ggtt ==================== [22:23:05] ======================== fair_vram ======================== [22:23:05] [PASSED] 1 VF [22:23:05] [PASSED] 2 VFs [22:23:05] [PASSED] 3 VFs [22:23:05] [PASSED] 4 VFs [22:23:05] [PASSED] 5 VFs [22:23:05] [PASSED] 6 VFs [22:23:05] [PASSED] 7 VFs [22:23:05] [PASSED] 8 VFs [22:23:05] [PASSED] 9 VFs [22:23:05] [PASSED] 10 VFs [22:23:05] [PASSED] 11 VFs [22:23:05] [PASSED] 12 VFs [22:23:05] [PASSED] 13 VFs [22:23:05] [PASSED] 14 VFs [22:23:05] [PASSED] 15 VFs [22:23:05] [PASSED] 16 VFs [22:23:05] [PASSED] 17 VFs [22:23:05] [PASSED] 18 VFs [22:23:05] [PASSED] 19 VFs [22:23:05] [PASSED] 20 VFs [22:23:05] [PASSED] 21 VFs [22:23:05] [PASSED] 22 VFs [22:23:05] [PASSED] 23 VFs [22:23:05] [PASSED] 24 VFs [22:23:05] [PASSED] 25 VFs [22:23:05] [PASSED] 26 VFs [22:23:05] [PASSED] 27 VFs [22:23:05] [PASSED] 28 VFs [22:23:05] [PASSED] 29 VFs [22:23:05] [PASSED] 30 VFs [22:23:05] [PASSED] 31 VFs [22:23:05] [PASSED] 32 VFs [22:23:05] [PASSED] 33 VFs [22:23:05] [PASSED] 34 VFs [22:23:05] [PASSED] 35 VFs [22:23:05] [PASSED] 36 VFs [22:23:05] [PASSED] 37 VFs [22:23:05] [PASSED] 38 VFs [22:23:05] [PASSED] 39 VFs [22:23:05] [PASSED] 40 VFs [22:23:05] [PASSED] 41 VFs [22:23:05] [PASSED] 42 VFs [22:23:05] [PASSED] 43 VFs [22:23:05] [PASSED] 44 VFs [22:23:05] [PASSED] 45 VFs [22:23:05] [PASSED] 46 VFs [22:23:05] [PASSED] 47 VFs [22:23:05] [PASSED] 48 VFs [22:23:05] [PASSED] 49 VFs [22:23:05] [PASSED] 50 VFs [22:23:05] [PASSED] 51 VFs [22:23:05] [PASSED] 52 VFs [22:23:05] [PASSED] 53 VFs [22:23:05] [PASSED] 54 VFs [22:23:05] [PASSED] 55 VFs [22:23:05] [PASSED] 56 VFs [22:23:05] [PASSED] 57 VFs [22:23:05] [PASSED] 58 VFs [22:23:05] [PASSED] 59 VFs [22:23:05] [PASSED] 60 VFs [22:23:05] [PASSED] 61 VFs [22:23:05] [PASSED] 62 VFs [22:23:05] [PASSED] 63 VFs [22:23:05] ==================== [PASSED] fair_vram ==================== [22:23:05] ================== [PASSED] pf_gt_config =================== [22:23:05] ===================== lmtt (1 subtest) ===================== [22:23:05] ======================== test_ops ========================= [22:23:05] [PASSED] 2-level [22:23:05] [PASSED] multi-level [22:23:05] ==================== [PASSED] test_ops ===================== [22:23:05] ====================== [PASSED] lmtt ======================= [22:23:05] ================= sriov_packet (1 subtest) ================= [22:23:05] [PASSED] test_descriptor_init [22:23:05] ================== [PASSED] sriov_packet =================== [22:23:05] ================= pf_service (11 subtests) ================= [22:23:05] [PASSED] pf_negotiate_any [22:23:05] [PASSED] pf_negotiate_base_match [22:23:05] [PASSED] pf_negotiate_base_newer [22:23:05] [PASSED] pf_negotiate_base_next [22:23:05] [SKIPPED] pf_negotiate_base_older (no older minor) [22:23:05] [PASSED] pf_negotiate_base_prev [22:23:05] [PASSED] pf_negotiate_latest_match [22:23:05] [PASSED] pf_negotiate_latest_newer [22:23:05] [PASSED] pf_negotiate_latest_next [22:23:05] [SKIPPED] pf_negotiate_latest_older (no older minor) [22:23:05] [SKIPPED] pf_negotiate_latest_prev (no prev major) [22:23:05] =================== [PASSED] pf_service ==================== [22:23:05] ================= xe_guc_g2g (2 subtests) ================== [22:23:05] ============== xe_live_guc_g2g_kunit_default ============== [22:23:05] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ========== [22:23:05] ============== xe_live_guc_g2g_kunit_allmem =============== [22:23:05] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ========== [22:23:05] =================== [SKIPPED] xe_guc_g2g =================== [22:23:05] =================== xe_mocs (2 subtests) =================== [22:23:05] ================ xe_live_mocs_kernel_kunit ================ [22:23:05] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============ [22:23:05] ================ xe_live_mocs_reset_kunit ================= [22:23:05] ============ [SKIPPED] xe_live_mocs_reset_kunit ============ [22:23:05] ==================== [SKIPPED] xe_mocs ===================== [22:23:05] ================= xe_migrate (2 subtests) ================== [22:23:05] ================= xe_migrate_sanity_kunit ================= [22:23:05] ============ [SKIPPED] xe_migrate_sanity_kunit ============= [22:23:05] ================== xe_validate_ccs_kunit ================== [22:23:05] ============= [SKIPPED] xe_validate_ccs_kunit ============== [22:23:05] =================== [SKIPPED] xe_migrate =================== [22:23:05] ================== xe_dma_buf (1 subtest) ================== [22:23:05] ==================== xe_dma_buf_kunit ===================== [22:23:05] ================ [SKIPPED] xe_dma_buf_kunit ================ [22:23:05] =================== [SKIPPED] xe_dma_buf =================== [22:23:05] ================= xe_bo_shrink (1 subtest) ================= [22:23:05] =================== xe_bo_shrink_kunit ==================== [22:23:05] =============== [SKIPPED] xe_bo_shrink_kunit =============== [22:23:05] ================== [SKIPPED] xe_bo_shrink ================== [22:23:05] ==================== xe_bo (2 subtests) ==================== [22:23:05] ================== xe_ccs_migrate_kunit =================== [22:23:05] ============== [SKIPPED] xe_ccs_migrate_kunit ============== [22:23:05] ==================== xe_bo_evict_kunit ==================== [22:23:05] =============== [SKIPPED] xe_bo_evict_kunit ================ [22:23:05] ===================== [SKIPPED] xe_bo ====================== [22:23:05] ==================== args (13 subtests) ==================== [22:23:05] [PASSED] count_args_test [22:23:05] [PASSED] call_args_example [22:23:05] [PASSED] call_args_test [22:23:05] [PASSED] drop_first_arg_example [22:23:05] [PASSED] drop_first_arg_test [22:23:05] [PASSED] first_arg_example [22:23:05] [PASSED] first_arg_test [22:23:05] [PASSED] last_arg_example [22:23:05] [PASSED] last_arg_test [22:23:05] [PASSED] pick_arg_example [22:23:05] [PASSED] if_args_example [22:23:05] [PASSED] if_args_test [22:23:05] [PASSED] sep_comma_example [22:23:05] ====================== [PASSED] args ======================= [22:23:05] =================== xe_pci (3 subtests) ==================== [22:23:05] ==================== check_graphics_ip ==================== [22:23:05] [PASSED] 12.00 Xe_LP [22:23:05] [PASSED] 12.10 Xe_LP+ [22:23:05] [PASSED] 12.55 Xe_HPG [22:23:05] [PASSED] 12.60 Xe_HPC [22:23:05] [PASSED] 12.70 Xe_LPG [22:23:05] [PASSED] 12.71 Xe_LPG [22:23:05] [PASSED] 12.74 Xe_LPG+ [22:23:05] [PASSED] 20.01 Xe2_HPG [22:23:05] [PASSED] 20.02 Xe2_HPG [22:23:05] [PASSED] 20.04 Xe2_LPG [22:23:05] [PASSED] 30.00 Xe3_LPG [22:23:05] [PASSED] 30.01 Xe3_LPG [22:23:05] [PASSED] 30.03 Xe3_LPG [22:23:05] [PASSED] 30.04 Xe3_LPG [22:23:05] [PASSED] 30.05 Xe3_LPG [22:23:05] [PASSED] 35.10 Xe3p_LPG [22:23:05] [PASSED] 35.11 Xe3p_XPC [22:23:05] ================ [PASSED] check_graphics_ip ================ [22:23:05] ===================== check_media_ip ====================== [22:23:05] [PASSED] 12.00 Xe_M [22:23:05] [PASSED] 12.55 Xe_HPM [22:23:05] [PASSED] 13.00 Xe_LPM+ [22:23:05] [PASSED] 13.01 Xe2_HPM [22:23:05] [PASSED] 20.00 Xe2_LPM [22:23:05] [PASSED] 30.00 Xe3_LPM [22:23:05] [PASSED] 30.02 Xe3_LPM [22:23:05] [PASSED] 35.00 Xe3p_LPM [22:23:05] [PASSED] 35.03 Xe3p_HPM [22:23:05] ================= [PASSED] check_media_ip ================== [22:23:05] =================== check_platform_desc =================== [22:23:05] [PASSED] 0x9A60 (TIGERLAKE) [22:23:05] [PASSED] 0x9A68 (TIGERLAKE) [22:23:05] [PASSED] 0x9A70 (TIGERLAKE) [22:23:05] [PASSED] 0x9A40 (TIGERLAKE) [22:23:05] [PASSED] 0x9A49 (TIGERLAKE) [22:23:05] [PASSED] 0x9A59 (TIGERLAKE) [22:23:05] [PASSED] 0x9A78 (TIGERLAKE) [22:23:05] [PASSED] 0x9AC0 (TIGERLAKE) [22:23:05] [PASSED] 0x9AC9 (TIGERLAKE) [22:23:05] [PASSED] 0x9AD9 (TIGERLAKE) [22:23:05] [PASSED] 0x9AF8 (TIGERLAKE) [22:23:05] [PASSED] 0x4C80 (ROCKETLAKE) [22:23:05] [PASSED] 0x4C8A (ROCKETLAKE) [22:23:05] [PASSED] 0x4C8B (ROCKETLAKE) [22:23:05] [PASSED] 0x4C8C (ROCKETLAKE) [22:23:05] [PASSED] 0x4C90 (ROCKETLAKE) [22:23:05] [PASSED] 0x4C9A (ROCKETLAKE) [22:23:05] [PASSED] 0x4680 (ALDERLAKE_S) [22:23:05] [PASSED] 0x4682 (ALDERLAKE_S) [22:23:05] [PASSED] 0x4688 (ALDERLAKE_S) [22:23:05] [PASSED] 0x468A (ALDERLAKE_S) [22:23:05] [PASSED] 0x468B (ALDERLAKE_S) [22:23:05] [PASSED] 0x4690 (ALDERLAKE_S) [22:23:05] [PASSED] 0x4692 (ALDERLAKE_S) [22:23:05] [PASSED] 0x4693 (ALDERLAKE_S) [22:23:05] [PASSED] 0x46A0 (ALDERLAKE_P) [22:23:05] [PASSED] 0x46A1 (ALDERLAKE_P) [22:23:05] [PASSED] 0x46A2 (ALDERLAKE_P) [22:23:05] [PASSED] 0x46A3 (ALDERLAKE_P) [22:23:05] [PASSED] 0x46A6 (ALDERLAKE_P) [22:23:05] [PASSED] 0x46A8 (ALDERLAKE_P) [22:23:05] [PASSED] 0x46AA (ALDERLAKE_P) [22:23:05] [PASSED] 0x462A (ALDERLAKE_P) [22:23:05] [PASSED] 0x4626 (ALDERLAKE_P) [22:23:05] [PASSED] 0x4628 (ALDERLAKE_P) [22:23:05] [PASSED] 0x46B0 (ALDERLAKE_P) [22:23:05] [PASSED] 0x46B1 (ALDERLAKE_P) [22:23:05] [PASSED] 0x46B2 (ALDERLAKE_P) [22:23:05] [PASSED] 0x46B3 (ALDERLAKE_P) [22:23:05] [PASSED] 0x46C0 (ALDERLAKE_P) [22:23:05] [PASSED] 0x46C1 (ALDERLAKE_P) [22:23:05] [PASSED] 0x46C2 (ALDERLAKE_P) [22:23:05] [PASSED] 0x46C3 (ALDERLAKE_P) [22:23:05] [PASSED] 0x46D0 (ALDERLAKE_N) [22:23:05] [PASSED] 0x46D1 (ALDERLAKE_N) [22:23:05] [PASSED] 0x46D2 (ALDERLAKE_N) [22:23:05] [PASSED] 0x46D3 (ALDERLAKE_N) [22:23:05] [PASSED] 0x46D4 (ALDERLAKE_N) [22:23:05] [PASSED] 0xA721 (ALDERLAKE_P) [22:23:05] [PASSED] 0xA7A1 (ALDERLAKE_P) [22:23:05] [PASSED] 0xA7A9 (ALDERLAKE_P) [22:23:05] [PASSED] 0xA7AC (ALDERLAKE_P) [22:23:05] [PASSED] 0xA7AD (ALDERLAKE_P) [22:23:05] [PASSED] 0xA720 (ALDERLAKE_P) [22:23:05] [PASSED] 0xA7A0 (ALDERLAKE_P) [22:23:05] [PASSED] 0xA7A8 (ALDERLAKE_P) [22:23:05] [PASSED] 0xA7AA (ALDERLAKE_P) [22:23:05] [PASSED] 0xA7AB (ALDERLAKE_P) [22:23:05] [PASSED] 0xA780 (ALDERLAKE_S) [22:23:05] [PASSED] 0xA781 (ALDERLAKE_S) [22:23:05] [PASSED] 0xA782 (ALDERLAKE_S) [22:23:05] [PASSED] 0xA783 (ALDERLAKE_S) [22:23:05] [PASSED] 0xA788 (ALDERLAKE_S) [22:23:05] [PASSED] 0xA789 (ALDERLAKE_S) [22:23:05] [PASSED] 0xA78A (ALDERLAKE_S) [22:23:05] [PASSED] 0xA78B (ALDERLAKE_S) [22:23:05] [PASSED] 0x4905 (DG1) [22:23:05] [PASSED] 0x4906 (DG1) [22:23:05] [PASSED] 0x4907 (DG1) [22:23:05] [PASSED] 0x4908 (DG1) [22:23:05] [PASSED] 0x4909 (DG1) [22:23:05] [PASSED] 0x56C0 (DG2) [22:23:05] [PASSED] 0x56C2 (DG2) [22:23:05] [PASSED] 0x56C1 (DG2) [22:23:05] [PASSED] 0x7D51 (METEORLAKE) [22:23:05] [PASSED] 0x7DD1 (METEORLAKE) [22:23:05] [PASSED] 0x7D41 (METEORLAKE) [22:23:05] [PASSED] 0x7D67 (METEORLAKE) [22:23:05] [PASSED] 0xB640 (METEORLAKE) [22:23:05] [PASSED] 0x56A0 (DG2) [22:23:05] [PASSED] 0x56A1 (DG2) [22:23:05] [PASSED] 0x56A2 (DG2) [22:23:05] [PASSED] 0x56BE (DG2) [22:23:05] [PASSED] 0x56BF (DG2) [22:23:05] [PASSED] 0x5690 (DG2) [22:23:05] [PASSED] 0x5691 (DG2) [22:23:05] [PASSED] 0x5692 (DG2) [22:23:05] [PASSED] 0x56A5 (DG2) [22:23:05] [PASSED] 0x56A6 (DG2) [22:23:05] [PASSED] 0x56B0 (DG2) [22:23:05] [PASSED] 0x56B1 (DG2) [22:23:05] [PASSED] 0x56BA (DG2) [22:23:05] [PASSED] 0x56BB (DG2) [22:23:05] [PASSED] 0x56BC (DG2) [22:23:05] [PASSED] 0x56BD (DG2) [22:23:05] [PASSED] 0x5693 (DG2) [22:23:05] [PASSED] 0x5694 (DG2) [22:23:05] [PASSED] 0x5695 (DG2) [22:23:05] [PASSED] 0x56A3 (DG2) [22:23:05] [PASSED] 0x56A4 (DG2) [22:23:05] [PASSED] 0x56B2 (DG2) [22:23:05] [PASSED] 0x56B3 (DG2) [22:23:05] [PASSED] 0x5696 (DG2) [22:23:05] [PASSED] 0x5697 (DG2) [22:23:05] [PASSED] 0xB69 (PVC) [22:23:05] [PASSED] 0xB6E (PVC) [22:23:05] [PASSED] 0xBD4 (PVC) [22:23:05] [PASSED] 0xBD5 (PVC) [22:23:05] [PASSED] 0xBD6 (PVC) [22:23:05] [PASSED] 0xBD7 (PVC) [22:23:05] [PASSED] 0xBD8 (PVC) [22:23:05] [PASSED] 0xBD9 (PVC) [22:23:05] [PASSED] 0xBDA (PVC) [22:23:05] [PASSED] 0xBDB (PVC) [22:23:05] [PASSED] 0xBE0 (PVC) [22:23:05] [PASSED] 0xBE1 (PVC) [22:23:05] [PASSED] 0xBE5 (PVC) [22:23:05] [PASSED] 0x7D40 (METEORLAKE) [22:23:05] [PASSED] 0x7D45 (METEORLAKE) [22:23:05] [PASSED] 0x7D55 (METEORLAKE) [22:23:05] [PASSED] 0x7D60 (METEORLAKE) [22:23:05] [PASSED] 0x7DD5 (METEORLAKE) [22:23:05] [PASSED] 0x6420 (LUNARLAKE) [22:23:05] [PASSED] 0x64A0 (LUNARLAKE) [22:23:05] [PASSED] 0x64B0 (LUNARLAKE) [22:23:05] [PASSED] 0xE202 (BATTLEMAGE) [22:23:05] [PASSED] 0xE209 (BATTLEMAGE) [22:23:05] [PASSED] 0xE20B (BATTLEMAGE) [22:23:05] [PASSED] 0xE20C (BATTLEMAGE) [22:23:05] [PASSED] 0xE20D (BATTLEMAGE) [22:23:05] [PASSED] 0xE210 (BATTLEMAGE) [22:23:05] [PASSED] 0xE211 (BATTLEMAGE) [22:23:05] [PASSED] 0xE212 (BATTLEMAGE) [22:23:05] [PASSED] 0xE216 (BATTLEMAGE) [22:23:05] [PASSED] 0xE220 (BATTLEMAGE) [22:23:05] [PASSED] 0xE221 (BATTLEMAGE) [22:23:05] [PASSED] 0xE222 (BATTLEMAGE) [22:23:05] [PASSED] 0xE223 (BATTLEMAGE) [22:23:05] [PASSED] 0xB080 (PANTHERLAKE) [22:23:05] [PASSED] 0xB081 (PANTHERLAKE) [22:23:05] [PASSED] 0xB082 (PANTHERLAKE) [22:23:05] [PASSED] 0xB083 (PANTHERLAKE) [22:23:05] [PASSED] 0xB084 (PANTHERLAKE) [22:23:05] [PASSED] 0xB085 (PANTHERLAKE) [22:23:05] [PASSED] 0xB086 (PANTHERLAKE) [22:23:05] [PASSED] 0xB087 (PANTHERLAKE) [22:23:05] [PASSED] 0xB08F (PANTHERLAKE) [22:23:05] [PASSED] 0xB090 (PANTHERLAKE) [22:23:05] [PASSED] 0xB0A0 (PANTHERLAKE) [22:23:05] [PASSED] 0xB0B0 (PANTHERLAKE) [22:23:05] [PASSED] 0xFD80 (PANTHERLAKE) [22:23:05] [PASSED] 0xFD81 (PANTHERLAKE) [22:23:05] [PASSED] 0xD740 (NOVALAKE_S) [22:23:05] [PASSED] 0xD741 (NOVALAKE_S) [22:23:05] [PASSED] 0xD742 (NOVALAKE_S) [22:23:05] [PASSED] 0xD743 (NOVALAKE_S) [22:23:05] [PASSED] 0xD745 (NOVALAKE_S) [22:23:05] [PASSED] 0xD74A (NOVALAKE_S) [22:23:05] [PASSED] 0xD74B (NOVALAKE_S) [22:23:05] [PASSED] 0x674C (CRESCENTISLAND) [22:23:05] [PASSED] 0x674D (CRESCENTISLAND) [22:23:05] [PASSED] 0x674E (CRESCENTISLAND) [22:23:05] [PASSED] 0x674F (CRESCENTISLAND) [22:23:05] [PASSED] 0x6750 (CRESCENTISLAND) [22:23:05] [PASSED] 0xD750 (NOVALAKE_P) [22:23:05] [PASSED] 0xD751 (NOVALAKE_P) [22:23:05] [PASSED] 0xD752 (NOVALAKE_P) [22:23:05] [PASSED] 0xD753 (NOVALAKE_P) [22:23:05] [PASSED] 0xD754 (NOVALAKE_P) [22:23:05] [PASSED] 0xD755 (NOVALAKE_P) [22:23:05] [PASSED] 0xD756 (NOVALAKE_P) [22:23:05] [PASSED] 0xD757 (NOVALAKE_P) [22:23:05] [PASSED] 0xD75F (NOVALAKE_P) [22:23:05] =============== [PASSED] check_platform_desc =============== [22:23:05] ===================== [PASSED] xe_pci ====================== [22:23:05] ============= xe_rtp_tables_test (5 subtests) ============== [22:23:05] ================== xe_rtp_table_gt_test =================== [22:23:05] [PASSED] gt_was/14011060649 [22:23:05] [PASSED] gt_was/14011059788 [22:23:05] [PASSED] gt_was/14015795083 [22:23:05] [PASSED] gt_was/16021867713 [22:23:05] [PASSED] gt_was/14019449301 [22:23:05] [PASSED] gt_was/16028005424 [22:23:05] [PASSED] gt_was/14026578760 [22:23:05] [PASSED] gt_was/1409420604 [22:23:05] [PASSED] gt_was/1408615072 [22:23:05] [PASSED] gt_was/22010523718 [22:23:05] [PASSED] gt_was/14011006942 [22:23:05] [PASSED] gt_was/14014830051 [22:23:05] [PASSED] gt_was/18018781329 [22:23:05] [PASSED] gt_was/1509235366 [22:23:05] [PASSED] gt_was/18018781329 [22:23:05] [PASSED] gt_was/16016694945 [22:23:05] [PASSED] gt_was/14018575942 [22:23:05] [PASSED] gt_was/22016670082 [22:23:05] [PASSED] gt_was/22016670082 [22:23:05] [PASSED] gt_was/14017421178 [22:23:05] [PASSED] gt_was/16025250150 [22:23:05] [PASSED] gt_was/14021871409 [22:23:05] [PASSED] gt_was/16021865536 [22:23:05] [PASSED] gt_was/14021486841 [22:23:05] [PASSED] gt_was/14025160223 [22:23:05] [PASSED] gt_was/14026144927, 16029437861, 14026127056 [22:23:05] [PASSED] gt_was/14025635424 [22:23:05] [PASSED] gt_was/16028005424 [22:23:05] ============== [PASSED] xe_rtp_table_gt_test =============== [22:23:05] ================== xe_rtp_table_gt_test =================== [22:23:05] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable [22:23:05] [PASSED] gt_tunings/Tuning: 32B Access Enable [22:23:05] [PASSED] gt_tunings/Tuning: L3 cache [22:23:05] [PASSED] gt_tunings/Tuning: L3 cache - media [22:23:05] [PASSED] gt_tunings/Tuning: Compression Overfetch [22:23:05] [PASSED] gt_tunings/Tuning: Compression Overfetch - media [22:23:05] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 [22:23:05] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media [22:23:05] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only [22:23:05] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media [22:23:05] [PASSED] gt_tunings/Tuning: Stateless compression control [22:23:05] [PASSED] gt_tunings/Tuning: Stateless compression control - media [22:23:05] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache [22:23:05] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media [22:23:05] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB [22:23:05] ============== [PASSED] xe_rtp_table_gt_test =============== [22:23:05] ================== xe_rtp_table_oob_test ================== [22:23:05] [PASSED] oob_was/1607983814 [22:23:05] [PASSED] oob_was/16010904313 [22:23:05] [PASSED] oob_was/18022495364 [22:23:05] [PASSED] oob_was/22012773006 [22:23:05] [PASSED] oob_was/14014475959 [22:23:05] [PASSED] oob_was/22011391025 [22:23:05] [PASSED] oob_was/22012727170 [22:23:05] [PASSED] oob_was/22012727685 [22:23:05] [PASSED] oob_was/22016596838 [22:23:05] [PASSED] oob_was/18020744125 [22:23:05] [PASSED] oob_was/1409600907 [22:23:05] [PASSED] oob_was/22014953428 [22:23:05] [PASSED] oob_was/16017236439 [22:23:05] [PASSED] oob_was/14019821291 [22:23:05] [PASSED] oob_was/14015076503 [22:23:05] [PASSED] oob_was/14018913170 [22:23:05] [PASSED] oob_was/14018094691 [22:23:05] [PASSED] oob_was/18024947630 [22:23:05] [PASSED] oob_was/16022287689 [22:23:05] [PASSED] oob_was/13011645652 [22:23:05] [PASSED] oob_was/14022293748 [22:23:05] [PASSED] oob_was/22019794406 [22:23:05] [PASSED] oob_was/22019338487 [22:23:05] [PASSED] oob_was/16023588340 [22:23:05] [PASSED] oob_was/14019789679 [22:23:05] [PASSED] oob_was/14022866841 [22:23:05] [PASSED] oob_was/16021333562 [22:23:05] [PASSED] oob_was/14016712196 [22:23:05] [PASSED] oob_was/14015568240 [22:23:05] [PASSED] oob_was/18013179988 [22:23:05] [PASSED] oob_was/1508761755 [22:23:05] [PASSED] oob_was/16023105232 [22:23:05] [PASSED] oob_was/16026508708 [22:23:05] [PASSED] oob_was/14020001231 [22:23:05] [PASSED] oob_was/16023683509 [22:23:05] [PASSED] oob_was/14025515070 [22:23:05] [PASSED] oob_was/15015404425_disable [22:23:05] [PASSED] oob_was/16026007364 [22:23:05] [PASSED] oob_was/14020316580 [22:23:05] [PASSED] oob_was/14025883347 [22:23:05] [PASSED] oob_was/16029380221 [22:23:05] [PASSED] oob_was/22022079272 [22:23:05] [PASSED] oob_was/16029897822 [22:23:05] [PASSED] oob_was/14026539277 [22:23:05] [PASSED] oob_was/14027054324 [22:23:05] ============== [PASSED] xe_rtp_table_oob_test ============== [22:23:05] ================ xe_rtp_table_dev_oob_test ================ [22:23:05] [PASSED] device_oob_was/22010954014 [22:23:05] [PASSED] device_oob_was/15015404425 [22:23:05] [PASSED] device_oob_was/22019338487_display [22:23:05] [PASSED] device_oob_was/14022085890 [22:23:05] [PASSED] device_oob_was/14026633728 [22:23:05] [PASSED] device_oob_was/14026746987 [22:23:05] [PASSED] device_oob_was/14026779378 [22:23:05] ============ [PASSED] xe_rtp_table_dev_oob_test ============ [22:23:05] ========== xe_rtp_table_missing_upper_bound_test ========== [22:23:05] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865 [22:23:05] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037 [22:23:05] [PASSED] register_whitelist/1806527549 [22:23:05] [PASSED] register_whitelist/allow_read_ctx_timestamp [22:23:05] [PASSED] register_whitelist/allow_read_queue_timestamp [22:23:05] [PASSED] register_whitelist/16014440446 [22:23:05] [PASSED] register_whitelist/16017236439 [22:23:05] [PASSED] register_whitelist/16020183090 [22:23:05] [PASSED] register_whitelist/14024997852 [22:23:05] [PASSED] register_whitelist/14024997852 [22:23:05] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ====== [22:23:05] =============== [PASSED] xe_rtp_tables_test ================ [22:23:05] =================== xe_rtp (3 subtests) ==================== [22:23:05] =================== xe_rtp_rules_tests ==================== [22:23:05] [PASSED] no [22:23:05] [PASSED] yes [22:23:05] [PASSED] no-and-no [22:23:05] [PASSED] no-and-yes [22:23:05] [PASSED] yes-and-no [22:23:05] [PASSED] yes-and-yes [22:23:05] [PASSED] no-or-no [22:23:05] [PASSED] no-or-yes [22:23:05] [PASSED] yes-or-no [22:23:05] [PASSED] yes-or-yes [22:23:05] [PASSED] no-yes-or-yes-no [22:23:05] [PASSED] no-yes-or-yes-yes [22:23:05] [PASSED] yes-yes-or-no-yes [22:23:05] [PASSED] yes-yes-or-yes-yes [22:23:05] [PASSED] no-no-or-yes-or-no [22:23:05] [PASSED] or [22:23:05] [PASSED] or-yes [22:23:05] [PASSED] or-no [22:23:05] [PASSED] yes-or [22:23:05] [PASSED] no-or [22:23:05] [PASSED] no-or-or-yes [22:23:05] [PASSED] yes-or-or-no [22:23:05] [PASSED] no-or-or-no [22:23:05] [PASSED] missing-context-engine-class [22:23:05] [PASSED] missing-context-engine-class-or-yes [22:23:05] [PASSED] missing-context-engine-class-or-or-yes [22:23:05] =============== [PASSED] xe_rtp_rules_tests ================ [22:23:05] =============== xe_rtp_process_to_sr_tests ================ [22:23:05] [PASSED] coalesce-same-reg [22:23:05] [PASSED] coalesce-same-reg-literal-and-func [22:23:05] [PASSED] no-match-no-add [22:23:05] [PASSED] two-regs-two-entries [22:23:05] [PASSED] clr-one-set-other [22:23:05] [PASSED] set-field [22:23:05] [PASSED] conflict-duplicate [22:23:05] [PASSED] conflict-not-disjoint [22:23:05] [PASSED] conflict-not-disjoint-literal-and-func [22:23:05] [PASSED] conflict-reg-type [22:23:05] [PASSED] bad-mcr-reg-forced-to-regular [22:23:05] [PASSED] bad-regular-reg-forced-to-mcr [22:23:05] =========== [PASSED] xe_rtp_process_to_sr_tests ============ [22:23:05] ================== xe_rtp_process_tests =================== [22:23:05] [PASSED] active1 [22:23:05] [PASSED] active2 [22:23:05] [PASSED] active-inactive [22:23:05] [PASSED] inactive-active [22:23:05] [PASSED] inactive-active-inactive [22:23:05] [PASSED] inactive-inactive-inactive [22:23:05] ============== [PASSED] xe_rtp_process_tests =============== [22:23:05] ===================== [PASSED] xe_rtp ====================== [22:23:05] ==================== xe_wa (1 subtest) ===================== [22:23:05] ======================== xe_wa_gt ========================= [22:23:05] [PASSED] TIGERLAKE B0 [22:23:05] [PASSED] DG1 A0 [22:23:05] [PASSED] DG1 B0 [22:23:05] [PASSED] ALDERLAKE_S A0 [22:23:05] [PASSED] ALDERLAKE_S B0 [22:23:05] [PASSED] ALDERLAKE_S C0 [22:23:05] [PASSED] ALDERLAKE_S D0 [22:23:05] [PASSED] ALDERLAKE_P A0 [22:23:05] [PASSED] ALDERLAKE_P B0 [22:23:05] [PASSED] ALDERLAKE_P C0 [22:23:05] [PASSED] ALDERLAKE_S RPLS D0 [22:23:05] [PASSED] ALDERLAKE_P RPLU E0 [22:23:05] [PASSED] DG2 G10 C0 [22:23:05] [PASSED] DG2 G11 B1 [22:23:05] [PASSED] DG2 G12 A1 [22:23:05] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0 [22:23:05] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0 [22:23:05] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0 [22:23:05] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0 [22:23:05] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0 [22:23:05] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1 [22:23:05] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0 [22:23:05] ==================== [PASSED] xe_wa_gt ===================== [22:23:05] ====================== [PASSED] xe_wa ====================== [22:23:05] ============================================================ [22:23:05] Testing complete. Ran 742 tests: passed: 724, skipped: 18 [22:23:06] Elapsed time: 37.603s total, 4.434s configuring, 32.503s building, 0.633s running + /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig [22:23:06] Configuring KUnit Kernel ... Regenerating .config ... Populating config with: $ make ARCH=um O=.kunit olddefconfig [22:23:07] Building KUnit Kernel ... Populating config with: $ make ARCH=um O=.kunit olddefconfig Building with: $ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48 [22:23:33] Starting KUnit Kernel (1/1)... [22:23:33] ============================================================ Running tests with: $ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt [22:23:33] ============ drm_test_pick_cmdline (2 subtests) ============ [22:23:33] [PASSED] drm_test_pick_cmdline_res_1920_1080_60 [22:23:33] =============== drm_test_pick_cmdline_named =============== [22:23:33] [PASSED] NTSC [22:23:33] [PASSED] NTSC-J [22:23:33] [PASSED] PAL [22:23:33] [PASSED] PAL-M [22:23:33] =========== [PASSED] drm_test_pick_cmdline_named =========== [22:23:33] ============== [PASSED] drm_test_pick_cmdline ============== [22:23:33] == drm_test_atomic_get_connector_for_encoder (1 subtest) === [22:23:33] [PASSED] drm_test_drm_atomic_get_connector_for_encoder [22:23:33] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ==== [22:23:33] =========== drm_validate_clone_mode (2 subtests) =========== [22:23:33] ============== drm_test_check_in_clone_mode =============== [22:23:33] [PASSED] in_clone_mode [22:23:33] [PASSED] not_in_clone_mode [22:23:33] ========== [PASSED] drm_test_check_in_clone_mode =========== [22:23:33] =============== drm_test_check_valid_clones =============== [22:23:33] [PASSED] not_in_clone_mode [22:23:33] [PASSED] valid_clone [22:23:33] [PASSED] invalid_clone [22:23:33] =========== [PASSED] drm_test_check_valid_clones =========== [22:23:33] ============= [PASSED] drm_validate_clone_mode ============= [22:23:33] ============= drm_validate_modeset (1 subtest) ============= [22:23:33] [PASSED] drm_test_check_connector_changed_modeset [22:23:33] ============== [PASSED] drm_validate_modeset =============== [22:23:33] ====== drm_test_bridge_get_current_state (1 subtest) ======= [22:23:33] [PASSED] drm_test_drm_bridge_get_current_state_atomic [22:23:33] ======== [PASSED] drm_test_bridge_get_current_state ======== [22:23:33] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ====== [22:23:33] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic [22:23:33] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled [22:23:33] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts [22:23:33] ======== [PASSED] drm_test_bridge_helper_reset_crtc ======== [22:23:33] ============== drm_bridge_alloc (2 subtests) =============== [22:23:33] [PASSED] drm_test_drm_bridge_alloc_basic [22:23:33] [PASSED] drm_test_drm_bridge_alloc_get_put [22:23:33] ================ [PASSED] drm_bridge_alloc ================= [22:23:33] ============= drm_bridge_bus_fmt (5 subtests) ============== [22:23:33] [PASSED] drm_test_bridge_rgb_yuv_rgb [22:23:33] [PASSED] drm_test_bridge_must_convert_to_yuv444 [22:23:33] [PASSED] drm_test_bridge_hdmi_auto_rgb [22:23:33] [PASSED] drm_test_bridge_auto_first [22:23:33] [PASSED] drm_test_bridge_rgb_yuv_no_path [22:23:33] =============== [PASSED] drm_bridge_bus_fmt ================ [22:23:33] ============= drm_cmdline_parser (40 subtests) ============= [22:23:33] [PASSED] drm_test_cmdline_force_d_only [22:23:33] [PASSED] drm_test_cmdline_force_D_only_dvi [22:23:33] [PASSED] drm_test_cmdline_force_D_only_hdmi [22:23:33] [PASSED] drm_test_cmdline_force_D_only_not_digital [22:23:33] [PASSED] drm_test_cmdline_force_e_only [22:23:33] [PASSED] drm_test_cmdline_res [22:23:33] [PASSED] drm_test_cmdline_res_vesa [22:23:33] [PASSED] drm_test_cmdline_res_vesa_rblank [22:23:33] [PASSED] drm_test_cmdline_res_rblank [22:23:33] [PASSED] drm_test_cmdline_res_bpp [22:23:33] [PASSED] drm_test_cmdline_res_refresh [22:23:33] [PASSED] drm_test_cmdline_res_bpp_refresh [22:23:33] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced [22:23:33] [PASSED] drm_test_cmdline_res_bpp_refresh_margins [22:23:33] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off [22:23:33] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on [22:23:33] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog [22:23:33] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital [22:23:33] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on [22:23:33] [PASSED] drm_test_cmdline_res_margins_force_on [22:23:33] [PASSED] drm_test_cmdline_res_vesa_margins [22:23:33] [PASSED] drm_test_cmdline_name [22:23:33] [PASSED] drm_test_cmdline_name_bpp [22:23:33] [PASSED] drm_test_cmdline_name_option [22:23:33] [PASSED] drm_test_cmdline_name_bpp_option [22:23:33] [PASSED] drm_test_cmdline_rotate_0 [22:23:33] [PASSED] drm_test_cmdline_rotate_90 [22:23:33] [PASSED] drm_test_cmdline_rotate_180 [22:23:33] [PASSED] drm_test_cmdline_rotate_270 [22:23:33] [PASSED] drm_test_cmdline_hmirror [22:23:33] [PASSED] drm_test_cmdline_vmirror [22:23:33] [PASSED] drm_test_cmdline_margin_options [22:23:33] [PASSED] drm_test_cmdline_multiple_options [22:23:33] [PASSED] drm_test_cmdline_bpp_extra_and_option [22:23:33] [PASSED] drm_test_cmdline_extra_and_option [22:23:33] [PASSED] drm_test_cmdline_freestanding_options [22:23:33] [PASSED] drm_test_cmdline_freestanding_force_e_and_options [22:23:33] [PASSED] drm_test_cmdline_panel_orientation [22:23:33] ================ drm_test_cmdline_invalid ================= [22:23:33] [PASSED] margin_only [22:23:33] [PASSED] interlace_only [22:23:33] [PASSED] res_missing_x [22:23:33] [PASSED] res_missing_y [22:23:33] [PASSED] res_bad_y [22:23:33] [PASSED] res_missing_y_bpp [22:23:33] [PASSED] res_bad_bpp [22:23:33] [PASSED] res_bad_refresh [22:23:33] [PASSED] res_bpp_refresh_force_on_off [22:23:33] [PASSED] res_invalid_mode [22:23:33] [PASSED] res_bpp_wrong_place_mode [22:23:33] [PASSED] name_bpp_refresh [22:23:33] [PASSED] name_refresh [22:23:33] [PASSED] name_refresh_wrong_mode [22:23:33] [PASSED] name_refresh_invalid_mode [22:23:33] [PASSED] rotate_multiple [22:23:33] [PASSED] rotate_invalid_val [22:23:33] [PASSED] rotate_truncated [22:23:33] [PASSED] invalid_option [22:23:33] [PASSED] invalid_tv_option [22:23:33] [PASSED] truncated_tv_option [22:23:33] ============ [PASSED] drm_test_cmdline_invalid ============= [22:23:33] =============== drm_test_cmdline_tv_options =============== [22:23:33] [PASSED] NTSC [22:23:33] [PASSED] NTSC_443 [22:23:33] [PASSED] NTSC_J [22:23:33] [PASSED] PAL [22:23:33] [PASSED] PAL_M [22:23:33] [PASSED] PAL_N [22:23:33] [PASSED] SECAM [22:23:33] [PASSED] MONO_525 [22:23:33] [PASSED] MONO_625 [22:23:33] =========== [PASSED] drm_test_cmdline_tv_options =========== [22:23:33] =============== [PASSED] drm_cmdline_parser ================ [22:23:33] ========== drmm_connector_hdmi_init (20 subtests) ========== [22:23:33] [PASSED] drm_test_connector_hdmi_init_valid [22:23:33] [PASSED] drm_test_connector_hdmi_init_bpc_8 [22:23:33] [PASSED] drm_test_connector_hdmi_init_bpc_10 [22:23:33] [PASSED] drm_test_connector_hdmi_init_bpc_12 [22:23:33] [PASSED] drm_test_connector_hdmi_init_bpc_invalid [22:23:33] [PASSED] drm_test_connector_hdmi_init_bpc_null [22:23:33] [PASSED] drm_test_connector_hdmi_init_formats_empty [22:23:33] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb [22:23:33] === drm_test_connector_hdmi_init_formats_yuv420_allowed === [22:23:33] [PASSED] supported_formats=0x9 yuv420_allowed=1 [22:23:33] [PASSED] supported_formats=0x9 yuv420_allowed=0 [22:23:33] [PASSED] supported_formats=0x5 yuv420_allowed=1 [22:23:33] [PASSED] supported_formats=0x5 yuv420_allowed=0 [22:23:33] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed === [22:23:33] [PASSED] drm_test_connector_hdmi_init_null_ddc [22:23:33] [PASSED] drm_test_connector_hdmi_init_null_product [22:23:33] [PASSED] drm_test_connector_hdmi_init_null_vendor [22:23:33] [PASSED] drm_test_connector_hdmi_init_product_length_exact [22:23:33] [PASSED] drm_test_connector_hdmi_init_product_length_too_long [22:23:33] [PASSED] drm_test_connector_hdmi_init_product_valid [22:23:33] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact [22:23:33] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long [22:23:33] [PASSED] drm_test_connector_hdmi_init_vendor_valid [22:23:33] ========= drm_test_connector_hdmi_init_type_valid ========= [22:23:33] [PASSED] HDMI-A [22:23:33] [PASSED] HDMI-B [22:23:33] ===== [PASSED] drm_test_connector_hdmi_init_type_valid ===== [22:23:33] ======== drm_test_connector_hdmi_init_type_invalid ======== [22:23:33] [PASSED] Unknown [22:23:33] [PASSED] VGA [22:23:33] [PASSED] DVI-I [22:23:33] [PASSED] DVI-D [22:23:33] [PASSED] DVI-A [22:23:33] [PASSED] Composite [22:23:33] [PASSED] SVIDEO [22:23:33] [PASSED] LVDS [22:23:33] [PASSED] Component [22:23:33] [PASSED] DIN [22:23:33] [PASSED] DP [22:23:33] [PASSED] TV [22:23:33] [PASSED] eDP [22:23:33] [PASSED] Virtual [22:23:33] [PASSED] DSI [22:23:33] [PASSED] DPI [22:23:33] [PASSED] Writeback [22:23:33] [PASSED] SPI [22:23:33] [PASSED] USB [22:23:33] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ==== [22:23:33] ============ [PASSED] drmm_connector_hdmi_init ============= [22:23:33] ============= drmm_connector_init (3 subtests) ============= [22:23:33] [PASSED] drm_test_drmm_connector_init [22:23:33] [PASSED] drm_test_drmm_connector_init_null_ddc [22:23:33] ========= drm_test_drmm_connector_init_type_valid ========= [22:23:33] [PASSED] Unknown [22:23:33] [PASSED] VGA [22:23:33] [PASSED] DVI-I [22:23:33] [PASSED] DVI-D [22:23:33] [PASSED] DVI-A [22:23:33] [PASSED] Composite [22:23:33] [PASSED] SVIDEO [22:23:33] [PASSED] LVDS [22:23:33] [PASSED] Component [22:23:33] [PASSED] DIN [22:23:33] [PASSED] DP [22:23:33] [PASSED] HDMI-A [22:23:33] [PASSED] HDMI-B [22:23:33] [PASSED] TV [22:23:33] [PASSED] eDP [22:23:33] [PASSED] Virtual [22:23:33] [PASSED] DSI [22:23:33] [PASSED] DPI [22:23:33] [PASSED] Writeback [22:23:33] [PASSED] SPI [22:23:33] [PASSED] USB [22:23:33] ===== [PASSED] drm_test_drmm_connector_init_type_valid ===== [22:23:33] =============== [PASSED] drmm_connector_init =============== [22:23:33] ========= drm_connector_dynamic_init (6 subtests) ========== [22:23:33] [PASSED] drm_test_drm_connector_dynamic_init [22:23:33] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc [22:23:33] [PASSED] drm_test_drm_connector_dynamic_init_not_added [22:23:33] [PASSED] drm_test_drm_connector_dynamic_init_properties [22:23:33] ===== drm_test_drm_connector_dynamic_init_type_valid ====== [22:23:33] [PASSED] Unknown [22:23:33] [PASSED] VGA [22:23:33] [PASSED] DVI-I [22:23:33] [PASSED] DVI-D [22:23:33] [PASSED] DVI-A [22:23:33] [PASSED] Composite [22:23:33] [PASSED] SVIDEO [22:23:33] [PASSED] LVDS [22:23:33] [PASSED] Component [22:23:33] [PASSED] DIN [22:23:33] [PASSED] DP [22:23:33] [PASSED] HDMI-A [22:23:33] [PASSED] HDMI-B [22:23:33] [PASSED] TV [22:23:33] [PASSED] eDP [22:23:33] [PASSED] Virtual [22:23:33] [PASSED] DSI [22:23:33] [PASSED] DPI [22:23:33] [PASSED] Writeback [22:23:33] [PASSED] SPI [22:23:33] [PASSED] USB [22:23:33] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid == [22:23:33] ======== drm_test_drm_connector_dynamic_init_name ========= [22:23:33] [PASSED] Unknown [22:23:33] [PASSED] VGA [22:23:33] [PASSED] DVI-I [22:23:33] [PASSED] DVI-D [22:23:33] [PASSED] DVI-A [22:23:33] [PASSED] Composite [22:23:33] [PASSED] SVIDEO [22:23:33] [PASSED] LVDS [22:23:33] [PASSED] Component [22:23:33] [PASSED] DIN [22:23:33] [PASSED] DP [22:23:33] [PASSED] HDMI-A [22:23:33] [PASSED] HDMI-B [22:23:33] [PASSED] TV [22:23:33] [PASSED] eDP [22:23:33] [PASSED] Virtual [22:23:33] [PASSED] DSI [22:23:33] [PASSED] DPI [22:23:33] [PASSED] Writeback [22:23:33] [PASSED] SPI [22:23:33] [PASSED] USB [22:23:33] ==== [PASSED] drm_test_drm_connector_dynamic_init_name ===== [22:23:33] =========== [PASSED] drm_connector_dynamic_init ============ [22:23:33] ==== drm_connector_dynamic_register_early (4 subtests) ===== [22:23:33] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list [22:23:33] [PASSED] drm_test_drm_connector_dynamic_register_early_defer [22:23:33] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init [22:23:33] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object [22:23:33] ====== [PASSED] drm_connector_dynamic_register_early ======= [22:23:33] ======= drm_connector_dynamic_register (7 subtests) ======== [22:23:33] [PASSED] drm_test_drm_connector_dynamic_register_on_list [22:23:33] [PASSED] drm_test_drm_connector_dynamic_register_no_defer [22:23:33] [PASSED] drm_test_drm_connector_dynamic_register_no_init [22:23:33] [PASSED] drm_test_drm_connector_dynamic_register_mode_object [22:23:33] [PASSED] drm_test_drm_connector_dynamic_register_sysfs [22:23:33] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name [22:23:33] [PASSED] drm_test_drm_connector_dynamic_register_debugfs [22:23:33] ========= [PASSED] drm_connector_dynamic_register ========== [22:23:33] = drm_connector_attach_broadcast_rgb_property (2 subtests) = [22:23:33] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property [22:23:33] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector [22:23:33] === [PASSED] drm_connector_attach_broadcast_rgb_property === [22:23:33] ========== drm_get_tv_mode_from_name (2 subtests) ========== [22:23:33] ========== drm_test_get_tv_mode_from_name_valid =========== [22:23:33] [PASSED] NTSC [22:23:33] [PASSED] NTSC-443 [22:23:33] [PASSED] NTSC-J [22:23:33] [PASSED] PAL [22:23:33] [PASSED] PAL-M [22:23:33] [PASSED] PAL-N [22:23:33] [PASSED] SECAM [22:23:33] [PASSED] Mono [22:23:33] ====== [PASSED] drm_test_get_tv_mode_from_name_valid ======= [22:23:33] [PASSED] drm_test_get_tv_mode_from_name_truncated [22:23:33] ============ [PASSED] drm_get_tv_mode_from_name ============ [22:23:33] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) = [22:23:33] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb [22:23:33] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc [22:23:33] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1 [22:23:33] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc [22:23:33] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1 [22:23:33] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double [22:23:33] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid = [22:23:33] [PASSED] VIC 96 [22:23:33] [PASSED] VIC 97 [22:23:33] [PASSED] VIC 101 [22:23:33] [PASSED] VIC 102 [22:23:33] [PASSED] VIC 106 [22:23:33] [PASSED] VIC 107 [22:23:33] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid === [22:23:33] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc [22:23:33] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc [22:23:33] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc [22:23:33] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc [22:23:33] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc [22:23:33] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ==== [22:23:33] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) == [22:23:33] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ==== [22:23:33] [PASSED] Automatic [22:23:33] [PASSED] Full [22:23:33] [PASSED] Limited 16:235 [22:23:33] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name === [22:23:33] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid [22:23:33] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ==== [22:23:33] == drm_hdmi_connector_get_output_format_name (2 subtests) == [22:23:33] === drm_test_drm_hdmi_connector_get_output_format_name ==== [22:23:33] [PASSED] RGB [22:23:33] [PASSED] YUV 4:2:0 [22:23:33] [PASSED] YUV 4:2:2 [22:23:33] [PASSED] YUV 4:4:4 [22:23:33] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name === [22:23:33] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid [22:23:33] ==== [PASSED] drm_hdmi_connector_get_output_format_name ==== [22:23:33] ============= drm_damage_helper (21 subtests) ============== [22:23:33] [PASSED] drm_test_damage_iter_no_damage [22:23:33] [PASSED] drm_test_damage_iter_no_damage_fractional_src [22:23:33] [PASSED] drm_test_damage_iter_no_damage_src_moved [22:23:33] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved [22:23:33] [PASSED] drm_test_damage_iter_no_damage_not_visible [22:23:33] [PASSED] drm_test_damage_iter_no_damage_no_crtc [22:23:33] [PASSED] drm_test_damage_iter_no_damage_no_fb [22:23:33] [PASSED] drm_test_damage_iter_simple_damage [22:23:33] [PASSED] drm_test_damage_iter_single_damage [22:23:33] [PASSED] drm_test_damage_iter_single_damage_intersect_src [22:23:33] [PASSED] drm_test_damage_iter_single_damage_outside_src [22:23:33] [PASSED] drm_test_damage_iter_single_damage_fractional_src [22:23:33] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src [22:23:33] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src [22:23:33] [PASSED] drm_test_damage_iter_single_damage_src_moved [22:23:33] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved [22:23:33] [PASSED] drm_test_damage_iter_damage [22:23:33] [PASSED] drm_test_damage_iter_damage_one_intersect [22:23:33] [PASSED] drm_test_damage_iter_damage_one_outside [22:23:33] [PASSED] drm_test_damage_iter_damage_src_moved [22:23:33] [PASSED] drm_test_damage_iter_damage_not_visible [22:23:33] ================ [PASSED] drm_damage_helper ================ [22:23:33] ============== drm_dp_mst_helper (3 subtests) ============== [22:23:33] ============== drm_test_dp_mst_calc_pbn_mode ============== [22:23:33] [PASSED] Clock 154000 BPP 30 DSC disabled [22:23:33] [PASSED] Clock 234000 BPP 30 DSC disabled [22:23:33] [PASSED] Clock 297000 BPP 24 DSC disabled [22:23:33] [PASSED] Clock 332880 BPP 24 DSC enabled [22:23:33] [PASSED] Clock 324540 BPP 24 DSC enabled [22:23:33] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ========== [22:23:33] ============== drm_test_dp_mst_calc_pbn_div =============== [22:23:33] [PASSED] Link rate 2000000 lane count 4 [22:23:33] [PASSED] Link rate 2000000 lane count 2 [22:23:33] [PASSED] Link rate 2000000 lane count 1 [22:23:33] [PASSED] Link rate 1350000 lane count 4 [22:23:33] [PASSED] Link rate 1350000 lane count 2 [22:23:33] [PASSED] Link rate 1350000 lane count 1 [22:23:33] [PASSED] Link rate 1000000 lane count 4 [22:23:33] [PASSED] Link rate 1000000 lane count 2 [22:23:33] [PASSED] Link rate 1000000 lane count 1 [22:23:33] [PASSED] Link rate 810000 lane count 4 [22:23:33] [PASSED] Link rate 810000 lane count 2 [22:23:33] [PASSED] Link rate 810000 lane count 1 [22:23:33] [PASSED] Link rate 540000 lane count 4 [22:23:33] [PASSED] Link rate 540000 lane count 2 [22:23:33] [PASSED] Link rate 540000 lane count 1 [22:23:33] [PASSED] Link rate 270000 lane count 4 [22:23:33] [PASSED] Link rate 270000 lane count 2 [22:23:33] [PASSED] Link rate 270000 lane count 1 [22:23:33] [PASSED] Link rate 162000 lane count 4 [22:23:33] [PASSED] Link rate 162000 lane count 2 [22:23:33] [PASSED] Link rate 162000 lane count 1 [22:23:33] ========== [PASSED] drm_test_dp_mst_calc_pbn_div =========== [22:23:33] ========= drm_test_dp_mst_sideband_msg_req_decode ========= [22:23:33] [PASSED] DP_ENUM_PATH_RESOURCES with port number [22:23:33] [PASSED] DP_POWER_UP_PHY with port number [22:23:33] [PASSED] DP_POWER_DOWN_PHY with port number [22:23:33] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks [22:23:33] [PASSED] DP_ALLOCATE_PAYLOAD with port number [22:23:33] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI [22:23:33] [PASSED] DP_ALLOCATE_PAYLOAD with PBN [22:23:33] [PASSED] DP_QUERY_PAYLOAD with port number [22:23:33] [PASSED] DP_QUERY_PAYLOAD with VCPI [22:23:33] [PASSED] DP_REMOTE_DPCD_READ with port number [22:23:33] [PASSED] DP_REMOTE_DPCD_READ with DPCD address [22:23:33] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes [22:23:33] [PASSED] DP_REMOTE_DPCD_WRITE with port number [22:23:33] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address [22:23:33] [PASSED] DP_REMOTE_DPCD_WRITE with data array [22:23:33] [PASSED] DP_REMOTE_I2C_READ with port number [22:23:33] [PASSED] DP_REMOTE_I2C_READ with I2C device ID [22:23:33] [PASSED] DP_REMOTE_I2C_READ with transactions array [22:23:33] [PASSED] DP_REMOTE_I2C_WRITE with port number [22:23:33] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID [22:23:33] [PASSED] DP_REMOTE_I2C_WRITE with data array [22:23:33] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID [22:23:33] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID [22:23:33] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event [22:23:33] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event [22:23:33] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior [22:23:33] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior [22:23:33] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode ===== [22:23:33] ================ [PASSED] drm_dp_mst_helper ================ [22:23:33] ================== drm_exec (7 subtests) =================== [22:23:33] [PASSED] sanitycheck [22:23:33] [PASSED] test_lock [22:23:33] [PASSED] test_lock_unlock [22:23:33] [PASSED] test_duplicates [22:23:33] [PASSED] test_prepare [22:23:33] [PASSED] test_prepare_array [22:23:33] [PASSED] test_multiple_loops [22:23:33] ==================== [PASSED] drm_exec ===================== [22:23:33] =========== drm_format_helper_test (17 subtests) =========== [22:23:33] ============== drm_test_fb_xrgb8888_to_gray8 ============== [22:23:33] [PASSED] single_pixel_source_buffer [22:23:33] [PASSED] single_pixel_clip_rectangle [22:23:33] [PASSED] well_known_colors [22:23:33] [PASSED] destination_pitch [22:23:33] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ========== [22:23:33] ============= drm_test_fb_xrgb8888_to_rgb332 ============== [22:23:33] [PASSED] single_pixel_source_buffer [22:23:33] [PASSED] single_pixel_clip_rectangle [22:23:33] [PASSED] well_known_colors [22:23:33] [PASSED] destination_pitch [22:23:33] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ========== [22:23:33] ============= drm_test_fb_xrgb8888_to_rgb565 ============== [22:23:33] [PASSED] single_pixel_source_buffer [22:23:33] [PASSED] single_pixel_clip_rectangle [22:23:33] [PASSED] well_known_colors [22:23:33] [PASSED] destination_pitch [22:23:33] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ========== [22:23:33] ============ drm_test_fb_xrgb8888_to_xrgb1555 ============= [22:23:33] [PASSED] single_pixel_source_buffer [22:23:33] [PASSED] single_pixel_clip_rectangle [22:23:33] [PASSED] well_known_colors [22:23:33] [PASSED] destination_pitch [22:23:33] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 ========= [22:23:33] ============ drm_test_fb_xrgb8888_to_argb1555 ============= [22:23:33] [PASSED] single_pixel_source_buffer [22:23:33] [PASSED] single_pixel_clip_rectangle [22:23:33] [PASSED] well_known_colors [22:23:33] [PASSED] destination_pitch [22:23:33] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 ========= [22:23:33] ============ drm_test_fb_xrgb8888_to_rgba5551 ============= [22:23:33] [PASSED] single_pixel_source_buffer [22:23:33] [PASSED] single_pixel_clip_rectangle [22:23:33] [PASSED] well_known_colors [22:23:33] [PASSED] destination_pitch [22:23:33] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 ========= [22:23:33] ============= drm_test_fb_xrgb8888_to_rgb888 ============== [22:23:33] [PASSED] single_pixel_source_buffer [22:23:33] [PASSED] single_pixel_clip_rectangle [22:23:33] [PASSED] well_known_colors [22:23:33] [PASSED] destination_pitch [22:23:33] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ========== [22:23:33] ============= drm_test_fb_xrgb8888_to_bgr888 ============== [22:23:33] [PASSED] single_pixel_source_buffer [22:23:33] [PASSED] single_pixel_clip_rectangle [22:23:33] [PASSED] well_known_colors [22:23:33] [PASSED] destination_pitch [22:23:33] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ========== [22:23:33] ============ drm_test_fb_xrgb8888_to_argb8888 ============= [22:23:33] [PASSED] single_pixel_source_buffer [22:23:33] [PASSED] single_pixel_clip_rectangle [22:23:33] [PASSED] well_known_colors [22:23:33] [PASSED] destination_pitch [22:23:33] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 ========= [22:23:33] =========== drm_test_fb_xrgb8888_to_xrgb2101010 =========== [22:23:33] [PASSED] single_pixel_source_buffer [22:23:33] [PASSED] single_pixel_clip_rectangle [22:23:33] [PASSED] well_known_colors [22:23:33] [PASSED] destination_pitch [22:23:33] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 ======= [22:23:33] =========== drm_test_fb_xrgb8888_to_argb2101010 =========== [22:23:33] [PASSED] single_pixel_source_buffer [22:23:33] [PASSED] single_pixel_clip_rectangle [22:23:33] [PASSED] well_known_colors [22:23:33] [PASSED] destination_pitch [22:23:33] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 ======= [22:23:33] ============== drm_test_fb_xrgb8888_to_mono =============== [22:23:33] [PASSED] single_pixel_source_buffer [22:23:33] [PASSED] single_pixel_clip_rectangle [22:23:33] [PASSED] well_known_colors [22:23:33] [PASSED] destination_pitch [22:23:33] ========== [PASSED] drm_test_fb_xrgb8888_to_mono =========== [22:23:33] ==================== drm_test_fb_swab ===================== [22:23:33] [PASSED] single_pixel_source_buffer [22:23:33] [PASSED] single_pixel_clip_rectangle [22:23:33] [PASSED] well_known_colors [22:23:33] [PASSED] destination_pitch [22:23:33] ================ [PASSED] drm_test_fb_swab ================= [22:23:33] ============ drm_test_fb_xrgb8888_to_xbgr8888 ============= [22:23:33] [PASSED] single_pixel_source_buffer [22:23:33] [PASSED] single_pixel_clip_rectangle [22:23:33] [PASSED] well_known_colors [22:23:33] [PASSED] destination_pitch [22:23:33] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 ========= [22:23:33] ============ drm_test_fb_xrgb8888_to_abgr8888 ============= [22:23:33] [PASSED] single_pixel_source_buffer [22:23:33] [PASSED] single_pixel_clip_rectangle [22:23:33] [PASSED] well_known_colors [22:23:33] [PASSED] destination_pitch [22:23:33] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 ========= [22:23:33] ================= drm_test_fb_clip_offset ================= [22:23:33] [PASSED] pass through [22:23:33] [PASSED] horizontal offset [22:23:33] [PASSED] vertical offset [22:23:33] [PASSED] horizontal and vertical offset [22:23:33] [PASSED] horizontal offset (custom pitch) [22:23:33] [PASSED] vertical offset (custom pitch) [22:23:33] [PASSED] horizontal and vertical offset (custom pitch) [22:23:33] ============= [PASSED] drm_test_fb_clip_offset ============= [22:23:33] =================== drm_test_fb_memcpy ==================== [22:23:33] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258) [22:23:33] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258) [22:23:33] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559) [22:23:33] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258) [22:23:33] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258) [22:23:33] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559) [22:23:33] [PASSED] well_known_colors: XB24 little-endian (0x34324258) [22:23:33] [PASSED] well_known_colors: XRA8 little-endian (0x38415258) [22:23:33] [PASSED] well_known_colors: YU24 little-endian (0x34325559) [22:23:33] [PASSED] destination_pitch: XB24 little-endian (0x34324258) [22:23:33] [PASSED] destination_pitch: XRA8 little-endian (0x38415258) [22:23:33] [PASSED] destination_pitch: YU24 little-endian (0x34325559) [22:23:33] =============== [PASSED] drm_test_fb_memcpy ================ [22:23:33] ============= [PASSED] drm_format_helper_test ============== [22:23:33] ================= drm_format (18 subtests) ================= [22:23:33] [PASSED] drm_test_format_block_width_invalid [22:23:33] [PASSED] drm_test_format_block_width_one_plane [22:23:33] [PASSED] drm_test_format_block_width_two_plane [22:23:33] [PASSED] drm_test_format_block_width_three_plane [22:23:33] [PASSED] drm_test_format_block_width_tiled [22:23:33] [PASSED] drm_test_format_block_height_invalid [22:23:33] [PASSED] drm_test_format_block_height_one_plane [22:23:33] [PASSED] drm_test_format_block_height_two_plane [22:23:33] [PASSED] drm_test_format_block_height_three_plane [22:23:33] [PASSED] drm_test_format_block_height_tiled [22:23:33] [PASSED] drm_test_format_min_pitch_invalid [22:23:33] [PASSED] drm_test_format_min_pitch_one_plane_8bpp [22:23:33] [PASSED] drm_test_format_min_pitch_one_plane_16bpp [22:23:33] [PASSED] drm_test_format_min_pitch_one_plane_24bpp [22:23:33] [PASSED] drm_test_format_min_pitch_one_plane_32bpp [22:23:33] [PASSED] drm_test_format_min_pitch_two_plane [22:23:33] [PASSED] drm_test_format_min_pitch_three_plane_8bpp [22:23:33] [PASSED] drm_test_format_min_pitch_tiled [22:23:33] =================== [PASSED] drm_format ==================== [22:23:33] ============== drm_framebuffer (10 subtests) =============== [22:23:33] ========== drm_test_framebuffer_check_src_coords ========== [22:23:33] [PASSED] Success: source fits into fb [22:23:33] [PASSED] Fail: overflowing fb with x-axis coordinate [22:23:33] [PASSED] Fail: overflowing fb with y-axis coordinate [22:23:33] [PASSED] Fail: overflowing fb with source width [22:23:33] [PASSED] Fail: overflowing fb with source height [22:23:33] ====== [PASSED] drm_test_framebuffer_check_src_coords ====== [22:23:33] [PASSED] drm_test_framebuffer_cleanup [22:23:33] =============== drm_test_framebuffer_create =============== [22:23:33] [PASSED] ABGR8888 normal sizes [22:23:33] [PASSED] ABGR8888 max sizes [22:23:33] [PASSED] ABGR8888 pitch greater than min required [22:23:33] [PASSED] ABGR8888 pitch less than min required [22:23:33] [PASSED] ABGR8888 Invalid width [22:23:33] [PASSED] ABGR8888 Invalid buffer handle [22:23:33] [PASSED] No pixel format [22:23:33] [PASSED] ABGR8888 Width 0 [22:23:33] [PASSED] ABGR8888 Height 0 [22:23:33] [PASSED] ABGR8888 Out of bound height * pitch combination [22:23:33] [PASSED] ABGR8888 Large buffer offset [22:23:33] [PASSED] ABGR8888 Buffer offset for inexistent plane [22:23:33] [PASSED] ABGR8888 Invalid flag [22:23:33] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers [22:23:33] [PASSED] ABGR8888 Valid buffer modifier [22:23:33] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE) [22:23:33] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS [22:23:33] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS [22:23:33] [PASSED] NV12 Normal sizes [22:23:33] [PASSED] NV12 Max sizes [22:23:33] [PASSED] NV12 Invalid pitch [22:23:33] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag [22:23:33] [PASSED] NV12 different modifier per-plane [22:23:33] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE [22:23:33] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS [22:23:33] [PASSED] NV12 Modifier for inexistent plane [22:23:33] [PASSED] NV12 Handle for inexistent plane [22:23:33] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS [22:23:33] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier [22:23:33] [PASSED] YVU420 Normal sizes [22:23:33] [PASSED] YVU420 Max sizes [22:23:33] [PASSED] YVU420 Invalid pitch [22:23:33] [PASSED] YVU420 Different pitches [22:23:33] [PASSED] YVU420 Different buffer offsets/pitches [22:23:33] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS [22:23:33] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS [22:23:33] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS [22:23:33] [PASSED] YVU420 Valid modifier [22:23:33] [PASSED] YVU420 Different modifiers per plane [22:23:33] [PASSED] YVU420 Modifier for inexistent plane [22:23:33] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR) [22:23:33] [PASSED] X0L2 Normal sizes [22:23:33] [PASSED] X0L2 Max sizes [22:23:33] [PASSED] X0L2 Invalid pitch [22:23:33] [PASSED] X0L2 Pitch greater than minimum required [22:23:33] [PASSED] X0L2 Handle for inexistent plane [22:23:33] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set [22:23:33] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set [22:23:33] [PASSED] X0L2 Valid modifier [22:23:33] [PASSED] X0L2 Modifier for inexistent plane [22:23:33] =========== [PASSED] drm_test_framebuffer_create =========== [22:23:33] [PASSED] drm_test_framebuffer_free [22:23:33] [PASSED] drm_test_framebuffer_init [22:23:33] [PASSED] drm_test_framebuffer_init_bad_format [22:23:33] [PASSED] drm_test_framebuffer_init_dev_mismatch [22:23:33] [PASSED] drm_test_framebuffer_lookup [22:23:33] [PASSED] drm_test_framebuffer_lookup_inexistent [22:23:33] [PASSED] drm_test_framebuffer_modifiers_not_supported [22:23:33] ================= [PASSED] drm_framebuffer ================= [22:23:33] ================ drm_gem_shmem (8 subtests) ================ [22:23:33] [PASSED] drm_gem_shmem_test_obj_create [22:23:33] [PASSED] drm_gem_shmem_test_obj_create_private [22:23:33] [PASSED] drm_gem_shmem_test_pin_pages [22:23:33] [PASSED] drm_gem_shmem_test_vmap [22:23:33] [PASSED] drm_gem_shmem_test_get_sg_table [22:23:33] [PASSED] drm_gem_shmem_test_get_pages_sgt [22:23:33] [PASSED] drm_gem_shmem_test_madvise [22:23:33] [PASSED] drm_gem_shmem_test_purge [22:23:33] ================== [PASSED] drm_gem_shmem ================== [22:23:33] === drm_atomic_helper_connector_hdmi_check (29 subtests) === [22:23:33] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode [22:23:33] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1 [22:23:33] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode [22:23:33] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1 [22:23:33] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode [22:23:33] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1 [22:23:33] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 ======= [22:23:33] [PASSED] Automatic [22:23:33] [PASSED] Full [22:23:33] [PASSED] Limited 16:235 [22:23:33] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 === [22:23:33] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed [22:23:33] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed [22:23:33] [PASSED] drm_test_check_disable_connector [22:23:33] [PASSED] drm_test_check_hdmi_funcs_reject_rate [22:23:33] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb [22:23:33] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420 [22:23:33] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422 [22:23:33] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420 [22:23:33] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420 [22:23:33] [PASSED] drm_test_check_output_bpc_crtc_mode_changed [22:23:33] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed [22:23:33] [PASSED] drm_test_check_output_bpc_dvi [22:23:33] [PASSED] drm_test_check_output_bpc_format_vic_1 [22:23:33] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only [22:23:33] [PASSED] drm_test_check_output_bpc_format_display_rgb_only [22:23:33] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only [22:23:33] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only [22:23:33] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc [22:23:33] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc [22:23:33] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc [22:23:33] ============ drm_test_check_hdmi_color_format ============= [22:23:33] [PASSED] AUTO -> RGB [22:23:33] [PASSED] YCBCR422 -> YUV422 [22:23:33] [PASSED] YCBCR420 -> YUV420 [22:23:33] [PASSED] YCBCR444 -> YUV444 [22:23:33] [PASSED] RGB -> RGB [22:23:33] ======== [PASSED] drm_test_check_hdmi_color_format ========= [22:23:33] ======== drm_test_check_hdmi_color_format_420_only ======== [22:23:33] [PASSED] RGB should fail [22:23:33] [PASSED] YUV444 should fail [22:23:33] [PASSED] YUV422 should fail [22:23:33] [PASSED] YUV420 should work [22:23:33] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ==== [22:23:33] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ====== [22:23:33] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ==== [22:23:33] [PASSED] drm_test_check_broadcast_rgb_value [22:23:33] [PASSED] drm_test_check_bpc_8_value [22:23:33] [PASSED] drm_test_check_bpc_10_value [22:23:33] [PASSED] drm_test_check_bpc_12_value [22:23:33] [PASSED] drm_test_check_format_value [22:23:33] [PASSED] drm_test_check_tmds_char_value [22:23:33] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ====== [22:23:33] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) = [22:23:33] [PASSED] drm_test_check_mode_valid [22:23:33] [PASSED] drm_test_check_mode_valid_reject [22:23:33] [PASSED] drm_test_check_mode_valid_reject_rate [22:23:33] [PASSED] drm_test_check_mode_valid_reject_max_clock [22:23:33] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock [22:23:33] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector [22:23:33] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb [22:23:33] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid === [22:23:33] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) = [22:23:33] [PASSED] drm_test_check_infoframes [22:23:33] [PASSED] drm_test_check_reject_avi_infoframe [22:23:33] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8 [22:23:33] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10 [22:23:33] [PASSED] drm_test_check_reject_audio_infoframe [22:23:33] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes === [22:23:33] ================= drm_managed (2 subtests) ================= [22:23:33] [PASSED] drm_test_managed_release_action [22:23:33] [PASSED] drm_test_managed_run_action [22:23:33] =================== [PASSED] drm_managed =================== [22:23:33] =================== drm_mm (6 subtests) ==================== [22:23:33] [PASSED] drm_test_mm_init [22:23:33] [PASSED] drm_test_mm_debug [22:23:33] [PASSED] drm_test_mm_align32 [22:23:33] [PASSED] drm_test_mm_align64 [22:23:33] [PASSED] drm_test_mm_lowest [22:23:33] [PASSED] drm_test_mm_highest [22:23:33] ===================== [PASSED] drm_mm ====================== [22:23:33] ============= drm_modes_analog_tv (5 subtests) ============= [22:23:33] [PASSED] drm_test_modes_analog_tv_mono_576i [22:23:33] [PASSED] drm_test_modes_analog_tv_ntsc_480i [22:23:33] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined [22:23:33] [PASSED] drm_test_modes_analog_tv_pal_576i [22:23:33] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined [22:23:33] =============== [PASSED] drm_modes_analog_tv =============== [22:23:33] ============== drm_plane_helper (2 subtests) =============== [22:23:33] =============== drm_test_check_plane_state ================ [22:23:33] [PASSED] clipping_simple [22:23:33] [PASSED] clipping_rotate_reflect [22:23:33] [PASSED] positioning_simple [22:23:33] [PASSED] upscaling [22:23:33] [PASSED] downscaling [22:23:33] [PASSED] rounding1 [22:23:33] [PASSED] rounding2 [22:23:33] [PASSED] rounding3 [22:23:33] [PASSED] rounding4 [22:23:33] =========== [PASSED] drm_test_check_plane_state ============ [22:23:33] =========== drm_test_check_invalid_plane_state ============ [22:23:33] [PASSED] positioning_invalid [22:23:33] [PASSED] upscaling_invalid [22:23:33] [PASSED] downscaling_invalid [22:23:33] ======= [PASSED] drm_test_check_invalid_plane_state ======== [22:23:33] ================ [PASSED] drm_plane_helper ================= [22:23:33] ====== drm_connector_helper_tv_get_modes (1 subtest) ======= [22:23:33] ====== drm_test_connector_helper_tv_get_modes_check ======= [22:23:33] [PASSED] None [22:23:33] [PASSED] PAL [22:23:33] [PASSED] NTSC [22:23:33] [PASSED] Both, NTSC Default [22:23:33] [PASSED] Both, PAL Default [22:23:33] [PASSED] Both, NTSC Default, with PAL on command-line [22:23:33] [PASSED] Both, PAL Default, with NTSC on command-line [22:23:33] == [PASSED] drm_test_connector_helper_tv_get_modes_check === [22:23:33] ======== [PASSED] drm_connector_helper_tv_get_modes ======== [22:23:33] ================== drm_rect (9 subtests) =================== [22:23:33] [PASSED] drm_test_rect_clip_scaled_div_by_zero [22:23:33] [PASSED] drm_test_rect_clip_scaled_not_clipped [22:23:33] [PASSED] drm_test_rect_clip_scaled_clipped [22:23:33] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned [22:23:33] ================= drm_test_rect_intersect ================= [22:23:33] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0 [22:23:33] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1 [22:23:33] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0 [22:23:33] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1 [22:23:33] [PASSED] right x left: 2x1+0+0 x 3x1+1+0 [22:23:33] [PASSED] left x right: 3x1+1+0 x 2x1+0+0 [22:23:33] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1 [22:23:33] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0 [22:23:33] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1 [22:23:33] [PASSED] touching side: 1x1+0+0 x 1x1+1+0 [22:23:33] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0 [22:23:33] [PASSED] inside another: 2x2+0+0 x 1x1+1+1 [22:23:33] [PASSED] far away: 1x1+0+0 x 1x1+3+6 [22:23:33] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10 [22:23:33] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10 [22:23:33] ============= [PASSED] drm_test_rect_intersect ============= [22:23:33] ================ drm_test_rect_calc_hscale ================ [22:23:33] [PASSED] normal use [22:23:33] [PASSED] out of max range [22:23:33] [PASSED] out of min range [22:23:33] [PASSED] zero dst [22:23:33] [PASSED] negative src [22:23:33] [PASSED] negative dst [22:23:33] ============ [PASSED] drm_test_rect_calc_hscale ============ [22:23:33] ================ drm_test_rect_calc_vscale ================ [22:23:33] [PASSED] normal use [22:23:33] [PASSED] out of max range [22:23:33] [PASSED] out of min range [22:23:33] [PASSED] zero dst [22:23:33] [PASSED] negative src [22:23:33] [PASSED] negative dst [22:23:33] ============ [PASSED] drm_test_rect_calc_vscale ============ [22:23:33] ================== drm_test_rect_rotate =================== [22:23:33] [PASSED] reflect-x [22:23:33] [PASSED] reflect-y [22:23:33] [PASSED] rotate-0 [22:23:33] [PASSED] rotate-90 [22:23:33] [PASSED] rotate-180 [22:23:33] [PASSED] rotate-270 [22:23:33] ============== [PASSED] drm_test_rect_rotate =============== [22:23:33] ================ drm_test_rect_rotate_inv ================= [22:23:33] [PASSED] reflect-x [22:23:33] [PASSED] reflect-y [22:23:33] [PASSED] rotate-0 [22:23:33] [PASSED] rotate-90 [22:23:33] [PASSED] rotate-180 [22:23:33] [PASSED] rotate-270 [22:23:33] ============ [PASSED] drm_test_rect_rotate_inv ============= [22:23:33] ==================== [PASSED] drm_rect ===================== [22:23:33] ============ drm_sysfb_modeset_test (1 subtest) ============ [22:23:33] ============ drm_test_sysfb_build_fourcc_list ============= [22:23:33] [PASSED] no native formats [22:23:33] [PASSED] XRGB8888 as native format [22:23:33] [PASSED] remove duplicates [22:23:33] [PASSED] convert alpha formats [22:23:33] [PASSED] random formats [22:23:33] ======== [PASSED] drm_test_sysfb_build_fourcc_list ========= [22:23:33] ============= [PASSED] drm_sysfb_modeset_test ============== [22:23:33] ================== drm_fixp (2 subtests) =================== [22:23:33] [PASSED] drm_test_int2fixp [22:23:33] [PASSED] drm_test_sm2fixp [22:23:33] ==================== [PASSED] drm_fixp ===================== [22:23:33] ============================================================ [22:23:33] Testing complete. Ran 637 tests: passed: 637 [22:23:33] Elapsed time: 27.143s total, 1.830s configuring, 25.148s building, 0.148s running + /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig [22:23:33] Configuring KUnit Kernel ... Regenerating .config ... Populating config with: $ make ARCH=um O=.kunit olddefconfig [22:23:35] Building KUnit Kernel ... Populating config with: $ make ARCH=um O=.kunit olddefconfig Building with: $ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48 [22:23:45] Starting KUnit Kernel (1/1)... [22:23:45] ============================================================ Running tests with: $ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt [22:23:45] ================= ttm_device (5 subtests) ================== [22:23:45] [PASSED] ttm_device_init_basic [22:23:45] [PASSED] ttm_device_init_multiple [22:23:45] [PASSED] ttm_device_fini_basic [22:23:45] [PASSED] ttm_device_init_no_vma_man [22:23:45] ================== ttm_device_init_pools ================== [22:23:45] [PASSED] No DMA allocations, no DMA32 required [22:23:45] [PASSED] DMA allocations, DMA32 required [22:23:45] [PASSED] No DMA allocations, DMA32 required [22:23:45] [PASSED] DMA allocations, no DMA32 required [22:23:45] ============== [PASSED] ttm_device_init_pools ============== [22:23:45] =================== [PASSED] ttm_device ==================== [22:23:45] ================== ttm_pool (8 subtests) =================== [22:23:45] ================== ttm_pool_alloc_basic =================== [22:23:45] [PASSED] One page [22:23:45] [PASSED] More than one page [22:23:45] [PASSED] Above the allocation limit [22:23:45] [PASSED] One page, with coherent DMA mappings enabled [22:23:45] [PASSED] Above the allocation limit, with coherent DMA mappings enabled [22:23:45] ============== [PASSED] ttm_pool_alloc_basic =============== [22:23:45] ============== ttm_pool_alloc_basic_dma_addr ============== [22:23:45] [PASSED] One page [22:23:45] [PASSED] More than one page [22:23:45] [PASSED] Above the allocation limit [22:23:45] [PASSED] One page, with coherent DMA mappings enabled [22:23:45] [PASSED] Above the allocation limit, with coherent DMA mappings enabled [22:23:45] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ========== [22:23:45] [PASSED] ttm_pool_alloc_order_caching_match [22:23:45] [PASSED] ttm_pool_alloc_caching_mismatch [22:23:45] [PASSED] ttm_pool_alloc_order_mismatch [22:23:45] [PASSED] ttm_pool_free_dma_alloc [22:23:45] [PASSED] ttm_pool_free_no_dma_alloc [22:23:45] [PASSED] ttm_pool_fini_basic [22:23:45] ==================== [PASSED] ttm_pool ===================== [22:23:45] ================ ttm_resource (8 subtests) ================= [22:23:45] ================= ttm_resource_init_basic ================= [22:23:45] [PASSED] Init resource in TTM_PL_SYSTEM [22:23:45] [PASSED] Init resource in TTM_PL_VRAM [22:23:45] [PASSED] Init resource in a private placement [22:23:45] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags [22:23:45] ============= [PASSED] ttm_resource_init_basic ============= [22:23:45] [PASSED] ttm_resource_init_pinned [22:23:45] [PASSED] ttm_resource_fini_basic [22:23:45] [PASSED] ttm_resource_manager_init_basic [22:23:45] [PASSED] ttm_resource_manager_usage_basic [22:23:45] [PASSED] ttm_resource_manager_set_used_basic [22:23:45] [PASSED] ttm_sys_man_alloc_basic [22:23:45] [PASSED] ttm_sys_man_free_basic [22:23:45] ================== [PASSED] ttm_resource =================== [22:23:45] =================== ttm_tt (15 subtests) =================== [22:23:45] ==================== ttm_tt_init_basic ==================== [22:23:45] [PASSED] Page-aligned size [22:23:45] [PASSED] Extra pages requested [22:23:45] ================ [PASSED] ttm_tt_init_basic ================ [22:23:45] [PASSED] ttm_tt_init_misaligned [22:23:45] [PASSED] ttm_tt_fini_basic [22:23:45] [PASSED] ttm_tt_fini_sg [22:23:45] [PASSED] ttm_tt_fini_shmem [22:23:45] [PASSED] ttm_tt_create_basic [22:23:45] [PASSED] ttm_tt_create_invalid_bo_type [22:23:45] [PASSED] ttm_tt_create_ttm_exists [22:23:45] [PASSED] ttm_tt_create_failed [22:23:45] [PASSED] ttm_tt_destroy_basic [22:23:45] [PASSED] ttm_tt_populate_null_ttm [22:23:45] [PASSED] ttm_tt_populate_populated_ttm [22:23:45] [PASSED] ttm_tt_unpopulate_basic [22:23:45] [PASSED] ttm_tt_unpopulate_empty_ttm [22:23:45] [PASSED] ttm_tt_swapin_basic [22:23:45] ===================== [PASSED] ttm_tt ====================== [22:23:45] =================== ttm_bo (14 subtests) =================== [22:23:45] =========== ttm_bo_reserve_optimistic_no_ticket =========== [22:23:45] [PASSED] Cannot be interrupted and sleeps [22:23:45] [PASSED] Cannot be interrupted, locks straight away [22:23:45] [PASSED] Can be interrupted, sleeps [22:23:45] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket ======= [22:23:45] [PASSED] ttm_bo_reserve_locked_no_sleep [22:23:45] [PASSED] ttm_bo_reserve_no_wait_ticket [22:23:45] [PASSED] ttm_bo_reserve_double_resv [22:23:45] [PASSED] ttm_bo_reserve_interrupted [22:23:45] [PASSED] ttm_bo_reserve_deadlock [22:23:45] [PASSED] ttm_bo_unreserve_basic [22:23:45] [PASSED] ttm_bo_unreserve_pinned [22:23:45] [PASSED] ttm_bo_unreserve_bulk [22:23:45] [PASSED] ttm_bo_fini_basic [22:23:45] [PASSED] ttm_bo_fini_shared_resv [22:23:45] [PASSED] ttm_bo_pin_basic [22:23:45] [PASSED] ttm_bo_pin_unpin_resource [22:23:45] [PASSED] ttm_bo_multiple_pin_one_unpin [22:23:45] ===================== [PASSED] ttm_bo ====================== [22:23:45] ============== ttm_bo_validate (22 subtests) =============== [22:23:45] ============== ttm_bo_init_reserved_sys_man =============== [22:23:45] [PASSED] Buffer object for userspace [22:23:45] [PASSED] Kernel buffer object [22:23:45] [PASSED] Shared buffer object [22:23:45] ========== [PASSED] ttm_bo_init_reserved_sys_man =========== [22:23:45] ============== ttm_bo_init_reserved_mock_man ============== [22:23:45] [PASSED] Buffer object for userspace [22:23:45] [PASSED] Kernel buffer object [22:23:45] [PASSED] Shared buffer object [22:23:45] ========== [PASSED] ttm_bo_init_reserved_mock_man ========== [22:23:45] [PASSED] ttm_bo_init_reserved_resv [22:23:45] ================== ttm_bo_validate_basic ================== [22:23:45] [PASSED] Buffer object for userspace [22:23:45] [PASSED] Kernel buffer object [22:23:45] [PASSED] Shared buffer object [22:23:45] ============== [PASSED] ttm_bo_validate_basic ============== [22:23:45] [PASSED] ttm_bo_validate_invalid_placement [22:23:45] ============= ttm_bo_validate_same_placement ============== [22:23:45] [PASSED] System manager [22:23:45] [PASSED] VRAM manager [22:23:45] ========= [PASSED] ttm_bo_validate_same_placement ========== [22:23:45] [PASSED] ttm_bo_validate_failed_alloc [22:23:45] [PASSED] ttm_bo_validate_pinned [22:23:45] [PASSED] ttm_bo_validate_busy_placement [22:23:45] ================ ttm_bo_validate_multihop ================= [22:23:45] [PASSED] Buffer object for userspace [22:23:45] [PASSED] Kernel buffer object [22:23:45] [PASSED] Shared buffer object [22:23:45] ============ [PASSED] ttm_bo_validate_multihop ============= [22:23:45] ========== ttm_bo_validate_no_placement_signaled ========== [22:23:45] [PASSED] Buffer object in system domain, no page vector [22:23:45] [PASSED] Buffer object in system domain with an existing page vector [22:23:45] ====== [PASSED] ttm_bo_validate_no_placement_signaled ====== [22:23:45] ======== ttm_bo_validate_no_placement_not_signaled ======== [22:23:45] [PASSED] Buffer object for userspace [22:23:45] [PASSED] Kernel buffer object [22:23:45] [PASSED] Shared buffer object [22:23:45] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ==== [22:23:45] [PASSED] ttm_bo_validate_move_fence_signaled [22:23:45] ========= ttm_bo_validate_move_fence_not_signaled ========= [22:23:45] [PASSED] Waits for GPU [22:23:45] [PASSED] Tries to lock straight away [22:23:45] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled ===== [22:23:45] [PASSED] ttm_bo_validate_swapout [22:23:45] [PASSED] ttm_bo_validate_happy_evict [22:23:45] [PASSED] ttm_bo_validate_all_pinned_evict [22:23:45] [PASSED] ttm_bo_validate_allowed_only_evict [22:23:45] [PASSED] ttm_bo_validate_deleted_evict [22:23:45] [PASSED] ttm_bo_validate_busy_domain_evict [22:23:45] [PASSED] ttm_bo_validate_evict_gutting [22:23:45] [PASSED] ttm_bo_validate_recrusive_evict [22:23:45] ================= [PASSED] ttm_bo_validate ================= [22:23:45] ============================================================ [22:23:45] Testing complete. Ran 102 tests: passed: 102 [22:23:45] Elapsed time: 12.057s total, 1.794s configuring, 9.998s building, 0.216s running + cleanup ++ stat -c %u:%g /kernel + chown -R 1003:1003 /kernel ^ permalink raw reply [flat|nested] 13+ messages in thread
* ✓ Xe.CI.BAT: success for drm/xe: Update Wa_14026539277 2026-07-24 21:44 [PATCH v2 0/3] drm/xe: Update Wa_14026539277 Gustavo Sousa ` (4 preceding siblings ...) 2026-07-24 22:23 ` ✓ CI.KUnit: success " Patchwork @ 2026-07-24 22:59 ` Patchwork 5 siblings, 0 replies; 13+ messages in thread From: Patchwork @ 2026-07-24 22:59 UTC (permalink / raw) To: Gustavo Sousa; +Cc: intel-xe [-- Attachment #1: Type: text/plain, Size: 943 bytes --] == Series Details == Series: drm/xe: Update Wa_14026539277 URL : https://patchwork.freedesktop.org/series/171093/ State : success == Summary == CI Bug Log - changes from xe-5480-d3598db200de654bf03fc68e8b99869da3c20e91_BAT -> xe-pw-171093v1_BAT ==================================================== Summary ------- **SUCCESS** No regressions found. Participating hosts (12 -> 12) ------------------------------ No changes in participating hosts Changes ------- No changes found Build changes ------------- * Linux: xe-5480-d3598db200de654bf03fc68e8b99869da3c20e91 -> xe-pw-171093v1 IGT_9025: 852c13ddd448fd668c43584ca3ad1aec49c4633c @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git xe-5480-d3598db200de654bf03fc68e8b99869da3c20e91: d3598db200de654bf03fc68e8b99869da3c20e91 xe-pw-171093v1: 171093v1 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171093v1/index.html [-- Attachment #2: Type: text/html, Size: 1491 bytes --] ^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2026-08-19 20:37 UTC | newest] Thread overview: 13+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-07-24 21:44 [PATCH v2 0/3] drm/xe: Update Wa_14026539277 Gustavo Sousa 2026-07-24 21:44 ` [PATCH v2 1/3] drm/xe: Extract override_has_cached_pt() Gustavo Sousa 2026-07-28 12:42 ` Matthew Auld 2026-07-24 21:44 ` [PATCH v2 2/3] Revert "drm/xe/nvlp: Implement Wa_14026539277" Gustavo Sousa 2026-08-19 13:23 ` Matthew Auld 2026-07-24 21:44 ` [PATCH v2 3/3] drm/xe: Add up-to-date implementation for Wa_14026539277 Gustavo Sousa 2026-07-28 12:40 ` Matthew Auld 2026-07-28 13:25 ` Souza, Jose 2026-08-19 13:53 ` Matthew Auld 2026-08-19 20:37 ` Gustavo Sousa 2026-07-24 22:22 ` ✗ CI.checkpatch: warning for drm/xe: Update Wa_14026539277 Patchwork 2026-07-24 22:23 ` ✓ CI.KUnit: success " Patchwork 2026-07-24 22:59 ` ✓ Xe.CI.BAT: " Patchwork
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