[Intel-xe] [PATCH 00/18] xe&i915 display integration: add uncore and pcode compat layers

[Intel-xe] [PATCH 00/18] xe&i915 display integration: add uncore and pcode compat layers

[Jani Nikula]

v2 of
https://lore.kernel.org/r/20230503131005.1602412-1-jani.nikula@intel.com

- rebase
- fix rmw now that xe follows i915 rmw arguments


Jani Nikula (18):
  fixup! drm/xe/display: Implement display support
  fixup! drm/xe/display: Implement display support
  fixup! drm/xe/display: Implement display support
  fixup! drm/xe/display: Rename intel_de.h to xe_de.h
  fixup! drm/xe/display: Implement display support
  fixup! drm/i915/display: Remaining changes to make xe compile
  fixup! drm/xe/display: Implement display support
  fixup! drm/i915/display: Add more macros to remove all direct calls to
    uncore
  fixup! drm/i915/display: Remove all uncore mmio accesses in favor of
    intel_de
  fixup! drm/i915/display: Remaining changes to make xe compile
  fixup! drm/xe: Introduce a new DRM driver for Intel GPUs
  fixup! drm/xe/display: Implement display support
  fixup! drm/i915/display: Remaining changes to make xe compile
  fixup! drm/i915/display: Remaining changes to make xe compile
  fixup! drm/xe/display: Implement display support
  fixup! drm/xe/display: Implement display support
  fixup! drm/xe/display: Implement display support
  fixup! drm/xe/display: Implement display support

 drivers/gpu/drm/i915/display/hsw_ips.c        |   7 +-
 drivers/gpu/drm/i915/display/intel_bios.c     |  19 +-
 drivers/gpu/drm/i915/display/intel_bw.c       |  34 ++--
 drivers/gpu/drm/i915/display/intel_cdclk.c    |  45 ++---
 drivers/gpu/drm/i915/display/intel_de.h       |  54 ------
 drivers/gpu/drm/i915/display/intel_display.c  |   1 +
 .../drm/i915/display/intel_display_power.c    |   3 +-
 .../i915/display/intel_display_power_well.c   |   7 +-
 drivers/gpu/drm/i915/display/intel_dpio_phy.c |   9 +-
 drivers/gpu/drm/i915/display/intel_hdcp.c     |   9 +-
 drivers/gpu/drm/i915/display/skl_watermark.c  |  23 +--
 .../gpu/drm/xe/compat-i915-headers/i915_drv.h |   1 +
 .../drm/xe/compat-i915-headers/intel_pcode.h  |  42 +++++
 .../drm/xe/compat-i915-headers/intel_uncore.h |  98 +++++++++++
 drivers/gpu/drm/xe/display/ext/i915_irq.c     | 118 ++++++-------
 .../drm/xe/display/ext/intel_clock_gating.c   |   1 +
 .../drm/xe/display/ext/intel_device_info.c    |   1 +
 drivers/gpu/drm/xe/display/ext/intel_dram.c   |   3 +-
 drivers/gpu/drm/xe/display/xe_de.h            | 163 ------------------
 drivers/gpu/drm/xe/xe_device_types.h          |   4 +
 drivers/gpu/drm/xe/xe_display.c               |   3 +
 drivers/gpu/drm/xe/xe_mmio.h                  |   8 +
 22 files changed, 298 insertions(+), 355 deletions(-)
 create mode 100644 drivers/gpu/drm/xe/compat-i915-headers/intel_pcode.h
 create mode 100644 drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
 delete mode 100644 drivers/gpu/drm/xe/display/xe_de.h

-- 
2.39.2

[Intel-xe] [PATCH 01/18] fixup! drm/xe/display: Implement display support

[Jani Nikula]

Add struct fake_uncore, mostly to allow getting at struct xe_device when
&i915->uncore is used.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/xe/xe_device_types.h | 4 ++++
 drivers/gpu/drm/xe/xe_display.c      | 3 +++
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 3a11caaf874b..6490a04614ce 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -311,6 +311,10 @@ struct xe_device {
 	bool display_irqs_enabled;
 	u32 enabled_irq_mask;
 
+	struct fake_uncore {
+		spinlock_t lock;
+	} uncore;
+
 	/* only to allow build, not used functionally */
 	struct {
 		unsigned int hpll_freq;
diff --git a/drivers/gpu/drm/xe/xe_display.c b/drivers/gpu/drm/xe/xe_display.c
index 69e223c9a1cc..77a158ecf4cb 100644
--- a/drivers/gpu/drm/xe/xe_display.c
+++ b/drivers/gpu/drm/xe/xe_display.c
@@ -140,6 +140,9 @@ int xe_display_init_nommio(struct xe_device *xe)
 	if (!xe->info.enable_display)
 		return 0;
 
+	/* Fake uncore lock */
+	spin_lock_init(&xe->uncore.lock);
+
 	/* This must be called before any calls to HAS_PCH_* */
 	intel_detect_pch(xe);
 	intel_display_irq_init(xe);
-- 
2.39.2

[Intel-xe] [PATCH 02/18] fixup! drm/xe/display: Implement display support

[Jani Nikula]

Add compat intel_uncore.h glue layer to direct all uncore calls to xe
mmio.

v2: fix rmw as xe now follows i915 style

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 .../drm/xe/compat-i915-headers/intel_uncore.h | 98 +++++++++++++++++++
 1 file changed, 98 insertions(+)
 create mode 100644 drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

diff --git a/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h b/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
new file mode 100644
index 000000000000..90d79290a211
--- /dev/null
+++ b/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#ifndef __INTEL_UNCORE_H__
+#define __INTEL_UNCORE_H__
+
+#include "xe_device.h"
+#include "xe_device_types.h"
+#include "xe_mmio.h"
+
+static inline struct xe_gt *__fake_uncore_to_gt(struct fake_uncore *uncore)
+{
+	struct xe_device *xe = container_of(uncore, struct xe_device, uncore);
+
+	return to_gt(xe);
+}
+
+static inline u32 intel_uncore_read(struct fake_uncore *uncore, i915_reg_t reg)
+{
+	return xe_mmio_read32(__fake_uncore_to_gt(uncore), reg.reg);
+}
+
+static inline u32 intel_uncore_read8(struct fake_uncore *uncore, i915_reg_t reg)
+{
+	return xe_mmio_read8(__fake_uncore_to_gt(uncore), reg.reg);
+}
+
+static inline u64 intel_uncore_read64_2x32(struct fake_uncore *uncore, i915_reg_t lower_reg, i915_reg_t upper_reg)
+{
+	u32 upper, lower, old_upper;
+	int loop = 0;
+
+	upper = xe_mmio_read32(__fake_uncore_to_gt(uncore), upper_reg.reg);
+	do {
+		old_upper = upper;
+		lower = xe_mmio_read32(__fake_uncore_to_gt(uncore), lower_reg.reg);
+		upper = xe_mmio_read32(__fake_uncore_to_gt(uncore), upper_reg.reg);
+	} while (upper != old_upper && loop++ < 2);
+
+	return (u64)upper << 32 | lower;
+}
+
+static inline void intel_uncore_posting_read(struct fake_uncore *uncore, i915_reg_t reg)
+{
+	xe_mmio_read32(__fake_uncore_to_gt(uncore), reg.reg);
+}
+
+static inline void intel_uncore_write(struct fake_uncore *uncore, i915_reg_t reg, u32 val)
+{
+	xe_mmio_write32(__fake_uncore_to_gt(uncore), reg.reg, val);
+}
+
+static inline u32 intel_uncore_rmw(struct fake_uncore *uncore, i915_reg_t reg, u32 clear, u32 set)
+{
+	return xe_mmio_rmw32(__fake_uncore_to_gt(uncore), reg.reg, clear, set);
+}
+
+static inline int intel_wait_for_register(struct fake_uncore *uncore, i915_reg_t reg, u32 mask, u32 value, unsigned int timeout)
+{
+	return xe_mmio_wait32(__fake_uncore_to_gt(uncore), reg.reg, value, mask, timeout * USEC_PER_MSEC, NULL, false);
+}
+
+static inline int intel_wait_for_register_fw(struct fake_uncore *uncore, i915_reg_t reg, u32 mask, u32 value, unsigned int timeout)
+{
+	return xe_mmio_wait32(__fake_uncore_to_gt(uncore), reg.reg, value, mask, timeout * USEC_PER_MSEC, NULL, false);
+}
+
+static inline int __intel_wait_for_register(struct fake_uncore *uncore, i915_reg_t reg, u32 mask, u32 value,
+					    unsigned int fast_timeout_us, unsigned int slow_timeout_ms, u32 *out_value)
+{
+	return xe_mmio_wait32(__fake_uncore_to_gt(uncore), reg.reg, value, mask,
+			      fast_timeout_us + 1000 * slow_timeout_ms,
+			      out_value, false);
+}
+
+static inline u32 intel_uncore_read_fw(struct fake_uncore *uncore, i915_reg_t reg)
+{
+	return xe_mmio_read32(__fake_uncore_to_gt(uncore), reg.reg);
+}
+
+static inline void intel_uncore_write_fw(struct fake_uncore *uncore, i915_reg_t reg, u32 val)
+{
+	xe_mmio_write32(__fake_uncore_to_gt(uncore), reg.reg, val);
+}
+
+static inline u32 intel_uncore_read_notrace(struct fake_uncore *uncore, i915_reg_t reg)
+{
+	return xe_mmio_read32(__fake_uncore_to_gt(uncore), reg.reg);
+}
+
+static inline void intel_uncore_write_notrace(struct fake_uncore *uncore, i915_reg_t reg, u32 val)
+{
+	xe_mmio_write32(__fake_uncore_to_gt(uncore), reg.reg, val);
+}
+
+#endif /* __INTEL_UNCORE_H__ */
-- 
2.39.2

[Intel-xe] [PATCH 03/18] fixup! drm/xe/display: Implement display support

[Jani Nikula]

Remove the dummy wrappers and use the uncore glue layer.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/xe/display/ext/i915_irq.c | 118 ++++++++++------------
 1 file changed, 56 insertions(+), 62 deletions(-)

diff --git a/drivers/gpu/drm/xe/display/ext/i915_irq.c b/drivers/gpu/drm/xe/display/ext/i915_irq.c
index 0349bca789d6..afde97b6faa6 100644
--- a/drivers/gpu/drm/xe/display/ext/i915_irq.c
+++ b/drivers/gpu/drm/xe/display/ext/i915_irq.c
@@ -35,7 +35,6 @@
 #include <drm/drm_drv.h>
 
 #include "icl_dsi_regs.h"
-#include "intel_de.h"
 #include "intel_display_trace.h"
 #include "intel_display_types.h"
 #include "intel_fifo_underrun.h"
@@ -45,13 +44,8 @@
 #include "intel_psr_regs.h"
 
 #include "i915_drv.h"
-#include "intel_de.h"
-
-#define intel_uncore_read(uncore, reg) intel_de_read(dev_priv, (reg))
-#define intel_uncore_read64(uncore, reg) intel_de_read64(dev_priv, (reg))
-#define intel_uncore_write(uncore, reg, value) intel_de_write(dev_priv, reg, value)
-#define intel_uncore_rmw(uncore, reg, clear, set) intel_de_rmw(dev_priv, reg, clear, set)
-#define intel_uncore_posting_read intel_uncore_read
+#include "i915_reg.h"
+#include "intel_uncore.h"
 
 static u32 raw_reg_read(void __iomem *base, i915_reg_t reg)
 {
@@ -69,16 +63,16 @@ static void raw_reg_write(void __iomem *base, i915_reg_t reg, u32 value)
 static void gen3_irq_reset(struct xe_device *dev_priv, i915_reg_t imr,
 		    i915_reg_t iir, i915_reg_t ier)
 {
-	intel_uncore_write(dev_priv, imr, 0xffffffff);
-	intel_uncore_posting_read(dev_priv, imr);
+	intel_uncore_write(&dev_priv->uncore, imr, 0xffffffff);
+	intel_uncore_posting_read(&dev_priv->uncore, imr);
 
-	intel_uncore_write(dev_priv, ier, 0);
+	intel_uncore_write(&dev_priv->uncore, ier, 0);
 
 	/* IIR can theoretically queue up two events. Be paranoid. */
-	intel_uncore_write(dev_priv, iir, 0xffffffff);
-	intel_uncore_posting_read(dev_priv, iir);
-	intel_uncore_write(dev_priv, iir, 0xffffffff);
-	intel_uncore_posting_read(dev_priv, iir);
+	intel_uncore_write(&dev_priv->uncore, iir, 0xffffffff);
+	intel_uncore_posting_read(&dev_priv->uncore, iir);
+	intel_uncore_write(&dev_priv->uncore, iir, 0xffffffff);
+	intel_uncore_posting_read(&dev_priv->uncore, iir);
 }
 
 /*
@@ -86,7 +80,7 @@ static void gen3_irq_reset(struct xe_device *dev_priv, i915_reg_t imr,
  */
 static void gen3_assert_iir_is_zero(struct xe_device *dev_priv, i915_reg_t reg)
 {
-	u32 val = intel_uncore_read(dev_priv, reg);
+	u32 val = intel_uncore_read(&dev_priv->uncore, reg);
 
 	if (val == 0)
 		return;
@@ -94,10 +88,10 @@ static void gen3_assert_iir_is_zero(struct xe_device *dev_priv, i915_reg_t reg)
 	drm_WARN(&dev_priv->drm, 1,
 		 "Interrupt register 0x%x is not zero: 0x%08x\n",
 		 reg.reg, val);
-	intel_uncore_write(dev_priv, reg, 0xffffffff);
-	intel_uncore_posting_read(dev_priv, reg);
-	intel_uncore_write(dev_priv, reg, 0xffffffff);
-	intel_uncore_posting_read(dev_priv, reg);
+	intel_uncore_write(&dev_priv->uncore, reg, 0xffffffff);
+	intel_uncore_posting_read(&dev_priv->uncore, reg);
+	intel_uncore_write(&dev_priv->uncore, reg, 0xffffffff);
+	intel_uncore_posting_read(&dev_priv->uncore, reg);
 }
 
 static void gen3_irq_init(struct xe_device *dev_priv,
@@ -107,9 +101,9 @@ static void gen3_irq_init(struct xe_device *dev_priv,
 {
 	gen3_assert_iir_is_zero(dev_priv, iir);
 
-	intel_uncore_write(xe, ier, ier_val);
-	intel_uncore_write(xe, imr, imr_val);
-	intel_uncore_posting_read(xe, imr);
+	intel_uncore_write(&dev_priv->uncore, ier, ier_val);
+	intel_uncore_write(&dev_priv->uncore, imr, imr_val);
+	intel_uncore_posting_read(&dev_priv->uncore, imr);
 }
 
 #define GEN8_IRQ_RESET_NDX(uncore, type, which) \
@@ -223,10 +217,10 @@ i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
 	lockdep_assert_held(&dev_priv->irq_lock);
 	drm_WARN_ON(&dev_priv->drm, bits & ~mask);
 
-	val = intel_uncore_read(dev_priv, PORT_HOTPLUG_EN);
+	val = intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_EN);
 	val &= ~mask;
 	val |= bits;
-	intel_uncore_write(dev_priv, PORT_HOTPLUG_EN, val);
+	intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_EN, val);
 }
 
 /**
@@ -276,8 +270,8 @@ static void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
 
 	if (new_val != dev_priv->de_irq_mask[pipe]) {
 		dev_priv->de_irq_mask[pipe] = new_val;
-		intel_uncore_write(dev_priv, GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
-		intel_uncore_posting_read(dev_priv, GEN8_DE_PIPE_IMR(pipe));
+		intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
+		intel_uncore_posting_read(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe));
 	}
 }
 
@@ -550,7 +544,7 @@ static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
 				     enum pipe pipe)
 {
 	display_pipe_crc_irq_handler(dev_priv, pipe,
-				     intel_uncore_read(dev_priv, PIPE_CRC_RES_1_IVB(pipe)),
+				     intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)),
 				     0, 0, 0, 0);
 }
 
@@ -563,8 +557,8 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
 	if (ddi_hotplug_trigger) {
 		u32 dig_hotplug_reg;
 
-		dig_hotplug_reg = intel_uncore_read(dev_priv, SHOTPLUG_CTL_DDI);
-		intel_uncore_write(dev_priv, SHOTPLUG_CTL_DDI, dig_hotplug_reg);
+		dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_DDI);
+		intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_DDI, dig_hotplug_reg);
 
 		intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
 				   ddi_hotplug_trigger, dig_hotplug_reg,
@@ -575,8 +569,8 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
 	if (tc_hotplug_trigger) {
 		u32 dig_hotplug_reg;
 
-		dig_hotplug_reg = intel_uncore_read(dev_priv, SHOTPLUG_CTL_TC);
-		intel_uncore_write(dev_priv, SHOTPLUG_CTL_TC, dig_hotplug_reg);
+		dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_TC);
+		intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_TC, dig_hotplug_reg);
 
 		intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
 				   tc_hotplug_trigger, dig_hotplug_reg,
@@ -600,8 +594,8 @@ static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
 	if (trigger_tc) {
 		u32 dig_hotplug_reg;
 
-		dig_hotplug_reg = intel_uncore_read(dev_priv, GEN11_TC_HOTPLUG_CTL);
-		intel_uncore_write(dev_priv, GEN11_TC_HOTPLUG_CTL, dig_hotplug_reg);
+		dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL);
+		intel_uncore_write(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL, dig_hotplug_reg);
 
 		intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
 				   trigger_tc, dig_hotplug_reg,
@@ -612,8 +606,8 @@ static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
 	if (trigger_tbt) {
 		u32 dig_hotplug_reg;
 
-		dig_hotplug_reg = intel_uncore_read(dev_priv, GEN11_TBT_HOTPLUG_CTL);
-		intel_uncore_write(dev_priv, GEN11_TBT_HOTPLUG_CTL, dig_hotplug_reg);
+		dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL);
+		intel_uncore_write(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL, dig_hotplug_reg);
 
 		intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
 				   trigger_tbt, dig_hotplug_reg,
@@ -703,8 +697,8 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
 			else
 				iir_reg = EDP_PSR_IIR;
 
-			psr_iir = intel_uncore_read(dev_priv, iir_reg);
-			intel_uncore_write(dev_priv, iir_reg, psr_iir);
+			psr_iir = intel_uncore_read(&dev_priv->uncore, iir_reg);
+			intel_uncore_write(&dev_priv->uncore, iir_reg, psr_iir);
 
 			if (psr_iir)
 				found = true;
@@ -733,7 +727,7 @@ static void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,
 	 * Incase of dual link, TE comes from DSI_1
 	 * this is to check if dual link is enabled
 	 */
-	val = intel_uncore_read(dev_priv, TRANS_DDI_FUNC_CTL2(TRANSCODER_DSI_0));
+	val = intel_uncore_read(&dev_priv->uncore, TRANS_DDI_FUNC_CTL2(TRANSCODER_DSI_0));
 	val &= PORT_SYNC_MODE_ENABLE;
 
 	/*
@@ -745,7 +739,7 @@ static void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,
 	dsi_trans = (port == PORT_A) ? TRANSCODER_DSI_0 : TRANSCODER_DSI_1;
 
 	/* Check if DSI configured in command mode */
-	val = intel_uncore_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans));
+	val = intel_uncore_read(&dev_priv->uncore, DSI_TRANS_FUNC_CONF(dsi_trans));
 	val = val & OP_MODE_MASK;
 
 	if (val != CMD_MODE_NO_GATE && val != CMD_MODE_TE_GATE) {
@@ -754,7 +748,7 @@ static void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,
 	}
 
 	/* Get PIPE for handling VBLANK event */
-	val = intel_uncore_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans));
+	val = intel_uncore_read(&dev_priv->uncore, TRANS_DDI_FUNC_CTL(dsi_trans));
 	switch (val & TRANS_DDI_EDP_INPUT_MASK) {
 	case TRANS_DDI_EDP_INPUT_A_ON:
 		pipe = PIPE_A;
@@ -774,8 +768,8 @@ static void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,
 
 	/* clear TE in dsi IIR */
 	port = (te_trigger & DSI1_TE) ? PORT_B : PORT_A;
-	tmp = intel_uncore_read(dev_priv, DSI_INTR_IDENT_REG(port));
-	intel_uncore_write(dev_priv, DSI_INTR_IDENT_REG(port), tmp);
+	tmp = intel_uncore_read(&dev_priv->uncore, DSI_INTR_IDENT_REG(port));
+	intel_uncore_write(&dev_priv->uncore, DSI_INTR_IDENT_REG(port), tmp);
 }
 
 static u32 gen8_de_pipe_flip_done_mask(struct drm_i915_private *i915)
@@ -807,9 +801,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 	drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_DISPLAY(dev_priv));
 
 	if (master_ctl & GEN8_DE_MISC_IRQ) {
-		iir = intel_uncore_read(dev_priv, GEN8_DE_MISC_IIR);
+		iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_MISC_IIR);
 		if (iir) {
-			intel_uncore_write(dev_priv, GEN8_DE_MISC_IIR, iir);
+			intel_uncore_write(&dev_priv->uncore, GEN8_DE_MISC_IIR, iir);
 			ret = IRQ_HANDLED;
 			gen8_de_misc_irq_handler(dev_priv, iir);
 		} else {
@@ -819,9 +813,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 	}
 
 	if (DISPLAY_VER(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) {
-		iir = intel_uncore_read(dev_priv, GEN11_DE_HPD_IIR);
+		iir = intel_uncore_read(&dev_priv->uncore, GEN11_DE_HPD_IIR);
 		if (iir) {
-			intel_uncore_write(dev_priv, GEN11_DE_HPD_IIR, iir);
+			intel_uncore_write(&dev_priv->uncore, GEN11_DE_HPD_IIR, iir);
 			ret = IRQ_HANDLED;
 			gen11_hpd_irq_handler(dev_priv, iir);
 		} else {
@@ -831,11 +825,11 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 	}
 
 	if (master_ctl & GEN8_DE_PORT_IRQ) {
-		iir = intel_uncore_read(dev_priv, GEN8_DE_PORT_IIR);
+		iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IIR);
 		if (iir) {
 			bool found = false;
 
-			intel_uncore_write(dev_priv, GEN8_DE_PORT_IIR, iir);
+			intel_uncore_write(&dev_priv->uncore, GEN8_DE_PORT_IIR, iir);
 			ret = IRQ_HANDLED;
 
 			if (iir & gen8_de_port_aux_mask(dev_priv)) {
@@ -867,7 +861,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 		if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
 			continue;
 
-		iir = intel_uncore_read(dev_priv, GEN8_DE_PIPE_IIR(pipe));
+		iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe));
 		if (!iir) {
 			drm_err(&dev_priv->drm,
 				"The master control interrupt lied (DE PIPE)!\n");
@@ -875,7 +869,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 		}
 
 		ret = IRQ_HANDLED;
-		intel_uncore_write(dev_priv, GEN8_DE_PIPE_IIR(pipe), iir);
+		intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe), iir);
 
 		if (iir & GEN8_PIPE_VBLANK)
 			intel_handle_vblank(dev_priv, pipe);
@@ -904,9 +898,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 		 * scheme also closed the SDE interrupt handling race we've seen
 		 * on older pch-split platforms. But this needs testing.
 		 */
-		iir = intel_uncore_read(dev_priv, SDEIIR);
+		iir = intel_uncore_read(&dev_priv->uncore, SDEIIR);
 		if (iir) {
-			intel_uncore_write(dev_priv, SDEIIR, iir);
+			intel_uncore_write(&dev_priv->uncore, SDEIIR, iir);
 			ret = IRQ_HANDLED;
 
 			if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
@@ -956,16 +950,16 @@ static bool gen11_dsi_configure_te(struct intel_crtc *intel_crtc,
 	else
 		port = PORT_A;
 
-	tmp =  intel_uncore_read(dev_priv, DSI_INTR_MASK_REG(port));
+	tmp =  intel_uncore_read(&dev_priv->uncore, DSI_INTR_MASK_REG(port));
 	if (enable)
 		tmp &= ~DSI_TE_EVENT;
 	else
 		tmp |= DSI_TE_EVENT;
 
-	intel_uncore_write(dev_priv, DSI_INTR_MASK_REG(port), tmp);
+	intel_uncore_write(&dev_priv->uncore, DSI_INTR_MASK_REG(port), tmp);
 
-	tmp = intel_uncore_read(dev_priv, DSI_INTR_IDENT_REG(port));
-	intel_uncore_write(dev_priv, DSI_INTR_IDENT_REG(port), tmp);
+	tmp = intel_uncore_read(&dev_priv->uncore, DSI_INTR_IDENT_REG(port));
+	intel_uncore_write(&dev_priv->uncore, DSI_INTR_IDENT_REG(port), tmp);
 
 	return true;
 }
@@ -1018,11 +1012,11 @@ void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
 	if (!HAS_DISPLAY(dev_priv))
 		return;
 
-	intel_uncore_write(dev_priv, GEN11_DISPLAY_INT_CTL, 0);
+	intel_uncore_write(&dev_priv->uncore, GEN11_DISPLAY_INT_CTL, 0);
 
 	for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) {
-		intel_uncore_write(dev_priv, TRANS_PSR_IMR(trans), 0xffffffff);
-		intel_uncore_write(dev_priv, TRANS_PSR_IIR(trans), 0xffffffff);
+		intel_uncore_write(&dev_priv->uncore, TRANS_PSR_IMR(trans), 0xffffffff);
+		intel_uncore_write(&dev_priv->uncore, TRANS_PSR_IIR(trans), 0xffffffff);
 	}
 
 	for_each_pipe(dev_priv, pipe)
@@ -1145,7 +1139,7 @@ static void icp_tc_hpd_enable_detection(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
-	intel_uncore_rmw(&i915->uncore, SHOTPLUG_CTL_TC,
+	intel_uncore_rmw(&dev_priv->uncore, SHOTPLUG_CTL_TC,
 			 icp_tc_hotplug_mask(encoder->hpd_pin),
 			 icp_tc_hotplug_enables(encoder));
 }
@@ -1354,7 +1348,7 @@ static void gen11_de_irq_postinstall(struct drm_i915_private *dev_priv)
 
 	gen8_de_irq_postinstall(dev_priv);
 
-	intel_uncore_write(dev_priv, GEN11_DISPLAY_INT_CTL,
+	intel_uncore_write(&dev_priv->uncore, GEN11_DISPLAY_INT_CTL,
 			   GEN11_DISPLAY_IRQ_ENABLE);
 }
 
-- 
2.39.2

[Intel-xe] [PATCH 04/18] fixup! drm/xe/display: Rename intel_de.h to xe_de.h

[Jani Nikula]

Revert "drm/xe/display: Rename intel_de.h to xe_de.h". Remove the entire
commit from history. This is just to revert further changes cleanly.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_de.h            | 4 ++--
 drivers/gpu/drm/xe/Makefile                        | 1 +
 drivers/gpu/drm/xe/display/{xe_de.h => intel_de.h} | 8 ++++----
 3 files changed, 7 insertions(+), 6 deletions(-)
 rename drivers/gpu/drm/xe/display/{xe_de.h => intel_de.h} (97%)

diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h
index 8ffe2a9e4913..5c223ff6b3ec 100644
--- a/drivers/gpu/drm/i915/display/intel_de.h
+++ b/drivers/gpu/drm/i915/display/intel_de.h
@@ -3,8 +3,8 @@
  * Copyright © 2019 Intel Corporation
  */
 
-#ifndef I915
-#include "xe_de.h"
+#ifdef BUILD_FOR_XE
+#include_next "intel_de.h"
 #else
 #ifndef __INTEL_DE_H__
 #define __INTEL_DE_H__
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index b6c41cd7dbe3..e5130613a943 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -103,6 +103,7 @@ subdir-ccflags-$(CONFIG_DRM_XE_DISPLAY) += \
 	-I$(srctree)/$(src)/compat-i915-headers \
 	-I$(srctree)/drivers/gpu/drm/xe/display/ \
 	-I$(srctree)/drivers/gpu/drm/i915/display/ \
+	-DBUILD_FOR_XE=1 \
 	-Ddrm_i915_gem_object=xe_bo \
 	-Ddrm_i915_private=xe_device
 
diff --git a/drivers/gpu/drm/xe/display/xe_de.h b/drivers/gpu/drm/xe/display/intel_de.h
similarity index 97%
rename from drivers/gpu/drm/xe/display/xe_de.h
rename to drivers/gpu/drm/xe/display/intel_de.h
index 0c76b0d24d96..31322cf5e7af 100644
--- a/drivers/gpu/drm/xe/display/xe_de.h
+++ b/drivers/gpu/drm/xe/display/intel_de.h
@@ -1,10 +1,10 @@
 /* SPDX-License-Identifier: MIT */
 /*
- * Copyright © 2019-2022 Intel Corporation
+ * Copyright © 2019 Intel Corporation
  */
 
-#ifndef _XE_DE_H_
-#define _XE_DE_H_
+#ifndef __INTEL_DE_H__
+#define __INTEL_DE_H__
 
 #include "i915_drv.h"
 #include "xe_mmio.h"
@@ -160,4 +160,4 @@ static inline int intel_de_pcode_request(struct drm_i915_private *i915, u32 mbox
 				timeout_base_ms);
 }
 
-#endif
+#endif /* __INTEL_DE_H__ */
-- 
2.39.2

[Intel-xe] [PATCH 05/18] fixup! drm/xe/display: Implement display support

[Jani Nikula]

Remove intel_de.h completely in favour of having i915/display/intel_de.h
route to the uncore glue layer.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/xe/display/intel_de.h | 163 --------------------------
 1 file changed, 163 deletions(-)
 delete mode 100644 drivers/gpu/drm/xe/display/intel_de.h

diff --git a/drivers/gpu/drm/xe/display/intel_de.h b/drivers/gpu/drm/xe/display/intel_de.h
deleted file mode 100644
index 31322cf5e7af..000000000000
--- a/drivers/gpu/drm/xe/display/intel_de.h
+++ /dev/null
@@ -1,163 +0,0 @@
-/* SPDX-License-Identifier: MIT */
-/*
- * Copyright © 2019 Intel Corporation
- */
-
-#ifndef __INTEL_DE_H__
-#define __INTEL_DE_H__
-
-#include "i915_drv.h"
-#include "xe_mmio.h"
-#include "xe_pcode.h"
-
-/* This was included from i915_trace.h -> i915_irq.h -> i915_reg.h, kept for compat */
-#include "i915_reg.h"
-
-static inline u32
-intel_de_read(struct drm_i915_private *i915, i915_reg_t reg)
-{
-	return xe_mmio_read32(to_gt(i915), reg.reg);
-}
-
-static inline u64
-intel_de_read64_2x32(struct drm_i915_private *i915,
-		     i915_reg_t lower_reg, i915_reg_t upper_reg)
-{
-	u32 upper, lower;
-
-	lower = xe_mmio_read32(to_gt(i915), lower_reg.reg);
-	upper = xe_mmio_read32(to_gt(i915), upper_reg.reg);
-	return (u64)upper << 32 | lower;
-}
-
-static inline void
-intel_de_posting_read(struct drm_i915_private *i915, i915_reg_t reg)
-{
-	xe_mmio_read32(to_gt(i915), reg.reg);
-}
-
-static inline void
-intel_de_write(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
-{
-	xe_mmio_write32(to_gt(i915), reg.reg, val);
-}
-
-static inline u32
-intel_de_rmw(struct drm_i915_private *i915, i915_reg_t reg, u32 clear, u32 set)
-{
-	return xe_mmio_rmw32(to_gt(i915), reg.reg, clear, set);
-}
-
-static inline int
-intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t reg,
-			   u32 mask, u32 value, unsigned int timeout)
-{
-	return xe_mmio_wait32(to_gt(i915), reg.reg, value, mask, timeout * USEC_PER_MSEC, NULL,
-			      false);
-}
-
-static inline int
-intel_de_wait_for_register_fw(struct drm_i915_private *i915, i915_reg_t reg,
-			      u32 mask, u32 value, unsigned int timeout)
-{
-	return xe_mmio_wait32(to_gt(i915), reg.reg, value, mask, timeout * USEC_PER_MSEC, NULL,
-			      false);
-}
-
-static inline int
-__intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t reg,
-			     u32 mask, u32 value,
-			     unsigned int fast_timeout_us,
-			     unsigned int slow_timeout_ms, u32 *out_value)
-{
-	return xe_mmio_wait32(to_gt(i915), reg.reg, value, mask,
-			      fast_timeout_us + 1000 * slow_timeout_ms,
-			      out_value, false);
-}
-
-static inline int
-intel_de_wait_for_set(struct drm_i915_private *i915, i915_reg_t reg,
-		      u32 mask, unsigned int timeout)
-{
-	return intel_de_wait_for_register(i915, reg, mask, mask, timeout);
-}
-
-static inline int
-intel_de_wait_for_clear(struct drm_i915_private *i915, i915_reg_t reg,
-			u32 mask, unsigned int timeout)
-{
-	return intel_de_wait_for_register(i915, reg, mask, 0, timeout);
-}
-
-/*
- * Unlocked mmio-accessors, think carefully before using these.
- *
- * Certain architectures will die if the same cacheline is concurrently accessed
- * by different clients (e.g. on Ivybridge). Access to registers should
- * therefore generally be serialised, by either the dev_priv->uncore.lock or
- * a more localised lock guarding all access to that bank of registers.
- */
-static inline u32
-intel_de_read_fw(struct drm_i915_private *i915, i915_reg_t reg)
-{
-	return xe_mmio_read32(to_gt(i915), reg.reg);
-}
-
-static inline void
-intel_de_write_fw(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
-{
-	xe_mmio_write32(to_gt(i915), reg.reg, val);
-}
-
-static inline void
-intel_de_write_samevalue(struct drm_i915_private *i915, i915_reg_t reg)
-{
-	/*
-	 * Not implemented, requires lock on all reads/writes.
-	 * only required for really old FBC. Not ever going to be needed.
-	 */
-	XE_BUG_ON(1);
-}
-
-static inline u32
-intel_de_read_notrace(struct drm_i915_private *i915, i915_reg_t reg)
-{
-	return xe_mmio_read32(to_gt(i915), reg.reg);
-}
-
-static inline void
-intel_de_write_notrace(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
-{
-	xe_mmio_write32(to_gt(i915), reg.reg, val);
-}
-
-static inline int
-intel_de_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox, u32 val,
-			    int fast_timeout_us, int slow_timeout_ms)
-{
-	return xe_pcode_write_timeout(to_gt(i915), mbox, val,
-				       slow_timeout_ms ?: 1);
-}
-
-static inline int
-intel_de_pcode_write(struct drm_i915_private *i915, u32 mbox, u32 val)
-{
-
-	return xe_pcode_write(to_gt(i915), mbox, val);
-}
-
-static inline int
-intel_de_pcode_read(struct drm_i915_private *i915, u32 mbox, u32 *val, u32 *val1)
-{
-	return xe_pcode_read(to_gt(i915), mbox, val, val1);
-}
-
-static inline int intel_de_pcode_request(struct drm_i915_private *i915, u32 mbox,
-					 u32 request, u32 reply_mask, u32 reply,
-					 int timeout_base_ms)
-{
-	return xe_pcode_request(to_gt(i915), mbox, request, reply_mask, reply,
-				timeout_base_ms);
-}
-
-#endif /* __INTEL_DE_H__ */
-- 
2.39.2

[Intel-xe] [PATCH 06/18] fixup! drm/i915/display: Remaining changes to make xe compile

[Jani Nikula]

Use i915/display/intel_de.h for real.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_de.h | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h
index 5c223ff6b3ec..22907719bb1e 100644
--- a/drivers/gpu/drm/i915/display/intel_de.h
+++ b/drivers/gpu/drm/i915/display/intel_de.h
@@ -3,9 +3,6 @@
  * Copyright © 2019 Intel Corporation
  */
 
-#ifdef BUILD_FOR_XE
-#include_next "intel_de.h"
-#else
 #ifndef __INTEL_DE_H__
 #define __INTEL_DE_H__
 
@@ -177,4 +174,3 @@ static inline int intel_de_pcode_request(struct drm_i915_private *i915, u32 mbox
 }
 
 #endif /* __INTEL_DE_H__ */
-#endif
-- 
2.39.2

[Intel-xe] [PATCH 07/18] fixup! drm/xe/display: Implement display support

[Jani Nikula]

Remove -DBUILD_FOR_XE=1. No longer needed.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/xe/Makefile | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index e5130613a943..b6c41cd7dbe3 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -103,7 +103,6 @@ subdir-ccflags-$(CONFIG_DRM_XE_DISPLAY) += \
 	-I$(srctree)/$(src)/compat-i915-headers \
 	-I$(srctree)/drivers/gpu/drm/xe/display/ \
 	-I$(srctree)/drivers/gpu/drm/i915/display/ \
-	-DBUILD_FOR_XE=1 \
 	-Ddrm_i915_gem_object=xe_bo \
 	-Ddrm_i915_private=xe_device
 
-- 
2.39.2

[Intel-xe] [PATCH 08/18] fixup! drm/i915/display: Add more macros to remove all direct calls to uncore

[Jani Nikula]

Revert "drm/i915/display: Add more macros to remove all direct calls to
uncore". Remove the entire commit from history. Move to pcode glue
layer.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_de.h | 38 -------------------------
 1 file changed, 38 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h
index 22907719bb1e..ab711b2cba12 100644
--- a/drivers/gpu/drm/i915/display/intel_de.h
+++ b/drivers/gpu/drm/i915/display/intel_de.h
@@ -9,7 +9,6 @@
 #include "i915_drv.h"
 #include "i915_trace.h"
 #include "intel_uncore.h"
-#include "intel_pcode.h"
 
 static inline u32
 intel_de_read(struct drm_i915_private *i915, i915_reg_t reg)
@@ -136,41 +135,4 @@ intel_de_write_notrace(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
 	intel_uncore_write_notrace(&i915->uncore, reg, val);
 }
 
-static inline void
-intel_de_write_samevalue(struct drm_i915_private *i915, i915_reg_t reg)
-{
-	spin_lock_irq(&i915->uncore.lock);
-	intel_de_write_fw(i915, reg, intel_de_read_fw(i915, reg));
-	spin_unlock_irq(&i915->uncore.lock);
-}
-
-static inline int
-intel_de_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox, u32 val,
-			    int fast_timeout_us, int slow_timeout_ms)
-{
-	return snb_pcode_write_timeout(&i915->uncore, mbox, val,
-				       fast_timeout_us, slow_timeout_ms);
-}
-
-static inline int
-intel_de_pcode_write(struct drm_i915_private *i915, u32 mbox, u32 val)
-{
-
-	return snb_pcode_write(&i915->uncore, mbox, val);
-}
-
-static inline int
-intel_de_pcode_read(struct drm_i915_private *i915, u32 mbox, u32 *val, u32 *val1)
-{
-	return snb_pcode_read(&i915->uncore, mbox, val, val1);
-}
-
-static inline int intel_de_pcode_request(struct drm_i915_private *i915, u32 mbox,
-					 u32 request, u32 reply_mask, u32 reply,
-					 int timeout_base_ms)
-{
-	return skl_pcode_request(&i915->uncore, mbox, request, reply_mask, reply,
-				 timeout_base_ms);
-}
-
 #endif /* __INTEL_DE_H__ */
-- 
2.39.2

[Intel-xe] [PATCH 09/18] fixup! drm/i915/display: Remove all uncore mmio accesses in favor of intel_de

[Jani Nikula]

Revert "drm/i915/display: Remove all uncore mmio accesses in favor of
intel_de". Remove the entire commit from history.

Use the compat glue layers for uncore and pcode.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/hsw_ips.c        |  7 +--
 drivers/gpu/drm/i915/display/intel_bios.c     | 19 ++++----
 drivers/gpu/drm/i915/display/intel_bw.c       | 34 +++++++-------
 drivers/gpu/drm/i915/display/intel_cdclk.c    | 45 ++++++++++---------
 drivers/gpu/drm/i915/display/intel_display.c  |  1 +
 .../drm/i915/display/intel_display_power.c    |  3 +-
 .../i915/display/intel_display_power_well.c   |  7 +--
 drivers/gpu/drm/i915/display/intel_dpio_phy.c |  9 ++--
 drivers/gpu/drm/i915/display/intel_hdcp.c     |  9 ++--
 drivers/gpu/drm/i915/display/skl_watermark.c  | 22 ++++-----
 10 files changed, 81 insertions(+), 75 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c b/drivers/gpu/drm/i915/display/hsw_ips.c
index 825b24f3356f..8eca0de065b6 100644
--- a/drivers/gpu/drm/i915/display/hsw_ips.c
+++ b/drivers/gpu/drm/i915/display/hsw_ips.c
@@ -8,6 +8,7 @@
 #include "i915_reg.h"
 #include "intel_de.h"
 #include "intel_display_types.h"
+#include "intel_pcode.h"
 
 static void hsw_ips_enable(const struct intel_crtc_state *crtc_state)
 {
@@ -33,8 +34,8 @@ static void hsw_ips_enable(const struct intel_crtc_state *crtc_state)
 
 	if (IS_BROADWELL(i915)) {
 		drm_WARN_ON(&i915->drm,
-			    intel_de_pcode_write(i915, DISPLAY_IPS_CONTROL,
-						 val | IPS_PCODE_CONTROL));
+			    snb_pcode_write(&i915->uncore, DISPLAY_IPS_CONTROL,
+					    val | IPS_PCODE_CONTROL));
 		/*
 		 * Quoting Art Runyan: "its not safe to expect any particular
 		 * value in IPS_CTL bit 31 after enabling IPS through the
@@ -67,7 +68,7 @@ bool hsw_ips_disable(const struct intel_crtc_state *crtc_state)
 
 	if (IS_BROADWELL(i915)) {
 		drm_WARN_ON(&i915->drm,
-			    intel_de_pcode_write(i915, DISPLAY_IPS_CONTROL, 0));
+			    snb_pcode_write(&i915->uncore, DISPLAY_IPS_CONTROL, 0));
 		/*
 		 * Wait for PCODE to finish disabling IPS. The BSpec specified
 		 * 42ms timeout value leads to occasional timeouts so use 100ms
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 8176e9fe2864..75e69dffc5e9 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -31,7 +31,6 @@
 
 #include "i915_drv.h"
 #include "i915_reg.h"
-#include "intel_de.h"
 #include "intel_display.h"
 #include "intel_display_types.h"
 #include "intel_gmbus.h"
@@ -3039,16 +3038,16 @@ static struct vbt_header *spi_oprom_get_vbt(struct drm_i915_private *i915)
 	u16 vbt_size;
 	u32 *vbt;
 
-	static_region = intel_de_read(i915, SPI_STATIC_REGIONS);
+	static_region = intel_uncore_read(&i915->uncore, SPI_STATIC_REGIONS);
 	static_region &= OPTIONROM_SPI_REGIONID_MASK;
-	intel_de_write(i915, PRIMARY_SPI_REGIONID, static_region);
+	intel_uncore_write(&i915->uncore, PRIMARY_SPI_REGIONID, static_region);
 
-	oprom_offset = intel_de_read(i915, OROM_OFFSET);
+	oprom_offset = intel_uncore_read(&i915->uncore, OROM_OFFSET);
 	oprom_offset &= OROM_OFFSET_MASK;
 
 	for (count = 0; count < oprom_size; count += 4) {
-		intel_de_write(i915, PRIMARY_SPI_ADDRESS, oprom_offset + count);
-		data = intel_de_read(i915, PRIMARY_SPI_TRIGGER);
+		intel_uncore_write(&i915->uncore, PRIMARY_SPI_ADDRESS, oprom_offset + count);
+		data = intel_uncore_read(&i915->uncore, PRIMARY_SPI_TRIGGER);
 
 		if (data == *((const u32 *)"$VBT")) {
 			found = oprom_offset + count;
@@ -3060,9 +3059,9 @@ static struct vbt_header *spi_oprom_get_vbt(struct drm_i915_private *i915)
 		goto err_not_found;
 
 	/* Get VBT size and allocate space for the VBT */
-	intel_de_write(i915, PRIMARY_SPI_ADDRESS, found +
+	intel_uncore_write(&i915->uncore, PRIMARY_SPI_ADDRESS, found +
 		   offsetof(struct vbt_header, vbt_size));
-	vbt_size = intel_de_read(i915, PRIMARY_SPI_TRIGGER);
+	vbt_size = intel_uncore_read(&i915->uncore, PRIMARY_SPI_TRIGGER);
 	vbt_size &= 0xffff;
 
 	vbt = kzalloc(round_up(vbt_size, 4), GFP_KERNEL);
@@ -3070,8 +3069,8 @@ static struct vbt_header *spi_oprom_get_vbt(struct drm_i915_private *i915)
 		goto err_not_found;
 
 	for (count = 0; count < vbt_size; count += 4) {
-		intel_de_write(i915, PRIMARY_SPI_ADDRESS, found + count);
-		data = intel_de_read(i915, PRIMARY_SPI_TRIGGER);
+		intel_uncore_write(&i915->uncore, PRIMARY_SPI_ADDRESS, found + count);
+		data = intel_uncore_read(&i915->uncore, PRIMARY_SPI_TRIGGER);
 		*(vbt + store++) = data;
 	}
 
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 171a341e1150..597d5816ad1b 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -11,11 +11,11 @@
 #include "intel_atomic.h"
 #include "intel_bw.h"
 #include "intel_cdclk.h"
-#include "intel_de.h"
 #include "intel_display_core.h"
 #include "intel_display_types.h"
 #include "skl_watermark.h"
 #include "intel_mchbar_regs.h"
+#include "intel_pcode.h"
 
 /* Parameters for Qclk Geyserville (QGV) */
 struct intel_qgv_point {
@@ -44,7 +44,7 @@ static int dg1_mchbar_read_qgv_point_info(struct drm_i915_private *dev_priv,
 	u32 dclk_ratio, dclk_reference;
 	u32 val;
 
-	val = intel_de_read(dev_priv, SA_PERF_STATUS_0_0_0_MCHBAR_PC);
+	val = intel_uncore_read(&dev_priv->uncore, SA_PERF_STATUS_0_0_0_MCHBAR_PC);
 	dclk_ratio = REG_FIELD_GET(DG1_QCLK_RATIO_MASK, val);
 	if (val & DG1_QCLK_REFERENCE)
 		dclk_reference = 6; /* 6 * 16.666 MHz = 100 MHz */
@@ -52,18 +52,18 @@ static int dg1_mchbar_read_qgv_point_info(struct drm_i915_private *dev_priv,
 		dclk_reference = 8; /* 8 * 16.666 MHz = 133 MHz */
 	sp->dclk = DIV_ROUND_UP((16667 * dclk_ratio * dclk_reference) + 500, 1000);
 
-	val = intel_de_read(dev_priv, SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
+	val = intel_uncore_read(&dev_priv->uncore, SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
 	if (val & DG1_GEAR_TYPE)
 		sp->dclk *= 2;
 
 	if (sp->dclk == 0)
 		return -EINVAL;
 
-	val = intel_de_read(dev_priv, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR);
+	val = intel_uncore_read(&dev_priv->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR);
 	sp->t_rp = REG_FIELD_GET(DG1_DRAM_T_RP_MASK, val);
 	sp->t_rdpre = REG_FIELD_GET(DG1_DRAM_T_RDPRE_MASK, val);
 
-	val = intel_de_read(dev_priv, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH);
+	val = intel_uncore_read(&dev_priv->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH);
 	sp->t_rcd = REG_FIELD_GET(DG1_DRAM_T_RCD_MASK, val);
 	sp->t_ras = REG_FIELD_GET(DG1_DRAM_T_RAS_MASK, val);
 
@@ -80,9 +80,9 @@ static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
 	u16 dclk;
 	int ret;
 
-	ret = intel_de_pcode_read(dev_priv, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
-				  ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point),
-				  &val, &val2);
+	ret = snb_pcode_read(&dev_priv->uncore, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
+			     ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point),
+			     &val, &val2);
 	if (ret)
 		return ret;
 
@@ -106,8 +106,8 @@ static int adls_pcode_read_psf_gv_point_info(struct drm_i915_private *dev_priv,
 	int ret;
 	int i;
 
-	ret = intel_de_pcode_read(dev_priv, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
-				  ADL_PCODE_MEM_SS_READ_PSF_GV_INFO, &val, NULL);
+	ret = snb_pcode_read(&dev_priv->uncore, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
+			     ADL_PCODE_MEM_SS_READ_PSF_GV_INFO, &val, NULL);
 	if (ret)
 		return ret;
 
@@ -154,11 +154,11 @@ int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
 		return 0;
 
 	/* bspec says to keep retrying for at least 1 ms */
-	ret = intel_de_pcode_request(dev_priv, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
-				     points_mask,
-				     ICL_PCODE_REP_QGV_MASK | ADLS_PCODE_REP_PSF_MASK,
-				     ICL_PCODE_REP_QGV_SAFE | ADLS_PCODE_REP_PSF_SAFE,
-				     1);
+	ret = skl_pcode_request(&dev_priv->uncore, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
+				points_mask,
+				ICL_PCODE_REP_QGV_MASK | ADLS_PCODE_REP_PSF_MASK,
+				ICL_PCODE_REP_QGV_SAFE | ADLS_PCODE_REP_PSF_SAFE,
+				1);
 
 	if (ret < 0) {
 		drm_err(&dev_priv->drm, "Failed to disable qgv points (%d) points: 0x%x\n", ret, points_mask);
@@ -177,9 +177,9 @@ static int mtl_read_qgv_point_info(struct drm_i915_private *dev_priv,
 	u32 val, val2;
 	u16 dclk;
 
-	val = intel_de_read(dev_priv,
+	val = intel_uncore_read(&dev_priv->uncore,
 				MTL_MEM_SS_INFO_QGV_POINT_LOW(point));
-	val2 = intel_de_read(dev_priv,
+	val2 = intel_uncore_read(&dev_priv->uncore,
 				 MTL_MEM_SS_INFO_QGV_POINT_HIGH(point));
 	dclk = REG_FIELD_GET(MTL_DCLK_MASK, val);
 	sp->dclk = DIV_ROUND_UP((16667 * dclk), 1000);
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index e719bb8fc1f6..f6223d8f13b8 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -35,6 +35,7 @@
 #include "intel_display_types.h"
 #include "intel_mchbar_regs.h"
 #include "intel_pci_config.h"
+#include "intel_pcode.h"
 #include "intel_psr.h"
 #include "vlv_sideband.h"
 
@@ -800,7 +801,7 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
 		     "trying to change cdclk frequency with cdclk not enabled\n"))
 		return;
 
-	ret = intel_de_pcode_write(dev_priv, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
+	ret = snb_pcode_write(&dev_priv->uncore, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
 	if (ret) {
 		drm_err(&dev_priv->drm,
 			"failed to inform pcode about cdclk change\n");
@@ -828,8 +829,8 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
 			 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
 		drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n");
 
-	intel_de_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
-			     cdclk_config->voltage_level);
+	snb_pcode_write(&dev_priv->uncore, HSW_PCODE_DE_WRITE_FREQ_REQ,
+			cdclk_config->voltage_level);
 
 	intel_de_write(dev_priv, CDCLK_FREQ,
 		       DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
@@ -1086,10 +1087,10 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
 	drm_WARN_ON_ONCE(&dev_priv->drm,
 			 IS_SKYLAKE(dev_priv) && vco == 8640000);
 
-	ret = intel_de_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
-				     SKL_CDCLK_PREPARE_FOR_CHANGE,
-				     SKL_CDCLK_READY_FOR_CHANGE,
-				     SKL_CDCLK_READY_FOR_CHANGE, 3);
+	ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
+				SKL_CDCLK_PREPARE_FOR_CHANGE,
+				SKL_CDCLK_READY_FOR_CHANGE,
+				SKL_CDCLK_READY_FOR_CHANGE, 3);
 	if (ret) {
 		drm_err(&dev_priv->drm,
 			"Failed to inform PCU about cdclk change (%d)\n", ret);
@@ -1132,8 +1133,8 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
 	intel_de_posting_read(dev_priv, CDCLK_CTL);
 
 	/* inform PCU of the change */
-	intel_de_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
-			     cdclk_config->voltage_level);
+	snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
+			cdclk_config->voltage_level);
 
 	intel_update_cdclk(dev_priv);
 }
@@ -1898,18 +1899,18 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 	if (DISPLAY_VER(dev_priv) >= 14)
 		/* NOOP */;
 	else if (DISPLAY_VER(dev_priv) >= 11)
-		ret = intel_de_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
-					     SKL_CDCLK_PREPARE_FOR_CHANGE,
-					     SKL_CDCLK_READY_FOR_CHANGE,
-					     SKL_CDCLK_READY_FOR_CHANGE, 3);
+		ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
+					SKL_CDCLK_PREPARE_FOR_CHANGE,
+					SKL_CDCLK_READY_FOR_CHANGE,
+					SKL_CDCLK_READY_FOR_CHANGE, 3);
 	else
 		/*
 		 * BSpec requires us to wait up to 150usec, but that leads to
 		 * timeouts; the 2ms used here is based on experiment.
 		 */
-		ret = intel_de_pcode_write_timeout(dev_priv,
-						   HSW_PCODE_DE_WRITE_FREQ_REQ,
-						   0x80000000, 150, 2);
+		ret = snb_pcode_write_timeout(&dev_priv->uncore,
+					      HSW_PCODE_DE_WRITE_FREQ_REQ,
+					      0x80000000, 150, 2);
 
 	if (ret) {
 		drm_err(&dev_priv->drm,
@@ -1932,8 +1933,8 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 		 * Display versions 14 and beyond
 		 */;
 	else if (DISPLAY_VER(dev_priv) >= 11)
-		ret = intel_de_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
-					   cdclk_config->voltage_level);
+		ret = snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
+				      cdclk_config->voltage_level);
 	else
 		/*
 		 * The timeout isn't specified, the 2ms used here is based on
@@ -1941,10 +1942,10 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 		 * FIXME: Waiting for the request completion could be delayed
 		 * until the next PCODE request based on BSpec.
 		 */
-		ret = intel_de_pcode_write_timeout(dev_priv,
-						   HSW_PCODE_DE_WRITE_FREQ_REQ,
-						   cdclk_config->voltage_level,
-						   150, 2);
+		ret = snb_pcode_write_timeout(&dev_priv->uncore,
+					      HSW_PCODE_DE_WRITE_FREQ_REQ,
+					      cdclk_config->voltage_level,
+					      150, 2);
 
 	if (ret) {
 		drm_err(&dev_priv->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 719e08d06a98..960f31a75e39 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -98,6 +98,7 @@
 #include "intel_panel.h"
 #include "intel_pch_display.h"
 #include "intel_pch_refclk.h"
+#include "intel_pcode.h"
 #include "intel_pipe_crc.h"
 #include "intel_plane_initial.h"
 #include "intel_pps.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 4a5e90c71554..177c85c598a4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -19,6 +19,7 @@
 #include "intel_dmc.h"
 #include "intel_mchbar_regs.h"
 #include "intel_pch_refclk.h"
+#include "intel_pcode.h"
 #include "intel_pps_regs.h"
 #include "intel_snps_phy.h"
 #include "skl_watermark.h"
@@ -1210,7 +1211,7 @@ static u32 hsw_read_dcomp(struct drm_i915_private *dev_priv)
 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, u32 val)
 {
 	if (IS_HASWELL(dev_priv)) {
-		if (intel_de_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
+		if (snb_pcode_write(&dev_priv->uncore, GEN6_PCODE_WRITE_D_COMP, val))
 			drm_dbg_kms(&dev_priv->drm,
 				    "Failed to write to D_COMP\n");
 	} else {
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 45ca3cc1dcee..41eabdf3e871 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -20,6 +20,7 @@
 #include "intel_dpio_phy.h"
 #include "intel_dpll.h"
 #include "intel_hotplug.h"
+#include "intel_pcode.h"
 #include "intel_pps.h"
 #include "intel_tc.h"
 #include "intel_vga.h"
@@ -474,8 +475,8 @@ static void icl_tc_cold_exit(struct drm_i915_private *i915)
 	int ret, tries = 0;
 
 	while (1) {
-		ret = intel_de_pcode_write_timeout(i915, ICL_PCODE_EXIT_TCCOLD, 0,
-						   250, 1);
+		ret = snb_pcode_write_timeout(&i915->uncore, ICL_PCODE_EXIT_TCCOLD, 0,
+					      250, 1);
 		if (ret != -EAGAIN || ++tries == 3)
 			break;
 		msleep(1);
@@ -1730,7 +1731,7 @@ tgl_tc_cold_request(struct drm_i915_private *i915, bool block)
 		 * Spec states that we should timeout the request after 200us
 		 * but the function below will timeout after 500us
 		 */
-		ret = intel_de_pcode_read(i915, TGL_PCODE_TCCOLD, &low_val, &high_val);
+		ret = snb_pcode_read(&i915->uncore, TGL_PCODE_TCCOLD, &low_val, &high_val);
 		if (ret == 0) {
 			if (block &&
 			    (low_val & TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED))
diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index 5b500cf53b51..62b93d097e44 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -399,10 +399,11 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
 	 * The flag should get set in 100us according to the HW team, but
 	 * use 1ms due to occasional timeouts observed with that.
 	 */
-	if (intel_de_wait_for_register_fw(dev_priv,
-					  BXT_PORT_CL1CM_DW0(phy),
-					  PHY_RESERVED | PHY_POWER_GOOD,
-					  PHY_POWER_GOOD, 1))
+	if (intel_wait_for_register_fw(&dev_priv->uncore,
+				       BXT_PORT_CL1CM_DW0(phy),
+				       PHY_RESERVED | PHY_POWER_GOOD,
+				       PHY_POWER_GOOD,
+				       1))
 		drm_err(&dev_priv->drm, "timeout during PHY%d power on\n",
 			phy);
 
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index b4f3489b9201..0c2ddbef5cfe 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -25,6 +25,7 @@
 #include "intel_hdcp.h"
 #include "intel_hdcp_gsc.h"
 #include "intel_hdcp_regs.h"
+#include "intel_pcode.h"
 
 #define KEY_LOAD_TRIES	5
 #define HDCP2_LC_RETRY_CNT			3
@@ -335,7 +336,7 @@ static int intel_hdcp_load_keys(struct drm_i915_private *dev_priv)
 	 * Mailbox interface.
 	 */
 	if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) {
-		ret = intel_de_pcode_write(dev_priv, SKL_PCODE_LOAD_HDCP_KEYS, 1);
+		ret = snb_pcode_write(&dev_priv->uncore, SKL_PCODE_LOAD_HDCP_KEYS, 1);
 		if (ret) {
 			drm_err(&dev_priv->drm,
 				"Failed to initiate HDCP key load (%d)\n",
@@ -347,9 +348,9 @@ static int intel_hdcp_load_keys(struct drm_i915_private *dev_priv)
 	}
 
 	/* Wait for the keys to load (500us) */
-	ret = __intel_de_wait_for_register(dev_priv, HDCP_KEY_STATUS,
-					   HDCP_KEY_LOAD_DONE, HDCP_KEY_LOAD_DONE,
-					   10, 1, &val);
+	ret = __intel_wait_for_register(&dev_priv->uncore, HDCP_KEY_STATUS,
+					HDCP_KEY_LOAD_DONE, HDCP_KEY_LOAD_DONE,
+					10, 1, &val);
 	if (ret)
 		return ret;
 	else if (!(val & HDCP_KEY_LOAD_STATUS))
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index f7b32823a9a9..0008676217b2 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -82,9 +82,9 @@ intel_sagv_block_time(struct drm_i915_private *i915)
 		u32 val = 0;
 		int ret;
 
-		ret = intel_de_pcode_read(i915,
-					  GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
-					  &val, NULL);
+		ret = snb_pcode_read(&i915->uncore,
+				     GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
+				     &val, NULL);
 		if (ret) {
 			drm_dbg_kms(&i915->drm, "Couldn't read SAGV block time!\n");
 			return 0;
@@ -151,8 +151,8 @@ static void skl_sagv_enable(struct drm_i915_private *i915)
 		return;
 
 	drm_dbg_kms(&i915->drm, "Enabling SAGV\n");
-	ret = intel_de_pcode_write(i915, GEN9_PCODE_SAGV_CONTROL,
-				   GEN9_SAGV_ENABLE);
+	ret = snb_pcode_write(&i915->uncore, GEN9_PCODE_SAGV_CONTROL,
+			      GEN9_SAGV_ENABLE);
 
 	/* We don't need to wait for SAGV when enabling */
 
@@ -184,10 +184,10 @@ static void skl_sagv_disable(struct drm_i915_private *i915)
 
 	drm_dbg_kms(&i915->drm, "Disabling SAGV\n");
 	/* bspec says to keep retrying for at least 1 ms */
-	ret = intel_de_pcode_request(i915, GEN9_PCODE_SAGV_CONTROL,
-				     GEN9_SAGV_DISABLE,
-				     GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED,
-				     1);
+	ret = skl_pcode_request(&i915->uncore, GEN9_PCODE_SAGV_CONTROL,
+				GEN9_SAGV_DISABLE,
+				GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED,
+				1);
 	/*
 	 * Some skl systems, pre-release machines in particular,
 	 * don't actually have SAGV.
@@ -3364,7 +3364,7 @@ static void skl_read_wm_latency(struct drm_i915_private *i915, u16 wm[])
 
 	/* read the first set of memory latencies[0:3] */
 	val = 0; /* data0 to be programmed to 0 for first set */
-	ret = intel_de_pcode_read(i915, GEN9_PCODE_READ_MEM_LATENCY, &val, NULL);
+	ret = snb_pcode_read(&i915->uncore, GEN9_PCODE_READ_MEM_LATENCY, &val, NULL);
 	if (ret) {
 		drm_err(&i915->drm, "SKL Mailbox read error = %d\n", ret);
 		return;
@@ -3377,7 +3377,7 @@ static void skl_read_wm_latency(struct drm_i915_private *i915, u16 wm[])
 
 	/* read the second set of memory latencies[4:7] */
 	val = 1; /* data0 to be programmed to 1 for second set */
-	ret = intel_de_pcode_read(i915, GEN9_PCODE_READ_MEM_LATENCY, &val, NULL);
+	ret = snb_pcode_read(&i915->uncore, GEN9_PCODE_READ_MEM_LATENCY, &val, NULL);
 	if (ret) {
 		drm_err(&i915->drm, "SKL Mailbox read error = %d\n", ret);
 		return;
-- 
2.39.2

[Intel-xe] [PATCH 10/18] fixup! drm/i915/display: Remaining changes to make xe compile

[Jani Nikula]

This is unused.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_de.h | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h
index ab711b2cba12..e858011efa02 100644
--- a/drivers/gpu/drm/i915/display/intel_de.h
+++ b/drivers/gpu/drm/i915/display/intel_de.h
@@ -22,12 +22,6 @@ intel_de_read8(struct drm_i915_private *i915, i915_reg_t reg)
 	return intel_uncore_read8(&i915->uncore, reg);
 }
 
-static inline u8
-intel_de_read64(struct drm_i915_private *i915, i915_reg_t reg)
-{
-	return intel_uncore_read64(&i915->uncore, reg);
-}
-
 static inline u64
 intel_de_read64_2x32(struct drm_i915_private *i915,
 		     i915_reg_t lower_reg, i915_reg_t upper_reg)
-- 
2.39.2

[Intel-xe] [PATCH 11/18] fixup! drm/xe: Introduce a new DRM driver for Intel GPUs

[Jani Nikula]

Add the read8 accessor to support intel_de_read8.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/xe/xe_mmio.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_mmio.h b/drivers/gpu/drm/xe/xe_mmio.h
index 1a32e0f52261..b72a0a75259f 100644
--- a/drivers/gpu/drm/xe/xe_mmio.h
+++ b/drivers/gpu/drm/xe/xe_mmio.h
@@ -17,6 +17,14 @@ struct xe_device;
 
 int xe_mmio_init(struct xe_device *xe);
 
+static inline u8 xe_mmio_read8(struct xe_gt *gt, u32 reg)
+{
+	if (reg < gt->mmio.adj_limit)
+		reg += gt->mmio.adj_offset;
+
+	return readb(gt->mmio.regs + reg);
+}
+
 static inline void xe_mmio_write32(struct xe_gt *gt,
 				   u32 reg, u32 val)
 {
-- 
2.39.2

Re: [Intel-xe] [PATCH 11/18] fixup! drm/xe: Introduce a new DRM driver for Intel GPUs

[Matt Roper]

On Mon, May 08, 2023 at 05:46:11PM +0300, Jani Nikula wrote:
> Add the read8 accessor to support intel_de_read8.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_mmio.h | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_mmio.h b/drivers/gpu/drm/xe/xe_mmio.h
> index 1a32e0f52261..b72a0a75259f 100644
> --- a/drivers/gpu/drm/xe/xe_mmio.h
> +++ b/drivers/gpu/drm/xe/xe_mmio.h
> @@ -17,6 +17,14 @@ struct xe_device;
>  
>  int xe_mmio_init(struct xe_device *xe);
>  
> +static inline u8 xe_mmio_read8(struct xe_gt *gt, u32 reg)
> +{
> +	if (reg < gt->mmio.adj_limit)
> +		reg += gt->mmio.adj_offset;

This could probably be a warn_on; as far as I know, there are no 8-bit
registers in the GT, so if we wind up trying to read sgunit or display
registers through a media GT's pointer it's a clue that something has
probably gone wrong.

Of course this MMIO stuff is a confusing mess due to the fact that xe_gt
is being used all over the driver for things that are completely
unrelated to any GT.  After cleaning up the GT vs tile mess, I plan to
work on coming up with something more sane for MMIO windows too.  I'm
thinking something like a "struct xe_mmio_view" that will replace xe_gt
as the first parameter to the xe_mmio_* functions and can provide them
with additional information to also do range validation on debug builds
to ensure you're accessing the subset of registers you think you are,
and functions to hand you an appropriate xe_mmio_view:
 - xe_mmio_for_display(xe): warns if read/write outside display range
 - xe_mmio_for_gt(gt): warns if read/write outside a GT range; if media
   GT is the parameter, also warns if outside the GSI range or one of
   the media engines
 - xe_mmio_for_tile(tile):  unrestricted MMIO access for a tile, mostly
   intended for use with sgunit, soc, etc. registers that are outside
   the GT


Matt

> +
> +	return readb(gt->mmio.regs + reg);
> +}
> +
>  static inline void xe_mmio_write32(struct xe_gt *gt,
>  				   u32 reg, u32 val)
>  {
> -- 
> 2.39.2
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-xe] [PATCH 11/18] fixup! drm/xe: Introduce a new DRM driver for Intel GPUs

[Jani Nikula]

On Mon, 08 May 2023, Matt Roper <matthew.d.roper@intel.com> wrote:
> On Mon, May 08, 2023 at 05:46:11PM +0300, Jani Nikula wrote:
>> Add the read8 accessor to support intel_de_read8.
>> 
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>>  drivers/gpu/drm/xe/xe_mmio.h | 8 ++++++++
>>  1 file changed, 8 insertions(+)
>> 
>> diff --git a/drivers/gpu/drm/xe/xe_mmio.h b/drivers/gpu/drm/xe/xe_mmio.h
>> index 1a32e0f52261..b72a0a75259f 100644
>> --- a/drivers/gpu/drm/xe/xe_mmio.h
>> +++ b/drivers/gpu/drm/xe/xe_mmio.h
>> @@ -17,6 +17,14 @@ struct xe_device;
>>  
>>  int xe_mmio_init(struct xe_device *xe);
>>  
>> +static inline u8 xe_mmio_read8(struct xe_gt *gt, u32 reg)
>> +{
>> +	if (reg < gt->mmio.adj_limit)
>> +		reg += gt->mmio.adj_offset;
>
> This could probably be a warn_on; as far as I know, there are no 8-bit
> registers in the GT, so if we wind up trying to read sgunit or display
> registers through a media GT's pointer it's a clue that something has
> probably gone wrong.

Looks like Rodrigo already pushed this, so this would need to be added
separately.

> Of course this MMIO stuff is a confusing mess due to the fact that xe_gt
> is being used all over the driver for things that are completely
> unrelated to any GT.

This. The abstractions don't match reality.


BR,
Jani.


> After cleaning up the GT vs tile mess, I plan to
> work on coming up with something more sane for MMIO windows too.  I'm
> thinking something like a "struct xe_mmio_view" that will replace xe_gt
> as the first parameter to the xe_mmio_* functions and can provide them
> with additional information to also do range validation on debug builds
> to ensure you're accessing the subset of registers you think you are,
> and functions to hand you an appropriate xe_mmio_view:
>  - xe_mmio_for_display(xe): warns if read/write outside display range
>  - xe_mmio_for_gt(gt): warns if read/write outside a GT range; if media
>    GT is the parameter, also warns if outside the GSI range or one of
>    the media engines
>  - xe_mmio_for_tile(tile):  unrestricted MMIO access for a tile, mostly
>    intended for use with sgunit, soc, etc. registers that are outside
>    the GT
>
>
> Matt
>
>> +
>> +	return readb(gt->mmio.regs + reg);
>> +}
>> +
>>  static inline void xe_mmio_write32(struct xe_gt *gt,
>>  				   u32 reg, u32 val)
>>  {
>> -- 
>> 2.39.2
>> 

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-xe] [PATCH 12/18] fixup! drm/xe/display: Implement display support

[Jani Nikula]

Add compat intel_pcode.h glue layer.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 .../drm/xe/compat-i915-headers/intel_pcode.h  | 42 +++++++++++++++++++
 1 file changed, 42 insertions(+)
 create mode 100644 drivers/gpu/drm/xe/compat-i915-headers/intel_pcode.h

diff --git a/drivers/gpu/drm/xe/compat-i915-headers/intel_pcode.h b/drivers/gpu/drm/xe/compat-i915-headers/intel_pcode.h
new file mode 100644
index 000000000000..71f1fd1de2fd
--- /dev/null
+++ b/drivers/gpu/drm/xe/compat-i915-headers/intel_pcode.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#ifndef __INTEL_PCODE_H__
+#define __INTEL_PCODE_H__
+
+#include "intel_uncore.h"
+#include "xe_pcode.h"
+
+static inline int
+snb_pcode_write_timeout(struct fake_uncore *uncore, u32 mbox, u32 val,
+			int fast_timeout_us, int slow_timeout_ms)
+{
+	return xe_pcode_write_timeout(__fake_uncore_to_gt(uncore), mbox, val,
+				      slow_timeout_ms ?: 1);
+}
+
+static inline int
+snb_pcode_write(struct fake_uncore *uncore, u32 mbox, u32 val)
+{
+
+	return xe_pcode_write(__fake_uncore_to_gt(uncore), mbox, val);
+}
+
+static inline int
+snb_pcode_read(struct fake_uncore *uncore, u32 mbox, u32 *val, u32 *val1)
+{
+	return xe_pcode_read(__fake_uncore_to_gt(uncore), mbox, val, val1);
+}
+
+static inline int
+skl_pcode_request(struct fake_uncore *uncore, u32 mbox,
+		  u32 request, u32 reply_mask, u32 reply,
+		  int timeout_base_ms)
+{
+	return xe_pcode_request(__fake_uncore_to_gt(uncore), mbox, request, reply_mask, reply,
+				timeout_base_ms);
+}
+
+#endif /* __INTEL_PCODE_H__ */
-- 
2.39.2

[Intel-xe] [PATCH 13/18] fixup! drm/i915/display: Remaining changes to make xe compile

[Jani Nikula]

Restore a removed include.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 0008676217b2..1c7e6468f3e3 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -18,6 +18,7 @@
 #include "intel_display_power.h"
 #include "intel_display_types.h"
 #include "intel_fb.h"
+#include "intel_pcode.h"
 #include "intel_wm.h"
 #include "skl_watermark.h"
 #include "skl_watermark_regs.h"
-- 
2.39.2

[Intel-xe] [PATCH 14/18] fixup! drm/i915/display: Remaining changes to make xe compile

[Jani Nikula]

Remove an unused function.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_de.h | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h
index e858011efa02..42552d8c151e 100644
--- a/drivers/gpu/drm/i915/display/intel_de.h
+++ b/drivers/gpu/drm/i915/display/intel_de.h
@@ -111,12 +111,6 @@ intel_de_write_fw(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
 	intel_uncore_write_fw(&i915->uncore, reg, val);
 }
 
-static inline void
-intel_de_posting_read_fw(struct drm_i915_private *i915, i915_reg_t reg)
-{
-	intel_uncore_posting_read_fw(&i915->uncore, reg);
-}
-
 static inline u32
 intel_de_read_notrace(struct drm_i915_private *i915, i915_reg_t reg)
 {
-- 
2.39.2

[Intel-xe] [PATCH 15/18] fixup! drm/xe/display: Implement display support

[Jani Nikula]

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/xe/display/ext/intel_clock_gating.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/xe/display/ext/intel_clock_gating.c b/drivers/gpu/drm/xe/display/ext/intel_clock_gating.c
index 7d1854652d17..0d67b0961d74 100644
--- a/drivers/gpu/drm/xe/display/ext/intel_clock_gating.c
+++ b/drivers/gpu/drm/xe/display/ext/intel_clock_gating.c
@@ -29,6 +29,7 @@
 #include "intel_display_trace.h"
 
 #include "i915_drv.h"
+#include "i915_reg.h"
 #include "intel_clock_gating.h"
 #include "intel_mchbar_regs.h"
 
-- 
2.39.2

[Intel-xe] [PATCH 16/18] fixup! drm/xe/display: Implement display support

[Jani Nikula]

There are some implicit dependences on i915_drv.h -> intel_uncore.h in
i915, work around them.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
index b55a42f06862..ddc0ad39b154 100644
--- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
+++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
@@ -17,6 +17,7 @@
 #include "i915_reg_defs.h"
 #include "intel_pch.h"
 #include "i915_utils.h"
+#include "intel_uncore.h"
 #include <linux/pm_runtime.h>
 
 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
-- 
2.39.2

[Intel-xe] [PATCH 17/18] fixup! drm/xe/display: Implement display support

[Jani Nikula]

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/xe/display/ext/intel_device_info.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/xe/display/ext/intel_device_info.c b/drivers/gpu/drm/xe/display/ext/intel_device_info.c
index 9e6844311ace..9a54611037b5 100644
--- a/drivers/gpu/drm/xe/display/ext/intel_device_info.c
+++ b/drivers/gpu/drm/xe/display/ext/intel_device_info.c
@@ -27,6 +27,7 @@
 #include "intel_display.h"
 #include "intel_device_info.h"
 #include "i915_drv.h"
+#include "i915_reg.h"
 #include <drm/drm_drv.h>
 
 /**
-- 
2.39.2

[Intel-xe] [PATCH 18/18] fixup! drm/xe/display: Implement display support

[Jani Nikula]

Use the compat glue layer pcode functions.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/xe/display/ext/intel_dram.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/display/ext/intel_dram.c b/drivers/gpu/drm/xe/display/ext/intel_dram.c
index a2df0c502c34..3e8c413280a5 100644
--- a/drivers/gpu/drm/xe/display/ext/intel_dram.c
+++ b/drivers/gpu/drm/xe/display/ext/intel_dram.c
@@ -10,6 +10,7 @@
 #include "intel_de.h"
 #include "intel_dram.h"
 #include "intel_mchbar_regs.h"
+#include "intel_pcode.h"
 
 struct dram_dimm_info {
 	u16 size;
@@ -390,7 +391,7 @@ static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv)
 	u32 val = 0;
 	int ret;
 
-	ret = intel_de_pcode_read(dev_priv, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
+	ret = snb_pcode_read(&dev_priv->uncore, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
 			     ICL_PCODE_MEM_SS_READ_GLOBAL_INFO, &val, NULL);
 	if (ret)
 		return ret;
-- 
2.39.2

[Intel-xe] ✓ CI.Patch_applied: success for xe&i915 display integration: add uncore and pcode compat layers (rev2)

[Patchwork]

== Series Details ==

Series: xe&i915 display integration: add uncore and pcode compat layers (rev2)
URL   : https://patchwork.freedesktop.org/series/117238/
State : success

== Summary ==

=== Applying kernel patches on branch 'drm-xe-next' with base: ===
Base commit: 181b15c86 drm/xe: Print GT info on TLB inv failure
=== git am output follows ===
Applying: fixup! drm/xe/display: Implement display support
Applying: fixup! drm/xe/display: Implement display support
Applying: fixup! drm/xe/display: Implement display support
Applying: fixup! drm/xe/display: Rename intel_de.h to xe_de.h
Applying: fixup! drm/xe/display: Implement display support
Applying: fixup! drm/i915/display: Remaining changes to make xe compile
Applying: fixup! drm/xe/display: Implement display support
Applying: fixup! drm/i915/display: Add more macros to remove all direct calls to uncore
Applying: fixup! drm/i915/display: Remove all uncore mmio accesses in favor of intel_de
Applying: fixup! drm/i915/display: Remaining changes to make xe compile
Applying: fixup! drm/xe: Introduce a new DRM driver for Intel GPUs
Applying: fixup! drm/xe/display: Implement display support
Applying: fixup! drm/i915/display: Remaining changes to make xe compile
Applying: fixup! drm/i915/display: Remaining changes to make xe compile
Applying: fixup! drm/xe/display: Implement display support
Applying: fixup! drm/xe/display: Implement display support
Applying: fixup! drm/xe/display: Implement display support
Applying: fixup! drm/xe/display: Implement display support

Re: [Intel-xe] [PATCH 00/18] xe&i915 display integration: add uncore and pcode compat layers

[Rodrigo Vivi]

On Mon, May 08, 2023 at 05:46:00PM +0300, Jani Nikula wrote:
> v2 of
> https://lore.kernel.org/r/20230503131005.1602412-1-jani.nikula@intel.com
> 
> - rebase
> - fix rmw now that xe follows i915 rmw arguments

Thanks for the rebase.
I tested here on my DG2 and pushed as is to drm-xe-next.

I will soon perform the rebase --auto-squash rounds...

> 
> 
> Jani Nikula (18):
>   fixup! drm/xe/display: Implement display support
>   fixup! drm/xe/display: Implement display support
>   fixup! drm/xe/display: Implement display support
>   fixup! drm/xe/display: Rename intel_de.h to xe_de.h
>   fixup! drm/xe/display: Implement display support
>   fixup! drm/i915/display: Remaining changes to make xe compile
>   fixup! drm/xe/display: Implement display support
>   fixup! drm/i915/display: Add more macros to remove all direct calls to
>     uncore
>   fixup! drm/i915/display: Remove all uncore mmio accesses in favor of
>     intel_de
>   fixup! drm/i915/display: Remaining changes to make xe compile
>   fixup! drm/xe: Introduce a new DRM driver for Intel GPUs
>   fixup! drm/xe/display: Implement display support
>   fixup! drm/i915/display: Remaining changes to make xe compile
>   fixup! drm/i915/display: Remaining changes to make xe compile
>   fixup! drm/xe/display: Implement display support
>   fixup! drm/xe/display: Implement display support
>   fixup! drm/xe/display: Implement display support
>   fixup! drm/xe/display: Implement display support
> 
>  drivers/gpu/drm/i915/display/hsw_ips.c        |   7 +-
>  drivers/gpu/drm/i915/display/intel_bios.c     |  19 +-
>  drivers/gpu/drm/i915/display/intel_bw.c       |  34 ++--
>  drivers/gpu/drm/i915/display/intel_cdclk.c    |  45 ++---
>  drivers/gpu/drm/i915/display/intel_de.h       |  54 ------
>  drivers/gpu/drm/i915/display/intel_display.c  |   1 +
>  .../drm/i915/display/intel_display_power.c    |   3 +-
>  .../i915/display/intel_display_power_well.c   |   7 +-
>  drivers/gpu/drm/i915/display/intel_dpio_phy.c |   9 +-
>  drivers/gpu/drm/i915/display/intel_hdcp.c     |   9 +-
>  drivers/gpu/drm/i915/display/skl_watermark.c  |  23 +--
>  .../gpu/drm/xe/compat-i915-headers/i915_drv.h |   1 +
>  .../drm/xe/compat-i915-headers/intel_pcode.h  |  42 +++++
>  .../drm/xe/compat-i915-headers/intel_uncore.h |  98 +++++++++++
>  drivers/gpu/drm/xe/display/ext/i915_irq.c     | 118 ++++++-------
>  .../drm/xe/display/ext/intel_clock_gating.c   |   1 +
>  .../drm/xe/display/ext/intel_device_info.c    |   1 +
>  drivers/gpu/drm/xe/display/ext/intel_dram.c   |   3 +-
>  drivers/gpu/drm/xe/display/xe_de.h            | 163 ------------------
>  drivers/gpu/drm/xe/xe_device_types.h          |   4 +
>  drivers/gpu/drm/xe/xe_display.c               |   3 +
>  drivers/gpu/drm/xe/xe_mmio.h                  |   8 +
>  22 files changed, 298 insertions(+), 355 deletions(-)
>  create mode 100644 drivers/gpu/drm/xe/compat-i915-headers/intel_pcode.h
>  create mode 100644 drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
>  delete mode 100644 drivers/gpu/drm/xe/display/xe_de.h
> 
> -- 
> 2.39.2
> 

[Intel-xe] [PATCH 00/18] xe&i915 display integration: add uncore and pcode compat layers

[Jani Nikula]

Add intel_uncore.h and intel_pcode.h compat layers to direct the calls
in i915 display code properly, without needing to change a lot of call
sites in i915 display.

The main trick or hack here is adding a fake uncore member to struct
xe_device, which lets all the call sites use &i915->uncore as before,
which we can use in the glue layers to get at the struct xe_device
pointer.

The fake uncore is intentionally struct fake_uncore in xe, so you can't
really start passing around uncore pointers in display code, only do
&i915->uncore, and it'll be the correct, but different type for each
driver.

IMO the trick and the compat layers are cleaner than what we've had
before, and doesn't force using intel_de_* accessors for non-de
registers in i915 display code.

BR,
Jani.


Jani Nikula (18):
  fixup! drm/xe/display: Implement display support
  fixup! drm/xe/display: Implement display support
  fixup! drm/xe/display: Implement display support
  fixup! drm/xe/display: Rename intel_de.h to xe_de.h
  fixup! drm/xe/display: Implement display support
  fixup! drm/i915/display: Remaining changes to make xe compile
  fixup! drm/xe/display: Implement display support
  fixup! drm/i915/display: Add more macros to remove all direct calls to
    uncore
  fixup! drm/i915/display: Remove all uncore mmio accesses in favor of
    intel_de
  fixup! drm/i915/display: Remaining changes to make xe compile
  fixup! drm/xe: Introduce a new DRM driver for Intel GPUs
  fixup! drm/xe/display: Implement display support
  fixup! drm/i915/display: Remaining changes to make xe compile
  fixup! drm/i915/display: Remaining changes to make xe compile
  fixup! drm/xe/display: Implement display support
  fixup! drm/xe/display: Implement display support
  fixup! drm/xe/display: Implement display support
  fixup! drm/xe/display: Implement display support

 drivers/gpu/drm/i915/display/hsw_ips.c        |   7 +-
 drivers/gpu/drm/i915/display/intel_bios.c     |  19 +-
 drivers/gpu/drm/i915/display/intel_bw.c       |  34 ++--
 drivers/gpu/drm/i915/display/intel_cdclk.c    |  45 ++---
 drivers/gpu/drm/i915/display/intel_de.h       |  54 ------
 drivers/gpu/drm/i915/display/intel_display.c  |   1 +
 .../drm/i915/display/intel_display_power.c    |   3 +-
 .../i915/display/intel_display_power_well.c   |   7 +-
 drivers/gpu/drm/i915/display/intel_dpio_phy.c |   9 +-
 drivers/gpu/drm/i915/display/intel_hdcp.c     |   9 +-
 drivers/gpu/drm/i915/display/skl_watermark.c  |  23 +--
 .../gpu/drm/xe/compat-i915-headers/i915_drv.h |   1 +
 .../drm/xe/compat-i915-headers/intel_pcode.h  |  42 +++++
 .../drm/xe/compat-i915-headers/intel_uncore.h |  99 +++++++++++
 drivers/gpu/drm/xe/display/ext/i915_irq.c     | 134 +++++++-------
 .../drm/xe/display/ext/intel_clock_gating.c   |   1 +
 .../drm/xe/display/ext/intel_device_info.c    |   1 +
 drivers/gpu/drm/xe/display/ext/intel_dram.c   |   3 +-
 drivers/gpu/drm/xe/display/xe_de.h            | 163 ------------------
 drivers/gpu/drm/xe/xe_device_types.h          |   4 +
 drivers/gpu/drm/xe/xe_display.c               |   3 +
 drivers/gpu/drm/xe/xe_mmio.h                  |   8 +
 22 files changed, 307 insertions(+), 363 deletions(-)
 create mode 100644 drivers/gpu/drm/xe/compat-i915-headers/intel_pcode.h
 create mode 100644 drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
 delete mode 100644 drivers/gpu/drm/xe/display/xe_de.h

-- 
2.39.2

[Intel-xe] [PATCH 11/18] fixup! drm/xe: Introduce a new DRM driver for Intel GPUs

[Jani Nikula]

Add the read8 accessor to support intel_de_read8.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/xe/xe_mmio.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_mmio.h b/drivers/gpu/drm/xe/xe_mmio.h
index 1a32e0f52261..b72a0a75259f 100644
--- a/drivers/gpu/drm/xe/xe_mmio.h
+++ b/drivers/gpu/drm/xe/xe_mmio.h
@@ -17,6 +17,14 @@ struct xe_device;
 
 int xe_mmio_init(struct xe_device *xe);
 
+static inline u8 xe_mmio_read8(struct xe_gt *gt, u32 reg)
+{
+	if (reg < gt->mmio.adj_limit)
+		reg += gt->mmio.adj_offset;
+
+	return readb(gt->mmio.regs + reg);
+}
+
 static inline void xe_mmio_write32(struct xe_gt *gt,
 				   u32 reg, u32 val)
 {
-- 
2.39.2

Re: [Intel-xe] [PATCH 11/18] fixup! drm/xe: Introduce a new DRM driver for Intel GPUs

[Rodrigo Vivi]

On Wed, May 03, 2023 at 04:09:58PM +0300, Jani Nikula wrote:
> Add the read8 accessor to support intel_de_read8.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

I wonder if we should have this as a new separated patch instead of a fixup?
Then when rebasing with autosquash we make sure to put this before the
xe/display patches...

Oded has already started to review the xe-rev1 branch and I'd like
to avoid changes to the patches that are in that branch already.

But this is really small, probably with his ack we can keep as this fixup!

> ---
>  drivers/gpu/drm/xe/xe_mmio.h | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_mmio.h b/drivers/gpu/drm/xe/xe_mmio.h
> index 1a32e0f52261..b72a0a75259f 100644
> --- a/drivers/gpu/drm/xe/xe_mmio.h
> +++ b/drivers/gpu/drm/xe/xe_mmio.h
> @@ -17,6 +17,14 @@ struct xe_device;
>  
>  int xe_mmio_init(struct xe_device *xe);
>  
> +static inline u8 xe_mmio_read8(struct xe_gt *gt, u32 reg)
> +{
> +	if (reg < gt->mmio.adj_limit)
> +		reg += gt->mmio.adj_offset;
> +
> +	return readb(gt->mmio.regs + reg);
> +}
> +
>  static inline void xe_mmio_write32(struct xe_gt *gt,
>  				   u32 reg, u32 val)
>  {
> -- 
> 2.39.2
> 

Re: [Intel-xe] [PATCH 11/18] fixup! drm/xe: Introduce a new DRM driver for Intel GPUs

[Oded Gabbay]

On Wed, May 3, 2023 at 4:59 PM Rodrigo Vivi <rodrigo.vivi@kernel.org> wrote:
>
> On Wed, May 03, 2023 at 04:09:58PM +0300, Jani Nikula wrote:
> > Add the read8 accessor to support intel_de_read8.
> >
> > Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> I wonder if we should have this as a new separated patch instead of a fixup?
> Then when rebasing with autosquash we make sure to put this before the
> xe/display patches...
>
> Oded has already started to review the xe-rev1 branch and I'd like
> to avoid changes to the patches that are in that branch already.
>
> But this is really small, probably with his ack we can keep as this fixup!
I haven't managed to do a lot yet, so keeping this patch as fixup is fine.
Oded
>
> > ---
> >  drivers/gpu/drm/xe/xe_mmio.h | 8 ++++++++
> >  1 file changed, 8 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/xe/xe_mmio.h b/drivers/gpu/drm/xe/xe_mmio.h
> > index 1a32e0f52261..b72a0a75259f 100644
> > --- a/drivers/gpu/drm/xe/xe_mmio.h
> > +++ b/drivers/gpu/drm/xe/xe_mmio.h
> > @@ -17,6 +17,14 @@ struct xe_device;
> >
> >  int xe_mmio_init(struct xe_device *xe);
> >
> > +static inline u8 xe_mmio_read8(struct xe_gt *gt, u32 reg)
> > +{
> > +     if (reg < gt->mmio.adj_limit)
> > +             reg += gt->mmio.adj_offset;
> > +
> > +     return readb(gt->mmio.regs + reg);
> > +}
> > +
> >  static inline void xe_mmio_write32(struct xe_gt *gt,
> >                                  u32 reg, u32 val)
> >  {
> > --
> > 2.39.2
> >