[PATCH 1/2] drm/i915/display: Refactor handling of dpkgc latency programming

[PATCH 1/2] drm/i915/display: Refactor handling of dpkgc latency programming

[Suraj Kandpal]

- We want to make sure we have all the required values specially
linetime which is computed after intel_wm_compute, this will also
help implement some WA's which require linetime.
-We do not want to write into any registers during compute_config phase
While we are at it do some more refactors in the function like:
-Use intel_display wherever possible
-Move away from using enable_dpkgc bool and call it fixed_refresh_rate
-Optimize value prepration

--v2
-No need to save anything in intel_display structure [Vinod]
-Move computation and writing into register to intel_atomic_commit_tail
[Vinod]

--v3
-Rename the subject [Vinod]
-Rearrange the variable initialization and declaration [Vinod]
-Reaarange condition evaluation for fixed_refresh_rate [Vinod]

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c |  2 +
 drivers/gpu/drm/i915/display/intel_wm.c      | 57 ++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_wm.h      |  2 +
 drivers/gpu/drm/i915/display/skl_watermark.c | 52 ------------------
 4 files changed, 61 insertions(+), 52 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e790a2de5b3d..4f8e45a794bb 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7826,6 +7826,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
 	dev_priv->display.funcs.display->commit_modeset_enables(state);
 
+	intel_program_dpkgc_latency(state, dev_priv);
+
 	if (state->modeset)
 		intel_set_cdclk_post_plane_update(state);
 
diff --git a/drivers/gpu/drm/i915/display/intel_wm.c b/drivers/gpu/drm/i915/display/intel_wm.c
index d7dc49aecd27..d893403ff611 100644
--- a/drivers/gpu/drm/i915/display/intel_wm.c
+++ b/drivers/gpu/drm/i915/display/intel_wm.c
@@ -7,9 +7,18 @@
 
 #include "i915_drv.h"
 #include "i9xx_wm.h"
+#include "intel_de.h"
 #include "intel_display_types.h"
 #include "intel_wm.h"
 #include "skl_watermark.h"
+#include "skl_watermark_regs.h"
+
+/*
+ * It is expected that DSB can do posted writes to every register in
+ * the pipe and planes within 100us. For flip queue use case, the
+ * recommended DSB execution time is 100us + one SAGV block time.
+ */
+#define DSB_EXE_TIME 100
 
 /**
  * intel_update_watermarks - update FIFO watermark values based on current modes
@@ -131,6 +140,54 @@ bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
 		return plane_state->uapi.visible;
 }
 
+/*
+ * If Fixed Refresh Rate or For VRR case Vmin = Vmax = Flipline:
+ * Program DEEP PKG_C_LATENCY Pkg C with highest valid latency from
+ * watermark level1 and up and above. If watermark level 1 is
+ * invalid program it with all 1's.
+ * Program PKG_C_LATENCY Added Wake Time = DSB execution time
+ * If Variable Refresh Rate where Vmin != Vmax != Flipline:
+ * Program DEEP PKG_C_LATENCY Pkg C with all 1's.
+ * Program PKG_C_LATENCY Added Wake Time = 0
+ */
+void
+intel_program_dpkgc_latency(struct intel_atomic_state *state,
+			    struct drm_i915_private *i915)
+{
+	struct intel_display *display = to_intel_display(state);
+	struct intel_crtc *crtc;
+	struct intel_crtc_state *new_crtc_state;
+	u32 max_latency = LNL_PKG_C_LATENCY_MASK;
+	u32 added_waketime = 0;
+	bool fixed_refresh_rate = false;
+	u32 clear, val;
+	int i;
+
+	if (DISPLAY_VER(display) < 20)
+		return;
+
+	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+		if (!new_crtc_state->vrr.enable ||
+		    (new_crtc_state->vrr.vmin == new_crtc_state->vrr.vmax &&
+		     new_crtc_state->vrr.vmin == new_crtc_state->vrr.flipline))
+			fixed_refresh_rate = true;
+	}
+
+	if (fixed_refresh_rate) {
+		max_latency = skl_watermark_max_latency(i915, 1);
+		if (max_latency == 0)
+			max_latency = LNL_PKG_C_LATENCY_MASK;
+		added_waketime = DSB_EXE_TIME +
+			display->sagv.block_time_us;
+	}
+
+	clear = LNL_ADDED_WAKE_TIME_MASK | LNL_PKG_C_LATENCY_MASK;
+	val = REG_FIELD_PREP(LNL_PKG_C_LATENCY_MASK, max_latency) |
+		REG_FIELD_PREP(LNL_ADDED_WAKE_TIME_MASK, added_waketime);
+
+	intel_de_rmw(display, LNL_PKG_C_LATENCY, clear, val);
+}
+
 void intel_print_wm_latency(struct drm_i915_private *dev_priv,
 			    const char *name, const u16 wm[])
 {
diff --git a/drivers/gpu/drm/i915/display/intel_wm.h b/drivers/gpu/drm/i915/display/intel_wm.h
index e97cdca89a5c..f47e1354605d 100644
--- a/drivers/gpu/drm/i915/display/intel_wm.h
+++ b/drivers/gpu/drm/i915/display/intel_wm.h
@@ -31,5 +31,7 @@ void intel_print_wm_latency(struct drm_i915_private *i915,
 			    const char *name, const u16 wm[]);
 void intel_wm_init(struct drm_i915_private *i915);
 void intel_wm_debugfs_register(struct drm_i915_private *i915);
+void intel_program_dpkgc_latency(struct intel_atomic_state *state,
+				 struct drm_i915_private *i915);
 
 #endif /* __INTEL_WM_H__ */
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 1a4c1fa24820..d419edb196c6 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -28,12 +28,6 @@
 #include "skl_watermark.h"
 #include "skl_watermark_regs.h"
 
-/*It is expected that DSB can do posted writes to every register in
- * the pipe and planes within 100us. For flip queue use case, the
- * recommended DSB execution time is 100us + one SAGV block time.
- */
-#define DSB_EXE_TIME 100
-
 static void skl_sagv_disable(struct drm_i915_private *i915);
 
 /* Stores plane specific WM parameters */
@@ -2844,51 +2838,12 @@ static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
 	return 0;
 }
 
-/*
- * If Fixed Refresh Rate or For VRR case Vmin = Vmax = Flipline:
- * Program DEEP PKG_C_LATENCY Pkg C with highest valid latency from
- * watermark level1 and up and above. If watermark level 1 is
- * invalid program it with all 1's.
- * Program PKG_C_LATENCY Added Wake Time = DSB execution time
- * If Variable Refresh Rate where Vmin != Vmax != Flipline:
- * Program DEEP PKG_C_LATENCY Pkg C with all 1's.
- * Program PKG_C_LATENCY Added Wake Time = 0
- */
-static void
-skl_program_dpkgc_latency(struct drm_i915_private *i915, bool enable_dpkgc)
-{
-	u32 max_latency = 0;
-	u32 clear = 0, val = 0;
-	u32 added_wake_time = 0;
-
-	if (DISPLAY_VER(i915) < 20)
-		return;
-
-	if (enable_dpkgc) {
-		max_latency = skl_watermark_max_latency(i915, 1);
-		if (max_latency == 0)
-			max_latency = LNL_PKG_C_LATENCY_MASK;
-		added_wake_time = DSB_EXE_TIME +
-			i915->display.sagv.block_time_us;
-	} else {
-		max_latency = LNL_PKG_C_LATENCY_MASK;
-		added_wake_time = 0;
-	}
-
-	clear |= LNL_ADDED_WAKE_TIME_MASK | LNL_PKG_C_LATENCY_MASK;
-	val |= REG_FIELD_PREP(LNL_PKG_C_LATENCY_MASK, max_latency);
-	val |= REG_FIELD_PREP(LNL_ADDED_WAKE_TIME_MASK, added_wake_time);
-
-	intel_uncore_rmw(&i915->uncore, LNL_PKG_C_LATENCY, clear, val);
-}
-
 static int
 skl_compute_wm(struct intel_atomic_state *state)
 {
 	struct intel_crtc *crtc;
 	struct intel_crtc_state __maybe_unused *new_crtc_state;
 	int ret, i;
-	bool enable_dpkgc = false;
 
 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
 		ret = skl_build_pipe_wm(state, crtc);
@@ -2913,15 +2868,8 @@ skl_compute_wm(struct intel_atomic_state *state)
 		ret = skl_wm_add_affected_planes(state, crtc);
 		if (ret)
 			return ret;
-
-		if ((new_crtc_state->vrr.vmin == new_crtc_state->vrr.vmax &&
-		     new_crtc_state->vrr.vmin == new_crtc_state->vrr.flipline) ||
-		    !new_crtc_state->vrr.enable)
-			enable_dpkgc = true;
 	}
 
-	skl_program_dpkgc_latency(to_i915(state->base.dev), enable_dpkgc);
-
 	skl_print_wm_changes(state);
 
 	return 0;
-- 
2.34.1

[PATCH 1/2] drm/i915/display: Refactor handling of dpkgc latency programming

[Suraj Kandpal]

- We want to make sure we have all the required values specially
linetime which is computed after intel_wm_compute, this will also
help implement some WA's which require linetime.
-We do not want to write into any registers during compute_config phase
While we are at it do some more refactors in the function like:
-Use intel_display wherever possible
-Move away from using enable_dpkgc bool and call it fixed_refresh_rate
-Optimize value prepration

--v2
-No need to save anything in intel_display structure [Vinod]
-Move computation and writing into register to intel_atomic_commit_tail
[Vinod]

--v3
-Rename the subject [Vinod]
-Rearrange the variable initialization and declaration [Vinod]
-Reaarange condition evaluation for fixed_refresh_rate [Vinod]

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c |  2 +
 drivers/gpu/drm/i915/display/intel_wm.c      | 56 ++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_wm.h      |  1 +
 drivers/gpu/drm/i915/display/skl_watermark.c | 52 ------------------
 4 files changed, 59 insertions(+), 52 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e790a2de5b3d..d1880e0a5d29 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7826,6 +7826,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
 	dev_priv->display.funcs.display->commit_modeset_enables(state);
 
+	intel_program_dpkgc_latency(state);
+
 	if (state->modeset)
 		intel_set_cdclk_post_plane_update(state);
 
diff --git a/drivers/gpu/drm/i915/display/intel_wm.c b/drivers/gpu/drm/i915/display/intel_wm.c
index d7dc49aecd27..4a2caf9cb03e 100644
--- a/drivers/gpu/drm/i915/display/intel_wm.c
+++ b/drivers/gpu/drm/i915/display/intel_wm.c
@@ -7,9 +7,18 @@
 
 #include "i915_drv.h"
 #include "i9xx_wm.h"
+#include "intel_de.h"
 #include "intel_display_types.h"
 #include "intel_wm.h"
 #include "skl_watermark.h"
+#include "skl_watermark_regs.h"
+
+/*
+ * It is expected that DSB can do posted writes to every register in
+ * the pipe and planes within 100us. For flip queue use case, the
+ * recommended DSB execution time is 100us + one SAGV block time.
+ */
+#define DSB_EXE_TIME 100
 
 /**
  * intel_update_watermarks - update FIFO watermark values based on current modes
@@ -131,6 +140,53 @@ bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
 		return plane_state->uapi.visible;
 }
 
+/*
+ * If Fixed Refresh Rate or For VRR case Vmin = Vmax = Flipline:
+ * Program DEEP PKG_C_LATENCY Pkg C with highest valid latency from
+ * watermark level1 and up and above. If watermark level 1 is
+ * invalid program it with all 1's.
+ * Program PKG_C_LATENCY Added Wake Time = DSB execution time
+ * If Variable Refresh Rate where Vmin != Vmax != Flipline:
+ * Program DEEP PKG_C_LATENCY Pkg C with all 1's.
+ * Program PKG_C_LATENCY Added Wake Time = 0
+ */
+void
+intel_program_dpkgc_latency(struct intel_atomic_state *state)
+{
+	struct intel_display *display = to_intel_display(state);
+	struct drm_i915_private *i915 = to_i915(display->drm);
+	struct intel_crtc *crtc;
+	struct intel_crtc_state *new_crtc_state;
+	u32 max_latency = LNL_PKG_C_LATENCY_MASK, added_waketime = 0;
+	bool fixed_refresh_rate = false;
+	u32 clear, val;
+	int i;
+
+	if (DISPLAY_VER(display) < 20)
+		return;
+
+	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+		if (!new_crtc_state->vrr.enable ||
+		    (new_crtc_state->vrr.vmin == new_crtc_state->vrr.vmax &&
+		     new_crtc_state->vrr.vmin == new_crtc_state->vrr.flipline))
+			fixed_refresh_rate = true;
+	}
+
+	if (fixed_refresh_rate) {
+		max_latency = skl_watermark_max_latency(i915, 1);
+		if (max_latency == 0)
+			max_latency = LNL_PKG_C_LATENCY_MASK;
+		added_waketime = DSB_EXE_TIME +
+			display->sagv.block_time_us;
+	}
+
+	clear = LNL_ADDED_WAKE_TIME_MASK | LNL_PKG_C_LATENCY_MASK;
+	val = REG_FIELD_PREP(LNL_PKG_C_LATENCY_MASK, max_latency) |
+		REG_FIELD_PREP(LNL_ADDED_WAKE_TIME_MASK, added_waketime);
+
+	intel_de_rmw(display, LNL_PKG_C_LATENCY, clear, val);
+}
+
 void intel_print_wm_latency(struct drm_i915_private *dev_priv,
 			    const char *name, const u16 wm[])
 {
diff --git a/drivers/gpu/drm/i915/display/intel_wm.h b/drivers/gpu/drm/i915/display/intel_wm.h
index e97cdca89a5c..07e3d9359d73 100644
--- a/drivers/gpu/drm/i915/display/intel_wm.h
+++ b/drivers/gpu/drm/i915/display/intel_wm.h
@@ -31,5 +31,6 @@ void intel_print_wm_latency(struct drm_i915_private *i915,
 			    const char *name, const u16 wm[]);
 void intel_wm_init(struct drm_i915_private *i915);
 void intel_wm_debugfs_register(struct drm_i915_private *i915);
+void intel_program_dpkgc_latency(struct intel_atomic_state *state);
 
 #endif /* __INTEL_WM_H__ */
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 1a4c1fa24820..d419edb196c6 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -28,12 +28,6 @@
 #include "skl_watermark.h"
 #include "skl_watermark_regs.h"
 
-/*It is expected that DSB can do posted writes to every register in
- * the pipe and planes within 100us. For flip queue use case, the
- * recommended DSB execution time is 100us + one SAGV block time.
- */
-#define DSB_EXE_TIME 100
-
 static void skl_sagv_disable(struct drm_i915_private *i915);
 
 /* Stores plane specific WM parameters */
@@ -2844,51 +2838,12 @@ static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
 	return 0;
 }
 
-/*
- * If Fixed Refresh Rate or For VRR case Vmin = Vmax = Flipline:
- * Program DEEP PKG_C_LATENCY Pkg C with highest valid latency from
- * watermark level1 and up and above. If watermark level 1 is
- * invalid program it with all 1's.
- * Program PKG_C_LATENCY Added Wake Time = DSB execution time
- * If Variable Refresh Rate where Vmin != Vmax != Flipline:
- * Program DEEP PKG_C_LATENCY Pkg C with all 1's.
- * Program PKG_C_LATENCY Added Wake Time = 0
- */
-static void
-skl_program_dpkgc_latency(struct drm_i915_private *i915, bool enable_dpkgc)
-{
-	u32 max_latency = 0;
-	u32 clear = 0, val = 0;
-	u32 added_wake_time = 0;
-
-	if (DISPLAY_VER(i915) < 20)
-		return;
-
-	if (enable_dpkgc) {
-		max_latency = skl_watermark_max_latency(i915, 1);
-		if (max_latency == 0)
-			max_latency = LNL_PKG_C_LATENCY_MASK;
-		added_wake_time = DSB_EXE_TIME +
-			i915->display.sagv.block_time_us;
-	} else {
-		max_latency = LNL_PKG_C_LATENCY_MASK;
-		added_wake_time = 0;
-	}
-
-	clear |= LNL_ADDED_WAKE_TIME_MASK | LNL_PKG_C_LATENCY_MASK;
-	val |= REG_FIELD_PREP(LNL_PKG_C_LATENCY_MASK, max_latency);
-	val |= REG_FIELD_PREP(LNL_ADDED_WAKE_TIME_MASK, added_wake_time);
-
-	intel_uncore_rmw(&i915->uncore, LNL_PKG_C_LATENCY, clear, val);
-}
-
 static int
 skl_compute_wm(struct intel_atomic_state *state)
 {
 	struct intel_crtc *crtc;
 	struct intel_crtc_state __maybe_unused *new_crtc_state;
 	int ret, i;
-	bool enable_dpkgc = false;
 
 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
 		ret = skl_build_pipe_wm(state, crtc);
@@ -2913,15 +2868,8 @@ skl_compute_wm(struct intel_atomic_state *state)
 		ret = skl_wm_add_affected_planes(state, crtc);
 		if (ret)
 			return ret;
-
-		if ((new_crtc_state->vrr.vmin == new_crtc_state->vrr.vmax &&
-		     new_crtc_state->vrr.vmin == new_crtc_state->vrr.flipline) ||
-		    !new_crtc_state->vrr.enable)
-			enable_dpkgc = true;
 	}
 
-	skl_program_dpkgc_latency(to_i915(state->base.dev), enable_dpkgc);
-
 	skl_print_wm_changes(state);
 
 	return 0;
-- 
2.34.1

[PATCH 2/2] drm/i915/display: Modify latency programmed into PKG_C_LATENCY

[Suraj Kandpal]

Increase the latency programmed into PKG_C_LATENCY latency to be
a multiple of line time which is written into WM_LINETIME.

--v2
-Fix commit subject line [Sai Teja]
-Use individual DISPLAY_VER checks instead of range [Sai Teja]
-Initialize max_linetime [Sai Teja]

--v3
-take into account the scenario when adjusted_latency is 0 [Vinod]

--v4
-rename adjusted_latency to latency [Mitul]
-fix the condition in which dpkgc is disabled [Vinod]

--v5
-Add check to see if max_linetime is 0 [Vinod]

WA: 22020299601
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_wm.c | 21 ++++++++++++++++-----
 1 file changed, 16 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_wm.c b/drivers/gpu/drm/i915/display/intel_wm.c
index 4a2caf9cb03e..2038e03b7d2c 100644
--- a/drivers/gpu/drm/i915/display/intel_wm.c
+++ b/drivers/gpu/drm/i915/display/intel_wm.c
@@ -157,7 +157,7 @@ intel_program_dpkgc_latency(struct intel_atomic_state *state)
 	struct drm_i915_private *i915 = to_i915(display->drm);
 	struct intel_crtc *crtc;
 	struct intel_crtc_state *new_crtc_state;
-	u32 max_latency = LNL_PKG_C_LATENCY_MASK, added_waketime = 0;
+	u32 latency = LNL_PKG_C_LATENCY_MASK, added_waketime = 0, max_linetime = 0;
 	bool fixed_refresh_rate = false;
 	u32 clear, val;
 	int i;
@@ -170,18 +170,29 @@ intel_program_dpkgc_latency(struct intel_atomic_state *state)
 		    (new_crtc_state->vrr.vmin == new_crtc_state->vrr.vmax &&
 		     new_crtc_state->vrr.vmin == new_crtc_state->vrr.flipline))
 			fixed_refresh_rate = true;
+
+		max_linetime = max(new_crtc_state->linetime, max_linetime);
 	}
 
 	if (fixed_refresh_rate) {
-		max_latency = skl_watermark_max_latency(i915, 1);
-		if (max_latency == 0)
-			max_latency = LNL_PKG_C_LATENCY_MASK;
+		latency = skl_watermark_max_latency(i915, 1);
+
+		/* Wa_22020299601 */
+		if (latency) {
+			if ((DISPLAY_VER(display) == 20 || DISPLAY_VER(display) == 30) &&
+			    max_linetime)
+				latency = max_linetime *
+					DIV_ROUND_UP(latency, max_linetime);
+		} else {
+			latency = LNL_PKG_C_LATENCY_MASK;
+		}
+
 		added_waketime = DSB_EXE_TIME +
 			display->sagv.block_time_us;
 	}
 
 	clear = LNL_ADDED_WAKE_TIME_MASK | LNL_PKG_C_LATENCY_MASK;
-	val = REG_FIELD_PREP(LNL_PKG_C_LATENCY_MASK, max_latency) |
+	val = REG_FIELD_PREP(LNL_PKG_C_LATENCY_MASK, latency) |
 		REG_FIELD_PREP(LNL_ADDED_WAKE_TIME_MASK, added_waketime);
 
 	intel_de_rmw(display, LNL_PKG_C_LATENCY, clear, val);
-- 
2.34.1

✓ CI.Patch_applied: success for series starting with [1/2] drm/i915/display: Refactor handling of dpkgc latency programming

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/display: Refactor handling of dpkgc latency programming
URL   : https://patchwork.freedesktop.org/series/141385/
State : success

== Summary ==

=== Applying kernel patches on branch 'drm-tip' with base: ===
Base commit: 36fec0eb8786 drm-tip: 2024y-11m-14d-23h-49m-25s UTC integration manifest
=== git am output follows ===
Applying: drm/i915/display: Refactor handling of dpkgc latency programming
Applying: drm/i915/display: Modify latency programmed into PKG_C_LATENCY

✓ CI.checkpatch: success for series starting with [1/2] drm/i915/display: Refactor handling of dpkgc latency programming

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/display: Refactor handling of dpkgc latency programming
URL   : https://patchwork.freedesktop.org/series/141385/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
30ab6715fc09baee6cc14cb3c89ad8858688d474
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit b144161fdaf314e5b2815166625b07a1b82f96b6
Author: Suraj Kandpal <suraj.kandpal@intel.com>
Date:   Fri Nov 15 12:04:42 2024 +0530

    drm/i915/display: Modify latency programmed into PKG_C_LATENCY
    
    Increase the latency programmed into PKG_C_LATENCY latency to be
    a multiple of line time which is written into WM_LINETIME.
    
    --v2
    -Fix commit subject line [Sai Teja]
    -Use individual DISPLAY_VER checks instead of range [Sai Teja]
    -Initialize max_linetime [Sai Teja]
    
    --v3
    -take into account the scenario when adjusted_latency is 0 [Vinod]
    
    --v4
    -rename adjusted_latency to latency [Mitul]
    -fix the condition in which dpkgc is disabled [Vinod]
    
    --v5
    -Add check to see if max_linetime is 0 [Vinod]
    
    WA: 22020299601
    Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
+ /mt/dim checkpatch 36fec0eb87867bca47f8829c9e5dbf5b3e2b3aaf drm-intel
fc2b4949ddbb drm/i915/display: Refactor handling of dpkgc latency programming
b144161fdaf3 drm/i915/display: Modify latency programmed into PKG_C_LATENCY

✓ CI.KUnit: success for series starting with [1/2] drm/i915/display: Refactor handling of dpkgc latency programming

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/display: Refactor handling of dpkgc latency programming
URL   : https://patchwork.freedesktop.org/series/141385/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[06:41:55] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[06:41:59] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json ARCH=um O=.kunit --jobs=48
../lib/iomap.c:156:5: warning: no previous prototype for ‘ioread64_lo_hi’ [-Wmissing-prototypes]
  156 | u64 ioread64_lo_hi(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~
../lib/iomap.c:163:5: warning: no previous prototype for ‘ioread64_hi_lo’ [-Wmissing-prototypes]
  163 | u64 ioread64_hi_lo(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~
../lib/iomap.c:170:5: warning: no previous prototype for ‘ioread64be_lo_hi’ [-Wmissing-prototypes]
  170 | u64 ioread64be_lo_hi(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~~~
../lib/iomap.c:178:5: warning: no previous prototype for ‘ioread64be_hi_lo’ [-Wmissing-prototypes]
  178 | u64 ioread64be_hi_lo(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~~~
../lib/iomap.c:264:6: warning: no previous prototype for ‘iowrite64_lo_hi’ [-Wmissing-prototypes]
  264 | void iowrite64_lo_hi(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~
../lib/iomap.c:272:6: warning: no previous prototype for ‘iowrite64_hi_lo’ [-Wmissing-prototypes]
  272 | void iowrite64_hi_lo(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~
../lib/iomap.c:280:6: warning: no previous prototype for ‘iowrite64be_lo_hi’ [-Wmissing-prototypes]
  280 | void iowrite64be_lo_hi(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~~~
../lib/iomap.c:288:6: warning: no previous prototype for ‘iowrite64be_hi_lo’ [-Wmissing-prototypes]
  288 | void iowrite64be_hi_lo(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~~~

[06:42:27] Starting KUnit Kernel (1/1)...
[06:42:27] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[06:42:27] =================== guc_dbm (7 subtests) ===================
[06:42:27] [PASSED] test_empty
[06:42:27] [PASSED] test_default
[06:42:27] ======================== test_size  ========================
[06:42:27] [PASSED] 4
[06:42:27] [PASSED] 8
[06:42:27] [PASSED] 32
[06:42:27] [PASSED] 256
[06:42:27] ==================== [PASSED] test_size ====================
[06:42:27] ======================= test_reuse  ========================
[06:42:27] [PASSED] 4
[06:42:27] [PASSED] 8
[06:42:27] [PASSED] 32
[06:42:27] [PASSED] 256
[06:42:27] =================== [PASSED] test_reuse ====================
[06:42:27] =================== test_range_overlap  ====================
[06:42:27] [PASSED] 4
[06:42:27] [PASSED] 8
[06:42:27] [PASSED] 32
[06:42:27] [PASSED] 256
[06:42:27] =============== [PASSED] test_range_overlap ================
[06:42:27] =================== test_range_compact  ====================
[06:42:27] [PASSED] 4
[06:42:27] [PASSED] 8
[06:42:27] [PASSED] 32
[06:42:27] [PASSED] 256
[06:42:27] =============== [PASSED] test_range_compact ================
[06:42:27] ==================== test_range_spare  =====================
[06:42:27] [PASSED] 4
[06:42:27] [PASSED] 8
[06:42:27] [PASSED] 32
[06:42:27] [PASSED] 256
[06:42:27] ================ [PASSED] test_range_spare =================
[06:42:27] ===================== [PASSED] guc_dbm =====================
[06:42:27] =================== guc_idm (6 subtests) ===================
[06:42:27] [PASSED] bad_init
[06:42:27] [PASSED] no_init
[06:42:27] [PASSED] init_fini
[06:42:27] [PASSED] check_used
[06:42:27] [PASSED] check_quota
[06:42:27] [PASSED] check_all
[06:42:27] ===================== [PASSED] guc_idm =====================
[06:42:27] ================== no_relay (3 subtests) ===================
[06:42:27] [PASSED] xe_drops_guc2pf_if_not_ready
[06:42:27] [PASSED] xe_drops_guc2vf_if_not_ready
[06:42:27] [PASSED] xe_rejects_send_if_not_ready
[06:42:27] ==================== [PASSED] no_relay =====================
[06:42:27] ================== pf_relay (14 subtests) ==================
[06:42:27] [PASSED] pf_rejects_guc2pf_too_short
[06:42:27] [PASSED] pf_rejects_guc2pf_too_long
[06:42:27] [PASSED] pf_rejects_guc2pf_no_payload
[06:42:27] [PASSED] pf_fails_no_payload
[06:42:27] [PASSED] pf_fails_bad_origin
[06:42:27] [PASSED] pf_fails_bad_type
[06:42:27] [PASSED] pf_txn_reports_error
[06:42:27] [PASSED] pf_txn_sends_pf2guc
[06:42:27] [PASSED] pf_sends_pf2guc
[06:42:27] [SKIPPED] pf_loopback_nop
[06:42:27] [SKIPPED] pf_loopback_echo
[06:42:27] [SKIPPED] pf_loopback_fail
[06:42:27] [SKIPPED] pf_loopback_busy
[06:42:27] [SKIPPED] pf_loopback_retry
[06:42:27] ==================== [PASSED] pf_relay =====================
[06:42:27] ================== vf_relay (3 subtests) ===================
[06:42:27] [PASSED] vf_rejects_guc2vf_too_short
[06:42:27] [PASSED] vf_rejects_guc2vf_too_long
[06:42:27] [PASSED] vf_rejects_guc2vf_no_payload
[06:42:27] ==================== [PASSED] vf_relay =====================
[06:42:27] ================= pf_service (11 subtests) =================
[06:42:27] [PASSED] pf_negotiate_any
[06:42:27] [PASSED] pf_negotiate_base_match
[06:42:27] [PASSED] pf_negotiate_base_newer
[06:42:27] [PASSED] pf_negotiate_base_next
[06:42:27] [SKIPPED] pf_negotiate_base_older
[06:42:27] [PASSED] pf_negotiate_base_prev
[06:42:27] [PASSED] pf_negotiate_latest_match
[06:42:27] [PASSED] pf_negotiate_latest_newer
[06:42:27] [PASSED] pf_negotiate_latest_next
[06:42:27] [SKIPPED] pf_negotiate_latest_older
[06:42:27] [SKIPPED] pf_negotiate_latest_prev
[06:42:27] =================== [PASSED] pf_service ====================
[06:42:27] ===================== lmtt (1 subtest) =====================
[06:42:27] ======================== test_ops  =========================
[06:42:27] [PASSED] 2-level
[06:42:27] [PASSED] multi-level
[06:42:27] ==================== [PASSED] test_ops =====================
[06:42:27] ====================== [PASSED] lmtt =======================
[06:42:27] =================== xe_mocs (2 subtests) ===================
[06:42:27] ================ xe_live_mocs_kernel_kunit  ================
[06:42:27] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[06:42:27] ================ xe_live_mocs_reset_kunit  =================
[06:42:27] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[06:42:27] ==================== [SKIPPED] xe_mocs =====================
[06:42:27] ================= xe_migrate (2 subtests) ==================
[06:42:27] ================= xe_migrate_sanity_kunit  =================
[06:42:27] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[06:42:27] ================== xe_validate_ccs_kunit  ==================
[06:42:27] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[06:42:27] =================== [SKIPPED] xe_migrate ===================
[06:42:27] ================== xe_dma_buf (1 subtest) ==================
[06:42:27] ==================== xe_dma_buf_kunit  =====================
[06:42:27] ================ [SKIPPED] xe_dma_buf_kunit ================
[06:42:27] =================== [SKIPPED] xe_dma_buf ===================
[06:42:27] ==================== xe_bo (3 subtests) ====================
[06:42:27] ================== xe_ccs_migrate_kunit  ===================
[06:42:27] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[06:42:27] ==================== xe_bo_evict_kunit  ====================
[06:42:27] =============== [SKIPPED] xe_bo_evict_kunit ================
[06:42:27] =================== xe_bo_shrink_kunit  ====================
[06:42:27] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[06:42:27] ===================== [SKIPPED] xe_bo ======================
[06:42:27] ==================== args (11 subtests) ====================
[06:42:27] [PASSED] count_args_test
[06:42:27] [PASSED] call_args_example
[06:42:27] [PASSED] call_args_test
[06:42:27] [PASSED] drop_first_arg_example
[06:42:27] [PASSED] drop_first_arg_test
[06:42:27] [PASSED] first_arg_example
[06:42:27] [PASSED] first_arg_test
[06:42:27] [PASSED] last_arg_example
[06:42:27] [PASSED] last_arg_test
[06:42:27] [PASSED] pick_arg_example
[06:42:27] [PASSED] sep_comma_examplestty: 'standard input': Inappropriate ioctl for device

[06:42:27] ====================== [PASSED] args =======================
[06:42:27] =================== xe_pci (2 subtests) ====================
[06:42:27] [PASSED] xe_gmdid_graphics_ip
[06:42:27] [PASSED] xe_gmdid_media_ip
[06:42:27] ===================== [PASSED] xe_pci ======================
[06:42:27] =================== xe_rtp (2 subtests) ====================
[06:42:27] =============== xe_rtp_process_to_sr_tests  ================
[06:42:27] [PASSED] coalesce-same-reg
[06:42:27] [PASSED] no-match-no-add
[06:42:27] [PASSED] match-or
[06:42:27] [PASSED] match-or-xfail
[06:42:27] [PASSED] no-match-no-add-multiple-rules
[06:42:27] [PASSED] two-regs-two-entries
[06:42:27] [PASSED] clr-one-set-other
[06:42:27] [PASSED] set-field
[06:42:27] [PASSED] conflict-duplicate
[06:42:27] [PASSED] conflict-not-disjoint
[06:42:27] [PASSED] conflict-reg-type
[06:42:27] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[06:42:27] ================== xe_rtp_process_tests  ===================
[06:42:27] [PASSED] active1
[06:42:27] [PASSED] active2
[06:42:27] [PASSED] active-inactive
[06:42:27] [PASSED] inactive-active
[06:42:27] [PASSED] inactive-1st_or_active-inactive
[06:42:27] [PASSED] inactive-2nd_or_active-inactive
[06:42:27] [PASSED] inactive-last_or_active-inactive
[06:42:27] [PASSED] inactive-no_or_active-inactive
[06:42:27] ============== [PASSED] xe_rtp_process_tests ===============
[06:42:27] ===================== [PASSED] xe_rtp ======================
[06:42:27] ==================== xe_wa (1 subtest) =====================
[06:42:27] ======================== xe_wa_gt  =========================
[06:42:27] [PASSED] TIGERLAKE (B0)
[06:42:27] [PASSED] DG1 (A0)
[06:42:27] [PASSED] DG1 (B0)
[06:42:27] [PASSED] ALDERLAKE_S (A0)
[06:42:27] [PASSED] ALDERLAKE_S (B0)
[06:42:27] [PASSED] ALDERLAKE_S (C0)
[06:42:27] [PASSED] ALDERLAKE_S (D0)
[06:42:27] [PASSED] ALDERLAKE_P (A0)
[06:42:27] [PASSED] ALDERLAKE_P (B0)
[06:42:27] [PASSED] ALDERLAKE_P (C0)
[06:42:27] [PASSED] ALDERLAKE_S_RPLS (D0)
[06:42:27] [PASSED] ALDERLAKE_P_RPLU (E0)
[06:42:27] [PASSED] DG2_G10 (C0)
[06:42:27] [PASSED] DG2_G11 (B1)
[06:42:27] [PASSED] DG2_G12 (A1)
[06:42:27] [PASSED] METEORLAKE (g:A0, m:A0)
[06:42:27] [PASSED] METEORLAKE (g:A0, m:A0)
[06:42:27] [PASSED] METEORLAKE (g:A0, m:A0)
[06:42:27] [PASSED] LUNARLAKE (g:A0, m:A0)
[06:42:27] [PASSED] LUNARLAKE (g:B0, m:A0)
[06:42:27] [PASSED] BATTLEMAGE (g:A0, m:A1)
[06:42:27] ==================== [PASSED] xe_wa_gt =====================
[06:42:27] ====================== [PASSED] xe_wa ======================
[06:42:27] ============================================================
[06:42:27] Testing complete. Ran 122 tests: passed: 106, skipped: 16
[06:42:27] Elapsed time: 32.576s total, 4.462s configuring, 27.848s building, 0.223s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[06:42:27] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[06:42:29] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json ARCH=um O=.kunit --jobs=48
../lib/iomap.c:156:5: warning: no previous prototype for ‘ioread64_lo_hi’ [-Wmissing-prototypes]
  156 | u64 ioread64_lo_hi(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~
../lib/iomap.c:163:5: warning: no previous prototype for ‘ioread64_hi_lo’ [-Wmissing-prototypes]
  163 | u64 ioread64_hi_lo(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~
../lib/iomap.c:170:5: warning: no previous prototype for ‘ioread64be_lo_hi’ [-Wmissing-prototypes]
  170 | u64 ioread64be_lo_hi(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~~~
../lib/iomap.c:178:5: warning: no previous prototype for ‘ioread64be_hi_lo’ [-Wmissing-prototypes]
  178 | u64 ioread64be_hi_lo(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~~~
../lib/iomap.c:264:6: warning: no previous prototype for ‘iowrite64_lo_hi’ [-Wmissing-prototypes]
  264 | void iowrite64_lo_hi(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~
../lib/iomap.c:272:6: warning: no previous prototype for ‘iowrite64_hi_lo’ [-Wmissing-prototypes]
  272 | void iowrite64_hi_lo(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~
../lib/iomap.c:280:6: warning: no previous prototype for ‘iowrite64be_lo_hi’ [-Wmissing-prototypes]
  280 | void iowrite64be_lo_hi(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~~~
../lib/iomap.c:288:6: warning: no previous prototype for ‘iowrite64be_hi_lo’ [-Wmissing-prototypes]
  288 | void iowrite64be_hi_lo(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~~~

[06:42:52] Starting KUnit Kernel (1/1)...
[06:42:52] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[06:42:52] ================== drm_buddy (7 subtests) ==================
[06:42:52] [PASSED] drm_test_buddy_alloc_limit
[06:42:52] [PASSED] drm_test_buddy_alloc_optimistic
[06:42:52] [PASSED] drm_test_buddy_alloc_pessimistic
[06:42:52] [PASSED] drm_test_buddy_alloc_pathological
[06:42:52] [PASSED] drm_test_buddy_alloc_contiguous
[06:42:52] [PASSED] drm_test_buddy_alloc_clear
[06:42:52] [PASSED] drm_test_buddy_alloc_range_bias
[06:42:52] ==================== [PASSED] drm_buddy ====================
[06:42:52] ============= drm_cmdline_parser (40 subtests) =============
[06:42:52] [PASSED] drm_test_cmdline_force_d_only
[06:42:52] [PASSED] drm_test_cmdline_force_D_only_dvi
[06:42:52] [PASSED] drm_test_cmdline_force_D_only_hdmi
[06:42:52] [PASSED] drm_test_cmdline_force_D_only_not_digital
[06:42:52] [PASSED] drm_test_cmdline_force_e_only
[06:42:52] [PASSED] drm_test_cmdline_res
[06:42:52] [PASSED] drm_test_cmdline_res_vesa
[06:42:52] [PASSED] drm_test_cmdline_res_vesa_rblank
[06:42:52] [PASSED] drm_test_cmdline_res_rblank
[06:42:52] [PASSED] drm_test_cmdline_res_bpp
[06:42:52] [PASSED] drm_test_cmdline_res_refresh
[06:42:52] [PASSED] drm_test_cmdline_res_bpp_refresh
[06:42:52] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[06:42:52] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[06:42:52] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[06:42:52] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[06:42:52] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[06:42:52] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[06:42:52] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[06:42:52] [PASSED] drm_test_cmdline_res_margins_force_on
[06:42:52] [PASSED] drm_test_cmdline_res_vesa_margins
[06:42:52] [PASSED] drm_test_cmdline_name
[06:42:52] [PASSED] drm_test_cmdline_name_bpp
[06:42:52] [PASSED] drm_test_cmdline_name_option
[06:42:52] [PASSED] drm_test_cmdline_name_bpp_option
[06:42:52] [PASSED] drm_test_cmdline_rotate_0
[06:42:52] [PASSED] drm_test_cmdline_rotate_90
[06:42:52] [PASSED] drm_test_cmdline_rotate_180
[06:42:52] [PASSED] drm_test_cmdline_rotate_270
[06:42:52] [PASSED] drm_test_cmdline_hmirror
[06:42:52] [PASSED] drm_test_cmdline_vmirror
[06:42:52] [PASSED] drm_test_cmdline_margin_options
[06:42:52] [PASSED] drm_test_cmdline_multiple_options
[06:42:52] [PASSED] drm_test_cmdline_bpp_extra_and_option
[06:42:52] [PASSED] drm_test_cmdline_extra_and_option
[06:42:52] [PASSED] drm_test_cmdline_freestanding_options
[06:42:52] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[06:42:52] [PASSED] drm_test_cmdline_panel_orientation
[06:42:52] ================ drm_test_cmdline_invalid  =================
[06:42:52] [PASSED] margin_only
[06:42:52] [PASSED] interlace_only
[06:42:52] [PASSED] res_missing_x
[06:42:52] [PASSED] res_missing_y
[06:42:52] [PASSED] res_bad_y
[06:42:52] [PASSED] res_missing_y_bpp
[06:42:52] [PASSED] res_bad_bpp
[06:42:52] [PASSED] res_bad_refresh
[06:42:52] [PASSED] res_bpp_refresh_force_on_off
[06:42:52] [PASSED] res_invalid_mode
[06:42:52] [PASSED] res_bpp_wrong_place_mode
[06:42:52] [PASSED] name_bpp_refresh
[06:42:52] [PASSED] name_refresh
[06:42:52] [PASSED] name_refresh_wrong_mode
[06:42:52] [PASSED] name_refresh_invalid_mode
[06:42:52] [PASSED] rotate_multiple
[06:42:52] [PASSED] rotate_invalid_val
[06:42:52] [PASSED] rotate_truncated
[06:42:52] [PASSED] invalid_option
[06:42:52] [PASSED] invalid_tv_option
[06:42:52] [PASSED] truncated_tv_option
[06:42:52] ============ [PASSED] drm_test_cmdline_invalid =============
[06:42:52] =============== drm_test_cmdline_tv_options  ===============
[06:42:52] [PASSED] NTSC
[06:42:52] [PASSED] NTSC_443
[06:42:52] [PASSED] NTSC_J
[06:42:52] [PASSED] PAL
[06:42:52] [PASSED] PAL_M
[06:42:52] [PASSED] PAL_N
[06:42:52] [PASSED] SECAM
[06:42:52] [PASSED] MONO_525
[06:42:52] [PASSED] MONO_625
[06:42:52] =========== [PASSED] drm_test_cmdline_tv_options ===========
[06:42:52] =============== [PASSED] drm_cmdline_parser ================
[06:42:52] ========== drmm_connector_hdmi_init (19 subtests) ==========
[06:42:52] [PASSED] drm_test_connector_hdmi_init_valid
[06:42:52] [PASSED] drm_test_connector_hdmi_init_bpc_8
[06:42:52] [PASSED] drm_test_connector_hdmi_init_bpc_10
[06:42:52] [PASSED] drm_test_connector_hdmi_init_bpc_12
[06:42:52] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[06:42:52] [PASSED] drm_test_connector_hdmi_init_bpc_null
[06:42:52] [PASSED] drm_test_connector_hdmi_init_formats_empty
[06:42:52] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[06:42:52] [PASSED] drm_test_connector_hdmi_init_null_ddc
[06:42:52] [PASSED] drm_test_connector_hdmi_init_null_product
[06:42:52] [PASSED] drm_test_connector_hdmi_init_null_vendor
[06:42:52] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[06:42:52] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[06:42:52] [PASSED] drm_test_connector_hdmi_init_product_valid
[06:42:52] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[06:42:52] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[06:42:52] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[06:42:52] ========= drm_test_connector_hdmi_init_type_valid  =========
[06:42:52] [PASSED] HDMI-A
[06:42:52] [PASSED] HDMI-B
[06:42:52] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[06:42:52] ======== drm_test_connector_hdmi_init_type_invalid  ========
[06:42:52] [PASSED] Unknown
[06:42:52] [PASSED] VGA
[06:42:52] [PASSED] DVI-I
[06:42:52] [PASSED] DVI-D
[06:42:52] [PASSED] DVI-A
[06:42:52] [PASSED] Composite
[06:42:52] [PASSED] SVIDEO
[06:42:52] [PASSED] LVDS
[06:42:52] [PASSED] Component
[06:42:52] [PASSED] DIN
[06:42:52] [PASSED] DP
[06:42:52] [PASSED] TV
[06:42:52] [PASSED] eDP
[06:42:52] [PASSED] Virtual
[06:42:52] [PASSED] DSI
[06:42:52] [PASSED] DPI
[06:42:52] [PASSED] Writeback
[06:42:52] [PASSED] SPI
[06:42:52] [PASSED] USB
[06:42:52] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[06:42:52] ============ [PASSED] drmm_connector_hdmi_init =============
[06:42:52] ============= drmm_connector_init (3 subtests) =============
[06:42:52] [PASSED] drm_test_drmm_connector_init
[06:42:52] [PASSED] drm_test_drmm_connector_init_null_ddc
[06:42:52] ========= drm_test_drmm_connector_init_type_valid  =========
[06:42:52] [PASSED] Unknown
[06:42:52] [PASSED] VGA
[06:42:52] [PASSED] DVI-I
[06:42:52] [PASSED] DVI-D
[06:42:52] [PASSED] DVI-A
[06:42:52] [PASSED] Composite
[06:42:52] [PASSED] SVIDEO
[06:42:52] [PASSED] LVDS
[06:42:52] [PASSED] Component
[06:42:52] [PASSED] DIN
[06:42:52] [PASSED] DP
[06:42:52] [PASSED] HDMI-A
[06:42:52] [PASSED] HDMI-B
[06:42:52] [PASSED] TV
[06:42:52] [PASSED] eDP
[06:42:52] [PASSED] Virtual
[06:42:52] [PASSED] DSI
[06:42:52] [PASSED] DPI
[06:42:52] [PASSED] Writeback
[06:42:52] [PASSED] SPI
[06:42:52] [PASSED] USB
[06:42:52] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[06:42:52] =============== [PASSED] drmm_connector_init ===============
[06:42:52] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[06:42:52] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[06:42:52] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[06:42:52] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[06:42:52] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[06:42:52] ========== drm_test_get_tv_mode_from_name_valid  ===========
[06:42:52] [PASSED] NTSC
[06:42:52] [PASSED] NTSC-443
[06:42:52] [PASSED] NTSC-J
[06:42:52] [PASSED] PAL
[06:42:52] [PASSED] PAL-M
[06:42:52] [PASSED] PAL-N
[06:42:52] [PASSED] SECAM
[06:42:52] [PASSED] Mono
[06:42:52] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[06:42:52] [PASSED] drm_test_get_tv_mode_from_name_truncated
[06:42:52] ============ [PASSED] drm_get_tv_mode_from_name ============
[06:42:52] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[06:42:52] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[06:42:52] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[06:42:52] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[06:42:52] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[06:42:52] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[06:42:52] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[06:42:52] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[06:42:52] [PASSED] VIC 96
[06:42:52] [PASSED] VIC 97
[06:42:52] [PASSED] VIC 101
[06:42:52] [PASSED] VIC 102
[06:42:52] [PASSED] VIC 106
[06:42:52] [PASSED] VIC 107
[06:42:52] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[06:42:52] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[06:42:52] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[06:42:52] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[06:42:52] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[06:42:52] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[06:42:52] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[06:42:52] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[06:42:52] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[06:42:52] [PASSED] Automatic
[06:42:52] [PASSED] Full
[06:42:52] [PASSED] Limited 16:235
[06:42:52] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[06:42:52] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[06:42:52] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[06:42:52] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[06:42:52] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[06:42:52] [PASSED] RGB
[06:42:52] [PASSED] YUV 4:2:0
[06:42:52] [PASSED] YUV 4:2:2
[06:42:52] [PASSED] YUV 4:4:4
[06:42:52] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[06:42:52] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[06:42:52] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[06:42:52] ============= drm_damage_helper (21 subtests) ==============
[06:42:52] [PASSED] drm_test_damage_iter_no_damage
[06:42:52] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[06:42:52] [PASSED] drm_test_damage_iter_no_damage_src_moved
[06:42:52] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[06:42:52] [PASSED] drm_test_damage_iter_no_damage_not_visible
[06:42:52] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[06:42:52] [PASSED] drm_test_damage_iter_no_damage_no_fb
[06:42:52] [PASSED] drm_test_damage_iter_simple_damage
[06:42:52] [PASSED] drm_test_damage_iter_single_damage
[06:42:52] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[06:42:52] [PASSED] drm_test_damage_iter_single_damage_outside_src
[06:42:52] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[06:42:52] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[06:42:52] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[06:42:52] [PASSED] drm_test_damage_iter_single_damage_src_moved
[06:42:52] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[06:42:52] [PASSED] drm_test_damage_iter_damage
[06:42:52] [PASSED] drm_test_damage_iter_damage_one_intersect
[06:42:52] [PASSED] drm_test_damage_iter_damage_one_outside
[06:42:52] [PASSED] drm_test_damage_iter_damage_src_moved
[06:42:52] [PASSED] drm_test_damage_iter_damage_not_visible
[06:42:52] ================ [PASSED] drm_damage_helper ================
[06:42:52] ============== drm_dp_mst_helper (3 subtests) ==============
[06:42:52] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[06:42:52] [PASSED] Clock 154000 BPP 30 DSC disabled
[06:42:52] [PASSED] Clock 234000 BPP 30 DSC disabled
[06:42:52] [PASSED] Clock 297000 BPP 24 DSC disabled
[06:42:52] [PASSED] Clock 332880 BPP 24 DSC enabled
[06:42:52] [PASSED] Clock 324540 BPP 24 DSC enabled
[06:42:52] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[06:42:52] ============== drm_test_dp_mst_calc_pbn_div  ===============
[06:42:52] [PASSED] Link rate 2000000 lane count 4
[06:42:52] [PASSED] Link rate 2000000 lane count 2
[06:42:52] [PASSED] Link rate 2000000 lane count 1
[06:42:52] [PASSED] Link rate 1350000 lane count 4
[06:42:52] [PASSED] Link rate 1350000 lane count 2
[06:42:52] [PASSED] Link rate 1350000 lane count 1
[06:42:52] [PASSED] Link rate 1000000 lane count 4
[06:42:52] [PASSED] Link rate 1000000 lane count 2
[06:42:52] [PASSED] Link rate 1000000 lane count 1
[06:42:52] [PASSED] Link rate 810000 lane count 4
[06:42:52] [PASSED] Link rate 810000 lane count 2
[06:42:52] [PASSED] Link rate 810000 lane count 1
[06:42:52] [PASSED] Link rate 540000 lane count 4
[06:42:52] [PASSED] Link rate 540000 lane count 2
[06:42:52] [PASSED] Link rate 540000 lane count 1
[06:42:52] [PASSED] Link rate 270000 lane count 4
[06:42:52] [PASSED] Link rate 270000 lane count 2
[06:42:52] [PASSED] Link rate 270000 lane count 1
[06:42:52] [PASSED] Link rate 162000 lane count 4
[06:42:52] [PASSED] Link rate 162000 lane count 2
[06:42:52] [PASSED] Link rate 162000 lane count 1
[06:42:52] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[06:42:52] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[06:42:52] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[06:42:52] [PASSED] DP_POWER_UP_PHY with port number
[06:42:52] [PASSED] DP_POWER_DOWN_PHY with port number
[06:42:52] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[06:42:52] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[06:42:52] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[06:42:52] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[06:42:52] [PASSED] DP_QUERY_PAYLOAD with port number
[06:42:52] [PASSED] DP_QUERY_PAYLOAD with VCPI
[06:42:52] [PASSED] DP_REMOTE_DPCD_READ with port number
[06:42:52] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[06:42:52] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[06:42:52] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[06:42:52] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[06:42:52] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[06:42:52] [PASSED] DP_REMOTE_I2C_READ with port number
[06:42:52] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[06:42:52] [PASSED] DP_REMOTE_I2C_READ with transactions array
[06:42:52] [PASSED] DP_REMOTE_I2C_WRITE with port number
[06:42:52] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[06:42:52] [PASSED] DP_REMOTE_I2C_WRITE with data array
[06:42:52] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[06:42:52] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[06:42:52] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[06:42:52] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[06:42:52] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[06:42:52] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[06:42:52] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[06:42:52] ================ [PASSED] drm_dp_mst_helper ================
[06:42:52] ================== drm_exec (7 subtests) ===================
[06:42:52] [PASSED] sanitycheck
[06:42:52] [PASSED] test_lock
[06:42:52] [PASSED] test_lock_unlock
[06:42:52] [PASSED] test_duplicates
[06:42:52] [PASSED] test_prepare
[06:42:52] [PASSED] test_prepare_array
[06:42:52] [PASSED] test_multiple_loops
[06:42:52] ==================== [PASSED] drm_exec =====================
[06:42:52] =========== drm_format_helper_test (17 subtests) ===========
[06:42:52] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[06:42:52] [PASSED] single_pixel_source_buffer
[06:42:52] [PASSED] single_pixel_clip_rectangle
[06:42:52] [PASSED] well_known_colors
[06:42:52] [PASSED] destination_pitch
[06:42:52] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[06:42:52] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[06:42:52] [PASSED] single_pixel_source_buffer
[06:42:52] [PASSED] single_pixel_clip_rectangle
[06:42:52] [PASSED] well_known_colors
[06:42:52] [PASSED] destination_pitch
[06:42:52] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[06:42:52] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[06:42:52] [PASSED] single_pixel_source_buffer
[06:42:52] [PASSED] single_pixel_clip_rectangle
[06:42:52] [PASSED] well_known_colors
[06:42:52] [PASSED] destination_pitch
[06:42:52] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[06:42:52] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[06:42:52] [PASSED] single_pixel_source_buffer
[06:42:52] [PASSED] single_pixel_clip_rectangle
[06:42:52] [PASSED] well_known_colors
[06:42:52] [PASSED] destination_pitch
[06:42:52] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[06:42:52] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[06:42:52] [PASSED] single_pixel_source_buffer
[06:42:52] [PASSED] single_pixel_clip_rectangle
[06:42:52] [PASSED] well_known_colors
[06:42:52] [PASSED] destination_pitch
[06:42:52] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[06:42:52] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[06:42:52] [PASSED] single_pixel_source_buffer
[06:42:52] [PASSED] single_pixel_clip_rectangle
[06:42:52] [PASSED] well_known_colors
[06:42:52] [PASSED] destination_pitch
[06:42:52] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[06:42:52] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[06:42:52] [PASSED] single_pixel_source_buffer
[06:42:52] [PASSED] single_pixel_clip_rectangle
[06:42:52] [PASSED] well_known_colors
[06:42:52] [PASSED] destination_pitch
[06:42:52] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[06:42:52] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[06:42:52] [PASSED] single_pixel_source_buffer
[06:42:52] [PASSED] single_pixel_clip_rectangle
[06:42:52] [PASSED] well_known_colors
[06:42:52] [PASSED] destination_pitch
[06:42:52] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[06:42:52] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[06:42:52] [PASSED] single_pixel_source_buffer
[06:42:52] [PASSED] single_pixel_clip_rectangle
[06:42:52] [PASSED] well_known_colors
[06:42:52] [PASSED] destination_pitch
[06:42:52] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[06:42:52] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[06:42:52] [PASSED] single_pixel_source_buffer
[06:42:52] [PASSED] single_pixel_clip_rectangle
[06:42:52] [PASSED] well_known_colors
[06:42:52] [PASSED] destination_pitch
[06:42:52] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[06:42:52] ============== drm_test_fb_xrgb8888_to_mono  ===============
[06:42:52] [PASSED] single_pixel_source_buffer
[06:42:52] [PASSED] single_pixel_clip_rectangle
[06:42:52] [PASSED] well_known_colors
[06:42:52] [PASSED] destination_pitch
[06:42:52] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[06:42:52] ==================== drm_test_fb_swab  =====================
[06:42:52] [PASSED] single_pixel_source_buffer
[06:42:52] [PASSED] single_pixel_clip_rectangle
[06:42:52] [PASSED] well_known_colors
[06:42:52] [PASSED] destination_pitch
[06:42:52] ================ [PASSED] drm_test_fb_swab =================
[06:42:52] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[06:42:52] [PASSED] single_pixel_source_buffer
[06:42:52] [PASSED] single_pixel_clip_rectangle
[06:42:52] [PASSED] well_known_colors
[06:42:52] [PASSED] destination_pitch
[06:42:52] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[06:42:52] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[06:42:52] [PASSED] single_pixel_source_buffer
[06:42:52] [PASSED] single_pixel_clip_rectangle
[06:42:52] [PASSED] well_known_colors
[06:42:52] [PASSED] destination_pitch
[06:42:52] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[06:42:52] ================= drm_test_fb_clip_offset  =================
[06:42:52] [PASSED] pass through
[06:42:52] [PASSED] horizontal offset
[06:42:52] [PASSED] vertical offset
[06:42:52] [PASSED] horizontal and vertical offset
[06:42:52] [PASSED] horizontal offset (custom pitch)
[06:42:52] [PASSED] vertical offset (custom pitch)
[06:42:52] [PASSED] horizontal and vertical offset (custom pitch)
[06:42:52] ============= [PASSED] drm_test_fb_clip_offset =============
[06:42:52] ============== drm_test_fb_build_fourcc_list  ==============
[06:42:52] [PASSED] no native formats
[06:42:52] [PASSED] XRGB8888 as native format
[06:42:52] [PASSED] remove duplicates
[06:42:52] [PASSED] convert alpha formats
[06:42:52] [PASSED] random formats
[06:42:52] ========== [PASSED] drm_test_fb_build_fourcc_list ==========
[06:42:52] =================== drm_test_fb_memcpy  ====================
[06:42:52] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[06:42:52] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[06:42:52] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[06:42:52] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[06:42:52] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[06:42:52] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[06:42:52] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[06:42:52] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[06:42:52] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[06:42:52] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[06:42:52] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[06:42:52] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[06:42:52] =============== [PASSED] drm_test_fb_memcpy ================
[06:42:52] ============= [PASSED] drm_format_helper_test ==============
[06:42:52] ================= drm_format (18 subtests) =================
[06:42:52] [PASSED] drm_test_format_block_width_invalid
[06:42:52] [PASSED] drm_test_format_block_width_one_plane
[06:42:52] [PASSED] drm_test_format_block_width_two_plane
[06:42:52] [PASSED] drm_test_format_block_width_three_plane
[06:42:52] [PASSED] drm_test_format_block_width_tiled
[06:42:52] [PASSED] drm_test_format_block_height_invalid
[06:42:52] [PASSED] drm_test_format_block_height_one_plane
[06:42:52] [PASSED] drm_test_format_block_height_two_plane
[06:42:52] [PASSED] drm_test_format_block_height_three_plane
[06:42:52] [PASSED] drm_test_format_block_height_tiled
[06:42:52] [PASSED] drm_test_format_min_pitch_invalid
[06:42:52] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[06:42:52] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[06:42:52] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[06:42:52] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[06:42:52] [PASSED] drm_test_format_min_pitch_two_plane
[06:42:52] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[06:42:52] [PASSED] drm_test_format_min_pitch_tiled
[06:42:52] =================== [PASSED] drm_format ====================
[06:42:52] ============== drm_framebuffer (10 subtests) ===============
[06:42:52] ========== drm_test_framebuffer_check_src_coords  ==========
[06:42:52] [PASSED] Success: source fits into fb
[06:42:52] [PASSED] Fail: overflowing fb with x-axis coordinate
[06:42:52] [PASSED] Fail: overflowing fb with y-axis coordinate
[06:42:52] [PASSED] Fail: overflowing fb with source width
[06:42:52] [PASSED] Fail: overflowing fb with source height
[06:42:52] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[06:42:52] [PASSED] drm_test_framebuffer_cleanup
[06:42:52] =============== drm_test_framebuffer_create  ===============
[06:42:52] [PASSED] ABGR8888 normal sizes
[06:42:52] [PASSED] ABGR8888 max sizes
[06:42:52] [PASSED] ABGR8888 pitch greater than min required
[06:42:52] [PASSED] ABGR8888 pitch less than min required
[06:42:52] [PASSED] ABGR8888 Invalid width
[06:42:52] [PASSED] ABGR8888 Invalid buffer handle
[06:42:52] [PASSED] No pixel format
[06:42:52] [PASSED] ABGR8888 Width 0
[06:42:52] [PASSED] ABGR8888 Height 0
[06:42:52] [PASSED] ABGR8888 Out of bound height * pitch combination
[06:42:52] [PASSED] ABGR8888 Large buffer offset
[06:42:52] [PASSED] ABGR8888 Buffer offset for inexistent plane
[06:42:52] [PASSED] ABGR8888 Invalid flag
[06:42:52] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[06:42:52] [PASSED] ABGR8888 Valid buffer modifier
[06:42:52] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[06:42:52] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[06:42:52] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[06:42:52] [PASSED] NV12 Normal sizes
[06:42:52] [PASSED] NV12 Max sizes
[06:42:52] [PASSED] NV12 Invalid pitch
[06:42:52] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[06:42:52] [PASSED] NV12 different  modifier per-plane
[06:42:52] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[06:42:52] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[06:42:52] [PASSED] NV12 Modifier for inexistent plane
[06:42:52] [PASSED] NV12 Handle for inexistent plane
[06:42:52] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[06:42:52] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[06:42:52] [PASSED] YVU420 Normal sizes
[06:42:52] [PASSED] YVU420 Max sizes
[06:42:52] [PASSED] YVU420 Invalid pitch
[06:42:52] [PASSED] YVU420 Different pitches
[06:42:52] [PASSED] YVU420 Different buffer offsets/pitches
[06:42:52] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[06:42:52] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[06:42:52] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[06:42:52] [PASSED] YVU420 Valid modifier
[06:42:52] [PASSED] YVU420 Different modifiers per plane
[06:42:52] [PASSED] YVU420 Modifier for inexistent plane
[06:42:52] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[06:42:52] [PASSED] X0L2 Normal sizes
[06:42:52] [PASSED] X0L2 Max sizes
[06:42:52] [PASSED] X0L2 Invalid pitch
[06:42:52] [PASSED] X0L2 Pitch greater than minimum required
[06:42:52] [PASSED] X0L2 Handle for inexistent plane
[06:42:52] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[06:42:52] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[06:42:52] [PASSED] X0L2 Valid modifier
[06:42:52] [PASSED] X0L2 Modifier for inexistent plane
[06:42:52] =========== [PASSED] drm_test_framebuffer_create ===========
[06:42:52] [PASSED] drm_test_framebuffer_free
[06:42:52] [PASSED] drm_test_framebuffer_init
[06:42:52] [PASSED] drm_test_framebuffer_init_bad_format
[06:42:52] [PASSED] drm_test_framebuffer_init_dev_mismatch
[06:42:52] [PASSED] drm_test_framebuffer_lookup
[06:42:52] [PASSED] drm_test_framebuffer_lookup_inexistent
[06:42:52] [PASSED] drm_test_framebuffer_modifiers_not_supported
[06:42:52] ================= [PASSED] drm_framebuffer =================
[06:42:52] ================ drm_gem_shmem (8 subtests) ================
[06:42:52] [PASSED] drm_gem_shmem_test_obj_create
[06:42:52] [PASSED] drm_gem_shmem_test_obj_create_private
[06:42:52] [PASSED] drm_gem_shmem_test_pin_pages
[06:42:52] [PASSED] drm_gem_shmem_test_vmap
[06:42:52] [PASSED] drm_gem_shmem_test_get_pages_sgt
[06:42:52] [PASSED] drm_gem_shmem_test_get_sg_table
[06:42:52] [PASSED] drm_gem_shmem_test_madvise
[06:42:52] [PASSED] drm_gem_shmem_test_purge
[06:42:52] ================== [PASSED] drm_gem_shmem ==================
[06:42:52] === drm_atomic_helper_connector_hdmi_check (22 subtests) ===
[06:42:52] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[06:42:52] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[06:42:52] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[06:42:52] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[06:42:52] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[06:42:52] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[06:42:52] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[06:42:52] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[06:42:52] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[06:42:52] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback
[06:42:52] [PASSED] drm_test_check_max_tmds_rate_format_fallback
[06:42:52] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[06:42:52] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[06:42:52] [PASSED] drm_test_check_output_bpc_dvi
[06:42:52] [PASSED] drm_test_check_output_bpc_format_vic_1
[06:42:52] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[06:42:52] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[06:42:52] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[06:42:52] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[06:42:52] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[06:42:52] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[06:42:52] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[06:42:52] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[06:42:52] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[06:42:52] [PASSED] drm_test_check_broadcast_rgb_value
[06:42:52] [PASSED] drm_test_check_bpc_8_value
[06:42:52] [PASSED] drm_test_check_bpc_10_value
[06:42:52] [PASSED] drm_test_check_bpc_12_value
[06:42:52] [PASSED] drm_test_check_format_value
[06:42:52] [PASSED] drm_test_check_tmds_char_value
[06:42:52] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[06:42:52] ================= drm_managed (2 subtests) =================
[06:42:52] [PASSED] drm_test_managed_release_action
[06:42:52] [PASSED] drm_test_managed_run_action
[06:42:52] =================== [PASSED] drm_managed ===================
[06:42:52] =================== drm_mm (6 subtests) ====================
[06:42:52] [PASSED] drm_test_mm_init
[06:42:52] [PASSED] drm_test_mm_debug
[06:42:52] [PASSED] drm_test_mm_align32
[06:42:52] [PASSED] drm_test_mm_align64
[06:42:52] [PASSED] drm_test_mm_lowest
[06:42:52] [PASSED] drm_test_mm_highest
[06:42:52] ===================== [PASSED] drm_mm ======================
[06:42:52] ============= drm_modes_analog_tv (5 subtests) =============
[06:42:52] [PASSED] drm_test_modes_analog_tv_mono_576i
[06:42:52] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[06:42:52] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[06:42:52] [PASSED] drm_test_modes_analog_tv_pal_576i
[06:42:52] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[06:42:52] =============== [PASSED] drm_modes_analog_tv ===============
stty: 'standard input': Inappropriate ioctl for device
[06:42:52] ============== drm_plane_helper (2 subtests) ===============
[06:42:52] =============== drm_test_check_plane_state  ================
[06:42:52] [PASSED] clipping_simple
[06:42:52] [PASSED] clipping_rotate_reflect
[06:42:52] [PASSED] positioning_simple
[06:42:52] [PASSED] upscaling
[06:42:52] [PASSED] downscaling
[06:42:52] [PASSED] rounding1
[06:42:52] [PASSED] rounding2
[06:42:52] [PASSED] rounding3
[06:42:52] [PASSED] rounding4
[06:42:52] =========== [PASSED] drm_test_check_plane_state ============
[06:42:52] =========== drm_test_check_invalid_plane_state  ============
[06:42:52] [PASSED] positioning_invalid
[06:42:52] [PASSED] upscaling_invalid
[06:42:52] [PASSED] downscaling_invalid
[06:42:52] ======= [PASSED] drm_test_check_invalid_plane_state ========
[06:42:52] ================ [PASSED] drm_plane_helper =================
[06:42:52] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[06:42:52] ====== drm_test_connector_helper_tv_get_modes_check  =======
[06:42:52] [PASSED] None
[06:42:52] [PASSED] PAL
[06:42:52] [PASSED] NTSC
[06:42:52] [PASSED] Both, NTSC Default
[06:42:52] [PASSED] Both, PAL Default
[06:42:52] [PASSED] Both, NTSC Default, with PAL on command-line
[06:42:52] [PASSED] Both, PAL Default, with NTSC on command-line
[06:42:52] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[06:42:52] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[06:42:52] ================== drm_rect (9 subtests) ===================
[06:42:52] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[06:42:52] [PASSED] drm_test_rect_clip_scaled_not_clipped
[06:42:52] [PASSED] drm_test_rect_clip_scaled_clipped
[06:42:52] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[06:42:52] ================= drm_test_rect_intersect  =================
[06:42:52] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[06:42:52] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[06:42:52] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[06:42:52] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[06:42:52] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[06:42:52] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[06:42:52] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[06:42:52] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[06:42:52] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[06:42:52] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[06:42:52] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[06:42:52] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[06:42:52] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[06:42:52] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[06:42:52] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[06:42:52] ============= [PASSED] drm_test_rect_intersect =============
[06:42:52] ================ drm_test_rect_calc_hscale  ================
[06:42:52] [PASSED] normal use
[06:42:52] [PASSED] out of max range
[06:42:52] [PASSED] out of min range
[06:42:52] [PASSED] zero dst
[06:42:52] [PASSED] negative src
[06:42:52] [PASSED] negative dst
[06:42:52] ============ [PASSED] drm_test_rect_calc_hscale ============
[06:42:52] ================ drm_test_rect_calc_vscale  ================
[06:42:52] [PASSED] normal use
[06:42:52] [PASSED] out of max range
[06:42:52] [PASSED] out of min range
[06:42:52] [PASSED] zero dst
[06:42:52] [PASSED] negative src
[06:42:52] [PASSED] negative dst
[06:42:52] ============ [PASSED] drm_test_rect_calc_vscale ============
[06:42:52] ================== drm_test_rect_rotate  ===================
[06:42:52] [PASSED] reflect-x
[06:42:52] [PASSED] reflect-y
[06:42:52] [PASSED] rotate-0
[06:42:52] [PASSED] rotate-90
[06:42:52] [PASSED] rotate-180
[06:42:52] [PASSED] rotate-270
[06:42:52] ============== [PASSED] drm_test_rect_rotate ===============
[06:42:52] ================ drm_test_rect_rotate_inv  =================
[06:42:52] [PASSED] reflect-x
[06:42:52] [PASSED] reflect-y
[06:42:52] [PASSED] rotate-0
[06:42:52] [PASSED] rotate-90
[06:42:52] [PASSED] rotate-180
[06:42:52] [PASSED] rotate-270
[06:42:52] ============ [PASSED] drm_test_rect_rotate_inv =============
[06:42:52] ==================== [PASSED] drm_rect =====================
[06:42:52] ============================================================
[06:42:52] Testing complete. Ran 526 tests: passed: 526
[06:42:52] Elapsed time: 24.837s total, 1.640s configuring, 22.980s building, 0.168s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[06:42:52] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[06:42:54] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json ARCH=um O=.kunit --jobs=48
[06:43:01] Starting KUnit Kernel (1/1)...
[06:43:01] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[06:43:02] ================= ttm_device (5 subtests) ==================
[06:43:02] [PASSED] ttm_device_init_basic
[06:43:02] [PASSED] ttm_device_init_multiple
[06:43:02] [PASSED] ttm_device_fini_basic
[06:43:02] [PASSED] ttm_device_init_no_vma_man
[06:43:02] ================== ttm_device_init_pools  ==================
[06:43:02] [PASSED] No DMA allocations, no DMA32 required
[06:43:02] [PASSED] DMA allocations, DMA32 required
[06:43:02] [PASSED] No DMA allocations, DMA32 required
[06:43:02] [PASSED] DMA allocations, no DMA32 required
[06:43:02] ============== [PASSED] ttm_device_init_pools ==============
[06:43:02] =================== [PASSED] ttm_device ====================
[06:43:02] ================== ttm_pool (8 subtests) ===================
[06:43:02] ================== ttm_pool_alloc_basic  ===================
[06:43:02] [PASSED] One page
[06:43:02] [PASSED] More than one page
[06:43:02] [PASSED] Above the allocation limit
[06:43:02] [PASSED] One page, with coherent DMA mappings enabled
[06:43:02] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[06:43:02] ============== [PASSED] ttm_pool_alloc_basic ===============
[06:43:02] ============== ttm_pool_alloc_basic_dma_addr  ==============
[06:43:02] [PASSED] One page
[06:43:02] [PASSED] More than one page
[06:43:02] [PASSED] Above the allocation limit
[06:43:02] [PASSED] One page, with coherent DMA mappings enabled
[06:43:02] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[06:43:02] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[06:43:02] [PASSED] ttm_pool_alloc_order_caching_match
[06:43:02] [PASSED] ttm_pool_alloc_caching_mismatch
[06:43:02] [PASSED] ttm_pool_alloc_order_mismatch
[06:43:02] [PASSED] ttm_pool_free_dma_alloc
[06:43:02] [PASSED] ttm_pool_free_no_dma_alloc
[06:43:02] [PASSED] ttm_pool_fini_basic
[06:43:02] ==================== [PASSED] ttm_pool =====================
[06:43:02] ================ ttm_resource (8 subtests) =================
[06:43:02] ================= ttm_resource_init_basic  =================
[06:43:02] [PASSED] Init resource in TTM_PL_SYSTEM
[06:43:02] [PASSED] Init resource in TTM_PL_VRAM
[06:43:02] [PASSED] Init resource in a private placement
[06:43:02] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[06:43:02] ============= [PASSED] ttm_resource_init_basic =============
[06:43:02] [PASSED] ttm_resource_init_pinned
[06:43:02] [PASSED] ttm_resource_fini_basic
[06:43:02] [PASSED] ttm_resource_manager_init_basic
[06:43:02] [PASSED] ttm_resource_manager_usage_basic
[06:43:02] [PASSED] ttm_resource_manager_set_used_basic
[06:43:02] [PASSED] ttm_sys_man_alloc_basic
[06:43:02] [PASSED] ttm_sys_man_free_basic
[06:43:02] ================== [PASSED] ttm_resource ===================
[06:43:02] =================== ttm_tt (15 subtests) ===================
[06:43:02] ==================== ttm_tt_init_basic  ====================
[06:43:02] [PASSED] Page-aligned size
[06:43:02] [PASSED] Extra pages requested
[06:43:02] ================ [PASSED] ttm_tt_init_basic ================
[06:43:02] [PASSED] ttm_tt_init_misaligned
[06:43:02] [PASSED] ttm_tt_fini_basic
[06:43:02] [PASSED] ttm_tt_fini_sg
[06:43:02] [PASSED] ttm_tt_fini_shmem
[06:43:02] [PASSED] ttm_tt_create_basic
[06:43:02] [PASSED] ttm_tt_create_invalid_bo_type
[06:43:02] [PASSED] ttm_tt_create_ttm_exists
[06:43:02] [PASSED] ttm_tt_create_failed
[06:43:02] [PASSED] ttm_tt_destroy_basic
[06:43:02] [PASSED] ttm_tt_populate_null_ttm
[06:43:02] [PASSED] ttm_tt_populate_populated_ttm
[06:43:02] [PASSED] ttm_tt_unpopulate_basic
[06:43:02] [PASSED] ttm_tt_unpopulate_empty_ttm
[06:43:02] [PASSED] ttm_tt_swapin_basic
[06:43:02] ===================== [PASSED] ttm_tt ======================
[06:43:02] =================== ttm_bo (14 subtests) ===================
[06:43:02] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[06:43:02] [PASSED] Cannot be interrupted and sleeps
[06:43:02] [PASSED] Cannot be interrupted, locks straight away
[06:43:02] [PASSED] Can be interrupted, sleeps
[06:43:02] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[06:43:02] [PASSED] ttm_bo_reserve_locked_no_sleep
[06:43:02] [PASSED] ttm_bo_reserve_no_wait_ticket
[06:43:02] [PASSED] ttm_bo_reserve_double_resv
[06:43:02] [PASSED] ttm_bo_reserve_interrupted
[06:43:02] [PASSED] ttm_bo_reserve_deadlock
[06:43:02] [PASSED] ttm_bo_unreserve_basic
[06:43:02] [PASSED] ttm_bo_unreserve_pinned
[06:43:02] [PASSED] ttm_bo_unreserve_bulk
[06:43:02] [PASSED] ttm_bo_put_basic
[06:43:02] [PASSED] ttm_bo_put_shared_resv
[06:43:02] [PASSED] ttm_bo_pin_basic
[06:43:02] [PASSED] ttm_bo_pin_unpin_resource
[06:43:02] [PASSED] ttm_bo_multiple_pin_one_unpin
[06:43:02] ===================== [PASSED] ttm_bo ======================
[06:43:02] ============== ttm_bo_validate (22 subtests) ===============
[06:43:02] ============== ttm_bo_init_reserved_sys_man  ===============
[06:43:02] [PASSED] Buffer object for userspace
[06:43:02] [PASSED] Kernel buffer object
[06:43:02] [PASSED] Shared buffer object
[06:43:02] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[06:43:02] ============== ttm_bo_init_reserved_mock_man  ==============
[06:43:02] [PASSED] Buffer object for userspace
[06:43:02] [PASSED] Kernel buffer object
[06:43:02] [PASSED] Shared buffer object
[06:43:02] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[06:43:02] [PASSED] ttm_bo_init_reserved_resv
[06:43:02] ================== ttm_bo_validate_basic  ==================
[06:43:02] [PASSED] Buffer object for userspace
[06:43:02] [PASSED] Kernel buffer object
[06:43:02] [PASSED] Shared buffer object
[06:43:02] ============== [PASSED] ttm_bo_validate_basic ==============
[06:43:02] [PASSED] ttm_bo_validate_invalid_placement
[06:43:02] ============= ttm_bo_validate_same_placement  ==============
[06:43:02] [PASSED] System manager
[06:43:02] [PASSED] VRAM manager
[06:43:02] ========= [PASSED] ttm_bo_validate_same_placement ==========
[06:43:02] [PASSED] ttm_bo_validate_failed_alloc
[06:43:02] [PASSED] ttm_bo_validate_pinned
[06:43:02] [PASSED] ttm_bo_validate_busy_placement
[06:43:02] ================ ttm_bo_validate_multihop  =================
[06:43:02] [PASSED] Buffer object for userspace
[06:43:02] [PASSED] Kernel buffer object
[06:43:02] [PASSED] Shared buffer object
[06:43:02] ============ [PASSED] ttm_bo_validate_multihop =============
[06:43:02] ========== ttm_bo_validate_no_placement_signaled  ==========
[06:43:02] [PASSED] Buffer object in system domain, no page vector
[06:43:02] [PASSED] Buffer object in system domain with an existing page vector
[06:43:02] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[06:43:02] ======== ttm_bo_validate_no_placement_not_signaled  ========
[06:43:02] [PASSED] Buffer object for userspace
[06:43:02] [PASSED] Kernel buffer object
[06:43:02] [PASSED] Shared buffer object
[06:43:02] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[06:43:02] [PASSED] ttm_bo_validate_move_fence_signaled
[06:43:02] ========= ttm_bo_validate_move_fence_not_signaled  =========
[06:43:02] [PASSED] Waits for GPU
[06:43:02] [PASSED] Tries to lock straight away
[06:43:02] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[06:43:02] [PASSED] ttm_bo_validate_swapout
[06:43:02] [PASSED] ttm_bo_validate_happy_evict
[06:43:02] [PASSED] ttm_bo_validate_all_pinned_evict
[06:43:02] [PASSED] ttm_bo_validate_allowed_only_evict
[06:43:02] [PASSED] ttm_bo_validate_deleted_evict
[06:43:02] [PASSED] ttm_bo_validate_busy_domain_evict
[06:43:02] [PASSED] ttm_bo_validate_evict_gutting
[06:43:02] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[06:43:02] ================= [PASSED] ttm_bo_validate =================
[06:43:02] ============================================================
[06:43:02] Testing complete. Ran 102 tests: passed: 102
[06:43:02] Elapsed time: 9.969s total, 1.633s configuring, 7.669s building, 0.562s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✗ CI.Build: failure for series starting with [1/2] drm/i915/display: Refactor handling of dpkgc latency programming

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/display: Refactor handling of dpkgc latency programming
URL   : https://patchwork.freedesktop.org/series/141385/
State : failure

== Summary ==

lib/modules/6.12.0-rc7-xe/kernel/crypto/ecrdsa_generic.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/xcbc.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/serpent_generic.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/aria_generic.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/crypto_simd.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/adiantum.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/tcrypt.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/crypto_engine.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/zstd.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/asymmetric_keys/
lib/modules/6.12.0-rc7-xe/kernel/crypto/asymmetric_keys/pkcs7_test_key.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/asymmetric_keys/pkcs8_key_parser.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/des_generic.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/xctr.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/authenc.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/sm4_generic.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/keywrap.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/camellia_generic.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/sm3.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/pcrypt.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/aegis128.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/af_alg.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/algif_aead.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/cmac.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/sm3_generic.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/aes_ti.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/chacha_generic.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/poly1305_generic.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/nhpoly1305.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/crc32_generic.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/essiv.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/ccm.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/wp512.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/streebog_generic.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/authencesn.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/echainiv.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/lrw.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/cryptd.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/crypto_user.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/algif_hash.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/vmac.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/polyval-generic.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/hctr2.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/842.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/pcbc.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/ansi_cprng.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/cast6_generic.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/twofish_common.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/twofish_generic.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/lz4hc.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/blowfish_generic.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/md4.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/chacha20poly1305.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/curve25519-generic.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/lz4.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/rmd160.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/algif_skcipher.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/cast5_generic.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/fcrypt.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/ecdsa_generic.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/sm4.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/cast_common.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/blowfish_common.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/michael_mic.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/async_tx/
lib/modules/6.12.0-rc7-xe/kernel/crypto/async_tx/async_xor.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/async_tx/async_tx.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/async_tx/async_memcpy.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/async_tx/async_pq.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/async_tx/async_raid6_recov.ko
lib/modules/6.12.0-rc7-xe/kernel/crypto/algif_rng.ko
lib/modules/6.12.0-rc7-xe/kernel/block/
lib/modules/6.12.0-rc7-xe/kernel/block/bfq.ko
lib/modules/6.12.0-rc7-xe/kernel/block/kyber-iosched.ko
lib/modules/6.12.0-rc7-xe/build
lib/modules/6.12.0-rc7-xe/modules.alias.bin
lib/modules/6.12.0-rc7-xe/modules.builtin
lib/modules/6.12.0-rc7-xe/modules.softdep
lib/modules/6.12.0-rc7-xe/modules.alias
lib/modules/6.12.0-rc7-xe/modules.order
lib/modules/6.12.0-rc7-xe/modules.symbols
lib/modules/6.12.0-rc7-xe/modules.dep.bin
+ mv kernel.tar.gz ..
+ cd ..
+ rm -rf archive
++ date +%s
+ echo -e '\e[0Ksection_end:1731653527:package_x86_64\r\e[0K'
^[[0Ksection_end:1731653527:package_x86_64
^[[0K
++ date +%s
+ echo -e '\e[0Ksection_start:1731653527:build_x86_64_nodebug[collapsed=true]\r\e[0KBuild x86-64 NoDebug'
^[[0Ksection_start:1731653527:build_x86_64_nodebug[collapsed=true]
^[[0KBuild x86-64 NoDebug
+ mkdir -p build64-nodebug
+ KCONFIG_CONFIG=build64-nodebug/.config
+ ./scripts/kconfig/merge_config.sh -m .ci/kernel/kconfig .ci/kernel/nodebug.fragment
Using .ci/kernel/kconfig as base
Merging .ci/kernel/nodebug.fragment
The merge file '.ci/kernel/nodebug.fragment' does not exist.  Exit.
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

Re: [PATCH 1/2] drm/i915/display: Refactor handling of dpkgc latency programming

[Jani Nikula]

On Fri, 15 Nov 2024, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> - We want to make sure we have all the required values specially
> linetime which is computed after intel_wm_compute, this will also
> help implement some WA's which require linetime.
> -We do not want to write into any registers during compute_config phase
> While we are at it do some more refactors in the function like:
> -Use intel_display wherever possible
> -Move away from using enable_dpkgc bool and call it fixed_refresh_rate
> -Optimize value prepration

Please write proper sentences instead of bullet points. And the general
advice is to do one thing per patch.

>
> --v2
> -No need to save anything in intel_display structure [Vinod]
> -Move computation and writing into register to intel_atomic_commit_tail
> [Vinod]
>
> --v3
> -Rename the subject [Vinod]
> -Rearrange the variable initialization and declaration [Vinod]
> -Reaarange condition evaluation for fixed_refresh_rate [Vinod]
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c |  2 +
>  drivers/gpu/drm/i915/display/intel_wm.c      | 56 ++++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_wm.h      |  1 +
>  drivers/gpu/drm/i915/display/skl_watermark.c | 52 ------------------
>  4 files changed, 59 insertions(+), 52 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index e790a2de5b3d..d1880e0a5d29 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7826,6 +7826,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
>  	dev_priv->display.funcs.display->commit_modeset_enables(state);
>  
> +	intel_program_dpkgc_latency(state);
> +
>  	if (state->modeset)
>  		intel_set_cdclk_post_plane_update(state);
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_wm.c b/drivers/gpu/drm/i915/display/intel_wm.c
> index d7dc49aecd27..4a2caf9cb03e 100644
> --- a/drivers/gpu/drm/i915/display/intel_wm.c
> +++ b/drivers/gpu/drm/i915/display/intel_wm.c
> @@ -7,9 +7,18 @@
>  
>  #include "i915_drv.h"
>  #include "i9xx_wm.h"
> +#include "intel_de.h"
>  #include "intel_display_types.h"
>  #include "intel_wm.h"
>  #include "skl_watermark.h"
> +#include "skl_watermark_regs.h"
> +
> +/*
> + * It is expected that DSB can do posted writes to every register in
> + * the pipe and planes within 100us. For flip queue use case, the
> + * recommended DSB execution time is 100us + one SAGV block time.
> + */
> +#define DSB_EXE_TIME 100
>  
>  /**
>   * intel_update_watermarks - update FIFO watermark values based on current modes
> @@ -131,6 +140,53 @@ bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
>  		return plane_state->uapi.visible;
>  }
>  
> +/*
> + * If Fixed Refresh Rate or For VRR case Vmin = Vmax = Flipline:
> + * Program DEEP PKG_C_LATENCY Pkg C with highest valid latency from
> + * watermark level1 and up and above. If watermark level 1 is
> + * invalid program it with all 1's.
> + * Program PKG_C_LATENCY Added Wake Time = DSB execution time
> + * If Variable Refresh Rate where Vmin != Vmax != Flipline:
> + * Program DEEP PKG_C_LATENCY Pkg C with all 1's.
> + * Program PKG_C_LATENCY Added Wake Time = 0
> + */
> +void
> +intel_program_dpkgc_latency(struct intel_atomic_state *state)

The function prefix should match the file name i.e. a function in
intel_foo.[ch] should be named intel_foo_bar().

But why is the function being relocated at all? That's also not
explained in the commit message.

> +{
> +	struct intel_display *display = to_intel_display(state);
> +	struct drm_i915_private *i915 = to_i915(display->drm);
> +	struct intel_crtc *crtc;
> +	struct intel_crtc_state *new_crtc_state;
> +	u32 max_latency = LNL_PKG_C_LATENCY_MASK, added_waketime = 0;
> +	bool fixed_refresh_rate = false;
> +	u32 clear, val;
> +	int i;
> +
> +	if (DISPLAY_VER(display) < 20)
> +		return;
> +
> +	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> +		if (!new_crtc_state->vrr.enable ||
> +		    (new_crtc_state->vrr.vmin == new_crtc_state->vrr.vmax &&
> +		     new_crtc_state->vrr.vmin == new_crtc_state->vrr.flipline))
> +			fixed_refresh_rate = true;
> +	}
> +
> +	if (fixed_refresh_rate) {
> +		max_latency = skl_watermark_max_latency(i915, 1);
> +		if (max_latency == 0)
> +			max_latency = LNL_PKG_C_LATENCY_MASK;
> +		added_waketime = DSB_EXE_TIME +
> +			display->sagv.block_time_us;
> +	}
> +
> +	clear = LNL_ADDED_WAKE_TIME_MASK | LNL_PKG_C_LATENCY_MASK;
> +	val = REG_FIELD_PREP(LNL_PKG_C_LATENCY_MASK, max_latency) |
> +		REG_FIELD_PREP(LNL_ADDED_WAKE_TIME_MASK, added_waketime);
> +
> +	intel_de_rmw(display, LNL_PKG_C_LATENCY, clear, val);
> +}
> +
>  void intel_print_wm_latency(struct drm_i915_private *dev_priv,
>  			    const char *name, const u16 wm[])
>  {
> diff --git a/drivers/gpu/drm/i915/display/intel_wm.h b/drivers/gpu/drm/i915/display/intel_wm.h
> index e97cdca89a5c..07e3d9359d73 100644
> --- a/drivers/gpu/drm/i915/display/intel_wm.h
> +++ b/drivers/gpu/drm/i915/display/intel_wm.h
> @@ -31,5 +31,6 @@ void intel_print_wm_latency(struct drm_i915_private *i915,
>  			    const char *name, const u16 wm[]);
>  void intel_wm_init(struct drm_i915_private *i915);
>  void intel_wm_debugfs_register(struct drm_i915_private *i915);
> +void intel_program_dpkgc_latency(struct intel_atomic_state *state);
>  
>  #endif /* __INTEL_WM_H__ */
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 1a4c1fa24820..d419edb196c6 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -28,12 +28,6 @@
>  #include "skl_watermark.h"
>  #include "skl_watermark_regs.h"
>  
> -/*It is expected that DSB can do posted writes to every register in
> - * the pipe and planes within 100us. For flip queue use case, the
> - * recommended DSB execution time is 100us + one SAGV block time.
> - */
> -#define DSB_EXE_TIME 100
> -
>  static void skl_sagv_disable(struct drm_i915_private *i915);
>  
>  /* Stores plane specific WM parameters */
> @@ -2844,51 +2838,12 @@ static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
>  	return 0;
>  }
>  
> -/*
> - * If Fixed Refresh Rate or For VRR case Vmin = Vmax = Flipline:
> - * Program DEEP PKG_C_LATENCY Pkg C with highest valid latency from
> - * watermark level1 and up and above. If watermark level 1 is
> - * invalid program it with all 1's.
> - * Program PKG_C_LATENCY Added Wake Time = DSB execution time
> - * If Variable Refresh Rate where Vmin != Vmax != Flipline:
> - * Program DEEP PKG_C_LATENCY Pkg C with all 1's.
> - * Program PKG_C_LATENCY Added Wake Time = 0
> - */
> -static void
> -skl_program_dpkgc_latency(struct drm_i915_private *i915, bool enable_dpkgc)
> -{
> -	u32 max_latency = 0;
> -	u32 clear = 0, val = 0;
> -	u32 added_wake_time = 0;
> -
> -	if (DISPLAY_VER(i915) < 20)
> -		return;
> -
> -	if (enable_dpkgc) {
> -		max_latency = skl_watermark_max_latency(i915, 1);
> -		if (max_latency == 0)
> -			max_latency = LNL_PKG_C_LATENCY_MASK;
> -		added_wake_time = DSB_EXE_TIME +
> -			i915->display.sagv.block_time_us;
> -	} else {
> -		max_latency = LNL_PKG_C_LATENCY_MASK;
> -		added_wake_time = 0;
> -	}
> -
> -	clear |= LNL_ADDED_WAKE_TIME_MASK | LNL_PKG_C_LATENCY_MASK;
> -	val |= REG_FIELD_PREP(LNL_PKG_C_LATENCY_MASK, max_latency);
> -	val |= REG_FIELD_PREP(LNL_ADDED_WAKE_TIME_MASK, added_wake_time);
> -
> -	intel_uncore_rmw(&i915->uncore, LNL_PKG_C_LATENCY, clear, val);
> -}
> -
>  static int
>  skl_compute_wm(struct intel_atomic_state *state)
>  {
>  	struct intel_crtc *crtc;
>  	struct intel_crtc_state __maybe_unused *new_crtc_state;
>  	int ret, i;
> -	bool enable_dpkgc = false;
>  
>  	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
>  		ret = skl_build_pipe_wm(state, crtc);
> @@ -2913,15 +2868,8 @@ skl_compute_wm(struct intel_atomic_state *state)
>  		ret = skl_wm_add_affected_planes(state, crtc);
>  		if (ret)
>  			return ret;
> -
> -		if ((new_crtc_state->vrr.vmin == new_crtc_state->vrr.vmax &&
> -		     new_crtc_state->vrr.vmin == new_crtc_state->vrr.flipline) ||
> -		    !new_crtc_state->vrr.enable)
> -			enable_dpkgc = true;
>  	}
>  
> -	skl_program_dpkgc_latency(to_i915(state->base.dev), enable_dpkgc);
> -
>  	skl_print_wm_changes(state);
>  
>  	return 0;

-- 
Jani Nikula, Intel

RE: [PATCH 1/2] drm/i915/display: Refactor handling of dpkgc latency programming

[Kandpal, Suraj]

> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Friday, November 15, 2024 3:50 PM
> To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-xe@lists.freedesktop.org;
> intel-gfx@lists.freedesktop.org
> Cc: Govindapillai, Vinod <vinod.govindapillai@intel.com>; Syrjala, Ville
> <ville.syrjala@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>
> Subject: Re: [PATCH 1/2] drm/i915/display: Refactor handling of dpkgc latency
> programming
> 
> On Fri, 15 Nov 2024, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> > - We want to make sure we have all the required values specially
> > linetime which is computed after intel_wm_compute, this will also help
> > implement some WA's which require linetime.
> > -We do not want to write into any registers during compute_config
> > phase While we are at it do some more refactors in the function like:
> > -Use intel_display wherever possible
> > -Move away from using enable_dpkgc bool and call it fixed_refresh_rate
> > -Optimize value prepration
> 
> Please write proper sentences instead of bullet points. And the general advice
> is to do one thing per patch.

Sure will fix that.
It was previously divided into 6 patches but squashed it after Vinod suggested to do you want me to go back to that convention
https://patchwork.freedesktop.org/series/141200/

> 
> >
> > --v2
> > -No need to save anything in intel_display structure [Vinod] -Move
> > computation and writing into register to intel_atomic_commit_tail
> > [Vinod]
> >
> > --v3
> > -Rename the subject [Vinod]
> > -Rearrange the variable initialization and declaration [Vinod]
> > -Reaarange condition evaluation for fixed_refresh_rate [Vinod]
> >
> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c |  2 +
> >  drivers/gpu/drm/i915/display/intel_wm.c      | 56 ++++++++++++++++++++
> >  drivers/gpu/drm/i915/display/intel_wm.h      |  1 +
> >  drivers/gpu/drm/i915/display/skl_watermark.c | 52 ------------------
> >  4 files changed, 59 insertions(+), 52 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index e790a2de5b3d..d1880e0a5d29 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -7826,6 +7826,8 @@ static void intel_atomic_commit_tail(struct
> intel_atomic_state *state)
> >  	/* Now enable the clocks, plane, pipe, and connectors that we set up.
> */
> >  	dev_priv->display.funcs.display->commit_modeset_enables(state);
> >
> > +	intel_program_dpkgc_latency(state);
> > +
> >  	if (state->modeset)
> >  		intel_set_cdclk_post_plane_update(state);
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_wm.c
> > b/drivers/gpu/drm/i915/display/intel_wm.c
> > index d7dc49aecd27..4a2caf9cb03e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_wm.c
> > +++ b/drivers/gpu/drm/i915/display/intel_wm.c
> > @@ -7,9 +7,18 @@
> >
> >  #include "i915_drv.h"
> >  #include "i9xx_wm.h"
> > +#include "intel_de.h"
> >  #include "intel_display_types.h"
> >  #include "intel_wm.h"
> >  #include "skl_watermark.h"
> > +#include "skl_watermark_regs.h"
> > +
> > +/*
> > + * It is expected that DSB can do posted writes to every register in
> > + * the pipe and planes within 100us. For flip queue use case, the
> > + * recommended DSB execution time is 100us + one SAGV block time.
> > + */
> > +#define DSB_EXE_TIME 100
> >
> >  /**
> >   * intel_update_watermarks - update FIFO watermark values based on
> > current modes @@ -131,6 +140,53 @@ bool intel_wm_plane_visible(const
> struct intel_crtc_state *crtc_state,
> >  		return plane_state->uapi.visible;
> >  }
> >
> > +/*
> > + * If Fixed Refresh Rate or For VRR case Vmin = Vmax = Flipline:
> > + * Program DEEP PKG_C_LATENCY Pkg C with highest valid latency from
> > + * watermark level1 and up and above. If watermark level 1 is
> > + * invalid program it with all 1's.
> > + * Program PKG_C_LATENCY Added Wake Time = DSB execution time
> > + * If Variable Refresh Rate where Vmin != Vmax != Flipline:
> > + * Program DEEP PKG_C_LATENCY Pkg C with all 1's.
> > + * Program PKG_C_LATENCY Added Wake Time = 0  */ void
> > +intel_program_dpkgc_latency(struct intel_atomic_state *state)
> 
> The function prefix should match the file name i.e. a function in intel_foo.[ch]
> should be named intel_foo_bar().
> 

Well it was previously intel_wm_program_dpkgc_latency but Vinod had asked to rename the function


> But why is the function being relocated at all? That's also not explained in the
> commit message.

The reason is in the commit message
"- We want to make sure we have all the required values specially
linetime which is computed after intel_wm_compute, this will also help
implement some WA's which require linetime."

Will reword the commit message into sentences to make it more clearer.

Regards,
Suraj Kandpal

> 
> > +{
> > +	struct intel_display *display = to_intel_display(state);
> > +	struct drm_i915_private *i915 = to_i915(display->drm);
> > +	struct intel_crtc *crtc;
> > +	struct intel_crtc_state *new_crtc_state;
> > +	u32 max_latency = LNL_PKG_C_LATENCY_MASK, added_waketime = 0;
> > +	bool fixed_refresh_rate = false;
> > +	u32 clear, val;
> > +	int i;
> > +
> > +	if (DISPLAY_VER(display) < 20)
> > +		return;
> > +
> > +	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> > +		if (!new_crtc_state->vrr.enable ||
> > +		    (new_crtc_state->vrr.vmin == new_crtc_state->vrr.vmax &&
> > +		     new_crtc_state->vrr.vmin == new_crtc_state->vrr.flipline))
> > +			fixed_refresh_rate = true;
> > +	}
> > +
> > +	if (fixed_refresh_rate) {
> > +		max_latency = skl_watermark_max_latency(i915, 1);
> > +		if (max_latency == 0)
> > +			max_latency = LNL_PKG_C_LATENCY_MASK;
> > +		added_waketime = DSB_EXE_TIME +
> > +			display->sagv.block_time_us;
> > +	}
> > +
> > +	clear = LNL_ADDED_WAKE_TIME_MASK |
> LNL_PKG_C_LATENCY_MASK;
> > +	val = REG_FIELD_PREP(LNL_PKG_C_LATENCY_MASK, max_latency) |
> > +		REG_FIELD_PREP(LNL_ADDED_WAKE_TIME_MASK,
> added_waketime);
> > +
> > +	intel_de_rmw(display, LNL_PKG_C_LATENCY, clear, val); }
> > +
> >  void intel_print_wm_latency(struct drm_i915_private *dev_priv,
> >  			    const char *name, const u16 wm[])  { diff --git
> > a/drivers/gpu/drm/i915/display/intel_wm.h
> > b/drivers/gpu/drm/i915/display/intel_wm.h
> > index e97cdca89a5c..07e3d9359d73 100644
> > --- a/drivers/gpu/drm/i915/display/intel_wm.h
> > +++ b/drivers/gpu/drm/i915/display/intel_wm.h
> > @@ -31,5 +31,6 @@ void intel_print_wm_latency(struct drm_i915_private
> *i915,
> >  			    const char *name, const u16 wm[]);  void
> intel_wm_init(struct
> > drm_i915_private *i915);  void intel_wm_debugfs_register(struct
> > drm_i915_private *i915);
> > +void intel_program_dpkgc_latency(struct intel_atomic_state *state);
> >
> >  #endif /* __INTEL_WM_H__ */
> > diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
> > b/drivers/gpu/drm/i915/display/skl_watermark.c
> > index 1a4c1fa24820..d419edb196c6 100644
> > --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> > +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> > @@ -28,12 +28,6 @@
> >  #include "skl_watermark.h"
> >  #include "skl_watermark_regs.h"
> >
> > -/*It is expected that DSB can do posted writes to every register in
> > - * the pipe and planes within 100us. For flip queue use case, the
> > - * recommended DSB execution time is 100us + one SAGV block time.
> > - */
> > -#define DSB_EXE_TIME 100
> > -
> >  static void skl_sagv_disable(struct drm_i915_private *i915);
> >
> >  /* Stores plane specific WM parameters */ @@ -2844,51 +2838,12 @@
> > static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
> >  	return 0;
> >  }
> >
> > -/*
> > - * If Fixed Refresh Rate or For VRR case Vmin = Vmax = Flipline:
> > - * Program DEEP PKG_C_LATENCY Pkg C with highest valid latency from
> > - * watermark level1 and up and above. If watermark level 1 is
> > - * invalid program it with all 1's.
> > - * Program PKG_C_LATENCY Added Wake Time = DSB execution time
> > - * If Variable Refresh Rate where Vmin != Vmax != Flipline:
> > - * Program DEEP PKG_C_LATENCY Pkg C with all 1's.
> > - * Program PKG_C_LATENCY Added Wake Time = 0
> > - */
> > -static void
> > -skl_program_dpkgc_latency(struct drm_i915_private *i915, bool
> > enable_dpkgc) -{
> > -	u32 max_latency = 0;
> > -	u32 clear = 0, val = 0;
> > -	u32 added_wake_time = 0;
> > -
> > -	if (DISPLAY_VER(i915) < 20)
> > -		return;
> > -
> > -	if (enable_dpkgc) {
> > -		max_latency = skl_watermark_max_latency(i915, 1);
> > -		if (max_latency == 0)
> > -			max_latency = LNL_PKG_C_LATENCY_MASK;
> > -		added_wake_time = DSB_EXE_TIME +
> > -			i915->display.sagv.block_time_us;
> > -	} else {
> > -		max_latency = LNL_PKG_C_LATENCY_MASK;
> > -		added_wake_time = 0;
> > -	}
> > -
> > -	clear |= LNL_ADDED_WAKE_TIME_MASK |
> LNL_PKG_C_LATENCY_MASK;
> > -	val |= REG_FIELD_PREP(LNL_PKG_C_LATENCY_MASK, max_latency);
> > -	val |= REG_FIELD_PREP(LNL_ADDED_WAKE_TIME_MASK,
> added_wake_time);
> > -
> > -	intel_uncore_rmw(&i915->uncore, LNL_PKG_C_LATENCY, clear, val);
> > -}
> > -
> >  static int
> >  skl_compute_wm(struct intel_atomic_state *state)  {
> >  	struct intel_crtc *crtc;
> >  	struct intel_crtc_state __maybe_unused *new_crtc_state;
> >  	int ret, i;
> > -	bool enable_dpkgc = false;
> >
> >  	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> >  		ret = skl_build_pipe_wm(state, crtc); @@ -2913,15 +2868,8
> @@
> > skl_compute_wm(struct intel_atomic_state *state)
> >  		ret = skl_wm_add_affected_planes(state, crtc);
> >  		if (ret)
> >  			return ret;
> > -
> > -		if ((new_crtc_state->vrr.vmin == new_crtc_state->vrr.vmax &&
> > -		     new_crtc_state->vrr.vmin == new_crtc_state->vrr.flipline)
> ||
> > -		    !new_crtc_state->vrr.enable)
> > -			enable_dpkgc = true;
> >  	}
> >
> > -	skl_program_dpkgc_latency(to_i915(state->base.dev), enable_dpkgc);
> > -
> >  	skl_print_wm_changes(state);
> >
> >  	return 0;
> 
> --
> Jani Nikula, Intel

RE: [PATCH 1/2] drm/i915/display: Refactor handling of dpkgc latency programming

[Jani Nikula]

On Fri, 15 Nov 2024, "Kandpal, Suraj" <suraj.kandpal@intel.com> wrote:
>> -----Original Message-----
>> From: Jani Nikula <jani.nikula@linux.intel.com>
>> Sent: Friday, November 15, 2024 3:50 PM
>> To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-xe@lists.freedesktop.org;
>> intel-gfx@lists.freedesktop.org
>> Cc: Govindapillai, Vinod <vinod.govindapillai@intel.com>; Syrjala, Ville
>> <ville.syrjala@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>
>> Subject: Re: [PATCH 1/2] drm/i915/display: Refactor handling of dpkgc latency
>> programming
>> 
>> On Fri, 15 Nov 2024, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
>> > - We want to make sure we have all the required values specially
>> > linetime which is computed after intel_wm_compute, this will also help
>> > implement some WA's which require linetime.
>> > -We do not want to write into any registers during compute_config
>> > phase While we are at it do some more refactors in the function like:
>> > -Use intel_display wherever possible
>> > -Move away from using enable_dpkgc bool and call it fixed_refresh_rate
>> > -Optimize value prepration
>> 
>> Please write proper sentences instead of bullet points. And the general advice
>> is to do one thing per patch.
>
> Sure will fix that.
> It was previously divided into 6 patches but squashed it after Vinod suggested to do you want me to go back to that convention
> https://patchwork.freedesktop.org/series/141200/

So the general rule of thumb is one change per patch. Especially, try to
separate non-functional changes from functional changes. It makes review
for both easier.

And you really want to help the reviewers. Make their life easy, and
it'll benefit you. And you should review a lot of patches, to get a hang
of what kind of changes are easy and fun to review, and what are hard
and painful.

Another guideline for size of changes: If you get a bisected regression
report on the commit 1-2 years down the line, when your memory of it has
faded, what are your chances of pinpointing the issue right away? If the
bisect lands on a commit that's supposed to be non-functional, it's
immediately fishy, right?

Yet another guideline: If you need to revert the commit due to the
regression, how much good stuff do you have to throw away in the revert
because something was not right? Or, what are your chances of reverting
at all?

There are no hard rules here, but if the commit message is accurate, and
contains things like, well, bullet lists, or sentences with "also", it's
an indicator maybe the patch should be split up. (I've certainly
rewritten patches just because the commit message was difficult to
write.)

>
>> 
>> >
>> > --v2
>> > -No need to save anything in intel_display structure [Vinod] -Move
>> > computation and writing into register to intel_atomic_commit_tail
>> > [Vinod]
>> >
>> > --v3
>> > -Rename the subject [Vinod]
>> > -Rearrange the variable initialization and declaration [Vinod]
>> > -Reaarange condition evaluation for fixed_refresh_rate [Vinod]
>> >
>> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/display/intel_display.c |  2 +
>> >  drivers/gpu/drm/i915/display/intel_wm.c      | 56 ++++++++++++++++++++
>> >  drivers/gpu/drm/i915/display/intel_wm.h      |  1 +
>> >  drivers/gpu/drm/i915/display/skl_watermark.c | 52 ------------------
>> >  4 files changed, 59 insertions(+), 52 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>> > b/drivers/gpu/drm/i915/display/intel_display.c
>> > index e790a2de5b3d..d1880e0a5d29 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_display.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> > @@ -7826,6 +7826,8 @@ static void intel_atomic_commit_tail(struct
>> intel_atomic_state *state)
>> >  	/* Now enable the clocks, plane, pipe, and connectors that we set up.
>> */
>> >  	dev_priv->display.funcs.display->commit_modeset_enables(state);
>> >
>> > +	intel_program_dpkgc_latency(state);
>> > +

I'll get back to naming, but this is oddly specific in the context of
intel_atomic_commit_tail(), which is fairly high level.

>> >  	if (state->modeset)
>> >  		intel_set_cdclk_post_plane_update(state);
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_wm.c
>> > b/drivers/gpu/drm/i915/display/intel_wm.c
>> > index d7dc49aecd27..4a2caf9cb03e 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_wm.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_wm.c
>> > @@ -7,9 +7,18 @@
>> >
>> >  #include "i915_drv.h"
>> >  #include "i9xx_wm.h"
>> > +#include "intel_de.h"
>> >  #include "intel_display_types.h"
>> >  #include "intel_wm.h"
>> >  #include "skl_watermark.h"
>> > +#include "skl_watermark_regs.h"
>> > +
>> > +/*
>> > + * It is expected that DSB can do posted writes to every register in
>> > + * the pipe and planes within 100us. For flip queue use case, the
>> > + * recommended DSB execution time is 100us + one SAGV block time.
>> > + */
>> > +#define DSB_EXE_TIME 100
>> >
>> >  /**
>> >   * intel_update_watermarks - update FIFO watermark values based on
>> > current modes @@ -131,6 +140,53 @@ bool intel_wm_plane_visible(const
>> struct intel_crtc_state *crtc_state,
>> >  		return plane_state->uapi.visible;
>> >  }
>> >
>> > +/*
>> > + * If Fixed Refresh Rate or For VRR case Vmin = Vmax = Flipline:
>> > + * Program DEEP PKG_C_LATENCY Pkg C with highest valid latency from
>> > + * watermark level1 and up and above. If watermark level 1 is
>> > + * invalid program it with all 1's.
>> > + * Program PKG_C_LATENCY Added Wake Time = DSB execution time
>> > + * If Variable Refresh Rate where Vmin != Vmax != Flipline:
>> > + * Program DEEP PKG_C_LATENCY Pkg C with all 1's.
>> > + * Program PKG_C_LATENCY Added Wake Time = 0  */ void
>> > +intel_program_dpkgc_latency(struct intel_atomic_state *state)
>> 
>> The function prefix should match the file name i.e. a function in intel_foo.[ch]
>> should be named intel_foo_bar().
>> 
>
> Well it was previously intel_wm_program_dpkgc_latency but Vinod had asked to rename the function

Again, the above rule is not a 100% hard rule, but the point kind of is,
if you had to guess which file the function is in, what would you say?
What is it related to? Yeah, cscope or gnu global or git grep will find
it, but it doesn't help you with the mental model.

C has no namespacing, so here we go with following the file name in the
function naming.

And if the argument is, it's not really related to wm, so maybe it
shouldn't be named wm something - that should be a hint maybe the
*location* is wrong, not the name.

>> But why is the function being relocated at all? That's also not explained in the
>> commit message.
>
> The reason is in the commit message
> "- We want to make sure we have all the required values specially
> linetime which is computed after intel_wm_compute, this will also help
> implement some WA's which require linetime."
>
> Will reword the commit message into sentences to make it more clearer.

That says absolutely nothing about why it's being moved from
skl_watermark.c to intel_wm.c. I have no clue. It's just moved around.

BR,
Jani.


>
> Regards,
> Suraj Kandpal
>
>> 
>> > +{
>> > +	struct intel_display *display = to_intel_display(state);
>> > +	struct drm_i915_private *i915 = to_i915(display->drm);
>> > +	struct intel_crtc *crtc;
>> > +	struct intel_crtc_state *new_crtc_state;
>> > +	u32 max_latency = LNL_PKG_C_LATENCY_MASK, added_waketime = 0;
>> > +	bool fixed_refresh_rate = false;
>> > +	u32 clear, val;
>> > +	int i;
>> > +
>> > +	if (DISPLAY_VER(display) < 20)
>> > +		return;
>> > +
>> > +	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
>> > +		if (!new_crtc_state->vrr.enable ||
>> > +		    (new_crtc_state->vrr.vmin == new_crtc_state->vrr.vmax &&
>> > +		     new_crtc_state->vrr.vmin == new_crtc_state->vrr.flipline))
>> > +			fixed_refresh_rate = true;
>> > +	}
>> > +
>> > +	if (fixed_refresh_rate) {
>> > +		max_latency = skl_watermark_max_latency(i915, 1);
>> > +		if (max_latency == 0)
>> > +			max_latency = LNL_PKG_C_LATENCY_MASK;
>> > +		added_waketime = DSB_EXE_TIME +
>> > +			display->sagv.block_time_us;
>> > +	}
>> > +
>> > +	clear = LNL_ADDED_WAKE_TIME_MASK |
>> LNL_PKG_C_LATENCY_MASK;
>> > +	val = REG_FIELD_PREP(LNL_PKG_C_LATENCY_MASK, max_latency) |
>> > +		REG_FIELD_PREP(LNL_ADDED_WAKE_TIME_MASK,
>> added_waketime);
>> > +
>> > +	intel_de_rmw(display, LNL_PKG_C_LATENCY, clear, val); }
>> > +
>> >  void intel_print_wm_latency(struct drm_i915_private *dev_priv,
>> >  			    const char *name, const u16 wm[])  { diff --git
>> > a/drivers/gpu/drm/i915/display/intel_wm.h
>> > b/drivers/gpu/drm/i915/display/intel_wm.h
>> > index e97cdca89a5c..07e3d9359d73 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_wm.h
>> > +++ b/drivers/gpu/drm/i915/display/intel_wm.h
>> > @@ -31,5 +31,6 @@ void intel_print_wm_latency(struct drm_i915_private
>> *i915,
>> >  			    const char *name, const u16 wm[]);  void
>> intel_wm_init(struct
>> > drm_i915_private *i915);  void intel_wm_debugfs_register(struct
>> > drm_i915_private *i915);
>> > +void intel_program_dpkgc_latency(struct intel_atomic_state *state);
>> >
>> >  #endif /* __INTEL_WM_H__ */
>> > diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
>> > b/drivers/gpu/drm/i915/display/skl_watermark.c
>> > index 1a4c1fa24820..d419edb196c6 100644
>> > --- a/drivers/gpu/drm/i915/display/skl_watermark.c
>> > +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
>> > @@ -28,12 +28,6 @@
>> >  #include "skl_watermark.h"
>> >  #include "skl_watermark_regs.h"
>> >
>> > -/*It is expected that DSB can do posted writes to every register in
>> > - * the pipe and planes within 100us. For flip queue use case, the
>> > - * recommended DSB execution time is 100us + one SAGV block time.
>> > - */
>> > -#define DSB_EXE_TIME 100
>> > -
>> >  static void skl_sagv_disable(struct drm_i915_private *i915);
>> >
>> >  /* Stores plane specific WM parameters */ @@ -2844,51 +2838,12 @@
>> > static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
>> >  	return 0;
>> >  }
>> >
>> > -/*
>> > - * If Fixed Refresh Rate or For VRR case Vmin = Vmax = Flipline:
>> > - * Program DEEP PKG_C_LATENCY Pkg C with highest valid latency from
>> > - * watermark level1 and up and above. If watermark level 1 is
>> > - * invalid program it with all 1's.
>> > - * Program PKG_C_LATENCY Added Wake Time = DSB execution time
>> > - * If Variable Refresh Rate where Vmin != Vmax != Flipline:
>> > - * Program DEEP PKG_C_LATENCY Pkg C with all 1's.
>> > - * Program PKG_C_LATENCY Added Wake Time = 0
>> > - */
>> > -static void
>> > -skl_program_dpkgc_latency(struct drm_i915_private *i915, bool
>> > enable_dpkgc) -{
>> > -	u32 max_latency = 0;
>> > -	u32 clear = 0, val = 0;
>> > -	u32 added_wake_time = 0;
>> > -
>> > -	if (DISPLAY_VER(i915) < 20)
>> > -		return;
>> > -
>> > -	if (enable_dpkgc) {
>> > -		max_latency = skl_watermark_max_latency(i915, 1);
>> > -		if (max_latency == 0)
>> > -			max_latency = LNL_PKG_C_LATENCY_MASK;
>> > -		added_wake_time = DSB_EXE_TIME +
>> > -			i915->display.sagv.block_time_us;
>> > -	} else {
>> > -		max_latency = LNL_PKG_C_LATENCY_MASK;
>> > -		added_wake_time = 0;
>> > -	}
>> > -
>> > -	clear |= LNL_ADDED_WAKE_TIME_MASK |
>> LNL_PKG_C_LATENCY_MASK;
>> > -	val |= REG_FIELD_PREP(LNL_PKG_C_LATENCY_MASK, max_latency);
>> > -	val |= REG_FIELD_PREP(LNL_ADDED_WAKE_TIME_MASK,
>> added_wake_time);
>> > -
>> > -	intel_uncore_rmw(&i915->uncore, LNL_PKG_C_LATENCY, clear, val);
>> > -}
>> > -
>> >  static int
>> >  skl_compute_wm(struct intel_atomic_state *state)  {
>> >  	struct intel_crtc *crtc;
>> >  	struct intel_crtc_state __maybe_unused *new_crtc_state;
>> >  	int ret, i;
>> > -	bool enable_dpkgc = false;
>> >
>> >  	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
>> >  		ret = skl_build_pipe_wm(state, crtc); @@ -2913,15 +2868,8
>> @@
>> > skl_compute_wm(struct intel_atomic_state *state)
>> >  		ret = skl_wm_add_affected_planes(state, crtc);
>> >  		if (ret)
>> >  			return ret;
>> > -
>> > -		if ((new_crtc_state->vrr.vmin == new_crtc_state->vrr.vmax &&
>> > -		     new_crtc_state->vrr.vmin == new_crtc_state->vrr.flipline)
>> ||
>> > -		    !new_crtc_state->vrr.enable)
>> > -			enable_dpkgc = true;
>> >  	}
>> >
>> > -	skl_program_dpkgc_latency(to_i915(state->base.dev), enable_dpkgc);
>> > -
>> >  	skl_print_wm_changes(state);
>> >
>> >  	return 0;
>> 
>> --
>> Jani Nikula, Intel

-- 
Jani Nikula, Intel

Re: [PATCH 1/2] drm/i915/display: Refactor handling of dpkgc latency programming

[Govindapillai, Vinod]

On Fri, 2024-11-15 at 10:28 +0000, Kandpal, Suraj wrote:
> 
> 
> > -----Original Message-----
> > From: Jani Nikula <jani.nikula@linux.intel.com>
> > Sent: Friday, November 15, 2024 3:50 PM
> > To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-xe@lists.freedesktop.org;
> > intel-gfx@lists.freedesktop.org
> > Cc: Govindapillai, Vinod <vinod.govindapillai@intel.com>; Syrjala, Ville
> > <ville.syrjala@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>
> > Subject: Re: [PATCH 1/2] drm/i915/display: Refactor handling of dpkgc latency
> > programming
> > 
> > On Fri, 15 Nov 2024, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> > > - We want to make sure we have all the required values specially
> > > linetime which is computed after intel_wm_compute, this will also help
> > > implement some WA's which require linetime.
> > > -We do not want to write into any registers during compute_config
> > > phase While we are at it do some more refactors in the function like:
> > > -Use intel_display wherever possible
> > > -Move away from using enable_dpkgc bool and call it fixed_refresh_rate
> > > -Optimize value prepration
> > 
> > Please write proper sentences instead of bullet points. And the general advice
> > is to do one thing per patch.
> 
> Sure will fix that.
> It was previously divided into 6 patches but squashed it after Vinod suggested to do you want me
> to go back to that convention
> https://patchwork.freedesktop.org/series/141200/

Most of the old function handling was changed - from where and when it is called etc. Thats why I
suggested to have one patch as refactoring the whole handling.

> 
> > 
> > > 
> > > --v2
> > > -No need to save anything in intel_display structure [Vinod] -Move
> > > computation and writing into register to intel_atomic_commit_tail
> > > [Vinod]
> > > 
> > > --v3
> > > -Rename the subject [Vinod]
> > > -Rearrange the variable initialization and declaration [Vinod]
> > > -Reaarange condition evaluation for fixed_refresh_rate [Vinod]
> > > 
> > > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_display.c |  2 +
> > >  drivers/gpu/drm/i915/display/intel_wm.c      | 56 ++++++++++++++++++++
> > >  drivers/gpu/drm/i915/display/intel_wm.h      |  1 +
> > >  drivers/gpu/drm/i915/display/skl_watermark.c | 52 ------------------
> > >  4 files changed, 59 insertions(+), 52 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > index e790a2de5b3d..d1880e0a5d29 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -7826,6 +7826,8 @@ static void intel_atomic_commit_tail(struct
> > intel_atomic_state *state)
> > >         /* Now enable the clocks, plane, pipe, and connectors that we set up.
> > */
> > >         dev_priv->display.funcs.display->commit_modeset_enables(state);
> > > 
> > > +       intel_program_dpkgc_latency(state);
> > > +
> > >         if (state->modeset)
> > >                 intel_set_cdclk_post_plane_update(state);
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_wm.c
> > > b/drivers/gpu/drm/i915/display/intel_wm.c
> > > index d7dc49aecd27..4a2caf9cb03e 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_wm.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_wm.c
> > > @@ -7,9 +7,18 @@
> > > 
> > >  #include "i915_drv.h"
> > >  #include "i9xx_wm.h"
> > > +#include "intel_de.h"
> > >  #include "intel_display_types.h"
> > >  #include "intel_wm.h"
> > >  #include "skl_watermark.h"
> > > +#include "skl_watermark_regs.h"
> > > +
> > > +/*
> > > + * It is expected that DSB can do posted writes to every register in
> > > + * the pipe and planes within 100us. For flip queue use case, the
> > > + * recommended DSB execution time is 100us + one SAGV block time.
> > > + */
> > > +#define DSB_EXE_TIME 100
> > > 
> > >  /**
> > >   * intel_update_watermarks - update FIFO watermark values based on
> > > current modes @@ -131,6 +140,53 @@ bool intel_wm_plane_visible(const
> > struct intel_crtc_state *crtc_state,
> > >                 return plane_state->uapi.visible;
> > >  }
> > > 
> > > +/*
> > > + * If Fixed Refresh Rate or For VRR case Vmin = Vmax = Flipline:
> > > + * Program DEEP PKG_C_LATENCY Pkg C with highest valid latency from
> > > + * watermark level1 and up and above. If watermark level 1 is
> > > + * invalid program it with all 1's.
> > > + * Program PKG_C_LATENCY Added Wake Time = DSB execution time
> > > + * If Variable Refresh Rate where Vmin != Vmax != Flipline:
> > > + * Program DEEP PKG_C_LATENCY Pkg C with all 1's.
> > > + * Program PKG_C_LATENCY Added Wake Time = 0  */ void
> > > +intel_program_dpkgc_latency(struct intel_atomic_state *state)
> > 
> > The function prefix should match the file name i.e. a function in intel_foo.[ch]
> > should be named intel_foo_bar().
> > 
> 
> Well it was previously intel_wm_program_dpkgc_latency but Vinod had asked to rename the function

Ah.. sorry! I didnt notice that you moved this to intel_wm.c. I guess it has mainly for old
generation wm handling. I am not sure if "skl_watermarks.c" the right place. But atleast it is
better than intel_wm.c. 

> 
> 
> > But why is the function being relocated at all? That's also not explained in the
> > commit message.
> 
> The reason is in the commit message
> "- We want to make sure we have all the required values specially
> linetime which is computed after intel_wm_compute, this will also help
> implement some WA's which require linetime."
> 
> Will reword the commit message into sentences to make it more clearer.
> 
> Regards,
> Suraj Kandpal
> 
> > 
> > > +{
> > > +       struct intel_display *display = to_intel_display(state);
> > > +       struct drm_i915_private *i915 = to_i915(display->drm);
> > > +       struct intel_crtc *crtc;
> > > +       struct intel_crtc_state *new_crtc_state;
> > > +       u32 max_latency = LNL_PKG_C_LATENCY_MASK, added_waketime = 0;
> > > +       bool fixed_refresh_rate = false;
> > > +       u32 clear, val;
> > > +       int i;
> > > +
> > > +       if (DISPLAY_VER(display) < 20)
> > > +               return;
> > > +
> > > +       for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> > > +               if (!new_crtc_state->vrr.enable ||
> > > +                   (new_crtc_state->vrr.vmin == new_crtc_state->vrr.vmax &&
> > > +                    new_crtc_state->vrr.vmin == new_crtc_state->vrr.flipline))
> > > +                       fixed_refresh_rate = true;
> > > +       }
> > > +
> > > +       if (fixed_refresh_rate) {
> > > +               max_latency = skl_watermark_max_latency(i915, 1);
> > > +               if (max_latency == 0)
> > > +                       max_latency = LNL_PKG_C_LATENCY_MASK;
> > > +               added_waketime = DSB_EXE_TIME +
> > > +                       display->sagv.block_time_us;
> > > +       }
> > > +
> > > +       clear = LNL_ADDED_WAKE_TIME_MASK |
> > LNL_PKG_C_LATENCY_MASK;
> > > +       val = REG_FIELD_PREP(LNL_PKG_C_LATENCY_MASK, max_latency) |
> > > +               REG_FIELD_PREP(LNL_ADDED_WAKE_TIME_MASK,
> > added_waketime);
> > > +
> > > +       intel_de_rmw(display, LNL_PKG_C_LATENCY, clear, val); }
> > > +
> > >  void intel_print_wm_latency(struct drm_i915_private *dev_priv,
> > >                             const char *name, const u16 wm[])  { diff --git
> > > a/drivers/gpu/drm/i915/display/intel_wm.h
> > > b/drivers/gpu/drm/i915/display/intel_wm.h
> > > index e97cdca89a5c..07e3d9359d73 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_wm.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_wm.h
> > > @@ -31,5 +31,6 @@ void intel_print_wm_latency(struct drm_i915_private
> > *i915,
> > >                             const char *name, const u16 wm[]);  void
> > intel_wm_init(struct
> > > drm_i915_private *i915);  void intel_wm_debugfs_register(struct
> > > drm_i915_private *i915);
> > > +void intel_program_dpkgc_latency(struct intel_atomic_state *state);
> > > 
> > >  #endif /* __INTEL_WM_H__ */
> > > diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
> > > b/drivers/gpu/drm/i915/display/skl_watermark.c
> > > index 1a4c1fa24820..d419edb196c6 100644
> > > --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> > > +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> > > @@ -28,12 +28,6 @@
> > >  #include "skl_watermark.h"
> > >  #include "skl_watermark_regs.h"
> > > 
> > > -/*It is expected that DSB can do posted writes to every register in
> > > - * the pipe and planes within 100us. For flip queue use case, the
> > > - * recommended DSB execution time is 100us + one SAGV block time.
> > > - */
> > > -#define DSB_EXE_TIME 100
> > > -
> > >  static void skl_sagv_disable(struct drm_i915_private *i915);
> > > 
> > >  /* Stores plane specific WM parameters */ @@ -2844,51 +2838,12 @@
> > > static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
> > >         return 0;
> > >  }
> > > 
> > > -/*
> > > - * If Fixed Refresh Rate or For VRR case Vmin = Vmax = Flipline:
> > > - * Program DEEP PKG_C_LATENCY Pkg C with highest valid latency from
> > > - * watermark level1 and up and above. If watermark level 1 is
> > > - * invalid program it with all 1's.
> > > - * Program PKG_C_LATENCY Added Wake Time = DSB execution time
> > > - * If Variable Refresh Rate where Vmin != Vmax != Flipline:
> > > - * Program DEEP PKG_C_LATENCY Pkg C with all 1's.
> > > - * Program PKG_C_LATENCY Added Wake Time = 0
> > > - */
> > > -static void
> > > -skl_program_dpkgc_latency(struct drm_i915_private *i915, bool
> > > enable_dpkgc) -{
> > > -       u32 max_latency = 0;
> > > -       u32 clear = 0, val = 0;
> > > -       u32 added_wake_time = 0;
> > > -
> > > -       if (DISPLAY_VER(i915) < 20)
> > > -               return;
> > > -
> > > -       if (enable_dpkgc) {
> > > -               max_latency = skl_watermark_max_latency(i915, 1);
> > > -               if (max_latency == 0)
> > > -                       max_latency = LNL_PKG_C_LATENCY_MASK;
> > > -               added_wake_time = DSB_EXE_TIME +
> > > -                       i915->display.sagv.block_time_us;
> > > -       } else {
> > > -               max_latency = LNL_PKG_C_LATENCY_MASK;
> > > -               added_wake_time = 0;
> > > -       }
> > > -
> > > -       clear |= LNL_ADDED_WAKE_TIME_MASK |
> > LNL_PKG_C_LATENCY_MASK;
> > > -       val |= REG_FIELD_PREP(LNL_PKG_C_LATENCY_MASK, max_latency);
> > > -       val |= REG_FIELD_PREP(LNL_ADDED_WAKE_TIME_MASK,
> > added_wake_time);
> > > -
> > > -       intel_uncore_rmw(&i915->uncore, LNL_PKG_C_LATENCY, clear, val);
> > > -}
> > > -
> > >  static int
> > >  skl_compute_wm(struct intel_atomic_state *state)  {
> > >         struct intel_crtc *crtc;
> > >         struct intel_crtc_state __maybe_unused *new_crtc_state;
> > >         int ret, i;
> > > -       bool enable_dpkgc = false;
> > > 
> > >         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> > >                 ret = skl_build_pipe_wm(state, crtc); @@ -2913,15 +2868,8
> > @@
> > > skl_compute_wm(struct intel_atomic_state *state)
> > >                 ret = skl_wm_add_affected_planes(state, crtc);
> > >                 if (ret)
> > >                         return ret;
> > > -
> > > -               if ((new_crtc_state->vrr.vmin == new_crtc_state->vrr.vmax &&
> > > -                    new_crtc_state->vrr.vmin == new_crtc_state->vrr.flipline)
> > > > 
> > > -                   !new_crtc_state->vrr.enable)
> > > -                       enable_dpkgc = true;
> > >         }
> > > 
> > > -       skl_program_dpkgc_latency(to_i915(state->base.dev), enable_dpkgc);
> > > -
> > >         skl_print_wm_changes(state);
> > > 
> > >         return 0;
> > 
> > --
> > Jani Nikula, Intel