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From: "Dixit, Ashutosh" <ashutosh.dixit@intel.com>
To: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: intel-xe@lists.freedesktop.org,
	Matt Roper <matthew.d.roper@intel.com>,
	Rodrigo Vivi <rodrigo.vivi@intel.com>
Subject: Re: [PATCH 3/3] drm/xe: Use VF_CAP_REG for device wmb
Date: Mon, 26 Aug 2024 16:24:30 -0700	[thread overview]
Message-ID: <87cyluuatt.wl-ashutosh.dixit@intel.com> (raw)
In-Reply-To: <20240702183704.1022-4-michal.wajdeczko@intel.com>

On Tue, 02 Jul 2024 11:37:04 -0700, Michal Wajdeczko wrote:
>

I have a couple of questions about xe_device_wmb() below:

> To force a write barrier on the device memory, we write to the
> SOFTWARE_FLAGS_SPR33 register, but this particular register was
> selected because it was one of the writable and unused register.
>
> Since a write barrier should also work if we use the read-only
> register, switch to VF_CAP_REG register that is also marked as
> accessible for VFs.
>
> While at it, add simple kernel-doc for xe_device_wmb() function.
>
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_device.c | 11 ++++++++++-
>  1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
> index cfda7cb5df2c..74beddb55284 100644
> --- a/drivers/gpu/drm/xe/xe_device.c
> +++ b/drivers/gpu/drm/xe/xe_device.c
> @@ -744,13 +744,22 @@ void xe_device_shutdown(struct xe_device *xe)
>  {
>  }
>
> +/**
> + * xe_device_wmb() - Device specific write memory barrier
> + * @xe: the &xe_device
> + *
> + * While wmb() is sufficient for a barrier if we use system memory, on discrete
> + * platforms with device memory we additionally need to issue a register write.
> + * Since it doesn't matter which register we write to, use the read-only VF_CAP
> + * register that is also marked as accessible by the VFs.
> + */
>  void xe_device_wmb(struct xe_device *xe)
>  {
>	struct xe_gt *gt = xe_root_mmio_gt(xe);
>
>	wmb();
>	if (IS_DGFX(xe))
> -		xe_mmio_write32(gt, SOFTWARE_FLAGS_SPR33, 0);
> +		xe_mmio_write32(gt, VF_CAP_REG, 0);

* What is the purpose of this register write following wmb (aka sfence)?
  As far as I understand, wmb/sfence should be sufficient by itself.

  If we wanted to flush PCI transactions, we should have to issue a PCI
  read, but here we are not doing that.

* Why only Xe has such a function, why is such a function not present in
  any of the other drivers, including i915?

* Also, as an aside, use of write barriers in the kernel requires a comment
  saying which read barrier the write barrier is paired with. Generally
  speaking, such comments are missing in Xe.

I have sent a patch with xe_device_wmb() replaced just with wmb() here:

	https://patchwork.freedesktop.org/series/137818/

Let's see if we see any failures in CI with this patch.

Thanks.
--
Ashutosh

  parent reply	other threads:[~2024-08-26 23:43 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-07-02 18:37 [PATCH 0/3] drm/xe: Use VF_CAP_REG for device wmb Michal Wajdeczko
2024-07-02 18:37 ` [PATCH 1/3] drm/xe: Fix register definition order in xe_regs.h Michal Wajdeczko
2024-07-04  3:17   ` Ghimiray, Himal Prasad
2024-07-02 18:37 ` [PATCH 2/3] drm/xe: Kill regs/xe_sriov_regs.h Michal Wajdeczko
2024-07-04  3:17   ` Ghimiray, Himal Prasad
2024-07-02 18:37 ` [PATCH 3/3] drm/xe: Use VF_CAP_REG for device wmb Michal Wajdeczko
2024-07-04  4:01   ` Ghimiray, Himal Prasad
2024-08-26 23:24   ` Dixit, Ashutosh [this message]
2024-08-27 21:05     ` Michal Wajdeczko
2024-07-02 22:13 ` [PATCH 0/3] " Matt Roper
2024-07-03 13:22 ` ✓ CI.Patch_applied: success for " Patchwork
2024-07-03 13:22 ` ✗ CI.checkpatch: warning " Patchwork
2024-07-03 13:23 ` ✓ CI.KUnit: success " Patchwork
2024-07-03 13:35 ` ✓ CI.Build: " Patchwork
2024-07-03 13:38 ` ✓ CI.Hooks: " Patchwork
2024-07-03 13:39 ` ✓ CI.checksparse: " Patchwork
2024-07-03 14:05 ` ✓ CI.BAT: " Patchwork
2024-07-03 17:52 ` ✗ CI.FULL: failure " Patchwork
2024-07-03 19:42   ` Michal Wajdeczko

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