Re: [PATCH v2 2/4] drm/xe/oa: Fix offset alignment for MERT WHITELIST_OA_MERT_MMIO_TRG

["Dixit, Ashutosh" <ashutosh.dixit@intel.com>]

On Thu, 25 Jun 2026 16:10:31 -0700, Umesh Nerlige Ramappa wrote:
>
> On Tue, Jun 16, 2026 at 06:54:20PM -0700, Ashutosh Dixit wrote:
> > 'tail_buf' argument for WHITELIST_OA_MERT_MMIO_TRG was previously
> > wrong (not multiple of 16). Fix this.
> >
> > Fixes: ec02e49f21bc ("drm/xe/rtp: Whitelist OAMERT MMIO trigger registers")
> > Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
>
> Note that the SW whitelist needs to be documented in the relevant spec
> sections here: BSpec 53688. Can you please have something to track that?

Sure I will do this.

> With that this is:
>
> Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

Thanks!

>
> > ---
> > drivers/gpu/drm/xe/xe_reg_whitelist.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
> > index a17ebacc1455b..880079473c26b 100644
> > --- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
> > +++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
> > @@ -124,7 +124,7 @@ static const struct xe_rtp_table_sr register_whitelist = XE_RTP_TABLE_SR(
> >			      OAM_HEAD_POINTER(XE_OAM_SCMI_1_BASE_ADJ))
> >
> > #define WHITELIST_OA_MERT_MMIO_TRG \
> > -	WHITELIST_OA_MMIO_TRG(OAMERT_MMIO_TRG, OAMERT_STATUS, OAMERT_HEAD_POINTER)
> > +	WHITELIST_OA_MMIO_TRG(OAMERT_MMIO_TRG, OAMERT_STATUS, OAMERT_TAIL_POINTER)
> >
> >	{ XE_RTP_NAME("oag_mmio_trg_rcs"),
> >	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, XE_RTP_END_VERSION_UNDEFINED),
> > --
> > 2.54.0
> >