[PATCH v2 0/4] drm/i915/bw: Split bandwidth params into platform- and display-IP-specific structs

[PATCH v2 0/4] drm/i915/bw: Split bandwidth params into platform- and display-IP-specific structs

[Gustavo Sousa]

Some of the parameters of used in display bandwidth calculations are
tied to the platform and are orthogonal to the display IP.  After talking
with the hardware team, we now have the information (and Bspec has been
updated) that the members deprogbwlimit and derating of struct
intel_sa_info are such platform-specific ones.

With that, we are now able to make the driver code more aligned with the
hardware by splitting structs intel_sa_info into two different structs:
one that is platform-specific and another that is display-IP-specific.

That change also allows us to simplify how we select the parameters for
the calculation.

Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
Changes in v2:
- Incorporated review feedback; see each individual patch for details.
- Link to v1: https://patch.msgid.link/20260408-separate-platform-from-diplay-ip-specific-bw-params-v1-0-23c53afa7db0@intel.com

---
Gustavo Sousa (4):
      drm/i915/bw: Extract platform-specific parameters
      drm/i915/bw: Deduplicate intel_sa_info instances
      drm/i915/bw: Rename struct intel_sa_info to intel_display_bw_params
      drm/i915/bw: Extract get_display_bw_params()

 drivers/gpu/drm/i915/display/intel_bw.c | 208 ++++++++++++++++++++------------
 1 file changed, 132 insertions(+), 76 deletions(-)
---
base-commit: 0a6c4b1478138dae3ff979b9e95879c6a4def444
change-id: 20260408-separate-platform-from-diplay-ip-specific-bw-params-65bfba0603be

Best regards,
--  
Gustavo Sousa <gustavo.sousa@intel.com>

[PATCH v2 1/4] drm/i915/bw: Extract platform-specific parameters

[Gustavo Sousa]

We got confirmation from the hardware team that the bandwidth parameters
deprogbwlimit and derating are platform-specific and not tied to the
display IP.  As such, let's make sure that we use platform checks for
those.

The rest of the members of struct intel_sa_info are tied to the display
IP and we will deal with them as a follow-up.

v2:
  - Use good old if-ladder instead of weird-looking pattern "assign ret,
    check platform, then return ret". (Jani, Matt)
  - Have a single call site for get_platform_bw_params() and pass the
    result as parameter to the *_get_bw_info() functions. (Jani)
  - Avoid using "plat" as abbreviation for "platform". (Jani)
  - s/_plat_bw_params/_bw_params/, since all of the instances are
    prefixed with platform names. (Jani)
  - s/struct intel_platform_bw_params/struct intel_soc_bw_params/.
    (Matt)
  - Do not return a default value; prefer to return NULL and
    intentionally cause a NULL pointer dereference if a platform is
    missing. (Gustavo)

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 161 ++++++++++++++++++++++----------
 1 file changed, 113 insertions(+), 48 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 9c3a9bbb49f6..cf6756b8ae52 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -372,81 +372,147 @@ static int icl_sagv_max_dclk(const struct intel_qgv_info *qi)
 	return dclk;
 }
 
+struct intel_soc_bw_params {
+	u8 deprogbwlimit;
+	u8 derating;
+};
+
+static const struct intel_soc_bw_params icl_bw_params = {
+	.deprogbwlimit = 25,
+	.derating = 10,
+};
+
+static const struct intel_soc_bw_params tgl_bw_params = {
+	.deprogbwlimit = 34,
+	.derating = 10,
+};
+
+static const struct intel_soc_bw_params rkl_bw_params = {
+	.deprogbwlimit = 20,
+	.derating = 10,
+};
+
+static const struct intel_soc_bw_params adl_s_bw_params = {
+	.deprogbwlimit = 38,
+	.derating = 10,
+};
+
+static const struct intel_soc_bw_params adl_p_bw_params = {
+	.deprogbwlimit = 38,
+	.derating = 20,
+};
+
+static const struct intel_soc_bw_params bmg_bw_params = {
+	.deprogbwlimit = 53,
+	.derating = 30,
+};
+
+static const struct intel_soc_bw_params bmg_ecc_bw_params = {
+	.deprogbwlimit = 53,
+	.derating = 45,
+};
+
+static const struct intel_soc_bw_params ptl_bw_params = {
+	.deprogbwlimit = 65,
+	.derating = 10,
+};
+
+static const struct intel_soc_bw_params wcl_bw_params = {
+	.deprogbwlimit = 22,
+	.derating = 10,
+};
+
+static const struct intel_soc_bw_params *get_soc_bw_params(struct intel_display *display)
+{
+	if (display->platform.dgfx) {
+		if (display->platform.dg1) {
+			return &tgl_bw_params;
+		} else if (display->platform.battlemage) {
+			const struct dram_info *dram_info = intel_dram_info(display);
+
+			if (dram_info->type == INTEL_DRAM_GDDR_ECC)
+				return &bmg_ecc_bw_params;
+			else
+				return &bmg_bw_params;
+		}
+	} else {
+		if (display->platform.icelake ||
+		    display->platform.jasperlake ||
+		    display->platform.elkhartlake) {
+			return &icl_bw_params;
+		} else if (display->platform.tigerlake) {
+			return &tgl_bw_params;
+		} else if (display->platform.rocketlake) {
+			return &rkl_bw_params;
+		} else if (display->platform.alderlake_s) {
+			return &adl_s_bw_params;
+		} else if (display->platform.alderlake_p) {
+			return &adl_p_bw_params;
+		} else if (display->platform.meteorlake ||
+			   display->platform.lunarlake) {
+			return &adl_s_bw_params;
+		} else if (display->platform.pantherlake ||
+			   display->platform.novalake) {
+			if (display->platform.pantherlake_wildcatlake)
+				return &wcl_bw_params;
+			else
+				return &ptl_bw_params;
+		}
+	}
+
+	drm_WARN(display->drm, 1, "Platform-specific bandwidth parameters not found!\n");
+
+	return NULL;
+}
+
 struct intel_sa_info {
 	u16 displayrtids;
-	u8 deburst, deprogbwlimit, derating;
+	u8 deburst;
 };
 
 static const struct intel_sa_info icl_sa_info = {
 	.deburst = 8,
-	.deprogbwlimit = 25, /* GB/s */
 	.displayrtids = 128,
-	.derating = 10,
 };
 
 static const struct intel_sa_info tgl_sa_info = {
 	.deburst = 16,
-	.deprogbwlimit = 34, /* GB/s */
 	.displayrtids = 256,
-	.derating = 10,
 };
 
 static const struct intel_sa_info rkl_sa_info = {
 	.deburst = 8,
-	.deprogbwlimit = 20, /* GB/s */
 	.displayrtids = 128,
-	.derating = 10,
 };
 
 static const struct intel_sa_info adls_sa_info = {
 	.deburst = 16,
-	.deprogbwlimit = 38, /* GB/s */
 	.displayrtids = 256,
-	.derating = 10,
 };
 
 static const struct intel_sa_info adlp_sa_info = {
 	.deburst = 16,
-	.deprogbwlimit = 38, /* GB/s */
 	.displayrtids = 256,
-	.derating = 20,
 };
 
 static const struct intel_sa_info mtl_sa_info = {
 	.deburst = 32,
-	.deprogbwlimit = 38, /* GB/s */
 	.displayrtids = 256,
-	.derating = 10,
-};
-
-static const struct intel_sa_info xe2_hpd_sa_info = {
-	.derating = 30,
-	.deprogbwlimit = 53,
-	/* Other values not used by simplified algorithm */
-};
-
-static const struct intel_sa_info xe2_hpd_ecc_sa_info = {
-	.derating = 45,
-	.deprogbwlimit = 53,
-	/* Other values not used by simplified algorithm */
 };
 
 static const struct intel_sa_info xe3lpd_sa_info = {
 	.deburst = 32,
-	.deprogbwlimit = 65, /* GB/s */
 	.displayrtids = 256,
-	.derating = 10,
 };
 
 static const struct intel_sa_info xe3lpd_3002_sa_info = {
 	.deburst = 32,
-	.deprogbwlimit = 22, /* GB/s */
 	.displayrtids = 256,
-	.derating = 10,
 };
 
 static int icl_get_bw_info(struct intel_display *display,
 			   const struct dram_info *dram_info,
+			   const struct intel_soc_bw_params *soc_bw_params,
 			   const struct intel_sa_info *sa)
 {
 	struct intel_qgv_info qi = {};
@@ -466,7 +532,7 @@ static int icl_get_bw_info(struct intel_display *display,
 	}
 
 	dclk_max = icl_sagv_max_dclk(&qi);
-	maxdebw = min(sa->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
+	maxdebw = min(soc_bw_params->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
 	ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
 	qi.deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
 
@@ -496,7 +562,7 @@ static int icl_get_bw_info(struct intel_display *display,
 			bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct);
 
 			bi->deratedbw[j] = min(maxdebw,
-					       bw * (100 - sa->derating) / 100);
+					       bw * (100 - soc_bw_params->derating) / 100);
 
 			drm_dbg_kms(display->drm,
 				    "BW%d / QGV %d: num_planes=%d deratedbw=%u\n",
@@ -518,6 +584,7 @@ static int icl_get_bw_info(struct intel_display *display,
 
 static int tgl_get_bw_info(struct intel_display *display,
 			   const struct dram_info *dram_info,
+			   const struct intel_soc_bw_params *soc_bw_params,
 			   const struct intel_sa_info *sa)
 {
 	struct intel_qgv_info qi = {};
@@ -554,7 +621,7 @@ static int tgl_get_bw_info(struct intel_display *display,
 	dclk_max = icl_sagv_max_dclk(&qi);
 
 	peakbw = num_channels * DIV_ROUND_UP(qi.channel_width, 8) * dclk_max;
-	maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100);
+	maxdebw = min(soc_bw_params->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100);
 
 	ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
 	/*
@@ -599,7 +666,7 @@ static int tgl_get_bw_info(struct intel_display *display,
 			bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct);
 
 			bi->deratedbw[j] = min(maxdebw,
-					       bw * (100 - sa->derating) / 100);
+					       bw * (100 - soc_bw_params->derating) / 100);
 			bi->peakbw[j] = DIV_ROUND_CLOSEST(sp->dclk *
 							  num_channels *
 							  qi.channel_width, 8);
@@ -661,7 +728,7 @@ static void dg2_get_bw_info(struct intel_display *display)
 
 static int xe2_hpd_get_bw_info(struct intel_display *display,
 			       const struct dram_info *dram_info,
-			       const struct intel_sa_info *sa)
+			       const struct intel_soc_bw_params *soc_bw_params)
 {
 	struct intel_qgv_info qi = {};
 	int num_channels = dram_info->num_channels;
@@ -676,14 +743,14 @@ static int xe2_hpd_get_bw_info(struct intel_display *display,
 	}
 
 	peakbw = num_channels * qi.channel_width / 8 * icl_sagv_max_dclk(&qi);
-	maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 10);
+	maxdebw = min(soc_bw_params->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 10);
 
 	for (i = 0; i < qi.num_points; i++) {
 		const struct intel_qgv_point *point = &qi.points[i];
 		int bw = num_channels * (qi.channel_width / 8) * point->dclk;
 
 		display->bw.max[0].deratedbw[i] =
-			min(maxdebw, (100 - sa->derating) * bw / 100);
+			min(maxdebw, (100 - soc_bw_params->derating) * bw / 100);
 		display->bw.max[0].peakbw[i] = bw;
 
 		drm_dbg_kms(display->drm, "QGV %d: deratedbw=%u peakbw: %u\n",
@@ -792,6 +859,7 @@ static unsigned int icl_qgv_bw(struct intel_display *display,
 void intel_bw_init_hw(struct intel_display *display)
 {
 	const struct dram_info *dram_info = intel_dram_info(display);
+	const struct intel_soc_bw_params *soc_bw_params = get_soc_bw_params(display);
 
 	if (!HAS_DISPLAY(display))
 		return;
@@ -807,28 +875,25 @@ void intel_bw_init_hw(struct intel_display *display)
 
 	if (DISPLAY_VER(display) >= 30) {
 		if (DISPLAY_VERx100(display) == 3002)
-			tgl_get_bw_info(display, dram_info, &xe3lpd_3002_sa_info);
+			tgl_get_bw_info(display, dram_info, soc_bw_params, &xe3lpd_3002_sa_info);
 		else
-			tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);
+			tgl_get_bw_info(display, dram_info, soc_bw_params, &xe3lpd_sa_info);
 	} else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
-		if (dram_info->type == INTEL_DRAM_GDDR_ECC)
-			xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_ecc_sa_info);
-		else
-			xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_sa_info);
+		xe2_hpd_get_bw_info(display, dram_info, soc_bw_params);
 	} else if (DISPLAY_VER(display) >= 14) {
-		tgl_get_bw_info(display, dram_info, &mtl_sa_info);
+		tgl_get_bw_info(display, dram_info, soc_bw_params, &mtl_sa_info);
 	} else if (display->platform.dg2) {
 		dg2_get_bw_info(display);
 	} else if (display->platform.alderlake_p) {
-		tgl_get_bw_info(display, dram_info, &adlp_sa_info);
+		tgl_get_bw_info(display, dram_info, soc_bw_params, &adlp_sa_info);
 	} else if (display->platform.alderlake_s) {
-		tgl_get_bw_info(display, dram_info, &adls_sa_info);
+		tgl_get_bw_info(display, dram_info, soc_bw_params, &adls_sa_info);
 	} else if (display->platform.rocketlake) {
-		tgl_get_bw_info(display, dram_info, &rkl_sa_info);
+		tgl_get_bw_info(display, dram_info, soc_bw_params, &rkl_sa_info);
 	} else if (DISPLAY_VER(display) == 12) {
-		tgl_get_bw_info(display, dram_info, &tgl_sa_info);
+		tgl_get_bw_info(display, dram_info, soc_bw_params, &tgl_sa_info);
 	} else if (DISPLAY_VER(display) == 11) {
-		icl_get_bw_info(display, dram_info, &icl_sa_info);
+		icl_get_bw_info(display, dram_info, soc_bw_params, &icl_sa_info);
 	}
 }
 

-- 
2.53.0

Re: [PATCH v2 1/4] drm/i915/bw: Extract platform-specific parameters

[Matt Roper]

On Mon, May 11, 2026 at 01:30:56PM -0300, Gustavo Sousa wrote:
> We got confirmation from the hardware team that the bandwidth parameters
> deprogbwlimit and derating are platform-specific and not tied to the
> display IP.  As such, let's make sure that we use platform checks for
> those.
> 
> The rest of the members of struct intel_sa_info are tied to the display
> IP and we will deal with them as a follow-up.
> 
> v2:
>   - Use good old if-ladder instead of weird-looking pattern "assign ret,
>     check platform, then return ret". (Jani, Matt)
>   - Have a single call site for get_platform_bw_params() and pass the
>     result as parameter to the *_get_bw_info() functions. (Jani)
>   - Avoid using "plat" as abbreviation for "platform". (Jani)
>   - s/_plat_bw_params/_bw_params/, since all of the instances are
>     prefixed with platform names. (Jani)
>   - s/struct intel_platform_bw_params/struct intel_soc_bw_params/.
>     (Matt)
>   - Do not return a default value; prefer to return NULL and
>     intentionally cause a NULL pointer dereference if a platform is
>     missing. (Gustavo)
> 
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_bw.c | 161 ++++++++++++++++++++++----------
>  1 file changed, 113 insertions(+), 48 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 9c3a9bbb49f6..cf6756b8ae52 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -372,81 +372,147 @@ static int icl_sagv_max_dclk(const struct intel_qgv_info *qi)
>  	return dclk;
>  }
>  
> +struct intel_soc_bw_params {
> +	u8 deprogbwlimit;
> +	u8 derating;
> +};
> +
> +static const struct intel_soc_bw_params icl_bw_params = {
> +	.deprogbwlimit = 25,
> +	.derating = 10,
> +};
> +
> +static const struct intel_soc_bw_params tgl_bw_params = {
> +	.deprogbwlimit = 34,
> +	.derating = 10,
> +};
> +
> +static const struct intel_soc_bw_params rkl_bw_params = {
> +	.deprogbwlimit = 20,
> +	.derating = 10,
> +};
> +
> +static const struct intel_soc_bw_params adl_s_bw_params = {
> +	.deprogbwlimit = 38,
> +	.derating = 10,
> +};
> +
> +static const struct intel_soc_bw_params adl_p_bw_params = {
> +	.deprogbwlimit = 38,
> +	.derating = 20,
> +};
> +
> +static const struct intel_soc_bw_params bmg_bw_params = {
> +	.deprogbwlimit = 53,
> +	.derating = 30,
> +};
> +
> +static const struct intel_soc_bw_params bmg_ecc_bw_params = {
> +	.deprogbwlimit = 53,
> +	.derating = 45,
> +};
> +
> +static const struct intel_soc_bw_params ptl_bw_params = {
> +	.deprogbwlimit = 65,
> +	.derating = 10,
> +};
> +
> +static const struct intel_soc_bw_params wcl_bw_params = {
> +	.deprogbwlimit = 22,
> +	.derating = 10,
> +};
> +
> +static const struct intel_soc_bw_params *get_soc_bw_params(struct intel_display *display)
> +{
> +	if (display->platform.dgfx) {
> +		if (display->platform.dg1) {
> +			return &tgl_bw_params;
> +		} else if (display->platform.battlemage) {
> +			const struct dram_info *dram_info = intel_dram_info(display);
> +
> +			if (dram_info->type == INTEL_DRAM_GDDR_ECC)
> +				return &bmg_ecc_bw_params;
> +			else
> +				return &bmg_bw_params;
> +		}
> +	} else {
> +		if (display->platform.icelake ||
> +		    display->platform.jasperlake ||
> +		    display->platform.elkhartlake) {
> +			return &icl_bw_params;
> +		} else if (display->platform.tigerlake) {
> +			return &tgl_bw_params;
> +		} else if (display->platform.rocketlake) {
> +			return &rkl_bw_params;
> +		} else if (display->platform.alderlake_s) {
> +			return &adl_s_bw_params;
> +		} else if (display->platform.alderlake_p) {
> +			return &adl_p_bw_params;
> +		} else if (display->platform.meteorlake ||
> +			   display->platform.lunarlake) {
> +			return &adl_s_bw_params;

Any reason not to combine this with the ADL-S branch of the if/else
ladder?

> +		} else if (display->platform.pantherlake ||
> +			   display->platform.novalake) {
> +			if (display->platform.pantherlake_wildcatlake)
> +				return &wcl_bw_params;

Can we just flatten this out rather than nesting?

        } else if (display->platform.pantherlake_wildcatlake) {
                return &wcl_bw_params;
        } else if (display->platform.pantherlake ||
                   display->platform.novalake) {
                return &ptl_bw_params;
        }


> +			else
> +				return &ptl_bw_params;
> +		}
> +	}
> +
> +	drm_WARN(display->drm, 1, "Platform-specific bandwidth parameters not found!\n");

I think 

  i915_driver_hw_probe -> intel_bw_init_hw -> get_soc_bw_params

is called unconditionally on all platforms for i915, not just the recent
ones where we started caring about memory bandwidth, so I'm not sure if
this WARN is appropriate since we'll always hit it on the pre-gen11
stuff.

Since the values populated here only get used when paired with display
IP version 11 or later, we should probably add that as a condition since
those are the only cases where it matters that we found a set of SoC
parameters.


Matt

> +
> +	return NULL;
> +}
> +
>  struct intel_sa_info {
>  	u16 displayrtids;
> -	u8 deburst, deprogbwlimit, derating;
> +	u8 deburst;
>  };
>  
>  static const struct intel_sa_info icl_sa_info = {
>  	.deburst = 8,
> -	.deprogbwlimit = 25, /* GB/s */
>  	.displayrtids = 128,
> -	.derating = 10,
>  };
>  
>  static const struct intel_sa_info tgl_sa_info = {
>  	.deburst = 16,
> -	.deprogbwlimit = 34, /* GB/s */
>  	.displayrtids = 256,
> -	.derating = 10,
>  };
>  
>  static const struct intel_sa_info rkl_sa_info = {
>  	.deburst = 8,
> -	.deprogbwlimit = 20, /* GB/s */
>  	.displayrtids = 128,
> -	.derating = 10,
>  };
>  
>  static const struct intel_sa_info adls_sa_info = {
>  	.deburst = 16,
> -	.deprogbwlimit = 38, /* GB/s */
>  	.displayrtids = 256,
> -	.derating = 10,
>  };
>  
>  static const struct intel_sa_info adlp_sa_info = {
>  	.deburst = 16,
> -	.deprogbwlimit = 38, /* GB/s */
>  	.displayrtids = 256,
> -	.derating = 20,
>  };
>  
>  static const struct intel_sa_info mtl_sa_info = {
>  	.deburst = 32,
> -	.deprogbwlimit = 38, /* GB/s */
>  	.displayrtids = 256,
> -	.derating = 10,
> -};
> -
> -static const struct intel_sa_info xe2_hpd_sa_info = {
> -	.derating = 30,
> -	.deprogbwlimit = 53,
> -	/* Other values not used by simplified algorithm */
> -};
> -
> -static const struct intel_sa_info xe2_hpd_ecc_sa_info = {
> -	.derating = 45,
> -	.deprogbwlimit = 53,
> -	/* Other values not used by simplified algorithm */
>  };
>  
>  static const struct intel_sa_info xe3lpd_sa_info = {
>  	.deburst = 32,
> -	.deprogbwlimit = 65, /* GB/s */
>  	.displayrtids = 256,
> -	.derating = 10,
>  };
>  
>  static const struct intel_sa_info xe3lpd_3002_sa_info = {
>  	.deburst = 32,
> -	.deprogbwlimit = 22, /* GB/s */
>  	.displayrtids = 256,
> -	.derating = 10,
>  };
>  
>  static int icl_get_bw_info(struct intel_display *display,
>  			   const struct dram_info *dram_info,
> +			   const struct intel_soc_bw_params *soc_bw_params,
>  			   const struct intel_sa_info *sa)
>  {
>  	struct intel_qgv_info qi = {};
> @@ -466,7 +532,7 @@ static int icl_get_bw_info(struct intel_display *display,
>  	}
>  
>  	dclk_max = icl_sagv_max_dclk(&qi);
> -	maxdebw = min(sa->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
> +	maxdebw = min(soc_bw_params->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
>  	ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
>  	qi.deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
>  
> @@ -496,7 +562,7 @@ static int icl_get_bw_info(struct intel_display *display,
>  			bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct);
>  
>  			bi->deratedbw[j] = min(maxdebw,
> -					       bw * (100 - sa->derating) / 100);
> +					       bw * (100 - soc_bw_params->derating) / 100);
>  
>  			drm_dbg_kms(display->drm,
>  				    "BW%d / QGV %d: num_planes=%d deratedbw=%u\n",
> @@ -518,6 +584,7 @@ static int icl_get_bw_info(struct intel_display *display,
>  
>  static int tgl_get_bw_info(struct intel_display *display,
>  			   const struct dram_info *dram_info,
> +			   const struct intel_soc_bw_params *soc_bw_params,
>  			   const struct intel_sa_info *sa)
>  {
>  	struct intel_qgv_info qi = {};
> @@ -554,7 +621,7 @@ static int tgl_get_bw_info(struct intel_display *display,
>  	dclk_max = icl_sagv_max_dclk(&qi);
>  
>  	peakbw = num_channels * DIV_ROUND_UP(qi.channel_width, 8) * dclk_max;
> -	maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100);
> +	maxdebw = min(soc_bw_params->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100);
>  
>  	ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
>  	/*
> @@ -599,7 +666,7 @@ static int tgl_get_bw_info(struct intel_display *display,
>  			bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct);
>  
>  			bi->deratedbw[j] = min(maxdebw,
> -					       bw * (100 - sa->derating) / 100);
> +					       bw * (100 - soc_bw_params->derating) / 100);
>  			bi->peakbw[j] = DIV_ROUND_CLOSEST(sp->dclk *
>  							  num_channels *
>  							  qi.channel_width, 8);
> @@ -661,7 +728,7 @@ static void dg2_get_bw_info(struct intel_display *display)
>  
>  static int xe2_hpd_get_bw_info(struct intel_display *display,
>  			       const struct dram_info *dram_info,
> -			       const struct intel_sa_info *sa)
> +			       const struct intel_soc_bw_params *soc_bw_params)
>  {
>  	struct intel_qgv_info qi = {};
>  	int num_channels = dram_info->num_channels;
> @@ -676,14 +743,14 @@ static int xe2_hpd_get_bw_info(struct intel_display *display,
>  	}
>  
>  	peakbw = num_channels * qi.channel_width / 8 * icl_sagv_max_dclk(&qi);
> -	maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 10);
> +	maxdebw = min(soc_bw_params->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 10);
>  
>  	for (i = 0; i < qi.num_points; i++) {
>  		const struct intel_qgv_point *point = &qi.points[i];
>  		int bw = num_channels * (qi.channel_width / 8) * point->dclk;
>  
>  		display->bw.max[0].deratedbw[i] =
> -			min(maxdebw, (100 - sa->derating) * bw / 100);
> +			min(maxdebw, (100 - soc_bw_params->derating) * bw / 100);
>  		display->bw.max[0].peakbw[i] = bw;
>  
>  		drm_dbg_kms(display->drm, "QGV %d: deratedbw=%u peakbw: %u\n",
> @@ -792,6 +859,7 @@ static unsigned int icl_qgv_bw(struct intel_display *display,
>  void intel_bw_init_hw(struct intel_display *display)
>  {
>  	const struct dram_info *dram_info = intel_dram_info(display);
> +	const struct intel_soc_bw_params *soc_bw_params = get_soc_bw_params(display);
>  
>  	if (!HAS_DISPLAY(display))
>  		return;
> @@ -807,28 +875,25 @@ void intel_bw_init_hw(struct intel_display *display)
>  
>  	if (DISPLAY_VER(display) >= 30) {
>  		if (DISPLAY_VERx100(display) == 3002)
> -			tgl_get_bw_info(display, dram_info, &xe3lpd_3002_sa_info);
> +			tgl_get_bw_info(display, dram_info, soc_bw_params, &xe3lpd_3002_sa_info);
>  		else
> -			tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);
> +			tgl_get_bw_info(display, dram_info, soc_bw_params, &xe3lpd_sa_info);
>  	} else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
> -		if (dram_info->type == INTEL_DRAM_GDDR_ECC)
> -			xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_ecc_sa_info);
> -		else
> -			xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_sa_info);
> +		xe2_hpd_get_bw_info(display, dram_info, soc_bw_params);
>  	} else if (DISPLAY_VER(display) >= 14) {
> -		tgl_get_bw_info(display, dram_info, &mtl_sa_info);
> +		tgl_get_bw_info(display, dram_info, soc_bw_params, &mtl_sa_info);
>  	} else if (display->platform.dg2) {
>  		dg2_get_bw_info(display);
>  	} else if (display->platform.alderlake_p) {
> -		tgl_get_bw_info(display, dram_info, &adlp_sa_info);
> +		tgl_get_bw_info(display, dram_info, soc_bw_params, &adlp_sa_info);
>  	} else if (display->platform.alderlake_s) {
> -		tgl_get_bw_info(display, dram_info, &adls_sa_info);
> +		tgl_get_bw_info(display, dram_info, soc_bw_params, &adls_sa_info);
>  	} else if (display->platform.rocketlake) {
> -		tgl_get_bw_info(display, dram_info, &rkl_sa_info);
> +		tgl_get_bw_info(display, dram_info, soc_bw_params, &rkl_sa_info);
>  	} else if (DISPLAY_VER(display) == 12) {
> -		tgl_get_bw_info(display, dram_info, &tgl_sa_info);
> +		tgl_get_bw_info(display, dram_info, soc_bw_params, &tgl_sa_info);
>  	} else if (DISPLAY_VER(display) == 11) {
> -		icl_get_bw_info(display, dram_info, &icl_sa_info);
> +		icl_get_bw_info(display, dram_info, soc_bw_params, &icl_sa_info);
>  	}
>  }
>  
> 
> -- 
> 2.53.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH v2 1/4] drm/i915/bw: Extract platform-specific parameters

[Jani Nikula]

On Mon, 11 May 2026, Matt Roper <matthew.d.roper@intel.com> wrote:
> On Mon, May 11, 2026 at 01:30:56PM -0300, Gustavo Sousa wrote:
>> We got confirmation from the hardware team that the bandwidth parameters
>> deprogbwlimit and derating are platform-specific and not tied to the
>> display IP.  As such, let's make sure that we use platform checks for
>> those.
>> 
>> The rest of the members of struct intel_sa_info are tied to the display
>> IP and we will deal with them as a follow-up.
>> 
>> v2:
>>   - Use good old if-ladder instead of weird-looking pattern "assign ret,
>>     check platform, then return ret". (Jani, Matt)
>>   - Have a single call site for get_platform_bw_params() and pass the
>>     result as parameter to the *_get_bw_info() functions. (Jani)
>>   - Avoid using "plat" as abbreviation for "platform". (Jani)
>>   - s/_plat_bw_params/_bw_params/, since all of the instances are
>>     prefixed with platform names. (Jani)
>>   - s/struct intel_platform_bw_params/struct intel_soc_bw_params/.
>>     (Matt)
>>   - Do not return a default value; prefer to return NULL and
>>     intentionally cause a NULL pointer dereference if a platform is
>>     missing. (Gustavo)
>> 
>> Cc: Jani Nikula <jani.nikula@intel.com>
>> Cc: Matt Roper <matthew.d.roper@intel.com>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_bw.c | 161 ++++++++++++++++++++++----------
>>  1 file changed, 113 insertions(+), 48 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
>> index 9c3a9bbb49f6..cf6756b8ae52 100644
>> --- a/drivers/gpu/drm/i915/display/intel_bw.c
>> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
>> @@ -372,81 +372,147 @@ static int icl_sagv_max_dclk(const struct intel_qgv_info *qi)
>>  	return dclk;
>>  }
>>  
>> +struct intel_soc_bw_params {
>> +	u8 deprogbwlimit;
>> +	u8 derating;
>> +};
>> +
>> +static const struct intel_soc_bw_params icl_bw_params = {
>> +	.deprogbwlimit = 25,
>> +	.derating = 10,
>> +};
>> +
>> +static const struct intel_soc_bw_params tgl_bw_params = {
>> +	.deprogbwlimit = 34,
>> +	.derating = 10,
>> +};
>> +
>> +static const struct intel_soc_bw_params rkl_bw_params = {
>> +	.deprogbwlimit = 20,
>> +	.derating = 10,
>> +};
>> +
>> +static const struct intel_soc_bw_params adl_s_bw_params = {
>> +	.deprogbwlimit = 38,
>> +	.derating = 10,
>> +};
>> +
>> +static const struct intel_soc_bw_params adl_p_bw_params = {
>> +	.deprogbwlimit = 38,
>> +	.derating = 20,
>> +};
>> +
>> +static const struct intel_soc_bw_params bmg_bw_params = {
>> +	.deprogbwlimit = 53,
>> +	.derating = 30,
>> +};
>> +
>> +static const struct intel_soc_bw_params bmg_ecc_bw_params = {
>> +	.deprogbwlimit = 53,
>> +	.derating = 45,
>> +};
>> +
>> +static const struct intel_soc_bw_params ptl_bw_params = {
>> +	.deprogbwlimit = 65,
>> +	.derating = 10,
>> +};
>> +
>> +static const struct intel_soc_bw_params wcl_bw_params = {
>> +	.deprogbwlimit = 22,
>> +	.derating = 10,
>> +};
>> +
>> +static const struct intel_soc_bw_params *get_soc_bw_params(struct intel_display *display)
>> +{
>> +	if (display->platform.dgfx) {
>> +		if (display->platform.dg1) {
>> +			return &tgl_bw_params;
>> +		} else if (display->platform.battlemage) {
>> +			const struct dram_info *dram_info = intel_dram_info(display);
>> +
>> +			if (dram_info->type == INTEL_DRAM_GDDR_ECC)
>> +				return &bmg_ecc_bw_params;
>> +			else
>> +				return &bmg_bw_params;
>> +		}
>> +	} else {
>> +		if (display->platform.icelake ||
>> +		    display->platform.jasperlake ||
>> +		    display->platform.elkhartlake) {
>> +			return &icl_bw_params;
>> +		} else if (display->platform.tigerlake) {
>> +			return &tgl_bw_params;
>> +		} else if (display->platform.rocketlake) {
>> +			return &rkl_bw_params;
>> +		} else if (display->platform.alderlake_s) {
>> +			return &adl_s_bw_params;
>> +		} else if (display->platform.alderlake_p) {
>> +			return &adl_p_bw_params;
>> +		} else if (display->platform.meteorlake ||
>> +			   display->platform.lunarlake) {
>> +			return &adl_s_bw_params;
>
> Any reason not to combine this with the ADL-S branch of the if/else
> ladder?
>
>> +		} else if (display->platform.pantherlake ||
>> +			   display->platform.novalake) {
>> +			if (display->platform.pantherlake_wildcatlake)
>> +				return &wcl_bw_params;
>
> Can we just flatten this out rather than nesting?
>
>         } else if (display->platform.pantherlake_wildcatlake) {
>                 return &wcl_bw_params;
>         } else if (display->platform.pantherlake ||
>                    display->platform.novalake) {
>                 return &ptl_bw_params;
>         }
>
>
>> +			else
>> +				return &ptl_bw_params;
>> +		}
>> +	}
>> +
>> +	drm_WARN(display->drm, 1, "Platform-specific bandwidth parameters not found!\n");
>
> I think 
>
>   i915_driver_hw_probe -> intel_bw_init_hw -> get_soc_bw_params
>
> is called unconditionally on all platforms for i915, not just the recent
> ones where we started caring about memory bandwidth, so I'm not sure if
> this WARN is appropriate since we'll always hit it on the pre-gen11
> stuff.
>
> Since the values populated here only get used when paired with display
> IP version 11 or later, we should probably add that as a condition since
> those are the only cases where it matters that we found a set of SoC
> parameters.

In general, we should stop calling low level display init functions from
i915 core code. Can we move the init call to some display init function?

That said, it'll still get called on all sorts of platforms.

BR,
Jani.


>
>
> Matt
>
>> +
>> +	return NULL;
>> +}
>> +
>>  struct intel_sa_info {
>>  	u16 displayrtids;
>> -	u8 deburst, deprogbwlimit, derating;
>> +	u8 deburst;
>>  };
>>  
>>  static const struct intel_sa_info icl_sa_info = {
>>  	.deburst = 8,
>> -	.deprogbwlimit = 25, /* GB/s */
>>  	.displayrtids = 128,
>> -	.derating = 10,
>>  };
>>  
>>  static const struct intel_sa_info tgl_sa_info = {
>>  	.deburst = 16,
>> -	.deprogbwlimit = 34, /* GB/s */
>>  	.displayrtids = 256,
>> -	.derating = 10,
>>  };
>>  
>>  static const struct intel_sa_info rkl_sa_info = {
>>  	.deburst = 8,
>> -	.deprogbwlimit = 20, /* GB/s */
>>  	.displayrtids = 128,
>> -	.derating = 10,
>>  };
>>  
>>  static const struct intel_sa_info adls_sa_info = {
>>  	.deburst = 16,
>> -	.deprogbwlimit = 38, /* GB/s */
>>  	.displayrtids = 256,
>> -	.derating = 10,
>>  };
>>  
>>  static const struct intel_sa_info adlp_sa_info = {
>>  	.deburst = 16,
>> -	.deprogbwlimit = 38, /* GB/s */
>>  	.displayrtids = 256,
>> -	.derating = 20,
>>  };
>>  
>>  static const struct intel_sa_info mtl_sa_info = {
>>  	.deburst = 32,
>> -	.deprogbwlimit = 38, /* GB/s */
>>  	.displayrtids = 256,
>> -	.derating = 10,
>> -};
>> -
>> -static const struct intel_sa_info xe2_hpd_sa_info = {
>> -	.derating = 30,
>> -	.deprogbwlimit = 53,
>> -	/* Other values not used by simplified algorithm */
>> -};
>> -
>> -static const struct intel_sa_info xe2_hpd_ecc_sa_info = {
>> -	.derating = 45,
>> -	.deprogbwlimit = 53,
>> -	/* Other values not used by simplified algorithm */
>>  };
>>  
>>  static const struct intel_sa_info xe3lpd_sa_info = {
>>  	.deburst = 32,
>> -	.deprogbwlimit = 65, /* GB/s */
>>  	.displayrtids = 256,
>> -	.derating = 10,
>>  };
>>  
>>  static const struct intel_sa_info xe3lpd_3002_sa_info = {
>>  	.deburst = 32,
>> -	.deprogbwlimit = 22, /* GB/s */
>>  	.displayrtids = 256,
>> -	.derating = 10,
>>  };
>>  
>>  static int icl_get_bw_info(struct intel_display *display,
>>  			   const struct dram_info *dram_info,
>> +			   const struct intel_soc_bw_params *soc_bw_params,
>>  			   const struct intel_sa_info *sa)
>>  {
>>  	struct intel_qgv_info qi = {};
>> @@ -466,7 +532,7 @@ static int icl_get_bw_info(struct intel_display *display,
>>  	}
>>  
>>  	dclk_max = icl_sagv_max_dclk(&qi);
>> -	maxdebw = min(sa->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
>> +	maxdebw = min(soc_bw_params->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
>>  	ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
>>  	qi.deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
>>  
>> @@ -496,7 +562,7 @@ static int icl_get_bw_info(struct intel_display *display,
>>  			bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct);
>>  
>>  			bi->deratedbw[j] = min(maxdebw,
>> -					       bw * (100 - sa->derating) / 100);
>> +					       bw * (100 - soc_bw_params->derating) / 100);
>>  
>>  			drm_dbg_kms(display->drm,
>>  				    "BW%d / QGV %d: num_planes=%d deratedbw=%u\n",
>> @@ -518,6 +584,7 @@ static int icl_get_bw_info(struct intel_display *display,
>>  
>>  static int tgl_get_bw_info(struct intel_display *display,
>>  			   const struct dram_info *dram_info,
>> +			   const struct intel_soc_bw_params *soc_bw_params,
>>  			   const struct intel_sa_info *sa)
>>  {
>>  	struct intel_qgv_info qi = {};
>> @@ -554,7 +621,7 @@ static int tgl_get_bw_info(struct intel_display *display,
>>  	dclk_max = icl_sagv_max_dclk(&qi);
>>  
>>  	peakbw = num_channels * DIV_ROUND_UP(qi.channel_width, 8) * dclk_max;
>> -	maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100);
>> +	maxdebw = min(soc_bw_params->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100);
>>  
>>  	ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
>>  	/*
>> @@ -599,7 +666,7 @@ static int tgl_get_bw_info(struct intel_display *display,
>>  			bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct);
>>  
>>  			bi->deratedbw[j] = min(maxdebw,
>> -					       bw * (100 - sa->derating) / 100);
>> +					       bw * (100 - soc_bw_params->derating) / 100);
>>  			bi->peakbw[j] = DIV_ROUND_CLOSEST(sp->dclk *
>>  							  num_channels *
>>  							  qi.channel_width, 8);
>> @@ -661,7 +728,7 @@ static void dg2_get_bw_info(struct intel_display *display)
>>  
>>  static int xe2_hpd_get_bw_info(struct intel_display *display,
>>  			       const struct dram_info *dram_info,
>> -			       const struct intel_sa_info *sa)
>> +			       const struct intel_soc_bw_params *soc_bw_params)
>>  {
>>  	struct intel_qgv_info qi = {};
>>  	int num_channels = dram_info->num_channels;
>> @@ -676,14 +743,14 @@ static int xe2_hpd_get_bw_info(struct intel_display *display,
>>  	}
>>  
>>  	peakbw = num_channels * qi.channel_width / 8 * icl_sagv_max_dclk(&qi);
>> -	maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 10);
>> +	maxdebw = min(soc_bw_params->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 10);
>>  
>>  	for (i = 0; i < qi.num_points; i++) {
>>  		const struct intel_qgv_point *point = &qi.points[i];
>>  		int bw = num_channels * (qi.channel_width / 8) * point->dclk;
>>  
>>  		display->bw.max[0].deratedbw[i] =
>> -			min(maxdebw, (100 - sa->derating) * bw / 100);
>> +			min(maxdebw, (100 - soc_bw_params->derating) * bw / 100);
>>  		display->bw.max[0].peakbw[i] = bw;
>>  
>>  		drm_dbg_kms(display->drm, "QGV %d: deratedbw=%u peakbw: %u\n",
>> @@ -792,6 +859,7 @@ static unsigned int icl_qgv_bw(struct intel_display *display,
>>  void intel_bw_init_hw(struct intel_display *display)
>>  {
>>  	const struct dram_info *dram_info = intel_dram_info(display);
>> +	const struct intel_soc_bw_params *soc_bw_params = get_soc_bw_params(display);
>>  
>>  	if (!HAS_DISPLAY(display))
>>  		return;
>> @@ -807,28 +875,25 @@ void intel_bw_init_hw(struct intel_display *display)
>>  
>>  	if (DISPLAY_VER(display) >= 30) {
>>  		if (DISPLAY_VERx100(display) == 3002)
>> -			tgl_get_bw_info(display, dram_info, &xe3lpd_3002_sa_info);
>> +			tgl_get_bw_info(display, dram_info, soc_bw_params, &xe3lpd_3002_sa_info);
>>  		else
>> -			tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);
>> +			tgl_get_bw_info(display, dram_info, soc_bw_params, &xe3lpd_sa_info);
>>  	} else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
>> -		if (dram_info->type == INTEL_DRAM_GDDR_ECC)
>> -			xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_ecc_sa_info);
>> -		else
>> -			xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_sa_info);
>> +		xe2_hpd_get_bw_info(display, dram_info, soc_bw_params);
>>  	} else if (DISPLAY_VER(display) >= 14) {
>> -		tgl_get_bw_info(display, dram_info, &mtl_sa_info);
>> +		tgl_get_bw_info(display, dram_info, soc_bw_params, &mtl_sa_info);
>>  	} else if (display->platform.dg2) {
>>  		dg2_get_bw_info(display);
>>  	} else if (display->platform.alderlake_p) {
>> -		tgl_get_bw_info(display, dram_info, &adlp_sa_info);
>> +		tgl_get_bw_info(display, dram_info, soc_bw_params, &adlp_sa_info);
>>  	} else if (display->platform.alderlake_s) {
>> -		tgl_get_bw_info(display, dram_info, &adls_sa_info);
>> +		tgl_get_bw_info(display, dram_info, soc_bw_params, &adls_sa_info);
>>  	} else if (display->platform.rocketlake) {
>> -		tgl_get_bw_info(display, dram_info, &rkl_sa_info);
>> +		tgl_get_bw_info(display, dram_info, soc_bw_params, &rkl_sa_info);
>>  	} else if (DISPLAY_VER(display) == 12) {
>> -		tgl_get_bw_info(display, dram_info, &tgl_sa_info);
>> +		tgl_get_bw_info(display, dram_info, soc_bw_params, &tgl_sa_info);
>>  	} else if (DISPLAY_VER(display) == 11) {
>> -		icl_get_bw_info(display, dram_info, &icl_sa_info);
>> +		icl_get_bw_info(display, dram_info, soc_bw_params, &icl_sa_info);
>>  	}
>>  }
>>  
>> 
>> -- 
>> 2.53.0
>> 

-- 
Jani Nikula, Intel

Re: [PATCH v2 1/4] drm/i915/bw: Extract platform-specific parameters

[Gustavo Sousa]

Jani Nikula <jani.nikula@intel.com> writes:

> On Mon, 11 May 2026, Matt Roper <matthew.d.roper@intel.com> wrote:
>> On Mon, May 11, 2026 at 01:30:56PM -0300, Gustavo Sousa wrote:
>>> We got confirmation from the hardware team that the bandwidth parameters
>>> deprogbwlimit and derating are platform-specific and not tied to the
>>> display IP.  As such, let's make sure that we use platform checks for
>>> those.
>>> 
>>> The rest of the members of struct intel_sa_info are tied to the display
>>> IP and we will deal with them as a follow-up.
>>> 
>>> v2:
>>>   - Use good old if-ladder instead of weird-looking pattern "assign ret,
>>>     check platform, then return ret". (Jani, Matt)
>>>   - Have a single call site for get_platform_bw_params() and pass the
>>>     result as parameter to the *_get_bw_info() functions. (Jani)
>>>   - Avoid using "plat" as abbreviation for "platform". (Jani)
>>>   - s/_plat_bw_params/_bw_params/, since all of the instances are
>>>     prefixed with platform names. (Jani)
>>>   - s/struct intel_platform_bw_params/struct intel_soc_bw_params/.
>>>     (Matt)
>>>   - Do not return a default value; prefer to return NULL and
>>>     intentionally cause a NULL pointer dereference if a platform is
>>>     missing. (Gustavo)
>>> 
>>> Cc: Jani Nikula <jani.nikula@intel.com>
>>> Cc: Matt Roper <matthew.d.roper@intel.com>
>>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>>> ---
>>>  drivers/gpu/drm/i915/display/intel_bw.c | 161 ++++++++++++++++++++++----------
>>>  1 file changed, 113 insertions(+), 48 deletions(-)
>>> 
>>> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
>>> index 9c3a9bbb49f6..cf6756b8ae52 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_bw.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
>>> @@ -372,81 +372,147 @@ static int icl_sagv_max_dclk(const struct intel_qgv_info *qi)
>>>  	return dclk;
>>>  }
>>>  
>>> +struct intel_soc_bw_params {
>>> +	u8 deprogbwlimit;
>>> +	u8 derating;
>>> +};
>>> +
>>> +static const struct intel_soc_bw_params icl_bw_params = {
>>> +	.deprogbwlimit = 25,
>>> +	.derating = 10,
>>> +};
>>> +
>>> +static const struct intel_soc_bw_params tgl_bw_params = {
>>> +	.deprogbwlimit = 34,
>>> +	.derating = 10,
>>> +};
>>> +
>>> +static const struct intel_soc_bw_params rkl_bw_params = {
>>> +	.deprogbwlimit = 20,
>>> +	.derating = 10,
>>> +};
>>> +
>>> +static const struct intel_soc_bw_params adl_s_bw_params = {
>>> +	.deprogbwlimit = 38,
>>> +	.derating = 10,
>>> +};
>>> +
>>> +static const struct intel_soc_bw_params adl_p_bw_params = {
>>> +	.deprogbwlimit = 38,
>>> +	.derating = 20,
>>> +};
>>> +
>>> +static const struct intel_soc_bw_params bmg_bw_params = {
>>> +	.deprogbwlimit = 53,
>>> +	.derating = 30,
>>> +};
>>> +
>>> +static const struct intel_soc_bw_params bmg_ecc_bw_params = {
>>> +	.deprogbwlimit = 53,
>>> +	.derating = 45,
>>> +};
>>> +
>>> +static const struct intel_soc_bw_params ptl_bw_params = {
>>> +	.deprogbwlimit = 65,
>>> +	.derating = 10,
>>> +};
>>> +
>>> +static const struct intel_soc_bw_params wcl_bw_params = {
>>> +	.deprogbwlimit = 22,
>>> +	.derating = 10,
>>> +};
>>> +
>>> +static const struct intel_soc_bw_params *get_soc_bw_params(struct intel_display *display)
>>> +{
>>> +	if (display->platform.dgfx) {
>>> +		if (display->platform.dg1) {
>>> +			return &tgl_bw_params;
>>> +		} else if (display->platform.battlemage) {
>>> +			const struct dram_info *dram_info = intel_dram_info(display);
>>> +
>>> +			if (dram_info->type == INTEL_DRAM_GDDR_ECC)
>>> +				return &bmg_ecc_bw_params;
>>> +			else
>>> +				return &bmg_bw_params;
>>> +		}
>>> +	} else {
>>> +		if (display->platform.icelake ||
>>> +		    display->platform.jasperlake ||
>>> +		    display->platform.elkhartlake) {
>>> +			return &icl_bw_params;
>>> +		} else if (display->platform.tigerlake) {
>>> +			return &tgl_bw_params;
>>> +		} else if (display->platform.rocketlake) {
>>> +			return &rkl_bw_params;
>>> +		} else if (display->platform.alderlake_s) {
>>> +			return &adl_s_bw_params;
>>> +		} else if (display->platform.alderlake_p) {
>>> +			return &adl_p_bw_params;
>>> +		} else if (display->platform.meteorlake ||
>>> +			   display->platform.lunarlake) {
>>> +			return &adl_s_bw_params;
>>
>> Any reason not to combine this with the ADL-S branch of the if/else
>> ladder?
>>
>>> +		} else if (display->platform.pantherlake ||
>>> +			   display->platform.novalake) {
>>> +			if (display->platform.pantherlake_wildcatlake)
>>> +				return &wcl_bw_params;
>>
>> Can we just flatten this out rather than nesting?
>>
>>         } else if (display->platform.pantherlake_wildcatlake) {
>>                 return &wcl_bw_params;
>>         } else if (display->platform.pantherlake ||
>>                    display->platform.novalake) {
>>                 return &ptl_bw_params;
>>         }
>>
>>
>>> +			else
>>> +				return &ptl_bw_params;
>>> +		}
>>> +	}
>>> +
>>> +	drm_WARN(display->drm, 1, "Platform-specific bandwidth parameters not found!\n");
>>
>> I think 
>>
>>   i915_driver_hw_probe -> intel_bw_init_hw -> get_soc_bw_params
>>
>> is called unconditionally on all platforms for i915, not just the recent
>> ones where we started caring about memory bandwidth, so I'm not sure if
>> this WARN is appropriate since we'll always hit it on the pre-gen11
>> stuff.
>>
>> Since the values populated here only get used when paired with display
>> IP version 11 or later, we should probably add that as a condition since
>> those are the only cases where it matters that we found a set of SoC
>> parameters.
>
> In general, we should stop calling low level display init functions from
> i915 core code. Can we move the init call to some display init function?

I guess we could try to move the calls to intel_dram_detect() and
intel_bw_init_hw() into intel_display_driver_probe_noirq()?

--
Gustavo Sousa

>
> That said, it'll still get called on all sorts of platforms.
>
> BR,
> Jani.
>
>
>>
>>
>> Matt
>>
>>> +
>>> +	return NULL;
>>> +}
>>> +
>>>  struct intel_sa_info {
>>>  	u16 displayrtids;
>>> -	u8 deburst, deprogbwlimit, derating;
>>> +	u8 deburst;
>>>  };
>>>  
>>>  static const struct intel_sa_info icl_sa_info = {
>>>  	.deburst = 8,
>>> -	.deprogbwlimit = 25, /* GB/s */
>>>  	.displayrtids = 128,
>>> -	.derating = 10,
>>>  };
>>>  
>>>  static const struct intel_sa_info tgl_sa_info = {
>>>  	.deburst = 16,
>>> -	.deprogbwlimit = 34, /* GB/s */
>>>  	.displayrtids = 256,
>>> -	.derating = 10,
>>>  };
>>>  
>>>  static const struct intel_sa_info rkl_sa_info = {
>>>  	.deburst = 8,
>>> -	.deprogbwlimit = 20, /* GB/s */
>>>  	.displayrtids = 128,
>>> -	.derating = 10,
>>>  };
>>>  
>>>  static const struct intel_sa_info adls_sa_info = {
>>>  	.deburst = 16,
>>> -	.deprogbwlimit = 38, /* GB/s */
>>>  	.displayrtids = 256,
>>> -	.derating = 10,
>>>  };
>>>  
>>>  static const struct intel_sa_info adlp_sa_info = {
>>>  	.deburst = 16,
>>> -	.deprogbwlimit = 38, /* GB/s */
>>>  	.displayrtids = 256,
>>> -	.derating = 20,
>>>  };
>>>  
>>>  static const struct intel_sa_info mtl_sa_info = {
>>>  	.deburst = 32,
>>> -	.deprogbwlimit = 38, /* GB/s */
>>>  	.displayrtids = 256,
>>> -	.derating = 10,
>>> -};
>>> -
>>> -static const struct intel_sa_info xe2_hpd_sa_info = {
>>> -	.derating = 30,
>>> -	.deprogbwlimit = 53,
>>> -	/* Other values not used by simplified algorithm */
>>> -};
>>> -
>>> -static const struct intel_sa_info xe2_hpd_ecc_sa_info = {
>>> -	.derating = 45,
>>> -	.deprogbwlimit = 53,
>>> -	/* Other values not used by simplified algorithm */
>>>  };
>>>  
>>>  static const struct intel_sa_info xe3lpd_sa_info = {
>>>  	.deburst = 32,
>>> -	.deprogbwlimit = 65, /* GB/s */
>>>  	.displayrtids = 256,
>>> -	.derating = 10,
>>>  };
>>>  
>>>  static const struct intel_sa_info xe3lpd_3002_sa_info = {
>>>  	.deburst = 32,
>>> -	.deprogbwlimit = 22, /* GB/s */
>>>  	.displayrtids = 256,
>>> -	.derating = 10,
>>>  };
>>>  
>>>  static int icl_get_bw_info(struct intel_display *display,
>>>  			   const struct dram_info *dram_info,
>>> +			   const struct intel_soc_bw_params *soc_bw_params,
>>>  			   const struct intel_sa_info *sa)
>>>  {
>>>  	struct intel_qgv_info qi = {};
>>> @@ -466,7 +532,7 @@ static int icl_get_bw_info(struct intel_display *display,
>>>  	}
>>>  
>>>  	dclk_max = icl_sagv_max_dclk(&qi);
>>> -	maxdebw = min(sa->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
>>> +	maxdebw = min(soc_bw_params->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
>>>  	ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
>>>  	qi.deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
>>>  
>>> @@ -496,7 +562,7 @@ static int icl_get_bw_info(struct intel_display *display,
>>>  			bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct);
>>>  
>>>  			bi->deratedbw[j] = min(maxdebw,
>>> -					       bw * (100 - sa->derating) / 100);
>>> +					       bw * (100 - soc_bw_params->derating) / 100);
>>>  
>>>  			drm_dbg_kms(display->drm,
>>>  				    "BW%d / QGV %d: num_planes=%d deratedbw=%u\n",
>>> @@ -518,6 +584,7 @@ static int icl_get_bw_info(struct intel_display *display,
>>>  
>>>  static int tgl_get_bw_info(struct intel_display *display,
>>>  			   const struct dram_info *dram_info,
>>> +			   const struct intel_soc_bw_params *soc_bw_params,
>>>  			   const struct intel_sa_info *sa)
>>>  {
>>>  	struct intel_qgv_info qi = {};
>>> @@ -554,7 +621,7 @@ static int tgl_get_bw_info(struct intel_display *display,
>>>  	dclk_max = icl_sagv_max_dclk(&qi);
>>>  
>>>  	peakbw = num_channels * DIV_ROUND_UP(qi.channel_width, 8) * dclk_max;
>>> -	maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100);
>>> +	maxdebw = min(soc_bw_params->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100);
>>>  
>>>  	ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
>>>  	/*
>>> @@ -599,7 +666,7 @@ static int tgl_get_bw_info(struct intel_display *display,
>>>  			bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct);
>>>  
>>>  			bi->deratedbw[j] = min(maxdebw,
>>> -					       bw * (100 - sa->derating) / 100);
>>> +					       bw * (100 - soc_bw_params->derating) / 100);
>>>  			bi->peakbw[j] = DIV_ROUND_CLOSEST(sp->dclk *
>>>  							  num_channels *
>>>  							  qi.channel_width, 8);
>>> @@ -661,7 +728,7 @@ static void dg2_get_bw_info(struct intel_display *display)
>>>  
>>>  static int xe2_hpd_get_bw_info(struct intel_display *display,
>>>  			       const struct dram_info *dram_info,
>>> -			       const struct intel_sa_info *sa)
>>> +			       const struct intel_soc_bw_params *soc_bw_params)
>>>  {
>>>  	struct intel_qgv_info qi = {};
>>>  	int num_channels = dram_info->num_channels;
>>> @@ -676,14 +743,14 @@ static int xe2_hpd_get_bw_info(struct intel_display *display,
>>>  	}
>>>  
>>>  	peakbw = num_channels * qi.channel_width / 8 * icl_sagv_max_dclk(&qi);
>>> -	maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 10);
>>> +	maxdebw = min(soc_bw_params->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 10);
>>>  
>>>  	for (i = 0; i < qi.num_points; i++) {
>>>  		const struct intel_qgv_point *point = &qi.points[i];
>>>  		int bw = num_channels * (qi.channel_width / 8) * point->dclk;
>>>  
>>>  		display->bw.max[0].deratedbw[i] =
>>> -			min(maxdebw, (100 - sa->derating) * bw / 100);
>>> +			min(maxdebw, (100 - soc_bw_params->derating) * bw / 100);
>>>  		display->bw.max[0].peakbw[i] = bw;
>>>  
>>>  		drm_dbg_kms(display->drm, "QGV %d: deratedbw=%u peakbw: %u\n",
>>> @@ -792,6 +859,7 @@ static unsigned int icl_qgv_bw(struct intel_display *display,
>>>  void intel_bw_init_hw(struct intel_display *display)
>>>  {
>>>  	const struct dram_info *dram_info = intel_dram_info(display);
>>> +	const struct intel_soc_bw_params *soc_bw_params = get_soc_bw_params(display);
>>>  
>>>  	if (!HAS_DISPLAY(display))
>>>  		return;
>>> @@ -807,28 +875,25 @@ void intel_bw_init_hw(struct intel_display *display)
>>>  
>>>  	if (DISPLAY_VER(display) >= 30) {
>>>  		if (DISPLAY_VERx100(display) == 3002)
>>> -			tgl_get_bw_info(display, dram_info, &xe3lpd_3002_sa_info);
>>> +			tgl_get_bw_info(display, dram_info, soc_bw_params, &xe3lpd_3002_sa_info);
>>>  		else
>>> -			tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);
>>> +			tgl_get_bw_info(display, dram_info, soc_bw_params, &xe3lpd_sa_info);
>>>  	} else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
>>> -		if (dram_info->type == INTEL_DRAM_GDDR_ECC)
>>> -			xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_ecc_sa_info);
>>> -		else
>>> -			xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_sa_info);
>>> +		xe2_hpd_get_bw_info(display, dram_info, soc_bw_params);
>>>  	} else if (DISPLAY_VER(display) >= 14) {
>>> -		tgl_get_bw_info(display, dram_info, &mtl_sa_info);
>>> +		tgl_get_bw_info(display, dram_info, soc_bw_params, &mtl_sa_info);
>>>  	} else if (display->platform.dg2) {
>>>  		dg2_get_bw_info(display);
>>>  	} else if (display->platform.alderlake_p) {
>>> -		tgl_get_bw_info(display, dram_info, &adlp_sa_info);
>>> +		tgl_get_bw_info(display, dram_info, soc_bw_params, &adlp_sa_info);
>>>  	} else if (display->platform.alderlake_s) {
>>> -		tgl_get_bw_info(display, dram_info, &adls_sa_info);
>>> +		tgl_get_bw_info(display, dram_info, soc_bw_params, &adls_sa_info);
>>>  	} else if (display->platform.rocketlake) {
>>> -		tgl_get_bw_info(display, dram_info, &rkl_sa_info);
>>> +		tgl_get_bw_info(display, dram_info, soc_bw_params, &rkl_sa_info);
>>>  	} else if (DISPLAY_VER(display) == 12) {
>>> -		tgl_get_bw_info(display, dram_info, &tgl_sa_info);
>>> +		tgl_get_bw_info(display, dram_info, soc_bw_params, &tgl_sa_info);
>>>  	} else if (DISPLAY_VER(display) == 11) {
>>> -		icl_get_bw_info(display, dram_info, &icl_sa_info);
>>> +		icl_get_bw_info(display, dram_info, soc_bw_params, &icl_sa_info);
>>>  	}
>>>  }
>>>  
>>> 
>>> -- 
>>> 2.53.0
>>> 
>
> -- 
> Jani Nikula, Intel

Re: [PATCH v2 1/4] drm/i915/bw: Extract platform-specific parameters

[Gustavo Sousa]

Matt Roper <matthew.d.roper@intel.com> writes:

> On Mon, May 11, 2026 at 01:30:56PM -0300, Gustavo Sousa wrote:
>> We got confirmation from the hardware team that the bandwidth parameters
>> deprogbwlimit and derating are platform-specific and not tied to the
>> display IP.  As such, let's make sure that we use platform checks for
>> those.
>> 
>> The rest of the members of struct intel_sa_info are tied to the display
>> IP and we will deal with them as a follow-up.
>> 
>> v2:
>>   - Use good old if-ladder instead of weird-looking pattern "assign ret,
>>     check platform, then return ret". (Jani, Matt)
>>   - Have a single call site for get_platform_bw_params() and pass the
>>     result as parameter to the *_get_bw_info() functions. (Jani)
>>   - Avoid using "plat" as abbreviation for "platform". (Jani)
>>   - s/_plat_bw_params/_bw_params/, since all of the instances are
>>     prefixed with platform names. (Jani)
>>   - s/struct intel_platform_bw_params/struct intel_soc_bw_params/.
>>     (Matt)
>>   - Do not return a default value; prefer to return NULL and
>>     intentionally cause a NULL pointer dereference if a platform is
>>     missing. (Gustavo)
>> 
>> Cc: Jani Nikula <jani.nikula@intel.com>
>> Cc: Matt Roper <matthew.d.roper@intel.com>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_bw.c | 161 ++++++++++++++++++++++----------
>>  1 file changed, 113 insertions(+), 48 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
>> index 9c3a9bbb49f6..cf6756b8ae52 100644
>> --- a/drivers/gpu/drm/i915/display/intel_bw.c
>> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
>> @@ -372,81 +372,147 @@ static int icl_sagv_max_dclk(const struct intel_qgv_info *qi)
>>  	return dclk;
>>  }
>>  
>> +struct intel_soc_bw_params {
>> +	u8 deprogbwlimit;
>> +	u8 derating;
>> +};
>> +
>> +static const struct intel_soc_bw_params icl_bw_params = {
>> +	.deprogbwlimit = 25,
>> +	.derating = 10,
>> +};
>> +
>> +static const struct intel_soc_bw_params tgl_bw_params = {
>> +	.deprogbwlimit = 34,
>> +	.derating = 10,
>> +};
>> +
>> +static const struct intel_soc_bw_params rkl_bw_params = {
>> +	.deprogbwlimit = 20,
>> +	.derating = 10,
>> +};
>> +
>> +static const struct intel_soc_bw_params adl_s_bw_params = {
>> +	.deprogbwlimit = 38,
>> +	.derating = 10,
>> +};
>> +
>> +static const struct intel_soc_bw_params adl_p_bw_params = {
>> +	.deprogbwlimit = 38,
>> +	.derating = 20,
>> +};
>> +
>> +static const struct intel_soc_bw_params bmg_bw_params = {
>> +	.deprogbwlimit = 53,
>> +	.derating = 30,
>> +};
>> +
>> +static const struct intel_soc_bw_params bmg_ecc_bw_params = {
>> +	.deprogbwlimit = 53,
>> +	.derating = 45,
>> +};
>> +
>> +static const struct intel_soc_bw_params ptl_bw_params = {
>> +	.deprogbwlimit = 65,
>> +	.derating = 10,
>> +};
>> +
>> +static const struct intel_soc_bw_params wcl_bw_params = {
>> +	.deprogbwlimit = 22,
>> +	.derating = 10,
>> +};
>> +
>> +static const struct intel_soc_bw_params *get_soc_bw_params(struct intel_display *display)
>> +{
>> +	if (display->platform.dgfx) {
>> +		if (display->platform.dg1) {
>> +			return &tgl_bw_params;
>> +		} else if (display->platform.battlemage) {
>> +			const struct dram_info *dram_info = intel_dram_info(display);
>> +
>> +			if (dram_info->type == INTEL_DRAM_GDDR_ECC)
>> +				return &bmg_ecc_bw_params;
>> +			else
>> +				return &bmg_bw_params;
>> +		}
>> +	} else {
>> +		if (display->platform.icelake ||
>> +		    display->platform.jasperlake ||
>> +		    display->platform.elkhartlake) {
>> +			return &icl_bw_params;
>> +		} else if (display->platform.tigerlake) {
>> +			return &tgl_bw_params;
>> +		} else if (display->platform.rocketlake) {
>> +			return &rkl_bw_params;
>> +		} else if (display->platform.alderlake_s) {
>> +			return &adl_s_bw_params;
>> +		} else if (display->platform.alderlake_p) {
>> +			return &adl_p_bw_params;
>> +		} else if (display->platform.meteorlake ||
>> +			   display->platform.lunarlake) {
>> +			return &adl_s_bw_params;
>
> Any reason not to combine this with the ADL-S branch of the if/else
> ladder?

I was trying to follow platforms in chronological order (not sure if I
got it completely right, though).  But, yeah, maybe just better to group
by bw params instances -- differently from IP version checks, there
isn't much benefit in sorting by platforms anyway, at least not in this
case.

>
>> +		} else if (display->platform.pantherlake ||
>> +			   display->platform.novalake) {
>> +			if (display->platform.pantherlake_wildcatlake)
>> +				return &wcl_bw_params;
>
> Can we just flatten this out rather than nesting?
>
>         } else if (display->platform.pantherlake_wildcatlake) {
>                 return &wcl_bw_params;
>         } else if (display->platform.pantherlake ||
>                    display->platform.novalake) {
>                 return &ptl_bw_params;
>         }

We can.

>
>
>> +			else
>> +				return &ptl_bw_params;
>> +		}
>> +	}
>> +
>> +	drm_WARN(display->drm, 1, "Platform-specific bandwidth parameters not found!\n");
>
> I think 
>
>   i915_driver_hw_probe -> intel_bw_init_hw -> get_soc_bw_params
>
> is called unconditionally on all platforms for i915, not just the recent
> ones where we started caring about memory bandwidth, so I'm not sure if
> this WARN is appropriate since we'll always hit it on the pre-gen11
> stuff.

Yep. My bad: I totally missed that this will end up getting called for
pre-gen11; and CI results made that very clear! :-)

>
> Since the values populated here only get used when paired with display
> IP version 11 or later, we should probably add that as a condition since
> those are the only cases where it matters that we found a set of SoC
> parameters.

Maybe we should just bail out from intel_bw_init_hw() if display version
is less than 11? I think that's probably cleaner and we can keep the
current get_soc_bw_params() as is.

Thoughts?

--
Gustavo Sousa

>
>
> Matt
>
>> +
>> +	return NULL;
>> +}
>> +
>>  struct intel_sa_info {
>>  	u16 displayrtids;
>> -	u8 deburst, deprogbwlimit, derating;
>> +	u8 deburst;
>>  };
>>  
>>  static const struct intel_sa_info icl_sa_info = {
>>  	.deburst = 8,
>> -	.deprogbwlimit = 25, /* GB/s */
>>  	.displayrtids = 128,
>> -	.derating = 10,
>>  };
>>  
>>  static const struct intel_sa_info tgl_sa_info = {
>>  	.deburst = 16,
>> -	.deprogbwlimit = 34, /* GB/s */
>>  	.displayrtids = 256,
>> -	.derating = 10,
>>  };
>>  
>>  static const struct intel_sa_info rkl_sa_info = {
>>  	.deburst = 8,
>> -	.deprogbwlimit = 20, /* GB/s */
>>  	.displayrtids = 128,
>> -	.derating = 10,
>>  };
>>  
>>  static const struct intel_sa_info adls_sa_info = {
>>  	.deburst = 16,
>> -	.deprogbwlimit = 38, /* GB/s */
>>  	.displayrtids = 256,
>> -	.derating = 10,
>>  };
>>  
>>  static const struct intel_sa_info adlp_sa_info = {
>>  	.deburst = 16,
>> -	.deprogbwlimit = 38, /* GB/s */
>>  	.displayrtids = 256,
>> -	.derating = 20,
>>  };
>>  
>>  static const struct intel_sa_info mtl_sa_info = {
>>  	.deburst = 32,
>> -	.deprogbwlimit = 38, /* GB/s */
>>  	.displayrtids = 256,
>> -	.derating = 10,
>> -};
>> -
>> -static const struct intel_sa_info xe2_hpd_sa_info = {
>> -	.derating = 30,
>> -	.deprogbwlimit = 53,
>> -	/* Other values not used by simplified algorithm */
>> -};
>> -
>> -static const struct intel_sa_info xe2_hpd_ecc_sa_info = {
>> -	.derating = 45,
>> -	.deprogbwlimit = 53,
>> -	/* Other values not used by simplified algorithm */
>>  };
>>  
>>  static const struct intel_sa_info xe3lpd_sa_info = {
>>  	.deburst = 32,
>> -	.deprogbwlimit = 65, /* GB/s */
>>  	.displayrtids = 256,
>> -	.derating = 10,
>>  };
>>  
>>  static const struct intel_sa_info xe3lpd_3002_sa_info = {
>>  	.deburst = 32,
>> -	.deprogbwlimit = 22, /* GB/s */
>>  	.displayrtids = 256,
>> -	.derating = 10,
>>  };
>>  
>>  static int icl_get_bw_info(struct intel_display *display,
>>  			   const struct dram_info *dram_info,
>> +			   const struct intel_soc_bw_params *soc_bw_params,
>>  			   const struct intel_sa_info *sa)
>>  {
>>  	struct intel_qgv_info qi = {};
>> @@ -466,7 +532,7 @@ static int icl_get_bw_info(struct intel_display *display,
>>  	}
>>  
>>  	dclk_max = icl_sagv_max_dclk(&qi);
>> -	maxdebw = min(sa->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
>> +	maxdebw = min(soc_bw_params->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
>>  	ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
>>  	qi.deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
>>  
>> @@ -496,7 +562,7 @@ static int icl_get_bw_info(struct intel_display *display,
>>  			bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct);
>>  
>>  			bi->deratedbw[j] = min(maxdebw,
>> -					       bw * (100 - sa->derating) / 100);
>> +					       bw * (100 - soc_bw_params->derating) / 100);
>>  
>>  			drm_dbg_kms(display->drm,
>>  				    "BW%d / QGV %d: num_planes=%d deratedbw=%u\n",
>> @@ -518,6 +584,7 @@ static int icl_get_bw_info(struct intel_display *display,
>>  
>>  static int tgl_get_bw_info(struct intel_display *display,
>>  			   const struct dram_info *dram_info,
>> +			   const struct intel_soc_bw_params *soc_bw_params,
>>  			   const struct intel_sa_info *sa)
>>  {
>>  	struct intel_qgv_info qi = {};
>> @@ -554,7 +621,7 @@ static int tgl_get_bw_info(struct intel_display *display,
>>  	dclk_max = icl_sagv_max_dclk(&qi);
>>  
>>  	peakbw = num_channels * DIV_ROUND_UP(qi.channel_width, 8) * dclk_max;
>> -	maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100);
>> +	maxdebw = min(soc_bw_params->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100);
>>  
>>  	ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
>>  	/*
>> @@ -599,7 +666,7 @@ static int tgl_get_bw_info(struct intel_display *display,
>>  			bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct);
>>  
>>  			bi->deratedbw[j] = min(maxdebw,
>> -					       bw * (100 - sa->derating) / 100);
>> +					       bw * (100 - soc_bw_params->derating) / 100);
>>  			bi->peakbw[j] = DIV_ROUND_CLOSEST(sp->dclk *
>>  							  num_channels *
>>  							  qi.channel_width, 8);
>> @@ -661,7 +728,7 @@ static void dg2_get_bw_info(struct intel_display *display)
>>  
>>  static int xe2_hpd_get_bw_info(struct intel_display *display,
>>  			       const struct dram_info *dram_info,
>> -			       const struct intel_sa_info *sa)
>> +			       const struct intel_soc_bw_params *soc_bw_params)
>>  {
>>  	struct intel_qgv_info qi = {};
>>  	int num_channels = dram_info->num_channels;
>> @@ -676,14 +743,14 @@ static int xe2_hpd_get_bw_info(struct intel_display *display,
>>  	}
>>  
>>  	peakbw = num_channels * qi.channel_width / 8 * icl_sagv_max_dclk(&qi);
>> -	maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 10);
>> +	maxdebw = min(soc_bw_params->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 10);
>>  
>>  	for (i = 0; i < qi.num_points; i++) {
>>  		const struct intel_qgv_point *point = &qi.points[i];
>>  		int bw = num_channels * (qi.channel_width / 8) * point->dclk;
>>  
>>  		display->bw.max[0].deratedbw[i] =
>> -			min(maxdebw, (100 - sa->derating) * bw / 100);
>> +			min(maxdebw, (100 - soc_bw_params->derating) * bw / 100);
>>  		display->bw.max[0].peakbw[i] = bw;
>>  
>>  		drm_dbg_kms(display->drm, "QGV %d: deratedbw=%u peakbw: %u\n",
>> @@ -792,6 +859,7 @@ static unsigned int icl_qgv_bw(struct intel_display *display,
>>  void intel_bw_init_hw(struct intel_display *display)
>>  {
>>  	const struct dram_info *dram_info = intel_dram_info(display);
>> +	const struct intel_soc_bw_params *soc_bw_params = get_soc_bw_params(display);
>>  
>>  	if (!HAS_DISPLAY(display))
>>  		return;
>> @@ -807,28 +875,25 @@ void intel_bw_init_hw(struct intel_display *display)
>>  
>>  	if (DISPLAY_VER(display) >= 30) {
>>  		if (DISPLAY_VERx100(display) == 3002)
>> -			tgl_get_bw_info(display, dram_info, &xe3lpd_3002_sa_info);
>> +			tgl_get_bw_info(display, dram_info, soc_bw_params, &xe3lpd_3002_sa_info);
>>  		else
>> -			tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);
>> +			tgl_get_bw_info(display, dram_info, soc_bw_params, &xe3lpd_sa_info);
>>  	} else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
>> -		if (dram_info->type == INTEL_DRAM_GDDR_ECC)
>> -			xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_ecc_sa_info);
>> -		else
>> -			xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_sa_info);
>> +		xe2_hpd_get_bw_info(display, dram_info, soc_bw_params);
>>  	} else if (DISPLAY_VER(display) >= 14) {
>> -		tgl_get_bw_info(display, dram_info, &mtl_sa_info);
>> +		tgl_get_bw_info(display, dram_info, soc_bw_params, &mtl_sa_info);
>>  	} else if (display->platform.dg2) {
>>  		dg2_get_bw_info(display);
>>  	} else if (display->platform.alderlake_p) {
>> -		tgl_get_bw_info(display, dram_info, &adlp_sa_info);
>> +		tgl_get_bw_info(display, dram_info, soc_bw_params, &adlp_sa_info);
>>  	} else if (display->platform.alderlake_s) {
>> -		tgl_get_bw_info(display, dram_info, &adls_sa_info);
>> +		tgl_get_bw_info(display, dram_info, soc_bw_params, &adls_sa_info);
>>  	} else if (display->platform.rocketlake) {
>> -		tgl_get_bw_info(display, dram_info, &rkl_sa_info);
>> +		tgl_get_bw_info(display, dram_info, soc_bw_params, &rkl_sa_info);
>>  	} else if (DISPLAY_VER(display) == 12) {
>> -		tgl_get_bw_info(display, dram_info, &tgl_sa_info);
>> +		tgl_get_bw_info(display, dram_info, soc_bw_params, &tgl_sa_info);
>>  	} else if (DISPLAY_VER(display) == 11) {
>> -		icl_get_bw_info(display, dram_info, &icl_sa_info);
>> +		icl_get_bw_info(display, dram_info, soc_bw_params, &icl_sa_info);
>>  	}
>>  }
>>  
>> 
>> -- 
>> 2.53.0
>> 
>
> -- 
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation

[PATCH v2 2/4] drm/i915/bw: Deduplicate intel_sa_info instances

[Gustavo Sousa]

Now that intel_sa_info contains bandwidth parameters specific to the
display IP, we can drop many duplicates and reuse from previous
releases.

Let's do that and also simplify intel_bw_init_hw() while at it.

v2:
  - Drop rkl_sa_info and reuse icl_sa_info. (Matt)
  - Add comment explaining RKL's display's peculiarity on using ICL's
    parameters. (Matt)
  - Don't rename xelpdp_sa_info to mtl_sa_info.  Renaming of instances
    to use IP names will be done in upcoming changes.

Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 51 ++++++++-------------------------
 1 file changed, 12 insertions(+), 39 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index cf6756b8ae52..2e580c1a3fab 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -480,36 +480,11 @@ static const struct intel_sa_info tgl_sa_info = {
 	.displayrtids = 256,
 };
 
-static const struct intel_sa_info rkl_sa_info = {
-	.deburst = 8,
-	.displayrtids = 128,
-};
-
-static const struct intel_sa_info adls_sa_info = {
-	.deburst = 16,
-	.displayrtids = 256,
-};
-
-static const struct intel_sa_info adlp_sa_info = {
-	.deburst = 16,
-	.displayrtids = 256,
-};
-
 static const struct intel_sa_info mtl_sa_info = {
 	.deburst = 32,
 	.displayrtids = 256,
 };
 
-static const struct intel_sa_info xe3lpd_sa_info = {
-	.deburst = 32,
-	.displayrtids = 256,
-};
-
-static const struct intel_sa_info xe3lpd_3002_sa_info = {
-	.deburst = 32,
-	.displayrtids = 256,
-};
-
 static int icl_get_bw_info(struct intel_display *display,
 			   const struct dram_info *dram_info,
 			   const struct intel_soc_bw_params *soc_bw_params,
@@ -873,25 +848,23 @@ void intel_bw_init_hw(struct intel_display *display)
 	if (DISPLAY_VER(display) >= 35)
 		drm_WARN_ON(display->drm, dram_info->ecc_impacting_de_bw);
 
-	if (DISPLAY_VER(display) >= 30) {
-		if (DISPLAY_VERx100(display) == 3002)
-			tgl_get_bw_info(display, dram_info, soc_bw_params, &xe3lpd_3002_sa_info);
-		else
-			tgl_get_bw_info(display, dram_info, soc_bw_params, &xe3lpd_sa_info);
-	} else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
+	if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
 		xe2_hpd_get_bw_info(display, dram_info, soc_bw_params);
 	} else if (DISPLAY_VER(display) >= 14) {
 		tgl_get_bw_info(display, dram_info, soc_bw_params, &mtl_sa_info);
 	} else if (display->platform.dg2) {
 		dg2_get_bw_info(display);
-	} else if (display->platform.alderlake_p) {
-		tgl_get_bw_info(display, dram_info, soc_bw_params, &adlp_sa_info);
-	} else if (display->platform.alderlake_s) {
-		tgl_get_bw_info(display, dram_info, soc_bw_params, &adls_sa_info);
-	} else if (display->platform.rocketlake) {
-		tgl_get_bw_info(display, dram_info, soc_bw_params, &rkl_sa_info);
-	} else if (DISPLAY_VER(display) == 12) {
-		tgl_get_bw_info(display, dram_info, soc_bw_params, &tgl_sa_info);
+	} else if (DISPLAY_VER(display) >= 12) {
+		/*
+		 * RKL's SoC was based on ICL and the display, even though being
+		 * gen12, had changes to the memory interface to match gen11's,
+		 * consequently inheriting gen11's display-specific bandwidth
+		 * parameters.
+		 */
+		if (display->platform.rocketlake)
+			tgl_get_bw_info(display, dram_info, soc_bw_params, &icl_sa_info);
+		else
+			tgl_get_bw_info(display, dram_info, soc_bw_params, &tgl_sa_info);
 	} else if (DISPLAY_VER(display) == 11) {
 		icl_get_bw_info(display, dram_info, soc_bw_params, &icl_sa_info);
 	}

-- 
2.53.0

Re: [PATCH v2 2/4] drm/i915/bw: Deduplicate intel_sa_info instances

[Matt Roper]

On Mon, May 11, 2026 at 01:30:57PM -0300, Gustavo Sousa wrote:
> Now that intel_sa_info contains bandwidth parameters specific to the
> display IP, we can drop many duplicates and reuse from previous
> releases.
> 
> Let's do that and also simplify intel_bw_init_hw() while at it.
> 
> v2:
>   - Drop rkl_sa_info and reuse icl_sa_info. (Matt)
>   - Add comment explaining RKL's display's peculiarity on using ICL's
>     parameters. (Matt)
>   - Don't rename xelpdp_sa_info to mtl_sa_info.  Renaming of instances
>     to use IP names will be done in upcoming changes.
> 
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_bw.c | 51 ++++++++-------------------------
>  1 file changed, 12 insertions(+), 39 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index cf6756b8ae52..2e580c1a3fab 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -480,36 +480,11 @@ static const struct intel_sa_info tgl_sa_info = {
>  	.displayrtids = 256,
>  };
>  
> -static const struct intel_sa_info rkl_sa_info = {
> -	.deburst = 8,
> -	.displayrtids = 128,
> -};
> -
> -static const struct intel_sa_info adls_sa_info = {
> -	.deburst = 16,
> -	.displayrtids = 256,
> -};
> -
> -static const struct intel_sa_info adlp_sa_info = {
> -	.deburst = 16,
> -	.displayrtids = 256,
> -};
> -
>  static const struct intel_sa_info mtl_sa_info = {
>  	.deburst = 32,
>  	.displayrtids = 256,
>  };
>  
> -static const struct intel_sa_info xe3lpd_sa_info = {
> -	.deburst = 32,
> -	.displayrtids = 256,
> -};
> -
> -static const struct intel_sa_info xe3lpd_3002_sa_info = {
> -	.deburst = 32,
> -	.displayrtids = 256,
> -};
> -
>  static int icl_get_bw_info(struct intel_display *display,
>  			   const struct dram_info *dram_info,
>  			   const struct intel_soc_bw_params *soc_bw_params,
> @@ -873,25 +848,23 @@ void intel_bw_init_hw(struct intel_display *display)
>  	if (DISPLAY_VER(display) >= 35)
>  		drm_WARN_ON(display->drm, dram_info->ecc_impacting_de_bw);
>  
> -	if (DISPLAY_VER(display) >= 30) {
> -		if (DISPLAY_VERx100(display) == 3002)
> -			tgl_get_bw_info(display, dram_info, soc_bw_params, &xe3lpd_3002_sa_info);
> -		else
> -			tgl_get_bw_info(display, dram_info, soc_bw_params, &xe3lpd_sa_info);
> -	} else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
> +	if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
>  		xe2_hpd_get_bw_info(display, dram_info, soc_bw_params);
>  	} else if (DISPLAY_VER(display) >= 14) {
>  		tgl_get_bw_info(display, dram_info, soc_bw_params, &mtl_sa_info);
>  	} else if (display->platform.dg2) {
>  		dg2_get_bw_info(display);
> -	} else if (display->platform.alderlake_p) {
> -		tgl_get_bw_info(display, dram_info, soc_bw_params, &adlp_sa_info);
> -	} else if (display->platform.alderlake_s) {
> -		tgl_get_bw_info(display, dram_info, soc_bw_params, &adls_sa_info);
> -	} else if (display->platform.rocketlake) {
> -		tgl_get_bw_info(display, dram_info, soc_bw_params, &rkl_sa_info);
> -	} else if (DISPLAY_VER(display) == 12) {
> -		tgl_get_bw_info(display, dram_info, soc_bw_params, &tgl_sa_info);
> +	} else if (DISPLAY_VER(display) >= 12) {
> +		/*
> +		 * RKL's SoC was based on ICL and the display, even though being
> +		 * gen12, had changes to the memory interface to match gen11's,
> +		 * consequently inheriting gen11's display-specific bandwidth
> +		 * parameters.
> +		 */
> +		if (display->platform.rocketlake)
> +			tgl_get_bw_info(display, dram_info, soc_bw_params, &icl_sa_info);
> +		else
> +			tgl_get_bw_info(display, dram_info, soc_bw_params, &tgl_sa_info);
>  	} else if (DISPLAY_VER(display) == 11) {
>  		icl_get_bw_info(display, dram_info, soc_bw_params, &icl_sa_info);
>  	}
> 
> -- 
> 2.53.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

[PATCH v2 3/4] drm/i915/bw: Rename struct intel_sa_info to intel_display_bw_params

[Gustavo Sousa]

To align with struct intel_platform_bw_params, rename struct
intel_sa_info to intel_display_bw_params.  Also add comments to contrast
their purposes.

v2:
  - Use gen11 and gen12 as prefixes for ICL's and TGL's display-specific
    parameters variables. (Matt)
  - Prefer to use "display" instead of "disp" in variable names. (Jani)
  - Drop the redundant "disp" from the variable names.

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 36 ++++++++++++++++++++-------------
 1 file changed, 22 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 2e580c1a3fab..c01356d38e64 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -372,6 +372,10 @@ static int icl_sagv_max_dclk(const struct intel_qgv_info *qi)
 	return dclk;
 }
 
+/*
+ * Bandwidth parameters that are tied to the SoC (as opposed to struct
+ * intel_display_bw_params).
+ */
 struct intel_soc_bw_params {
 	u8 deprogbwlimit;
 	u8 derating;
@@ -465,22 +469,26 @@ static const struct intel_soc_bw_params *get_soc_bw_params(struct intel_display
 	return NULL;
 }
 
-struct intel_sa_info {
+/*
+ * Bandwidth parameters that are tied to the display IP (as opposed to struct
+ * intel_soc_bw_params).
+ */
+struct intel_display_bw_params {
 	u16 displayrtids;
 	u8 deburst;
 };
 
-static const struct intel_sa_info icl_sa_info = {
+static const struct intel_display_bw_params gen11_bw_params = {
 	.deburst = 8,
 	.displayrtids = 128,
 };
 
-static const struct intel_sa_info tgl_sa_info = {
+static const struct intel_display_bw_params gen12_bw_params = {
 	.deburst = 16,
 	.displayrtids = 256,
 };
 
-static const struct intel_sa_info mtl_sa_info = {
+static const struct intel_display_bw_params xelpdp_bw_params = {
 	.deburst = 32,
 	.displayrtids = 256,
 };
@@ -488,7 +496,7 @@ static const struct intel_sa_info mtl_sa_info = {
 static int icl_get_bw_info(struct intel_display *display,
 			   const struct dram_info *dram_info,
 			   const struct intel_soc_bw_params *soc_bw_params,
-			   const struct intel_sa_info *sa)
+			   const struct intel_display_bw_params *display_bw_params)
 {
 	struct intel_qgv_info qi = {};
 	bool is_y_tile = true; /* assume y tile may be used */
@@ -508,7 +516,7 @@ static int icl_get_bw_info(struct intel_display *display,
 
 	dclk_max = icl_sagv_max_dclk(&qi);
 	maxdebw = min(soc_bw_params->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
-	ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
+	ipqdepth = min(ipqdepthpch, display_bw_params->displayrtids / num_channels);
 	qi.deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
 
 	for (i = 0; i < num_groups; i++) {
@@ -516,7 +524,7 @@ static int icl_get_bw_info(struct intel_display *display,
 		int clpchgroup;
 		int j;
 
-		clpchgroup = (sa->deburst * qi.deinterleave / num_channels) << i;
+		clpchgroup = (display_bw_params->deburst * qi.deinterleave / num_channels) << i;
 		bi->num_planes = (ipqdepth - clpchgroup) / clpchgroup + 1;
 
 		bi->num_qgv_points = qi.num_points;
@@ -560,7 +568,7 @@ static int icl_get_bw_info(struct intel_display *display,
 static int tgl_get_bw_info(struct intel_display *display,
 			   const struct dram_info *dram_info,
 			   const struct intel_soc_bw_params *soc_bw_params,
-			   const struct intel_sa_info *sa)
+			   const struct intel_display_bw_params *display_bw_params)
 {
 	struct intel_qgv_info qi = {};
 	bool is_y_tile = true; /* assume y tile may be used */
@@ -598,7 +606,7 @@ static int tgl_get_bw_info(struct intel_display *display,
 	peakbw = num_channels * DIV_ROUND_UP(qi.channel_width, 8) * dclk_max;
 	maxdebw = min(soc_bw_params->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100);
 
-	ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
+	ipqdepth = min(ipqdepthpch, display_bw_params->displayrtids / num_channels);
 	/*
 	 * clperchgroup = 4kpagespermempage * clperchperblock,
 	 * clperchperblock = 8 / num_channels * interleave
@@ -611,7 +619,7 @@ static int tgl_get_bw_info(struct intel_display *display,
 		int clpchgroup;
 		int j;
 
-		clpchgroup = (sa->deburst * qi.deinterleave / num_channels) << i;
+		clpchgroup = (display_bw_params->deburst * qi.deinterleave / num_channels) << i;
 
 		if (i < num_groups - 1) {
 			bi_next = &display->bw.max[i + 1];
@@ -851,7 +859,7 @@ void intel_bw_init_hw(struct intel_display *display)
 	if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
 		xe2_hpd_get_bw_info(display, dram_info, soc_bw_params);
 	} else if (DISPLAY_VER(display) >= 14) {
-		tgl_get_bw_info(display, dram_info, soc_bw_params, &mtl_sa_info);
+		tgl_get_bw_info(display, dram_info, soc_bw_params, &xelpdp_bw_params);
 	} else if (display->platform.dg2) {
 		dg2_get_bw_info(display);
 	} else if (DISPLAY_VER(display) >= 12) {
@@ -862,11 +870,11 @@ void intel_bw_init_hw(struct intel_display *display)
 		 * parameters.
 		 */
 		if (display->platform.rocketlake)
-			tgl_get_bw_info(display, dram_info, soc_bw_params, &icl_sa_info);
+			tgl_get_bw_info(display, dram_info, soc_bw_params, &gen11_bw_params);
 		else
-			tgl_get_bw_info(display, dram_info, soc_bw_params, &tgl_sa_info);
+			tgl_get_bw_info(display, dram_info, soc_bw_params, &gen12_bw_params);
 	} else if (DISPLAY_VER(display) == 11) {
-		icl_get_bw_info(display, dram_info, soc_bw_params, &icl_sa_info);
+		icl_get_bw_info(display, dram_info, soc_bw_params, &gen11_bw_params);
 	}
 }
 

-- 
2.53.0

Re: [PATCH v2 3/4] drm/i915/bw: Rename struct intel_sa_info to intel_display_bw_params

[Matt Roper]

On Mon, May 11, 2026 at 01:30:58PM -0300, Gustavo Sousa wrote:
> To align with struct intel_platform_bw_params, rename struct
> intel_sa_info to intel_display_bw_params.  Also add comments to contrast
> their purposes.
> 
> v2:
>   - Use gen11 and gen12 as prefixes for ICL's and TGL's display-specific
>     parameters variables. (Matt)
>   - Prefer to use "display" instead of "disp" in variable names. (Jani)
>   - Drop the redundant "disp" from the variable names.
> 
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_bw.c | 36 ++++++++++++++++++++-------------
>  1 file changed, 22 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 2e580c1a3fab..c01356d38e64 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -372,6 +372,10 @@ static int icl_sagv_max_dclk(const struct intel_qgv_info *qi)
>  	return dclk;
>  }
>  
> +/*
> + * Bandwidth parameters that are tied to the SoC (as opposed to struct
> + * intel_display_bw_params).
> + */
>  struct intel_soc_bw_params {
>  	u8 deprogbwlimit;
>  	u8 derating;
> @@ -465,22 +469,26 @@ static const struct intel_soc_bw_params *get_soc_bw_params(struct intel_display
>  	return NULL;
>  }
>  
> -struct intel_sa_info {
> +/*
> + * Bandwidth parameters that are tied to the display IP (as opposed to struct
> + * intel_soc_bw_params).
> + */
> +struct intel_display_bw_params {
>  	u16 displayrtids;
>  	u8 deburst;
>  };
>  
> -static const struct intel_sa_info icl_sa_info = {
> +static const struct intel_display_bw_params gen11_bw_params = {
>  	.deburst = 8,
>  	.displayrtids = 128,
>  };
>  
> -static const struct intel_sa_info tgl_sa_info = {
> +static const struct intel_display_bw_params gen12_bw_params = {
>  	.deburst = 16,
>  	.displayrtids = 256,
>  };
>  
> -static const struct intel_sa_info mtl_sa_info = {
> +static const struct intel_display_bw_params xelpdp_bw_params = {
>  	.deburst = 32,
>  	.displayrtids = 256,
>  };
> @@ -488,7 +496,7 @@ static const struct intel_sa_info mtl_sa_info = {
>  static int icl_get_bw_info(struct intel_display *display,
>  			   const struct dram_info *dram_info,
>  			   const struct intel_soc_bw_params *soc_bw_params,
> -			   const struct intel_sa_info *sa)
> +			   const struct intel_display_bw_params *display_bw_params)
>  {
>  	struct intel_qgv_info qi = {};
>  	bool is_y_tile = true; /* assume y tile may be used */
> @@ -508,7 +516,7 @@ static int icl_get_bw_info(struct intel_display *display,
>  
>  	dclk_max = icl_sagv_max_dclk(&qi);
>  	maxdebw = min(soc_bw_params->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
> -	ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
> +	ipqdepth = min(ipqdepthpch, display_bw_params->displayrtids / num_channels);
>  	qi.deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
>  
>  	for (i = 0; i < num_groups; i++) {
> @@ -516,7 +524,7 @@ static int icl_get_bw_info(struct intel_display *display,
>  		int clpchgroup;
>  		int j;
>  
> -		clpchgroup = (sa->deburst * qi.deinterleave / num_channels) << i;
> +		clpchgroup = (display_bw_params->deburst * qi.deinterleave / num_channels) << i;
>  		bi->num_planes = (ipqdepth - clpchgroup) / clpchgroup + 1;
>  
>  		bi->num_qgv_points = qi.num_points;
> @@ -560,7 +568,7 @@ static int icl_get_bw_info(struct intel_display *display,
>  static int tgl_get_bw_info(struct intel_display *display,
>  			   const struct dram_info *dram_info,
>  			   const struct intel_soc_bw_params *soc_bw_params,
> -			   const struct intel_sa_info *sa)
> +			   const struct intel_display_bw_params *display_bw_params)
>  {
>  	struct intel_qgv_info qi = {};
>  	bool is_y_tile = true; /* assume y tile may be used */
> @@ -598,7 +606,7 @@ static int tgl_get_bw_info(struct intel_display *display,
>  	peakbw = num_channels * DIV_ROUND_UP(qi.channel_width, 8) * dclk_max;
>  	maxdebw = min(soc_bw_params->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100);
>  
> -	ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
> +	ipqdepth = min(ipqdepthpch, display_bw_params->displayrtids / num_channels);
>  	/*
>  	 * clperchgroup = 4kpagespermempage * clperchperblock,
>  	 * clperchperblock = 8 / num_channels * interleave
> @@ -611,7 +619,7 @@ static int tgl_get_bw_info(struct intel_display *display,
>  		int clpchgroup;
>  		int j;
>  
> -		clpchgroup = (sa->deburst * qi.deinterleave / num_channels) << i;
> +		clpchgroup = (display_bw_params->deburst * qi.deinterleave / num_channels) << i;
>  
>  		if (i < num_groups - 1) {
>  			bi_next = &display->bw.max[i + 1];
> @@ -851,7 +859,7 @@ void intel_bw_init_hw(struct intel_display *display)
>  	if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
>  		xe2_hpd_get_bw_info(display, dram_info, soc_bw_params);
>  	} else if (DISPLAY_VER(display) >= 14) {
> -		tgl_get_bw_info(display, dram_info, soc_bw_params, &mtl_sa_info);
> +		tgl_get_bw_info(display, dram_info, soc_bw_params, &xelpdp_bw_params);
>  	} else if (display->platform.dg2) {
>  		dg2_get_bw_info(display);
>  	} else if (DISPLAY_VER(display) >= 12) {
> @@ -862,11 +870,11 @@ void intel_bw_init_hw(struct intel_display *display)
>  		 * parameters.
>  		 */
>  		if (display->platform.rocketlake)
> -			tgl_get_bw_info(display, dram_info, soc_bw_params, &icl_sa_info);
> +			tgl_get_bw_info(display, dram_info, soc_bw_params, &gen11_bw_params);
>  		else
> -			tgl_get_bw_info(display, dram_info, soc_bw_params, &tgl_sa_info);
> +			tgl_get_bw_info(display, dram_info, soc_bw_params, &gen12_bw_params);
>  	} else if (DISPLAY_VER(display) == 11) {
> -		icl_get_bw_info(display, dram_info, soc_bw_params, &icl_sa_info);
> +		icl_get_bw_info(display, dram_info, soc_bw_params, &gen11_bw_params);
>  	}
>  }
>  
> 
> -- 
> 2.53.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

[PATCH v2 4/4] drm/i915/bw: Extract get_display_bw_params()

[Gustavo Sousa]

Just like it is done for the platform-specific bandwidth parameters, use
a separate function named get_display_bw_params() to return the display
IP-specific parameters.  This simplifies intel_bw_init_hw() by having
just one call for each of the *_get_bw_info() functions.

v2:
  - Prefer to call get_display_bw_params() only once in
    intel_bw_init_hw() instead of having multiple calls in each of the
    affected *_get_bw_info() functions. (Jani)

Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 36 +++++++++++++++++++++------------
 1 file changed, 23 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index c01356d38e64..acd1b6901b46 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -493,6 +493,26 @@ static const struct intel_display_bw_params xelpdp_bw_params = {
 	.displayrtids = 256,
 };
 
+static const struct intel_display_bw_params *get_display_bw_params(struct intel_display *display)
+{
+	if (DISPLAY_VER(display) >= 14) {
+		return &xelpdp_bw_params;
+	} else if (DISPLAY_VER(display) >= 12) {
+		/*
+		 * RKL's SoC was based on ICL and the display, even though being
+		 * gen12, had changes to the memory interface to match gen11's,
+		 * consequently inheriting gen11's display-specific bandwidth
+		 * parameters.
+		 */
+		if (display->platform.rocketlake)
+			return &gen11_bw_params;
+		else
+			return &gen12_bw_params;
+	} else {
+		return &gen11_bw_params;
+	}
+}
+
 static int icl_get_bw_info(struct intel_display *display,
 			   const struct dram_info *dram_info,
 			   const struct intel_soc_bw_params *soc_bw_params,
@@ -843,6 +863,7 @@ void intel_bw_init_hw(struct intel_display *display)
 {
 	const struct dram_info *dram_info = intel_dram_info(display);
 	const struct intel_soc_bw_params *soc_bw_params = get_soc_bw_params(display);
+	const struct intel_display_bw_params *display_bw_params = get_display_bw_params(display);
 
 	if (!HAS_DISPLAY(display))
 		return;
@@ -858,23 +879,12 @@ void intel_bw_init_hw(struct intel_display *display)
 
 	if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
 		xe2_hpd_get_bw_info(display, dram_info, soc_bw_params);
-	} else if (DISPLAY_VER(display) >= 14) {
-		tgl_get_bw_info(display, dram_info, soc_bw_params, &xelpdp_bw_params);
 	} else if (display->platform.dg2) {
 		dg2_get_bw_info(display);
 	} else if (DISPLAY_VER(display) >= 12) {
-		/*
-		 * RKL's SoC was based on ICL and the display, even though being
-		 * gen12, had changes to the memory interface to match gen11's,
-		 * consequently inheriting gen11's display-specific bandwidth
-		 * parameters.
-		 */
-		if (display->platform.rocketlake)
-			tgl_get_bw_info(display, dram_info, soc_bw_params, &gen11_bw_params);
-		else
-			tgl_get_bw_info(display, dram_info, soc_bw_params, &gen12_bw_params);
+		tgl_get_bw_info(display, dram_info, soc_bw_params, display_bw_params);
 	} else if (DISPLAY_VER(display) == 11) {
-		icl_get_bw_info(display, dram_info, soc_bw_params, &gen11_bw_params);
+		icl_get_bw_info(display, dram_info, soc_bw_params, display_bw_params);
 	}
 }
 

-- 
2.53.0

Re: [PATCH v2 4/4] drm/i915/bw: Extract get_display_bw_params()

[Matt Roper]

On Mon, May 11, 2026 at 01:30:59PM -0300, Gustavo Sousa wrote:
> Just like it is done for the platform-specific bandwidth parameters, use
> a separate function named get_display_bw_params() to return the display
> IP-specific parameters.  This simplifies intel_bw_init_hw() by having
> just one call for each of the *_get_bw_info() functions.
> 
> v2:
>   - Prefer to call get_display_bw_params() only once in
>     intel_bw_init_hw() instead of having multiple calls in each of the
>     affected *_get_bw_info() functions. (Jani)
> 
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_bw.c | 36 +++++++++++++++++++++------------
>  1 file changed, 23 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index c01356d38e64..acd1b6901b46 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -493,6 +493,26 @@ static const struct intel_display_bw_params xelpdp_bw_params = {
>  	.displayrtids = 256,
>  };
>  
> +static const struct intel_display_bw_params *get_display_bw_params(struct intel_display *display)
> +{
> +	if (DISPLAY_VER(display) >= 14) {
> +		return &xelpdp_bw_params;
> +	} else if (DISPLAY_VER(display) >= 12) {
> +		/*
> +		 * RKL's SoC was based on ICL and the display, even though being
> +		 * gen12, had changes to the memory interface to match gen11's,
> +		 * consequently inheriting gen11's display-specific bandwidth
> +		 * parameters.
> +		 */
> +		if (display->platform.rocketlake)
> +			return &gen11_bw_params;
> +		else
> +			return &gen12_bw_params;
> +	} else {
> +		return &gen11_bw_params;

It doesn't really matter, but this is technically going to assign gen11
parameters for all the pre-gen11 platforms that call through here on
i915.  If we never use the values it probably doesn't hurt anything, but
it might be best to make this a condition on gen11 rather than an 'else'
just to avoid any confusion.


Matt

> +	}
> +}
> +
>  static int icl_get_bw_info(struct intel_display *display,
>  			   const struct dram_info *dram_info,
>  			   const struct intel_soc_bw_params *soc_bw_params,
> @@ -843,6 +863,7 @@ void intel_bw_init_hw(struct intel_display *display)
>  {
>  	const struct dram_info *dram_info = intel_dram_info(display);
>  	const struct intel_soc_bw_params *soc_bw_params = get_soc_bw_params(display);
> +	const struct intel_display_bw_params *display_bw_params = get_display_bw_params(display);
>  
>  	if (!HAS_DISPLAY(display))
>  		return;
> @@ -858,23 +879,12 @@ void intel_bw_init_hw(struct intel_display *display)
>  
>  	if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
>  		xe2_hpd_get_bw_info(display, dram_info, soc_bw_params);
> -	} else if (DISPLAY_VER(display) >= 14) {
> -		tgl_get_bw_info(display, dram_info, soc_bw_params, &xelpdp_bw_params);
>  	} else if (display->platform.dg2) {
>  		dg2_get_bw_info(display);
>  	} else if (DISPLAY_VER(display) >= 12) {
> -		/*
> -		 * RKL's SoC was based on ICL and the display, even though being
> -		 * gen12, had changes to the memory interface to match gen11's,
> -		 * consequently inheriting gen11's display-specific bandwidth
> -		 * parameters.
> -		 */
> -		if (display->platform.rocketlake)
> -			tgl_get_bw_info(display, dram_info, soc_bw_params, &gen11_bw_params);
> -		else
> -			tgl_get_bw_info(display, dram_info, soc_bw_params, &gen12_bw_params);
> +		tgl_get_bw_info(display, dram_info, soc_bw_params, display_bw_params);
>  	} else if (DISPLAY_VER(display) == 11) {
> -		icl_get_bw_info(display, dram_info, soc_bw_params, &gen11_bw_params);
> +		icl_get_bw_info(display, dram_info, soc_bw_params, display_bw_params);
>  	}
>  }
>  
> 
> -- 
> 2.53.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH v2 4/4] drm/i915/bw: Extract get_display_bw_params()

[Jani Nikula]

On Mon, 11 May 2026, Matt Roper <matthew.d.roper@intel.com> wrote:
> On Mon, May 11, 2026 at 01:30:59PM -0300, Gustavo Sousa wrote:
>> Just like it is done for the platform-specific bandwidth parameters, use
>> a separate function named get_display_bw_params() to return the display
>> IP-specific parameters.  This simplifies intel_bw_init_hw() by having
>> just one call for each of the *_get_bw_info() functions.
>> 
>> v2:
>>   - Prefer to call get_display_bw_params() only once in
>>     intel_bw_init_hw() instead of having multiple calls in each of the
>>     affected *_get_bw_info() functions. (Jani)
>> 
>> Cc: Jani Nikula <jani.nikula@intel.com>
>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_bw.c | 36 +++++++++++++++++++++------------
>>  1 file changed, 23 insertions(+), 13 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
>> index c01356d38e64..acd1b6901b46 100644
>> --- a/drivers/gpu/drm/i915/display/intel_bw.c
>> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
>> @@ -493,6 +493,26 @@ static const struct intel_display_bw_params xelpdp_bw_params = {
>>  	.displayrtids = 256,
>>  };
>>  
>> +static const struct intel_display_bw_params *get_display_bw_params(struct intel_display *display)
>> +{
>> +	if (DISPLAY_VER(display) >= 14) {
>> +		return &xelpdp_bw_params;
>> +	} else if (DISPLAY_VER(display) >= 12) {
>> +		/*
>> +		 * RKL's SoC was based on ICL and the display, even though being
>> +		 * gen12, had changes to the memory interface to match gen11's,
>> +		 * consequently inheriting gen11's display-specific bandwidth
>> +		 * parameters.
>> +		 */
>> +		if (display->platform.rocketlake)
>> +			return &gen11_bw_params;
>> +		else
>> +			return &gen12_bw_params;
>> +	} else {
>> +		return &gen11_bw_params;
>
> It doesn't really matter, but this is technically going to assign gen11
> parameters for all the pre-gen11 platforms that call through here on
> i915.  If we never use the values it probably doesn't hurt anything, but
> it might be best to make this a condition on gen11 rather than an 'else'
> just to avoid any confusion.
>
>
> Matt
>
>> +	}
>> +}
>> +
>>  static int icl_get_bw_info(struct intel_display *display,
>>  			   const struct dram_info *dram_info,
>>  			   const struct intel_soc_bw_params *soc_bw_params,
>> @@ -843,6 +863,7 @@ void intel_bw_init_hw(struct intel_display *display)
>>  {
>>  	const struct dram_info *dram_info = intel_dram_info(display);
>>  	const struct intel_soc_bw_params *soc_bw_params = get_soc_bw_params(display);
>> +	const struct intel_display_bw_params *display_bw_params = get_display_bw_params(display);

Feels like it gets increasingly weird to call all these functions
unconditionally when we bail out for !display right below.

BR,
Jani.

>>  
>>  	if (!HAS_DISPLAY(display))
>>  		return;
>> @@ -858,23 +879,12 @@ void intel_bw_init_hw(struct intel_display *display)
>>  
>>  	if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
>>  		xe2_hpd_get_bw_info(display, dram_info, soc_bw_params);
>> -	} else if (DISPLAY_VER(display) >= 14) {
>> -		tgl_get_bw_info(display, dram_info, soc_bw_params, &xelpdp_bw_params);
>>  	} else if (display->platform.dg2) {
>>  		dg2_get_bw_info(display);
>>  	} else if (DISPLAY_VER(display) >= 12) {
>> -		/*
>> -		 * RKL's SoC was based on ICL and the display, even though being
>> -		 * gen12, had changes to the memory interface to match gen11's,
>> -		 * consequently inheriting gen11's display-specific bandwidth
>> -		 * parameters.
>> -		 */
>> -		if (display->platform.rocketlake)
>> -			tgl_get_bw_info(display, dram_info, soc_bw_params, &gen11_bw_params);
>> -		else
>> -			tgl_get_bw_info(display, dram_info, soc_bw_params, &gen12_bw_params);
>> +		tgl_get_bw_info(display, dram_info, soc_bw_params, display_bw_params);
>>  	} else if (DISPLAY_VER(display) == 11) {
>> -		icl_get_bw_info(display, dram_info, soc_bw_params, &gen11_bw_params);
>> +		icl_get_bw_info(display, dram_info, soc_bw_params, display_bw_params);
>>  	}
>>  }
>>  
>> 
>> -- 
>> 2.53.0
>> 

-- 
Jani Nikula, Intel

Re: [PATCH v2 4/4] drm/i915/bw: Extract get_display_bw_params()

[Gustavo Sousa]

Jani Nikula <jani.nikula@intel.com> writes:

> On Mon, 11 May 2026, Matt Roper <matthew.d.roper@intel.com> wrote:
>> On Mon, May 11, 2026 at 01:30:59PM -0300, Gustavo Sousa wrote:
>>> Just like it is done for the platform-specific bandwidth parameters, use
>>> a separate function named get_display_bw_params() to return the display
>>> IP-specific parameters.  This simplifies intel_bw_init_hw() by having
>>> just one call for each of the *_get_bw_info() functions.
>>> 
>>> v2:
>>>   - Prefer to call get_display_bw_params() only once in
>>>     intel_bw_init_hw() instead of having multiple calls in each of the
>>>     affected *_get_bw_info() functions. (Jani)
>>> 
>>> Cc: Jani Nikula <jani.nikula@intel.com>
>>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>>> ---
>>>  drivers/gpu/drm/i915/display/intel_bw.c | 36 +++++++++++++++++++++------------
>>>  1 file changed, 23 insertions(+), 13 deletions(-)
>>> 
>>> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
>>> index c01356d38e64..acd1b6901b46 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_bw.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
>>> @@ -493,6 +493,26 @@ static const struct intel_display_bw_params xelpdp_bw_params = {
>>>  	.displayrtids = 256,
>>>  };
>>>  
>>> +static const struct intel_display_bw_params *get_display_bw_params(struct intel_display *display)
>>> +{
>>> +	if (DISPLAY_VER(display) >= 14) {
>>> +		return &xelpdp_bw_params;
>>> +	} else if (DISPLAY_VER(display) >= 12) {
>>> +		/*
>>> +		 * RKL's SoC was based on ICL and the display, even though being
>>> +		 * gen12, had changes to the memory interface to match gen11's,
>>> +		 * consequently inheriting gen11's display-specific bandwidth
>>> +		 * parameters.
>>> +		 */
>>> +		if (display->platform.rocketlake)
>>> +			return &gen11_bw_params;
>>> +		else
>>> +			return &gen12_bw_params;
>>> +	} else {
>>> +		return &gen11_bw_params;
>>
>> It doesn't really matter, but this is technically going to assign gen11
>> parameters for all the pre-gen11 platforms that call through here on
>> i915.  If we never use the values it probably doesn't hurt anything, but
>> it might be best to make this a condition on gen11 rather than an 'else'
>> just to avoid any confusion.
>>
>>
>> Matt
>>
>>> +	}
>>> +}
>>> +
>>>  static int icl_get_bw_info(struct intel_display *display,
>>>  			   const struct dram_info *dram_info,
>>>  			   const struct intel_soc_bw_params *soc_bw_params,
>>> @@ -843,6 +863,7 @@ void intel_bw_init_hw(struct intel_display *display)
>>>  {
>>>  	const struct dram_info *dram_info = intel_dram_info(display);
>>>  	const struct intel_soc_bw_params *soc_bw_params = get_soc_bw_params(display);
>>> +	const struct intel_display_bw_params *display_bw_params = get_display_bw_params(display);
>
> Feels like it gets increasingly weird to call all these functions
> unconditionally when we bail out for !display right below.

Yeah.  Let's fix that. I'll have a separate patch for moving
intel_dram_info() down and then fix the two patches that add the other
calls.

--
Gustavo Sousa

>
> BR,
> Jani.
>
>>>  
>>>  	if (!HAS_DISPLAY(display))
>>>  		return;
>>> @@ -858,23 +879,12 @@ void intel_bw_init_hw(struct intel_display *display)
>>>  
>>>  	if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
>>>  		xe2_hpd_get_bw_info(display, dram_info, soc_bw_params);
>>> -	} else if (DISPLAY_VER(display) >= 14) {
>>> -		tgl_get_bw_info(display, dram_info, soc_bw_params, &xelpdp_bw_params);
>>>  	} else if (display->platform.dg2) {
>>>  		dg2_get_bw_info(display);
>>>  	} else if (DISPLAY_VER(display) >= 12) {
>>> -		/*
>>> -		 * RKL's SoC was based on ICL and the display, even though being
>>> -		 * gen12, had changes to the memory interface to match gen11's,
>>> -		 * consequently inheriting gen11's display-specific bandwidth
>>> -		 * parameters.
>>> -		 */
>>> -		if (display->platform.rocketlake)
>>> -			tgl_get_bw_info(display, dram_info, soc_bw_params, &gen11_bw_params);
>>> -		else
>>> -			tgl_get_bw_info(display, dram_info, soc_bw_params, &gen12_bw_params);
>>> +		tgl_get_bw_info(display, dram_info, soc_bw_params, display_bw_params);
>>>  	} else if (DISPLAY_VER(display) == 11) {
>>> -		icl_get_bw_info(display, dram_info, soc_bw_params, &gen11_bw_params);
>>> +		icl_get_bw_info(display, dram_info, soc_bw_params, display_bw_params);
>>>  	}
>>>  }
>>>  
>>> 
>>> -- 
>>> 2.53.0
>>> 
>
> -- 
> Jani Nikula, Intel

Re: [PATCH v2 4/4] drm/i915/bw: Extract get_display_bw_params()

[Gustavo Sousa]

Matt Roper <matthew.d.roper@intel.com> writes:

> On Mon, May 11, 2026 at 01:30:59PM -0300, Gustavo Sousa wrote:
>> Just like it is done for the platform-specific bandwidth parameters, use
>> a separate function named get_display_bw_params() to return the display
>> IP-specific parameters.  This simplifies intel_bw_init_hw() by having
>> just one call for each of the *_get_bw_info() functions.
>> 
>> v2:
>>   - Prefer to call get_display_bw_params() only once in
>>     intel_bw_init_hw() instead of having multiple calls in each of the
>>     affected *_get_bw_info() functions. (Jani)
>> 
>> Cc: Jani Nikula <jani.nikula@intel.com>
>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_bw.c | 36 +++++++++++++++++++++------------
>>  1 file changed, 23 insertions(+), 13 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
>> index c01356d38e64..acd1b6901b46 100644
>> --- a/drivers/gpu/drm/i915/display/intel_bw.c
>> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
>> @@ -493,6 +493,26 @@ static const struct intel_display_bw_params xelpdp_bw_params = {
>>  	.displayrtids = 256,
>>  };
>>  
>> +static const struct intel_display_bw_params *get_display_bw_params(struct intel_display *display)
>> +{
>> +	if (DISPLAY_VER(display) >= 14) {
>> +		return &xelpdp_bw_params;
>> +	} else if (DISPLAY_VER(display) >= 12) {
>> +		/*
>> +		 * RKL's SoC was based on ICL and the display, even though being
>> +		 * gen12, had changes to the memory interface to match gen11's,
>> +		 * consequently inheriting gen11's display-specific bandwidth
>> +		 * parameters.
>> +		 */
>> +		if (display->platform.rocketlake)
>> +			return &gen11_bw_params;
>> +		else
>> +			return &gen12_bw_params;
>> +	} else {
>> +		return &gen11_bw_params;
>
> It doesn't really matter, but this is technically going to assign gen11
> parameters for all the pre-gen11 platforms that call through here on
> i915.  If we never use the values it probably doesn't hurt anything, but
> it might be best to make this a condition on gen11 rather than an 'else'
> just to avoid any confusion.

Sounds good.  I'll add a check for display version == 11 and then take
the same approach as for get_soc_bw_params(), by returning NULL with a
warning.

--
Gustavo Sousa

>
>
> Matt
>
>> +	}
>> +}
>> +
>>  static int icl_get_bw_info(struct intel_display *display,
>>  			   const struct dram_info *dram_info,
>>  			   const struct intel_soc_bw_params *soc_bw_params,
>> @@ -843,6 +863,7 @@ void intel_bw_init_hw(struct intel_display *display)
>>  {
>>  	const struct dram_info *dram_info = intel_dram_info(display);
>>  	const struct intel_soc_bw_params *soc_bw_params = get_soc_bw_params(display);
>> +	const struct intel_display_bw_params *display_bw_params = get_display_bw_params(display);
>>  
>>  	if (!HAS_DISPLAY(display))
>>  		return;
>> @@ -858,23 +879,12 @@ void intel_bw_init_hw(struct intel_display *display)
>>  
>>  	if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
>>  		xe2_hpd_get_bw_info(display, dram_info, soc_bw_params);
>> -	} else if (DISPLAY_VER(display) >= 14) {
>> -		tgl_get_bw_info(display, dram_info, soc_bw_params, &xelpdp_bw_params);
>>  	} else if (display->platform.dg2) {
>>  		dg2_get_bw_info(display);
>>  	} else if (DISPLAY_VER(display) >= 12) {
>> -		/*
>> -		 * RKL's SoC was based on ICL and the display, even though being
>> -		 * gen12, had changes to the memory interface to match gen11's,
>> -		 * consequently inheriting gen11's display-specific bandwidth
>> -		 * parameters.
>> -		 */
>> -		if (display->platform.rocketlake)
>> -			tgl_get_bw_info(display, dram_info, soc_bw_params, &gen11_bw_params);
>> -		else
>> -			tgl_get_bw_info(display, dram_info, soc_bw_params, &gen12_bw_params);
>> +		tgl_get_bw_info(display, dram_info, soc_bw_params, display_bw_params);
>>  	} else if (DISPLAY_VER(display) == 11) {
>> -		icl_get_bw_info(display, dram_info, soc_bw_params, &gen11_bw_params);
>> +		icl_get_bw_info(display, dram_info, soc_bw_params, display_bw_params);
>>  	}
>>  }
>>  
>> 
>> -- 
>> 2.53.0
>> 
>
> -- 
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation

✓ CI.KUnit: success for drm/i915/bw: Split bandwidth params into platform- and display-IP-specific structs

[Patchwork]

== Series Details ==

Series: drm/i915/bw: Split bandwidth params into platform- and display-IP-specific structs
URL   : https://patchwork.freedesktop.org/series/166340/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[22:13:26] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[22:13:31] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[22:14:12] Starting KUnit Kernel (1/1)...
[22:14:12] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[22:14:12] ================== guc_buf (11 subtests) ===================
[22:14:12] [PASSED] test_smallest
[22:14:12] [PASSED] test_largest
[22:14:12] [PASSED] test_granular
[22:14:12] [PASSED] test_unique
[22:14:12] [PASSED] test_overlap
[22:14:12] [PASSED] test_reusable
[22:14:12] [PASSED] test_too_big
[22:14:12] [PASSED] test_flush
[22:14:12] [PASSED] test_lookup
[22:14:12] [PASSED] test_data
[22:14:12] [PASSED] test_class
[22:14:12] ===================== [PASSED] guc_buf =====================
[22:14:12] =================== guc_dbm (7 subtests) ===================
[22:14:12] [PASSED] test_empty
[22:14:12] [PASSED] test_default
[22:14:12] ======================== test_size  ========================
[22:14:12] [PASSED] 4
[22:14:12] [PASSED] 8
[22:14:12] [PASSED] 32
[22:14:12] [PASSED] 256
[22:14:12] ==================== [PASSED] test_size ====================
[22:14:12] ======================= test_reuse  ========================
[22:14:12] [PASSED] 4
[22:14:12] [PASSED] 8
[22:14:12] [PASSED] 32
[22:14:12] [PASSED] 256
[22:14:12] =================== [PASSED] test_reuse ====================
[22:14:12] =================== test_range_overlap  ====================
[22:14:12] [PASSED] 4
[22:14:12] [PASSED] 8
[22:14:12] [PASSED] 32
[22:14:12] [PASSED] 256
[22:14:12] =============== [PASSED] test_range_overlap ================
[22:14:12] =================== test_range_compact  ====================
[22:14:12] [PASSED] 4
[22:14:12] [PASSED] 8
[22:14:12] [PASSED] 32
[22:14:12] [PASSED] 256
[22:14:12] =============== [PASSED] test_range_compact ================
[22:14:12] ==================== test_range_spare  =====================
[22:14:12] [PASSED] 4
[22:14:12] [PASSED] 8
[22:14:12] [PASSED] 32
[22:14:12] [PASSED] 256
[22:14:12] ================ [PASSED] test_range_spare =================
[22:14:12] ===================== [PASSED] guc_dbm =====================
[22:14:12] =================== guc_idm (6 subtests) ===================
[22:14:12] [PASSED] bad_init
[22:14:12] [PASSED] no_init
[22:14:12] [PASSED] init_fini
[22:14:12] [PASSED] check_used
[22:14:12] [PASSED] check_quota
[22:14:12] [PASSED] check_all
[22:14:12] ===================== [PASSED] guc_idm =====================
[22:14:12] ================== no_relay (3 subtests) ===================
[22:14:12] [PASSED] xe_drops_guc2pf_if_not_ready
[22:14:12] [PASSED] xe_drops_guc2vf_if_not_ready
[22:14:12] [PASSED] xe_rejects_send_if_not_ready
[22:14:12] ==================== [PASSED] no_relay =====================
[22:14:12] ================== pf_relay (14 subtests) ==================
[22:14:12] [PASSED] pf_rejects_guc2pf_too_short
[22:14:12] [PASSED] pf_rejects_guc2pf_too_long
[22:14:12] [PASSED] pf_rejects_guc2pf_no_payload
[22:14:12] [PASSED] pf_fails_no_payload
[22:14:12] [PASSED] pf_fails_bad_origin
[22:14:12] [PASSED] pf_fails_bad_type
[22:14:12] [PASSED] pf_txn_reports_error
[22:14:12] [PASSED] pf_txn_sends_pf2guc
[22:14:12] [PASSED] pf_sends_pf2guc
[22:14:12] [SKIPPED] pf_loopback_nop
[22:14:12] [SKIPPED] pf_loopback_echo
[22:14:12] [SKIPPED] pf_loopback_fail
[22:14:12] [SKIPPED] pf_loopback_busy
[22:14:12] [SKIPPED] pf_loopback_retry
[22:14:12] ==================== [PASSED] pf_relay =====================
[22:14:12] ================== vf_relay (3 subtests) ===================
[22:14:12] [PASSED] vf_rejects_guc2vf_too_short
[22:14:12] [PASSED] vf_rejects_guc2vf_too_long
[22:14:12] [PASSED] vf_rejects_guc2vf_no_payload
[22:14:12] ==================== [PASSED] vf_relay =====================
[22:14:12] ================ pf_gt_config (9 subtests) =================
[22:14:12] [PASSED] fair_contexts_1vf
[22:14:12] [PASSED] fair_doorbells_1vf
[22:14:12] [PASSED] fair_ggtt_1vf
[22:14:12] ====================== fair_vram_1vf  ======================
[22:14:12] [PASSED] 3.50 GiB
[22:14:12] [PASSED] 11.5 GiB
[22:14:12] [PASSED] 15.5 GiB
[22:14:12] [PASSED] 31.5 GiB
[22:14:12] [PASSED] 63.5 GiB
[22:14:12] [PASSED] 1.91 GiB
[22:14:12] ================== [PASSED] fair_vram_1vf ==================
[22:14:12] ================ fair_vram_1vf_admin_only  =================
[22:14:12] [PASSED] 3.50 GiB
[22:14:12] [PASSED] 11.5 GiB
[22:14:12] [PASSED] 15.5 GiB
[22:14:12] [PASSED] 31.5 GiB
[22:14:12] [PASSED] 63.5 GiB
[22:14:12] [PASSED] 1.91 GiB
[22:14:12] ============ [PASSED] fair_vram_1vf_admin_only =============
[22:14:12] ====================== fair_contexts  ======================
[22:14:12] [PASSED] 1 VF
[22:14:13] [PASSED] 2 VFs
[22:14:13] [PASSED] 3 VFs
[22:14:13] [PASSED] 4 VFs
[22:14:13] [PASSED] 5 VFs
[22:14:13] [PASSED] 6 VFs
[22:14:13] [PASSED] 7 VFs
[22:14:13] [PASSED] 8 VFs
[22:14:13] [PASSED] 9 VFs
[22:14:13] [PASSED] 10 VFs
[22:14:13] [PASSED] 11 VFs
[22:14:13] [PASSED] 12 VFs
[22:14:13] [PASSED] 13 VFs
[22:14:13] [PASSED] 14 VFs
[22:14:13] [PASSED] 15 VFs
[22:14:13] [PASSED] 16 VFs
[22:14:13] [PASSED] 17 VFs
[22:14:13] [PASSED] 18 VFs
[22:14:13] [PASSED] 19 VFs
[22:14:13] [PASSED] 20 VFs
[22:14:13] [PASSED] 21 VFs
[22:14:13] [PASSED] 22 VFs
[22:14:13] [PASSED] 23 VFs
[22:14:13] [PASSED] 24 VFs
[22:14:13] [PASSED] 25 VFs
[22:14:13] [PASSED] 26 VFs
[22:14:13] [PASSED] 27 VFs
[22:14:13] [PASSED] 28 VFs
[22:14:13] [PASSED] 29 VFs
[22:14:13] [PASSED] 30 VFs
[22:14:13] [PASSED] 31 VFs
[22:14:13] [PASSED] 32 VFs
[22:14:13] [PASSED] 33 VFs
[22:14:13] [PASSED] 34 VFs
[22:14:13] [PASSED] 35 VFs
[22:14:13] [PASSED] 36 VFs
[22:14:13] [PASSED] 37 VFs
[22:14:13] [PASSED] 38 VFs
[22:14:13] [PASSED] 39 VFs
[22:14:13] [PASSED] 40 VFs
[22:14:13] [PASSED] 41 VFs
[22:14:13] [PASSED] 42 VFs
[22:14:13] [PASSED] 43 VFs
[22:14:13] [PASSED] 44 VFs
[22:14:13] [PASSED] 45 VFs
[22:14:13] [PASSED] 46 VFs
[22:14:13] [PASSED] 47 VFs
[22:14:13] [PASSED] 48 VFs
[22:14:13] [PASSED] 49 VFs
[22:14:13] [PASSED] 50 VFs
[22:14:13] [PASSED] 51 VFs
[22:14:13] [PASSED] 52 VFs
[22:14:13] [PASSED] 53 VFs
[22:14:13] [PASSED] 54 VFs
[22:14:13] [PASSED] 55 VFs
[22:14:13] [PASSED] 56 VFs
[22:14:13] [PASSED] 57 VFs
[22:14:13] [PASSED] 58 VFs
[22:14:13] [PASSED] 59 VFs
[22:14:13] [PASSED] 60 VFs
[22:14:13] [PASSED] 61 VFs
[22:14:13] [PASSED] 62 VFs
[22:14:13] [PASSED] 63 VFs
[22:14:13] ================== [PASSED] fair_contexts ==================
[22:14:13] ===================== fair_doorbells  ======================
[22:14:13] [PASSED] 1 VF
[22:14:13] [PASSED] 2 VFs
[22:14:13] [PASSED] 3 VFs
[22:14:13] [PASSED] 4 VFs
[22:14:13] [PASSED] 5 VFs
[22:14:13] [PASSED] 6 VFs
[22:14:13] [PASSED] 7 VFs
[22:14:13] [PASSED] 8 VFs
[22:14:13] [PASSED] 9 VFs
[22:14:13] [PASSED] 10 VFs
[22:14:13] [PASSED] 11 VFs
[22:14:13] [PASSED] 12 VFs
[22:14:13] [PASSED] 13 VFs
[22:14:13] [PASSED] 14 VFs
[22:14:13] [PASSED] 15 VFs
[22:14:13] [PASSED] 16 VFs
[22:14:13] [PASSED] 17 VFs
[22:14:13] [PASSED] 18 VFs
[22:14:13] [PASSED] 19 VFs
[22:14:13] [PASSED] 20 VFs
[22:14:13] [PASSED] 21 VFs
[22:14:13] [PASSED] 22 VFs
[22:14:13] [PASSED] 23 VFs
[22:14:13] [PASSED] 24 VFs
[22:14:13] [PASSED] 25 VFs
[22:14:13] [PASSED] 26 VFs
[22:14:13] [PASSED] 27 VFs
[22:14:13] [PASSED] 28 VFs
[22:14:13] [PASSED] 29 VFs
[22:14:13] [PASSED] 30 VFs
[22:14:13] [PASSED] 31 VFs
[22:14:13] [PASSED] 32 VFs
[22:14:13] [PASSED] 33 VFs
[22:14:13] [PASSED] 34 VFs
[22:14:13] [PASSED] 35 VFs
[22:14:13] [PASSED] 36 VFs
[22:14:13] [PASSED] 37 VFs
[22:14:13] [PASSED] 38 VFs
[22:14:13] [PASSED] 39 VFs
[22:14:13] [PASSED] 40 VFs
[22:14:13] [PASSED] 41 VFs
[22:14:13] [PASSED] 42 VFs
[22:14:13] [PASSED] 43 VFs
[22:14:13] [PASSED] 44 VFs
[22:14:13] [PASSED] 45 VFs
[22:14:13] [PASSED] 46 VFs
[22:14:13] [PASSED] 47 VFs
[22:14:13] [PASSED] 48 VFs
[22:14:13] [PASSED] 49 VFs
[22:14:13] [PASSED] 50 VFs
[22:14:13] [PASSED] 51 VFs
[22:14:13] [PASSED] 52 VFs
[22:14:13] [PASSED] 53 VFs
[22:14:13] [PASSED] 54 VFs
[22:14:13] [PASSED] 55 VFs
[22:14:13] [PASSED] 56 VFs
[22:14:13] [PASSED] 57 VFs
[22:14:13] [PASSED] 58 VFs
[22:14:13] [PASSED] 59 VFs
[22:14:13] [PASSED] 60 VFs
[22:14:13] [PASSED] 61 VFs
[22:14:13] [PASSED] 62 VFs
[22:14:13] [PASSED] 63 VFs
[22:14:13] ================= [PASSED] fair_doorbells ==================
[22:14:13] ======================== fair_ggtt  ========================
[22:14:13] [PASSED] 1 VF
[22:14:13] [PASSED] 2 VFs
[22:14:13] [PASSED] 3 VFs
[22:14:13] [PASSED] 4 VFs
[22:14:13] [PASSED] 5 VFs
[22:14:13] [PASSED] 6 VFs
[22:14:13] [PASSED] 7 VFs
[22:14:13] [PASSED] 8 VFs
[22:14:13] [PASSED] 9 VFs
[22:14:13] [PASSED] 10 VFs
[22:14:13] [PASSED] 11 VFs
[22:14:13] [PASSED] 12 VFs
[22:14:13] [PASSED] 13 VFs
[22:14:13] [PASSED] 14 VFs
[22:14:13] [PASSED] 15 VFs
[22:14:13] [PASSED] 16 VFs
[22:14:13] [PASSED] 17 VFs
[22:14:13] [PASSED] 18 VFs
[22:14:13] [PASSED] 19 VFs
[22:14:13] [PASSED] 20 VFs
[22:14:13] [PASSED] 21 VFs
[22:14:13] [PASSED] 22 VFs
[22:14:13] [PASSED] 23 VFs
[22:14:13] [PASSED] 24 VFs
[22:14:13] [PASSED] 25 VFs
[22:14:13] [PASSED] 26 VFs
[22:14:13] [PASSED] 27 VFs
[22:14:13] [PASSED] 28 VFs
[22:14:13] [PASSED] 29 VFs
[22:14:13] [PASSED] 30 VFs
[22:14:13] [PASSED] 31 VFs
[22:14:13] [PASSED] 32 VFs
[22:14:13] [PASSED] 33 VFs
[22:14:13] [PASSED] 34 VFs
[22:14:13] [PASSED] 35 VFs
[22:14:13] [PASSED] 36 VFs
[22:14:13] [PASSED] 37 VFs
[22:14:13] [PASSED] 38 VFs
[22:14:13] [PASSED] 39 VFs
[22:14:13] [PASSED] 40 VFs
[22:14:13] [PASSED] 41 VFs
[22:14:13] [PASSED] 42 VFs
[22:14:13] [PASSED] 43 VFs
[22:14:13] [PASSED] 44 VFs
[22:14:13] [PASSED] 45 VFs
[22:14:13] [PASSED] 46 VFs
[22:14:13] [PASSED] 47 VFs
[22:14:13] [PASSED] 48 VFs
[22:14:13] [PASSED] 49 VFs
[22:14:13] [PASSED] 50 VFs
[22:14:13] [PASSED] 51 VFs
[22:14:13] [PASSED] 52 VFs
[22:14:13] [PASSED] 53 VFs
[22:14:13] [PASSED] 54 VFs
[22:14:13] [PASSED] 55 VFs
[22:14:13] [PASSED] 56 VFs
[22:14:13] [PASSED] 57 VFs
[22:14:13] [PASSED] 58 VFs
[22:14:13] [PASSED] 59 VFs
[22:14:13] [PASSED] 60 VFs
[22:14:13] [PASSED] 61 VFs
[22:14:13] [PASSED] 62 VFs
[22:14:13] [PASSED] 63 VFs
[22:14:13] ==================== [PASSED] fair_ggtt ====================
[22:14:13] ======================== fair_vram  ========================
[22:14:13] [PASSED] 1 VF
[22:14:13] [PASSED] 2 VFs
[22:14:13] [PASSED] 3 VFs
[22:14:13] [PASSED] 4 VFs
[22:14:13] [PASSED] 5 VFs
[22:14:13] [PASSED] 6 VFs
[22:14:13] [PASSED] 7 VFs
[22:14:13] [PASSED] 8 VFs
[22:14:13] [PASSED] 9 VFs
[22:14:13] [PASSED] 10 VFs
[22:14:13] [PASSED] 11 VFs
[22:14:13] [PASSED] 12 VFs
[22:14:13] [PASSED] 13 VFs
[22:14:13] [PASSED] 14 VFs
[22:14:13] [PASSED] 15 VFs
[22:14:13] [PASSED] 16 VFs
[22:14:13] [PASSED] 17 VFs
[22:14:13] [PASSED] 18 VFs
[22:14:13] [PASSED] 19 VFs
[22:14:13] [PASSED] 20 VFs
[22:14:13] [PASSED] 21 VFs
[22:14:13] [PASSED] 22 VFs
[22:14:13] [PASSED] 23 VFs
[22:14:13] [PASSED] 24 VFs
[22:14:13] [PASSED] 25 VFs
[22:14:13] [PASSED] 26 VFs
[22:14:13] [PASSED] 27 VFs
[22:14:13] [PASSED] 28 VFs
[22:14:13] [PASSED] 29 VFs
[22:14:13] [PASSED] 30 VFs
[22:14:13] [PASSED] 31 VFs
[22:14:13] [PASSED] 32 VFs
[22:14:13] [PASSED] 33 VFs
[22:14:13] [PASSED] 34 VFs
[22:14:13] [PASSED] 35 VFs
[22:14:13] [PASSED] 36 VFs
[22:14:13] [PASSED] 37 VFs
[22:14:13] [PASSED] 38 VFs
[22:14:13] [PASSED] 39 VFs
[22:14:13] [PASSED] 40 VFs
[22:14:13] [PASSED] 41 VFs
[22:14:13] [PASSED] 42 VFs
[22:14:13] [PASSED] 43 VFs
[22:14:13] [PASSED] 44 VFs
[22:14:13] [PASSED] 45 VFs
[22:14:13] [PASSED] 46 VFs
[22:14:13] [PASSED] 47 VFs
[22:14:13] [PASSED] 48 VFs
[22:14:13] [PASSED] 49 VFs
[22:14:13] [PASSED] 50 VFs
[22:14:13] [PASSED] 51 VFs
[22:14:13] [PASSED] 52 VFs
[22:14:13] [PASSED] 53 VFs
[22:14:13] [PASSED] 54 VFs
[22:14:13] [PASSED] 55 VFs
[22:14:13] [PASSED] 56 VFs
[22:14:13] [PASSED] 57 VFs
[22:14:13] [PASSED] 58 VFs
[22:14:13] [PASSED] 59 VFs
[22:14:13] [PASSED] 60 VFs
[22:14:13] [PASSED] 61 VFs
[22:14:13] [PASSED] 62 VFs
[22:14:13] [PASSED] 63 VFs
[22:14:13] ==================== [PASSED] fair_vram ====================
[22:14:13] ================== [PASSED] pf_gt_config ===================
[22:14:13] ===================== lmtt (1 subtest) =====================
[22:14:13] ======================== test_ops  =========================
[22:14:13] [PASSED] 2-level
[22:14:13] [PASSED] multi-level
[22:14:13] ==================== [PASSED] test_ops =====================
[22:14:13] ====================== [PASSED] lmtt =======================
[22:14:13] ================= pf_service (11 subtests) =================
[22:14:13] [PASSED] pf_negotiate_any
[22:14:13] [PASSED] pf_negotiate_base_match
[22:14:13] [PASSED] pf_negotiate_base_newer
[22:14:13] [PASSED] pf_negotiate_base_next
[22:14:13] [SKIPPED] pf_negotiate_base_older
[22:14:13] [PASSED] pf_negotiate_base_prev
[22:14:13] [PASSED] pf_negotiate_latest_match
[22:14:13] [PASSED] pf_negotiate_latest_newer
[22:14:13] [PASSED] pf_negotiate_latest_next
[22:14:13] [SKIPPED] pf_negotiate_latest_older
[22:14:13] [SKIPPED] pf_negotiate_latest_prev
[22:14:13] =================== [PASSED] pf_service ====================
[22:14:13] ================= xe_guc_g2g (2 subtests) ==================
[22:14:13] ============== xe_live_guc_g2g_kunit_default  ==============
[22:14:13] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[22:14:13] ============== xe_live_guc_g2g_kunit_allmem  ===============
[22:14:13] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[22:14:13] =================== [SKIPPED] xe_guc_g2g ===================
[22:14:13] =================== xe_mocs (2 subtests) ===================
[22:14:13] ================ xe_live_mocs_kernel_kunit  ================
[22:14:13] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[22:14:13] ================ xe_live_mocs_reset_kunit  =================
[22:14:13] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[22:14:13] ==================== [SKIPPED] xe_mocs =====================
[22:14:13] ================= xe_migrate (2 subtests) ==================
[22:14:13] ================= xe_migrate_sanity_kunit  =================
[22:14:13] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[22:14:13] ================== xe_validate_ccs_kunit  ==================
[22:14:13] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[22:14:13] =================== [SKIPPED] xe_migrate ===================
[22:14:13] ================== xe_dma_buf (1 subtest) ==================
[22:14:13] ==================== xe_dma_buf_kunit  =====================
[22:14:13] ================ [SKIPPED] xe_dma_buf_kunit ================
[22:14:13] =================== [SKIPPED] xe_dma_buf ===================
[22:14:13] ================= xe_bo_shrink (1 subtest) =================
[22:14:13] =================== xe_bo_shrink_kunit  ====================
[22:14:13] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[22:14:13] ================== [SKIPPED] xe_bo_shrink ==================
[22:14:13] ==================== xe_bo (2 subtests) ====================
[22:14:13] ================== xe_ccs_migrate_kunit  ===================
[22:14:13] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[22:14:13] ==================== xe_bo_evict_kunit  ====================
[22:14:13] =============== [SKIPPED] xe_bo_evict_kunit ================
[22:14:13] ===================== [SKIPPED] xe_bo ======================
[22:14:13] ==================== args (13 subtests) ====================
[22:14:13] [PASSED] count_args_test
[22:14:13] [PASSED] call_args_example
[22:14:13] [PASSED] call_args_test
[22:14:13] [PASSED] drop_first_arg_example
[22:14:13] [PASSED] drop_first_arg_test
[22:14:13] [PASSED] first_arg_example
[22:14:13] [PASSED] first_arg_test
[22:14:13] [PASSED] last_arg_example
[22:14:13] [PASSED] last_arg_test
[22:14:13] [PASSED] pick_arg_example
[22:14:13] [PASSED] if_args_example
[22:14:13] [PASSED] if_args_test
[22:14:13] [PASSED] sep_comma_example
[22:14:13] ====================== [PASSED] args =======================
[22:14:13] =================== xe_pci (3 subtests) ====================
[22:14:13] ==================== check_graphics_ip  ====================
[22:14:13] [PASSED] 12.00 Xe_LP
[22:14:13] [PASSED] 12.10 Xe_LP+
[22:14:13] [PASSED] 12.55 Xe_HPG
[22:14:13] [PASSED] 12.60 Xe_HPC
[22:14:13] [PASSED] 12.70 Xe_LPG
[22:14:13] [PASSED] 12.71 Xe_LPG
[22:14:13] [PASSED] 12.74 Xe_LPG+
[22:14:13] [PASSED] 20.01 Xe2_HPG
[22:14:13] [PASSED] 20.02 Xe2_HPG
[22:14:13] [PASSED] 20.04 Xe2_LPG
[22:14:13] [PASSED] 30.00 Xe3_LPG
[22:14:13] [PASSED] 30.01 Xe3_LPG
[22:14:13] [PASSED] 30.03 Xe3_LPG
[22:14:13] [PASSED] 30.04 Xe3_LPG
[22:14:13] [PASSED] 30.05 Xe3_LPG
[22:14:13] [PASSED] 35.10 Xe3p_LPG
[22:14:13] [PASSED] 35.11 Xe3p_XPC
[22:14:13] ================ [PASSED] check_graphics_ip ================
[22:14:13] ===================== check_media_ip  ======================
[22:14:13] [PASSED] 12.00 Xe_M
[22:14:13] [PASSED] 12.55 Xe_HPM
[22:14:13] [PASSED] 13.00 Xe_LPM+
[22:14:13] [PASSED] 13.01 Xe2_HPM
[22:14:13] [PASSED] 20.00 Xe2_LPM
[22:14:13] [PASSED] 30.00 Xe3_LPM
[22:14:13] [PASSED] 30.02 Xe3_LPM
[22:14:13] [PASSED] 35.00 Xe3p_LPM
[22:14:13] [PASSED] 35.03 Xe3p_HPM
[22:14:13] ================= [PASSED] check_media_ip ==================
[22:14:13] =================== check_platform_desc  ===================
[22:14:13] [PASSED] 0x9A60 (TIGERLAKE)
[22:14:13] [PASSED] 0x9A68 (TIGERLAKE)
[22:14:13] [PASSED] 0x9A70 (TIGERLAKE)
[22:14:13] [PASSED] 0x9A40 (TIGERLAKE)
[22:14:13] [PASSED] 0x9A49 (TIGERLAKE)
[22:14:13] [PASSED] 0x9A59 (TIGERLAKE)
[22:14:13] [PASSED] 0x9A78 (TIGERLAKE)
[22:14:13] [PASSED] 0x9AC0 (TIGERLAKE)
[22:14:13] [PASSED] 0x9AC9 (TIGERLAKE)
[22:14:13] [PASSED] 0x9AD9 (TIGERLAKE)
[22:14:13] [PASSED] 0x9AF8 (TIGERLAKE)
[22:14:13] [PASSED] 0x4C80 (ROCKETLAKE)
[22:14:13] [PASSED] 0x4C8A (ROCKETLAKE)
[22:14:13] [PASSED] 0x4C8B (ROCKETLAKE)
[22:14:13] [PASSED] 0x4C8C (ROCKETLAKE)
[22:14:13] [PASSED] 0x4C90 (ROCKETLAKE)
[22:14:13] [PASSED] 0x4C9A (ROCKETLAKE)
[22:14:13] [PASSED] 0x4680 (ALDERLAKE_S)
[22:14:13] [PASSED] 0x4682 (ALDERLAKE_S)
[22:14:13] [PASSED] 0x4688 (ALDERLAKE_S)
[22:14:13] [PASSED] 0x468A (ALDERLAKE_S)
[22:14:13] [PASSED] 0x468B (ALDERLAKE_S)
[22:14:13] [PASSED] 0x4690 (ALDERLAKE_S)
[22:14:13] [PASSED] 0x4692 (ALDERLAKE_S)
[22:14:13] [PASSED] 0x4693 (ALDERLAKE_S)
[22:14:13] [PASSED] 0x46A0 (ALDERLAKE_P)
[22:14:13] [PASSED] 0x46A1 (ALDERLAKE_P)
[22:14:13] [PASSED] 0x46A2 (ALDERLAKE_P)
[22:14:13] [PASSED] 0x46A3 (ALDERLAKE_P)
[22:14:13] [PASSED] 0x46A6 (ALDERLAKE_P)
[22:14:13] [PASSED] 0x46A8 (ALDERLAKE_P)
[22:14:13] [PASSED] 0x46AA (ALDERLAKE_P)
[22:14:13] [PASSED] 0x462A (ALDERLAKE_P)
[22:14:13] [PASSED] 0x4626 (ALDERLAKE_P)
[22:14:13] [PASSED] 0x4628 (ALDERLAKE_P)
[22:14:13] [PASSED] 0x46B0 (ALDERLAKE_P)
[22:14:13] [PASSED] 0x46B1 (ALDERLAKE_P)
[22:14:13] [PASSED] 0x46B2 (ALDERLAKE_P)
[22:14:13] [PASSED] 0x46B3 (ALDERLAKE_P)
[22:14:13] [PASSED] 0x46C0 (ALDERLAKE_P)
[22:14:13] [PASSED] 0x46C1 (ALDERLAKE_P)
[22:14:13] [PASSED] 0x46C2 (ALDERLAKE_P)
[22:14:13] [PASSED] 0x46C3 (ALDERLAKE_P)
[22:14:13] [PASSED] 0x46D0 (ALDERLAKE_N)
[22:14:13] [PASSED] 0x46D1 (ALDERLAKE_N)
[22:14:13] [PASSED] 0x46D2 (ALDERLAKE_N)
[22:14:13] [PASSED] 0x46D3 (ALDERLAKE_N)
[22:14:13] [PASSED] 0x46D4 (ALDERLAKE_N)
[22:14:13] [PASSED] 0xA721 (ALDERLAKE_P)
[22:14:13] [PASSED] 0xA7A1 (ALDERLAKE_P)
[22:14:13] [PASSED] 0xA7A9 (ALDERLAKE_P)
[22:14:13] [PASSED] 0xA7AC (ALDERLAKE_P)
[22:14:13] [PASSED] 0xA7AD (ALDERLAKE_P)
[22:14:13] [PASSED] 0xA720 (ALDERLAKE_P)
[22:14:13] [PASSED] 0xA7A0 (ALDERLAKE_P)
[22:14:13] [PASSED] 0xA7A8 (ALDERLAKE_P)
[22:14:13] [PASSED] 0xA7AA (ALDERLAKE_P)
[22:14:13] [PASSED] 0xA7AB (ALDERLAKE_P)
[22:14:13] [PASSED] 0xA780 (ALDERLAKE_S)
[22:14:13] [PASSED] 0xA781 (ALDERLAKE_S)
[22:14:13] [PASSED] 0xA782 (ALDERLAKE_S)
[22:14:13] [PASSED] 0xA783 (ALDERLAKE_S)
[22:14:13] [PASSED] 0xA788 (ALDERLAKE_S)
[22:14:13] [PASSED] 0xA789 (ALDERLAKE_S)
[22:14:13] [PASSED] 0xA78A (ALDERLAKE_S)
[22:14:13] [PASSED] 0xA78B (ALDERLAKE_S)
[22:14:13] [PASSED] 0x4905 (DG1)
[22:14:13] [PASSED] 0x4906 (DG1)
[22:14:13] [PASSED] 0x4907 (DG1)
[22:14:13] [PASSED] 0x4908 (DG1)
[22:14:13] [PASSED] 0x4909 (DG1)
[22:14:13] [PASSED] 0x56C0 (DG2)
[22:14:13] [PASSED] 0x56C2 (DG2)
[22:14:13] [PASSED] 0x56C1 (DG2)
[22:14:13] [PASSED] 0x7D51 (METEORLAKE)
[22:14:13] [PASSED] 0x7DD1 (METEORLAKE)
[22:14:13] [PASSED] 0x7D41 (METEORLAKE)
[22:14:13] [PASSED] 0x7D67 (METEORLAKE)
[22:14:13] [PASSED] 0xB640 (METEORLAKE)
[22:14:13] [PASSED] 0x56A0 (DG2)
[22:14:13] [PASSED] 0x56A1 (DG2)
[22:14:13] [PASSED] 0x56A2 (DG2)
[22:14:13] [PASSED] 0x56BE (DG2)
[22:14:13] [PASSED] 0x56BF (DG2)
[22:14:13] [PASSED] 0x5690 (DG2)
[22:14:13] [PASSED] 0x5691 (DG2)
[22:14:13] [PASSED] 0x5692 (DG2)
[22:14:13] [PASSED] 0x56A5 (DG2)
[22:14:13] [PASSED] 0x56A6 (DG2)
[22:14:13] [PASSED] 0x56B0 (DG2)
[22:14:13] [PASSED] 0x56B1 (DG2)
[22:14:13] [PASSED] 0x56BA (DG2)
[22:14:13] [PASSED] 0x56BB (DG2)
[22:14:13] [PASSED] 0x56BC (DG2)
[22:14:13] [PASSED] 0x56BD (DG2)
[22:14:13] [PASSED] 0x5693 (DG2)
[22:14:13] [PASSED] 0x5694 (DG2)
[22:14:13] [PASSED] 0x5695 (DG2)
[22:14:13] [PASSED] 0x56A3 (DG2)
[22:14:13] [PASSED] 0x56A4 (DG2)
[22:14:13] [PASSED] 0x56B2 (DG2)
[22:14:13] [PASSED] 0x56B3 (DG2)
[22:14:13] [PASSED] 0x5696 (DG2)
[22:14:13] [PASSED] 0x5697 (DG2)
[22:14:13] [PASSED] 0xB69 (PVC)
[22:14:13] [PASSED] 0xB6E (PVC)
[22:14:13] [PASSED] 0xBD4 (PVC)
[22:14:13] [PASSED] 0xBD5 (PVC)
[22:14:13] [PASSED] 0xBD6 (PVC)
[22:14:13] [PASSED] 0xBD7 (PVC)
[22:14:13] [PASSED] 0xBD8 (PVC)
[22:14:13] [PASSED] 0xBD9 (PVC)
[22:14:13] [PASSED] 0xBDA (PVC)
[22:14:13] [PASSED] 0xBDB (PVC)
[22:14:13] [PASSED] 0xBE0 (PVC)
[22:14:13] [PASSED] 0xBE1 (PVC)
[22:14:13] [PASSED] 0xBE5 (PVC)
[22:14:13] [PASSED] 0x7D40 (METEORLAKE)
[22:14:13] [PASSED] 0x7D45 (METEORLAKE)
[22:14:13] [PASSED] 0x7D55 (METEORLAKE)
[22:14:13] [PASSED] 0x7D60 (METEORLAKE)
[22:14:13] [PASSED] 0x7DD5 (METEORLAKE)
[22:14:13] [PASSED] 0x6420 (LUNARLAKE)
[22:14:13] [PASSED] 0x64A0 (LUNARLAKE)
[22:14:13] [PASSED] 0x64B0 (LUNARLAKE)
[22:14:13] [PASSED] 0xE202 (BATTLEMAGE)
[22:14:13] [PASSED] 0xE209 (BATTLEMAGE)
[22:14:13] [PASSED] 0xE20B (BATTLEMAGE)
[22:14:13] [PASSED] 0xE20C (BATTLEMAGE)
[22:14:13] [PASSED] 0xE20D (BATTLEMAGE)
[22:14:13] [PASSED] 0xE210 (BATTLEMAGE)
[22:14:13] [PASSED] 0xE211 (BATTLEMAGE)
[22:14:13] [PASSED] 0xE212 (BATTLEMAGE)
[22:14:13] [PASSED] 0xE216 (BATTLEMAGE)
[22:14:13] [PASSED] 0xE220 (BATTLEMAGE)
[22:14:13] [PASSED] 0xE221 (BATTLEMAGE)
[22:14:13] [PASSED] 0xE222 (BATTLEMAGE)
[22:14:13] [PASSED] 0xE223 (BATTLEMAGE)
[22:14:13] [PASSED] 0xB080 (PANTHERLAKE)
[22:14:13] [PASSED] 0xB081 (PANTHERLAKE)
[22:14:13] [PASSED] 0xB082 (PANTHERLAKE)
[22:14:13] [PASSED] 0xB083 (PANTHERLAKE)
[22:14:13] [PASSED] 0xB084 (PANTHERLAKE)
[22:14:13] [PASSED] 0xB085 (PANTHERLAKE)
[22:14:13] [PASSED] 0xB086 (PANTHERLAKE)
[22:14:13] [PASSED] 0xB087 (PANTHERLAKE)
[22:14:13] [PASSED] 0xB08F (PANTHERLAKE)
[22:14:13] [PASSED] 0xB090 (PANTHERLAKE)
[22:14:13] [PASSED] 0xB0A0 (PANTHERLAKE)
[22:14:13] [PASSED] 0xB0B0 (PANTHERLAKE)
[22:14:13] [PASSED] 0xFD80 (PANTHERLAKE)
[22:14:13] [PASSED] 0xFD81 (PANTHERLAKE)
[22:14:13] [PASSED] 0xD740 (NOVALAKE_S)
[22:14:13] [PASSED] 0xD741 (NOVALAKE_S)
[22:14:13] [PASSED] 0xD742 (NOVALAKE_S)
[22:14:13] [PASSED] 0xD743 (NOVALAKE_S)
[22:14:13] [PASSED] 0xD744 (NOVALAKE_S)
[22:14:13] [PASSED] 0xD745 (NOVALAKE_S)
[22:14:13] [PASSED] 0x674C (CRESCENTISLAND)
[22:14:13] [PASSED] 0x674D (CRESCENTISLAND)
[22:14:13] [PASSED] 0x674E (CRESCENTISLAND)
[22:14:13] [PASSED] 0x674F (CRESCENTISLAND)
[22:14:13] [PASSED] 0x6750 (CRESCENTISLAND)
[22:14:13] [PASSED] 0xD750 (NOVALAKE_P)
[22:14:13] [PASSED] 0xD751 (NOVALAKE_P)
[22:14:13] [PASSED] 0xD752 (NOVALAKE_P)
[22:14:13] [PASSED] 0xD753 (NOVALAKE_P)
[22:14:13] [PASSED] 0xD754 (NOVALAKE_P)
[22:14:13] [PASSED] 0xD755 (NOVALAKE_P)
[22:14:13] [PASSED] 0xD756 (NOVALAKE_P)
[22:14:13] [PASSED] 0xD757 (NOVALAKE_P)
[22:14:13] [PASSED] 0xD75F (NOVALAKE_P)
[22:14:13] =============== [PASSED] check_platform_desc ===============
[22:14:13] ===================== [PASSED] xe_pci ======================
[22:14:13] =================== xe_rtp (2 subtests) ====================
[22:14:13] =============== xe_rtp_process_to_sr_tests  ================
[22:14:13] [PASSED] coalesce-same-reg
[22:14:13] [PASSED] no-match-no-add
[22:14:13] [PASSED] match-or
[22:14:13] [PASSED] match-or-xfail
[22:14:13] [PASSED] no-match-no-add-multiple-rules
[22:14:13] [PASSED] two-regs-two-entries
[22:14:13] [PASSED] clr-one-set-other
[22:14:13] [PASSED] set-field
[22:14:13] [PASSED] conflict-duplicate
[22:14:13] [PASSED] conflict-not-disjoint
[22:14:13] [PASSED] conflict-reg-type
[22:14:13] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[22:14:13] ================== xe_rtp_process_tests  ===================
[22:14:13] [PASSED] active1
[22:14:13] [PASSED] active2
[22:14:13] [PASSED] active-inactive
[22:14:13] [PASSED] inactive-active
[22:14:13] [PASSED] inactive-1st_or_active-inactive
[22:14:13] [PASSED] inactive-2nd_or_active-inactive
[22:14:13] [PASSED] inactive-last_or_active-inactive
[22:14:13] [PASSED] inactive-no_or_active-inactive
[22:14:13] ============== [PASSED] xe_rtp_process_tests ===============
[22:14:13] ===================== [PASSED] xe_rtp ======================
[22:14:13] ==================== xe_wa (1 subtest) =====================
[22:14:13] ======================== xe_wa_gt  =========================
[22:14:13] [PASSED] TIGERLAKE B0
[22:14:13] [PASSED] DG1 A0
[22:14:13] [PASSED] DG1 B0
[22:14:13] [PASSED] ALDERLAKE_S A0
[22:14:13] [PASSED] ALDERLAKE_S B0
[22:14:13] [PASSED] ALDERLAKE_S C0
[22:14:13] [PASSED] ALDERLAKE_S D0
[22:14:13] [PASSED] ALDERLAKE_P A0
[22:14:13] [PASSED] ALDERLAKE_P B0
[22:14:13] [PASSED] ALDERLAKE_P C0
[22:14:13] [PASSED] ALDERLAKE_S RPLS D0
[22:14:13] [PASSED] ALDERLAKE_P RPLU E0
[22:14:13] [PASSED] DG2 G10 C0
[22:14:13] [PASSED] DG2 G11 B1
[22:14:13] [PASSED] DG2 G12 A1
[22:14:13] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[22:14:13] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[22:14:13] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[22:14:13] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[22:14:13] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[22:14:13] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[22:14:13] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[22:14:13] ==================== [PASSED] xe_wa_gt =====================
[22:14:13] ====================== [PASSED] xe_wa ======================
[22:14:13] ============================================================
[22:14:13] Testing complete. Ran 601 tests: passed: 583, skipped: 18
[22:14:13] Elapsed time: 46.628s total, 4.614s configuring, 41.347s building, 0.631s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[22:14:13] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[22:14:15] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[22:14:49] Starting KUnit Kernel (1/1)...
[22:14:49] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[22:14:49] ============ drm_test_pick_cmdline (2 subtests) ============
[22:14:49] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[22:14:49] =============== drm_test_pick_cmdline_named  ===============
[22:14:49] [PASSED] NTSC
[22:14:49] [PASSED] NTSC-J
[22:14:49] [PASSED] PAL
[22:14:49] [PASSED] PAL-M
[22:14:49] =========== [PASSED] drm_test_pick_cmdline_named ===========
[22:14:49] ============== [PASSED] drm_test_pick_cmdline ==============
[22:14:49] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[22:14:49] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[22:14:49] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[22:14:49] =========== drm_validate_clone_mode (2 subtests) ===========
[22:14:49] ============== drm_test_check_in_clone_mode  ===============
[22:14:49] [PASSED] in_clone_mode
[22:14:49] [PASSED] not_in_clone_mode
[22:14:49] ========== [PASSED] drm_test_check_in_clone_mode ===========
[22:14:49] =============== drm_test_check_valid_clones  ===============
[22:14:49] [PASSED] not_in_clone_mode
[22:14:49] [PASSED] valid_clone
[22:14:49] [PASSED] invalid_clone
[22:14:49] =========== [PASSED] drm_test_check_valid_clones ===========
[22:14:49] ============= [PASSED] drm_validate_clone_mode =============
[22:14:49] ============= drm_validate_modeset (1 subtest) =============
[22:14:49] [PASSED] drm_test_check_connector_changed_modeset
[22:14:49] ============== [PASSED] drm_validate_modeset ===============
[22:14:49] ====== drm_test_bridge_get_current_state (2 subtests) ======
[22:14:49] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[22:14:49] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[22:14:49] ======== [PASSED] drm_test_bridge_get_current_state ========
[22:14:49] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[22:14:49] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[22:14:49] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[22:14:49] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[22:14:49] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[22:14:49] ============== drm_bridge_alloc (2 subtests) ===============
[22:14:49] [PASSED] drm_test_drm_bridge_alloc_basic
[22:14:49] [PASSED] drm_test_drm_bridge_alloc_get_put
[22:14:49] ================ [PASSED] drm_bridge_alloc =================
[22:14:49] ============= drm_cmdline_parser (40 subtests) =============
[22:14:49] [PASSED] drm_test_cmdline_force_d_only
[22:14:49] [PASSED] drm_test_cmdline_force_D_only_dvi
[22:14:49] [PASSED] drm_test_cmdline_force_D_only_hdmi
[22:14:49] [PASSED] drm_test_cmdline_force_D_only_not_digital
[22:14:49] [PASSED] drm_test_cmdline_force_e_only
[22:14:49] [PASSED] drm_test_cmdline_res
[22:14:49] [PASSED] drm_test_cmdline_res_vesa
[22:14:49] [PASSED] drm_test_cmdline_res_vesa_rblank
[22:14:49] [PASSED] drm_test_cmdline_res_rblank
[22:14:49] [PASSED] drm_test_cmdline_res_bpp
[22:14:49] [PASSED] drm_test_cmdline_res_refresh
[22:14:49] [PASSED] drm_test_cmdline_res_bpp_refresh
[22:14:49] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[22:14:49] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[22:14:49] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[22:14:49] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[22:14:49] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[22:14:49] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[22:14:49] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[22:14:49] [PASSED] drm_test_cmdline_res_margins_force_on
[22:14:49] [PASSED] drm_test_cmdline_res_vesa_margins
[22:14:49] [PASSED] drm_test_cmdline_name
[22:14:49] [PASSED] drm_test_cmdline_name_bpp
[22:14:49] [PASSED] drm_test_cmdline_name_option
[22:14:49] [PASSED] drm_test_cmdline_name_bpp_option
[22:14:49] [PASSED] drm_test_cmdline_rotate_0
[22:14:49] [PASSED] drm_test_cmdline_rotate_90
[22:14:49] [PASSED] drm_test_cmdline_rotate_180
[22:14:49] [PASSED] drm_test_cmdline_rotate_270
[22:14:49] [PASSED] drm_test_cmdline_hmirror
[22:14:49] [PASSED] drm_test_cmdline_vmirror
[22:14:49] [PASSED] drm_test_cmdline_margin_options
[22:14:49] [PASSED] drm_test_cmdline_multiple_options
[22:14:49] [PASSED] drm_test_cmdline_bpp_extra_and_option
[22:14:49] [PASSED] drm_test_cmdline_extra_and_option
[22:14:49] [PASSED] drm_test_cmdline_freestanding_options
[22:14:49] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[22:14:49] [PASSED] drm_test_cmdline_panel_orientation
[22:14:49] ================ drm_test_cmdline_invalid  =================
[22:14:49] [PASSED] margin_only
[22:14:49] [PASSED] interlace_only
[22:14:49] [PASSED] res_missing_x
[22:14:49] [PASSED] res_missing_y
[22:14:49] [PASSED] res_bad_y
[22:14:49] [PASSED] res_missing_y_bpp
[22:14:49] [PASSED] res_bad_bpp
[22:14:49] [PASSED] res_bad_refresh
[22:14:49] [PASSED] res_bpp_refresh_force_on_off
[22:14:49] [PASSED] res_invalid_mode
[22:14:49] [PASSED] res_bpp_wrong_place_mode
[22:14:49] [PASSED] name_bpp_refresh
[22:14:49] [PASSED] name_refresh
[22:14:49] [PASSED] name_refresh_wrong_mode
[22:14:49] [PASSED] name_refresh_invalid_mode
[22:14:49] [PASSED] rotate_multiple
[22:14:49] [PASSED] rotate_invalid_val
[22:14:49] [PASSED] rotate_truncated
[22:14:49] [PASSED] invalid_option
[22:14:49] [PASSED] invalid_tv_option
[22:14:49] [PASSED] truncated_tv_option
[22:14:49] ============ [PASSED] drm_test_cmdline_invalid =============
[22:14:49] =============== drm_test_cmdline_tv_options  ===============
[22:14:49] [PASSED] NTSC
[22:14:49] [PASSED] NTSC_443
[22:14:49] [PASSED] NTSC_J
[22:14:49] [PASSED] PAL
[22:14:49] [PASSED] PAL_M
[22:14:49] [PASSED] PAL_N
[22:14:49] [PASSED] SECAM
[22:14:49] [PASSED] MONO_525
[22:14:49] [PASSED] MONO_625
[22:14:49] =========== [PASSED] drm_test_cmdline_tv_options ===========
[22:14:49] =============== [PASSED] drm_cmdline_parser ================
[22:14:49] ========== drmm_connector_hdmi_init (20 subtests) ==========
[22:14:49] [PASSED] drm_test_connector_hdmi_init_valid
[22:14:49] [PASSED] drm_test_connector_hdmi_init_bpc_8
[22:14:49] [PASSED] drm_test_connector_hdmi_init_bpc_10
[22:14:49] [PASSED] drm_test_connector_hdmi_init_bpc_12
[22:14:49] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[22:14:49] [PASSED] drm_test_connector_hdmi_init_bpc_null
[22:14:49] [PASSED] drm_test_connector_hdmi_init_formats_empty
[22:14:49] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[22:14:49] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[22:14:49] [PASSED] supported_formats=0x9 yuv420_allowed=1
[22:14:49] [PASSED] supported_formats=0x9 yuv420_allowed=0
[22:14:49] [PASSED] supported_formats=0x5 yuv420_allowed=1
[22:14:49] [PASSED] supported_formats=0x5 yuv420_allowed=0
[22:14:49] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[22:14:49] [PASSED] drm_test_connector_hdmi_init_null_ddc
[22:14:49] [PASSED] drm_test_connector_hdmi_init_null_product
[22:14:49] [PASSED] drm_test_connector_hdmi_init_null_vendor
[22:14:49] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[22:14:49] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[22:14:49] [PASSED] drm_test_connector_hdmi_init_product_valid
[22:14:49] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[22:14:49] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[22:14:49] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[22:14:49] ========= drm_test_connector_hdmi_init_type_valid  =========
[22:14:49] [PASSED] HDMI-A
[22:14:49] [PASSED] HDMI-B
[22:14:49] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[22:14:49] ======== drm_test_connector_hdmi_init_type_invalid  ========
[22:14:49] [PASSED] Unknown
[22:14:49] [PASSED] VGA
[22:14:49] [PASSED] DVI-I
[22:14:49] [PASSED] DVI-D
[22:14:49] [PASSED] DVI-A
[22:14:49] [PASSED] Composite
[22:14:49] [PASSED] SVIDEO
[22:14:49] [PASSED] LVDS
[22:14:49] [PASSED] Component
[22:14:49] [PASSED] DIN
[22:14:49] [PASSED] DP
[22:14:49] [PASSED] TV
[22:14:49] [PASSED] eDP
[22:14:49] [PASSED] Virtual
[22:14:49] [PASSED] DSI
[22:14:49] [PASSED] DPI
[22:14:49] [PASSED] Writeback
[22:14:49] [PASSED] SPI
[22:14:49] [PASSED] USB
[22:14:49] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[22:14:49] ============ [PASSED] drmm_connector_hdmi_init =============
[22:14:49] ============= drmm_connector_init (3 subtests) =============
[22:14:49] [PASSED] drm_test_drmm_connector_init
[22:14:49] [PASSED] drm_test_drmm_connector_init_null_ddc
[22:14:49] ========= drm_test_drmm_connector_init_type_valid  =========
[22:14:49] [PASSED] Unknown
[22:14:49] [PASSED] VGA
[22:14:49] [PASSED] DVI-I
[22:14:49] [PASSED] DVI-D
[22:14:49] [PASSED] DVI-A
[22:14:49] [PASSED] Composite
[22:14:49] [PASSED] SVIDEO
[22:14:49] [PASSED] LVDS
[22:14:49] [PASSED] Component
[22:14:49] [PASSED] DIN
[22:14:49] [PASSED] DP
[22:14:49] [PASSED] HDMI-A
[22:14:49] [PASSED] HDMI-B
[22:14:49] [PASSED] TV
[22:14:49] [PASSED] eDP
[22:14:49] [PASSED] Virtual
[22:14:49] [PASSED] DSI
[22:14:49] [PASSED] DPI
[22:14:49] [PASSED] Writeback
[22:14:49] [PASSED] SPI
[22:14:49] [PASSED] USB
[22:14:49] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[22:14:49] =============== [PASSED] drmm_connector_init ===============
[22:14:49] ========= drm_connector_dynamic_init (6 subtests) ==========
[22:14:49] [PASSED] drm_test_drm_connector_dynamic_init
[22:14:49] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[22:14:49] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[22:14:49] [PASSED] drm_test_drm_connector_dynamic_init_properties
[22:14:49] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[22:14:49] [PASSED] Unknown
[22:14:49] [PASSED] VGA
[22:14:49] [PASSED] DVI-I
[22:14:49] [PASSED] DVI-D
[22:14:49] [PASSED] DVI-A
[22:14:49] [PASSED] Composite
[22:14:49] [PASSED] SVIDEO
[22:14:49] [PASSED] LVDS
[22:14:49] [PASSED] Component
[22:14:49] [PASSED] DIN
[22:14:49] [PASSED] DP
[22:14:49] [PASSED] HDMI-A
[22:14:49] [PASSED] HDMI-B
[22:14:49] [PASSED] TV
[22:14:49] [PASSED] eDP
[22:14:49] [PASSED] Virtual
[22:14:49] [PASSED] DSI
[22:14:49] [PASSED] DPI
[22:14:49] [PASSED] Writeback
[22:14:49] [PASSED] SPI
[22:14:49] [PASSED] USB
[22:14:49] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[22:14:49] ======== drm_test_drm_connector_dynamic_init_name  =========
[22:14:49] [PASSED] Unknown
[22:14:49] [PASSED] VGA
[22:14:49] [PASSED] DVI-I
[22:14:49] [PASSED] DVI-D
[22:14:49] [PASSED] DVI-A
[22:14:49] [PASSED] Composite
[22:14:49] [PASSED] SVIDEO
[22:14:49] [PASSED] LVDS
[22:14:49] [PASSED] Component
[22:14:49] [PASSED] DIN
[22:14:49] [PASSED] DP
[22:14:49] [PASSED] HDMI-A
[22:14:49] [PASSED] HDMI-B
[22:14:49] [PASSED] TV
[22:14:49] [PASSED] eDP
[22:14:49] [PASSED] Virtual
[22:14:49] [PASSED] DSI
[22:14:49] [PASSED] DPI
[22:14:49] [PASSED] Writeback
[22:14:49] [PASSED] SPI
[22:14:49] [PASSED] USB
[22:14:49] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[22:14:49] =========== [PASSED] drm_connector_dynamic_init ============
[22:14:49] ==== drm_connector_dynamic_register_early (4 subtests) =====
[22:14:49] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[22:14:49] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[22:14:49] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[22:14:49] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[22:14:49] ====== [PASSED] drm_connector_dynamic_register_early =======
[22:14:49] ======= drm_connector_dynamic_register (7 subtests) ========
[22:14:49] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[22:14:49] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[22:14:49] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[22:14:49] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[22:14:49] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[22:14:49] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[22:14:49] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[22:14:49] ========= [PASSED] drm_connector_dynamic_register ==========
[22:14:49] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[22:14:49] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[22:14:49] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[22:14:49] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[22:14:49] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[22:14:49] ========== drm_test_get_tv_mode_from_name_valid  ===========
[22:14:49] [PASSED] NTSC
[22:14:49] [PASSED] NTSC-443
[22:14:49] [PASSED] NTSC-J
[22:14:49] [PASSED] PAL
[22:14:49] [PASSED] PAL-M
[22:14:49] [PASSED] PAL-N
[22:14:49] [PASSED] SECAM
[22:14:49] [PASSED] Mono
[22:14:49] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[22:14:49] [PASSED] drm_test_get_tv_mode_from_name_truncated
[22:14:49] ============ [PASSED] drm_get_tv_mode_from_name ============
[22:14:49] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[22:14:49] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[22:14:49] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[22:14:49] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[22:14:49] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[22:14:49] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[22:14:49] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[22:14:49] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[22:14:49] [PASSED] VIC 96
[22:14:49] [PASSED] VIC 97
[22:14:49] [PASSED] VIC 101
[22:14:49] [PASSED] VIC 102
[22:14:49] [PASSED] VIC 106
[22:14:49] [PASSED] VIC 107
[22:14:49] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[22:14:49] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[22:14:49] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[22:14:49] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[22:14:49] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[22:14:49] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[22:14:49] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[22:14:49] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[22:14:49] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[22:14:49] [PASSED] Automatic
[22:14:49] [PASSED] Full
[22:14:49] [PASSED] Limited 16:235
[22:14:49] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[22:14:49] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[22:14:49] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[22:14:49] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[22:14:49] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[22:14:49] [PASSED] RGB
[22:14:49] [PASSED] YUV 4:2:0
[22:14:49] [PASSED] YUV 4:2:2
[22:14:49] [PASSED] YUV 4:4:4
[22:14:49] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[22:14:49] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[22:14:49] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[22:14:49] ============= drm_damage_helper (21 subtests) ==============
[22:14:49] [PASSED] drm_test_damage_iter_no_damage
[22:14:49] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[22:14:49] [PASSED] drm_test_damage_iter_no_damage_src_moved
[22:14:49] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[22:14:49] [PASSED] drm_test_damage_iter_no_damage_not_visible
[22:14:49] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[22:14:49] [PASSED] drm_test_damage_iter_no_damage_no_fb
[22:14:49] [PASSED] drm_test_damage_iter_simple_damage
[22:14:49] [PASSED] drm_test_damage_iter_single_damage
[22:14:49] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[22:14:49] [PASSED] drm_test_damage_iter_single_damage_outside_src
[22:14:49] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[22:14:49] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[22:14:49] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[22:14:49] [PASSED] drm_test_damage_iter_single_damage_src_moved
[22:14:49] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[22:14:49] [PASSED] drm_test_damage_iter_damage
[22:14:49] [PASSED] drm_test_damage_iter_damage_one_intersect
[22:14:49] [PASSED] drm_test_damage_iter_damage_one_outside
[22:14:49] [PASSED] drm_test_damage_iter_damage_src_moved
[22:14:49] [PASSED] drm_test_damage_iter_damage_not_visible
[22:14:49] ================ [PASSED] drm_damage_helper ================
[22:14:49] ============== drm_dp_mst_helper (3 subtests) ==============
[22:14:49] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[22:14:49] [PASSED] Clock 154000 BPP 30 DSC disabled
[22:14:49] [PASSED] Clock 234000 BPP 30 DSC disabled
[22:14:49] [PASSED] Clock 297000 BPP 24 DSC disabled
[22:14:49] [PASSED] Clock 332880 BPP 24 DSC enabled
[22:14:49] [PASSED] Clock 324540 BPP 24 DSC enabled
[22:14:49] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[22:14:49] ============== drm_test_dp_mst_calc_pbn_div  ===============
[22:14:49] [PASSED] Link rate 2000000 lane count 4
[22:14:49] [PASSED] Link rate 2000000 lane count 2
[22:14:49] [PASSED] Link rate 2000000 lane count 1
[22:14:49] [PASSED] Link rate 1350000 lane count 4
[22:14:49] [PASSED] Link rate 1350000 lane count 2
[22:14:49] [PASSED] Link rate 1350000 lane count 1
[22:14:49] [PASSED] Link rate 1000000 lane count 4
[22:14:49] [PASSED] Link rate 1000000 lane count 2
[22:14:49] [PASSED] Link rate 1000000 lane count 1
[22:14:49] [PASSED] Link rate 810000 lane count 4
[22:14:49] [PASSED] Link rate 810000 lane count 2
[22:14:49] [PASSED] Link rate 810000 lane count 1
[22:14:49] [PASSED] Link rate 540000 lane count 4
[22:14:49] [PASSED] Link rate 540000 lane count 2
[22:14:49] [PASSED] Link rate 540000 lane count 1
[22:14:49] [PASSED] Link rate 270000 lane count 4
[22:14:49] [PASSED] Link rate 270000 lane count 2
[22:14:49] [PASSED] Link rate 270000 lane count 1
[22:14:49] [PASSED] Link rate 162000 lane count 4
[22:14:49] [PASSED] Link rate 162000 lane count 2
[22:14:49] [PASSED] Link rate 162000 lane count 1
[22:14:49] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[22:14:49] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[22:14:49] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[22:14:49] [PASSED] DP_POWER_UP_PHY with port number
[22:14:49] [PASSED] DP_POWER_DOWN_PHY with port number
[22:14:49] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[22:14:49] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[22:14:49] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[22:14:49] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[22:14:49] [PASSED] DP_QUERY_PAYLOAD with port number
[22:14:49] [PASSED] DP_QUERY_PAYLOAD with VCPI
[22:14:49] [PASSED] DP_REMOTE_DPCD_READ with port number
[22:14:49] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[22:14:49] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[22:14:49] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[22:14:49] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[22:14:49] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[22:14:49] [PASSED] DP_REMOTE_I2C_READ with port number
[22:14:49] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[22:14:49] [PASSED] DP_REMOTE_I2C_READ with transactions array
[22:14:49] [PASSED] DP_REMOTE_I2C_WRITE with port number
[22:14:49] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[22:14:49] [PASSED] DP_REMOTE_I2C_WRITE with data array
[22:14:49] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[22:14:49] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[22:14:49] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[22:14:49] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[22:14:49] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[22:14:49] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[22:14:49] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[22:14:49] ================ [PASSED] drm_dp_mst_helper ================
[22:14:49] ================== drm_exec (7 subtests) ===================
[22:14:49] [PASSED] sanitycheck
[22:14:49] [PASSED] test_lock
[22:14:49] [PASSED] test_lock_unlock
[22:14:49] [PASSED] test_duplicates
[22:14:49] [PASSED] test_prepare
[22:14:49] [PASSED] test_prepare_array
[22:14:49] [PASSED] test_multiple_loops
[22:14:49] ==================== [PASSED] drm_exec =====================
[22:14:49] =========== drm_format_helper_test (17 subtests) ===========
[22:14:49] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[22:14:49] [PASSED] single_pixel_source_buffer
[22:14:49] [PASSED] single_pixel_clip_rectangle
[22:14:49] [PASSED] well_known_colors
[22:14:49] [PASSED] destination_pitch
[22:14:49] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[22:14:49] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[22:14:49] [PASSED] single_pixel_source_buffer
[22:14:49] [PASSED] single_pixel_clip_rectangle
[22:14:49] [PASSED] well_known_colors
[22:14:49] [PASSED] destination_pitch
[22:14:49] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[22:14:49] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[22:14:49] [PASSED] single_pixel_source_buffer
[22:14:49] [PASSED] single_pixel_clip_rectangle
[22:14:49] [PASSED] well_known_colors
[22:14:49] [PASSED] destination_pitch
[22:14:49] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[22:14:49] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[22:14:49] [PASSED] single_pixel_source_buffer
[22:14:49] [PASSED] single_pixel_clip_rectangle
[22:14:49] [PASSED] well_known_colors
[22:14:49] [PASSED] destination_pitch
[22:14:49] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[22:14:49] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[22:14:49] [PASSED] single_pixel_source_buffer
[22:14:49] [PASSED] single_pixel_clip_rectangle
[22:14:49] [PASSED] well_known_colors
[22:14:49] [PASSED] destination_pitch
[22:14:49] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[22:14:49] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[22:14:49] [PASSED] single_pixel_source_buffer
[22:14:49] [PASSED] single_pixel_clip_rectangle
[22:14:49] [PASSED] well_known_colors
[22:14:49] [PASSED] destination_pitch
[22:14:49] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[22:14:49] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[22:14:49] [PASSED] single_pixel_source_buffer
[22:14:49] [PASSED] single_pixel_clip_rectangle
[22:14:49] [PASSED] well_known_colors
[22:14:49] [PASSED] destination_pitch
[22:14:49] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[22:14:49] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[22:14:49] [PASSED] single_pixel_source_buffer
[22:14:49] [PASSED] single_pixel_clip_rectangle
[22:14:49] [PASSED] well_known_colors
[22:14:49] [PASSED] destination_pitch
[22:14:49] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[22:14:49] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[22:14:49] [PASSED] single_pixel_source_buffer
[22:14:49] [PASSED] single_pixel_clip_rectangle
[22:14:49] [PASSED] well_known_colors
[22:14:49] [PASSED] destination_pitch
[22:14:49] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[22:14:49] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[22:14:49] [PASSED] single_pixel_source_buffer
[22:14:49] [PASSED] single_pixel_clip_rectangle
[22:14:49] [PASSED] well_known_colors
[22:14:49] [PASSED] destination_pitch
[22:14:49] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[22:14:49] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[22:14:49] [PASSED] single_pixel_source_buffer
[22:14:49] [PASSED] single_pixel_clip_rectangle
[22:14:49] [PASSED] well_known_colors
[22:14:49] [PASSED] destination_pitch
[22:14:49] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[22:14:49] ============== drm_test_fb_xrgb8888_to_mono  ===============
[22:14:49] [PASSED] single_pixel_source_buffer
[22:14:49] [PASSED] single_pixel_clip_rectangle
[22:14:49] [PASSED] well_known_colors
[22:14:49] [PASSED] destination_pitch
[22:14:49] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[22:14:49] ==================== drm_test_fb_swab  =====================
[22:14:49] [PASSED] single_pixel_source_buffer
[22:14:49] [PASSED] single_pixel_clip_rectangle
[22:14:49] [PASSED] well_known_colors
[22:14:49] [PASSED] destination_pitch
[22:14:49] ================ [PASSED] drm_test_fb_swab =================
[22:14:49] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[22:14:49] [PASSED] single_pixel_source_buffer
[22:14:49] [PASSED] single_pixel_clip_rectangle
[22:14:49] [PASSED] well_known_colors
[22:14:49] [PASSED] destination_pitch
[22:14:49] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[22:14:49] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[22:14:49] [PASSED] single_pixel_source_buffer
[22:14:49] [PASSED] single_pixel_clip_rectangle
[22:14:49] [PASSED] well_known_colors
[22:14:49] [PASSED] destination_pitch
[22:14:49] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[22:14:49] ================= drm_test_fb_clip_offset  =================
[22:14:49] [PASSED] pass through
[22:14:49] [PASSED] horizontal offset
[22:14:49] [PASSED] vertical offset
[22:14:49] [PASSED] horizontal and vertical offset
[22:14:49] [PASSED] horizontal offset (custom pitch)
[22:14:49] [PASSED] vertical offset (custom pitch)
[22:14:49] [PASSED] horizontal and vertical offset (custom pitch)
[22:14:49] ============= [PASSED] drm_test_fb_clip_offset =============
[22:14:49] =================== drm_test_fb_memcpy  ====================
[22:14:49] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[22:14:49] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[22:14:49] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[22:14:49] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[22:14:49] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[22:14:49] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[22:14:49] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[22:14:49] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[22:14:49] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[22:14:49] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[22:14:49] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[22:14:49] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[22:14:49] =============== [PASSED] drm_test_fb_memcpy ================
[22:14:49] ============= [PASSED] drm_format_helper_test ==============
[22:14:49] ================= drm_format (18 subtests) =================
[22:14:49] [PASSED] drm_test_format_block_width_invalid
[22:14:49] [PASSED] drm_test_format_block_width_one_plane
[22:14:49] [PASSED] drm_test_format_block_width_two_plane
[22:14:49] [PASSED] drm_test_format_block_width_three_plane
[22:14:49] [PASSED] drm_test_format_block_width_tiled
[22:14:49] [PASSED] drm_test_format_block_height_invalid
[22:14:49] [PASSED] drm_test_format_block_height_one_plane
[22:14:49] [PASSED] drm_test_format_block_height_two_plane
[22:14:49] [PASSED] drm_test_format_block_height_three_plane
[22:14:49] [PASSED] drm_test_format_block_height_tiled
[22:14:49] [PASSED] drm_test_format_min_pitch_invalid
[22:14:49] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[22:14:49] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[22:14:49] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[22:14:49] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[22:14:49] [PASSED] drm_test_format_min_pitch_two_plane
[22:14:49] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[22:14:49] [PASSED] drm_test_format_min_pitch_tiled
[22:14:49] =================== [PASSED] drm_format ====================
[22:14:49] ============== drm_framebuffer (10 subtests) ===============
[22:14:49] ========== drm_test_framebuffer_check_src_coords  ==========
[22:14:49] [PASSED] Success: source fits into fb
[22:14:49] [PASSED] Fail: overflowing fb with x-axis coordinate
[22:14:49] [PASSED] Fail: overflowing fb with y-axis coordinate
[22:14:49] [PASSED] Fail: overflowing fb with source width
[22:14:49] [PASSED] Fail: overflowing fb with source height
[22:14:49] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[22:14:49] [PASSED] drm_test_framebuffer_cleanup
[22:14:49] =============== drm_test_framebuffer_create  ===============
[22:14:49] [PASSED] ABGR8888 normal sizes
[22:14:49] [PASSED] ABGR8888 max sizes
[22:14:49] [PASSED] ABGR8888 pitch greater than min required
[22:14:49] [PASSED] ABGR8888 pitch less than min required
[22:14:49] [PASSED] ABGR8888 Invalid width
[22:14:49] [PASSED] ABGR8888 Invalid buffer handle
[22:14:49] [PASSED] No pixel format
[22:14:49] [PASSED] ABGR8888 Width 0
[22:14:49] [PASSED] ABGR8888 Height 0
[22:14:49] [PASSED] ABGR8888 Out of bound height * pitch combination
[22:14:49] [PASSED] ABGR8888 Large buffer offset
[22:14:49] [PASSED] ABGR8888 Buffer offset for inexistent plane
[22:14:49] [PASSED] ABGR8888 Invalid flag
[22:14:49] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[22:14:49] [PASSED] ABGR8888 Valid buffer modifier
[22:14:49] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[22:14:49] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[22:14:49] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[22:14:49] [PASSED] NV12 Normal sizes
[22:14:49] [PASSED] NV12 Max sizes
[22:14:49] [PASSED] NV12 Invalid pitch
[22:14:49] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[22:14:49] [PASSED] NV12 different  modifier per-plane
[22:14:49] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[22:14:49] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[22:14:49] [PASSED] NV12 Modifier for inexistent plane
[22:14:49] [PASSED] NV12 Handle for inexistent plane
[22:14:49] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[22:14:49] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[22:14:49] [PASSED] YVU420 Normal sizes
[22:14:49] [PASSED] YVU420 Max sizes
[22:14:49] [PASSED] YVU420 Invalid pitch
[22:14:49] [PASSED] YVU420 Different pitches
[22:14:49] [PASSED] YVU420 Different buffer offsets/pitches
[22:14:49] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[22:14:49] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[22:14:49] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[22:14:49] [PASSED] YVU420 Valid modifier
[22:14:49] [PASSED] YVU420 Different modifiers per plane
[22:14:49] [PASSED] YVU420 Modifier for inexistent plane
[22:14:49] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[22:14:49] [PASSED] X0L2 Normal sizes
[22:14:49] [PASSED] X0L2 Max sizes
[22:14:49] [PASSED] X0L2 Invalid pitch
[22:14:49] [PASSED] X0L2 Pitch greater than minimum required
[22:14:49] [PASSED] X0L2 Handle for inexistent plane
[22:14:49] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[22:14:49] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[22:14:49] [PASSED] X0L2 Valid modifier
[22:14:49] [PASSED] X0L2 Modifier for inexistent plane
[22:14:49] =========== [PASSED] drm_test_framebuffer_create ===========
[22:14:49] [PASSED] drm_test_framebuffer_free
[22:14:49] [PASSED] drm_test_framebuffer_init
[22:14:49] [PASSED] drm_test_framebuffer_init_bad_format
[22:14:49] [PASSED] drm_test_framebuffer_init_dev_mismatch
[22:14:49] [PASSED] drm_test_framebuffer_lookup
[22:14:49] [PASSED] drm_test_framebuffer_lookup_inexistent
[22:14:49] [PASSED] drm_test_framebuffer_modifiers_not_supported
[22:14:49] ================= [PASSED] drm_framebuffer =================
[22:14:49] ================ drm_gem_shmem (8 subtests) ================
[22:14:49] [PASSED] drm_gem_shmem_test_obj_create
[22:14:49] [PASSED] drm_gem_shmem_test_obj_create_private
[22:14:49] [PASSED] drm_gem_shmem_test_pin_pages
[22:14:49] [PASSED] drm_gem_shmem_test_vmap
[22:14:49] [PASSED] drm_gem_shmem_test_get_sg_table
[22:14:49] [PASSED] drm_gem_shmem_test_get_pages_sgt
[22:14:49] [PASSED] drm_gem_shmem_test_madvise
[22:14:49] [PASSED] drm_gem_shmem_test_purge
[22:14:49] ================== [PASSED] drm_gem_shmem ==================
[22:14:49] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[22:14:49] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[22:14:49] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[22:14:49] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[22:14:49] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[22:14:49] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[22:14:49] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[22:14:49] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[22:14:49] [PASSED] Automatic
[22:14:49] [PASSED] Full
[22:14:49] [PASSED] Limited 16:235
[22:14:49] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[22:14:49] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[22:14:49] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[22:14:49] [PASSED] drm_test_check_disable_connector
[22:14:49] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[22:14:49] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[22:14:49] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[22:14:49] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[22:14:49] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[22:14:49] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[22:14:49] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[22:14:49] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[22:14:49] [PASSED] drm_test_check_output_bpc_dvi
[22:14:49] [PASSED] drm_test_check_output_bpc_format_vic_1
[22:14:49] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[22:14:49] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[22:14:49] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[22:14:49] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[22:14:49] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[22:14:49] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[22:14:49] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[22:14:49] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[22:14:49] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[22:14:49] [PASSED] drm_test_check_broadcast_rgb_value
[22:14:49] [PASSED] drm_test_check_bpc_8_value
[22:14:49] [PASSED] drm_test_check_bpc_10_value
[22:14:49] [PASSED] drm_test_check_bpc_12_value
[22:14:49] [PASSED] drm_test_check_format_value
[22:14:49] [PASSED] drm_test_check_tmds_char_value
[22:14:49] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[22:14:49] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[22:14:49] [PASSED] drm_test_check_mode_valid
[22:14:49] [PASSED] drm_test_check_mode_valid_reject
[22:14:49] [PASSED] drm_test_check_mode_valid_reject_rate
[22:14:49] [PASSED] drm_test_check_mode_valid_reject_max_clock
[22:14:49] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[22:14:49] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[22:14:49] [PASSED] drm_test_check_infoframes
[22:14:49] [PASSED] drm_test_check_reject_avi_infoframe
[22:14:49] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[22:14:49] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[22:14:49] [PASSED] drm_test_check_reject_audio_infoframe
[22:14:49] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[22:14:49] ================= drm_managed (2 subtests) =================
[22:14:49] [PASSED] drm_test_managed_release_action
[22:14:49] [PASSED] drm_test_managed_run_action
[22:14:49] =================== [PASSED] drm_managed ===================
[22:14:49] =================== drm_mm (6 subtests) ====================
[22:14:49] [PASSED] drm_test_mm_init
[22:14:49] [PASSED] drm_test_mm_debug
[22:14:49] [PASSED] drm_test_mm_align32
[22:14:49] [PASSED] drm_test_mm_align64
[22:14:49] [PASSED] drm_test_mm_lowest
[22:14:49] [PASSED] drm_test_mm_highest
[22:14:49] ===================== [PASSED] drm_mm ======================
[22:14:49] ============= drm_modes_analog_tv (5 subtests) =============
[22:14:49] [PASSED] drm_test_modes_analog_tv_mono_576i
[22:14:49] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[22:14:49] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[22:14:49] [PASSED] drm_test_modes_analog_tv_pal_576i
[22:14:49] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[22:14:49] =============== [PASSED] drm_modes_analog_tv ===============
[22:14:49] ============== drm_plane_helper (2 subtests) ===============
[22:14:49] =============== drm_test_check_plane_state  ================
[22:14:49] [PASSED] clipping_simple
[22:14:49] [PASSED] clipping_rotate_reflect
[22:14:49] [PASSED] positioning_simple
[22:14:49] [PASSED] upscaling
[22:14:49] [PASSED] downscaling
[22:14:49] [PASSED] rounding1
[22:14:49] [PASSED] rounding2
[22:14:49] [PASSED] rounding3
[22:14:49] [PASSED] rounding4
[22:14:49] =========== [PASSED] drm_test_check_plane_state ============
[22:14:49] =========== drm_test_check_invalid_plane_state  ============
[22:14:49] [PASSED] positioning_invalid
[22:14:49] [PASSED] upscaling_invalid
[22:14:49] [PASSED] downscaling_invalid
[22:14:49] ======= [PASSED] drm_test_check_invalid_plane_state ========
[22:14:49] ================ [PASSED] drm_plane_helper =================
[22:14:49] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[22:14:49] ====== drm_test_connector_helper_tv_get_modes_check  =======
[22:14:49] [PASSED] None
[22:14:49] [PASSED] PAL
[22:14:49] [PASSED] NTSC
[22:14:49] [PASSED] Both, NTSC Default
[22:14:49] [PASSED] Both, PAL Default
[22:14:49] [PASSED] Both, NTSC Default, with PAL on command-line
[22:14:49] [PASSED] Both, PAL Default, with NTSC on command-line
[22:14:49] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[22:14:49] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[22:14:49] ================== drm_rect (9 subtests) ===================
[22:14:49] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[22:14:49] [PASSED] drm_test_rect_clip_scaled_not_clipped
[22:14:49] [PASSED] drm_test_rect_clip_scaled_clipped
[22:14:49] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[22:14:49] ================= drm_test_rect_intersect  =================
[22:14:49] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[22:14:49] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[22:14:49] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[22:14:49] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[22:14:49] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[22:14:49] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[22:14:49] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[22:14:49] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[22:14:49] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[22:14:49] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[22:14:49] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[22:14:49] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[22:14:49] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[22:14:49] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[22:14:49] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[22:14:49] ============= [PASSED] drm_test_rect_intersect =============
[22:14:49] ================ drm_test_rect_calc_hscale  ================
[22:14:49] [PASSED] normal use
[22:14:49] [PASSED] out of max range
[22:14:49] [PASSED] out of min range
[22:14:49] [PASSED] zero dst
[22:14:49] [PASSED] negative src
[22:14:49] [PASSED] negative dst
[22:14:49] ============ [PASSED] drm_test_rect_calc_hscale ============
[22:14:49] ================ drm_test_rect_calc_vscale  ================
[22:14:49] [PASSED] normal use
[22:14:49] [PASSED] out of max range
[22:14:49] [PASSED] out of min range
[22:14:49] [PASSED] zero dst
[22:14:49] [PASSED] negative src
[22:14:49] [PASSED] negative dst
[22:14:49] ============ [PASSED] drm_test_rect_calc_vscale ============
[22:14:49] ================== drm_test_rect_rotate  ===================
[22:14:49] [PASSED] reflect-x
[22:14:49] [PASSED] reflect-y
[22:14:49] [PASSED] rotate-0
[22:14:49] [PASSED] rotate-90
[22:14:49] [PASSED] rotate-180
[22:14:49] [PASSED] rotate-270
[22:14:49] ============== [PASSED] drm_test_rect_rotate ===============
[22:14:49] ================ drm_test_rect_rotate_inv  =================
[22:14:49] [PASSED] reflect-x
[22:14:49] [PASSED] reflect-y
[22:14:49] [PASSED] rotate-0
[22:14:49] [PASSED] rotate-90
[22:14:49] [PASSED] rotate-180
[22:14:49] [PASSED] rotate-270
[22:14:49] ============ [PASSED] drm_test_rect_rotate_inv =============
[22:14:49] ==================== [PASSED] drm_rect =====================
[22:14:49] ============ drm_sysfb_modeset_test (1 subtest) ============
[22:14:49] ============ drm_test_sysfb_build_fourcc_list  =============
[22:14:49] [PASSED] no native formats
[22:14:49] [PASSED] XRGB8888 as native format
[22:14:49] [PASSED] remove duplicates
[22:14:49] [PASSED] convert alpha formats
[22:14:49] [PASSED] random formats
[22:14:49] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[22:14:49] ============= [PASSED] drm_sysfb_modeset_test ==============
[22:14:49] ================== drm_fixp (2 subtests) ===================
[22:14:49] [PASSED] drm_test_int2fixp
[22:14:49] [PASSED] drm_test_sm2fixp
[22:14:49] ==================== [PASSED] drm_fixp =====================
[22:14:49] ============================================================
[22:14:49] Testing complete. Ran 621 tests: passed: 621
[22:14:49] Elapsed time: 35.937s total, 1.851s configuring, 33.870s building, 0.169s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[22:14:49] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[22:14:51] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[22:15:04] Starting KUnit Kernel (1/1)...
[22:15:04] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[22:15:04] ================= ttm_device (5 subtests) ==================
[22:15:04] [PASSED] ttm_device_init_basic
[22:15:04] [PASSED] ttm_device_init_multiple
[22:15:04] [PASSED] ttm_device_fini_basic
[22:15:04] [PASSED] ttm_device_init_no_vma_man
[22:15:04] ================== ttm_device_init_pools  ==================
[22:15:04] [PASSED] No DMA allocations, no DMA32 required
[22:15:04] [PASSED] DMA allocations, DMA32 required
[22:15:04] [PASSED] No DMA allocations, DMA32 required
[22:15:04] [PASSED] DMA allocations, no DMA32 required
[22:15:04] ============== [PASSED] ttm_device_init_pools ==============
[22:15:04] =================== [PASSED] ttm_device ====================
[22:15:04] ================== ttm_pool (8 subtests) ===================
[22:15:04] ================== ttm_pool_alloc_basic  ===================
[22:15:04] [PASSED] One page
[22:15:04] [PASSED] More than one page
[22:15:04] [PASSED] Above the allocation limit
[22:15:04] [PASSED] One page, with coherent DMA mappings enabled
[22:15:04] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[22:15:04] ============== [PASSED] ttm_pool_alloc_basic ===============
[22:15:04] ============== ttm_pool_alloc_basic_dma_addr  ==============
[22:15:04] [PASSED] One page
[22:15:04] [PASSED] More than one page
[22:15:04] [PASSED] Above the allocation limit
[22:15:04] [PASSED] One page, with coherent DMA mappings enabled
[22:15:04] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[22:15:04] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[22:15:04] [PASSED] ttm_pool_alloc_order_caching_match
[22:15:04] [PASSED] ttm_pool_alloc_caching_mismatch
[22:15:04] [PASSED] ttm_pool_alloc_order_mismatch
[22:15:04] [PASSED] ttm_pool_free_dma_alloc
[22:15:04] [PASSED] ttm_pool_free_no_dma_alloc
[22:15:04] [PASSED] ttm_pool_fini_basic
[22:15:04] ==================== [PASSED] ttm_pool =====================
[22:15:04] ================ ttm_resource (8 subtests) =================
[22:15:04] ================= ttm_resource_init_basic  =================
[22:15:04] [PASSED] Init resource in TTM_PL_SYSTEM
[22:15:04] [PASSED] Init resource in TTM_PL_VRAM
[22:15:04] [PASSED] Init resource in a private placement
[22:15:04] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[22:15:04] ============= [PASSED] ttm_resource_init_basic =============
[22:15:04] [PASSED] ttm_resource_init_pinned
[22:15:04] [PASSED] ttm_resource_fini_basic
[22:15:04] [PASSED] ttm_resource_manager_init_basic
[22:15:04] [PASSED] ttm_resource_manager_usage_basic
[22:15:04] [PASSED] ttm_resource_manager_set_used_basic
[22:15:04] [PASSED] ttm_sys_man_alloc_basic
[22:15:04] [PASSED] ttm_sys_man_free_basic
[22:15:04] ================== [PASSED] ttm_resource ===================
[22:15:04] =================== ttm_tt (15 subtests) ===================
[22:15:04] ==================== ttm_tt_init_basic  ====================
[22:15:04] [PASSED] Page-aligned size
[22:15:04] [PASSED] Extra pages requested
[22:15:04] ================ [PASSED] ttm_tt_init_basic ================
[22:15:04] [PASSED] ttm_tt_init_misaligned
[22:15:04] [PASSED] ttm_tt_fini_basic
[22:15:04] [PASSED] ttm_tt_fini_sg
[22:15:04] [PASSED] ttm_tt_fini_shmem
[22:15:04] [PASSED] ttm_tt_create_basic
[22:15:04] [PASSED] ttm_tt_create_invalid_bo_type
[22:15:04] [PASSED] ttm_tt_create_ttm_exists
[22:15:04] [PASSED] ttm_tt_create_failed
[22:15:04] [PASSED] ttm_tt_destroy_basic
[22:15:04] [PASSED] ttm_tt_populate_null_ttm
[22:15:04] [PASSED] ttm_tt_populate_populated_ttm
[22:15:04] [PASSED] ttm_tt_unpopulate_basic
[22:15:04] [PASSED] ttm_tt_unpopulate_empty_ttm
[22:15:04] [PASSED] ttm_tt_swapin_basic
[22:15:04] ===================== [PASSED] ttm_tt ======================
[22:15:04] =================== ttm_bo (14 subtests) ===================
[22:15:04] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[22:15:04] [PASSED] Cannot be interrupted and sleeps
[22:15:04] [PASSED] Cannot be interrupted, locks straight away
[22:15:04] [PASSED] Can be interrupted, sleeps
[22:15:04] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[22:15:04] [PASSED] ttm_bo_reserve_locked_no_sleep
[22:15:04] [PASSED] ttm_bo_reserve_no_wait_ticket
[22:15:04] [PASSED] ttm_bo_reserve_double_resv
[22:15:04] [PASSED] ttm_bo_reserve_interrupted
[22:15:04] [PASSED] ttm_bo_reserve_deadlock
[22:15:04] [PASSED] ttm_bo_unreserve_basic
[22:15:04] [PASSED] ttm_bo_unreserve_pinned
[22:15:04] [PASSED] ttm_bo_unreserve_bulk
[22:15:04] [PASSED] ttm_bo_fini_basic
[22:15:04] [PASSED] ttm_bo_fini_shared_resv
[22:15:04] [PASSED] ttm_bo_pin_basic
[22:15:04] [PASSED] ttm_bo_pin_unpin_resource
[22:15:04] [PASSED] ttm_bo_multiple_pin_one_unpin
[22:15:04] ===================== [PASSED] ttm_bo ======================
[22:15:04] ============== ttm_bo_validate (22 subtests) ===============
[22:15:04] ============== ttm_bo_init_reserved_sys_man  ===============
[22:15:04] [PASSED] Buffer object for userspace
[22:15:04] [PASSED] Kernel buffer object
[22:15:04] [PASSED] Shared buffer object
[22:15:04] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[22:15:04] ============== ttm_bo_init_reserved_mock_man  ==============
[22:15:04] [PASSED] Buffer object for userspace
[22:15:04] [PASSED] Kernel buffer object
[22:15:04] [PASSED] Shared buffer object
[22:15:04] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[22:15:04] [PASSED] ttm_bo_init_reserved_resv
[22:15:04] ================== ttm_bo_validate_basic  ==================
[22:15:04] [PASSED] Buffer object for userspace
[22:15:04] [PASSED] Kernel buffer object
[22:15:04] [PASSED] Shared buffer object
[22:15:04] ============== [PASSED] ttm_bo_validate_basic ==============
[22:15:04] [PASSED] ttm_bo_validate_invalid_placement
[22:15:04] ============= ttm_bo_validate_same_placement  ==============
[22:15:04] [PASSED] System manager
[22:15:04] [PASSED] VRAM manager
[22:15:04] ========= [PASSED] ttm_bo_validate_same_placement ==========
[22:15:04] [PASSED] ttm_bo_validate_failed_alloc
[22:15:04] [PASSED] ttm_bo_validate_pinned
[22:15:04] [PASSED] ttm_bo_validate_busy_placement
[22:15:04] ================ ttm_bo_validate_multihop  =================
[22:15:04] [PASSED] Buffer object for userspace
[22:15:04] [PASSED] Kernel buffer object
[22:15:04] [PASSED] Shared buffer object
[22:15:04] ============ [PASSED] ttm_bo_validate_multihop =============
[22:15:04] ========== ttm_bo_validate_no_placement_signaled  ==========
[22:15:04] [PASSED] Buffer object in system domain, no page vector
[22:15:04] [PASSED] Buffer object in system domain with an existing page vector
[22:15:04] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[22:15:04] ======== ttm_bo_validate_no_placement_not_signaled  ========
[22:15:04] [PASSED] Buffer object for userspace
[22:15:04] [PASSED] Kernel buffer object
[22:15:04] [PASSED] Shared buffer object
[22:15:04] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[22:15:04] [PASSED] ttm_bo_validate_move_fence_signaled
[22:15:04] ========= ttm_bo_validate_move_fence_not_signaled  =========
[22:15:04] [PASSED] Waits for GPU
[22:15:04] [PASSED] Tries to lock straight away
[22:15:04] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[22:15:04] [PASSED] ttm_bo_validate_swapout
[22:15:04] [PASSED] ttm_bo_validate_happy_evict
[22:15:04] [PASSED] ttm_bo_validate_all_pinned_evict
[22:15:04] [PASSED] ttm_bo_validate_allowed_only_evict
[22:15:04] [PASSED] ttm_bo_validate_deleted_evict
[22:15:04] [PASSED] ttm_bo_validate_busy_domain_evict
[22:15:04] [PASSED] ttm_bo_validate_evict_gutting
[22:15:04] [PASSED] ttm_bo_validate_recrusive_evict
[22:15:04] ================= [PASSED] ttm_bo_validate =================
[22:15:04] ============================================================
[22:15:04] Testing complete. Ran 102 tests: passed: 102
[22:15:04] Elapsed time: 14.988s total, 2.361s configuring, 12.362s building, 0.225s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for drm/i915/bw: Split bandwidth params into platform- and display-IP-specific structs

[Patchwork]

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== Series Details ==

Series: drm/i915/bw: Split bandwidth params into platform- and display-IP-specific structs
URL   : https://patchwork.freedesktop.org/series/166340/
State : success

== Summary ==

CI Bug Log - changes from xe-5042-311a7de0a4e360124ba1abb933df42b021ef8b9d_BAT -> xe-pw-166340v1_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 13)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * Linux: xe-5042-311a7de0a4e360124ba1abb933df42b021ef8b9d -> xe-pw-166340v1

  IGT_8903: 6f88532e2fe22529195cc2f8cabff93d994688f8 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-5042-311a7de0a4e360124ba1abb933df42b021ef8b9d: 311a7de0a4e360124ba1abb933df42b021ef8b9d
  xe-pw-166340v1: 166340v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/index.html

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✗ Xe.CI.FULL: failure for drm/i915/bw: Split bandwidth params into platform- and display-IP-specific structs

[Patchwork]

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== Series Details ==

Series: drm/i915/bw: Split bandwidth params into platform- and display-IP-specific structs
URL   : https://patchwork.freedesktop.org/series/166340/
State : failure

== Summary ==

CI Bug Log - changes from xe-5042-311a7de0a4e360124ba1abb933df42b021ef8b9d_FULL -> xe-pw-166340v1_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-166340v1_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-166340v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-166340v1_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@xe_copy_basic@mem-page-copy-17:
    - shard-bmg:          NOTRUN -> [ABORT][1]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-bmg-5/igt@xe_copy_basic@mem-page-copy-17.html

  
Known issues
------------

  Here are the changes found in xe-pw-166340v1_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
    - shard-lnl:          NOTRUN -> [SKIP][2] ([Intel XE#3658] / [Intel XE#7360])
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-lnl:          NOTRUN -> [SKIP][3] ([Intel XE#1124]) +5 other tests skip
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_bw@connected-linear-tiling-4-displays-target-2160x1440p:
    - shard-lnl:          NOTRUN -> [SKIP][4] ([Intel XE#7676])
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@kms_bw@connected-linear-tiling-4-displays-target-2160x1440p.html

  * igt@kms_bw@linear-tiling-3-displays-target-2560x1440p:
    - shard-lnl:          NOTRUN -> [SKIP][5] ([Intel XE#367])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@kms_bw@linear-tiling-3-displays-target-2560x1440p.html

  * igt@kms_ccs@bad-pixel-format-yf-tiled-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][6] ([Intel XE#2887]) +7 other tests skip
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@kms_ccs@bad-pixel-format-yf-tiled-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-a-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][7] ([Intel XE#2669] / [Intel XE#3433] / [Intel XE#7389]) +3 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-a-edp-1.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-d-hdmi-a-3:
    - shard-bmg:          NOTRUN -> [INCOMPLETE][8] ([Intel XE#7084])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-bmg-10/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-d-hdmi-a-3.html

  * igt@kms_chamelium_color@degamma:
    - shard-lnl:          NOTRUN -> [SKIP][9] ([Intel XE#306] / [Intel XE#7358])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@kms_chamelium_color@degamma.html

  * igt@kms_chamelium_edid@hdmi-edid-read:
    - shard-lnl:          NOTRUN -> [SKIP][10] ([Intel XE#373]) +2 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@kms_chamelium_edid@hdmi-edid-read.html

  * igt@kms_content_protection@dp-mst-type-1-suspend-resume:
    - shard-lnl:          NOTRUN -> [SKIP][11] ([Intel XE#6974])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@kms_content_protection@dp-mst-type-1-suspend-resume.html

  * igt@kms_content_protection@uevent:
    - shard-lnl:          NOTRUN -> [SKIP][12] ([Intel XE#7642]) +1 other test skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@kms_content_protection@uevent.html

  * igt@kms_cursor_crc@cursor-random-32x32:
    - shard-lnl:          NOTRUN -> [SKIP][13] ([Intel XE#1424])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@kms_cursor_crc@cursor-random-32x32.html

  * igt@kms_cursor_crc@cursor-random-512x170:
    - shard-lnl:          NOTRUN -> [SKIP][14] ([Intel XE#2321] / [Intel XE#7355])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@kms_cursor_crc@cursor-random-512x170.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size:
    - shard-lnl:          NOTRUN -> [SKIP][15] ([Intel XE#309] / [Intel XE#7343]) +2 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html

  * igt@kms_dp_link_training@non-uhbr-sst:
    - shard-lnl:          NOTRUN -> [SKIP][16] ([Intel XE#4354] / [Intel XE#7450])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@kms_dp_link_training@non-uhbr-sst.html

  * igt@kms_dp_linktrain_fallback@dp-fallback:
    - shard-lnl:          NOTRUN -> [SKIP][17] ([Intel XE#4294] / [Intel XE#7477])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@kms_dp_linktrain_fallback@dp-fallback.html

  * igt@kms_dsc@dsc-with-bpc:
    - shard-lnl:          NOTRUN -> [SKIP][18] ([Intel XE#2244])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@kms_dsc@dsc-with-bpc.html

  * igt@kms_flip@2x-flip-vs-suspend-interruptible:
    - shard-lnl:          NOTRUN -> [SKIP][19] ([Intel XE#1421]) +4 other tests skip
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@kms_flip@2x-flip-vs-suspend-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-linear-to-32bpp-linear-reflect-x:
    - shard-lnl:          NOTRUN -> [SKIP][20] ([Intel XE#7179])
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@kms_flip_scaled_crc@flip-32bpp-linear-to-32bpp-linear-reflect-x.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling:
    - shard-lnl:          NOTRUN -> [SKIP][21] ([Intel XE#7178] / [Intel XE#7351]) +1 other test skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-lnl:          NOTRUN -> [SKIP][22] ([Intel XE#6312] / [Intel XE#651]) +5 other tests skip
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-modesetfrombusy:
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#4141])
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-modesetfrombusy.html

  * igt@kms_frontbuffer_tracking@fbcdrrshdr-1p-pri-indfb-multidraw:
    - shard-lnl:          NOTRUN -> [SKIP][24] ([Intel XE#6312]) +6 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@kms_frontbuffer_tracking@fbcdrrshdr-1p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@fbcdrrshdr-2p-scndscrn-cur-indfb-draw-render:
    - shard-lnl:          NOTRUN -> [SKIP][25] ([Intel XE#7905]) +23 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@kms_frontbuffer_tracking@fbcdrrshdr-2p-scndscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][26] ([Intel XE#2313])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-argb161616f-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][27] ([Intel XE#7061] / [Intel XE#7356]) +3 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@kms_frontbuffer_tracking@fbcpsr-argb161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@hdr-rgb565-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][28] ([Intel XE#7865]) +13 other tests skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@kms_frontbuffer_tracking@hdr-rgb565-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-render:
    - shard-lnl:          NOTRUN -> [SKIP][29] ([Intel XE#656] / [Intel XE#7905]) +19 other tests skip
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psrhdr-abgr161616f-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][30] ([Intel XE#7061]) +1 other test skip
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@kms_frontbuffer_tracking@psrhdr-abgr161616f-draw-blt.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [PASS][31] -> [SKIP][32] ([Intel XE#1503])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5042-311a7de0a4e360124ba1abb933df42b021ef8b9d/shard-bmg-1/igt@kms_hdr@invalid-hdr.html
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-bmg-9/igt@kms_hdr@invalid-hdr.html

  * igt@kms_hdr@invalid-hdr@pipe-a-hdmi-a-3-xrgb2101010:
    - shard-bmg:          [PASS][33] -> [SKIP][34] ([Intel XE#7922]) +1 other test skip
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5042-311a7de0a4e360124ba1abb933df42b021ef8b9d/shard-bmg-1/igt@kms_hdr@invalid-hdr@pipe-a-hdmi-a-3-xrgb2101010.html
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-bmg-9/igt@kms_hdr@invalid-hdr@pipe-a-hdmi-a-3-xrgb2101010.html

  * igt@kms_hdr@static-swap:
    - shard-lnl:          NOTRUN -> [SKIP][35] ([Intel XE#1503] / [Intel XE#7915])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@kms_hdr@static-swap.html

  * igt@kms_hdr@static-swap@pipe-a-edp-1-xrgb2101010:
    - shard-lnl:          NOTRUN -> [SKIP][36] ([Intel XE#7915]) +1 other test skip
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@kms_hdr@static-swap@pipe-a-edp-1-xrgb2101010.html

  * igt@kms_hdr@static-swap@pipe-a-hdmi-a-3-xrgb2101010:
    - shard-bmg:          [PASS][37] -> [SKIP][38] ([Intel XE#7915]) +3 other tests skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5042-311a7de0a4e360124ba1abb933df42b021ef8b9d/shard-bmg-4/igt@kms_hdr@static-swap@pipe-a-hdmi-a-3-xrgb2101010.html
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-bmg-8/igt@kms_hdr@static-swap@pipe-a-hdmi-a-3-xrgb2101010.html

  * igt@kms_joiner@basic-big-joiner:
    - shard-lnl:          NOTRUN -> [SKIP][39] ([Intel XE#6901])
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@kms_joiner@basic-big-joiner.html

  * igt@kms_pipe_stress@stress-xrgb8888-ytiled:
    - shard-lnl:          NOTRUN -> [SKIP][40] ([Intel XE#4329] / [Intel XE#6912] / [Intel XE#7375])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@kms_pipe_stress@stress-xrgb8888-ytiled.html

  * igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier-source-clamping:
    - shard-lnl:          NOTRUN -> [SKIP][41] ([Intel XE#7283]) +3 other tests skip
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier-source-clamping.html

  * igt@kms_plane_multiple@tiling-yf:
    - shard-lnl:          NOTRUN -> [SKIP][42] ([Intel XE#5020] / [Intel XE#7348])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@kms_plane_multiple@tiling-yf.html

  * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b:
    - shard-lnl:          NOTRUN -> [SKIP][43] ([Intel XE#2763] / [Intel XE#6886]) +1 other test skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf:
    - shard-lnl:          NOTRUN -> [SKIP][44] ([Intel XE#2893] / [Intel XE#4608] / [Intel XE#7304])
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf@pipe-a-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][45] ([Intel XE#4608])
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf@pipe-a-edp-1.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf@pipe-b-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][46] ([Intel XE#4608] / [Intel XE#7304])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf@pipe-b-edp-1.html

  * igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area:
    - shard-lnl:          NOTRUN -> [SKIP][47] ([Intel XE#2893] / [Intel XE#7304]) +1 other test skip
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area.html

  * igt@kms_psr@fbc-psr2-sprite-plane-onoff:
    - shard-lnl:          NOTRUN -> [SKIP][48] ([Intel XE#1406] / [Intel XE#7345]) +1 other test skip
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@kms_psr@fbc-psr2-sprite-plane-onoff.html

  * igt@kms_psr@fbc-psr2-sprite-plane-onoff@edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][49] ([Intel XE#1406] / [Intel XE#4609]) +1 other test skip
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@kms_psr@fbc-psr2-sprite-plane-onoff@edp-1.html

  * igt@kms_psr@pr-sprite-plane-onoff:
    - shard-lnl:          NOTRUN -> [SKIP][50] ([Intel XE#1406]) +2 other tests skip
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@kms_psr@pr-sprite-plane-onoff.html

  * igt@kms_rotation_crc@primary-rotation-270:
    - shard-lnl:          NOTRUN -> [SKIP][51] ([Intel XE#3414] / [Intel XE#3904] / [Intel XE#7342]) +1 other test skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@kms_rotation_crc@primary-rotation-270.html

  * igt@kms_setmode@clone-exclusive-crtc:
    - shard-lnl:          NOTRUN -> [SKIP][52] ([Intel XE#1435])
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@kms_setmode@clone-exclusive-crtc.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-lnl:          NOTRUN -> [SKIP][53] ([Intel XE#362] / [Intel XE#5848])
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_vrr@seamless-rr-switch-vrr:
    - shard-lnl:          NOTRUN -> [SKIP][54] ([Intel XE#1499])
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@kms_vrr@seamless-rr-switch-vrr.html

  * igt@xe_ccs@vm-bind-decompress:
    - shard-lnl:          NOTRUN -> [SKIP][55] ([Intel XE#7644])
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@xe_ccs@vm-bind-decompress.html

  * igt@xe_eudebug@basic-close:
    - shard-lnl:          NOTRUN -> [SKIP][56] ([Intel XE#7636]) +6 other tests skip
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@xe_eudebug@basic-close.html

  * igt@xe_evict@evict-large-external-cm:
    - shard-lnl:          NOTRUN -> [SKIP][57] ([Intel XE#6540] / [Intel XE#688]) +5 other tests skip
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@xe_evict@evict-large-external-cm.html

  * igt@xe_exec_balancer@once-parallel-userptr:
    - shard-lnl:          NOTRUN -> [SKIP][58] ([Intel XE#7482]) +8 other tests skip
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@xe_exec_balancer@once-parallel-userptr.html

  * igt@xe_exec_basic@multigpu-no-exec-userptr:
    - shard-lnl:          NOTRUN -> [SKIP][59] ([Intel XE#1392]) +4 other tests skip
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@xe_exec_basic@multigpu-no-exec-userptr.html

  * igt@xe_exec_fault_mode@many-multi-queue-userptr-prefetch:
    - shard-lnl:          NOTRUN -> [SKIP][60] ([Intel XE#7136]) +3 other tests skip
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@xe_exec_fault_mode@many-multi-queue-userptr-prefetch.html

  * igt@xe_exec_multi_queue@many-execs-priority:
    - shard-lnl:          NOTRUN -> [SKIP][61] ([Intel XE#6874]) +15 other tests skip
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@xe_exec_multi_queue@many-execs-priority.html

  * igt@xe_exec_reset@multi-queue-close-execqueues:
    - shard-lnl:          NOTRUN -> [SKIP][62] ([Intel XE#7866])
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@xe_exec_reset@multi-queue-close-execqueues.html

  * igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-comp-multi-vma:
    - shard-lnl:          NOTRUN -> [SKIP][63] ([Intel XE#6196])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-comp-multi-vma.html

  * igt@xe_exec_threads@threads-multi-queue-cm-shared-vm-basic:
    - shard-lnl:          NOTRUN -> [SKIP][64] ([Intel XE#7138]) +4 other tests skip
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@xe_exec_threads@threads-multi-queue-cm-shared-vm-basic.html

  * igt@xe_multigpu_svm@mgpu-coherency-fail-basic:
    - shard-lnl:          NOTRUN -> [SKIP][65] ([Intel XE#6964])
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@xe_multigpu_svm@mgpu-coherency-fail-basic.html

  * igt@xe_page_reclaim@basic-mixed:
    - shard-lnl:          NOTRUN -> [SKIP][66] ([Intel XE#7793])
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@xe_page_reclaim@basic-mixed.html

  * igt@xe_pat@pat-sw-hw-reset-compare:
    - shard-lnl:          NOTRUN -> [FAIL][67] ([Intel XE#7695])
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@xe_pat@pat-sw-hw-reset-compare.html

  * igt@xe_query@multigpu-query-invalid-size:
    - shard-lnl:          NOTRUN -> [SKIP][68] ([Intel XE#944]) +2 other tests skip
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@xe_query@multigpu-query-invalid-size.html

  * igt@xe_sriov_admin@bulk-sched-priority-vfs-disabled:
    - shard-lnl:          NOTRUN -> [SKIP][69] ([Intel XE#7174])
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@xe_sriov_admin@bulk-sched-priority-vfs-disabled.html

  * igt@xe_sriov_flr@flr-vfs-parallel:
    - shard-lnl:          NOTRUN -> [SKIP][70] ([Intel XE#4273])
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@xe_sriov_flr@flr-vfs-parallel.html

  * igt@xe_sriov_vfio@region-info:
    - shard-lnl:          NOTRUN -> [SKIP][71] ([Intel XE#7724])
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-2/igt@xe_sriov_vfio@region-info.html

  
#### Possible fixes ####

  * igt@fbdev@unaligned-write:
    - shard-bmg:          [FAIL][72] ([Intel XE#7950]) -> [PASS][73]
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5042-311a7de0a4e360124ba1abb933df42b021ef8b9d/shard-bmg-2/igt@fbdev@unaligned-write.html
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-bmg-2/igt@fbdev@unaligned-write.html

  * igt@kms_atomic_transition@plane-primary-toggle-with-vblank-wait:
    - shard-bmg:          [ABORT][74] ([Intel XE#5545] / [Intel XE#7814]) -> [PASS][75] +1 other test pass
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5042-311a7de0a4e360124ba1abb933df42b021ef8b9d/shard-bmg-2/igt@kms_atomic_transition@plane-primary-toggle-with-vblank-wait.html
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-bmg-2/igt@kms_atomic_transition@plane-primary-toggle-with-vblank-wait.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-d-dp-2:
    - shard-bmg:          [INCOMPLETE][76] ([Intel XE#7084]) -> [PASS][77]
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5042-311a7de0a4e360124ba1abb933df42b021ef8b9d/shard-bmg-3/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-d-dp-2.html
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-bmg-10/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-d-dp-2.html

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
    - shard-bmg:          [FAIL][78] ([Intel XE#7571]) -> [PASS][79]
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5042-311a7de0a4e360124ba1abb933df42b021ef8b9d/shard-bmg-5/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-bmg-1/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

  * igt@kms_flip@wf_vblank-ts-check-interruptible@a-edp1:
    - shard-lnl:          [FAIL][80] ([Intel XE#3098]) -> [PASS][81] +1 other test pass
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5042-311a7de0a4e360124ba1abb933df42b021ef8b9d/shard-lnl-1/igt@kms_flip@wf_vblank-ts-check-interruptible@a-edp1.html
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-7/igt@kms_flip@wf_vblank-ts-check-interruptible@a-edp1.html

  * igt@xe_exec_reset@long-spin-reuse-many-preempt-gt0-threads:
    - shard-bmg:          [FAIL][82] -> [PASS][83]
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5042-311a7de0a4e360124ba1abb933df42b021ef8b9d/shard-bmg-2/igt@xe_exec_reset@long-spin-reuse-many-preempt-gt0-threads.html
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-bmg-3/igt@xe_exec_reset@long-spin-reuse-many-preempt-gt0-threads.html

  * igt@xe_module_load@reload:
    - shard-bmg:          [DMESG-WARN][84] -> [PASS][85]
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5042-311a7de0a4e360124ba1abb933df42b021ef8b9d/shard-bmg-2/igt@xe_module_load@reload.html
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-bmg-2/igt@xe_module_load@reload.html

  * igt@xe_survivability@runtime-survivability:
    - shard-bmg:          [DMESG-WARN][86] ([Intel XE#6627] / [Intel XE#7419]) -> [PASS][87]
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5042-311a7de0a4e360124ba1abb933df42b021ef8b9d/shard-bmg-6/igt@xe_survivability@runtime-survivability.html
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-bmg-2/igt@xe_survivability@runtime-survivability.html

  * igt@xe_sysfs_scheduler@preempt_timeout_us-invalid-string:
    - shard-bmg:          [SKIP][88] ([Intel XE#6703]) -> [PASS][89] +88 other tests pass
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5042-311a7de0a4e360124ba1abb933df42b021ef8b9d/shard-bmg-2/igt@xe_sysfs_scheduler@preempt_timeout_us-invalid-string.html
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-bmg-2/igt@xe_sysfs_scheduler@preempt_timeout_us-invalid-string.html

  * igt@xe_wedged@wedged-mode-toggle:
    - shard-bmg:          [ABORT][90] ([Intel XE#7914]) -> [PASS][91]
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5042-311a7de0a4e360124ba1abb933df42b021ef8b9d/shard-bmg-10/igt@xe_wedged@wedged-mode-toggle.html
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-bmg-5/igt@xe_wedged@wedged-mode-toggle.html

  
#### Warnings ####

  * igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-bmg:          [SKIP][92] ([Intel XE#6703]) -> [SKIP][93] ([Intel XE#7059] / [Intel XE#7085])
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5042-311a7de0a4e360124ba1abb933df42b021ef8b9d/shard-bmg-2/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180-hflip.html
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-bmg-2/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - shard-bmg:          [SKIP][94] ([Intel XE#6703]) -> [SKIP][95] ([Intel XE#1124]) +1 other test skip
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5042-311a7de0a4e360124ba1abb933df42b021ef8b9d/shard-bmg-2/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-bmg-2/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_bw@connected-linear-tiling-4-displays-target-2560x1440p:
    - shard-bmg:          [SKIP][96] ([Intel XE#6703]) -> [SKIP][97] ([Intel XE#7679])
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5042-311a7de0a4e360124ba1abb933df42b021ef8b9d/shard-bmg-2/igt@kms_bw@connected-linear-tiling-4-displays-target-2560x1440p.html
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-bmg-2/igt@kms_bw@connected-linear-tiling-4-displays-target-2560x1440p.html

  * igt@kms_ccs@bad-aux-stride-yf-tiled-ccs:
    - shard-bmg:          [SKIP][98] ([Intel XE#6703]) -> [SKIP][99] ([Intel XE#2887]) +2 other tests skip
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5042-311a7de0a4e360124ba1abb933df42b021ef8b9d/shard-bmg-2/igt@kms_ccs@bad-aux-stride-yf-tiled-ccs.html
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-bmg-2/igt@kms_ccs@bad-aux-stride-yf-tiled-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs:
    - shard-bmg:          [SKIP][100] ([Intel XE#6703]) -> [SKIP][101] ([Intel XE#3432])
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5042-311a7de0a4e360124ba1abb933df42b021ef8b9d/shard-bmg-2/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs.html
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-bmg-2/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs.html

  * igt@kms_chamelium_frames@dp-crc-single:
    - shard-bmg:          [SKIP][102] ([Intel XE#6703]) -> [SKIP][103] ([Intel XE#2252])
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5042-311a7de0a4e360124ba1abb933df42b021ef8b9d/shard-bmg-2/igt@kms_chamelium_frames@dp-crc-single.html
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-bmg-2/igt@kms_chamelium_frames@dp-crc-single.html

  * igt@kms_content_protection@dp-mst-type-0:
    - shard-bmg:          [SKIP][104] ([Intel XE#6703]) -> [SKIP][105] ([Intel XE#2390] / [Intel XE#6974])
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5042-311a7de0a4e360124ba1abb933df42b021ef8b9d/shard-bmg-2/igt@kms_content_protection@dp-mst-type-0.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-bmg-2/igt@kms_content_protection@dp-mst-type-0.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions:
    - shard-lnl:          [SKIP][106] ([Intel XE#309] / [Intel XE#7343]) -> [SKIP][107] ([Intel XE#309] / [Intel XE#7343] / [Intel XE#7935])
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5042-311a7de0a4e360124ba1abb933df42b021ef8b9d/shard-lnl-4/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-lnl-8/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html

  * igt@kms_dsc@dsc-with-formats:
    - shard-bmg:          [SKIP][108] ([Intel XE#6703]) -> [SKIP][109] ([Intel XE#2244])
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5042-311a7de0a4e360124ba1abb933df42b021ef8b9d/shard-bmg-2/igt@kms_dsc@dsc-with-formats.html
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-bmg-2/igt@kms_dsc@dsc-with-formats.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling:
    - shard-bmg:          [SKIP][110] ([Intel XE#6703]) -> [SKIP][111] ([Intel XE#7178] / [Intel XE#7351])
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5042-311a7de0a4e360124ba1abb933df42b021ef8b9d/shard-bmg-2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-bmg-2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][112] ([Intel XE#6703]) -> [SKIP][113] ([Intel XE#4141])
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5042-311a7de0a4e360124ba1abb933df42b021ef8b9d/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-wc.html
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcdrrshdr-2p-primscrn-shrfb-msflip-blt:
    - shard-bmg:          [SKIP][114] ([Intel XE#6703]) -> [SKIP][115] ([Intel XE#2311]) +8 other tests skip
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5042-311a7de0a4e360124ba1abb933df42b021ef8b9d/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcdrrshdr-2p-primscrn-shrfb-msflip-blt.html
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcdrrshdr-2p-primscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][116] ([Intel XE#6703]) -> [SKIP][117] ([Intel XE#2313]) +9 other tests skip
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5042-311a7de0a4e360124ba1abb933df42b021ef8b9d/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc.html
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@hdr-argb161616f-draw-render:
    - shard-bmg:          [SKIP][118] ([Intel XE#6703]) -> [SKIP][119] ([Intel XE#7061]) +1 other test skip
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5042-311a7de0a4e360124ba1abb933df42b021ef8b9d/shard-bmg-2/igt@kms_frontbuffer_tracking@hdr-argb161616f-draw-render.html
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-bmg-2/igt@kms_frontbuffer_tracking@hdr-argb161616f-draw-render.html

  * igt@kms_plane@pixel-format-y-tiled-ccs-modifier:
    - shard-bmg:          [SKIP][120] ([Intel XE#6703]) -> [SKIP][121] ([Intel XE#7283]) +1 other test skip
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5042-311a7de0a4e360124ba1abb933df42b021ef8b9d/shard-bmg-2/igt@kms_plane@pixel-format-y-tiled-ccs-modifier.html
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-bmg-2/igt@kms_plane@pixel-format-y-tiled-ccs-modifier.html

  * igt@kms_pm_backlight@basic-brightness:
    - shard-bmg:          [SKIP][122] ([Intel XE#6703]) -> [SKIP][123] ([Intel XE#7376] / [Intel XE#870])
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5042-311a7de0a4e360124ba1abb933df42b021ef8b9d/shard-bmg-2/igt@kms_pm_backlight@basic-brightness.html
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-bmg-2/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_psr2_sf@fbc-pr-cursor-plane-update-sf:
    - shard-bmg:          [SKIP][124] ([Intel XE#6703]) -> [SKIP][125] ([Intel XE#1489])
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5042-311a7de0a4e360124ba1abb933df42b021ef8b9d/shard-bmg-2/igt@kms_psr2_sf@fbc-pr-cursor-plane-update-sf.html
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-bmg-2/igt@kms_psr2_sf@fbc-pr-cursor-plane-update-sf.html

  * igt@kms_psr@fbc-psr-no-drrs:
    - shard-bmg:          [SKIP][126] ([Intel XE#6703]) -> [SKIP][127] ([Intel XE#2234] / [Intel XE#2850])
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5042-311a7de0a4e360124ba1abb933df42b021ef8b9d/shard-bmg-2/igt@kms_psr@fbc-psr-no-drrs.html
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-bmg-2/igt@kms_psr@fbc-psr-no-drrs.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          [FAIL][128] ([Intel XE#1729] / [Intel XE#7424]) -> [SKIP][129] ([Intel XE#2426] / [Intel XE#5848])
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5042-311a7de0a4e360124ba1abb933df42b021ef8b9d/shard-bmg-4/igt@kms_tiled_display@basic-test-pattern.html
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-bmg-8/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          [SKIP][130] ([Intel XE#2426] / [Intel XE#5848]) -> [SKIP][131] ([Intel XE#2509] / [Intel XE#7437])
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5042-311a7de0a4e360124ba1abb933df42b021ef8b9d/shard-bmg-3/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-bmg-6/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@xe_eudebug_online@single-step-one:
    - shard-bmg:          [SKIP][132] ([Intel XE#6703]) -> [SKIP][133] ([Intel XE#7636]) +1 other test skip
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5042-311a7de0a4e360124ba1abb933df42b021ef8b9d/shard-bmg-2/igt@xe_eudebug_online@single-step-one.html
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-bmg-2/igt@xe_eudebug_online@single-step-one.html

  * igt@xe_evict@evict-mixed-threads-small-multi-queue:
    - shard-bmg:          [SKIP][134] ([Intel XE#6703]) -> [SKIP][135] ([Intel XE#7140])
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5042-311a7de0a4e360124ba1abb933df42b021ef8b9d/shard-bmg-2/igt@xe_evict@evict-mixed-threads-small-multi-queue.html
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-bmg-2/igt@xe_evict@evict-mixed-threads-small-multi-queue.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-invalidate:
    - shard-bmg:          [SKIP][136] ([Intel XE#6703]) -> [SKIP][137] ([Intel XE#2322] / [Intel XE#7372]) +1 other test skip
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5042-311a7de0a4e360124ba1abb933df42b021ef8b9d/shard-bmg-2/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-invalidate.html
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-bmg-2/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-invalidate.html

  * igt@xe_exec_multi_queue@few-execs-preempt-mode-fault-userptr:
    - shard-bmg:          [SKIP][138] ([Intel XE#6703]) -> [SKIP][139] ([Intel XE#6874]) +2 other tests skip
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5042-311a7de0a4e360124ba1abb933df42b021ef8b9d/shard-bmg-2/igt@xe_exec_multi_queue@few-execs-preempt-mode-fault-userptr.html
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-bmg-2/igt@xe_exec_multi_queue@few-execs-preempt-mode-fault-userptr.html

  * igt@xe_exec_threads@threads-multi-queue-mixed-rebind:
    - shard-bmg:          [SKIP][140] ([Intel XE#6703]) -> [SKIP][141] ([Intel XE#7138])
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5042-311a7de0a4e360124ba1abb933df42b021ef8b9d/shard-bmg-2/igt@xe_exec_threads@threads-multi-queue-mixed-rebind.html
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-bmg-2/igt@xe_exec_threads@threads-multi-queue-mixed-rebind.html

  * igt@xe_pm@s2idle-d3cold-basic-exec:
    - shard-bmg:          [SKIP][142] ([Intel XE#6703]) -> [SKIP][143] ([Intel XE#2284] / [Intel XE#7370])
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5042-311a7de0a4e360124ba1abb933df42b021ef8b9d/shard-bmg-2/igt@xe_pm@s2idle-d3cold-basic-exec.html
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-bmg-2/igt@xe_pm@s2idle-d3cold-basic-exec.html

  * igt@xe_query@multigpu-query-uc-fw-version-guc:
    - shard-bmg:          [SKIP][144] ([Intel XE#6703]) -> [SKIP][145] ([Intel XE#944])
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5042-311a7de0a4e360124ba1abb933df42b021ef8b9d/shard-bmg-2/igt@xe_query@multigpu-query-uc-fw-version-guc.html
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/shard-bmg-2/igt@xe_query@multigpu-query-uc-fw-version-guc.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2390
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2669]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2669
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#3098]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3098
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#3433]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3433
  [Intel XE#362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/362
  [Intel XE#3658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3658
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4273]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4273
  [Intel XE#4294]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4294
  [Intel XE#4329]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4329
  [Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
  [Intel XE#4608]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4608
  [Intel XE#4609]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4609
  [Intel XE#5020]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5020
  [Intel XE#5545]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5545
  [Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
  [Intel XE#6196]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6196
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#6540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6540
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#6627]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6627
  [Intel XE#6703]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6703
  [Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
  [Intel XE#6901]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6901
  [Intel XE#6912]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6912
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#6974]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6974
  [Intel XE#7059]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7059
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7084]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7084
  [Intel XE#7085]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7085
  [Intel XE#7136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7136
  [Intel XE#7138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7138
  [Intel XE#7140]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7140
  [Intel XE#7174]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7174
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7179]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7179
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7304
  [Intel XE#7342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7342
  [Intel XE#7343]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7343
  [Intel XE#7345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7345
  [Intel XE#7348]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7348
  [Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
  [Intel XE#7355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7355
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
  [Intel XE#7360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7360
  [Intel XE#7370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7370
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7375]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7375
  [Intel XE#7376]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7376
  [Intel XE#7389]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7389
  [Intel XE#7419]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7419
  [Intel XE#7424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7424
  [Intel XE#7437]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7437
  [Intel XE#7450]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7450
  [Intel XE#7477]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7477
  [Intel XE#7482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7482
  [Intel XE#7571]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7571
  [Intel XE#7636]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7636
  [Intel XE#7642]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7642
  [Intel XE#7644]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7644
  [Intel XE#7676]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7676
  [Intel XE#7679]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7679
  [Intel XE#7695]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7695
  [Intel XE#7724]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7724
  [Intel XE#7793]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7793
  [Intel XE#7814]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7814
  [Intel XE#7865]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7865
  [Intel XE#7866]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7866
  [Intel XE#7905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7905
  [Intel XE#7914]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7914
  [Intel XE#7915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7915
  [Intel XE#7922]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7922
  [Intel XE#7935]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7935
  [Intel XE#7950]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7950
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-5042-311a7de0a4e360124ba1abb933df42b021ef8b9d -> xe-pw-166340v1

  IGT_8903: 6f88532e2fe22529195cc2f8cabff93d994688f8 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-5042-311a7de0a4e360124ba1abb933df42b021ef8b9d: 311a7de0a4e360124ba1abb933df42b021ef8b9d
  xe-pw-166340v1: 166340v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v1/index.html

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