Re: [Intel-xe] [PATCH] drm/xe/rtp: Fix displayed whitelisted register range

["Dixit, Ashutosh" <ashutosh.dixit@intel.com>]

On Thu, 09 Nov 2023 13:19:09 -0800, Dixit, Ashutosh wrote:
>
> On Thu, 09 Nov 2023 09:07:54 -0800, Ashutosh Dixit wrote:
> >
> > Fix displayed whitelisted register range. For example, with:
> >
> >	XE_RTP_ACTIONS(WHITELIST(0xdafc, RING_FORCE_TO_NONPRIV_RANGE_4))
> >
> > Before we would show:
> >	xe REG[0xdaf0-0xdaff]: allow read access
> >
> > With this patch we show:
> >	xe REG[0xdafc-0xdb0b]: allow read access
>
> Please ignore this patch for now. I am still looking into this.

Please ignore this patch. The previous code is correct according to Bspec
45925 / Bspec 60340.

The confusion was there because there seems to be some change in register
whitelisting in Xe2. Prior to Xe2 it appears the alignment mentioned in
bits 1:0 (of the above Bspec links) was not enforced. E.g. the statement:

	XE_RTP_ACTIONS(WHITELIST(0xdafc, RING_FORCE_TO_NONPRIV_RANGE_4))

whitelisted registers 0xdafc, 0xdb00, 0xdb04, 0xdb08 with a single nonpriv
slot.

This seems to have changed in Xe2, where the above statement whitelists
registers 0xdaf0, 0xdaf4, 0xdaf8, 0xdafc instead, following Bspec.

Therefore in Xe2 we need two slots to whitelist these registers as follows:

	XE_RTP_ACTIONS(WHITELIST(0xdafc, RING_FORCE_TO_NONPRIV_RANGE_1))
	XE_RTP_ACTIONS(WHITELIST(0xdb00, RING_FORCE_TO_NONPRIV_RANGE_4))

So the patch assumes the behavior which is present in generations prior to
Xe2 (but has changed Xe2 onwards, at least as far as I can tell).

In any case, please ignore this patch, let's keep the previous code which
follows Bspec from Xe2 onwards.

Thanks.
--
Ashutosh