[Intel-xe] [PATCH 0/4] Add Raptorlake Support

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* [Intel-xe] [PATCH 0/4] Add Raptorlake Support
@ 2023-09-15 19:46 Anusha Srivatsa
  2023-09-15 19:46 ` [Intel-xe] [PATCH 1/4] drm/xe/rplu: s/ADLP/ALDERLAKE_P Anusha Srivatsa
                   ` (3 more replies)
  0 siblings, 4 replies; 6+ messages in thread
From: Anusha Srivatsa @ 2023-09-15 19:46 UTC (permalink / raw)
  To: intel-xe; +Cc: Anusha Srivatsa

Keep the naming convention consistent with i915.
As part of it making some consistent naming changes
so we can continue to use some macro magic moving forward.
It does make the name bigger - ALDERLAKE instead of
just ADL. But this way the platform name is ALDERLAKE_P
everywhere which is easier to remember and use.(previosuly
the driver had ADLP_ usages for some defines - like ADLP_RPLU_* etc)

While at it also adding some missing support in kunit for the
some subplatforms.

Anusha Srivatsa (4):
  drm/xe/rplu: s/ADLP/ALDERLAKE_P
  drm/xe/rpls: Add RPLS Support
  drm/xe/rpls: Add Stepping info for RPLS
  drm/xe: Add missing ADL entries to xe_test_wa

 drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h |  2 +-
 drivers/gpu/drm/xe/tests/xe_wa_test.c             |  2 ++
 drivers/gpu/drm/xe/xe_pci.c                       |  9 ++++++++-
 drivers/gpu/drm/xe/xe_platform_types.h            |  3 ++-
 drivers/gpu/drm/xe/xe_step.c                      | 10 +++++++++-
 5 files changed, 22 insertions(+), 4 deletions(-)

-- 
2.25.1

^ permalink raw reply	[flat|nested] 6+ messages in thread

* [Intel-xe] [PATCH 1/4] drm/xe/rplu: s/ADLP/ALDERLAKE_P
  2023-09-15 19:46 [Intel-xe] [PATCH 0/4] Add Raptorlake Support Anusha Srivatsa
@ 2023-09-15 19:46 ` Anusha Srivatsa
  2023-09-18 12:22   ` Jani Nikula
  2023-09-15 19:46 ` [Intel-xe] [PATCH 2/4] drm/xe/rpls: Add RPLS Support Anusha Srivatsa
                   ` (2 subsequent siblings)
  3 siblings, 1 reply; 6+ messages in thread
From: Anusha Srivatsa @ 2023-09-15 19:46 UTC (permalink / raw)
  To: intel-xe; +Cc: Anusha Srivatsa

i915 now uses full names for platforms. So we now have
ALDERLAKE instead of ADL. Extend this to xe driver as well.
This will make it easier for macro magic usages.

Cc: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 2 +-
 drivers/gpu/drm/xe/xe_pci.c                       | 2 +-
 drivers/gpu/drm/xe/xe_platform_types.h            | 2 +-
 drivers/gpu/drm/xe/xe_step.c                      | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
index 03ac39efba38..012d15565727 100644
--- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
+++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
@@ -144,7 +144,7 @@ static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
 #define IS_DG2_G10(xe) ((xe)->info.subplatform == XE_SUBPLATFORM_DG2_G10)
 #define IS_DG2_G11(xe) ((xe)->info.subplatform == XE_SUBPLATFORM_DG2_G11)
 #define IS_DG2_G12(xe) ((xe)->info.subplatform == XE_SUBPLATFORM_DG2_G12)
-#define IS_RAPTORLAKE_U(xe) ((xe)->info.subplatform == XE_SUBPLATFORM_ADLP_RPLU)
+#define IS_RAPTORLAKE_U(xe) ((xe)->info.subplatform == XE_SUBPLATFORM_ALDERLAKE_P_RPLU)
 #define IS_ICL_WITH_PORT_F(xe) (xe && 0)
 #define HAS_FLAT_CCS(xe) (xe_device_has_flat_ccs(xe))
 #define to_intel_bo(x) gem_to_xe_bo((x))
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index dc233a1226bd..96a34d9197a8 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -241,7 +241,7 @@ static const struct xe_device_desc adl_p_desc = {
 	.has_llc = true,
 	.require_force_probe = true,
 	.subplatforms = (const struct xe_subplatform_desc[]) {
-		{ XE_SUBPLATFORM_ADLP_RPLU, "RPLU", adlp_rplu_ids },
+		{ XE_SUBPLATFORM_ALDERLAKE_P_RPLU, "RPLU", adlp_rplu_ids },
 		{},
 	},
 };
diff --git a/drivers/gpu/drm/xe/xe_platform_types.h b/drivers/gpu/drm/xe/xe_platform_types.h
index e378a64a0f86..b6fe4342f9f6 100644
--- a/drivers/gpu/drm/xe/xe_platform_types.h
+++ b/drivers/gpu/drm/xe/xe_platform_types.h
@@ -27,7 +27,7 @@ enum xe_platform {
 enum xe_subplatform {
 	XE_SUBPLATFORM_UNINITIALIZED = 0,
 	XE_SUBPLATFORM_NONE,
-	XE_SUBPLATFORM_ADLP_RPLU,
+	XE_SUBPLATFORM_ALDERLAKE_P_RPLU,
 	XE_SUBPLATFORM_DG2_G10,
 	XE_SUBPLATFORM_DG2_G11,
 	XE_SUBPLATFORM_DG2_G12,
diff --git a/drivers/gpu/drm/xe/xe_step.c b/drivers/gpu/drm/xe/xe_step.c
index 371cac951e0f..903c65405d3a 100644
--- a/drivers/gpu/drm/xe/xe_step.c
+++ b/drivers/gpu/drm/xe/xe_step.c
@@ -143,7 +143,7 @@ struct xe_step_info xe_step_pre_gmdid_get(struct xe_device *xe)
 	} else if (xe->info.platform == XE_ALDERLAKE_N) {
 		revids = adln_revids;
 		size = ARRAY_SIZE(adln_revids);
-	} else if (xe->info.subplatform == XE_SUBPLATFORM_ADLP_RPLU) {
+	} else if (xe->info.subplatform == XE_SUBPLATFORM_ALDERLAKE_P_RPLU) {
 		revids = adlp_rpl_revids;
 		size = ARRAY_SIZE(adlp_rpl_revids);
 	} else if (xe->info.platform == XE_ALDERLAKE_P) {
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 6+ messages in thread

* Re: [Intel-xe] [PATCH 1/4] drm/xe/rplu: s/ADLP/ALDERLAKE_P
  2023-09-15 19:46 ` [Intel-xe] [PATCH 1/4] drm/xe/rplu: s/ADLP/ALDERLAKE_P Anusha Srivatsa
@ 2023-09-18 12:22   ` Jani Nikula
  0 siblings, 0 replies; 6+ messages in thread
From: Jani Nikula @ 2023-09-18 12:22 UTC (permalink / raw)
  To: Anusha Srivatsa, intel-xe; +Cc: Anusha Srivatsa

On Fri, 15 Sep 2023, Anusha Srivatsa <anusha.srivatsa@intel.com> wrote:
> i915 now uses full names for platforms. So we now have
> ALDERLAKE instead of ADL. Extend this to xe driver as well.
> This will make it easier for macro magic usages.
>
> Cc: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
>  drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 2 +-

Please don't make changes to this file at the same time as the ones
below.

Regardless of whether it breaks the build at this time.

BR,
Jani.

>  drivers/gpu/drm/xe/xe_pci.c                       | 2 +-
>  drivers/gpu/drm/xe/xe_platform_types.h            | 2 +-
>  drivers/gpu/drm/xe/xe_step.c                      | 2 +-
>  4 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
> index 03ac39efba38..012d15565727 100644
> --- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
> +++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
> @@ -144,7 +144,7 @@ static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
>  #define IS_DG2_G10(xe) ((xe)->info.subplatform == XE_SUBPLATFORM_DG2_G10)
>  #define IS_DG2_G11(xe) ((xe)->info.subplatform == XE_SUBPLATFORM_DG2_G11)
>  #define IS_DG2_G12(xe) ((xe)->info.subplatform == XE_SUBPLATFORM_DG2_G12)
> -#define IS_RAPTORLAKE_U(xe) ((xe)->info.subplatform == XE_SUBPLATFORM_ADLP_RPLU)
> +#define IS_RAPTORLAKE_U(xe) ((xe)->info.subplatform == XE_SUBPLATFORM_ALDERLAKE_P_RPLU)
>  #define IS_ICL_WITH_PORT_F(xe) (xe && 0)
>  #define HAS_FLAT_CCS(xe) (xe_device_has_flat_ccs(xe))
>  #define to_intel_bo(x) gem_to_xe_bo((x))
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index dc233a1226bd..96a34d9197a8 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -241,7 +241,7 @@ static const struct xe_device_desc adl_p_desc = {
>  	.has_llc = true,
>  	.require_force_probe = true,
>  	.subplatforms = (const struct xe_subplatform_desc[]) {
> -		{ XE_SUBPLATFORM_ADLP_RPLU, "RPLU", adlp_rplu_ids },
> +		{ XE_SUBPLATFORM_ALDERLAKE_P_RPLU, "RPLU", adlp_rplu_ids },
>  		{},
>  	},
>  };
> diff --git a/drivers/gpu/drm/xe/xe_platform_types.h b/drivers/gpu/drm/xe/xe_platform_types.h
> index e378a64a0f86..b6fe4342f9f6 100644
> --- a/drivers/gpu/drm/xe/xe_platform_types.h
> +++ b/drivers/gpu/drm/xe/xe_platform_types.h
> @@ -27,7 +27,7 @@ enum xe_platform {
>  enum xe_subplatform {
>  	XE_SUBPLATFORM_UNINITIALIZED = 0,
>  	XE_SUBPLATFORM_NONE,
> -	XE_SUBPLATFORM_ADLP_RPLU,
> +	XE_SUBPLATFORM_ALDERLAKE_P_RPLU,
>  	XE_SUBPLATFORM_DG2_G10,
>  	XE_SUBPLATFORM_DG2_G11,
>  	XE_SUBPLATFORM_DG2_G12,
> diff --git a/drivers/gpu/drm/xe/xe_step.c b/drivers/gpu/drm/xe/xe_step.c
> index 371cac951e0f..903c65405d3a 100644
> --- a/drivers/gpu/drm/xe/xe_step.c
> +++ b/drivers/gpu/drm/xe/xe_step.c
> @@ -143,7 +143,7 @@ struct xe_step_info xe_step_pre_gmdid_get(struct xe_device *xe)
>  	} else if (xe->info.platform == XE_ALDERLAKE_N) {
>  		revids = adln_revids;
>  		size = ARRAY_SIZE(adln_revids);
> -	} else if (xe->info.subplatform == XE_SUBPLATFORM_ADLP_RPLU) {
> +	} else if (xe->info.subplatform == XE_SUBPLATFORM_ALDERLAKE_P_RPLU) {
>  		revids = adlp_rpl_revids;
>  		size = ARRAY_SIZE(adlp_rpl_revids);
>  	} else if (xe->info.platform == XE_ALDERLAKE_P) {

-- 
Jani Nikula, Intel

^ permalink raw reply	[flat|nested] 6+ messages in thread

* [Intel-xe] [PATCH 2/4] drm/xe/rpls: Add RPLS Support
  2023-09-15 19:46 [Intel-xe] [PATCH 0/4] Add Raptorlake Support Anusha Srivatsa
  2023-09-15 19:46 ` [Intel-xe] [PATCH 1/4] drm/xe/rplu: s/ADLP/ALDERLAKE_P Anusha Srivatsa
@ 2023-09-15 19:46 ` Anusha Srivatsa
  2023-09-15 19:46 ` [Intel-xe] [PATCH 3/4] drm/xe/rpls: Add Stepping info for RPLS Anusha Srivatsa
  2023-09-15 19:47 ` [Intel-xe] [PATCH 4/4] drm/xe: Add missing ADL entries to xe_test_wa Anusha Srivatsa
  3 siblings, 0 replies; 6+ messages in thread
From: Anusha Srivatsa @ 2023-09-15 19:46 UTC (permalink / raw)
  To: intel-xe; +Cc: Anusha Srivatsa, Matt Roper

Add RPLS support that was missing apart from the PCI IDs.

v2: Also add the support in xe_wa_test kunit
v3: rebased.

Cc: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>(v1)
---
 drivers/gpu/drm/xe/tests/xe_wa_test.c  | 1 +
 drivers/gpu/drm/xe/xe_pci.c            | 7 +++++++
 drivers/gpu/drm/xe/xe_platform_types.h | 1 +
 3 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/xe/tests/xe_wa_test.c b/drivers/gpu/drm/xe/tests/xe_wa_test.c
index 16f7f157c875..69c9ea1fa82b 100644
--- a/drivers/gpu/drm/xe/tests/xe_wa_test.c
+++ b/drivers/gpu/drm/xe/tests/xe_wa_test.c
@@ -49,6 +49,7 @@ static const struct platform_test_case cases[] = {
 	PLATFORM_CASE(ALDERLAKE_P, A0),
 	PLATFORM_CASE(ALDERLAKE_P, B0),
 	PLATFORM_CASE(ALDERLAKE_P, C0),
+	SUBPLATFORM_CASE(ALDERLAKE_S, RPLS, D0),
 	SUBPLATFORM_CASE(DG2, G10, A0),
 	SUBPLATFORM_CASE(DG2, G10, A1),
 	SUBPLATFORM_CASE(DG2, G10, B0),
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 96a34d9197a8..50022294b2f6 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -222,6 +222,8 @@ static const struct xe_device_desc rkl_desc = {
 	.require_force_probe = true,
 };
 
+static const u16 adls_rpls_ids[] = { XE_RPLS_IDS(NOP), 0 };
+
 static const struct xe_device_desc adl_s_desc = {
 	.graphics = &graphics_xelp,
 	.media = &media_xem,
@@ -229,6 +231,10 @@ static const struct xe_device_desc adl_s_desc = {
 	.has_display = true,
 	.has_llc = true,
 	.require_force_probe = true,
+	.subplatforms = (const struct xe_subplatform_desc[]) {
+		{ XE_SUBPLATFORM_ALDERLAKE_S_RPLS, "RPLS", adls_rpls_ids },
+		{},
+	},
 };
 
 static const u16 adlp_rplu_ids[] = { XE_RPLU_IDS(NOP), 0 };
@@ -353,6 +359,7 @@ static const struct pci_device_id pciidlist[] = {
 	XE_ADLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc),
 	XE_ADLN_IDS(INTEL_VGA_DEVICE, &adl_n_desc),
 	XE_RPLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc),
+	XE_RPLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc),
 	XE_DG1_IDS(INTEL_VGA_DEVICE, &dg1_desc),
 	XE_ATS_M_IDS(INTEL_VGA_DEVICE, &ats_m_desc),
 	XE_DG2_IDS(INTEL_VGA_DEVICE, &dg2_desc),
diff --git a/drivers/gpu/drm/xe/xe_platform_types.h b/drivers/gpu/drm/xe/xe_platform_types.h
index b6fe4342f9f6..553f53dbd093 100644
--- a/drivers/gpu/drm/xe/xe_platform_types.h
+++ b/drivers/gpu/drm/xe/xe_platform_types.h
@@ -28,6 +28,7 @@ enum xe_subplatform {
 	XE_SUBPLATFORM_UNINITIALIZED = 0,
 	XE_SUBPLATFORM_NONE,
 	XE_SUBPLATFORM_ALDERLAKE_P_RPLU,
+	XE_SUBPLATFORM_ALDERLAKE_S_RPLS,
 	XE_SUBPLATFORM_DG2_G10,
 	XE_SUBPLATFORM_DG2_G11,
 	XE_SUBPLATFORM_DG2_G12,
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 6+ messages in thread

* [Intel-xe] [PATCH 3/4] drm/xe/rpls: Add Stepping info for RPLS
  2023-09-15 19:46 [Intel-xe] [PATCH 0/4] Add Raptorlake Support Anusha Srivatsa
  2023-09-15 19:46 ` [Intel-xe] [PATCH 1/4] drm/xe/rplu: s/ADLP/ALDERLAKE_P Anusha Srivatsa
  2023-09-15 19:46 ` [Intel-xe] [PATCH 2/4] drm/xe/rpls: Add RPLS Support Anusha Srivatsa
@ 2023-09-15 19:46 ` Anusha Srivatsa
  2023-09-15 19:47 ` [Intel-xe] [PATCH 4/4] drm/xe: Add missing ADL entries to xe_test_wa Anusha Srivatsa
  3 siblings, 0 replies; 6+ messages in thread
From: Anusha Srivatsa @ 2023-09-15 19:46 UTC (permalink / raw)
  To: intel-xe; +Cc: Anusha Srivatsa, Matt Roper

Add stepping-substepping info. Though it looks
weird, the revision ID for the newer stepping
is indeed backwards and is in accordance to the spec.

v2: s/RPLS/RAPTORLAKE_S (Anusha)
v3: rebase (Anusha)

Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>(v1)
---
 drivers/gpu/drm/xe/xe_step.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_step.c b/drivers/gpu/drm/xe/xe_step.c
index 903c65405d3a..eaf1b718f26c 100644
--- a/drivers/gpu/drm/xe/xe_step.c
+++ b/drivers/gpu/drm/xe/xe_step.c
@@ -60,6 +60,11 @@ static const struct xe_step_info adls_revids[] = {
 	[0xC] = { COMMON_GT_MEDIA_STEP(D0), .display = STEP_C0 },
 };
 
+static const struct xe_step_info adls_rpls_revids[] = {
+	[0x4] = { COMMON_GT_MEDIA_STEP(D0), .display = STEP_D0 },
+	[0xC] = { COMMON_GT_MEDIA_STEP(D0), .display = STEP_C0 },
+};
+
 static const struct xe_step_info adlp_revids[] = {
 	[0x0] = { COMMON_GT_MEDIA_STEP(A0), .display = STEP_A0 },
 	[0x4] = { COMMON_GT_MEDIA_STEP(B0), .display = STEP_B0 },
@@ -143,6 +148,9 @@ struct xe_step_info xe_step_pre_gmdid_get(struct xe_device *xe)
 	} else if (xe->info.platform == XE_ALDERLAKE_N) {
 		revids = adln_revids;
 		size = ARRAY_SIZE(adln_revids);
+	} else if (xe->info.subplatform == XE_SUBPLATFORM_ALDERLAKE_S_RPLS) {
+		revids = adls_rpls_revids;
+		size = ARRAY_SIZE(adls_rpls_revids);
 	} else if (xe->info.subplatform == XE_SUBPLATFORM_ALDERLAKE_P_RPLU) {
 		revids = adlp_rpl_revids;
 		size = ARRAY_SIZE(adlp_rpl_revids);
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 6+ messages in thread

* [Intel-xe] [PATCH 4/4] drm/xe: Add missing ADL entries to xe_test_wa
  2023-09-15 19:46 [Intel-xe] [PATCH 0/4] Add Raptorlake Support Anusha Srivatsa
                   ` (2 preceding siblings ...)
  2023-09-15 19:46 ` [Intel-xe] [PATCH 3/4] drm/xe/rpls: Add Stepping info for RPLS Anusha Srivatsa
@ 2023-09-15 19:47 ` Anusha Srivatsa
  3 siblings, 0 replies; 6+ messages in thread
From: Anusha Srivatsa @ 2023-09-15 19:47 UTC (permalink / raw)
  To: intel-xe; +Cc: Anusha Srivatsa, Lucas De Marchi

With all ADl platforms and subplatforms added,
also add support to xe_wa_test kunit tests for checking
their WAs.

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/xe/tests/xe_wa_test.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/xe/tests/xe_wa_test.c b/drivers/gpu/drm/xe/tests/xe_wa_test.c
index 69c9ea1fa82b..6e1127b276ea 100644
--- a/drivers/gpu/drm/xe/tests/xe_wa_test.c
+++ b/drivers/gpu/drm/xe/tests/xe_wa_test.c
@@ -50,6 +50,7 @@ static const struct platform_test_case cases[] = {
 	PLATFORM_CASE(ALDERLAKE_P, B0),
 	PLATFORM_CASE(ALDERLAKE_P, C0),
 	SUBPLATFORM_CASE(ALDERLAKE_S, RPLS, D0),
+	SUBPLATFORM_CASE(ALDERLAKE_P, RPLU, E0),
 	SUBPLATFORM_CASE(DG2, G10, A0),
 	SUBPLATFORM_CASE(DG2, G10, A1),
 	SUBPLATFORM_CASE(DG2, G10, B0),
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2023-09-18 12:22 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-09-15 19:46 [Intel-xe] [PATCH 0/4] Add Raptorlake Support Anusha Srivatsa
2023-09-15 19:46 ` [Intel-xe] [PATCH 1/4] drm/xe/rplu: s/ADLP/ALDERLAKE_P Anusha Srivatsa
2023-09-18 12:22   ` Jani Nikula
2023-09-15 19:46 ` [Intel-xe] [PATCH 2/4] drm/xe/rpls: Add RPLS Support Anusha Srivatsa
2023-09-15 19:46 ` [Intel-xe] [PATCH 3/4] drm/xe/rpls: Add Stepping info for RPLS Anusha Srivatsa
2023-09-15 19:47 ` [Intel-xe] [PATCH 4/4] drm/xe: Add missing ADL entries to xe_test_wa Anusha Srivatsa

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