* [Intel-xe] [PATCH 00/17] Cleanup registers and introduce xe_reg_t
@ 2023-04-19 7:44 Lucas De Marchi
2023-04-19 7:44 ` [Intel-xe] [PATCH 01/17] drm/xe: Cleanup page-related defines Lucas De Marchi
` (20 more replies)
0 siblings, 21 replies; 41+ messages in thread
From: Lucas De Marchi @ 2023-04-19 7:44 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, Matt Roper, Rodrigo Vivi
Continuation of https://patchwork.freedesktop.org/series/116411/. Now
not only the trivial cleanup/renames is done, but also the harder
migration to xe_reg_t. This is meant to replace our uses of i915_reg_t
and i915_mcr_reg_t.
There is still more to do: probably migrate xe_mmio_* to use the new
type, remove the several REGISTER.reg spread throughout the code.
Lightly tested on a DG2. Probably needs more soaking time to ensure it
doesn't regress.
Lucas De Marchi (17):
drm/xe: Cleanup page-related defines
fixup! drm/i915/display: Remaining changes to make xe compile
fixup! drm/i915/display: Allow fbdev to allocate stolen memory
drm/xe: Rename RC0/RC6 macros
drm/xe: Rename instruction field to avoid confusion
drm/xe/guc: Rename GEN11_SOFT_SCRATCH for clarity
drm/xe/guc: Move GuC registers to regs/
drm/xe/guc: Convert GuC registers to REG_FIELD/REG_BIT
drm/xe: Drop gen prefixes and suffixes from registers
drm/xe: Use REG_FIELD/REG_BIT for all regs/*.h
drm/xe: Introduce xe_reg_t
drm/xe: Clarify register types on PAT programming
drm/xe/rtp: Improve magic macros for RTP tables
drm/xe: Add XE_REG/XE_REG_MCR
drm/xe: Annotate masked registers used by RTP
drm/xe: Plumb xe_reg_t into WAs, rtp, etc
drm/xe: Move helper macros to separate header
drivers/gpu/drm/i915/display/intel_fbdev.c | 4 +-
drivers/gpu/drm/xe/Makefile | 2 +-
drivers/gpu/drm/xe/display/xe_fb_pin.c | 23 +-
drivers/gpu/drm/xe/display/xe_plane_initial.c | 4 +-
drivers/gpu/drm/xe/regs/xe_engine_regs.h | 100 ++---
drivers/gpu/drm/xe/regs/xe_gpu_commands.h | 6 +-
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 358 +++++++++---------
drivers/gpu/drm/xe/regs/xe_guc_regs.h | 146 +++++++
drivers/gpu/drm/xe/regs/xe_reg_defs.h | 64 ++++
drivers/gpu/drm/xe/regs/xe_regs.h | 65 ++--
drivers/gpu/drm/xe/tests/xe_migrate.c | 15 +-
drivers/gpu/drm/xe/tests/xe_rtp_test.c | 50 +--
drivers/gpu/drm/xe/xe_bo.h | 52 +--
drivers/gpu/drm/xe/xe_execlist.c | 8 +-
drivers/gpu/drm/xe/xe_force_wake.c | 18 +-
drivers/gpu/drm/xe/xe_ggtt.c | 42 +-
drivers/gpu/drm/xe/xe_gt.c | 4 +-
drivers/gpu/drm/xe/xe_gt_clock.c | 27 +-
drivers/gpu/drm/xe/xe_gt_mcr.c | 52 ++-
drivers/gpu/drm/xe/xe_gt_mcr.h | 8 +-
drivers/gpu/drm/xe/xe_guc.c | 52 ++-
drivers/gpu/drm/xe/xe_guc_ads.c | 16 +-
drivers/gpu/drm/xe/xe_guc_pc.c | 30 +-
drivers/gpu/drm/xe/xe_guc_reg.h | 151 --------
drivers/gpu/drm/xe/xe_huc.c | 6 +-
drivers/gpu/drm/xe/xe_hw_engine.c | 42 +-
drivers/gpu/drm/xe/xe_irq.c | 8 +-
drivers/gpu/drm/xe/xe_migrate.c | 73 ++--
drivers/gpu/drm/xe/xe_mmio.c | 7 +-
drivers/gpu/drm/xe/xe_mocs.c | 11 +-
drivers/gpu/drm/xe/xe_pat.c | 35 +-
drivers/gpu/drm/xe/xe_pcode_api.h | 6 +-
drivers/gpu/drm/xe/xe_pt.c | 40 +-
drivers/gpu/drm/xe/xe_reg_sr.c | 29 +-
drivers/gpu/drm/xe/xe_reg_sr.h | 3 +-
drivers/gpu/drm/xe/xe_reg_sr_types.h | 10 +-
drivers/gpu/drm/xe/xe_reg_whitelist.c | 11 +-
drivers/gpu/drm/xe/xe_ring_ops.c | 8 +-
drivers/gpu/drm/xe/xe_rtp.c | 7 +-
drivers/gpu/drm/xe/xe_rtp.h | 106 ++----
drivers/gpu/drm/xe/xe_rtp_helpers.h | 48 +++
drivers/gpu/drm/xe/xe_rtp_types.h | 14 +-
drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c | 2 +-
drivers/gpu/drm/xe/xe_tuning.c | 10 +-
drivers/gpu/drm/xe/xe_uc_fw.c | 2 +-
drivers/gpu/drm/xe/xe_vm.c | 20 +-
drivers/gpu/drm/xe/xe_wa.c | 177 +++------
drivers/gpu/drm/xe/xe_wopcm.c | 2 +-
48 files changed, 987 insertions(+), 987 deletions(-)
create mode 100644 drivers/gpu/drm/xe/regs/xe_guc_regs.h
delete mode 100644 drivers/gpu/drm/xe/xe_guc_reg.h
create mode 100644 drivers/gpu/drm/xe/xe_rtp_helpers.h
--
2.39.0
^ permalink raw reply [flat|nested] 41+ messages in thread
* [Intel-xe] [PATCH 01/17] drm/xe: Cleanup page-related defines
2023-04-19 7:44 [Intel-xe] [PATCH 00/17] Cleanup registers and introduce xe_reg_t Lucas De Marchi
@ 2023-04-19 7:44 ` Lucas De Marchi
2023-04-19 7:44 ` [Intel-xe] [PATCH 02/17] fixup! drm/i915/display: Remaining changes to make xe compile Lucas De Marchi
` (19 subsequent siblings)
20 siblings, 0 replies; 41+ messages in thread
From: Lucas De Marchi @ 2023-04-19 7:44 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, Matt Roper, Rodrigo Vivi
Rename the following defines to lose the GEN* prefixes since they don't
make sense for xe:
GEN8_PTE_SHIFT -> XE_PTE_SHIFT
GEN8_PAGE_SIZE -> XE_PAGE_SIZE
GEN8_PTE_MASK -> XE_PTE_MASK
GEN8_PDE_SHIFT -> XE_PDE_SHIFT
GEN8_PDES -> XE_PDES
GEN8_PDE_MASK -> XE_PDE_MASK
GEN8_64K_PTE_SHIFT -> XE_64K_PTE_SHIFT
GEN8_64K_PAGE_SIZE -> XE_64K_PAGE_SIZE
GEN8_64K_PTE_MASK -> XE_64K_PTE_MASK
GEN8_64K_PDE_MASK -> XE_64K_PDE_MASK
GEN8_PDE_PS_2M -> XE_PDE_PS_2M
GEN8_PDPE_PS_1G -> XE_PDPE_PS_1G
GEN8_PDE_IPS_64K -> XE_PDE_IPS_64K
GEN12_GGTT_PTE_LM -> XE_GGTT_PTE_LM
GEN12_USM_PPGTT_PTE_AE -> XE_USM_PPGTT_PTE_AE
GEN12_PPGTT_PTE_LM -> XE_PPGTT_PTE_LM
GEN12_PDE_64K -> XE_PDE_64K
GEN12_PTE_PS64 -> XE_PTE_PS64
GEN8_PAGE_PRESENT -> XE_PAGE_PRESENT
GEN8_PAGE_RW -> XE_PAGE_RW
PTE_READ_ONLY -> XE_PTE_READ_ONLY
Keep an XE_ prefix to make sure we don't mix the defines for the CPU
(e.g. PAGE_SIZE) with the ones fro the GPU).
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/display/xe_fb_pin.c | 23 ++++---
drivers/gpu/drm/xe/display/xe_plane_initial.c | 4 +-
drivers/gpu/drm/xe/tests/xe_migrate.c | 15 ++--
drivers/gpu/drm/xe/xe_bo.h | 52 +++++++-------
drivers/gpu/drm/xe/xe_ggtt.c | 24 +++----
drivers/gpu/drm/xe/xe_migrate.c | 69 ++++++++++---------
drivers/gpu/drm/xe/xe_pt.c | 40 +++++------
drivers/gpu/drm/xe/xe_vm.c | 20 +++---
8 files changed, 126 insertions(+), 121 deletions(-)
diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c
index 65c0bc28a3d1..ed691d28b34d 100644
--- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
+++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
@@ -27,7 +27,7 @@ write_dpt_rotated(struct xe_bo *bo, struct iosys_map *map, u32 *dpt_ofs, u32 bo_
for (row = 0; row < height; row++) {
iosys_map_wr(map, *dpt_ofs, u64,
- xe_ggtt_pte_encode(bo, src_idx * GEN8_PAGE_SIZE));
+ xe_ggtt_pte_encode(bo, src_idx * XE_PAGE_SIZE));
*dpt_ofs += 8;
src_idx -= src_stride;
}
@@ -49,10 +49,11 @@ static int __xe_pin_fb_vma_dpt(struct intel_framebuffer *fb,
u32 dpt_size, size = bo->ttm.base.size;
if (view->type == I915_GTT_VIEW_NORMAL)
- dpt_size = ALIGN(size / GEN8_PAGE_SIZE * 8, GEN8_PAGE_SIZE);
+ dpt_size = ALIGN(size / XE_PAGE_SIZE * 8, XE_PAGE_SIZE);
else
/* display uses 4K tiles instead of bytes here, convert to entries.. */
- dpt_size = ALIGN(intel_rotation_info_size(&view->rotated) * 8, GEN8_PAGE_SIZE);
+ dpt_size = ALIGN(intel_rotation_info_size(&view->rotated) * 8,
+ XE_PAGE_SIZE);
dpt = xe_bo_create_pin_map(xe, to_gt(xe), NULL, dpt_size,
ttm_bo_type_kernel,
@@ -74,9 +75,9 @@ static int __xe_pin_fb_vma_dpt(struct intel_framebuffer *fb,
if (view->type == I915_GTT_VIEW_NORMAL) {
u32 x;
- for (x = 0; x < size / GEN8_PAGE_SIZE; x++)
+ for (x = 0; x < size / XE_PAGE_SIZE; x++)
iosys_map_wr(&dpt->vmap, x * 8, u64,
- xe_ggtt_pte_encode(bo, x * GEN8_PAGE_SIZE));
+ xe_ggtt_pte_encode(bo, x * XE_PAGE_SIZE));
} else {
const struct intel_rotation_info *rot_info = &view->rotated;
u32 i, dpt_ofs = 0;
@@ -106,13 +107,13 @@ write_ggtt_rotated(struct xe_bo *bo, struct xe_ggtt *ggtt, u32 *ggtt_ofs, u32 bo
for (row = 0; row < height; row++) {
xe_ggtt_set_pte(ggtt, *ggtt_ofs,
- xe_ggtt_pte_encode(bo, src_idx * GEN8_PAGE_SIZE));
- *ggtt_ofs += GEN8_PAGE_SIZE;
+ xe_ggtt_pte_encode(bo, src_idx * XE_PAGE_SIZE));
+ *ggtt_ofs += XE_PAGE_SIZE;
src_idx -= src_stride;
}
/* The DE ignores the PTEs for the padding tiles */
- *ggtt_ofs += (dst_stride - height) * GEN8_PAGE_SIZE;
+ *ggtt_ofs += (dst_stride - height) * XE_PAGE_SIZE;
}
}
@@ -133,7 +134,7 @@ static int __xe_pin_fb_vma_ggtt(struct intel_framebuffer *fb,
if (ret)
return ret;
- align = GEN8_PAGE_SIZE;
+ align = XE_PAGE_SIZE;
if (xe_bo_is_vram(bo) && ggtt->flags & XE_GGTT_FLAGS_64K)
align = max_t(u32, align, SZ_64K);
@@ -147,14 +148,14 @@ static int __xe_pin_fb_vma_ggtt(struct intel_framebuffer *fb,
if (ret)
goto out;
- for (x = 0; x < size; x += GEN8_PAGE_SIZE)
+ for (x = 0; x < size; x += XE_PAGE_SIZE)
xe_ggtt_set_pte(ggtt, vma->node.start + x, xe_ggtt_pte_encode(bo, x));
} else {
u32 i, ggtt_ofs;
const struct intel_rotation_info *rot_info = &view->rotated;
/* display seems to use tiles instead of bytes here, so convert it back.. */
- u32 size = intel_rotation_info_size(rot_info) * GEN8_PAGE_SIZE;
+ u32 size = intel_rotation_info_size(rot_info) * XE_PAGE_SIZE;
ret = xe_ggtt_insert_special_node_locked(ggtt, &vma->node, size,
align, 0);
diff --git a/drivers/gpu/drm/xe/display/xe_plane_initial.c b/drivers/gpu/drm/xe/display/xe_plane_initial.c
index a2ef0823ed02..d0f91f37b6d8 100644
--- a/drivers/gpu/drm/xe/display/xe_plane_initial.c
+++ b/drivers/gpu/drm/xe/display/xe_plane_initial.c
@@ -67,10 +67,10 @@ initial_plane_bo(struct xe_device *xe,
u64 __iomem *gte = gt0->mem.ggtt->gsm;
u64 pte;
- gte += base / GEN8_PAGE_SIZE;
+ gte += base / XE_PAGE_SIZE;
pte = ioread64(gte);
- if (!(pte & GEN12_GGTT_PTE_LM)) {
+ if (!(pte & XE_GGTT_PTE_LM)) {
drm_err(&xe->drm,
"Initial plane programming missing PTE_LM bit\n");
return NULL;
diff --git a/drivers/gpu/drm/xe/tests/xe_migrate.c b/drivers/gpu/drm/xe/tests/xe_migrate.c
index cdcecf8d5eef..0f4371ad1fd9 100644
--- a/drivers/gpu/drm/xe/tests/xe_migrate.c
+++ b/drivers/gpu/drm/xe/tests/xe_migrate.c
@@ -265,7 +265,7 @@ static void xe_migrate_sanity_test(struct xe_migrate *m, struct kunit *test)
goto vunmap;
}
- pt = xe_bo_create_pin_map(xe, m->gt, m->eng->vm, GEN8_PAGE_SIZE,
+ pt = xe_bo_create_pin_map(xe, m->gt, m->eng->vm, XE_PAGE_SIZE,
ttm_bo_type_kernel,
XE_BO_CREATE_VRAM_IF_DGFX(m->gt) |
XE_BO_CREATE_PINNED_BIT);
@@ -294,20 +294,21 @@ static void xe_migrate_sanity_test(struct xe_migrate *m, struct kunit *test)
}
kunit_info(test, "Starting tests, top level PT addr: %lx, special pagetable base addr: %lx\n",
- (unsigned long)xe_bo_main_addr(m->eng->vm->pt_root[id]->bo, GEN8_PAGE_SIZE),
- (unsigned long)xe_bo_main_addr(m->pt_bo, GEN8_PAGE_SIZE));
+ (unsigned long)xe_bo_main_addr(m->eng->vm->pt_root[id]->bo, XE_PAGE_SIZE),
+ (unsigned long)xe_bo_main_addr(m->pt_bo, XE_PAGE_SIZE));
/* First part of the test, are we updating our pagetable bo with a new entry? */
- xe_map_wr(xe, &bo->vmap, GEN8_PAGE_SIZE * (NUM_KERNEL_PDE - 1), u64, 0xdeaddeadbeefbeef);
+ xe_map_wr(xe, &bo->vmap, XE_PAGE_SIZE * (NUM_KERNEL_PDE - 1), u64,
+ 0xdeaddeadbeefbeef);
expected = gen8_pte_encode(NULL, pt, 0, XE_CACHE_WB, 0, 0);
if (m->eng->vm->flags & XE_VM_FLAGS_64K)
- expected |= GEN12_PTE_PS64;
+ expected |= XE_PTE_PS64;
xe_res_first(pt->ttm.resource, 0, pt->size, &src_it);
emit_pte(m, bb, NUM_KERNEL_PDE - 1, xe_bo_is_vram(pt),
- &src_it, GEN8_PAGE_SIZE, pt);
+ &src_it, XE_PAGE_SIZE, pt);
run_sanity_job(m, xe, bb, bb->len, "Writing PTE for our fake PT", test);
- retval = xe_map_rd(xe, &bo->vmap, GEN8_PAGE_SIZE * (NUM_KERNEL_PDE - 1),
+ retval = xe_map_rd(xe, &bo->vmap, XE_PAGE_SIZE * (NUM_KERNEL_PDE - 1),
u64);
check(retval, expected, "PTE entry write", test);
diff --git a/drivers/gpu/drm/xe/xe_bo.h b/drivers/gpu/drm/xe/xe_bo.h
index effa9d0cf0f6..8354d05ccdf3 100644
--- a/drivers/gpu/drm/xe/xe_bo.h
+++ b/drivers/gpu/drm/xe/xe_bo.h
@@ -39,32 +39,32 @@
#define PPAT_CACHED BIT_ULL(7)
#define PPAT_DISPLAY_ELLC BIT_ULL(4)
-#define GEN8_PTE_SHIFT 12
-#define GEN8_PAGE_SIZE (1 << GEN8_PTE_SHIFT)
-#define GEN8_PTE_MASK (GEN8_PAGE_SIZE - 1)
-#define GEN8_PDE_SHIFT (GEN8_PTE_SHIFT - 3)
-#define GEN8_PDES (1 << GEN8_PDE_SHIFT)
-#define GEN8_PDE_MASK (GEN8_PDES - 1)
-
-#define GEN8_64K_PTE_SHIFT 16
-#define GEN8_64K_PAGE_SIZE (1 << GEN8_64K_PTE_SHIFT)
-#define GEN8_64K_PTE_MASK (GEN8_64K_PAGE_SIZE - 1)
-#define GEN8_64K_PDE_MASK (GEN8_PDE_MASK >> 4)
-
-#define GEN8_PDE_PS_2M BIT_ULL(7)
-#define GEN8_PDPE_PS_1G BIT_ULL(7)
-#define GEN8_PDE_IPS_64K BIT_ULL(11)
-
-#define GEN12_GGTT_PTE_LM BIT_ULL(1)
-#define GEN12_USM_PPGTT_PTE_AE BIT_ULL(10)
-#define GEN12_PPGTT_PTE_LM BIT_ULL(11)
-#define GEN12_PDE_64K BIT_ULL(6)
-#define GEN12_PTE_PS64 BIT_ULL(8)
-
-#define GEN8_PAGE_PRESENT BIT_ULL(0)
-#define GEN8_PAGE_RW BIT_ULL(1)
-
-#define PTE_READ_ONLY BIT(0)
+#define XE_PTE_SHIFT 12
+#define XE_PAGE_SIZE (1 << XE_PTE_SHIFT)
+#define XE_PTE_MASK (XE_PAGE_SIZE - 1)
+#define XE_PDE_SHIFT (XE_PTE_SHIFT - 3)
+#define XE_PDES (1 << XE_PDE_SHIFT)
+#define XE_PDE_MASK (XE_PDES - 1)
+
+#define XE_64K_PTE_SHIFT 16
+#define XE_64K_PAGE_SIZE (1 << XE_64K_PTE_SHIFT)
+#define XE_64K_PTE_MASK (XE_64K_PAGE_SIZE - 1)
+#define XE_64K_PDE_MASK (XE_PDE_MASK >> 4)
+
+#define XE_PDE_PS_2M BIT_ULL(7)
+#define XE_PDPE_PS_1G BIT_ULL(7)
+#define XE_PDE_IPS_64K BIT_ULL(11)
+
+#define XE_GGTT_PTE_LM BIT_ULL(1)
+#define XE_USM_PPGTT_PTE_AE BIT_ULL(10)
+#define XE_PPGTT_PTE_LM BIT_ULL(11)
+#define XE_PDE_64K BIT_ULL(6)
+#define XE_PTE_PS64 BIT_ULL(8)
+
+#define XE_PAGE_PRESENT BIT_ULL(0)
+#define XE_PAGE_RW BIT_ULL(1)
+
+#define XE_PTE_READ_ONLY BIT(0)
#define XE_PL_SYSTEM TTM_PL_SYSTEM
#define XE_PL_TT TTM_PL_TT
diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
index 0ae373b604f6..862e810ef407 100644
--- a/drivers/gpu/drm/xe/xe_ggtt.c
+++ b/drivers/gpu/drm/xe/xe_ggtt.c
@@ -30,11 +30,11 @@ u64 xe_ggtt_pte_encode(struct xe_bo *bo, u64 bo_offset)
u64 pte;
bool is_vram;
- pte = xe_bo_addr(bo, bo_offset, GEN8_PAGE_SIZE, &is_vram);
- pte |= GEN8_PAGE_PRESENT;
+ pte = xe_bo_addr(bo, bo_offset, XE_PAGE_SIZE, &is_vram);
+ pte |= XE_PAGE_PRESENT;
if (is_vram)
- pte |= GEN12_GGTT_PTE_LM;
+ pte |= XE_GGTT_PTE_LM;
/* FIXME: vfunc + pass in caching rules */
if (xe->info.platform == XE_METEORLAKE) {
@@ -56,10 +56,10 @@ static unsigned int probe_gsm_size(struct pci_dev *pdev)
void xe_ggtt_set_pte(struct xe_ggtt *ggtt, u64 addr, u64 pte)
{
- XE_BUG_ON(addr & GEN8_PTE_MASK);
+ XE_BUG_ON(addr & XE_PTE_MASK);
XE_BUG_ON(addr >= ggtt->size);
- writeq(pte, &ggtt->gsm[addr >> GEN8_PTE_SHIFT]);
+ writeq(pte, &ggtt->gsm[addr >> XE_PTE_SHIFT]);
}
static void xe_ggtt_clear(struct xe_ggtt *ggtt, u64 start, u64 size)
@@ -76,7 +76,7 @@ static void xe_ggtt_clear(struct xe_ggtt *ggtt, u64 start, u64 size)
while (start < end) {
xe_ggtt_set_pte(ggtt, start, scratch_pte);
- start += GEN8_PAGE_SIZE;
+ start += XE_PAGE_SIZE;
}
}
@@ -107,7 +107,7 @@ int xe_ggtt_init_noalloc(struct xe_gt *gt, struct xe_ggtt *ggtt)
}
ggtt->gsm = gt->mmio.regs + SZ_8M;
- ggtt->size = (gsm_size / 8) * (u64)GEN8_PAGE_SIZE;
+ ggtt->size = (gsm_size / 8) * (u64) XE_PAGE_SIZE;
if (IS_DGFX(xe) && xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K)
ggtt->flags |= XE_GGTT_FLAGS_64K;
@@ -167,7 +167,7 @@ int xe_ggtt_init(struct xe_gt *gt, struct xe_ggtt *ggtt)
else
flags |= XE_BO_CREATE_VRAM_IF_DGFX(gt);
- ggtt->scratch = xe_bo_create_pin_map(xe, gt, NULL, GEN8_PAGE_SIZE,
+ ggtt->scratch = xe_bo_create_pin_map(xe, gt, NULL, XE_PAGE_SIZE,
ttm_bo_type_kernel,
flags);
@@ -229,8 +229,8 @@ void xe_ggtt_printk(struct xe_ggtt *ggtt, const char *prefix)
scratch_pte = xe_ggtt_pte_encode(ggtt->scratch, 0);
printk("%sGlobal GTT:", prefix);
- for (addr = 0; addr < ggtt->size; addr += GEN8_PAGE_SIZE) {
- unsigned int i = addr / GEN8_PAGE_SIZE;
+ for (addr = 0; addr < ggtt->size; addr += XE_PAGE_SIZE) {
+ unsigned int i = addr / XE_PAGE_SIZE;
XE_BUG_ON(addr > U32_MAX);
if (ggtt->gsm[i] == scratch_pte)
@@ -266,7 +266,7 @@ void xe_ggtt_map_bo(struct xe_ggtt *ggtt, struct xe_bo *bo)
u64 start = bo->ggtt_node.start;
u64 offset, pte;
- for (offset = 0; offset < bo->size; offset += GEN8_PAGE_SIZE) {
+ for (offset = 0; offset < bo->size; offset += XE_PAGE_SIZE) {
pte = xe_ggtt_pte_encode(bo, offset);
xe_ggtt_set_pte(ggtt, start + offset, pte);
}
@@ -278,7 +278,7 @@ static int __xe_ggtt_insert_bo_at(struct xe_ggtt *ggtt, struct xe_bo *bo,
u64 start, u64 end)
{
int err;
- u64 alignment = GEN8_PAGE_SIZE;
+ u64 alignment = XE_PAGE_SIZE;
if (xe_bo_is_vram(bo) && ggtt->flags & XE_GGTT_FLAGS_64K)
alignment = SZ_64K;
diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
index 8686a2a7b035..5acb227f2b5a 100644
--- a/drivers/gpu/drm/xe/xe_migrate.c
+++ b/drivers/gpu/drm/xe/xe_migrate.c
@@ -147,7 +147,7 @@ static int xe_migrate_create_cleared_bo(struct xe_migrate *m, struct xe_vm *vm)
return PTR_ERR(m->cleared_bo);
xe_map_memset(xe, &m->cleared_bo->vmap, 0, 0x00, cleared_size);
- vram_addr = xe_bo_addr(m->cleared_bo, 0, GEN8_PAGE_SIZE, &is_vram);
+ vram_addr = xe_bo_addr(m->cleared_bo, 0, XE_PAGE_SIZE, &is_vram);
XE_BUG_ON(!is_vram);
m->cleared_vram_ofs = xe_migrate_vram_ofs(vram_addr);
@@ -166,9 +166,9 @@ static int xe_migrate_prepare_vm(struct xe_gt *gt, struct xe_migrate *m,
int ret;
/* Can't bump NUM_PT_SLOTS too high */
- BUILD_BUG_ON(NUM_PT_SLOTS > SZ_2M/GEN8_PAGE_SIZE);
+ BUILD_BUG_ON(NUM_PT_SLOTS > SZ_2M/XE_PAGE_SIZE);
/* Must be a multiple of 64K to support all platforms */
- BUILD_BUG_ON(NUM_PT_SLOTS * GEN8_PAGE_SIZE % SZ_64K);
+ BUILD_BUG_ON(NUM_PT_SLOTS * XE_PAGE_SIZE % SZ_64K);
/* And one slot reserved for the 4KiB page table updates */
BUILD_BUG_ON(!(NUM_KERNEL_PDE & 1));
@@ -176,7 +176,7 @@ static int xe_migrate_prepare_vm(struct xe_gt *gt, struct xe_migrate *m,
XE_BUG_ON(m->batch_base_ofs + batch->size >= SZ_2M);
bo = xe_bo_create_pin_map(vm->xe, m->gt, vm,
- num_entries * GEN8_PAGE_SIZE,
+ num_entries * XE_PAGE_SIZE,
ttm_bo_type_kernel,
XE_BO_CREATE_VRAM_IF_DGFX(m->gt) |
XE_BO_CREATE_PINNED_BIT);
@@ -189,14 +189,14 @@ static int xe_migrate_prepare_vm(struct xe_gt *gt, struct xe_migrate *m,
return ret;
}
- entry = gen8_pde_encode(bo, bo->size - GEN8_PAGE_SIZE, XE_CACHE_WB);
+ entry = gen8_pde_encode(bo, bo->size - XE_PAGE_SIZE, XE_CACHE_WB);
xe_pt_write(xe, &vm->pt_root[id]->bo->vmap, 0, entry);
- map_ofs = (num_entries - num_level) * GEN8_PAGE_SIZE;
+ map_ofs = (num_entries - num_level) * XE_PAGE_SIZE;
/* Map the entire BO in our level 0 pt */
for (i = 0, level = 0; i < num_entries; level++) {
- entry = gen8_pte_encode(NULL, bo, i * GEN8_PAGE_SIZE,
+ entry = gen8_pte_encode(NULL, bo, i * XE_PAGE_SIZE,
XE_CACHE_WB, 0, 0);
xe_map_wr(xe, &bo->vmap, map_ofs + level * 8, u64, entry);
@@ -211,10 +211,10 @@ static int xe_migrate_prepare_vm(struct xe_gt *gt, struct xe_migrate *m,
XE_BUG_ON(xe->info.supports_usm);
/* Write out batch too */
- m->batch_base_ofs = NUM_PT_SLOTS * GEN8_PAGE_SIZE;
+ m->batch_base_ofs = NUM_PT_SLOTS * XE_PAGE_SIZE;
for (i = 0; i < batch->size;
- i += vm->flags & XE_VM_FLAGS_64K ? GEN8_64K_PAGE_SIZE :
- GEN8_PAGE_SIZE) {
+ i += vm->flags & XE_VM_FLAGS_64K ? XE_64K_PAGE_SIZE :
+ XE_PAGE_SIZE) {
entry = gen8_pte_encode(NULL, batch, i,
XE_CACHE_WB, 0, 0);
@@ -224,13 +224,13 @@ static int xe_migrate_prepare_vm(struct xe_gt *gt, struct xe_migrate *m,
}
} else {
bool is_vram;
- u64 batch_addr = xe_bo_addr(batch, 0, GEN8_PAGE_SIZE, &is_vram);
+ u64 batch_addr = xe_bo_addr(batch, 0, XE_PAGE_SIZE, &is_vram);
m->batch_base_ofs = xe_migrate_vram_ofs(batch_addr);
if (xe->info.supports_usm) {
batch = gt->usm.bb_pool->bo;
- batch_addr = xe_bo_addr(batch, 0, GEN8_PAGE_SIZE,
+ batch_addr = xe_bo_addr(batch, 0, XE_PAGE_SIZE,
&is_vram);
m->usm_batch_base_ofs = xe_migrate_vram_ofs(batch_addr);
}
@@ -240,20 +240,20 @@ static int xe_migrate_prepare_vm(struct xe_gt *gt, struct xe_migrate *m,
u32 flags = 0;
if (vm->flags & XE_VM_FLAGS_64K && level == 1)
- flags = GEN12_PDE_64K;
+ flags = XE_PDE_64K;
entry = gen8_pde_encode(bo, map_ofs + (level - 1) *
- GEN8_PAGE_SIZE, XE_CACHE_WB);
- xe_map_wr(xe, &bo->vmap, map_ofs + GEN8_PAGE_SIZE * level, u64,
+ XE_PAGE_SIZE, XE_CACHE_WB);
+ xe_map_wr(xe, &bo->vmap, map_ofs + XE_PAGE_SIZE * level, u64,
entry | flags);
}
/* Write PDE's that point to our BO. */
for (i = 0; i < num_entries - num_level; i++) {
- entry = gen8_pde_encode(bo, i * GEN8_PAGE_SIZE,
+ entry = gen8_pde_encode(bo, i * XE_PAGE_SIZE,
XE_CACHE_WB);
- xe_map_wr(xe, &bo->vmap, map_ofs + GEN8_PAGE_SIZE +
+ xe_map_wr(xe, &bo->vmap, map_ofs + XE_PAGE_SIZE +
(i + 1) * 8, u64, entry);
}
@@ -262,9 +262,9 @@ static int xe_migrate_prepare_vm(struct xe_gt *gt, struct xe_migrate *m,
u64 pos, ofs, flags;
level = 2;
- ofs = map_ofs + GEN8_PAGE_SIZE * level + 256 * 8;
- flags = GEN8_PAGE_RW | GEN8_PAGE_PRESENT | PPAT_CACHED |
- GEN12_PPGTT_PTE_LM | GEN8_PDPE_PS_1G;
+ ofs = map_ofs + XE_PAGE_SIZE * level + 256 * 8;
+ flags = XE_PAGE_RW | XE_PAGE_PRESENT | PPAT_CACHED |
+ XE_PPGTT_PTE_LM | XE_PDPE_PS_1G;
/*
* Use 1GB pages, it shouldn't matter the physical amount of
@@ -294,10 +294,10 @@ static int xe_migrate_prepare_vm(struct xe_gt *gt, struct xe_migrate *m,
* the different addresses in VM.
*/
#define NUM_VMUSA_UNIT_PER_PAGE 32
-#define VM_SA_UPDATE_UNIT_SIZE (GEN8_PAGE_SIZE / NUM_VMUSA_UNIT_PER_PAGE)
+#define VM_SA_UPDATE_UNIT_SIZE (XE_PAGE_SIZE / NUM_VMUSA_UNIT_PER_PAGE)
#define NUM_VMUSA_WRITES_PER_UNIT (VM_SA_UPDATE_UNIT_SIZE / sizeof(u64))
drm_suballoc_manager_init(&m->vm_update_sa,
- (map_ofs / GEN8_PAGE_SIZE - NUM_KERNEL_PDE) *
+ (map_ofs / XE_PAGE_SIZE - NUM_KERNEL_PDE) *
NUM_VMUSA_UNIT_PER_PAGE, 0);
m->pt_bo = bo;
@@ -403,7 +403,7 @@ static u32 pte_update_size(struct xe_migrate *m,
if (!is_vram) {
/* Clip L0 to available size */
u64 size = min(*L0, (u64)avail_pts * SZ_2M);
- u64 num_4k_pages = DIV_ROUND_UP(size, GEN8_PAGE_SIZE);
+ u64 num_4k_pages = DIV_ROUND_UP(size, XE_PAGE_SIZE);
*L0 = size;
*L0_ofs = xe_migrate_vm_addr(pt_ofs, 0);
@@ -433,7 +433,7 @@ static void emit_pte(struct xe_migrate *m,
u32 size, struct xe_bo *bo)
{
u32 ptes;
- u64 ofs = at_pt * GEN8_PAGE_SIZE;
+ u64 ofs = at_pt * XE_PAGE_SIZE;
u64 cur_ofs;
/*
@@ -443,7 +443,7 @@ static void emit_pte(struct xe_migrate *m,
* on running tests.
*/
- ptes = DIV_ROUND_UP(size, GEN8_PAGE_SIZE);
+ ptes = DIV_ROUND_UP(size, XE_PAGE_SIZE);
while (ptes) {
u32 chunk = min(0x1ffU, ptes);
@@ -466,13 +466,13 @@ static void emit_pte(struct xe_migrate *m,
if ((m->eng->vm->flags & XE_VM_FLAGS_64K) &&
!(cur_ofs & (16 * 8 - 1))) {
XE_WARN_ON(!IS_ALIGNED(addr, SZ_64K));
- addr |= GEN12_PTE_PS64;
+ addr |= XE_PTE_PS64;
}
addr += vram_region_io_offset(bo->ttm.resource);
- addr |= GEN12_PPGTT_PTE_LM;
+ addr |= XE_PPGTT_PTE_LM;
}
- addr |= PPAT_CACHED | GEN8_PAGE_PRESENT | GEN8_PAGE_RW;
+ addr |= PPAT_CACHED | XE_PAGE_PRESENT | XE_PAGE_RW;
bb->cs[bb->len++] = lower_32_bits(addr);
bb->cs[bb->len++] = upper_32_bits(addr);
@@ -697,7 +697,8 @@ struct dma_fence *xe_migrate_copy(struct xe_migrate *m,
bb->cs[bb->len++] = MI_BATCH_BUFFER_END;
update_idx = bb->len;
- emit_copy(gt, bb, src_L0_ofs, dst_L0_ofs, src_L0, GEN8_PAGE_SIZE);
+ emit_copy(gt, bb, src_L0_ofs, dst_L0_ofs, src_L0,
+ XE_PAGE_SIZE);
flush_flags = xe_migrate_ccs_copy(m, bb, src_L0_ofs, src_is_vram,
dst_L0_ofs, dst_is_vram,
src_L0, ccs_ofs, copy_ccs);
@@ -915,7 +916,7 @@ struct dma_fence *xe_migrate_clear(struct xe_migrate *m,
bb->cs[bb->len++] = MI_BATCH_BUFFER_END;
update_idx = bb->len;
- emit_clear(gt, bb, clear_L0_ofs, clear_L0, GEN8_PAGE_SIZE,
+ emit_clear(gt, bb, clear_L0_ofs, clear_L0, XE_PAGE_SIZE,
clear_vram);
if (xe_device_has_flat_ccs(xe) && clear_vram) {
emit_copy_ccs(gt, bb, clear_L0_ofs, true,
@@ -985,7 +986,7 @@ static void write_pgtable(struct xe_gt *gt, struct xe_bb *bb, u64 ppgtt_ofs,
bool is_vram;
ppgtt_ofs = xe_migrate_vram_ofs(xe_bo_addr(update->pt_bo, 0,
- GEN8_PAGE_SIZE,
+ XE_PAGE_SIZE,
&is_vram));
XE_BUG_ON(!is_vram);
}
@@ -1202,7 +1203,7 @@ xe_migrate_update_pgtables(struct xe_migrate *m,
/* Map our PT's to gtt */
bb->cs[bb->len++] = MI_STORE_DATA_IMM | BIT(21) |
(num_updates * 2 + 1);
- bb->cs[bb->len++] = ppgtt_ofs * GEN8_PAGE_SIZE + page_ofs;
+ bb->cs[bb->len++] = ppgtt_ofs * XE_PAGE_SIZE + page_ofs;
bb->cs[bb->len++] = 0; /* upper_32_bits */
for (i = 0; i < num_updates; i++) {
@@ -1220,9 +1221,9 @@ xe_migrate_update_pgtables(struct xe_migrate *m,
update_idx = bb->len;
addr = xe_migrate_vm_addr(ppgtt_ofs, 0) +
- (page_ofs / sizeof(u64)) * GEN8_PAGE_SIZE;
+ (page_ofs / sizeof(u64)) * XE_PAGE_SIZE;
for (i = 0; i < num_updates; i++)
- write_pgtable(m->gt, bb, addr + i * GEN8_PAGE_SIZE,
+ write_pgtable(m->gt, bb, addr + i * XE_PAGE_SIZE,
&updates[i], pt_update);
} else {
/* phys pages, no preamble required */
diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c
index 6b2943efcdbc..4ee5ea2cabc9 100644
--- a/drivers/gpu/drm/xe/xe_pt.c
+++ b/drivers/gpu/drm/xe/xe_pt.c
@@ -64,8 +64,8 @@ u64 gen8_pde_encode(struct xe_bo *bo, u64 bo_offset,
u64 pde;
bool is_vram;
- pde = xe_bo_addr(bo, bo_offset, GEN8_PAGE_SIZE, &is_vram);
- pde |= GEN8_PAGE_PRESENT | GEN8_PAGE_RW;
+ pde = xe_bo_addr(bo, bo_offset, XE_PAGE_SIZE, &is_vram);
+ pde |= XE_PAGE_PRESENT | XE_PAGE_RW;
XE_WARN_ON(IS_DGFX(xe_bo_device(bo)) && !is_vram);
@@ -101,10 +101,10 @@ static dma_addr_t vma_addr(struct xe_vma *vma, u64 offset,
static u64 __gen8_pte_encode(u64 pte, enum xe_cache_level cache, u32 flags,
u32 pt_level)
{
- pte |= GEN8_PAGE_PRESENT | GEN8_PAGE_RW;
+ pte |= XE_PAGE_PRESENT | XE_PAGE_RW;
- if (unlikely(flags & PTE_READ_ONLY))
- pte &= ~GEN8_PAGE_RW;
+ if (unlikely(flags & XE_PTE_READ_ONLY))
+ pte &= ~XE_PAGE_RW;
/* FIXME: I don't think the PPAT handling is correct for MTL */
@@ -121,9 +121,9 @@ static u64 __gen8_pte_encode(u64 pte, enum xe_cache_level cache, u32 flags,
}
if (pt_level == 1)
- pte |= GEN8_PDE_PS_2M;
+ pte |= XE_PDE_PS_2M;
else if (pt_level == 2)
- pte |= GEN8_PDPE_PS_1G;
+ pte |= XE_PDPE_PS_1G;
/* XXX: Does hw support 1 GiB pages? */
XE_BUG_ON(pt_level > 2);
@@ -153,14 +153,14 @@ u64 gen8_pte_encode(struct xe_vma *vma, struct xe_bo *bo,
bool is_vram;
if (vma)
- pte = vma_addr(vma, offset, GEN8_PAGE_SIZE, &is_vram);
+ pte = vma_addr(vma, offset, XE_PAGE_SIZE, &is_vram);
else
- pte = xe_bo_addr(bo, offset, GEN8_PAGE_SIZE, &is_vram);
+ pte = xe_bo_addr(bo, offset, XE_PAGE_SIZE, &is_vram);
if (is_vram) {
- pte |= GEN12_PPGTT_PTE_LM;
+ pte |= XE_PPGTT_PTE_LM;
if (vma && vma->use_atomic_access_pte_bit)
- pte |= GEN12_USM_PPGTT_PTE_AE;
+ pte |= XE_USM_PPGTT_PTE_AE;
}
return __gen8_pte_encode(pte, cache, flags, pt_level);
@@ -211,7 +211,7 @@ struct xe_pt *xe_pt_create(struct xe_vm *vm, struct xe_gt *gt,
int err;
size = !level ? sizeof(struct xe_pt) : sizeof(struct xe_pt_dir) +
- GEN8_PDES * sizeof(struct drm_pt *);
+ XE_PDES * sizeof(struct drm_pt *);
pt = kzalloc(size, GFP_KERNEL);
if (!pt)
return ERR_PTR(-ENOMEM);
@@ -265,7 +265,7 @@ void xe_pt_populate_empty(struct xe_gt *gt, struct xe_vm *vm,
xe_map_memset(vm->xe, map, 0, 0, SZ_4K);
} else {
empty = __xe_pt_empty_pte(gt, vm, pt->level);
- for (i = 0; i < GEN8_PDES; i++)
+ for (i = 0; i < XE_PDES; i++)
xe_pt_write(vm->xe, map, i, empty);
}
}
@@ -280,7 +280,7 @@ void xe_pt_populate_empty(struct xe_gt *gt, struct xe_vm *vm,
*/
unsigned int xe_pt_shift(unsigned int level)
{
- return GEN8_PTE_SHIFT + GEN8_PDE_SHIFT * level;
+ return XE_PTE_SHIFT + XE_PDE_SHIFT * level;
}
/**
@@ -307,7 +307,7 @@ void xe_pt_destroy(struct xe_pt *pt, u32 flags, struct llist_head *deferred)
if (pt->level > 0 && pt->num_live) {
struct xe_pt_dir *pt_dir = as_xe_pt_dir(pt);
- for (i = 0; i < GEN8_PDES; i++) {
+ for (i = 0; i < XE_PDES; i++) {
if (xe_pt_entry(pt_dir, i))
xe_pt_destroy(xe_pt_entry(pt_dir, i), flags,
deferred);
@@ -489,7 +489,7 @@ xe_pt_new_shared(struct xe_walk_update *wupd, struct xe_pt *parent,
entry->qwords = 0;
if (alloc_entries) {
- entry->pt_entries = kmalloc_array(GEN8_PDES,
+ entry->pt_entries = kmalloc_array(XE_PDES,
sizeof(*entry->pt_entries),
GFP_KERNEL);
if (!entry->pt_entries)
@@ -649,7 +649,7 @@ xe_pt_stage_bind_entry(struct drm_pt *parent, pgoff_t offset,
*/
if (level == 0 && !xe_parent->is_compact) {
if (xe_pt_is_pte_ps64K(addr, next, xe_walk))
- pte |= GEN12_PTE_PS64;
+ pte |= XE_PTE_PS64;
else if (XE_WARN_ON(xe_walk->needs_64K))
return -EINVAL;
}
@@ -699,7 +699,7 @@ xe_pt_stage_bind_entry(struct drm_pt *parent, pgoff_t offset,
if (GRAPHICS_VERx100(xe_walk->gt->xe) >= 1250 && level == 1 &&
covers && xe_pt_scan_64K(addr, next, xe_walk)) {
walk->shifts = xe_compact_pt_shifts;
- flags |= GEN12_PDE_64K;
+ flags |= XE_PDE_64K;
xe_child->is_compact = true;
}
@@ -761,9 +761,9 @@ xe_pt_stage_bind(struct xe_gt *gt, struct xe_vma *vma,
if (is_vram) {
struct xe_gt *bo_gt = xe_bo_to_gt(bo);
- xe_walk.default_pte = GEN12_PPGTT_PTE_LM;
+ xe_walk.default_pte = XE_PPGTT_PTE_LM;
if (vma && vma->use_atomic_access_pte_bit)
- xe_walk.default_pte |= GEN12_USM_PPGTT_PTE_AE;
+ xe_walk.default_pte |= XE_USM_PPGTT_PTE_AE;
xe_walk.dma_offset = bo_gt->mem.vram.io_start -
gt_to_xe(gt)->mem.vram.io_start;
xe_walk.cache = XE_CACHE_WB;
diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
index bdf82d34eb66..272f0f7f24fe 100644
--- a/drivers/gpu/drm/xe/xe_vm.c
+++ b/drivers/gpu/drm/xe/xe_vm.c
@@ -59,7 +59,7 @@ int xe_vma_userptr_pin_pages(struct xe_vma *vma)
bool in_kthread = !current->mm;
unsigned long notifier_seq;
int pinned, ret, i;
- bool read_only = vma->pte_flags & PTE_READ_ONLY;
+ bool read_only = vma->pte_flags & XE_PTE_READ_ONLY;
lockdep_assert_held(&vm->lock);
XE_BUG_ON(!xe_vma_is_userptr(vma));
@@ -844,7 +844,7 @@ static struct xe_vma *xe_vma_create(struct xe_vm *vm,
vma->start = start;
vma->end = end;
if (read_only)
- vma->pte_flags = PTE_READ_ONLY;
+ vma->pte_flags = XE_PTE_READ_ONLY;
if (gt_mask) {
vma->gt_mask = gt_mask;
@@ -897,7 +897,7 @@ static void xe_vma_destroy_late(struct xe_vma *vma)
{
struct xe_vm *vm = vma->vm;
struct xe_device *xe = vm->xe;
- bool read_only = vma->pte_flags & PTE_READ_ONLY;
+ bool read_only = vma->pte_flags & XE_PTE_READ_ONLY;
if (xe_vma_is_userptr(vma)) {
if (vma->userptr.sg) {
@@ -1902,7 +1902,7 @@ int xe_vm_create_ioctl(struct drm_device *dev, void *data,
#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
/* Warning: Security issue - never enable by default */
- args->reserved[0] = xe_bo_main_addr(vm->pt_root[0]->bo, GEN8_PAGE_SIZE);
+ args->reserved[0] = xe_bo_main_addr(vm->pt_root[0]->bo, XE_PAGE_SIZE);
#endif
return 0;
@@ -2593,7 +2593,7 @@ static struct xe_vma *vm_unbind_lookup_vmas(struct xe_vm *vm,
first->userptr.ptr,
first->start,
lookup->start - 1,
- (first->pte_flags & PTE_READ_ONLY),
+ (first->pte_flags & XE_PTE_READ_ONLY),
first->gt_mask);
if (first->bo)
xe_bo_unlock(first->bo, &ww);
@@ -2624,7 +2624,7 @@ static struct xe_vma *vm_unbind_lookup_vmas(struct xe_vm *vm,
last->userptr.ptr + chunk,
last->start + chunk,
last->end,
- (last->pte_flags & PTE_READ_ONLY),
+ (last->pte_flags & XE_PTE_READ_ONLY),
last->gt_mask);
if (last->bo)
xe_bo_unlock(last->bo, &ww);
@@ -3381,7 +3381,8 @@ int xe_analyze_vm(struct drm_printer *p, struct xe_vm *vm, int gt_id)
return 0;
}
if (vm->pt_root[gt_id]) {
- addr = xe_bo_addr(vm->pt_root[gt_id]->bo, 0, GEN8_PAGE_SIZE, &is_vram);
+ addr = xe_bo_addr(vm->pt_root[gt_id]->bo, 0, XE_PAGE_SIZE,
+ &is_vram);
drm_printf(p, " VM root: A:0x%llx %s\n", addr, is_vram ? "VRAM" : "SYS");
}
@@ -3392,10 +3393,11 @@ int xe_analyze_vm(struct drm_printer *p, struct xe_vm *vm, int gt_id)
if (is_userptr) {
struct xe_res_cursor cur;
- xe_res_first_sg(vma->userptr.sg, 0, GEN8_PAGE_SIZE, &cur);
+ xe_res_first_sg(vma->userptr.sg, 0, XE_PAGE_SIZE,
+ &cur);
addr = xe_res_dma(&cur);
} else {
- addr = xe_bo_addr(vma->bo, 0, GEN8_PAGE_SIZE, &is_vram);
+ addr = xe_bo_addr(vma->bo, 0, XE_PAGE_SIZE, &is_vram);
}
drm_printf(p, " [%016llx-%016llx] S:0x%016llx A:%016llx %s\n",
vma->start, vma->end, vma->end - vma->start + 1ull,
--
2.39.0
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Intel-xe] [PATCH 02/17] fixup! drm/i915/display: Remaining changes to make xe compile
2023-04-19 7:44 [Intel-xe] [PATCH 00/17] Cleanup registers and introduce xe_reg_t Lucas De Marchi
2023-04-19 7:44 ` [Intel-xe] [PATCH 01/17] drm/xe: Cleanup page-related defines Lucas De Marchi
@ 2023-04-19 7:44 ` Lucas De Marchi
2023-04-19 7:44 ` [Intel-xe] [PATCH 03/17] fixup! drm/i915/display: Allow fbdev to allocate stolen memory Lucas De Marchi
` (18 subsequent siblings)
20 siblings, 0 replies; 41+ messages in thread
From: Lucas De Marchi @ 2023-04-19 7:44 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, Matt Roper, Rodrigo Vivi
---
drivers/gpu/drm/i915/display/intel_fbdev.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c
index ed996546edfc..46447dd58f3f 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -165,7 +165,7 @@ static int intelfb_alloc(struct drm_fb_helper *helper,
DIV_ROUND_UP(sizes->surface_bpp, 8), 64);
#else
mode_cmd.pitches[0] = ALIGN(mode_cmd.width *
- DIV_ROUND_UP(sizes->surface_bpp, 8), GEN8_PAGE_SIZE);
+ DIV_ROUND_UP(sizes->surface_bpp, 8), XE_PAGE_SIZE);
#endif
mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
sizes->surface_depth);
--
2.39.0
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Intel-xe] [PATCH 03/17] fixup! drm/i915/display: Allow fbdev to allocate stolen memory
2023-04-19 7:44 [Intel-xe] [PATCH 00/17] Cleanup registers and introduce xe_reg_t Lucas De Marchi
2023-04-19 7:44 ` [Intel-xe] [PATCH 01/17] drm/xe: Cleanup page-related defines Lucas De Marchi
2023-04-19 7:44 ` [Intel-xe] [PATCH 02/17] fixup! drm/i915/display: Remaining changes to make xe compile Lucas De Marchi
@ 2023-04-19 7:44 ` Lucas De Marchi
2023-04-19 7:44 ` [Intel-xe] [PATCH 04/17] drm/xe: Rename RC0/RC6 macros Lucas De Marchi
` (17 subsequent siblings)
20 siblings, 0 replies; 41+ messages in thread
From: Lucas De Marchi @ 2023-04-19 7:44 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, Matt Roper, Rodrigo Vivi
---
drivers/gpu/drm/i915/display/intel_fbdev.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c
index 46447dd58f3f..2d2388cbc626 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -349,7 +349,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
else
info->fix.smem_start =
pci_resource_start(pdev, 2) +
- xe_bo_addr(obj, 0, GEN8_PAGE_SIZE, &lmem);
+ xe_bo_addr(obj, 0, XE_PAGE_SIZE, &lmem);
info->fix.smem_len = obj->ttm.base.size;
} else {
--
2.39.0
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Intel-xe] [PATCH 04/17] drm/xe: Rename RC0/RC6 macros
2023-04-19 7:44 [Intel-xe] [PATCH 00/17] Cleanup registers and introduce xe_reg_t Lucas De Marchi
` (2 preceding siblings ...)
2023-04-19 7:44 ` [Intel-xe] [PATCH 03/17] fixup! drm/i915/display: Allow fbdev to allocate stolen memory Lucas De Marchi
@ 2023-04-19 7:44 ` Lucas De Marchi
2023-04-19 7:44 ` [Intel-xe] [PATCH 05/17] drm/xe: Rename instruction field to avoid confusion Lucas De Marchi
` (16 subsequent siblings)
20 siblings, 0 replies; 41+ messages in thread
From: Lucas De Marchi @ 2023-04-19 7:44 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, Matt Roper, Rodrigo Vivi
Follow up commits will mass-remove the gen prefix/suffix. For GEN6_RC0
and GEN6_RC6 that would make the variable too short and easy to
conflict. So, add "GT_" prefix that is also part of the register name.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 4 ++--
drivers/gpu/drm/xe/xe_guc_pc.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index f174758d8307..778d34afae93 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -345,8 +345,8 @@
#define GEN6_GT_CORE_STATUS _MMIO(0x138060)
#define RCN_MASK REG_GENMASK(2, 0)
-#define GEN6_RC0 0
-#define GEN6_RC6 3
+#define GT_RC0 0
+#define GT_RC6 3
#define GEN6_GT_GFX_RC6_LOCKED _MMIO(0x138104)
#define GEN6_GT_GFX_RC6 _MMIO(0x138108)
diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
index 5a8d827ba770..2f98544736ae 100644
--- a/drivers/gpu/drm/xe/xe_guc_pc.c
+++ b/drivers/gpu/drm/xe/xe_guc_pc.c
@@ -592,9 +592,9 @@ static ssize_t rc_status_show(struct device *dev,
xe_device_mem_access_put(gt_to_xe(gt));
switch (REG_FIELD_GET(RCN_MASK, reg)) {
- case GEN6_RC6:
+ case GT_RC6:
return sysfs_emit(buff, "rc6\n");
- case GEN6_RC0:
+ case GT_RC0:
return sysfs_emit(buff, "rc0\n");
default:
return -ENOENT;
--
2.39.0
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Intel-xe] [PATCH 05/17] drm/xe: Rename instruction field to avoid confusion
2023-04-19 7:44 [Intel-xe] [PATCH 00/17] Cleanup registers and introduce xe_reg_t Lucas De Marchi
` (3 preceding siblings ...)
2023-04-19 7:44 ` [Intel-xe] [PATCH 04/17] drm/xe: Rename RC0/RC6 macros Lucas De Marchi
@ 2023-04-19 7:44 ` Lucas De Marchi
2023-04-19 7:44 ` [Intel-xe] [PATCH 06/17] drm/xe/guc: Rename GEN11_SOFT_SCRATCH for clarity Lucas De Marchi
` (15 subsequent siblings)
20 siblings, 0 replies; 41+ messages in thread
From: Lucas De Marchi @ 2023-04-19 7:44 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, Matt Roper, Rodrigo Vivi
There was both BLT_DEPTH_32 and XY_FAST_COLOR_BLT_DEPTH_32 - also add
the prefix to the first to make it clear this is about the FAST_**COPY**
operation. While at it, remove the GEN9_ prefix.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/regs/xe_gpu_commands.h | 4 ++--
drivers/gpu/drm/xe/xe_migrate.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/xe/regs/xe_gpu_commands.h b/drivers/gpu/drm/xe/regs/xe_gpu_commands.h
index 9d6508d74d62..05531d43514f 100644
--- a/drivers/gpu/drm/xe/regs/xe_gpu_commands.h
+++ b/drivers/gpu/drm/xe/regs/xe_gpu_commands.h
@@ -55,8 +55,8 @@
#define XY_FAST_COLOR_BLT_MOCS_MASK GENMASK(27, 21)
#define XY_FAST_COLOR_BLT_MEM_TYPE_SHIFT 31
-#define GEN9_XY_FAST_COPY_BLT_CMD (2 << 29 | 0x42 << 22)
-#define BLT_DEPTH_32 (3<<24)
+#define XY_FAST_COPY_BLT_CMD (2 << 29 | 0x42 << 22)
+#define XY_FAST_COPY_BLT_DEPTH_32 (3<<24)
#define PVC_MEM_SET_CMD (2 << 29 | 0x5b << 22)
#define PVC_MEM_SET_CMD_LEN_DW 7
diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
index 5acb227f2b5a..f40f47ccb76f 100644
--- a/drivers/gpu/drm/xe/xe_migrate.c
+++ b/drivers/gpu/drm/xe/xe_migrate.c
@@ -518,8 +518,8 @@ static void emit_copy(struct xe_gt *gt, struct xe_bb *bb,
XE_BUG_ON(pitch / 4 > S16_MAX);
XE_BUG_ON(pitch > U16_MAX);
- bb->cs[bb->len++] = GEN9_XY_FAST_COPY_BLT_CMD | (10 - 2);
- bb->cs[bb->len++] = BLT_DEPTH_32 | pitch;
+ bb->cs[bb->len++] = XY_FAST_COPY_BLT_CMD | (10 - 2);
+ bb->cs[bb->len++] = XY_FAST_COPY_BLT_DEPTH_32 | pitch;
bb->cs[bb->len++] = 0;
bb->cs[bb->len++] = (size / pitch) << 16 | pitch / 4;
bb->cs[bb->len++] = lower_32_bits(dst_ofs);
--
2.39.0
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Intel-xe] [PATCH 06/17] drm/xe/guc: Rename GEN11_SOFT_SCRATCH for clarity
2023-04-19 7:44 [Intel-xe] [PATCH 00/17] Cleanup registers and introduce xe_reg_t Lucas De Marchi
` (4 preceding siblings ...)
2023-04-19 7:44 ` [Intel-xe] [PATCH 05/17] drm/xe: Rename instruction field to avoid confusion Lucas De Marchi
@ 2023-04-19 7:44 ` Lucas De Marchi
2023-04-19 7:44 ` [Intel-xe] [PATCH 07/17] drm/xe/guc: Move GuC registers to regs/ Lucas De Marchi
` (14 subsequent siblings)
20 siblings, 0 replies; 41+ messages in thread
From: Lucas De Marchi @ 2023-04-19 7:44 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, Matt Roper, Rodrigo Vivi
That register is a completely different register, it's not the same as
SOFT_SCRATCH for GEN11 and beyond. Rename to to the same name as the
bspec uses, including the new variant for media. Also, move the
definitions to the guc header.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/xe_guc.c | 26 +++++++++++---------------
drivers/gpu/drm/xe/xe_guc_reg.h | 9 ++++++---
2 files changed, 17 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index ee71b969bcbf..ff2df4f30e97 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -622,9 +622,6 @@ int xe_guc_auth_huc(struct xe_guc *guc, u32 rsa_addr)
return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action));
}
-#define MEDIA_SOFT_SCRATCH(n) _MMIO(0x190310 + (n) * 4)
-#define MEDIA_SOFT_SCRATCH_COUNT 4
-
int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request,
u32 len, u32 *response_buf)
{
@@ -632,15 +629,17 @@ int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request,
struct xe_gt *gt = guc_to_gt(guc);
u32 header, reply;
u32 reply_reg = xe_gt_is_media_type(gt) ?
- MEDIA_SOFT_SCRATCH(0).reg : GEN11_SOFT_SCRATCH(0).reg;
+ MED_VF_SW_FLAG(0).reg : VF_SW_FLAG(0).reg;
+ const u32 LAST_INDEX = VF_SW_FLAG_COUNT;
int ret;
int i;
- BUILD_BUG_ON(GEN11_SOFT_SCRATCH_COUNT != MEDIA_SOFT_SCRATCH_COUNT);
+ BUILD_BUG_ON(VF_SW_FLAG_COUNT != MED_VF_SW_FLAG_COUNT);
+
XE_BUG_ON(guc->ct.enabled);
XE_BUG_ON(!len);
- XE_BUG_ON(len > GEN11_SOFT_SCRATCH_COUNT);
- XE_BUG_ON(len > MEDIA_SOFT_SCRATCH_COUNT);
+ XE_BUG_ON(len > VF_SW_FLAG_COUNT);
+ XE_BUG_ON(len > MED_VF_SW_FLAG_COUNT);
XE_BUG_ON(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, request[0]) !=
GUC_HXG_ORIGIN_HOST);
XE_BUG_ON(FIELD_GET(GUC_HXG_MSG_0_TYPE, request[0]) !=
@@ -650,17 +649,14 @@ int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request,
/* Not in critical data-path, just do if else for GT type */
if (xe_gt_is_media_type(gt)) {
for (i = 0; i < len; ++i)
- xe_mmio_write32(gt, MEDIA_SOFT_SCRATCH(i).reg,
+ xe_mmio_write32(gt, MED_VF_SW_FLAG(i).reg,
request[i]);
-#define LAST_INDEX MEDIA_SOFT_SCRATCH_COUNT - 1
- xe_mmio_read32(gt, MEDIA_SOFT_SCRATCH(LAST_INDEX).reg);
+ xe_mmio_read32(gt, MED_VF_SW_FLAG(LAST_INDEX).reg);
} else {
for (i = 0; i < len; ++i)
- xe_mmio_write32(gt, GEN11_SOFT_SCRATCH(i).reg,
+ xe_mmio_write32(gt, VF_SW_FLAG(i).reg,
request[i]);
-#undef LAST_INDEX
-#define LAST_INDEX GEN11_SOFT_SCRATCH_COUNT - 1
- xe_mmio_read32(gt, GEN11_SOFT_SCRATCH(LAST_INDEX).reg);
+ xe_mmio_read32(gt, VF_SW_FLAG(LAST_INDEX).reg);
}
xe_guc_notify(guc);
@@ -724,7 +720,7 @@ int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request,
if (response_buf) {
response_buf[0] = header;
- for (i = 1; i < GEN11_SOFT_SCRATCH_COUNT; i++)
+ for (i = 1; i < VF_SW_FLAG_COUNT; i++)
response_buf[i] =
xe_mmio_read32(gt, reply_reg + i * sizeof(u32));
}
diff --git a/drivers/gpu/drm/xe/xe_guc_reg.h b/drivers/gpu/drm/xe/xe_guc_reg.h
index efd60c186bbc..0cd38d51cc60 100644
--- a/drivers/gpu/drm/xe/xe_guc_reg.h
+++ b/drivers/gpu/drm/xe/xe_guc_reg.h
@@ -35,9 +35,6 @@
#define SOFT_SCRATCH(n) _MMIO(0xc180 + (n) * 4)
#define SOFT_SCRATCH_COUNT 16
-#define GEN11_SOFT_SCRATCH(n) _MMIO(0x190240 + (n) * 4)
-#define GEN11_SOFT_SCRATCH_COUNT 4
-
#define UOS_RSA_SCRATCH(i) _MMIO(0xc200 + (i) * 4)
#define UOS_RSA_SCRATCH_COUNT 64
@@ -130,6 +127,12 @@ struct guc_doorbell_info {
#define GUC_WD_VECS_IER _MMIO(0xC558)
#define GUC_PM_P24C_IER _MMIO(0xC55C)
+#define VF_SW_FLAG(n) _MMIO(0x190240 + (n) * 4)
+#define VF_SW_FLAG_COUNT 4
+
+#define MED_VF_SW_FLAG(n) _MMIO(0x190310 + (n) * 4)
+#define MED_VF_SW_FLAG_COUNT 4
+
/* GuC Interrupt Vector */
#define GUC_INTR_GUC2HOST BIT(15)
#define GUC_INTR_EXEC_ERROR BIT(14)
--
2.39.0
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Intel-xe] [PATCH 07/17] drm/xe/guc: Move GuC registers to regs/
2023-04-19 7:44 [Intel-xe] [PATCH 00/17] Cleanup registers and introduce xe_reg_t Lucas De Marchi
` (5 preceding siblings ...)
2023-04-19 7:44 ` [Intel-xe] [PATCH 06/17] drm/xe/guc: Rename GEN11_SOFT_SCRATCH for clarity Lucas De Marchi
@ 2023-04-19 7:44 ` Lucas De Marchi
2023-04-19 7:44 ` [Intel-xe] [PATCH 08/17] drm/xe/guc: Convert GuC registers to REG_FIELD/REG_BIT Lucas De Marchi
` (13 subsequent siblings)
20 siblings, 0 replies; 41+ messages in thread
From: Lucas De Marchi @ 2023-04-19 7:44 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, Matt Roper, Rodrigo Vivi
There's no good reason to keep the GuC registers outside the regs/
directory: move the header with GuC registers under that.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/{xe_guc_reg.h => regs/xe_guc_regs.h} | 4 ++--
drivers/gpu/drm/xe/xe_guc.c | 2 +-
drivers/gpu/drm/xe/xe_guc_ads.c | 2 +-
drivers/gpu/drm/xe/xe_huc.c | 2 +-
drivers/gpu/drm/xe/xe_uc_fw.c | 2 +-
drivers/gpu/drm/xe/xe_wopcm.c | 2 +-
6 files changed, 7 insertions(+), 7 deletions(-)
rename drivers/gpu/drm/xe/{xe_guc_reg.h => regs/xe_guc_regs.h} (99%)
diff --git a/drivers/gpu/drm/xe/xe_guc_reg.h b/drivers/gpu/drm/xe/regs/xe_guc_regs.h
similarity index 99%
rename from drivers/gpu/drm/xe/xe_guc_reg.h
rename to drivers/gpu/drm/xe/regs/xe_guc_regs.h
index 0cd38d51cc60..011868ff38aa 100644
--- a/drivers/gpu/drm/xe/xe_guc_reg.h
+++ b/drivers/gpu/drm/xe/regs/xe_guc_regs.h
@@ -3,8 +3,8 @@
* Copyright © 2022 Intel Corporation
*/
-#ifndef _XE_GUC_REG_H_
-#define _XE_GUC_REG_H_
+#ifndef _XE_GUC_REGS_H_
+#define _XE_GUC_REGS_H_
#include <linux/compiler.h>
#include <linux/types.h>
diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index ff2df4f30e97..e00177f4d294 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -6,6 +6,7 @@
#include "xe_guc.h"
#include "regs/xe_gt_regs.h"
+#include "regs/xe_guc_regs.h"
#include "xe_bo.h"
#include "xe_device.h"
#include "xe_force_wake.h"
@@ -15,7 +16,6 @@
#include "xe_guc_hwconfig.h"
#include "xe_guc_log.h"
#include "xe_guc_pc.h"
-#include "xe_guc_reg.h"
#include "xe_guc_submit.h"
#include "xe_mmio.h"
#include "xe_platform_types.h"
diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index fd9911ffeae4..fe1d5be1241e 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -9,10 +9,10 @@
#include "regs/xe_engine_regs.h"
#include "regs/xe_gt_regs.h"
+#include "regs/xe_guc_regs.h"
#include "xe_bo.h"
#include "xe_gt.h"
#include "xe_guc.h"
-#include "xe_guc_reg.h"
#include "xe_hw_engine.h"
#include "xe_lrc.h"
#include "xe_map.h"
diff --git a/drivers/gpu/drm/xe/xe_huc.c b/drivers/gpu/drm/xe/xe_huc.c
index a9448c6f6418..a1c3e54faa6e 100644
--- a/drivers/gpu/drm/xe/xe_huc.c
+++ b/drivers/gpu/drm/xe/xe_huc.c
@@ -5,12 +5,12 @@
#include "xe_huc.h"
+#include "regs/xe_guc_regs.h"
#include "xe_bo.h"
#include "xe_device.h"
#include "xe_force_wake.h"
#include "xe_gt.h"
#include "xe_guc.h"
-#include "xe_guc_reg.h"
#include "xe_mmio.h"
#include "xe_uc_fw.h"
diff --git a/drivers/gpu/drm/xe/xe_uc_fw.c b/drivers/gpu/drm/xe/xe_uc_fw.c
index 97328e441f0f..cd5433b5c970 100644
--- a/drivers/gpu/drm/xe/xe_uc_fw.c
+++ b/drivers/gpu/drm/xe/xe_uc_fw.c
@@ -8,11 +8,11 @@
#include <drm/drm_managed.h>
+#include "regs/xe_guc_regs.h"
#include "xe_bo.h"
#include "xe_device_types.h"
#include "xe_force_wake.h"
#include "xe_gt.h"
-#include "xe_guc_reg.h"
#include "xe_map.h"
#include "xe_mmio.h"
#include "xe_uc_fw.h"
diff --git a/drivers/gpu/drm/xe/xe_wopcm.c b/drivers/gpu/drm/xe/xe_wopcm.c
index c8cc3f5e6154..7b5014aea9c8 100644
--- a/drivers/gpu/drm/xe/xe_wopcm.c
+++ b/drivers/gpu/drm/xe/xe_wopcm.c
@@ -5,10 +5,10 @@
#include "xe_wopcm.h"
+#include "regs/xe_guc_regs.h"
#include "xe_device.h"
#include "xe_force_wake.h"
#include "xe_gt.h"
-#include "xe_guc_reg.h"
#include "xe_mmio.h"
#include "xe_uc_fw.h"
--
2.39.0
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Intel-xe] [PATCH 08/17] drm/xe/guc: Convert GuC registers to REG_FIELD/REG_BIT
2023-04-19 7:44 [Intel-xe] [PATCH 00/17] Cleanup registers and introduce xe_reg_t Lucas De Marchi
` (6 preceding siblings ...)
2023-04-19 7:44 ` [Intel-xe] [PATCH 07/17] drm/xe/guc: Move GuC registers to regs/ Lucas De Marchi
@ 2023-04-19 7:44 ` Lucas De Marchi
2023-04-19 7:44 ` [Intel-xe] [PATCH 09/17] drm/xe: Drop gen prefixes and suffixes from registers Lucas De Marchi
` (12 subsequent siblings)
20 siblings, 0 replies; 41+ messages in thread
From: Lucas De Marchi @ 2023-04-19 7:44 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, Matt Roper, Rodrigo Vivi
Cleanup GuC register declarations by converting them to use REG_FIELD,
REG_BIT and REG_GENMASK. While converting, also reorder the bitfields
so they follow the convention of declaring the higher bits first.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/regs/xe_guc_regs.h | 168 +++++++++++++-------------
drivers/gpu/drm/xe/xe_ggtt.c | 6 +-
drivers/gpu/drm/xe/xe_guc.c | 8 +-
drivers/gpu/drm/xe/xe_guc_ads.c | 3 +-
4 files changed, 89 insertions(+), 96 deletions(-)
diff --git a/drivers/gpu/drm/xe/regs/xe_guc_regs.h b/drivers/gpu/drm/xe/regs/xe_guc_regs.h
index 011868ff38aa..facb1f0a55b6 100644
--- a/drivers/gpu/drm/xe/regs/xe_guc_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_guc_regs.h
@@ -14,23 +14,18 @@
/* Definitions of GuC H/W registers, bits, etc */
#define GUC_STATUS _MMIO(0xc000)
-#define GS_RESET_SHIFT 0
-#define GS_MIA_IN_RESET (0x01 << GS_RESET_SHIFT)
-#define GS_BOOTROM_SHIFT 1
-#define GS_BOOTROM_MASK (0x7F << GS_BOOTROM_SHIFT)
-#define GS_BOOTROM_RSA_FAILED (0x50 << GS_BOOTROM_SHIFT)
-#define GS_BOOTROM_JUMP_PASSED (0x76 << GS_BOOTROM_SHIFT)
-#define GS_UKERNEL_SHIFT 8
-#define GS_UKERNEL_MASK (0xFF << GS_UKERNEL_SHIFT)
-#define GS_MIA_SHIFT 16
-#define GS_MIA_MASK (0x07 << GS_MIA_SHIFT)
-#define GS_MIA_CORE_STATE (0x01 << GS_MIA_SHIFT)
-#define GS_MIA_HALT_REQUESTED (0x02 << GS_MIA_SHIFT)
-#define GS_MIA_ISR_ENTRY (0x04 << GS_MIA_SHIFT)
-#define GS_AUTH_STATUS_SHIFT 30
-#define GS_AUTH_STATUS_MASK (0x03 << GS_AUTH_STATUS_SHIFT)
-#define GS_AUTH_STATUS_BAD (0x01 << GS_AUTH_STATUS_SHIFT)
-#define GS_AUTH_STATUS_GOOD (0x02 << GS_AUTH_STATUS_SHIFT)
+#define GS_AUTH_STATUS_MASK REG_GENMASK(31, 30)
+#define GS_AUTH_STATUS_BAD REG_FIELD_PREP(GS_AUTH_STATUS_MASK, 0x1)
+#define GS_AUTH_STATUS_GOOD REG_FIELD_PREP(GS_AUTH_STATUS_MASK, 0x2)
+#define GS_MIA_MASK REG_GENMASK(18, 16)
+#define GS_MIA_CORE_STATE REG_FIELD_PREP(GS_MIA_MASK, 0x1)
+#define GS_MIA_HALT_REQUESTED REG_FIELD_PREP(GS_MIA_MASK, 0x2)
+#define GS_MIA_ISR_ENTRY REG_FIELD_PREP(GS_MIA_MASK, 0x4)
+#define GS_UKERNEL_MASK REG_GENMASK(15, 8)
+#define GS_BOOTROM_MASK REG_GENMASK(7, 1)
+#define GS_BOOTROM_RSA_FAILED REG_FIELD_PREP(GS_BOOTROM_MASK, 0x50)
+#define GS_BOOTROM_JUMP_PASSED REG_FIELD_PREP(GS_BOOTROM_MASK, 0x76)
+#define GS_MIA_IN_RESET REG_BIT(0)
#define SOFT_SCRATCH(n) _MMIO(0xc180 + (n) * 4)
#define SOFT_SCRATCH_COUNT 16
@@ -42,90 +37,89 @@
#define DMA_ADDR_0_HIGH _MMIO(0xc304)
#define DMA_ADDR_1_LOW _MMIO(0xc308)
#define DMA_ADDR_1_HIGH _MMIO(0xc30c)
-#define DMA_ADDRESS_SPACE_WOPCM (7 << 16)
-#define DMA_ADDRESS_SPACE_GTT (8 << 16)
+#define DMA_ADDR_SPACE_MASK REG_GENMASK(20, 16)
+#define DMA_ADDRESS_SPACE_WOPCM REG_FIELD_PREP(DMA_ADDR_SPACE_MASK, 7)
+#define DMA_ADDRESS_SPACE_GTT REG_FIEDL_PREP(DMA_ADDR_SPACE_MASK, 8)
#define DMA_COPY_SIZE _MMIO(0xc310)
#define DMA_CTRL _MMIO(0xc314)
-#define HUC_UKERNEL (1<<9)
-#define UOS_MOVE (1<<4)
-#define START_DMA (1<<0)
+#define HUC_UKERNEL REG_BIT(9)
+#define UOS_MOVE REG_BIT(4)
+#define START_DMA REG_BIT(0)
#define DMA_GUC_WOPCM_OFFSET _MMIO(0xc340)
-#define GUC_WOPCM_OFFSET_VALID (1<<0)
-#define HUC_LOADING_AGENT_VCR (0<<1)
-#define HUC_LOADING_AGENT_GUC (1<<1)
#define GUC_WOPCM_OFFSET_SHIFT 14
-#define GUC_WOPCM_OFFSET_MASK (0x3ffff << GUC_WOPCM_OFFSET_SHIFT)
-#define GUC_MAX_IDLE_COUNT _MMIO(0xC3E4)
+#define GUC_WOPCM_OFFSET_MASK REG_GENMASK(31, GUC_WOPCM_OFFSET_SHIFT)
+#define HUC_LOADING_AGENT_MASK REG_BIT(1)
+#define HUC_LOADING_AGENT_VCR REG_FIELD_PREP(HUC_LOADING_AGENT_MASK, 0)
+#define HUC_LOADING_AGENT_GUC REG_FIELD_PREP(HUC_LOADING_AGENT_MASK, 1)
+#define GUC_WOPCM_OFFSET_VALID REG_BIT(0)
+#define GUC_MAX_IDLE_COUNT _MMIO(0xc3e4)
-#define HUC_STATUS2 _MMIO(0xD3B0)
-#define HUC_FW_VERIFIED (1<<7)
+#define HUC_STATUS2 _MMIO(0xd3b0)
+#define HUC_FW_VERIFIED REG_BIT(7)
-#define GEN11_HUC_KERNEL_LOAD_INFO _MMIO(0xC1DC)
-#define HUC_LOAD_SUCCESSFUL (1 << 0)
+#define GEN11_HUC_KERNEL_LOAD_INFO _MMIO(0xc1dc)
+#define HUC_LOAD_SUCCESSFUL REG_BIT(0)
#define GUC_WOPCM_SIZE _MMIO(0xc050)
-#define GUC_WOPCM_SIZE_LOCKED (1<<0)
-#define GUC_WOPCM_SIZE_SHIFT 12
-#define GUC_WOPCM_SIZE_MASK (0xfffff << GUC_WOPCM_SIZE_SHIFT)
+#define GUC_WOPCM_SIZE_MASK REG_GENMASK(31, 12)
+#define GUC_WOPCM_SIZE_LOCKED REG_BIT(0)
#define GEN8_GT_PM_CONFIG _MMIO(0x138140)
#define GEN9LP_GT_PM_CONFIG _MMIO(0x138140)
#define GEN9_GT_PM_CONFIG _MMIO(0x13816c)
-#define GT_DOORBELL_ENABLE (1<<0)
+#define GT_DOORBELL_ENABLE REG_BIT(0)
#define GEN8_GTCR _MMIO(0x4274)
-#define GEN8_GTCR_INVALIDATE (1<<0)
-
-#define GEN12_GUC_TLB_INV_CR _MMIO(0xcee8)
-#define GEN12_GUC_TLB_INV_CR_INVALIDATE (1 << 0)
-
-#define GUC_ARAT_C6DIS _MMIO(0xA178)
-
-#define GUC_SHIM_CONTROL _MMIO(0xc064)
-#define GUC_DISABLE_SRAM_INIT_TO_ZEROES (1<<0)
-#define GUC_ENABLE_READ_CACHE_LOGIC (1<<1)
-#define GUC_ENABLE_MIA_CACHING (1<<2)
-#define GUC_GEN10_MSGCH_ENABLE (1<<4)
-#define GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA (1<<9)
-#define GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA (1<<10)
-#define GUC_ENABLE_MIA_CLOCK_GATING (1<<15)
-#define GUC_GEN10_SHIM_WC_ENABLE (1<<21)
+#define GEN8_GTCR_INVALIDATE REG_BIT(0)
+
+#define GEN12_GUC_TLB_INV_CR _MMIO(0xcee8)
+#define GEN12_GUC_TLB_INV_CR_INVALIDATE REG_BIT(0)
+
+#define GUC_ARAT_C6DIS _MMIO(0xa178)
+
+#define GUC_SHIM_CONTROL _MMIO(0xc064)
#define PVC_GUC_MOCS_INDEX_MASK REG_GENMASK(25, 24)
-#define PVC_MOCS_UC_INDEX 1
-#define PVC_GUC_MOCS_INDEX(index) REG_FIELD_PREP(PVC_GUC_MOCS_INDEX_MASK,\
+#define PVC_GUC_MOCS_UC_INDEX 1
+#define PVC_GUC_MOCS_INDEX(index) REG_FIELD_PREP(PVC_GUC_MOCS_INDEX_MASK, \
index)
+#define GUC_GEN10_SHIM_WC_ENABLE REG_BIT(21)
+#define GUC_ENABLE_MIA_CLOCK_GATING REG_BIT(15)
+#define GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA REG_BIT(10)
+#define GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA REG_BIT(9)
+#define GUC_GEN10_MSGCH_ENABLE REG_BIT(4)
+#define GUC_ENABLE_MIA_CACHING REG_BIT(2)
+#define GUC_ENABLE_READ_CACHE_LOGIC REG_BIT(1)
+#define GUC_DISABLE_SRAM_INIT_TO_ZEROES REG_BIT(0)
-#define GUC_SEND_INTERRUPT _MMIO(0xc4c8)
-#define GUC_SEND_TRIGGER (1<<0)
-#define GEN11_GUC_HOST_INTERRUPT _MMIO(0x1901f0)
-#define GUC_NUM_DOORBELLS 256
+#define GUC_SEND_INTERRUPT _MMIO(0xc4c8)
+#define GUC_SEND_TRIGGER REG_BIT(0)
+#define GEN11_GUC_HOST_INTERRUPT _MMIO(0x1901f0)
+
+#define GUC_NUM_DOORBELLS 256
/* format of the HW-monitored doorbell cacheline */
struct guc_doorbell_info {
u32 db_status;
-#define GUC_DOORBELL_DISABLED 0
-#define GUC_DOORBELL_ENABLED 1
+#define GUC_DOORBELL_DISABLED 0
+#define GUC_DOORBELL_ENABLED 1
u32 cookie;
u32 reserved[14];
} __packed;
-#define GEN8_DRBREGL(x) _MMIO(0x1000 + (x) * 8)
-#define GEN8_DRB_VALID (1<<0)
-#define GEN8_DRBREGU(x) _MMIO(0x1000 + (x) * 8 + 4)
+#define GEN8_DRBREGL(x) _MMIO(0x1000 + (x) * 8)
+#define GEN8_DRB_VALID REG_BIT(0)
+#define GEN8_DRBREGU(x) _MMIO(0x1000 + (x) * 8 + 4)
#define GEN12_DIST_DBS_POPULATED _MMIO(0xd08)
-#define GEN12_DOORBELLS_PER_SQIDI_SHIFT 16
-#define GEN12_DOORBELLS_PER_SQIDI (0xff)
-#define GEN12_SQIDIS_DOORBELL_EXIST (0xffff)
-
-#define DE_GUCRMR _MMIO(0x44054)
+#define GEN12_DOORBELLS_PER_SQIDI_MASK REG_GENMASK(23, 16)
+#define GEN12_SQIDIS_DOORBELL_EXIST_MASK REG_GENMASK(15, 0)
-#define GUC_BCS_RCS_IER _MMIO(0xC550)
-#define GUC_VCS2_VCS1_IER _MMIO(0xC554)
-#define GUC_WD_VECS_IER _MMIO(0xC558)
-#define GUC_PM_P24C_IER _MMIO(0xC55C)
+#define GUC_BCS_RCS_IER _MMIO(0xC550)
+#define GUC_VCS2_VCS1_IER _MMIO(0xC554)
+#define GUC_WD_VECS_IER _MMIO(0xC558)
+#define GUC_PM_P24C_IER _MMIO(0xC55C)
#define VF_SW_FLAG(n) _MMIO(0x190240 + (n) * 4)
#define VF_SW_FLAG_COUNT 4
@@ -134,21 +128,21 @@ struct guc_doorbell_info {
#define MED_VF_SW_FLAG_COUNT 4
/* GuC Interrupt Vector */
-#define GUC_INTR_GUC2HOST BIT(15)
-#define GUC_INTR_EXEC_ERROR BIT(14)
-#define GUC_INTR_DISPLAY_EVENT BIT(13)
-#define GUC_INTR_SEM_SIG BIT(12)
-#define GUC_INTR_IOMMU2GUC BIT(11)
-#define GUC_INTR_DOORBELL_RANG BIT(10)
-#define GUC_INTR_DMA_DONE BIT(9)
-#define GUC_INTR_FATAL_ERROR BIT(8)
-#define GUC_INTR_NOTIF_ERROR BIT(7)
-#define GUC_INTR_SW_INT_6 BIT(6)
-#define GUC_INTR_SW_INT_5 BIT(5)
-#define GUC_INTR_SW_INT_4 BIT(4)
-#define GUC_INTR_SW_INT_3 BIT(3)
-#define GUC_INTR_SW_INT_2 BIT(2)
-#define GUC_INTR_SW_INT_1 BIT(1)
-#define GUC_INTR_SW_INT_0 BIT(0)
+#define GUC_INTR_GUC2HOST BIT(15)
+#define GUC_INTR_EXEC_ERROR BIT(14)
+#define GUC_INTR_DISPLAY_EVENT BIT(13)
+#define GUC_INTR_SEM_SIG BIT(12)
+#define GUC_INTR_IOMMU2GUC BIT(11)
+#define GUC_INTR_DOORBELL_RANG BIT(10)
+#define GUC_INTR_DMA_DONE BIT(9)
+#define GUC_INTR_FATAL_ERROR BIT(8)
+#define GUC_INTR_NOTIF_ERROR BIT(7)
+#define GUC_INTR_SW_INT_6 BIT(6)
+#define GUC_INTR_SW_INT_5 BIT(5)
+#define GUC_INTR_SW_INT_4 BIT(4)
+#define GUC_INTR_SW_INT_3 BIT(3)
+#define GUC_INTR_SW_INT_2 BIT(2)
+#define GUC_INTR_SW_INT_1 BIT(1)
+#define GUC_INTR_SW_INT_0 BIT(0)
#endif
diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
index 862e810ef407..cde80eb09d07 100644
--- a/drivers/gpu/drm/xe/xe_ggtt.c
+++ b/drivers/gpu/drm/xe/xe_ggtt.c
@@ -186,11 +186,11 @@ int xe_ggtt_init(struct xe_gt *gt, struct xe_ggtt *ggtt)
}
#define GEN12_GUC_TLB_INV_CR _MMIO(0xcee8)
-#define GEN12_GUC_TLB_INV_CR_INVALIDATE (1 << 0)
+#define GEN12_GUC_TLB_INV_CR_INVALIDATE REG_BIT(0)
#define PVC_GUC_TLB_INV_DESC0 _MMIO(0xcf7c)
-#define PVC_GUC_TLB_INV_DESC0_VALID (1 << 0)
+#define PVC_GUC_TLB_INV_DESC0_VALID REG_BIT(0)
#define PVC_GUC_TLB_INV_DESC1 _MMIO(0xcf80)
-#define PVC_GUC_TLB_INV_DESC1_INVALIDATE (1 << 6)
+#define PVC_GUC_TLB_INV_DESC1_INVALIDATE REG_BIT(6)
void xe_ggtt_invalidate(struct xe_gt *gt)
{
diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index e00177f4d294..d18f2e25ce56 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -357,7 +357,7 @@ static void guc_prepare_xfer(struct xe_guc *guc)
GUC_ENABLE_MIA_CACHING;
if (xe->info.platform == XE_PVC)
- shim_flags |= PVC_GUC_MOCS_INDEX(PVC_MOCS_UC_INDEX);
+ shim_flags |= PVC_GUC_MOCS_INDEX(PVC_GUC_MOCS_UC_INDEX);
/* Must program this register before loading the ucode with DMA */
xe_mmio_write32(gt, GUC_SHIM_CONTROL.reg, shim_flags);
@@ -848,11 +848,11 @@ void xe_guc_print_info(struct xe_guc *guc, struct drm_printer *p)
drm_printf(p, "\nGuC status 0x%08x:\n", status);
drm_printf(p, "\tBootrom status = 0x%x\n",
- (status & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
+ REG_FIELD_GET(GS_BOOTROM_MASK, status));
drm_printf(p, "\tuKernel status = 0x%x\n",
- (status & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
+ REG_FIELD_GET(GS_UKERNEL_MASK, status));
drm_printf(p, "\tMIA Core status = 0x%x\n",
- (status & GS_MIA_MASK) >> GS_MIA_SHIFT);
+ REG_FIELD_GET(GS_MIA_MASK, status));
drm_printf(p, "\tLog level = %d\n",
xe_guc_log_get_level(&guc->log));
diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index fe1d5be1241e..d4fc2d357a78 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -561,8 +561,7 @@ static void guc_doorbell_init(struct xe_guc_ads *ads)
ads_blob_write(ads,
system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI],
- ((distdbreg >> GEN12_DOORBELLS_PER_SQIDI_SHIFT)
- & GEN12_DOORBELLS_PER_SQIDI) + 1);
+ REG_FIELD_GET(GEN12_DOORBELLS_PER_SQIDI_MASK, distdbreg) + 1);
}
}
--
2.39.0
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Intel-xe] [PATCH 09/17] drm/xe: Drop gen prefixes and suffixes from registers
2023-04-19 7:44 [Intel-xe] [PATCH 00/17] Cleanup registers and introduce xe_reg_t Lucas De Marchi
` (7 preceding siblings ...)
2023-04-19 7:44 ` [Intel-xe] [PATCH 08/17] drm/xe/guc: Convert GuC registers to REG_FIELD/REG_BIT Lucas De Marchi
@ 2023-04-19 7:44 ` Lucas De Marchi
2023-04-19 7:44 ` [Intel-xe] [PATCH 10/17] drm/xe: Use REG_FIELD/REG_BIT for all regs/*.h Lucas De Marchi
` (11 subsequent siblings)
20 siblings, 0 replies; 41+ messages in thread
From: Lucas De Marchi @ 2023-04-19 7:44 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, Matt Roper, Rodrigo Vivi
The defines for the registers were brought over from i915 while
bootstrapping the driver. As xe supports TGL and later only, it doesn't
make sense to keep the GEN* prefixes and suffixes in the registers: TGL
is graphics version 12, previously called "GEN12". So drop the prefix
everywhere.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/regs/xe_engine_regs.h | 8 +-
drivers/gpu/drm/xe/regs/xe_gpu_commands.h | 2 +-
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 190 +++++++++++-----------
drivers/gpu/drm/xe/regs/xe_guc_regs.h | 32 ++--
drivers/gpu/drm/xe/regs/xe_regs.h | 41 +++--
drivers/gpu/drm/xe/xe_execlist.c | 8 +-
drivers/gpu/drm/xe/xe_force_wake.c | 18 +-
drivers/gpu/drm/xe/xe_ggtt.c | 14 +-
drivers/gpu/drm/xe/xe_gt.c | 4 +-
drivers/gpu/drm/xe/xe_gt_clock.c | 26 +--
drivers/gpu/drm/xe/xe_gt_mcr.c | 30 ++--
drivers/gpu/drm/xe/xe_guc.c | 10 +-
drivers/gpu/drm/xe/xe_guc_ads.c | 11 +-
drivers/gpu/drm/xe/xe_guc_pc.c | 12 +-
drivers/gpu/drm/xe/xe_huc.c | 4 +-
drivers/gpu/drm/xe/xe_hw_engine.c | 42 ++---
drivers/gpu/drm/xe/xe_mmio.c | 3 +-
drivers/gpu/drm/xe/xe_mocs.c | 7 +-
drivers/gpu/drm/xe/xe_reg_whitelist.c | 2 +-
drivers/gpu/drm/xe/xe_ring_ops.c | 8 +-
drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c | 2 +-
drivers/gpu/drm/xe/xe_tuning.c | 2 +-
drivers/gpu/drm/xe/xe_wa.c | 84 +++++-----
23 files changed, 279 insertions(+), 281 deletions(-)
diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
index 2aa67d001c34..bfcb0e9a6d4c 100644
--- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
@@ -22,8 +22,8 @@
#define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */
#define RING_PSMI_CTL(base) _MMIO((base) + 0x50)
-#define GEN8_RC_SEMA_IDLE_MSG_DISABLE REG_BIT(12)
-#define GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
+#define RC_SEMA_IDLE_MSG_DISABLE REG_BIT(12)
+#define WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
#define RING_ACTHD_UDW(base) _MMIO((base) + 0x5c)
#define RING_DMA_FADD_UDW(base) _MMIO((base) + 0x60)
@@ -53,8 +53,8 @@
#define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH REG_BIT(3)
#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT REG_BIT(0)
-#define RING_MODE_GEN7(base) _MMIO((base) + 0x29c)
-#define GEN11_GFX_DISABLE_LEGACY_MODE (1 << 3)
+#define RING_MODE(base) _MMIO((base) + 0x29c)
+#define GFX_DISABLE_LEGACY_MODE (1 << 3)
#define RING_TIMESTAMP(base) _MMIO((base) + 0x358)
diff --git a/drivers/gpu/drm/xe/regs/xe_gpu_commands.h b/drivers/gpu/drm/xe/regs/xe_gpu_commands.h
index 05531d43514f..0f9c5b0b8a3b 100644
--- a/drivers/gpu/drm/xe/regs/xe_gpu_commands.h
+++ b/drivers/gpu/drm/xe/regs/xe_gpu_commands.h
@@ -37,7 +37,7 @@
#define MI_FLUSH_DW_OP_STOREDW (1<<14)
#define MI_FLUSH_DW_USE_GTT (1<<2)
-#define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1)
+#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 1)
#define XY_CTRL_SURF_COPY_BLT ((2 << 29) | (0x48 << 22) | 3)
#define SRC_ACCESS_TYPE_SHIFT 21
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 778d34afae93..0908224737dc 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -10,18 +10,18 @@
/* RPM unit config (Gen8+) */
#define RPM_CONFIG0 _MMIO(0xd00)
-#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3
-#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (0x7 << GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
-#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 0
-#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 1
-#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ 2
-#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ 3
-#define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT 1
-#define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK (0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT)
-
-#define FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n) _MMIO(0xd50 + (n) * 4)
-#define FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n) _MMIO(0xd70 + (n) * 4)
-#define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0xd84)
+#define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3
+#define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (0x7 << RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
+#define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 0
+#define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 1
+#define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ 2
+#define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ 3
+#define RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT 1
+#define RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK (0x3 << RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT)
+
+#define FORCEWAKE_ACK_MEDIA_VDBOX(n) _MMIO(0xd50 + (n) * 4)
+#define FORCEWAKE_ACK_MEDIA_VEBOX(n) _MMIO(0xd70 + (n) * 4)
+#define FORCEWAKE_ACK_RENDER _MMIO(0xd84)
#define GMD_ID _MMIO(0xd8c)
#define GMD_ID_ARCH_MASK REG_GENMASK(31, 22)
@@ -30,49 +30,49 @@
#define FORCEWAKE_ACK_GT_MTL _MMIO(0xdfc)
-#define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
+#define LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
#define LNCFCMOCS_REG_COUNT 32
#define MCFG_MCR_SELECTOR _MMIO(0xfd0)
#define MTL_MCR_SELECTOR _MMIO(0xfd4)
#define SF_MCR_SELECTOR _MMIO(0xfd8)
-#define GEN8_MCR_SELECTOR _MMIO(0xfdc)
+#define MCR_SELECTOR _MMIO(0xfdc)
#define GAM_MCR_SELECTOR _MMIO(0xfe0)
-#define GEN11_MCR_MULTICAST REG_BIT(31)
-#define GEN11_MCR_SLICE(slice) (((slice) & 0xf) << 27)
-#define GEN11_MCR_SLICE_MASK GEN11_MCR_SLICE(0xf)
-#define GEN11_MCR_SUBSLICE(subslice) (((subslice) & 0x7) << 24)
-#define GEN11_MCR_SUBSLICE_MASK GEN11_MCR_SUBSLICE(0x7)
+#define MCR_MULTICAST REG_BIT(31)
+#define MCR_SLICE(slice) (((slice) & 0xf) << 27)
+#define MCR_SLICE_MASK MCR_SLICE(0xf)
+#define MCR_SUBSLICE(subslice) (((subslice) & 0x7) << 24)
+#define MCR_SUBSLICE_MASK MCR_SUBSLICE(0x7)
#define MTL_MCR_GROUPID REG_GENMASK(11, 8)
#define MTL_MCR_INSTANCEID REG_GENMASK(3, 0)
-#define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0)
-#define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1 << 14)
+#define FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0)
+#define FFSC_PERCTX_PREEMPT_CTRL (1 << 14)
#define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4)
#define PERF_FIX_BALANCING_CFE_DISABLE REG_BIT(15)
-#define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec)
+#define CS_DEBUG_MODE1 _MMIO(0x20ec)
#define FF_DOP_CLOCK_GATE_DISABLE REG_BIT(1)
-#define GEN12_REPLAY_MODE_GRANULARITY REG_BIT(0)
+#define REPLAY_MODE_GRANULARITY REG_BIT(0)
#define PS_INVOCATION_COUNT _MMIO(0x2348)
-#define GEN8_CS_CHICKEN1 _MMIO(0x2580)
-#define GEN9_PREEMPT_3D_OBJECT_LEVEL (1 << 0)
-#define GEN9_PREEMPT_GPGPU_LEVEL(hi, lo) (((hi) << 2) | ((lo) << 1))
-#define GEN9_PREEMPT_GPGPU_MID_THREAD_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 0)
-#define GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 1)
-#define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(1, 0)
-#define GEN9_PREEMPT_GPGPU_LEVEL_MASK GEN9_PREEMPT_GPGPU_LEVEL(1, 1)
+#define CS_CHICKEN1 _MMIO(0x2580)
+#define PREEMPT_3D_OBJECT_LEVEL (1 << 0)
+#define PREEMPT_GPGPU_LEVEL(hi, lo) (((hi) << 2) | ((lo) << 1))
+#define PREEMPT_GPGPU_MID_THREAD_LEVEL PREEMPT_GPGPU_LEVEL(0, 0)
+#define PREEMPT_GPGPU_THREAD_GROUP_LEVEL PREEMPT_GPGPU_LEVEL(0, 1)
+#define PREEMPT_GPGPU_COMMAND_LEVEL PREEMPT_GPGPU_LEVEL(1, 0)
+#define PREEMPT_GPGPU_LEVEL_MASK PREEMPT_GPGPU_LEVEL(1, 1)
-#define GEN12_GLOBAL_MOCS(i) _MMIO(0x4000 + (i) * 4) /* Global MOCS regs */
-#define GEN12_GFX_CCS_AUX_NV _MMIO(0x4208)
+#define GLOBAL_MOCS(i) _MMIO(0x4000 + (i) * 4) /* Global MOCS regs */
+#define GFX_CCS_AUX_NV _MMIO(0x4208)
-#define GEN12_VD0_AUX_NV _MMIO(0x4218)
-#define GEN12_VE0_AUX_NV _MMIO(0x4238)
+#define VD0_AUX_NV _MMIO(0x4218)
+#define VE0_AUX_NV _MMIO(0x4238)
-#define GEN12_VE1_AUX_NV _MMIO(0x42b8)
+#define VE1_AUX_NV _MMIO(0x42b8)
#define AUX_INV REG_BIT(0)
#define XEHP_TILE0_ADDR_RANGE MCR_REG(0x4900)
@@ -88,7 +88,7 @@
#define DIS_OVER_FETCH_CACHE REG_BIT(1)
#define DIS_MULT_MISS_RD_SQUASH REG_BIT(0)
-#define GEN12_FF_MODE2 _MMIO(0x6604)
+#define FF_MODE2 _MMIO(0x6604)
#define XEHP_FF_MODE2 MCR_REG(0x6604)
#define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24)
#define FF_MODE2_GS_TIMER_224 REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224)
@@ -101,22 +101,21 @@
#define XEHP_PSS_MODE2 MCR_REG(0x703c)
#define SCOREBOARD_STALL_FLUSH_CONTROL REG_BIT(5)
-#define HIZ_CHICKEN _MMIO(0x7018)
+#define HIZ_CHICKEN _MMIO(0x7018)
#define DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE REG_BIT(14)
-#define HZ_DEPTH_TEST_LE_GE_OPT_DISABLE REG_BIT(13)
+#define HZ_DEPTH_TEST_LE_GE_OPT_DISABLE REG_BIT(13)
-/* GEN7 chicken */
-#define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
+#define COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
#define COMMON_SLICE_CHICKEN4 _MMIO(0x7300)
#define DISABLE_TDC_LOAD_BALANCING_CALC REG_BIT(6)
-#define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
-#define XEHP_COMMON_SLICE_CHICKEN3 MCR_REG(0x7304)
+#define COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
+#define XEHP_COMMON_SLICE_CHICKEN3 MCR_REG(0x7304)
#define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN REG_BIT(12)
-#define XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE REG_BIT(12)
-#define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11)
-#define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE REG_BIT(9)
+#define XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE REG_BIT(12)
+#define BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11)
+#define DISABLE_CPS_AWARE_COLOR_PIPE REG_BIT(9)
#define XEHP_SLICE_COMMON_ECO_CHICKEN1 MCR_REG(0x731c)
#define MSC_MSAA_REODER_BUF_BYPASS_DISABLE REG_BIT(14)
@@ -130,21 +129,21 @@
#define XEHP_SQCM MCR_REG(0x8724)
#define EN_32B_ACCESS REG_BIT(30)
-#define GEN10_MIRROR_FUSE3 _MMIO(0x9118)
-#define GEN10_L3BANK_PAIR_COUNT 4
-#define GEN10_L3BANK_MASK 0x0F
+#define MIRROR_FUSE3 _MMIO(0x9118)
+#define L3BANK_PAIR_COUNT 4
+#define L3BANK_MASK 0x0F
/* on Xe_HP the same fuses indicates mslices instead of L3 banks */
-#define GEN12_MAX_MSLICES 4
-#define GEN12_MEML3_EN_MASK 0x0F
+#define MAX_MSLICES 4
+#define MEML3_EN_MASK 0x0F
/* Fuse readout registers for GT */
#define XEHP_FUSE4 _MMIO(0x9114)
#define GT_L3_EXC_MASK REG_GENMASK(6, 4)
-#define GEN11_GT_VEBOX_VDBOX_DISABLE _MMIO(0x9140)
-#define GEN11_GT_VDBOX_DISABLE_MASK 0xff
-#define GEN11_GT_VEBOX_DISABLE_SHIFT 16
-#define GEN11_GT_VEBOX_DISABLE_MASK (0x0f << GEN11_GT_VEBOX_DISABLE_SHIFT)
+#define GT_VEBOX_VDBOX_DISABLE _MMIO(0x9140)
+#define GT_VDBOX_DISABLE_MASK 0xff
+#define GT_VEBOX_DISABLE_SHIFT 16
+#define GT_VEBOX_DISABLE_MASK (0x0f << GT_VEBOX_DISABLE_SHIFT)
#define XELP_EU_ENABLE _MMIO(0x9134) /* "_DISABLE" on Xe_LP */
#define XELP_EU_MASK REG_GENMASK(7, 0)
@@ -152,14 +151,13 @@
#define XEHP_GT_COMPUTE_DSS_ENABLE _MMIO(0x9144)
#define XEHPC_GT_COMPUTE_DSS_ENABLE_EXT _MMIO(0x9148)
-#define GEN6_GDRST _MMIO(0x941c)
-#define GEN11_GRDOM_GUC REG_BIT(3)
-#define GEN6_GRDOM_FULL (1 << 0)
-#define GEN11_GRDOM_FULL GEN6_GRDOM_FULL
+#define GDRST _MMIO(0x941c)
+#define GRDOM_GUC REG_BIT(3)
+#define GRDOM_FULL REG_BIT(0)
-#define GEN7_MISCCPCTL _MMIO(0x9424)
-#define GEN7_DOP_CLOCK_GATE_ENABLE (1 << 0)
-#define GEN12_DOP_CLOCK_GATE_RENDER_ENABLE REG_BIT(1)
+#define MISCCPCTL _MMIO(0x9424)
+#define DOP_CLOCK_GATE_RENDER_ENABLE REG_BIT(1)
+#define DOP_CLOCK_GATE_ENABLE REG_BIT((0)
#define UNSLCGCTL9430 _MMIO(0x9430)
#define MSQDUNIT_CLKGATE_DIS REG_BIT(3)
@@ -216,7 +214,7 @@
#define VSUNIT_CLKGATE_DIS_TGL REG_BIT(19)
#define PSDUNIT_CLKGATE_DIS REG_BIT(5)
-#define GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE MCR_REG(0x9524)
+#define SUBSLICE_UNIT_LEVEL_CLKGATE MCR_REG(0x9524)
#define DSS_ROUTER_CLKGATE_DIS REG_BIT(28)
#define GWUNIT_CLKGATE_DIS REG_BIT(16)
@@ -226,21 +224,21 @@
#define SSMCGCTL9530 MCR_REG(0x9530)
#define RTFUNIT_CLKGATE_DIS REG_BIT(18)
-#define GEN10_DFR_RATIO_EN_AND_CHICKEN MCR_REG(0x9550)
+#define DFR_RATIO_EN_AND_CHICKEN MCR_REG(0x9550)
#define DFR_DISABLE (1 << 9)
-#define GEN6_RPNSWREQ _MMIO(0xa008)
+#define RPNSWREQ _MMIO(0xa008)
#define REQ_RATIO_MASK REG_GENMASK(31, 23)
-#define GEN6_RC_CONTROL _MMIO(0xa090)
-#define GEN6_RC_STATE _MMIO(0xa094)
+#define RC_CONTROL _MMIO(0xa090)
+#define RC_STATE _MMIO(0xa094)
-#define GEN6_PMINTRMSK _MMIO(0xa168)
-#define GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC (1 << 31)
+#define PMINTRMSK _MMIO(0xa168)
+#define PMINTR_DISABLE_REDIRECT_TO_GUC (1 << 31)
#define ARAT_EXPIRED_INTRMSK (1 << 9)
-#define FORCEWAKE_GT_GEN9 _MMIO(0xa188)
+#define FORCEWAKE_GT _MMIO(0xa188)
-#define GEN9_PG_ENABLE _MMIO(0xa210)
+#define PG_ENABLE _MMIO(0xa210)
/* GPM unit config (Gen9+) */
#define CTC_MODE _MMIO(0xa26c)
@@ -250,9 +248,9 @@
#define CTC_SHIFT_PARAMETER_SHIFT 1
#define CTC_SHIFT_PARAMETER_MASK (0x3 << CTC_SHIFT_PARAMETER_SHIFT)
-#define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278)
-#define FORCEWAKE_MEDIA_VDBOX_GEN11(n) _MMIO(0xa540 + (n) * 4)
-#define FORCEWAKE_MEDIA_VEBOX_GEN11(n) _MMIO(0xa560 + (n) * 4)
+#define FORCEWAKE_RENDER _MMIO(0xa278)
+#define FORCEWAKE_MEDIA_VDBOX(n) _MMIO(0xa540 + (n) * 4)
+#define FORCEWAKE_MEDIA_VEBOX(n) _MMIO(0xa560 + (n) * 4)
#define XEHPC_LNCFMISCCFGREG0 MCR_REG(0xb01c)
#define XEHPC_OVRLSCCC REG_BIT(0)
@@ -282,12 +280,12 @@
#define INVALIDATION_BROADCAST_MODE_DIS REG_BIT(12)
#define GLOBAL_INVALIDATION_MODE REG_BIT(2)
-#define GEN10_SAMPLER_MODE MCR_REG(0xe18c)
+#define SAMPLER_MODE MCR_REG(0xe18c)
#define ENABLE_SMALLPL REG_BIT(15)
#define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
-#define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
+#define SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
-#define GEN9_HALF_SLICE_CHICKEN7 MCR_REG(0xe194)
+#define HALF_SLICE_CHICKEN7 MCR_REG(0xe194)
#define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15)
#define CACHE_MODE_SS MCR_REG(0xe420)
@@ -295,27 +293,27 @@
#define DISABLE_ECC REG_BIT(5)
#define ENABLE_PREFETCH_INTO_IC REG_BIT(3)
-#define GEN9_ROW_CHICKEN4 MCR_REG(0xe48c)
-#define GEN12_DISABLE_GRF_CLEAR REG_BIT(13)
+#define ROW_CHICKEN4 MCR_REG(0xe48c)
+#define DISABLE_GRF_CLEAR REG_BIT(13)
#define XEHP_DIS_BBL_SYSPIPE REG_BIT(11)
-#define GEN12_DISABLE_TDL_PUSH REG_BIT(9)
-#define GEN11_DIS_PICK_2ND_EU REG_BIT(7)
-#define GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX REG_BIT(4)
+#define DISABLE_TDL_PUSH REG_BIT(9)
+#define DIS_PICK_2ND_EU REG_BIT(7)
+#define DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX REG_BIT(4)
#define THREAD_EX_ARB_MODE REG_GENMASK(3, 2)
#define THREAD_EX_ARB_MODE_RR_AFTER_DEP REG_FIELD_PREP(THREAD_EX_ARB_MODE, 0x2)
-#define GEN8_ROW_CHICKEN MCR_REG(0xe4f0)
+#define ROW_CHICKEN MCR_REG(0xe4f0)
#define UGM_BACKUP_MODE REG_BIT(13)
#define MDQ_ARBITRATION_MODE REG_BIT(12)
-#define GEN8_ROW_CHICKEN2 MCR_REG(0xe4f4)
-#define GEN12_DISABLE_READ_SUPPRESSION REG_BIT(15)
-#define GEN12_DISABLE_EARLY_READ REG_BIT(14)
-#define GEN12_ENABLE_LARGE_GRF_MODE REG_BIT(12)
-#define GEN12_PUSH_CONST_DEREF_HOLD_DIS REG_BIT(8)
-#define GEN12_DISABLE_DOP_GATING REG_BIT(0)
+#define ROW_CHICKEN2 MCR_REG(0xe4f4)
+#define DISABLE_READ_SUPPRESSION REG_BIT(15)
+#define DISABLE_EARLY_READ REG_BIT(14)
+#define ENABLE_LARGE_GRF_MODE REG_BIT(12)
+#define PUSH_CONST_DEREF_HOLD_DIS REG_BIT(8)
+#define DISABLE_DOP_GATING REG_BIT(0)
-#define XEHP_HDC_CHICKEN0 MCR_REG(0xe5f0)
+#define XEHP_HDC_CHICKEN0 MCR_REG(0xe5f0)
#define LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK REG_GENMASK(13, 11)
#define RT_CTRL MCR_REG(0xe530)
@@ -335,23 +333,23 @@
#define SARB_CHICKEN1 MCR_REG(0xe90c)
#define COMP_CKN_IN REG_GENMASK(30, 29)
-#define GEN12_RCU_MODE _MMIO(0x14800)
-#define GEN12_RCU_MODE_CCS_ENABLE REG_BIT(0)
+#define RCU_MODE _MMIO(0x14800)
+#define RCU_MODE_CCS_ENABLE REG_BIT(0)
-#define FORCEWAKE_ACK_GT_GEN9 _MMIO(0x130044)
+#define FORCEWAKE_ACK_GT _MMIO(0x130044)
#define FORCEWAKE_KERNEL BIT(0)
#define FORCEWAKE_USER BIT(1)
#define FORCEWAKE_KERNEL_FALLBACK BIT(15)
-#define GEN6_GT_CORE_STATUS _MMIO(0x138060)
+#define GT_CORE_STATUS _MMIO(0x138060)
#define RCN_MASK REG_GENMASK(2, 0)
#define GT_RC0 0
#define GT_RC6 3
-#define GEN6_GT_GFX_RC6_LOCKED _MMIO(0x138104)
-#define GEN6_GT_GFX_RC6 _MMIO(0x138108)
+#define GT_GFX_RC6_LOCKED _MMIO(0x138104)
+#define GT_GFX_RC6 _MMIO(0x138108)
-#define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008)
+#define GFX_FLSH_CNTL _MMIO(0x101008)
#define GFX_FLSH_CNTL_EN (1 << 0)
#define GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4))
diff --git a/drivers/gpu/drm/xe/regs/xe_guc_regs.h b/drivers/gpu/drm/xe/regs/xe_guc_regs.h
index facb1f0a55b6..835d413ae186 100644
--- a/drivers/gpu/drm/xe/regs/xe_guc_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_guc_regs.h
@@ -57,23 +57,21 @@
#define HUC_STATUS2 _MMIO(0xd3b0)
#define HUC_FW_VERIFIED REG_BIT(7)
-#define GEN11_HUC_KERNEL_LOAD_INFO _MMIO(0xc1dc)
+#define HUC_KERNEL_LOAD_INFO _MMIO(0xc1dc)
#define HUC_LOAD_SUCCESSFUL REG_BIT(0)
#define GUC_WOPCM_SIZE _MMIO(0xc050)
#define GUC_WOPCM_SIZE_MASK REG_GENMASK(31, 12)
#define GUC_WOPCM_SIZE_LOCKED REG_BIT(0)
-#define GEN8_GT_PM_CONFIG _MMIO(0x138140)
-#define GEN9LP_GT_PM_CONFIG _MMIO(0x138140)
-#define GEN9_GT_PM_CONFIG _MMIO(0x13816c)
+#define GT_PM_CONFIG _MMIO(0x13816c)
#define GT_DOORBELL_ENABLE REG_BIT(0)
-#define GEN8_GTCR _MMIO(0x4274)
-#define GEN8_GTCR_INVALIDATE REG_BIT(0)
+#define GTCR _MMIO(0x4274)
+#define GTCR_INVALIDATE REG_BIT(0)
-#define GEN12_GUC_TLB_INV_CR _MMIO(0xcee8)
-#define GEN12_GUC_TLB_INV_CR_INVALIDATE REG_BIT(0)
+#define GUC_TLB_INV_CR _MMIO(0xcee8)
+#define GUC_TLB_INV_CR_INVALIDATE REG_BIT(0)
#define GUC_ARAT_C6DIS _MMIO(0xa178)
@@ -82,11 +80,11 @@
#define PVC_GUC_MOCS_UC_INDEX 1
#define PVC_GUC_MOCS_INDEX(index) REG_FIELD_PREP(PVC_GUC_MOCS_INDEX_MASK, \
index)
-#define GUC_GEN10_SHIM_WC_ENABLE REG_BIT(21)
+#define GUC_SHIM_WC_ENABLE REG_BIT(21)
#define GUC_ENABLE_MIA_CLOCK_GATING REG_BIT(15)
#define GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA REG_BIT(10)
#define GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA REG_BIT(9)
-#define GUC_GEN10_MSGCH_ENABLE REG_BIT(4)
+#define GUC_MSGCH_ENABLE REG_BIT(4)
#define GUC_ENABLE_MIA_CACHING REG_BIT(2)
#define GUC_ENABLE_READ_CACHE_LOGIC REG_BIT(1)
#define GUC_DISABLE_SRAM_INIT_TO_ZEROES REG_BIT(0)
@@ -94,7 +92,7 @@
#define GUC_SEND_INTERRUPT _MMIO(0xc4c8)
#define GUC_SEND_TRIGGER REG_BIT(0)
-#define GEN11_GUC_HOST_INTERRUPT _MMIO(0x1901f0)
+#define GUC_HOST_INTERRUPT _MMIO(0x1901f0)
#define GUC_NUM_DOORBELLS 256
@@ -108,13 +106,13 @@ struct guc_doorbell_info {
u32 reserved[14];
} __packed;
-#define GEN8_DRBREGL(x) _MMIO(0x1000 + (x) * 8)
-#define GEN8_DRB_VALID REG_BIT(0)
-#define GEN8_DRBREGU(x) _MMIO(0x1000 + (x) * 8 + 4)
+#define DRBREGL(x) _MMIO(0x1000 + (x) * 8)
+#define DRB_VALID REG_BIT(0)
+#define DRBREGU(x) _MMIO(0x1000 + (x) * 8 + 4)
-#define GEN12_DIST_DBS_POPULATED _MMIO(0xd08)
-#define GEN12_DOORBELLS_PER_SQIDI_MASK REG_GENMASK(23, 16)
-#define GEN12_SQIDIS_DOORBELL_EXIST_MASK REG_GENMASK(15, 0)
+#define DIST_DBS_POPULATED _MMIO(0xd08)
+#define DOORBELLS_PER_SQIDI_MASK REG_GENMASK(23, 16)
+#define SQIDIS_DOORBELL_EXIST_MASK REG_GENMASK(15, 0)
#define GUC_BCS_RCS_IER _MMIO(0xC550)
#define GUC_VCS2_VCS1_IER _MMIO(0xC554)
diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h
index 89b51857fd3d..e6b81bcff91f 100644
--- a/drivers/gpu/drm/xe/regs/xe_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_regs.h
@@ -11,23 +11,22 @@
#define LMEM_INIT REG_BIT(7)
#define RENDER_RING_BASE 0x02000
-#define GEN11_BSD_RING_BASE 0x1c0000
-#define GEN11_BSD2_RING_BASE 0x1c4000
-#define GEN11_BSD3_RING_BASE 0x1d0000
-#define GEN11_BSD4_RING_BASE 0x1d4000
+#define BSD_RING_BASE 0x1c0000
+#define BSD2_RING_BASE 0x1c4000
+#define BSD3_RING_BASE 0x1d0000
+#define BSD4_RING_BASE 0x1d4000
#define XEHP_BSD5_RING_BASE 0x1e0000
#define XEHP_BSD6_RING_BASE 0x1e4000
#define XEHP_BSD7_RING_BASE 0x1f0000
#define XEHP_BSD8_RING_BASE 0x1f4000
-#define VEBOX_RING_BASE 0x1a000
-#define GEN11_VEBOX_RING_BASE 0x1c8000
-#define GEN11_VEBOX2_RING_BASE 0x1d8000
+#define VEBOX_RING_BASE 0x1c8000
+#define VEBOX2_RING_BASE 0x1d8000
#define XEHP_VEBOX3_RING_BASE 0x1e8000
#define XEHP_VEBOX4_RING_BASE 0x1f8000
-#define GEN12_COMPUTE0_RING_BASE 0x1a000
-#define GEN12_COMPUTE1_RING_BASE 0x1c000
-#define GEN12_COMPUTE2_RING_BASE 0x1e000
-#define GEN12_COMPUTE3_RING_BASE 0x26000
+#define COMPUTE0_RING_BASE 0x1a000
+#define COMPUTE1_RING_BASE 0x1c000
+#define COMPUTE2_RING_BASE 0x1e000
+#define COMPUTE3_RING_BASE 0x26000
#define BLT_RING_BASE 0x22000
#define XEHPC_BCS1_RING_BASE 0x3e0000
#define XEHPC_BCS2_RING_BASE 0x3e2000
@@ -43,8 +42,8 @@
#define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3)
#define GT_RENDER_USER_INTERRUPT (1 << 0)
-#define GEN7_FF_THREAD_MODE _MMIO(0x20a0)
-#define GEN12_FF_TESSELATION_DOP_GATE_DISABLE BIT(19)
+#define FF_THREAD_MODE _MMIO(0x20a0)
+#define FF_TESSELATION_DOP_GATE_DISABLE BIT(19)
#define PVC_RP_STATE_CAP _MMIO(0x281014)
#define MTL_RP_STATE_CAP _MMIO(0x138000)
@@ -90,18 +89,18 @@
#define DG1_MSTR_IRQ REG_BIT(31)
#define DG1_MSTR_TILE(t) REG_BIT(t)
-#define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074)
-#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0
-#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff
-#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12
-#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12)
+#define TIMESTAMP_OVERRIDE _MMIO(0x44074)
+#define TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0
+#define TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff
+#define TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12
+#define TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12)
#define GGC _MMIO(0x108040)
#define GMS_MASK REG_GENMASK(15, 8)
#define GGMS_MASK REG_GENMASK(7, 6)
-#define GEN12_GSMBASE _MMIO(0x108100)
-#define GEN12_DSMBASE _MMIO(0x1080C0)
-#define GEN12_BDSM_MASK REG_GENMASK64(63, 20)
+#define GSMBASE _MMIO(0x108100)
+#define DSMBASE _MMIO(0x1080C0)
+#define BDSM_MASK REG_GENMASK64(63, 20)
#endif
diff --git a/drivers/gpu/drm/xe/xe_execlist.c b/drivers/gpu/drm/xe/xe_execlist.c
index 02021457b1f0..ac23731bc8fe 100644
--- a/drivers/gpu/drm/xe/xe_execlist.c
+++ b/drivers/gpu/drm/xe/xe_execlist.c
@@ -60,8 +60,8 @@ static void __start_lrc(struct xe_hw_engine *hwe, struct xe_lrc *lrc,
}
if (hwe->class == XE_ENGINE_CLASS_COMPUTE)
- xe_mmio_write32(hwe->gt, GEN12_RCU_MODE.reg,
- _MASKED_BIT_ENABLE(GEN12_RCU_MODE_CCS_ENABLE));
+ xe_mmio_write32(hwe->gt, RCU_MODE.reg,
+ _MASKED_BIT_ENABLE(RCU_MODE_CCS_ENABLE));
xe_lrc_write_ctx_reg(lrc, CTX_RING_TAIL, lrc->ring.tail);
lrc->ring.old_tail = lrc->ring.tail;
@@ -81,8 +81,8 @@ static void __start_lrc(struct xe_hw_engine *hwe, struct xe_lrc *lrc,
xe_mmio_write32(gt, RING_HWS_PGA(hwe->mmio_base).reg,
xe_bo_ggtt_addr(hwe->hwsp));
xe_mmio_read32(gt, RING_HWS_PGA(hwe->mmio_base).reg);
- xe_mmio_write32(gt, RING_MODE_GEN7(hwe->mmio_base).reg,
- _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE));
+ xe_mmio_write32(gt, RING_MODE(hwe->mmio_base).reg,
+ _MASKED_BIT_ENABLE(GFX_DISABLE_LEGACY_MODE));
xe_mmio_write32(gt, RING_EXECLIST_SQ_CONTENTS(hwe->mmio_base).reg + 0,
lower_32_bits(lrc_desc));
diff --git a/drivers/gpu/drm/xe/xe_force_wake.c b/drivers/gpu/drm/xe/xe_force_wake.c
index 77a210acfac3..53d73f36a121 100644
--- a/drivers/gpu/drm/xe/xe_force_wake.c
+++ b/drivers/gpu/drm/xe/xe_force_wake.c
@@ -49,14 +49,14 @@ void xe_force_wake_init_gt(struct xe_gt *gt, struct xe_force_wake *fw)
if (xe->info.graphics_verx100 >= 1270) {
domain_init(&fw->domains[XE_FW_DOMAIN_ID_GT],
XE_FW_DOMAIN_ID_GT,
- FORCEWAKE_GT_GEN9.reg,
+ FORCEWAKE_GT.reg,
FORCEWAKE_ACK_GT_MTL.reg,
BIT(0), BIT(16));
} else {
domain_init(&fw->domains[XE_FW_DOMAIN_ID_GT],
XE_FW_DOMAIN_ID_GT,
- FORCEWAKE_GT_GEN9.reg,
- FORCEWAKE_ACK_GT_GEN9.reg,
+ FORCEWAKE_GT.reg,
+ FORCEWAKE_ACK_GT.reg,
BIT(0), BIT(16));
}
}
@@ -71,8 +71,8 @@ void xe_force_wake_init_engines(struct xe_gt *gt, struct xe_force_wake *fw)
if (!xe_gt_is_media_type(gt))
domain_init(&fw->domains[XE_FW_DOMAIN_ID_RENDER],
XE_FW_DOMAIN_ID_RENDER,
- FORCEWAKE_RENDER_GEN9.reg,
- FORCEWAKE_ACK_RENDER_GEN9.reg,
+ FORCEWAKE_RENDER.reg,
+ FORCEWAKE_ACK_RENDER.reg,
BIT(0), BIT(16));
for (i = XE_HW_ENGINE_VCS0, j = 0; i <= XE_HW_ENGINE_VCS7; ++i, ++j) {
@@ -81,8 +81,8 @@ void xe_force_wake_init_engines(struct xe_gt *gt, struct xe_force_wake *fw)
domain_init(&fw->domains[XE_FW_DOMAIN_ID_MEDIA_VDBOX0 + j],
XE_FW_DOMAIN_ID_MEDIA_VDBOX0 + j,
- FORCEWAKE_MEDIA_VDBOX_GEN11(j).reg,
- FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(j).reg,
+ FORCEWAKE_MEDIA_VDBOX(j).reg,
+ FORCEWAKE_ACK_MEDIA_VDBOX(j).reg,
BIT(0), BIT(16));
}
@@ -92,8 +92,8 @@ void xe_force_wake_init_engines(struct xe_gt *gt, struct xe_force_wake *fw)
domain_init(&fw->domains[XE_FW_DOMAIN_ID_MEDIA_VEBOX0 + j],
XE_FW_DOMAIN_ID_MEDIA_VEBOX0 + j,
- FORCEWAKE_MEDIA_VEBOX_GEN11(j).reg,
- FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(j).reg,
+ FORCEWAKE_MEDIA_VEBOX(j).reg,
+ FORCEWAKE_ACK_MEDIA_VEBOX(j).reg,
BIT(0), BIT(16));
}
}
diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
index cde80eb09d07..3417cc7e0291 100644
--- a/drivers/gpu/drm/xe/xe_ggtt.c
+++ b/drivers/gpu/drm/xe/xe_ggtt.c
@@ -185,12 +185,12 @@ int xe_ggtt_init(struct xe_gt *gt, struct xe_ggtt *ggtt)
return err;
}
-#define GEN12_GUC_TLB_INV_CR _MMIO(0xcee8)
-#define GEN12_GUC_TLB_INV_CR_INVALIDATE REG_BIT(0)
+#define GUC_TLB_INV_CR _MMIO(0xcee8)
+#define GUC_TLB_INV_CR_INVALIDATE REG_BIT(0)
#define PVC_GUC_TLB_INV_DESC0 _MMIO(0xcf7c)
-#define PVC_GUC_TLB_INV_DESC0_VALID REG_BIT(0)
+#define PVC_GUC_TLB_INV_DESC0_VALID REG_BIT(0)
#define PVC_GUC_TLB_INV_DESC1 _MMIO(0xcf80)
-#define PVC_GUC_TLB_INV_DESC1_INVALIDATE REG_BIT(6)
+#define PVC_GUC_TLB_INV_DESC1_INVALIDATE REG_BIT(6)
void xe_ggtt_invalidate(struct xe_gt *gt)
{
@@ -199,7 +199,7 @@ void xe_ggtt_invalidate(struct xe_gt *gt)
/* TODO: i915 makes comments about this being uncached and
* therefore flushing WC buffers. Is that really true here?
*/
- xe_mmio_write32(gt, GFX_FLSH_CNTL_GEN6.reg, GFX_FLSH_CNTL_EN);
+ xe_mmio_write32(gt, GFX_FLSH_CNTL.reg, GFX_FLSH_CNTL_EN);
if (gt->uc.guc.submission_state.enabled) {
int seqno;
@@ -217,8 +217,8 @@ void xe_ggtt_invalidate(struct xe_gt *gt)
xe_mmio_write32(gt, PVC_GUC_TLB_INV_DESC0.reg,
PVC_GUC_TLB_INV_DESC0_VALID);
} else
- xe_mmio_write32(gt, GEN12_GUC_TLB_INV_CR.reg,
- GEN12_GUC_TLB_INV_CR_INVALIDATE);
+ xe_mmio_write32(gt, GUC_TLB_INV_CR.reg,
+ GUC_TLB_INV_CR_INVALIDATE);
}
}
diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
index 4186f7f0d42f..0d4664e344da 100644
--- a/drivers/gpu/drm/xe/xe_gt.c
+++ b/drivers/gpu/drm/xe/xe_gt.c
@@ -541,8 +541,8 @@ static int do_gt_reset(struct xe_gt *gt)
struct xe_device *xe = gt_to_xe(gt);
int err;
- xe_mmio_write32(gt, GEN6_GDRST.reg, GEN11_GRDOM_FULL);
- err = xe_mmio_wait32(gt, GEN6_GDRST.reg, 0, GEN11_GRDOM_FULL, 5000,
+ xe_mmio_write32(gt, GDRST.reg, GRDOM_FULL);
+ err = xe_mmio_wait32(gt, GDRST.reg, 0, GRDOM_FULL, 5000,
NULL, false);
if (err)
drm_err(&xe->drm,
diff --git a/drivers/gpu/drm/xe/xe_gt_clock.c b/drivers/gpu/drm/xe/xe_gt_clock.c
index 60a2966bc1fd..1b7d00284535 100644
--- a/drivers/gpu/drm/xe/xe_gt_clock.c
+++ b/drivers/gpu/drm/xe/xe_gt_clock.c
@@ -14,16 +14,16 @@
static u32 read_reference_ts_freq(struct xe_gt *gt)
{
- u32 ts_override = xe_mmio_read32(gt, GEN9_TIMESTAMP_OVERRIDE.reg);
+ u32 ts_override = xe_mmio_read32(gt, TIMESTAMP_OVERRIDE.reg);
u32 base_freq, frac_freq;
- base_freq = ((ts_override & GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK) >>
- GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT) + 1;
+ base_freq = ((ts_override & TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK) >>
+ TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT) + 1;
base_freq *= 1000000;
frac_freq = ((ts_override &
- GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK) >>
- GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT);
+ TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK) >>
+ TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT);
frac_freq = 1000000 / (frac_freq + 1);
return base_freq + frac_freq;
@@ -36,17 +36,17 @@ static u32 get_crystal_clock_freq(u32 rpm_config_reg)
const u32 f25_mhz = 25000000;
const u32 f38_4_mhz = 38400000;
u32 crystal_clock =
- (rpm_config_reg & GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >>
- GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
+ (rpm_config_reg & RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >>
+ RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
switch (crystal_clock) {
- case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ:
+ case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ :
return f24_mhz;
- case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ:
+ case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ :
return f19_2_mhz;
- case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ:
+ case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ :
return f38_4_mhz;
- case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ:
+ case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ :
return f25_mhz;
default:
XE_BUG_ON("NOT_POSSIBLE");
@@ -74,8 +74,8 @@ int xe_gt_clock_init(struct xe_gt *gt)
* register increments from this frequency (it might
* increment only every few clock cycle).
*/
- freq >>= 3 - ((c0 & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
- GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);
+ freq >>= 3 - ((c0 & RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
+ RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);
}
gt->info.clock_freq = freq;
diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
index 5412f77bc26f..aa04ba5a6dbe 100644
--- a/drivers/gpu/drm/xe/xe_gt_mcr.c
+++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
@@ -177,8 +177,8 @@ static const struct xe_mmio_range dg2_implicit_steering_table[] = {
static void init_steering_l3bank(struct xe_gt *gt)
{
if (GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270) {
- u32 mslice_mask = REG_FIELD_GET(GEN12_MEML3_EN_MASK,
- xe_mmio_read32(gt, GEN10_MIRROR_FUSE3.reg));
+ u32 mslice_mask = REG_FIELD_GET(MEML3_EN_MASK,
+ xe_mmio_read32(gt, MIRROR_FUSE3.reg));
u32 bank_mask = REG_FIELD_GET(GT_L3_EXC_MASK,
xe_mmio_read32(gt, XEHP_FUSE4.reg));
@@ -190,8 +190,8 @@ static void init_steering_l3bank(struct xe_gt *gt)
gt->steering[L3BANK].instance_target =
bank_mask & BIT(0) ? 0 : 2;
} else if (gt_to_xe(gt)->info.platform == XE_DG2) {
- u32 mslice_mask = REG_FIELD_GET(GEN12_MEML3_EN_MASK,
- xe_mmio_read32(gt, GEN10_MIRROR_FUSE3.reg));
+ u32 mslice_mask = REG_FIELD_GET(MEML3_EN_MASK,
+ xe_mmio_read32(gt, MIRROR_FUSE3.reg));
u32 bank = __ffs(mslice_mask) * 8;
/*
@@ -202,8 +202,8 @@ static void init_steering_l3bank(struct xe_gt *gt)
gt->steering[L3BANK].group_target = (bank >> 2) & 0x7;
gt->steering[L3BANK].instance_target = bank & 0x3;
} else {
- u32 fuse = REG_FIELD_GET(GEN10_L3BANK_MASK,
- ~xe_mmio_read32(gt, GEN10_MIRROR_FUSE3.reg));
+ u32 fuse = REG_FIELD_GET(L3BANK_MASK,
+ ~xe_mmio_read32(gt, MIRROR_FUSE3.reg));
gt->steering[L3BANK].group_target = 0; /* unused */
gt->steering[L3BANK].instance_target = __ffs(fuse);
@@ -212,8 +212,8 @@ static void init_steering_l3bank(struct xe_gt *gt)
static void init_steering_mslice(struct xe_gt *gt)
{
- u32 mask = REG_FIELD_GET(GEN12_MEML3_EN_MASK,
- xe_mmio_read32(gt, GEN10_MIRROR_FUSE3.reg));
+ u32 mask = REG_FIELD_GET(MEML3_EN_MASK,
+ xe_mmio_read32(gt, MIRROR_FUSE3.reg));
/*
* mslice registers are valid (not terminated) if either the meml3
@@ -329,8 +329,8 @@ void xe_gt_mcr_set_implicit_defaults(struct xe_gt *gt)
struct xe_device *xe = gt_to_xe(gt);
if (xe->info.platform == XE_DG2) {
- u32 steer_val = REG_FIELD_PREP(GEN11_MCR_SLICE_MASK, 0) |
- REG_FIELD_PREP(GEN11_MCR_SUBSLICE_MASK, 2);
+ u32 steer_val = REG_FIELD_PREP(MCR_SLICE_MASK, 0) |
+ REG_FIELD_PREP(MCR_SUBSLICE_MASK, 2);
xe_mmio_write32(gt, MCFG_MCR_SELECTOR.reg, steer_val);
xe_mmio_write32(gt, SF_MCR_SELECTOR.reg, steer_val);
@@ -448,9 +448,9 @@ static u32 rw_with_mcr_steering(struct xe_gt *gt, i915_mcr_reg_t reg, u8 rw_flag
steer_val = REG_FIELD_PREP(MTL_MCR_GROUPID, group) |
REG_FIELD_PREP(MTL_MCR_INSTANCEID, instance);
} else {
- steer_reg = GEN8_MCR_SELECTOR.reg;
- steer_val = REG_FIELD_PREP(GEN11_MCR_SLICE_MASK, group) |
- REG_FIELD_PREP(GEN11_MCR_SUBSLICE_MASK, instance);
+ steer_reg = MCR_SELECTOR.reg;
+ steer_val = REG_FIELD_PREP(MCR_SLICE_MASK, group) |
+ REG_FIELD_PREP(MCR_SUBSLICE_MASK, instance);
}
/*
@@ -461,7 +461,7 @@ static u32 rw_with_mcr_steering(struct xe_gt *gt, i915_mcr_reg_t reg, u8 rw_flag
* No need to save old steering reg value.
*/
if (rw_flag == MCR_OP_READ)
- steer_val |= GEN11_MCR_MULTICAST;
+ steer_val |= MCR_MULTICAST;
xe_mmio_write32(gt, steer_reg, steer_val);
@@ -477,7 +477,7 @@ static u32 rw_with_mcr_steering(struct xe_gt *gt, i915_mcr_reg_t reg, u8 rw_flag
* operation.
*/
if (rw_flag == MCR_OP_WRITE)
- xe_mmio_write32(gt, steer_reg, GEN11_MCR_MULTICAST);
+ xe_mmio_write32(gt, steer_reg, MCR_MULTICAST);
return val;
}
diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index d18f2e25ce56..4e9e9b1aad02 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -278,7 +278,7 @@ int xe_guc_init(struct xe_guc *guc)
if (xe_gt_is_media_type(gt))
guc->notify_reg = MEDIA_GUC_HOST_INTERRUPT.reg;
else
- guc->notify_reg = GEN11_GUC_HOST_INTERRUPT.reg;
+ guc->notify_reg = GUC_HOST_INTERRUPT.reg;
xe_uc_fw_change_status(&guc->fw, XE_UC_FIRMWARE_LOADABLE);
@@ -317,9 +317,9 @@ int xe_guc_reset(struct xe_guc *guc)
xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
- xe_mmio_write32(gt, GEN6_GDRST.reg, GEN11_GRDOM_GUC);
+ xe_mmio_write32(gt, GDRST.reg, GRDOM_GUC);
- ret = xe_mmio_wait32(gt, GEN6_GDRST.reg, 0, GEN11_GRDOM_GUC, 5000,
+ ret = xe_mmio_wait32(gt, GDRST.reg, 0, GRDOM_GUC, 5000,
&gdrst, false);
if (ret) {
drm_err(&xe->drm, "GuC reset timed out, GEN6_GDRST=0x%8x\n",
@@ -362,7 +362,7 @@ static void guc_prepare_xfer(struct xe_guc *guc)
/* Must program this register before loading the ucode with DMA */
xe_mmio_write32(gt, GUC_SHIM_CONTROL.reg, shim_flags);
- xe_mmio_write32(gt, GEN9_GT_PM_CONFIG.reg, GT_DOORBELL_ENABLE);
+ xe_mmio_write32(gt, GT_PM_CONFIG.reg, GT_DOORBELL_ENABLE);
}
/*
@@ -575,7 +575,7 @@ int xe_guc_enable_communication(struct xe_guc *guc)
guc_enable_irq(guc);
- xe_mmio_rmw32(guc_to_gt(guc), GEN6_PMINTRMSK.reg,
+ xe_mmio_rmw32(guc_to_gt(guc), PMINTRMSK.reg,
ARAT_EXPIRED_INTRMSK, 0);
err = xe_guc_ct_enable(&guc->ct);
diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index d4fc2d357a78..6a723bda2aa9 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -450,10 +450,10 @@ static unsigned int guc_mmio_regset_write(struct xe_guc_ads *ads,
u32 flags;
bool skip;
} *e, extra_regs[] = {
- { .reg = RING_MODE_GEN7(hwe->mmio_base).reg, },
+ { .reg = RING_MODE(hwe->mmio_base).reg, },
{ .reg = RING_HWS_PGA(hwe->mmio_base).reg, },
{ .reg = RING_IMR(hwe->mmio_base).reg, },
- { .reg = GEN12_RCU_MODE.reg, .flags = 0x3,
+ { .reg = RCU_MODE.reg, .flags = 0x3,
.skip = hwe != hwe_rcs_reset_domain },
};
u32 i;
@@ -478,7 +478,8 @@ static unsigned int guc_mmio_regset_write(struct xe_guc_ads *ads,
if (needs_wa_1607983814(xe) && hwe->class == XE_ENGINE_CLASS_RENDER) {
for (i = 0; i < LNCFCMOCS_REG_COUNT; i++) {
guc_mmio_regset_write_one(ads, regset_map,
- GEN9_LNCFCMOCS(i).reg, 0, count++);
+ LNCFCMOCS(i).reg, 0,
+ count++);
}
}
@@ -557,11 +558,11 @@ static void guc_doorbell_init(struct xe_guc_ads *ads)
if (GRAPHICS_VER(xe) >= 12 && !IS_DGFX(xe)) {
u32 distdbreg =
- xe_mmio_read32(gt, GEN12_DIST_DBS_POPULATED.reg);
+ xe_mmio_read32(gt, DIST_DBS_POPULATED.reg);
ads_blob_write(ads,
system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI],
- REG_FIELD_GET(GEN12_DOORBELLS_PER_SQIDI_MASK, distdbreg) + 1);
+ REG_FIELD_GET(DOORBELLS_PER_SQIDI_MASK, distdbreg) + 1);
}
}
diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
index 2f98544736ae..10c3a442ecd9 100644
--- a/drivers/gpu/drm/xe/xe_guc_pc.c
+++ b/drivers/gpu/drm/xe/xe_guc_pc.c
@@ -414,7 +414,7 @@ static ssize_t freq_cur_show(struct device *dev,
return ret;
xe_device_mem_access_get(gt_to_xe(gt));
- freq = xe_mmio_read32(gt, GEN6_RPNSWREQ.reg);
+ freq = xe_mmio_read32(gt, RPNSWREQ.reg);
xe_device_mem_access_put(gt_to_xe(gt));
freq = REG_FIELD_GET(REQ_RATIO_MASK, freq);
@@ -588,7 +588,7 @@ static ssize_t rc_status_show(struct device *dev,
u32 reg;
xe_device_mem_access_get(gt_to_xe(gt));
- reg = xe_mmio_read32(gt, GEN6_GT_CORE_STATUS.reg);
+ reg = xe_mmio_read32(gt, GT_CORE_STATUS.reg);
xe_device_mem_access_put(gt_to_xe(gt));
switch (REG_FIELD_GET(RCN_MASK, reg)) {
@@ -615,7 +615,7 @@ static ssize_t rc6_residency_show(struct device *dev,
return ret;
xe_device_mem_access_get(pc_to_xe(pc));
- reg = xe_mmio_read32(gt, GEN6_GT_GFX_RC6.reg);
+ reg = xe_mmio_read32(gt, GT_GFX_RC6.reg);
xe_device_mem_access_put(pc_to_xe(pc));
ret = sysfs_emit(buff, "%u\n", reg);
@@ -745,9 +745,9 @@ static int pc_gucrc_disable(struct xe_guc_pc *pc)
if (ret)
return ret;
- xe_mmio_write32(gt, GEN9_PG_ENABLE.reg, 0);
- xe_mmio_write32(gt, GEN6_RC_CONTROL.reg, 0);
- xe_mmio_write32(gt, GEN6_RC_STATE.reg, 0);
+ xe_mmio_write32(gt, PG_ENABLE.reg, 0);
+ xe_mmio_write32(gt, RC_CONTROL.reg, 0);
+ xe_mmio_write32(gt, RC_STATE.reg, 0);
XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL));
return 0;
diff --git a/drivers/gpu/drm/xe/xe_huc.c b/drivers/gpu/drm/xe/xe_huc.c
index a1c3e54faa6e..55dcaab34ea4 100644
--- a/drivers/gpu/drm/xe/xe_huc.c
+++ b/drivers/gpu/drm/xe/xe_huc.c
@@ -84,7 +84,7 @@ int xe_huc_auth(struct xe_huc *huc)
goto fail;
}
- ret = xe_mmio_wait32(gt, GEN11_HUC_KERNEL_LOAD_INFO.reg,
+ ret = xe_mmio_wait32(gt, HUC_KERNEL_LOAD_INFO.reg,
HUC_LOAD_SUCCESSFUL,
HUC_LOAD_SUCCESSFUL, 100000, NULL, false);
if (ret) {
@@ -126,7 +126,7 @@ void xe_huc_print_info(struct xe_huc *huc, struct drm_printer *p)
return;
drm_printf(p, "\nHuC status: 0x%08x\n",
- xe_mmio_read32(gt, GEN11_HUC_KERNEL_LOAD_INFO.reg));
+ xe_mmio_read32(gt, HUC_KERNEL_LOAD_INFO.reg));
xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
}
diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index 4b56c35b988d..620b6008c272 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -110,28 +110,28 @@ static const struct engine_info engine_infos[] = {
.class = XE_ENGINE_CLASS_VIDEO_DECODE,
.instance = 0,
.domain = XE_FW_MEDIA_VDBOX0,
- .mmio_base = GEN11_BSD_RING_BASE,
+ .mmio_base = BSD_RING_BASE,
},
[XE_HW_ENGINE_VCS1] = {
.name = "vcs1",
.class = XE_ENGINE_CLASS_VIDEO_DECODE,
.instance = 1,
.domain = XE_FW_MEDIA_VDBOX1,
- .mmio_base = GEN11_BSD2_RING_BASE,
+ .mmio_base = BSD2_RING_BASE,
},
[XE_HW_ENGINE_VCS2] = {
.name = "vcs2",
.class = XE_ENGINE_CLASS_VIDEO_DECODE,
.instance = 2,
.domain = XE_FW_MEDIA_VDBOX2,
- .mmio_base = GEN11_BSD3_RING_BASE,
+ .mmio_base = BSD3_RING_BASE,
},
[XE_HW_ENGINE_VCS3] = {
.name = "vcs3",
.class = XE_ENGINE_CLASS_VIDEO_DECODE,
.instance = 3,
.domain = XE_FW_MEDIA_VDBOX3,
- .mmio_base = GEN11_BSD4_RING_BASE,
+ .mmio_base = BSD4_RING_BASE,
},
[XE_HW_ENGINE_VCS4] = {
.name = "vcs4",
@@ -166,14 +166,14 @@ static const struct engine_info engine_infos[] = {
.class = XE_ENGINE_CLASS_VIDEO_ENHANCE,
.instance = 0,
.domain = XE_FW_MEDIA_VEBOX0,
- .mmio_base = GEN11_VEBOX_RING_BASE,
+ .mmio_base = VEBOX_RING_BASE,
},
[XE_HW_ENGINE_VECS1] = {
.name = "vecs1",
.class = XE_ENGINE_CLASS_VIDEO_ENHANCE,
.instance = 1,
.domain = XE_FW_MEDIA_VEBOX1,
- .mmio_base = GEN11_VEBOX2_RING_BASE,
+ .mmio_base = VEBOX2_RING_BASE,
},
[XE_HW_ENGINE_VECS2] = {
.name = "vecs2",
@@ -194,28 +194,28 @@ static const struct engine_info engine_infos[] = {
.class = XE_ENGINE_CLASS_COMPUTE,
.instance = 0,
.domain = XE_FW_RENDER,
- .mmio_base = GEN12_COMPUTE0_RING_BASE,
+ .mmio_base = COMPUTE0_RING_BASE,
},
[XE_HW_ENGINE_CCS1] = {
.name = "ccs1",
.class = XE_ENGINE_CLASS_COMPUTE,
.instance = 1,
.domain = XE_FW_RENDER,
- .mmio_base = GEN12_COMPUTE1_RING_BASE,
+ .mmio_base = COMPUTE1_RING_BASE,
},
[XE_HW_ENGINE_CCS2] = {
.name = "ccs2",
.class = XE_ENGINE_CLASS_COMPUTE,
.instance = 2,
.domain = XE_FW_RENDER,
- .mmio_base = GEN12_COMPUTE2_RING_BASE,
+ .mmio_base = COMPUTE2_RING_BASE,
},
[XE_HW_ENGINE_CCS3] = {
.name = "ccs3",
.class = XE_ENGINE_CLASS_COMPUTE,
.instance = 3,
.domain = XE_FW_RENDER,
- .mmio_base = GEN12_COMPUTE3_RING_BASE,
+ .mmio_base = COMPUTE3_RING_BASE,
},
};
@@ -254,14 +254,14 @@ void xe_hw_engine_enable_ring(struct xe_hw_engine *hwe)
xe_hw_engine_mask_per_class(hwe->gt, XE_ENGINE_CLASS_COMPUTE);
if (hwe->class == XE_ENGINE_CLASS_COMPUTE && ccs_mask)
- xe_mmio_write32(hwe->gt, GEN12_RCU_MODE.reg,
- _MASKED_BIT_ENABLE(GEN12_RCU_MODE_CCS_ENABLE));
+ xe_mmio_write32(hwe->gt, RCU_MODE.reg,
+ _MASKED_BIT_ENABLE(RCU_MODE_CCS_ENABLE));
hw_engine_mmio_write32(hwe, RING_HWSTAM(0).reg, ~0x0);
hw_engine_mmio_write32(hwe, RING_HWS_PGA(0).reg,
xe_bo_ggtt_addr(hwe->hwsp));
- hw_engine_mmio_write32(hwe, RING_MODE_GEN7(0).reg,
- _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE));
+ hw_engine_mmio_write32(hwe, RING_MODE(0).reg,
+ _MASKED_BIT_ENABLE(GFX_DISABLE_LEGACY_MODE));
hw_engine_mmio_write32(hwe, RING_MI_MODE(0).reg,
_MASKED_BIT_DISABLE(STOP_RING));
hw_engine_mmio_read32(hwe, RING_MI_MODE(0).reg);
@@ -379,7 +379,7 @@ static void read_media_fuses(struct xe_gt *gt)
xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
- media_fuse = xe_mmio_read32(gt, GEN11_GT_VEBOX_VDBOX_DISABLE.reg);
+ media_fuse = xe_mmio_read32(gt, GT_VEBOX_VDBOX_DISABLE.reg);
/*
* Pre-Xe_HP platforms had register bits representing absent engines,
@@ -390,8 +390,8 @@ static void read_media_fuses(struct xe_gt *gt)
if (GRAPHICS_VERx100(xe) < 1250)
media_fuse = ~media_fuse;
- vdbox_mask = REG_FIELD_GET(GEN11_GT_VDBOX_DISABLE_MASK, media_fuse);
- vebox_mask = REG_FIELD_GET(GEN11_GT_VEBOX_DISABLE_MASK, media_fuse);
+ vdbox_mask = REG_FIELD_GET(GT_VDBOX_DISABLE_MASK, media_fuse);
+ vebox_mask = REG_FIELD_GET(GT_VEBOX_DISABLE_MASK, media_fuse);
for (i = XE_HW_ENGINE_VCS0, j = 0; i <= XE_HW_ENGINE_VCS7; ++i, ++j) {
if (!(gt->info.engine_mask & BIT(i)))
@@ -421,8 +421,8 @@ static void read_copy_fuses(struct xe_gt *gt)
xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
- bcs_mask = xe_mmio_read32(gt, GEN10_MIRROR_FUSE3.reg);
- bcs_mask = REG_FIELD_GET(GEN12_MEML3_EN_MASK, bcs_mask);
+ bcs_mask = xe_mmio_read32(gt, MIRROR_FUSE3.reg);
+ bcs_mask = REG_FIELD_GET(MEML3_EN_MASK, bcs_mask);
/* BCS0 is always present; only BCS1-BCS8 may be fused off */
for (int i = XE_HW_ENGINE_BCS1, j = 0; i <= XE_HW_ENGINE_BCS8; ++i, ++j) {
@@ -546,7 +546,7 @@ void xe_hw_engine_print_state(struct xe_hw_engine *hwe, struct drm_printer *p)
drm_printf(p, "\tRING_MODE: 0x%08x\n",
hw_engine_mmio_read32(hwe, RING_MI_MODE(0).reg));
drm_printf(p, "\tRING_MODE_GEN7: 0x%08x\n",
- hw_engine_mmio_read32(hwe, RING_MODE_GEN7(0).reg));
+ hw_engine_mmio_read32(hwe, RING_MODE(0).reg));
drm_printf(p, "\tRING_IMR: 0x%08x\n",
hw_engine_mmio_read32(hwe, RING_IMR(0).reg));
@@ -574,7 +574,7 @@ void xe_hw_engine_print_state(struct xe_hw_engine *hwe, struct drm_printer *p)
if (hwe->class == XE_ENGINE_CLASS_COMPUTE)
drm_printf(p, "\tGEN12_RCU_MODE: 0x%08x\n",
- xe_mmio_read32(hwe->gt, GEN12_RCU_MODE.reg));
+ xe_mmio_read32(hwe->gt, RCU_MODE.reg));
}
diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
index 98357c1f109f..a93838e23b7b 100644
--- a/drivers/gpu/drm/xe/xe_mmio.c
+++ b/drivers/gpu/drm/xe/xe_mmio.c
@@ -155,7 +155,8 @@ int xe_mmio_total_vram_size(struct xe_device *xe, u64 *vram_size, u64 *usable_si
if (!xe->info.has_flat_ccs) {
*vram_size = pci_resource_len(pdev, GEN12_LMEM_BAR);
if (usable_size)
- *usable_size = min(*vram_size, xe_mmio_read64(gt, GEN12_GSMBASE.reg));
+ *usable_size = min(*vram_size,
+ xe_mmio_read64(gt, GSMBASE.reg));
return 0;
}
diff --git a/drivers/gpu/drm/xe/xe_mocs.c b/drivers/gpu/drm/xe/xe_mocs.c
index e09c6242aafc..67c63facdbf9 100644
--- a/drivers/gpu/drm/xe/xe_mocs.c
+++ b/drivers/gpu/drm/xe/xe_mocs.c
@@ -512,8 +512,9 @@ static void init_l3cc_table(struct xe_gt *gt,
(l3cc = l3cc_combine(get_entry_l3cc(info, 2 * i),
get_entry_l3cc(info, 2 * i + 1))), 1 : 0;
i++) {
- mocs_dbg(>->xe->drm, "%d 0x%x 0x%x\n", i, GEN9_LNCFCMOCS(i).reg, l3cc);
- xe_mmio_write32(gt, GEN9_LNCFCMOCS(i).reg, l3cc);
+ mocs_dbg(>->xe->drm, "%d 0x%x 0x%x\n", i, LNCFCMOCS(i).reg,
+ l3cc);
+ xe_mmio_write32(gt, LNCFCMOCS(i).reg, l3cc);
}
}
@@ -531,7 +532,7 @@ void xe_mocs_init(struct xe_gt *gt)
gt->mocs.wb_index = table.wb_index;
if (flags & HAS_GLOBAL_MOCS)
- __init_mocs_table(gt, &table, GEN12_GLOBAL_MOCS(0).reg);
+ __init_mocs_table(gt, &table, GLOBAL_MOCS(0).reg);
/*
* Initialize the L3CC table as part of mocs initalization to make
diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
index c4b3a2045299..5a2665706912 100644
--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
+++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
@@ -31,7 +31,7 @@ static const struct xe_rtp_entry register_whitelist[] = {
},
{ XE_RTP_NAME("1508744258, 14012131227, 1808121037"),
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
- XE_RTP_ACTIONS(WHITELIST(GEN7_COMMON_SLICE_CHICKEN1, 0))
+ XE_RTP_ACTIONS(WHITELIST(COMMON_SLICE_CHICKEN1, 0))
},
{ XE_RTP_NAME("1806527549"),
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
index 918e819e7c91..5e61b6e61f3a 100644
--- a/drivers/gpu/drm/xe/xe_ring_ops.c
+++ b/drivers/gpu/drm/xe/xe_ring_ops.c
@@ -85,7 +85,7 @@ static int emit_flush_imm_ggtt(u32 addr, u32 value, u32 *dw, int i)
static int emit_bb_start(u64 batch_addr, u32 ppgtt_flag, u32 *dw, int i)
{
- dw[i++] = MI_BATCH_BUFFER_START_GEN8 | ppgtt_flag;
+ dw[i++] = MI_BATCH_BUFFER_START | ppgtt_flag;
dw[i++] = lower_32_bits(batch_addr);
dw[i++] = upper_32_bits(batch_addr);
@@ -202,9 +202,9 @@ static void __emit_job_gen12_video(struct xe_sched_job *job, struct xe_lrc *lrc,
/* Wa_1809175790 */
if (!xe->info.has_flat_ccs) {
if (decode)
- i = emit_aux_table_inv(gt, GEN12_VD0_AUX_NV.reg, dw, i);
+ i = emit_aux_table_inv(gt, VD0_AUX_NV.reg, dw, i);
else
- i = emit_aux_table_inv(gt, GEN12_VE0_AUX_NV.reg, dw, i);
+ i = emit_aux_table_inv(gt, VE0_AUX_NV.reg, dw, i);
}
dw[i++] = preparser_disable(false);
@@ -246,7 +246,7 @@ static void __emit_job_gen12_render_compute(struct xe_sched_job *job,
i = emit_pipe_invalidate(mask_flags, dw, i);
/* Wa_1809175790 */
if (!xe->info.has_flat_ccs)
- i = emit_aux_table_inv(gt, GEN12_GFX_CCS_AUX_NV.reg, dw, i);
+ i = emit_aux_table_inv(gt, GFX_CCS_AUX_NV.reg, dw, i);
dw[i++] = preparser_disable(false);
i = emit_store_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc),
diff --git a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
index 31887fec1073..9ce0a0585539 100644
--- a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
+++ b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
@@ -65,7 +65,7 @@ static s64 detect_bar2_dgfx(struct xe_device *xe, struct xe_ttm_stolen_mgr *mgr)
}
/* Use DSM base address instead for stolen memory */
- mgr->stolen_base = xe_mmio_read64(gt, GEN12_DSMBASE.reg) & GEN12_BDSM_MASK;
+ mgr->stolen_base = xe_mmio_read64(gt, DSMBASE.reg) & BDSM_MASK;
if (drm_WARN_ON(&xe->drm, vram_size < mgr->stolen_base))
return 0;
diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
index 27cf1330facd..43912312cfba 100644
--- a/drivers/gpu/drm/xe/xe_tuning.c
+++ b/drivers/gpu/drm/xe/xe_tuning.c
@@ -33,7 +33,7 @@ static const struct xe_rtp_entry lrc_tunings[] = {
{ XE_RTP_NAME("Tuning: ganged timer, also known as 16011163337"),
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
/* read verification is ignored due to 1608008084. */
- XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(GEN12_FF_MODE2,
+ XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(FF_MODE2,
FF_MODE2_GS_TIMER_MASK,
FF_MODE2_GS_TIMER_224))
},
diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index a7d681b7538d..f402d56c675c 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -105,7 +105,7 @@ static const struct xe_rtp_entry gt_was[] = {
},
{ XE_RTP_NAME("14011059788"),
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
- XE_RTP_ACTIONS(SET(GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE))
+ XE_RTP_ACTIONS(SET(DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE))
},
/* DG1 */
@@ -134,7 +134,7 @@ static const struct xe_rtp_entry gt_was[] = {
},
{ XE_RTP_NAME("14011006942"),
XE_RTP_RULES(SUBPLATFORM(DG2, G10)),
- XE_RTP_ACTIONS(SET(GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE, DSS_ROUTER_CLKGATE_DIS))
+ XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE, DSS_ROUTER_CLKGATE_DIS))
},
{ XE_RTP_NAME("14012362059"),
XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, B0)),
@@ -197,7 +197,7 @@ static const struct xe_rtp_entry gt_was[] = {
},
{ XE_RTP_NAME("14015795083"),
XE_RTP_RULES(PLATFORM(DG2)),
- XE_RTP_ACTIONS(CLR(GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE))
+ XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE))
},
{ XE_RTP_NAME("18018781329"),
XE_RTP_RULES(PLATFORM(DG2)),
@@ -221,7 +221,7 @@ static const struct xe_rtp_entry gt_was[] = {
{ XE_RTP_NAME("14015795083"),
XE_RTP_RULES(PLATFORM(PVC)),
- XE_RTP_ACTIONS(CLR(GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE))
+ XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE))
},
{ XE_RTP_NAME("18018781329"),
XE_RTP_RULES(PLATFORM(PVC)),
@@ -241,42 +241,42 @@ static const struct xe_rtp_entry gt_was[] = {
static const struct xe_rtp_entry engine_was[] = {
{ XE_RTP_NAME("22010931296, 18011464164, 14010919138"),
XE_RTP_RULES(GRAPHICS_VERSION(1200), ENGINE_CLASS(RENDER)),
- XE_RTP_ACTIONS(SET(GEN7_FF_THREAD_MODE,
- GEN12_FF_TESSELATION_DOP_GATE_DISABLE))
+ XE_RTP_ACTIONS(SET(FF_THREAD_MODE,
+ FF_TESSELATION_DOP_GATE_DISABLE))
},
{ XE_RTP_NAME("1409804808"),
XE_RTP_RULES(GRAPHICS_VERSION(1200),
ENGINE_CLASS(RENDER),
IS_INTEGRATED),
- XE_RTP_ACTIONS(SET(GEN8_ROW_CHICKEN2, GEN12_PUSH_CONST_DEREF_HOLD_DIS,
+ XE_RTP_ACTIONS(SET(ROW_CHICKEN2, PUSH_CONST_DEREF_HOLD_DIS,
XE_RTP_ACTION_FLAG(MASKED_REG)))
},
{ XE_RTP_NAME("14010229206, 1409085225"),
XE_RTP_RULES(GRAPHICS_VERSION(1200),
ENGINE_CLASS(RENDER),
IS_INTEGRATED),
- XE_RTP_ACTIONS(SET(GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH,
+ XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH,
XE_RTP_ACTION_FLAG(MASKED_REG)))
},
{ XE_RTP_NAME("1606931601"),
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
- XE_RTP_ACTIONS(SET(GEN8_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ,
+ XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_EARLY_READ,
XE_RTP_ACTION_FLAG(MASKED_REG)))
},
{ XE_RTP_NAME("14010826681, 1606700617, 22010271021, 18019627453"),
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1255), ENGINE_CLASS(RENDER)),
- XE_RTP_ACTIONS(SET(GEN9_CS_DEBUG_MODE1, FF_DOP_CLOCK_GATE_DISABLE,
+ XE_RTP_ACTIONS(SET(CS_DEBUG_MODE1, FF_DOP_CLOCK_GATE_DISABLE,
XE_RTP_ACTION_FLAG(MASKED_REG)))
},
{ XE_RTP_NAME("1406941453"),
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
- XE_RTP_ACTIONS(SET(GEN10_SAMPLER_MODE, ENABLE_SMALLPL,
+ XE_RTP_ACTIONS(SET(SAMPLER_MODE, ENABLE_SMALLPL,
XE_RTP_ACTION_FLAG(MASKED_REG)))
},
{ XE_RTP_NAME("FtrPerCtxtPreemptionGranularityControl"),
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1250), ENGINE_CLASS(RENDER)),
- XE_RTP_ACTIONS(SET(GEN7_FF_SLICE_CS_CHICKEN1,
- GEN9_FFSC_PERCTX_PREEMPT_CTRL,
+ XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN1,
+ FFSC_PERCTX_PREEMPT_CTRL,
XE_RTP_ACTION_FLAG(MASKED_REG)))
},
@@ -285,8 +285,8 @@ static const struct xe_rtp_entry engine_was[] = {
{ XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
XE_RTP_RULES(PLATFORM(TIGERLAKE), ENGINE_CLASS(RENDER)),
XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
- GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
- GEN8_RC_SEMA_IDLE_MSG_DISABLE,
+ WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
+ RC_SEMA_IDLE_MSG_DISABLE,
XE_RTP_ACTION_FLAG(MASKED_REG)))
},
@@ -295,8 +295,8 @@ static const struct xe_rtp_entry engine_was[] = {
{ XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
XE_RTP_RULES(PLATFORM(ROCKETLAKE), ENGINE_CLASS(RENDER)),
XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
- GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
- GEN8_RC_SEMA_IDLE_MSG_DISABLE,
+ WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
+ RC_SEMA_IDLE_MSG_DISABLE,
XE_RTP_ACTION_FLAG(MASKED_REG)))
},
@@ -305,8 +305,8 @@ static const struct xe_rtp_entry engine_was[] = {
{ XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
XE_RTP_RULES(PLATFORM(ALDERLAKE_P), ENGINE_CLASS(RENDER)),
XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
- GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
- GEN8_RC_SEMA_IDLE_MSG_DISABLE,
+ WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
+ RC_SEMA_IDLE_MSG_DISABLE,
XE_RTP_ACTION_FLAG(MASKED_REG)))
},
@@ -366,7 +366,7 @@ static const struct xe_rtp_entry engine_was[] = {
{ XE_RTP_NAME("14015227452"),
XE_RTP_RULES(PLATFORM(DG2),
FUNC(xe_rtp_match_first_render_or_compute)),
- XE_RTP_ACTIONS(SET(GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE,
+ XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE,
XE_RTP_ACTION_FLAG(MASKED_REG)))
},
{ XE_RTP_NAME("16015675438"),
@@ -405,36 +405,36 @@ static const struct xe_rtp_entry engine_was[] = {
},
{ XE_RTP_NAME("1509727124"),
XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
- XE_RTP_ACTIONS(SET(GEN10_SAMPLER_MODE, SC_DISABLE_POWER_OPTIMIZATION_EBB,
+ XE_RTP_ACTIONS(SET(SAMPLER_MODE, SC_DISABLE_POWER_OPTIMIZATION_EBB,
XE_RTP_ACTION_FLAG(MASKED_REG)))
},
{ XE_RTP_NAME("22012856258"),
XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
- XE_RTP_ACTIONS(SET(GEN8_ROW_CHICKEN2, GEN12_DISABLE_READ_SUPPRESSION,
+ XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_READ_SUPPRESSION,
XE_RTP_ACTION_FLAG(MASKED_REG)))
},
{ XE_RTP_NAME("14013392000"),
XE_RTP_RULES(SUBPLATFORM(DG2, G11), STEP(A0, B0), ENGINE_CLASS(RENDER)),
- XE_RTP_ACTIONS(SET(GEN8_ROW_CHICKEN2, GEN12_ENABLE_LARGE_GRF_MODE,
+ XE_RTP_ACTIONS(SET(ROW_CHICKEN2, ENABLE_LARGE_GRF_MODE,
XE_RTP_ACTION_FLAG(MASKED_REG)))
},
{ XE_RTP_NAME("14012419201"),
XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, B0), ENGINE_CLASS(RENDER)),
- XE_RTP_ACTIONS(SET(GEN9_ROW_CHICKEN4,
- GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX,
+ XE_RTP_ACTIONS(SET(ROW_CHICKEN4,
+ DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX,
XE_RTP_ACTION_FLAG(MASKED_REG)))
},
{ XE_RTP_NAME("14012419201"),
XE_RTP_RULES(SUBPLATFORM(DG2, G11), STEP(A0, B0), ENGINE_CLASS(RENDER)),
- XE_RTP_ACTIONS(SET(GEN9_ROW_CHICKEN4,
- GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX,
+ XE_RTP_ACTIONS(SET(ROW_CHICKEN4,
+ DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX,
XE_RTP_ACTION_FLAG(MASKED_REG)))
},
{ XE_RTP_NAME("1308578152"),
XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(B0, C0), ENGINE_CLASS(RENDER),
FUNC(xe_rtp_match_first_gslice_fused_off)),
- XE_RTP_ACTIONS(CLR(GEN9_CS_DEBUG_MODE1,
- GEN12_REPLAY_MODE_GRANULARITY,
+ XE_RTP_ACTIONS(CLR(CS_DEBUG_MODE1,
+ REPLAY_MODE_GRANULARITY,
XE_RTP_ACTION_FLAG(MASKED_REG)))
},
{ XE_RTP_NAME("22010960976, 14013347512"),
@@ -445,14 +445,14 @@ static const struct xe_rtp_entry engine_was[] = {
},
{ XE_RTP_NAME("1608949956, 14010198302"),
XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
- XE_RTP_ACTIONS(SET(GEN8_ROW_CHICKEN,
+ XE_RTP_ACTIONS(SET(ROW_CHICKEN,
MDQ_ARBITRATION_MODE | UGM_BACKUP_MODE,
XE_RTP_ACTION_FLAG(MASKED_REG)))
},
{ XE_RTP_NAME("22010430635"),
XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, B0), ENGINE_CLASS(RENDER)),
- XE_RTP_ACTIONS(SET(GEN9_ROW_CHICKEN4,
- GEN12_DISABLE_GRF_CLEAR,
+ XE_RTP_ACTIONS(SET(ROW_CHICKEN4,
+ DISABLE_GRF_CLEAR,
XE_RTP_ACTION_FLAG(MASKED_REG)))
},
{ XE_RTP_NAME("14013202645"),
@@ -465,13 +465,13 @@ static const struct xe_rtp_entry engine_was[] = {
},
{ XE_RTP_NAME("22012532006"),
XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, C0), ENGINE_CLASS(RENDER)),
- XE_RTP_ACTIONS(SET(GEN9_HALF_SLICE_CHICKEN7,
+ XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7,
DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA,
XE_RTP_ACTION_FLAG(MASKED_REG)))
},
{ XE_RTP_NAME("22012532006"),
XE_RTP_RULES(SUBPLATFORM(DG2, G11), STEP(A0, B0), ENGINE_CLASS(RENDER)),
- XE_RTP_ACTIONS(SET(GEN9_HALF_SLICE_CHICKEN7,
+ XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7,
DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA,
XE_RTP_ACTION_FLAG(MASKED_REG)))
},
@@ -507,7 +507,7 @@ static const struct xe_rtp_entry engine_was[] = {
},
{ XE_RTP_NAME("14015227452"),
XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)),
- XE_RTP_ACTIONS(SET(GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE,
+ XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE,
XE_RTP_ACTION_FLAG(MASKED_REG)))
},
{ XE_RTP_NAME("16015675438"),
@@ -526,15 +526,15 @@ static const struct xe_rtp_entry engine_was[] = {
static const struct xe_rtp_entry lrc_was[] = {
{ XE_RTP_NAME("1409342910, 14010698770, 14010443199, 1408979724, 1409178076, 1409207793, 1409217633, 1409252684, 1409347922, 1409142259"),
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
- XE_RTP_ACTIONS(SET(GEN11_COMMON_SLICE_CHICKEN3,
- GEN12_DISABLE_CPS_AWARE_COLOR_PIPE,
+ XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN3,
+ DISABLE_CPS_AWARE_COLOR_PIPE,
XE_RTP_ACTION_FLAG(MASKED_REG)))
},
{ XE_RTP_NAME("WaDisableGPGPUMidThreadPreemption"),
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
- XE_RTP_ACTIONS(FIELD_SET(GEN8_CS_CHICKEN1,
- GEN9_PREEMPT_GPGPU_LEVEL_MASK,
- GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL,
+ XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1,
+ PREEMPT_GPGPU_LEVEL_MASK,
+ PREEMPT_GPGPU_THREAD_GROUP_LEVEL,
XE_RTP_ACTION_FLAG(MASKED_REG)))
},
{ XE_RTP_NAME("1806527549"),
@@ -552,7 +552,7 @@ static const struct xe_rtp_entry lrc_was[] = {
{ XE_RTP_NAME("1409044764"),
XE_RTP_RULES(PLATFORM(DG1)),
- XE_RTP_ACTIONS(CLR(GEN11_COMMON_SLICE_CHICKEN3,
+ XE_RTP_ACTIONS(CLR(COMMON_SLICE_CHICKEN3,
DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN,
XE_RTP_ACTION_FLAG(MASKED_REG)))
},
@@ -581,7 +581,7 @@ static const struct xe_rtp_entry lrc_was[] = {
{ XE_RTP_NAME("14010698770, 22010613112, 22010465075"),
XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, B0)),
XE_RTP_ACTIONS(SET(XEHP_COMMON_SLICE_CHICKEN3,
- GEN12_DISABLE_CPS_AWARE_COLOR_PIPE,
+ DISABLE_CPS_AWARE_COLOR_PIPE,
XE_RTP_ACTION_FLAG(MASKED_REG)))
},
{ XE_RTP_NAME("16013271637"),
--
2.39.0
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Intel-xe] [PATCH 10/17] drm/xe: Use REG_FIELD/REG_BIT for all regs/*.h
2023-04-19 7:44 [Intel-xe] [PATCH 00/17] Cleanup registers and introduce xe_reg_t Lucas De Marchi
` (8 preceding siblings ...)
2023-04-19 7:44 ` [Intel-xe] [PATCH 09/17] drm/xe: Drop gen prefixes and suffixes from registers Lucas De Marchi
@ 2023-04-19 7:44 ` Lucas De Marchi
2023-04-19 7:44 ` [Intel-xe] [PATCH 11/17] drm/xe: Introduce xe_reg_t Lucas De Marchi
` (10 subsequent siblings)
20 siblings, 0 replies; 41+ messages in thread
From: Lucas De Marchi @ 2023-04-19 7:44 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, Matt Roper, Rodrigo Vivi
Convert the macro declarations to the equivalent GENMASK and
and bitfield prep for all registers.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/regs/xe_engine_regs.h | 24 +++++------
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 53 +++++++++++-------------
drivers/gpu/drm/xe/regs/xe_regs.h | 12 +++---
drivers/gpu/drm/xe/xe_gt_clock.c | 17 ++++----
4 files changed, 48 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
index bfcb0e9a6d4c..938055f75492 100644
--- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
@@ -22,7 +22,7 @@
#define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */
#define RING_PSMI_CTL(base) _MMIO((base) + 0x50)
-#define RC_SEMA_IDLE_MSG_DISABLE REG_BIT(12)
+#define RC_SEMA_IDLE_MSG_DISABLE REG_BIT(12)
#define WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
#define RING_ACTHD_UDW(base) _MMIO((base) + 0x5c)
@@ -54,7 +54,7 @@
#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT REG_BIT(0)
#define RING_MODE(base) _MMIO((base) + 0x29c)
-#define GFX_DISABLE_LEGACY_MODE (1 << 3)
+#define GFX_DISABLE_LEGACY_MODE REG_BIT(3)
#define RING_TIMESTAMP(base) _MMIO((base) + 0x358)
@@ -68,17 +68,17 @@
#define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4d0) + (i) * 4)
#define RING_FORCE_TO_NONPRIV_DENY REG_BIT(30)
+#define RING_FORCE_TO_NONPRIV_ACCESS_MASK REG_GENMASK(29, 28)
+#define RING_FORCE_TO_NONPRIV_ACCESS_RW REG_FIELD_PREP(RING_FORCE_TO_NONPRIV_ACCESS_MASK, 0)
+#define RING_FORCE_TO_NONPRIV_ACCESS_RD REG_FIELD_PREP(RING_FORCE_TO_NONPRIV_ACCESS_MASK, 1)
+#define RING_FORCE_TO_NONPRIV_ACCESS_WR REG_FIELD_PREP(RING_FORCE_TO_NONPRIV_ACCESS_MASK, 2)
+#define RING_FORCE_TO_NONPRIV_ACCESS_INVALID REG_FIELD_PREP(RING_FORCE_TO_NONPRIV_ACCESS_MASK, 3)
#define RING_FORCE_TO_NONPRIV_ADDRESS_MASK REG_GENMASK(25, 2)
-#define RING_FORCE_TO_NONPRIV_ACCESS_RW (0 << 28)
-#define RING_FORCE_TO_NONPRIV_ACCESS_RD (1 << 28)
-#define RING_FORCE_TO_NONPRIV_ACCESS_WR (2 << 28)
-#define RING_FORCE_TO_NONPRIV_ACCESS_INVALID (3 << 28)
-#define RING_FORCE_TO_NONPRIV_ACCESS_MASK (3 << 28)
-#define RING_FORCE_TO_NONPRIV_RANGE_1 (0 << 0)
-#define RING_FORCE_TO_NONPRIV_RANGE_4 (1 << 0)
-#define RING_FORCE_TO_NONPRIV_RANGE_16 (2 << 0)
-#define RING_FORCE_TO_NONPRIV_RANGE_64 (3 << 0)
-#define RING_FORCE_TO_NONPRIV_RANGE_MASK (3 << 0)
+#define RING_FORCE_TO_NONPRIV_RANGE_MASK REG_GENMASK(1, 0)
+#define RING_FORCE_TO_NONPRIV_RANGE_1 REG_FIELD_PREP(RING_FORCE_TO_NONPRIV_RANGE_MASK, 0)
+#define RING_FORCE_TO_NONPRIV_RANGE_4 REG_FIELD_PREP(RING_FORCE_TO_NONPRIV_RANGE_MASK, 1)
+#define RING_FORCE_TO_NONPRIV_RANGE_16 REG_FIELD_PREP(RING_FORCE_TO_NONPRIV_RANGE_MASK, 2)
+#define RING_FORCE_TO_NONPRIV_RANGE_64 REG_FIELD_PREP(RING_FORCE_TO_NONPRIV_RANGE_MASK, 3)
#define RING_FORCE_TO_NONPRIV_MASK_VALID (RING_FORCE_TO_NONPRIV_RANGE_MASK | \
RING_FORCE_TO_NONPRIV_ACCESS_MASK | \
RING_FORCE_TO_NONPRIV_DENY)
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 0908224737dc..4076d903b20e 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -9,15 +9,13 @@
#include "regs/xe_reg_defs.h"
/* RPM unit config (Gen8+) */
-#define RPM_CONFIG0 _MMIO(0xd00)
-#define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3
-#define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (0x7 << RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
-#define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 0
+#define RPM_CONFIG0 _MMIO(0xd00)
+#define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK REG_GENMASK(5, 4)
+#define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 0
#define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 1
#define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ 2
-#define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ 3
-#define RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT 1
-#define RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK (0x3 << RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT)
+#define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ 3
+#define RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK REG_GENMASK(2, 1)
#define FORCEWAKE_ACK_MEDIA_VDBOX(n) _MMIO(0xd50 + (n) * 4)
#define FORCEWAKE_ACK_MEDIA_VEBOX(n) _MMIO(0xd70 + (n) * 4)
@@ -39,15 +37,15 @@
#define MCR_SELECTOR _MMIO(0xfdc)
#define GAM_MCR_SELECTOR _MMIO(0xfe0)
#define MCR_MULTICAST REG_BIT(31)
-#define MCR_SLICE(slice) (((slice) & 0xf) << 27)
-#define MCR_SLICE_MASK MCR_SLICE(0xf)
-#define MCR_SUBSLICE(subslice) (((subslice) & 0x7) << 24)
-#define MCR_SUBSLICE_MASK MCR_SUBSLICE(0x7)
+#define MCR_SLICE_MASK REG_GENMASK(30, 27)
+#define MCR_SLICE(slice) REG_FIELD_PREP(MCR_SLICE_MASK, slice)
+#define MCR_SUBSLICE_MASK REG_GENMASK(26, 24)
+#define MCR_SUBSLICE(subslice) REG_FIELD_PREP(MCR_SUBSLICE_MASK, subslice)
#define MTL_MCR_GROUPID REG_GENMASK(11, 8)
#define MTL_MCR_INSTANCEID REG_GENMASK(3, 0)
#define FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0)
-#define FFSC_PERCTX_PREEMPT_CTRL (1 << 14)
+#define FFSC_PERCTX_PREEMPT_CTRL REG_BIT(14)
#define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4)
#define PERF_FIX_BALANCING_CFE_DISABLE REG_BIT(15)
@@ -59,12 +57,12 @@
#define PS_INVOCATION_COUNT _MMIO(0x2348)
#define CS_CHICKEN1 _MMIO(0x2580)
-#define PREEMPT_3D_OBJECT_LEVEL (1 << 0)
#define PREEMPT_GPGPU_LEVEL(hi, lo) (((hi) << 2) | ((lo) << 1))
#define PREEMPT_GPGPU_MID_THREAD_LEVEL PREEMPT_GPGPU_LEVEL(0, 0)
#define PREEMPT_GPGPU_THREAD_GROUP_LEVEL PREEMPT_GPGPU_LEVEL(0, 1)
#define PREEMPT_GPGPU_COMMAND_LEVEL PREEMPT_GPGPU_LEVEL(1, 0)
#define PREEMPT_GPGPU_LEVEL_MASK PREEMPT_GPGPU_LEVEL(1, 1)
+#define PREEMPT_3D_OBJECT_LEVEL REG_BIT(0)
#define GLOBAL_MOCS(i) _MMIO(0x4000 + (i) * 4) /* Global MOCS regs */
#define GFX_CCS_AUX_NV _MMIO(0x4208)
@@ -131,19 +129,18 @@
#define MIRROR_FUSE3 _MMIO(0x9118)
#define L3BANK_PAIR_COUNT 4
-#define L3BANK_MASK 0x0F
+#define L3BANK_MASK REG_GENMASK(3, 0)
/* on Xe_HP the same fuses indicates mslices instead of L3 banks */
#define MAX_MSLICES 4
-#define MEML3_EN_MASK 0x0F
+#define MEML3_EN_MASK REG_GENMASK(3, 0)
/* Fuse readout registers for GT */
#define XEHP_FUSE4 _MMIO(0x9114)
#define GT_L3_EXC_MASK REG_GENMASK(6, 4)
#define GT_VEBOX_VDBOX_DISABLE _MMIO(0x9140)
-#define GT_VDBOX_DISABLE_MASK 0xff
-#define GT_VEBOX_DISABLE_SHIFT 16
-#define GT_VEBOX_DISABLE_MASK (0x0f << GT_VEBOX_DISABLE_SHIFT)
+#define GT_VEBOX_DISABLE_MASK REG_GENMASK(19, 16)
+#define GT_VDBOX_DISABLE_MASK REG_GENMASK(7, 0)
#define XELP_EU_ENABLE _MMIO(0x9134) /* "_DISABLE" on Xe_LP */
#define XELP_EU_MASK REG_GENMASK(7, 0)
@@ -203,9 +200,9 @@
#define LTCDD_CLKGATE_DIS REG_BIT(10)
#define XEHP_SLICE_UNIT_LEVEL_CLKGATE MCR_REG(0x94d4)
-#define SARBUNIT_CLKGATE_DIS (1 << 5)
-#define RCCUNIT_CLKGATE_DIS (1 << 7)
-#define MSCUNIT_CLKGATE_DIS (1 << 10)
+#define SARBUNIT_CLKGATE_DIS REG_BIT(5)
+#define RCCUNIT_CLKGATE_DIS REG_BIT(7)
+#define MSCUNIT_CLKGATE_DIS REG_BIT(10)
#define NODEDSS_CLKGATE_DIS REG_BIT(12)
#define L3_CLKGATE_DIS REG_BIT(16)
#define L3_CR2X_CLKGATE_DIS REG_BIT(17)
@@ -225,7 +222,7 @@
#define RTFUNIT_CLKGATE_DIS REG_BIT(18)
#define DFR_RATIO_EN_AND_CHICKEN MCR_REG(0x9550)
-#define DFR_DISABLE (1 << 9)
+#define DFR_DISABLE REG_BIT(9)
#define RPNSWREQ _MMIO(0xa008)
#define REQ_RATIO_MASK REG_GENMASK(31, 23)
@@ -233,20 +230,18 @@
#define RC_STATE _MMIO(0xa094)
#define PMINTRMSK _MMIO(0xa168)
-#define PMINTR_DISABLE_REDIRECT_TO_GUC (1 << 31)
-#define ARAT_EXPIRED_INTRMSK (1 << 9)
+#define PMINTR_DISABLE_REDIRECT_TO_GUC REG_BIT(31)
+#define ARAT_EXPIRED_INTRMSK REG_BIT(9)
#define FORCEWAKE_GT _MMIO(0xa188)
#define PG_ENABLE _MMIO(0xa210)
-/* GPM unit config (Gen9+) */
#define CTC_MODE _MMIO(0xa26c)
-#define CTC_SOURCE_PARAMETER_MASK 1
+#define CTC_SHIFT_PARAMETER_MASK REG_GENMASK(2, 1)
+#define CTC_SOURCE_PARAMETER_MASK REG_BIT(0)
#define CTC_SOURCE_CRYSTAL_CLOCK 0
#define CTC_SOURCE_DIVIDE_LOGIC 1
-#define CTC_SHIFT_PARAMETER_SHIFT 1
-#define CTC_SHIFT_PARAMETER_MASK (0x3 << CTC_SHIFT_PARAMETER_SHIFT)
#define FORCEWAKE_RENDER _MMIO(0xa278)
#define FORCEWAKE_MEDIA_VDBOX(n) _MMIO(0xa540 + (n) * 4)
@@ -350,7 +345,7 @@
#define GT_GFX_RC6 _MMIO(0x138108)
#define GFX_FLSH_CNTL _MMIO(0x101008)
-#define GFX_FLSH_CNTL_EN (1 << 0)
+#define GFX_FLSH_CNTL_EN REG_BIT(0)
#define GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4))
diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h
index e6b81bcff91f..da1d5aa6cdb7 100644
--- a/drivers/gpu/drm/xe/regs/xe_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_regs.h
@@ -37,10 +37,10 @@
#define XEHPC_BCS7_RING_BASE 0x3ec000
#define XEHPC_BCS8_RING_BASE 0x3ee000
#define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11)
-#define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8)
-#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
+#define GT_CONTEXT_SWITCH_INTERRUPT REG_BIT(8)
+#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT REG_BIT(4)
#define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3)
-#define GT_RENDER_USER_INTERRUPT (1 << 0)
+#define GT_RENDER_USER_INTERRUPT REG_BIT(0)
#define FF_THREAD_MODE _MMIO(0x20a0)
#define FF_TESSELATION_DOP_GATE_DISABLE BIT(19)
@@ -90,10 +90,8 @@
#define DG1_MSTR_TILE(t) REG_BIT(t)
#define TIMESTAMP_OVERRIDE _MMIO(0x44074)
-#define TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0
-#define TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff
-#define TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12
-#define TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12)
+#define TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK REG_GENMASK(15, 12)
+#define TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK REG_GENMASK(9, 0)
#define GGC _MMIO(0x108040)
#define GMS_MASK REG_GENMASK(15, 8)
diff --git a/drivers/gpu/drm/xe/xe_gt_clock.c b/drivers/gpu/drm/xe/xe_gt_clock.c
index 1b7d00284535..384a47d3c3eb 100644
--- a/drivers/gpu/drm/xe/xe_gt_clock.c
+++ b/drivers/gpu/drm/xe/xe_gt_clock.c
@@ -17,13 +17,12 @@ static u32 read_reference_ts_freq(struct xe_gt *gt)
u32 ts_override = xe_mmio_read32(gt, TIMESTAMP_OVERRIDE.reg);
u32 base_freq, frac_freq;
- base_freq = ((ts_override & TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK) >>
- TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT) + 1;
+ base_freq = REG_FIELD_GET(TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK,
+ ts_override) + 1;
base_freq *= 1000000;
- frac_freq = ((ts_override &
- TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK) >>
- TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT);
+ frac_freq = REG_FIELD_GET(TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK,
+ ts_override);
frac_freq = 1000000 / (frac_freq + 1);
return base_freq + frac_freq;
@@ -35,9 +34,8 @@ static u32 get_crystal_clock_freq(u32 rpm_config_reg)
const u32 f24_mhz = 24000000;
const u32 f25_mhz = 25000000;
const u32 f38_4_mhz = 38400000;
- u32 crystal_clock =
- (rpm_config_reg & RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >>
- RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
+ u32 crystal_clock = REG_FIELD_GET(RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK,
+ rpm_config_reg);
switch (crystal_clock) {
case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ :
@@ -74,8 +72,7 @@ int xe_gt_clock_init(struct xe_gt *gt)
* register increments from this frequency (it might
* increment only every few clock cycle).
*/
- freq >>= 3 - ((c0 & RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
- RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);
+ freq >>= 3 - REG_FIELD_GET(RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, c0);
}
gt->info.clock_freq = freq;
--
2.39.0
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Intel-xe] [PATCH 11/17] drm/xe: Introduce xe_reg_t
2023-04-19 7:44 [Intel-xe] [PATCH 00/17] Cleanup registers and introduce xe_reg_t Lucas De Marchi
` (9 preceding siblings ...)
2023-04-19 7:44 ` [Intel-xe] [PATCH 10/17] drm/xe: Use REG_FIELD/REG_BIT for all regs/*.h Lucas De Marchi
@ 2023-04-19 7:44 ` Lucas De Marchi
2023-04-19 16:06 ` Jani Nikula
2023-04-19 17:33 ` Matt Roper
2023-04-19 7:44 ` [Intel-xe] [PATCH 12/17] drm/xe: Clarify register types on PAT programming Lucas De Marchi
` (9 subsequent siblings)
20 siblings, 2 replies; 41+ messages in thread
From: Lucas De Marchi @ 2023-04-19 7:44 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, Matt Roper, Rodrigo Vivi
Stop using i915 types for register our own xe_reg_t. Differently from
i915, this will keep under this will keep under the register definition
the knowledge for the different types of registers. For now, the "flags"
are mcr and masked, although only the former is being used.
Most of the driver is agnostic to the register differences. Convert the
few places that care about that, namely xe_gt_mcr.c, to take the generic
type and warn if the wrong register is used.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/regs/xe_reg_defs.h | 15 +++++++++++++++
drivers/gpu/drm/xe/xe_gt_mcr.c | 22 ++++++++++++++++------
drivers/gpu/drm/xe/xe_gt_mcr.h | 8 ++++----
drivers/gpu/drm/xe/xe_irq.c | 2 +-
drivers/gpu/drm/xe/xe_mmio.c | 2 +-
5 files changed, 37 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/xe/regs/xe_reg_defs.h b/drivers/gpu/drm/xe/regs/xe_reg_defs.h
index b5c25e31b889..1e78508c737b 100644
--- a/drivers/gpu/drm/xe/regs/xe_reg_defs.h
+++ b/drivers/gpu/drm/xe/regs/xe_reg_defs.h
@@ -8,4 +8,19 @@
#include "compat-i915-headers/i915_reg_defs.h"
+typedef union {
+ struct {
+ u32 reg:30;
+ u32 mcr:1;
+ u32 masked:1;
+ };
+ u32 raw;
+} xe_reg_t;
+
+/* TODO: remove these once the register declarations are not using them anymore */
+#undef _MMIO
+#undef MCR_REG
+#define _MMIO(r) ((const xe_reg_t){ .reg = (r) })
+#define MCR_REG(r) ((const xe_reg_t){ .reg = (r), .mcr = 1 })
+
#endif
diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
index aa04ba5a6dbe..b9631cfd5b81 100644
--- a/drivers/gpu/drm/xe/xe_gt_mcr.c
+++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
@@ -360,11 +360,13 @@ void xe_gt_mcr_set_implicit_defaults(struct xe_gt *gt)
* returned. Returns false if the caller need not perform any steering
*/
static bool xe_gt_mcr_get_nonterminated_steering(struct xe_gt *gt,
- i915_mcr_reg_t reg,
+ xe_reg_t reg,
u8 *group, u8 *instance)
{
const struct xe_mmio_range *implicit_ranges;
+ drm_WARN_ON(>_to_xe(gt)->drm, !reg.mcr);
+
for (int type = 0; type < IMPLICIT_STEERING; type++) {
if (!gt->steering[type].ranges)
continue;
@@ -436,11 +438,13 @@ static void mcr_unlock(struct xe_gt *gt) {
*
* Caller needs to make sure the relevant forcewake wells are up.
*/
-static u32 rw_with_mcr_steering(struct xe_gt *gt, i915_mcr_reg_t reg, u8 rw_flag,
+static u32 rw_with_mcr_steering(struct xe_gt *gt, xe_reg_t reg, u8 rw_flag,
int group, int instance, u32 value)
{
u32 steer_reg, steer_val, val = 0;
+ drm_WARN_ON(>_to_xe(gt)->drm, !reg.mcr);
+
lockdep_assert_held(>->mcr_lock);
if (GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270) {
@@ -494,12 +498,14 @@ static u32 rw_with_mcr_steering(struct xe_gt *gt, i915_mcr_reg_t reg, u8 rw_flag
*
* Returns the value from a non-terminated instance of @reg.
*/
-u32 xe_gt_mcr_unicast_read_any(struct xe_gt *gt, i915_mcr_reg_t reg)
+u32 xe_gt_mcr_unicast_read_any(struct xe_gt *gt, xe_reg_t reg)
{
u8 group, instance;
u32 val;
bool steer;
+ drm_WARN_ON(>_to_xe(gt)->drm, !reg.mcr);
+
steer = xe_gt_mcr_get_nonterminated_steering(gt, reg, &group, &instance);
if (steer) {
@@ -525,11 +531,13 @@ u32 xe_gt_mcr_unicast_read_any(struct xe_gt *gt, i915_mcr_reg_t reg)
* group/instance.
*/
u32 xe_gt_mcr_unicast_read(struct xe_gt *gt,
- i915_mcr_reg_t reg,
+ xe_reg_t reg,
int group, int instance)
{
u32 val;
+ drm_WARN_ON(>_to_xe(gt)->drm, !reg.mcr);
+
mcr_lock(gt);
val = rw_with_mcr_steering(gt, reg, MCR_OP_READ, group, instance, 0);
mcr_unlock(gt);
@@ -548,9 +556,11 @@ u32 xe_gt_mcr_unicast_read(struct xe_gt *gt,
* Write an MCR register in unicast mode after steering toward a specific
* group/instance.
*/
-void xe_gt_mcr_unicast_write(struct xe_gt *gt, i915_mcr_reg_t reg, u32 value,
+void xe_gt_mcr_unicast_write(struct xe_gt *gt, xe_reg_t reg, u32 value,
int group, int instance)
{
+ drm_WARN_ON(>_to_xe(gt)->drm, !reg.mcr);
+
mcr_lock(gt);
rw_with_mcr_steering(gt, reg, MCR_OP_WRITE, group, instance, value);
mcr_unlock(gt);
@@ -564,7 +574,7 @@ void xe_gt_mcr_unicast_write(struct xe_gt *gt, i915_mcr_reg_t reg, u32 value,
*
* Write an MCR register in multicast mode to update all instances.
*/
-void xe_gt_mcr_multicast_write(struct xe_gt *gt, i915_mcr_reg_t reg, u32 value)
+void xe_gt_mcr_multicast_write(struct xe_gt *gt, xe_reg_t reg, u32 value)
{
/*
* Synchronize with any unicast operations. Once we have exclusive
diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.h b/drivers/gpu/drm/xe/xe_gt_mcr.h
index 2a6cd38c8cb7..492d9519784a 100644
--- a/drivers/gpu/drm/xe/xe_gt_mcr.h
+++ b/drivers/gpu/drm/xe/xe_gt_mcr.h
@@ -15,13 +15,13 @@ void xe_gt_mcr_init(struct xe_gt *gt);
void xe_gt_mcr_set_implicit_defaults(struct xe_gt *gt);
-u32 xe_gt_mcr_unicast_read(struct xe_gt *gt, i915_mcr_reg_t reg,
+u32 xe_gt_mcr_unicast_read(struct xe_gt *gt, xe_reg_t reg,
int group, int instance);
-u32 xe_gt_mcr_unicast_read_any(struct xe_gt *gt, i915_mcr_reg_t reg);
+u32 xe_gt_mcr_unicast_read_any(struct xe_gt *gt, xe_reg_t reg);
-void xe_gt_mcr_unicast_write(struct xe_gt *gt, i915_mcr_reg_t reg, u32 value,
+void xe_gt_mcr_unicast_write(struct xe_gt *gt, xe_reg_t reg, u32 value,
int group, int instance);
-void xe_gt_mcr_multicast_write(struct xe_gt *gt, i915_mcr_reg_t reg, u32 value);
+void xe_gt_mcr_multicast_write(struct xe_gt *gt, xe_reg_t reg, u32 value);
void xe_gt_mcr_steering_dump(struct xe_gt *gt, struct drm_printer *p);
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index 13f9f220bca0..8e5f8e7c16c8 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -27,7 +27,7 @@
#define IIR(offset) _MMIO(offset + 0x8)
#define IER(offset) _MMIO(offset + 0xc)
-static void assert_iir_is_zero(struct xe_gt *gt, i915_reg_t reg)
+static void assert_iir_is_zero(struct xe_gt *gt, xe_reg_t reg)
{
u32 val = xe_mmio_read32(gt, reg.reg);
diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
index a93838e23b7b..1029b9f27988 100644
--- a/drivers/gpu/drm/xe/xe_mmio.c
+++ b/drivers/gpu/drm/xe/xe_mmio.c
@@ -397,7 +397,7 @@ int xe_mmio_init(struct xe_device *xe)
DRM_XE_MMIO_READ |\
DRM_XE_MMIO_WRITE)
-static const i915_reg_t mmio_read_whitelist[] = {
+static const xe_reg_t mmio_read_whitelist[] = {
RING_TIMESTAMP(RENDER_RING_BASE),
};
--
2.39.0
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Intel-xe] [PATCH 12/17] drm/xe: Clarify register types on PAT programming
2023-04-19 7:44 [Intel-xe] [PATCH 00/17] Cleanup registers and introduce xe_reg_t Lucas De Marchi
` (10 preceding siblings ...)
2023-04-19 7:44 ` [Intel-xe] [PATCH 11/17] drm/xe: Introduce xe_reg_t Lucas De Marchi
@ 2023-04-19 7:44 ` Lucas De Marchi
2023-04-19 7:44 ` [Intel-xe] [PATCH 13/17] drm/xe/rtp: Improve magic macros for RTP tables Lucas De Marchi
` (8 subsequent siblings)
20 siblings, 0 replies; 41+ messages in thread
From: Lucas De Marchi @ 2023-04-19 7:44 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, Matt Roper, Rodrigo Vivi
Clarify a few things related to the PAT programming, particularly on
MTL:
- The register type doesn't change depending on the GT - what
happens is that media GT writes to other set of registers that
are not MCR
- Remove "UNICAST": otherwise it's confusing why it's not using
MCR registers with the unicast function variant
Also, there isn't much reason to keep those parts as macros: promote
them to proper functions and let the compiler inline if it sees fit.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/xe_pat.c | 35 ++++++++++++++++++++---------------
1 file changed, 20 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c
index c2faf0931649..fcf6ae2c92cc 100644
--- a/drivers/gpu/drm/xe/xe_pat.c
+++ b/drivers/gpu/drm/xe/xe_pat.c
@@ -62,31 +62,36 @@ static const u32 mtl_pat_table[] = {
[4] = MTL_PAT_0_WB | MTL_3_COH_2W,
};
-#define PROGRAM_PAT_UNICAST(gt, table) do { \
- for (int i = 0; i < ARRAY_SIZE(table); i++) \
- xe_mmio_write32(gt, _PAT_INDEX(i), table[i]); \
-} while (0)
+static void program_pat(struct xe_gt *gt, const u32 table[], int n_entries)
+{
+ for (int i = 0; i < n_entries; i++)
+ xe_mmio_write32(gt, _PAT_INDEX(i), table[i]);
+}
-#define PROGRAM_PAT_MCR(gt, table) do { \
- for (int i = 0; i < ARRAY_SIZE(table); i++) \
- xe_gt_mcr_multicast_write(gt, MCR_REG(_PAT_INDEX(i)), table[i]); \
-} while (0)
+static void program_pat_mcr(struct xe_gt *gt, const u32 table[], int n_entries)
+{
+ for (int i = 0; i < n_entries; i++)
+ xe_gt_mcr_multicast_write(gt, MCR_REG(_PAT_INDEX(i)), table[i]);
+}
void xe_pat_init(struct xe_gt *gt)
{
struct xe_device *xe = gt_to_xe(gt);
if (xe->info.platform == XE_METEORLAKE) {
+ /*
+ * SAMedia register offsets are adjusted by the write methods
+ * and they target registers that are not MCR, while for normal
+ * GT they are MCR
+ */
if (xe_gt_is_media_type(gt))
- PROGRAM_PAT_UNICAST(gt, mtl_pat_table);
+ program_pat(gt, mtl_pat_table, ARRAY_SIZE(mtl_pat_table));
else
- PROGRAM_PAT_MCR(gt, mtl_pat_table);
- } else if (xe->info.platform == XE_PVC) {
- PROGRAM_PAT_MCR(gt, pvc_pat_table);
- } else if (xe->info.platform == XE_DG2) {
- PROGRAM_PAT_MCR(gt, pvc_pat_table);
+ program_pat_mcr(gt, mtl_pat_table, ARRAY_SIZE(mtl_pat_table));
+ } else if (xe->info.platform == XE_PVC || xe->info.platform == XE_DG2) {
+ program_pat_mcr(gt, pvc_pat_table, ARRAY_SIZE(pvc_pat_table));
} else if (GRAPHICS_VERx100(xe) <= 1210) {
- PROGRAM_PAT_UNICAST(gt, tgl_pat_table);
+ program_pat(gt, tgl_pat_table, ARRAY_SIZE(tgl_pat_table));
} else {
/*
* Going forward we expect to need new PAT settings for most
--
2.39.0
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Intel-xe] [PATCH 13/17] drm/xe/rtp: Improve magic macros for RTP tables
2023-04-19 7:44 [Intel-xe] [PATCH 00/17] Cleanup registers and introduce xe_reg_t Lucas De Marchi
` (11 preceding siblings ...)
2023-04-19 7:44 ` [Intel-xe] [PATCH 12/17] drm/xe: Clarify register types on PAT programming Lucas De Marchi
@ 2023-04-19 7:44 ` Lucas De Marchi
2023-04-19 7:44 ` [Intel-xe] [PATCH 14/17] drm/xe: Add XE_REG/XE_REG_MCR Lucas De Marchi
` (7 subsequent siblings)
20 siblings, 0 replies; 41+ messages in thread
From: Lucas De Marchi @ 2023-04-19 7:44 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, Matt Roper, Rodrigo Vivi
The macros for writing the rtp tables have some downsides:
1) They are fragile, and when making a typo it's hard to know
where it's failing for someone not used to them
2) They polute the global scope. The CONCAT/COUNT_ARGS/etc only
work because they are defined exactly the same as the ones in
kernel.h.
3) They are not compatible with rules/actions with registers
passing additional options
This new implementation fixes (2) and (3).
For (2), prefix everything with "_XE", so there is less chance of
clashes. Also, the maximum number of rules and actions is 4, so there is
no need to make the helper macros go until 12: reduce that to 5, so if
more arguments is passed, the compiler gives an error that there is not
definition with _5 suffix.
For (3), change the implementation to concentrate on "pasting a prefix
to each argument" rather than the more general "call any macro for each
argument". Hopefully this will avoid trying to extending this infra and
making it more complex. The new changes to how the arguments are
constructed using tuples will allow extending the interface where it's
needed: passing additional register fields to allow creating our own
xe_reg_t.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/xe_rtp.h | 68 ++++++++++++++++++-------------------
1 file changed, 33 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_rtp.h b/drivers/gpu/drm/xe/xe_rtp.h
index a3be7c77753a..53650f09efe9 100644
--- a/drivers/gpu/drm/xe/xe_rtp.h
+++ b/drivers/gpu/drm/xe/xe_rtp.h
@@ -22,43 +22,42 @@ struct xe_reg_sr;
/*
* Helper macros - not to be used outside this header.
*/
-/* This counts to 12. Any more, it will return 13th argument. */
-#define __COUNT_ARGS(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, _n, X...) _n
-#define COUNT_ARGS(X...) __COUNT_ARGS(, ##X, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0)
+#define _XE_ESC(...) __VA_ARGS__
+#define _XE_COUNT_ARGS(...) _XE_ESC(__XE_COUNT_ARGS(__VA_ARGS__,5,4,3,2,1,))
+#define __XE_COUNT_ARGS(_,_5,_4,_3,_2,X_,...) X_
-#define __CONCAT(a, b) a ## b
-#define CONCATENATE(a, b) __CONCAT(a, b)
+#define _XE_CONCAT(a, b) __XE_CONCAT(a, b)
+#define __XE_CONCAT(a, b) a ## b
-#define __CALL_FOR_EACH_1(MACRO_, x, ...) MACRO_(x)
-#define __CALL_FOR_EACH_2(MACRO_, x, ...) \
- MACRO_(x) __CALL_FOR_EACH_1(MACRO_, ##__VA_ARGS__)
-#define __CALL_FOR_EACH_3(MACRO_, x, ...) \
- MACRO_(x) __CALL_FOR_EACH_2(MACRO_, ##__VA_ARGS__)
-#define __CALL_FOR_EACH_4(MACRO_, x, ...) \
- MACRO_(x) __CALL_FOR_EACH_3(MACRO_, ##__VA_ARGS__)
+#define _XE_FIRST(...) _XE_ESC(__XE_FIRST(__VA_ARGS__,))
+#define __XE_FIRST(x_,...) x_
+#define _XE_TUPLE_TAIL(...) _XE_ESC(__XE_TUPLE_TAIL(__VA_ARGS__))
+#define __XE_TUPLE_TAIL(x_,...) (__VA_ARGS__)
-#define _CALL_FOR_EACH(NARGS_, MACRO_, x, ...) \
- CONCATENATE(__CALL_FOR_EACH_, NARGS_)(MACRO_, x, ##__VA_ARGS__)
-#define CALL_FOR_EACH(MACRO_, x, ...) \
- _CALL_FOR_EACH(COUNT_ARGS(x, ##__VA_ARGS__), MACRO_, x, ##__VA_ARGS__)
+#define __XE_PASTE_SEP_COMMA ,
+#define __XE_PASTE_SEP_BITWISE_OR |
+#define __XE_PASTE(prefix_, sep_, args_) _XE_ESC(_XE_CONCAT(__XE_PASTE_,_XE_COUNT_ARGS args_)(prefix_, sep_, args_))
+#define __XE_PASTE_1(prefix_, sep_, args_) prefix_ args_
+#define __XE_PASTE_2(prefix_, sep_, args_) prefix_(_XE_FIRST args_) __XE_PASTE_SEP_ ## sep_ __XE_PASTE_1(prefix_, sep_, _XE_TUPLE_TAIL args_)
+#define __XE_PASTE_3(prefix_, sep_, args_) prefix_(_XE_FIRST args_) __XE_PASTE_SEP_ ## sep_ __XE_PASTE_2(prefix_, sep_, _XE_TUPLE_TAIL args_)
+#define __XE_PASTE_4(prefix_, sep_, args_) prefix_(_XE_FIRST args_) __XE_PASTE_SEP_ ## sep_ __XE_PASTE_3(prefix_, sep_, _XE_TUPLE_TAIL args_)
-#define _XE_RTP_REG(x_) (x_), XE_RTP_REG_REGULAR
-#define _XE_RTP_MCR_REG(x_) (x_), XE_RTP_REG_MCR
+#define _XE_RTP_REG(x_) (x_), XE_RTP_REG_REGULAR
+#define _XE_RTP_MCR_REG(x_) (x_), XE_RTP_REG_MCR
/*
* Helper macros for concatenating prefix - do not use them directly outside
* this header
*/
-#define __ADD_XE_RTP_ENTRY_FLAG_PREFIX(x) CONCATENATE(XE_RTP_ENTRY_FLAG_, x) |
-#define __ADD_XE_RTP_ACTION_FLAG_PREFIX(x) CONCATENATE(XE_RTP_ACTION_FLAG_, x) |
-#define __ADD_XE_RTP_RULE_PREFIX(x) CONCATENATE(XE_RTP_RULE_, x) ,
-#define __ADD_XE_RTP_ACTION_PREFIX(x) CONCATENATE(XE_RTP_ACTION_, x) ,
+#define __XE_PASTE_XE_RTP_ENTRY_FLAG_(x_) _XE_CONCAT(XE_RTP_ENTRY_FLAG_, x_)
+#define __XE_PASTE_XE_RTP_ACTION_FLAG_(x_) _XE_CONCAT(XE_RTP_ACTION_FLAG_, x_)
+#define __XE_PASTE_XE_RTP_ACTION_(x_) _XE_CONCAT(XE_RTP_ACTION_, x_)
+#define __XE_PASTE_XE_RTP_RULE_(x_) _XE_CONCAT(XE_RTP_RULE_, x_)
/*
* Macros to encode rules to match against platform, IP version, stepping, etc.
* Shouldn't be used directly - see XE_RTP_RULES()
*/
-
#define _XE_RTP_RULE_PLATFORM(plat__) \
{ .match_type = XE_RTP_MATCH_PLATFORM, .platform = plat__ }
@@ -315,8 +314,8 @@ struct xe_reg_sr;
* ...
* };
*/
-#define XE_RTP_ENTRY_FLAG(f1_, ...) \
- .flags = (CALL_FOR_EACH(__ADD_XE_RTP_ENTRY_FLAG_PREFIX, f1_, ##__VA_ARGS__) 0)
+#define XE_RTP_ENTRY_FLAG(...) \
+ .flags = (__XE_PASTE(__XE_PASTE_XE_RTP_ENTRY_FLAG_, BITWISE_OR, (__VA_ARGS__)))
/**
* XE_RTP_ACTION_FLAG - Helper to add multiple flags to a struct xe_rtp_action
@@ -338,8 +337,8 @@ struct xe_reg_sr;
* ...
* };
*/
-#define XE_RTP_ACTION_FLAG(f1_, ...) \
- .flags = (CALL_FOR_EACH(__ADD_XE_RTP_ACTION_FLAG_PREFIX, f1_, ##__VA_ARGS__) 0)
+#define XE_RTP_ACTION_FLAG(...) \
+ .flags = (__XE_PASTE(__XE_PASTE_XE_RTP_ACTION_FLAG_, BITWISE_OR, (__VA_ARGS__)))
/**
* XE_RTP_RULES - Helper to set multiple rules to a struct xe_rtp_entry entry
@@ -361,16 +360,15 @@ struct xe_reg_sr;
* ...
* };
*/
-#define XE_RTP_RULES(r1, ...) \
- .n_rules = COUNT_ARGS(r1, ##__VA_ARGS__), \
+#define XE_RTP_RULES(...) \
+ .n_rules = _XE_COUNT_ARGS(__VA_ARGS__), \
.rules = (const struct xe_rtp_rule[]) { \
- CALL_FOR_EACH(__ADD_XE_RTP_RULE_PREFIX, r1, ##__VA_ARGS__) \
+ __XE_PASTE(__XE_PASTE_XE_RTP_RULE_, COMMA, (__VA_ARGS__)) \
}
/**
* XE_RTP_ACTIONS - Helper to set multiple actions to a struct xe_rtp_entry
- * @a1: Action to take. Last part of XE_RTP_ACTION_*
- * @...: Additional rules, defined like @r1
+ * @...: Actions to be taken
*
* At least one rule is needed and up to 4 are supported. Multiple rules are
* AND'ed together, i.e. all the rules must evaluate to true for the entry to
@@ -388,10 +386,10 @@ struct xe_reg_sr;
* ...
* };
*/
-#define XE_RTP_ACTIONS(a1, ...) \
- .n_actions = COUNT_ARGS(a1, ##__VA_ARGS__), \
+#define XE_RTP_ACTIONS(...) \
+ .n_actions = _XE_COUNT_ARGS(__VA_ARGS__), \
.actions = (const struct xe_rtp_action[]) { \
- CALL_FOR_EACH(__ADD_XE_RTP_ACTION_PREFIX, a1, ##__VA_ARGS__) \
+ __XE_PASTE(__XE_PASTE_XE_RTP_ACTION_, COMMA, (__VA_ARGS__)) \
}
void xe_rtp_process(const struct xe_rtp_entry *entries, struct xe_reg_sr *sr,
--
2.39.0
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Intel-xe] [PATCH 14/17] drm/xe: Add XE_REG/XE_REG_MCR
2023-04-19 7:44 [Intel-xe] [PATCH 00/17] Cleanup registers and introduce xe_reg_t Lucas De Marchi
` (12 preceding siblings ...)
2023-04-19 7:44 ` [Intel-xe] [PATCH 13/17] drm/xe/rtp: Improve magic macros for RTP tables Lucas De Marchi
@ 2023-04-19 7:44 ` Lucas De Marchi
2023-04-19 7:44 ` [Intel-xe] [PATCH 15/17] drm/xe: Annotate masked registers used by RTP Lucas De Marchi
` (6 subsequent siblings)
20 siblings, 0 replies; 41+ messages in thread
From: Lucas De Marchi @ 2023-04-19 7:44 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, Matt Roper, Rodrigo Vivi
These should replace the _MMIO() and MCR_REG() from i915, with the goal
of being more extensible, allowing to pass the additional fields for
xe_reg_t. Add the new declarations and replace all uses of _MMIO() and
MCR_REG() in xe.
Since the RTP, reg-save-restore and WA infra are not ready to use the
new type, just undef the macro like was done for the i915 types
previously. That conversion will come later.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/regs/xe_engine_regs.h | 72 +++----
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 237 ++++++++++++-----------
drivers/gpu/drm/xe/regs/xe_guc_regs.h | 64 +++---
drivers/gpu/drm/xe/regs/xe_reg_defs.h | 53 ++++-
drivers/gpu/drm/xe/regs/xe_regs.h | 28 +--
drivers/gpu/drm/xe/tests/xe_rtp_test.c | 20 +-
drivers/gpu/drm/xe/xe_ggtt.c | 6 +-
drivers/gpu/drm/xe/xe_guc.c | 6 +-
drivers/gpu/drm/xe/xe_guc_pc.c | 14 +-
drivers/gpu/drm/xe/xe_irq.c | 6 +-
drivers/gpu/drm/xe/xe_mmio.c | 2 +-
drivers/gpu/drm/xe/xe_mocs.c | 4 +-
drivers/gpu/drm/xe/xe_pat.c | 2 +-
drivers/gpu/drm/xe/xe_pcode_api.h | 6 +-
drivers/gpu/drm/xe/xe_reg_sr.c | 4 +-
drivers/gpu/drm/xe/xe_reg_whitelist.c | 12 +-
drivers/gpu/drm/xe/xe_rtp.h | 10 +-
drivers/gpu/drm/xe/xe_tuning.c | 8 +-
drivers/gpu/drm/xe/xe_wa.c | 8 +-
19 files changed, 304 insertions(+), 258 deletions(-)
diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
index 938055f75492..c13aac8f900c 100644
--- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
@@ -10,63 +10,63 @@
#include "regs/xe_reg_defs.h"
-#define RING_TAIL(base) _MMIO((base) + 0x30)
+#define RING_TAIL(base) XE_REG((base) + 0x30)
-#define RING_HEAD(base) _MMIO((base) + 0x34)
+#define RING_HEAD(base) XE_REG((base) + 0x34)
#define HEAD_ADDR 0x001FFFFC
-#define RING_START(base) _MMIO((base) + 0x38)
+#define RING_START(base) XE_REG((base) + 0x38)
-#define RING_CTL(base) _MMIO((base) + 0x3c)
+#define RING_CTL(base) XE_REG((base) + 0x3c)
#define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */
#define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */
-#define RING_PSMI_CTL(base) _MMIO((base) + 0x50)
+#define RING_PSMI_CTL(base) XE_REG((base) + 0x50)
#define RC_SEMA_IDLE_MSG_DISABLE REG_BIT(12)
#define WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
-#define RING_ACTHD_UDW(base) _MMIO((base) + 0x5c)
-#define RING_DMA_FADD_UDW(base) _MMIO((base) + 0x60)
-#define RING_IPEIR(base) _MMIO((base) + 0x64)
-#define RING_IPEHR(base) _MMIO((base) + 0x68)
-#define RING_ACTHD(base) _MMIO((base) + 0x74)
-#define RING_DMA_FADD(base) _MMIO((base) + 0x78)
-#define RING_HWS_PGA(base) _MMIO((base) + 0x80)
-#define IPEIR(base) _MMIO((base) + 0x88)
-#define IPEHR(base) _MMIO((base) + 0x8c)
-#define RING_HWSTAM(base) _MMIO((base) + 0x98)
-#define RING_MI_MODE(base) _MMIO((base) + 0x9c)
-#define RING_NOPID(base) _MMIO((base) + 0x94)
-
-#define RING_IMR(base) _MMIO((base) + 0xa8)
+#define RING_ACTHD_UDW(base) XE_REG((base) + 0x5c)
+#define RING_DMA_FADD_UDW(base) XE_REG((base) + 0x60)
+#define RING_IPEIR(base) XE_REG((base) + 0x64)
+#define RING_IPEHR(base) XE_REG((base) + 0x68)
+#define RING_ACTHD(base) XE_REG((base) + 0x74)
+#define RING_DMA_FADD(base) XE_REG((base) + 0x78)
+#define RING_HWS_PGA(base) XE_REG((base) + 0x80)
+#define IPEIR(base) XE_REG((base) + 0x88)
+#define IPEHR(base) XE_REG((base) + 0x8c)
+#define RING_HWSTAM(base) XE_REG((base) + 0x98)
+#define RING_MI_MODE(base) XE_REG((base) + 0x9c)
+#define RING_NOPID(base) XE_REG((base) + 0x94)
+
+#define RING_IMR(base) XE_REG((base) + 0xa8)
#define RING_MAX_NONPRIV_SLOTS 12
-#define RING_EIR(base) _MMIO((base) + 0xb0)
-#define RING_EMR(base) _MMIO((base) + 0xb4)
-#define RING_ESR(base) _MMIO((base) + 0xb8)
-#define RING_BBADDR(base) _MMIO((base) + 0x140)
-#define RING_BBADDR_UDW(base) _MMIO((base) + 0x168)
-#define RING_EXECLIST_STATUS_LO(base) _MMIO((base) + 0x234)
-#define RING_EXECLIST_STATUS_HI(base) _MMIO((base) + 0x234 + 4)
+#define RING_EIR(base) XE_REG((base) + 0xb0)
+#define RING_EMR(base) XE_REG((base) + 0xb4)
+#define RING_ESR(base) XE_REG((base) + 0xb8)
+#define RING_BBADDR(base) XE_REG((base) + 0x140)
+#define RING_BBADDR_UDW(base) XE_REG((base) + 0x168)
+#define RING_EXECLIST_STATUS_LO(base) XE_REG((base) + 0x234)
+#define RING_EXECLIST_STATUS_HI(base) XE_REG((base) + 0x234 + 4)
-#define RING_CONTEXT_CONTROL(base) _MMIO((base) + 0x244)
+#define RING_CONTEXT_CONTROL(base) XE_REG((base) + 0x244)
#define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH REG_BIT(3)
#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT REG_BIT(0)
-#define RING_MODE(base) _MMIO((base) + 0x29c)
+#define RING_MODE(base) XE_REG((base) + 0x29c)
#define GFX_DISABLE_LEGACY_MODE REG_BIT(3)
-#define RING_TIMESTAMP(base) _MMIO((base) + 0x358)
+#define RING_TIMESTAMP(base) XE_REG((base) + 0x358)
-#define RING_TIMESTAMP_UDW(base) _MMIO((base) + 0x358 + 4)
+#define RING_TIMESTAMP_UDW(base) XE_REG((base) + 0x358 + 4)
#define RING_VALID_MASK 0x00000001
#define RING_VALID 0x00000001
#define STOP_RING REG_BIT(8)
#define TAIL_ADDR 0x001FFFF8
-#define RING_CTX_TIMESTAMP(base) _MMIO((base) + 0x3a8)
+#define RING_CTX_TIMESTAMP(base) XE_REG((base) + 0x3a8)
-#define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4d0) + (i) * 4)
+#define RING_FORCE_TO_NONPRIV(base, i) XE_REG(((base) + 0x4d0) + (i) * 4)
#define RING_FORCE_TO_NONPRIV_DENY REG_BIT(30)
#define RING_FORCE_TO_NONPRIV_ACCESS_MASK REG_GENMASK(29, 28)
#define RING_FORCE_TO_NONPRIV_ACCESS_RW REG_FIELD_PREP(RING_FORCE_TO_NONPRIV_ACCESS_MASK, 0)
@@ -84,15 +84,15 @@
RING_FORCE_TO_NONPRIV_DENY)
#define RING_MAX_NONPRIV_SLOTS 12
-#define RING_EXECLIST_SQ_CONTENTS(base) _MMIO((base) + 0x510)
+#define RING_EXECLIST_SQ_CONTENTS(base) XE_REG((base) + 0x510)
-#define RING_EXECLIST_CONTROL(base) _MMIO((base) + 0x550)
+#define RING_EXECLIST_CONTROL(base) XE_REG((base) + 0x550)
#define EL_CTRL_LOAD REG_BIT(0)
-#define VDBOX_CGCTL3F10(base) _MMIO((base) + 0x3f10)
+#define VDBOX_CGCTL3F10(base) XE_REG((base) + 0x3f10)
#define IECPUNIT_CLKGATE_DIS REG_BIT(22)
-#define VDBOX_CGCTL3F18(base) _MMIO((base) + 0x3f18)
+#define VDBOX_CGCTL3F18(base) XE_REG((base) + 0x3f18)
#define ALNUNIT_CLKGATE_DIS REG_BIT(13)
#endif
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 4076d903b20e..64ab2255a406 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -9,7 +9,7 @@
#include "regs/xe_reg_defs.h"
/* RPM unit config (Gen8+) */
-#define RPM_CONFIG0 _MMIO(0xd00)
+#define RPM_CONFIG0 XE_REG(0xd00)
#define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK REG_GENMASK(5, 4)
#define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 0
#define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 1
@@ -17,25 +17,26 @@
#define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ 3
#define RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK REG_GENMASK(2, 1)
-#define FORCEWAKE_ACK_MEDIA_VDBOX(n) _MMIO(0xd50 + (n) * 4)
-#define FORCEWAKE_ACK_MEDIA_VEBOX(n) _MMIO(0xd70 + (n) * 4)
-#define FORCEWAKE_ACK_RENDER _MMIO(0xd84)
+#define FORCEWAKE_ACK_MEDIA_VDBOX(n) XE_REG(0xd50 + (n) * 4)
+#define FORCEWAKE_ACK_MEDIA_VEBOX(n) XE_REG(0xd70 + (n) * 4)
+#define FORCEWAKE_ACK_RENDER XE_REG(0xd84)
-#define GMD_ID _MMIO(0xd8c)
+#define GMD_ID XE_REG(0xd8c)
#define GMD_ID_ARCH_MASK REG_GENMASK(31, 22)
#define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14)
#define GMD_ID_STEP REG_GENMASK(5, 0)
-#define FORCEWAKE_ACK_GT_MTL _MMIO(0xdfc)
+#define FORCEWAKE_ACK_GT_MTL XE_REG(0xdfc)
-#define LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
+/* L3 Cache Control */
+#define LNCFCMOCS(i) XE_REG(0xb020 + (i) * 4)
#define LNCFCMOCS_REG_COUNT 32
-#define MCFG_MCR_SELECTOR _MMIO(0xfd0)
-#define MTL_MCR_SELECTOR _MMIO(0xfd4)
-#define SF_MCR_SELECTOR _MMIO(0xfd8)
-#define MCR_SELECTOR _MMIO(0xfdc)
-#define GAM_MCR_SELECTOR _MMIO(0xfe0)
+#define MCFG_MCR_SELECTOR XE_REG(0xfd0)
+#define MTL_MCR_SELECTOR XE_REG(0xfd4)
+#define SF_MCR_SELECTOR XE_REG(0xfd8)
+#define MCR_SELECTOR XE_REG(0xfdc)
+#define GAM_MCR_SELECTOR XE_REG(0xfe0)
#define MCR_MULTICAST REG_BIT(31)
#define MCR_SLICE_MASK REG_GENMASK(30, 27)
#define MCR_SLICE(slice) REG_FIELD_PREP(MCR_SLICE_MASK, slice)
@@ -44,19 +45,19 @@
#define MTL_MCR_GROUPID REG_GENMASK(11, 8)
#define MTL_MCR_INSTANCEID REG_GENMASK(3, 0)
-#define FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0)
+#define FF_SLICE_CS_CHICKEN1 XE_REG(0x20e0)
#define FFSC_PERCTX_PREEMPT_CTRL REG_BIT(14)
-#define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4)
+#define FF_SLICE_CS_CHICKEN2 XE_REG(0x20e4)
#define PERF_FIX_BALANCING_CFE_DISABLE REG_BIT(15)
-#define CS_DEBUG_MODE1 _MMIO(0x20ec)
+#define CS_DEBUG_MODE1 XE_REG(0x20ec)
#define FF_DOP_CLOCK_GATE_DISABLE REG_BIT(1)
#define REPLAY_MODE_GRANULARITY REG_BIT(0)
-#define PS_INVOCATION_COUNT _MMIO(0x2348)
+#define PS_INVOCATION_COUNT XE_REG(0x2348)
-#define CS_CHICKEN1 _MMIO(0x2580)
+#define CS_CHICKEN1 XE_REG(0x2580)
#define PREEMPT_GPGPU_LEVEL(hi, lo) (((hi) << 2) | ((lo) << 1))
#define PREEMPT_GPGPU_MID_THREAD_LEVEL PREEMPT_GPGPU_LEVEL(0, 0)
#define PREEMPT_GPGPU_THREAD_GROUP_LEVEL PREEMPT_GPGPU_LEVEL(0, 1)
@@ -64,70 +65,70 @@
#define PREEMPT_GPGPU_LEVEL_MASK PREEMPT_GPGPU_LEVEL(1, 1)
#define PREEMPT_3D_OBJECT_LEVEL REG_BIT(0)
-#define GLOBAL_MOCS(i) _MMIO(0x4000 + (i) * 4) /* Global MOCS regs */
-#define GFX_CCS_AUX_NV _MMIO(0x4208)
+#define GLOBAL_MOCS(i) XE_REG(0x4000 + (i) * 4) /* Global MOCS regs */
+#define GFX_CCS_AUX_NV XE_REG(0x4208)
-#define VD0_AUX_NV _MMIO(0x4218)
-#define VE0_AUX_NV _MMIO(0x4238)
+#define VD0_AUX_NV XE_REG(0x4218)
+#define VE0_AUX_NV XE_REG(0x4238)
-#define VE1_AUX_NV _MMIO(0x42b8)
+#define VE1_AUX_NV XE_REG(0x42b8)
#define AUX_INV REG_BIT(0)
-#define XEHP_TILE0_ADDR_RANGE MCR_REG(0x4900)
-#define XEHP_FLAT_CCS_BASE_ADDR MCR_REG(0x4910)
+#define XEHP_TILE0_ADDR_RANGE XE_REG_MCR(0x4900)
+#define XEHP_FLAT_CCS_BASE_ADDR XE_REG_MCR(0x4910)
-#define CHICKEN_RASTER_1 MCR_REG(0x6204)
+#define CHICKEN_RASTER_1 XE_REG_MCR(0x6204)
#define DIS_SF_ROUND_NEAREST_EVEN REG_BIT(8)
-#define CHICKEN_RASTER_2 MCR_REG(0x6208)
+#define CHICKEN_RASTER_2 XE_REG_MCR(0x6208)
#define TBIMR_FAST_CLIP REG_BIT(5)
-#define VFLSKPD MCR_REG(0x62a8)
+#define VFLSKPD XE_REG_MCR(0x62a8)
#define DIS_OVER_FETCH_CACHE REG_BIT(1)
#define DIS_MULT_MISS_RD_SQUASH REG_BIT(0)
-#define FF_MODE2 _MMIO(0x6604)
-#define XEHP_FF_MODE2 MCR_REG(0x6604)
+#define FF_MODE2 XE_REG(0x6604)
+#define XEHP_FF_MODE2 XE_REG_MCR(0x6604)
#define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24)
#define FF_MODE2_GS_TIMER_224 REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224)
#define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16)
#define FF_MODE2_TDS_TIMER_128 REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
-#define CACHE_MODE_1 _MMIO(0x7004)
+#define CACHE_MODE_1 XE_REG(0x7004)
#define MSAA_OPTIMIZATION_REDUC_DISABLE REG_BIT(11)
-#define XEHP_PSS_MODE2 MCR_REG(0x703c)
+#define XEHP_PSS_MODE2 XE_REG_MCR(0x703c)
#define SCOREBOARD_STALL_FLUSH_CONTROL REG_BIT(5)
-#define HIZ_CHICKEN _MMIO(0x7018)
+#define HIZ_CHICKEN XE_REG(0x7018)
#define DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE REG_BIT(14)
#define HZ_DEPTH_TEST_LE_GE_OPT_DISABLE REG_BIT(13)
-#define COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
+#define COMMON_SLICE_CHICKEN1 XE_REG(0x7010)
-#define COMMON_SLICE_CHICKEN4 _MMIO(0x7300)
+#define COMMON_SLICE_CHICKEN4 XE_REG(0x7300)
#define DISABLE_TDC_LOAD_BALANCING_CALC REG_BIT(6)
-#define COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
-#define XEHP_COMMON_SLICE_CHICKEN3 MCR_REG(0x7304)
+#define COMMON_SLICE_CHICKEN3 XE_REG(0x7304)
+#define XEHP_COMMON_SLICE_CHICKEN3 XE_REG_MCR(0x7304)
#define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN REG_BIT(12)
#define XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE REG_BIT(12)
#define BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11)
#define DISABLE_CPS_AWARE_COLOR_PIPE REG_BIT(9)
-#define XEHP_SLICE_COMMON_ECO_CHICKEN1 MCR_REG(0x731c)
+#define XEHP_SLICE_COMMON_ECO_CHICKEN1 XE_REG_MCR(0x731c)
#define MSC_MSAA_REODER_BUF_BYPASS_DISABLE REG_BIT(14)
-#define VF_PREEMPTION _MMIO(0x83a4)
+#define VF_PREEMPTION XE_REG(0x83a4)
#define PREEMPTION_VERTEX_COUNT REG_GENMASK(15, 0)
-#define VFG_PREEMPTION_CHICKEN _MMIO(0x83b4)
+#define VFG_PREEMPTION_CHICKEN XE_REG(0x83b4)
#define POLYGON_TRIFAN_LINELOOP_DISABLE REG_BIT(4)
-#define XEHP_SQCM MCR_REG(0x8724)
+#define XEHP_SQCM XE_REG_MCR(0x8724)
#define EN_32B_ACCESS REG_BIT(30)
-#define MIRROR_FUSE3 _MMIO(0x9118)
+#define MIRROR_FUSE3 XE_REG(0x9118)
#define L3BANK_PAIR_COUNT 4
#define L3BANK_MASK REG_GENMASK(3, 0)
/* on Xe_HP the same fuses indicates mslices instead of L3 banks */
@@ -135,31 +136,31 @@
#define MEML3_EN_MASK REG_GENMASK(3, 0)
/* Fuse readout registers for GT */
-#define XEHP_FUSE4 _MMIO(0x9114)
+#define XEHP_FUSE4 XE_REG(0x9114)
#define GT_L3_EXC_MASK REG_GENMASK(6, 4)
-#define GT_VEBOX_VDBOX_DISABLE _MMIO(0x9140)
+#define GT_VEBOX_VDBOX_DISABLE XE_REG(0x9140)
#define GT_VEBOX_DISABLE_MASK REG_GENMASK(19, 16)
#define GT_VDBOX_DISABLE_MASK REG_GENMASK(7, 0)
-#define XELP_EU_ENABLE _MMIO(0x9134) /* "_DISABLE" on Xe_LP */
+#define XELP_EU_ENABLE XE_REG(0x9134) /* "_DISABLE" on Xe_LP */
#define XELP_EU_MASK REG_GENMASK(7, 0)
-#define XELP_GT_GEOMETRY_DSS_ENABLE _MMIO(0x913c)
-#define XEHP_GT_COMPUTE_DSS_ENABLE _MMIO(0x9144)
-#define XEHPC_GT_COMPUTE_DSS_ENABLE_EXT _MMIO(0x9148)
+#define XELP_GT_GEOMETRY_DSS_ENABLE XE_REG(0x913c)
+#define XEHP_GT_COMPUTE_DSS_ENABLE XE_REG(0x9144)
+#define XEHPC_GT_COMPUTE_DSS_ENABLE_EXT XE_REG(0x9148)
-#define GDRST _MMIO(0x941c)
+#define GDRST XE_REG(0x941c)
#define GRDOM_GUC REG_BIT(3)
#define GRDOM_FULL REG_BIT(0)
-#define MISCCPCTL _MMIO(0x9424)
+#define MISCCPCTL XE_REG(0x9424)
#define DOP_CLOCK_GATE_RENDER_ENABLE REG_BIT(1)
#define DOP_CLOCK_GATE_ENABLE REG_BIT((0)
-#define UNSLCGCTL9430 _MMIO(0x9430)
+#define UNSLCGCTL9430 XE_REG(0x9430)
#define MSQDUNIT_CLKGATE_DIS REG_BIT(3)
-#define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434)
+#define UNSLICE_UNIT_LEVEL_CLKGATE XE_REG(0x9434)
#define VFUNIT_CLKGATE_DIS REG_BIT(20)
#define TSGUNIT_CLKGATE_DIS REG_BIT(17) /* XEHPSDV */
#define CG3DDISCFEG_CLKGATE_DIS REG_BIT(17) /* DG2 */
@@ -167,7 +168,7 @@
#define HSUNIT_CLKGATE_DIS REG_BIT(8)
#define VSUNIT_CLKGATE_DIS REG_BIT(3)
-#define UNSLCGCTL9440 _MMIO(0x9440)
+#define UNSLCGCTL9440 XE_REG(0x9440)
#define GAMTLBOACS_CLKGATE_DIS REG_BIT(28)
#define GAMTLBVDBOX5_CLKGATE_DIS REG_BIT(27)
#define GAMTLBVDBOX6_CLKGATE_DIS REG_BIT(26)
@@ -181,7 +182,7 @@
#define GAMTLBBLT_CLKGATE_DIS REG_BIT(14)
#define GAMTLBVDBOX1_CLKGATE_DIS REG_BIT(6)
-#define UNSLCGCTL9444 _MMIO(0x9444)
+#define UNSLCGCTL9444 XE_REG(0x9444)
#define GAMTLBGFXA0_CLKGATE_DIS REG_BIT(30)
#define GAMTLBGFXA1_CLKGATE_DIS REG_BIT(29)
#define GAMTLBCOMPA0_CLKGATE_DIS REG_BIT(28)
@@ -199,7 +200,7 @@
#define GAMTLBVEBOX0_CLKGATE_DIS REG_BIT(16)
#define LTCDD_CLKGATE_DIS REG_BIT(10)
-#define XEHP_SLICE_UNIT_LEVEL_CLKGATE MCR_REG(0x94d4)
+#define XEHP_SLICE_UNIT_LEVEL_CLKGATE XE_REG_MCR(0x94d4)
#define SARBUNIT_CLKGATE_DIS REG_BIT(5)
#define RCCUNIT_CLKGATE_DIS REG_BIT(7)
#define MSCUNIT_CLKGATE_DIS REG_BIT(10)
@@ -207,88 +208,88 @@
#define L3_CLKGATE_DIS REG_BIT(16)
#define L3_CR2X_CLKGATE_DIS REG_BIT(17)
-#define UNSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x94e4)
+#define UNSLICE_UNIT_LEVEL_CLKGATE2 XE_REG(0x94e4)
#define VSUNIT_CLKGATE_DIS_TGL REG_BIT(19)
#define PSDUNIT_CLKGATE_DIS REG_BIT(5)
-#define SUBSLICE_UNIT_LEVEL_CLKGATE MCR_REG(0x9524)
+#define SUBSLICE_UNIT_LEVEL_CLKGATE XE_REG_MCR(0x9524)
#define DSS_ROUTER_CLKGATE_DIS REG_BIT(28)
#define GWUNIT_CLKGATE_DIS REG_BIT(16)
-#define SUBSLICE_UNIT_LEVEL_CLKGATE2 MCR_REG(0x9528)
+#define SUBSLICE_UNIT_LEVEL_CLKGATE2 XE_REG_MCR(0x9528)
#define CPSSUNIT_CLKGATE_DIS REG_BIT(9)
-#define SSMCGCTL9530 MCR_REG(0x9530)
+#define SSMCGCTL9530 XE_REG_MCR(0x9530)
#define RTFUNIT_CLKGATE_DIS REG_BIT(18)
-#define DFR_RATIO_EN_AND_CHICKEN MCR_REG(0x9550)
+#define DFR_RATIO_EN_AND_CHICKEN XE_REG_MCR(0x9550)
#define DFR_DISABLE REG_BIT(9)
-#define RPNSWREQ _MMIO(0xa008)
+#define RPNSWREQ XE_REG(0xa008)
#define REQ_RATIO_MASK REG_GENMASK(31, 23)
-#define RC_CONTROL _MMIO(0xa090)
-#define RC_STATE _MMIO(0xa094)
+#define RC_CONTROL XE_REG(0xa090)
+#define RC_STATE XE_REG(0xa094)
-#define PMINTRMSK _MMIO(0xa168)
+#define PMINTRMSK XE_REG(0xa168)
#define PMINTR_DISABLE_REDIRECT_TO_GUC REG_BIT(31)
#define ARAT_EXPIRED_INTRMSK REG_BIT(9)
-#define FORCEWAKE_GT _MMIO(0xa188)
+#define FORCEWAKE_GT XE_REG(0xa188)
-#define PG_ENABLE _MMIO(0xa210)
+#define PG_ENABLE XE_REG(0xa210)
-#define CTC_MODE _MMIO(0xa26c)
+#define CTC_MODE XE_REG(0xa26c)
#define CTC_SHIFT_PARAMETER_MASK REG_GENMASK(2, 1)
#define CTC_SOURCE_PARAMETER_MASK REG_BIT(0)
#define CTC_SOURCE_CRYSTAL_CLOCK 0
#define CTC_SOURCE_DIVIDE_LOGIC 1
-#define FORCEWAKE_RENDER _MMIO(0xa278)
-#define FORCEWAKE_MEDIA_VDBOX(n) _MMIO(0xa540 + (n) * 4)
-#define FORCEWAKE_MEDIA_VEBOX(n) _MMIO(0xa560 + (n) * 4)
+#define FORCEWAKE_RENDER XE_REG(0xa278)
+#define FORCEWAKE_MEDIA_VDBOX(n) XE_REG(0xa540 + (n) * 4)
+#define FORCEWAKE_MEDIA_VEBOX(n) XE_REG(0xa560 + (n) * 4)
-#define XEHPC_LNCFMISCCFGREG0 MCR_REG(0xb01c)
+#define XEHPC_LNCFMISCCFGREG0 XE_REG_MCR(0xb01c)
#define XEHPC_OVRLSCCC REG_BIT(0)
-#define XEHP_L3NODEARBCFG MCR_REG(0xb0b4)
+#define XEHP_L3NODEARBCFG XE_REG_MCR(0xb0b4)
#define XEHP_LNESPARE REG_BIT(19)
-#define XEHP_L3SQCREG5 MCR_REG(0xb158)
+#define XEHP_L3SQCREG5 XE_REG_MCR(0xb158)
#define L3_PWM_TIMER_INIT_VAL_MASK REG_GENMASK(9, 0)
-#define XEHP_L3SCQREG7 MCR_REG(0xb188)
+#define XEHP_L3SCQREG7 XE_REG_MCR(0xb188)
#define BLEND_FILL_CACHING_OPT_DIS REG_BIT(3)
-#define XEHP_MERT_MOD_CTRL MCR_REG(0xcf28)
-#define RENDER_MOD_CTRL MCR_REG(0xcf2c)
-#define COMP_MOD_CTRL MCR_REG(0xcf30)
-#define XEHP_VDBX_MOD_CTRL MCR_REG(0xcf34)
-#define XEHP_VEBX_MOD_CTRL MCR_REG(0xcf38)
+#define XEHP_MERT_MOD_CTRL XE_REG_MCR(0xcf28)
+#define RENDER_MOD_CTRL XE_REG_MCR(0xcf2c)
+#define COMP_MOD_CTRL XE_REG_MCR(0xcf30)
+#define XEHP_VDBX_MOD_CTRL XE_REG_MCR(0xcf34)
+#define XEHP_VEBX_MOD_CTRL XE_REG_MCR(0xcf38)
#define FORCE_MISS_FTLB REG_BIT(3)
-#define XEHP_GAMSTLB_CTRL MCR_REG(0xcf4c)
+#define XEHP_GAMSTLB_CTRL XE_REG_MCR(0xcf4c)
#define CONTROL_BLOCK_CLKGATE_DIS REG_BIT(12)
#define EGRESS_BLOCK_CLKGATE_DIS REG_BIT(11)
#define TAG_BLOCK_CLKGATE_DIS REG_BIT(7)
-#define XEHP_GAMCNTRL_CTRL MCR_REG(0xcf54)
+#define XEHP_GAMCNTRL_CTRL XE_REG_MCR(0xcf54)
#define INVALIDATION_BROADCAST_MODE_DIS REG_BIT(12)
#define GLOBAL_INVALIDATION_MODE REG_BIT(2)
-#define SAMPLER_MODE MCR_REG(0xe18c)
+#define SAMPLER_MODE XE_REG_MCR(0xe18c)
#define ENABLE_SMALLPL REG_BIT(15)
#define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
#define SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
-#define HALF_SLICE_CHICKEN7 MCR_REG(0xe194)
+#define HALF_SLICE_CHICKEN7 XE_REG_MCR(0xe194)
#define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15)
-#define CACHE_MODE_SS MCR_REG(0xe420)
+#define CACHE_MODE_SS XE_REG_MCR(0xe420)
#define ENABLE_EU_COUNT_FOR_TDL_FLUSH REG_BIT(10)
#define DISABLE_ECC REG_BIT(5)
#define ENABLE_PREFETCH_INTO_IC REG_BIT(3)
-#define ROW_CHICKEN4 MCR_REG(0xe48c)
+#define ROW_CHICKEN4 XE_REG_MCR(0xe48c)
#define DISABLE_GRF_CLEAR REG_BIT(13)
#define XEHP_DIS_BBL_SYSPIPE REG_BIT(11)
#define DISABLE_TDL_PUSH REG_BIT(9)
@@ -297,87 +298,87 @@
#define THREAD_EX_ARB_MODE REG_GENMASK(3, 2)
#define THREAD_EX_ARB_MODE_RR_AFTER_DEP REG_FIELD_PREP(THREAD_EX_ARB_MODE, 0x2)
-#define ROW_CHICKEN MCR_REG(0xe4f0)
+#define ROW_CHICKEN XE_REG_MCR(0xe4f0)
#define UGM_BACKUP_MODE REG_BIT(13)
#define MDQ_ARBITRATION_MODE REG_BIT(12)
-#define ROW_CHICKEN2 MCR_REG(0xe4f4)
+#define ROW_CHICKEN2 XE_REG_MCR(0xe4f4)
#define DISABLE_READ_SUPPRESSION REG_BIT(15)
#define DISABLE_EARLY_READ REG_BIT(14)
#define ENABLE_LARGE_GRF_MODE REG_BIT(12)
#define PUSH_CONST_DEREF_HOLD_DIS REG_BIT(8)
#define DISABLE_DOP_GATING REG_BIT(0)
-#define XEHP_HDC_CHICKEN0 MCR_REG(0xe5f0)
+#define XEHP_HDC_CHICKEN0 XE_REG_MCR(0xe5f0)
#define LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK REG_GENMASK(13, 11)
-#define RT_CTRL MCR_REG(0xe530)
+#define RT_CTRL XE_REG_MCR(0xe530)
#define DIS_NULL_QUERY REG_BIT(10)
-#define LSC_CHICKEN_BIT_0 MCR_REG(0xe7c8)
+#define LSC_CHICKEN_BIT_0 XE_REG_MCR(0xe7c8)
#define DISABLE_D8_D16_COASLESCE REG_BIT(30)
#define FORCE_1_SUB_MESSAGE_PER_FRAGMENT REG_BIT(15)
-#define LSC_CHICKEN_BIT_0_UDW MCR_REG(0xe7c8 + 4)
+#define LSC_CHICKEN_BIT_0_UDW XE_REG_MCR(0xe7c8 + 4)
#define DIS_CHAIN_2XSIMD8 REG_BIT(55 - 32)
#define FORCE_SLM_FENCE_SCOPE_TO_TILE REG_BIT(42 - 32)
#define FORCE_UGM_FENCE_SCOPE_TO_TILE REG_BIT(41 - 32)
#define MAXREQS_PER_BANK REG_GENMASK(39 - 32, 37 - 32)
#define DISABLE_128B_EVICTION_COMMAND_UDW REG_BIT(36 - 32)
-#define SARB_CHICKEN1 MCR_REG(0xe90c)
+#define SARB_CHICKEN1 XE_REG_MCR(0xe90c)
#define COMP_CKN_IN REG_GENMASK(30, 29)
-#define RCU_MODE _MMIO(0x14800)
+#define RCU_MODE XE_REG(0x14800)
#define RCU_MODE_CCS_ENABLE REG_BIT(0)
-#define FORCEWAKE_ACK_GT _MMIO(0x130044)
+#define FORCEWAKE_ACK_GT XE_REG(0x130044)
#define FORCEWAKE_KERNEL BIT(0)
#define FORCEWAKE_USER BIT(1)
#define FORCEWAKE_KERNEL_FALLBACK BIT(15)
-#define GT_CORE_STATUS _MMIO(0x138060)
+#define GT_CORE_STATUS XE_REG(0x138060)
#define RCN_MASK REG_GENMASK(2, 0)
#define GT_RC0 0
#define GT_RC6 3
-#define GT_GFX_RC6_LOCKED _MMIO(0x138104)
-#define GT_GFX_RC6 _MMIO(0x138108)
+#define GT_GFX_RC6_LOCKED XE_REG(0x138104)
+#define GT_GFX_RC6 XE_REG(0x138108)
-#define GFX_FLSH_CNTL _MMIO(0x101008)
+#define GFX_FLSH_CNTL XE_REG(0x101008)
#define GFX_FLSH_CNTL_EN REG_BIT(0)
-#define GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4))
+#define GT_INTR_DW(x) XE_REG(0x190018 + ((x) * 4))
-#define GUC_SG_INTR_ENABLE _MMIO(0x190038)
+#define GUC_SG_INTR_ENABLE XE_REG(0x190038)
#define ENGINE1_MASK REG_GENMASK(31, 16)
#define ENGINE0_MASK REG_GENMASK(15, 0)
-#define GPM_WGBOXPERF_INTR_ENABLE _MMIO(0x19003c)
+#define GPM_WGBOXPERF_INTR_ENABLE XE_REG(0x19003c)
-#define INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
+#define INTR_IDENTITY_REG(x) XE_REG(0x190060 + ((x) * 4))
#define INTR_DATA_VALID REG_BIT(31)
#define INTR_ENGINE_INSTANCE(x) REG_FIELD_GET(GENMASK(25, 20), x)
#define INTR_ENGINE_CLASS(x) REG_FIELD_GET(GENMASK(18, 16), x)
#define INTR_ENGINE_INTR(x) REG_FIELD_GET(GENMASK(15, 0), x)
#define OTHER_GUC_INSTANCE 0
-#define RENDER_COPY_INTR_ENABLE _MMIO(0x190030)
-#define VCS_VECS_INTR_ENABLE _MMIO(0x190034)
-#define CCS_RSVD_INTR_ENABLE _MMIO(0x190048)
-#define IIR_REG_SELECTOR(x) _MMIO(0x190070 + ((x) * 4))
-#define RCS0_RSVD_INTR_MASK _MMIO(0x190090)
-#define BCS_RSVD_INTR_MASK _MMIO(0x1900a0)
-#define VCS0_VCS1_INTR_MASK _MMIO(0x1900a8)
-#define VCS2_VCS3_INTR_MASK _MMIO(0x1900ac)
-#define VECS0_VECS1_INTR_MASK _MMIO(0x1900d0)
-#define GUC_SG_INTR_MASK _MMIO(0x1900e8)
-#define GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec)
-#define CCS0_CCS1_INTR_MASK _MMIO(0x190100)
-#define CCS2_CCS3_INTR_MASK _MMIO(0x190104)
-#define XEHPC_BCS1_BCS2_INTR_MASK _MMIO(0x190110)
-#define XEHPC_BCS3_BCS4_INTR_MASK _MMIO(0x190114)
-#define XEHPC_BCS5_BCS6_INTR_MASK _MMIO(0x190118)
-#define XEHPC_BCS7_BCS8_INTR_MASK _MMIO(0x19011c)
+#define RENDER_COPY_INTR_ENABLE XE_REG(0x190030)
+#define VCS_VECS_INTR_ENABLE XE_REG(0x190034)
+#define CCS_RSVD_INTR_ENABLE XE_REG(0x190048)
+#define IIR_REG_SELECTOR(x) XE_REG(0x190070 + ((x) * 4))
+#define RCS0_RSVD_INTR_MASK XE_REG(0x190090)
+#define BCS_RSVD_INTR_MASK XE_REG(0x1900a0)
+#define VCS0_VCS1_INTR_MASK XE_REG(0x1900a8)
+#define VCS2_VCS3_INTR_MASK XE_REG(0x1900ac)
+#define VECS0_VECS1_INTR_MASK XE_REG(0x1900d0)
+#define GUC_SG_INTR_MASK XE_REG(0x1900e8)
+#define GPM_WGBOXPERF_INTR_MASK XE_REG(0x1900ec)
+#define CCS0_CCS1_INTR_MASK XE_REG(0x190100)
+#define CCS2_CCS3_INTR_MASK XE_REG(0x190104)
+#define XEHPC_BCS1_BCS2_INTR_MASK XE_REG(0x190110)
+#define XEHPC_BCS3_BCS4_INTR_MASK XE_REG(0x190114)
+#define XEHPC_BCS5_BCS6_INTR_MASK XE_REG(0x190118)
+#define XEHPC_BCS7_BCS8_INTR_MASK XE_REG(0x19011c)
#endif
diff --git a/drivers/gpu/drm/xe/regs/xe_guc_regs.h b/drivers/gpu/drm/xe/regs/xe_guc_regs.h
index 835d413ae186..f9095407bee7 100644
--- a/drivers/gpu/drm/xe/regs/xe_guc_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_guc_regs.h
@@ -13,7 +13,7 @@
/* Definitions of GuC H/W registers, bits, etc */
-#define GUC_STATUS _MMIO(0xc000)
+#define GUC_STATUS XE_REG(0xc000)
#define GS_AUTH_STATUS_MASK REG_GENMASK(31, 30)
#define GS_AUTH_STATUS_BAD REG_FIELD_PREP(GS_AUTH_STATUS_MASK, 0x1)
#define GS_AUTH_STATUS_GOOD REG_FIELD_PREP(GS_AUTH_STATUS_MASK, 0x2)
@@ -27,55 +27,55 @@
#define GS_BOOTROM_JUMP_PASSED REG_FIELD_PREP(GS_BOOTROM_MASK, 0x76)
#define GS_MIA_IN_RESET REG_BIT(0)
-#define SOFT_SCRATCH(n) _MMIO(0xc180 + (n) * 4)
+#define SOFT_SCRATCH(n) XE_REG(0xc180 + (n) * 4)
#define SOFT_SCRATCH_COUNT 16
-#define UOS_RSA_SCRATCH(i) _MMIO(0xc200 + (i) * 4)
+#define UOS_RSA_SCRATCH(i) XE_REG(0xc200 + (i) * 4)
#define UOS_RSA_SCRATCH_COUNT 64
-#define DMA_ADDR_0_LOW _MMIO(0xc300)
-#define DMA_ADDR_0_HIGH _MMIO(0xc304)
-#define DMA_ADDR_1_LOW _MMIO(0xc308)
-#define DMA_ADDR_1_HIGH _MMIO(0xc30c)
+#define DMA_ADDR_0_LOW XE_REG(0xc300)
+#define DMA_ADDR_0_HIGH XE_REG(0xc304)
+#define DMA_ADDR_1_LOW XE_REG(0xc308)
+#define DMA_ADDR_1_HIGH XE_REG(0xc30c)
#define DMA_ADDR_SPACE_MASK REG_GENMASK(20, 16)
#define DMA_ADDRESS_SPACE_WOPCM REG_FIELD_PREP(DMA_ADDR_SPACE_MASK, 7)
#define DMA_ADDRESS_SPACE_GTT REG_FIEDL_PREP(DMA_ADDR_SPACE_MASK, 8)
-#define DMA_COPY_SIZE _MMIO(0xc310)
-#define DMA_CTRL _MMIO(0xc314)
+#define DMA_COPY_SIZE XE_REG(0xc310)
+#define DMA_CTRL XE_REG(0xc314)
#define HUC_UKERNEL REG_BIT(9)
#define UOS_MOVE REG_BIT(4)
#define START_DMA REG_BIT(0)
-#define DMA_GUC_WOPCM_OFFSET _MMIO(0xc340)
+#define DMA_GUC_WOPCM_OFFSET XE_REG(0xc340)
#define GUC_WOPCM_OFFSET_SHIFT 14
#define GUC_WOPCM_OFFSET_MASK REG_GENMASK(31, GUC_WOPCM_OFFSET_SHIFT)
#define HUC_LOADING_AGENT_MASK REG_BIT(1)
#define HUC_LOADING_AGENT_VCR REG_FIELD_PREP(HUC_LOADING_AGENT_MASK, 0)
#define HUC_LOADING_AGENT_GUC REG_FIELD_PREP(HUC_LOADING_AGENT_MASK, 1)
#define GUC_WOPCM_OFFSET_VALID REG_BIT(0)
-#define GUC_MAX_IDLE_COUNT _MMIO(0xc3e4)
+#define GUC_MAX_IDLE_COUNT XE_REG(0xc3e4)
-#define HUC_STATUS2 _MMIO(0xd3b0)
+#define HUC_STATUS2 XE_REG(0xd3b0)
#define HUC_FW_VERIFIED REG_BIT(7)
-#define HUC_KERNEL_LOAD_INFO _MMIO(0xc1dc)
+#define HUC_KERNEL_LOAD_INFO XE_REG(0xc1dc)
#define HUC_LOAD_SUCCESSFUL REG_BIT(0)
-#define GUC_WOPCM_SIZE _MMIO(0xc050)
+#define GUC_WOPCM_SIZE XE_REG(0xc050)
#define GUC_WOPCM_SIZE_MASK REG_GENMASK(31, 12)
#define GUC_WOPCM_SIZE_LOCKED REG_BIT(0)
-#define GT_PM_CONFIG _MMIO(0x13816c)
+#define GT_PM_CONFIG XE_REG(0x13816c)
#define GT_DOORBELL_ENABLE REG_BIT(0)
-#define GTCR _MMIO(0x4274)
+#define GTCR XE_REG(0x4274)
#define GTCR_INVALIDATE REG_BIT(0)
-#define GUC_TLB_INV_CR _MMIO(0xcee8)
+#define GUC_TLB_INV_CR XE_REG(0xcee8)
#define GUC_TLB_INV_CR_INVALIDATE REG_BIT(0)
-#define GUC_ARAT_C6DIS _MMIO(0xa178)
+#define GUC_ARAT_C6DIS XE_REG(0xa178)
-#define GUC_SHIM_CONTROL _MMIO(0xc064)
+#define GUC_SHIM_CONTROL XE_REG(0xc064)
#define PVC_GUC_MOCS_INDEX_MASK REG_GENMASK(25, 24)
#define PVC_GUC_MOCS_UC_INDEX 1
#define PVC_GUC_MOCS_INDEX(index) REG_FIELD_PREP(PVC_GUC_MOCS_INDEX_MASK, \
@@ -90,9 +90,9 @@
#define GUC_DISABLE_SRAM_INIT_TO_ZEROES REG_BIT(0)
-#define GUC_SEND_INTERRUPT _MMIO(0xc4c8)
+#define GUC_SEND_INTERRUPT XE_REG(0xc4c8)
#define GUC_SEND_TRIGGER REG_BIT(0)
-#define GUC_HOST_INTERRUPT _MMIO(0x1901f0)
+#define GUC_HOST_INTERRUPT XE_REG(0x1901f0)
#define GUC_NUM_DOORBELLS 256
@@ -106,24 +106,24 @@ struct guc_doorbell_info {
u32 reserved[14];
} __packed;
-#define DRBREGL(x) _MMIO(0x1000 + (x) * 8)
+#define DRBREGL(x) XE_REG(0x1000 + (x) * 8)
#define DRB_VALID REG_BIT(0)
-#define DRBREGU(x) _MMIO(0x1000 + (x) * 8 + 4)
+#define DRBREGU(x) XE_REG(0x1000 + (x) * 8 + 4)
-#define DIST_DBS_POPULATED _MMIO(0xd08)
+#define DIST_DBS_POPULATED XE_REG(0xd08)
#define DOORBELLS_PER_SQIDI_MASK REG_GENMASK(23, 16)
#define SQIDIS_DOORBELL_EXIST_MASK REG_GENMASK(15, 0)
-#define GUC_BCS_RCS_IER _MMIO(0xC550)
-#define GUC_VCS2_VCS1_IER _MMIO(0xC554)
-#define GUC_WD_VECS_IER _MMIO(0xC558)
-#define GUC_PM_P24C_IER _MMIO(0xC55C)
+#define GUC_BCS_RCS_IER XE_REG(0xC550)
+#define GUC_VCS2_VCS1_IER XE_REG(0xC554)
+#define GUC_WD_VECS_IER XE_REG(0xC558)
+#define GUC_PM_P24C_IER XE_REG(0xC55C)
-#define VF_SW_FLAG(n) _MMIO(0x190240 + (n) * 4)
-#define VF_SW_FLAG_COUNT 4
+#define VF_SW_FLAG(n) XE_REG(0x190240 + (n) * 4)
+#define VF_SW_FLAG_COUNT 4
-#define MED_VF_SW_FLAG(n) _MMIO(0x190310 + (n) * 4)
-#define MED_VF_SW_FLAG_COUNT 4
+#define MED_VF_SW_FLAG(n) XE_REG(0x190310 + (n) * 4)
+#define MED_VF_SW_FLAG_COUNT 4
/* GuC Interrupt Vector */
#define GUC_INTR_GUC2HOST BIT(15)
diff --git a/drivers/gpu/drm/xe/regs/xe_reg_defs.h b/drivers/gpu/drm/xe/regs/xe_reg_defs.h
index 1e78508c737b..ddf734b59257 100644
--- a/drivers/gpu/drm/xe/regs/xe_reg_defs.h
+++ b/drivers/gpu/drm/xe/regs/xe_reg_defs.h
@@ -17,10 +17,53 @@ typedef union {
u32 raw;
} xe_reg_t;
-/* TODO: remove these once the register declarations are not using them anymore */
-#undef _MMIO
-#undef MCR_REG
-#define _MMIO(r) ((const xe_reg_t){ .reg = (r) })
-#define MCR_REG(r) ((const xe_reg_t){ .reg = (r), .mcr = 1 })
+
+/**
+ * XE_REG_INITIALIZER - Initializer for xe_reg_t.
+ * @r_: Register offset
+ * @...: Additional options like register type, access mode, etc. See
+ * ``xe_reg_t``.
+ *
+ * Register field is mandatory, and additional options may be passed as
+ * arguments. Usually ``XE_REG()`` should be preferred since it creates an
+ * object of the right type. However when initializing static const storage,
+ * where a compound statement is not allowed, this can be used instead.
+ */
+#define XE_REG_INITIALIZER(r_, ...) { .reg = r_, __VA_ARGS__ }
+
+/**
+ * XE_REG_OPTION_MASKED - Register is "masked", with upper 16 bits marking the
+ * read/written bits on the lower 16 bits
+ *
+ * To be used with ``XE_REG()`` and ``XE_REG_INITIALIZER()``
+ */
+#define XE_REG_OPTION_MASKED .masked = 1
+
+/**
+ * XE_REG_OPTION_MCR - Register is replicated, possibly needing the reads/writes
+ * to be steered to the right unit via ``xe_gt_mcr``.
+ *
+ * To be used with ``XE_REG()`` and ``XE_REG_INITIALIZER()``
+ */
+#define XE_REG_OPTION_MCR .mcr = 1
+
+
+/**
+ * XE_REG - Create a xe_reg_t from offset and additional flags
+ * @r: Register offset
+ * @...: Additional options like register type, access mode, etc. See
+ * ``xe_reg_t`` for available options.
+ */
+#define XE_REG(r_, ...) ((xe_reg_t)XE_REG_INITIALIZER(r_, ##__VA_ARGS__))
+
+/**
+ * XE_REG_MCR - Shortcut helper to declare multicast registers
+ * @r: Register offset
+ * @...: Additional options like register type, access mode, etc. See
+ * ``xe_reg_t`` for available options.
+ *
+ * Same as XE_REG(r, .mcr = 1)
+ */
+#define XE_REG_MCR(r_, ...) XE_REG(r_, XE_REG_OPTION_MCR, ##__VA_ARGS__)
#endif
diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h
index da1d5aa6cdb7..8be616a1bd51 100644
--- a/drivers/gpu/drm/xe/regs/xe_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_regs.h
@@ -7,7 +7,7 @@
#include "regs/xe_reg_defs.h"
-#define GU_CNTL _MMIO(0x101010)
+#define GU_CNTL XE_REG(0x101010)
#define LMEM_INIT REG_BIT(7)
#define RENDER_RING_BASE 0x02000
@@ -42,18 +42,18 @@
#define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3)
#define GT_RENDER_USER_INTERRUPT REG_BIT(0)
-#define FF_THREAD_MODE _MMIO(0x20a0)
+#define FF_THREAD_MODE XE_REG(0x20a0)
#define FF_TESSELATION_DOP_GATE_DISABLE BIT(19)
-#define PVC_RP_STATE_CAP _MMIO(0x281014)
-#define MTL_RP_STATE_CAP _MMIO(0x138000)
+#define PVC_RP_STATE_CAP XE_REG(0x281014)
+#define MTL_RP_STATE_CAP XE_REG(0x138000)
-#define MTL_MEDIAP_STATE_CAP _MMIO(0x138020)
+#define MTL_MEDIAP_STATE_CAP XE_REG(0x138020)
#define MTL_RP0_CAP_MASK REG_GENMASK(8, 0)
#define MTL_RPN_CAP_MASK REG_GENMASK(24, 16)
-#define MTL_GT_RPE_FREQUENCY _MMIO(0x13800c)
-#define MTL_MPE_FREQUENCY _MMIO(0x13802c)
+#define MTL_GT_RPE_FREQUENCY XE_REG(0x13800c)
+#define MTL_MPE_FREQUENCY XE_REG(0x13802c)
#define MTL_RPE_MASK REG_GENMASK(8, 0)
#define TRANSCODER_A_OFFSET 0x60000
@@ -73,32 +73,32 @@
#define CURSOR_C_OFFSET 0x72080
#define CURSOR_D_OFFSET 0x73080
-#define SOFTWARE_FLAGS_SPR33 _MMIO(0x4f084)
+#define SOFTWARE_FLAGS_SPR33 XE_REG(0x4f084)
#define PCU_IRQ_OFFSET 0x444e0
#define GU_MISC_IRQ_OFFSET 0x444f0
#define GU_MISC_GSE REG_BIT(27)
-#define GFX_MSTR_IRQ _MMIO(0x190010)
+#define GFX_MSTR_IRQ XE_REG(0x190010)
#define MASTER_IRQ REG_BIT(31)
#define GU_MISC_IRQ REG_BIT(29)
#define DISPLAY_IRQ REG_BIT(16)
#define GT_DW_IRQ(x) REG_BIT(x)
-#define DG1_MSTR_TILE_INTR _MMIO(0x190008)
+#define DG1_MSTR_TILE_INTR XE_REG(0x190008)
#define DG1_MSTR_IRQ REG_BIT(31)
#define DG1_MSTR_TILE(t) REG_BIT(t)
-#define TIMESTAMP_OVERRIDE _MMIO(0x44074)
+#define TIMESTAMP_OVERRIDE XE_REG(0x44074)
#define TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK REG_GENMASK(15, 12)
#define TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK REG_GENMASK(9, 0)
-#define GGC _MMIO(0x108040)
+#define GGC XE_REG(0x108040)
#define GMS_MASK REG_GENMASK(15, 8)
#define GGMS_MASK REG_GENMASK(7, 6)
-#define GSMBASE _MMIO(0x108100)
-#define DSMBASE _MMIO(0x1080C0)
+#define GSMBASE XE_REG(0x108100)
+#define DSMBASE XE_REG(0x1080C0)
#define BDSM_MASK REG_GENMASK64(63, 20)
#endif
diff --git a/drivers/gpu/drm/xe/tests/xe_rtp_test.c b/drivers/gpu/drm/xe/tests/xe_rtp_test.c
index 29e112c108c6..51d215f08113 100644
--- a/drivers/gpu/drm/xe/tests/xe_rtp_test.c
+++ b/drivers/gpu/drm/xe/tests/xe_rtp_test.c
@@ -18,17 +18,17 @@
#include "xe_reg_sr.h"
#include "xe_rtp.h"
-#undef _MMIO
-#undef MCR_REG
-#define _MMIO(x) _XE_RTP_REG(x)
-#define MCR_REG(x) _XE_RTP_MCR_REG(x)
+#undef XE_REG
+#undef XE_REG_MCR
+#define XE_REG(x, ...) _XE_RTP_REG(x)
+#define XE_REG_MCR(x, ...) _XE_RTP_MCR_REG(x)
-#define REGULAR_REG1 _MMIO(1)
-#define REGULAR_REG2 _MMIO(2)
-#define REGULAR_REG3 _MMIO(3)
-#define MCR_REG1 MCR_REG(1)
-#define MCR_REG2 MCR_REG(2)
-#define MCR_REG3 MCR_REG(3)
+#define REGULAR_REG1 XE_REG(1)
+#define REGULAR_REG2 XE_REG(2)
+#define REGULAR_REG3 XE_REG(3)
+#define MCR_REG1 XE_REG_MCR(1)
+#define MCR_REG2 XE_REG_MCR(2)
+#define MCR_REG3 XE_REG_MCR(3)
struct rtp_test_case {
const char *name;
diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
index 3417cc7e0291..6d450e431872 100644
--- a/drivers/gpu/drm/xe/xe_ggtt.c
+++ b/drivers/gpu/drm/xe/xe_ggtt.c
@@ -185,11 +185,11 @@ int xe_ggtt_init(struct xe_gt *gt, struct xe_ggtt *ggtt)
return err;
}
-#define GUC_TLB_INV_CR _MMIO(0xcee8)
+#define GUC_TLB_INV_CR XE_REG(0xcee8)
#define GUC_TLB_INV_CR_INVALIDATE REG_BIT(0)
-#define PVC_GUC_TLB_INV_DESC0 _MMIO(0xcf7c)
+#define PVC_GUC_TLB_INV_DESC0 XE_REG(0xcf7c)
#define PVC_GUC_TLB_INV_DESC0_VALID REG_BIT(0)
-#define PVC_GUC_TLB_INV_DESC1 _MMIO(0xcf80)
+#define PVC_GUC_TLB_INV_DESC1 XE_REG(0xcf80)
#define PVC_GUC_TLB_INV_DESC1_INVALIDATE REG_BIT(6)
void xe_ggtt_invalidate(struct xe_gt *gt)
diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index 4e9e9b1aad02..3794fdf3d35a 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -22,6 +22,10 @@
#include "xe_uc_fw.h"
#include "xe_wopcm.h"
+#define MEDIA_GUC_HOST_INTERRUPT XE_REG(0x190304)
+#define MEDIA_SOFT_SCRATCH(n) XE_REG(0x190310 + (n) * 4)
+#define MEDIA_SOFT_SCRATCH_COUNT 4
+
static struct xe_gt *
guc_to_gt(struct xe_guc *guc)
{
@@ -244,8 +248,6 @@ static void guc_write_params(struct xe_guc *guc)
xe_mmio_write32(gt, SOFT_SCRATCH(1 + i).reg, guc->params[i]);
}
-#define MEDIA_GUC_HOST_INTERRUPT _MMIO(0x190304)
-
int xe_guc_init(struct xe_guc *guc)
{
struct xe_device *xe = guc_to_xe(guc);
diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
index 10c3a442ecd9..fdbcfbcc9861 100644
--- a/drivers/gpu/drm/xe/xe_guc_pc.c
+++ b/drivers/gpu/drm/xe/xe_guc_pc.c
@@ -23,18 +23,18 @@
#define MCHBAR_MIRROR_BASE_SNB 0x140000
-#define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
-#define RP0_MASK REG_GENMASK(7, 0)
-#define RP1_MASK REG_GENMASK(15, 8)
-#define RPN_MASK REG_GENMASK(23, 16)
+#define GEN6_RP_STATE_CAP XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5998)
+#define RP0_MASK REG_GENMASK(7, 0)
+#define RP1_MASK REG_GENMASK(15, 8)
+#define RPN_MASK REG_GENMASK(23, 16)
-#define GEN10_FREQ_INFO_REC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5ef0)
+#define GEN10_FREQ_INFO_REC XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5ef0)
#define RPE_MASK REG_GENMASK(15, 8)
-#define GEN12_RPSTAT1 _MMIO(0x1381b4)
+#define GEN12_RPSTAT1 XE_REG(0x1381b4)
#define GEN12_CAGF_MASK REG_GENMASK(19, 11)
-#define MTL_MIRROR_TARGET_WP1 _MMIO(0xc60)
+#define MTL_MIRROR_TARGET_WP1 XE_REG(0xc60)
#define MTL_CAGF_MASK REG_GENMASK(8, 0)
#define GT_FREQUENCY_MULTIPLIER 50
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index 8e5f8e7c16c8..fe359480f129 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -23,9 +23,9 @@
* Interrupt registers for a unit are always consecutive and ordered
* ISR, IMR, IIR, IER.
*/
-#define IMR(offset) _MMIO(offset + 0x4)
-#define IIR(offset) _MMIO(offset + 0x8)
-#define IER(offset) _MMIO(offset + 0xc)
+#define IMR(offset) XE_REG(offset + 0x4)
+#define IIR(offset) XE_REG(offset + 0x8)
+#define IER(offset) XE_REG(offset + 0xc)
static void assert_iir_is_zero(struct xe_gt *gt, xe_reg_t reg)
{
diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
index 1029b9f27988..c84bfa4365c1 100644
--- a/drivers/gpu/drm/xe/xe_mmio.c
+++ b/drivers/gpu/drm/xe/xe_mmio.c
@@ -17,7 +17,7 @@
#include "xe_macros.h"
#include "xe_module.h"
-#define XEHP_MTCFG_ADDR _MMIO(0x101800)
+#define XEHP_MTCFG_ADDR XE_REG(0x101800)
#define TILE_COUNT REG_GENMASK(15, 8)
#define GEN12_LMEM_BAR 2
diff --git a/drivers/gpu/drm/xe/xe_mocs.c b/drivers/gpu/drm/xe/xe_mocs.c
index 67c63facdbf9..f2ceecd536ed 100644
--- a/drivers/gpu/drm/xe/xe_mocs.c
+++ b/drivers/gpu/drm/xe/xe_mocs.c
@@ -477,8 +477,8 @@ static void __init_mocs_table(struct xe_gt *gt,
for (i = 0;
i < info->n_entries ? (mocs = get_entry_control(info, i)), 1 : 0;
i++) {
- mocs_dbg(>->xe->drm, "%d 0x%x 0x%x\n", i, _MMIO(addr + i * 4).reg, mocs);
- xe_mmio_write32(gt, _MMIO(addr + i * 4).reg, mocs);
+ mocs_dbg(>->xe->drm, "%d 0x%x 0x%x\n", i, XE_REG(addr + i * 4).reg, mocs);
+ xe_mmio_write32(gt, XE_REG(addr + i * 4).reg, mocs);
}
}
diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c
index fcf6ae2c92cc..abee41fa3cb9 100644
--- a/drivers/gpu/drm/xe/xe_pat.c
+++ b/drivers/gpu/drm/xe/xe_pat.c
@@ -71,7 +71,7 @@ static void program_pat(struct xe_gt *gt, const u32 table[], int n_entries)
static void program_pat_mcr(struct xe_gt *gt, const u32 table[], int n_entries)
{
for (int i = 0; i < n_entries; i++)
- xe_gt_mcr_multicast_write(gt, MCR_REG(_PAT_INDEX(i)), table[i]);
+ xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_INDEX(i)), table[i]);
}
void xe_pat_init(struct xe_gt *gt)
diff --git a/drivers/gpu/drm/xe/xe_pcode_api.h b/drivers/gpu/drm/xe/xe_pcode_api.h
index 4e689cd4b23b..837ff7c71280 100644
--- a/drivers/gpu/drm/xe/xe_pcode_api.h
+++ b/drivers/gpu/drm/xe/xe_pcode_api.h
@@ -7,7 +7,7 @@
#include "regs/xe_reg_defs.h"
-#define PCODE_MAILBOX _MMIO(0x138124)
+#define PCODE_MAILBOX XE_REG(0x138124)
#define PCODE_READY REG_BIT(31)
#define PCODE_MB_PARAM2 REG_GENMASK(23, 16)
#define PCODE_MB_PARAM1 REG_GENMASK(15, 8)
@@ -22,8 +22,8 @@
#define PCODE_GT_RATIO_OUT_OF_RANGE 0x10
#define PCODE_REJECTED 0x11
-#define PCODE_DATA0 _MMIO(0x138128)
-#define PCODE_DATA1 _MMIO(0x13812C)
+#define PCODE_DATA0 XE_REG(0x138128)
+#define PCODE_DATA1 XE_REG(0x13812C)
/* Min Freq QOS Table */
#define PCODE_WRITE_MIN_FREQ_TABLE 0x8
diff --git a/drivers/gpu/drm/xe/xe_reg_sr.c b/drivers/gpu/drm/xe/xe_reg_sr.c
index feed87109e93..78cb0e93a7ed 100644
--- a/drivers/gpu/drm/xe/xe_reg_sr.c
+++ b/drivers/gpu/drm/xe/xe_reg_sr.c
@@ -153,7 +153,7 @@ static void apply_one_mmio(struct xe_gt *gt, u32 reg,
val = (entry->clr_bits ?: entry->set_bits << 16);
else if (entry->clr_bits + 1)
val = (entry->reg_type == XE_RTP_REG_MCR ?
- xe_gt_mcr_unicast_read_any(gt, MCR_REG(reg)) :
+ xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(reg)) :
xe_mmio_read32(gt, reg)) & (~entry->clr_bits);
else
val = 0;
@@ -168,7 +168,7 @@ static void apply_one_mmio(struct xe_gt *gt, u32 reg,
drm_dbg(&xe->drm, "REG[0x%x] = 0x%08x", reg, val);
if (entry->reg_type == XE_RTP_REG_MCR)
- xe_gt_mcr_multicast_write(gt, MCR_REG(reg), val);
+ xe_gt_mcr_multicast_write(gt, XE_REG_MCR(reg), val);
else
xe_mmio_write32(gt, reg, val);
}
diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
index 5a2665706912..310d5dfe30d5 100644
--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
+++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
@@ -11,10 +11,10 @@
#include "xe_platform_types.h"
#include "xe_rtp.h"
-#undef _MMIO
-#undef MCR_REG
-#define _MMIO(x) _XE_RTP_REG(x)
-#define MCR_REG(x) _XE_RTP_MCR_REG(x)
+#undef XE_REG
+#undef XE_REG_MCR
+#define XE_REG(x, ...) _XE_RTP_REG(x)
+#define XE_REG_MCR(x, ...) _XE_RTP_MCR_REG(x)
static bool match_not_render(const struct xe_gt *gt,
const struct xe_hw_engine *hwe)
@@ -45,10 +45,10 @@ static const struct xe_rtp_entry register_whitelist[] = {
},
{ XE_RTP_NAME("16014440446"),
XE_RTP_RULES(PLATFORM(PVC)),
- XE_RTP_ACTIONS(WHITELIST(_MMIO(0x4400),
+ XE_RTP_ACTIONS(WHITELIST(XE_REG(0x4400),
RING_FORCE_TO_NONPRIV_DENY |
RING_FORCE_TO_NONPRIV_RANGE_64),
- WHITELIST(_MMIO(0x4500),
+ WHITELIST(XE_REG(0x4500),
RING_FORCE_TO_NONPRIV_DENY |
RING_FORCE_TO_NONPRIV_RANGE_64))
},
diff --git a/drivers/gpu/drm/xe/xe_rtp.h b/drivers/gpu/drm/xe/xe_rtp.h
index 53650f09efe9..9148f32baa02 100644
--- a/drivers/gpu/drm/xe/xe_rtp.h
+++ b/drivers/gpu/drm/xe/xe_rtp.h
@@ -196,7 +196,7 @@ struct xe_reg_sr;
* XE_RTP_ACTION_WR - Helper to write a value to the register, overriding all
* the bits
* @reg_: Register
- * @reg_type_: Register type - automatically expanded by MCR_REG/_MMIO
+ * @reg_type_: Register type - automatically expanded by XE_REG
* @val_: Value to set
* @...: Additional fields to override in the struct xe_rtp_action entry
*
@@ -212,7 +212,7 @@ struct xe_reg_sr;
/**
* XE_RTP_ACTION_SET - Set bits from @val_ in the register.
* @reg_: Register
- * @reg_type_: Register type - automatically expanded by MCR_REG/_MMIO
+ * @reg_type_: Register type - automatically expanded by XE_REG
* @val_: Bits to set in the register
* @...: Additional fields to override in the struct xe_rtp_action entry
*
@@ -231,7 +231,7 @@ struct xe_reg_sr;
/**
* XE_RTP_ACTION_CLR: Clear bits from @val_ in the register.
* @reg_: Register
- * @reg_type_: Register type - automatically expanded by MCR_REG/_MMIO
+ * @reg_type_: Register type - automatically expanded by XE_REG
* @val_: Bits to clear in the register
* @...: Additional fields to override in the struct xe_rtp_action entry
*
@@ -250,7 +250,7 @@ struct xe_reg_sr;
/**
* XE_RTP_ACTION_FIELD_SET: Set a bit range
* @reg_: Register
- * @reg_type_: Register type - automatically expanded by MCR_REG/_MMIO
+ * @reg_type_: Register type - automatically expanded by XE_REG
* @mask_bits_: Mask of bits to be changed in the register, forming a field
* @val_: Value to set in the field denoted by @mask_bits_
* @...: Additional fields to override in the struct xe_rtp_action entry
@@ -273,7 +273,7 @@ struct xe_reg_sr;
/**
* XE_RTP_ACTION_WHITELIST - Add register to userspace whitelist
* @reg_: Register
- * @reg_type_: Register type - automatically expanded by MCR_REG/_MMIO
+ * @reg_type_: Register type - automatically expanded by XE_REG
* @val_: Whitelist-specific flags to set
* @...: Additional fields to override in the struct xe_rtp_action entry
*
diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
index 43912312cfba..f6eefa951175 100644
--- a/drivers/gpu/drm/xe/xe_tuning.c
+++ b/drivers/gpu/drm/xe/xe_tuning.c
@@ -12,10 +12,10 @@
#include "xe_platform_types.h"
#include "xe_rtp.h"
-#undef _MMIO
-#undef MCR_REG
-#define _MMIO(x) _XE_RTP_REG(x)
-#define MCR_REG(x) _XE_RTP_MCR_REG(x)
+#undef XE_REG
+#undef XE_REG_MCR
+#define XE_REG(x, ...) _XE_RTP_REG(x)
+#define XE_REG_MCR(x, ...) _XE_RTP_MCR_REG(x)
static const struct xe_rtp_entry gt_tunings[] = {
{ XE_RTP_NAME("Tuning: Blend Fill Caching Optimization Disable"),
diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index f402d56c675c..b7dc71f63c8a 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -87,10 +87,10 @@
* a more declarative approach rather than procedural.
*/
-#undef _MMIO
-#undef MCR_REG
-#define _MMIO(x) _XE_RTP_REG(x)
-#define MCR_REG(x) _XE_RTP_MCR_REG(x)
+#undef XE_REG
+#undef XE_REG_MCR
+#define XE_REG(x, ...) _XE_RTP_REG(x)
+#define XE_REG_MCR(x, ...) _XE_RTP_MCR_REG(x)
__diag_push();
__diag_ignore_all("-Woverride-init", "Allow field overrides in table");
--
2.39.0
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Intel-xe] [PATCH 15/17] drm/xe: Annotate masked registers used by RTP
2023-04-19 7:44 [Intel-xe] [PATCH 00/17] Cleanup registers and introduce xe_reg_t Lucas De Marchi
` (13 preceding siblings ...)
2023-04-19 7:44 ` [Intel-xe] [PATCH 14/17] drm/xe: Add XE_REG/XE_REG_MCR Lucas De Marchi
@ 2023-04-19 7:44 ` Lucas De Marchi
2023-04-19 7:44 ` [Intel-xe] [PATCH 16/17] drm/xe: Plumb xe_reg_t into WAs, rtp, etc Lucas De Marchi
` (5 subsequent siblings)
20 siblings, 0 replies; 41+ messages in thread
From: Lucas De Marchi @ 2023-04-19 7:44 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, Matt Roper, Rodrigo Vivi
Go over all registers used in xe_rtp tables and mark the registers as
masked if they were passed a XE_RTP_ACTION_FLAG(MASKED_REG) flag.
This will allow the flag to be removed in future when xe_rtp starts
using the real xe_reg_t type.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/regs/xe_engine_regs.h | 2 +-
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 46 ++++++++++++------------
drivers/gpu/drm/xe/regs/xe_reg_defs.h | 6 ++++
3 files changed, 30 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
index c13aac8f900c..f8851e045c0a 100644
--- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
@@ -21,7 +21,7 @@
#define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */
#define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */
-#define RING_PSMI_CTL(base) XE_REG((base) + 0x50)
+#define RING_PSMI_CTL(base) XE_REG((base) + 0x50, XE_REG_OPTION_MASKED)
#define RC_SEMA_IDLE_MSG_DISABLE REG_BIT(12)
#define WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 64ab2255a406..c6949cec1dc3 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -45,19 +45,19 @@
#define MTL_MCR_GROUPID REG_GENMASK(11, 8)
#define MTL_MCR_INSTANCEID REG_GENMASK(3, 0)
-#define FF_SLICE_CS_CHICKEN1 XE_REG(0x20e0)
+#define FF_SLICE_CS_CHICKEN1 XE_REG(0x20e0, XE_REG_OPTION_MASKED)
#define FFSC_PERCTX_PREEMPT_CTRL REG_BIT(14)
-#define FF_SLICE_CS_CHICKEN2 XE_REG(0x20e4)
+#define FF_SLICE_CS_CHICKEN2 XE_REG(0x20e4, XE_REG_OPTION_MASKED)
#define PERF_FIX_BALANCING_CFE_DISABLE REG_BIT(15)
-#define CS_DEBUG_MODE1 XE_REG(0x20ec)
+#define CS_DEBUG_MODE1 XE_REG(0x20ec, XE_REG_OPTION_MASKED)
#define FF_DOP_CLOCK_GATE_DISABLE REG_BIT(1)
#define REPLAY_MODE_GRANULARITY REG_BIT(0)
#define PS_INVOCATION_COUNT XE_REG(0x2348)
-#define CS_CHICKEN1 XE_REG(0x2580)
+#define CS_CHICKEN1 XE_REG(0x2580, XE_REG_OPTION_MASKED)
#define PREEMPT_GPGPU_LEVEL(hi, lo) (((hi) << 2) | ((lo) << 1))
#define PREEMPT_GPGPU_MID_THREAD_LEVEL PREEMPT_GPGPU_LEVEL(0, 0)
#define PREEMPT_GPGPU_THREAD_GROUP_LEVEL PREEMPT_GPGPU_LEVEL(0, 1)
@@ -77,10 +77,10 @@
#define XEHP_TILE0_ADDR_RANGE XE_REG_MCR(0x4900)
#define XEHP_FLAT_CCS_BASE_ADDR XE_REG_MCR(0x4910)
-#define CHICKEN_RASTER_1 XE_REG_MCR(0x6204)
+#define CHICKEN_RASTER_1 XE_REG_MCR(0x6204, XE_REG_OPTION_MASKED)
#define DIS_SF_ROUND_NEAREST_EVEN REG_BIT(8)
-#define CHICKEN_RASTER_2 XE_REG_MCR(0x6208)
+#define CHICKEN_RASTER_2 XE_REG_MCR(0x6208, XE_REG_OPTION_MASKED)
#define TBIMR_FAST_CLIP REG_BIT(5)
#define VFLSKPD XE_REG_MCR(0x62a8)
@@ -94,35 +94,35 @@
#define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16)
#define FF_MODE2_TDS_TIMER_128 REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
-#define CACHE_MODE_1 XE_REG(0x7004)
+#define CACHE_MODE_1 XE_REG(0x7004, XE_REG_OPTION_MASKED)
#define MSAA_OPTIMIZATION_REDUC_DISABLE REG_BIT(11)
-#define XEHP_PSS_MODE2 XE_REG_MCR(0x703c)
+#define XEHP_PSS_MODE2 XE_REG_MCR(0x703c, XE_REG_OPTION_MASKED)
#define SCOREBOARD_STALL_FLUSH_CONTROL REG_BIT(5)
-#define HIZ_CHICKEN XE_REG(0x7018)
+#define HIZ_CHICKEN XE_REG(0x7018, XE_REG_OPTION_MASKED)
#define DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE REG_BIT(14)
#define HZ_DEPTH_TEST_LE_GE_OPT_DISABLE REG_BIT(13)
#define COMMON_SLICE_CHICKEN1 XE_REG(0x7010)
-#define COMMON_SLICE_CHICKEN4 XE_REG(0x7300)
+#define COMMON_SLICE_CHICKEN4 XE_REG(0x7300, XE_REG_OPTION_MASKED)
#define DISABLE_TDC_LOAD_BALANCING_CALC REG_BIT(6)
-#define COMMON_SLICE_CHICKEN3 XE_REG(0x7304)
-#define XEHP_COMMON_SLICE_CHICKEN3 XE_REG_MCR(0x7304)
+#define COMMON_SLICE_CHICKEN3 XE_REG(0x7304, XE_REG_OPTION_MASKED)
+#define XEHP_COMMON_SLICE_CHICKEN3 XE_REG_MCR(0x7304, XE_REG_OPTION_MASKED)
#define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN REG_BIT(12)
#define XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE REG_BIT(12)
#define BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11)
#define DISABLE_CPS_AWARE_COLOR_PIPE REG_BIT(9)
-#define XEHP_SLICE_COMMON_ECO_CHICKEN1 XE_REG_MCR(0x731c)
+#define XEHP_SLICE_COMMON_ECO_CHICKEN1 XE_REG_MCR(0x731c, XE_REG_OPTION_MASKED)
#define MSC_MSAA_REODER_BUF_BYPASS_DISABLE REG_BIT(14)
-#define VF_PREEMPTION XE_REG(0x83a4)
+#define VF_PREEMPTION XE_REG(0x83a4, XE_REG_OPTION_MASKED)
#define PREEMPTION_VERTEX_COUNT REG_GENMASK(15, 0)
-#define VFG_PREEMPTION_CHICKEN XE_REG(0x83b4)
+#define VFG_PREEMPTION_CHICKEN XE_REG(0x83b4, XE_REG_OPTION_MASKED)
#define POLYGON_TRIFAN_LINELOOP_DISABLE REG_BIT(4)
#define XEHP_SQCM XE_REG_MCR(0x8724)
@@ -248,7 +248,7 @@
#define FORCEWAKE_MEDIA_VDBOX(n) XE_REG(0xa540 + (n) * 4)
#define FORCEWAKE_MEDIA_VEBOX(n) XE_REG(0xa560 + (n) * 4)
-#define XEHPC_LNCFMISCCFGREG0 XE_REG_MCR(0xb01c)
+#define XEHPC_LNCFMISCCFGREG0 XE_REG_MCR(0xb01c, XE_REG_OPTION_MASKED)
#define XEHPC_OVRLSCCC REG_BIT(0)
#define XEHP_L3NODEARBCFG XE_REG_MCR(0xb0b4)
@@ -276,20 +276,20 @@
#define INVALIDATION_BROADCAST_MODE_DIS REG_BIT(12)
#define GLOBAL_INVALIDATION_MODE REG_BIT(2)
-#define SAMPLER_MODE XE_REG_MCR(0xe18c)
+#define SAMPLER_MODE XE_REG_MCR(0xe18c, XE_REG_OPTION_MASKED)
#define ENABLE_SMALLPL REG_BIT(15)
#define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
#define SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
-#define HALF_SLICE_CHICKEN7 XE_REG_MCR(0xe194)
+#define HALF_SLICE_CHICKEN7 XE_REG_MCR(0xe194, XE_REG_OPTION_MASKED)
#define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15)
-#define CACHE_MODE_SS XE_REG_MCR(0xe420)
+#define CACHE_MODE_SS XE_REG_MCR(0xe420, XE_REG_OPTION_MASKED)
#define ENABLE_EU_COUNT_FOR_TDL_FLUSH REG_BIT(10)
#define DISABLE_ECC REG_BIT(5)
#define ENABLE_PREFETCH_INTO_IC REG_BIT(3)
-#define ROW_CHICKEN4 XE_REG_MCR(0xe48c)
+#define ROW_CHICKEN4 XE_REG_MCR(0xe48c, XE_REG_OPTION_MASKED)
#define DISABLE_GRF_CLEAR REG_BIT(13)
#define XEHP_DIS_BBL_SYSPIPE REG_BIT(11)
#define DISABLE_TDL_PUSH REG_BIT(9)
@@ -298,18 +298,18 @@
#define THREAD_EX_ARB_MODE REG_GENMASK(3, 2)
#define THREAD_EX_ARB_MODE_RR_AFTER_DEP REG_FIELD_PREP(THREAD_EX_ARB_MODE, 0x2)
-#define ROW_CHICKEN XE_REG_MCR(0xe4f0)
+#define ROW_CHICKEN XE_REG_MCR(0xe4f0, XE_REG_OPTION_MASKED)
#define UGM_BACKUP_MODE REG_BIT(13)
#define MDQ_ARBITRATION_MODE REG_BIT(12)
-#define ROW_CHICKEN2 XE_REG_MCR(0xe4f4)
+#define ROW_CHICKEN2 XE_REG_MCR(0xe4f4, XE_REG_OPTION_MASKED)
#define DISABLE_READ_SUPPRESSION REG_BIT(15)
#define DISABLE_EARLY_READ REG_BIT(14)
#define ENABLE_LARGE_GRF_MODE REG_BIT(12)
#define PUSH_CONST_DEREF_HOLD_DIS REG_BIT(8)
#define DISABLE_DOP_GATING REG_BIT(0)
-#define XEHP_HDC_CHICKEN0 XE_REG_MCR(0xe5f0)
+#define XEHP_HDC_CHICKEN0 XE_REG_MCR(0xe5f0, XE_REG_OPTION_MASKED)
#define LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK REG_GENMASK(13, 11)
#define RT_CTRL XE_REG_MCR(0xe530)
diff --git a/drivers/gpu/drm/xe/regs/xe_reg_defs.h b/drivers/gpu/drm/xe/regs/xe_reg_defs.h
index ddf734b59257..9c2d23142cb2 100644
--- a/drivers/gpu/drm/xe/regs/xe_reg_defs.h
+++ b/drivers/gpu/drm/xe/regs/xe_reg_defs.h
@@ -48,6 +48,12 @@ typedef union {
#define XE_REG_OPTION_MCR .mcr = 1
+/**
+ * XE_REG_MASKED - Register is "masked", with upper 16 bits marking the
+ * read/written bits on the lower 16 bits
+ */
+#define XE_REG_MASKED .masked = 1
+
/**
* XE_REG - Create a xe_reg_t from offset and additional flags
* @r: Register offset
--
2.39.0
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Intel-xe] [PATCH 16/17] drm/xe: Plumb xe_reg_t into WAs, rtp, etc
2023-04-19 7:44 [Intel-xe] [PATCH 00/17] Cleanup registers and introduce xe_reg_t Lucas De Marchi
` (14 preceding siblings ...)
2023-04-19 7:44 ` [Intel-xe] [PATCH 15/17] drm/xe: Annotate masked registers used by RTP Lucas De Marchi
@ 2023-04-19 7:44 ` Lucas De Marchi
2023-04-19 16:15 ` Jani Nikula
2023-04-19 7:44 ` [Intel-xe] [PATCH 17/17] drm/xe: Move helper macros to separate header Lucas De Marchi
` (4 subsequent siblings)
20 siblings, 1 reply; 41+ messages in thread
From: Lucas De Marchi @ 2023-04-19 7:44 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, Matt Roper, Rodrigo Vivi
Now that xe_reg_t is a type that can be used by xe, convert the rest of
the driver to use it:
- The RTP tables don't need the MASKED flags anymore in the
actions as that information now comes from the register
definition
- There is no need for the _XE_RTP_REG/_XE_RTP_REG_MCR macros an
the register types on RTP infra: that comes from the register
definitions.
- When declaring the RTP entries, there is no need anymore to
undef XE_REG and friends: the RTP macros deal with removing
the cast where needed due to not being able to use a compound
statement for initialization in the tables
- The index in the reg-sr xarray is the register offset only.
Otherwise we wouldn't catch mistakes about adding both a
MCR-style and normal-style registers. For that, the register
is now also part of the entry, so the options can be compared
to check for compatible entries.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/tests/xe_rtp_test.c | 40 +++-----
drivers/gpu/drm/xe/xe_guc_ads.c | 2 +-
drivers/gpu/drm/xe/xe_reg_sr.c | 25 +++--
drivers/gpu/drm/xe/xe_reg_sr.h | 3 +-
drivers/gpu/drm/xe/xe_reg_sr_types.h | 10 +-
drivers/gpu/drm/xe/xe_reg_whitelist.c | 5 -
drivers/gpu/drm/xe/xe_rtp.c | 7 +-
drivers/gpu/drm/xe/xe_rtp.h | 46 ++++-----
drivers/gpu/drm/xe/xe_rtp_types.h | 14 +--
drivers/gpu/drm/xe/xe_tuning.c | 8 +-
drivers/gpu/drm/xe/xe_wa.c | 135 ++++++++-----------------
11 files changed, 106 insertions(+), 189 deletions(-)
diff --git a/drivers/gpu/drm/xe/tests/xe_rtp_test.c b/drivers/gpu/drm/xe/tests/xe_rtp_test.c
index 51d215f08113..ad917638d088 100644
--- a/drivers/gpu/drm/xe/tests/xe_rtp_test.c
+++ b/drivers/gpu/drm/xe/tests/xe_rtp_test.c
@@ -18,25 +18,18 @@
#include "xe_reg_sr.h"
#include "xe_rtp.h"
-#undef XE_REG
-#undef XE_REG_MCR
-#define XE_REG(x, ...) _XE_RTP_REG(x)
-#define XE_REG_MCR(x, ...) _XE_RTP_MCR_REG(x)
-
#define REGULAR_REG1 XE_REG(1)
#define REGULAR_REG2 XE_REG(2)
#define REGULAR_REG3 XE_REG(3)
#define MCR_REG1 XE_REG_MCR(1)
#define MCR_REG2 XE_REG_MCR(2)
#define MCR_REG3 XE_REG_MCR(3)
+#define MASKED_REG1 XE_REG(1, XE_REG_OPTION_MASKED)
struct rtp_test_case {
const char *name;
- struct {
- u32 offset;
- u32 type;
- } expected_reg;
- u32 expected_set_bits;
+ xe_reg_t expected_reg;
+ u32 expected_set_bits;
u32 expected_clr_bits;
unsigned long expected_count;
unsigned int expected_sr_errors;
@@ -56,7 +49,7 @@ static bool match_no(const struct xe_gt *gt, const struct xe_hw_engine *hwe)
static const struct rtp_test_case cases[] = {
{
.name = "coalesce-same-reg",
- .expected_reg = { REGULAR_REG1 },
+ .expected_reg = REGULAR_REG1,
.expected_set_bits = REG_BIT(0) | REG_BIT(1),
.expected_clr_bits = REG_BIT(0) | REG_BIT(1),
.expected_count = 1,
@@ -64,7 +57,7 @@ static const struct rtp_test_case cases[] = {
.entries = (const struct xe_rtp_entry[]) {
{ XE_RTP_NAME("basic-1"),
XE_RTP_RULES(FUNC(match_yes)),
- XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
+ XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(1)))
},
{ XE_RTP_NAME("basic-2"),
XE_RTP_RULES(FUNC(match_yes)),
@@ -75,7 +68,7 @@ static const struct rtp_test_case cases[] = {
},
{
.name = "no-match-no-add",
- .expected_reg = { REGULAR_REG1 },
+ .expected_reg = REGULAR_REG1,
.expected_set_bits = REG_BIT(0),
.expected_clr_bits = REG_BIT(0),
.expected_count = 1,
@@ -94,7 +87,7 @@ static const struct rtp_test_case cases[] = {
},
{
.name = "no-match-no-add-multiple-rules",
- .expected_reg = { REGULAR_REG1 },
+ .expected_reg = REGULAR_REG1,
.expected_set_bits = REG_BIT(0),
.expected_clr_bits = REG_BIT(0),
.expected_count = 1,
@@ -113,7 +106,7 @@ static const struct rtp_test_case cases[] = {
},
{
.name = "two-regs-two-entries",
- .expected_reg = { REGULAR_REG1 },
+ .expected_reg = REGULAR_REG1,
.expected_set_bits = REG_BIT(0),
.expected_clr_bits = REG_BIT(0),
.expected_count = 2,
@@ -132,7 +125,7 @@ static const struct rtp_test_case cases[] = {
},
{
.name = "clr-one-set-other",
- .expected_reg = { REGULAR_REG1 },
+ .expected_reg = REGULAR_REG1,
.expected_set_bits = REG_BIT(0),
.expected_clr_bits = REG_BIT(1) | REG_BIT(0),
.expected_count = 1,
@@ -153,7 +146,7 @@ static const struct rtp_test_case cases[] = {
#define TEMP_MASK REG_GENMASK(10, 8)
#define TEMP_FIELD REG_FIELD_PREP(TEMP_MASK, 2)
.name = "set-field",
- .expected_reg = { REGULAR_REG1 },
+ .expected_reg = REGULAR_REG1,
.expected_set_bits = TEMP_FIELD,
.expected_clr_bits = TEMP_MASK,
.expected_count = 1,
@@ -171,7 +164,7 @@ static const struct rtp_test_case cases[] = {
},
{
.name = "conflict-duplicate",
- .expected_reg = { REGULAR_REG1 },
+ .expected_reg = REGULAR_REG1,
.expected_set_bits = REG_BIT(0),
.expected_clr_bits = REG_BIT(0),
.expected_count = 1,
@@ -191,7 +184,7 @@ static const struct rtp_test_case cases[] = {
},
{
.name = "conflict-not-disjoint",
- .expected_reg = { REGULAR_REG1 },
+ .expected_reg = REGULAR_REG1,
.expected_set_bits = REG_BIT(0),
.expected_clr_bits = REG_BIT(0),
.expected_count = 1,
@@ -211,7 +204,7 @@ static const struct rtp_test_case cases[] = {
},
{
.name = "conflict-reg-type",
- .expected_reg = { REGULAR_REG1 },
+ .expected_reg = REGULAR_REG1,
.expected_set_bits = REG_BIT(0),
.expected_clr_bits = REG_BIT(0),
.expected_count = 1,
@@ -229,8 +222,7 @@ static const struct rtp_test_case cases[] = {
/* drop: regular vs masked */
{ XE_RTP_NAME("basic-3"),
XE_RTP_RULES(FUNC(match_yes)),
- XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0),
- XE_RTP_ACTION_FLAG(MASKED_REG)))
+ XE_RTP_ACTIONS(SET(MASKED_REG1, REG_BIT(0)))
},
{}
},
@@ -249,7 +241,7 @@ static void xe_rtp_process_tests(struct kunit *test)
xe_rtp_process(param->entries, reg_sr, &xe->gt[0], NULL);
xa_for_each(®_sr->xa, idx, sre) {
- if (idx == param->expected_reg.offset)
+ if (idx == param->expected_reg.reg)
sr_entry = sre;
count++;
@@ -258,7 +250,7 @@ static void xe_rtp_process_tests(struct kunit *test)
KUNIT_EXPECT_EQ(test, count, param->expected_count);
KUNIT_EXPECT_EQ(test, sr_entry->clr_bits, param->expected_clr_bits);
KUNIT_EXPECT_EQ(test, sr_entry->set_bits, param->expected_set_bits);
- KUNIT_EXPECT_EQ(test, sr_entry->reg_type, param->expected_reg.type);
+ KUNIT_EXPECT_EQ(test, sr_entry->reg.raw, param->expected_reg.raw);
KUNIT_EXPECT_EQ(test, reg_sr->errors, param->expected_sr_errors);
}
diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index 6a723bda2aa9..676137dcb510 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -461,7 +461,7 @@ static unsigned int guc_mmio_regset_write(struct xe_guc_ads *ads,
BUILD_BUG_ON(ARRAY_SIZE(extra_regs) > ADS_REGSET_EXTRA_MAX);
xa_for_each(&hwe->reg_sr.xa, idx, entry) {
- u32 flags = entry->masked_reg ? GUC_REGSET_MASKED : 0;
+ u32 flags = entry->reg.masked ? GUC_REGSET_MASKED : 0;
guc_mmio_regset_write_one(ads, regset_map, idx, flags, count++);
}
diff --git a/drivers/gpu/drm/xe/xe_reg_sr.c b/drivers/gpu/drm/xe/xe_reg_sr.c
index 78cb0e93a7ed..ff00e1b20548 100644
--- a/drivers/gpu/drm/xe/xe_reg_sr.c
+++ b/drivers/gpu/drm/xe/xe_reg_sr.c
@@ -77,10 +77,7 @@ static bool compatible_entries(const struct xe_reg_sr_entry *e1,
e1->clr_bits & e2->set_bits || e1->set_bits & e2->clr_bits)
return false;
- if (e1->masked_reg != e2->masked_reg)
- return false;
-
- if (e1->reg_type != e2->reg_type)
+ if (e1->reg.raw != e2->reg.raw)
return false;
return true;
@@ -93,10 +90,10 @@ static void reg_sr_inc_error(struct xe_reg_sr *sr)
#endif
}
-int xe_reg_sr_add(struct xe_reg_sr *sr, u32 reg,
+int xe_reg_sr_add(struct xe_reg_sr *sr, xe_reg_t reg,
const struct xe_reg_sr_entry *e)
{
- unsigned long idx = reg;
+ unsigned long idx = reg.reg;
struct xe_reg_sr_entry *pentry = xa_load(&sr->xa, idx);
int ret;
@@ -127,9 +124,11 @@ int xe_reg_sr_add(struct xe_reg_sr *sr, u32 reg,
return 0;
fail:
- DRM_ERROR("Discarding save-restore reg %04lx (clear: %08x, set: %08x, masked: %s): ret=%d\n",
+ DRM_ERROR("Discarding save-restore reg %04lx (clear: %08x, set: %08x, masked: %s, mcr: %s): ret=%d\n",
idx, e->clr_bits, e->set_bits,
- str_yes_no(e->masked_reg), ret);
+ str_yes_no(e->reg.masked),
+ str_yes_no(e->reg.mcr),
+ ret);
reg_sr_inc_error(sr);
return ret;
@@ -149,10 +148,10 @@ static void apply_one_mmio(struct xe_gt *gt, u32 reg,
* When it's not masked, we have to read it from hardware, unless we are
* supposed to set all bits.
*/
- if (entry->masked_reg)
+ if (entry->reg.masked)
val = (entry->clr_bits ?: entry->set_bits << 16);
else if (entry->clr_bits + 1)
- val = (entry->reg_type == XE_RTP_REG_MCR ?
+ val = (entry->reg.mcr ?
xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(reg)) :
xe_mmio_read32(gt, reg)) & (~entry->clr_bits);
else
@@ -167,7 +166,7 @@ static void apply_one_mmio(struct xe_gt *gt, u32 reg,
drm_dbg(&xe->drm, "REG[0x%x] = 0x%08x", reg, val);
- if (entry->reg_type == XE_RTP_REG_MCR)
+ if (entry->reg.mcr)
xe_gt_mcr_multicast_write(gt, XE_REG_MCR(reg), val);
else
xe_mmio_write32(gt, reg, val);
@@ -259,6 +258,6 @@ void xe_reg_sr_dump(struct xe_reg_sr *sr, struct drm_printer *p)
xa_for_each(&sr->xa, reg, entry)
drm_printf(p, "\tREG[0x%lx] clr=0x%08x set=0x%08x masked=%s mcr=%s\n",
reg, entry->clr_bits, entry->set_bits,
- str_yes_no(entry->masked_reg),
- str_yes_no(entry->reg_type == XE_RTP_REG_MCR));
+ str_yes_no(entry->reg.masked),
+ str_yes_no(entry->reg.mcr));
}
diff --git a/drivers/gpu/drm/xe/xe_reg_sr.h b/drivers/gpu/drm/xe/xe_reg_sr.h
index 3af369089faa..2bdea4d119fe 100644
--- a/drivers/gpu/drm/xe/xe_reg_sr.h
+++ b/drivers/gpu/drm/xe/xe_reg_sr.h
@@ -6,6 +6,7 @@
#ifndef _XE_REG_SR_
#define _XE_REG_SR_
+#include "regs/xe_reg_defs.h"
#include "xe_reg_sr_types.h"
/*
@@ -19,7 +20,7 @@ struct drm_printer;
int xe_reg_sr_init(struct xe_reg_sr *sr, const char *name, struct xe_device *xe);
void xe_reg_sr_dump(struct xe_reg_sr *sr, struct drm_printer *p);
-int xe_reg_sr_add(struct xe_reg_sr *sr, u32 reg,
+int xe_reg_sr_add(struct xe_reg_sr *sr, xe_reg_t reg,
const struct xe_reg_sr_entry *e);
void xe_reg_sr_apply_mmio(struct xe_reg_sr *sr, struct xe_gt *gt);
void xe_reg_sr_apply_whitelist(struct xe_reg_sr *sr, u32 mmio_base,
diff --git a/drivers/gpu/drm/xe/xe_reg_sr_types.h b/drivers/gpu/drm/xe/xe_reg_sr_types.h
index 91469784fd90..eefbe20c0a22 100644
--- a/drivers/gpu/drm/xe/xe_reg_sr_types.h
+++ b/drivers/gpu/drm/xe/xe_reg_sr_types.h
@@ -9,18 +9,14 @@
#include <linux/types.h>
#include <linux/xarray.h>
+#include "regs/xe_reg_defs.h"
+
struct xe_reg_sr_entry {
+ xe_reg_t reg;
u32 clr_bits;
u32 set_bits;
/* Mask for bits to consider when reading value back */
u32 read_mask;
- /*
- * "Masked registers" are marked in spec as register with the upper 16
- * bits as a mask for the bits that is being updated on the lower 16
- * bits when writing to it.
- */
- u8 masked_reg;
- u8 reg_type;
};
struct xe_reg_sr {
diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
index 310d5dfe30d5..e3e71b6060b2 100644
--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
+++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
@@ -11,11 +11,6 @@
#include "xe_platform_types.h"
#include "xe_rtp.h"
-#undef XE_REG
-#undef XE_REG_MCR
-#define XE_REG(x, ...) _XE_RTP_REG(x)
-#define XE_REG_MCR(x, ...) _XE_RTP_MCR_REG(x)
-
static bool match_not_render(const struct xe_gt *gt,
const struct xe_hw_engine *hwe)
{
diff --git a/drivers/gpu/drm/xe/xe_rtp.c b/drivers/gpu/drm/xe/xe_rtp.c
index 20acd43cb60b..b8c406b937df 100644
--- a/drivers/gpu/drm/xe/xe_rtp.c
+++ b/drivers/gpu/drm/xe/xe_rtp.c
@@ -94,15 +94,16 @@ static void rtp_add_sr_entry(const struct xe_rtp_action *action,
u32 mmio_base,
struct xe_reg_sr *sr)
{
- u32 reg = action->reg + mmio_base;
+ xe_reg_t reg = action->reg;
struct xe_reg_sr_entry sr_entry = {
.clr_bits = action->clr_bits,
.set_bits = action->set_bits,
.read_mask = action->read_mask,
- .masked_reg = action->flags & XE_RTP_ACTION_FLAG_MASKED_REG,
- .reg_type = action->reg_type,
};
+ reg.reg += mmio_base;
+ sr_entry.reg = reg;
+
xe_reg_sr_add(sr, reg, &sr_entry);
}
diff --git a/drivers/gpu/drm/xe/xe_rtp.h b/drivers/gpu/drm/xe/xe_rtp.h
index 9148f32baa02..ca458e4b0d3c 100644
--- a/drivers/gpu/drm/xe/xe_rtp.h
+++ b/drivers/gpu/drm/xe/xe_rtp.h
@@ -42,8 +42,8 @@ struct xe_reg_sr;
#define __XE_PASTE_3(prefix_, sep_, args_) prefix_(_XE_FIRST args_) __XE_PASTE_SEP_ ## sep_ __XE_PASTE_2(prefix_, sep_, _XE_TUPLE_TAIL args_)
#define __XE_PASTE_4(prefix_, sep_, args_) prefix_(_XE_FIRST args_) __XE_PASTE_SEP_ ## sep_ __XE_PASTE_3(prefix_, sep_, _XE_TUPLE_TAIL args_)
-#define _XE_RTP_REG(x_) (x_), XE_RTP_REG_REGULAR
-#define _XE_RTP_MCR_REG(x_) (x_), XE_RTP_REG_MCR
+#define _XE_DROP_FIRST(x_, ...) __VA_ARGS__
+#define _XE_DROP_CAST(...) _XE_ESC(_XE_DROP_FIRST _XE_ESC __VA_ARGS__)
/*
* Helper macros for concatenating prefix - do not use them directly outside
@@ -196,7 +196,6 @@ struct xe_reg_sr;
* XE_RTP_ACTION_WR - Helper to write a value to the register, overriding all
* the bits
* @reg_: Register
- * @reg_type_: Register type - automatically expanded by XE_REG
* @val_: Value to set
* @...: Additional fields to override in the struct xe_rtp_action entry
*
@@ -204,15 +203,14 @@ struct xe_reg_sr;
*
* REGNAME = VALUE
*/
-#define XE_RTP_ACTION_WR(reg_, reg_type_, val_, ...) \
- { .reg = (reg_), .reg_type = (reg_type_), \
+#define XE_RTP_ACTION_WR(reg_, val_, ...) \
+ { .reg = _XE_DROP_CAST(reg_), \
.clr_bits = ~0u, .set_bits = (val_), \
.read_mask = (~0u), ##__VA_ARGS__ }
/**
* XE_RTP_ACTION_SET - Set bits from @val_ in the register.
* @reg_: Register
- * @reg_type_: Register type - automatically expanded by XE_REG
* @val_: Bits to set in the register
* @...: Additional fields to override in the struct xe_rtp_action entry
*
@@ -223,15 +221,14 @@ struct xe_reg_sr;
* REGNAME[2] = 1
* REGNAME[5] = 1
*/
-#define XE_RTP_ACTION_SET(reg_, reg_type_, val_, ...) \
- { .reg = (reg_), .reg_type = (reg_type_), \
- .clr_bits = (val_), .set_bits = (val_), \
- .read_mask = (val_), ##__VA_ARGS__ }
+#define XE_RTP_ACTION_SET(reg_, val_, ...) \
+ { .reg = _XE_DROP_CAST(reg_), \
+ .clr_bits = val_, .set_bits = val_, \
+ .read_mask = val_, ##__VA_ARGS__ }
/**
* XE_RTP_ACTION_CLR: Clear bits from @val_ in the register.
* @reg_: Register
- * @reg_type_: Register type - automatically expanded by XE_REG
* @val_: Bits to clear in the register
* @...: Additional fields to override in the struct xe_rtp_action entry
*
@@ -242,15 +239,14 @@ struct xe_reg_sr;
* REGNAME[2] = 0
* REGNAME[5] = 0
*/
-#define XE_RTP_ACTION_CLR(reg_, reg_type_, val_, ...) \
- { .reg = (reg_), .reg_type = (reg_type_), \
- .clr_bits = (val_), .set_bits = 0, \
- .read_mask = (val_), ##__VA_ARGS__ }
+#define XE_RTP_ACTION_CLR(reg_, val_, ...) \
+ { .reg = _XE_DROP_CAST(reg_), \
+ .clr_bits = val_, .set_bits = 0, \
+ .read_mask = val_, ##__VA_ARGS__ }
/**
* XE_RTP_ACTION_FIELD_SET: Set a bit range
* @reg_: Register
- * @reg_type_: Register type - automatically expanded by XE_REG
* @mask_bits_: Mask of bits to be changed in the register, forming a field
* @val_: Value to set in the field denoted by @mask_bits_
* @...: Additional fields to override in the struct xe_rtp_action entry
@@ -260,29 +256,29 @@ struct xe_reg_sr;
*
* REGNAME[<end>:<start>] = VALUE
*/
-#define XE_RTP_ACTION_FIELD_SET(reg_, reg_type_, mask_bits_, val_, ...) \
- { .reg = (reg_), .reg_type = (reg_type_), \
- .clr_bits = (mask_bits_), .set_bits = (val_), \
- .read_mask = (mask_bits_), ##__VA_ARGS__ }
+#define XE_RTP_ACTION_FIELD_SET(reg_, mask_bits_, val_, ...) \
+ { .reg = _XE_DROP_CAST(reg_), \
+ .clr_bits = mask_bits_, .set_bits = val_, \
+ .read_mask = mask_bits_, ##__VA_ARGS__ }
-#define XE_RTP_ACTION_FIELD_SET_NO_READ_MASK(reg_, reg_type_, mask_bits_, val_, ...) \
- { .reg = (reg_), .reg_type = (reg_type_), \
+#define XE_RTP_ACTION_FIELD_SET_NO_READ_MASK(reg_, mask_bits_, val_, ...) \
+ { .reg = _XE_DROP_CAST(reg_), \
.clr_bits = (mask_bits_), .set_bits = (val_), \
.read_mask = 0, ##__VA_ARGS__ }
/**
* XE_RTP_ACTION_WHITELIST - Add register to userspace whitelist
* @reg_: Register
- * @reg_type_: Register type - automatically expanded by XE_REG
* @val_: Whitelist-specific flags to set
* @...: Additional fields to override in the struct xe_rtp_action entry
*
* Add a register to the whitelist, allowing userspace to modify the ster with
* regular user privileges.
*/
-#define XE_RTP_ACTION_WHITELIST(reg_, reg_type_, val_, ...) \
+#define XE_RTP_ACTION_WHITELIST(reg_, val_, ...) \
/* TODO fail build if ((flags) & ~(RING_FORCE_TO_NONPRIV_MASK_VALID)) */\
- { .reg = (reg_), .reg_type = (reg_type_), .set_bits = (val_), \
+ { .reg = _XE_DROP_CAST(reg_), \
+ .set_bits = val_, \
.clr_bits = RING_FORCE_TO_NONPRIV_MASK_VALID, \
##__VA_ARGS__ }
diff --git a/drivers/gpu/drm/xe/xe_rtp_types.h b/drivers/gpu/drm/xe/xe_rtp_types.h
index e87f1b280d96..4ad6b5453992 100644
--- a/drivers/gpu/drm/xe/xe_rtp_types.h
+++ b/drivers/gpu/drm/xe/xe_rtp_types.h
@@ -8,14 +8,11 @@
#include <linux/types.h>
+#include "regs/xe_reg_defs.h"
+
struct xe_hw_engine;
struct xe_gt;
-enum {
- XE_RTP_REG_REGULAR,
- XE_RTP_REG_MCR,
-};
-
/**
* struct xe_rtp_action - action to take for any matching rule
*
@@ -24,7 +21,7 @@ enum {
*/
struct xe_rtp_action {
/** @reg: Register */
- u32 reg;
+ xe_reg_t reg;
/** @clr_bits: bits to clear when updating register */
u32 clr_bits;
/** @set_bits: bits to set when updating register */
@@ -32,12 +29,9 @@ struct xe_rtp_action {
#define XE_RTP_NOCHECK .read_mask = 0
/** @read_mask: mask for bits to consider when reading value back */
u32 read_mask;
-#define XE_RTP_ACTION_FLAG_MASKED_REG BIT(0)
-#define XE_RTP_ACTION_FLAG_ENGINE_BASE BIT(1)
+#define XE_RTP_ACTION_FLAG_ENGINE_BASE BIT(0)
/** @flags: flags to apply on rule evaluation or action */
u8 flags;
- /** @reg_type: register type, see ``XE_RTP_REG_*`` */
- u8 reg_type;
};
enum {
diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
index f6eefa951175..041593387efc 100644
--- a/drivers/gpu/drm/xe/xe_tuning.c
+++ b/drivers/gpu/drm/xe/xe_tuning.c
@@ -12,11 +12,6 @@
#include "xe_platform_types.h"
#include "xe_rtp.h"
-#undef XE_REG
-#undef XE_REG_MCR
-#define XE_REG(x, ...) _XE_RTP_REG(x)
-#define XE_REG_MCR(x, ...) _XE_RTP_MCR_REG(x)
-
static const struct xe_rtp_entry gt_tunings[] = {
{ XE_RTP_NAME("Tuning: Blend Fill Caching Optimization Disable"),
XE_RTP_RULES(PLATFORM(DG2)),
@@ -54,8 +49,7 @@ static const struct xe_rtp_entry lrc_tunings[] = {
},
{ XE_RTP_NAME("Tuning: TBIMR fast clip"),
XE_RTP_RULES(PLATFORM(DG2)),
- XE_RTP_ACTIONS(SET(CHICKEN_RASTER_2, TBIMR_FAST_CLIP,
- XE_RTP_ACTION_FLAG(MASKED_REG)))
+ XE_RTP_ACTIONS(SET(CHICKEN_RASTER_2, TBIMR_FAST_CLIP))
},
{}
};
diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index b7dc71f63c8a..21ef74873553 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -87,11 +87,6 @@
* a more declarative approach rather than procedural.
*/
-#undef XE_REG
-#undef XE_REG_MCR
-#define XE_REG(x, ...) _XE_RTP_REG(x)
-#define XE_REG_MCR(x, ...) _XE_RTP_MCR_REG(x)
-
__diag_push();
__diag_ignore_all("-Woverride-init", "Allow field overrides in table");
@@ -232,8 +227,7 @@ static const struct xe_rtp_entry gt_was[] = {
},
{ XE_RTP_NAME("16016694945"),
XE_RTP_RULES(PLATFORM(PVC)),
- XE_RTP_ACTIONS(SET(XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC,
- XE_RTP_ACTION_FLAG(MASKED_REG)))
+ XE_RTP_ACTIONS(SET(XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC))
},
{}
};
@@ -248,36 +242,30 @@ static const struct xe_rtp_entry engine_was[] = {
XE_RTP_RULES(GRAPHICS_VERSION(1200),
ENGINE_CLASS(RENDER),
IS_INTEGRATED),
- XE_RTP_ACTIONS(SET(ROW_CHICKEN2, PUSH_CONST_DEREF_HOLD_DIS,
- XE_RTP_ACTION_FLAG(MASKED_REG)))
+ XE_RTP_ACTIONS(SET(ROW_CHICKEN2, PUSH_CONST_DEREF_HOLD_DIS))
},
{ XE_RTP_NAME("14010229206, 1409085225"),
XE_RTP_RULES(GRAPHICS_VERSION(1200),
ENGINE_CLASS(RENDER),
IS_INTEGRATED),
- XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH,
- XE_RTP_ACTION_FLAG(MASKED_REG)))
+ XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH))
},
{ XE_RTP_NAME("1606931601"),
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
- XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_EARLY_READ,
- XE_RTP_ACTION_FLAG(MASKED_REG)))
+ XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_EARLY_READ))
},
{ XE_RTP_NAME("14010826681, 1606700617, 22010271021, 18019627453"),
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1255), ENGINE_CLASS(RENDER)),
- XE_RTP_ACTIONS(SET(CS_DEBUG_MODE1, FF_DOP_CLOCK_GATE_DISABLE,
- XE_RTP_ACTION_FLAG(MASKED_REG)))
+ XE_RTP_ACTIONS(SET(CS_DEBUG_MODE1, FF_DOP_CLOCK_GATE_DISABLE))
},
{ XE_RTP_NAME("1406941453"),
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
- XE_RTP_ACTIONS(SET(SAMPLER_MODE, ENABLE_SMALLPL,
- XE_RTP_ACTION_FLAG(MASKED_REG)))
+ XE_RTP_ACTIONS(SET(SAMPLER_MODE, ENABLE_SMALLPL))
},
{ XE_RTP_NAME("FtrPerCtxtPreemptionGranularityControl"),
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1250), ENGINE_CLASS(RENDER)),
XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN1,
- FFSC_PERCTX_PREEMPT_CTRL,
- XE_RTP_ACTION_FLAG(MASKED_REG)))
+ FFSC_PERCTX_PREEMPT_CTRL))
},
/* TGL */
@@ -286,8 +274,7 @@ static const struct xe_rtp_entry engine_was[] = {
XE_RTP_RULES(PLATFORM(TIGERLAKE), ENGINE_CLASS(RENDER)),
XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
- RC_SEMA_IDLE_MSG_DISABLE,
- XE_RTP_ACTION_FLAG(MASKED_REG)))
+ RC_SEMA_IDLE_MSG_DISABLE))
},
/* RKL */
@@ -296,8 +283,7 @@ static const struct xe_rtp_entry engine_was[] = {
XE_RTP_RULES(PLATFORM(ROCKETLAKE), ENGINE_CLASS(RENDER)),
XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
- RC_SEMA_IDLE_MSG_DISABLE,
- XE_RTP_ACTION_FLAG(MASKED_REG)))
+ RC_SEMA_IDLE_MSG_DISABLE))
},
/* ADL-P */
@@ -306,8 +292,7 @@ static const struct xe_rtp_entry engine_was[] = {
XE_RTP_RULES(PLATFORM(ALDERLAKE_P), ENGINE_CLASS(RENDER)),
XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
- RC_SEMA_IDLE_MSG_DISABLE,
- XE_RTP_ACTION_FLAG(MASKED_REG)))
+ RC_SEMA_IDLE_MSG_DISABLE))
},
/* DG2 */
@@ -324,8 +309,7 @@ static const struct xe_rtp_entry engine_was[] = {
{ XE_RTP_NAME("18017747507"),
XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
XE_RTP_ACTIONS(SET(VFG_PREEMPTION_CHICKEN,
- POLYGON_TRIFAN_LINELOOP_DISABLE,
- XE_RTP_ACTION_FLAG(MASKED_REG)))
+ POLYGON_TRIFAN_LINELOOP_DISABLE))
},
{ XE_RTP_NAME("22012826095, 22013059131"),
XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(B0, C0),
@@ -366,15 +350,13 @@ static const struct xe_rtp_entry engine_was[] = {
{ XE_RTP_NAME("14015227452"),
XE_RTP_RULES(PLATFORM(DG2),
FUNC(xe_rtp_match_first_render_or_compute)),
- XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE,
- XE_RTP_ACTION_FLAG(MASKED_REG)))
+ XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE))
},
{ XE_RTP_NAME("16015675438"),
XE_RTP_RULES(PLATFORM(DG2),
FUNC(xe_rtp_match_first_render_or_compute)),
XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN2,
- PERF_FIX_BALANCING_CFE_DISABLE,
- XE_RTP_ACTION_FLAG(MASKED_REG)))
+ PERF_FIX_BALANCING_CFE_DISABLE))
},
{ XE_RTP_NAME("16011620976, 22015475538"),
XE_RTP_RULES(PLATFORM(DG2),
@@ -385,7 +367,6 @@ static const struct xe_rtp_entry engine_was[] = {
XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, C0),
FUNC(xe_rtp_match_first_render_or_compute)),
XE_RTP_ACTIONS(SET(CACHE_MODE_SS, ENABLE_PREFETCH_INTO_IC,
- XE_RTP_ACTION_FLAG(MASKED_REG),
/*
* Register can't be read back for verification on
* DG2 due to Wa_14012342262
@@ -396,7 +377,6 @@ static const struct xe_rtp_entry engine_was[] = {
XE_RTP_RULES(SUBPLATFORM(DG2, G11),
FUNC(xe_rtp_match_first_render_or_compute)),
XE_RTP_ACTIONS(SET(CACHE_MODE_SS, ENABLE_PREFETCH_INTO_IC,
- XE_RTP_ACTION_FLAG(MASKED_REG),
/*
* Register can't be read back for verification on
* DG2 due to Wa_14012342262
@@ -405,55 +385,46 @@ static const struct xe_rtp_entry engine_was[] = {
},
{ XE_RTP_NAME("1509727124"),
XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
- XE_RTP_ACTIONS(SET(SAMPLER_MODE, SC_DISABLE_POWER_OPTIMIZATION_EBB,
- XE_RTP_ACTION_FLAG(MASKED_REG)))
+ XE_RTP_ACTIONS(SET(SAMPLER_MODE, SC_DISABLE_POWER_OPTIMIZATION_EBB))
},
{ XE_RTP_NAME("22012856258"),
XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
- XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_READ_SUPPRESSION,
- XE_RTP_ACTION_FLAG(MASKED_REG)))
+ XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_READ_SUPPRESSION))
},
{ XE_RTP_NAME("14013392000"),
XE_RTP_RULES(SUBPLATFORM(DG2, G11), STEP(A0, B0), ENGINE_CLASS(RENDER)),
- XE_RTP_ACTIONS(SET(ROW_CHICKEN2, ENABLE_LARGE_GRF_MODE,
- XE_RTP_ACTION_FLAG(MASKED_REG)))
+ XE_RTP_ACTIONS(SET(ROW_CHICKEN2, ENABLE_LARGE_GRF_MODE))
},
{ XE_RTP_NAME("14012419201"),
XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, B0), ENGINE_CLASS(RENDER)),
XE_RTP_ACTIONS(SET(ROW_CHICKEN4,
- DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX,
- XE_RTP_ACTION_FLAG(MASKED_REG)))
+ DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX))
},
{ XE_RTP_NAME("14012419201"),
XE_RTP_RULES(SUBPLATFORM(DG2, G11), STEP(A0, B0), ENGINE_CLASS(RENDER)),
XE_RTP_ACTIONS(SET(ROW_CHICKEN4,
- DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX,
- XE_RTP_ACTION_FLAG(MASKED_REG)))
+ DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX))
},
{ XE_RTP_NAME("1308578152"),
XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(B0, C0), ENGINE_CLASS(RENDER),
FUNC(xe_rtp_match_first_gslice_fused_off)),
XE_RTP_ACTIONS(CLR(CS_DEBUG_MODE1,
- REPLAY_MODE_GRANULARITY,
- XE_RTP_ACTION_FLAG(MASKED_REG)))
+ REPLAY_MODE_GRANULARITY))
},
{ XE_RTP_NAME("22010960976, 14013347512"),
XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
XE_RTP_ACTIONS(CLR(XEHP_HDC_CHICKEN0,
- LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK,
- XE_RTP_ACTION_FLAG(MASKED_REG)))
+ LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK))
},
{ XE_RTP_NAME("1608949956, 14010198302"),
XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
XE_RTP_ACTIONS(SET(ROW_CHICKEN,
- MDQ_ARBITRATION_MODE | UGM_BACKUP_MODE,
- XE_RTP_ACTION_FLAG(MASKED_REG)))
+ MDQ_ARBITRATION_MODE | UGM_BACKUP_MODE))
},
{ XE_RTP_NAME("22010430635"),
XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, B0), ENGINE_CLASS(RENDER)),
XE_RTP_ACTIONS(SET(ROW_CHICKEN4,
- DISABLE_GRF_CLEAR,
- XE_RTP_ACTION_FLAG(MASKED_REG)))
+ DISABLE_GRF_CLEAR))
},
{ XE_RTP_NAME("14013202645"),
XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(B0, C0), ENGINE_CLASS(RENDER)),
@@ -466,21 +437,18 @@ static const struct xe_rtp_entry engine_was[] = {
{ XE_RTP_NAME("22012532006"),
XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, C0), ENGINE_CLASS(RENDER)),
XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7,
- DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA,
- XE_RTP_ACTION_FLAG(MASKED_REG)))
+ DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA))
},
{ XE_RTP_NAME("22012532006"),
XE_RTP_RULES(SUBPLATFORM(DG2, G11), STEP(A0, B0), ENGINE_CLASS(RENDER)),
XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7,
- DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA,
- XE_RTP_ACTION_FLAG(MASKED_REG)))
+ DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA))
},
{ XE_RTP_NAME("22014600077"),
XE_RTP_RULES(SUBPLATFORM(DG2, G11), STEP(B0, FOREVER),
ENGINE_CLASS(RENDER)),
XE_RTP_ACTIONS(SET(CACHE_MODE_SS,
ENABLE_EU_COUNT_FOR_TDL_FLUSH,
- XE_RTP_ACTION_FLAG(MASKED_REG),
/*
* Wa_14012342262 write-only reg, so skip
* verification
@@ -491,7 +459,6 @@ static const struct xe_rtp_entry engine_was[] = {
XE_RTP_RULES(SUBPLATFORM(DG2, G10), ENGINE_CLASS(RENDER)),
XE_RTP_ACTIONS(SET(CACHE_MODE_SS,
ENABLE_EU_COUNT_FOR_TDL_FLUSH,
- XE_RTP_ACTION_FLAG(MASKED_REG),
/*
* Wa_14012342262 write-only reg, so skip
* verification
@@ -507,18 +474,15 @@ static const struct xe_rtp_entry engine_was[] = {
},
{ XE_RTP_NAME("14015227452"),
XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)),
- XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE,
- XE_RTP_ACTION_FLAG(MASKED_REG)))
+ XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE))
},
{ XE_RTP_NAME("16015675438"),
XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)),
- XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN2, PERF_FIX_BALANCING_CFE_DISABLE,
- XE_RTP_ACTION_FLAG(MASKED_REG)))
+ XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN2, PERF_FIX_BALANCING_CFE_DISABLE))
},
{ XE_RTP_NAME("14014999345"),
XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COMPUTE), STEP(B0, C0)),
- XE_RTP_ACTIONS(SET(CACHE_MODE_SS, DISABLE_ECC,
- XE_RTP_ACTION_FLAG(MASKED_REG)))
+ XE_RTP_ACTIONS(SET(CACHE_MODE_SS, DISABLE_ECC))
},
{}
};
@@ -527,25 +491,21 @@ static const struct xe_rtp_entry lrc_was[] = {
{ XE_RTP_NAME("1409342910, 14010698770, 14010443199, 1408979724, 1409178076, 1409207793, 1409217633, 1409252684, 1409347922, 1409142259"),
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN3,
- DISABLE_CPS_AWARE_COLOR_PIPE,
- XE_RTP_ACTION_FLAG(MASKED_REG)))
+ DISABLE_CPS_AWARE_COLOR_PIPE))
},
{ XE_RTP_NAME("WaDisableGPGPUMidThreadPreemption"),
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1,
PREEMPT_GPGPU_LEVEL_MASK,
- PREEMPT_GPGPU_THREAD_GROUP_LEVEL,
- XE_RTP_ACTION_FLAG(MASKED_REG)))
+ PREEMPT_GPGPU_THREAD_GROUP_LEVEL))
},
{ XE_RTP_NAME("1806527549"),
XE_RTP_RULES(GRAPHICS_VERSION(1200)),
- XE_RTP_ACTIONS(SET(HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE,
- XE_RTP_ACTION_FLAG(MASKED_REG)))
+ XE_RTP_ACTIONS(SET(HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE))
},
{ XE_RTP_NAME("1606376872"),
XE_RTP_RULES(GRAPHICS_VERSION(1200)),
- XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC,
- XE_RTP_ACTION_FLAG(MASKED_REG)))
+ XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC))
},
/* DG1 */
@@ -553,65 +513,54 @@ static const struct xe_rtp_entry lrc_was[] = {
{ XE_RTP_NAME("1409044764"),
XE_RTP_RULES(PLATFORM(DG1)),
XE_RTP_ACTIONS(CLR(COMMON_SLICE_CHICKEN3,
- DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN,
- XE_RTP_ACTION_FLAG(MASKED_REG)))
+ DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN))
},
{ XE_RTP_NAME("22010493298"),
XE_RTP_RULES(PLATFORM(DG1)),
XE_RTP_ACTIONS(SET(HIZ_CHICKEN,
- DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE,
- XE_RTP_ACTION_FLAG(MASKED_REG)))
+ DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE))
},
/* DG2 */
{ XE_RTP_NAME("16011186671"),
XE_RTP_RULES(SUBPLATFORM(DG2, G11), STEP(A0, B0)),
- XE_RTP_ACTIONS(CLR(VFLSKPD, DIS_MULT_MISS_RD_SQUASH,
- .flags = XE_RTP_ACTION_FLAG_MASKED_REG),
- SET(VFLSKPD, DIS_OVER_FETCH_CACHE,
- .flags = XE_RTP_ACTION_FLAG_MASKED_REG))
+ XE_RTP_ACTIONS(CLR(VFLSKPD, DIS_MULT_MISS_RD_SQUASH),
+ SET(VFLSKPD, DIS_OVER_FETCH_CACHE))
},
{ XE_RTP_NAME("14010469329"),
XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, B0)),
XE_RTP_ACTIONS(SET(XEHP_COMMON_SLICE_CHICKEN3,
- XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE,
- XE_RTP_ACTION_FLAG(MASKED_REG)))
+ XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE))
},
{ XE_RTP_NAME("14010698770, 22010613112, 22010465075"),
XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, B0)),
XE_RTP_ACTIONS(SET(XEHP_COMMON_SLICE_CHICKEN3,
- DISABLE_CPS_AWARE_COLOR_PIPE,
- XE_RTP_ACTION_FLAG(MASKED_REG)))
+ DISABLE_CPS_AWARE_COLOR_PIPE))
},
{ XE_RTP_NAME("16013271637"),
XE_RTP_RULES(PLATFORM(DG2)),
XE_RTP_ACTIONS(SET(XEHP_SLICE_COMMON_ECO_CHICKEN1,
- MSC_MSAA_REODER_BUF_BYPASS_DISABLE,
- XE_RTP_ACTION_FLAG(MASKED_REG)))
+ MSC_MSAA_REODER_BUF_BYPASS_DISABLE))
},
{ XE_RTP_NAME("14014947963"),
XE_RTP_RULES(PLATFORM(DG2)),
XE_RTP_ACTIONS(FIELD_SET(VF_PREEMPTION,
PREEMPTION_VERTEX_COUNT,
- 0x4000,
- XE_RTP_ACTION_FLAG(MASKED_REG)))
+ 0x4000))
},
{ XE_RTP_NAME("18018764978"),
XE_RTP_RULES(PLATFORM(DG2)),
XE_RTP_ACTIONS(SET(XEHP_PSS_MODE2,
- SCOREBOARD_STALL_FLUSH_CONTROL,
- XE_RTP_ACTION_FLAG(MASKED_REG)))
+ SCOREBOARD_STALL_FLUSH_CONTROL))
},
{ XE_RTP_NAME("15010599737"),
XE_RTP_RULES(PLATFORM(DG2)),
- XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN,
- XE_RTP_ACTION_FLAG(MASKED_REG)))
+ XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN))
},
{ XE_RTP_NAME("18019271663"),
XE_RTP_RULES(PLATFORM(DG2)),
- XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE,
- XE_RTP_ACTION_FLAG(MASKED_REG)))
+ XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE))
},
{}
};
--
2.39.0
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Intel-xe] [PATCH 17/17] drm/xe: Move helper macros to separate header
2023-04-19 7:44 [Intel-xe] [PATCH 00/17] Cleanup registers and introduce xe_reg_t Lucas De Marchi
` (15 preceding siblings ...)
2023-04-19 7:44 ` [Intel-xe] [PATCH 16/17] drm/xe: Plumb xe_reg_t into WAs, rtp, etc Lucas De Marchi
@ 2023-04-19 7:44 ` Lucas De Marchi
2023-04-19 16:17 ` Jani Nikula
2023-04-19 7:47 ` [Intel-xe] ✓ CI.Patch_applied: success for Cleanup registers and introduce xe_reg_t Patchwork
` (3 subsequent siblings)
20 siblings, 1 reply; 41+ messages in thread
From: Lucas De Marchi @ 2023-04-19 7:44 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, Matt Roper, Rodrigo Vivi
The macros to handle the RTP tables are very scary, but shouldn't be
used outside of the header adding the infra. Move it to a separate
header and make sure it's only included when it can be.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/Makefile | 2 +-
drivers/gpu/drm/xe/tests/xe_rtp_test.c | 2 +-
drivers/gpu/drm/xe/xe_rtp.h | 40 +++------------------
drivers/gpu/drm/xe/xe_rtp_helpers.h | 48 ++++++++++++++++++++++++++
4 files changed, 55 insertions(+), 37 deletions(-)
create mode 100644 drivers/gpu/drm/xe/xe_rtp_helpers.h
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index aceca651de57..f3c38815011e 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -225,7 +225,7 @@ endif
# header test
always-$(CONFIG_DRM_XE_WERROR) += \
- $(patsubst %.h,%.hdrtest, $(shell cd $(srctree)/$(src) && find * -name '*.h' $(skipdisplay)))
+ $(patsubst %.h,%.hdrtest, $(shell cd $(srctree)/$(src) && find * -name '*.h' -not -path xe_rtp_helpers.h $(skipdisplay)))
quiet_cmd_hdrtest = HDRTEST $(patsubst %.hdrtest,%.h,$@)
cmd_hdrtest = $(CC) -DHDRTEST $(filter-out $(CFLAGS_GCOV), $(c_flags)) $(cflags-display) -S -o /dev/null -x c /dev/null -include $<; touch $@
diff --git a/drivers/gpu/drm/xe/tests/xe_rtp_test.c b/drivers/gpu/drm/xe/tests/xe_rtp_test.c
index ad917638d088..a5ec9ae22156 100644
--- a/drivers/gpu/drm/xe/tests/xe_rtp_test.c
+++ b/drivers/gpu/drm/xe/tests/xe_rtp_test.c
@@ -57,7 +57,7 @@ static const struct rtp_test_case cases[] = {
.entries = (const struct xe_rtp_entry[]) {
{ XE_RTP_NAME("basic-1"),
XE_RTP_RULES(FUNC(match_yes)),
- XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(1)))
+ XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
},
{ XE_RTP_NAME("basic-2"),
XE_RTP_RULES(FUNC(match_yes)),
diff --git a/drivers/gpu/drm/xe/xe_rtp.h b/drivers/gpu/drm/xe/xe_rtp.h
index ca458e4b0d3c..7242342f4971 100644
--- a/drivers/gpu/drm/xe/xe_rtp.h
+++ b/drivers/gpu/drm/xe/xe_rtp.h
@@ -9,8 +9,13 @@
#include <linux/types.h>
#include <linux/xarray.h>
+#define _XE_RTP_INCLUDE_PRIVATE_HELPERS
+
+#include "xe_rtp_helpers.h"
#include "xe_rtp_types.h"
+#undef _XE_RTP_INCLUDE_PRIVATE_HELPERS
+
/*
* Register table poke infrastructure
*/
@@ -19,41 +24,6 @@ struct xe_hw_engine;
struct xe_gt;
struct xe_reg_sr;
-/*
- * Helper macros - not to be used outside this header.
- */
-#define _XE_ESC(...) __VA_ARGS__
-#define _XE_COUNT_ARGS(...) _XE_ESC(__XE_COUNT_ARGS(__VA_ARGS__,5,4,3,2,1,))
-#define __XE_COUNT_ARGS(_,_5,_4,_3,_2,X_,...) X_
-
-#define _XE_CONCAT(a, b) __XE_CONCAT(a, b)
-#define __XE_CONCAT(a, b) a ## b
-
-#define _XE_FIRST(...) _XE_ESC(__XE_FIRST(__VA_ARGS__,))
-#define __XE_FIRST(x_,...) x_
-#define _XE_TUPLE_TAIL(...) _XE_ESC(__XE_TUPLE_TAIL(__VA_ARGS__))
-#define __XE_TUPLE_TAIL(x_,...) (__VA_ARGS__)
-
-#define __XE_PASTE_SEP_COMMA ,
-#define __XE_PASTE_SEP_BITWISE_OR |
-#define __XE_PASTE(prefix_, sep_, args_) _XE_ESC(_XE_CONCAT(__XE_PASTE_,_XE_COUNT_ARGS args_)(prefix_, sep_, args_))
-#define __XE_PASTE_1(prefix_, sep_, args_) prefix_ args_
-#define __XE_PASTE_2(prefix_, sep_, args_) prefix_(_XE_FIRST args_) __XE_PASTE_SEP_ ## sep_ __XE_PASTE_1(prefix_, sep_, _XE_TUPLE_TAIL args_)
-#define __XE_PASTE_3(prefix_, sep_, args_) prefix_(_XE_FIRST args_) __XE_PASTE_SEP_ ## sep_ __XE_PASTE_2(prefix_, sep_, _XE_TUPLE_TAIL args_)
-#define __XE_PASTE_4(prefix_, sep_, args_) prefix_(_XE_FIRST args_) __XE_PASTE_SEP_ ## sep_ __XE_PASTE_3(prefix_, sep_, _XE_TUPLE_TAIL args_)
-
-#define _XE_DROP_FIRST(x_, ...) __VA_ARGS__
-#define _XE_DROP_CAST(...) _XE_ESC(_XE_DROP_FIRST _XE_ESC __VA_ARGS__)
-
-/*
- * Helper macros for concatenating prefix - do not use them directly outside
- * this header
- */
-#define __XE_PASTE_XE_RTP_ENTRY_FLAG_(x_) _XE_CONCAT(XE_RTP_ENTRY_FLAG_, x_)
-#define __XE_PASTE_XE_RTP_ACTION_FLAG_(x_) _XE_CONCAT(XE_RTP_ACTION_FLAG_, x_)
-#define __XE_PASTE_XE_RTP_ACTION_(x_) _XE_CONCAT(XE_RTP_ACTION_, x_)
-#define __XE_PASTE_XE_RTP_RULE_(x_) _XE_CONCAT(XE_RTP_RULE_, x_)
-
/*
* Macros to encode rules to match against platform, IP version, stepping, etc.
* Shouldn't be used directly - see XE_RTP_RULES()
diff --git a/drivers/gpu/drm/xe/xe_rtp_helpers.h b/drivers/gpu/drm/xe/xe_rtp_helpers.h
new file mode 100644
index 000000000000..0f0635692254
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_rtp_helpers.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#ifndef _XE_RTP_HELPERS_
+#define _XE_RTP_HELPERS_
+
+#ifndef _XE_RTP_INCLUDE_PRIVATE_HELPERS
+#error "This header is supposed to be included by xe_rtp.h only"
+#endif
+
+/*
+ * Helper macros - not to be used outside xe_rtp.h/xe_rtp_helpers.h
+ */
+#define _XE_ESC(...) __VA_ARGS__
+#define _XE_COUNT_ARGS(...) _XE_ESC(__XE_COUNT_ARGS(__VA_ARGS__,5,4,3,2,1,))
+#define __XE_COUNT_ARGS(_,_5,_4,_3,_2,X_,...) X_
+
+#define _XE_CONCAT(a, b) __XE_CONCAT(a, b)
+#define __XE_CONCAT(a, b) a ## b
+
+#define _XE_FIRST(...) _XE_ESC(__XE_FIRST(__VA_ARGS__,))
+#define __XE_FIRST(x_,...) x_
+#define _XE_TUPLE_TAIL(...) _XE_ESC(__XE_TUPLE_TAIL(__VA_ARGS__))
+#define __XE_TUPLE_TAIL(x_,...) (__VA_ARGS__)
+
+#define __XE_PASTE_SEP_COMMA ,
+#define __XE_PASTE_SEP_BITWISE_OR |
+#define __XE_PASTE(prefix_, sep_, args_) _XE_ESC(_XE_CONCAT(__XE_PASTE_,_XE_COUNT_ARGS args_)(prefix_, sep_, args_))
+#define __XE_PASTE_1(prefix_, sep_, args_) prefix_ args_
+#define __XE_PASTE_2(prefix_, sep_, args_) prefix_(_XE_FIRST args_) __XE_PASTE_SEP_ ## sep_ __XE_PASTE_1(prefix_, sep_, _XE_TUPLE_TAIL args_)
+#define __XE_PASTE_3(prefix_, sep_, args_) prefix_(_XE_FIRST args_) __XE_PASTE_SEP_ ## sep_ __XE_PASTE_2(prefix_, sep_, _XE_TUPLE_TAIL args_)
+#define __XE_PASTE_4(prefix_, sep_, args_) prefix_(_XE_FIRST args_) __XE_PASTE_SEP_ ## sep_ __XE_PASTE_3(prefix_, sep_, _XE_TUPLE_TAIL args_)
+
+#define _XE_DROP_FIRST(x_, ...) __VA_ARGS__
+#define _XE_DROP_CAST(...) _XE_ESC(_XE_DROP_FIRST _XE_ESC __VA_ARGS__)
+
+/*
+ * Helper macros for concatenating prefix - do not use them directly outside
+ * this header
+ */
+#define __XE_PASTE_XE_RTP_ENTRY_FLAG_(x_) _XE_CONCAT(XE_RTP_ENTRY_FLAG_, x_)
+#define __XE_PASTE_XE_RTP_ACTION_FLAG_(x_) _XE_CONCAT(XE_RTP_ACTION_FLAG_, x_)
+#define __XE_PASTE_XE_RTP_ACTION_(x_) _XE_CONCAT(XE_RTP_ACTION_, x_)
+#define __XE_PASTE_XE_RTP_RULE_(x_) _XE_CONCAT(XE_RTP_RULE_, x_)
+
+#endif
--
2.39.0
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Intel-xe] ✓ CI.Patch_applied: success for Cleanup registers and introduce xe_reg_t
2023-04-19 7:44 [Intel-xe] [PATCH 00/17] Cleanup registers and introduce xe_reg_t Lucas De Marchi
` (16 preceding siblings ...)
2023-04-19 7:44 ` [Intel-xe] [PATCH 17/17] drm/xe: Move helper macros to separate header Lucas De Marchi
@ 2023-04-19 7:47 ` Patchwork
2023-04-19 7:48 ` [Intel-xe] ✓ CI.KUnit: " Patchwork
` (2 subsequent siblings)
20 siblings, 0 replies; 41+ messages in thread
From: Patchwork @ 2023-04-19 7:47 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-xe
== Series Details ==
Series: Cleanup registers and introduce xe_reg_t
URL : https://patchwork.freedesktop.org/series/116678/
State : success
== Summary ==
=== Applying kernel patches on branch 'drm-xe-next' with base: ===
Base commit: 5c309c81e fixup! drm/i915/display: Remaining changes to make xe compile
=== git am output follows ===
Applying: drm/xe: Cleanup page-related defines
Applying: fixup! drm/i915/display: Remaining changes to make xe compile
Applying: fixup! drm/i915/display: Allow fbdev to allocate stolen memory
Applying: drm/xe: Rename RC0/RC6 macros
Applying: drm/xe: Rename instruction field to avoid confusion
Applying: drm/xe/guc: Rename GEN11_SOFT_SCRATCH for clarity
Applying: drm/xe/guc: Move GuC registers to regs/
Applying: drm/xe/guc: Convert GuC registers to REG_FIELD/REG_BIT
Applying: drm/xe: Drop gen prefixes and suffixes from registers
Applying: drm/xe: Use REG_FIELD/REG_BIT for all regs/*.h
Applying: drm/xe: Introduce xe_reg_t
Applying: drm/xe: Clarify register types on PAT programming
Applying: drm/xe/rtp: Improve magic macros for RTP tables
Applying: drm/xe: Add XE_REG/XE_REG_MCR
Applying: drm/xe: Annotate masked registers used by RTP
Applying: drm/xe: Plumb xe_reg_t into WAs, rtp, etc
Applying: drm/xe: Move helper macros to separate header
^ permalink raw reply [flat|nested] 41+ messages in thread
* [Intel-xe] ✓ CI.KUnit: success for Cleanup registers and introduce xe_reg_t
2023-04-19 7:44 [Intel-xe] [PATCH 00/17] Cleanup registers and introduce xe_reg_t Lucas De Marchi
` (17 preceding siblings ...)
2023-04-19 7:47 ` [Intel-xe] ✓ CI.Patch_applied: success for Cleanup registers and introduce xe_reg_t Patchwork
@ 2023-04-19 7:48 ` Patchwork
2023-04-19 7:52 ` [Intel-xe] ✓ CI.Build: " Patchwork
2023-04-19 8:12 ` [Intel-xe] ○ CI.BAT: info " Patchwork
20 siblings, 0 replies; 41+ messages in thread
From: Patchwork @ 2023-04-19 7:48 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-xe
== Series Details ==
Series: Cleanup registers and introduce xe_reg_t
URL : https://patchwork.freedesktop.org/series/116678/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
stty: 'standard input': Inappropriate ioctl for device
[07:47:23] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[07:47:27] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make ARCH=um O=.kunit --jobs=48
[07:47:49] Starting KUnit Kernel (1/1)...
[07:47:49] ============================================================
[07:47:49] ==================== xe_bo (2 subtests) ====================
[07:47:49] [SKIPPED] xe_ccs_migrate_kunit
[07:47:49] [SKIPPED] xe_bo_evict_kunit
[07:47:49] ===================== [SKIPPED] xe_bo ======================
[07:47:49] ================== xe_dma_buf (1 subtest) ==================
[07:47:49] [SKIPPED] xe_dma_buf_kunit
[07:47:49] =================== [SKIPPED] xe_dma_buf ===================
[07:47:49] ================== xe_migrate (1 subtest) ==================
[07:47:49] [SKIPPED] xe_migrate_sanity_kunit
[07:47:49] =================== [SKIPPED] xe_migrate ===================
[07:47:49] =================== xe_pci (2 subtests) ====================
[07:47:49] [PASSED] xe_gmdid_graphics_ip
[07:47:49] [PASSED] xe_gmdid_media_ip
[07:47:49] ===================== [PASSED] xe_pci ======================
[07:47:49] ==================== xe_rtp (1 subtest) ====================
[07:47:49] ================== xe_rtp_process_tests ===================
[07:47:49] [PASSED] coalesce-same-reg
[07:47:49] [PASSED] no-match-no-add
[07:47:49] [PASSED] no-match-no-add-multiple-rules
[07:47:49] [PASSED] two-regs-two-entries
[07:47:49] [PASSED] clr-one-set-other
[07:47:49] [PASSED] set-field
[07:47:49] [PASSED] conflict-duplicate
[07:47:49] [PASSED] conflict-not-disjoint
[07:47:49] [PASSED] conflict-reg-type
[07:47:49] ============== [PASSED] xe_rtp_process_tests ===============
[07:47:49] ===================== [PASSED] xe_rtp ======================
[07:47:49] ==================== xe_wa (1 subtest) =====================
[07:47:49] ======================== xe_wa_gt =========================
[07:47:49] [PASSED] TIGERLAKE (B0)
[07:47:49] [PASSED] DG1 (A0)
[07:47:49] [PASSED] DG1 (B0)
[07:47:49] [PASSED] ALDERLAKE_S (A0)
[07:47:49] [PASSED] ALDERLAKE_S (B0)
[07:47:49] [PASSED] ALDERLAKE_S (C0)
[07:47:49] [PASSED] ALDERLAKE_S (D0)
[07:47:49] [PASSED] DG2_G10 (A0)
[07:47:49] [PASSED] DG2_G10 (A1)
[07:47:49] [PASSED] DG2_G10 (B0)
[07:47:49] [PASSED] DG2_G10 (C0)
[07:47:49] [PASSED] DG2_G11 (A0)
[07:47:49] [PASSED] DG2_G11 (B0)
[07:47:49] [PASSED] DG2_G11 (B1)
[07:47:49] [PASSED] DG2_G12 (A0)
[07:47:49] [PASSED] DG2_G12 (A1)
[07:47:49] [PASSED] PVC (B0)
[07:47:49] [PASSED] PVC (B1)
[07:47:49] [PASSED] PVC (C0)
[07:47:49] ==================== [PASSED] xe_wa_gt =====================
[07:47:49] ====================== [PASSED] xe_wa ======================
[07:47:49] ============================================================
[07:47:49] Testing complete. Ran 34 tests: passed: 30, skipped: 4
[07:47:49] Elapsed time: 26.053s total, 4.239s configuring, 21.695s building, 0.094s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[07:47:49] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[07:47:51] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make ARCH=um O=.kunit --jobs=48
[07:48:09] Starting KUnit Kernel (1/1)...
[07:48:09] ============================================================
[07:48:09] ============ drm_test_pick_cmdline (2 subtests) ============
[07:48:09] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[07:48:09] =============== drm_test_pick_cmdline_named ===============
[07:48:09] [PASSED] NTSC
[07:48:09] [PASSED] NTSC-J
[07:48:09] [PASSED] PAL
[07:48:09] [PASSED] PAL-M
[07:48:09] =========== [PASSED] drm_test_pick_cmdline_named ===========
[07:48:09] ============== [PASSED] drm_test_pick_cmdline ==============
[07:48:09] ================== drm_buddy (6 subtests) ==================
[07:48:09] [PASSED] drm_test_buddy_alloc_limit
[07:48:09] [PASSED] drm_test_buddy_alloc_range
[07:48:09] [PASSED] drm_test_buddy_alloc_optimistic
[07:48:09] [PASSED] drm_test_buddy_alloc_pessimistic
[07:48:09] [PASSED] drm_test_buddy_alloc_smoke
[07:48:09] [PASSED] drm_test_buddy_alloc_pathological
[07:48:09] ==================== [PASSED] drm_buddy ====================
[07:48:09] ============= drm_cmdline_parser (40 subtests) =============
[07:48:09] [PASSED] drm_test_cmdline_force_d_only
[07:48:09] [PASSED] drm_test_cmdline_force_D_only_dvi
[07:48:09] [PASSED] drm_test_cmdline_force_D_only_hdmi
[07:48:09] [PASSED] drm_test_cmdline_force_D_only_not_digital
[07:48:09] [PASSED] drm_test_cmdline_force_e_only
[07:48:09] [PASSED] drm_test_cmdline_res
[07:48:09] [PASSED] drm_test_cmdline_res_vesa
[07:48:09] [PASSED] drm_test_cmdline_res_vesa_rblank
[07:48:09] [PASSED] drm_test_cmdline_res_rblank
[07:48:09] [PASSED] drm_test_cmdline_res_bpp
[07:48:09] [PASSED] drm_test_cmdline_res_refresh
[07:48:09] [PASSED] drm_test_cmdline_res_bpp_refresh
[07:48:09] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[07:48:09] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[07:48:09] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[07:48:09] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[07:48:09] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[07:48:09] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[07:48:09] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[07:48:09] [PASSED] drm_test_cmdline_res_margins_force_on
[07:48:09] [PASSED] drm_test_cmdline_res_vesa_margins
[07:48:09] [PASSED] drm_test_cmdline_name
[07:48:09] [PASSED] drm_test_cmdline_name_bpp
[07:48:09] [PASSED] drm_test_cmdline_name_option
[07:48:09] [PASSED] drm_test_cmdline_name_bpp_option
[07:48:09] [PASSED] drm_test_cmdline_rotate_0
[07:48:09] [PASSED] drm_test_cmdline_rotate_90
[07:48:09] [PASSED] drm_test_cmdline_rotate_180
[07:48:09] [PASSED] drm_test_cmdline_rotate_270
[07:48:09] [PASSED] drm_test_cmdline_hmirror
[07:48:09] [PASSED] drm_test_cmdline_vmirror
[07:48:09] [PASSED] drm_test_cmdline_margin_options
[07:48:09] [PASSED] drm_test_cmdline_multiple_options
[07:48:09] [PASSED] drm_test_cmdline_bpp_extra_and_option
[07:48:09] [PASSED] drm_test_cmdline_extra_and_option
[07:48:09] [PASSED] drm_test_cmdline_freestanding_options
[07:48:09] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[07:48:09] [PASSED] drm_test_cmdline_panel_orientation
[07:48:09] ================ drm_test_cmdline_invalid =================
[07:48:09] [PASSED] margin_only
[07:48:09] [PASSED] interlace_only
[07:48:09] [PASSED] res_missing_x
[07:48:09] [PASSED] res_missing_y
[07:48:09] [PASSED] res_bad_y
[07:48:09] [PASSED] res_missing_y_bpp
[07:48:09] [PASSED] res_bad_bpp
[07:48:09] [PASSED] res_bad_refresh
[07:48:09] [PASSED] res_bpp_refresh_force_on_off
[07:48:09] [PASSED] res_invalid_mode
[07:48:09] [PASSED] res_bpp_wrong_place_mode
[07:48:09] [PASSED] name_bpp_refresh
[07:48:09] [PASSED] name_refresh
[07:48:09] [PASSED] name_refresh_wrong_mode
[07:48:09] [PASSED] name_refresh_invalid_mode
[07:48:09] [PASSED] rotate_multiple
[07:48:09] [PASSED] rotate_invalid_val
[07:48:09] [PASSED] rotate_truncated
[07:48:09] [PASSED] invalid_option
[07:48:09] [PASSED] invalid_tv_option
[07:48:09] [PASSED] truncated_tv_option
[07:48:09] ============ [PASSED] drm_test_cmdline_invalid =============
[07:48:09] =============== drm_test_cmdline_tv_options ===============
[07:48:09] [PASSED] NTSC
[07:48:09] [PASSED] NTSC_443
[07:48:09] [PASSED] NTSC_J
[07:48:09] [PASSED] PAL
[07:48:09] [PASSED] PAL_M
[07:48:09] [PASSED] PAL_N
[07:48:09] [PASSED] SECAM
[07:48:09] =========== [PASSED] drm_test_cmdline_tv_options ===========
[07:48:09] =============== [PASSED] drm_cmdline_parser ================
[07:48:09] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[07:48:09] ========== drm_test_get_tv_mode_from_name_valid ===========
[07:48:09] [PASSED] NTSC
[07:48:09] [PASSED] NTSC-443
[07:48:09] [PASSED] NTSC-J
[07:48:09] [PASSED] PAL
[07:48:09] [PASSED] PAL-M
[07:48:09] [PASSED] PAL-N
[07:48:09] [PASSED] SECAM
[07:48:09] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[07:48:09] [PASSED] drm_test_get_tv_mode_from_name_truncated
[07:48:09] ============ [PASSED] drm_get_tv_mode_from_name ============
[07:48:09] ============= drm_damage_helper (21 subtests) ==============
[07:48:09] [PASSED] drm_test_damage_iter_no_damage
[07:48:09] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[07:48:09] [PASSED] drm_test_damage_iter_no_damage_src_moved
[07:48:09] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[07:48:09] [PASSED] drm_test_damage_iter_no_damage_not_visible
[07:48:09] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[07:48:09] [PASSED] drm_test_damage_iter_no_damage_no_fb
[07:48:09] [PASSED] drm_test_damage_iter_simple_damage
[07:48:09] [PASSED] drm_test_damage_iter_single_damage
[07:48:09] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[07:48:09] [PASSED] drm_test_damage_iter_single_damage_outside_src
[07:48:09] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[07:48:09] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[07:48:09] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[07:48:09] [PASSED] drm_test_damage_iter_single_damage_src_moved
[07:48:09] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[07:48:09] [PASSED] drm_test_damage_iter_damage
[07:48:09] [PASSED] drm_test_damage_iter_damage_one_intersect
[07:48:09] [PASSED] drm_test_damage_iter_damage_one_outside
[07:48:09] [PASSED] drm_test_damage_iter_damage_src_moved
[07:48:09] [PASSED] drm_test_damage_iter_damage_not_visible
[07:48:09] ================ [PASSED] drm_damage_helper ================
[07:48:09] ============== drm_dp_mst_helper (2 subtests) ==============
[07:48:09] ============== drm_test_dp_mst_calc_pbn_mode ==============
[07:48:09] [PASSED] Clock 154000 BPP 30 DSC disabled
[07:48:09] [PASSED] Clock 234000 BPP 30 DSC disabled
[07:48:09] [PASSED] Clock 297000 BPP 24 DSC disabled
[07:48:09] [PASSED] Clock 332880 BPP 24 DSC enabled
[07:48:09] [PASSED] Clock 324540 BPP 24 DSC enabled
[07:48:09] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[07:48:09] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[07:48:09] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[07:48:09] [PASSED] DP_POWER_UP_PHY with port number
[07:48:09] [PASSED] DP_POWER_DOWN_PHY with port number
[07:48:09] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[07:48:09] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[07:48:09] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[07:48:09] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[07:48:09] [PASSED] DP_QUERY_PAYLOAD with port number
[07:48:09] [PASSED] DP_QUERY_PAYLOAD with VCPI
[07:48:09] [PASSED] DP_REMOTE_DPCD_READ with port number
[07:48:09] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[07:48:09] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[07:48:09] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[07:48:09] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[07:48:09] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[07:48:09] [PASSED] DP_REMOTE_I2C_READ with port number
[07:48:09] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[07:48:09] [PASSED] DP_REMOTE_I2C_READ with transactions array
[07:48:09] [PASSED] DP_REMOTE_I2C_WRITE with port number
[07:48:09] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[07:48:09] [PASSED] DP_REMOTE_I2C_WRITE with data array
[07:48:09] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[07:48:09] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[07:48:09] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[07:48:09] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[07:48:09] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[07:48:09] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[07:48:09] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[07:48:09] ================ [PASSED] drm_dp_mst_helper ================
[07:48:09] =========== drm_format_helper_test (11 subtests) ===========
[07:48:09] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[07:48:09] [PASSED] single_pixel_source_buffer
[07:48:09] [PASSED] single_pixel_clip_rectangle
[07:48:09] [PASSED] well_known_colors
[07:48:09] [PASSED] destination_pitch
[07:48:09] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[07:48:09] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[07:48:09] [PASSED] single_pixel_source_buffer
[07:48:09] [PASSED] single_pixel_clip_rectangle
[07:48:09] [PASSED] well_known_colors
[07:48:09] [PASSED] destination_pitch
[07:48:09] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[07:48:09] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[07:48:09] [PASSED] single_pixel_source_buffer
[07:48:09] [PASSED] single_pixel_clip_rectangle
[07:48:09] [PASSED] well_known_colors
[07:48:09] [PASSED] destination_pitch
[07:48:09] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[07:48:09] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[07:48:09] [PASSED] single_pixel_source_buffer
[07:48:09] [PASSED] single_pixel_clip_rectangle
[07:48:09] [PASSED] well_known_colors
[07:48:09] [PASSED] destination_pitch
[07:48:09] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[07:48:09] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[07:48:09] [PASSED] single_pixel_source_buffer
[07:48:09] [PASSED] single_pixel_clip_rectangle
[07:48:09] [PASSED] well_known_colors
[07:48:09] [PASSED] destination_pitch
[07:48:09] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[07:48:09] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[07:48:09] [PASSED] single_pixel_source_buffer
[07:48:09] [PASSED] single_pixel_clip_rectangle
[07:48:09] [PASSED] well_known_colors
[07:48:09] [PASSED] destination_pitch
[07:48:09] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[07:48:09] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[07:48:09] [PASSED] single_pixel_source_buffer
[07:48:09] [PASSED] single_pixel_clip_rectangle
[07:48:09] [PASSED] well_known_colors
[07:48:09] [PASSED] destination_pitch
[07:48:09] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[07:48:09] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[07:48:09] [PASSED] single_pixel_source_buffer
[07:48:09] [PASSED] single_pixel_clip_rectangle
[07:48:09] [PASSED] well_known_colors
[07:48:09] [PASSED] destination_pitch
[07:48:09] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[07:48:09] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[07:48:09] [PASSED] single_pixel_source_buffer
[07:48:09] [PASSED] single_pixel_clip_rectangle
[07:48:09] [PASSED] well_known_colors
[07:48:09] [PASSED] destination_pitch
[07:48:09] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[07:48:09] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[07:48:09] [PASSED] single_pixel_source_buffer
[07:48:09] [PASSED] single_pixel_clip_rectangle
[07:48:09] [PASSED] well_known_colors
[07:48:09] [PASSED] destination_pitch
[07:48:09] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[07:48:09] ============== drm_test_fb_xrgb8888_to_mono ===============
[07:48:09] [PASSED] single_pixel_source_buffer
[07:48:09] [PASSED] single_pixel_clip_rectangle
[07:48:09] [PASSED] well_known_colors
[07:48:09] [PASSED] destination_pitch
[07:48:09] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[07:48:09] ============= [PASSED] drm_format_helper_test ==============
[07:48:09] ================= drm_format (18 subtests) =================
[07:48:09] [PASSED] drm_test_format_block_width_invalid
[07:48:09] [PASSED] drm_test_format_block_width_one_plane
[07:48:09] [PASSED] drm_test_format_block_width_two_plane
[07:48:09] [PASSED] drm_test_format_block_width_three_plane
[07:48:09] [PASSED] drm_test_format_block_width_tiled
[07:48:09] [PASSED] drm_test_format_block_height_invalid
[07:48:09] [PASSED] drm_test_format_block_height_one_plane
[07:48:09] [PASSED] drm_test_format_block_height_two_plane
[07:48:09] [PASSED] drm_test_format_block_height_three_plane
[07:48:09] [PASSED] drm_test_format_block_height_tiled
[07:48:09] [PASSED] drm_test_format_min_pitch_invalid
[07:48:09] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[07:48:09] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[07:48:09] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[07:48:09] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[07:48:09] [PASSED] drm_test_format_min_pitch_two_plane
[07:48:09] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[07:48:09] [PASSED] drm_test_format_min_pitch_tiled
[07:48:09] =================== [PASSED] drm_format ====================
[07:48:09] =============== drm_framebuffer (1 subtest) ================
[07:48:09] =============== drm_test_framebuffer_create ===============
[07:48:09] [PASSED] ABGR8888 normal sizes
[07:48:09] [PASSED] ABGR8888 max sizes
[07:48:09] [PASSED] ABGR8888 pitch greater than min required
[07:48:09] [PASSED] ABGR8888 pitch less than min required
[07:48:09] [PASSED] ABGR8888 Invalid width
[07:48:09] [PASSED] ABGR8888 Invalid buffer handle
[07:48:09] [PASSED] No pixel format
[07:48:09] [PASSED] ABGR8888 Width 0
[07:48:09] [PASSED] ABGR8888 Height 0
[07:48:09] [PASSED] ABGR8888 Out of bound height * pitch combination
[07:48:09] [PASSED] ABGR8888 Large buffer offset
[07:48:09] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[07:48:09] [PASSED] ABGR8888 Valid buffer modifier
[07:48:09] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[07:48:09] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[07:48:09] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[07:48:09] [PASSED] NV12 Normal sizes
[07:48:09] [PASSED] NV12 Max sizes
[07:48:09] [PASSED] NV12 Invalid pitch
[07:48:09] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[07:48:09] [PASSED] NV12 different modifier per-plane
[07:48:09] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[07:48:09] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[07:48:09] [PASSED] NV12 Modifier for inexistent plane
[07:48:09] [PASSED] NV12 Handle for inexistent plane
[07:48:09] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[07:48:09] [PASSED] YVU420 Normal sizes
[07:48:09] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[07:48:09] [PASSED] YVU420 Max sizes
[07:48:09] [PASSED] YVU420 Invalid pitch
[07:48:09] [PASSED] YVU420 Different pitches
[07:48:09] [PASSED] YVU420 Different buffer offsets/pitches
[07:48:09] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[07:48:09] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[07:48:09] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[07:48:09] [PASSED] YVU420 Valid modifier
[07:48:09] [PASSED] YVU420 Different modifiers per plane
[07:48:09] [PASSED] YVU420 Modifier for inexistent plane
[07:48:09] [PASSED] X0L2 Normal sizes
[07:48:09] [PASSED] X0L2 Max sizes
[07:48:09] [PASSED] X0L2 Invalid pitch
[07:48:09] [PASSED] X0L2 Pitch greater than minimum required
stty: 'standard input': Inappropriate ioctl for device
[07:48:09] [PASSED] X0L2 Handle for inexistent plane
[07:48:09] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[07:48:09] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[07:48:09] [PASSED] X0L2 Valid modifier
[07:48:09] [PASSED] X0L2 Modifier for inexistent plane
[07:48:09] =========== [PASSED] drm_test_framebuffer_create ===========
[07:48:09] ================= [PASSED] drm_framebuffer =================
[07:48:09] =============== drm-test-managed (1 subtest) ===============
[07:48:09] [PASSED] drm_test_managed_run_action
[07:48:09] ================ [PASSED] drm-test-managed =================
[07:48:09] =================== drm_mm (19 subtests) ===================
[07:48:09] [PASSED] drm_test_mm_init
[07:48:09] [PASSED] drm_test_mm_debug
[07:48:19] [PASSED] drm_test_mm_reserve
[07:48:29] [PASSED] drm_test_mm_insert
[07:48:30] [PASSED] drm_test_mm_replace
[07:48:30] [PASSED] drm_test_mm_insert_range
[07:48:30] [PASSED] drm_test_mm_frag
[07:48:30] [PASSED] drm_test_mm_align
[07:48:30] [PASSED] drm_test_mm_align32
[07:48:30] [PASSED] drm_test_mm_align64
[07:48:31] [PASSED] drm_test_mm_evict
[07:48:31] [PASSED] drm_test_mm_evict_range
[07:48:31] [PASSED] drm_test_mm_topdown
[07:48:31] [PASSED] drm_test_mm_bottomup
[07:48:31] [PASSED] drm_test_mm_lowest
[07:48:31] [PASSED] drm_test_mm_highest
[07:48:32] [PASSED] drm_test_mm_color
[07:48:32] [PASSED] drm_test_mm_color_evict
[07:48:32] [PASSED] drm_test_mm_color_evict_range
[07:48:32] ===================== [PASSED] drm_mm ======================
[07:48:32] ============= drm_modes_analog_tv (4 subtests) =============
[07:48:32] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[07:48:32] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[07:48:32] [PASSED] drm_test_modes_analog_tv_pal_576i
[07:48:32] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[07:48:32] =============== [PASSED] drm_modes_analog_tv ===============
[07:48:32] ============== drm_plane_helper (2 subtests) ===============
[07:48:32] =============== drm_test_check_plane_state ================
[07:48:32] [PASSED] clipping_simple
[07:48:32] [PASSED] clipping_rotate_reflect
[07:48:32] [PASSED] positioning_simple
[07:48:32] [PASSED] upscaling
[07:48:32] [PASSED] downscaling
[07:48:32] [PASSED] rounding1
[07:48:32] [PASSED] rounding2
[07:48:32] [PASSED] rounding3
[07:48:32] [PASSED] rounding4
[07:48:32] =========== [PASSED] drm_test_check_plane_state ============
[07:48:32] =========== drm_test_check_invalid_plane_state ============
[07:48:32] [PASSED] positioning_invalid
[07:48:32] [PASSED] upscaling_invalid
[07:48:32] [PASSED] downscaling_invalid
[07:48:32] ======= [PASSED] drm_test_check_invalid_plane_state ========
[07:48:32] ================ [PASSED] drm_plane_helper =================
[07:48:32] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[07:48:32] ====== drm_test_connector_helper_tv_get_modes_check =======
[07:48:32] [PASSED] None
[07:48:32] [PASSED] PAL
[07:48:32] [PASSED] NTSC
[07:48:32] [PASSED] Both, NTSC Default
[07:48:32] [PASSED] Both, PAL Default
[07:48:32] [PASSED] Both, NTSC Default, with PAL on command-line
[07:48:32] [PASSED] Both, PAL Default, with NTSC on command-line
[07:48:32] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[07:48:32] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[07:48:32] ================== drm_rect (4 subtests) ===================
[07:48:32] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[07:48:32] [PASSED] drm_test_rect_clip_scaled_not_clipped
[07:48:32] [PASSED] drm_test_rect_clip_scaled_clipped
[07:48:32] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[07:48:32] ==================== [PASSED] drm_rect =====================
[07:48:32] ============================================================
[07:48:32] Testing complete. Ran 294 tests: passed: 294
[07:48:32] Elapsed time: 43.151s total, 1.688s configuring, 18.333s building, 23.119s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 41+ messages in thread
* [Intel-xe] ✓ CI.Build: success for Cleanup registers and introduce xe_reg_t
2023-04-19 7:44 [Intel-xe] [PATCH 00/17] Cleanup registers and introduce xe_reg_t Lucas De Marchi
` (18 preceding siblings ...)
2023-04-19 7:48 ` [Intel-xe] ✓ CI.KUnit: " Patchwork
@ 2023-04-19 7:52 ` Patchwork
2023-04-19 8:12 ` [Intel-xe] ○ CI.BAT: info " Patchwork
20 siblings, 0 replies; 41+ messages in thread
From: Patchwork @ 2023-04-19 7:52 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-xe
== Series Details ==
Series: Cleanup registers and introduce xe_reg_t
URL : https://patchwork.freedesktop.org/series/116678/
State : success
== Summary ==
+ trap cleanup EXIT
+ cd /kernel
+ git clone https://gitlab.freedesktop.org/drm/xe/ci.git .ci
Cloning into '.ci'...
++ date +%s
+ echo -e '\e[0Ksection_start:1681890522:build_x86_64[collapsed=true]\r\e[0KBuild x86-64'
+ mkdir -p build64
^[[0Ksection_start:1681890522:build_x86_64[collapsed=true]
^[[0KBuild x86-64
+ cat .ci/kernel/kconfig
+ make O=build64 olddefconfig
make[1]: Entering directory '/kernel/build64'
GEN Makefile
HOSTCC scripts/basic/fixdep
HOSTCC scripts/kconfig/conf.o
HOSTCC scripts/kconfig/confdata.o
HOSTCC scripts/kconfig/expr.o
LEX scripts/kconfig/lexer.lex.c
YACC scripts/kconfig/parser.tab.[ch]
HOSTCC scripts/kconfig/lexer.lex.o
HOSTCC scripts/kconfig/menu.o
HOSTCC scripts/kconfig/parser.tab.o
HOSTCC scripts/kconfig/preprocess.o
HOSTCC scripts/kconfig/symbol.o
HOSTCC scripts/kconfig/util.o
HOSTLD scripts/kconfig/conf
#
# configuration written to .config
#
make[1]: Leaving directory '/kernel/build64'
++ nproc
+ make O=build64 -j48
make[1]: Entering directory '/kernel/build64'
GEN Makefile
WRAP arch/x86/include/generated/uapi/asm/bpf_perf_event.h
WRAP arch/x86/include/generated/uapi/asm/errno.h
WRAP arch/x86/include/generated/uapi/asm/fcntl.h
WRAP arch/x86/include/generated/uapi/asm/ioctl.h
SYSHDR arch/x86/include/generated/uapi/asm/unistd_32.h
WRAP arch/x86/include/generated/uapi/asm/ioctls.h
WRAP arch/x86/include/generated/uapi/asm/ipcbuf.h
SYSHDR arch/x86/include/generated/uapi/asm/unistd_64.h
WRAP arch/x86/include/generated/uapi/asm/param.h
SYSHDR arch/x86/include/generated/uapi/asm/unistd_x32.h
WRAP arch/x86/include/generated/uapi/asm/poll.h
WRAP arch/x86/include/generated/uapi/asm/resource.h
SYSTBL arch/x86/include/generated/asm/syscalls_32.h
WRAP arch/x86/include/generated/uapi/asm/socket.h
SYSHDR arch/x86/include/generated/asm/unistd_32_ia32.h
WRAP arch/x86/include/generated/uapi/asm/sockios.h
SYSHDR arch/x86/include/generated/asm/unistd_64_x32.h
SYSTBL arch/x86/include/generated/asm/syscalls_64.h
WRAP arch/x86/include/generated/uapi/asm/termbits.h
WRAP arch/x86/include/generated/uapi/asm/termios.h
WRAP arch/x86/include/generated/uapi/asm/types.h
UPD include/generated/uapi/linux/version.h
UPD include/config/kernel.release
UPD include/generated/compile.h
HOSTCC arch/x86/tools/relocs_32.o
HOSTCC arch/x86/tools/relocs_common.o
HOSTCC arch/x86/tools/relocs_64.o
WRAP arch/x86/include/generated/asm/early_ioremap.h
WRAP arch/x86/include/generated/asm/export.h
WRAP arch/x86/include/generated/asm/mcs_spinlock.h
WRAP arch/x86/include/generated/asm/irq_regs.h
WRAP arch/x86/include/generated/asm/kmap_size.h
WRAP arch/x86/include/generated/asm/local64.h
WRAP arch/x86/include/generated/asm/mmiowb.h
WRAP arch/x86/include/generated/asm/module.lds.h
WRAP arch/x86/include/generated/asm/rwonce.h
WRAP arch/x86/include/generated/asm/unaligned.h
HOSTCC scripts/unifdef
UPD include/generated/utsrelease.h
HOSTCC scripts/kallsyms
HOSTCC scripts/sorttable
HOSTCC scripts/asn1_compiler
DESCEND objtool
HOSTCC /kernel/build64/tools/objtool/fixdep.o
HOSTLD /kernel/build64/tools/objtool/fixdep-in.o
LINK /kernel/build64/tools/objtool/fixdep
INSTALL /kernel/build64/tools/objtool/libsubcmd/include/subcmd/exec-cmd.h
INSTALL /kernel/build64/tools/objtool/libsubcmd/include/subcmd/help.h
INSTALL /kernel/build64/tools/objtool/libsubcmd/include/subcmd/pager.h
INSTALL /kernel/build64/tools/objtool/libsubcmd/include/subcmd/parse-options.h
INSTALL /kernel/build64/tools/objtool/libsubcmd/include/subcmd/run-command.h
CC /kernel/build64/tools/objtool/libsubcmd/exec-cmd.o
CC /kernel/build64/tools/objtool/libsubcmd/help.o
CC /kernel/build64/tools/objtool/libsubcmd/pager.o
INSTALL libsubcmd_headers
CC /kernel/build64/tools/objtool/libsubcmd/parse-options.o
CC /kernel/build64/tools/objtool/libsubcmd/run-command.o
CC /kernel/build64/tools/objtool/libsubcmd/sigchain.o
CC /kernel/build64/tools/objtool/libsubcmd/subcmd-config.o
HOSTLD arch/x86/tools/relocs
CC scripts/mod/empty.o
HOSTCC scripts/mod/mk_elfconfig
CC scripts/mod/devicetable-offsets.s
HDRINST usr/include/video/edid.h
HDRINST usr/include/video/sisfb.h
HDRINST usr/include/drm/amdgpu_drm.h
HDRINST usr/include/video/uvesafb.h
HDRINST usr/include/drm/i915_drm.h
HDRINST usr/include/drm/vgem_drm.h
HDRINST usr/include/drm/virtgpu_drm.h
HDRINST usr/include/drm/xe_drm.h
HDRINST usr/include/drm/omap_drm.h
HDRINST usr/include/drm/radeon_drm.h
HDRINST usr/include/drm/tegra_drm.h
HDRINST usr/include/drm/drm_mode.h
HDRINST usr/include/drm/ivpu_accel.h
HDRINST usr/include/drm/exynos_drm.h
HDRINST usr/include/drm/drm_sarea.h
HDRINST usr/include/drm/v3d_drm.h
HDRINST usr/include/drm/qxl_drm.h
HDRINST usr/include/drm/drm_fourcc.h
HDRINST usr/include/drm/nouveau_drm.h
HDRINST usr/include/drm/habanalabs_accel.h
HDRINST usr/include/drm/vmwgfx_drm.h
HDRINST usr/include/drm/msm_drm.h
HDRINST usr/include/drm/etnaviv_drm.h
HDRINST usr/include/drm/vc4_drm.h
HDRINST usr/include/drm/panfrost_drm.h
HDRINST usr/include/drm/drm.h
HDRINST usr/include/drm/armada_drm.h
HDRINST usr/include/drm/lima_drm.h
HDRINST usr/include/mtd/inftl-user.h
HDRINST usr/include/mtd/mtd-user.h
HDRINST usr/include/mtd/nftl-user.h
HDRINST usr/include/mtd/ubi-user.h
HDRINST usr/include/mtd/mtd-abi.h
HDRINST usr/include/xen/gntdev.h
HDRINST usr/include/xen/gntalloc.h
HDRINST usr/include/xen/evtchn.h
HDRINST usr/include/xen/privcmd.h
HDRINST usr/include/asm-generic/auxvec.h
HDRINST usr/include/asm-generic/bitsperlong.h
HDRINST usr/include/asm-generic/posix_types.h
HDRINST usr/include/asm-generic/ioctls.h
HDRINST usr/include/asm-generic/mman.h
HDRINST usr/include/asm-generic/bpf_perf_event.h
HDRINST usr/include/asm-generic/shmbuf.h
HDRINST usr/include/asm-generic/types.h
HDRINST usr/include/asm-generic/poll.h
UPD scripts/mod/devicetable-offsets.h
HDRINST usr/include/asm-generic/swab.h
HDRINST usr/include/asm-generic/msgbuf.h
HDRINST usr/include/asm-generic/statfs.h
HDRINST usr/include/asm-generic/unistd.h
HDRINST usr/include/asm-generic/hugetlb_encode.h
HDRINST usr/include/asm-generic/resource.h
HDRINST usr/include/asm-generic/param.h
HDRINST usr/include/asm-generic/termbits-common.h
HDRINST usr/include/asm-generic/sockios.h
HDRINST usr/include/asm-generic/kvm_para.h
HDRINST usr/include/asm-generic/errno.h
HDRINST usr/include/asm-generic/termios.h
HDRINST usr/include/asm-generic/mman-common.h
HDRINST usr/include/asm-generic/ioctl.h
HDRINST usr/include/asm-generic/socket.h
HDRINST usr/include/asm-generic/signal-defs.h
HDRINST usr/include/asm-generic/termbits.h
HDRINST usr/include/asm-generic/int-ll64.h
HDRINST usr/include/asm-generic/signal.h
HDRINST usr/include/asm-generic/siginfo.h
HDRINST usr/include/asm-generic/stat.h
HDRINST usr/include/asm-generic/int-l64.h
HDRINST usr/include/asm-generic/errno-base.h
HDRINST usr/include/asm-generic/fcntl.h
HDRINST usr/include/asm-generic/setup.h
HDRINST usr/include/asm-generic/ipcbuf.h
HDRINST usr/include/asm-generic/sembuf.h
HDRINST usr/include/asm-generic/ucontext.h
HDRINST usr/include/rdma/mlx5_user_ioctl_cmds.h
HDRINST usr/include/rdma/irdma-abi.h
HDRINST usr/include/rdma/mana-abi.h
HDRINST usr/include/rdma/hfi/hfi1_user.h
HDRINST usr/include/rdma/hfi/hfi1_ioctl.h
HDRINST usr/include/rdma/rdma_user_rxe.h
HDRINST usr/include/rdma/rdma_user_ioctl.h
HDRINST usr/include/rdma/mlx5_user_ioctl_verbs.h
HDRINST usr/include/rdma/bnxt_re-abi.h
HDRINST usr/include/rdma/hns-abi.h
HDRINST usr/include/rdma/qedr-abi.h
HDRINST usr/include/rdma/ib_user_ioctl_cmds.h
HDRINST usr/include/rdma/vmw_pvrdma-abi.h
HDRINST usr/include/rdma/ib_user_sa.h
HDRINST usr/include/rdma/ib_user_ioctl_verbs.h
HDRINST usr/include/rdma/rvt-abi.h
HDRINST usr/include/rdma/mlx5-abi.h
HDRINST usr/include/rdma/rdma_netlink.h
HDRINST usr/include/rdma/erdma-abi.h
HDRINST usr/include/rdma/rdma_user_ioctl_cmds.h
HDRINST usr/include/rdma/rdma_user_cm.h
HDRINST usr/include/rdma/ib_user_verbs.h
HDRINST usr/include/rdma/efa-abi.h
HDRINST usr/include/rdma/siw-abi.h
HDRINST usr/include/rdma/mlx4-abi.h
MKELF scripts/mod/elfconfig.h
HDRINST usr/include/rdma/ib_user_mad.h
HDRINST usr/include/rdma/mthca-abi.h
HDRINST usr/include/rdma/ocrdma-abi.h
HDRINST usr/include/rdma/cxgb4-abi.h
HDRINST usr/include/misc/xilinx_sdfec.h
HDRINST usr/include/misc/uacce/hisi_qm.h
HDRINST usr/include/misc/uacce/uacce.h
HDRINST usr/include/misc/cxl.h
HOSTCC scripts/mod/modpost.o
HOSTCC scripts/mod/file2alias.o
HDRINST usr/include/misc/ocxl.h
HDRINST usr/include/misc/fastrpc.h
HOSTCC scripts/mod/sumversion.o
HDRINST usr/include/misc/pvpanic.h
HDRINST usr/include/linux/i8k.h
HDRINST usr/include/linux/acct.h
HDRINST usr/include/linux/atmmpc.h
HDRINST usr/include/linux/fs.h
HDRINST usr/include/linux/cifs/cifs_mount.h
HDRINST usr/include/linux/cifs/cifs_netlink.h
HDRINST usr/include/linux/if_packet.h
HDRINST usr/include/linux/route.h
HDRINST usr/include/linux/patchkey.h
HDRINST usr/include/linux/tc_ematch/tc_em_cmp.h
HDRINST usr/include/linux/tc_ematch/tc_em_ipt.h
HDRINST usr/include/linux/tc_ematch/tc_em_meta.h
HDRINST usr/include/linux/tc_ematch/tc_em_nbyte.h
HDRINST usr/include/linux/tc_ematch/tc_em_text.h
HDRINST usr/include/linux/virtio_pmem.h
HDRINST usr/include/linux/rkisp1-config.h
HDRINST usr/include/linux/vhost.h
HDRINST usr/include/linux/cec-funcs.h
HDRINST usr/include/linux/ppdev.h
HDRINST usr/include/linux/isdn/capicmd.h
HDRINST usr/include/linux/virtio_fs.h
HDRINST usr/include/linux/netfilter_ipv6.h
HDRINST usr/include/linux/lirc.h
HDRINST usr/include/linux/mroute6.h
HDRINST usr/include/linux/nl80211-vnd-intel.h
HDRINST usr/include/linux/ivtvfb.h
HDRINST usr/include/linux/auxvec.h
HDRINST usr/include/linux/dm-log-userspace.h
HDRINST usr/include/linux/dccp.h
HDRINST usr/include/linux/virtio_scmi.h
HDRINST usr/include/linux/atmarp.h
HDRINST usr/include/linux/arcfb.h
HDRINST usr/include/linux/nbd-netlink.h
HDRINST usr/include/linux/sched/types.h
HDRINST usr/include/linux/tcp.h
HDRINST usr/include/linux/neighbour.h
HDRINST usr/include/linux/dlm_device.h
HDRINST usr/include/linux/wmi.h
HDRINST usr/include/linux/btrfs_tree.h
HDRINST usr/include/linux/virtio_crypto.h
HDRINST usr/include/linux/vbox_err.h
HDRINST usr/include/linux/edd.h
HDRINST usr/include/linux/loop.h
HDRINST usr/include/linux/nvme_ioctl.h
HDRINST usr/include/linux/mmtimer.h
HDRINST usr/include/linux/if_pppol2tp.h
HDRINST usr/include/linux/mtio.h
HDRINST usr/include/linux/if_arcnet.h
HDRINST usr/include/linux/romfs_fs.h
HDRINST usr/include/linux/posix_types.h
HDRINST usr/include/linux/rtc.h
HDRINST usr/include/linux/landlock.h
HDRINST usr/include/linux/gpio.h
HDRINST usr/include/linux/selinux_netlink.h
HDRINST usr/include/linux/pps.h
HDRINST usr/include/linux/ndctl.h
HDRINST usr/include/linux/virtio_gpu.h
HDRINST usr/include/linux/android/binderfs.h
HDRINST usr/include/linux/android/binder.h
HDRINST usr/include/linux/virtio_vsock.h
HDRINST usr/include/linux/sound.h
HDRINST usr/include/linux/vtpm_proxy.h
HDRINST usr/include/linux/nfs_fs.h
HDRINST usr/include/linux/elf-fdpic.h
HDRINST usr/include/linux/adfs_fs.h
HDRINST usr/include/linux/target_core_user.h
HDRINST usr/include/linux/netlink_diag.h
HDRINST usr/include/linux/const.h
HDRINST usr/include/linux/firewire-cdev.h
HDRINST usr/include/linux/vdpa.h
HDRINST usr/include/linux/if_infiniband.h
HDRINST usr/include/linux/serial.h
HDRINST usr/include/linux/iio/types.h
HDRINST usr/include/linux/iio/buffer.h
HDRINST usr/include/linux/iio/events.h
HDRINST usr/include/linux/baycom.h
HDRINST usr/include/linux/major.h
HDRINST usr/include/linux/atmppp.h
HDRINST usr/include/linux/ipv6_route.h
HDRINST usr/include/linux/spi/spidev.h
HDRINST usr/include/linux/spi/spi.h
HDRINST usr/include/linux/virtio_ring.h
HDRINST usr/include/linux/hdlc/ioctl.h
HDRINST usr/include/linux/remoteproc_cdev.h
HDRINST usr/include/linux/hyperv.h
HDRINST usr/include/linux/rpl_iptunnel.h
HDRINST usr/include/linux/sync_file.h
HDRINST usr/include/linux/igmp.h
HDRINST usr/include/linux/v4l2-dv-timings.h
HDRINST usr/include/linux/virtio_i2c.h
HDRINST usr/include/linux/xfrm.h
HDRINST usr/include/linux/capability.h
HDRINST usr/include/linux/gtp.h
HDRINST usr/include/linux/xdp_diag.h
HDRINST usr/include/linux/pkt_cls.h
HDRINST usr/include/linux/suspend_ioctls.h
HDRINST usr/include/linux/vt.h
HDRINST usr/include/linux/loadpin.h
HDRINST usr/include/linux/dlm_plock.h
HDRINST usr/include/linux/fb.h
HDRINST usr/include/linux/max2175.h
HDRINST usr/include/linux/sunrpc/debug.h
HDRINST usr/include/linux/gsmmux.h
HDRINST usr/include/linux/watchdog.h
HDRINST usr/include/linux/vhost_types.h
HDRINST usr/include/linux/vduse.h
HDRINST usr/include/linux/ila.h
HDRINST usr/include/linux/tdx-guest.h
HDRINST usr/include/linux/close_range.h
HDRINST usr/include/linux/ivtv.h
HDRINST usr/include/linux/cryptouser.h
HDRINST usr/include/linux/netfilter/xt_string.h
HDRINST usr/include/linux/netfilter/nfnetlink_compat.h
HDRINST usr/include/linux/netfilter/nf_nat.h
HDRINST usr/include/linux/netfilter/xt_recent.h
HDRINST usr/include/linux/netfilter/xt_addrtype.h
HDRINST usr/include/linux/netfilter/nf_conntrack_tcp.h
HDRINST usr/include/linux/netfilter/xt_MARK.h
HDRINST usr/include/linux/netfilter/xt_SYNPROXY.h
HDRINST usr/include/linux/netfilter/xt_multiport.h
HDRINST usr/include/linux/netfilter/nfnetlink.h
HDRINST usr/include/linux/netfilter/xt_cgroup.h
HDRINST usr/include/linux/netfilter/nf_synproxy.h
HDRINST usr/include/linux/netfilter/xt_TCPOPTSTRIP.h
HDRINST usr/include/linux/netfilter/nfnetlink_log.h
HDRINST usr/include/linux/netfilter/xt_TPROXY.h
HDRINST usr/include/linux/netfilter/xt_u32.h
HDRINST usr/include/linux/netfilter/nfnetlink_osf.h
HDRINST usr/include/linux/netfilter/xt_ecn.h
HDRINST usr/include/linux/netfilter/xt_esp.h
HDRINST usr/include/linux/netfilter/nfnetlink_hook.h
HDRINST usr/include/linux/netfilter/xt_mac.h
HDRINST usr/include/linux/netfilter/xt_comment.h
HDRINST usr/include/linux/netfilter/xt_NFQUEUE.h
HDRINST usr/include/linux/netfilter/xt_osf.h
HDRINST usr/include/linux/netfilter/xt_hashlimit.h
HDRINST usr/include/linux/netfilter/nf_conntrack_sctp.h
HDRINST usr/include/linux/netfilter/xt_socket.h
HDRINST usr/include/linux/netfilter/xt_connmark.h
HDRINST usr/include/linux/netfilter/xt_sctp.h
HDRINST usr/include/linux/netfilter/xt_tcpudp.h
HDRINST usr/include/linux/netfilter/xt_DSCP.h
HDRINST usr/include/linux/netfilter/xt_time.h
HDRINST usr/include/linux/netfilter/xt_IDLETIMER.h
HDRINST usr/include/linux/netfilter/xt_policy.h
HDRINST usr/include/linux/netfilter/xt_rpfilter.h
HDRINST usr/include/linux/netfilter/xt_nfacct.h
HDRINST usr/include/linux/netfilter/xt_SECMARK.h
HDRINST usr/include/linux/netfilter/xt_length.h
HDRINST usr/include/linux/netfilter/nfnetlink_cthelper.h
HDRINST usr/include/linux/netfilter/xt_quota.h
HDRINST usr/include/linux/netfilter/xt_CLASSIFY.h
HDRINST usr/include/linux/netfilter/xt_ipcomp.h
HDRINST usr/include/linux/netfilter/xt_iprange.h
HDRINST usr/include/linux/netfilter/xt_bpf.h
HDRINST usr/include/linux/netfilter/xt_LOG.h
HDRINST usr/include/linux/netfilter/xt_rateest.h
HDRINST usr/include/linux/netfilter/xt_CONNSECMARK.h
HDRINST usr/include/linux/netfilter/xt_HMARK.h
HDRINST usr/include/linux/netfilter/xt_CONNMARK.h
HDRINST usr/include/linux/netfilter/xt_pkttype.h
HDRINST usr/include/linux/netfilter/xt_ipvs.h
HDRINST usr/include/linux/netfilter/xt_devgroup.h
HDRINST usr/include/linux/netfilter/xt_AUDIT.h
HDRINST usr/include/linux/netfilter/xt_realm.h
HDRINST usr/include/linux/netfilter/nf_conntrack_common.h
HDRINST usr/include/linux/netfilter/xt_set.h
HDRINST usr/include/linux/netfilter/xt_LED.h
HDRINST usr/include/linux/netfilter/xt_connlabel.h
HDRINST usr/include/linux/netfilter/xt_owner.h
HDRINST usr/include/linux/netfilter/xt_dccp.h
HDRINST usr/include/linux/netfilter/xt_limit.h
HDRINST usr/include/linux/netfilter/xt_conntrack.h
HDRINST usr/include/linux/netfilter/xt_TEE.h
HDRINST usr/include/linux/netfilter/xt_RATEEST.h
HDRINST usr/include/linux/netfilter/xt_connlimit.h
HDRINST usr/include/linux/netfilter/ipset/ip_set.h
HDRINST usr/include/linux/netfilter/ipset/ip_set_list.h
HDRINST usr/include/linux/netfilter/ipset/ip_set_hash.h
HDRINST usr/include/linux/netfilter/ipset/ip_set_bitmap.h
HDRINST usr/include/linux/netfilter/x_tables.h
HDRINST usr/include/linux/netfilter/xt_dscp.h
HDRINST usr/include/linux/netfilter/nf_conntrack_ftp.h
HDRINST usr/include/linux/netfilter/xt_cluster.h
HDRINST usr/include/linux/netfilter/nf_conntrack_tuple_common.h
HDRINST usr/include/linux/netfilter/nf_log.h
HDRINST usr/include/linux/netfilter/xt_tcpmss.h
HDRINST usr/include/linux/netfilter/xt_NFLOG.h
HDRINST usr/include/linux/netfilter/xt_l2tp.h
HDRINST usr/include/linux/netfilter/xt_helper.h
HDRINST usr/include/linux/netfilter/xt_statistic.h
HDRINST usr/include/linux/netfilter/nfnetlink_queue.h
HDRINST usr/include/linux/netfilter/nfnetlink_cttimeout.h
HDRINST usr/include/linux/netfilter/xt_CT.h
HDRINST usr/include/linux/netfilter/xt_CHECKSUM.h
HDRINST usr/include/linux/netfilter/xt_connbytes.h
HDRINST usr/include/linux/netfilter/xt_state.h
HDRINST usr/include/linux/netfilter/nf_tables.h
HDRINST usr/include/linux/netfilter/xt_mark.h
HDRINST usr/include/linux/netfilter/xt_cpu.h
HDRINST usr/include/linux/netfilter/nf_tables_compat.h
HDRINST usr/include/linux/netfilter/xt_physdev.h
HDRINST usr/include/linux/netfilter/nfnetlink_conntrack.h
HDRINST usr/include/linux/netfilter/nfnetlink_acct.h
HDRINST usr/include/linux/netfilter/xt_TCPMSS.h
HDRINST usr/include/linux/tty_flags.h
HDRINST usr/include/linux/if_phonet.h
HDRINST usr/include/linux/elf-em.h
HDRINST usr/include/linux/vm_sockets.h
HDRINST usr/include/linux/dlmconstants.h
HDRINST usr/include/linux/bsg.h
HDRINST usr/include/linux/matroxfb.h
HDRINST usr/include/linux/sysctl.h
HDRINST usr/include/linux/unix_diag.h
HDRINST usr/include/linux/pcitest.h
HDRINST usr/include/linux/mman.h
HDRINST usr/include/linux/if_plip.h
HDRINST usr/include/linux/virtio_balloon.h
HDRINST usr/include/linux/pidfd.h
HDRINST usr/include/linux/f2fs.h
HDRINST usr/include/linux/x25.h
HDRINST usr/include/linux/if_cablemodem.h
HDRINST usr/include/linux/utsname.h
HDRINST usr/include/linux/counter.h
HDRINST usr/include/linux/atm_tcp.h
HDRINST usr/include/linux/atalk.h
HDRINST usr/include/linux/virtio_rng.h
HDRINST usr/include/linux/vboxguest.h
HDRINST usr/include/linux/bpf_perf_event.h
HDRINST usr/include/linux/ipmi_ssif_bmc.h
HDRINST usr/include/linux/nfs_mount.h
HDRINST usr/include/linux/sonet.h
HDRINST usr/include/linux/netfilter.h
HDRINST usr/include/linux/keyctl.h
HDRINST usr/include/linux/nl80211.h
HDRINST usr/include/linux/misc/bcm_vk.h
HDRINST usr/include/linux/audit.h
HDRINST usr/include/linux/tipc_config.h
HDRINST usr/include/linux/tipc_sockets_diag.h
HDRINST usr/include/linux/futex.h
HDRINST usr/include/linux/sev-guest.h
HDRINST usr/include/linux/ublk_cmd.h
HDRINST usr/include/linux/types.h
HDRINST usr/include/linux/virtio_input.h
HDRINST usr/include/linux/if_slip.h
HDRINST usr/include/linux/personality.h
HDRINST usr/include/linux/openat2.h
HDRINST usr/include/linux/poll.h
HDRINST usr/include/linux/posix_acl.h
HDRINST usr/include/linux/smc_diag.h
HDRINST usr/include/linux/snmp.h
HDRINST usr/include/linux/errqueue.h
HDRINST usr/include/linux/if_tunnel.h
HDRINST usr/include/linux/fanotify.h
HDRINST usr/include/linux/kernel.h
HDRINST usr/include/linux/rtnetlink.h
HDRINST usr/include/linux/rpl.h
HDRINST usr/include/linux/memfd.h
HDRINST usr/include/linux/serial_core.h
HDRINST usr/include/linux/dns_resolver.h
HDRINST usr/include/linux/pr.h
HDRINST usr/include/linux/atm_eni.h
HDRINST usr/include/linux/lp.h
HDRINST usr/include/linux/virtio_mem.h
HDRINST usr/include/linux/ultrasound.h
HDRINST usr/include/linux/sctp.h
HDRINST usr/include/linux/uio.h
HDRINST usr/include/linux/tcp_metrics.h
HDRINST usr/include/linux/wwan.h
HDRINST usr/include/linux/atmbr2684.h
HDRINST usr/include/linux/in_route.h
HDRINST usr/include/linux/qemu_fw_cfg.h
HDRINST usr/include/linux/if_macsec.h
HDRINST usr/include/linux/usb/charger.h
HDRINST usr/include/linux/usb/g_uvc.h
HDRINST usr/include/linux/usb/gadgetfs.h
HDRINST usr/include/linux/usb/raw_gadget.h
HDRINST usr/include/linux/usb/cdc-wdm.h
HDRINST usr/include/linux/usb/g_printer.h
HDRINST usr/include/linux/usb/midi.h
HDRINST usr/include/linux/usb/tmc.h
HDRINST usr/include/linux/usb/video.h
HDRINST usr/include/linux/usb/functionfs.h
HDRINST usr/include/linux/usb/audio.h
HDRINST usr/include/linux/usb/ch11.h
HDRINST usr/include/linux/usb/ch9.h
HDRINST usr/include/linux/usb/cdc.h
HDRINST usr/include/linux/jffs2.h
HDRINST usr/include/linux/ax25.h
HDRINST usr/include/linux/auto_fs.h
HDRINST usr/include/linux/tiocl.h
HDRINST usr/include/linux/scc.h
HDRINST usr/include/linux/psci.h
HDRINST usr/include/linux/swab.h
HDRINST usr/include/linux/cec.h
HDRINST usr/include/linux/kfd_ioctl.h
HDRINST usr/include/linux/smc.h
HDRINST usr/include/linux/qrtr.h
HDRINST usr/include/linux/screen_info.h
HDRINST usr/include/linux/nfsacl.h
HDRINST usr/include/linux/seg6_hmac.h
HDRINST usr/include/linux/gameport.h
HDRINST usr/include/linux/wireless.h
HDRINST usr/include/linux/fdreg.h
HDRINST usr/include/linux/cciss_defs.h
HDRINST usr/include/linux/serial_reg.h
HDRINST usr/include/linux/perf_event.h
HDRINST usr/include/linux/in6.h
HDRINST usr/include/linux/hid.h
HDRINST usr/include/linux/netlink.h
HDRINST usr/include/linux/fuse.h
HDRINST usr/include/linux/magic.h
HDRINST usr/include/linux/ioam6_iptunnel.h
HDRINST usr/include/linux/stm.h
HDRINST usr/include/linux/vsockmon.h
HDRINST usr/include/linux/seg6.h
HDRINST usr/include/linux/idxd.h
HDRINST usr/include/linux/nitro_enclaves.h
HDRINST usr/include/linux/ptrace.h
HDRINST usr/include/linux/ioam6_genl.h
HDRINST usr/include/linux/qnx4_fs.h
HDRINST usr/include/linux/fsl_mc.h
HDRINST usr/include/linux/net_tstamp.h
HDRINST usr/include/linux/msg.h
HDRINST usr/include/linux/netfilter_ipv4/ipt_TTL.h
HDRINST usr/include/linux/netfilter_ipv4/ipt_ttl.h
HDRINST usr/include/linux/netfilter_ipv4/ipt_ah.h
HDRINST usr/include/linux/netfilter_ipv4/ipt_ECN.h
HDRINST usr/include/linux/netfilter_ipv4/ip_tables.h
HDRINST usr/include/linux/netfilter_ipv4/ipt_ecn.h
HDRINST usr/include/linux/netfilter_ipv4/ipt_CLUSTERIP.h
HDRINST usr/include/linux/netfilter_ipv4/ipt_REJECT.h
HDRINST usr/include/linux/netfilter_ipv4/ipt_LOG.h
HDRINST usr/include/linux/sem.h
HDRINST usr/include/linux/net_namespace.h
HDRINST usr/include/linux/radeonfb.h
HDRINST usr/include/linux/tee.h
HDRINST usr/include/linux/udp.h
HDRINST usr/include/linux/virtio_bt.h
HDRINST usr/include/linux/v4l2-subdev.h
HDRINST usr/include/linux/posix_acl_xattr.h
HDRINST usr/include/linux/v4l2-mediabus.h
HDRINST usr/include/linux/atmapi.h
HDRINST usr/include/linux/raid/md_p.h
HDRINST usr/include/linux/raid/md_u.h
HDRINST usr/include/linux/zorro_ids.h
HDRINST usr/include/linux/nbd.h
HDRINST usr/include/linux/isst_if.h
HDRINST usr/include/linux/rxrpc.h
HDRINST usr/include/linux/unistd.h
HDRINST usr/include/linux/if_arp.h
HDRINST usr/include/linux/atm_zatm.h
HDRINST usr/include/linux/io_uring.h
HDRINST usr/include/linux/if_fddi.h
HDRINST usr/include/linux/bpqether.h
HDRINST usr/include/linux/sysinfo.h
HDRINST usr/include/linux/auto_dev-ioctl.h
HDRINST usr/include/linux/nfs4_mount.h
HDRINST usr/include/linux/keyboard.h
HDRINST usr/include/linux/virtio_mmio.h
HDRINST usr/include/linux/input.h
HDRINST usr/include/linux/qnxtypes.h
HDRINST usr/include/linux/mdio.h
HDRINST usr/include/linux/lwtunnel.h
HDRINST usr/include/linux/gfs2_ondisk.h
HDRINST usr/include/linux/nfs4.h
HDRINST usr/include/linux/ptp_clock.h
HDRINST usr/include/linux/nubus.h
HDRINST usr/include/linux/if_bonding.h
HDRINST usr/include/linux/kcov.h
HDRINST usr/include/linux/fadvise.h
HDRINST usr/include/linux/taskstats.h
HDRINST usr/include/linux/veth.h
HDRINST usr/include/linux/atm.h
HDRINST usr/include/linux/ipmi.h
HDRINST usr/include/linux/kdev_t.h
HDRINST usr/include/linux/mount.h
HDRINST usr/include/linux/shm.h
HDRINST usr/include/linux/resource.h
HDRINST usr/include/linux/prctl.h
HDRINST usr/include/linux/watch_queue.h
HDRINST usr/include/linux/sched.h
HDRINST usr/include/linux/phonet.h
HDRINST usr/include/linux/random.h
HDRINST usr/include/linux/tty.h
HDRINST usr/include/linux/apm_bios.h
HDRINST usr/include/linux/fd.h
HDRINST usr/include/linux/um_timetravel.h
HDRINST usr/include/linux/tls.h
HDRINST usr/include/linux/rpmsg_types.h
HDRINST usr/include/linux/pfrut.h
HDRINST usr/include/linux/mei.h
HDRINST usr/include/linux/fsi.h
HDRINST usr/include/linux/rds.h
HDRINST usr/include/linux/if_x25.h
HDRINST usr/include/linux/param.h
HDRINST usr/include/linux/netdevice.h
HDRINST usr/include/linux/binfmts.h
HDRINST usr/include/linux/if_pppox.h
HDRINST usr/include/linux/sockios.h
HDRINST usr/include/linux/kcm.h
HDRINST usr/include/linux/virtio_9p.h
HDRINST usr/include/linux/genwqe/genwqe_card.h
HDRINST usr/include/linux/if_tun.h
HDRINST usr/include/linux/if_ether.h
HDRINST usr/include/linux/kvm_para.h
HDRINST usr/include/linux/kernel-page-flags.h
HDRINST usr/include/linux/cdrom.h
HDRINST usr/include/linux/un.h
HDRINST usr/include/linux/module.h
HDRINST usr/include/linux/mqueue.h
HDRINST usr/include/linux/a.out.h
HDRINST usr/include/linux/input-event-codes.h
HDRINST usr/include/linux/coda.h
HDRINST usr/include/linux/rio_mport_cdev.h
HDRINST usr/include/linux/ipsec.h
HDRINST usr/include/linux/blkpg.h
HDRINST usr/include/linux/blkzoned.h
HDRINST usr/include/linux/netfilter_bridge/ebt_arpreply.h
HDRINST usr/include/linux/netfilter_bridge/ebt_redirect.h
HDRINST usr/include/linux/netfilter_bridge/ebt_nflog.h
HDRINST usr/include/linux/netfilter_bridge/ebt_802_3.h
HDRINST usr/include/linux/netfilter_bridge/ebt_nat.h
HDRINST usr/include/linux/netfilter_bridge/ebt_mark_m.h
HDRINST usr/include/linux/netfilter_bridge/ebtables.h
HDRINST usr/include/linux/netfilter_bridge/ebt_vlan.h
HDRINST usr/include/linux/netfilter_bridge/ebt_limit.h
HDRINST usr/include/linux/netfilter_bridge/ebt_log.h
HDRINST usr/include/linux/netfilter_bridge/ebt_stp.h
HDRINST usr/include/linux/netfilter_bridge/ebt_pkttype.h
HDRINST usr/include/linux/netfilter_bridge/ebt_ip.h
HDRINST usr/include/linux/netfilter_bridge/ebt_ip6.h
HDRINST usr/include/linux/netfilter_bridge/ebt_arp.h
HDRINST usr/include/linux/netfilter_bridge/ebt_mark_t.h
HDRINST usr/include/linux/netfilter_bridge/ebt_among.h
LD /kernel/build64/tools/objtool/libsubcmd/libsubcmd-in.o
HDRINST usr/include/linux/reiserfs_fs.h
HDRINST usr/include/linux/cciss_ioctl.h
HDRINST usr/include/linux/fsmap.h
HDRINST usr/include/linux/smiapp.h
HDRINST usr/include/linux/switchtec_ioctl.h
HDRINST usr/include/linux/atmdev.h
HDRINST usr/include/linux/hpet.h
HDRINST usr/include/linux/virtio_config.h
HDRINST usr/include/linux/string.h
HDRINST usr/include/linux/kfd_sysfs.h
HDRINST usr/include/linux/inet_diag.h
HDRINST usr/include/linux/xattr.h
HDRINST usr/include/linux/netdev.h
HDRINST usr/include/linux/iommufd.h
HDRINST usr/include/linux/errno.h
HDRINST usr/include/linux/icmp.h
HDRINST usr/include/linux/i2o-dev.h
HDRINST usr/include/linux/pg.h
HDRINST usr/include/linux/if_bridge.h
HDRINST usr/include/linux/thermal.h
HDRINST usr/include/linux/uinput.h
HDRINST usr/include/linux/dqblk_xfs.h
HDRINST usr/include/linux/v4l2-common.h
HDRINST usr/include/linux/nvram.h
HDRINST usr/include/linux/if_vlan.h
HDRINST usr/include/linux/uhid.h
HDRINST usr/include/linux/omap3isp.h
HDRINST usr/include/linux/rose.h
HDRINST usr/include/linux/phantom.h
HDRINST usr/include/linux/ipmi_msgdefs.h
HDRINST usr/include/linux/bcm933xx_hcs.h
HDRINST usr/include/linux/bpf.h
HDRINST usr/include/linux/mempolicy.h
HDRINST usr/include/linux/efs_fs_sb.h
HDRINST usr/include/linux/nexthop.h
HDRINST usr/include/linux/net_dropmon.h
HDRINST usr/include/linux/surface_aggregator/cdev.h
AR /kernel/build64/tools/objtool/libsubcmd/libsubcmd.a
HDRINST usr/include/linux/surface_aggregator/dtx.h
HDRINST usr/include/linux/net.h
HDRINST usr/include/linux/mii.h
HDRINST usr/include/linux/cm4000_cs.h
HDRINST usr/include/linux/virtio_pcidev.h
HDRINST usr/include/linux/termios.h
HDRINST usr/include/linux/cgroupstats.h
HDRINST usr/include/linux/mpls.h
HDRINST usr/include/linux/iommu.h
HDRINST usr/include/linux/toshiba.h
HDRINST usr/include/linux/virtio_scsi.h
HDRINST usr/include/linux/zorro.h
HDRINST usr/include/linux/chio.h
HDRINST usr/include/linux/pkt_sched.h
HDRINST usr/include/linux/cramfs_fs.h
HDRINST usr/include/linux/nfs3.h
HDRINST usr/include/linux/vfio_ccw.h
HDRINST usr/include/linux/atm_nicstar.h
HDRINST usr/include/linux/ncsi.h
HDRINST usr/include/linux/virtio_net.h
HDRINST usr/include/linux/ioctl.h
HDRINST usr/include/linux/stddef.h
HDRINST usr/include/linux/limits.h
HDRINST usr/include/linux/ipmi_bmc.h
HDRINST usr/include/linux/netfilter_arp.h
HDRINST usr/include/linux/if_addr.h
HDRINST usr/include/linux/rpmsg.h
HDRINST usr/include/linux/media-bus-format.h
HDRINST usr/include/linux/kernelcapi.h
HDRINST usr/include/linux/ppp_defs.h
HDRINST usr/include/linux/ethtool.h
HDRINST usr/include/linux/aspeed-video.h
HDRINST usr/include/linux/hdlc.h
HDRINST usr/include/linux/fscrypt.h
HDRINST usr/include/linux/batadv_packet.h
HDRINST usr/include/linux/uuid.h
HDRINST usr/include/linux/capi.h
HDRINST usr/include/linux/mptcp.h
HDRINST usr/include/linux/hidraw.h
HDRINST usr/include/linux/virtio_console.h
HDRINST usr/include/linux/irqnr.h
HDRINST usr/include/linux/coresight-stm.h
HDRINST usr/include/linux/cxl_mem.h
HDRINST usr/include/linux/iso_fs.h
HDRINST usr/include/linux/virtio_blk.h
HDRINST usr/include/linux/udf_fs_i.h
HDRINST usr/include/linux/coff.h
HDRINST usr/include/linux/dma-buf.h
HDRINST usr/include/linux/ife.h
HDRINST usr/include/linux/agpgart.h
HDRINST usr/include/linux/socket.h
HDRINST usr/include/linux/nilfs2_ondisk.h
HDRINST usr/include/linux/connector.h
HDRINST usr/include/linux/auto_fs4.h
HDRINST usr/include/linux/bt-bmc.h
HDRINST usr/include/linux/map_to_7segment.h
HDRINST usr/include/linux/tc_act/tc_skbedit.h
CC /kernel/build64/tools/objtool/weak.o
HDRINST usr/include/linux/tc_act/tc_ctinfo.h
CC /kernel/build64/tools/objtool/check.o
HDRINST usr/include/linux/tc_act/tc_defact.h
CC /kernel/build64/tools/objtool/special.o
HDRINST usr/include/linux/tc_act/tc_gact.h
CC /kernel/build64/tools/objtool/builtin-check.o
HDRINST usr/include/linux/tc_act/tc_vlan.h
MKDIR /kernel/build64/tools/objtool/arch/x86/
CC /kernel/build64/tools/objtool/elf.o
HDRINST usr/include/linux/tc_act/tc_skbmod.h
CC /kernel/build64/tools/objtool/objtool.o
CC /kernel/build64/tools/objtool/orc_gen.o
HDRINST usr/include/linux/tc_act/tc_sample.h
HDRINST usr/include/linux/tc_act/tc_tunnel_key.h
MKDIR /kernel/build64/tools/objtool/arch/x86/lib/
CC /kernel/build64/tools/objtool/orc_dump.o
CC /kernel/build64/tools/objtool/arch/x86/special.o
HDRINST usr/include/linux/tc_act/tc_gate.h
CC /kernel/build64/tools/objtool/libstring.o
HDRINST usr/include/linux/tc_act/tc_mirred.h
GEN /kernel/build64/tools/objtool/arch/x86/lib/inat-tables.c
CC /kernel/build64/tools/objtool/libctype.o
HDRINST usr/include/linux/tc_act/tc_nat.h
CC /kernel/build64/tools/objtool/str_error_r.o
HDRINST usr/include/linux/tc_act/tc_csum.h
CC /kernel/build64/tools/objtool/librbtree.o
HDRINST usr/include/linux/tc_act/tc_connmark.h
HDRINST usr/include/linux/tc_act/tc_ife.h
HDRINST usr/include/linux/tc_act/tc_mpls.h
HDRINST usr/include/linux/tc_act/tc_ct.h
HDRINST usr/include/linux/tc_act/tc_pedit.h
HDRINST usr/include/linux/tc_act/tc_bpf.h
HDRINST usr/include/linux/tc_act/tc_ipt.h
HDRINST usr/include/linux/netrom.h
HDRINST usr/include/linux/joystick.h
HDRINST usr/include/linux/falloc.h
HDRINST usr/include/linux/cycx_cfm.h
HDRINST usr/include/linux/omapfb.h
HDRINST usr/include/linux/msdos_fs.h
HDRINST usr/include/linux/virtio_types.h
HDRINST usr/include/linux/mroute.h
HDRINST usr/include/linux/psample.h
HDRINST usr/include/linux/ipv6.h
HDRINST usr/include/linux/dw100.h
HDRINST usr/include/linux/psp-sev.h
HDRINST usr/include/linux/vfio.h
HDRINST usr/include/linux/if_ppp.h
HDRINST usr/include/linux/byteorder/big_endian.h
HDRINST usr/include/linux/byteorder/little_endian.h
HDRINST usr/include/linux/comedi.h
HDRINST usr/include/linux/scif_ioctl.h
HDRINST usr/include/linux/timerfd.h
HDRINST usr/include/linux/firewire-constants.h
HDRINST usr/include/linux/time_types.h
HDRINST usr/include/linux/virtio_snd.h
HDRINST usr/include/linux/ppp-ioctl.h
HDRINST usr/include/linux/fib_rules.h
HDRINST usr/include/linux/gen_stats.h
HDRINST usr/include/linux/virtio_iommu.h
HDRINST usr/include/linux/genetlink.h
HDRINST usr/include/linux/uvcvideo.h
HDRINST usr/include/linux/pfkeyv2.h
HDRINST usr/include/linux/soundcard.h
HDRINST usr/include/linux/times.h
HDRINST usr/include/linux/nfc.h
HDRINST usr/include/linux/affs_hardblocks.h
HDRINST usr/include/linux/nilfs2_api.h
HDRINST usr/include/linux/rseq.h
HDRINST usr/include/linux/caif/caif_socket.h
HDRINST usr/include/linux/caif/if_caif.h
HDRINST usr/include/linux/i2c-dev.h
HDRINST usr/include/linux/cuda.h
HDRINST usr/include/linux/cn_proc.h
HDRINST usr/include/linux/parport.h
HDRINST usr/include/linux/v4l2-controls.h
HDRINST usr/include/linux/hsi/cs-protocol.h
HDRINST usr/include/linux/hsi/hsi_char.h
HDRINST usr/include/linux/seg6_genl.h
HDRINST usr/include/linux/am437x-vpfe.h
HDRINST usr/include/linux/amt.h
HDRINST usr/include/linux/netconf.h
HDRINST usr/include/linux/erspan.h
HDRINST usr/include/linux/nsfs.h
HDRINST usr/include/linux/xilinx-v4l2-controls.h
HDRINST usr/include/linux/aspeed-p2a-ctrl.h
HDRINST usr/include/linux/vfio_zdev.h
HDRINST usr/include/linux/serio.h
HDRINST usr/include/linux/acrn.h
HDRINST usr/include/linux/nfs2.h
HDRINST usr/include/linux/virtio_pci.h
HDRINST usr/include/linux/ipc.h
HDRINST usr/include/linux/ethtool_netlink.h
HDRINST usr/include/linux/kd.h
HDRINST usr/include/linux/elf.h
CC /kernel/build64/tools/objtool/arch/x86/decode.o
HDRINST usr/include/linux/videodev2.h
HDRINST usr/include/linux/if_alg.h
HDRINST usr/include/linux/sonypi.h
HDRINST usr/include/linux/fsverity.h
HDRINST usr/include/linux/if.h
HDRINST usr/include/linux/btrfs.h
HDRINST usr/include/linux/vm_sockets_diag.h
HDRINST usr/include/linux/netfilter_bridge.h
HDRINST usr/include/linux/packet_diag.h
HDRINST usr/include/linux/netfilter_ipv4.h
HDRINST usr/include/linux/kvm.h
HDRINST usr/include/linux/pci.h
HDRINST usr/include/linux/if_addrlabel.h
HDRINST usr/include/linux/hdlcdrv.h
HDRINST usr/include/linux/cfm_bridge.h
HDRINST usr/include/linux/fiemap.h
HDRINST usr/include/linux/dm-ioctl.h
HDRINST usr/include/linux/aspeed-lpc-ctrl.h
HDRINST usr/include/linux/atmioc.h
HDRINST usr/include/linux/dlm.h
HDRINST usr/include/linux/pci_regs.h
HDRINST usr/include/linux/cachefiles.h
HDRINST usr/include/linux/membarrier.h
HDRINST usr/include/linux/nfs_idmap.h
HDRINST usr/include/linux/ip.h
HDRINST usr/include/linux/atm_he.h
HDRINST usr/include/linux/nfsd/export.h
HDRINST usr/include/linux/nfsd/stats.h
HDRINST usr/include/linux/nfsd/debug.h
HDRINST usr/include/linux/nfsd/cld.h
HDRINST usr/include/linux/ip_vs.h
HDRINST usr/include/linux/vmcore.h
HDRINST usr/include/linux/vbox_vmmdev_types.h
HDRINST usr/include/linux/dvb/osd.h
HDRINST usr/include/linux/dvb/dmx.h
HDRINST usr/include/linux/dvb/net.h
HDRINST usr/include/linux/dvb/frontend.h
HDRINST usr/include/linux/dvb/ca.h
HDRINST usr/include/linux/dvb/version.h
HDRINST usr/include/linux/dvb/video.h
HDRINST usr/include/linux/dvb/audio.h
HDRINST usr/include/linux/nfs.h
HDRINST usr/include/linux/if_link.h
HDRINST usr/include/linux/wait.h
HDRINST usr/include/linux/icmpv6.h
HDRINST usr/include/linux/media.h
HDRINST usr/include/linux/seg6_local.h
HDRINST usr/include/linux/openvswitch.h
HDRINST usr/include/linux/atmsap.h
HDRINST usr/include/linux/bpfilter.h
HDRINST usr/include/linux/fpga-dfl.h
HDRINST usr/include/linux/userio.h
HDRINST usr/include/linux/signal.h
HDRINST usr/include/linux/map_to_14segment.h
HDRINST usr/include/linux/hdreg.h
HDRINST usr/include/linux/utime.h
HDRINST usr/include/linux/usbdevice_fs.h
HDRINST usr/include/linux/timex.h
HDRINST usr/include/linux/if_fc.h
HDRINST usr/include/linux/reiserfs_xattr.h
HDRINST usr/include/linux/hw_breakpoint.h
HDRINST usr/include/linux/quota.h
HDRINST usr/include/linux/ioprio.h
HDRINST usr/include/linux/eventpoll.h
HDRINST usr/include/linux/atmclip.h
HDRINST usr/include/linux/can.h
HDRINST usr/include/linux/if_team.h
HDRINST usr/include/linux/usbip.h
HDRINST usr/include/linux/stat.h
HDRINST usr/include/linux/fou.h
HDRINST usr/include/linux/hash_info.h
HDRINST usr/include/linux/ppp-comp.h
HDRINST usr/include/linux/ip6_tunnel.h
HDRINST usr/include/linux/tipc_netlink.h
HDRINST usr/include/linux/in.h
HDRINST usr/include/linux/wireguard.h
HDRINST usr/include/linux/btf.h
HDRINST usr/include/linux/batman_adv.h
HDRINST usr/include/linux/fcntl.h
HDRINST usr/include/linux/if_ltalk.h
HDRINST usr/include/linux/i2c.h
HDRINST usr/include/linux/atm_idt77105.h
HDRINST usr/include/linux/kexec.h
HDRINST usr/include/linux/arm_sdei.h
HDRINST usr/include/linux/netfilter_ipv6/ip6_tables.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_ah.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_NPT.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_rt.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_REJECT.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_opts.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_srh.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_LOG.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_mh.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_HL.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_hl.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_frag.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_ipv6header.h
HDRINST usr/include/linux/minix_fs.h
HDRINST usr/include/linux/aio_abi.h
HDRINST usr/include/linux/pktcdvd.h
HDRINST usr/include/linux/libc-compat.h
HDRINST usr/include/linux/atmlec.h
HDRINST usr/include/linux/signalfd.h
HDRINST usr/include/linux/bpf_common.h
HDRINST usr/include/linux/seg6_iptunnel.h
HDRINST usr/include/linux/synclink.h
HDRINST usr/include/linux/mpls_iptunnel.h
HDRINST usr/include/linux/mctp.h
HDRINST usr/include/linux/if_xdp.h
HDRINST usr/include/linux/llc.h
HDRINST usr/include/linux/atmsvc.h
HDRINST usr/include/linux/sed-opal.h
HDRINST usr/include/linux/sock_diag.h
HDRINST usr/include/linux/time.h
HDRINST usr/include/linux/securebits.h
HDRINST usr/include/linux/fsl_hypervisor.h
HDRINST usr/include/linux/if_hippi.h
HDRINST usr/include/linux/dlm_netlink.h
HDRINST usr/include/linux/seccomp.h
HDRINST usr/include/linux/oom.h
HDRINST usr/include/linux/filter.h
HDRINST usr/include/linux/inotify.h
HDRINST usr/include/linux/rfkill.h
HDRINST usr/include/linux/reboot.h
HDRINST usr/include/linux/can/vxcan.h
HDRINST usr/include/linux/can/j1939.h
HDRINST usr/include/linux/can/netlink.h
HDRINST usr/include/linux/can/bcm.h
HDRINST usr/include/linux/can/raw.h
HDRINST usr/include/linux/can/gw.h
HDRINST usr/include/linux/can/error.h
HDRINST usr/include/linux/can/isotp.h
HDRINST usr/include/linux/if_eql.h
HDRINST usr/include/linux/hiddev.h
HDRINST usr/include/linux/blktrace_api.h
HDRINST usr/include/linux/ccs.h
HDRINST usr/include/linux/ioam6.h
HDRINST usr/include/linux/hsr_netlink.h
HDRINST usr/include/linux/mmc/ioctl.h
HDRINST usr/include/linux/bfs_fs.h
HDRINST usr/include/linux/rio_cm_cdev.h
HDRINST usr/include/linux/uleds.h
HDRINST usr/include/linux/mrp_bridge.h
HDRINST usr/include/linux/adb.h
HDRINST usr/include/linux/pmu.h
HDRINST usr/include/linux/udmabuf.h
HDRINST usr/include/linux/kcmp.h
HDRINST usr/include/linux/dma-heap.h
HDRINST usr/include/linux/userfaultfd.h
HDRINST usr/include/linux/netfilter_arp/arpt_mangle.h
HDRINST usr/include/linux/netfilter_arp/arp_tables.h
HDRINST usr/include/linux/tipc.h
HDRINST usr/include/linux/virtio_ids.h
HDRINST usr/include/linux/l2tp.h
HDRINST usr/include/linux/devlink.h
HDRINST usr/include/linux/virtio_gpio.h
HDRINST usr/include/linux/dcbnl.h
HDRINST usr/include/linux/cyclades.h
HDRINST usr/include/sound/intel/avs/tokens.h
HDRINST usr/include/sound/sof/fw.h
HDRINST usr/include/sound/sof/abi.h
HDRINST usr/include/sound/sof/tokens.h
HDRINST usr/include/sound/sof/header.h
HDRINST usr/include/sound/sfnt_info.h
HDRINST usr/include/sound/usb_stream.h
HDRINST usr/include/sound/asequencer.h
HDRINST usr/include/sound/tlv.h
HDRINST usr/include/sound/asound.h
HDRINST usr/include/sound/asoc.h
HDRINST usr/include/sound/sb16_csp.h
HDRINST usr/include/sound/compress_offload.h
HDRINST usr/include/sound/hdsp.h
HDRINST usr/include/sound/emu10k1.h
HDRINST usr/include/sound/snd_ar_tokens.h
HDRINST usr/include/sound/snd_sst_tokens.h
HDRINST usr/include/sound/asound_fm.h
HDRINST usr/include/sound/hdspm.h
HDRINST usr/include/sound/compress_params.h
HDRINST usr/include/sound/firewire.h
HDRINST usr/include/sound/skl-tplg-interface.h
HDRINST usr/include/scsi/scsi_bsg_ufs.h
HDRINST usr/include/scsi/scsi_netlink_fc.h
HDRINST usr/include/scsi/scsi_bsg_mpi3mr.h
HDRINST usr/include/scsi/fc/fc_ns.h
HDRINST usr/include/scsi/fc/fc_fs.h
HDRINST usr/include/scsi/fc/fc_els.h
HDRINST usr/include/scsi/fc/fc_gs.h
HDRINST usr/include/scsi/scsi_bsg_fc.h
HDRINST usr/include/scsi/cxlflash_ioctl.h
HDRINST usr/include/scsi/scsi_netlink.h
HDRINST usr/include/linux/version.h
HDRINST usr/include/asm/processor-flags.h
HDRINST usr/include/asm/auxvec.h
HDRINST usr/include/asm/svm.h
HDRINST usr/include/asm/bitsperlong.h
HDRINST usr/include/asm/kvm_perf.h
HDRINST usr/include/asm/mce.h
HDRINST usr/include/asm/posix_types.h
HDRINST usr/include/asm/msr.h
HDRINST usr/include/asm/sigcontext32.h
HDRINST usr/include/asm/mman.h
HDRINST usr/include/asm/shmbuf.h
HDRINST usr/include/asm/e820.h
HDRINST usr/include/asm/posix_types_64.h
HDRINST usr/include/asm/vsyscall.h
HDRINST usr/include/asm/msgbuf.h
HDRINST usr/include/asm/swab.h
HDRINST usr/include/asm/statfs.h
HDRINST usr/include/asm/posix_types_x32.h
HDRINST usr/include/asm/ptrace.h
HDRINST usr/include/asm/unistd.h
HDRINST usr/include/asm/ist.h
HDRINST usr/include/asm/prctl.h
HDRINST usr/include/asm/boot.h
HDRINST usr/include/asm/sigcontext.h
HDRINST usr/include/asm/posix_types_32.h
HDRINST usr/include/asm/kvm_para.h
HDRINST usr/include/asm/a.out.h
HDRINST usr/include/asm/mtrr.h
HDRINST usr/include/asm/amd_hsmp.h
HDRINST usr/include/asm/hwcap2.h
HDRINST usr/include/asm/ptrace-abi.h
HDRINST usr/include/asm/vm86.h
HDRINST usr/include/asm/vmx.h
HDRINST usr/include/asm/ldt.h
HDRINST usr/include/asm/perf_regs.h
HDRINST usr/include/asm/kvm.h
HDRINST usr/include/asm/debugreg.h
HDRINST usr/include/asm/signal.h
HDRINST usr/include/asm/bootparam.h
HDRINST usr/include/asm/siginfo.h
HDRINST usr/include/asm/hw_breakpoint.h
HDRINST usr/include/asm/stat.h
HDRINST usr/include/asm/setup.h
HDRINST usr/include/asm/sembuf.h
HDRINST usr/include/asm/sgx.h
HDRINST usr/include/asm/ucontext.h
HDRINST usr/include/asm/byteorder.h
HDRINST usr/include/asm/unistd_64.h
HDRINST usr/include/asm/ioctls.h
HDRINST usr/include/asm/bpf_perf_event.h
HDRINST usr/include/asm/types.h
HDRINST usr/include/asm/poll.h
HDRINST usr/include/asm/resource.h
HDRINST usr/include/asm/param.h
HDRINST usr/include/asm/sockios.h
HDRINST usr/include/asm/errno.h
HDRINST usr/include/asm/unistd_x32.h
HDRINST usr/include/asm/termios.h
HDRINST usr/include/asm/ioctl.h
HDRINST usr/include/asm/socket.h
HDRINST usr/include/asm/unistd_32.h
HDRINST usr/include/asm/termbits.h
HDRINST usr/include/asm/fcntl.h
HDRINST usr/include/asm/ipcbuf.h
HOSTLD scripts/mod/modpost
CC kernel/bounds.s
CHKSHA1 ../include/linux/atomic/atomic-arch-fallback.h
CHKSHA1 ../include/linux/atomic/atomic-instrumented.h
CHKSHA1 ../include/linux/atomic/atomic-long.h
UPD include/generated/timeconst.h
UPD include/generated/bounds.h
CC arch/x86/kernel/asm-offsets.s
LD /kernel/build64/tools/objtool/arch/x86/objtool-in.o
UPD include/generated/asm-offsets.h
CALL ../scripts/checksyscalls.sh
LD /kernel/build64/tools/objtool/objtool-in.o
LINK /kernel/build64/tools/objtool/objtool
LDS scripts/module.lds
CC ipc/compat.o
CC ipc/util.o
HOSTCC usr/gen_init_cpio
AR certs/built-in.a
CC io_uring/io_uring.o
CC ipc/msgutil.o
CC io_uring/xattr.o
CC init/main.o
CC ipc/msg.o
CC io_uring/nop.o
CC ipc/sem.o
CC io_uring/fs.o
CC arch/x86/pci/i386.o
AS arch/x86/lib/clear_page_64.o
CC ipc/shm.o
CC security/commoncap.o
AR arch/x86/video/built-in.a
UPD init/utsversion-tmp.h
CC arch/x86/realmode/init.o
CC ipc/syscall.o
CC arch/x86/power/cpu.o
CC net/llc/llc_core.o
AR virt/lib/built-in.a
AS arch/x86/crypto/aesni-intel_asm.o
CC net/ethernet/eth.o
CC net/sched/sch_generic.o
AR arch/x86/ia32/built-in.a
CC net/802/p8022.o
CC fs/nfs_common/grace.o
CC fs/iomap/trace.o
CC net/netlink/af_netlink.o
AR fs/quota/built-in.a
CC block/partitions/core.o
CC net/core/sock.o
CC [M] arch/x86/video/fbdev.o
AR drivers/irqchip/built-in.a
CC security/keys/gc.o
CC arch/x86/power/hibernate_64.o
AR sound/i2c/other/built-in.a
CC [M] virt/lib/irqbypass.o
CC fs/notify/dnotify/dnotify.o
CC sound/core/seq/seq.o
CC arch/x86/mm/pat/set_memory.o
CC arch/x86/events/amd/core.o
AR arch/x86/platform/atom/built-in.a
AR sound/drivers/opl3/built-in.a
CC arch/x86/kernel/fpu/init.o
AR sound/i2c/built-in.a
AR sound/drivers/opl4/built-in.a
CC block/partitions/ldm.o
CC arch/x86/lib/cmdline.o
AR drivers/bus/mhi/built-in.a
CC ipc/ipc_sysctl.o
AR arch/x86/platform/ce4100/built-in.a
CC fs/iomap/iter.o
CC lib/kunit/test.o
AR drivers/bus/built-in.a
CC arch/x86/entry/vdso/vma.o
AR sound/drivers/mpu401/built-in.a
CC arch/x86/platform/efi/memmap.o
CC mm/kasan/common.o
AR sound/drivers/vx/built-in.a
CC arch/x86/crypto/aesni-intel_glue.o
CC crypto/api.o
CC kernel/sched/core.o
AR drivers/phy/allwinner/built-in.a
AR sound/drivers/pcsp/built-in.a
AR drivers/phy/amlogic/built-in.a
AR drivers/phy/broadcom/built-in.a
AR sound/drivers/built-in.a
AR drivers/phy/cadence/built-in.a
AR drivers/phy/hisilicon/built-in.a
AR drivers/phy/freescale/built-in.a
AR drivers/phy/ingenic/built-in.a
AR sound/isa/ad1816a/built-in.a
AR drivers/phy/intel/built-in.a
AR sound/isa/ad1848/built-in.a
AR drivers/phy/lantiq/built-in.a
AS arch/x86/lib/cmpxchg16b_emu.o
AR sound/isa/cs423x/built-in.a
AR drivers/phy/marvell/built-in.a
AR drivers/phy/mediatek/built-in.a
CC arch/x86/lib/copy_mc.o
AR sound/isa/es1688/built-in.a
AR drivers/phy/microchip/built-in.a
AR sound/isa/galaxy/built-in.a
AR drivers/phy/motorola/built-in.a
AR sound/isa/gus/built-in.a
AR drivers/phy/mscc/built-in.a
AR sound/isa/msnd/built-in.a
AR drivers/phy/qualcomm/built-in.a
AR sound/isa/opti9xx/built-in.a
AR drivers/phy/ralink/built-in.a
AR sound/isa/sb/built-in.a
AR drivers/phy/renesas/built-in.a
AR sound/isa/wavefront/built-in.a
AR drivers/phy/rockchip/built-in.a
AR sound/isa/wss/built-in.a
AR drivers/phy/samsung/built-in.a
AR sound/isa/built-in.a
GEN usr/initramfs_data.cpio
AR drivers/phy/socionext/built-in.a
COPY usr/initramfs_inc_data
AS usr/initramfs_data.o
CC sound/core/sound.o
AR drivers/phy/st/built-in.a
AR drivers/phy/sunplus/built-in.a
AR usr/built-in.a
AR drivers/phy/tegra/built-in.a
AR drivers/phy/ti/built-in.a
AR drivers/phy/xilinx/built-in.a
CC drivers/phy/phy-core.o
CC fs/proc/task_mmu.o
AR virt/built-in.a
AS arch/x86/lib/copy_mc_64.o
CC arch/x86/pci/init.o
AS arch/x86/lib/copy_page_64.o
CC sound/core/seq/seq_lock.o
AS arch/x86/lib/copy_user_64.o
CC block/bdev.o
CC arch/x86/lib/cpu.o
CC arch/x86/kernel/fpu/bugs.o
CC net/802/psnap.o
AS arch/x86/realmode/rm/header.o
AS arch/x86/realmode/rm/trampoline_64.o
CC security/keys/key.o
CC security/keys/keyring.o
CC net/llc/llc_input.o
AS arch/x86/realmode/rm/stack.o
CC arch/x86/kernel/cpu/mce/core.o
AR fs/notify/dnotify/built-in.a
AS arch/x86/realmode/rm/reboot.o
CC fs/notify/inotify/inotify_fsnotify.o
AR drivers/pinctrl/actions/built-in.a
AR fs/nfs_common/built-in.a
AR drivers/pinctrl/bcm/built-in.a
CC arch/x86/kernel/cpu/mce/severity.o
AR drivers/pinctrl/cirrus/built-in.a
CC arch/x86/kernel/cpu/mce/genpool.o
CC kernel/sched/fair.o
AS arch/x86/realmode/rm/wakeup_asm.o
CC arch/x86/kernel/acpi/boot.o
AR drivers/pinctrl/freescale/built-in.a
CC arch/x86/kernel/apic/apic.o
CC drivers/pinctrl/intel/pinctrl-baytrail.o
CC arch/x86/kernel/fpu/core.o
CC arch/x86/realmode/rm/wakemain.o
CC lib/kunit/resource.o
CC drivers/pinctrl/intel/pinctrl-intel.o
CC arch/x86/kernel/fpu/regset.o
CC arch/x86/platform/efi/quirks.o
CC [M] drivers/pinctrl/intel/pinctrl-cherryview.o
CC arch/x86/entry/vdso/extable.o
AS arch/x86/power/hibernate_asm_64.o
CC crypto/cipher.o
CC mm/kasan/report.o
CC arch/x86/realmode/rm/video-mode.o
AS arch/x86/realmode/rm/copy.o
CC arch/x86/power/hibernate.o
CC sound/core/seq/seq_clientmgr.o
CC fs/iomap/buffered-io.o
CC [M] drivers/pinctrl/intel/pinctrl-broxton.o
CC sound/core/init.o
CC arch/x86/lib/delay.o
AS arch/x86/realmode/rm/bioscall.o
CC arch/x86/realmode/rm/regs.o
CC arch/x86/realmode/rm/video-vga.o
AS arch/x86/crypto/aesni-intel_avx-x86_64.o
CC arch/x86/events/amd/lbr.o
CC arch/x86/pci/mmconfig_64.o
CC arch/x86/realmode/rm/video-vesa.o
CC block/partitions/msdos.o
CC lib/kunit/static_stub.o
CC arch/x86/kernel/acpi/sleep.o
CC kernel/locking/mutex.o
CC fs/notify/inotify/inotify_user.o
AR net/ethernet/built-in.a
CC kernel/locking/semaphore.o
CC kernel/locking/rwsem.o
CC arch/x86/realmode/rm/video-bios.o
AS arch/x86/lib/getuser.o
CC kernel/locking/percpu-rwsem.o
CC crypto/compress.o
GEN arch/x86/lib/inat-tables.c
PASYMS arch/x86/realmode/rm/pasyms.h
LDS arch/x86/realmode/rm/realmode.lds
CC arch/x86/lib/insn-eval.o
LD arch/x86/realmode/rm/realmode.elf
AR drivers/phy/built-in.a
AS arch/x86/crypto/aes_ctrby8_avx-x86_64.o
RELOCS arch/x86/realmode/rm/realmode.relocs
OBJCOPY arch/x86/realmode/rm/realmode.bin
CC net/802/stp.o
AS arch/x86/realmode/rmpiggy.o
AR arch/x86/realmode/built-in.a
CC net/llc/llc_output.o
CC ipc/mqueue.o
CC [M] drivers/pinctrl/intel/pinctrl-geminilake.o
CC block/partitions/efi.o
AS [M] arch/x86/crypto/ghash-clmulni-intel_asm.o
CC mm/kasan/init.o
CC [M] arch/x86/crypto/ghash-clmulni-intel_glue.o
CC init/do_mounts.o
CC arch/x86/entry/vdso/vdso32-setup.o
CC init/do_mounts_initrd.o
CC arch/x86/entry/vsyscall/vsyscall_64.o
CC init/initramfs.o
AS arch/x86/entry/vsyscall/vsyscall_emu_64.o
CC arch/x86/mm/pat/memtype.o
AR arch/x86/power/built-in.a
CC init/calibrate.o
CC ipc/namespace.o
CC arch/x86/platform/efi/efi.o
CC fs/proc/inode.o
CC lib/kunit/string-stream.o
LDS arch/x86/entry/vdso/vdso.lds
CC crypto/algapi.o
AS arch/x86/entry/vdso/vdso-note.o
CC arch/x86/pci/direct.o
CC arch/x86/entry/vdso/vclock_gettime.o
CC lib/kunit/assert.o
CC arch/x86/events/amd/ibs.o
CC security/keys/keyctl.o
CC arch/x86/kernel/fpu/signal.o
CC init/init_task.o
AS arch/x86/kernel/acpi/wakeup_64.o
CC lib/kunit/try-catch.o
CC arch/x86/kernel/acpi/apei.o
CC arch/x86/kernel/acpi/cppc.o
CC [M] drivers/pinctrl/intel/pinctrl-sunrisepoint.o
CC arch/x86/kernel/kprobes/core.o
CC kernel/sched/build_policy.o
CC lib/kunit/executor.o
AS [M] arch/x86/crypto/crc32-pclmul_asm.o
CC kernel/sched/build_utility.o
CC [M] arch/x86/crypto/crc32-pclmul_glue.o
CC net/sched/sch_mq.o
CC arch/x86/kernel/kprobes/opt.o
CC arch/x86/kernel/apic/apic_common.o
AR net/llc/built-in.a
CC lib/kunit/hooks.o
CC arch/x86/kernel/apic/apic_noop.o
AR net/802/built-in.a
CC ipc/mq_sysctl.o
AR net/bpf/built-in.a
CC fs/notify/fanotify/fanotify.o
CC fs/notify/fsnotify.o
CC net/sched/sch_frag.o
AR fs/notify/inotify/built-in.a
CC fs/notify/fanotify/fanotify_user.o
CC arch/x86/lib/insn.o
CC drivers/gpio/gpiolib.o
CC mm/kasan/generic.o
CC arch/x86/entry/vdso/vgetcpu.o
CC sound/core/seq/seq_memory.o
CC arch/x86/kernel/cpu/mce/intel.o
CC fs/proc/root.o
AR block/partitions/built-in.a
AR arch/x86/entry/vsyscall/built-in.a
HOSTCC arch/x86/entry/vdso/vdso2c
CC block/fops.o
AR drivers/pinctrl/mediatek/built-in.a
AS arch/x86/entry/entry.o
CC arch/x86/events/intel/core.o
CC arch/x86/kernel/cpu/mce/threshold.o
CC arch/x86/pci/mmconfig-shared.o
CC arch/x86/mm/pat/memtype_interval.o
CC arch/x86/events/zhaoxin/core.o
AS arch/x86/entry/entry_64.o
AR drivers/pinctrl/intel/built-in.a
CC arch/x86/entry/syscall_64.o
AR lib/kunit/built-in.a
CC arch/x86/entry/common.o
AR drivers/pinctrl/mvebu/built-in.a
CC lib/math/div64.o
AR drivers/pinctrl/nomadik/built-in.a
AS [M] arch/x86/crypto/crct10dif-pcl-asm_64.o
AR drivers/pinctrl/nuvoton/built-in.a
CC arch/x86/kernel/acpi/cstate.o
AR drivers/pinctrl/sprd/built-in.a
CC lib/math/gcd.o
AR drivers/pinctrl/sunplus/built-in.a
CC [M] arch/x86/crypto/crct10dif-pclmul_glue.o
CC mm/kasan/report_generic.o
AR drivers/pinctrl/ti/built-in.a
CC arch/x86/platform/efi/efi_64.o
CC drivers/pinctrl/core.o
CC lib/math/lcm.o
AS arch/x86/platform/efi/efi_stub_64.o
CC arch/x86/kernel/apic/ipi.o
CC lib/math/int_pow.o
CC arch/x86/kernel/fpu/xstate.o
CC kernel/locking/irqflag-debug.o
CC io_uring/splice.o
AS arch/x86/lib/memcpy_64.o
LDS arch/x86/entry/vdso/vdso32/vdso32.lds
CC lib/math/int_sqrt.o
AS arch/x86/entry/vdso/vdso32/note.o
AS arch/x86/lib/memmove_64.o
CC io_uring/sync.o
AS arch/x86/lib/memset_64.o
AS arch/x86/entry/vdso/vdso32/system_call.o
CC arch/x86/lib/misc.o
AS arch/x86/entry/thunk_64.o
CC lib/math/reciprocal_div.o
CC init/version.o
AS arch/x86/entry/vdso/vdso32/sigreturn.o
CC arch/x86/lib/pc-conf-reg.o
CC arch/x86/kernel/cpu/mtrr/mtrr.o
CC arch/x86/entry/vdso/vdso32/vclock_gettime.o
CC arch/x86/kernel/cpu/mce/apei.o
CC lib/math/rational.o
CC arch/x86/kernel/cpu/cacheinfo.o
CC fs/iomap/direct-io.o
CC net/netlink/genetlink.o
CC arch/x86/kernel/kprobes/ftrace.o
CC arch/x86/events/amd/uncore.o
AR arch/x86/net/built-in.a
AS arch/x86/lib/putuser.o
CC crypto/scatterwalk.o
CC crypto/proc.o
CC arch/x86/kernel/apic/vector.o
LD [M] arch/x86/crypto/ghash-clmulni-intel.o
AR init/built-in.a
AS arch/x86/lib/retpoline.o
LD [M] arch/x86/crypto/crc32-pclmul.o
CC mm/filemap.o
LD [M] arch/x86/crypto/crct10dif-pclmul.o
CC fs/proc/base.o
CC crypto/aead.o
AR arch/x86/crypto/built-in.a
CC fs/proc/generic.o
CC fs/notify/notification.o
CC arch/x86/lib/usercopy.o
CC security/keys/permission.o
AR arch/x86/mm/pat/built-in.a
CC arch/x86/mm/init.o
CC sound/core/seq/seq_queue.o
AR drivers/pwm/built-in.a
AR arch/x86/kernel/acpi/built-in.a
CC arch/x86/lib/usercopy_64.o
CC block/bio.o
AS arch/x86/entry/entry_64_compat.o
CC sound/core/memory.o
CC kernel/locking/mutex-debug.o
AR ipc/built-in.a
CC net/core/request_sock.o
CC [M] lib/math/prime_numbers.o
AR arch/x86/platform/geode/built-in.a
AR sound/ppc/built-in.a
CC [M] arch/x86/kvm/../../../virt/kvm/kvm_main.o
AR sound/pci/ac97/built-in.a
CC fs/kernfs/mount.o
AR sound/pci/ali5451/built-in.a
AR sound/pci/asihpi/built-in.a
CC mm/kasan/shadow.o
AR sound/pci/au88x0/built-in.a
AR sound/pci/aw2/built-in.a
AR arch/x86/events/zhaoxin/built-in.a
AR sound/pci/ctxfi/built-in.a
AR sound/pci/ca0106/built-in.a
CC net/sched/sch_api.o
AR sound/arm/built-in.a
AR sound/pci/cs46xx/built-in.a
CC net/sched/sch_blackhole.o
AR sound/pci/cs5535audio/built-in.a
AR sound/pci/lola/built-in.a
AR sound/pci/lx6464es/built-in.a
AR sound/pci/echoaudio/built-in.a
CC mm/mempool.o
AR arch/x86/platform/efi/built-in.a
AR sound/pci/emu10k1/built-in.a
AR arch/x86/platform/iris/built-in.a
CC arch/x86/pci/fixup.o
CC arch/x86/entry/vdso/vdso32/vgetcpu.o
CC arch/x86/pci/acpi.o
CC arch/x86/platform/intel/iosf_mbi.o
AR sound/pci/hda/built-in.a
CC [M] sound/pci/hda/hda_bind.o
AR arch/x86/kernel/cpu/mce/built-in.a
CC mm/oom_kill.o
CC crypto/geniv.o
CC arch/x86/kernel/cpu/scattered.o
CC net/core/skbuff.o
VDSO arch/x86/entry/vdso/vdso64.so.dbg
AR arch/x86/kernel/kprobes/built-in.a
CC arch/x86/events/core.o
VDSO arch/x86/entry/vdso/vdso32.so.dbg
OBJCOPY arch/x86/entry/vdso/vdso64.so
OBJCOPY arch/x86/entry/vdso/vdso32.so
CC [M] arch/x86/kvm/../../../virt/kvm/eventfd.o
CC arch/x86/kernel/cpu/mtrr/if.o
VDSO2C arch/x86/entry/vdso/vdso-image-64.c
VDSO2C arch/x86/entry/vdso/vdso-image-32.c
CC arch/x86/entry/vdso/vdso-image-64.o
CC [M] arch/x86/kvm/../../../virt/kvm/binary_stats.o
CC security/keys/process_keys.o
CC arch/x86/kernel/cpu/mtrr/generic.o
CC arch/x86/entry/vdso/vdso-image-32.o
AR fs/notify/fanotify/built-in.a
CC fs/notify/group.o
CC arch/x86/lib/msr-smp.o
CC crypto/skcipher.o
CC arch/x86/lib/cache-smp.o
CC kernel/locking/lockdep.o
AR lib/math/built-in.a
CC lib/crypto/memneq.o
AR arch/x86/kernel/fpu/built-in.a
CC arch/x86/lib/msr.o
AR arch/x86/events/amd/built-in.a
AR arch/x86/entry/vdso/built-in.a
CC security/min_addr.o
CC arch/x86/entry/syscall_32.o
CC mm/kasan/quarantine.o
CC drivers/pinctrl/pinmux.o
CC drivers/pinctrl/pinctrl-utils.o
CC sound/core/seq/seq_fifo.o
CC fs/iomap/fiemap.o
CC lib/crypto/utils.o
CC fs/kernfs/inode.o
CC fs/iomap/seek.o
CC arch/x86/kernel/cpu/topology.o
CC net/sched/sch_fifo.o
CC arch/x86/mm/init_64.o
CC security/inode.o
CC net/core/datagram.o
CC [M] sound/pci/hda/hda_codec.o
AR arch/x86/platform/intel/built-in.a
AR arch/x86/platform/intel-mid/built-in.a
AR sound/pci/ice1712/built-in.a
CC drivers/pinctrl/pinconf.o
AR arch/x86/platform/intel-quark/built-in.a
AR arch/x86/platform/olpc/built-in.a
AR arch/x86/platform/scx200/built-in.a
CC drivers/pinctrl/pinconf-generic.o
CC arch/x86/pci/legacy.o
AR arch/x86/platform/ts5500/built-in.a
AR arch/x86/platform/uv/built-in.a
AR arch/x86/platform/built-in.a
CC drivers/gpio/gpiolib-devres.o
CC fs/proc/array.o
CC arch/x86/pci/irq.o
AR sound/pci/korg1212/built-in.a
AR sound/pci/mixart/built-in.a
AR sound/pci/nm256/built-in.a
CC lib/crypto/chacha.o
LDS arch/x86/kernel/vmlinux.lds
AS arch/x86/lib/msr-reg.o
CC fs/notify/mark.o
CC arch/x86/pci/common.o
CC fs/iomap/swapfile.o
CC arch/x86/pci/early.o
CC kernel/locking/lockdep_proc.o
CC kernel/locking/spinlock.o
CC lib/crypto/aes.o
CC arch/x86/kernel/cpu/mtrr/cleanup.o
CC arch/x86/kernel/apic/hw_nmi.o
CC net/netlink/policy.o
AR arch/x86/entry/built-in.a
CC sound/core/seq/seq_prioq.o
CC crypto/seqiv.o
CC security/device_cgroup.o
CC net/ethtool/ioctl.o
CC security/keys/request_key.o
CC io_uring/advise.o
AR mm/kasan/built-in.a
CC arch/x86/lib/msr-reg-export.o
AS arch/x86/kernel/head_64.o
CC fs/kernfs/dir.o
CC security/keys/request_key_auth.o
CC arch/x86/kernel/head64.o
CC lib/zlib_inflate/inffast.o
CC lib/zlib_deflate/deflate.o
AS arch/x86/lib/hweight.o
AR drivers/pinctrl/built-in.a
CC arch/x86/kernel/ebda.o
CC arch/x86/lib/iomem.o
CC drivers/gpio/gpiolib-legacy.o
CC arch/x86/kernel/platform-quirks.o
CC drivers/gpio/gpiolib-cdev.o
CC block/elevator.o
CC lib/zlib_inflate/inflate.o
CC arch/x86/kernel/apic/io_apic.o
CC security/keys/user_defined.o
CC drivers/gpio/gpiolib-sysfs.o
CC [M] net/netfilter/ipvs/ip_vs_conn.o
CC arch/x86/pci/bus_numa.o
CC arch/x86/events/intel/bts.o
AR fs/iomap/built-in.a
CC [M] arch/x86/kvm/../../../virt/kvm/vfio.o
CC net/netfilter/core.o
CC lib/crypto/gf128mul.o
CC drivers/gpio/gpiolib-acpi.o
CC crypto/echainiv.o
CC kernel/locking/osq_lock.o
AS arch/x86/lib/iomap_copy_64.o
CC sound/core/seq/seq_timer.o
CC arch/x86/lib/inat.o
CC lib/lzo/lzo1x_compress.o
CC mm/fadvise.o
CC net/netlink/diag.o
CC mm/maccess.o
CC fs/notify/fdinfo.o
CC mm/page-writeback.o
AR arch/x86/lib/built-in.a
CC security/keys/compat.o
AR arch/x86/lib/lib.a
CC lib/lz4/lz4_compress.o
CC io_uring/filetable.o
CC lib/lz4/lz4hc_compress.o
CC fs/proc/fd.o
AR arch/x86/kernel/cpu/mtrr/built-in.a
CC mm/folio-compat.o
CC arch/x86/kernel/cpu/common.o
AR net/sched/built-in.a
CC lib/lz4/lz4_decompress.o
CC fs/sysfs/file.o
CC arch/x86/mm/fault.o
CC fs/configfs/inode.o
CC arch/x86/pci/amd_bus.o
CC lib/crypto/blake2s.o
CC arch/x86/kernel/process_64.o
CC sound/core/control.o
CC lib/zlib_inflate/infutil.o
CC lib/zlib_inflate/inftrees.o
CC lib/zlib_deflate/deftree.o
CC fs/configfs/file.o
CC io_uring/openclose.o
CC arch/x86/mm/ioremap.o
CC lib/lzo/lzo1x_decompress_safe.o
CC crypto/ahash.o
CC arch/x86/kernel/cpu/rdrand.o
CC fs/kernfs/file.o
CC lib/crypto/blake2s-generic.o
CC arch/x86/events/intel/ds.o
CC lib/crypto/blake2s-selftest.o
AR fs/notify/built-in.a
CC lib/crypto/des.o
CC block/blk-core.o
CC sound/core/seq/seq_system.o
CC lib/zlib_inflate/inflate_syms.o
CC fs/devpts/inode.o
CC security/keys/proc.o
CC arch/x86/kernel/cpu/match.o
CC lib/crypto/sha1.o
CC mm/readahead.o
CC fs/proc/proc_tty.o
CC lib/zlib_deflate/deflate_syms.o
CC block/blk-sysfs.o
CC fs/sysfs/dir.o
CC drivers/gpio/gpiolib-swnode.o
AR arch/x86/pci/built-in.a
CC io_uring/uring_cmd.o
CC io_uring/epoll.o
AR net/netlink/built-in.a
CC arch/x86/events/probe.o
AR lib/lzo/built-in.a
CC block/blk-flush.o
AR lib/zlib_inflate/built-in.a
CC kernel/locking/qspinlock.o
CC [M] sound/pci/hda/hda_jack.o
CC sound/core/seq/seq_ports.o
CC fs/configfs/dir.o
CC security/keys/sysctl.o
CC sound/core/seq/seq_info.o
CC mm/swap.o
CC net/netfilter/nf_log.o
CC lib/crypto/sha256.o
CC kernel/locking/rtmutex_api.o
CC arch/x86/events/utils.o
AR lib/zlib_deflate/built-in.a
CC [M] sound/pci/hda/hda_auto_parser.o
CC arch/x86/events/rapl.o
CC fs/ext4/balloc.o
CC fs/jbd2/transaction.o
CC fs/ext4/bitmap.o
CC arch/x86/kernel/apic/msi.o
CC mm/truncate.o
CC mm/vmscan.o
CC crypto/shash.o
AR drivers/gpio/built-in.a
CC fs/sysfs/symlink.o
CC drivers/pci/msi/pcidev_msi.o
CC drivers/pci/msi/api.o
CC arch/x86/events/intel/knc.o
AR fs/devpts/built-in.a
CC drivers/pci/msi/msi.o
CC arch/x86/mm/extable.o
CC drivers/pci/msi/irqdomain.o
CC fs/proc/cmdline.o
CC drivers/pci/pcie/portdrv.o
CC fs/kernfs/symlink.o
CC [M] net/netfilter/ipvs/ip_vs_core.o
CC arch/x86/kernel/cpu/bugs.o
CC drivers/pci/pcie/rcec.o
AR security/keys/built-in.a
AR security/built-in.a
CC kernel/locking/spinlock_debug.o
CC fs/proc/consoles.o
CC fs/proc/cpuinfo.o
CC mm/shmem.o
AR lib/lz4/built-in.a
CC drivers/pci/hotplug/pci_hotplug_core.o
CC [M] lib/crypto/arc4.o
AR drivers/pci/controller/dwc/built-in.a
CC net/ethtool/common.o
AR drivers/pci/controller/mobiveil/built-in.a
CC drivers/pci/controller/vmd.o
CC lib/zstd/zstd_compress_module.o
AR sound/core/seq/built-in.a
CC block/blk-settings.o
CC block/blk-ioc.o
CC drivers/video/console/dummycon.o
CC sound/core/misc.o
AR kernel/sched/built-in.a
CC io_uring/statx.o
CC drivers/video/console/vgacon.o
CC kernel/power/qos.o
CC fs/sysfs/mount.o
CC arch/x86/events/msr.o
CC drivers/pci/hotplug/acpi_pcihp.o
CC lib/xz/xz_dec_syms.o
CC lib/raid6/algos.o
CC kernel/locking/qrwlock.o
CC arch/x86/kernel/apic/x2apic_phys.o
AR fs/kernfs/built-in.a
CC arch/x86/kernel/signal.o
AR lib/crypto/built-in.a
LD [M] lib/crypto/libarc4.o
CC [M] net/netfilter/ipvs/ip_vs_ctl.o
CC lib/fonts/fonts.o
CC arch/x86/kernel/apic/x2apic_cluster.o
CC lib/raid6/recov.o
AR sound/sh/built-in.a
CC arch/x86/kernel/signal_64.o
CC fs/proc/devices.o
CC arch/x86/kernel/cpu/aperfmperf.o
CC arch/x86/mm/mmap.o
CC arch/x86/events/intel/lbr.o
CC fs/configfs/symlink.o
CC lib/zstd/compress/fse_compress.o
CC arch/x86/events/intel/p4.o
CC drivers/pci/pcie/aspm.o
CC net/netfilter/nf_queue.o
CC [M] sound/pci/hda/hda_sysfs.o
CC lib/fonts/font_8x8.o
CC lib/fonts/font_8x16.o
CC crypto/akcipher.o
CC drivers/pci/hotplug/pciehp_core.o
AR drivers/pci/switch/built-in.a
CC net/core/stream.o
CC lib/xz/xz_dec_stream.o
AR drivers/pci/msi/built-in.a
CC crypto/kpp.o
CC kernel/power/main.o
CC arch/x86/events/intel/p6.o
CC [M] sound/pci/hda/hda_controller.o
CC sound/core/device.o
AR kernel/locking/built-in.a
CC net/core/scm.o
CC io_uring/net.o
CC net/ethtool/netlink.o
CC fs/sysfs/group.o
CC lib/argv_split.o
CC lib/zstd/compress/hist.o
AR lib/fonts/built-in.a
HOSTCC lib/raid6/mktables
CC lib/bug.o
CC net/ethtool/bitset.o
AR sound/synth/emux/built-in.a
CC kernel/power/console.o
AR sound/synth/built-in.a
CC net/core/gen_stats.o
CC lib/zstd/compress/huf_compress.o
CC fs/proc/interrupts.o
AR drivers/pci/controller/built-in.a
CC kernel/power/process.o
CC drivers/pci/hotplug/pciehp_ctrl.o
CC drivers/pci/access.o
CC fs/ext4/block_validity.o
CC drivers/pci/bus.o
CC arch/x86/kernel/apic/apic_flat_64.o
CC [M] arch/x86/kvm/../../../virt/kvm/coalesced_mmio.o
CC arch/x86/mm/pgtable.o
CC fs/jbd2/commit.o
UNROLL lib/raid6/int1.c
CC drivers/pci/probe.o
CC fs/configfs/mount.o
UNROLL lib/raid6/int2.c
UNROLL lib/raid6/int4.c
UNROLL lib/raid6/int8.c
UNROLL lib/raid6/int16.c
CC block/blk-map.o
CC fs/jbd2/recovery.o
UNROLL lib/raid6/int32.c
CC lib/raid6/recov_ssse3.o
CC lib/zstd/compress/zstd_compress.o
AR drivers/video/console/built-in.a
CC lib/raid6/recov_avx2.o
CC drivers/video/logo/logo.o
CC arch/x86/kernel/cpu/cpuid-deps.o
CC lib/xz/xz_dec_lzma2.o
HOSTCC drivers/video/logo/pnmtologo
CC lib/buildid.o
CC lib/zstd/compress/zstd_compress_literals.o
CC sound/core/info.o
CC drivers/pci/hotplug/pciehp_pci.o
CC crypto/acompress.o
CC drivers/pci/host-bridge.o
CC lib/cmdline.o
CC drivers/idle/intel_idle.o
CC mm/util.o
CC fs/proc/loadavg.o
CC mm/mmzone.o
AR fs/sysfs/built-in.a
CC crypto/scompress.o
LOGO drivers/video/logo/logo_linux_clut224.c
CC drivers/video/logo/logo_linux_clut224.o
CC fs/ramfs/inode.o
CC fs/hugetlbfs/inode.o
CC arch/x86/kernel/apic/probe_64.o
CC crypto/algboss.o
AR drivers/video/logo/built-in.a
CC arch/x86/kernel/cpu/umwait.o
CC drivers/video/backlight/backlight.o
CC drivers/pci/pcie/aer.o
CC net/core/gen_estimator.o
CC arch/x86/events/intel/pt.o
CC [M] sound/pci/hda/hda_proc.o
CC fs/configfs/item.o
CC fs/fat/cache.o
CC fs/fat/dir.o
CC fs/proc/meminfo.o
CC fs/fat/fatent.o
CC lib/raid6/mmx.o
CC [M] arch/x86/kvm/../../../virt/kvm/async_pf.o
CC lib/raid6/sse1.o
AR arch/x86/kernel/apic/built-in.a
CC fs/ext4/dir.o
CC fs/fat/file.o
CC fs/proc/stat.o
CC fs/fat/inode.o
CC lib/raid6/sse2.o
CC net/netfilter/nf_sockopt.o
CC [M] net/netfilter/ipvs/ip_vs_sched.o
CC fs/fat/misc.o
CC kernel/power/suspend.o
CC lib/xz/xz_dec_bcj.o
CC drivers/pci/hotplug/pciehp_hpc.o
CC drivers/pci/hotplug/acpiphp_core.o
CC mm/vmstat.o
CC kernel/power/hibernate.o
CC io_uring/msg_ring.o
CC arch/x86/mm/physaddr.o
CC block/blk-merge.o
CC net/ethtool/strset.o
CC net/core/net_namespace.o
CC lib/cpumask.o
CC lib/ctype.o
CC sound/core/isadma.o
AR fs/configfs/built-in.a
CC [M] arch/x86/kvm/../../../virt/kvm/irqchip.o
CC block/blk-timeout.o
CC fs/ramfs/file-mmu.o
CC arch/x86/kernel/cpu/proc.o
AR sound/usb/misc/built-in.a
AR sound/usb/usx2y/built-in.a
AR sound/usb/caiaq/built-in.a
AR sound/usb/6fire/built-in.a
AR sound/usb/hiface/built-in.a
AR sound/usb/bcd2000/built-in.a
AR sound/usb/built-in.a
AR sound/firewire/built-in.a
AR sound/sparc/built-in.a
AR drivers/char/ipmi/built-in.a
CC lib/zstd/compress/zstd_compress_sequences.o
CC net/core/secure_seq.o
CC drivers/acpi/acpica/dsargs.o
AR lib/xz/built-in.a
CC crypto/testmgr.o
CC drivers/acpi/apei/apei-base.o
CC drivers/acpi/apei/hest.o
CC drivers/acpi/apei/erst.o
CC fs/proc/uptime.o
AR drivers/video/backlight/built-in.a
CC drivers/video/fbdev/core/fb_notify.o
AR drivers/idle/built-in.a
CC fs/jbd2/checkpoint.o
AR drivers/video/fbdev/omap/built-in.a
CC fs/jbd2/revoke.o
CC lib/raid6/avx2.o
CC arch/x86/mm/tlb.o
CC sound/core/vmaster.o
CC net/core/flow_dissector.o
AR drivers/video/fbdev/omap2/omapfb/dss/built-in.a
AR drivers/video/fbdev/omap2/omapfb/displays/built-in.a
CC lib/raid6/avx512.o
AR drivers/video/fbdev/omap2/omapfb/built-in.a
AR drivers/acpi/pmic/built-in.a
CC [M] drivers/video/fbdev/uvesafb.o
AR drivers/video/fbdev/omap2/built-in.a
CC fs/proc/util.o
CC io_uring/timeout.o
CC [M] sound/pci/hda/hda_hwdep.o
CC block/blk-lib.o
CC [M] net/netfilter/ipvs/ip_vs_xmit.o
AR sound/spi/built-in.a
CC sound/core/ctljack.o
CC io_uring/sqpoll.o
AR fs/ramfs/built-in.a
CC mm/backing-dev.o
CC lib/dec_and_lock.o
CC lib/decompress.o
CC [M] net/netfilter/ipvs/ip_vs_app.o
CC fs/ext4/ext4_jbd2.o
CC drivers/pci/pcie/err.o
MKCAP arch/x86/kernel/cpu/capflags.c
CC [M] net/netfilter/ipvs/ip_vs_sync.o
CC drivers/acpi/acpica/dscontrol.o
CC net/netfilter/utils.o
AR fs/hugetlbfs/built-in.a
CC lib/decompress_bunzip2.o
CC net/ethtool/linkinfo.o
CC arch/x86/events/intel/uncore.o
CC arch/x86/events/intel/uncore_nhmex.o
CC arch/x86/events/intel/uncore_snb.o
CC drivers/pci/hotplug/acpiphp_glue.o
CC arch/x86/events/intel/uncore_snbep.o
CC drivers/pci/remove.o
CC [M] arch/x86/kvm/../../../virt/kvm/dirty_ring.o
CC fs/proc/version.o
CC drivers/pci/pci.o
CC drivers/pci/pci-driver.o
CC drivers/video/aperture.o
CC [M] drivers/video/fbdev/core/fbmem.o
CC sound/core/jack.o
CC drivers/video/cmdline.o
CC [M] drivers/video/fbdev/simplefb.o
CC kernel/power/snapshot.o
CC fs/fat/nfs.o
CC fs/ext4/extents.o
CC lib/raid6/recov_avx512.o
CC [M] sound/pci/hda/hda_generic.o
CC drivers/acpi/acpica/dsdebug.o
CC arch/x86/events/intel/uncore_discovery.o
CC fs/ext4/extents_status.o
CC net/ethtool/linkmodes.o
CC drivers/acpi/apei/bert.o
CC net/ethtool/rss.o
CC kernel/power/swap.o
CC drivers/pci/pcie/aer_inject.o
CC fs/jbd2/journal.o
CC block/blk-mq.o
CC fs/proc/softirqs.o
CC block/blk-mq-tag.o
CC arch/x86/mm/cpu_entry_area.o
CC arch/x86/kernel/cpu/powerflags.o
CC arch/x86/kernel/cpu/feat_ctl.o
CC io_uring/fdinfo.o
CC drivers/pci/search.o
CC drivers/acpi/acpica/dsfield.o
CC drivers/video/nomodeset.o
CC fs/ext4/file.o
CC fs/nfs/client.o
CC sound/core/timer.o
CC fs/nfs/dir.o
TABLE lib/raid6/tables.c
CC lib/raid6/int1.o
CC fs/fat/namei_vfat.o
CC arch/x86/events/intel/cstate.o
CC drivers/video/hdmi.o
CC [M] arch/x86/kvm/../../../virt/kvm/pfncache.o
CC [M] arch/x86/kvm/x86.o
CC drivers/acpi/apei/ghes.o
CC fs/proc/namespaces.o
CC [M] net/netfilter/nfnetlink.o
CC fs/proc/self.o
CC sound/core/hrtimer.o
CC [M] net/netfilter/nf_conntrack_core.o
CC kernel/printk/printk.o
AR drivers/pci/hotplug/built-in.a
CC fs/ext4/fsmap.o
CC kernel/printk/printk_safe.o
CC arch/x86/mm/maccess.o
CC lib/zstd/compress/zstd_compress_superblock.o
CC mm/mm_init.o
CC mm/percpu.o
CC fs/ext4/fsync.o
CC drivers/acpi/acpica/dsinit.o
CC drivers/pci/pcie/pme.o
CC kernel/power/user.o
CC fs/nfs/file.o
CC net/ethtool/linkstate.o
CC fs/nfs/getroot.o
CC arch/x86/mm/pgprot.o
CC lib/zstd/compress/zstd_double_fast.o
CC lib/zstd/compress/zstd_fast.o
CC lib/zstd/compress/zstd_lazy.o
CC lib/raid6/int2.o
CC net/core/sysctl_net_core.o
CC [M] arch/x86/kvm/emulate.o
CC arch/x86/kernel/traps.o
CC arch/x86/kernel/idt.o
CC [M] net/netfilter/ipvs/ip_vs_est.o
CC [M] net/netfilter/ipvs/ip_vs_proto.o
CC [M] drivers/video/fbdev/core/fbmon.o
CC drivers/acpi/acpica/dsmethod.o
CC [M] drivers/video/fbdev/core/fbcmap.o
CC net/core/dev.o
CC crypto/cmac.o
CC sound/core/seq_device.o
CC fs/proc/thread_self.o
CC arch/x86/mm/hugetlbpage.o
CC fs/nfs/inode.o
CC io_uring/tctx.o
CC [M] arch/x86/kvm/i8259.o
CC io_uring/poll.o
CC mm/slab_common.o
CC drivers/pci/pcie/dpc.o
CC fs/fat/namei_msdos.o
CC kernel/power/poweroff.o
CC [M] drivers/video/fbdev/core/fbsysfs.o
CC lib/raid6/int4.o
AR arch/x86/events/intel/built-in.a
AR drivers/acpi/apei/built-in.a
CC [M] net/netfilter/ipvs/ip_vs_pe.o
AR arch/x86/events/built-in.a
CC drivers/acpi/acpica/dsmthdat.o
CC drivers/acpi/dptf/int340x_thermal.o
CC crypto/hmac.o
CC crypto/vmac.o
CC fs/proc/proc_sysctl.o
AR kernel/power/built-in.a
CC fs/nfs/super.o
CC fs/nfs/io.o
CC net/ethtool/debug.o
CC kernel/irq/irqdesc.o
CC io_uring/cancel.o
CC kernel/rcu/update.o
CC [M] sound/core/control_led.o
AR kernel/livepatch/built-in.a
CC [M] net/netfilter/nf_conntrack_standalone.o
CC mm/compaction.o
CC arch/x86/mm/kasan_init_64.o
CC io_uring/kbuf.o
CC arch/x86/kernel/cpu/intel.o
CC io_uring/rsrc.o
CC drivers/acpi/acpica/dsobject.o
AR drivers/acpi/dptf/built-in.a
CC kernel/dma/mapping.o
CC kernel/entry/common.o
AR drivers/pci/pcie/built-in.a
CC kernel/module/main.o
CC kernel/dma/direct.o
CC lib/raid6/int8.o
CC kernel/module/strict_rwx.o
AR fs/fat/built-in.a
CC lib/decompress_inflate.o
CC kernel/entry/syscall_user_dispatch.o
CC kernel/irq/handle.o
CC drivers/pci/pci-sysfs.o
CC [M] drivers/video/fbdev/core/modedb.o
CC fs/nfs/direct.o
CC fs/nfs/pagelist.o
CC fs/nfs/read.o
CC kernel/printk/printk_ringbuffer.o
CC crypto/xcbc.o
CC crypto/crypto_null.o
AR fs/jbd2/built-in.a
CC [M] net/netfilter/ipvs/ip_vs_proto_tcp.o
CC [M] net/netfilter/ipvs/ip_vs_proto_udp.o
CC [M] net/netfilter/ipvs/ip_vs_nfct.o
CC arch/x86/kernel/cpu/intel_pconfig.o
CC drivers/acpi/acpica/dsopcode.o
CC [M] sound/core/hwdep.o
CC mm/interval_tree.o
CC arch/x86/mm/pkeys.o
CC net/ethtool/wol.o
CC fs/exportfs/expfs.o
CC fs/ext4/hash.o
CC drivers/acpi/tables.o
CC io_uring/rw.o
CC kernel/irq/manage.o
CC mm/list_lru.o
CC lib/raid6/int16.o
CC fs/lockd/clntlock.o
CC fs/nls/nls_base.o
AR fs/unicode/built-in.a
CC io_uring/opdef.o
CC fs/ntfs/aops.o
CC kernel/dma/ops_helpers.o
CC arch/x86/kernel/cpu/tsx.o
CC crypto/md5.o
CC kernel/entry/kvm.o
CC kernel/printk/sysctl.o
CC drivers/acpi/acpica/dspkginit.o
CC drivers/acpi/acpica/dsutils.o
CC fs/nfs/symlink.o
CC fs/autofs/init.o
CC kernel/rcu/sync.o
CC fs/lockd/clntproc.o
CC arch/x86/mm/pti.o
CC fs/proc/proc_net.o
AR fs/exportfs/built-in.a
CC [M] sound/core/pcm.o
CC kernel/module/tree_lookup.o
CC [M] drivers/video/fbdev/core/fbcvt.o
CC [M] sound/pci/hda/patch_realtek.o
AR kernel/printk/built-in.a
CC drivers/pnp/pnpacpi/core.o
CC kernel/rcu/srcutree.o
CC fs/nls/nls_cp437.o
CC mm/workingset.o
CC drivers/pnp/core.o
CC drivers/pci/rom.o
CC lib/raid6/int32.o
CC net/ethtool/features.o
CC arch/x86/kernel/cpu/intel_epb.o
CC fs/ext4/ialloc.o
CC block/blk-stat.o
CC block/blk-mq-sysfs.o
CC block/blk-mq-cpumap.o
CC crypto/sha1_generic.o
CC drivers/acpi/acpica/dswexec.o
CC kernel/dma/dummy.o
CC fs/nfs/unlink.o
CC drivers/acpi/blacklist.o
CC fs/autofs/inode.o
CC drivers/pci/setup-res.o
CC io_uring/notif.o
CC [M] net/netfilter/ipvs/ip_vs_rr.o
CC fs/nls/nls_ascii.o
CC mm/debug.o
CC kernel/module/debug_kmemleak.o
AR kernel/entry/built-in.a
CC fs/proc/kcore.o
CC drivers/pnp/pnpacpi/rsparser.o
CC arch/x86/kernel/cpu/amd.o
AR arch/x86/mm/built-in.a
CC fs/autofs/root.o
CC mm/gup.o
CC fs/autofs/symlink.o
CC fs/ntfs/attrib.o
CC lib/raid6/tables.o
CC fs/autofs/waitq.o
CC kernel/dma/contiguous.o
CC fs/autofs/expire.o
CC crypto/sha256_generic.o
CC fs/proc/kmsg.o
CC drivers/acpi/acpica/dswload.o
CC [M] drivers/video/fbdev/core/fb_cmdline.o
CC drivers/acpi/osi.o
CC io_uring/io-wq.o
CC [M] sound/core/pcm_native.o
CC kernel/irq/spurious.o
CC kernel/irq/resend.o
CC drivers/pnp/card.o
CC fs/nls/nls_iso8859-1.o
CC drivers/pnp/driver.o
CC fs/ntfs/collate.o
CC kernel/irq/chip.o
CC arch/x86/kernel/irq.o
CC kernel/time/time.o
CC kernel/futex/core.o
CC fs/nfs/write.o
CC block/blk-mq-sched.o
CC kernel/module/kallsyms.o
CC drivers/pci/irq.o
CC net/ethtool/privflags.o
CC fs/lockd/clntxdr.o
CC kernel/time/timer.o
CC block/ioctl.o
CC drivers/acpi/acpica/dswload2.o
CC fs/nfs/namespace.o
CC kernel/rcu/tree.o
CC drivers/pnp/resource.o
CC crypto/sha512_generic.o
CC fs/nls/nls_utf8.o
CC kernel/dma/swiotlb.o
CC arch/x86/kernel/cpu/hygon.o
CC drivers/acpi/osl.o
CC [M] sound/core/pcm_lib.o
AR lib/raid6/built-in.a
CC lib/decompress_unlz4.o
CC kernel/rcu/rcu_segcblist.o
AR sound/pci/oxygen/built-in.a
CC block/genhd.o
CC drivers/acpi/utils.o
CC [M] drivers/video/fbdev/core/fb_defio.o
CC [M] arch/x86/kvm/irq.o
CC fs/autofs/dev-ioctl.o
CC drivers/pnp/manager.o
AR sound/pci/pcxhr/built-in.a
CC drivers/pnp/support.o
CC crypto/blake2b_generic.o
CC fs/proc/page.o
CC drivers/pnp/interface.o
AR drivers/pnp/pnpacpi/built-in.a
AR sound/pci/riptide/built-in.a
LD [M] net/netfilter/ipvs/ip_vs.o
CC kernel/dma/remap.o
CC drivers/acpi/acpica/dswscope.o
CC net/ethtool/rings.o
CC [M] net/netfilter/nf_conntrack_expect.o
CC drivers/pci/vpd.o
AR fs/nls/built-in.a
CC fs/ext4/indirect.o
CC fs/ntfs/compress.o
CC kernel/time/hrtimer.o
CC mm/mmap_lock.o
CC arch/x86/kernel/cpu/centaur.o
CC kernel/module/procfs.o
CC lib/decompress_unlzma.o
CC drivers/acpi/acpica/dswstate.o
CC drivers/pnp/quirks.o
CC kernel/futex/syscalls.o
CC kernel/irq/dummychip.o
CC kernel/futex/pi.o
CC fs/ext4/inline.o
CC fs/lockd/host.o
CC arch/x86/kernel/cpu/zhaoxin.o
CC net/ethtool/channels.o
CC drivers/pnp/system.o
CC kernel/module/sysfs.o
CC kernel/irq/devres.o
AR drivers/amba/built-in.a
AR fs/autofs/built-in.a
AR drivers/clk/actions/built-in.a
CC drivers/dma/dw/core.o
AR drivers/clk/analogbits/built-in.a
CC fs/debugfs/inode.o
AR drivers/clk/bcm/built-in.a
AR drivers/clk/imgtec/built-in.a
CC fs/debugfs/file.o
AR drivers/clk/imx/built-in.a
AR drivers/clk/ingenic/built-in.a
AR drivers/clk/mediatek/built-in.a
AR drivers/clk/microchip/built-in.a
AR drivers/clk/mstar/built-in.a
CC drivers/acpi/reboot.o
CC block/ioprio.o
AR drivers/clk/mvebu/built-in.a
AR drivers/clk/ralink/built-in.a
AR drivers/clk/renesas/built-in.a
AR drivers/clk/socfpga/built-in.a
CC [M] drivers/video/fbdev/core/fbcon.o
CC drivers/acpi/nvs.o
AR drivers/clk/sprd/built-in.a
AR drivers/clk/sunxi-ng/built-in.a
AR io_uring/built-in.a
CC fs/nfs/mount_clnt.o
AR drivers/clk/ti/built-in.a
CC crypto/ecb.o
AR drivers/clk/versatile/built-in.a
CC drivers/clk/x86/clk-lpss-atom.o
AR fs/proc/built-in.a
AR drivers/soc/apple/built-in.a
CC drivers/pci/setup-bus.o
AR drivers/soc/aspeed/built-in.a
CC net/core/dev_addr_lists.o
CC drivers/virtio/virtio.o
CC drivers/acpi/wakeup.o
AR drivers/soc/bcm/bcm63xx/built-in.a
AR drivers/soc/bcm/built-in.a
AR drivers/soc/fsl/built-in.a
CC drivers/acpi/acpica/evevent.o
CC arch/x86/kernel/cpu/perfctr-watchdog.o
AR drivers/soc/fujitsu/built-in.a
AR kernel/dma/built-in.a
AR drivers/soc/imx/built-in.a
CC [M] drivers/video/fbdev/core/bitblit.o
AR drivers/soc/ixp4xx/built-in.a
CC drivers/tty/vt/vt_ioctl.o
AR drivers/soc/loongson/built-in.a
AR drivers/soc/mediatek/built-in.a
AR drivers/soc/microchip/built-in.a
CC drivers/char/hw_random/core.o
CC lib/decompress_unlzo.o
AR drivers/soc/nuvoton/built-in.a
AR drivers/soc/pxa/built-in.a
AR drivers/soc/amlogic/built-in.a
CC [M] sound/pci/hda/patch_analog.o
CC fs/nfs/nfstrace.o
AR drivers/soc/qcom/built-in.a
AR drivers/soc/renesas/built-in.a
AR drivers/soc/rockchip/built-in.a
AR drivers/soc/sifive/built-in.a
AR drivers/soc/sunxi/built-in.a
AR drivers/soc/ti/built-in.a
AR drivers/soc/xilinx/built-in.a
AR drivers/soc/built-in.a
CC kernel/cgroup/cgroup.o
CC lib/decompress_unxz.o
CC kernel/irq/autoprobe.o
CC lib/decompress_unzstd.o
CC kernel/cgroup/rstat.o
CC mm/highmem.o
AR drivers/pnp/built-in.a
CC drivers/acpi/acpica/evgpe.o
CC drivers/tty/hvc/hvc_console.o
AR kernel/module/built-in.a
CC mm/memory.o
CC drivers/clk/x86/clk-pmc-atom.o
CC crypto/cbc.o
CC fs/ntfs/debug.o
CC kernel/futex/requeue.o
CC drivers/virtio/virtio_ring.o
CC lib/dump_stack.o
CC drivers/acpi/sleep.o
CC drivers/tty/serial/8250/8250_core.o
CC drivers/tty/serial/8250/8250_pnp.o
CC net/ethtool/coalesce.o
CC drivers/tty/serial/8250/8250_port.o
CC drivers/acpi/device_sysfs.o
CC lib/earlycpio.o
CC [M] net/netfilter/nf_conntrack_helper.o
CC arch/x86/kernel/cpu/vmware.o
CC block/badblocks.o
CC drivers/acpi/acpica/evgpeblk.o
CC kernel/time/timekeeping.o
CC [M] sound/pci/hda/patch_hdmi.o
CC [M] net/netfilter/nf_conntrack_proto.o
CC lib/extable.o
CC [M] net/netfilter/nf_conntrack_proto_generic.o
AR fs/debugfs/built-in.a
CC [M] sound/pci/hda/hda_eld.o
CC kernel/irq/irqdomain.o
CC drivers/tty/serial/serial_core.o
CC fs/lockd/svc.o
CC mm/mincore.o
CC drivers/char/hw_random/intel-rng.o
CC mm/mlock.o
CC crypto/pcbc.o
CC fs/ntfs/dir.o
CC drivers/virtio/virtio_anchor.o
AR drivers/clk/x86/built-in.a
AR drivers/clk/xilinx/built-in.a
CC kernel/futex/waitwake.o
CC drivers/clk/clk-devres.o
CC kernel/trace/trace_clock.o
CC drivers/dma/dw/dw.o
CC drivers/clk/clk-bulk.o
CC fs/tracefs/inode.o
CC lib/flex_proportions.o
CC kernel/bpf/core.o
CC drivers/tty/vt/vc_screen.o
CC lib/idr.o
CC fs/ntfs/file.o
CC drivers/acpi/acpica/evgpeinit.o
CC arch/x86/kernel/cpu/hypervisor.o
CC kernel/events/core.o
CC [M] sound/core/pcm_misc.o
AR drivers/tty/hvc/built-in.a
CC [M] drivers/video/fbdev/core/softcursor.o
CC kernel/events/ring_buffer.o
CC block/blk-rq-qos.o
CC kernel/trace/ftrace.o
CC crypto/cts.o
CC kernel/trace/ring_buffer.o
CC fs/ext4/inode.o
CC kernel/irq/proc.o
AR drivers/char/hw_random/built-in.a
CC arch/x86/kernel/cpu/mshyperv.o
CC fs/lockd/svclock.o
CC drivers/char/agp/backend.o
AR kernel/futex/built-in.a
CC fs/lockd/svcshare.o
CC drivers/char/tpm/tpm-chip.o
CC drivers/clk/clkdev.o
CC drivers/dma/dw/idma32.o
CC drivers/char/tpm/tpm-dev-common.o
CC drivers/pci/vc.o
CC drivers/dma/dw/acpi.o
CC net/ethtool/pause.o
CC drivers/acpi/acpica/evgpeutil.o
CC drivers/acpi/device_pm.o
CC kernel/fork.o
CC drivers/pci/mmap.o
CC drivers/char/tpm/tpm-dev.o
AR fs/tracefs/built-in.a
CC fs/nfs/export.o
CC kernel/irq/migration.o
CC [M] sound/core/pcm_memory.o
CC kernel/irq/cpuhotplug.o
CC drivers/tty/vt/selection.o
CC fs/ext4/ioctl.o
CC [M] drivers/video/fbdev/core/tileblit.o
CC drivers/virtio/virtio_pci_modern_dev.o
CC [M] drivers/video/fbdev/core/cfbfillrect.o
CC fs/ntfs/index.o
CC block/disk-events.o
CC [M] net/netfilter/nf_conntrack_proto_tcp.o
CC drivers/acpi/acpica/evglock.o
CC crypto/lrw.o
CC drivers/clk/clk.o
CC kernel/time/ntp.o
CC kernel/irq/pm.o
CC drivers/dma/dw/pci.o
CC fs/ntfs/inode.o
CC drivers/char/agp/generic.o
CC arch/x86/kernel/cpu/capflags.o
CC [M] sound/core/memalloc.o
CC drivers/virtio/virtio_pci_legacy_dev.o
AR drivers/tty/ipwireless/built-in.a
CC drivers/char/tpm/tpm-interface.o
CC drivers/pci/setup-irq.o
AR arch/x86/kernel/cpu/built-in.a
CC kernel/trace/trace.o
CC arch/x86/kernel/irq_64.o
CC mm/mmap.o
CC [M] net/netfilter/nf_conntrack_proto_udp.o
CC drivers/clk/clk-divider.o
CC [M] drivers/video/fbdev/core/cfbcopyarea.o
CC drivers/tty/serial/8250/8250_dma.o
CC net/core/dst.o
CC drivers/clk/clk-fixed-factor.o
CC drivers/acpi/acpica/evhandler.o
CC net/ethtool/eee.o
CC lib/irq_regs.o
CC drivers/tty/vt/keyboard.o
CC lib/is_single_threaded.o
CC net/core/netevent.o
CC fs/ntfs/mft.o
CC drivers/virtio/virtio_pci_modern.o
CC kernel/exec_domain.o
CC fs/lockd/svcproc.o
CC crypto/xts.o
CC block/blk-ia-ranges.o
CC fs/ntfs/mst.o
CC [M] sound/pci/hda/hda_intel.o
AR drivers/dma/dw/built-in.a
CC [M] sound/core/pcm_timer.o
CC drivers/dma/hsu/hsu.o
CC drivers/pci/proc.o
CC arch/x86/kernel/dumpstack_64.o
CC drivers/virtio/virtio_pci_common.o
CC kernel/time/clocksource.o
CC kernel/irq/msi.o
CC drivers/acpi/acpica/evmisc.o
CC net/ethtool/tsinfo.o
CC lib/klist.o
CC fs/ntfs/namei.o
CC drivers/char/tpm/tpm1-cmd.o
CC fs/ntfs/runlist.o
LD [M] sound/core/snd-ctl-led.o
LD [M] sound/core/snd-hwdep.o
CC drivers/tty/serial/8250/8250_dwlib.o
AR sound/core/built-in.a
CC drivers/tty/serial/8250/8250_pcilib.o
CC [M] drivers/video/fbdev/core/cfbimgblt.o
CC drivers/acpi/acpica/evregion.o
AR kernel/rcu/built-in.a
CC drivers/acpi/acpica/evrgnini.o
CC drivers/acpi/acpica/evsci.o
CC drivers/acpi/acpica/evxface.o
CC drivers/char/agp/isoch.o
AR sound/parisc/built-in.a
CC drivers/char/agp/intel-agp.o
LD [M] sound/core/snd-pcm.o
CC drivers/acpi/acpica/evxfevnt.o
CC drivers/tty/serial/8250/8250_pci.o
CC arch/x86/kernel/time.o
AR sound/pcmcia/vx/built-in.a
CC drivers/acpi/acpica/evxfgpe.o
CC drivers/acpi/acpica/evxfregn.o
AR sound/pcmcia/pdaudiocf/built-in.a
CC drivers/acpi/acpica/exconcat.o
AR sound/pcmcia/built-in.a
CC lib/zstd/compress/zstd_ldm.o
CC block/bsg.o
CC crypto/ctr.o
CC net/core/neighbour.o
AR kernel/bpf/built-in.a
CC drivers/pci/slot.o
CC fs/lockd/svcsubs.o
AR sound/mips/built-in.a
CC drivers/pci/pci-acpi.o
AR drivers/dma/hsu/built-in.a
AR drivers/dma/idxd/built-in.a
AR drivers/dma/mediatek/built-in.a
CC drivers/clk/clk-fixed-rate.o
AR drivers/dma/qcom/built-in.a
CC [M] net/netfilter/nf_conntrack_proto_icmp.o
CC drivers/virtio/virtio_pci_legacy.o
AR drivers/dma/ti/built-in.a
CC [M] drivers/virtio/virtio_mem.o
AR drivers/dma/xilinx/built-in.a
CC [M] drivers/dma/ioat/init.o
CC drivers/dma/dmaengine.o
CC kernel/time/jiffies.o
CC [M] drivers/dma/ioat/dma.o
CC drivers/char/agp/intel-gtt.o
CC net/ethtool/cabletest.o
CC drivers/dma/virt-dma.o
CC kernel/cgroup/namespace.o
CC kernel/cgroup/cgroup-v1.o
CC drivers/tty/vt/consolemap.o
CC [M] drivers/video/fbdev/core/sysfillrect.o
CC arch/x86/kernel/ioport.o
CC fs/lockd/mon.o
CC drivers/char/tpm/tpm2-cmd.o
AR sound/soc/built-in.a
CC [M] arch/x86/kvm/lapic.o
CC drivers/acpi/acpica/exconfig.o
CC net/ethtool/tunnels.o
CC fs/btrfs/super.o
CC crypto/gcm.o
CC kernel/irq/affinity.o
CC fs/ntfs/super.o
CC [M] arch/x86/kvm/i8254.o
CC drivers/tty/serial/8250/8250_exar.o
CC arch/x86/kernel/dumpstack.o
CC fs/pstore/inode.o
CC kernel/time/timer_list.o
CC kernel/time/timeconv.o
CC fs/pstore/platform.o
CC block/bsg-lib.o
CC fs/nfs/sysfs.o
CC fs/pstore/pmsg.o
CC [M] arch/x86/kvm/ioapic.o
LD [M] sound/pci/hda/snd-hda-codec.o
LD [M] sound/pci/hda/snd-hda-codec-generic.o
CC drivers/acpi/acpica/exconvrt.o
LD [M] sound/pci/hda/snd-hda-codec-realtek.o
LD [M] sound/pci/hda/snd-hda-codec-analog.o
LD [M] sound/pci/hda/snd-hda-codec-hdmi.o
CC kernel/irq/matrix.o
LD [M] sound/pci/hda/snd-hda-intel.o
CC drivers/dma/acpi-dma.o
CC kernel/cgroup/freezer.o
AR sound/pci/rme9652/built-in.a
AR sound/pci/trident/built-in.a
CC kernel/cgroup/legacy_freezer.o
AR sound/pci/ymfpci/built-in.a
AR sound/pci/vx222/built-in.a
AR sound/pci/built-in.a
CC drivers/tty/serial/8250/8250_early.o
CC fs/nfs/fs_context.o
AR sound/atmel/built-in.a
CC drivers/pci/quirks.o
AR sound/hda/built-in.a
CC [M] sound/hda/hda_bus_type.o
CC [M] drivers/video/fbdev/core/syscopyarea.o
CC [M] sound/hda/hdac_bus.o
HOSTCC drivers/tty/vt/conmakehash
CC [M] net/netfilter/nf_conntrack_extend.o
AR drivers/char/agp/built-in.a
CC drivers/char/mem.o
CC drivers/char/random.o
CC drivers/char/misc.o
CC arch/x86/kernel/nmi.o
CC drivers/tty/vt/vt.o
CC drivers/char/tpm/tpmrm-dev.o
CC kernel/trace/trace_output.o
CC drivers/char/virtio_console.o
CC [M] drivers/dma/ioat/prep.o
CC [M] drivers/video/fbdev/core/sysimgblt.o
COPY drivers/tty/vt/defkeymap.c
CC arch/x86/kernel/ldt.o
CC kernel/time/timecounter.o
AR fs/pstore/built-in.a
CC drivers/acpi/acpica/excreate.o
CC arch/x86/kernel/setup.o
CC [M] drivers/video/fbdev/core/fb_sys_fops.o
CC net/ethtool/fec.o
CC fs/lockd/xdr.o
CC kernel/time/alarmtimer.o
CC mm/mmu_gather.o
CC block/blk-cgroup.o
CC drivers/acpi/acpica/exdebug.o
CC kernel/trace/trace_seq.o
CC crypto/pcrypt.o
CC drivers/char/hpet.o
CC kernel/cgroup/pids.o
CC fs/efivarfs/inode.o
CC drivers/tty/serial/8250/8250_dw.o
CC fs/efivarfs/file.o
CC drivers/clk/clk-gate.o
AR drivers/dma/built-in.a
CC [M] sound/hda/hdac_device.o
CC net/ethtool/eeprom.o
CC fs/ntfs/sysctl.o
CC fs/ntfs/unistr.o
CC [M] fs/netfs/buffered_read.o
CC kernel/cgroup/cpuset.o
CC [M] fs/netfs/io.o
CC kernel/panic.o
AR drivers/virtio/built-in.a
CC [M] fs/netfs/iterator.o
CC kernel/events/callchain.o
CC drivers/acpi/acpica/exdump.o
AR drivers/iommu/amd/built-in.a
CC drivers/iommu/intel/dmar.o
CC drivers/char/tpm/tpm2-space.o
CC drivers/iommu/intel/iommu.o
CC kernel/cpu.o
CC crypto/cryptd.o
CC [M] fs/fscache/cache.o
CC [M] fs/fscache/cookie.o
CC drivers/tty/serial/8250/8250_lpss.o
AR kernel/irq/built-in.a
CC [M] fs/fscache/io.o
CC [M] net/netfilter/nf_conntrack_acct.o
CC mm/mprotect.o
LD [M] drivers/video/fbdev/core/fb.o
CC [M] fs/fscache/main.o
CC net/ethtool/stats.o
CC drivers/clk/clk-multiplier.o
CC fs/efivarfs/super.o
AR drivers/video/fbdev/core/built-in.a
AR drivers/video/fbdev/built-in.a
AR drivers/video/built-in.a
CC drivers/clk/clk-mux.o
CC [M] fs/netfs/main.o
CC drivers/acpi/acpica/exfield.o
CC fs/ext4/mballoc.o
CC fs/ext4/migrate.o
CC arch/x86/kernel/x86_init.o
CC [M] drivers/dma/ioat/dca.o
CC fs/lockd/clnt4xdr.o
CC kernel/time/posix-timers.o
CC lib/kobject.o
CC fs/ntfs/upcase.o
CC [M] sound/hda/hdac_sysfs.o
CC [M] net/netfilter/nf_conntrack_seqadj.o
CC kernel/trace/trace_stat.o
CC drivers/acpi/acpica/exfldio.o
CC [M] drivers/dma/ioat/sysfs.o
CC kernel/exit.o
CC kernel/softirq.o
CC drivers/iommu/intel/pasid.o
CC net/ethtool/phc_vclocks.o
CC crypto/des_generic.o
CC lib/kobject_uevent.o
CC drivers/char/nvram.o
CC fs/nfs/sysctl.o
CC drivers/char/tpm/tpm-sysfs.o
AR net/ipv4/netfilter/built-in.a
CC drivers/clk/clk-composite.o
CC [M] net/ipv4/netfilter/nf_defrag_ipv4.o
CC drivers/tty/serial/8250/8250_mid.o
CC fs/efivarfs/vars.o
CC [M] net/ipv4/netfilter/nf_reject_ipv4.o
CC [M] arch/x86/kvm/irq_comm.o
CC lib/zstd/compress/zstd_opt.o
CC drivers/clk/clk-fractional-divider.o
CC arch/x86/kernel/i8259.o
CC drivers/char/tpm/eventlog/common.o
CC [M] net/netfilter/nf_conntrack_proto_icmpv6.o
AR fs/ntfs/built-in.a
CC [M] fs/fscache/volume.o
CC [M] net/netfilter/nf_conntrack_proto_dccp.o
CC drivers/acpi/acpica/exmisc.o
CC crypto/aes_generic.o
CC [M] fs/netfs/objects.o
CC block/blk-cgroup-rwstat.o
CC drivers/tty/serial/8250/8250_pericom.o
CC drivers/pci/ats.o
LD [M] drivers/dma/ioat/ioatdma.o
CC fs/ext4/mmp.o
CC [M] fs/fscache/proc.o
CC kernel/trace/trace_printk.o
CC net/core/rtnetlink.o
CC [M] sound/hda/hdac_regmap.o
CC drivers/clk/clk-gpio.o
CC drivers/char/tpm/eventlog/tpm1.o
CC arch/x86/kernel/irqinit.o
CC fs/lockd/xdr4.o
CC fs/nfs/nfs2super.o
CC fs/nfs/proc.o
CC lib/logic_pio.o
CC fs/ext4/move_extent.o
CC mm/mremap.o
CC net/ethtool/mm.o
CC drivers/acpi/acpica/exmutex.o
CC fs/lockd/svc4proc.o
CC drivers/iommu/intel/trace.o
CC fs/lockd/procfs.o
AR drivers/gpu/host1x/built-in.a
AR fs/efivarfs/built-in.a
CC mm/msync.o
CC [M] net/ipv4/netfilter/ip_tables.o
AR drivers/gpu/drm/tests/built-in.a
CC [M] drivers/gpu/drm/tests/drm_kunit_helpers.o
CC [M] net/ipv4/netfilter/iptable_filter.o
AR drivers/gpu/drm/arm/built-in.a
AR drivers/gpu/drm/display/built-in.a
CC [M] drivers/gpu/drm/display/drm_display_helper_mod.o
AR drivers/gpu/drm/rcar-du/built-in.a
CC drivers/tty/vt/defkeymap.o
CC [M] drivers/gpu/drm/display/drm_dp_dual_mode_helper.o
AR drivers/clk/built-in.a
CC [M] net/ipv4/netfilter/iptable_mangle.o
CC [M] drivers/gpu/drm/display/drm_dp_helper.o
CC drivers/iommu/intel/cap_audit.o
AR drivers/tty/serial/8250/built-in.a
CC drivers/tty/serial/earlycon.o
CC block/blk-throttle.o
CC drivers/pci/iov.o
CC block/mq-deadline.o
CC [M] arch/x86/kvm/cpuid.o
CC kernel/time/posix-cpu-timers.o
LD [M] fs/netfs/netfs.o
CONMK drivers/tty/vt/consolemap_deftbl.c
CC drivers/tty/vt/consolemap_deftbl.o
CC arch/x86/kernel/jump_label.o
CC drivers/acpi/acpica/exnames.o
AR drivers/tty/vt/built-in.a
CC drivers/char/tpm/eventlog/tpm2.o
LD [M] fs/fscache/fscache.o
AR drivers/gpu/vga/built-in.a
CC drivers/char/tpm/tpm_ppi.o
CC kernel/trace/pid_list.o
CC kernel/resource.o
CC [M] fs/smbfs_common/cifs_arc4.o
AR sound/x86/built-in.a
CC kernel/sysctl.o
CC [M] sound/hda/hdac_controller.o
CC fs/ext4/namei.o
CC drivers/acpi/acpica/exoparg1.o
CC fs/ext4/page-io.o
CC [M] drivers/gpu/drm/tests/drm_buddy_test.o
CC [M] sound/hda/hdac_stream.o
CC [M] drivers/gpu/drm/display/drm_dp_mst_topology.o
CC [M] net/netfilter/nf_conntrack_proto_sctp.o
CC crypto/deflate.o
CC net/core/utils.o
AR sound/xen/built-in.a
AR drivers/iommu/arm/arm-smmu/built-in.a
AR sound/virtio/built-in.a
AR drivers/iommu/arm/arm-smmu-v3/built-in.a
CC sound/sound_core.o
AR drivers/iommu/arm/built-in.a
AR drivers/iommu/iommufd/built-in.a
CC drivers/iommu/iommu.o
AR kernel/cgroup/built-in.a
CC [M] drivers/gpu/drm/display/drm_dsc_helper.o
CC [M] drivers/gpu/drm/tests/drm_cmdline_parser_test.o
CC crypto/crc32c_generic.o
CC [M] fs/smbfs_common/cifs_md4.o
CC kernel/events/hw_breakpoint.o
CC drivers/iommu/iommu-traces.o
CC net/ethtool/module.o
CC drivers/tty/serial/serial_mctrl_gpio.o
CC fs/nfs/nfs2xdr.o
CC arch/x86/kernel/irq_work.o
CC kernel/capability.o
CC drivers/acpi/acpica/exoparg2.o
CC drivers/iommu/intel/irq_remapping.o
CC drivers/acpi/acpica/exoparg3.o
CC drivers/char/tpm/eventlog/acpi.o
CC mm/page_vma_mapped.o
AR fs/lockd/built-in.a
CC lib/zstd/zstd_decompress_module.o
CC lib/zstd/decompress/huf_decompress.o
CC net/ipv4/route.o
CC lib/zstd/decompress/zstd_ddict.o
CC [M] drivers/gpu/drm/display/drm_hdcp_helper.o
CC arch/x86/kernel/probe_roms.o
CC [M] net/netfilter/nf_conntrack_netlink.o
CC drivers/iommu/intel/perfmon.o
CC kernel/trace/trace_sched_switch.o
CC kernel/trace/trace_functions.o
CC lib/zstd/decompress/zstd_decompress.o
CC crypto/crct10dif_common.o
CC net/ipv4/inetpeer.o
CC drivers/pci/pci-label.o
CC lib/zstd/decompress/zstd_decompress_block.o
CC [M] sound/hda/array.o
CC drivers/acpi/acpica/exoparg6.o
CC [M] net/ipv4/netfilter/iptable_nat.o
CC [M] drivers/gpu/drm/display/drm_hdmi_helper.o
CC drivers/acpi/acpica/exprep.o
CC fs/ext4/readpage.o
CC lib/zstd/zstd_common_module.o
CC kernel/time/posix-clock.o
CC kernel/time/itimer.o
CC lib/zstd/common/debug.o
AR drivers/tty/serial/built-in.a
CC drivers/tty/tty_io.o
CC crypto/crct10dif_generic.o
CC drivers/pci/pci-stub.o
CC [M] sound/hda/hdmi_chmap.o
CC block/kyber-iosched.o
CC net/core/link_watch.o
CC drivers/char/tpm/eventlog/efi.o
CC net/core/filter.o
CC [M] net/netfilter/nf_nat_core.o
CC net/ethtool/pse-pd.o
CC drivers/pci/vgaarb.o
CC arch/x86/kernel/sys_ia32.o
CC kernel/ptrace.o
CC fs/ext4/resize.o
CC drivers/acpi/acpica/exregion.o
CC block/bfq-iosched.o
CC net/core/sock_diag.o
CC [M] fs/cifs/trace.o
CC mm/pagewalk.o
CC [M] fs/fuse/dev.o
CC [M] fs/overlayfs/super.o
CC mm/pgtable-generic.o
CC [M] sound/hda/trace.o
CC crypto/authenc.o
CC [M] fs/cifs/cifsfs.o
CC mm/rmap.o
CC kernel/trace/trace_preemptirq.o
CC kernel/events/uprobes.o
CC kernel/trace/trace_nop.o
CC mm/vmalloc.o
CC [M] fs/overlayfs/namei.o
CC fs/btrfs/ctree.o
CC [M] arch/x86/kvm/pmu.o
CC net/core/dev_ioctl.o
CC drivers/char/tpm/tpm_crb.o
CC drivers/acpi/acpica/exresnte.o
AR drivers/iommu/intel/built-in.a
CC drivers/tty/n_tty.o
CC fs/open.o
CC kernel/time/clockevents.o
CC fs/nfs/nfs3super.o
CC [M] net/ipv4/netfilter/ipt_REJECT.o
CC [M] drivers/gpu/drm/tests/drm_connector_test.o
CC [M] sound/hda/hdac_component.o
CC arch/x86/kernel/signal_32.o
CC [M] fs/cifs/cifs_debug.o
CC net/ethtool/plca.o
CC block/bfq-wf2q.o
CC drivers/iommu/iommu-sysfs.o
CC [M] drivers/gpu/drm/display/drm_scdc_helper.o
CC drivers/acpi/acpica/exresolv.o
CC [M] drivers/gpu/drm/display/drm_dp_aux_dev.o
CC kernel/trace/trace_functions_graph.o
AR drivers/pci/built-in.a
CC kernel/time/tick-common.o
CC fs/read_write.o
CC [M] drivers/gpu/drm/tests/drm_damage_helper_test.o
CC lib/maple_tree.o
CC crypto/authencesn.o
CC net/xfrm/xfrm_policy.o
CC lib/memcat_p.o
CC crypto/lzo.o
CC fs/nfs/nfs3client.o
AR drivers/char/tpm/built-in.a
AR drivers/char/built-in.a
CC drivers/connector/cn_queue.o
CC [M] net/netfilter/nf_nat_proto.o
CC drivers/acpi/acpica/exresop.o
CC [M] sound/hda/hdac_i915.o
CC drivers/base/power/sysfs.o
CC drivers/iommu/dma-iommu.o
CC drivers/base/power/generic_ops.o
CC drivers/base/power/common.o
CC arch/x86/kernel/sys_x86_64.o
CC [M] fs/overlayfs/util.o
CC drivers/acpi/acpica/exserial.o
CC drivers/connector/connector.o
CC block/bfq-cgroup.o
CC fs/file_table.o
CC [M] arch/x86/kvm/mtrr.o
CC drivers/tty/tty_ioctl.o
CC arch/x86/kernel/espfix_64.o
CC net/xfrm/xfrm_state.o
AR net/ethtool/built-in.a
CC net/unix/af_unix.o
CC fs/ext4/super.o
CC net/xfrm/xfrm_hash.o
CC block/blk-mq-pci.o
CC fs/ext4/symlink.o
CC fs/nfs/nfs3proc.o
CC drivers/base/power/qos.o
LD [M] drivers/gpu/drm/display/drm_display_helper.o
CC kernel/time/tick-broadcast.o
AR drivers/gpu/drm/omapdrm/built-in.a
CC [M] fs/fuse/dir.o
CC kernel/time/tick-broadcast-hrtimer.o
CC [M] fs/fuse/file.o
CC drivers/acpi/acpica/exstore.o
CC [M] sound/hda/intel-dsp-config.o
CC kernel/time/tick-oneshot.o
CC drivers/tty/tty_ldisc.o
AR kernel/events/built-in.a
CC kernel/user.o
CC crypto/lzo-rle.o
CC kernel/trace/fgraph.o
CC [M] sound/hda/intel-nhlt.o
CC mm/page_alloc.o
CC [M] drivers/gpu/drm/tests/drm_dp_mst_helper_test.o
CC [M] drivers/gpu/drm/tests/drm_format_helper_test.o
CC fs/nfs/nfs3xdr.o
CC drivers/acpi/acpica/exstoren.o
CC [M] fs/cifs/connect.o
CC crypto/lz4.o
CC crypto/lz4hc.o
CC net/ipv4/protocol.o
CC fs/super.o
CC drivers/base/power/runtime.o
CC arch/x86/kernel/ksysfs.o
CC arch/x86/kernel/bootflag.o
CC drivers/acpi/acpica/exstorob.o
AR drivers/gpu/drm/tilcdc/built-in.a
CC drivers/acpi/proc.o
AR net/ipv6/netfilter/built-in.a
CC [M] net/netfilter/nf_nat_helper.o
CC [M] net/ipv6/netfilter/nf_defrag_ipv6_hooks.o
CC [M] net/netfilter/nf_nat_redirect.o
CC net/unix/garbage.o
CC drivers/connector/cn_proc.o
AR drivers/gpu/drm/imx/built-in.a
AR drivers/gpu/drm/i2c/built-in.a
CC [M] arch/x86/kvm/hyperv.o
AR drivers/gpu/drm/panel/built-in.a
CC [M] arch/x86/kvm/debugfs.o
CC [M] net/ipv6/netfilter/nf_conntrack_reasm.o
CC [M] fs/overlayfs/inode.o
CC drivers/tty/tty_buffer.o
CC kernel/time/tick-sched.o
CC lib/zstd/common/entropy_common.o
CC drivers/acpi/acpica/exsystem.o
CC [M] net/netfilter/nf_nat_masquerade.o
CC [M] sound/hda/intel-sdw-acpi.o
CC lib/nmi_backtrace.o
CC [M] arch/x86/kvm/mmu/mmu.o
CC sound/last.o
CC drivers/iommu/ioasid.o
CC crypto/xxhash_generic.o
CC fs/char_dev.o
CC net/ipv6/af_inet6.o
CC lib/zstd/common/error_private.o
CC drivers/base/firmware_loader/builtin/main.o
CC kernel/trace/blktrace.o
CC lib/zstd/common/fse_decompress.o
CC drivers/base/firmware_loader/main.o
AR drivers/gpu/drm/bridge/analogix/built-in.a
CC arch/x86/kernel/e820.o
AR drivers/gpu/drm/bridge/cadence/built-in.a
AR drivers/gpu/drm/bridge/imx/built-in.a
CC [M] net/netfilter/x_tables.o
AR drivers/gpu/drm/bridge/synopsys/built-in.a
AR drivers/gpu/drm/bridge/built-in.a
CC [M] fs/cifs/dir.o
CC [M] drivers/gpu/drm/tests/drm_format_test.o
CC drivers/acpi/acpica/extrace.o
CC [M] arch/x86/kvm/mmu/page_track.o
AR drivers/base/firmware_loader/builtin/built-in.a
CC net/xfrm/xfrm_input.o
CC crypto/rng.o
CC [M] net/netfilter/xt_tcpudp.o
CC block/blk-mq-virtio.o
LD [M] sound/hda/snd-hda-core.o
CC net/ipv4/ip_input.o
CC drivers/acpi/acpica/exutils.o
LD [M] sound/hda/snd-intel-dspcfg.o
LD [M] sound/hda/snd-intel-sdw-acpi.o
AR sound/built-in.a
CC drivers/iommu/iova.o
CC net/ipv4/ip_fragment.o
CC net/ipv6/anycast.o
CC drivers/tty/tty_port.o
CC [M] fs/fuse/inode.o
CC [M] arch/x86/kvm/mmu/spte.o
CC [M] fs/cifs/file.o
CC drivers/base/power/wakeirq.o
CC net/xfrm/xfrm_output.o
CC drivers/base/regmap/regmap.o
CC [M] fs/overlayfs/file.o
AR drivers/connector/built-in.a
AR drivers/base/test/built-in.a
CC lib/plist.o
CC drivers/acpi/acpica/hwacpi.o
CC block/blk-mq-debugfs.o
CC mm/init-mm.o
CC kernel/time/vsyscall.o
CC kernel/time/timekeeping_debug.o
CC fs/stat.o
CC kernel/trace/trace_events.o
CC [M] arch/x86/kvm/mmu/tdp_iter.o
CC drivers/acpi/acpica/hwesleep.o
CC lib/zstd/common/zstd_common.o
CC fs/btrfs/extent-tree.o
AR lib/zstd/built-in.a
CC block/blk-pm.o
AR drivers/gpu/drm/hisilicon/built-in.a
CC [M] net/netfilter/xt_mark.o
AR drivers/gpu/drm/mxsfb/built-in.a
AR drivers/gpu/drm/tiny/built-in.a
AR drivers/gpu/drm/xlnx/built-in.a
CC crypto/drbg.o
AR drivers/gpu/drm/gud/built-in.a
CC drivers/base/power/main.o
LD [M] net/ipv6/netfilter/nf_defrag_ipv6.o
CC drivers/acpi/acpica/hwgpe.o
CC drivers/base/power/wakeup.o
AR drivers/base/firmware_loader/built-in.a
CC lib/radix-tree.o
CC [M] drivers/gpu/drm/tests/drm_framebuffer_test.o
CC drivers/acpi/acpica/hwregs.o
CC drivers/block/loop.o
AR fs/nfs/built-in.a
CC arch/x86/kernel/pci-dma.o
CC arch/x86/kernel/quirks.o
CC drivers/base/power/wakeup_stats.o
AR drivers/misc/eeprom/built-in.a
AR drivers/misc/cb710/built-in.a
AR drivers/misc/ti-st/built-in.a
CC drivers/iommu/irq_remapping.o
AR drivers/misc/lis3lv02d/built-in.a
CC mm/memblock.o
AR drivers/misc/cardreader/built-in.a
CC drivers/tty/tty_mutex.o
CC [M] drivers/misc/mei/hdcp/mei_hdcp.o
CC kernel/time/namespace.o
CC net/unix/sysctl_net_unix.o
CC mm/memory_hotplug.o
CC fs/exec.o
CC [M] drivers/misc/mei/pxp/mei_pxp.o
CC net/packet/af_packet.o
CC drivers/acpi/acpica/hwsleep.o
CC net/packet/diag.o
CC block/holder.o
CC [M] drivers/gpu/drm/tests/drm_managed_test.o
CC [M] drivers/gpu/drm/tests/drm_mm_test.o
CC [M] fs/overlayfs/dir.o
CC drivers/acpi/acpica/hwvalid.o
CC net/ipv6/ip6_output.o
CC [M] net/netfilter/xt_nat.o
CC net/key/af_key.o
CC drivers/base/power/domain.o
CC fs/pipe.o
CC drivers/tty/tty_ldsem.o
CC mm/madvise.o
CC drivers/mfd/mfd-core.o
CC net/ipv4/ip_forward.o
AR drivers/iommu/built-in.a
AR drivers/nfc/built-in.a
CC net/ipv4/ip_options.o
AR drivers/dax/hmem/built-in.a
CC arch/x86/kernel/topology.o
CC drivers/dax/super.o
CC [M] fs/fuse/control.o
CC net/xfrm/xfrm_sysctl.o
CC crypto/jitterentropy.o
CC [M] fs/cifs/inode.o
CC drivers/acpi/acpica/hwxface.o
AR kernel/time/built-in.a
CC drivers/acpi/acpica/hwxfsleep.o
CC crypto/jitterentropy-kcapi.o
CC crypto/ghash-generic.o
CC [M] net/netfilter/xt_REDIRECT.o
AR net/bridge/netfilter/built-in.a
CC net/bridge/br.o
CC [M] drivers/misc/mei/init.o
CC [M] net/sunrpc/auth_gss/auth_gss.o
CC net/sunrpc/clnt.o
CC net/unix/diag.o
AR block/built-in.a
CC net/sunrpc/xprt.o
CC arch/x86/kernel/kdebugfs.o
CC net/ipv6/ip6_input.o
CC lib/ratelimit.o
CC drivers/base/power/domain_governor.o
CC drivers/acpi/acpica/hwpci.o
CC drivers/acpi/acpica/nsaccess.o
AR drivers/misc/built-in.a
CC crypto/af_alg.o
CC crypto/algif_hash.o
CC mm/page_io.o
CC lib/rbtree.o
CC drivers/tty/tty_baudrate.o
CC drivers/dax/bus.o
CC [M] net/sunrpc/auth_gss/gss_generic_token.o
CC drivers/mfd/intel-lpss.o
CC [M] fs/fuse/xattr.o
CC [M] fs/cifs/link.o
CC [M] fs/overlayfs/readdir.o
CC [M] drivers/block/nbd.o
CC [M] drivers/misc/mei/hbm.o
CC net/unix/scm.o
CC arch/x86/kernel/alternative.o
CC net/bridge/br_device.o
CC net/xfrm/xfrm_replay.o
CC net/ipv4/ip_output.o
CC [M] net/netfilter/xt_MASQUERADE.o
CC lib/seq_buf.o
CC kernel/trace/trace_export.o
CC drivers/acpi/acpica/nsalloc.o
CC lib/show_mem.o
CC lib/siphash.o
CC lib/string.o
CC kernel/trace/trace_event_perf.o
CC drivers/tty/tty_jobctrl.o
CC arch/x86/kernel/i8253.o
CC drivers/mfd/intel-lpss-pci.o
CC net/ipv6/addrconf.o
CC net/ipv6/addrlabel.o
CC drivers/base/power/clock_ops.o
CC drivers/mfd/intel-lpss-acpi.o
CC arch/x86/kernel/hw_breakpoint.o
CC [M] fs/fuse/acl.o
CC [M] arch/x86/kvm/mmu/tdp_mmu.o
CC drivers/base/regmap/regcache.o
CC [M] drivers/gpu/drm/tests/drm_modes_test.o
CC drivers/acpi/acpica/nsarguments.o
CC lib/timerqueue.o
CC net/bridge/br_fdb.o
CC crypto/algif_skcipher.o
CC mm/swap_state.o
CC lib/vsprintf.o
CC arch/x86/kernel/tsc.o
CC drivers/base/regmap/regcache-rbtree.o
CC [M] fs/fuse/readdir.o
CC [M] arch/x86/kvm/smm.o
CC net/ipv6/route.o
AR net/unix/built-in.a
CC [M] drivers/misc/mei/interrupt.o
CC [M] drivers/misc/mei/client.o
AR drivers/dax/built-in.a
CC drivers/mfd/intel_soc_pmic_crc.o
CC drivers/tty/n_null.o
CC [M] fs/overlayfs/copy_up.o
CC drivers/tty/pty.o
CC drivers/acpi/acpica/nsconvert.o
AR drivers/base/power/built-in.a
CC [M] net/netfilter/xt_addrtype.o
CC drivers/tty/sysrq.o
CC arch/x86/kernel/tsc_msr.o
CC mm/swapfile.o
CC [M] drivers/mfd/lpc_sch.o
CC kernel/trace/trace_events_filter.o
CC crypto/xor.o
CC [M] net/netfilter/xt_conntrack.o
CC [M] fs/fuse/ioctl.o
CC fs/btrfs/print-tree.o
CC [M] drivers/gpu/drm/tests/drm_plane_helper_test.o
CC fs/btrfs/root-tree.o
CC net/xfrm/xfrm_device.o
CC fs/btrfs/dir-item.o
AR net/key/built-in.a
CC net/ipv4/ip_sockglue.o
CC net/bridge/br_forward.o
CC net/core/tso.o
CC net/sunrpc/socklib.o
CC drivers/base/regmap/regcache-flat.o
CC net/ipv6/ip6_fib.o
CC mm/swap_slots.o
CC [M] net/sunrpc/auth_gss/gss_mech_switch.o
CC drivers/acpi/acpica/nsdump.o
CC [M] drivers/mfd/lpc_ich.o
CC net/sunrpc/xprtsock.o
CC crypto/hash_info.o
CC net/sunrpc/sched.o
CC crypto/simd.o
CC arch/x86/kernel/io_delay.o
CC arch/x86/kernel/rtc.o
CC [M] drivers/misc/mei/main.o
CC net/sunrpc/auth.o
CC drivers/dma-buf/dma-buf.o
CC drivers/dma-buf/dma-fence.o
CC mm/dmapool.o
LD [M] fs/fuse/fuse.o
CC [M] drivers/gpu/drm/tests/drm_probe_helper_test.o
AR net/packet/built-in.a
CC net/core/sock_reuseport.o
CC drivers/base/regmap/regmap-debugfs.o
CC arch/x86/kernel/resource.o
CC [M] fs/overlayfs/export.o
CC drivers/acpi/acpica/nseval.o
AR drivers/tty/built-in.a
CC fs/btrfs/file-item.o
CC fs/namei.o
CC [M] arch/x86/kvm/vmx/vmx.o
CC net/core/fib_notifier.o
CC mm/hugetlb.o
CC lib/win_minmax.o
CC [M] fs/cifs/misc.o
CC net/8021q/vlan_core.o
CC [M] net/netfilter/xt_ipvs.o
CC [M] crypto/md4.o
CC net/core/xdp.o
CC fs/btrfs/inode-item.o
AR drivers/block/built-in.a
AS arch/x86/kernel/irqflags.o
CC kernel/trace/trace_events_trigger.o
CC net/ipv4/inet_hashtables.o
CC drivers/acpi/acpica/nsinit.o
CC arch/x86/kernel/static_call.o
CC net/dcb/dcbnl.o
AR drivers/mfd/built-in.a
CC net/dcb/dcbevent.o
CC net/l3mdev/l3mdev.o
CC net/xfrm/xfrm_algo.o
CC kernel/trace/trace_eprobe.o
CC [M] fs/cifs/netmisc.o
CC drivers/acpi/acpica/nsload.o
CC net/bridge/br_if.o
CC kernel/trace/trace_kprobe.o
CC [M] net/sunrpc/auth_gss/svcauth_gss.o
CC [M] drivers/gpu/drm/tests/drm_rect_test.o
CC drivers/acpi/bus.o
CC drivers/acpi/glue.o
CC mm/hugetlb_vmemmap.o
CC drivers/base/regmap/regmap-i2c.o
CC [M] drivers/misc/mei/dma-ring.o
LD [M] fs/overlayfs/overlay.o
CC arch/x86/kernel/process.o
CC [M] crypto/ccm.o
CC net/ipv4/inet_timewait_sock.o
CC drivers/base/regmap/regmap-irq.o
CC net/sunrpc/auth_null.o
CC drivers/dma-buf/dma-fence-array.o
CC drivers/acpi/acpica/nsnames.o
CC [M] crypto/arc4.o
CC [M] crypto/ecc.o
CC drivers/dma-buf/dma-fence-chain.o
CC lib/xarray.o
CC lib/lockref.o
CC net/ipv4/inet_connection_sock.o
AR drivers/gpu/drm/solomon/built-in.a
CC [M] drivers/gpu/drm/ttm/ttm_tt.o
LD [M] net/netfilter/nf_conntrack.o
CC net/ipv4/tcp.o
AR net/l3mdev/built-in.a
CC [M] drivers/misc/mei/bus.o
LD [M] net/netfilter/nf_nat.o
CC drivers/dma-buf/dma-fence-unwrap.o
AR net/netfilter/built-in.a
CC [M] fs/cifs/smbencrypt.o
CC [M] crypto/essiv.o
CC kernel/signal.o
CC drivers/acpi/acpica/nsobject.o
CC [M] net/8021q/vlan.o
CC [M] drivers/gpu/drm/ttm/ttm_bo.o
CC lib/bcd.o
CC [M] net/bluetooth/af_bluetooth.o
CC lib/sort.o
CC mm/sparse.o
CC net/xfrm/xfrm_user.o
CC net/ipv6/ipv6_sockglue.o
CC drivers/acpi/scan.o
CC mm/sparse-vmemmap.o
CC drivers/acpi/resource.o
CC net/sunrpc/auth_unix.o
CC net/sunrpc/svc.o
CC [M] drivers/misc/mei/bus-fixup.o
CC [M] net/sunrpc/auth_gss/gss_rpc_upcall.o
CC fs/ext4/sysfs.o
CC fs/btrfs/disk-io.o
CC [M] crypto/ecdh.o
CC net/ipv6/ndisc.o
CC [M] drivers/gpu/drm/ttm/ttm_bo_util.o
CC net/core/flow_offload.o
CC [M] net/sunrpc/auth_gss/gss_rpc_xdr.o
CC drivers/dma-buf/dma-resv.o
CC net/bridge/br_input.o
CC drivers/acpi/acpica/nsparse.o
CC kernel/trace/error_report-traces.o
CC net/ipv4/tcp_input.o
AR drivers/base/regmap/built-in.a
CC drivers/base/component.o
CC arch/x86/kernel/ptrace.o
CC [M] drivers/gpu/drm/ttm/ttm_bo_vm.o
CC [M] crypto/ecdh_helper.o
CC [M] drivers/misc/mei/debugfs.o
CC lib/parser.o
CC drivers/acpi/acpica/nspredef.o
AR net/dcb/built-in.a
CC drivers/acpi/acpica/nsprepkg.o
CC mm/mmu_notifier.o
CC kernel/trace/power-traces.o
CC net/bridge/br_ioctl.o
CC arch/x86/kernel/tls.o
CC net/sunrpc/svcsock.o
CC mm/ksm.o
CC mm/slub.o
CC arch/x86/kernel/step.o
CC [M] fs/cifs/transport.o
CC [M] net/bluetooth/hci_core.o
CC fs/btrfs/transaction.o
CC fs/btrfs/inode.o
CC [M] net/dns_resolver/dns_key.o
CC [M] net/8021q/vlan_dev.o
CC [M] net/dns_resolver/dns_query.o
CC fs/ext4/xattr.o
CC [M] drivers/gpu/drm/scheduler/sched_main.o
CC lib/debug_locks.o
LD [M] crypto/ecdh_generic.o
CC net/core/gro.o
CC kernel/trace/rpm-traces.o
AR crypto/built-in.a
CC [M] net/sunrpc/auth_gss/trace.o
CC [M] net/bluetooth/hci_conn.o
CC kernel/trace/trace_dynevent.o
CC drivers/base/core.o
CC drivers/acpi/acpica/nsrepair.o
CC [M] drivers/misc/mei/mei-trace.o
CC drivers/dma-buf/sync_file.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_drv.o
CC [M] drivers/gpu/drm/ttm/ttm_module.o
CC [M] drivers/gpu/drm/scheduler/sched_fence.o
CC lib/random32.o
CC drivers/dma-buf/sw_sync.o
CC drivers/acpi/acpi_processor.o
CC drivers/acpi/processor_core.o
CC net/ipv4/tcp_output.o
CC fs/fcntl.o
CC net/devres.o
CC arch/x86/kernel/i8237.o
CC [M] arch/x86/kvm/kvm-asm-offsets.s
CC drivers/acpi/acpica/nsrepair2.o
CC drivers/acpi/acpica/nssearch.o
CC lib/bust_spinlocks.o
LD [M] net/dns_resolver/dns_resolver.o
CC [M] drivers/gpu/drm/ttm/ttm_execbuf_util.o
CC fs/btrfs/file.o
CC kernel/trace/trace_probe.o
CC drivers/dma-buf/sync_debug.o
CC net/ipv4/tcp_timer.o
CC kernel/trace/trace_uprobe.o
CC net/bridge/br_stp.o
CC kernel/trace/rethook.o
CC mm/migrate.o
CC arch/x86/kernel/stacktrace.o
CC net/sunrpc/svcauth.o
CC [M] drivers/misc/mei/pci-me.o
CC drivers/acpi/acpica/nsutils.o
CC [M] net/bluetooth/hci_event.o
CC [M] net/8021q/vlan_netlink.o
CC [M] drivers/dma-buf/selftest.o
CC [M] drivers/dma-buf/st-dma-fence.o
CC lib/kasprintf.o
CC [M] drivers/dma-buf/st-dma-fence-chain.o
CC net/ipv6/udp.o
CC net/bridge/br_stp_bpdu.o
CC net/socket.o
CC net/sunrpc/svcauth_unix.o
CC drivers/acpi/acpica/nswalk.o
CC [M] drivers/gpu/drm/ttm/ttm_range_manager.o
CC arch/x86/kernel/reboot.o
AR net/xfrm/built-in.a
CC [M] drivers/gpu/drm/scheduler/sched_entity.o
CC drivers/acpi/processor_pdc.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_device.o
CC arch/x86/kernel/msr.o
CC lib/bitmap.o
CC drivers/acpi/acpica/nsxfeval.o
CC net/sunrpc/addr.o
CC [M] drivers/gpu/drm/ttm/ttm_resource.o
CC [M] arch/x86/kvm/vmx/pmu_intel.o
CC net/core/netdev-genl.o
CC [M] drivers/misc/mei/hw-me.o
CC drivers/acpi/acpica/nsxfname.o
CC mm/migrate_device.o
CC [M] drivers/dma-buf/st-dma-fence-unwrap.o
CC arch/x86/kernel/cpuid.o
CC arch/x86/kernel/early-quirks.o
CC [M] net/8021q/vlanproc.o
CC fs/ioctl.o
CC fs/readdir.o
CC net/bridge/br_stp_if.o
CC [M] fs/cifs/cached_dir.o
CC [M] drivers/dma-buf/st-dma-resv.o
CC drivers/acpi/ec.o
CC drivers/acpi/acpica/nsxfobj.o
CC [M] net/sunrpc/auth_gss/gss_krb5_mech.o
CC fs/ext4/xattr_hurd.o
CC [M] net/sunrpc/auth_gss/gss_krb5_seal.o
LD [M] drivers/gpu/drm/scheduler/gpu-sched.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_kms.o
CC drivers/acpi/dock.o
CC [M] net/sunrpc/auth_gss/gss_krb5_unseal.o
CC net/ipv4/tcp_ipv4.o
AR drivers/dma-buf/built-in.a
CC [M] drivers/gpu/drm/vgem/vgem_drv.o
CC [M] drivers/gpu/drm/i915/i915_driver.o
CC [M] drivers/gpu/drm/vgem/vgem_fence.o
CC net/ipv6/udplite.o
CC [M] drivers/gpu/drm/xe/tests/xe_bo_test.o
CC net/sunrpc/rpcb_clnt.o
CC [M] drivers/gpu/drm/ttm/ttm_pool.o
CC drivers/acpi/acpica/psargs.o
CC net/sunrpc/timer.o
CC lib/scatterlist.o
LD [M] drivers/dma-buf/dmabuf_selftests.o
AR drivers/cxl/core/built-in.a
AR drivers/cxl/built-in.a
CC net/core/netdev-genl-gen.o
AR kernel/trace/built-in.a
CC net/core/net-sysfs.o
CC fs/btrfs/defrag.o
CC kernel/sys.o
CC [M] fs/cifs/cifs_unicode.o
CC [M] drivers/gpu/drm/xe/tests/xe_dma_buf_test.o
CC drivers/base/bus.o
CC [M] net/bluetooth/mgmt.o
CC mm/huge_memory.o
CC arch/x86/kernel/smp.o
CC drivers/acpi/pci_root.o
CC fs/ext4/xattr_trusted.o
AR net/8021q/built-in.a
LD [M] net/8021q/8021q.o
CC [M] drivers/gpu/drm/xe/tests/xe_migrate_test.o
CC [M] net/bluetooth/hci_sock.o
CC net/sunrpc/xdr.o
CC mm/khugepaged.o
CC mm/page_counter.o
CC [M] net/sunrpc/auth_gss/gss_krb5_seqnum.o
CC drivers/acpi/pci_link.o
CC [M] net/sunrpc/auth_gss/gss_krb5_wrap.o
CC [M] net/bluetooth/hci_sysfs.o
CC [M] arch/x86/kvm/vmx/vmcs12.o
LD [M] drivers/gpu/drm/vgem/vgem.o
CC arch/x86/kernel/smpboot.o
CC [M] drivers/gpu/drm/nouveau/nvif/object.o
CC drivers/acpi/acpica/psloop.o
AR drivers/macintosh/built-in.a
CC arch/x86/kernel/tsc_sync.o
CC net/bridge/br_stp_timer.o
CC [M] drivers/gpu/drm/xe/tests/xe_pci_test.o
CC [M] arch/x86/kvm/vmx/hyperv.o
CC fs/ext4/xattr_user.o
CC net/compat.o
CC [M] drivers/misc/mei/gsc-me.o
CC arch/x86/kernel/setup_percpu.o
CC [M] drivers/gpu/drm/ttm/ttm_device.o
CC arch/x86/kernel/ftrace.o
CC kernel/umh.o
CC lib/list_sort.o
CC fs/ext4/fast_commit.o
CC net/ipv6/raw.o
CC net/sysctl_net.o
CC drivers/acpi/pci_irq.o
CC drivers/base/dd.o
CC mm/memcontrol.o
CC lib/uuid.o
CC drivers/acpi/acpica/psobject.o
LD [M] drivers/misc/mei/mei.o
CC [M] drivers/gpu/drm/i915/i915_drm_client.o
LD [M] drivers/misc/mei/mei-me.o
CC [M] drivers/gpu/drm/xe/xe_bb.o
CC [M] net/sunrpc/auth_gss/gss_krb5_crypto.o
CC fs/btrfs/extent_map.o
CC lib/iov_iter.o
CC [M] fs/cifs/nterr.o
CC net/ipv6/icmp.o
CC lib/clz_ctz.o
CC lib/bsearch.o
CC fs/btrfs/sysfs.o
CC lib/find_bit.o
CC [M] fs/cifs/cifsencrypt.o
CC lib/llist.o
CC net/ipv6/mcast.o
CC [M] arch/x86/kvm/vmx/nested.o
AS arch/x86/kernel/ftrace_64.o
CC [M] drivers/gpu/drm/xe/tests/xe_rtp_test.o
CC [M] drivers/gpu/drm/nouveau/nvif/client.o
CC [M] drivers/gpu/drm/nouveau/nvif/conn.o
CC [M] net/bluetooth/l2cap_core.o
CC [M] drivers/gpu/drm/nouveau/nvif/device.o
CC lib/memweight.o
LD [M] drivers/misc/mei/mei-gsc.o
CC drivers/scsi/scsi.o
CC [M] drivers/gpu/drm/ttm/ttm_sys_manager.o
CC drivers/scsi/hosts.o
CC drivers/acpi/acpica/psopcode.o
CC drivers/scsi/scsi_ioctl.o
CC drivers/scsi/scsicam.o
CC drivers/nvme/host/core.o
CC net/sunrpc/sunrpc_syms.o
CC net/bridge/br_netlink.o
CC kernel/workqueue.o
CC drivers/nvme/host/ioctl.o
CC drivers/acpi/acpi_lpss.o
CC net/core/net-procfs.o
CC drivers/nvme/host/trace.o
CC net/core/netpoll.o
CC arch/x86/kernel/trace_clock.o
CC net/bridge/br_netlink_tunnel.o
CC net/sunrpc/cache.o
CC kernel/pid.o
CC arch/x86/kernel/trace.o
CC drivers/base/syscore.o
CC drivers/acpi/acpica/psopinfo.o
CC [M] drivers/gpu/drm/ttm/ttm_agp_backend.o
CC [M] drivers/gpu/drm/i915/i915_config.o
CC drivers/acpi/acpica/psparse.o
CC drivers/acpi/acpica/psscope.o
CC [M] drivers/gpu/drm/xe/tests/xe_wa_test.o
CC drivers/ata/libata-core.o
CC drivers/spi/spi.o
CC [M] drivers/gpu/drm/nouveau/nvif/disp.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.o
CC [M] net/sunrpc/auth_gss/gss_krb5_keys.o
CC drivers/scsi/scsi_error.o
CC [M] drivers/gpu/drm/i915/i915_getparam.o
CC drivers/acpi/acpica/pstree.o
CC arch/x86/kernel/rethook.o
CC drivers/scsi/scsi_lib.o
CC net/sunrpc/rpc_pipe.o
CC net/ipv4/tcp_minisocks.o
CC drivers/acpi/acpica/psutils.o
CC [M] drivers/gpu/drm/ast/ast_drv.o
CC drivers/acpi/acpica/pswalk.o
CC drivers/gpu/drm/drm_mipi_dsi.o
CC net/ipv4/tcp_cong.o
LD [M] drivers/gpu/drm/ttm/ttm.o
CC drivers/scsi/scsi_lib_dma.o
CC [M] net/bluetooth/l2cap_sock.o
CC fs/ext4/orphan.o
CC [M] drivers/gpu/drm/ast/ast_i2c.o
CC [M] drivers/gpu/drm/xe/xe_bo.o
CC drivers/acpi/acpica/psxface.o
CC [M] drivers/gpu/drm/xe/xe_bo_evict.o
CC drivers/base/driver.o
CC fs/btrfs/accessors.o
CC [M] fs/cifs/readdir.o
CC [M] fs/cifs/ioctl.o
CC net/ipv6/reassembly.o
CC drivers/base/class.o
CC arch/x86/kernel/crash_core_64.o
CC drivers/ata/libata-scsi.o
CC [M] drivers/gpu/drm/nouveau/nvif/driver.o
CC net/sunrpc/sysfs.o
CC [M] drivers/gpu/drm/nouveau/nvif/event.o
LD [M] net/sunrpc/auth_gss/auth_rpcgss.o
CC [M] drivers/gpu/drm/i915/i915_ioctl.o
CC fs/btrfs/xattr.o
CC fs/btrfs/ordered-data.o
CC [M] fs/cifs/sess.o
LD [M] net/sunrpc/auth_gss/rpcsec_gss_krb5.o
CC net/bridge/br_arp_nd_proxy.o
CC net/core/fib_rules.o
CC drivers/acpi/acpica/rsaddr.o
CC drivers/base/platform.o
CC net/ipv6/tcp_ipv6.o
CC [M] fs/cifs/export.o
CC [M] drivers/gpu/drm/ast/ast_main.o
CC fs/btrfs/extent_io.o
CC drivers/acpi/acpica/rscalc.o
CC arch/x86/kernel/module.o
CC drivers/scsi/scsi_scan.o
CC net/sunrpc/svc_xprt.o
CC net/ipv6/ping.o
CC net/ipv6/exthdrs.o
AR fs/ext4/built-in.a
CC net/ipv6/datagram.o
CC [M] drivers/gpu/drm/ast/ast_mm.o
CC drivers/base/cpu.o
CC arch/x86/kernel/early_printk.o
CC [M] arch/x86/kvm/vmx/posted_intr.o
CC [M] drivers/gpu/drm/nouveau/nvif/fifo.o
CC lib/kfifo.o
CC [M] drivers/gpu/drm/amd/amdgpu/atombios_crtc.o
GEN drivers/scsi/scsi_devinfo_tbl.c
CC drivers/scsi/scsi_devinfo.o
CC drivers/scsi/scsi_sysctl.o
CC drivers/acpi/acpica/rscreate.o
CC net/ipv4/tcp_metrics.o
CC [M] drivers/gpu/drm/i915/i915_irq.o
CC [M] net/bluetooth/smp.o
CC [M] drivers/gpu/drm/drm_aperture.o
CC net/sunrpc/xprtmultipath.o
CC drivers/scsi/scsi_debugfs.o
CC arch/x86/kernel/hpet.o
CC net/ipv6/ip6_flowlabel.o
CC drivers/scsi/scsi_trace.o
CC mm/vmpressure.o
CC [M] drivers/gpu/drm/drm_atomic.o
CC arch/x86/kernel/amd_nb.o
CC arch/x86/kernel/kvm.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.o
CC arch/x86/kernel/kvmclock.o
CC [M] drivers/gpu/drm/ast/ast_mode.o
CC net/bridge/br_sysfs_if.o
CC drivers/base/firmware.o
CC [M] fs/cifs/unc.o
CC drivers/acpi/acpica/rsdumpinfo.o
CC [M] drivers/gpu/drm/nouveau/nvif/head.o
CC drivers/scsi/scsi_logging.o
CC [M] drivers/gpu/drm/drm_atomic_uapi.o
CC fs/btrfs/volumes.o
CC lib/percpu-refcount.o
CC net/ipv6/inet6_connection_sock.o
AR drivers/nvme/target/built-in.a
CC [M] fs/cifs/winucase.o
CC [M] fs/cifs/smb2ops.o
CC [M] drivers/gpu/drm/xe/xe_debugfs.o
CC [M] drivers/gpu/drm/i915/i915_mitigations.o
CC drivers/base/init.o
CC [M] drivers/gpu/drm/nouveau/nvif/mem.o
CC [M] net/bluetooth/lib.o
CC [M] drivers/gpu/drm/amd/amdgpu/atom.o
CC drivers/acpi/acpica/rsinfo.o
CC kernel/task_work.o
CC drivers/net/phy/mdio-boardinfo.o
CC net/core/net-traces.o
AR drivers/net/pse-pd/built-in.a
CC drivers/net/phy/mdio_devres.o
CC net/core/selftests.o
CC drivers/acpi/acpica/rsio.o
CC arch/x86/kernel/paravirt.o
CC kernel/extable.o
CC kernel/params.o
CC kernel/kthread.o
CC drivers/nvme/host/pci.o
CC drivers/acpi/acpica/rsirq.o
CC drivers/acpi/acpi_apd.o
CC fs/btrfs/async-thread.o
CC net/core/ptp_classifier.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_fence.o
CC lib/rhashtable.o
AR drivers/spi/built-in.a
CC drivers/scsi/scsi_pm.o
AR drivers/firewire/built-in.a
CC drivers/base/map.o
CC lib/base64.o
CC drivers/acpi/acpica/rslist.o
CC net/sunrpc/stats.o
CC [M] drivers/gpu/drm/xe/xe_device.o
CC [M] fs/cifs/smb2maperror.o
CC [M] drivers/gpu/drm/nouveau/nvif/mmu.o
CC net/bridge/br_sysfs_br.o
CC [M] drivers/gpu/drm/i915/i915_module.o
CC drivers/base/devres.o
CC [M] drivers/gpu/drm/xe/xe_dma_buf.o
CC [M] fs/cifs/smb2transport.o
CC net/ipv4/tcp_fastopen.o
CC drivers/net/phy/phy.o
CC lib/once.o
CC [M] drivers/gpu/drm/drm_auth.o
CC [M] drivers/gpu/drm/i915/i915_params.o
CC [M] drivers/gpu/drm/drm_blend.o
CC [M] drivers/gpu/drm/xe/xe_engine.o
CC net/ipv6/udp_offload.o
CC arch/x86/kernel/pvclock.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.o
CC fs/btrfs/ioctl.o
CC [M] drivers/gpu/drm/ast/ast_post.o
CC drivers/net/phy/phy-c45.o
CC drivers/acpi/acpica/rsmemory.o
CC net/sunrpc/sysctl.o
CC drivers/acpi/acpi_platform.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_object.o
CC [M] drivers/gpu/drm/drm_bridge.o
CC mm/swap_cgroup.o
CC drivers/scsi/scsi_bsg.o
CC lib/refcount.o
CC kernel/sys_ni.o
CC kernel/nsproxy.o
CC [M] net/bluetooth/ecdh_helper.o
CC [M] net/bluetooth/hci_request.o
CC drivers/acpi/acpica/rsmisc.o
CC lib/usercopy.o
CC [M] drivers/gpu/drm/xe/xe_exec.o
CC [M] drivers/gpu/drm/nouveau/nvif/outp.o
CC arch/x86/kernel/pcspeaker.o
CC fs/btrfs/locking.o
CC arch/x86/kernel/check.o
CC [M] drivers/gpu/drm/nouveau/nvif/timer.o
CC drivers/base/attribute_container.o
CC [M] drivers/gpu/drm/ast/ast_dp501.o
CC lib/errseq.o
CC drivers/ata/libata-eh.o
CC net/core/netprio_cgroup.o
CC [M] net/bluetooth/mgmt_util.o
CC [M] drivers/gpu/drm/nouveau/nvif/vmm.o
CC drivers/acpi/acpi_pnp.o
CC drivers/ata/libata-transport.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_gart.o
CC [M] drivers/gpu/drm/nouveau/nvif/user.o
CC [M] drivers/gpu/drm/nouveau/nvif/userc361.o
CC drivers/ata/libata-trace.o
CC lib/bucket_locks.o
LD [M] arch/x86/kvm/kvm.o
CC drivers/scsi/scsi_common.o
CC mm/hugetlb_cgroup.o
CC drivers/scsi/sd.o
UPD arch/x86/kvm/kvm-asm-offsets.h
AS [M] arch/x86/kvm/vmx/vmenter.o
CC kernel/notifier.o
CC net/ipv6/seg6.o
CC drivers/acpi/acpica/rsserial.o
CC drivers/acpi/acpica/rsutils.o
LD [M] arch/x86/kvm/kvm-intel.o
CC kernel/ksysfs.o
CC net/bridge/br_nf_core.o
CC net/ipv6/fib6_notifier.o
CC [M] drivers/gpu/drm/i915/i915_pci.o
CC [M] drivers/gpu/drm/i915/i915_scatterlist.o
CC mm/kmemleak.o
CC [M] drivers/gpu/drm/drm_cache.o
CC arch/x86/kernel/uprobes.o
CC drivers/base/transport_class.o
AR net/sunrpc/built-in.a
CC kernel/cred.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.o
CC net/ipv4/tcp_rate.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_display.o
CC [M] drivers/gpu/drm/ast/ast_dp.o
CC drivers/net/phy/phy-core.o
CC drivers/net/mdio/acpi_mdio.o
CC arch/x86/kernel/perf_regs.o
CC drivers/net/mdio/fwnode_mdio.o
CC lib/generic-radix-tree.o
CC [M] drivers/gpu/drm/xe/xe_execlist.o
CC arch/x86/kernel/tracepoint.o
CC [M] fs/cifs/smb2misc.o
CC drivers/scsi/sg.o
CC drivers/acpi/acpica/rsxface.o
CC lib/string_helpers.o
CC fs/btrfs/orphan.o
CC drivers/ata/libata-sata.o
CC fs/btrfs/export.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/client.o
CC net/core/dst_cache.o
CC drivers/base/topology.o
CC drivers/base/container.o
CC arch/x86/kernel/itmt.o
CC arch/x86/kernel/umip.o
CC arch/x86/kernel/unwind_orc.o
AR drivers/nvme/host/built-in.a
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/engine.o
CC drivers/ata/libata-sff.o
AR drivers/nvme/built-in.a
CC [M] drivers/gpu/drm/nouveau/nvkm/core/enum.o
CC drivers/acpi/acpica/tbdata.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/event.o
CC drivers/base/property.o
CC [M] net/bluetooth/mgmt_config.o
CC fs/btrfs/tree-log.o
CC net/ipv6/rpl.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/firmware.o
CC [M] drivers/gpu/drm/xe/xe_force_wake.o
CC net/bridge/br_multicast.o
CC drivers/acpi/power.o
CC net/ipv6/ioam6.o
CC net/core/gro_cells.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_gem.o
LD [M] drivers/gpu/drm/ast/ast.o
CC drivers/base/cacheinfo.o
CC [M] drivers/gpu/drm/xe/xe_ggtt.o
CC net/bridge/br_mdb.o
AR drivers/net/mdio/built-in.a
CC arch/x86/kernel/callthunks.o
CC net/ipv6/sysctl_net_ipv6.o
CC [M] drivers/gpu/drm/i915/i915_suspend.o
CC kernel/reboot.o
CC fs/select.o
CC drivers/net/phy/phy_device.o
CC drivers/scsi/scsi_sysfs.o
CC arch/x86/kernel/mmconf-fam10h_64.o
CC lib/hexdump.o
CC fs/btrfs/free-space-cache.o
CC drivers/acpi/acpica/tbfadt.o
CC net/ipv4/tcp_recovery.o
CC fs/dcache.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ring.o
CC mm/page_isolation.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_cs.o
CC fs/inode.o
CC lib/kstrtox.o
CC kernel/async.o
CC [M] drivers/gpu/drm/drm_client.o
CC [M] drivers/gpu/drm/drm_client_modeset.o
CC kernel/range.o
CC [M] drivers/gpu/drm/xe/xe_gt.o
CC fs/btrfs/zlib.o
CC lib/debug_info.o
CC arch/x86/kernel/vsmp_64.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/gpuobj.o
CC drivers/ata/libata-pmp.o
CC drivers/acpi/event.o
CC drivers/acpi/acpica/tbfind.o
CC [M] net/bluetooth/hci_codec.o
CC drivers/base/swnode.o
CC [M] drivers/gpu/drm/i915/i915_switcheroo.o
CC drivers/ata/libata-acpi.o
CC [M] drivers/gpu/drm/i915/i915_sysfs.o
CC [M] net/bluetooth/eir.o
CC kernel/smpboot.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_bios.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/intr.o
CC drivers/acpi/acpica/tbinstal.o
CC drivers/acpi/acpica/tbprint.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.o
CC [M] fs/cifs/smb2pdu.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/ioctl.o
CC drivers/net/phy/linkmode.o
AR net/core/built-in.a
CC fs/btrfs/lzo.o
CC net/ipv6/xfrm6_policy.o
CC [M] drivers/gpu/drm/amd/amdgpu/atombios_dp.o
AR arch/x86/kernel/built-in.a
AR arch/x86/built-in.a
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_afmt.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_trace_points.o
CC drivers/net/phy/mdio_bus.o
CC drivers/ata/libata-pata-timings.o
CC [M] drivers/gpu/drm/drm_color_mgmt.o
CC drivers/acpi/evged.o
CC drivers/acpi/acpica/tbutils.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/memory.o
CC net/ipv4/tcp_ulp.o
CC mm/early_ioremap.o
CC net/ipv4/tcp_offload.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/mm.o
CC [M] fs/cifs/smb2inode.o
CC drivers/net/phy/mdio_device.o
CC fs/btrfs/zstd.o
CC kernel/ucount.o
CC net/bridge/br_multicast_eht.o
AR drivers/scsi/built-in.a
CC net/ipv4/tcp_plb.o
CC drivers/base/auxiliary.o
CC drivers/net/phy/swphy.o
CC drivers/net/phy/fixed_phy.o
CC [M] drivers/gpu/drm/xe/xe_gt_clock.o
CC [M] drivers/gpu/drm/i915/i915_utils.o
CC net/ipv6/xfrm6_state.o
CC net/bridge/br_vlan.o
CC [M] drivers/gpu/drm/drm_connector.o
CC drivers/ata/ahci.o
CC lib/iomap.o
CC [M] drivers/net/phy/phylink.o
CC lib/pci_iomap.o
CC drivers/acpi/acpica/tbxface.o
CC kernel/regset.o
AR drivers/cdrom/built-in.a
CC drivers/ata/libahci.o
AR drivers/auxdisplay/built-in.a
CC [M] net/bluetooth/hci_sync.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/object.o
CC net/bridge/br_vlan_tunnel.o
CC [M] drivers/gpu/drm/i915/intel_device_info.o
CC lib/iomap_copy.o
CC [M] drivers/gpu/drm/amd/amdgpu/atombios_encoders.o
CC drivers/ata/ata_piix.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_sa.o
CC [M] net/bluetooth/sco.o
CC drivers/acpi/acpica/tbxfload.o
CC net/bridge/br_vlan_options.o
CC mm/cma.o
CC drivers/base/devtmpfs.o
CC lib/devres.o
CC [M] drivers/gpu/drm/i915/intel_memory_region.o
CC net/ipv6/xfrm6_input.o
CC drivers/input/serio/serio.o
CC drivers/usb/common/common.o
CC kernel/kmod.o
CC drivers/input/keyboard/atkbd.o
CC drivers/rtc/lib.o
AR drivers/i2c/algos/built-in.a
CC [M] drivers/i2c/algos/i2c-algo-bit.o
CC drivers/input/serio/i8042.o
CC [M] drivers/gpu/drm/xe/xe_gt_debugfs.o
CC drivers/i2c/busses/i2c-designware-common.o
AR drivers/i3c/built-in.a
CC [M] drivers/gpu/drm/xe/xe_gt_mcr.o
CC drivers/i2c/busses/i2c-designware-master.o
CC drivers/acpi/sysfs.o
CC lib/check_signature.o
CC [M] drivers/gpu/drm/xe/xe_gt_pagefault.o
CC lib/interval_tree.o
CC drivers/usb/common/debug.o
CC drivers/acpi/acpica/tbxfroot.o
AR drivers/net/pcs/built-in.a
CC fs/btrfs/compression.o
CC net/ipv4/datagram.o
CC drivers/acpi/acpica/utaddress.o
AR drivers/net/ethernet/adi/built-in.a
AR drivers/net/ethernet/alacritech/built-in.a
AR drivers/net/ethernet/amazon/built-in.a
CC drivers/acpi/acpica/utalloc.o
CC net/ipv6/xfrm6_output.o
AR drivers/net/ethernet/aquantia/built-in.a
AR drivers/net/ethernet/asix/built-in.a
AR drivers/net/ethernet/cadence/built-in.a
AR drivers/net/ethernet/broadcom/built-in.a
CC [M] drivers/net/ethernet/broadcom/b44.o
CC lib/assoc_array.o
CC [M] drivers/net/ethernet/broadcom/bnx2.o
AR drivers/net/ethernet/cavium/common/built-in.a
CC [M] drivers/gpu/drm/nouveau/nvkm/core/oproxy.o
AR drivers/net/ethernet/cavium/thunder/built-in.a
CC drivers/rtc/class.o
AR drivers/net/ethernet/cavium/liquidio/built-in.a
AR drivers/net/ethernet/cavium/octeon/built-in.a
AR drivers/net/ethernet/cavium/built-in.a
AR drivers/net/ethernet/cortina/built-in.a
CC net/ipv4/raw.o
CC drivers/input/serio/libps2.o
CC [M] drivers/gpu/drm/amd/amdgpu/atombios_i2c.o
CC kernel/groups.o
AR drivers/usb/common/built-in.a
CC drivers/usb/core/usb.o
CC drivers/base/memory.o
CC [M] drivers/gpu/drm/drm_crtc.o
CC [M] drivers/gpu/drm/drm_displayid.o
CC net/bridge/br_mst.o
CC fs/attr.o
CC fs/btrfs/delayed-ref.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.o
CC [M] drivers/gpu/drm/i915/intel_pcode.o
CC drivers/acpi/acpica/utascii.o
CC drivers/acpi/acpica/utbuffer.o
CC [M] drivers/gpu/drm/drm_drv.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_vm.o
CC drivers/acpi/property.o
CC mm/secretmem.o
CC drivers/acpi/acpi_cmos_rtc.o
AR drivers/i2c/muxes/built-in.a
CC [M] drivers/i2c/muxes/i2c-mux-gpio.o
CC drivers/i2c/i2c-boardinfo.o
CC drivers/acpi/x86/apple.o
AR drivers/input/keyboard/built-in.a
AR drivers/input/mouse/built-in.a
CC drivers/input/input.o
CC drivers/i2c/busses/i2c-designware-platdrv.o
AR drivers/net/ethernet/engleder/built-in.a
CC drivers/rtc/interface.o
CC drivers/usb/core/hub.o
CC drivers/i2c/busses/i2c-designware-baytrail.o
CC drivers/rtc/nvmem.o
AR drivers/usb/phy/built-in.a
CC drivers/rtc/dev.o
CC [M] drivers/gpu/drm/drm_dumb_buffers.o
CC drivers/usb/core/hcd.o
CC drivers/usb/core/urb.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/option.o
AR drivers/input/serio/built-in.a
CC drivers/acpi/acpica/utcksum.o
CC [M] drivers/i2c/busses/i2c-scmi.o
CC drivers/input/input-compat.o
AR drivers/ata/built-in.a
CC drivers/acpi/acpica/utcopy.o
CC drivers/acpi/acpica/utexcep.o
CC kernel/kcmp.o
CC drivers/usb/host/pci-quirks.o
CC lib/list_debug.o
CC [M] drivers/gpu/drm/xe/xe_gt_sysfs.o
CC drivers/rtc/proc.o
CC drivers/base/module.o
CC drivers/usb/storage/scsiglue.o
CC drivers/acpi/x86/utils.o
CC drivers/usb/storage/protocol.o
CC net/ipv6/xfrm6_protocol.o
CC net/ipv6/netfilter.o
CC drivers/usb/serial/usb-serial.o
CC lib/debugobjects.o
CC [M] drivers/net/phy/aquantia_main.o
CC drivers/usb/serial/generic.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ib.o
CC [M] drivers/gpu/drm/i915/intel_pm.o
CC mm/userfaultfd.o
AR drivers/usb/misc/built-in.a
CC [M] drivers/usb/misc/ftdi-elan.o
CC drivers/usb/gadget/udc/core.o
CC [M] drivers/usb/class/usbtmc.o
AR drivers/usb/gadget/function/built-in.a
AR drivers/usb/gadget/legacy/built-in.a
CC [M] drivers/i2c/busses/i2c-ccgx-ucsi.o
CC drivers/acpi/acpica/utdebug.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_pll.o
CC [M] net/bridge/br_netfilter_hooks.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.o
CC drivers/input/input-mt.o
CC drivers/input/input-poller.o
CC [M] drivers/gpu/drm/drm_edid.o
CC drivers/usb/gadget/usbstring.o
CC drivers/base/pinctrl.o
CC drivers/usb/gadget/config.o
CC [M] drivers/i2c/busses/i2c-i801.o
CC drivers/usb/serial/bus.o
CC [M] net/bridge/br_netfilter_ipv6.o
CC mm/memremap.o
CC drivers/rtc/sysfs.o
CC kernel/freezer.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/ramht.o
CC [M] drivers/gpu/drm/xe/xe_gt_tlb_invalidation.o
CC kernel/stacktrace.o
CC drivers/acpi/x86/s2idle.o
CC net/ipv4/udp.o
CC drivers/acpi/acpica/utdecode.o
CC net/ipv4/udplite.o
CC drivers/usb/storage/transport.o
CC fs/btrfs/relocation.o
CC drivers/usb/host/ehci-hcd.o
CC drivers/base/platform-msi.o
CC [M] drivers/net/ethernet/broadcom/cnic.o
AR net/bridge/built-in.a
CC drivers/usb/gadget/epautoconf.o
CC drivers/usb/gadget/composite.o
CC [M] drivers/net/phy/aquantia_hwmon.o
CC kernel/dma.o
CC drivers/acpi/acpica/utdelete.o
CC net/ipv4/udp_offload.o
CC drivers/input/ff-core.o
CC drivers/usb/host/ehci-pci.o
CC lib/bitrev.o
CC drivers/usb/host/ohci-hcd.o
CC drivers/usb/host/ohci-pci.o
CC drivers/rtc/rtc-mc146818-lib.o
CC drivers/rtc/rtc-cmos.o
CC drivers/usb/gadget/functions.o
CC kernel/smp.o
CC [M] drivers/net/phy/ax88796b.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.o
CC net/ipv6/fib6_rules.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/subdev.o
CC drivers/usb/serial/console.o
CC drivers/base/physical_location.o
CC [M] fs/cifs/smb2file.o
CC drivers/usb/gadget/configfs.o
CC kernel/uid16.o
CC lib/crc16.o
CC mm/hmm.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/uevent.o
AR drivers/net/usb/built-in.a
CC [M] drivers/net/usb/pegasus.o
CC mm/memfd.o
CC [M] drivers/gpu/drm/xe/xe_gt_topology.o
CC drivers/acpi/acpica/uterror.o
CC mm/bootmem_info.o
CC [M] net/bluetooth/iso.o
CC drivers/usb/gadget/udc/trace.o
CC drivers/usb/gadget/u_f.o
AR drivers/net/ethernet/ezchip/built-in.a
CC drivers/input/touchscreen.o
CC [M] drivers/gpu/drm/nouveau/nvkm/nvfw/fw.o
CC [M] drivers/gpu/drm/i915/intel_region_ttm.o
CC lib/crc-t10dif.o
CC drivers/base/trace.o
CC [M] drivers/i2c/busses/i2c-isch.o
CC drivers/usb/storage/usb.o
CC drivers/usb/storage/initializers.o
CC fs/bad_inode.o
CC [M] fs/cifs/cifsacl.o
CC drivers/usb/host/uhci-hcd.o
CC drivers/usb/core/message.o
AR drivers/net/ethernet/fungible/built-in.a
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_sync.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.o
CC [M] drivers/gpu/drm/i915/intel_runtime_pm.o
CC [M] drivers/net/phy/bcm7xxx.o
CC drivers/acpi/acpica/uteval.o
CC [M] drivers/gpu/drm/drm_encoder.o
CC drivers/usb/serial/ftdi_sio.o
CC drivers/usb/serial/pl2303.o
CC net/ipv4/arp.o
AR drivers/rtc/built-in.a
CC [M] drivers/net/phy/bcm87xx.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.o
HOSTCC lib/gen_crc32table
CC [M] drivers/gpu/drm/xe/xe_guc.o
CC fs/file.o
CC drivers/input/ff-memless.o
CC fs/filesystems.o
CC [M] drivers/gpu/drm/nouveau/nvkm/nvfw/hs.o
CC lib/libcrc32c.o
CC kernel/kallsyms.o
CC drivers/acpi/acpica/utglobal.o
LD [M] net/bridge/br_netfilter.o
CC [M] drivers/gpu/drm/drm_file.o
CC drivers/usb/host/xhci.o
AR drivers/base/built-in.a
CC drivers/usb/storage/sierra_ms.o
CC [M] drivers/gpu/drm/nouveau/nvkm/nvfw/ls.o
CC fs/namespace.o
CC drivers/acpi/acpica/uthex.o
CC lib/xxhash.o
AR mm/built-in.a
CC net/ipv6/proc.o
CC kernel/acct.o
CC [M] drivers/i2c/busses/i2c-ismt.o
AR drivers/net/ethernet/huawei/built-in.a
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.o
CC kernel/crash_core.o
AR drivers/usb/gadget/udc/built-in.a
CC drivers/usb/storage/option_ms.o
CC [M] drivers/gpu/drm/drm_fourcc.o
AR drivers/media/i2c/built-in.a
AR drivers/media/tuners/built-in.a
AR drivers/ptp/built-in.a
CC [M] drivers/ptp/ptp_clock.o
AR drivers/media/rc/keymaps/built-in.a
CC [M] drivers/ptp/ptp_chardev.o
AR drivers/media/rc/built-in.a
CC [M] drivers/net/phy/bcm-phy-lib.o
CC [M] drivers/ptp/ptp_sysfs.o
CC [M] drivers/ptp/ptp_vclock.o
CC lib/genalloc.o
AR drivers/media/common/b2c2/built-in.a
AR drivers/usb/gadget/built-in.a
AR drivers/media/common/saa7146/built-in.a
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_virt.o
AR drivers/power/reset/built-in.a
AR drivers/media/common/siano/built-in.a
CC drivers/acpi/acpica/utids.o
AR drivers/media/common/v4l2-tpg/built-in.a
CC drivers/power/supply/power_supply_core.o
CC drivers/acpi/acpica/utinit.o
CC [M] drivers/net/usb/rtl8150.o
AR drivers/media/common/videobuf2/built-in.a
AR drivers/media/common/built-in.a
AR drivers/media/platform/allegro-dvt/built-in.a
AR drivers/media/platform/amlogic/meson-ge2d/built-in.a
AR drivers/media/platform/amlogic/built-in.a
AR drivers/media/platform/amphion/built-in.a
AR drivers/media/platform/aspeed/built-in.a
AR drivers/media/platform/atmel/built-in.a
AR drivers/media/platform/cadence/built-in.a
AR drivers/media/platform/chips-media/built-in.a
AR drivers/media/platform/intel/built-in.a
CC [M] drivers/gpu/drm/i915/intel_sbi.o
CC [M] drivers/gpu/drm/i915/intel_step.o
CC [M] drivers/net/phy/broadcom.o
AR drivers/media/platform/marvell/built-in.a
AR drivers/media/platform/mediatek/jpeg/built-in.a
AR drivers/media/platform/microchip/built-in.a
CC [M] drivers/net/ethernet/broadcom/tg3.o
AR drivers/media/platform/mediatek/mdp/built-in.a
AR drivers/media/platform/mediatek/vcodec/built-in.a
CC drivers/input/vivaldi-fmap.o
AR drivers/media/platform/mediatek/vpu/built-in.a
CC drivers/acpi/debugfs.o
AR drivers/media/platform/mediatek/mdp3/built-in.a
CC [M] drivers/gpu/drm/drm_framebuffer.o
AR drivers/media/platform/mediatek/built-in.a
CC drivers/input/input-leds.o
CC fs/btrfs/delayed-inode.o
AR drivers/media/platform/nvidia/tegra-vde/built-in.a
AR drivers/media/platform/nvidia/built-in.a
AR drivers/media/platform/nxp/dw100/built-in.a
AR drivers/media/platform/nxp/imx-jpeg/built-in.a
CC fs/btrfs/scrub.o
AR drivers/media/platform/nxp/built-in.a
AR drivers/media/platform/qcom/camss/built-in.a
AR drivers/media/platform/qcom/venus/built-in.a
AR drivers/media/platform/qcom/built-in.a
CC [M] drivers/gpu/drm/i915/intel_uncore.o
AR drivers/media/platform/renesas/rcar-vin/built-in.a
AR drivers/media/platform/renesas/rzg2l-cru/built-in.a
CC drivers/usb/core/driver.o
AR drivers/media/platform/renesas/vsp1/built-in.a
CC [M] drivers/gpu/drm/nouveau/nvkm/nvfw/acr.o
AR drivers/media/platform/renesas/built-in.a
CC [M] net/bluetooth/a2mp.o
CC fs/seq_file.o
AR drivers/usb/serial/built-in.a
CC [M] net/bluetooth/amp.o
CC drivers/acpi/acpica/utlock.o
AR drivers/media/platform/rockchip/rga/built-in.a
AR drivers/media/platform/rockchip/rkisp1/built-in.a
CC [M] drivers/i2c/busses/i2c-piix4.o
AR drivers/media/platform/rockchip/built-in.a
CC drivers/power/supply/power_supply_sysfs.o
CC drivers/usb/storage/usual-tables.o
AR drivers/media/platform/samsung/exynos-gsc/built-in.a
CC [M] drivers/gpu/drm/xe/xe_guc_ads.o
AR drivers/media/platform/samsung/exynos4-is/built-in.a
AR drivers/media/platform/samsung/s3c-camif/built-in.a
AR drivers/media/platform/samsung/s5p-g2d/built-in.a
CC drivers/power/supply/power_supply_leds.o
AR drivers/media/platform/samsung/s5p-jpeg/built-in.a
AR drivers/media/platform/samsung/s5p-mfc/built-in.a
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.o
AR drivers/media/platform/samsung/built-in.a
AR drivers/media/platform/st/sti/bdisp/built-in.a
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_vf_error.o
AR drivers/media/platform/st/sti/c8sectpfe/built-in.a
AR drivers/media/platform/st/sti/delta/built-in.a
CC kernel/compat.o
AR drivers/media/platform/st/sti/hva/built-in.a
AR drivers/media/platform/st/stm32/built-in.a
CC net/ipv6/syncookies.o
AR drivers/media/platform/st/built-in.a
AR drivers/media/platform/sunxi/sun4i-csi/built-in.a
CC net/ipv6/mip6.o
AR drivers/media/platform/sunxi/sun6i-csi/built-in.a
AR drivers/media/platform/sunxi/sun6i-mipi-csi2/built-in.a
AR drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/built-in.a
CC lib/percpu_counter.o
AR drivers/media/platform/sunxi/sun8i-di/built-in.a
AR drivers/media/platform/sunxi/sun8i-rotate/built-in.a
AR drivers/media/platform/sunxi/built-in.a
CC [M] drivers/gpu/drm/i915/intel_wakeref.o
CC [M] drivers/net/usb/r8152.o
AR drivers/media/platform/ti/am437x/built-in.a
CC [M] drivers/i2c/busses/i2c-designware-pcidrv.o
CC [M] drivers/ptp/ptp_kvm_x86.o
CC [M] drivers/net/phy/lxt.o
AR drivers/media/platform/ti/cal/built-in.a
CC [M] drivers/net/phy/realtek.o
AR drivers/media/platform/ti/vpe/built-in.a
CC drivers/input/mousedev.o
AR drivers/media/platform/ti/davinci/built-in.a
AR drivers/media/platform/ti/omap/built-in.a
AR drivers/media/platform/ti/omap3isp/built-in.a
AR drivers/media/platform/ti/built-in.a
CC net/ipv6/addrconf_core.o
AR drivers/media/platform/verisilicon/built-in.a
CC drivers/acpi/acpica/utmath.o
AR drivers/media/platform/via/built-in.a
AR drivers/media/platform/xilinx/built-in.a
AR drivers/media/platform/built-in.a
CC [M] fs/cifs/fs_context.o
AR drivers/media/pci/ttpci/built-in.a
CC drivers/power/supply/power_supply_hwmon.o
AR drivers/media/pci/b2c2/built-in.a
AR drivers/media/pci/pluto2/built-in.a
CC lib/fault-inject.o
AR drivers/media/pci/dm1105/built-in.a
AR drivers/media/pci/pt1/built-in.a
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_sched.o
CC net/ipv4/icmp.o
AR drivers/media/pci/pt3/built-in.a
AR drivers/media/pci/mantis/built-in.a
AR drivers/usb/storage/built-in.a
CC drivers/acpi/acpica/utmisc.o
AR drivers/media/pci/ngene/built-in.a
AR drivers/media/pci/ddbridge/built-in.a
CC drivers/input/evdev.o
CC drivers/acpi/acpica/utmutex.o
CC drivers/acpi/acpica/utnonansi.o
AR drivers/media/pci/saa7146/built-in.a
CC net/ipv6/exthdrs_core.o
CC [M] drivers/gpu/drm/i915/vlv_sideband.o
AR drivers/media/pci/smipcie/built-in.a
AR drivers/media/pci/netup_unidvb/built-in.a
AR drivers/media/pci/intel/ipu3/built-in.a
AR drivers/media/pci/intel/built-in.a
CC [M] drivers/net/phy/smsc.o
AR drivers/media/pci/built-in.a
AR drivers/media/usb/b2c2/built-in.a
AR drivers/media/usb/dvb-usb/built-in.a
AR drivers/media/usb/dvb-usb-v2/built-in.a
CC net/ipv4/devinet.o
AR drivers/media/usb/s2255/built-in.a
CC [M] drivers/net/ipvlan/ipvlan_core.o
AR drivers/media/usb/siano/built-in.a
AR drivers/media/usb/ttusb-budget/built-in.a
CC [M] drivers/net/ipvlan/ipvlan_main.o
AR drivers/media/usb/ttusb-dec/built-in.a
CC [M] drivers/net/ipvlan/ipvlan_l3s.o
AR drivers/media/usb/built-in.a
CC drivers/usb/core/config.o
CC drivers/usb/core/file.o
AR drivers/media/mmc/siano/built-in.a
AR drivers/media/mmc/built-in.a
AR drivers/media/firewire/built-in.a
CC [M] drivers/gpu/drm/i915/vlv_suspend.o
AR drivers/media/spi/built-in.a
AR drivers/media/test-drivers/built-in.a
AR drivers/media/built-in.a
CC fs/xattr.o
CC [M] drivers/gpu/drm/drm_gem.o
CC [M] drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.o
CC [M] drivers/gpu/drm/drm_ioctl.o
CC kernel/utsname.o
CC [M] drivers/ptp/ptp_kvm_common.o
CC drivers/hwmon/hwmon.o
AR drivers/power/supply/built-in.a
AR drivers/thermal/broadcom/built-in.a
AR drivers/power/built-in.a
CC drivers/acpi/acpica/utobject.o
AR drivers/thermal/samsung/built-in.a
CC drivers/usb/core/buffer.o
CC drivers/thermal/intel/intel_tcc.o
CC lib/syscall.o
CC kernel/user_namespace.o
CC [M] drivers/hwmon/acpi_power_meter.o
CC net/ipv6/ip6_checksum.o
CC drivers/thermal/intel/therm_throt.o
LD [M] drivers/i2c/busses/i2c-designware-pci.o
CC [M] drivers/thermal/intel/x86_pkg_temp_thermal.o
AR drivers/i2c/busses/built-in.a
CC net/ipv6/ip6_icmp.o
CC drivers/i2c/i2c-core-base.o
CC net/ipv6/output_core.o
CC [M] drivers/gpu/drm/xe/xe_guc_ct.o
CC drivers/acpi/acpica/utosi.o
CC lib/dynamic_debug.o
CC drivers/i2c/i2c-core-smbus.o
CC [M] net/bluetooth/hci_debugfs.o
LD [M] drivers/ptp/ptp.o
CC drivers/usb/host/xhci-mem.o
LD [M] drivers/net/phy/aquantia.o
CC [M] drivers/hwmon/coretemp.o
CC fs/libfs.o
CC fs/fs-writeback.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.o
CC [M] drivers/gpu/drm/i915/soc/intel_dram.o
AR drivers/net/phy/built-in.a
CC drivers/acpi/acpica/utownerid.o
CC net/ipv6/protocol.o
CC [M] drivers/net/usb/asix_devices.o
CC drivers/usb/core/sysfs.o
LD [M] drivers/ptp/ptp_kvm.o
AR drivers/input/built-in.a
CC net/ipv4/af_inet.o
CC drivers/i2c/i2c-core-acpi.o
CC drivers/i2c/i2c-core-slave.o
CC drivers/acpi/acpica/utpredef.o
CC [M] drivers/gpu/drm/drm_lease.o
CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/base.o
CC [M] drivers/gpu/drm/drm_managed.o
CC drivers/usb/host/xhci-ext-caps.o
CC kernel/pid_namespace.o
CC net/ipv4/igmp.o
CC drivers/watchdog/watchdog_core.o
CC drivers/watchdog/watchdog_dev.o
CC [M] drivers/md/persistent-data/dm-array.o
CC [M] drivers/thermal/intel/intel_menlow.o
CC drivers/usb/core/endpoint.o
CC drivers/md/md.o
CC [M] drivers/gpu/drm/i915/soc/intel_gmch.o
CC drivers/opp/core.o
CC fs/btrfs/backref.o
CC drivers/acpi/acpica/utresdecode.o
CC drivers/opp/cpu.o
CC drivers/opp/debugfs.o
LD [M] drivers/net/ipvlan/ipvlan.o
CC net/ipv6/ip6_offload.o
CC drivers/usb/host/xhci-ring.o
CC drivers/md/md-bitmap.o
CC drivers/cpufreq/cpufreq.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ids.o
AR drivers/hwmon/built-in.a
CC fs/btrfs/ulist.o
CC [M] drivers/gpu/drm/i915/soc/intel_pch.o
CC net/ipv4/fib_frontend.o
CC drivers/md/md-autodetect.o
CC [M] fs/cifs/dns_resolve.o
CC drivers/usb/host/xhci-hub.o
CC drivers/acpi/acpica/utresrc.o
CC drivers/i2c/i2c-dev.o
CC [M] drivers/net/vxlan/vxlan_core.o
CC [M] drivers/i2c/i2c-smbus.o
CC [M] drivers/gpu/drm/i915/i915_memcpy.o
CC drivers/usb/core/devio.o
CC [M] drivers/net/vxlan/vxlan_multicast.o
AR drivers/thermal/intel/built-in.a
CC [M] drivers/i2c/i2c-mux.o
CC [M] drivers/gpu/drm/xe/xe_guc_debugfs.o
CC fs/pnode.o
CC [M] drivers/gpu/drm/drm_mm.o
CC [M] drivers/net/vxlan/vxlan_vnifilter.o
AR drivers/thermal/st/built-in.a
UPD kernel/config_data
CC kernel/stop_machine.o
AR drivers/thermal/qcom/built-in.a
AR drivers/thermal/tegra/built-in.a
AR drivers/thermal/mediatek/built-in.a
CC drivers/thermal/thermal_core.o
CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/cmdq.o
CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/fw.o
CC drivers/usb/host/xhci-dbg.o
CC [M] drivers/md/persistent-data/dm-bitset.o
CC drivers/acpi/acpica/utstate.o
CC lib/errname.o
CC [M] drivers/md/persistent-data/dm-block-manager.o
CC drivers/watchdog/softdog.o
LD [M] net/bluetooth/bluetooth.o
CC [M] drivers/net/usb/asix_common.o
CC lib/nlattr.o
CC drivers/net/loopback.o
CC drivers/acpi/acpica/utstring.o
CC drivers/usb/host/xhci-trace.o
CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/msgq.o
CC net/ipv4/fib_semantics.o
CC drivers/md/dm-uevent.o
CC net/ipv6/tcpv6_offload.o
CC [M] drivers/md/persistent-data/dm-space-map-common.o
CC drivers/acpi/acpica/utstrsuppt.o
AR drivers/watchdog/built-in.a
CC drivers/acpi/acpi_lpat.o
CC [M] drivers/gpu/drm/xe/xe_guc_hwconfig.o
CC [M] drivers/gpu/drm/xe/xe_guc_log.o
ASN.1 fs/cifs/cifs_spnego_negtokeninit.asn1.[ch]
CC [M] fs/cifs/smb1ops.o
CC [M] drivers/gpu/drm/i915/i915_mm.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.o
CC drivers/acpi/acpi_lpit.o
CC fs/splice.o
CC [M] drivers/gpu/drm/i915/i915_sw_fence.o
CC net/ipv6/exthdrs_offload.o
CC [M] drivers/gpu/drm/i915/i915_sw_fence_work.o
CC [M] drivers/md/persistent-data/dm-space-map-disk.o
AR drivers/i2c/built-in.a
CC kernel/kprobes.o
CC net/ipv6/inet6_hashtables.o
AR drivers/opp/built-in.a
CC net/ipv4/fib_trie.o
CC drivers/cpuidle/governors/menu.o
CC drivers/cpuidle/cpuidle.o
CC net/ipv6/mcast_snoop.o
CC [M] drivers/gpu/drm/drm_mode_config.o
CC [M] drivers/gpu/drm/drm_mode_object.o
CC drivers/acpi/acpica/utstrtoul64.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.o
CC drivers/md/dm.o
CC [M] net/ipv6/ip6_udp_tunnel.o
CC drivers/mmc/core/core.o
CC drivers/mmc/host/sdhci.o
CC drivers/md/dm-table.o
CC drivers/mmc/core/bus.o
CC drivers/mmc/core/host.o
CC lib/checksum.o
CC drivers/mmc/core/mmc.o
CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/qmgr.o
CC drivers/cpufreq/freq_table.o
CC fs/btrfs/qgroup.o
CC [M] drivers/gpu/drm/xe/xe_guc_pc.o
CC drivers/cpuidle/governors/haltpoll.o
CC drivers/acpi/acpica/utxface.o
CC [M] drivers/md/persistent-data/dm-space-map-metadata.o
CC drivers/cpufreq/cpufreq_performance.o
CC drivers/thermal/thermal_sysfs.o
CC [M] drivers/gpu/drm/i915/i915_syncmap.o
CC lib/cpu_rmap.o
CC [M] drivers/md/persistent-data/dm-transaction-manager.o
CC [M] drivers/net/ethernet/intel/e1000/e1000_main.o
CC [M] drivers/net/ethernet/intel/e1000e/82571.o
CC [M] drivers/net/ethernet/intel/igb/igb_main.o
CC [M] drivers/net/ethernet/intel/igc/igc_main.o
CC [M] drivers/net/ethernet/intel/igb/igb_ethtool.o
CC drivers/cpuidle/driver.o
CC drivers/acpi/acpica/utxfinit.o
CC drivers/cpufreq/cpufreq_ondemand.o
CC lib/dynamic_queue_limits.o
CC drivers/md/dm-target.o
CC [M] drivers/gpu/drm/drm_modes.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.o
CC lib/glob.o
AR drivers/net/ethernet/i825xx/built-in.a
CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/v1.o
CC drivers/acpi/acpica/utxferror.o
CC drivers/mmc/core/mmc_ops.o
CC drivers/usb/core/notify.o
CC fs/btrfs/send.o
CC drivers/cpuidle/governor.o
CC [M] drivers/gpu/drm/drm_modeset_lock.o
CC drivers/cpufreq/cpufreq_governor.o
AR drivers/ufs/built-in.a
CC drivers/mmc/core/sd.o
AR net/ipv6/built-in.a
AR drivers/leds/trigger/built-in.a
AR drivers/firmware/arm_ffa/built-in.a
CC [M] drivers/leds/trigger/ledtrig-audio.o
AR drivers/firmware/arm_scmi/built-in.a
CC drivers/mmc/core/sd_ops.o
AR drivers/firmware/broadcom/built-in.a
AR drivers/firmware/cirrus/built-in.a
AR drivers/cpuidle/governors/built-in.a
CC [M] fs/cifs/cifssmb.o
AR drivers/firmware/meson/built-in.a
CC drivers/firmware/efi/efi-bgrt.o
CC drivers/mmc/core/sdio.o
CC lib/strncpy_from_user.o
CC [M] drivers/gpu/drm/i915/i915_user_extensions.o
AR drivers/leds/blink/built-in.a
CC [M] drivers/gpu/drm/i915/i915_ioc32.o
CC drivers/thermal/thermal_trip.o
CC [M] drivers/md/persistent-data/dm-btree.o
AR drivers/leds/simple/built-in.a
CC [M] drivers/md/persistent-data/dm-btree-remove.o
CC drivers/thermal/thermal_helpers.o
CC drivers/firmware/efi/libstub/efi-stub-helper.o
CC [M] drivers/md/persistent-data/dm-btree-spine.o
CC drivers/acpi/acpica/utxfmutex.o
CC [M] drivers/gpu/drm/xe/xe_guc_submit.o
CC drivers/cpuidle/sysfs.o
CC [M] drivers/gpu/drm/i915/i915_debugfs.o
CC [M] drivers/gpu/drm/i915/i915_debugfs_params.o
CC kernel/hung_task.o
CC drivers/leds/led-core.o
CC kernel/watchdog.o
CC drivers/usb/core/generic.o
CC [M] drivers/net/usb/ax88172a.o
CC [M] drivers/gpu/drm/i915/display/intel_display_debugfs.o
AR drivers/firmware/imx/built-in.a
CC drivers/cpufreq/cpufreq_governor_attr_set.o
CC drivers/usb/host/xhci-debugfs.o
AR drivers/firmware/psci/built-in.a
CC drivers/usb/host/xhci-pci.o
CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/gm200.o
CC [M] drivers/net/ethernet/intel/igb/e1000_82575.o
CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/gp102.o
CC lib/strnlen_user.o
CC drivers/leds/led-class.o
AR drivers/acpi/acpica/built-in.a
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.o
CC fs/btrfs/dev-replace.o
CC drivers/acpi/prmt.o
CC drivers/thermal/thermal_hwmon.o
CC fs/btrfs/raid56.o
CC [M] fs/cifs/cifs_spnego_negtokeninit.asn1.o
CC drivers/acpi/acpi_pcc.o
CC fs/btrfs/uuid-tree.o
CC [M] drivers/net/ethernet/intel/e1000e/ich8lan.o
CC drivers/cpufreq/acpi-cpufreq.o
CC drivers/firmware/efi/libstub/gop.o
CC drivers/cpuidle/poll_state.o
AR drivers/crypto/stm32/built-in.a
CC drivers/cpufreq/intel_pstate.o
CC drivers/clocksource/acpi_pm.o
AR drivers/crypto/xilinx/built-in.a
AR drivers/crypto/hisilicon/built-in.a
AR drivers/crypto/keembay/built-in.a
AR drivers/crypto/built-in.a
CC drivers/md/dm-linear.o
CC drivers/md/dm-stripe.o
CC drivers/mmc/core/sdio_ops.o
CC drivers/clocksource/i8253.o
CC drivers/usb/core/quirks.o
CC lib/net_utils.o
CC drivers/cpuidle/cpuidle-haltpoll.o
CC drivers/mmc/host/sdhci-pci-core.o
CC [M] drivers/gpu/drm/drm_plane.o
CC drivers/hid/usbhid/hid-core.o
CC drivers/leds/led-triggers.o
CC drivers/thermal/gov_fair_share.o
AR drivers/staging/media/built-in.a
AR drivers/staging/built-in.a
CC [M] drivers/gpu/drm/i915/display/intel_pipe_crc.o
CC kernel/watchdog_hld.o
CC drivers/hid/hid-core.o
AR drivers/platform/x86/amd/built-in.a
CC net/ipv4/fib_notifier.o
CC drivers/platform/x86/intel/pmc/core.o
CC [M] drivers/net/usb/ax88179_178a.o
LD [M] drivers/md/persistent-data/dm-persistent-data.o
CC drivers/usb/core/devices.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_csa.o
CC [M] drivers/platform/x86/intel/pmt/class.o
CC drivers/acpi/ac.o
CC [M] drivers/platform/x86/intel/pmt/telemetry.o
AR drivers/clocksource/built-in.a
AR drivers/firmware/smccc/built-in.a
CC [M] drivers/gpu/drm/drm_prime.o
AR drivers/usb/host/built-in.a
AR drivers/cpuidle/built-in.a
CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/ga100.o
CC drivers/platform/x86/intel/pmc/spt.o
CC [M] drivers/net/usb/cdc_ether.o
CC [M] drivers/net/usb/cdc_eem.o
CC drivers/firmware/efi/libstub/secureboot.o
AR drivers/firmware/tegra/built-in.a
CC drivers/mmc/core/sdio_bus.o
CC drivers/mmc/core/sdio_cis.o
CC drivers/thermal/gov_step_wise.o
CC drivers/thermal/gov_user_space.o
CC lib/sg_pool.o
CC [M] drivers/net/ethernet/intel/igb/e1000_mac.o
CC [M] drivers/gpu/drm/i915/i915_pmu.o
CC fs/sync.o
LD [M] drivers/net/vxlan/vxlan.o
CC drivers/net/netconsole.o
CC fs/btrfs/props.o
CC [M] drivers/gpu/drm/drm_print.o
CC kernel/seccomp.o
AR drivers/leds/built-in.a
CC drivers/md/dm-ioctl.o
CC drivers/acpi/button.o
CC drivers/md/dm-io.o
CC drivers/platform/x86/intel/turbo_max_3.o
CC [M] drivers/net/ethernet/intel/e1000e/80003es2lan.o
CC [M] drivers/platform/x86/intel/pmt/crashlog.o
CC drivers/hid/usbhid/hiddev.o
CC drivers/usb/core/phy.o
CC fs/btrfs/free-space-tree.o
CC net/ipv4/inet_fragment.o
AR drivers/thermal/built-in.a
CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/ga102.o
CC drivers/firmware/efi/libstub/tpm.o
CC drivers/platform/x86/p2sb.o
CC fs/btrfs/tree-checker.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ras.o
CC lib/stackdepot.o
CC [M] drivers/gpu/drm/i915/gt/gen2_engine_cs.o
CC [M] drivers/gpu/drm/xe/xe_hw_engine.o
CC [M] drivers/gpu/drm/i915/gt/gen6_engine_cs.o
CC drivers/hid/hid-input.o
CC drivers/mailbox/mailbox.o
CC drivers/mmc/host/sdhci-pci-o2micro.o
CC [M] drivers/gpu/drm/i915/gt/gen6_ppgtt.o
CC drivers/platform/x86/pmc_atom.o
CC drivers/mmc/core/sdio_io.o
CC drivers/platform/x86/intel/pmc/cnp.o
CC drivers/platform/x86/intel/pmc/icl.o
CC [M] drivers/gpu/drm/drm_property.o
CC fs/utimes.o
CC [M] drivers/net/ethernet/intel/igb/e1000_nvm.o
CC fs/d_path.o
CC [M] drivers/net/usb/smsc75xx.o
CC [M] drivers/net/ethernet/intel/e1000/e1000_hw.o
CC fs/stack.o
LD [M] drivers/platform/x86/intel/pmt/pmt_class.o
LD [M] drivers/platform/x86/intel/pmt/pmt_telemetry.o
LD [M] drivers/platform/x86/intel/pmt/pmt_crashlog.o
CC drivers/acpi/fan_core.o
CC lib/ucs2_string.o
CC drivers/usb/core/port.o
CC [M] drivers/gpu/drm/xe/xe_hw_fence.o
AR drivers/cpufreq/built-in.a
CC drivers/md/dm-kcopyd.o
CC [M] drivers/net/dummy.o
CC [M] drivers/net/usb/smsc95xx.o
CC drivers/firmware/efi/libstub/file.o
CC [M] drivers/net/usb/mcs7830.o
CC drivers/platform/x86/intel/pmc/tgl.o
CC [M] drivers/platform/x86/wmi.o
AR drivers/net/ethernet/microsoft/built-in.a
CC drivers/mailbox/pcc.o
AR drivers/net/ethernet/litex/built-in.a
CC drivers/devfreq/devfreq.o
CC drivers/powercap/powercap_sys.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.o
AR drivers/net/ethernet/microchip/built-in.a
CC [M] drivers/platform/x86/wmi-bmof.o
CC [M] drivers/net/usb/usbnet.o
CC [M] drivers/gpu/drm/i915/gt/gen7_renderclear.o
CC [M] drivers/devfreq/governor_simpleondemand.o
AR drivers/net/ethernet/mscc/built-in.a
CC drivers/usb/core/hcd-pci.o
CC lib/sbitmap.o
AR drivers/hid/usbhid/built-in.a
CC drivers/hid/hid-quirks.o
CC drivers/hid/hid-debug.o
CC drivers/mmc/core/sdio_irq.o
CC [M] drivers/gpu/drm/drm_pt_walk.o
CC [M] drivers/net/ethernet/intel/e1000e/mac.o
CC [M] drivers/gpu/drm/drm_syncobj.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/lsfw.o
CC [M] fs/cifs/asn1.o
CC drivers/acpi/fan_attr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm200.o
CC drivers/mmc/host/sdhci-pci-arasan.o
CC [M] drivers/gpu/drm/xe/xe_huc.o
CC [M] drivers/devfreq/governor_performance.o
CC drivers/platform/x86/intel/pmc/adl.o
CC [M] drivers/net/usb/cdc_ncm.o
CC [M] drivers/net/ethernet/intel/igc/igc_mac.o
CC [M] drivers/gpu/drm/i915/gt/gen8_engine_cs.o
CC [M] drivers/platform/x86/intel/vsec.o
CC drivers/md/dm-sysfs.o
CC drivers/firmware/efi/libstub/mem.o
CC net/ipv4/ping.o
AR drivers/mailbox/built-in.a
CC [M] drivers/net/macvlan.o
AR drivers/firmware/xilinx/built-in.a
CC kernel/relay.o
CC [M] drivers/platform/x86/mxm-wmi.o
AR drivers/platform/surface/built-in.a
CC [M] drivers/net/mii.o
CC drivers/firmware/efi/libstub/random.o
CC [M] drivers/gpu/drm/xe/xe_huc_debugfs.o
CC [M] drivers/gpu/drm/xe/xe_irq.o
CC drivers/firmware/efi/efi.o
CC drivers/powercap/intel_rapl_common.o
AR drivers/net/ethernet/neterion/built-in.a
CC [M] drivers/net/usb/r8153_ecm.o
AR drivers/net/ethernet/netronome/built-in.a
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm20b.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp102.o
CC drivers/powercap/intel_rapl_msr.o
CC drivers/acpi/processor_driver.o
CC drivers/platform/x86/intel/pmc/mtl.o
CC drivers/mmc/core/slot-gpio.o
CC [M] drivers/gpu/drm/i915/gt/gen8_ppgtt.o
CC drivers/md/dm-stats.o
CC drivers/usb/core/usb-acpi.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp108.o
CC fs/btrfs/space-info.o
CC lib/group_cpus.o
CC drivers/firmware/dmi_scan.o
CC drivers/mmc/host/sdhci-pci-dwc-mshc.o
CC [M] drivers/net/ethernet/intel/igb/e1000_phy.o
CC [M] drivers/net/mdio.o
CC drivers/firmware/efi/vars.o
CC drivers/firmware/dmi-sysfs.o
CC [M] drivers/gpu/drm/xe/xe_lrc.o
CC fs/fs_struct.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/gv100.o
CC drivers/hid/hidraw.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.o
CC drivers/firmware/efi/libstub/randomalloc.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp10b.o
CC [M] drivers/gpu/drm/xe/xe_migrate.o
CC drivers/platform/x86/intel/pmc/pltdrv.o
AR drivers/devfreq/built-in.a
LD [M] fs/cifs/cifs.o
CC drivers/acpi/processor_thermal.o
AR drivers/perf/built-in.a
CC drivers/ras/ras.o
AR drivers/hwtracing/intel_th/built-in.a
CC [M] drivers/net/ethernet/intel/igc/igc_i225.o
CC drivers/android/binderfs.o
CC fs/statfs.o
CC drivers/mmc/core/regulator.o
CC [M] lib/asn1_decoder.o
CC drivers/ras/debugfs.o
CC [M] drivers/net/ethernet/intel/igc/igc_base.o
CC [M] drivers/net/ethernet/intel/e1000e/manage.o
CC [M] drivers/net/ethernet/intel/e1000e/nvm.o
AR drivers/usb/core/built-in.a
AR drivers/usb/built-in.a
CC drivers/mmc/host/sdhci-pci-gli.o
CC drivers/acpi/processor_idle.o
AR drivers/net/ethernet/ni/built-in.a
CC [M] drivers/net/ethernet/intel/e1000e/phy.o
CC net/ipv4/ip_tunnel_core.o
CC drivers/nvmem/core.o
CC [M] drivers/net/ethernet/intel/e1000e/param.o
CC [M] drivers/mtd/chips/chipreg.o
CC kernel/utsname_sysctl.o
AR drivers/net/ethernet/packetengines/built-in.a
CC drivers/hid/hid-generic.o
CC [M] drivers/uio/uio.o
CC drivers/firmware/efi/libstub/pci.o
CC [M] drivers/vfio/pci/vfio_pci_core.o
CC drivers/firmware/dmi-id.o
AR drivers/powercap/built-in.a
AR drivers/platform/x86/intel/pmc/built-in.a
CC [M] drivers/platform/x86/intel/rst.o
LD [M] drivers/platform/x86/intel/intel_vsec.o
CC drivers/firmware/memmap.o
CC [M] drivers/vfio/pci/vfio_pci_intrs.o
CC [M] drivers/net/tun.o
CC [M] drivers/bluetooth/btusb.o
CC [M] drivers/pps/pps.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/tu102.o
CC [M] drivers/bluetooth/btintel.o
CC [M] drivers/pps/kapi.o
CC [M] drivers/pps/sysfs.o
CC kernel/delayacct.o
CC [M] drivers/net/ethernet/intel/e1000/e1000_ethtool.o
CC net/ipv4/gre_offload.o
CC [M] drivers/bluetooth/btbcm.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/ga100.o
LD [M] drivers/net/usb/asix.o
GEN lib/oid_registry_data.c
CC fs/btrfs/block-rsv.o
CC [M] lib/oid_registry.o
CC drivers/mmc/host/sdhci-acpi.o
CC [M] drivers/platform/x86/intel_ips.o
CC drivers/mmc/core/debugfs.o
CC net/ipv4/metrics.o
CC [M] drivers/net/ethernet/intel/igc/igc_nvm.o
CC drivers/md/dm-rq.o
CC [M] drivers/mtd/mtdcore.o
CC drivers/android/binder.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.o
CC [M] drivers/net/ethernet/intel/igc/igc_phy.o
CC [M] drivers/dca/dca-core.o
CC [M] drivers/ssb/main.o
AR drivers/platform/x86/intel/built-in.a
LD [M] drivers/platform/x86/intel/intel-rst.o
CC [M] drivers/ssb/scan.o
CC [M] drivers/ssb/sprom.o
CC drivers/hid/hid-a4tech.o
CC drivers/firmware/efi/libstub/skip_spaces.o
CC [M] drivers/gpu/drm/i915/gt/intel_breadcrumbs.o
AR drivers/ras/built-in.a
CC drivers/firmware/efi/libstub/lib-cmdline.o
CC [M] drivers/net/veth.o
CC [M] drivers/dca/dca-sysfs.o
CC drivers/hid/hid-apple.o
CC [M] drivers/net/ethernet/intel/igb/e1000_mbx.o
CC drivers/firmware/efi/libstub/lib-ctype.o
AR lib/lib.a
CC [M] drivers/gpu/drm/drm_sysfs.o
CC [M] drivers/ssb/pci.o
GEN lib/crc32table.h
CC kernel/taskstats.o
LD [M] drivers/pps/pps_core.o
CC lib/crc32.o
CC drivers/firmware/efi/libstub/alignedmem.o
CC fs/fs_pin.o
CC [M] drivers/gpu/drm/xe/xe_mmio.o
CC fs/btrfs/delalloc-space.o
CC fs/btrfs/block-group.o
CC [M] drivers/gpu/drm/drm_trace_points.o
CC [M] drivers/gpu/drm/i915/gt/intel_context.o
AR drivers/nvmem/built-in.a
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.o
CC [M] drivers/vfio/pci/vfio_pci_rdwr.o
CC [M] drivers/vfio/pci/vfio_pci_config.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/ga102.o
CC drivers/mmc/core/block.o
CC drivers/acpi/processor_throttling.o
CC kernel/tsacct.o
CC [M] drivers/net/ethernet/intel/igc/igc_diag.o
CC fs/nsfs.o
CC [M] drivers/vhost/net.o
CC [M] drivers/vhost/vhost.o
LD [M] drivers/dca/dca.o
CC fs/fs_types.o
CC drivers/mmc/host/cqhci-core.o
CC drivers/firmware/efi/libstub/relocate.o
CC drivers/hid/hid-belkin.o
CC fs/fs_context.o
AR lib/built-in.a
CC drivers/hid/hid-cherry.o
CC drivers/hid/hid-chicony.o
CC kernel/tracepoint.o
CC drivers/firmware/efi/reboot.o
CC drivers/md/dm-io-rewind.o
AR drivers/platform/x86/built-in.a
AR drivers/platform/built-in.a
CC drivers/md/dm-builtin.o
CC net/ipv4/netlink.o
CC [M] drivers/net/ethernet/intel/igc/igc_ethtool.o
CC [M] drivers/net/ethernet/intel/igb/e1000_i210.o
CC [M] drivers/gpu/drm/xe/xe_mocs.o
CC [M] drivers/net/ethernet/intel/e1000e/ethtool.o
CC [M] drivers/vhost/iotlb.o
CC [M] drivers/ssb/pcihost_wrapper.o
CC [M] drivers/md/dm-bufio.o
CC drivers/mmc/core/queue.o
CC fs/fs_parser.o
CC drivers/firmware/efi/memattr.o
CC [M] drivers/mmc/host/sdhci-pltfm.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.o
CC fs/fsopen.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_umc.o
CC kernel/latencytop.o
CC kernel/irq_work.o
CC kernel/static_call.o
CC [M] drivers/gpu/drm/i915/gt/intel_context_sseu.o
CC drivers/firmware/efi/libstub/printk.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.o
CC [M] drivers/vfio/vfio_main.o
CC [M] drivers/net/ethernet/intel/e1000/e1000_param.o
CC drivers/acpi/processor_perflib.o
CC [M] drivers/mtd/mtdsuper.o
CC drivers/firmware/efi/libstub/vsprintf.o
CC drivers/acpi/container.o
CC [M] drivers/bluetooth/btrtl.o
CC kernel/static_call_inline.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.o
CC [M] drivers/gpu/drm/i915/gt/intel_engine_cs.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bar/g84.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.o
CC drivers/hid/hid-cypress.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bar/gk20a.o
CC [M] drivers/net/ethernet/intel/igb/igb_ptp.o
CC [M] drivers/net/ethernet/intel/igb/igb_hwmon.o
CC fs/init.o
CC [M] drivers/ssb/driver_chipcommon.o
CC fs/kernel_read_file.o
CC [M] drivers/gpu/drm/xe/xe_module.o
CC [M] drivers/vfio/pci/vfio_pci.o
CC net/ipv4/nexthop.o
CC [M] drivers/vfio/group.o
CC [M] drivers/vfio/iova_bitmap.o
CC drivers/firmware/efi/tpm.o
CC [M] drivers/gpu/drm/xe/xe_pat.o
CC [M] drivers/mtd/mtdconcat.o
CC drivers/firmware/efi/libstub/x86-stub.o
CC fs/mnt_idmapping.o
CC [M] drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.o
CC drivers/acpi/thermal.o
CC drivers/android/binder_alloc.o
AR drivers/mmc/host/built-in.a
LD [M] drivers/vhost/vhost_iotlb.o
CC fs/remap_range.o
STUBCPY drivers/firmware/efi/libstub/alignedmem.stub.o
STUBCPY drivers/firmware/efi/libstub/efi-stub-helper.stub.o
CC kernel/user-return-notifier.o
CC [M] drivers/ssb/driver_chipcommon_pmu.o
CC [M] drivers/net/ethernet/intel/igc/igc_ptp.o
CC [M] drivers/mtd/mtdpart.o
CC drivers/firmware/efi/memmap.o
STUBCPY drivers/firmware/efi/libstub/file.stub.o
CC [M] drivers/gpu/drm/i915/gt/intel_engine_heartbeat.o
STUBCPY drivers/firmware/efi/libstub/gop.stub.o
CC drivers/firmware/efi/esrt.o
CC drivers/firmware/efi/efi-pstore.o
CC [M] drivers/mtd/mtdchar.o
CC fs/buffer.o
CC drivers/hid/hid-ezkey.o
CC kernel/padata.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bar/gm107.o
CC drivers/acpi/acpi_memhotplug.o
CC [M] drivers/gpu/drm/xe/xe_pci.o
CC drivers/acpi/ioapic.o
CC fs/btrfs/discard.o
AR drivers/mmc/core/built-in.a
AR drivers/mmc/built-in.a
CC [M] drivers/vfio/container.o
STUBCPY drivers/firmware/efi/libstub/lib-cmdline.stub.o
CC drivers/hid/hid-kensington.o
CC [M] drivers/gpu/drm/i915/gt/intel_engine_pm.o
CC drivers/hid/hid-lg.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bar/gm20b.o
LD [M] drivers/vfio/pci/vfio-pci-core.o
LD [M] drivers/vfio/pci/vfio-pci.o
CC [M] drivers/gpu/drm/xe/xe_pcode.o
CC fs/mpage.o
STUBCPY drivers/firmware/efi/libstub/lib-ctype.stub.o
CC [M] drivers/vfio/virqfd.o
CC [M] drivers/vfio/vfio_iommu_type1.o
CC [M] drivers/md/dm-bio-prison-v1.o
LD [M] drivers/net/ethernet/intel/e1000/e1000.o
CC [M] drivers/net/ethernet/intel/igc/igc_dump.o
STUBCPY drivers/firmware/efi/libstub/mem.stub.o
LD [M] drivers/vhost/vhost_net.o
CC [M] drivers/ssb/driver_pcicore.o
CC drivers/acpi/battery.o
CC [M] drivers/gpu/drm/i915/gt/intel_engine_user.o
CC drivers/firmware/efi/cper.o
CC kernel/jump_label.o
CC [M] drivers/gpu/drm/xe/xe_pm.o
CC [M] drivers/gpu/drm/xe/xe_preempt_fence.o
CC [M] drivers/net/ethernet/intel/igbvf/vf.o
STUBCPY drivers/firmware/efi/libstub/pci.stub.o
STUBCPY drivers/firmware/efi/libstub/printk.stub.o
STUBCPY drivers/firmware/efi/libstub/random.stub.o
STUBCPY drivers/firmware/efi/libstub/randomalloc.stub.o
STUBCPY drivers/firmware/efi/libstub/relocate.stub.o
STUBCPY drivers/firmware/efi/libstub/secureboot.stub.o
STUBCPY drivers/firmware/efi/libstub/skip_spaces.stub.o
STUBCPY drivers/firmware/efi/libstub/tpm.stub.o
STUBCPY drivers/firmware/efi/libstub/vsprintf.stub.o
STUBCPY drivers/firmware/efi/libstub/x86-stub.stub.o
AR drivers/firmware/efi/libstub/lib.a
CC drivers/firmware/efi/cper_cxl.o
CC [M] drivers/gpu/drm/xe/xe_pt.o
CC kernel/context_tracking.o
CC fs/proc_namespace.o
CC fs/direct-io.o
AR drivers/net/ethernet/realtek/built-in.a
CC [M] drivers/net/ethernet/realtek/8139cp.o
CC fs/eventpoll.o
CC fs/anon_inodes.o
CC [M] drivers/net/ethernet/intel/e1000e/netdev.o
CC drivers/firmware/efi/runtime-wrappers.o
CC [M] drivers/net/ethernet/intel/igc/igc_tsn.o
CC [M] drivers/net/ethernet/realtek/8139too.o
CC [M] drivers/net/ethernet/intel/e1000e/ptp.o
CC drivers/hid/hid-lg-g15.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.o
CC [M] drivers/gpu/drm/xe/xe_query.o
CC [M] drivers/gpu/drm/xe/xe_reg_sr.o
CC [M] drivers/gpu/drm/xe/xe_reg_whitelist.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bar/tu102.o
LD [M] drivers/net/ethernet/intel/igb/igb.o
CC kernel/iomem.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_rap.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.o
CC kernel/rseq.o
CC fs/signalfd.o
CC [M] drivers/md/dm-bio-prison-v2.o
LD [M] drivers/ssb/ssb.o
CC drivers/hid/hid-microsoft.o
LD [M] drivers/mtd/mtd.o
CC net/ipv4/udp_tunnel_stub.o
AR drivers/net/ethernet/renesas/built-in.a
CC [M] drivers/net/ethernet/realtek/r8169_main.o
LD [M] drivers/vfio/vfio.o
CC fs/btrfs/reflink.o
CC [M] drivers/gpu/drm/drm_vblank.o
CC [M] drivers/gpu/drm/drm_vblank_work.o
CC fs/btrfs/subpage.o
CC net/ipv4/sysctl_net_ipv4.o
CC net/ipv4/proc.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.o
CC fs/timerfd.o
CC drivers/acpi/hed.o
CC drivers/hid/hid-monterey.o
CC drivers/acpi/bgrt.o
CC [M] drivers/gpu/drm/xe/xe_rtp.o
CC [M] drivers/net/ethernet/intel/igbvf/mbx.o
AR drivers/net/ethernet/sfc/built-in.a
AR drivers/net/ethernet/smsc/built-in.a
CC [M] drivers/net/ethernet/smsc/smsc9420.o
AR drivers/net/ethernet/socionext/built-in.a
CC drivers/firmware/efi/dev-path-parser.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/base.o
CC drivers/acpi/cppc_acpi.o
CC [M] drivers/gpu/drm/i915/gt/intel_execlists_submission.o
CC fs/btrfs/tree-mod-log.o
CC [M] drivers/gpu/drm/i915/gt/intel_ggtt.o
CC [M] drivers/net/ethernet/intel/igc/igc_xdp.o
CC [M] drivers/gpu/drm/i915/gt/intel_ggtt_fencing.o
CC [M] drivers/gpu/drm/xe/xe_ring_ops.o
CC [M] drivers/gpu/drm/xe/xe_sa.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.o
CC [M] drivers/gpu/drm/xe/xe_sched_job.o
CC net/ipv4/syncookies.o
GZIP kernel/config_data.gz
CC [M] drivers/md/dm-crypt.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_main.o
CC kernel/configs.o
CC [M] drivers/net/ethernet/intel/ixgbevf/vf.o
CC drivers/acpi/spcr.o
CC drivers/acpi/acpi_pad.o
AR drivers/net/ethernet/intel/built-in.a
CC [M] drivers/net/ethernet/intel/ixgb/ixgb_main.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_common.o
CC [M] drivers/net/ethernet/intel/ixgbevf/mbx.o
CC [M] drivers/net/ethernet/intel/ixgb/ixgb_hw.o
CC [M] drivers/net/ethernet/intel/ixgbevf/ethtool.o
AR drivers/hid/built-in.a
CC [M] drivers/net/ethernet/intel/e100.o
CC [M] drivers/net/ethernet/realtek/r8169_firmware.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_mca.o
CC [M] drivers/net/ethernet/intel/igbvf/ethtool.o
CC [M] drivers/md/dm-thin.o
CC drivers/firmware/efi/apple-properties.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.o
CC fs/eventfd.o
CC [M] drivers/net/ethernet/intel/ixgb/ixgb_ee.o
CC [M] drivers/net/ethernet/realtek/r8169_phy_config.o
AR kernel/built-in.a
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/bit.o
CC [M] drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.o
CC [M] drivers/net/ethernet/intel/ixgbevf/ipsec.o
AR drivers/net/ethernet/vertexcom/built-in.a
CC [M] drivers/gpu/drm/xe/xe_step.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/boost.o
AR drivers/android/built-in.a
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_lsdma.o
CC drivers/firmware/efi/earlycon.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/conn.o
LD [M] drivers/net/ethernet/intel/igc/igc.o
CC drivers/firmware/efi/cper-x86.o
CC net/ipv4/esp4.o
AR drivers/net/ethernet/wangxun/built-in.a
CC fs/userfaultfd.o
CC [M] drivers/gpu/drm/xe/xe_sync.o
CC net/ipv4/esp4_offload.o
CC [M] drivers/md/dm-thin-metadata.o
CC net/ipv4/netfilter.o
AR drivers/net/ethernet/xilinx/built-in.a
CC [M] drivers/net/ethernet/intel/ixgb/ixgb_ethtool.o
CC [M] drivers/gpu/drm/drm_vma_manager.o
CC [M] drivers/gpu/drm/xe/xe_trace.o
CC [M] drivers/gpu/drm/i915/gt/intel_gt.o
CC [M] drivers/acpi/acpi_video.o
CC [M] drivers/gpu/drm/xe/xe_ttm_sys_mgr.o
LD [M] drivers/md/dm-bio-prison.o
CC [M] drivers/net/ethernet/intel/ixgb/ixgb_param.o
CC fs/aio.o
CC [M] drivers/net/ethernet/intel/igbvf/netdev.o
CC fs/locks.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.o
CC fs/btrfs/extent-io-tree.o
CC [M] drivers/acpi/video_detect.o
AR drivers/net/ethernet/synopsys/built-in.a
CC net/ipv4/inet_diag.o
CC [M] drivers/gpu/drm/xe/xe_ttm_stolen_mgr.o
AR drivers/net/ethernet/pensando/built-in.a
CC net/ipv4/tcp_diag.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.o
CC [M] drivers/gpu/drm/xe/xe_ttm_vram_mgr.o
CC net/ipv4/udp_diag.o
CC [M] drivers/gpu/drm/xe/xe_tuning.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.o
CC [M] drivers/gpu/drm/xe/xe_uc.o
CC [M] drivers/gpu/drm/amd/amdgpu/cik.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/cstep.o
CC fs/btrfs/fs.o
AR drivers/firmware/efi/built-in.a
AR drivers/firmware/built-in.a
CC fs/btrfs/messages.o
CC [M] drivers/gpu/drm/xe/xe_uc_debugfs.o
CC [M] drivers/gpu/drm/drm_writeback.o
CC fs/binfmt_script.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.o
CC [M] drivers/gpu/drm/amd/amdgpu/cik_ih.o
CC fs/binfmt_elf.o
CC [M] drivers/gpu/drm/xe/xe_uc_fw.o
CC net/ipv4/tcp_cubic.o
CC net/ipv4/xfrm4_policy.o
CC [M] drivers/gpu/drm/xe/xe_vm.o
CC [M] drivers/gpu/drm/xe/xe_vm_madvise.o
CC [M] drivers/gpu/drm/xe/xe_wait_user_fence.o
CC fs/compat_binfmt_elf.o
AR drivers/acpi/built-in.a
AR drivers/md/built-in.a
CC [M] drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.o
CC fs/btrfs/bio.o
CC [M] drivers/gpu/drm/xe/xe_wa.o
CC [M] drivers/gpu/drm/xe/xe_wopcm.o
LD [M] drivers/net/ethernet/intel/ixgb/ixgb.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/disp.o
CC [M] drivers/gpu/drm/amd/amdgpu/dce_v8_0.o
CC [M] drivers/gpu/drm/xe/xe_display.o
CC net/ipv4/xfrm4_state.o
CC fs/mbcache.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v7_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/cik_sdma.o
LD [M] drivers/net/ethernet/realtek/r8169.o
CC [M] drivers/gpu/drm/amd/amdgpu/uvd_v4_2.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_82599.o
CC [M] drivers/gpu/drm/amd/amdgpu/vce_v2_0.o
CC fs/btrfs/lru_cache.o
CC fs/btrfs/acl.o
LD [M] drivers/acpi/video.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.o
CC net/ipv4/xfrm4_input.o
CC [M] drivers/gpu/drm/lib/drm_random.o
CC [M] drivers/gpu/drm/i915/gt/intel_gt_clock_utils.o
CC net/ipv4/xfrm4_output.o
CC fs/posix_acl.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_82598.o
CC [M] drivers/gpu/drm/xe/display/icl_dsi.o
CC [M] drivers/gpu/drm/amd/amdgpu/si.o
CC fs/coredump.o
CC [M] drivers/gpu/drm/drm_ioc32.o
LD [M] drivers/md/dm-thin-pool.o
CC [M] drivers/gpu/drm/drm_panel.o
CC [M] drivers/gpu/drm/drm_pci.o
CC [M] drivers/gpu/drm/drm_debugfs.o
CC [M] drivers/gpu/drm/xe/display/intel_atomic.o
CC [M] drivers/gpu/drm/xe/display/intel_atomic_plane.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/extdev.o
CC [M] drivers/gpu/drm/xe/display/intel_audio.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/fan.o
CC [M] drivers/gpu/drm/amd/amdgpu/gmc_v6_0.o
CC net/ipv4/xfrm4_protocol.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v6_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/si_ih.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_phy.o
CC [M] drivers/gpu/drm/amd/amdgpu/si_dma.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/gpio.o
CC [M] net/ipv4/ip_tunnel.o
CC [M] drivers/gpu/drm/i915/gt/intel_gt_debugfs.o
CC [M] net/ipv4/udp_tunnel_core.o
LD [M] drivers/net/ethernet/intel/igbvf/igbvf.o
CC [M] net/ipv4/udp_tunnel_nic.o
CC [M] drivers/gpu/drm/xe/display/intel_backlight.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/i2c.o
CC fs/drop_caches.o
CC [M] drivers/gpu/drm/i915/gt/intel_gt_engines_debugfs.o
CC [M] drivers/gpu/drm/amd/amdgpu/dce_v6_0.o
CC [M] drivers/gpu/drm/drm_debugfs_crc.o
CC [M] drivers/gpu/drm/drm_edid_load.o
CC [M] drivers/gpu/drm/amd/amdgpu/uvd_v3_1.o
CC [M] drivers/gpu/drm/drm_panel_orientation_quirks.o
LD [M] drivers/net/ethernet/intel/e1000e/e1000e.o
CC fs/fhandle.o
CC [M] drivers/gpu/drm/drm_buddy.o
CC [M] drivers/gpu/drm/amd/amdgpu/vi.o
CC [M] drivers/gpu/drm/amd/amdgpu/mxgpu_vi.o
CC [M] drivers/gpu/drm/amd/amdgpu/nbio_v6_1.o
CC [M] drivers/gpu/drm/amd/amdgpu/soc15.o
AR fs/btrfs/built-in.a
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.o
CC [M] drivers/gpu/drm/xe/display/intel_bios.o
CC [M] drivers/gpu/drm/i915/gt/intel_gt_irq.o
CC [M] drivers/gpu/drm/xe/display/intel_bw.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/iccsense.o
CC [M] drivers/gpu/drm/drm_gem_shmem_helper.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_x540.o
LD [M] drivers/net/ethernet/intel/ixgbevf/ixgbevf.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_x550.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/image.o
CC [M] drivers/gpu/drm/amd/amdgpu/emu_soc.o
CC [M] drivers/gpu/drm/amd/amdgpu/mxgpu_ai.o
CC [M] drivers/gpu/drm/amd/amdgpu/nbio_v7_0.o
CC [M] drivers/gpu/drm/drm_suballoc.o
CC [M] drivers/gpu/drm/drm_gem_ttm_helper.o
CC [M] drivers/gpu/drm/i915/gt/intel_gt_mcr.o
AR net/ipv4/built-in.a
CC [M] drivers/gpu/drm/i915/gt/intel_gt_pm.o
CC [M] drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.o
CC [M] drivers/gpu/drm/i915/gt/intel_gt_pm_irq.o
CC [M] drivers/gpu/drm/i915/gt/intel_gt_requests.o
CC [M] drivers/gpu/drm/i915/gt/intel_gt_sysfs.o
CC [M] drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.o
CC [M] drivers/gpu/drm/amd/amdgpu/vega10_reg_init.o
CC [M] drivers/gpu/drm/i915/gt/intel_gtt.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/mxm.o
CC [M] drivers/gpu/drm/i915/gt/intel_llc.o
AR fs/built-in.a
CC [M] drivers/gpu/drm/i915/gt/intel_lrc.o
CC [M] drivers/gpu/drm/i915/gt/intel_migrate.o
CC [M] drivers/gpu/drm/xe/display/intel_cdclk.o
CC [M] drivers/gpu/drm/amd/amdgpu/vega20_reg_init.o
CC [M] drivers/gpu/drm/drm_atomic_helper.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/npde.o
CC [M] drivers/gpu/drm/drm_atomic_state_helper.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/pcir.o
CC [M] drivers/gpu/drm/drm_bridge_connector.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_lib.o
CC [M] drivers/gpu/drm/amd/amdgpu/nbio_v7_4.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.o
CC [M] drivers/gpu/drm/drm_crtc_helper.o
LD [M] net/ipv4/udp_tunnel.o
CC [M] drivers/gpu/drm/drm_damage_helper.o
CC [M] drivers/gpu/drm/amd/amdgpu/nbio_v2_3.o
CC [M] drivers/gpu/drm/i915/gt/intel_mocs.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_xsk.o
CC [M] drivers/gpu/drm/i915/gt/intel_ppgtt.o
CC [M] drivers/gpu/drm/i915/gt/intel_rc6.o
CC [M] drivers/gpu/drm/xe/display/intel_color.o
CC [M] drivers/gpu/drm/i915/gt/intel_region_lmem.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.o
CC [M] drivers/gpu/drm/amd/amdgpu/nv.o
CC [M] drivers/gpu/drm/i915/gt/intel_renderstate.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/pmu.o
CC [M] drivers/gpu/drm/i915/gt/intel_reset.o
AR net/built-in.a
CC [M] drivers/gpu/drm/i915/gt/intel_ring.o
CC [M] drivers/gpu/drm/amd/amdgpu/arct_reg_init.o
CC [M] drivers/gpu/drm/i915/gt/intel_ring_submission.o
CC [M] drivers/gpu/drm/i915/gt/intel_rps.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/power_budget.o
CC [M] drivers/gpu/drm/i915/gt/intel_sa_media.o
CC [M] drivers/gpu/drm/amd/amdgpu/mxgpu_nv.o
CC [M] drivers/gpu/drm/amd/amdgpu/nbio_v7_2.o
CC [M] drivers/gpu/drm/amd/amdgpu/hdp_v4_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/ramcfg.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/rammap.o
CC [M] drivers/gpu/drm/xe/display/intel_combo_phy.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_dcb.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.o
CC [M] drivers/gpu/drm/amd/amdgpu/hdp_v5_0.o
CC [M] drivers/gpu/drm/drm_encoder_slave.o
CC [M] drivers/gpu/drm/i915/gt/intel_sseu.o
CC [M] drivers/gpu/drm/drm_flip_work.o
CC [M] drivers/gpu/drm/amd/amdgpu/aldebaran_reg_init.o
CC [M] drivers/gpu/drm/drm_format_helper.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowacpi.o
CC [M] drivers/gpu/drm/i915/gt/intel_sseu_debugfs.o
CC [M] drivers/gpu/drm/amd/amdgpu/aldebaran.o
CC [M] drivers/gpu/drm/amd/amdgpu/soc21.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.o
CC [M] drivers/gpu/drm/i915/gt/intel_timeline.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowof.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_nl.o
CC [M] drivers/gpu/drm/amd/amdgpu/sienna_cichlid.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowpci.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowramin.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowrom.o
CC [M] drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.o
CC [M] drivers/gpu/drm/amd/amdgpu/nbio_v4_3.o
CC [M] drivers/gpu/drm/xe/display/intel_connector.o
CC [M] drivers/gpu/drm/drm_gem_atomic_helper.o
CC [M] drivers/gpu/drm/i915/gt/intel_wopcm.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_sysfs.o
CC [M] drivers/gpu/drm/i915/gt/intel_workarounds.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/therm.o
CC [M] drivers/gpu/drm/xe/display/intel_crtc_state_dump.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/vmap.o
CC [M] drivers/gpu/drm/amd/amdgpu/hdp_v6_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.o
CC [M] drivers/gpu/drm/amd/amdgpu/nbio_v7_7.o
CC [M] drivers/gpu/drm/amd/amdgpu/hdp_v5_2.o
CC [M] drivers/gpu/drm/i915/gt/shmem_utils.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_debugfs.o
CC [M] drivers/gpu/drm/amd/amdgpu/lsdma_v6_0.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.o
CC [M] drivers/gpu/drm/amd/amdgpu/df_v1_7.o
CC [M] drivers/gpu/drm/xe/display/intel_crtc.o
CC [M] drivers/gpu/drm/i915/gt/sysfs_engines.o
CC [M] drivers/gpu/drm/i915/gt/intel_ggtt_gmch.o
CC [M] drivers/gpu/drm/i915/gt/gen6_renderstate.o
CC [M] drivers/gpu/drm/xe/display/intel_cursor.o
CC [M] drivers/gpu/drm/i915/gt/gen7_renderstate.o
CC [M] drivers/gpu/drm/amd/amdgpu/df_v3_6.o
CC [M] drivers/gpu/drm/amd/amdgpu/df_v4_3.o
CC [M] drivers/gpu/drm/drm_gem_framebuffer_helper.o
CC [M] drivers/gpu/drm/amd/amdgpu/gmc_v7_0.o
CC [M] drivers/gpu/drm/i915/gt/gen8_renderstate.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/vpstate.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/xpio.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0203.o
CC [M] drivers/gpu/drm/i915/gt/gen9_renderstate.o
CC [M] drivers/gpu/drm/amd/amdgpu/gmc_v8_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0205.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_busy.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0209.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_clflush.o
CC [M] drivers/gpu/drm/drm_kms_helper_common.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/P0260.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_context.o
CC [M] drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/gmc_v9_0.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_create.o
CC [M] drivers/gpu/drm/xe/display/intel_ddi_buf_trans.o
CC [M] drivers/gpu/drm/drm_modeset_helper.o
CC [M] drivers/gpu/drm/drm_plane_helper.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_dmabuf.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_domain.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_execbuffer.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_internal.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_object.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_lmem.o
CC [M] drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_mman.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bus/base.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_pages.o
CC [M] drivers/gpu/drm/xe/display/intel_ddi.o
CC [M] drivers/gpu/drm/xe/display/intel_display.o
CC [M] drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_phys.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_pm.o
CC [M] drivers/gpu/drm/drm_probe_helper.o
CC [M] drivers/gpu/drm/drm_rect.o
CC [M] drivers/gpu/drm/xe/display/intel_display_debugfs.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.o
CC [M] drivers/gpu/drm/amd/amdgpu/gmc_v10_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.o
CC [M] drivers/gpu/drm/xe/display/intel_display_power.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bus/g94.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bus/gf100.o
CC [M] drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_region.o
CC [M] drivers/gpu/drm/drm_self_refresh_helper.o
CC [M] drivers/gpu/drm/drm_simple_kms_helper.o
CC [M] drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_shmem.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_shrinker.o
LD [M] drivers/net/ethernet/intel/ixgbe/ixgbe.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_stolen.o
CC [M] drivers/gpu/drm/xe/display/intel_display_power_map.o
CC [M] drivers/gpu/drm/bridge/panel.o
CC [M] drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.o
CC [M] drivers/gpu/drm/drm_fbdev_generic.o
AR drivers/net/ethernet/built-in.a
AR drivers/net/built-in.a
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.o
CC [M] drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.o
CC [M] drivers/gpu/drm/amd/amdgpu/gmc_v11_0.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_throttle.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_tiling.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_ttm.o
CC [M] drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_ttm_move.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/g84.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.o
CC [M] drivers/gpu/drm/amd/amdgpu/umc_v6_0.o
CC [M] drivers/gpu/drm/drm_fb_helper.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_userptr.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_wait.o
CC [M] drivers/gpu/drm/i915/gem/i915_gemfs.o
CC [M] drivers/gpu/drm/i915/i915_active.o
LD [M] drivers/gpu/drm/drm.o
LD [M] drivers/gpu/drm/drm_shmem_helper.o
LD [M] drivers/gpu/drm/drm_suballoc_helper.o
CC [M] drivers/gpu/drm/i915/i915_cmd_parser.o
CC [M] drivers/gpu/drm/amd/amdgpu/umc_v6_1.o
CC [M] drivers/gpu/drm/i915/i915_deps.o
LD [M] drivers/gpu/drm/drm_ttm_helper.o
CC [M] drivers/gpu/drm/i915/i915_gem_evict.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.o
CC [M] drivers/gpu/drm/i915/i915_gem_gtt.o
CC [M] drivers/gpu/drm/i915/i915_gem_ww.o
AR drivers/gpu/drm/built-in.a
CC [M] drivers/gpu/drm/i915/i915_gem.o
CC [M] drivers/gpu/drm/i915/i915_query.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.o
CC [M] drivers/gpu/drm/amd/amdgpu/umc_v6_7.o
CC [M] drivers/gpu/drm/i915/i915_request.o
CC [M] drivers/gpu/drm/amd/amdgpu/umc_v8_7.o
CC [M] drivers/gpu/drm/xe/display/intel_display_power_well.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.o
CC [M] drivers/gpu/drm/i915/i915_scheduler.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.o
CC [M] drivers/gpu/drm/i915/i915_trace_points.o
CC [M] drivers/gpu/drm/amd/amdgpu/umc_v8_10.o
CC [M] drivers/gpu/drm/xe/display/intel_display_trace.o
CC [M] drivers/gpu/drm/i915/i915_ttm_buddy_manager.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_irq.o
CC [M] drivers/gpu/drm/i915/i915_vma.o
CC [M] drivers/gpu/drm/i915/i915_vma_resource.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ih.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.o
CC [M] drivers/gpu/drm/amd/amdgpu/iceland_ih.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_ads.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.o
CC [M] drivers/gpu/drm/amd/amdgpu/tonga_ih.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_capture.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_ct.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_fw.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.o
CC [M] drivers/gpu/drm/amd/amdgpu/cz_ih.o
CC [M] drivers/gpu/drm/amd/amdgpu/vega10_ih.o
CC [M] drivers/gpu/drm/amd/amdgpu/vega20_ih.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_log.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.o
LD [M] drivers/gpu/drm/drm_kms_helper.o
CC [M] drivers/gpu/drm/amd/amdgpu/navi10_ih.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllgt215.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_rc.o
CC [M] drivers/gpu/drm/amd/amdgpu/ih_v6_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_psp.o
CC [M] drivers/gpu/drm/amd/amdgpu/psp_v3_1.o
CC [M] drivers/gpu/drm/amd/amdgpu/psp_v10_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/base.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv05.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.o
CC [M] drivers/gpu/drm/amd/amdgpu/psp_v11_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/psp_v11_0_8.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_submission.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv10.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_huc.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_huc_debugfs.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_huc_fw.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_uc.o
CC [M] drivers/gpu/drm/amd/amdgpu/psp_v12_0.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.o
CC [M] drivers/gpu/drm/amd/amdgpu/psp_v13_0.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_uc_fw.o
CC [M] drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv1a.o
CC [M] drivers/gpu/drm/i915/gt/intel_gsc.o
CC [M] drivers/gpu/drm/i915/i915_hwmon.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv20.o
CC [M] drivers/gpu/drm/i915/display/hsw_ips.o
CC [M] drivers/gpu/drm/amd/amdgpu/dce_v10_0.o
CC [M] drivers/gpu/drm/xe/display/intel_dkl_phy.o
CC [M] drivers/gpu/drm/amd/amdgpu/dce_v11_0.o
CC [M] drivers/gpu/drm/i915/display/intel_atomic.o
CC [M] drivers/gpu/drm/i915/display/intel_atomic_plane.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.o
CC [M] drivers/gpu/drm/xe/display/intel_dmc.o
CC [M] drivers/gpu/drm/i915/display/intel_audio.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g84.o
CC [M] drivers/gpu/drm/i915/display/intel_bios.o
CC [M] drivers/gpu/drm/i915/display/intel_bw.o
CC [M] drivers/gpu/drm/xe/display/intel_dp_aux_backlight.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g98.o
CC [M] drivers/gpu/drm/i915/display/intel_cdclk.o
CC [M] drivers/gpu/drm/i915/display/intel_color.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v8_0.o
CC [M] drivers/gpu/drm/i915/display/intel_combo_phy.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v9_0.o
CC [M] drivers/gpu/drm/xe/display/intel_dp_aux.o
CC [M] drivers/gpu/drm/i915/display/intel_connector.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/mcp89.o
CC [M] drivers/gpu/drm/xe/display/intel_dp.o
CC [M] drivers/gpu/drm/i915/display/intel_crtc.o
CC [M] drivers/gpu/drm/i915/display/intel_crtc_state_dump.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v9_4.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.o
CC [M] drivers/gpu/drm/i915/display/intel_cursor.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.o
CC [M] drivers/gpu/drm/i915/display/intel_display.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v10_0.o
CC [M] drivers/gpu/drm/i915/display/intel_display_power.o
CC [M] drivers/gpu/drm/i915/display/intel_display_power_map.o
CC [M] drivers/gpu/drm/xe/display/intel_dp_hdcp.o
CC [M] drivers/gpu/drm/amd/amdgpu/imu_v11_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v11_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm200.o
CC [M] drivers/gpu/drm/i915/display/intel_display_power_well.o
CC [M] drivers/gpu/drm/i915/display/intel_display_rps.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gv100.o
CC [M] drivers/gpu/drm/i915/display/intel_dmc.o
CC [M] drivers/gpu/drm/xe/display/intel_dp_link_training.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v11_0_3.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/tu102.o
CC [M] drivers/gpu/drm/i915/display/intel_dpio_phy.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ga100.o
CC [M] drivers/gpu/drm/xe/display/intel_dp_mst.o
CC [M] drivers/gpu/drm/i915/display/intel_dpll.o
CC [M] drivers/gpu/drm/xe/display/intel_dpll.o
CC [M] drivers/gpu/drm/xe/display/intel_dpll_mgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fault/base.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fault/user.o
CC [M] drivers/gpu/drm/amd/amdgpu/imu_v11_0_3.o
CC [M] drivers/gpu/drm/i915/display/intel_dpll_mgr.o
CC [M] drivers/gpu/drm/xe/display/intel_dpt.o
CC [M] drivers/gpu/drm/i915/display/intel_dpt.o
CC [M] drivers/gpu/drm/i915/display/intel_drrs.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fault/gp100.o
CC [M] drivers/gpu/drm/i915/display/intel_dsb.o
CC [M] drivers/gpu/drm/i915/display/intel_fb.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fault/gp10b.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.o
CC [M] drivers/gpu/drm/i915/display/intel_fb_pin.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.o
CC [M] drivers/gpu/drm/i915/display/intel_fbc.o
CC [M] drivers/gpu/drm/i915/display/intel_fdi.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fault/tu102.o
CC [M] drivers/gpu/drm/i915/display/intel_fifo_underrun.o
CC [M] drivers/gpu/drm/amd/amdgpu/sdma_v2_4.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.o
CC [M] drivers/gpu/drm/i915/display/intel_frontbuffer.o
CC [M] drivers/gpu/drm/amd/amdgpu/sdma_v3_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/sdma_v4_0.o
CC [M] drivers/gpu/drm/i915/display/intel_global_state.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.o
CC [M] drivers/gpu/drm/amd/amdgpu/sdma_v4_4.o
CC [M] drivers/gpu/drm/i915/display/intel_hdcp.o
CC [M] drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.o
CC [M] drivers/gpu/drm/xe/display/intel_drrs.o
CC [M] drivers/gpu/drm/i915/display/intel_hdcp_gsc.o
CC [M] drivers/gpu/drm/i915/display/intel_hotplug.o
CC [M] drivers/gpu/drm/amd/amdgpu/sdma_v5_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.o
CC [M] drivers/gpu/drm/xe/display/intel_dsb.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.o
CC [M] drivers/gpu/drm/xe/display/intel_dsi.o
CC [M] drivers/gpu/drm/xe/display/intel_dsi_dcs_backlight.o
CC [M] drivers/gpu/drm/i915/display/intel_hti.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.o
CC [M] drivers/gpu/drm/amd/amdgpu/sdma_v5_2.o
CC [M] drivers/gpu/drm/i915/display/intel_lpe_audio.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.o
CC [M] drivers/gpu/drm/i915/display/intel_modeset_verify.o
CC [M] drivers/gpu/drm/i915/display/intel_modeset_setup.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.o
CC [M] drivers/gpu/drm/amd/amdgpu/sdma_v6_0.o
CC [M] drivers/gpu/drm/i915/display/intel_overlay.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_mes.o
CC [M] drivers/gpu/drm/xe/display/intel_dsi_vbt.o
CC [M] drivers/gpu/drm/i915/display/intel_pch_display.o
CC [M] drivers/gpu/drm/amd/amdgpu/mes_v10_1.o
CC [M] drivers/gpu/drm/i915/display/intel_pch_refclk.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.o
CC [M] drivers/gpu/drm/i915/display/intel_plane_initial.o
CC [M] drivers/gpu/drm/amd/amdgpu/mes_v11_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.o
CC [M] drivers/gpu/drm/xe/display/intel_fb.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.o
CC [M] drivers/gpu/drm/xe/display/intel_fbc.o
CC [M] drivers/gpu/drm/xe/display/intel_fdi.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.o
CC [M] drivers/gpu/drm/i915/display/intel_psr.o
CC [M] drivers/gpu/drm/i915/display/intel_quirks.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/g84.o
CC [M] drivers/gpu/drm/xe/display/intel_fifo_underrun.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gt215.o
CC [M] drivers/gpu/drm/i915/display/intel_sprite.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp77.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp89.o
CC [M] drivers/gpu/drm/i915/display/intel_sprite_uapi.o
CC [M] drivers/gpu/drm/amd/amdgpu/uvd_v5_0.o
CC [M] drivers/gpu/drm/i915/display/intel_tc.o
CC [M] drivers/gpu/drm/xe/display/intel_frontbuffer.o
CC [M] drivers/gpu/drm/i915/display/intel_vblank.o
CC [M] drivers/gpu/drm/i915/display/intel_vga.o
CC [M] drivers/gpu/drm/amd/amdgpu/uvd_v6_0.o
CC [M] drivers/gpu/drm/i915/display/intel_wm.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf108.o
CC [M] drivers/gpu/drm/i915/display/i9xx_plane.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk104.o
CC [M] drivers/gpu/drm/amd/amdgpu/uvd_v7_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk110.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk20a.o
CC [M] drivers/gpu/drm/xe/display/intel_global_state.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm107.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm200.o
CC [M] drivers/gpu/drm/i915/display/i9xx_wm.o
CC [M] drivers/gpu/drm/i915/display/skl_scaler.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm20b.o
CC [M] drivers/gpu/drm/i915/display/skl_universal_plane.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp102.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp10b.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gv100.o
CC [M] drivers/gpu/drm/i915/display/skl_watermark.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_vce.o
CC [M] drivers/gpu/drm/amd/amdgpu/vce_v3_0.o
CC [M] drivers/gpu/drm/i915/display/intel_acpi.o
CC [M] drivers/gpu/drm/amd/amdgpu/vce_v4_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.o
CC [M] drivers/gpu/drm/i915/display/intel_opregion.o
CC [M] drivers/gpu/drm/xe/display/intel_gmbus.o
CC [M] drivers/gpu/drm/xe/display/intel_hdcp.o
CC [M] drivers/gpu/drm/xe/display/intel_hdmi.o
CC [M] drivers/gpu/drm/amd/amdgpu/vcn_sw_ring.o
CC [M] drivers/gpu/drm/xe/display/intel_hotplug.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/tu102.o
CC [M] drivers/gpu/drm/xe/display/intel_hti.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ga100.o
CC [M] drivers/gpu/drm/i915/display/intel_fbdev.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ga102.o
CC [M] drivers/gpu/drm/i915/display/dvo_ch7017.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.o
CC [M] drivers/gpu/drm/amd/amdgpu/vcn_v1_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv04.o
CC [M] drivers/gpu/drm/amd/amdgpu/vcn_v2_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv10.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.o
CC [M] drivers/gpu/drm/i915/display/dvo_ch7xxx.o
CC [M] drivers/gpu/drm/i915/display/dvo_ivch.o
CC [M] drivers/gpu/drm/amd/amdgpu/vcn_v2_5.o
CC [M] drivers/gpu/drm/i915/display/dvo_ns2501.o
CC [M] drivers/gpu/drm/xe/display/intel_lspcon.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv20.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.o
CC [M] drivers/gpu/drm/amd/amdgpu/vcn_v3_0.o
CC [M] drivers/gpu/drm/xe/display/intel_modeset_setup.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv41.o
CC [M] drivers/gpu/drm/i915/display/dvo_sil164.o
CC [M] drivers/gpu/drm/xe/display/intel_modeset_verify.o
CC [M] drivers/gpu/drm/xe/display/intel_panel.o
CC [M] drivers/gpu/drm/xe/display/intel_pipe_crc.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv44.o
CC [M] drivers/gpu/drm/amd/amdgpu/vcn_v4_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.o
CC [M] drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.o
CC [M] drivers/gpu/drm/i915/display/dvo_tfp410.o
CC [M] drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.o
CC [M] drivers/gpu/drm/i915/display/g4x_dp.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv49.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv4e.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.o
CC [M] drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.o
CC [M] drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.o
CC [M] drivers/gpu/drm/i915/display/g4x_hdmi.o
CC [M] drivers/gpu/drm/i915/display/icl_dsi.o
CC [M] drivers/gpu/drm/i915/display/intel_backlight.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.o
CC [M] drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.o
CC [M] drivers/gpu/drm/xe/display/intel_pps.o
CC [M] drivers/gpu/drm/i915/display/intel_crt.o
CC [M] drivers/gpu/drm/amd/amdgpu/athub_v1_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.o
CC [M] drivers/gpu/drm/amd/amdgpu/athub_v2_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.o
CC [M] drivers/gpu/drm/i915/display/intel_ddi.o
CC [M] drivers/gpu/drm/i915/display/intel_ddi_buf_trans.o
CC [M] drivers/gpu/drm/amd/amdgpu/athub_v2_1.o
CC [M] drivers/gpu/drm/i915/display/intel_display_trace.o
CC [M] drivers/gpu/drm/i915/display/intel_dkl_phy.o
CC [M] drivers/gpu/drm/i915/display/intel_dp.o
CC [M] drivers/gpu/drm/xe/display/intel_psr.o
CC [M] drivers/gpu/drm/i915/display/intel_dp_aux.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf108.o
CC [M] drivers/gpu/drm/xe/display/intel_qp_tables.o
CC [M] drivers/gpu/drm/i915/display/intel_dp_aux_backlight.o
CC [M] drivers/gpu/drm/xe/display/intel_quirks.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm107.o
CC [M] drivers/gpu/drm/amd/amdgpu/athub_v3_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/smuio_v9_0.o
CC [M] drivers/gpu/drm/xe/display/intel_snps_phy.o
CC [M] drivers/gpu/drm/xe/display/intel_tc.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm200.o
CC [M] drivers/gpu/drm/xe/display/intel_vblank.o
CC [M] drivers/gpu/drm/i915/display/intel_dp_hdcp.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgp100.o
CC [M] drivers/gpu/drm/amd/amdgpu/smuio_v11_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/smuio_v11_0_6.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramga102.o
CC [M] drivers/gpu/drm/amd/amdgpu/smuio_v13_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/smuio_v13_0_6.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_reset.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr2.o
CC [M] drivers/gpu/drm/amd/amdgpu/mca_v3_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.o
CC [M] drivers/gpu/drm/xe/display/intel_vdsc.o
CC [M] drivers/gpu/drm/i915/display/intel_dp_link_training.o
CC [M] drivers/gpu/drm/i915/display/intel_dp_mst.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_module.o
CC [M] drivers/gpu/drm/i915/display/intel_dsi.o
CC [M] drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.o
CC [M] drivers/gpu/drm/i915/display/intel_dsi_vbt.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr3.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.o
CC [M] drivers/gpu/drm/i915/display/intel_dvo.o
CC [M] drivers/gpu/drm/i915/display/intel_gmbus.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr5.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fuse/base.o
CC [M] drivers/gpu/drm/i915/display/intel_hdmi.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fuse/nv50.o
CC [M] drivers/gpu/drm/xe/display/intel_vga.o
CC [M] drivers/gpu/drm/i915/display/intel_lspcon.o
CC [M] drivers/gpu/drm/i915/display/intel_lvds.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gf100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gm107.o
CC [M] drivers/gpu/drm/xe/display/intel_vrr.o
CC [M] drivers/gpu/drm/i915/display/intel_panel.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device.o
CC [M] drivers/gpu/drm/i915/display/intel_pps.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_chardev.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv10.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_topology.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_pasid.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_doorbell.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_flat_memory.o
CC [M] drivers/gpu/drm/i915/display/intel_qp_tables.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_process.o
CC [M] drivers/gpu/drm/xe/display/intel_wm.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.o
CC [M] drivers/gpu/drm/i915/display/intel_sdvo.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gpio/g94.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gf119.o
CC [M] drivers/gpu/drm/xe/display/xe_fb_pin.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_queue.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gk104.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_cik.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gpio/ga102.o
CC [M] drivers/gpu/drm/i915/display/intel_snps_phy.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gsp/base.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gv100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_vi.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gsp/ga102.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv04.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv4e.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv50.o
CC [M] drivers/gpu/drm/i915/display/intel_tv.o
CC [M] drivers/gpu/drm/i915/display/intel_vdsc.o
CC [M] drivers/gpu/drm/i915/display/intel_vrr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_v9.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_v10.o
CC [M] drivers/gpu/drm/i915/display/vlv_dsi.o
CC [M] drivers/gpu/drm/i915/display/vlv_dsi_pll.o
CC [M] drivers/gpu/drm/xe/display/xe_hdcp_gsc.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_v11.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_kernel_queue.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_packet_manager.o
CC [M] drivers/gpu/drm/i915/i915_perf.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/g94.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf117.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf119.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk104.o
CC [M] drivers/gpu/drm/i915/pxp/intel_pxp.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk110.o
CC [M] drivers/gpu/drm/i915/pxp/intel_pxp_tee.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gm200.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_packet_manager_vi.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_packet_manager_v9.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_process_queue_manager.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/pad.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padnv04.o
CC [M] drivers/gpu/drm/xe/display/xe_plane_initial.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager.o
CC [M] drivers/gpu/drm/i915/pxp/intel_pxp_huc.o
CC [M] drivers/gpu/drm/xe/display/xe_display_rps.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager_cik.o
CC [M] drivers/gpu/drm/xe/display/skl_scaler.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager_vi.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padnv4e.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padnv50.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padg94.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager_v9.o
CC [M] drivers/gpu/drm/xe/display/skl_universal_plane.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager_v10.o
CC [M] drivers/gpu/drm/i915/pxp/intel_pxp_cmd.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager_v11.o
CC [M] drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_interrupt.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padgf119.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padgm200.o
CC [M] drivers/gpu/drm/i915/pxp/intel_pxp_irq.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/bus.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv04.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv4e.o
CC [M] drivers/gpu/drm/i915/pxp/intel_pxp_pm.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv50.o
CC [M] drivers/gpu/drm/xe/display/skl_watermark.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_events.o
CC [M] drivers/gpu/drm/i915/pxp/intel_pxp_session.o
CC [M] drivers/gpu/drm/xe/display/ext/i915_irq.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/cik_event_interrupt.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_int_process_v9.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_int_process_v11.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_smi_events.o
CC [M] drivers/gpu/drm/i915/i915_gpu_error.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_crat.o
CC [M] drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busgf119.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/bit.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_debugfs.o
CC [M] drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/aux.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_svm.o
CC [M] drivers/gpu/drm/i915/selftests/intel_scheduler_helpers.o
CC [M] drivers/gpu/drm/i915/selftests/i915_random.o
CC [M] drivers/gpu/drm/i915/selftests/i915_selftest.o
CC [M] drivers/gpu/drm/i915/selftests/igt_atomic.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_migrate.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.o
CC [M] drivers/gpu/drm/xe/display/ext/i9xx_wm.o
CC [M] drivers/gpu/drm/xe/display/ext/intel_device_info.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.o
CC [M] drivers/gpu/drm/i915/selftests/igt_flush_test.o
CC [M] drivers/gpu/drm/i915/selftests/igt_live_test.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgf119.o
CC [M] drivers/gpu/drm/xe/display/ext/intel_dram.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.o
CC [M] drivers/gpu/drm/i915/selftests/igt_mmap.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.o
CC [M] drivers/gpu/drm/i915/selftests/igt_reset.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/base.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/gf100.o
CC [M] drivers/gpu/drm/i915/selftests/igt_spinner.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.o
CC [M] drivers/gpu/drm/i915/selftests/librapl.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.o
CC [M] drivers/gpu/drm/i915/i915_vgpu.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.o
HDRTEST drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.o
CC [M] drivers/gpu/drm/xe/display/ext/intel_pch.o
CC [M] drivers/gpu/drm/xe/display/ext/intel_pm.o
HDRTEST drivers/gpu/drm/i915/display/intel_crtc_state_dump.h
HDRTEST drivers/gpu/drm/i915/display/hsw_ips.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/ltc/base.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.o
CC [M] drivers/gpu/drm/xe/display/intel_acpi.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.o
HDRTEST drivers/gpu/drm/i915/display/g4x_hdmi.h
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gk104.o
HDRTEST drivers/gpu/drm/i915/display/intel_hdcp_regs.h
HDRTEST drivers/gpu/drm/i915/display/intel_overlay.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm200.o
HDRTEST drivers/gpu/drm/i915/display/intel_display.h
HDRTEST drivers/gpu/drm/i915/display/intel_dmc.h
HDRTEST drivers/gpu/drm/i915/display/intel_vga.h
HDRTEST drivers/gpu/drm/i915/display/intel_audio.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp100.o
HDRTEST drivers/gpu/drm/i915/display/intel_lvds.h
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_job.o
CC [M] drivers/gpu/drm/xe/display/intel_opregion.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_acp.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp102.o
HDRTEST drivers/gpu/drm/i915/display/intel_modeset_setup.h
CC [M] drivers/gpu/drm/amd/amdgpu/../acp/acp_hw.o
HDRTEST drivers/gpu/drm/i915/display/intel_cdclk.h
HDRTEST drivers/gpu/drm/i915/display/intel_display_limits.h
HDRTEST drivers/gpu/drm/i915/display/intel_hotplug.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.o
HDRTEST drivers/gpu/drm/i915/display/intel_dkl_phy.h
HDRTEST drivers/gpu/drm/i915/display/intel_atomic.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/ltc/ga102.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.o
HDRTEST drivers/gpu/drm/i915/display/intel_dpll.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.o
HDRTEST drivers/gpu/drm/i915/display/vlv_dsi_pll_regs.h
CC [M] drivers/gpu/drm/xe/display/intel_fbdev.o
HDRTEST drivers/gpu/drm/i915/display/intel_dp_mst.h
HDRTEST drivers/gpu/drm/xe/abi/guc_klvs_abi.h
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ioc32.o
HDRTEST drivers/gpu/drm/xe/abi/guc_errors_abi.h
HDRTEST drivers/gpu/drm/i915/display/g4x_dp.h
HDRTEST drivers/gpu/drm/xe/abi/guc_actions_slpc_abi.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv11.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.o
HDRTEST drivers/gpu/drm/xe/abi/guc_communication_mmio_abi.h
HDRTEST drivers/gpu/drm/xe/abi/guc_actions_abi.h
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.o
HDRTEST drivers/gpu/drm/xe/abi/guc_communication_ctb_abi.h
HDRTEST drivers/gpu/drm/xe/abi/guc_messages_abi.h
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_vma_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/arcturus_ppt.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/vlv_sideband_reg.h
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_wakeref.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv17.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/sienna_cichlid_ppt.o
HDRTEST drivers/gpu/drm/i915/display/intel_tc.h
HDRTEST drivers/gpu/drm/i915/display/intel_frontbuffer.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv44.o
HDRTEST drivers/gpu/drm/i915/display/intel_dsi_vbt.h
HDRTEST drivers/gpu/drm/i915/display/intel_psr.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/vangogh_ppt.o
HDRTEST drivers/gpu/drm/i915/display/intel_crt.h
HDRTEST drivers/gpu/drm/i915/display/intel_opregion.h
HDRTEST drivers/gpu/drm/i915/display/intel_snps_phy_regs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/g84.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/g98.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_reg_defs.h
HDRTEST drivers/gpu/drm/i915/display/i9xx_wm.h
HDRTEST drivers/gpu/drm/i915/display/intel_global_state.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/cyan_skillfish_ppt.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_trace.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/smu_v11_0.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_reg.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu12/renoir_ppt.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/gt215.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_active_types.h
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_utils.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu12/smu_v12_0.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_config.h
HDRTEST drivers/gpu/drm/i915/display/intel_lpe_audio.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk104.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_vma.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk20a.o
HDRTEST drivers/gpu/drm/i915/display/intel_drrs.h
HDRTEST drivers/gpu/drm/i915/display/intel_display_rps.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp100.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/vlv_sideband.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp10b.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_mchbar_regs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/ga100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/aldebaran_ppt.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_debugfs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/yellow_carp_ppt.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/soc/intel_gmch.h
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_vgpu.h
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_fixed.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0_0_ppt.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_runtime_pm.h
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_pm_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_pci_config.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0_4_ppt.o
HDRTEST drivers/gpu/drm/xe/display/ext/i915_irq.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0_5_ppt.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/g84.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0_7_ppt.o
HDRTEST drivers/gpu/drm/xe/display/ext/intel_pch.h
HDRTEST drivers/gpu/drm/i915/display/intel_fbdev.h
HDRTEST drivers/gpu/drm/i915/display/intel_hdmi.h
HDRTEST drivers/gpu/drm/xe/display/ext/intel_pm.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0_6_ppt.o
HDRTEST drivers/gpu/drm/xe/display/ext/i9xx_wm.h
HDRTEST drivers/gpu/drm/i915/display/intel_fdi.h
HDRTEST drivers/gpu/drm/xe/display/ext/intel_dram.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/mcp77.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/amdgpu_smu.o
HDRTEST drivers/gpu/drm/i915/display/intel_fb.h
HDRTEST drivers/gpu/drm/xe/display/ext/intel_device_info.h
HDRTEST drivers/gpu/drm/i915/display/intel_qp_tables.h
HDRTEST drivers/gpu/drm/xe/display/xe_de.h
HDRTEST drivers/gpu/drm/xe/regs/xe_reg_defs.h
HDRTEST drivers/gpu/drm/xe/regs/xe_guc_regs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.o
HDRTEST drivers/gpu/drm/i915/display/intel_vdsc.h
HDRTEST drivers/gpu/drm/i915/display/intel_snps_phy.h
HDRTEST drivers/gpu/drm/xe/regs/xe_gt_regs.h
HDRTEST drivers/gpu/drm/xe/regs/xe_regs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gk104.o
HDRTEST drivers/gpu/drm/xe/regs/xe_gpu_commands.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu_cmn.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gk20a.o
HDRTEST drivers/gpu/drm/xe/regs/xe_lrc_layout.h
HDRTEST drivers/gpu/drm/xe/regs/xe_engine_regs.h
HDRTEST drivers/gpu/drm/i915/display/intel_display_core.h
HDRTEST drivers/gpu/drm/xe/tests/xe_test.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gm200.o
HDRTEST drivers/gpu/drm/i915/display/vlv_dsi_pll.h
HDRTEST drivers/gpu/drm/i915/display/intel_dvo_dev.h
HDRTEST drivers/gpu/drm/i915/display/intel_hdcp.h
HDRTEST drivers/gpu/drm/xe/tests/xe_pci_test.h
HDRTEST drivers/gpu/drm/i915/display/intel_sdvo_regs.h
HDRTEST drivers/gpu/drm/i915/display/intel_pch_refclk.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/smumgr.o
HDRTEST drivers/gpu/drm/i915/display/intel_display_trace.h
HDRTEST drivers/gpu/drm/i915/display/intel_display_power.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gm20b.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gp100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/smu8_smumgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/tonga_smumgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/fiji_smumgr.o
HDRTEST drivers/gpu/drm/xe/tests/xe_migrate_test.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/polaris10_smumgr.o
HDRTEST drivers/gpu/drm/xe/tests/xe_dma_buf_test.h
HDRTEST drivers/gpu/drm/xe/tests/xe_bo_test.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/iceland_smumgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/smu7_smumgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gp10b.o
HDRTEST drivers/gpu/drm/xe/xe_bb.h
HDRTEST drivers/gpu/drm/xe/xe_bb_types.h
HDRTEST drivers/gpu/drm/xe/xe_bo.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/vega10_smumgr.o
HDRTEST drivers/gpu/drm/xe/xe_bo_doc.h
HDRTEST drivers/gpu/drm/xe/xe_bo_evict.h
HDRTEST drivers/gpu/drm/i915/display/i9xx_plane.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gv100.o
HDRTEST drivers/gpu/drm/xe/xe_bo_types.h
HDRTEST drivers/gpu/drm/xe/xe_debugfs.h
HDRTEST drivers/gpu/drm/xe/xe_device.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/tu102.o
HDRTEST drivers/gpu/drm/i915/display/intel_dp_aux_backlight.h
HDRTEST drivers/gpu/drm/i915/display/intel_dpll_mgr.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/mem.o
HDRTEST drivers/gpu/drm/xe/xe_device_types.h
HDRTEST drivers/gpu/drm/xe/xe_display.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/smu10_smumgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memnv04.o
HDRTEST drivers/gpu/drm/xe/xe_dma_buf.h
HDRTEST drivers/gpu/drm/i915/display/vlv_dsi.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memnv50.o
HDRTEST drivers/gpu/drm/i915/display/intel_plane_initial.h
HDRTEST drivers/gpu/drm/i915/display/intel_fifo_underrun.h
HDRTEST drivers/gpu/drm/i915/display/intel_cursor.h
HDRTEST drivers/gpu/drm/i915/display/vlv_dsi_regs.h
HDRTEST drivers/gpu/drm/i915/display/skl_scaler.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/ci_smumgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/vega12_smumgr.o
HDRTEST drivers/gpu/drm/i915/display/intel_hti.h
HDRTEST drivers/gpu/drm/i915/display/icl_dsi_regs.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/vegam_smumgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memgf100.o
HDRTEST drivers/gpu/drm/i915/display/intel_atomic_plane.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/smu9_smumgr.o
HDRTEST drivers/gpu/drm/i915/display/skl_watermark.h
HDRTEST drivers/gpu/drm/i915/display/intel_fbc.h
HDRTEST drivers/gpu/drm/i915/display/intel_display_reg_defs.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/vega20_smumgr.o
HDRTEST drivers/gpu/drm/i915/display/intel_acpi.h
HDRTEST drivers/gpu/drm/i915/display/intel_connector.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/hwmgr.o
HDRTEST drivers/gpu/drm/i915/display/intel_dpt.h
HDRTEST drivers/gpu/drm/i915/display/intel_quirks.h
HDRTEST drivers/gpu/drm/i915/display/intel_dp_link_training.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/processpptables.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv04.o
HDRTEST drivers/gpu/drm/xe/xe_drv.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/hardwaremanager.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu8_hwmgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/pppcielanes.o
HDRTEST drivers/gpu/drm/xe/xe_engine.h
HDRTEST drivers/gpu/drm/xe/xe_engine_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/process_pptables_v1_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv41.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/ppatomctrl.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/ppatomfwctrl.o
HDRTEST drivers/gpu/drm/xe/xe_exec.h
HDRTEST drivers/gpu/drm/xe/xe_execlist.h
HDRTEST drivers/gpu/drm/xe/xe_execlist_types.h
HDRTEST drivers/gpu/drm/i915/display/intel_color.h
HDRTEST drivers/gpu/drm/xe/xe_force_wake.h
HDRTEST drivers/gpu/drm/i915/display/intel_crtc.h
HDRTEST drivers/gpu/drm/xe/xe_force_wake_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_hwmgr.o
HDRTEST drivers/gpu/drm/i915/display/intel_display_debugfs.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_powertune.o
HDRTEST drivers/gpu/drm/i915/display/intel_modeset_verify.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv44.o
HDRTEST drivers/gpu/drm/i915/display/intel_display_power_well.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.o
HDRTEST drivers/gpu/drm/xe/xe_ggtt.h
HDRTEST drivers/gpu/drm/xe/xe_ggtt_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_thermal.o
HDRTEST drivers/gpu/drm/xe/xe_gt.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmmcp77.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_clockpowergating.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_processpptables.o
HDRTEST drivers/gpu/drm/xe/xe_gt_clock.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.o
HDRTEST drivers/gpu/drm/xe/xe_gt_debugfs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgk104.o
HDRTEST drivers/gpu/drm/xe/xe_gt_mcr.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgk20a.o
HDRTEST drivers/gpu/drm/xe/xe_gt_pagefault.h
HDRTEST drivers/gpu/drm/xe/xe_gt_sysfs.h
HDRTEST drivers/gpu/drm/xe/xe_gt_sysfs_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_powertune.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_thermal.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm200.o
HDRTEST drivers/gpu/drm/i915/display/intel_wm.h
HDRTEST drivers/gpu/drm/i915/display/intel_pipe_crc.h
HDRTEST drivers/gpu/drm/i915/display/intel_audio_regs.h
HDRTEST drivers/gpu/drm/xe/xe_gt_tlb_invalidation.h
HDRTEST drivers/gpu/drm/i915/display/intel_panel.h
HDRTEST drivers/gpu/drm/i915/display/intel_sprite.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu10_hwmgr.o
HDRTEST drivers/gpu/drm/i915/display/intel_wm_types.h
HDRTEST drivers/gpu/drm/i915/display/intel_tv.h
HDRTEST drivers/gpu/drm/xe/xe_gt_tlb_invalidation_types.h
HDRTEST drivers/gpu/drm/xe/xe_gt_topology.h
HDRTEST drivers/gpu/drm/i915/display/intel_hti_regs.h
HDRTEST drivers/gpu/drm/xe/xe_gt_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm20b.o
HDRTEST drivers/gpu/drm/i915/display/intel_vrr.h
HDRTEST drivers/gpu/drm/i915/display/skl_universal_plane.h
HDRTEST drivers/gpu/drm/i915/display/intel_mg_phy_regs.h
HDRTEST drivers/gpu/drm/xe/xe_guc.h
HDRTEST drivers/gpu/drm/i915/display/intel_bw.h
HDRTEST drivers/gpu/drm/i915/display/intel_de.h
HDRTEST drivers/gpu/drm/i915/display/intel_lvds_regs.h
HDRTEST drivers/gpu/drm/xe/xe_guc_ads.h
HDRTEST drivers/gpu/drm/xe/xe_guc_ads_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/pp_psm.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega12_processpptables.o
HDRTEST drivers/gpu/drm/i915/display/intel_gmbus_regs.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega12_hwmgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.o
HDRTEST drivers/gpu/drm/xe/xe_guc_ct.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp10b.o
HDRTEST drivers/gpu/drm/xe/xe_guc_ct_types.h
HDRTEST drivers/gpu/drm/xe/xe_guc_debugfs.h
HDRTEST drivers/gpu/drm/xe/xe_guc_engine_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega12_thermal.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/pp_overdriver.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgv100.o
HDRTEST drivers/gpu/drm/xe/xe_guc_fwif.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmtu102.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu_helper.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega20_processpptables.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/umem.o
HDRTEST drivers/gpu/drm/xe/xe_guc_hwconfig.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega20_hwmgr.o
HDRTEST drivers/gpu/drm/xe/xe_guc_log.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega20_powertune.o
HDRTEST drivers/gpu/drm/xe/xe_guc_log_types.h
HDRTEST drivers/gpu/drm/xe/xe_guc_pc.h
HDRTEST drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.h
HDRTEST drivers/gpu/drm/xe/xe_guc_pc_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega20_thermal.o
HDRTEST drivers/gpu/drm/xe/xe_guc_submit.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/common_baco.o
HDRTEST drivers/gpu/drm/i915/display/intel_dvo.h
HDRTEST drivers/gpu/drm/xe/xe_guc_types.h
HDRTEST drivers/gpu/drm/xe/xe_huc.h
HDRTEST drivers/gpu/drm/xe/xe_huc_debugfs.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_baco.o
HDRTEST drivers/gpu/drm/xe/xe_huc_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.o
HDRTEST drivers/gpu/drm/xe/xe_hw_engine.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.o
HDRTEST drivers/gpu/drm/xe/xe_hw_engine_types.h
HDRTEST drivers/gpu/drm/xe/xe_hw_fence.h
HDRTEST drivers/gpu/drm/i915/display/intel_sdvo.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega20_baco.o
HDRTEST drivers/gpu/drm/i915/display/intel_dp_aux.h
HDRTEST drivers/gpu/drm/i915/display/intel_vdsc_regs.h
HDRTEST drivers/gpu/drm/i915/display/intel_combo_phy.h
HDRTEST drivers/gpu/drm/i915/display/intel_dvo_regs.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega12_baco.o
HDRTEST drivers/gpu/drm/i915/display/intel_gmbus.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu9_baco.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/tonga_baco.o
HDRTEST drivers/gpu/drm/i915/display/intel_hdcp_gsc.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/polaris_baco.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/fiji_baco.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mxm/mxms.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/ci_baco.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mxm/nv50.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_baco.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/agp.o
HDRTEST drivers/gpu/drm/xe/xe_hw_fence_types.h
HDRTEST drivers/gpu/drm/xe/xe_irq.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.o
HDRTEST drivers/gpu/drm/xe/xe_lrc.h
HDRTEST drivers/gpu/drm/xe/xe_lrc_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/amd_powerplay.o
HDRTEST drivers/gpu/drm/xe/xe_macros.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/legacy-dpm/legacy_dpm.o
HDRTEST drivers/gpu/drm/xe/xe_map.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/pcie.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/legacy-dpm/kv_dpm.o
HDRTEST drivers/gpu/drm/i915/display/intel_dsi.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/legacy-dpm/kv_smc.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv04.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/legacy-dpm/si_dpm.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv40.o
HDRTEST drivers/gpu/drm/i915/display/intel_dmc_regs.h
HDRTEST drivers/gpu/drm/xe/xe_migrate.h
HDRTEST drivers/gpu/drm/i915/display/intel_ddi.h
HDRTEST drivers/gpu/drm/xe/xe_migrate_doc.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv46.o
HDRTEST drivers/gpu/drm/i915/display/intel_dsb.h
HDRTEST drivers/gpu/drm/xe/xe_mmio.h
HDRTEST drivers/gpu/drm/xe/xe_mocs.h
HDRTEST drivers/gpu/drm/i915/display/intel_bios.h
HDRTEST drivers/gpu/drm/xe/xe_module.h
HDRTEST drivers/gpu/drm/i915/display/intel_pch_display.h
HDRTEST drivers/gpu/drm/xe/xe_pat.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv4c.o
HDRTEST drivers/gpu/drm/i915/display/intel_display_types.h
HDRTEST drivers/gpu/drm/xe/xe_pci.h
HDRTEST drivers/gpu/drm/i915/display/intel_backlight.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/legacy-dpm/si_smc.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/g84.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_pm.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm_internal.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_crtc.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/g92.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/g94.o
HDRTEST drivers/gpu/drm/i915/display/intel_vblank.h
HDRTEST drivers/gpu/drm/i915/display/intel_dp.h
HDRTEST drivers/gpu/drm/i915/display/intel_backlight_regs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf106.o
HDRTEST drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
HDRTEST drivers/gpu/drm/i915/display/intel_display_power_map.h
HDRTEST drivers/gpu/drm/xe/xe_pci_types.h
HDRTEST drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
HDRTEST drivers/gpu/drm/xe/xe_pcode.h
HDRTEST drivers/gpu/drm/i915/display/icl_dsi.h
HDRTEST drivers/gpu/drm/i915/display/intel_lspcon.h
HDRTEST drivers/gpu/drm/xe/xe_pcode_api.h
HDRTEST drivers/gpu/drm/i915/display/intel_dpio_phy.h
HDRTEST drivers/gpu/drm/xe/xe_platform_types.h
HDRTEST drivers/gpu/drm/xe/xe_pm.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_irq.o
HDRTEST drivers/gpu/drm/i915/display/intel_dp_hdcp.h
HDRTEST drivers/gpu/drm/xe/xe_preempt_fence.h
HDRTEST drivers/gpu/drm/i915/display/intel_fb_pin.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_mst_types.o
HDRTEST drivers/gpu/drm/xe/xe_preempt_fence_types.h
HDRTEST drivers/gpu/drm/xe/xe_pt.h
HDRTEST drivers/gpu/drm/i915/display/intel_pps.h
HDRTEST drivers/gpu/drm/i915/display/intel_sprite_uapi.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_color.o
HDRTEST drivers/gpu/drm/xe/xe_pt_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/dc_fpu.o
HDRTEST drivers/gpu/drm/xe/xe_query.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_services.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_ttm.h
HDRTEST drivers/gpu/drm/xe/xe_reg_sr.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_helpers.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_region.h
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_context_types.h
HDRTEST drivers/gpu/drm/xe/xe_reg_sr_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_pp_smu.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_psr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/gk104.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/gp100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_hdcp.o
HDRTEST drivers/gpu/drm/xe/xe_reg_whitelist.h
HDRTEST drivers/gpu/drm/xe/xe_res_cursor.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_lmem.h
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_mman.h
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_object_types.h
HDRTEST drivers/gpu/drm/xe/xe_ring_ops.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_context.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_crc.o
HDRTEST drivers/gpu/drm/xe/xe_ring_ops_types.h
HDRTEST drivers/gpu/drm/xe/xe_rtp.h
HDRTEST drivers/gpu/drm/xe/xe_rtp_types.h
HDRTEST drivers/gpu/drm/xe/xe_sa.h
HDRTEST drivers/gpu/drm/xe/xe_sa_types.h
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_clflush.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_tiling.h
HDRTEST drivers/gpu/drm/xe/xe_sched_job.h
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_stolen.h
HDRTEST drivers/gpu/drm/xe/xe_sched_job_types.h
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf100.o
HDRTEST drivers/gpu/drm/xe/xe_step.h
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_create.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/basics/conversion.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_ttm_move.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf119.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/basics/fixpt31_32.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/basics/vector.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk110.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk208.o
HDRTEST drivers/gpu/drm/xe/xe_step_types.h
HDRTEST drivers/gpu/drm/xe/xe_sync.h
HDRTEST drivers/gpu/drm/xe/xe_sync_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/basics/dc_common.o
HDRTEST drivers/gpu/drm/xe/xe_trace.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_ioctls.h
HDRTEST drivers/gpu/drm/xe/xe_ttm_stolen_mgr.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser_interface.o
HDRTEST drivers/gpu/drm/xe/xe_ttm_sys_mgr.h
HDRTEST drivers/gpu/drm/xe/xe_ttm_vram_mgr.h
HDRTEST drivers/gpu/drm/xe/xe_ttm_vram_mgr_types.h
HDRTEST drivers/gpu/drm/xe/xe_tuning.h
HDRTEST drivers/gpu/drm/xe/xe_uc.h
HDRTEST drivers/gpu/drm/xe/xe_uc_debugfs.h
HDRTEST drivers/gpu/drm/xe/xe_uc_fw.h
HDRTEST drivers/gpu/drm/xe/xe_uc_fw_abi.h
HDRTEST drivers/gpu/drm/xe/xe_uc_fw_types.h
HDRTEST drivers/gpu/drm/xe/xe_uc_types.h
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_domain.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser_helper.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_internal.h
HDRTEST drivers/gpu/drm/xe/xe_vm.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm107.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_dmabuf.h
HDRTEST drivers/gpu/drm/xe/xe_vm_doc.h
HDRTEST drivers/gpu/drm/xe/xe_vm_madvise.h
HDRTEST drivers/gpu/drm/i915/gem/selftests/mock_context.h
HDRTEST drivers/gpu/drm/xe/xe_vm_types.h
HDRTEST drivers/gpu/drm/xe/xe_wa.h
HDRTEST drivers/gpu/drm/i915/gem/selftests/huge_gem_object.h
HDRTEST drivers/gpu/drm/i915/gem/selftests/mock_gem_object.h
HDRTEST drivers/gpu/drm/xe/xe_wait_user_fence.h
HDRTEST drivers/gpu/drm/xe/xe_wopcm.h
HDRTEST drivers/gpu/drm/i915/gem/selftests/mock_dmabuf.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/command_table.o
HDRTEST drivers/gpu/drm/xe/xe_wopcm_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/command_table_helper.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm200.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser_common.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/command_table2.o
LD [M] drivers/gpu/drm/xe/xe.o
HDRTEST drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/command_table_helper2.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp102.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp10b.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/privring/gf100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser2.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/privring/gf117.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/privring/gk104.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce60/command_table_helper_dce60.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/privring/gk20a.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce80/command_table_helper_dce80.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_userptr.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce110/command_table_helper_dce110.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/privring/gm200.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/privring/gp10b.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_pm.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce112/command_table_helper_dce112.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_shrinker.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce112/command_table_helper2_dce112.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/calcs/dce_calcs.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gemfs.h
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_object.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/calcs/custom_float.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/calcs/bw_fixed.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_rq_dlg_helpers.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/fan.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/fannil.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/fantog.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/ic.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dml1_display_rq_dlg_calc.o
HDRTEST drivers/gpu/drm/i915/gt/intel_timeline_types.h
HDRTEST drivers/gpu/drm/i915/gt/selftest_engine.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn10/dcn10_fpu.o
drivers/gpu/drm/xe/xe.o: warning: objtool: intel_set_cpu_fifo_underrun_reporting+0x286: unreachable instruction
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv50.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/g84.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/dcn20_fpu.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_vba.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.o
HDRTEST drivers/gpu/drm/i915/gt/intel_breadcrumbs.h
HDRTEST drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/gt215.o
HDRTEST drivers/gpu/drm/i915/gt/intel_context_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf119.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_mode_vba_20.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20v2.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_mode_vba_20v2.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm107.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm200.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/gp100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/timer/base.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn21/display_rq_dlg_calc_21.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv40.o
HDRTEST drivers/gpu/drm/i915/gt/intel_execlists_submission.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn21/display_mode_vba_21.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_pm.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/dcn30_fpu.o
HDRTEST drivers/gpu/drm/i915/gt/selftest_rc6.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv41.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/display_mode_vba_30.o
HDRTEST drivers/gpu/drm/i915/gt/intel_llc_types.h
HDRTEST drivers/gpu/drm/i915/gt/intel_gt.h
HDRTEST drivers/gpu/drm/i915/gt/intel_region_lmem.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/timer/gk20a.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_requests.h
HDRTEST drivers/gpu/drm/i915/gt/intel_ggtt_gmch.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/top/base.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/display_rq_dlg_calc_30.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/display_mode_vba_31.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/top/gk104.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/display_rq_dlg_calc_31.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/top/ga100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/vfn/base.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_print.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/display_mode_vba_314.o
HDRTEST drivers/gpu/drm/i915/gt/gen8_ppgtt.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/vfn/uvfn.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/display_rq_dlg_calc_314.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_mcr.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/vfn/gv100.o
HDRTEST drivers/gpu/drm/i915/gt/intel_timeline.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.o
HDRTEST drivers/gpu/drm/i915/gt/gen6_engine_cs.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_rq_dlg_calc_32.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/vfn/tu102.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_util_32.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/dcn31_fpu.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h
HDRTEST drivers/gpu/drm/i915/gt/intel_workarounds_types.h
HDRTEST drivers/gpu/drm/i915/gt/selftest_rps.h
HDRTEST drivers/gpu/drm/i915/gt/intel_sa_media.h
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_debugfs.h
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_clock_utils.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/vfn/ga100.o
HDRTEST drivers/gpu/drm/i915/gt/intel_rps_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/dcn32_fpu.o
HDRTEST drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn321/dcn321_fpu.o
HDRTEST drivers/gpu/drm/i915/gt/sysfs_engines.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn301/dcn301_fpu.o
HDRTEST drivers/gpu/drm/i915/gt/gen7_renderclear.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/volt/gpio.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/volt/nv40.o
HDRTEST drivers/gpu/drm/i915/gt/intel_context.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn302/dcn302_fpu.o
HDRTEST drivers/gpu/drm/i915/gt/intel_wopcm.h
HDRTEST drivers/gpu/drm/i915/gt/intel_mocs.h
HDRTEST drivers/gpu/drm/i915/gt/intel_engine_pm.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/volt/gf100.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_sysfs.h
HDRTEST drivers/gpu/drm/i915/gt/intel_rc6.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/volt/gf117.o
HDRTEST drivers/gpu/drm/i915/gt/intel_ring_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.o
HDRTEST drivers/gpu/drm/i915/gt/intel_workarounds.h
HDRTEST drivers/gpu/drm/i915/gt/intel_engine_regs.h
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_pm_irq.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn303/dcn303_fpu.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/volt/gm20b.o
HDRTEST drivers/gpu/drm/i915/gt/shmem_utils.h
HDRTEST drivers/gpu/drm/i915/gt/intel_engine.h
HDRTEST drivers/gpu/drm/i915/gt/intel_reset_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/falcon.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/dcn314_fpu.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/xtensa.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/bsp/g84.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dsc/rc_calc_fpu.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/calcs/dcn_calcs.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/calcs/dcn_calc_math.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/calcs/dcn_calc_auto.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_regs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.o
HDRTEST drivers/gpu/drm/i915/gt/intel_reset.h
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.o
HDRTEST drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/clk_mgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dce60/dce60_clk_mgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dce100/dce_clk_mgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/gm107.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/gm200.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_uc.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/gp100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/gp102.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dce110/dce110_clk_mgr.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_print.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/gv100.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_fw.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dce112/dce112_clk_mgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dce120/dce120_clk_mgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn10/rv1_clk_mgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/tu102.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/ga100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn10/rv2_clk_mgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/ga102.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn201/dcn201_clk_mgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.h
HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h
HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h
HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h
HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/device/base.o
HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn21/rn_clk_mgr.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.h
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_huc.h
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc.h
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_huc_fw.h
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_capture.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/device/pci.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/device/user.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/base.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/chan.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.h
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmi.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/head.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn301/vg_clk_mgr.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_log.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn301/dcn301_smu.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn31/dcn31_smu.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn31/dcn31_clk_mgr.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn314/dcn314_smu.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn314/dcn314_clk_mgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn315/dcn315_smu.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.h
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_rc.h
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_huc_debugfs.h
HDRTEST drivers/gpu/drm/i915/gt/intel_hwconfig.h
HDRTEST drivers/gpu/drm/i915/gt/intel_llc.h
HDRTEST drivers/gpu/drm/i915/gt/gen8_engine_cs.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn315/dcn315_clk_mgr.o
HDRTEST drivers/gpu/drm/i915/gt/intel_sseu_debugfs.h
HDRTEST drivers/gpu/drm/i915/gt/intel_rc6_types.h
HDRTEST drivers/gpu/drm/i915/gt/intel_context_param.h
HDRTEST drivers/gpu/drm/i915/gt/intel_gpu_commands.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/vga.o
HDRTEST drivers/gpu/drm/i915/gt/intel_engine_user.h
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_irq.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn316/dcn316_smu.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gsc.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn316/dcn316_clk_mgr.o
HDRTEST drivers/gpu/drm/i915/gt/intel_rps.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.o
HDRTEST drivers/gpu/drm/i915/gt/selftest_llc.h
HDRTEST drivers/gpu/drm/i915/gt/gen6_ppgtt.h
HDRTEST drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gt200.o
HDRTEST drivers/gpu/drm/i915/gt/intel_migrate_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp77.o
HDRTEST drivers/gpu/drm/i915/gt/selftests/mock_timeline.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.o
HDRTEST drivers/gpu/drm/i915/gt/intel_lrc.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.o
HDRTEST drivers/gpu/drm/i915/gt/intel_lrc_reg.h
HDRTEST drivers/gpu/drm/i915/gt/intel_migrate.h
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.h
HDRTEST drivers/gpu/drm/i915/gt/intel_breadcrumbs_types.h
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_audio.o
HDRTEST drivers/gpu/drm/i915/gt/mock_engine.h
HDRTEST drivers/gpu/drm/i915/gt/intel_engine_stats.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_stream_encoder.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gtt.h
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_buffer_pool_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp89.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_link_encoder.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_hwseq.o
HDRTEST drivers/gpu/drm/i915/gt/intel_ring.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_clock_source.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gm200.o
HDRTEST drivers/gpu/drm/i915/gt/intel_renderstate.h
HDRTEST drivers/gpu/drm/i915/gt/intel_sseu.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_scl_filters.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gp100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_transform.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_opp.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_dmcu.o
HDRTEST drivers/gpu/drm/i915/gt/intel_engine_types.h
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_engines_debugfs.h
HDRTEST drivers/gpu/drm/i915/gt/gen2_engine_cs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.o
HDRTEST drivers/gpu/drm/i915/gvt/gvt.h
HDRTEST drivers/gpu/drm/i915/gvt/trace.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/ga102.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/udisp.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_abm.o
HDRTEST drivers/gpu/drm/i915/gvt/debug.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_ipp.o
HDRTEST drivers/gpu/drm/i915/gvt/edid.h
HDRTEST drivers/gpu/drm/i915/gvt/page_track.h
HDRTEST drivers/gpu/drm/i915/gvt/mmio.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/uhead.o
HDRTEST drivers/gpu/drm/i915/gvt/sched_policy.h
HDRTEST drivers/gpu/drm/i915/gvt/fb_decoder.h
HDRTEST drivers/gpu/drm/i915/gvt/cmd_parser.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/base.o
HDRTEST drivers/gpu/drm/i915/gvt/dmabuf.h
HDRTEST drivers/gpu/drm/i915/gvt/mmio_context.h
HDRTEST drivers/gpu/drm/i915/gvt/display.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/nv04.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_i2c.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/nv50.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/gf100.o
HDRTEST drivers/gpu/drm/i915/gvt/gtt.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/gf119.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/gv100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/user.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_i2c_hw.o
HDRTEST drivers/gpu/drm/i915/gvt/scheduler.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.o
HDRTEST drivers/gpu/drm/i915/gvt/reg.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_i2c_sw.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dmub_psr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.o
HDRTEST drivers/gpu/drm/i915/gvt/execlist.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dmub_abm.o
HDRTEST drivers/gpu/drm/i915/gvt/interrupt.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.o
HDRTEST drivers/gpu/drm/i915/i915_active.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/cgrp.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_panel_cntl.o
HDRTEST drivers/gpu/drm/i915/i915_active_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/chid.o
HDRTEST drivers/gpu/drm/i915/i915_cmd_parser.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dmub_hw_lock_mgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/runl.o
HDRTEST drivers/gpu/drm/i915/i915_config.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dmub_outbox.o
HDRTEST drivers/gpu/drm/i915/i915_debugfs.h
HDRTEST drivers/gpu/drm/i915/i915_debugfs_params.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/runq.o
HDRTEST drivers/gpu/drm/i915/i915_deps.h
HDRTEST drivers/gpu/drm/i915/i915_driver.h
HDRTEST drivers/gpu/drm/i915/i915_drm_client.h
HDRTEST drivers/gpu/drm/i915/i915_drv.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/gpio_base.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.o
HDRTEST drivers/gpu/drm/i915/i915_file_private.h
HDRTEST drivers/gpu/drm/i915/i915_fixed.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/gpio_service.o
HDRTEST drivers/gpu/drm/i915/i915_gem.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.o
HDRTEST drivers/gpu/drm/i915/i915_gem_evict.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/hw_factory.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/hw_gpio.o
HDRTEST drivers/gpu/drm/i915/i915_gem_gtt.h
HDRTEST drivers/gpu/drm/i915/i915_gem_ww.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/g98.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/hw_hpd.o
HDRTEST drivers/gpu/drm/i915/i915_getparam.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/hw_ddc.o
HDRTEST drivers/gpu/drm/i915/i915_gpu_error.h
HDRTEST drivers/gpu/drm/i915/i915_hwmon.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk110.o
HDRTEST drivers/gpu/drm/i915/i915_ioc32.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/hw_generic.o
HDRTEST drivers/gpu/drm/i915/i915_ioctl.h
HDRTEST drivers/gpu/drm/i915/i915_iosf_mbi.h
HDRTEST drivers/gpu/drm/i915/i915_irq.h
HDRTEST drivers/gpu/drm/i915/i915_memcpy.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.o
HDRTEST drivers/gpu/drm/i915/i915_mitigations.h
HDRTEST drivers/gpu/drm/i915/i915_mm.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/hw_translate.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm200.o
HDRTEST drivers/gpu/drm/i915/i915_params.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dce60/hw_translate_dce60.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dce60/hw_factory_dce60.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dce80/hw_translate_dce80.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dce80/hw_factory_dce80.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dce110/hw_translate_dce110.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dce110/hw_factory_dce110.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/tu102.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga102.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dce120/hw_translate_dce120.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/ucgrp.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/uchan.o
HDRTEST drivers/gpu/drm/i915/i915_pci.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/base.o
HDRTEST drivers/gpu/drm/i915/i915_perf.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dce120/hw_factory_dce120.o
HDRTEST drivers/gpu/drm/i915/i915_perf_oa_regs.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn10/hw_translate_dcn10.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn10/hw_factory_dcn10.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn20/hw_translate_dcn20.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn20/hw_factory_dcn20.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn21/hw_translate_dcn21.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn21/hw_factory_dcn21.o
HDRTEST drivers/gpu/drm/i915/i915_perf_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/nv15.o
HDRTEST drivers/gpu/drm/i915/i915_pmu.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn30/hw_translate_dcn30.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn30/hw_factory_dcn30.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/nv17.o
HDRTEST drivers/gpu/drm/i915/i915_priolist_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn315/hw_translate_dcn315.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn315/hw_factory_dcn315.o
HDRTEST drivers/gpu/drm/i915/i915_pvinfo.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.o
HDRTEST drivers/gpu/drm/i915/i915_query.h
HDRTEST drivers/gpu/drm/i915/i915_reg.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.o
HDRTEST drivers/gpu/drm/i915/i915_reg_defs.h
HDRTEST drivers/gpu/drm/i915/i915_request.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn32/hw_translate_dcn32.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.o
HDRTEST drivers/gpu/drm/i915/i915_scatterlist.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn32/hw_factory_dcn32.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/irq_service.o
HDRTEST drivers/gpu/drm/i915/i915_scheduler.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.o
HDRTEST drivers/gpu/drm/i915/i915_scheduler_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dce60/irq_service_dce60.o
HDRTEST drivers/gpu/drm/i915/i915_selftest.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dce80/irq_service_dce80.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/gt200.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dce110/irq_service_dce110.o
HDRTEST drivers/gpu/drm/i915/i915_suspend.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp79.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dce120/irq_service_dce120.o
HDRTEST drivers/gpu/drm/i915/i915_sw_fence.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn10/irq_service_dcn10.o
HDRTEST drivers/gpu/drm/i915/i915_sw_fence_work.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/gt215.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn20/irq_service_dcn20.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp89.o
HDRTEST drivers/gpu/drm/i915/i915_switcheroo.h
HDRTEST drivers/gpu/drm/i915/i915_syncmap.h
HDRTEST drivers/gpu/drm/i915/i915_sysfs.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.o
HDRTEST drivers/gpu/drm/i915/i915_tasklet.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn201/irq_service_dcn201.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn30/irq_service_dcn30.o
HDRTEST drivers/gpu/drm/i915/i915_trace.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn302/irq_service_dcn302.o
HDRTEST drivers/gpu/drm/i915/i915_ttm_buddy_manager.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn303/irq_service_dcn303.o
HDRTEST drivers/gpu/drm/i915/i915_user_extensions.h
HDRTEST drivers/gpu/drm/i915/i915_utils.h
HDRTEST drivers/gpu/drm/i915/i915_vma.h
HDRTEST drivers/gpu/drm/i915/i915_vgpu.h
HDRTEST drivers/gpu/drm/i915/i915_vma_resource.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.o
HDRTEST drivers/gpu/drm/i915/i915_vma_types.h
HDRTEST drivers/gpu/drm/i915/intel_device_info.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.o
HDRTEST drivers/gpu/drm/i915/intel_gvt.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn31/irq_service_dcn31.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn314/irq_service_dcn314.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn315/irq_service_dcn315.o
HDRTEST drivers/gpu/drm/i915/intel_mchbar_regs.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn32/irq_service_dcn32.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_detection.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.o
HDRTEST drivers/gpu/drm/i915/intel_memory_region.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_dpms.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.o
HDRTEST drivers/gpu/drm/i915/intel_pci_config.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.o
HDRTEST drivers/gpu/drm/i915/intel_pcode.h
HDRTEST drivers/gpu/drm/i915/intel_pm.h
HDRTEST drivers/gpu/drm/i915/intel_region_ttm.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_factory.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.o
HDRTEST drivers/gpu/drm/i915/intel_runtime_pm.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_resource.o
HDRTEST drivers/gpu/drm/i915/intel_sbi.h
HDRTEST drivers/gpu/drm/i915/intel_step.h
HDRTEST drivers/gpu/drm/i915/intel_uncore.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_validation.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/accessories/link_dp_trace.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.o
HDRTEST drivers/gpu/drm/i915/intel_wakeref.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/accessories/link_dp_cts.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/accessories/link_fpga.o
HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/gp104.o
HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_irq.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/hwss/link_hwss_dio.o
HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_session.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/gp107.o
HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/gp108.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/hwss/link_hwss_dpia.o
HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp.h
HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/gp10b.o
HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/hwss/link_hwss_hpo_dp.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_hpd.o
HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_cmn.h
HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_huc.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_ddc.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/tu102.o
HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_42.h
HDRTEST drivers/gpu/drm/i915/selftests/igt_live_test.h
HDRTEST drivers/gpu/drm/i915/selftests/igt_atomic.h
HDRTEST drivers/gpu/drm/i915/selftests/mock_gem_device.h
HDRTEST drivers/gpu/drm/i915/selftests/mock_drm.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dpcd.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_dpia.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_training.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ga102.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_training_8b_10b.o
HDRTEST drivers/gpu/drm/i915/selftests/igt_reset.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_training_128b_132b.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_training_dpia.o
HDRTEST drivers/gpu/drm/i915/selftests/intel_scheduler_helpers.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_training_auxless.o
HDRTEST drivers/gpu/drm/i915/selftests/lib_sw_fence.h
HDRTEST drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
HDRTEST drivers/gpu/drm/i915/selftests/mock_uncore.h
HDRTEST drivers/gpu/drm/i915/selftests/mock_gtt.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf104.o
HDRTEST drivers/gpu/drm/i915/selftests/i915_mock_selftests.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf110.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_phy.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf119.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110b.o
HDRTEST drivers/gpu/drm/i915/selftests/mock_request.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_capability.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk208.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_edp_panel_control.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_irq_handler.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.o
HDRTEST drivers/gpu/drm/i915/selftests/i915_random.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.o
HDRTEST drivers/gpu/drm/i915/selftests/igt_spinner.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp102.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_dpia_bw.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp104.o
HDRTEST drivers/gpu/drm/i915/selftests/librapl.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/virtual/virtual_link_encoder.o
HDRTEST drivers/gpu/drm/i915/selftests/mock_region.h
HDRTEST drivers/gpu/drm/i915/selftests/i915_live_selftests.h
HDRTEST drivers/gpu/drm/i915/selftests/igt_mmap.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp107.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxtu102.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxga102.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/virtual/virtual_stream_encoder.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/virtual/virtual_link_hwss.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dsc/dc_dsc.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dsc/rc_calc.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dsc/rc_calc_dpi.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_init.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hwseq.o
CC [M] d
^ permalink raw reply [flat|nested] 41+ messages in thread
* [Intel-xe] ○ CI.BAT: info for Cleanup registers and introduce xe_reg_t
2023-04-19 7:44 [Intel-xe] [PATCH 00/17] Cleanup registers and introduce xe_reg_t Lucas De Marchi
` (19 preceding siblings ...)
2023-04-19 7:52 ` [Intel-xe] ✓ CI.Build: " Patchwork
@ 2023-04-19 8:12 ` Patchwork
20 siblings, 0 replies; 41+ messages in thread
From: Patchwork @ 2023-04-19 8:12 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 341 bytes --]
== Series Details ==
Series: Cleanup registers and introduce xe_reg_t
URL : https://patchwork.freedesktop.org/series/116678/
State : info
== Summary ==
Participating hosts:
bat-atsm-2
bat-dg2-oem2
bat-adlp-7
Missing hosts results[1]:
bat-adlp-7
Results: [xe-pw-116678v1](https://intel-gfx-ci.01.org/tree/xe/xe-pw-116678v1/index.html)
[-- Attachment #2: Type: text/html, Size: 857 bytes --]
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [Intel-xe] [PATCH 11/17] drm/xe: Introduce xe_reg_t
2023-04-19 7:44 ` [Intel-xe] [PATCH 11/17] drm/xe: Introduce xe_reg_t Lucas De Marchi
@ 2023-04-19 16:06 ` Jani Nikula
2023-04-19 17:17 ` Lucas De Marchi
2023-04-19 17:33 ` Matt Roper
1 sibling, 1 reply; 41+ messages in thread
From: Jani Nikula @ 2023-04-19 16:06 UTC (permalink / raw)
To: Lucas De Marchi, intel-xe; +Cc: Matt Roper, Lucas De Marchi, Rodrigo Vivi
On Wed, 19 Apr 2023, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> Stop using i915 types for register our own xe_reg_t. Differently from
> i915, this will keep under this will keep under the register definition
> the knowledge for the different types of registers. For now, the "flags"
> are mcr and masked, although only the former is being used.
>
> Most of the driver is agnostic to the register differences. Convert the
> few places that care about that, namely xe_gt_mcr.c, to take the generic
> type and warn if the wrong register is used.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/xe/regs/xe_reg_defs.h | 15 +++++++++++++++
> drivers/gpu/drm/xe/xe_gt_mcr.c | 22 ++++++++++++++++------
> drivers/gpu/drm/xe/xe_gt_mcr.h | 8 ++++----
> drivers/gpu/drm/xe/xe_irq.c | 2 +-
> drivers/gpu/drm/xe/xe_mmio.c | 2 +-
> 5 files changed, 37 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_reg_defs.h b/drivers/gpu/drm/xe/regs/xe_reg_defs.h
> index b5c25e31b889..1e78508c737b 100644
> --- a/drivers/gpu/drm/xe/regs/xe_reg_defs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_reg_defs.h
> @@ -8,4 +8,19 @@
>
> #include "compat-i915-headers/i915_reg_defs.h"
>
> +typedef union {
> + struct {
> + u32 reg:30;
> + u32 mcr:1;
> + u32 masked:1;
> + };
> + u32 raw;
> +} xe_reg_t;
> +
> +/* TODO: remove these once the register declarations are not using them anymore */
> +#undef _MMIO
> +#undef MCR_REG
> +#define _MMIO(r) ((const xe_reg_t){ .reg = (r) })
> +#define MCR_REG(r) ((const xe_reg_t){ .reg = (r), .mcr = 1 })
> +
> #endif
> diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
> index aa04ba5a6dbe..b9631cfd5b81 100644
> --- a/drivers/gpu/drm/xe/xe_gt_mcr.c
> +++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
> @@ -360,11 +360,13 @@ void xe_gt_mcr_set_implicit_defaults(struct xe_gt *gt)
> * returned. Returns false if the caller need not perform any steering
> */
> static bool xe_gt_mcr_get_nonterminated_steering(struct xe_gt *gt,
> - i915_mcr_reg_t reg,
> + xe_reg_t reg,
> u8 *group, u8 *instance)
> {
> const struct xe_mmio_range *implicit_ranges;
>
> + drm_WARN_ON(>_to_xe(gt)->drm, !reg.mcr);
I'd add some is_mcr_reg() style macro and use it throughout instead of
poking directly at xe_reg_t guts. The idea should be that xe_reg_t is
opaque.
BR,
Jani.
> +
> for (int type = 0; type < IMPLICIT_STEERING; type++) {
> if (!gt->steering[type].ranges)
> continue;
> @@ -436,11 +438,13 @@ static void mcr_unlock(struct xe_gt *gt) {
> *
> * Caller needs to make sure the relevant forcewake wells are up.
> */
> -static u32 rw_with_mcr_steering(struct xe_gt *gt, i915_mcr_reg_t reg, u8 rw_flag,
> +static u32 rw_with_mcr_steering(struct xe_gt *gt, xe_reg_t reg, u8 rw_flag,
> int group, int instance, u32 value)
> {
> u32 steer_reg, steer_val, val = 0;
>
> + drm_WARN_ON(>_to_xe(gt)->drm, !reg.mcr);
> +
> lockdep_assert_held(>->mcr_lock);
>
> if (GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270) {
> @@ -494,12 +498,14 @@ static u32 rw_with_mcr_steering(struct xe_gt *gt, i915_mcr_reg_t reg, u8 rw_flag
> *
> * Returns the value from a non-terminated instance of @reg.
> */
> -u32 xe_gt_mcr_unicast_read_any(struct xe_gt *gt, i915_mcr_reg_t reg)
> +u32 xe_gt_mcr_unicast_read_any(struct xe_gt *gt, xe_reg_t reg)
> {
> u8 group, instance;
> u32 val;
> bool steer;
>
> + drm_WARN_ON(>_to_xe(gt)->drm, !reg.mcr);
> +
> steer = xe_gt_mcr_get_nonterminated_steering(gt, reg, &group, &instance);
>
> if (steer) {
> @@ -525,11 +531,13 @@ u32 xe_gt_mcr_unicast_read_any(struct xe_gt *gt, i915_mcr_reg_t reg)
> * group/instance.
> */
> u32 xe_gt_mcr_unicast_read(struct xe_gt *gt,
> - i915_mcr_reg_t reg,
> + xe_reg_t reg,
> int group, int instance)
> {
> u32 val;
>
> + drm_WARN_ON(>_to_xe(gt)->drm, !reg.mcr);
> +
> mcr_lock(gt);
> val = rw_with_mcr_steering(gt, reg, MCR_OP_READ, group, instance, 0);
> mcr_unlock(gt);
> @@ -548,9 +556,11 @@ u32 xe_gt_mcr_unicast_read(struct xe_gt *gt,
> * Write an MCR register in unicast mode after steering toward a specific
> * group/instance.
> */
> -void xe_gt_mcr_unicast_write(struct xe_gt *gt, i915_mcr_reg_t reg, u32 value,
> +void xe_gt_mcr_unicast_write(struct xe_gt *gt, xe_reg_t reg, u32 value,
> int group, int instance)
> {
> + drm_WARN_ON(>_to_xe(gt)->drm, !reg.mcr);
> +
> mcr_lock(gt);
> rw_with_mcr_steering(gt, reg, MCR_OP_WRITE, group, instance, value);
> mcr_unlock(gt);
> @@ -564,7 +574,7 @@ void xe_gt_mcr_unicast_write(struct xe_gt *gt, i915_mcr_reg_t reg, u32 value,
> *
> * Write an MCR register in multicast mode to update all instances.
> */
> -void xe_gt_mcr_multicast_write(struct xe_gt *gt, i915_mcr_reg_t reg, u32 value)
> +void xe_gt_mcr_multicast_write(struct xe_gt *gt, xe_reg_t reg, u32 value)
> {
> /*
> * Synchronize with any unicast operations. Once we have exclusive
> diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.h b/drivers/gpu/drm/xe/xe_gt_mcr.h
> index 2a6cd38c8cb7..492d9519784a 100644
> --- a/drivers/gpu/drm/xe/xe_gt_mcr.h
> +++ b/drivers/gpu/drm/xe/xe_gt_mcr.h
> @@ -15,13 +15,13 @@ void xe_gt_mcr_init(struct xe_gt *gt);
>
> void xe_gt_mcr_set_implicit_defaults(struct xe_gt *gt);
>
> -u32 xe_gt_mcr_unicast_read(struct xe_gt *gt, i915_mcr_reg_t reg,
> +u32 xe_gt_mcr_unicast_read(struct xe_gt *gt, xe_reg_t reg,
> int group, int instance);
> -u32 xe_gt_mcr_unicast_read_any(struct xe_gt *gt, i915_mcr_reg_t reg);
> +u32 xe_gt_mcr_unicast_read_any(struct xe_gt *gt, xe_reg_t reg);
>
> -void xe_gt_mcr_unicast_write(struct xe_gt *gt, i915_mcr_reg_t reg, u32 value,
> +void xe_gt_mcr_unicast_write(struct xe_gt *gt, xe_reg_t reg, u32 value,
> int group, int instance);
> -void xe_gt_mcr_multicast_write(struct xe_gt *gt, i915_mcr_reg_t reg, u32 value);
> +void xe_gt_mcr_multicast_write(struct xe_gt *gt, xe_reg_t reg, u32 value);
>
> void xe_gt_mcr_steering_dump(struct xe_gt *gt, struct drm_printer *p);
>
> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> index 13f9f220bca0..8e5f8e7c16c8 100644
> --- a/drivers/gpu/drm/xe/xe_irq.c
> +++ b/drivers/gpu/drm/xe/xe_irq.c
> @@ -27,7 +27,7 @@
> #define IIR(offset) _MMIO(offset + 0x8)
> #define IER(offset) _MMIO(offset + 0xc)
>
> -static void assert_iir_is_zero(struct xe_gt *gt, i915_reg_t reg)
> +static void assert_iir_is_zero(struct xe_gt *gt, xe_reg_t reg)
> {
> u32 val = xe_mmio_read32(gt, reg.reg);
>
> diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
> index a93838e23b7b..1029b9f27988 100644
> --- a/drivers/gpu/drm/xe/xe_mmio.c
> +++ b/drivers/gpu/drm/xe/xe_mmio.c
> @@ -397,7 +397,7 @@ int xe_mmio_init(struct xe_device *xe)
> DRM_XE_MMIO_READ |\
> DRM_XE_MMIO_WRITE)
>
> -static const i915_reg_t mmio_read_whitelist[] = {
> +static const xe_reg_t mmio_read_whitelist[] = {
> RING_TIMESTAMP(RENDER_RING_BASE),
> };
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [Intel-xe] [PATCH 16/17] drm/xe: Plumb xe_reg_t into WAs, rtp, etc
2023-04-19 7:44 ` [Intel-xe] [PATCH 16/17] drm/xe: Plumb xe_reg_t into WAs, rtp, etc Lucas De Marchi
@ 2023-04-19 16:15 ` Jani Nikula
0 siblings, 0 replies; 41+ messages in thread
From: Jani Nikula @ 2023-04-19 16:15 UTC (permalink / raw)
To: Lucas De Marchi, intel-xe; +Cc: Matt Roper, Lucas De Marchi, Rodrigo Vivi
On Wed, 19 Apr 2023, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> Now that xe_reg_t is a type that can be used by xe, convert the rest of
> the driver to use it:
>
> - The RTP tables don't need the MASKED flags anymore in the
> actions as that information now comes from the register
> definition
>
> - There is no need for the _XE_RTP_REG/_XE_RTP_REG_MCR macros an
> the register types on RTP infra: that comes from the register
> definitions.
>
> - When declaring the RTP entries, there is no need anymore to
> undef XE_REG and friends: the RTP macros deal with removing
> the cast where needed due to not being able to use a compound
> statement for initialization in the tables
>
> - The index in the reg-sr xarray is the register offset only.
> Otherwise we wouldn't catch mistakes about adding both a
> MCR-style and normal-style registers. For that, the register
> is now also part of the entry, so the options can be compared
> to check for compatible entries.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/xe/tests/xe_rtp_test.c | 40 +++-----
> drivers/gpu/drm/xe/xe_guc_ads.c | 2 +-
> drivers/gpu/drm/xe/xe_reg_sr.c | 25 +++--
> drivers/gpu/drm/xe/xe_reg_sr.h | 3 +-
> drivers/gpu/drm/xe/xe_reg_sr_types.h | 10 +-
> drivers/gpu/drm/xe/xe_reg_whitelist.c | 5 -
> drivers/gpu/drm/xe/xe_rtp.c | 7 +-
> drivers/gpu/drm/xe/xe_rtp.h | 46 ++++-----
> drivers/gpu/drm/xe/xe_rtp_types.h | 14 +--
> drivers/gpu/drm/xe/xe_tuning.c | 8 +-
> drivers/gpu/drm/xe/xe_wa.c | 135 ++++++++-----------------
> 11 files changed, 106 insertions(+), 189 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/tests/xe_rtp_test.c b/drivers/gpu/drm/xe/tests/xe_rtp_test.c
> index 51d215f08113..ad917638d088 100644
> --- a/drivers/gpu/drm/xe/tests/xe_rtp_test.c
> +++ b/drivers/gpu/drm/xe/tests/xe_rtp_test.c
> @@ -18,25 +18,18 @@
> #include "xe_reg_sr.h"
> #include "xe_rtp.h"
>
> -#undef XE_REG
> -#undef XE_REG_MCR
> -#define XE_REG(x, ...) _XE_RTP_REG(x)
> -#define XE_REG_MCR(x, ...) _XE_RTP_MCR_REG(x)
> -
> #define REGULAR_REG1 XE_REG(1)
> #define REGULAR_REG2 XE_REG(2)
> #define REGULAR_REG3 XE_REG(3)
> #define MCR_REG1 XE_REG_MCR(1)
> #define MCR_REG2 XE_REG_MCR(2)
> #define MCR_REG3 XE_REG_MCR(3)
> +#define MASKED_REG1 XE_REG(1, XE_REG_OPTION_MASKED)
>
> struct rtp_test_case {
> const char *name;
> - struct {
> - u32 offset;
> - u32 type;
> - } expected_reg;
> - u32 expected_set_bits;
> + xe_reg_t expected_reg;
> + u32 expected_set_bits;
> u32 expected_clr_bits;
> unsigned long expected_count;
> unsigned int expected_sr_errors;
> @@ -56,7 +49,7 @@ static bool match_no(const struct xe_gt *gt, const struct xe_hw_engine *hwe)
> static const struct rtp_test_case cases[] = {
> {
> .name = "coalesce-same-reg",
> - .expected_reg = { REGULAR_REG1 },
> + .expected_reg = REGULAR_REG1,
> .expected_set_bits = REG_BIT(0) | REG_BIT(1),
> .expected_clr_bits = REG_BIT(0) | REG_BIT(1),
> .expected_count = 1,
> @@ -64,7 +57,7 @@ static const struct rtp_test_case cases[] = {
> .entries = (const struct xe_rtp_entry[]) {
> { XE_RTP_NAME("basic-1"),
> XE_RTP_RULES(FUNC(match_yes)),
> - XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
> + XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(1)))
I'm not doing a detailed review, but this caught my eye and looked
suspicious.
> },
> { XE_RTP_NAME("basic-2"),
> XE_RTP_RULES(FUNC(match_yes)),
> @@ -75,7 +68,7 @@ static const struct rtp_test_case cases[] = {
> },
> {
> .name = "no-match-no-add",
> - .expected_reg = { REGULAR_REG1 },
> + .expected_reg = REGULAR_REG1,
> .expected_set_bits = REG_BIT(0),
> .expected_clr_bits = REG_BIT(0),
> .expected_count = 1,
> @@ -94,7 +87,7 @@ static const struct rtp_test_case cases[] = {
> },
> {
> .name = "no-match-no-add-multiple-rules",
> - .expected_reg = { REGULAR_REG1 },
> + .expected_reg = REGULAR_REG1,
> .expected_set_bits = REG_BIT(0),
> .expected_clr_bits = REG_BIT(0),
> .expected_count = 1,
> @@ -113,7 +106,7 @@ static const struct rtp_test_case cases[] = {
> },
> {
> .name = "two-regs-two-entries",
> - .expected_reg = { REGULAR_REG1 },
> + .expected_reg = REGULAR_REG1,
> .expected_set_bits = REG_BIT(0),
> .expected_clr_bits = REG_BIT(0),
> .expected_count = 2,
> @@ -132,7 +125,7 @@ static const struct rtp_test_case cases[] = {
> },
> {
> .name = "clr-one-set-other",
> - .expected_reg = { REGULAR_REG1 },
> + .expected_reg = REGULAR_REG1,
> .expected_set_bits = REG_BIT(0),
> .expected_clr_bits = REG_BIT(1) | REG_BIT(0),
> .expected_count = 1,
> @@ -153,7 +146,7 @@ static const struct rtp_test_case cases[] = {
> #define TEMP_MASK REG_GENMASK(10, 8)
> #define TEMP_FIELD REG_FIELD_PREP(TEMP_MASK, 2)
> .name = "set-field",
> - .expected_reg = { REGULAR_REG1 },
> + .expected_reg = REGULAR_REG1,
> .expected_set_bits = TEMP_FIELD,
> .expected_clr_bits = TEMP_MASK,
> .expected_count = 1,
> @@ -171,7 +164,7 @@ static const struct rtp_test_case cases[] = {
> },
> {
> .name = "conflict-duplicate",
> - .expected_reg = { REGULAR_REG1 },
> + .expected_reg = REGULAR_REG1,
> .expected_set_bits = REG_BIT(0),
> .expected_clr_bits = REG_BIT(0),
> .expected_count = 1,
> @@ -191,7 +184,7 @@ static const struct rtp_test_case cases[] = {
> },
> {
> .name = "conflict-not-disjoint",
> - .expected_reg = { REGULAR_REG1 },
> + .expected_reg = REGULAR_REG1,
> .expected_set_bits = REG_BIT(0),
> .expected_clr_bits = REG_BIT(0),
> .expected_count = 1,
> @@ -211,7 +204,7 @@ static const struct rtp_test_case cases[] = {
> },
> {
> .name = "conflict-reg-type",
> - .expected_reg = { REGULAR_REG1 },
> + .expected_reg = REGULAR_REG1,
> .expected_set_bits = REG_BIT(0),
> .expected_clr_bits = REG_BIT(0),
> .expected_count = 1,
> @@ -229,8 +222,7 @@ static const struct rtp_test_case cases[] = {
> /* drop: regular vs masked */
> { XE_RTP_NAME("basic-3"),
> XE_RTP_RULES(FUNC(match_yes)),
> - XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0),
> - XE_RTP_ACTION_FLAG(MASKED_REG)))
> + XE_RTP_ACTIONS(SET(MASKED_REG1, REG_BIT(0)))
> },
> {}
> },
> @@ -249,7 +241,7 @@ static void xe_rtp_process_tests(struct kunit *test)
> xe_rtp_process(param->entries, reg_sr, &xe->gt[0], NULL);
>
> xa_for_each(®_sr->xa, idx, sre) {
> - if (idx == param->expected_reg.offset)
> + if (idx == param->expected_reg.reg)
> sr_entry = sre;
>
> count++;
> @@ -258,7 +250,7 @@ static void xe_rtp_process_tests(struct kunit *test)
> KUNIT_EXPECT_EQ(test, count, param->expected_count);
> KUNIT_EXPECT_EQ(test, sr_entry->clr_bits, param->expected_clr_bits);
> KUNIT_EXPECT_EQ(test, sr_entry->set_bits, param->expected_set_bits);
> - KUNIT_EXPECT_EQ(test, sr_entry->reg_type, param->expected_reg.type);
> + KUNIT_EXPECT_EQ(test, sr_entry->reg.raw, param->expected_reg.raw);
> KUNIT_EXPECT_EQ(test, reg_sr->errors, param->expected_sr_errors);
> }
>
> diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
> index 6a723bda2aa9..676137dcb510 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ads.c
> +++ b/drivers/gpu/drm/xe/xe_guc_ads.c
> @@ -461,7 +461,7 @@ static unsigned int guc_mmio_regset_write(struct xe_guc_ads *ads,
> BUILD_BUG_ON(ARRAY_SIZE(extra_regs) > ADS_REGSET_EXTRA_MAX);
>
> xa_for_each(&hwe->reg_sr.xa, idx, entry) {
> - u32 flags = entry->masked_reg ? GUC_REGSET_MASKED : 0;
> + u32 flags = entry->reg.masked ? GUC_REGSET_MASKED : 0;
>
> guc_mmio_regset_write_one(ads, regset_map, idx, flags, count++);
> }
> diff --git a/drivers/gpu/drm/xe/xe_reg_sr.c b/drivers/gpu/drm/xe/xe_reg_sr.c
> index 78cb0e93a7ed..ff00e1b20548 100644
> --- a/drivers/gpu/drm/xe/xe_reg_sr.c
> +++ b/drivers/gpu/drm/xe/xe_reg_sr.c
> @@ -77,10 +77,7 @@ static bool compatible_entries(const struct xe_reg_sr_entry *e1,
> e1->clr_bits & e2->set_bits || e1->set_bits & e2->clr_bits)
> return false;
>
> - if (e1->masked_reg != e2->masked_reg)
> - return false;
> -
> - if (e1->reg_type != e2->reg_type)
> + if (e1->reg.raw != e2->reg.raw)
Similar to is_mcr_reg() or i915_mmio_reg_offset() I think there should
be an accessor to get the offset. Don't look at it directly.
One simple reason is that you may want to change the implementation
details in the future, and none of this code should have to be changed.
> return false;
>
> return true;
> @@ -93,10 +90,10 @@ static void reg_sr_inc_error(struct xe_reg_sr *sr)
> #endif
> }
>
> -int xe_reg_sr_add(struct xe_reg_sr *sr, u32 reg,
> +int xe_reg_sr_add(struct xe_reg_sr *sr, xe_reg_t reg,
> const struct xe_reg_sr_entry *e)
> {
> - unsigned long idx = reg;
> + unsigned long idx = reg.reg;
> struct xe_reg_sr_entry *pentry = xa_load(&sr->xa, idx);
> int ret;
>
> @@ -127,9 +124,11 @@ int xe_reg_sr_add(struct xe_reg_sr *sr, u32 reg,
> return 0;
>
> fail:
> - DRM_ERROR("Discarding save-restore reg %04lx (clear: %08x, set: %08x, masked: %s): ret=%d\n",
> + DRM_ERROR("Discarding save-restore reg %04lx (clear: %08x, set: %08x, masked: %s, mcr: %s): ret=%d\n",
> idx, e->clr_bits, e->set_bits,
> - str_yes_no(e->masked_reg), ret);
> + str_yes_no(e->reg.masked),
Ditto, is_masked_reg() or whatever.
> + str_yes_no(e->reg.mcr),
> + ret);
> reg_sr_inc_error(sr);
>
> return ret;
> @@ -149,10 +148,10 @@ static void apply_one_mmio(struct xe_gt *gt, u32 reg,
> * When it's not masked, we have to read it from hardware, unless we are
> * supposed to set all bits.
> */
> - if (entry->masked_reg)
> + if (entry->reg.masked)
> val = (entry->clr_bits ?: entry->set_bits << 16);
> else if (entry->clr_bits + 1)
> - val = (entry->reg_type == XE_RTP_REG_MCR ?
> + val = (entry->reg.mcr ?
> xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(reg)) :
> xe_mmio_read32(gt, reg)) & (~entry->clr_bits);
> else
> @@ -167,7 +166,7 @@ static void apply_one_mmio(struct xe_gt *gt, u32 reg,
>
> drm_dbg(&xe->drm, "REG[0x%x] = 0x%08x", reg, val);
>
> - if (entry->reg_type == XE_RTP_REG_MCR)
> + if (entry->reg.mcr)
> xe_gt_mcr_multicast_write(gt, XE_REG_MCR(reg), val);
> else
> xe_mmio_write32(gt, reg, val);
> @@ -259,6 +258,6 @@ void xe_reg_sr_dump(struct xe_reg_sr *sr, struct drm_printer *p)
> xa_for_each(&sr->xa, reg, entry)
> drm_printf(p, "\tREG[0x%lx] clr=0x%08x set=0x%08x masked=%s mcr=%s\n",
> reg, entry->clr_bits, entry->set_bits,
> - str_yes_no(entry->masked_reg),
> - str_yes_no(entry->reg_type == XE_RTP_REG_MCR));
> + str_yes_no(entry->reg.masked),
> + str_yes_no(entry->reg.mcr));
> }
> diff --git a/drivers/gpu/drm/xe/xe_reg_sr.h b/drivers/gpu/drm/xe/xe_reg_sr.h
> index 3af369089faa..2bdea4d119fe 100644
> --- a/drivers/gpu/drm/xe/xe_reg_sr.h
> +++ b/drivers/gpu/drm/xe/xe_reg_sr.h
> @@ -6,6 +6,7 @@
> #ifndef _XE_REG_SR_
> #define _XE_REG_SR_
>
> +#include "regs/xe_reg_defs.h"
> #include "xe_reg_sr_types.h"
>
> /*
> @@ -19,7 +20,7 @@ struct drm_printer;
> int xe_reg_sr_init(struct xe_reg_sr *sr, const char *name, struct xe_device *xe);
> void xe_reg_sr_dump(struct xe_reg_sr *sr, struct drm_printer *p);
>
> -int xe_reg_sr_add(struct xe_reg_sr *sr, u32 reg,
> +int xe_reg_sr_add(struct xe_reg_sr *sr, xe_reg_t reg,
> const struct xe_reg_sr_entry *e);
> void xe_reg_sr_apply_mmio(struct xe_reg_sr *sr, struct xe_gt *gt);
> void xe_reg_sr_apply_whitelist(struct xe_reg_sr *sr, u32 mmio_base,
> diff --git a/drivers/gpu/drm/xe/xe_reg_sr_types.h b/drivers/gpu/drm/xe/xe_reg_sr_types.h
> index 91469784fd90..eefbe20c0a22 100644
> --- a/drivers/gpu/drm/xe/xe_reg_sr_types.h
> +++ b/drivers/gpu/drm/xe/xe_reg_sr_types.h
> @@ -9,18 +9,14 @@
> #include <linux/types.h>
> #include <linux/xarray.h>
>
> +#include "regs/xe_reg_defs.h"
> +
> struct xe_reg_sr_entry {
> + xe_reg_t reg;
> u32 clr_bits;
> u32 set_bits;
> /* Mask for bits to consider when reading value back */
> u32 read_mask;
> - /*
> - * "Masked registers" are marked in spec as register with the upper 16
> - * bits as a mask for the bits that is being updated on the lower 16
> - * bits when writing to it.
> - */
> - u8 masked_reg;
> - u8 reg_type;
> };
>
> struct xe_reg_sr {
> diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
> index 310d5dfe30d5..e3e71b6060b2 100644
> --- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
> +++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
> @@ -11,11 +11,6 @@
> #include "xe_platform_types.h"
> #include "xe_rtp.h"
>
> -#undef XE_REG
> -#undef XE_REG_MCR
> -#define XE_REG(x, ...) _XE_RTP_REG(x)
> -#define XE_REG_MCR(x, ...) _XE_RTP_MCR_REG(x)
> -
> static bool match_not_render(const struct xe_gt *gt,
> const struct xe_hw_engine *hwe)
> {
> diff --git a/drivers/gpu/drm/xe/xe_rtp.c b/drivers/gpu/drm/xe/xe_rtp.c
> index 20acd43cb60b..b8c406b937df 100644
> --- a/drivers/gpu/drm/xe/xe_rtp.c
> +++ b/drivers/gpu/drm/xe/xe_rtp.c
> @@ -94,15 +94,16 @@ static void rtp_add_sr_entry(const struct xe_rtp_action *action,
> u32 mmio_base,
> struct xe_reg_sr *sr)
> {
> - u32 reg = action->reg + mmio_base;
> + xe_reg_t reg = action->reg;
> struct xe_reg_sr_entry sr_entry = {
> .clr_bits = action->clr_bits,
> .set_bits = action->set_bits,
> .read_mask = action->read_mask,
> - .masked_reg = action->flags & XE_RTP_ACTION_FLAG_MASKED_REG,
> - .reg_type = action->reg_type,
> };
>
> + reg.reg += mmio_base;
> + sr_entry.reg = reg;
> +
> xe_reg_sr_add(sr, reg, &sr_entry);
> }
>
> diff --git a/drivers/gpu/drm/xe/xe_rtp.h b/drivers/gpu/drm/xe/xe_rtp.h
> index 9148f32baa02..ca458e4b0d3c 100644
> --- a/drivers/gpu/drm/xe/xe_rtp.h
> +++ b/drivers/gpu/drm/xe/xe_rtp.h
> @@ -42,8 +42,8 @@ struct xe_reg_sr;
> #define __XE_PASTE_3(prefix_, sep_, args_) prefix_(_XE_FIRST args_) __XE_PASTE_SEP_ ## sep_ __XE_PASTE_2(prefix_, sep_, _XE_TUPLE_TAIL args_)
> #define __XE_PASTE_4(prefix_, sep_, args_) prefix_(_XE_FIRST args_) __XE_PASTE_SEP_ ## sep_ __XE_PASTE_3(prefix_, sep_, _XE_TUPLE_TAIL args_)
>
> -#define _XE_RTP_REG(x_) (x_), XE_RTP_REG_REGULAR
> -#define _XE_RTP_MCR_REG(x_) (x_), XE_RTP_REG_MCR
> +#define _XE_DROP_FIRST(x_, ...) __VA_ARGS__
> +#define _XE_DROP_CAST(...) _XE_ESC(_XE_DROP_FIRST _XE_ESC __VA_ARGS__)
>
> /*
> * Helper macros for concatenating prefix - do not use them directly outside
> @@ -196,7 +196,6 @@ struct xe_reg_sr;
> * XE_RTP_ACTION_WR - Helper to write a value to the register, overriding all
> * the bits
> * @reg_: Register
> - * @reg_type_: Register type - automatically expanded by XE_REG
> * @val_: Value to set
> * @...: Additional fields to override in the struct xe_rtp_action entry
> *
> @@ -204,15 +203,14 @@ struct xe_reg_sr;
> *
> * REGNAME = VALUE
> */
> -#define XE_RTP_ACTION_WR(reg_, reg_type_, val_, ...) \
> - { .reg = (reg_), .reg_type = (reg_type_), \
> +#define XE_RTP_ACTION_WR(reg_, val_, ...) \
> + { .reg = _XE_DROP_CAST(reg_), \
> .clr_bits = ~0u, .set_bits = (val_), \
> .read_mask = (~0u), ##__VA_ARGS__ }
>
> /**
> * XE_RTP_ACTION_SET - Set bits from @val_ in the register.
> * @reg_: Register
> - * @reg_type_: Register type - automatically expanded by XE_REG
> * @val_: Bits to set in the register
> * @...: Additional fields to override in the struct xe_rtp_action entry
> *
> @@ -223,15 +221,14 @@ struct xe_reg_sr;
> * REGNAME[2] = 1
> * REGNAME[5] = 1
> */
> -#define XE_RTP_ACTION_SET(reg_, reg_type_, val_, ...) \
> - { .reg = (reg_), .reg_type = (reg_type_), \
> - .clr_bits = (val_), .set_bits = (val_), \
> - .read_mask = (val_), ##__VA_ARGS__ }
> +#define XE_RTP_ACTION_SET(reg_, val_, ...) \
> + { .reg = _XE_DROP_CAST(reg_), \
> + .clr_bits = val_, .set_bits = val_, \
> + .read_mask = val_, ##__VA_ARGS__ }
>
> /**
> * XE_RTP_ACTION_CLR: Clear bits from @val_ in the register.
> * @reg_: Register
> - * @reg_type_: Register type - automatically expanded by XE_REG
> * @val_: Bits to clear in the register
> * @...: Additional fields to override in the struct xe_rtp_action entry
> *
> @@ -242,15 +239,14 @@ struct xe_reg_sr;
> * REGNAME[2] = 0
> * REGNAME[5] = 0
> */
> -#define XE_RTP_ACTION_CLR(reg_, reg_type_, val_, ...) \
> - { .reg = (reg_), .reg_type = (reg_type_), \
> - .clr_bits = (val_), .set_bits = 0, \
> - .read_mask = (val_), ##__VA_ARGS__ }
> +#define XE_RTP_ACTION_CLR(reg_, val_, ...) \
> + { .reg = _XE_DROP_CAST(reg_), \
> + .clr_bits = val_, .set_bits = 0, \
> + .read_mask = val_, ##__VA_ARGS__ }
>
> /**
> * XE_RTP_ACTION_FIELD_SET: Set a bit range
> * @reg_: Register
> - * @reg_type_: Register type - automatically expanded by XE_REG
> * @mask_bits_: Mask of bits to be changed in the register, forming a field
> * @val_: Value to set in the field denoted by @mask_bits_
> * @...: Additional fields to override in the struct xe_rtp_action entry
> @@ -260,29 +256,29 @@ struct xe_reg_sr;
> *
> * REGNAME[<end>:<start>] = VALUE
> */
> -#define XE_RTP_ACTION_FIELD_SET(reg_, reg_type_, mask_bits_, val_, ...) \
> - { .reg = (reg_), .reg_type = (reg_type_), \
> - .clr_bits = (mask_bits_), .set_bits = (val_), \
> - .read_mask = (mask_bits_), ##__VA_ARGS__ }
> +#define XE_RTP_ACTION_FIELD_SET(reg_, mask_bits_, val_, ...) \
> + { .reg = _XE_DROP_CAST(reg_), \
> + .clr_bits = mask_bits_, .set_bits = val_, \
> + .read_mask = mask_bits_, ##__VA_ARGS__ }
>
> -#define XE_RTP_ACTION_FIELD_SET_NO_READ_MASK(reg_, reg_type_, mask_bits_, val_, ...) \
> - { .reg = (reg_), .reg_type = (reg_type_), \
> +#define XE_RTP_ACTION_FIELD_SET_NO_READ_MASK(reg_, mask_bits_, val_, ...) \
> + { .reg = _XE_DROP_CAST(reg_), \
> .clr_bits = (mask_bits_), .set_bits = (val_), \
> .read_mask = 0, ##__VA_ARGS__ }
>
> /**
> * XE_RTP_ACTION_WHITELIST - Add register to userspace whitelist
> * @reg_: Register
> - * @reg_type_: Register type - automatically expanded by XE_REG
> * @val_: Whitelist-specific flags to set
> * @...: Additional fields to override in the struct xe_rtp_action entry
> *
> * Add a register to the whitelist, allowing userspace to modify the ster with
> * regular user privileges.
> */
> -#define XE_RTP_ACTION_WHITELIST(reg_, reg_type_, val_, ...) \
> +#define XE_RTP_ACTION_WHITELIST(reg_, val_, ...) \
> /* TODO fail build if ((flags) & ~(RING_FORCE_TO_NONPRIV_MASK_VALID)) */\
> - { .reg = (reg_), .reg_type = (reg_type_), .set_bits = (val_), \
> + { .reg = _XE_DROP_CAST(reg_), \
> + .set_bits = val_, \
> .clr_bits = RING_FORCE_TO_NONPRIV_MASK_VALID, \
> ##__VA_ARGS__ }
>
> diff --git a/drivers/gpu/drm/xe/xe_rtp_types.h b/drivers/gpu/drm/xe/xe_rtp_types.h
> index e87f1b280d96..4ad6b5453992 100644
> --- a/drivers/gpu/drm/xe/xe_rtp_types.h
> +++ b/drivers/gpu/drm/xe/xe_rtp_types.h
> @@ -8,14 +8,11 @@
>
> #include <linux/types.h>
>
> +#include "regs/xe_reg_defs.h"
> +
> struct xe_hw_engine;
> struct xe_gt;
>
> -enum {
> - XE_RTP_REG_REGULAR,
> - XE_RTP_REG_MCR,
> -};
> -
> /**
> * struct xe_rtp_action - action to take for any matching rule
> *
> @@ -24,7 +21,7 @@ enum {
> */
> struct xe_rtp_action {
> /** @reg: Register */
> - u32 reg;
> + xe_reg_t reg;
> /** @clr_bits: bits to clear when updating register */
> u32 clr_bits;
> /** @set_bits: bits to set when updating register */
> @@ -32,12 +29,9 @@ struct xe_rtp_action {
> #define XE_RTP_NOCHECK .read_mask = 0
> /** @read_mask: mask for bits to consider when reading value back */
> u32 read_mask;
> -#define XE_RTP_ACTION_FLAG_MASKED_REG BIT(0)
> -#define XE_RTP_ACTION_FLAG_ENGINE_BASE BIT(1)
> +#define XE_RTP_ACTION_FLAG_ENGINE_BASE BIT(0)
> /** @flags: flags to apply on rule evaluation or action */
> u8 flags;
> - /** @reg_type: register type, see ``XE_RTP_REG_*`` */
> - u8 reg_type;
> };
>
> enum {
> diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
> index f6eefa951175..041593387efc 100644
> --- a/drivers/gpu/drm/xe/xe_tuning.c
> +++ b/drivers/gpu/drm/xe/xe_tuning.c
> @@ -12,11 +12,6 @@
> #include "xe_platform_types.h"
> #include "xe_rtp.h"
>
> -#undef XE_REG
> -#undef XE_REG_MCR
> -#define XE_REG(x, ...) _XE_RTP_REG(x)
> -#define XE_REG_MCR(x, ...) _XE_RTP_MCR_REG(x)
> -
> static const struct xe_rtp_entry gt_tunings[] = {
> { XE_RTP_NAME("Tuning: Blend Fill Caching Optimization Disable"),
> XE_RTP_RULES(PLATFORM(DG2)),
> @@ -54,8 +49,7 @@ static const struct xe_rtp_entry lrc_tunings[] = {
> },
> { XE_RTP_NAME("Tuning: TBIMR fast clip"),
> XE_RTP_RULES(PLATFORM(DG2)),
> - XE_RTP_ACTIONS(SET(CHICKEN_RASTER_2, TBIMR_FAST_CLIP,
> - XE_RTP_ACTION_FLAG(MASKED_REG)))
> + XE_RTP_ACTIONS(SET(CHICKEN_RASTER_2, TBIMR_FAST_CLIP))
> },
> {}
> };
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> index b7dc71f63c8a..21ef74873553 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -87,11 +87,6 @@
> * a more declarative approach rather than procedural.
> */
>
> -#undef XE_REG
> -#undef XE_REG_MCR
> -#define XE_REG(x, ...) _XE_RTP_REG(x)
> -#define XE_REG_MCR(x, ...) _XE_RTP_MCR_REG(x)
> -
> __diag_push();
> __diag_ignore_all("-Woverride-init", "Allow field overrides in table");
>
> @@ -232,8 +227,7 @@ static const struct xe_rtp_entry gt_was[] = {
> },
> { XE_RTP_NAME("16016694945"),
> XE_RTP_RULES(PLATFORM(PVC)),
> - XE_RTP_ACTIONS(SET(XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC,
> - XE_RTP_ACTION_FLAG(MASKED_REG)))
> + XE_RTP_ACTIONS(SET(XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC))
> },
> {}
> };
> @@ -248,36 +242,30 @@ static const struct xe_rtp_entry engine_was[] = {
> XE_RTP_RULES(GRAPHICS_VERSION(1200),
> ENGINE_CLASS(RENDER),
> IS_INTEGRATED),
> - XE_RTP_ACTIONS(SET(ROW_CHICKEN2, PUSH_CONST_DEREF_HOLD_DIS,
> - XE_RTP_ACTION_FLAG(MASKED_REG)))
> + XE_RTP_ACTIONS(SET(ROW_CHICKEN2, PUSH_CONST_DEREF_HOLD_DIS))
> },
> { XE_RTP_NAME("14010229206, 1409085225"),
> XE_RTP_RULES(GRAPHICS_VERSION(1200),
> ENGINE_CLASS(RENDER),
> IS_INTEGRATED),
> - XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH,
> - XE_RTP_ACTION_FLAG(MASKED_REG)))
> + XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH))
> },
> { XE_RTP_NAME("1606931601"),
> XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
> - XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_EARLY_READ,
> - XE_RTP_ACTION_FLAG(MASKED_REG)))
> + XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_EARLY_READ))
> },
> { XE_RTP_NAME("14010826681, 1606700617, 22010271021, 18019627453"),
> XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1255), ENGINE_CLASS(RENDER)),
> - XE_RTP_ACTIONS(SET(CS_DEBUG_MODE1, FF_DOP_CLOCK_GATE_DISABLE,
> - XE_RTP_ACTION_FLAG(MASKED_REG)))
> + XE_RTP_ACTIONS(SET(CS_DEBUG_MODE1, FF_DOP_CLOCK_GATE_DISABLE))
> },
> { XE_RTP_NAME("1406941453"),
> XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
> - XE_RTP_ACTIONS(SET(SAMPLER_MODE, ENABLE_SMALLPL,
> - XE_RTP_ACTION_FLAG(MASKED_REG)))
> + XE_RTP_ACTIONS(SET(SAMPLER_MODE, ENABLE_SMALLPL))
> },
> { XE_RTP_NAME("FtrPerCtxtPreemptionGranularityControl"),
> XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1250), ENGINE_CLASS(RENDER)),
> XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN1,
> - FFSC_PERCTX_PREEMPT_CTRL,
> - XE_RTP_ACTION_FLAG(MASKED_REG)))
> + FFSC_PERCTX_PREEMPT_CTRL))
> },
>
> /* TGL */
> @@ -286,8 +274,7 @@ static const struct xe_rtp_entry engine_was[] = {
> XE_RTP_RULES(PLATFORM(TIGERLAKE), ENGINE_CLASS(RENDER)),
> XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
> WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
> - RC_SEMA_IDLE_MSG_DISABLE,
> - XE_RTP_ACTION_FLAG(MASKED_REG)))
> + RC_SEMA_IDLE_MSG_DISABLE))
> },
>
> /* RKL */
> @@ -296,8 +283,7 @@ static const struct xe_rtp_entry engine_was[] = {
> XE_RTP_RULES(PLATFORM(ROCKETLAKE), ENGINE_CLASS(RENDER)),
> XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
> WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
> - RC_SEMA_IDLE_MSG_DISABLE,
> - XE_RTP_ACTION_FLAG(MASKED_REG)))
> + RC_SEMA_IDLE_MSG_DISABLE))
> },
>
> /* ADL-P */
> @@ -306,8 +292,7 @@ static const struct xe_rtp_entry engine_was[] = {
> XE_RTP_RULES(PLATFORM(ALDERLAKE_P), ENGINE_CLASS(RENDER)),
> XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
> WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
> - RC_SEMA_IDLE_MSG_DISABLE,
> - XE_RTP_ACTION_FLAG(MASKED_REG)))
> + RC_SEMA_IDLE_MSG_DISABLE))
> },
>
> /* DG2 */
> @@ -324,8 +309,7 @@ static const struct xe_rtp_entry engine_was[] = {
> { XE_RTP_NAME("18017747507"),
> XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
> XE_RTP_ACTIONS(SET(VFG_PREEMPTION_CHICKEN,
> - POLYGON_TRIFAN_LINELOOP_DISABLE,
> - XE_RTP_ACTION_FLAG(MASKED_REG)))
> + POLYGON_TRIFAN_LINELOOP_DISABLE))
> },
> { XE_RTP_NAME("22012826095, 22013059131"),
> XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(B0, C0),
> @@ -366,15 +350,13 @@ static const struct xe_rtp_entry engine_was[] = {
> { XE_RTP_NAME("14015227452"),
> XE_RTP_RULES(PLATFORM(DG2),
> FUNC(xe_rtp_match_first_render_or_compute)),
> - XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE,
> - XE_RTP_ACTION_FLAG(MASKED_REG)))
> + XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE))
> },
> { XE_RTP_NAME("16015675438"),
> XE_RTP_RULES(PLATFORM(DG2),
> FUNC(xe_rtp_match_first_render_or_compute)),
> XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN2,
> - PERF_FIX_BALANCING_CFE_DISABLE,
> - XE_RTP_ACTION_FLAG(MASKED_REG)))
> + PERF_FIX_BALANCING_CFE_DISABLE))
> },
> { XE_RTP_NAME("16011620976, 22015475538"),
> XE_RTP_RULES(PLATFORM(DG2),
> @@ -385,7 +367,6 @@ static const struct xe_rtp_entry engine_was[] = {
> XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, C0),
> FUNC(xe_rtp_match_first_render_or_compute)),
> XE_RTP_ACTIONS(SET(CACHE_MODE_SS, ENABLE_PREFETCH_INTO_IC,
> - XE_RTP_ACTION_FLAG(MASKED_REG),
> /*
> * Register can't be read back for verification on
> * DG2 due to Wa_14012342262
> @@ -396,7 +377,6 @@ static const struct xe_rtp_entry engine_was[] = {
> XE_RTP_RULES(SUBPLATFORM(DG2, G11),
> FUNC(xe_rtp_match_first_render_or_compute)),
> XE_RTP_ACTIONS(SET(CACHE_MODE_SS, ENABLE_PREFETCH_INTO_IC,
> - XE_RTP_ACTION_FLAG(MASKED_REG),
> /*
> * Register can't be read back for verification on
> * DG2 due to Wa_14012342262
> @@ -405,55 +385,46 @@ static const struct xe_rtp_entry engine_was[] = {
> },
> { XE_RTP_NAME("1509727124"),
> XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
> - XE_RTP_ACTIONS(SET(SAMPLER_MODE, SC_DISABLE_POWER_OPTIMIZATION_EBB,
> - XE_RTP_ACTION_FLAG(MASKED_REG)))
> + XE_RTP_ACTIONS(SET(SAMPLER_MODE, SC_DISABLE_POWER_OPTIMIZATION_EBB))
> },
> { XE_RTP_NAME("22012856258"),
> XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
> - XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_READ_SUPPRESSION,
> - XE_RTP_ACTION_FLAG(MASKED_REG)))
> + XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_READ_SUPPRESSION))
> },
> { XE_RTP_NAME("14013392000"),
> XE_RTP_RULES(SUBPLATFORM(DG2, G11), STEP(A0, B0), ENGINE_CLASS(RENDER)),
> - XE_RTP_ACTIONS(SET(ROW_CHICKEN2, ENABLE_LARGE_GRF_MODE,
> - XE_RTP_ACTION_FLAG(MASKED_REG)))
> + XE_RTP_ACTIONS(SET(ROW_CHICKEN2, ENABLE_LARGE_GRF_MODE))
> },
> { XE_RTP_NAME("14012419201"),
> XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, B0), ENGINE_CLASS(RENDER)),
> XE_RTP_ACTIONS(SET(ROW_CHICKEN4,
> - DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX,
> - XE_RTP_ACTION_FLAG(MASKED_REG)))
> + DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX))
> },
> { XE_RTP_NAME("14012419201"),
> XE_RTP_RULES(SUBPLATFORM(DG2, G11), STEP(A0, B0), ENGINE_CLASS(RENDER)),
> XE_RTP_ACTIONS(SET(ROW_CHICKEN4,
> - DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX,
> - XE_RTP_ACTION_FLAG(MASKED_REG)))
> + DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX))
> },
> { XE_RTP_NAME("1308578152"),
> XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(B0, C0), ENGINE_CLASS(RENDER),
> FUNC(xe_rtp_match_first_gslice_fused_off)),
> XE_RTP_ACTIONS(CLR(CS_DEBUG_MODE1,
> - REPLAY_MODE_GRANULARITY,
> - XE_RTP_ACTION_FLAG(MASKED_REG)))
> + REPLAY_MODE_GRANULARITY))
> },
> { XE_RTP_NAME("22010960976, 14013347512"),
> XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
> XE_RTP_ACTIONS(CLR(XEHP_HDC_CHICKEN0,
> - LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK,
> - XE_RTP_ACTION_FLAG(MASKED_REG)))
> + LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK))
> },
> { XE_RTP_NAME("1608949956, 14010198302"),
> XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
> XE_RTP_ACTIONS(SET(ROW_CHICKEN,
> - MDQ_ARBITRATION_MODE | UGM_BACKUP_MODE,
> - XE_RTP_ACTION_FLAG(MASKED_REG)))
> + MDQ_ARBITRATION_MODE | UGM_BACKUP_MODE))
> },
> { XE_RTP_NAME("22010430635"),
> XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, B0), ENGINE_CLASS(RENDER)),
> XE_RTP_ACTIONS(SET(ROW_CHICKEN4,
> - DISABLE_GRF_CLEAR,
> - XE_RTP_ACTION_FLAG(MASKED_REG)))
> + DISABLE_GRF_CLEAR))
> },
> { XE_RTP_NAME("14013202645"),
> XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(B0, C0), ENGINE_CLASS(RENDER)),
> @@ -466,21 +437,18 @@ static const struct xe_rtp_entry engine_was[] = {
> { XE_RTP_NAME("22012532006"),
> XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, C0), ENGINE_CLASS(RENDER)),
> XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7,
> - DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA,
> - XE_RTP_ACTION_FLAG(MASKED_REG)))
> + DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA))
> },
> { XE_RTP_NAME("22012532006"),
> XE_RTP_RULES(SUBPLATFORM(DG2, G11), STEP(A0, B0), ENGINE_CLASS(RENDER)),
> XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7,
> - DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA,
> - XE_RTP_ACTION_FLAG(MASKED_REG)))
> + DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA))
> },
> { XE_RTP_NAME("22014600077"),
> XE_RTP_RULES(SUBPLATFORM(DG2, G11), STEP(B0, FOREVER),
> ENGINE_CLASS(RENDER)),
> XE_RTP_ACTIONS(SET(CACHE_MODE_SS,
> ENABLE_EU_COUNT_FOR_TDL_FLUSH,
> - XE_RTP_ACTION_FLAG(MASKED_REG),
> /*
> * Wa_14012342262 write-only reg, so skip
> * verification
> @@ -491,7 +459,6 @@ static const struct xe_rtp_entry engine_was[] = {
> XE_RTP_RULES(SUBPLATFORM(DG2, G10), ENGINE_CLASS(RENDER)),
> XE_RTP_ACTIONS(SET(CACHE_MODE_SS,
> ENABLE_EU_COUNT_FOR_TDL_FLUSH,
> - XE_RTP_ACTION_FLAG(MASKED_REG),
> /*
> * Wa_14012342262 write-only reg, so skip
> * verification
> @@ -507,18 +474,15 @@ static const struct xe_rtp_entry engine_was[] = {
> },
> { XE_RTP_NAME("14015227452"),
> XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)),
> - XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE,
> - XE_RTP_ACTION_FLAG(MASKED_REG)))
> + XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE))
> },
> { XE_RTP_NAME("16015675438"),
> XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)),
> - XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN2, PERF_FIX_BALANCING_CFE_DISABLE,
> - XE_RTP_ACTION_FLAG(MASKED_REG)))
> + XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN2, PERF_FIX_BALANCING_CFE_DISABLE))
> },
> { XE_RTP_NAME("14014999345"),
> XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COMPUTE), STEP(B0, C0)),
> - XE_RTP_ACTIONS(SET(CACHE_MODE_SS, DISABLE_ECC,
> - XE_RTP_ACTION_FLAG(MASKED_REG)))
> + XE_RTP_ACTIONS(SET(CACHE_MODE_SS, DISABLE_ECC))
> },
> {}
> };
> @@ -527,25 +491,21 @@ static const struct xe_rtp_entry lrc_was[] = {
> { XE_RTP_NAME("1409342910, 14010698770, 14010443199, 1408979724, 1409178076, 1409207793, 1409217633, 1409252684, 1409347922, 1409142259"),
> XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
> XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN3,
> - DISABLE_CPS_AWARE_COLOR_PIPE,
> - XE_RTP_ACTION_FLAG(MASKED_REG)))
> + DISABLE_CPS_AWARE_COLOR_PIPE))
> },
> { XE_RTP_NAME("WaDisableGPGPUMidThreadPreemption"),
> XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
> XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1,
> PREEMPT_GPGPU_LEVEL_MASK,
> - PREEMPT_GPGPU_THREAD_GROUP_LEVEL,
> - XE_RTP_ACTION_FLAG(MASKED_REG)))
> + PREEMPT_GPGPU_THREAD_GROUP_LEVEL))
> },
> { XE_RTP_NAME("1806527549"),
> XE_RTP_RULES(GRAPHICS_VERSION(1200)),
> - XE_RTP_ACTIONS(SET(HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE,
> - XE_RTP_ACTION_FLAG(MASKED_REG)))
> + XE_RTP_ACTIONS(SET(HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE))
> },
> { XE_RTP_NAME("1606376872"),
> XE_RTP_RULES(GRAPHICS_VERSION(1200)),
> - XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC,
> - XE_RTP_ACTION_FLAG(MASKED_REG)))
> + XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC))
> },
>
> /* DG1 */
> @@ -553,65 +513,54 @@ static const struct xe_rtp_entry lrc_was[] = {
> { XE_RTP_NAME("1409044764"),
> XE_RTP_RULES(PLATFORM(DG1)),
> XE_RTP_ACTIONS(CLR(COMMON_SLICE_CHICKEN3,
> - DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN,
> - XE_RTP_ACTION_FLAG(MASKED_REG)))
> + DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN))
> },
> { XE_RTP_NAME("22010493298"),
> XE_RTP_RULES(PLATFORM(DG1)),
> XE_RTP_ACTIONS(SET(HIZ_CHICKEN,
> - DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE,
> - XE_RTP_ACTION_FLAG(MASKED_REG)))
> + DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE))
> },
>
> /* DG2 */
>
> { XE_RTP_NAME("16011186671"),
> XE_RTP_RULES(SUBPLATFORM(DG2, G11), STEP(A0, B0)),
> - XE_RTP_ACTIONS(CLR(VFLSKPD, DIS_MULT_MISS_RD_SQUASH,
> - .flags = XE_RTP_ACTION_FLAG_MASKED_REG),
> - SET(VFLSKPD, DIS_OVER_FETCH_CACHE,
> - .flags = XE_RTP_ACTION_FLAG_MASKED_REG))
> + XE_RTP_ACTIONS(CLR(VFLSKPD, DIS_MULT_MISS_RD_SQUASH),
> + SET(VFLSKPD, DIS_OVER_FETCH_CACHE))
> },
> { XE_RTP_NAME("14010469329"),
> XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, B0)),
> XE_RTP_ACTIONS(SET(XEHP_COMMON_SLICE_CHICKEN3,
> - XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE,
> - XE_RTP_ACTION_FLAG(MASKED_REG)))
> + XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE))
> },
> { XE_RTP_NAME("14010698770, 22010613112, 22010465075"),
> XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, B0)),
> XE_RTP_ACTIONS(SET(XEHP_COMMON_SLICE_CHICKEN3,
> - DISABLE_CPS_AWARE_COLOR_PIPE,
> - XE_RTP_ACTION_FLAG(MASKED_REG)))
> + DISABLE_CPS_AWARE_COLOR_PIPE))
> },
> { XE_RTP_NAME("16013271637"),
> XE_RTP_RULES(PLATFORM(DG2)),
> XE_RTP_ACTIONS(SET(XEHP_SLICE_COMMON_ECO_CHICKEN1,
> - MSC_MSAA_REODER_BUF_BYPASS_DISABLE,
> - XE_RTP_ACTION_FLAG(MASKED_REG)))
> + MSC_MSAA_REODER_BUF_BYPASS_DISABLE))
> },
> { XE_RTP_NAME("14014947963"),
> XE_RTP_RULES(PLATFORM(DG2)),
> XE_RTP_ACTIONS(FIELD_SET(VF_PREEMPTION,
> PREEMPTION_VERTEX_COUNT,
> - 0x4000,
> - XE_RTP_ACTION_FLAG(MASKED_REG)))
> + 0x4000))
> },
> { XE_RTP_NAME("18018764978"),
> XE_RTP_RULES(PLATFORM(DG2)),
> XE_RTP_ACTIONS(SET(XEHP_PSS_MODE2,
> - SCOREBOARD_STALL_FLUSH_CONTROL,
> - XE_RTP_ACTION_FLAG(MASKED_REG)))
> + SCOREBOARD_STALL_FLUSH_CONTROL))
> },
> { XE_RTP_NAME("15010599737"),
> XE_RTP_RULES(PLATFORM(DG2)),
> - XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN,
> - XE_RTP_ACTION_FLAG(MASKED_REG)))
> + XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN))
> },
> { XE_RTP_NAME("18019271663"),
> XE_RTP_RULES(PLATFORM(DG2)),
> - XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE,
> - XE_RTP_ACTION_FLAG(MASKED_REG)))
> + XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE))
> },
> {}
> };
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [Intel-xe] [PATCH 17/17] drm/xe: Move helper macros to separate header
2023-04-19 7:44 ` [Intel-xe] [PATCH 17/17] drm/xe: Move helper macros to separate header Lucas De Marchi
@ 2023-04-19 16:17 ` Jani Nikula
2023-04-19 17:06 ` Lucas De Marchi
0 siblings, 1 reply; 41+ messages in thread
From: Jani Nikula @ 2023-04-19 16:17 UTC (permalink / raw)
To: Lucas De Marchi, intel-xe; +Cc: Matt Roper, Lucas De Marchi, Rodrigo Vivi
On Wed, 19 Apr 2023, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> The macros to handle the RTP tables are very scary, but shouldn't be
> used outside of the header adding the infra. Move it to a separate
> header and make sure it's only included when it can be.
I've wondered if the macros are more trouble than they're worth...
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/xe/Makefile | 2 +-
> drivers/gpu/drm/xe/tests/xe_rtp_test.c | 2 +-
> drivers/gpu/drm/xe/xe_rtp.h | 40 +++------------------
> drivers/gpu/drm/xe/xe_rtp_helpers.h | 48 ++++++++++++++++++++++++++
> 4 files changed, 55 insertions(+), 37 deletions(-)
> create mode 100644 drivers/gpu/drm/xe/xe_rtp_helpers.h
>
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index aceca651de57..f3c38815011e 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -225,7 +225,7 @@ endif
>
> # header test
> always-$(CONFIG_DRM_XE_WERROR) += \
> - $(patsubst %.h,%.hdrtest, $(shell cd $(srctree)/$(src) && find * -name '*.h' $(skipdisplay)))
> + $(patsubst %.h,%.hdrtest, $(shell cd $(srctree)/$(src) && find * -name '*.h' -not -path xe_rtp_helpers.h $(skipdisplay)))
>
> quiet_cmd_hdrtest = HDRTEST $(patsubst %.hdrtest,%.h,$@)
> cmd_hdrtest = $(CC) -DHDRTEST $(filter-out $(CFLAGS_GCOV), $(c_flags)) $(cflags-display) -S -o /dev/null -x c /dev/null -include $<; touch $@
> diff --git a/drivers/gpu/drm/xe/tests/xe_rtp_test.c b/drivers/gpu/drm/xe/tests/xe_rtp_test.c
> index ad917638d088..a5ec9ae22156 100644
> --- a/drivers/gpu/drm/xe/tests/xe_rtp_test.c
> +++ b/drivers/gpu/drm/xe/tests/xe_rtp_test.c
> @@ -57,7 +57,7 @@ static const struct rtp_test_case cases[] = {
> .entries = (const struct xe_rtp_entry[]) {
> { XE_RTP_NAME("basic-1"),
> XE_RTP_RULES(FUNC(match_yes)),
> - XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(1)))
> + XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
Ah, this was changed earlier in the series.
> },
> { XE_RTP_NAME("basic-2"),
> XE_RTP_RULES(FUNC(match_yes)),
> diff --git a/drivers/gpu/drm/xe/xe_rtp.h b/drivers/gpu/drm/xe/xe_rtp.h
> index ca458e4b0d3c..7242342f4971 100644
> --- a/drivers/gpu/drm/xe/xe_rtp.h
> +++ b/drivers/gpu/drm/xe/xe_rtp.h
> @@ -9,8 +9,13 @@
> #include <linux/types.h>
> #include <linux/xarray.h>
>
> +#define _XE_RTP_INCLUDE_PRIVATE_HELPERS
> +
> +#include "xe_rtp_helpers.h"
> #include "xe_rtp_types.h"
>
> +#undef _XE_RTP_INCLUDE_PRIVATE_HELPERS
> +
> /*
> * Register table poke infrastructure
> */
> @@ -19,41 +24,6 @@ struct xe_hw_engine;
> struct xe_gt;
> struct xe_reg_sr;
>
> -/*
> - * Helper macros - not to be used outside this header.
> - */
> -#define _XE_ESC(...) __VA_ARGS__
> -#define _XE_COUNT_ARGS(...) _XE_ESC(__XE_COUNT_ARGS(__VA_ARGS__,5,4,3,2,1,))
> -#define __XE_COUNT_ARGS(_,_5,_4,_3,_2,X_,...) X_
> -
> -#define _XE_CONCAT(a, b) __XE_CONCAT(a, b)
> -#define __XE_CONCAT(a, b) a ## b
> -
> -#define _XE_FIRST(...) _XE_ESC(__XE_FIRST(__VA_ARGS__,))
> -#define __XE_FIRST(x_,...) x_
> -#define _XE_TUPLE_TAIL(...) _XE_ESC(__XE_TUPLE_TAIL(__VA_ARGS__))
> -#define __XE_TUPLE_TAIL(x_,...) (__VA_ARGS__)
> -
> -#define __XE_PASTE_SEP_COMMA ,
> -#define __XE_PASTE_SEP_BITWISE_OR |
> -#define __XE_PASTE(prefix_, sep_, args_) _XE_ESC(_XE_CONCAT(__XE_PASTE_,_XE_COUNT_ARGS args_)(prefix_, sep_, args_))
> -#define __XE_PASTE_1(prefix_, sep_, args_) prefix_ args_
> -#define __XE_PASTE_2(prefix_, sep_, args_) prefix_(_XE_FIRST args_) __XE_PASTE_SEP_ ## sep_ __XE_PASTE_1(prefix_, sep_, _XE_TUPLE_TAIL args_)
> -#define __XE_PASTE_3(prefix_, sep_, args_) prefix_(_XE_FIRST args_) __XE_PASTE_SEP_ ## sep_ __XE_PASTE_2(prefix_, sep_, _XE_TUPLE_TAIL args_)
> -#define __XE_PASTE_4(prefix_, sep_, args_) prefix_(_XE_FIRST args_) __XE_PASTE_SEP_ ## sep_ __XE_PASTE_3(prefix_, sep_, _XE_TUPLE_TAIL args_)
> -
> -#define _XE_DROP_FIRST(x_, ...) __VA_ARGS__
> -#define _XE_DROP_CAST(...) _XE_ESC(_XE_DROP_FIRST _XE_ESC __VA_ARGS__)
> -
> -/*
> - * Helper macros for concatenating prefix - do not use them directly outside
> - * this header
> - */
> -#define __XE_PASTE_XE_RTP_ENTRY_FLAG_(x_) _XE_CONCAT(XE_RTP_ENTRY_FLAG_, x_)
> -#define __XE_PASTE_XE_RTP_ACTION_FLAG_(x_) _XE_CONCAT(XE_RTP_ACTION_FLAG_, x_)
> -#define __XE_PASTE_XE_RTP_ACTION_(x_) _XE_CONCAT(XE_RTP_ACTION_, x_)
> -#define __XE_PASTE_XE_RTP_RULE_(x_) _XE_CONCAT(XE_RTP_RULE_, x_)
> -
> /*
> * Macros to encode rules to match against platform, IP version, stepping, etc.
> * Shouldn't be used directly - see XE_RTP_RULES()
> diff --git a/drivers/gpu/drm/xe/xe_rtp_helpers.h b/drivers/gpu/drm/xe/xe_rtp_helpers.h
> new file mode 100644
> index 000000000000..0f0635692254
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_rtp_helpers.h
> @@ -0,0 +1,48 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#ifndef _XE_RTP_HELPERS_
> +#define _XE_RTP_HELPERS_
> +
> +#ifndef _XE_RTP_INCLUDE_PRIVATE_HELPERS
> +#error "This header is supposed to be included by xe_rtp.h only"
> +#endif
> +
> +/*
> + * Helper macros - not to be used outside xe_rtp.h/xe_rtp_helpers.h
> + */
> +#define _XE_ESC(...) __VA_ARGS__
> +#define _XE_COUNT_ARGS(...) _XE_ESC(__XE_COUNT_ARGS(__VA_ARGS__,5,4,3,2,1,))
> +#define __XE_COUNT_ARGS(_,_5,_4,_3,_2,X_,...) X_
> +
> +#define _XE_CONCAT(a, b) __XE_CONCAT(a, b)
> +#define __XE_CONCAT(a, b) a ## b
> +
> +#define _XE_FIRST(...) _XE_ESC(__XE_FIRST(__VA_ARGS__,))
> +#define __XE_FIRST(x_,...) x_
> +#define _XE_TUPLE_TAIL(...) _XE_ESC(__XE_TUPLE_TAIL(__VA_ARGS__))
> +#define __XE_TUPLE_TAIL(x_,...) (__VA_ARGS__)
> +
> +#define __XE_PASTE_SEP_COMMA ,
> +#define __XE_PASTE_SEP_BITWISE_OR |
> +#define __XE_PASTE(prefix_, sep_, args_) _XE_ESC(_XE_CONCAT(__XE_PASTE_,_XE_COUNT_ARGS args_)(prefix_, sep_, args_))
> +#define __XE_PASTE_1(prefix_, sep_, args_) prefix_ args_
> +#define __XE_PASTE_2(prefix_, sep_, args_) prefix_(_XE_FIRST args_) __XE_PASTE_SEP_ ## sep_ __XE_PASTE_1(prefix_, sep_, _XE_TUPLE_TAIL args_)
> +#define __XE_PASTE_3(prefix_, sep_, args_) prefix_(_XE_FIRST args_) __XE_PASTE_SEP_ ## sep_ __XE_PASTE_2(prefix_, sep_, _XE_TUPLE_TAIL args_)
> +#define __XE_PASTE_4(prefix_, sep_, args_) prefix_(_XE_FIRST args_) __XE_PASTE_SEP_ ## sep_ __XE_PASTE_3(prefix_, sep_, _XE_TUPLE_TAIL args_)
> +
> +#define _XE_DROP_FIRST(x_, ...) __VA_ARGS__
> +#define _XE_DROP_CAST(...) _XE_ESC(_XE_DROP_FIRST _XE_ESC __VA_ARGS__)
> +
> +/*
> + * Helper macros for concatenating prefix - do not use them directly outside
> + * this header
> + */
> +#define __XE_PASTE_XE_RTP_ENTRY_FLAG_(x_) _XE_CONCAT(XE_RTP_ENTRY_FLAG_, x_)
> +#define __XE_PASTE_XE_RTP_ACTION_FLAG_(x_) _XE_CONCAT(XE_RTP_ACTION_FLAG_, x_)
> +#define __XE_PASTE_XE_RTP_ACTION_(x_) _XE_CONCAT(XE_RTP_ACTION_, x_)
> +#define __XE_PASTE_XE_RTP_RULE_(x_) _XE_CONCAT(XE_RTP_RULE_, x_)
> +
> +#endif
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [Intel-xe] [PATCH 17/17] drm/xe: Move helper macros to separate header
2023-04-19 16:17 ` Jani Nikula
@ 2023-04-19 17:06 ` Lucas De Marchi
0 siblings, 0 replies; 41+ messages in thread
From: Lucas De Marchi @ 2023-04-19 17:06 UTC (permalink / raw)
To: Jani Nikula; +Cc: Matt Roper, intel-xe, Rodrigo Vivi
On Wed, Apr 19, 2023 at 07:17:14PM +0300, Jani Nikula wrote:
>On Wed, 19 Apr 2023, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>> The macros to handle the RTP tables are very scary, but shouldn't be
>> used outside of the header adding the infra. Move it to a separate
>> header and make sure it's only included when it can be.
>
>I've wondered if the macros are more trouble than they're worth...
The problem is that writting the tables would become very very verbose,
to the point of not being feasible (and error-prone). I think the
alternative would be to eventually move out of .c and just write it in a
format that generates the .c. It comes with its own downsides though.
>
>>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>> drivers/gpu/drm/xe/Makefile | 2 +-
>> drivers/gpu/drm/xe/tests/xe_rtp_test.c | 2 +-
>> drivers/gpu/drm/xe/xe_rtp.h | 40 +++------------------
>> drivers/gpu/drm/xe/xe_rtp_helpers.h | 48 ++++++++++++++++++++++++++
>> 4 files changed, 55 insertions(+), 37 deletions(-)
>> create mode 100644 drivers/gpu/drm/xe/xe_rtp_helpers.h
>>
>> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
>> index aceca651de57..f3c38815011e 100644
>> --- a/drivers/gpu/drm/xe/Makefile
>> +++ b/drivers/gpu/drm/xe/Makefile
>> @@ -225,7 +225,7 @@ endif
>>
>> # header test
>> always-$(CONFIG_DRM_XE_WERROR) += \
>> - $(patsubst %.h,%.hdrtest, $(shell cd $(srctree)/$(src) && find * -name '*.h' $(skipdisplay)))
>> + $(patsubst %.h,%.hdrtest, $(shell cd $(srctree)/$(src) && find * -name '*.h' -not -path xe_rtp_helpers.h $(skipdisplay)))
>>
>> quiet_cmd_hdrtest = HDRTEST $(patsubst %.hdrtest,%.h,$@)
>> cmd_hdrtest = $(CC) -DHDRTEST $(filter-out $(CFLAGS_GCOV), $(c_flags)) $(cflags-display) -S -o /dev/null -x c /dev/null -include $<; touch $@
>> diff --git a/drivers/gpu/drm/xe/tests/xe_rtp_test.c b/drivers/gpu/drm/xe/tests/xe_rtp_test.c
>> index ad917638d088..a5ec9ae22156 100644
>> --- a/drivers/gpu/drm/xe/tests/xe_rtp_test.c
>> +++ b/drivers/gpu/drm/xe/tests/xe_rtp_test.c
>> @@ -57,7 +57,7 @@ static const struct rtp_test_case cases[] = {
>> .entries = (const struct xe_rtp_entry[]) {
>> { XE_RTP_NAME("basic-1"),
>> XE_RTP_RULES(FUNC(match_yes)),
>> - XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(1)))
>> + XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
>
>Ah, this was changed earlier in the series.
yeah... I noticed the kunit regression just before submitting and ended up
squashing the fix in the wrong place.
thanks
Lucas De Marchi
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [Intel-xe] [PATCH 11/17] drm/xe: Introduce xe_reg_t
2023-04-19 16:06 ` Jani Nikula
@ 2023-04-19 17:17 ` Lucas De Marchi
2023-04-19 19:39 ` Jani Nikula
0 siblings, 1 reply; 41+ messages in thread
From: Lucas De Marchi @ 2023-04-19 17:17 UTC (permalink / raw)
To: Jani Nikula; +Cc: Matt Roper, intel-xe, Rodrigo Vivi
On Wed, Apr 19, 2023 at 07:06:51PM +0300, Jani Nikula wrote:
>On Wed, 19 Apr 2023, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>> Stop using i915 types for register our own xe_reg_t. Differently from
>> i915, this will keep under this will keep under the register definition
>> the knowledge for the different types of registers. For now, the "flags"
>> are mcr and masked, although only the former is being used.
>>
>> Most of the driver is agnostic to the register differences. Convert the
>> few places that care about that, namely xe_gt_mcr.c, to take the generic
>> type and warn if the wrong register is used.
>>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>> drivers/gpu/drm/xe/regs/xe_reg_defs.h | 15 +++++++++++++++
>> drivers/gpu/drm/xe/xe_gt_mcr.c | 22 ++++++++++++++++------
>> drivers/gpu/drm/xe/xe_gt_mcr.h | 8 ++++----
>> drivers/gpu/drm/xe/xe_irq.c | 2 +-
>> drivers/gpu/drm/xe/xe_mmio.c | 2 +-
>> 5 files changed, 37 insertions(+), 12 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/regs/xe_reg_defs.h b/drivers/gpu/drm/xe/regs/xe_reg_defs.h
>> index b5c25e31b889..1e78508c737b 100644
>> --- a/drivers/gpu/drm/xe/regs/xe_reg_defs.h
>> +++ b/drivers/gpu/drm/xe/regs/xe_reg_defs.h
>> @@ -8,4 +8,19 @@
>>
>> #include "compat-i915-headers/i915_reg_defs.h"
>>
>> +typedef union {
>> + struct {
>> + u32 reg:30;
>> + u32 mcr:1;
>> + u32 masked:1;
>> + };
>> + u32 raw;
>> +} xe_reg_t;
>> +
>> +/* TODO: remove these once the register declarations are not using them anymore */
>> +#undef _MMIO
>> +#undef MCR_REG
>> +#define _MMIO(r) ((const xe_reg_t){ .reg = (r) })
>> +#define MCR_REG(r) ((const xe_reg_t){ .reg = (r), .mcr = 1 })
>> +
>> #endif
>> diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
>> index aa04ba5a6dbe..b9631cfd5b81 100644
>> --- a/drivers/gpu/drm/xe/xe_gt_mcr.c
>> +++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
>> @@ -360,11 +360,13 @@ void xe_gt_mcr_set_implicit_defaults(struct xe_gt *gt)
>> * returned. Returns false if the caller need not perform any steering
>> */
>> static bool xe_gt_mcr_get_nonterminated_steering(struct xe_gt *gt,
>> - i915_mcr_reg_t reg,
>> + xe_reg_t reg,
>> u8 *group, u8 *instance)
>> {
>> const struct xe_mmio_range *implicit_ranges;
>>
>> + drm_WARN_ON(>_to_xe(gt)->drm, !reg.mcr);
>
>I'd add some is_mcr_reg() style macro and use it throughout instead of
>poking directly at xe_reg_t guts. The idea should be that xe_reg_t is
>opaque.
humn... in xe the tendency is not to hide too much as it creates a
unneeded level of indirection. I don't see us needing to change
xe_reg_t much in future or make it depend on platform, etc. I think a
helper like that could be added if we end up with such need.
*changing* the values underneath the struct is probably something that
we should avoid doing (there are a few places we do though to account
for base offset), but I don't see a problem *reading* it. We should
probably sprinkle some const around.
The extra verbosity imposed by the wrapper function call doesn't bring
much benefit IMO.
Lucas De Marchi
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [Intel-xe] [PATCH 11/17] drm/xe: Introduce xe_reg_t
2023-04-19 7:44 ` [Intel-xe] [PATCH 11/17] drm/xe: Introduce xe_reg_t Lucas De Marchi
2023-04-19 16:06 ` Jani Nikula
@ 2023-04-19 17:33 ` Matt Roper
2023-04-19 18:49 ` Lucas De Marchi
2023-04-19 19:49 ` Jani Nikula
1 sibling, 2 replies; 41+ messages in thread
From: Matt Roper @ 2023-04-19 17:33 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-xe, Rodrigo Vivi
On Wed, Apr 19, 2023 at 12:44:34AM -0700, Lucas De Marchi wrote:
> Stop using i915 types for register our own xe_reg_t. Differently from
> i915, this will keep under this will keep under the register definition
> the knowledge for the different types of registers. For now, the "flags"
> are mcr and masked, although only the former is being used.
>
> Most of the driver is agnostic to the register differences. Convert the
> few places that care about that, namely xe_gt_mcr.c, to take the generic
> type and warn if the wrong register is used.
The disadvantage of this approach is that we don't get the nice
type-checking that we have in i915 to catch register misuse at build
time. Instead we wind up with a bunch of run-time checks that only tell
you that you used the wrong register semantics after the fact. Wouldn't
it be better to keep the strict types and let the compiler find mistakes
for us at build time?
The only real problem with using strict types is that there are a few
places where the driver is just trying to refer to registers/offsets
without actually accessing them (e.g., whitelists, OA register groups,
etc.) and the strict typing makes it harder to provide a heterogeneous
list of those registers. But I still feel the benefits of compile-time
checking outweighs the extra complexity we wind up with in a handful of
places.
Matt
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/xe/regs/xe_reg_defs.h | 15 +++++++++++++++
> drivers/gpu/drm/xe/xe_gt_mcr.c | 22 ++++++++++++++++------
> drivers/gpu/drm/xe/xe_gt_mcr.h | 8 ++++----
> drivers/gpu/drm/xe/xe_irq.c | 2 +-
> drivers/gpu/drm/xe/xe_mmio.c | 2 +-
> 5 files changed, 37 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_reg_defs.h b/drivers/gpu/drm/xe/regs/xe_reg_defs.h
> index b5c25e31b889..1e78508c737b 100644
> --- a/drivers/gpu/drm/xe/regs/xe_reg_defs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_reg_defs.h
> @@ -8,4 +8,19 @@
>
> #include "compat-i915-headers/i915_reg_defs.h"
>
> +typedef union {
> + struct {
> + u32 reg:30;
> + u32 mcr:1;
> + u32 masked:1;
> + };
> + u32 raw;
> +} xe_reg_t;
> +
> +/* TODO: remove these once the register declarations are not using them anymore */
> +#undef _MMIO
> +#undef MCR_REG
> +#define _MMIO(r) ((const xe_reg_t){ .reg = (r) })
> +#define MCR_REG(r) ((const xe_reg_t){ .reg = (r), .mcr = 1 })
> +
> #endif
> diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
> index aa04ba5a6dbe..b9631cfd5b81 100644
> --- a/drivers/gpu/drm/xe/xe_gt_mcr.c
> +++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
> @@ -360,11 +360,13 @@ void xe_gt_mcr_set_implicit_defaults(struct xe_gt *gt)
> * returned. Returns false if the caller need not perform any steering
> */
> static bool xe_gt_mcr_get_nonterminated_steering(struct xe_gt *gt,
> - i915_mcr_reg_t reg,
> + xe_reg_t reg,
> u8 *group, u8 *instance)
> {
> const struct xe_mmio_range *implicit_ranges;
>
> + drm_WARN_ON(>_to_xe(gt)->drm, !reg.mcr);
> +
> for (int type = 0; type < IMPLICIT_STEERING; type++) {
> if (!gt->steering[type].ranges)
> continue;
> @@ -436,11 +438,13 @@ static void mcr_unlock(struct xe_gt *gt) {
> *
> * Caller needs to make sure the relevant forcewake wells are up.
> */
> -static u32 rw_with_mcr_steering(struct xe_gt *gt, i915_mcr_reg_t reg, u8 rw_flag,
> +static u32 rw_with_mcr_steering(struct xe_gt *gt, xe_reg_t reg, u8 rw_flag,
> int group, int instance, u32 value)
> {
> u32 steer_reg, steer_val, val = 0;
>
> + drm_WARN_ON(>_to_xe(gt)->drm, !reg.mcr);
> +
> lockdep_assert_held(>->mcr_lock);
>
> if (GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270) {
> @@ -494,12 +498,14 @@ static u32 rw_with_mcr_steering(struct xe_gt *gt, i915_mcr_reg_t reg, u8 rw_flag
> *
> * Returns the value from a non-terminated instance of @reg.
> */
> -u32 xe_gt_mcr_unicast_read_any(struct xe_gt *gt, i915_mcr_reg_t reg)
> +u32 xe_gt_mcr_unicast_read_any(struct xe_gt *gt, xe_reg_t reg)
> {
> u8 group, instance;
> u32 val;
> bool steer;
>
> + drm_WARN_ON(>_to_xe(gt)->drm, !reg.mcr);
> +
> steer = xe_gt_mcr_get_nonterminated_steering(gt, reg, &group, &instance);
>
> if (steer) {
> @@ -525,11 +531,13 @@ u32 xe_gt_mcr_unicast_read_any(struct xe_gt *gt, i915_mcr_reg_t reg)
> * group/instance.
> */
> u32 xe_gt_mcr_unicast_read(struct xe_gt *gt,
> - i915_mcr_reg_t reg,
> + xe_reg_t reg,
> int group, int instance)
> {
> u32 val;
>
> + drm_WARN_ON(>_to_xe(gt)->drm, !reg.mcr);
> +
> mcr_lock(gt);
> val = rw_with_mcr_steering(gt, reg, MCR_OP_READ, group, instance, 0);
> mcr_unlock(gt);
> @@ -548,9 +556,11 @@ u32 xe_gt_mcr_unicast_read(struct xe_gt *gt,
> * Write an MCR register in unicast mode after steering toward a specific
> * group/instance.
> */
> -void xe_gt_mcr_unicast_write(struct xe_gt *gt, i915_mcr_reg_t reg, u32 value,
> +void xe_gt_mcr_unicast_write(struct xe_gt *gt, xe_reg_t reg, u32 value,
> int group, int instance)
> {
> + drm_WARN_ON(>_to_xe(gt)->drm, !reg.mcr);
> +
> mcr_lock(gt);
> rw_with_mcr_steering(gt, reg, MCR_OP_WRITE, group, instance, value);
> mcr_unlock(gt);
> @@ -564,7 +574,7 @@ void xe_gt_mcr_unicast_write(struct xe_gt *gt, i915_mcr_reg_t reg, u32 value,
> *
> * Write an MCR register in multicast mode to update all instances.
> */
> -void xe_gt_mcr_multicast_write(struct xe_gt *gt, i915_mcr_reg_t reg, u32 value)
> +void xe_gt_mcr_multicast_write(struct xe_gt *gt, xe_reg_t reg, u32 value)
> {
> /*
> * Synchronize with any unicast operations. Once we have exclusive
> diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.h b/drivers/gpu/drm/xe/xe_gt_mcr.h
> index 2a6cd38c8cb7..492d9519784a 100644
> --- a/drivers/gpu/drm/xe/xe_gt_mcr.h
> +++ b/drivers/gpu/drm/xe/xe_gt_mcr.h
> @@ -15,13 +15,13 @@ void xe_gt_mcr_init(struct xe_gt *gt);
>
> void xe_gt_mcr_set_implicit_defaults(struct xe_gt *gt);
>
> -u32 xe_gt_mcr_unicast_read(struct xe_gt *gt, i915_mcr_reg_t reg,
> +u32 xe_gt_mcr_unicast_read(struct xe_gt *gt, xe_reg_t reg,
> int group, int instance);
> -u32 xe_gt_mcr_unicast_read_any(struct xe_gt *gt, i915_mcr_reg_t reg);
> +u32 xe_gt_mcr_unicast_read_any(struct xe_gt *gt, xe_reg_t reg);
>
> -void xe_gt_mcr_unicast_write(struct xe_gt *gt, i915_mcr_reg_t reg, u32 value,
> +void xe_gt_mcr_unicast_write(struct xe_gt *gt, xe_reg_t reg, u32 value,
> int group, int instance);
> -void xe_gt_mcr_multicast_write(struct xe_gt *gt, i915_mcr_reg_t reg, u32 value);
> +void xe_gt_mcr_multicast_write(struct xe_gt *gt, xe_reg_t reg, u32 value);
>
> void xe_gt_mcr_steering_dump(struct xe_gt *gt, struct drm_printer *p);
>
> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> index 13f9f220bca0..8e5f8e7c16c8 100644
> --- a/drivers/gpu/drm/xe/xe_irq.c
> +++ b/drivers/gpu/drm/xe/xe_irq.c
> @@ -27,7 +27,7 @@
> #define IIR(offset) _MMIO(offset + 0x8)
> #define IER(offset) _MMIO(offset + 0xc)
>
> -static void assert_iir_is_zero(struct xe_gt *gt, i915_reg_t reg)
> +static void assert_iir_is_zero(struct xe_gt *gt, xe_reg_t reg)
> {
> u32 val = xe_mmio_read32(gt, reg.reg);
>
> diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
> index a93838e23b7b..1029b9f27988 100644
> --- a/drivers/gpu/drm/xe/xe_mmio.c
> +++ b/drivers/gpu/drm/xe/xe_mmio.c
> @@ -397,7 +397,7 @@ int xe_mmio_init(struct xe_device *xe)
> DRM_XE_MMIO_READ |\
> DRM_XE_MMIO_WRITE)
>
> -static const i915_reg_t mmio_read_whitelist[] = {
> +static const xe_reg_t mmio_read_whitelist[] = {
> RING_TIMESTAMP(RENDER_RING_BASE),
> };
>
> --
> 2.39.0
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [Intel-xe] [PATCH 11/17] drm/xe: Introduce xe_reg_t
2023-04-19 17:33 ` Matt Roper
@ 2023-04-19 18:49 ` Lucas De Marchi
2023-04-19 19:30 ` Rodrigo Vivi
2023-04-19 19:49 ` Jani Nikula
1 sibling, 1 reply; 41+ messages in thread
From: Lucas De Marchi @ 2023-04-19 18:49 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe, Rodrigo Vivi
On Wed, Apr 19, 2023 at 10:33:45AM -0700, Matt Roper wrote:
>On Wed, Apr 19, 2023 at 12:44:34AM -0700, Lucas De Marchi wrote:
>> Stop using i915 types for register our own xe_reg_t. Differently from
>> i915, this will keep under this will keep under the register definition
>> the knowledge for the different types of registers. For now, the "flags"
>> are mcr and masked, although only the former is being used.
>>
>> Most of the driver is agnostic to the register differences. Convert the
>> few places that care about that, namely xe_gt_mcr.c, to take the generic
>> type and warn if the wrong register is used.
>
>The disadvantage of this approach is that we don't get the nice
>type-checking that we have in i915 to catch register misuse at build
>time. Instead we wind up with a bunch of run-time checks that only tell
>you that you used the wrong register semantics after the fact. Wouldn't
>it be better to keep the strict types and let the compiler find mistakes
>for us at build time?
>
>The only real problem with using strict types is that there are a few
>places where the driver is just trying to refer to registers/offsets
>without actually accessing them (e.g., whitelists, OA register groups,
that is not true.
>etc.) and the strict typing makes it harder to provide a heterogeneous
>list of those registers. But I still feel the benefits of compile-time
>checking outweighs the extra complexity we wind up with in a handful of
>places.
I disagree here because the strict type checking is only checking for
"regular vs mcr". Add "masked" in the mix (that has been a huge source
of mistakes in i915) and you already have 4 types(?) to deal with.
There are also places in the code where we want that "this is an
mcr/regular/masked register" info to be used later. See how the reg-sr is
handling that.
In the end I believe having this info encoded in the regs/*.h is
sufficient to avoid the mistakes we had in the past.
Any change in the code triggering these warnings has a very easy an
actionable fix.
If for some reason we want to only differentiate mcr/normal as strict
type checks, then I think we need to provide a better struct for the
places that don't care about that. Something like below maybe
typedef {
xe_reg_t reg;
} xe_reg_mcr_t;
but reg.mcr still being there. Or going the other way around:
typedef union {
xe_reg_normal_t normal;
xe_reg_mcr_t mcr;
} xe_reg_t;
but xe_reg_normal_t and xe_reg_mcr_t actually having the same defintion.
Lucas De Marchi
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [Intel-xe] [PATCH 11/17] drm/xe: Introduce xe_reg_t
2023-04-19 18:49 ` Lucas De Marchi
@ 2023-04-19 19:30 ` Rodrigo Vivi
2023-04-19 20:19 ` Lucas De Marchi
0 siblings, 1 reply; 41+ messages in thread
From: Rodrigo Vivi @ 2023-04-19 19:30 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: Matt Roper, intel-xe
On Wed, Apr 19, 2023 at 11:49:56AM -0700, Lucas De Marchi wrote:
> On Wed, Apr 19, 2023 at 10:33:45AM -0700, Matt Roper wrote:
> > On Wed, Apr 19, 2023 at 12:44:34AM -0700, Lucas De Marchi wrote:
> > > Stop using i915 types for register our own xe_reg_t. Differently from
> > > i915, this will keep under this will keep under the register definition
> > > the knowledge for the different types of registers. For now, the "flags"
> > > are mcr and masked, although only the former is being used.
> > >
> > > Most of the driver is agnostic to the register differences. Convert the
> > > few places that care about that, namely xe_gt_mcr.c, to take the generic
> > > type and warn if the wrong register is used.
> >
> > The disadvantage of this approach is that we don't get the nice
> > type-checking that we have in i915 to catch register misuse at build
> > time. Instead we wind up with a bunch of run-time checks that only tell
> > you that you used the wrong register semantics after the fact. Wouldn't
> > it be better to keep the strict types and let the compiler find mistakes
> > for us at build time?
> >
> > The only real problem with using strict types is that there are a few
> > places where the driver is just trying to refer to registers/offsets
> > without actually accessing them (e.g., whitelists, OA register groups,
>
> that is not true.
>
> > etc.) and the strict typing makes it harder to provide a heterogeneous
> > list of those registers. But I still feel the benefits of compile-time
> > checking outweighs the extra complexity we wind up with in a handful of
> > places.
>
> I disagree here because the strict type checking is only checking for
> "regular vs mcr". Add "masked" in the mix (that has been a huge source
> of mistakes in i915) and you already have 4 types(?) to deal with.
>
> There are also places in the code where we want that "this is an
> mcr/regular/masked register" info to be used later. See how the reg-sr is
> handling that.
>
> In the end I believe having this info encoded in the regs/*.h is
> sufficient to avoid the mistakes we had in the past.
>
> Any change in the code triggering these warnings has a very easy an
> actionable fix.
>
> If for some reason we want to only differentiate mcr/normal as strict
> type checks, then I think we need to provide a better struct for the
> places that don't care about that. Something like below maybe
>
> typedef {
> xe_reg_t reg;
> } xe_reg_mcr_t;
>
> but reg.mcr still being there. Or going the other way around:
>
> typedef union {
> xe_reg_normal_t normal;
> xe_reg_mcr_t mcr;
> } xe_reg_t;
>
> but xe_reg_normal_t and xe_reg_mcr_t actually having the same defintion.
>
> Lucas De Marchi
I honestly liked the approach you took on this patch here. Getting rid of
the i915_mcr is already a win by itself.
One case that came to my mind though is some time sensitive mmio operations
like display inside vblank areas. any runtime check could potentially
increase latency, no?! If that's irrelevant time, than let's move with this
but if it is really a problem, then explore your latest suggestion here
with the compiler doing the checks for us seems a good alternative.
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [Intel-xe] [PATCH 11/17] drm/xe: Introduce xe_reg_t
2023-04-19 17:17 ` Lucas De Marchi
@ 2023-04-19 19:39 ` Jani Nikula
2023-04-19 20:30 ` Lucas De Marchi
0 siblings, 1 reply; 41+ messages in thread
From: Jani Nikula @ 2023-04-19 19:39 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: Matt Roper, intel-xe, Rodrigo Vivi
On Wed, 19 Apr 2023, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> On Wed, Apr 19, 2023 at 07:06:51PM +0300, Jani Nikula wrote:
>>On Wed, 19 Apr 2023, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>>> Stop using i915 types for register our own xe_reg_t. Differently from
>>> i915, this will keep under this will keep under the register definition
>>> the knowledge for the different types of registers. For now, the "flags"
>>> are mcr and masked, although only the former is being used.
>>>
>>> Most of the driver is agnostic to the register differences. Convert the
>>> few places that care about that, namely xe_gt_mcr.c, to take the generic
>>> type and warn if the wrong register is used.
>>>
>>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>>> ---
>>> drivers/gpu/drm/xe/regs/xe_reg_defs.h | 15 +++++++++++++++
>>> drivers/gpu/drm/xe/xe_gt_mcr.c | 22 ++++++++++++++++------
>>> drivers/gpu/drm/xe/xe_gt_mcr.h | 8 ++++----
>>> drivers/gpu/drm/xe/xe_irq.c | 2 +-
>>> drivers/gpu/drm/xe/xe_mmio.c | 2 +-
>>> 5 files changed, 37 insertions(+), 12 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/xe/regs/xe_reg_defs.h b/drivers/gpu/drm/xe/regs/xe_reg_defs.h
>>> index b5c25e31b889..1e78508c737b 100644
>>> --- a/drivers/gpu/drm/xe/regs/xe_reg_defs.h
>>> +++ b/drivers/gpu/drm/xe/regs/xe_reg_defs.h
>>> @@ -8,4 +8,19 @@
>>>
>>> #include "compat-i915-headers/i915_reg_defs.h"
>>>
>>> +typedef union {
>>> + struct {
>>> + u32 reg:30;
>>> + u32 mcr:1;
>>> + u32 masked:1;
>>> + };
>>> + u32 raw;
>>> +} xe_reg_t;
>>> +
>>> +/* TODO: remove these once the register declarations are not using them anymore */
>>> +#undef _MMIO
>>> +#undef MCR_REG
>>> +#define _MMIO(r) ((const xe_reg_t){ .reg = (r) })
>>> +#define MCR_REG(r) ((const xe_reg_t){ .reg = (r), .mcr = 1 })
>>> +
>>> #endif
>>> diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
>>> index aa04ba5a6dbe..b9631cfd5b81 100644
>>> --- a/drivers/gpu/drm/xe/xe_gt_mcr.c
>>> +++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
>>> @@ -360,11 +360,13 @@ void xe_gt_mcr_set_implicit_defaults(struct xe_gt *gt)
>>> * returned. Returns false if the caller need not perform any steering
>>> */
>>> static bool xe_gt_mcr_get_nonterminated_steering(struct xe_gt *gt,
>>> - i915_mcr_reg_t reg,
>>> + xe_reg_t reg,
>>> u8 *group, u8 *instance)
>>> {
>>> const struct xe_mmio_range *implicit_ranges;
>>>
>>> + drm_WARN_ON(>_to_xe(gt)->drm, !reg.mcr);
>>
>>I'd add some is_mcr_reg() style macro and use it throughout instead of
>>poking directly at xe_reg_t guts. The idea should be that xe_reg_t is
>>opaque.
>
> humn... in xe the tendency is not to hide too much as it creates a
> unneeded level of indirection. I don't see us needing to change
> xe_reg_t much in future or make it depend on platform, etc. I think a
> helper like that could be added if we end up with such need.
If you hide the underlying type with a typedef, don't look inside. If
you need to look inside, don't hide the type. See coding-style.rst.
> *changing* the values underneath the struct is probably something that
> we should avoid doing (there are a few places we do though to account
> for base offset), but I don't see a problem *reading* it. We should
> probably sprinkle some const around.
>
> The extra verbosity imposed by the wrapper function call doesn't bring
> much benefit IMO.
To me, the main benefit is readability and self-documenting code:
if (reg.mcr)
vs.
if (is_mcr_reg(reg))
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [Intel-xe] [PATCH 11/17] drm/xe: Introduce xe_reg_t
2023-04-19 17:33 ` Matt Roper
2023-04-19 18:49 ` Lucas De Marchi
@ 2023-04-19 19:49 ` Jani Nikula
2023-04-19 20:13 ` Lucas De Marchi
2023-04-19 20:13 ` Matt Roper
1 sibling, 2 replies; 41+ messages in thread
From: Jani Nikula @ 2023-04-19 19:49 UTC (permalink / raw)
To: Matt Roper, Lucas De Marchi; +Cc: intel-xe, Rodrigo Vivi
On Wed, 19 Apr 2023, Matt Roper <matthew.d.roper@intel.com> wrote:
> On Wed, Apr 19, 2023 at 12:44:34AM -0700, Lucas De Marchi wrote:
>> Stop using i915 types for register our own xe_reg_t. Differently from
>> i915, this will keep under this will keep under the register definition
>> the knowledge for the different types of registers. For now, the "flags"
>> are mcr and masked, although only the former is being used.
>>
>> Most of the driver is agnostic to the register differences. Convert the
>> few places that care about that, namely xe_gt_mcr.c, to take the generic
>> type and warn if the wrong register is used.
>
> The disadvantage of this approach is that we don't get the nice
> type-checking that we have in i915 to catch register misuse at build
> time. Instead we wind up with a bunch of run-time checks that only tell
> you that you used the wrong register semantics after the fact. Wouldn't
> it be better to keep the strict types and let the compiler find mistakes
> for us at build time?
>
> The only real problem with using strict types is that there are a few
> places where the driver is just trying to refer to registers/offsets
> without actually accessing them (e.g., whitelists, OA register groups,
> etc.) and the strict typing makes it harder to provide a heterogeneous
> list of those registers. But I still feel the benefits of compile-time
> checking outweighs the extra complexity we wind up with in a handful of
> places.
The history of i915_reg_t is that there were subtle bugs where the
arguments to the register write call were accidentally swapped, they
went unnoticed, and needed lengthy debugging to finally figure out.
This can happen with xe_mmio_write32().
Strong typing for i915_reg_t has positive score 9 on Rusty's API Design
Manifesto [1].
BR,
Jani.
[1] https://ozlabs.org/~rusty/index.cgi/tech/2008-03-30.html
>
>
> Matt
>
>>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>> drivers/gpu/drm/xe/regs/xe_reg_defs.h | 15 +++++++++++++++
>> drivers/gpu/drm/xe/xe_gt_mcr.c | 22 ++++++++++++++++------
>> drivers/gpu/drm/xe/xe_gt_mcr.h | 8 ++++----
>> drivers/gpu/drm/xe/xe_irq.c | 2 +-
>> drivers/gpu/drm/xe/xe_mmio.c | 2 +-
>> 5 files changed, 37 insertions(+), 12 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/regs/xe_reg_defs.h b/drivers/gpu/drm/xe/regs/xe_reg_defs.h
>> index b5c25e31b889..1e78508c737b 100644
>> --- a/drivers/gpu/drm/xe/regs/xe_reg_defs.h
>> +++ b/drivers/gpu/drm/xe/regs/xe_reg_defs.h
>> @@ -8,4 +8,19 @@
>>
>> #include "compat-i915-headers/i915_reg_defs.h"
>>
>> +typedef union {
>> + struct {
>> + u32 reg:30;
>> + u32 mcr:1;
>> + u32 masked:1;
>> + };
>> + u32 raw;
>> +} xe_reg_t;
>> +
>> +/* TODO: remove these once the register declarations are not using them anymore */
>> +#undef _MMIO
>> +#undef MCR_REG
>> +#define _MMIO(r) ((const xe_reg_t){ .reg = (r) })
>> +#define MCR_REG(r) ((const xe_reg_t){ .reg = (r), .mcr = 1 })
>> +
>> #endif
>> diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
>> index aa04ba5a6dbe..b9631cfd5b81 100644
>> --- a/drivers/gpu/drm/xe/xe_gt_mcr.c
>> +++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
>> @@ -360,11 +360,13 @@ void xe_gt_mcr_set_implicit_defaults(struct xe_gt *gt)
>> * returned. Returns false if the caller need not perform any steering
>> */
>> static bool xe_gt_mcr_get_nonterminated_steering(struct xe_gt *gt,
>> - i915_mcr_reg_t reg,
>> + xe_reg_t reg,
>> u8 *group, u8 *instance)
>> {
>> const struct xe_mmio_range *implicit_ranges;
>>
>> + drm_WARN_ON(>_to_xe(gt)->drm, !reg.mcr);
>> +
>> for (int type = 0; type < IMPLICIT_STEERING; type++) {
>> if (!gt->steering[type].ranges)
>> continue;
>> @@ -436,11 +438,13 @@ static void mcr_unlock(struct xe_gt *gt) {
>> *
>> * Caller needs to make sure the relevant forcewake wells are up.
>> */
>> -static u32 rw_with_mcr_steering(struct xe_gt *gt, i915_mcr_reg_t reg, u8 rw_flag,
>> +static u32 rw_with_mcr_steering(struct xe_gt *gt, xe_reg_t reg, u8 rw_flag,
>> int group, int instance, u32 value)
>> {
>> u32 steer_reg, steer_val, val = 0;
>>
>> + drm_WARN_ON(>_to_xe(gt)->drm, !reg.mcr);
>> +
>> lockdep_assert_held(>->mcr_lock);
>>
>> if (GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270) {
>> @@ -494,12 +498,14 @@ static u32 rw_with_mcr_steering(struct xe_gt *gt, i915_mcr_reg_t reg, u8 rw_flag
>> *
>> * Returns the value from a non-terminated instance of @reg.
>> */
>> -u32 xe_gt_mcr_unicast_read_any(struct xe_gt *gt, i915_mcr_reg_t reg)
>> +u32 xe_gt_mcr_unicast_read_any(struct xe_gt *gt, xe_reg_t reg)
>> {
>> u8 group, instance;
>> u32 val;
>> bool steer;
>>
>> + drm_WARN_ON(>_to_xe(gt)->drm, !reg.mcr);
>> +
>> steer = xe_gt_mcr_get_nonterminated_steering(gt, reg, &group, &instance);
>>
>> if (steer) {
>> @@ -525,11 +531,13 @@ u32 xe_gt_mcr_unicast_read_any(struct xe_gt *gt, i915_mcr_reg_t reg)
>> * group/instance.
>> */
>> u32 xe_gt_mcr_unicast_read(struct xe_gt *gt,
>> - i915_mcr_reg_t reg,
>> + xe_reg_t reg,
>> int group, int instance)
>> {
>> u32 val;
>>
>> + drm_WARN_ON(>_to_xe(gt)->drm, !reg.mcr);
>> +
>> mcr_lock(gt);
>> val = rw_with_mcr_steering(gt, reg, MCR_OP_READ, group, instance, 0);
>> mcr_unlock(gt);
>> @@ -548,9 +556,11 @@ u32 xe_gt_mcr_unicast_read(struct xe_gt *gt,
>> * Write an MCR register in unicast mode after steering toward a specific
>> * group/instance.
>> */
>> -void xe_gt_mcr_unicast_write(struct xe_gt *gt, i915_mcr_reg_t reg, u32 value,
>> +void xe_gt_mcr_unicast_write(struct xe_gt *gt, xe_reg_t reg, u32 value,
>> int group, int instance)
>> {
>> + drm_WARN_ON(>_to_xe(gt)->drm, !reg.mcr);
>> +
>> mcr_lock(gt);
>> rw_with_mcr_steering(gt, reg, MCR_OP_WRITE, group, instance, value);
>> mcr_unlock(gt);
>> @@ -564,7 +574,7 @@ void xe_gt_mcr_unicast_write(struct xe_gt *gt, i915_mcr_reg_t reg, u32 value,
>> *
>> * Write an MCR register in multicast mode to update all instances.
>> */
>> -void xe_gt_mcr_multicast_write(struct xe_gt *gt, i915_mcr_reg_t reg, u32 value)
>> +void xe_gt_mcr_multicast_write(struct xe_gt *gt, xe_reg_t reg, u32 value)
>> {
>> /*
>> * Synchronize with any unicast operations. Once we have exclusive
>> diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.h b/drivers/gpu/drm/xe/xe_gt_mcr.h
>> index 2a6cd38c8cb7..492d9519784a 100644
>> --- a/drivers/gpu/drm/xe/xe_gt_mcr.h
>> +++ b/drivers/gpu/drm/xe/xe_gt_mcr.h
>> @@ -15,13 +15,13 @@ void xe_gt_mcr_init(struct xe_gt *gt);
>>
>> void xe_gt_mcr_set_implicit_defaults(struct xe_gt *gt);
>>
>> -u32 xe_gt_mcr_unicast_read(struct xe_gt *gt, i915_mcr_reg_t reg,
>> +u32 xe_gt_mcr_unicast_read(struct xe_gt *gt, xe_reg_t reg,
>> int group, int instance);
>> -u32 xe_gt_mcr_unicast_read_any(struct xe_gt *gt, i915_mcr_reg_t reg);
>> +u32 xe_gt_mcr_unicast_read_any(struct xe_gt *gt, xe_reg_t reg);
>>
>> -void xe_gt_mcr_unicast_write(struct xe_gt *gt, i915_mcr_reg_t reg, u32 value,
>> +void xe_gt_mcr_unicast_write(struct xe_gt *gt, xe_reg_t reg, u32 value,
>> int group, int instance);
>> -void xe_gt_mcr_multicast_write(struct xe_gt *gt, i915_mcr_reg_t reg, u32 value);
>> +void xe_gt_mcr_multicast_write(struct xe_gt *gt, xe_reg_t reg, u32 value);
>>
>> void xe_gt_mcr_steering_dump(struct xe_gt *gt, struct drm_printer *p);
>>
>> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
>> index 13f9f220bca0..8e5f8e7c16c8 100644
>> --- a/drivers/gpu/drm/xe/xe_irq.c
>> +++ b/drivers/gpu/drm/xe/xe_irq.c
>> @@ -27,7 +27,7 @@
>> #define IIR(offset) _MMIO(offset + 0x8)
>> #define IER(offset) _MMIO(offset + 0xc)
>>
>> -static void assert_iir_is_zero(struct xe_gt *gt, i915_reg_t reg)
>> +static void assert_iir_is_zero(struct xe_gt *gt, xe_reg_t reg)
>> {
>> u32 val = xe_mmio_read32(gt, reg.reg);
>>
>> diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
>> index a93838e23b7b..1029b9f27988 100644
>> --- a/drivers/gpu/drm/xe/xe_mmio.c
>> +++ b/drivers/gpu/drm/xe/xe_mmio.c
>> @@ -397,7 +397,7 @@ int xe_mmio_init(struct xe_device *xe)
>> DRM_XE_MMIO_READ |\
>> DRM_XE_MMIO_WRITE)
>>
>> -static const i915_reg_t mmio_read_whitelist[] = {
>> +static const xe_reg_t mmio_read_whitelist[] = {
>> RING_TIMESTAMP(RENDER_RING_BASE),
>> };
>>
>> --
>> 2.39.0
>>
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [Intel-xe] [PATCH 11/17] drm/xe: Introduce xe_reg_t
2023-04-19 19:49 ` Jani Nikula
@ 2023-04-19 20:13 ` Lucas De Marchi
2023-04-19 20:13 ` Matt Roper
1 sibling, 0 replies; 41+ messages in thread
From: Lucas De Marchi @ 2023-04-19 20:13 UTC (permalink / raw)
To: Jani Nikula; +Cc: Matt Roper, intel-xe, Rodrigo Vivi
On Wed, Apr 19, 2023 at 10:49:41PM +0300, Jani Nikula wrote:
>On Wed, 19 Apr 2023, Matt Roper <matthew.d.roper@intel.com> wrote:
>> On Wed, Apr 19, 2023 at 12:44:34AM -0700, Lucas De Marchi wrote:
>>> Stop using i915 types for register our own xe_reg_t. Differently from
>>> i915, this will keep under this will keep under the register definition
>>> the knowledge for the different types of registers. For now, the "flags"
>>> are mcr and masked, although only the former is being used.
>>>
>>> Most of the driver is agnostic to the register differences. Convert the
>>> few places that care about that, namely xe_gt_mcr.c, to take the generic
>>> type and warn if the wrong register is used.
>>
>> The disadvantage of this approach is that we don't get the nice
>> type-checking that we have in i915 to catch register misuse at build
>> time. Instead we wind up with a bunch of run-time checks that only tell
>> you that you used the wrong register semantics after the fact. Wouldn't
>> it be better to keep the strict types and let the compiler find mistakes
>> for us at build time?
>>
>> The only real problem with using strict types is that there are a few
>> places where the driver is just trying to refer to registers/offsets
>> without actually accessing them (e.g., whitelists, OA register groups,
>> etc.) and the strict typing makes it harder to provide a heterogeneous
>> list of those registers. But I still feel the benefits of compile-time
>> checking outweighs the extra complexity we wind up with in a handful of
>> places.
>
>The history of i915_reg_t is that there were subtle bugs where the
>arguments to the register write call were accidentally swapped, they
>went unnoticed, and needed lengthy debugging to finally figure out.
>
>This can happen with xe_mmio_write32().
but this is another topic that would be a follow up. Somewhere in the
commit messages I mentioned that the next step would be to make
xe_mmio_* strong typed
>
>Strong typing for i915_reg_t has positive score 9 on Rusty's API Design
>Manifesto [1].
here the discussion is having or not N types for the different types of
registers we have, instead of one type, xe_reg_t, and proper runtime
checks where needed.
Btw, note that we already rely on runtime checks for misuse of
i915_mcr_reg_t: when that type is used and there isn't a range for it
in xe_gt_mcr.c
Lucas De Marchi
>
>
>BR,
>Jani.
>
>
>[1] https://ozlabs.org/~rusty/index.cgi/tech/2008-03-30.html
>
>
>
>>
>>
>> Matt
>>
>>>
>>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>>> ---
>>> drivers/gpu/drm/xe/regs/xe_reg_defs.h | 15 +++++++++++++++
>>> drivers/gpu/drm/xe/xe_gt_mcr.c | 22 ++++++++++++++++------
>>> drivers/gpu/drm/xe/xe_gt_mcr.h | 8 ++++----
>>> drivers/gpu/drm/xe/xe_irq.c | 2 +-
>>> drivers/gpu/drm/xe/xe_mmio.c | 2 +-
>>> 5 files changed, 37 insertions(+), 12 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/xe/regs/xe_reg_defs.h b/drivers/gpu/drm/xe/regs/xe_reg_defs.h
>>> index b5c25e31b889..1e78508c737b 100644
>>> --- a/drivers/gpu/drm/xe/regs/xe_reg_defs.h
>>> +++ b/drivers/gpu/drm/xe/regs/xe_reg_defs.h
>>> @@ -8,4 +8,19 @@
>>>
>>> #include "compat-i915-headers/i915_reg_defs.h"
>>>
>>> +typedef union {
>>> + struct {
>>> + u32 reg:30;
>>> + u32 mcr:1;
>>> + u32 masked:1;
>>> + };
>>> + u32 raw;
>>> +} xe_reg_t;
>>> +
>>> +/* TODO: remove these once the register declarations are not using them anymore */
>>> +#undef _MMIO
>>> +#undef MCR_REG
>>> +#define _MMIO(r) ((const xe_reg_t){ .reg = (r) })
>>> +#define MCR_REG(r) ((const xe_reg_t){ .reg = (r), .mcr = 1 })
>>> +
>>> #endif
>>> diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
>>> index aa04ba5a6dbe..b9631cfd5b81 100644
>>> --- a/drivers/gpu/drm/xe/xe_gt_mcr.c
>>> +++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
>>> @@ -360,11 +360,13 @@ void xe_gt_mcr_set_implicit_defaults(struct xe_gt *gt)
>>> * returned. Returns false if the caller need not perform any steering
>>> */
>>> static bool xe_gt_mcr_get_nonterminated_steering(struct xe_gt *gt,
>>> - i915_mcr_reg_t reg,
>>> + xe_reg_t reg,
>>> u8 *group, u8 *instance)
>>> {
>>> const struct xe_mmio_range *implicit_ranges;
>>>
>>> + drm_WARN_ON(>_to_xe(gt)->drm, !reg.mcr);
>>> +
>>> for (int type = 0; type < IMPLICIT_STEERING; type++) {
>>> if (!gt->steering[type].ranges)
>>> continue;
>>> @@ -436,11 +438,13 @@ static void mcr_unlock(struct xe_gt *gt) {
>>> *
>>> * Caller needs to make sure the relevant forcewake wells are up.
>>> */
>>> -static u32 rw_with_mcr_steering(struct xe_gt *gt, i915_mcr_reg_t reg, u8 rw_flag,
>>> +static u32 rw_with_mcr_steering(struct xe_gt *gt, xe_reg_t reg, u8 rw_flag,
>>> int group, int instance, u32 value)
>>> {
>>> u32 steer_reg, steer_val, val = 0;
>>>
>>> + drm_WARN_ON(>_to_xe(gt)->drm, !reg.mcr);
>>> +
>>> lockdep_assert_held(>->mcr_lock);
>>>
>>> if (GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270) {
>>> @@ -494,12 +498,14 @@ static u32 rw_with_mcr_steering(struct xe_gt *gt, i915_mcr_reg_t reg, u8 rw_flag
>>> *
>>> * Returns the value from a non-terminated instance of @reg.
>>> */
>>> -u32 xe_gt_mcr_unicast_read_any(struct xe_gt *gt, i915_mcr_reg_t reg)
>>> +u32 xe_gt_mcr_unicast_read_any(struct xe_gt *gt, xe_reg_t reg)
>>> {
>>> u8 group, instance;
>>> u32 val;
>>> bool steer;
>>>
>>> + drm_WARN_ON(>_to_xe(gt)->drm, !reg.mcr);
>>> +
>>> steer = xe_gt_mcr_get_nonterminated_steering(gt, reg, &group, &instance);
>>>
>>> if (steer) {
>>> @@ -525,11 +531,13 @@ u32 xe_gt_mcr_unicast_read_any(struct xe_gt *gt, i915_mcr_reg_t reg)
>>> * group/instance.
>>> */
>>> u32 xe_gt_mcr_unicast_read(struct xe_gt *gt,
>>> - i915_mcr_reg_t reg,
>>> + xe_reg_t reg,
>>> int group, int instance)
>>> {
>>> u32 val;
>>>
>>> + drm_WARN_ON(>_to_xe(gt)->drm, !reg.mcr);
>>> +
>>> mcr_lock(gt);
>>> val = rw_with_mcr_steering(gt, reg, MCR_OP_READ, group, instance, 0);
>>> mcr_unlock(gt);
>>> @@ -548,9 +556,11 @@ u32 xe_gt_mcr_unicast_read(struct xe_gt *gt,
>>> * Write an MCR register in unicast mode after steering toward a specific
>>> * group/instance.
>>> */
>>> -void xe_gt_mcr_unicast_write(struct xe_gt *gt, i915_mcr_reg_t reg, u32 value,
>>> +void xe_gt_mcr_unicast_write(struct xe_gt *gt, xe_reg_t reg, u32 value,
>>> int group, int instance)
>>> {
>>> + drm_WARN_ON(>_to_xe(gt)->drm, !reg.mcr);
>>> +
>>> mcr_lock(gt);
>>> rw_with_mcr_steering(gt, reg, MCR_OP_WRITE, group, instance, value);
>>> mcr_unlock(gt);
>>> @@ -564,7 +574,7 @@ void xe_gt_mcr_unicast_write(struct xe_gt *gt, i915_mcr_reg_t reg, u32 value,
>>> *
>>> * Write an MCR register in multicast mode to update all instances.
>>> */
>>> -void xe_gt_mcr_multicast_write(struct xe_gt *gt, i915_mcr_reg_t reg, u32 value)
>>> +void xe_gt_mcr_multicast_write(struct xe_gt *gt, xe_reg_t reg, u32 value)
>>> {
>>> /*
>>> * Synchronize with any unicast operations. Once we have exclusive
>>> diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.h b/drivers/gpu/drm/xe/xe_gt_mcr.h
>>> index 2a6cd38c8cb7..492d9519784a 100644
>>> --- a/drivers/gpu/drm/xe/xe_gt_mcr.h
>>> +++ b/drivers/gpu/drm/xe/xe_gt_mcr.h
>>> @@ -15,13 +15,13 @@ void xe_gt_mcr_init(struct xe_gt *gt);
>>>
>>> void xe_gt_mcr_set_implicit_defaults(struct xe_gt *gt);
>>>
>>> -u32 xe_gt_mcr_unicast_read(struct xe_gt *gt, i915_mcr_reg_t reg,
>>> +u32 xe_gt_mcr_unicast_read(struct xe_gt *gt, xe_reg_t reg,
>>> int group, int instance);
>>> -u32 xe_gt_mcr_unicast_read_any(struct xe_gt *gt, i915_mcr_reg_t reg);
>>> +u32 xe_gt_mcr_unicast_read_any(struct xe_gt *gt, xe_reg_t reg);
>>>
>>> -void xe_gt_mcr_unicast_write(struct xe_gt *gt, i915_mcr_reg_t reg, u32 value,
>>> +void xe_gt_mcr_unicast_write(struct xe_gt *gt, xe_reg_t reg, u32 value,
>>> int group, int instance);
>>> -void xe_gt_mcr_multicast_write(struct xe_gt *gt, i915_mcr_reg_t reg, u32 value);
>>> +void xe_gt_mcr_multicast_write(struct xe_gt *gt, xe_reg_t reg, u32 value);
>>>
>>> void xe_gt_mcr_steering_dump(struct xe_gt *gt, struct drm_printer *p);
>>>
>>> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
>>> index 13f9f220bca0..8e5f8e7c16c8 100644
>>> --- a/drivers/gpu/drm/xe/xe_irq.c
>>> +++ b/drivers/gpu/drm/xe/xe_irq.c
>>> @@ -27,7 +27,7 @@
>>> #define IIR(offset) _MMIO(offset + 0x8)
>>> #define IER(offset) _MMIO(offset + 0xc)
>>>
>>> -static void assert_iir_is_zero(struct xe_gt *gt, i915_reg_t reg)
>>> +static void assert_iir_is_zero(struct xe_gt *gt, xe_reg_t reg)
>>> {
>>> u32 val = xe_mmio_read32(gt, reg.reg);
>>>
>>> diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
>>> index a93838e23b7b..1029b9f27988 100644
>>> --- a/drivers/gpu/drm/xe/xe_mmio.c
>>> +++ b/drivers/gpu/drm/xe/xe_mmio.c
>>> @@ -397,7 +397,7 @@ int xe_mmio_init(struct xe_device *xe)
>>> DRM_XE_MMIO_READ |\
>>> DRM_XE_MMIO_WRITE)
>>>
>>> -static const i915_reg_t mmio_read_whitelist[] = {
>>> +static const xe_reg_t mmio_read_whitelist[] = {
>>> RING_TIMESTAMP(RENDER_RING_BASE),
>>> };
>>>
>>> --
>>> 2.39.0
>>>
>
>--
>Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [Intel-xe] [PATCH 11/17] drm/xe: Introduce xe_reg_t
2023-04-19 19:49 ` Jani Nikula
2023-04-19 20:13 ` Lucas De Marchi
@ 2023-04-19 20:13 ` Matt Roper
2023-04-19 21:24 ` Lucas De Marchi
1 sibling, 1 reply; 41+ messages in thread
From: Matt Roper @ 2023-04-19 20:13 UTC (permalink / raw)
To: Jani Nikula; +Cc: Lucas De Marchi, intel-xe, Rodrigo Vivi
On Wed, Apr 19, 2023 at 10:49:41PM +0300, Jani Nikula wrote:
> On Wed, 19 Apr 2023, Matt Roper <matthew.d.roper@intel.com> wrote:
> > On Wed, Apr 19, 2023 at 12:44:34AM -0700, Lucas De Marchi wrote:
> >> Stop using i915 types for register our own xe_reg_t. Differently from
> >> i915, this will keep under this will keep under the register definition
> >> the knowledge for the different types of registers. For now, the "flags"
> >> are mcr and masked, although only the former is being used.
> >>
> >> Most of the driver is agnostic to the register differences. Convert the
> >> few places that care about that, namely xe_gt_mcr.c, to take the generic
> >> type and warn if the wrong register is used.
> >
> > The disadvantage of this approach is that we don't get the nice
> > type-checking that we have in i915 to catch register misuse at build
> > time. Instead we wind up with a bunch of run-time checks that only tell
> > you that you used the wrong register semantics after the fact. Wouldn't
> > it be better to keep the strict types and let the compiler find mistakes
> > for us at build time?
> >
> > The only real problem with using strict types is that there are a few
> > places where the driver is just trying to refer to registers/offsets
> > without actually accessing them (e.g., whitelists, OA register groups,
> > etc.) and the strict typing makes it harder to provide a heterogeneous
> > list of those registers. But I still feel the benefits of compile-time
> > checking outweighs the extra complexity we wind up with in a handful of
> > places.
>
> The history of i915_reg_t is that there were subtle bugs where the
> arguments to the register write call were accidentally swapped, they
> went unnoticed, and needed lengthy debugging to finally figure out.
>
> This can happen with xe_mmio_write32().
>
> Strong typing for i915_reg_t has positive score 9 on Rusty's API Design
> Manifesto [1].
Exactly. That's why I think we should stick with the strong typing for
MCR vs non-MCR as well, rather than just adding a bunch of runtime
assertions. It sounds like the proposal here would only earn a score of
5 by that website's metrics, whereas we have a 9 in i915.
Matt
>
>
> BR,
> Jani.
>
>
> [1] https://ozlabs.org/~rusty/index.cgi/tech/2008-03-30.html
>
>
>
> >
> >
> > Matt
> >
> >>
> >> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> >> ---
> >> drivers/gpu/drm/xe/regs/xe_reg_defs.h | 15 +++++++++++++++
> >> drivers/gpu/drm/xe/xe_gt_mcr.c | 22 ++++++++++++++++------
> >> drivers/gpu/drm/xe/xe_gt_mcr.h | 8 ++++----
> >> drivers/gpu/drm/xe/xe_irq.c | 2 +-
> >> drivers/gpu/drm/xe/xe_mmio.c | 2 +-
> >> 5 files changed, 37 insertions(+), 12 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/xe/regs/xe_reg_defs.h b/drivers/gpu/drm/xe/regs/xe_reg_defs.h
> >> index b5c25e31b889..1e78508c737b 100644
> >> --- a/drivers/gpu/drm/xe/regs/xe_reg_defs.h
> >> +++ b/drivers/gpu/drm/xe/regs/xe_reg_defs.h
> >> @@ -8,4 +8,19 @@
> >>
> >> #include "compat-i915-headers/i915_reg_defs.h"
> >>
> >> +typedef union {
> >> + struct {
> >> + u32 reg:30;
> >> + u32 mcr:1;
> >> + u32 masked:1;
> >> + };
> >> + u32 raw;
> >> +} xe_reg_t;
> >> +
> >> +/* TODO: remove these once the register declarations are not using them anymore */
> >> +#undef _MMIO
> >> +#undef MCR_REG
> >> +#define _MMIO(r) ((const xe_reg_t){ .reg = (r) })
> >> +#define MCR_REG(r) ((const xe_reg_t){ .reg = (r), .mcr = 1 })
> >> +
> >> #endif
> >> diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
> >> index aa04ba5a6dbe..b9631cfd5b81 100644
> >> --- a/drivers/gpu/drm/xe/xe_gt_mcr.c
> >> +++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
> >> @@ -360,11 +360,13 @@ void xe_gt_mcr_set_implicit_defaults(struct xe_gt *gt)
> >> * returned. Returns false if the caller need not perform any steering
> >> */
> >> static bool xe_gt_mcr_get_nonterminated_steering(struct xe_gt *gt,
> >> - i915_mcr_reg_t reg,
> >> + xe_reg_t reg,
> >> u8 *group, u8 *instance)
> >> {
> >> const struct xe_mmio_range *implicit_ranges;
> >>
> >> + drm_WARN_ON(>_to_xe(gt)->drm, !reg.mcr);
> >> +
> >> for (int type = 0; type < IMPLICIT_STEERING; type++) {
> >> if (!gt->steering[type].ranges)
> >> continue;
> >> @@ -436,11 +438,13 @@ static void mcr_unlock(struct xe_gt *gt) {
> >> *
> >> * Caller needs to make sure the relevant forcewake wells are up.
> >> */
> >> -static u32 rw_with_mcr_steering(struct xe_gt *gt, i915_mcr_reg_t reg, u8 rw_flag,
> >> +static u32 rw_with_mcr_steering(struct xe_gt *gt, xe_reg_t reg, u8 rw_flag,
> >> int group, int instance, u32 value)
> >> {
> >> u32 steer_reg, steer_val, val = 0;
> >>
> >> + drm_WARN_ON(>_to_xe(gt)->drm, !reg.mcr);
> >> +
> >> lockdep_assert_held(>->mcr_lock);
> >>
> >> if (GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270) {
> >> @@ -494,12 +498,14 @@ static u32 rw_with_mcr_steering(struct xe_gt *gt, i915_mcr_reg_t reg, u8 rw_flag
> >> *
> >> * Returns the value from a non-terminated instance of @reg.
> >> */
> >> -u32 xe_gt_mcr_unicast_read_any(struct xe_gt *gt, i915_mcr_reg_t reg)
> >> +u32 xe_gt_mcr_unicast_read_any(struct xe_gt *gt, xe_reg_t reg)
> >> {
> >> u8 group, instance;
> >> u32 val;
> >> bool steer;
> >>
> >> + drm_WARN_ON(>_to_xe(gt)->drm, !reg.mcr);
> >> +
> >> steer = xe_gt_mcr_get_nonterminated_steering(gt, reg, &group, &instance);
> >>
> >> if (steer) {
> >> @@ -525,11 +531,13 @@ u32 xe_gt_mcr_unicast_read_any(struct xe_gt *gt, i915_mcr_reg_t reg)
> >> * group/instance.
> >> */
> >> u32 xe_gt_mcr_unicast_read(struct xe_gt *gt,
> >> - i915_mcr_reg_t reg,
> >> + xe_reg_t reg,
> >> int group, int instance)
> >> {
> >> u32 val;
> >>
> >> + drm_WARN_ON(>_to_xe(gt)->drm, !reg.mcr);
> >> +
> >> mcr_lock(gt);
> >> val = rw_with_mcr_steering(gt, reg, MCR_OP_READ, group, instance, 0);
> >> mcr_unlock(gt);
> >> @@ -548,9 +556,11 @@ u32 xe_gt_mcr_unicast_read(struct xe_gt *gt,
> >> * Write an MCR register in unicast mode after steering toward a specific
> >> * group/instance.
> >> */
> >> -void xe_gt_mcr_unicast_write(struct xe_gt *gt, i915_mcr_reg_t reg, u32 value,
> >> +void xe_gt_mcr_unicast_write(struct xe_gt *gt, xe_reg_t reg, u32 value,
> >> int group, int instance)
> >> {
> >> + drm_WARN_ON(>_to_xe(gt)->drm, !reg.mcr);
> >> +
> >> mcr_lock(gt);
> >> rw_with_mcr_steering(gt, reg, MCR_OP_WRITE, group, instance, value);
> >> mcr_unlock(gt);
> >> @@ -564,7 +574,7 @@ void xe_gt_mcr_unicast_write(struct xe_gt *gt, i915_mcr_reg_t reg, u32 value,
> >> *
> >> * Write an MCR register in multicast mode to update all instances.
> >> */
> >> -void xe_gt_mcr_multicast_write(struct xe_gt *gt, i915_mcr_reg_t reg, u32 value)
> >> +void xe_gt_mcr_multicast_write(struct xe_gt *gt, xe_reg_t reg, u32 value)
> >> {
> >> /*
> >> * Synchronize with any unicast operations. Once we have exclusive
> >> diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.h b/drivers/gpu/drm/xe/xe_gt_mcr.h
> >> index 2a6cd38c8cb7..492d9519784a 100644
> >> --- a/drivers/gpu/drm/xe/xe_gt_mcr.h
> >> +++ b/drivers/gpu/drm/xe/xe_gt_mcr.h
> >> @@ -15,13 +15,13 @@ void xe_gt_mcr_init(struct xe_gt *gt);
> >>
> >> void xe_gt_mcr_set_implicit_defaults(struct xe_gt *gt);
> >>
> >> -u32 xe_gt_mcr_unicast_read(struct xe_gt *gt, i915_mcr_reg_t reg,
> >> +u32 xe_gt_mcr_unicast_read(struct xe_gt *gt, xe_reg_t reg,
> >> int group, int instance);
> >> -u32 xe_gt_mcr_unicast_read_any(struct xe_gt *gt, i915_mcr_reg_t reg);
> >> +u32 xe_gt_mcr_unicast_read_any(struct xe_gt *gt, xe_reg_t reg);
> >>
> >> -void xe_gt_mcr_unicast_write(struct xe_gt *gt, i915_mcr_reg_t reg, u32 value,
> >> +void xe_gt_mcr_unicast_write(struct xe_gt *gt, xe_reg_t reg, u32 value,
> >> int group, int instance);
> >> -void xe_gt_mcr_multicast_write(struct xe_gt *gt, i915_mcr_reg_t reg, u32 value);
> >> +void xe_gt_mcr_multicast_write(struct xe_gt *gt, xe_reg_t reg, u32 value);
> >>
> >> void xe_gt_mcr_steering_dump(struct xe_gt *gt, struct drm_printer *p);
> >>
> >> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> >> index 13f9f220bca0..8e5f8e7c16c8 100644
> >> --- a/drivers/gpu/drm/xe/xe_irq.c
> >> +++ b/drivers/gpu/drm/xe/xe_irq.c
> >> @@ -27,7 +27,7 @@
> >> #define IIR(offset) _MMIO(offset + 0x8)
> >> #define IER(offset) _MMIO(offset + 0xc)
> >>
> >> -static void assert_iir_is_zero(struct xe_gt *gt, i915_reg_t reg)
> >> +static void assert_iir_is_zero(struct xe_gt *gt, xe_reg_t reg)
> >> {
> >> u32 val = xe_mmio_read32(gt, reg.reg);
> >>
> >> diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
> >> index a93838e23b7b..1029b9f27988 100644
> >> --- a/drivers/gpu/drm/xe/xe_mmio.c
> >> +++ b/drivers/gpu/drm/xe/xe_mmio.c
> >> @@ -397,7 +397,7 @@ int xe_mmio_init(struct xe_device *xe)
> >> DRM_XE_MMIO_READ |\
> >> DRM_XE_MMIO_WRITE)
> >>
> >> -static const i915_reg_t mmio_read_whitelist[] = {
> >> +static const xe_reg_t mmio_read_whitelist[] = {
> >> RING_TIMESTAMP(RENDER_RING_BASE),
> >> };
> >>
> >> --
> >> 2.39.0
> >>
>
> --
> Jani Nikula, Intel Open Source Graphics Center
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [Intel-xe] [PATCH 11/17] drm/xe: Introduce xe_reg_t
2023-04-19 19:30 ` Rodrigo Vivi
@ 2023-04-19 20:19 ` Lucas De Marchi
2023-04-19 20:24 ` Matt Roper
0 siblings, 1 reply; 41+ messages in thread
From: Lucas De Marchi @ 2023-04-19 20:19 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: Matt Roper, intel-xe
On Wed, Apr 19, 2023 at 03:30:17PM -0400, Rodrigo Vivi wrote:
>On Wed, Apr 19, 2023 at 11:49:56AM -0700, Lucas De Marchi wrote:
>> On Wed, Apr 19, 2023 at 10:33:45AM -0700, Matt Roper wrote:
>> > On Wed, Apr 19, 2023 at 12:44:34AM -0700, Lucas De Marchi wrote:
>> > > Stop using i915 types for register our own xe_reg_t. Differently from
>> > > i915, this will keep under this will keep under the register definition
>> > > the knowledge for the different types of registers. For now, the "flags"
>> > > are mcr and masked, although only the former is being used.
>> > >
>> > > Most of the driver is agnostic to the register differences. Convert the
>> > > few places that care about that, namely xe_gt_mcr.c, to take the generic
>> > > type and warn if the wrong register is used.
>> >
>> > The disadvantage of this approach is that we don't get the nice
>> > type-checking that we have in i915 to catch register misuse at build
>> > time. Instead we wind up with a bunch of run-time checks that only tell
>> > you that you used the wrong register semantics after the fact. Wouldn't
>> > it be better to keep the strict types and let the compiler find mistakes
>> > for us at build time?
>> >
>> > The only real problem with using strict types is that there are a few
>> > places where the driver is just trying to refer to registers/offsets
>> > without actually accessing them (e.g., whitelists, OA register groups,
>>
>> that is not true.
>>
>> > etc.) and the strict typing makes it harder to provide a heterogeneous
>> > list of those registers. But I still feel the benefits of compile-time
>> > checking outweighs the extra complexity we wind up with in a handful of
>> > places.
>>
>> I disagree here because the strict type checking is only checking for
>> "regular vs mcr". Add "masked" in the mix (that has been a huge source
>> of mistakes in i915) and you already have 4 types(?) to deal with.
>>
>> There are also places in the code where we want that "this is an
>> mcr/regular/masked register" info to be used later. See how the reg-sr is
>> handling that.
>>
>> In the end I believe having this info encoded in the regs/*.h is
>> sufficient to avoid the mistakes we had in the past.
>>
>> Any change in the code triggering these warnings has a very easy an
>> actionable fix.
>>
>> If for some reason we want to only differentiate mcr/normal as strict
>> type checks, then I think we need to provide a better struct for the
>> places that don't care about that. Something like below maybe
>>
>> typedef {
>> xe_reg_t reg;
>> } xe_reg_mcr_t;
>>
>> but reg.mcr still being there. Or going the other way around:
>>
>> typedef union {
>> xe_reg_normal_t normal;
>> xe_reg_mcr_t mcr;
>> } xe_reg_t;
>>
>> but xe_reg_normal_t and xe_reg_mcr_t actually having the same defintion.
>>
>> Lucas De Marchi
>
>I honestly liked the approach you took on this patch here. Getting rid of
>the i915_mcr is already a win by itself.
>
>One case that came to my mind though is some time sensitive mmio operations
>like display inside vblank areas. any runtime check could potentially
>increase latency, no?! If that's irrelevant time, than let's move with this
>but if it is really a problem, then explore your latest suggestion here
>with the compiler doing the checks for us seems a good alternative.
the additional check is inside xe_gt_mcr.c... I think the additional
check is negligible compared to the other operations there, with each
access to reg X requiring other 2 mmio accesses to take place.
Besides, there is no such user in display/
$ git grep xe_gt_mcr -- drivers/gpu/drm/xe/display/
Lucas De Marchi
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [Intel-xe] [PATCH 11/17] drm/xe: Introduce xe_reg_t
2023-04-19 20:19 ` Lucas De Marchi
@ 2023-04-19 20:24 ` Matt Roper
2023-04-19 21:09 ` Lucas De Marchi
0 siblings, 1 reply; 41+ messages in thread
From: Matt Roper @ 2023-04-19 20:24 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-xe, Rodrigo Vivi
On Wed, Apr 19, 2023 at 01:19:49PM -0700, Lucas De Marchi wrote:
> On Wed, Apr 19, 2023 at 03:30:17PM -0400, Rodrigo Vivi wrote:
> > On Wed, Apr 19, 2023 at 11:49:56AM -0700, Lucas De Marchi wrote:
> > > On Wed, Apr 19, 2023 at 10:33:45AM -0700, Matt Roper wrote:
> > > > On Wed, Apr 19, 2023 at 12:44:34AM -0700, Lucas De Marchi wrote:
> > > > > Stop using i915 types for register our own xe_reg_t. Differently from
> > > > > i915, this will keep under this will keep under the register definition
> > > > > the knowledge for the different types of registers. For now, the "flags"
> > > > > are mcr and masked, although only the former is being used.
> > > > >
> > > > > Most of the driver is agnostic to the register differences. Convert the
> > > > > few places that care about that, namely xe_gt_mcr.c, to take the generic
> > > > > type and warn if the wrong register is used.
> > > >
> > > > The disadvantage of this approach is that we don't get the nice
> > > > type-checking that we have in i915 to catch register misuse at build
> > > > time. Instead we wind up with a bunch of run-time checks that only tell
> > > > you that you used the wrong register semantics after the fact. Wouldn't
> > > > it be better to keep the strict types and let the compiler find mistakes
> > > > for us at build time?
> > > >
> > > > The only real problem with using strict types is that there are a few
> > > > places where the driver is just trying to refer to registers/offsets
> > > > without actually accessing them (e.g., whitelists, OA register groups,
> > >
> > > that is not true.
> > >
> > > > etc.) and the strict typing makes it harder to provide a heterogeneous
> > > > list of those registers. But I still feel the benefits of compile-time
> > > > checking outweighs the extra complexity we wind up with in a handful of
> > > > places.
> > >
> > > I disagree here because the strict type checking is only checking for
> > > "regular vs mcr". Add "masked" in the mix (that has been a huge source
> > > of mistakes in i915) and you already have 4 types(?) to deal with.
> > >
> > > There are also places in the code where we want that "this is an
> > > mcr/regular/masked register" info to be used later. See how the reg-sr is
> > > handling that.
> > >
> > > In the end I believe having this info encoded in the regs/*.h is
> > > sufficient to avoid the mistakes we had in the past.
> > >
> > > Any change in the code triggering these warnings has a very easy an
> > > actionable fix.
> > >
> > > If for some reason we want to only differentiate mcr/normal as strict
> > > type checks, then I think we need to provide a better struct for the
> > > places that don't care about that. Something like below maybe
> > >
> > > typedef {
> > > xe_reg_t reg;
> > > } xe_reg_mcr_t;
> > >
> > > but reg.mcr still being there. Or going the other way around:
> > >
> > > typedef union {
> > > xe_reg_normal_t normal;
> > > xe_reg_mcr_t mcr;
> > > } xe_reg_t;
> > >
> > > but xe_reg_normal_t and xe_reg_mcr_t actually having the same defintion.
> > >
> > > Lucas De Marchi
> >
> > I honestly liked the approach you took on this patch here. Getting rid of
> > the i915_mcr is already a win by itself.
> >
> > One case that came to my mind though is some time sensitive mmio operations
> > like display inside vblank areas. any runtime check could potentially
> > increase latency, no?! If that's irrelevant time, than let's move with this
> > but if it is really a problem, then explore your latest suggestion here
> > with the compiler doing the checks for us seems a good alternative.
>
> the additional check is inside xe_gt_mcr.c... I think the additional
> check is negligible compared to the other operations there, with each
> access to reg X requiring other 2 mmio accesses to take place.
The super critical checks (which don't exist yet in this series; they'd
presumably be added in a follow-up series) are the ones to make sure you
don't try to call xe_mmio_{read,write}32() on an MCR register. Doing
that can lead to all kinds of subtle bugs (which become even more
problematic on the more recent platforms), and unfortunately that kind
of mistake is what people are going to write in the code 99% of the time
out of habit.
Matt
>
> Besides, there is no such user in display/
>
> $ git grep xe_gt_mcr -- drivers/gpu/drm/xe/display/
>
>
> Lucas De Marchi
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [Intel-xe] [PATCH 11/17] drm/xe: Introduce xe_reg_t
2023-04-19 19:39 ` Jani Nikula
@ 2023-04-19 20:30 ` Lucas De Marchi
0 siblings, 0 replies; 41+ messages in thread
From: Lucas De Marchi @ 2023-04-19 20:30 UTC (permalink / raw)
To: Jani Nikula; +Cc: Matt Roper, intel-xe, Rodrigo Vivi
On Wed, Apr 19, 2023 at 10:39:55PM +0300, Jani Nikula wrote:
>On Wed, 19 Apr 2023, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>> On Wed, Apr 19, 2023 at 07:06:51PM +0300, Jani Nikula wrote:
>>>On Wed, 19 Apr 2023, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>>>> Stop using i915 types for register our own xe_reg_t. Differently from
>>>> i915, this will keep under this will keep under the register definition
>>>> the knowledge for the different types of registers. For now, the "flags"
>>>> are mcr and masked, although only the former is being used.
>>>>
>>>> Most of the driver is agnostic to the register differences. Convert the
>>>> few places that care about that, namely xe_gt_mcr.c, to take the generic
>>>> type and warn if the wrong register is used.
>>>>
>>>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>>>> ---
>>>> drivers/gpu/drm/xe/regs/xe_reg_defs.h | 15 +++++++++++++++
>>>> drivers/gpu/drm/xe/xe_gt_mcr.c | 22 ++++++++++++++++------
>>>> drivers/gpu/drm/xe/xe_gt_mcr.h | 8 ++++----
>>>> drivers/gpu/drm/xe/xe_irq.c | 2 +-
>>>> drivers/gpu/drm/xe/xe_mmio.c | 2 +-
>>>> 5 files changed, 37 insertions(+), 12 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/xe/regs/xe_reg_defs.h b/drivers/gpu/drm/xe/regs/xe_reg_defs.h
>>>> index b5c25e31b889..1e78508c737b 100644
>>>> --- a/drivers/gpu/drm/xe/regs/xe_reg_defs.h
>>>> +++ b/drivers/gpu/drm/xe/regs/xe_reg_defs.h
>>>> @@ -8,4 +8,19 @@
>>>>
>>>> #include "compat-i915-headers/i915_reg_defs.h"
>>>>
>>>> +typedef union {
>>>> + struct {
>>>> + u32 reg:30;
>>>> + u32 mcr:1;
>>>> + u32 masked:1;
>>>> + };
>>>> + u32 raw;
>>>> +} xe_reg_t;
>>>> +
>>>> +/* TODO: remove these once the register declarations are not using them anymore */
>>>> +#undef _MMIO
>>>> +#undef MCR_REG
>>>> +#define _MMIO(r) ((const xe_reg_t){ .reg = (r) })
>>>> +#define MCR_REG(r) ((const xe_reg_t){ .reg = (r), .mcr = 1 })
>>>> +
>>>> #endif
>>>> diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
>>>> index aa04ba5a6dbe..b9631cfd5b81 100644
>>>> --- a/drivers/gpu/drm/xe/xe_gt_mcr.c
>>>> +++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
>>>> @@ -360,11 +360,13 @@ void xe_gt_mcr_set_implicit_defaults(struct xe_gt *gt)
>>>> * returned. Returns false if the caller need not perform any steering
>>>> */
>>>> static bool xe_gt_mcr_get_nonterminated_steering(struct xe_gt *gt,
>>>> - i915_mcr_reg_t reg,
>>>> + xe_reg_t reg,
>>>> u8 *group, u8 *instance)
>>>> {
>>>> const struct xe_mmio_range *implicit_ranges;
>>>>
>>>> + drm_WARN_ON(>_to_xe(gt)->drm, !reg.mcr);
>>>
>>>I'd add some is_mcr_reg() style macro and use it throughout instead of
>>>poking directly at xe_reg_t guts. The idea should be that xe_reg_t is
>>>opaque.
>>
>> humn... in xe the tendency is not to hide too much as it creates a
>> unneeded level of indirection. I don't see us needing to change
>> xe_reg_t much in future or make it depend on platform, etc. I think a
>> helper like that could be added if we end up with such need.
>
>If you hide the underlying type with a typedef, don't look inside. If
>you need to look inside, don't hide the type. See coding-style.rst.
I only typedef'ed to follow what was already there. To be honest, I
think we can lose the typedef.
>
>> *changing* the values underneath the struct is probably something that
>> we should avoid doing (there are a few places we do though to account
>> for base offset), but I don't see a problem *reading* it. We should
>> probably sprinkle some const around.
>>
>> The extra verbosity imposed by the wrapper function call doesn't bring
>> much benefit IMO.
>
>To me, the main benefit is readability and self-documenting code:
>
> if (reg.mcr)
>
>vs.
>
> if (is_mcr_reg(reg))
which is also against our coding style, so it should be
xe_reg_is_mcr(reg). My personal taste here: I don't think it
reads better than `if (reg.mcr)`. If anything, one would have to
consult the meaning of "mcr" rather than what one vs the other is
doing.
Lucas De Marchi
>
>
>BR,
>Jani.
>
>--
>Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [Intel-xe] [PATCH 11/17] drm/xe: Introduce xe_reg_t
2023-04-19 20:24 ` Matt Roper
@ 2023-04-19 21:09 ` Lucas De Marchi
2023-04-19 23:14 ` Matt Roper
0 siblings, 1 reply; 41+ messages in thread
From: Lucas De Marchi @ 2023-04-19 21:09 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe, Rodrigo Vivi
On Wed, Apr 19, 2023 at 01:24:31PM -0700, Matt Roper wrote:
>On Wed, Apr 19, 2023 at 01:19:49PM -0700, Lucas De Marchi wrote:
>> On Wed, Apr 19, 2023 at 03:30:17PM -0400, Rodrigo Vivi wrote:
>> > On Wed, Apr 19, 2023 at 11:49:56AM -0700, Lucas De Marchi wrote:
>> > > On Wed, Apr 19, 2023 at 10:33:45AM -0700, Matt Roper wrote:
>> > > > On Wed, Apr 19, 2023 at 12:44:34AM -0700, Lucas De Marchi wrote:
>> > > > > Stop using i915 types for register our own xe_reg_t. Differently from
>> > > > > i915, this will keep under this will keep under the register definition
>> > > > > the knowledge for the different types of registers. For now, the "flags"
>> > > > > are mcr and masked, although only the former is being used.
>> > > > >
>> > > > > Most of the driver is agnostic to the register differences. Convert the
>> > > > > few places that care about that, namely xe_gt_mcr.c, to take the generic
>> > > > > type and warn if the wrong register is used.
>> > > >
>> > > > The disadvantage of this approach is that we don't get the nice
>> > > > type-checking that we have in i915 to catch register misuse at build
>> > > > time. Instead we wind up with a bunch of run-time checks that only tell
>> > > > you that you used the wrong register semantics after the fact. Wouldn't
>> > > > it be better to keep the strict types and let the compiler find mistakes
>> > > > for us at build time?
>> > > >
>> > > > The only real problem with using strict types is that there are a few
>> > > > places where the driver is just trying to refer to registers/offsets
>> > > > without actually accessing them (e.g., whitelists, OA register groups,
>> > >
>> > > that is not true.
>> > >
>> > > > etc.) and the strict typing makes it harder to provide a heterogeneous
>> > > > list of those registers. But I still feel the benefits of compile-time
>> > > > checking outweighs the extra complexity we wind up with in a handful of
>> > > > places.
>> > >
>> > > I disagree here because the strict type checking is only checking for
>> > > "regular vs mcr". Add "masked" in the mix (that has been a huge source
>> > > of mistakes in i915) and you already have 4 types(?) to deal with.
>> > >
>> > > There are also places in the code where we want that "this is an
>> > > mcr/regular/masked register" info to be used later. See how the reg-sr is
>> > > handling that.
>> > >
>> > > In the end I believe having this info encoded in the regs/*.h is
>> > > sufficient to avoid the mistakes we had in the past.
>> > >
>> > > Any change in the code triggering these warnings has a very easy an
>> > > actionable fix.
>> > >
>> > > If for some reason we want to only differentiate mcr/normal as strict
>> > > type checks, then I think we need to provide a better struct for the
>> > > places that don't care about that. Something like below maybe
>> > >
>> > > typedef {
>> > > xe_reg_t reg;
>> > > } xe_reg_mcr_t;
>> > >
>> > > but reg.mcr still being there. Or going the other way around:
>> > >
>> > > typedef union {
>> > > xe_reg_normal_t normal;
>> > > xe_reg_mcr_t mcr;
>> > > } xe_reg_t;
>> > >
>> > > but xe_reg_normal_t and xe_reg_mcr_t actually having the same defintion.
>> > >
>> > > Lucas De Marchi
>> >
>> > I honestly liked the approach you took on this patch here. Getting rid of
>> > the i915_mcr is already a win by itself.
>> >
>> > One case that came to my mind though is some time sensitive mmio operations
>> > like display inside vblank areas. any runtime check could potentially
>> > increase latency, no?! If that's irrelevant time, than let's move with this
>> > but if it is really a problem, then explore your latest suggestion here
>> > with the compiler doing the checks for us seems a good alternative.
>>
>> the additional check is inside xe_gt_mcr.c... I think the additional
>> check is negligible compared to the other operations there, with each
>> access to reg X requiring other 2 mmio accesses to take place.
>
>The super critical checks (which don't exist yet in this series; they'd
>presumably be added in a follow-up series) are the ones to make sure you
>don't try to call xe_mmio_{read,write}32() on an MCR register. Doing
>that can lead to all kinds of subtle bugs (which become even more
>problematic on the more recent platforms), and unfortunately that kind
>of mistake is what people are going to write in the code 99% of the time
>out of habit.
I'm not sure when that would happen... when the next GPU changes a register
from normal to MCR, we rightfully updated the header to update its type
and forgot to change the calls using that register?
Currently xe_mmio_* receives u32 and we just do FOO.reg, with reg being the
name both in i915_reg_t and i915_mcr_reg_t. So, right now the different
types are not helping anything. I'm planning to add xe_reg_t to
xe_mmio_* and have a companion xe_mmio_raw_* for the cases we use a u32
(one of the reasons being because xe_gt_mcr.c itself also needs to call
xe_mmio_*)
How does the type protect us against "daily task of enabling the next
generation of GPUs?":
- gpu version N+1 changed register FOO from normal to MCR.
we didn't notice the register changed. Type doesn't help
because we are still using the old one. If we did notice,
the type would only help if adopted the approach "change the
type", build and see what breaks to fix it, which is IMO
worse than a git-grep approach.
That would mean the hw changed a register from being MCR to being a
normal register which is more rare than the oppposite: a normal register
becoming MCR.
Even if we do the strict type, it doesn't protect us from such mistakes
when we have a normal register becoming MCR. We will have this:
#define FOO XE_REG(10)
and will continue to happily call xe_mmio_* even if in version X of the
GPU the register is now mcr.
Hence my point: the header with the register definition must be the
source of truth on the different register behaviors*. The additional
type checks only help in some cases, and make it harder to handle
others.
On the other hand, I think the different types would be handy when/if we
have the following:
#define xe_mmio_read32(reg) _Generic((reg), \
xe_reg_t: xe_mmio_raw_read32((reg).reg), \
xe_reg_mcr_t: xe_gt_mcr_read32(reg),
)
because that would eliminate an entire class of bugs, encoding in each
call place what is the right function to be called based on the
declaration in the header, with no additional overhead...
Lucas De Marchi
* https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/204 and ideally
be generated from the spec with proper filters in place so we don't
blow out the size of our headers. My goal is to clean our headers and
have them in a state that would be 90% identical to something
generated by a script parsing the spec.
>
>
>Matt
>
>>
>> Besides, there is no such user in display/
>>
>> $ git grep xe_gt_mcr -- drivers/gpu/drm/xe/display/
>>
>>
>> Lucas De Marchi
>
>--
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [Intel-xe] [PATCH 11/17] drm/xe: Introduce xe_reg_t
2023-04-19 20:13 ` Matt Roper
@ 2023-04-19 21:24 ` Lucas De Marchi
0 siblings, 0 replies; 41+ messages in thread
From: Lucas De Marchi @ 2023-04-19 21:24 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe, Rodrigo Vivi
On Wed, Apr 19, 2023 at 01:13:59PM -0700, Matt Roper wrote:
>On Wed, Apr 19, 2023 at 10:49:41PM +0300, Jani Nikula wrote:
>> On Wed, 19 Apr 2023, Matt Roper <matthew.d.roper@intel.com> wrote:
>> > On Wed, Apr 19, 2023 at 12:44:34AM -0700, Lucas De Marchi wrote:
>> >> Stop using i915 types for register our own xe_reg_t. Differently from
>> >> i915, this will keep under this will keep under the register definition
>> >> the knowledge for the different types of registers. For now, the "flags"
>> >> are mcr and masked, although only the former is being used.
>> >>
>> >> Most of the driver is agnostic to the register differences. Convert the
>> >> few places that care about that, namely xe_gt_mcr.c, to take the generic
>> >> type and warn if the wrong register is used.
>> >
>> > The disadvantage of this approach is that we don't get the nice
>> > type-checking that we have in i915 to catch register misuse at build
>> > time. Instead we wind up with a bunch of run-time checks that only tell
>> > you that you used the wrong register semantics after the fact. Wouldn't
>> > it be better to keep the strict types and let the compiler find mistakes
>> > for us at build time?
>> >
>> > The only real problem with using strict types is that there are a few
>> > places where the driver is just trying to refer to registers/offsets
>> > without actually accessing them (e.g., whitelists, OA register groups,
>> > etc.) and the strict typing makes it harder to provide a heterogeneous
>> > list of those registers. But I still feel the benefits of compile-time
>> > checking outweighs the extra complexity we wind up with in a handful of
>> > places.
>>
>> The history of i915_reg_t is that there were subtle bugs where the
>> arguments to the register write call were accidentally swapped, they
>> went unnoticed, and needed lengthy debugging to finally figure out.
>>
>> This can happen with xe_mmio_write32().
>>
>> Strong typing for i915_reg_t has positive score 9 on Rusty's API Design
>> Manifesto [1].
>
>Exactly. That's why I think we should stick with the strong typing for
>MCR vs non-MCR as well, rather than just adding a bunch of runtime
>assertions. It sounds like the proposal here would only earn a score of
>5 by that website's metrics, whereas we have a 9 in i915.
I'd say it's a "false 9" for i915: I detailed in the other thread how we
trigger bugs with the false impression of safety. For the bugs I fixed
regarding the misuse of MCR had nothing to to with the type: it was
either because register was declared wrongly or the runtime check showed
up. Examples (git log --grep MCR --author=lucas.demarchi@intel.com to
get some):
abac0c5d9e0cbb7acad3affbf3a1ec00b4bb1a58
2bb891af095ef287aee454bef930d75565361fea
6a8b2e4984f73f8d00c8c16b87a8b115d34088e4
With the masked vs non-masked in i915 we get a straight 3(?) or 2(?). Not
sure documentation and spec stand for the same thing there.
Lucas De Marchi
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [Intel-xe] [PATCH 11/17] drm/xe: Introduce xe_reg_t
2023-04-19 21:09 ` Lucas De Marchi
@ 2023-04-19 23:14 ` Matt Roper
2023-04-19 23:38 ` Lucas De Marchi
0 siblings, 1 reply; 41+ messages in thread
From: Matt Roper @ 2023-04-19 23:14 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-xe, Rodrigo Vivi
On Wed, Apr 19, 2023 at 02:09:20PM -0700, Lucas De Marchi wrote:
> On Wed, Apr 19, 2023 at 01:24:31PM -0700, Matt Roper wrote:
> > On Wed, Apr 19, 2023 at 01:19:49PM -0700, Lucas De Marchi wrote:
> > > On Wed, Apr 19, 2023 at 03:30:17PM -0400, Rodrigo Vivi wrote:
> > > > On Wed, Apr 19, 2023 at 11:49:56AM -0700, Lucas De Marchi wrote:
> > > > > On Wed, Apr 19, 2023 at 10:33:45AM -0700, Matt Roper wrote:
> > > > > > On Wed, Apr 19, 2023 at 12:44:34AM -0700, Lucas De Marchi wrote:
> > > > > > > Stop using i915 types for register our own xe_reg_t. Differently from
> > > > > > > i915, this will keep under this will keep under the register definition
> > > > > > > the knowledge for the different types of registers. For now, the "flags"
> > > > > > > are mcr and masked, although only the former is being used.
> > > > > > >
> > > > > > > Most of the driver is agnostic to the register differences. Convert the
> > > > > > > few places that care about that, namely xe_gt_mcr.c, to take the generic
> > > > > > > type and warn if the wrong register is used.
> > > > > >
> > > > > > The disadvantage of this approach is that we don't get the nice
> > > > > > type-checking that we have in i915 to catch register misuse at build
> > > > > > time. Instead we wind up with a bunch of run-time checks that only tell
> > > > > > you that you used the wrong register semantics after the fact. Wouldn't
> > > > > > it be better to keep the strict types and let the compiler find mistakes
> > > > > > for us at build time?
> > > > > >
> > > > > > The only real problem with using strict types is that there are a few
> > > > > > places where the driver is just trying to refer to registers/offsets
> > > > > > without actually accessing them (e.g., whitelists, OA register groups,
> > > > >
> > > > > that is not true.
> > > > >
> > > > > > etc.) and the strict typing makes it harder to provide a heterogeneous
> > > > > > list of those registers. But I still feel the benefits of compile-time
> > > > > > checking outweighs the extra complexity we wind up with in a handful of
> > > > > > places.
> > > > >
> > > > > I disagree here because the strict type checking is only checking for
> > > > > "regular vs mcr". Add "masked" in the mix (that has been a huge source
> > > > > of mistakes in i915) and you already have 4 types(?) to deal with.
> > > > >
> > > > > There are also places in the code where we want that "this is an
> > > > > mcr/regular/masked register" info to be used later. See how the reg-sr is
> > > > > handling that.
> > > > >
> > > > > In the end I believe having this info encoded in the regs/*.h is
> > > > > sufficient to avoid the mistakes we had in the past.
> > > > >
> > > > > Any change in the code triggering these warnings has a very easy an
> > > > > actionable fix.
> > > > >
> > > > > If for some reason we want to only differentiate mcr/normal as strict
> > > > > type checks, then I think we need to provide a better struct for the
> > > > > places that don't care about that. Something like below maybe
> > > > >
> > > > > typedef {
> > > > > xe_reg_t reg;
> > > > > } xe_reg_mcr_t;
> > > > >
> > > > > but reg.mcr still being there. Or going the other way around:
> > > > >
> > > > > typedef union {
> > > > > xe_reg_normal_t normal;
> > > > > xe_reg_mcr_t mcr;
> > > > > } xe_reg_t;
> > > > >
> > > > > but xe_reg_normal_t and xe_reg_mcr_t actually having the same defintion.
> > > > >
> > > > > Lucas De Marchi
> > > >
> > > > I honestly liked the approach you took on this patch here. Getting rid of
> > > > the i915_mcr is already a win by itself.
> > > >
> > > > One case that came to my mind though is some time sensitive mmio operations
> > > > like display inside vblank areas. any runtime check could potentially
> > > > increase latency, no?! If that's irrelevant time, than let's move with this
> > > > but if it is really a problem, then explore your latest suggestion here
> > > > with the compiler doing the checks for us seems a good alternative.
> > >
> > > the additional check is inside xe_gt_mcr.c... I think the additional
> > > check is negligible compared to the other operations there, with each
> > > access to reg X requiring other 2 mmio accesses to take place.
> >
> > The super critical checks (which don't exist yet in this series; they'd
> > presumably be added in a follow-up series) are the ones to make sure you
> > don't try to call xe_mmio_{read,write}32() on an MCR register. Doing
> > that can lead to all kinds of subtle bugs (which become even more
> > problematic on the more recent platforms), and unfortunately that kind
> > of mistake is what people are going to write in the code 99% of the time
> > out of habit.
>
> I'm not sure when that would happen... when the next GPU changes a register
> from normal to MCR, we rightfully updated the header to update its type
> and forgot to change the calls using that register?
It happened really frequently on i915 until we finally added the strict
typing. It's not a matter of adding new platforms, it's a matter of
just writing new code in the driver (generally for platforms we already
have and with register definitions that already exist). When someone
needs to add a new register read/write operation for something they're
working on, they'll generally reach for xe_mmio_*() out of habit (or
intel_uncore_*() on i915) since that's what gets used for 90% of
register accesses. If the register is actually an MCR register, and the
compiler doesn't catch this for you, then you just wind up with
incorrect semantics at runtime.
Of course nothing is foolproof. If the read/write is against a
completely new register, and the patch is adding both an incorrect
register definition _and_ an incorrect usage at the same time, then the
compiler won't help there. Although the fact that a completely new
register is being defined makes it slightly more likely that the
reviewers will scrutinize the register details more carefully and catch
the incorrect definition. It's a shame that the MCR nature of registers
isn't documented more clearly in the bspec...
Cases where the same register changed type between platforms is also a
problematic case that will never be foolproof since we wind up with
multiple definitions for the same register offset; if you pick the wrong
definition _and_ the wrong access semantics, then the compiler won't be
able to catch that either. But again, the multiple definitions with
different types will still make it more likely that the developer and/or
reviewer take a closer look and realize the mistake.
>
> Currently xe_mmio_* receives u32 and we just do FOO.reg, with reg being the
Right, this is obviously completely wrong and was something I raised as
a concern months ago when the first Xe megapatch got posted. I started
typing up a fix for that a few weeks ago but got sidetracked and didn't
finish it. xe_mmio_* should obviously be accepting i915_reg_t (or a new
Xe-specific equivalent) rather than a u32. That will protect against
both the 'misordered parameters' problem Jani mentioned, as well as the
'used wrong function on an MCR register' problem that was problematic on
i915.
> name both in i915_reg_t and i915_mcr_reg_t. So, right now the different
> types are not helping anything. I'm planning to add xe_reg_t to
> xe_mmio_* and have a companion xe_mmio_raw_* for the cases we use a u32
> (one of the reasons being because xe_gt_mcr.c itself also needs to call
> xe_mmio_*)
>
> How does the type protect us against "daily task of enabling the next
> generation of GPUs?":
>
> - gpu version N+1 changed register FOO from normal to MCR.
> we didn't notice the register changed. Type doesn't help
> because we are still using the old one. If we did notice,
> the type would only help if adopted the approach "change the
> type", build and see what breaks to fix it, which is IMO
> worse than a git-grep approach.
>
> That would mean the hw changed a register from being MCR to being a
> normal register which is more rare than the oppposite: a normal register
> becoming MCR.
The strict type safety protects us in both directions. xe_mmio_* only
takes unicast registers (after the obvious fixes to replace the u32
parameters), xe_gt_mcr_* only takes MCR registers. If you pass the
wrong register type to either type of function, the compiler catches it
immediately. As you noted, it's still possible to combine two bugs
(incorrect register definition + wrong usage semantics) to sneak by the
compiler; that will surely still happen, but we've raised the bar and
made it harder.
Having registers change between MCR and non-MCR between platforms is
still a problem, but not the most common one based on past history. The
much more common source of problems is people just writing new code that
uses registers we already have in the driver. Assuming the definition
is correct, the new code has to be correct too to get past the compiler.
If all registers become the same type, as you're moving toward in this
series, you could also probably get similar guardrails by turning
xe_mmio_*() into macros that do a BUILD_BUG_ON() before calling the a
real __xe_mmio_*() function, although then you run into issues anywhere
that non-constant register variables get passed up/down the callstack.
>
> Even if we do the strict type, it doesn't protect us from such mistakes
> when we have a normal register becoming MCR. We will have this:
>
> #define FOO XE_REG(10)
>
> and will continue to happily call xe_mmio_* even if in version X of the
> GPU the register is now mcr.
When enabling a new platform and implementing the MCR stuff for the
first time, we do need to be careful to not only add the new ranges to
the driver, but also to go analyze any registers that live in a range
that changed. If there's code that will still be executed that works on
those registers, then we need to figure out how that code needs to
change. We can't automatically assume that writes should become
broadcast_writes and that reads should become read_any's (although
that's the most common outcome); in some situations we actually need to
re-write the code to loop through the various hardware instances and
handle them all independently.
>
> Hence my point: the header with the register definition must be the
> source of truth on the different register behaviors*. The additional
> type checks only help in some cases, and make it harder to handle
> others.
With xe it seems like we have a lot fewer areas where multiple types
become harder. IIRC, the biggest pain points on i915 were GVT and
cmd_parser since both of those needed to provide giant lists of
registers with MCR and non-MCR mixed together. Both of those are no
longer relevant to Xe, so I think the main areas that will still have a
bit of pain are:
* OA/perf register lists
* userspace whitelist (although I'm not sure if we ever whitelist MCR
registers...userspace would have difficult steering to specific
instances)
>
> On the other hand, I think the different types would be handy when/if we
> have the following:
>
> #define xe_mmio_read32(reg) _Generic((reg), \
> xe_reg_t: xe_mmio_raw_read32((reg).reg), \
> xe_reg_mcr_t: xe_gt_mcr_read32(reg),
Unfortunately there's a trap here. There are multiple ways to read (and
write) a multicast register and it's very important that you explicitly
pick the proper semantics to use. Sometimes you want just want to read
any random instance's value (e.g., when verifying that workarounds
stuck), but in other cases you need to read and process every single
instance independently (various error reporting, INSTDONE, etc.
registers). Likewise, sometimes it's okay to broadcast a single value
into every instance of the register, but other times we potentially need
to write different values into each instance, or even do per-instance
RMW's to avoid clobbering other bitfields.
Matt
> )
>
> because that would eliminate an entire class of bugs, encoding in each
> call place what is the right function to be called based on the
> declaration in the header, with no additional overhead...
>
> Lucas De Marchi
>
> * https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/204 and ideally
> be generated from the spec with proper filters in place so we don't
> blow out the size of our headers. My goal is to clean our headers and
> have them in a state that would be 90% identical to something
> generated by a script parsing the spec.
>
> >
> >
> > Matt
> >
> > >
> > > Besides, there is no such user in display/
> > >
> > > $ git grep xe_gt_mcr -- drivers/gpu/drm/xe/display/
> > >
> > >
> > > Lucas De Marchi
> >
> > --
> > Matt Roper
> > Graphics Software Engineer
> > Linux GPU Platform Enablement
> > Intel Corporation
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [Intel-xe] [PATCH 11/17] drm/xe: Introduce xe_reg_t
2023-04-19 23:14 ` Matt Roper
@ 2023-04-19 23:38 ` Lucas De Marchi
0 siblings, 0 replies; 41+ messages in thread
From: Lucas De Marchi @ 2023-04-19 23:38 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe, Rodrigo Vivi
On Wed, Apr 19, 2023 at 04:14:45PM -0700, Matt Roper wrote:
>On Wed, Apr 19, 2023 at 02:09:20PM -0700, Lucas De Marchi wrote:
>> On Wed, Apr 19, 2023 at 01:24:31PM -0700, Matt Roper wrote:
>> > On Wed, Apr 19, 2023 at 01:19:49PM -0700, Lucas De Marchi wrote:
>> > > On Wed, Apr 19, 2023 at 03:30:17PM -0400, Rodrigo Vivi wrote:
>> > > > On Wed, Apr 19, 2023 at 11:49:56AM -0700, Lucas De Marchi wrote:
>> > > > > On Wed, Apr 19, 2023 at 10:33:45AM -0700, Matt Roper wrote:
>> > > > > > On Wed, Apr 19, 2023 at 12:44:34AM -0700, Lucas De Marchi wrote:
>> > > > > > > Stop using i915 types for register our own xe_reg_t. Differently from
>> > > > > > > i915, this will keep under this will keep under the register definition
>> > > > > > > the knowledge for the different types of registers. For now, the "flags"
>> > > > > > > are mcr and masked, although only the former is being used.
>> > > > > > >
>> > > > > > > Most of the driver is agnostic to the register differences. Convert the
>> > > > > > > few places that care about that, namely xe_gt_mcr.c, to take the generic
>> > > > > > > type and warn if the wrong register is used.
>> > > > > >
>> > > > > > The disadvantage of this approach is that we don't get the nice
>> > > > > > type-checking that we have in i915 to catch register misuse at build
>> > > > > > time. Instead we wind up with a bunch of run-time checks that only tell
>> > > > > > you that you used the wrong register semantics after the fact. Wouldn't
>> > > > > > it be better to keep the strict types and let the compiler find mistakes
>> > > > > > for us at build time?
>> > > > > >
>> > > > > > The only real problem with using strict types is that there are a few
>> > > > > > places where the driver is just trying to refer to registers/offsets
>> > > > > > without actually accessing them (e.g., whitelists, OA register groups,
>> > > > >
>> > > > > that is not true.
>> > > > >
>> > > > > > etc.) and the strict typing makes it harder to provide a heterogeneous
>> > > > > > list of those registers. But I still feel the benefits of compile-time
>> > > > > > checking outweighs the extra complexity we wind up with in a handful of
>> > > > > > places.
>> > > > >
>> > > > > I disagree here because the strict type checking is only checking for
>> > > > > "regular vs mcr". Add "masked" in the mix (that has been a huge source
>> > > > > of mistakes in i915) and you already have 4 types(?) to deal with.
>> > > > >
>> > > > > There are also places in the code where we want that "this is an
>> > > > > mcr/regular/masked register" info to be used later. See how the reg-sr is
>> > > > > handling that.
>> > > > >
>> > > > > In the end I believe having this info encoded in the regs/*.h is
>> > > > > sufficient to avoid the mistakes we had in the past.
>> > > > >
>> > > > > Any change in the code triggering these warnings has a very easy an
>> > > > > actionable fix.
>> > > > >
>> > > > > If for some reason we want to only differentiate mcr/normal as strict
>> > > > > type checks, then I think we need to provide a better struct for the
>> > > > > places that don't care about that. Something like below maybe
>> > > > >
>> > > > > typedef {
>> > > > > xe_reg_t reg;
>> > > > > } xe_reg_mcr_t;
>> > > > >
>> > > > > but reg.mcr still being there. Or going the other way around:
>> > > > >
>> > > > > typedef union {
>> > > > > xe_reg_normal_t normal;
>> > > > > xe_reg_mcr_t mcr;
>> > > > > } xe_reg_t;
>> > > > >
>> > > > > but xe_reg_normal_t and xe_reg_mcr_t actually having the same defintion.
>> > > > >
>> > > > > Lucas De Marchi
>> > > >
>> > > > I honestly liked the approach you took on this patch here. Getting rid of
>> > > > the i915_mcr is already a win by itself.
>> > > >
>> > > > One case that came to my mind though is some time sensitive mmio operations
>> > > > like display inside vblank areas. any runtime check could potentially
>> > > > increase latency, no?! If that's irrelevant time, than let's move with this
>> > > > but if it is really a problem, then explore your latest suggestion here
>> > > > with the compiler doing the checks for us seems a good alternative.
>> > >
>> > > the additional check is inside xe_gt_mcr.c... I think the additional
>> > > check is negligible compared to the other operations there, with each
>> > > access to reg X requiring other 2 mmio accesses to take place.
>> >
>> > The super critical checks (which don't exist yet in this series; they'd
>> > presumably be added in a follow-up series) are the ones to make sure you
>> > don't try to call xe_mmio_{read,write}32() on an MCR register. Doing
>> > that can lead to all kinds of subtle bugs (which become even more
>> > problematic on the more recent platforms), and unfortunately that kind
>> > of mistake is what people are going to write in the code 99% of the time
>> > out of habit.
>>
>> I'm not sure when that would happen... when the next GPU changes a register
>> from normal to MCR, we rightfully updated the header to update its type
>> and forgot to change the calls using that register?
>
>It happened really frequently on i915 until we finally added the strict
>typing. It's not a matter of adding new platforms, it's a matter of
>just writing new code in the driver (generally for platforms we already
>have and with register definitions that already exist). When someone
>needs to add a new register read/write operation for something they're
>working on, they'll generally reach for xe_mmio_*() out of habit (or
>intel_uncore_*() on i915) since that's what gets used for 90% of
>register accesses. If the register is actually an MCR register, and the
>compiler doesn't catch this for you, then you just wind up with
>incorrect semantics at runtime.
>
>Of course nothing is foolproof. If the read/write is against a
>completely new register, and the patch is adding both an incorrect
>register definition _and_ an incorrect usage at the same time, then the
>compiler won't help there. Although the fact that a completely new
>register is being defined makes it slightly more likely that the
>reviewers will scrutinize the register details more carefully and catch
>the incorrect definition. It's a shame that the MCR nature of registers
>isn't documented more clearly in the bspec...
>
>Cases where the same register changed type between platforms is also a
>problematic case that will never be foolproof since we wind up with
>multiple definitions for the same register offset; if you pick the wrong
>definition _and_ the wrong access semantics, then the compiler won't be
>able to catch that either. But again, the multiple definitions with
>different types will still make it more likely that the developer and/or
>reviewer take a closer look and realize the mistake.
>
>>
>> Currently xe_mmio_* receives u32 and we just do FOO.reg, with reg being the
>
>Right, this is obviously completely wrong and was something I raised as
>a concern months ago when the first Xe megapatch got posted. I started
>typing up a fix for that a few weeks ago but got sidetracked and didn't
>finish it. xe_mmio_* should obviously be accepting i915_reg_t (or a new
>Xe-specific equivalent) rather than a u32. That will protect against
>both the 'misordered parameters' problem Jani mentioned, as well as the
>'used wrong function on an MCR register' problem that was problematic on
>i915.
>
>> name both in i915_reg_t and i915_mcr_reg_t. So, right now the different
>> types are not helping anything. I'm planning to add xe_reg_t to
>> xe_mmio_* and have a companion xe_mmio_raw_* for the cases we use a u32
>> (one of the reasons being because xe_gt_mcr.c itself also needs to call
>> xe_mmio_*)
>>
>> How does the type protect us against "daily task of enabling the next
>> generation of GPUs?":
>>
>> - gpu version N+1 changed register FOO from normal to MCR.
>> we didn't notice the register changed. Type doesn't help
>> because we are still using the old one. If we did notice,
>> the type would only help if adopted the approach "change the
>> type", build and see what breaks to fix it, which is IMO
>> worse than a git-grep approach.
>>
>> That would mean the hw changed a register from being MCR to being a
>> normal register which is more rare than the oppposite: a normal register
>> becoming MCR.
>
>The strict type safety protects us in both directions. xe_mmio_* only
>takes unicast registers (after the obvious fixes to replace the u32
>parameters), xe_gt_mcr_* only takes MCR registers. If you pass the
>wrong register type to either type of function, the compiler catches it
>immediately. As you noted, it's still possible to combine two bugs
>(incorrect register definition + wrong usage semantics) to sneak by the
>compiler; that will surely still happen, but we've raised the bar and
>made it harder.
>
>Having registers change between MCR and non-MCR between platforms is
>still a problem, but not the most common one based on past history. The
>much more common source of problems is people just writing new code that
>uses registers we already have in the driver. Assuming the definition
>is correct, the new code has to be correct too to get past the compiler.
>If all registers become the same type, as you're moving toward in this
>series, you could also probably get similar guardrails by turning
>xe_mmio_*() into macros that do a BUILD_BUG_ON() before calling the a
>real __xe_mmio_*() function, although then you run into issues anywhere
>that non-constant register variables get passed up/down the callstack.
>
>>
>> Even if we do the strict type, it doesn't protect us from such mistakes
>> when we have a normal register becoming MCR. We will have this:
>>
>> #define FOO XE_REG(10)
>>
>> and will continue to happily call xe_mmio_* even if in version X of the
>> GPU the register is now mcr.
>
>When enabling a new platform and implementing the MCR stuff for the
>first time, we do need to be careful to not only add the new ranges to
>the driver, but also to go analyze any registers that live in a range
>that changed. If there's code that will still be executed that works on
>those registers, then we need to figure out how that code needs to
>change. We can't automatically assume that writes should become
>broadcast_writes and that reads should become read_any's (although
>that's the most common outcome); in some situations we actually need to
>re-write the code to loop through the various hardware instances and
>handle them all independently.
>
>>
>> Hence my point: the header with the register definition must be the
>> source of truth on the different register behaviors*. The additional
>> type checks only help in some cases, and make it harder to handle
>> others.
>
>With xe it seems like we have a lot fewer areas where multiple types
>become harder. IIRC, the biggest pain points on i915 were GVT and
>cmd_parser since both of those needed to provide giant lists of
>registers with MCR and non-MCR mixed together. Both of those are no
>longer relevant to Xe, so I think the main areas that will still have a
>bit of pain are:
> * OA/perf register lists
> * userspace whitelist (although I'm not sure if we ever whitelist MCR
> registers...userspace would have difficult steering to specific
> instances)
>
>>
>> On the other hand, I think the different types would be handy when/if we
>> have the following:
>>
>> #define xe_mmio_read32(reg) _Generic((reg), \
>> xe_reg_t: xe_mmio_raw_read32((reg).reg), \
>> xe_reg_mcr_t: xe_gt_mcr_read32(reg),
>
>Unfortunately there's a trap here. There are multiple ways to read (and
>write) a multicast register and it's very important that you explicitly
>pick the proper semantics to use. Sometimes you want just want to read
>any random instance's value (e.g., when verifying that workarounds
>stuck), but in other cases you need to read and process every single
>instance independently (various error reporting, INSTDONE, etc.
>registers). Likewise, sometimes it's okay to broadcast a single value
>into every instance of the register, but other times we potentially need
>to write different values into each instance, or even do per-instance
>RMW's to avoid clobbering other bitfields.
I still think the extra type gives more a false sense of safety here.
Anyway, it seems an area we've had issues in the past and it will be
hard to reach a consensus on changing it. If we were talking about this
a few days ago, I'd be very sad because that'd meant my plans to fixup
the hacky #undef in the rtp part was dead in the water. However with the
new macros I think I can workaround that and work with both types.
So... going back to what I said above:
typedef {
xe_reg_t reg;
} xe_reg_mcr_t;
Would you be ok with that? The information I need would still be
available in the register definition.
Inside xe_gt_mcr.c it then does an up-cast.
We keep the up-cast macro private to xe_gt_mcr.c so nobody tries to use
it elsewhere. Example:
u32 xe_gt_mcr_unicast_read_any(struct xe_gt *gt, xe_reg_mcr_t mcr_reg)
{
const xe_reg_t reg = to_xe_reg(mcr_reg);
...
}
... probably to be done only in the few functions accessing reg.*, not
the ones passing it around. And then we probably need to rename reg to
"addr" or "off".
Thoughts?
thanks
Lucas De Marchi
^ permalink raw reply [flat|nested] 41+ messages in thread
end of thread, other threads:[~2023-04-19 23:38 UTC | newest]
Thread overview: 41+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-04-19 7:44 [Intel-xe] [PATCH 00/17] Cleanup registers and introduce xe_reg_t Lucas De Marchi
2023-04-19 7:44 ` [Intel-xe] [PATCH 01/17] drm/xe: Cleanup page-related defines Lucas De Marchi
2023-04-19 7:44 ` [Intel-xe] [PATCH 02/17] fixup! drm/i915/display: Remaining changes to make xe compile Lucas De Marchi
2023-04-19 7:44 ` [Intel-xe] [PATCH 03/17] fixup! drm/i915/display: Allow fbdev to allocate stolen memory Lucas De Marchi
2023-04-19 7:44 ` [Intel-xe] [PATCH 04/17] drm/xe: Rename RC0/RC6 macros Lucas De Marchi
2023-04-19 7:44 ` [Intel-xe] [PATCH 05/17] drm/xe: Rename instruction field to avoid confusion Lucas De Marchi
2023-04-19 7:44 ` [Intel-xe] [PATCH 06/17] drm/xe/guc: Rename GEN11_SOFT_SCRATCH for clarity Lucas De Marchi
2023-04-19 7:44 ` [Intel-xe] [PATCH 07/17] drm/xe/guc: Move GuC registers to regs/ Lucas De Marchi
2023-04-19 7:44 ` [Intel-xe] [PATCH 08/17] drm/xe/guc: Convert GuC registers to REG_FIELD/REG_BIT Lucas De Marchi
2023-04-19 7:44 ` [Intel-xe] [PATCH 09/17] drm/xe: Drop gen prefixes and suffixes from registers Lucas De Marchi
2023-04-19 7:44 ` [Intel-xe] [PATCH 10/17] drm/xe: Use REG_FIELD/REG_BIT for all regs/*.h Lucas De Marchi
2023-04-19 7:44 ` [Intel-xe] [PATCH 11/17] drm/xe: Introduce xe_reg_t Lucas De Marchi
2023-04-19 16:06 ` Jani Nikula
2023-04-19 17:17 ` Lucas De Marchi
2023-04-19 19:39 ` Jani Nikula
2023-04-19 20:30 ` Lucas De Marchi
2023-04-19 17:33 ` Matt Roper
2023-04-19 18:49 ` Lucas De Marchi
2023-04-19 19:30 ` Rodrigo Vivi
2023-04-19 20:19 ` Lucas De Marchi
2023-04-19 20:24 ` Matt Roper
2023-04-19 21:09 ` Lucas De Marchi
2023-04-19 23:14 ` Matt Roper
2023-04-19 23:38 ` Lucas De Marchi
2023-04-19 19:49 ` Jani Nikula
2023-04-19 20:13 ` Lucas De Marchi
2023-04-19 20:13 ` Matt Roper
2023-04-19 21:24 ` Lucas De Marchi
2023-04-19 7:44 ` [Intel-xe] [PATCH 12/17] drm/xe: Clarify register types on PAT programming Lucas De Marchi
2023-04-19 7:44 ` [Intel-xe] [PATCH 13/17] drm/xe/rtp: Improve magic macros for RTP tables Lucas De Marchi
2023-04-19 7:44 ` [Intel-xe] [PATCH 14/17] drm/xe: Add XE_REG/XE_REG_MCR Lucas De Marchi
2023-04-19 7:44 ` [Intel-xe] [PATCH 15/17] drm/xe: Annotate masked registers used by RTP Lucas De Marchi
2023-04-19 7:44 ` [Intel-xe] [PATCH 16/17] drm/xe: Plumb xe_reg_t into WAs, rtp, etc Lucas De Marchi
2023-04-19 16:15 ` Jani Nikula
2023-04-19 7:44 ` [Intel-xe] [PATCH 17/17] drm/xe: Move helper macros to separate header Lucas De Marchi
2023-04-19 16:17 ` Jani Nikula
2023-04-19 17:06 ` Lucas De Marchi
2023-04-19 7:47 ` [Intel-xe] ✓ CI.Patch_applied: success for Cleanup registers and introduce xe_reg_t Patchwork
2023-04-19 7:48 ` [Intel-xe] ✓ CI.KUnit: " Patchwork
2023-04-19 7:52 ` [Intel-xe] ✓ CI.Build: " Patchwork
2023-04-19 8:12 ` [Intel-xe] ○ CI.BAT: info " Patchwork
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox