* ✗ CI.checkpatch: warning for Add get-error-counter and clear-error-counter support for CRI (rev4)
2026-05-04 6:56 [PATCH v5 0/6] Add get-error-counter and clear-error-counter support for CRI Riana Tauro
@ 2026-05-04 6:43 ` Patchwork
2026-05-04 6:45 ` ✓ CI.KUnit: success " Patchwork
` (7 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2026-05-04 6:43 UTC (permalink / raw)
To: Riana Tauro; +Cc: intel-xe
== Series Details ==
Series: Add get-error-counter and clear-error-counter support for CRI (rev4)
URL : https://patchwork.freedesktop.org/series/164393/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
c8c12e558adaef7a4d125d83b6e1f8824bc13b82
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 579a341de8b50abc89db2a8ef738f27d185e1b2f
Author: Riana Tauro <riana.tauro@intel.com>
Date: Mon May 4 12:26:21 2026 +0530
drm/xe/xe_ras: Control xe drm_ras registration with a flag
Add a flag to control xe drm_ras registration.
Enable this flag for PVC and CRI to support exposing RAS error counters via netlink.
Signed-off-by: Riana Tauro <riana.tauro@intel.com>
+ /mt/dim checkpatch 59b0faed1d239bc0f433999671c2d195bd62f9b8 drm-intel
b190520f86c7 drm/xe/uapi: Add additional error components to xe drm_ras
d706ccb20437 drm/xe/xe_ras: Add support to get error counter in CRI
-:42: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#42: FILE: drivers/gpu/drm/xe/xe_ras.c:64:
+};
+static_assert(ARRAY_SIZE(drm_to_xe_ras_component) == DRM_XE_RAS_ERR_COMP_MAX);
-:49: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#49: FILE: drivers/gpu/drm/xe/xe_ras.c:71:
+};
+static_assert(ARRAY_SIZE(drm_to_xe_ras_severity) == DRM_XE_RAS_ERR_SEV_MAX);
total: 0 errors, 0 warnings, 2 checks, 176 lines checked
c5efb7b17ae1 drm/xe/xe_ras: Add helper to clear error counter
fd5de937474e drm/xe/xe_drm_ras: Wire get-error-counter and clear-error-counter support for CRI
4108f84f6825 drm/xe/xe_ras: Move xe drm_ras registration
579a341de8b5 drm/xe/xe_ras: Control xe drm_ras registration with a flag
-:7: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible unwrapped commit description?)
#7:
Enable this flag for PVC and CRI to support exposing RAS error counters via netlink.
-:19: WARNING:LONG_LINE_COMMENT: line length of 109 exceeds 100 columns
#19: FILE: drivers/gpu/drm/xe/xe_device_types.h:158:
+ /** @info.has_drm_ras: Device supports drm_ras (Reliability, Availability, Serviceability) */
total: 0 errors, 2 warnings, 0 checks, 44 lines checked
^ permalink raw reply [flat|nested] 14+ messages in thread
* ✓ CI.KUnit: success for Add get-error-counter and clear-error-counter support for CRI (rev4)
2026-05-04 6:56 [PATCH v5 0/6] Add get-error-counter and clear-error-counter support for CRI Riana Tauro
2026-05-04 6:43 ` ✗ CI.checkpatch: warning for Add get-error-counter and clear-error-counter support for CRI (rev4) Patchwork
@ 2026-05-04 6:45 ` Patchwork
2026-05-04 6:56 ` [PATCH v5 1/6] drm/xe/uapi: Add additional error components to xe drm_ras Riana Tauro
` (6 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2026-05-04 6:45 UTC (permalink / raw)
To: Riana Tauro; +Cc: intel-xe
== Series Details ==
Series: Add get-error-counter and clear-error-counter support for CRI (rev4)
URL : https://patchwork.freedesktop.org/series/164393/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[06:43:49] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[06:43:53] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[06:44:25] Starting KUnit Kernel (1/1)...
[06:44:25] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[06:44:25] ================== guc_buf (11 subtests) ===================
[06:44:25] [PASSED] test_smallest
[06:44:25] [PASSED] test_largest
[06:44:25] [PASSED] test_granular
[06:44:25] [PASSED] test_unique
[06:44:25] [PASSED] test_overlap
[06:44:25] [PASSED] test_reusable
[06:44:25] [PASSED] test_too_big
[06:44:25] [PASSED] test_flush
[06:44:25] [PASSED] test_lookup
[06:44:25] [PASSED] test_data
[06:44:25] [PASSED] test_class
[06:44:25] ===================== [PASSED] guc_buf =====================
[06:44:25] =================== guc_dbm (7 subtests) ===================
[06:44:25] [PASSED] test_empty
[06:44:25] [PASSED] test_default
[06:44:25] ======================== test_size ========================
[06:44:25] [PASSED] 4
[06:44:25] [PASSED] 8
[06:44:25] [PASSED] 32
[06:44:25] [PASSED] 256
[06:44:25] ==================== [PASSED] test_size ====================
[06:44:25] ======================= test_reuse ========================
[06:44:25] [PASSED] 4
[06:44:25] [PASSED] 8
[06:44:25] [PASSED] 32
[06:44:25] [PASSED] 256
[06:44:25] =================== [PASSED] test_reuse ====================
[06:44:25] =================== test_range_overlap ====================
[06:44:25] [PASSED] 4
[06:44:25] [PASSED] 8
[06:44:25] [PASSED] 32
[06:44:25] [PASSED] 256
[06:44:25] =============== [PASSED] test_range_overlap ================
[06:44:25] =================== test_range_compact ====================
[06:44:25] [PASSED] 4
[06:44:25] [PASSED] 8
[06:44:25] [PASSED] 32
[06:44:25] [PASSED] 256
[06:44:25] =============== [PASSED] test_range_compact ================
[06:44:25] ==================== test_range_spare =====================
[06:44:25] [PASSED] 4
[06:44:25] [PASSED] 8
[06:44:25] [PASSED] 32
[06:44:25] [PASSED] 256
[06:44:25] ================ [PASSED] test_range_spare =================
[06:44:25] ===================== [PASSED] guc_dbm =====================
[06:44:25] =================== guc_idm (6 subtests) ===================
[06:44:25] [PASSED] bad_init
[06:44:25] [PASSED] no_init
[06:44:25] [PASSED] init_fini
[06:44:25] [PASSED] check_used
[06:44:25] [PASSED] check_quota
[06:44:25] [PASSED] check_all
[06:44:25] ===================== [PASSED] guc_idm =====================
[06:44:25] ================== no_relay (3 subtests) ===================
[06:44:25] [PASSED] xe_drops_guc2pf_if_not_ready
[06:44:25] [PASSED] xe_drops_guc2vf_if_not_ready
[06:44:25] [PASSED] xe_rejects_send_if_not_ready
[06:44:25] ==================== [PASSED] no_relay =====================
[06:44:25] ================== pf_relay (14 subtests) ==================
[06:44:25] [PASSED] pf_rejects_guc2pf_too_short
[06:44:25] [PASSED] pf_rejects_guc2pf_too_long
[06:44:25] [PASSED] pf_rejects_guc2pf_no_payload
[06:44:25] [PASSED] pf_fails_no_payload
[06:44:25] [PASSED] pf_fails_bad_origin
[06:44:25] [PASSED] pf_fails_bad_type
[06:44:25] [PASSED] pf_txn_reports_error
[06:44:25] [PASSED] pf_txn_sends_pf2guc
[06:44:25] [PASSED] pf_sends_pf2guc
[06:44:25] [SKIPPED] pf_loopback_nop
[06:44:25] [SKIPPED] pf_loopback_echo
[06:44:25] [SKIPPED] pf_loopback_fail
[06:44:25] [SKIPPED] pf_loopback_busy
[06:44:25] [SKIPPED] pf_loopback_retry
[06:44:25] ==================== [PASSED] pf_relay =====================
[06:44:25] ================== vf_relay (3 subtests) ===================
[06:44:25] [PASSED] vf_rejects_guc2vf_too_short
[06:44:25] [PASSED] vf_rejects_guc2vf_too_long
[06:44:25] [PASSED] vf_rejects_guc2vf_no_payload
[06:44:25] ==================== [PASSED] vf_relay =====================
[06:44:25] ================ pf_gt_config (9 subtests) =================
[06:44:25] [PASSED] fair_contexts_1vf
[06:44:25] [PASSED] fair_doorbells_1vf
[06:44:25] [PASSED] fair_ggtt_1vf
[06:44:25] ====================== fair_vram_1vf ======================
[06:44:25] [PASSED] 3.50 GiB
[06:44:25] [PASSED] 11.5 GiB
[06:44:25] [PASSED] 15.5 GiB
[06:44:25] [PASSED] 31.5 GiB
[06:44:25] [PASSED] 63.5 GiB
[06:44:25] [PASSED] 1.91 GiB
[06:44:25] ================== [PASSED] fair_vram_1vf ==================
[06:44:25] ================ fair_vram_1vf_admin_only =================
[06:44:25] [PASSED] 3.50 GiB
[06:44:25] [PASSED] 11.5 GiB
[06:44:25] [PASSED] 15.5 GiB
[06:44:25] [PASSED] 31.5 GiB
[06:44:25] [PASSED] 63.5 GiB
[06:44:25] [PASSED] 1.91 GiB
[06:44:25] ============ [PASSED] fair_vram_1vf_admin_only =============
[06:44:25] ====================== fair_contexts ======================
[06:44:25] [PASSED] 1 VF
[06:44:25] [PASSED] 2 VFs
[06:44:25] [PASSED] 3 VFs
[06:44:25] [PASSED] 4 VFs
[06:44:25] [PASSED] 5 VFs
[06:44:25] [PASSED] 6 VFs
[06:44:25] [PASSED] 7 VFs
[06:44:25] [PASSED] 8 VFs
[06:44:25] [PASSED] 9 VFs
[06:44:25] [PASSED] 10 VFs
[06:44:25] [PASSED] 11 VFs
[06:44:25] [PASSED] 12 VFs
[06:44:25] [PASSED] 13 VFs
[06:44:25] [PASSED] 14 VFs
[06:44:25] [PASSED] 15 VFs
[06:44:25] [PASSED] 16 VFs
[06:44:25] [PASSED] 17 VFs
[06:44:25] [PASSED] 18 VFs
[06:44:25] [PASSED] 19 VFs
[06:44:25] [PASSED] 20 VFs
[06:44:25] [PASSED] 21 VFs
[06:44:25] [PASSED] 22 VFs
[06:44:25] [PASSED] 23 VFs
[06:44:25] [PASSED] 24 VFs
[06:44:25] [PASSED] 25 VFs
[06:44:25] [PASSED] 26 VFs
[06:44:25] [PASSED] 27 VFs
[06:44:25] [PASSED] 28 VFs
[06:44:25] [PASSED] 29 VFs
[06:44:25] [PASSED] 30 VFs
[06:44:25] [PASSED] 31 VFs
[06:44:25] [PASSED] 32 VFs
[06:44:25] [PASSED] 33 VFs
[06:44:25] [PASSED] 34 VFs
[06:44:25] [PASSED] 35 VFs
[06:44:25] [PASSED] 36 VFs
[06:44:25] [PASSED] 37 VFs
[06:44:25] [PASSED] 38 VFs
[06:44:25] [PASSED] 39 VFs
[06:44:25] [PASSED] 40 VFs
[06:44:25] [PASSED] 41 VFs
[06:44:25] [PASSED] 42 VFs
[06:44:25] [PASSED] 43 VFs
[06:44:25] [PASSED] 44 VFs
[06:44:25] [PASSED] 45 VFs
[06:44:25] [PASSED] 46 VFs
[06:44:25] [PASSED] 47 VFs
[06:44:25] [PASSED] 48 VFs
[06:44:25] [PASSED] 49 VFs
[06:44:25] [PASSED] 50 VFs
[06:44:25] [PASSED] 51 VFs
[06:44:25] [PASSED] 52 VFs
[06:44:25] [PASSED] 53 VFs
[06:44:25] [PASSED] 54 VFs
[06:44:25] [PASSED] 55 VFs
[06:44:25] [PASSED] 56 VFs
[06:44:25] [PASSED] 57 VFs
[06:44:25] [PASSED] 58 VFs
[06:44:25] [PASSED] 59 VFs
[06:44:25] [PASSED] 60 VFs
[06:44:25] [PASSED] 61 VFs
[06:44:25] [PASSED] 62 VFs
[06:44:25] [PASSED] 63 VFs
[06:44:25] ================== [PASSED] fair_contexts ==================
[06:44:25] ===================== fair_doorbells ======================
[06:44:25] [PASSED] 1 VF
[06:44:25] [PASSED] 2 VFs
[06:44:25] [PASSED] 3 VFs
[06:44:25] [PASSED] 4 VFs
[06:44:25] [PASSED] 5 VFs
[06:44:25] [PASSED] 6 VFs
[06:44:25] [PASSED] 7 VFs
[06:44:25] [PASSED] 8 VFs
[06:44:25] [PASSED] 9 VFs
[06:44:25] [PASSED] 10 VFs
[06:44:25] [PASSED] 11 VFs
[06:44:25] [PASSED] 12 VFs
[06:44:25] [PASSED] 13 VFs
[06:44:25] [PASSED] 14 VFs
[06:44:25] [PASSED] 15 VFs
[06:44:25] [PASSED] 16 VFs
[06:44:25] [PASSED] 17 VFs
[06:44:25] [PASSED] 18 VFs
[06:44:25] [PASSED] 19 VFs
[06:44:25] [PASSED] 20 VFs
[06:44:25] [PASSED] 21 VFs
[06:44:25] [PASSED] 22 VFs
[06:44:25] [PASSED] 23 VFs
[06:44:25] [PASSED] 24 VFs
[06:44:25] [PASSED] 25 VFs
[06:44:25] [PASSED] 26 VFs
[06:44:25] [PASSED] 27 VFs
[06:44:25] [PASSED] 28 VFs
[06:44:25] [PASSED] 29 VFs
[06:44:25] [PASSED] 30 VFs
[06:44:25] [PASSED] 31 VFs
[06:44:25] [PASSED] 32 VFs
[06:44:25] [PASSED] 33 VFs
[06:44:25] [PASSED] 34 VFs
[06:44:25] [PASSED] 35 VFs
[06:44:25] [PASSED] 36 VFs
[06:44:25] [PASSED] 37 VFs
[06:44:25] [PASSED] 38 VFs
[06:44:25] [PASSED] 39 VFs
[06:44:25] [PASSED] 40 VFs
[06:44:25] [PASSED] 41 VFs
[06:44:25] [PASSED] 42 VFs
[06:44:25] [PASSED] 43 VFs
[06:44:25] [PASSED] 44 VFs
[06:44:25] [PASSED] 45 VFs
[06:44:25] [PASSED] 46 VFs
[06:44:25] [PASSED] 47 VFs
[06:44:25] [PASSED] 48 VFs
[06:44:25] [PASSED] 49 VFs
[06:44:25] [PASSED] 50 VFs
[06:44:25] [PASSED] 51 VFs
[06:44:25] [PASSED] 52 VFs
[06:44:25] [PASSED] 53 VFs
[06:44:25] [PASSED] 54 VFs
[06:44:25] [PASSED] 55 VFs
[06:44:25] [PASSED] 56 VFs
[06:44:25] [PASSED] 57 VFs
[06:44:25] [PASSED] 58 VFs
[06:44:25] [PASSED] 59 VFs
[06:44:25] [PASSED] 60 VFs
[06:44:25] [PASSED] 61 VFs
[06:44:25] [PASSED] 62 VFs
[06:44:25] [PASSED] 63 VFs
[06:44:25] ================= [PASSED] fair_doorbells ==================
[06:44:25] ======================== fair_ggtt ========================
[06:44:25] [PASSED] 1 VF
[06:44:25] [PASSED] 2 VFs
[06:44:25] [PASSED] 3 VFs
[06:44:25] [PASSED] 4 VFs
[06:44:25] [PASSED] 5 VFs
[06:44:25] [PASSED] 6 VFs
[06:44:25] [PASSED] 7 VFs
[06:44:25] [PASSED] 8 VFs
[06:44:25] [PASSED] 9 VFs
[06:44:25] [PASSED] 10 VFs
[06:44:25] [PASSED] 11 VFs
[06:44:25] [PASSED] 12 VFs
[06:44:25] [PASSED] 13 VFs
[06:44:25] [PASSED] 14 VFs
[06:44:25] [PASSED] 15 VFs
[06:44:25] [PASSED] 16 VFs
[06:44:25] [PASSED] 17 VFs
[06:44:25] [PASSED] 18 VFs
[06:44:25] [PASSED] 19 VFs
[06:44:25] [PASSED] 20 VFs
[06:44:25] [PASSED] 21 VFs
[06:44:25] [PASSED] 22 VFs
[06:44:25] [PASSED] 23 VFs
[06:44:25] [PASSED] 24 VFs
[06:44:25] [PASSED] 25 VFs
[06:44:25] [PASSED] 26 VFs
[06:44:25] [PASSED] 27 VFs
[06:44:25] [PASSED] 28 VFs
[06:44:25] [PASSED] 29 VFs
[06:44:25] [PASSED] 30 VFs
[06:44:25] [PASSED] 31 VFs
[06:44:25] [PASSED] 32 VFs
[06:44:25] [PASSED] 33 VFs
[06:44:25] [PASSED] 34 VFs
[06:44:25] [PASSED] 35 VFs
[06:44:25] [PASSED] 36 VFs
[06:44:25] [PASSED] 37 VFs
[06:44:25] [PASSED] 38 VFs
[06:44:25] [PASSED] 39 VFs
[06:44:25] [PASSED] 40 VFs
[06:44:25] [PASSED] 41 VFs
[06:44:25] [PASSED] 42 VFs
[06:44:25] [PASSED] 43 VFs
[06:44:25] [PASSED] 44 VFs
[06:44:25] [PASSED] 45 VFs
[06:44:25] [PASSED] 46 VFs
[06:44:25] [PASSED] 47 VFs
[06:44:25] [PASSED] 48 VFs
[06:44:25] [PASSED] 49 VFs
[06:44:25] [PASSED] 50 VFs
[06:44:25] [PASSED] 51 VFs
[06:44:25] [PASSED] 52 VFs
[06:44:25] [PASSED] 53 VFs
[06:44:25] [PASSED] 54 VFs
[06:44:25] [PASSED] 55 VFs
[06:44:25] [PASSED] 56 VFs
[06:44:25] [PASSED] 57 VFs
[06:44:25] [PASSED] 58 VFs
[06:44:25] [PASSED] 59 VFs
[06:44:25] [PASSED] 60 VFs
[06:44:25] [PASSED] 61 VFs
[06:44:25] [PASSED] 62 VFs
[06:44:25] [PASSED] 63 VFs
[06:44:25] ==================== [PASSED] fair_ggtt ====================
[06:44:25] ======================== fair_vram ========================
[06:44:25] [PASSED] 1 VF
[06:44:25] [PASSED] 2 VFs
[06:44:25] [PASSED] 3 VFs
[06:44:25] [PASSED] 4 VFs
[06:44:25] [PASSED] 5 VFs
[06:44:25] [PASSED] 6 VFs
[06:44:25] [PASSED] 7 VFs
[06:44:25] [PASSED] 8 VFs
[06:44:25] [PASSED] 9 VFs
[06:44:25] [PASSED] 10 VFs
[06:44:25] [PASSED] 11 VFs
[06:44:25] [PASSED] 12 VFs
[06:44:25] [PASSED] 13 VFs
[06:44:25] [PASSED] 14 VFs
[06:44:25] [PASSED] 15 VFs
[06:44:25] [PASSED] 16 VFs
[06:44:25] [PASSED] 17 VFs
[06:44:25] [PASSED] 18 VFs
[06:44:25] [PASSED] 19 VFs
[06:44:25] [PASSED] 20 VFs
[06:44:25] [PASSED] 21 VFs
[06:44:25] [PASSED] 22 VFs
[06:44:25] [PASSED] 23 VFs
[06:44:25] [PASSED] 24 VFs
[06:44:25] [PASSED] 25 VFs
[06:44:25] [PASSED] 26 VFs
[06:44:25] [PASSED] 27 VFs
[06:44:25] [PASSED] 28 VFs
[06:44:25] [PASSED] 29 VFs
[06:44:25] [PASSED] 30 VFs
[06:44:25] [PASSED] 31 VFs
[06:44:25] [PASSED] 32 VFs
[06:44:25] [PASSED] 33 VFs
[06:44:25] [PASSED] 34 VFs
[06:44:25] [PASSED] 35 VFs
[06:44:25] [PASSED] 36 VFs
[06:44:25] [PASSED] 37 VFs
[06:44:25] [PASSED] 38 VFs
[06:44:25] [PASSED] 39 VFs
[06:44:25] [PASSED] 40 VFs
[06:44:25] [PASSED] 41 VFs
[06:44:25] [PASSED] 42 VFs
[06:44:25] [PASSED] 43 VFs
[06:44:25] [PASSED] 44 VFs
[06:44:25] [PASSED] 45 VFs
[06:44:25] [PASSED] 46 VFs
[06:44:25] [PASSED] 47 VFs
[06:44:25] [PASSED] 48 VFs
[06:44:25] [PASSED] 49 VFs
[06:44:25] [PASSED] 50 VFs
[06:44:25] [PASSED] 51 VFs
[06:44:25] [PASSED] 52 VFs
[06:44:25] [PASSED] 53 VFs
[06:44:25] [PASSED] 54 VFs
[06:44:25] [PASSED] 55 VFs
[06:44:25] [PASSED] 56 VFs
[06:44:25] [PASSED] 57 VFs
[06:44:25] [PASSED] 58 VFs
[06:44:25] [PASSED] 59 VFs
[06:44:25] [PASSED] 60 VFs
[06:44:25] [PASSED] 61 VFs
[06:44:25] [PASSED] 62 VFs
[06:44:25] [PASSED] 63 VFs
[06:44:25] ==================== [PASSED] fair_vram ====================
[06:44:25] ================== [PASSED] pf_gt_config ===================
[06:44:25] ===================== lmtt (1 subtest) =====================
[06:44:25] ======================== test_ops =========================
[06:44:25] [PASSED] 2-level
[06:44:25] [PASSED] multi-level
[06:44:25] ==================== [PASSED] test_ops =====================
[06:44:25] ====================== [PASSED] lmtt =======================
[06:44:25] ================= pf_service (11 subtests) =================
[06:44:25] [PASSED] pf_negotiate_any
[06:44:25] [PASSED] pf_negotiate_base_match
[06:44:25] [PASSED] pf_negotiate_base_newer
[06:44:25] [PASSED] pf_negotiate_base_next
[06:44:25] [SKIPPED] pf_negotiate_base_older
[06:44:25] [PASSED] pf_negotiate_base_prev
[06:44:25] [PASSED] pf_negotiate_latest_match
[06:44:25] [PASSED] pf_negotiate_latest_newer
[06:44:25] [PASSED] pf_negotiate_latest_next
[06:44:25] [SKIPPED] pf_negotiate_latest_older
[06:44:25] [SKIPPED] pf_negotiate_latest_prev
[06:44:25] =================== [PASSED] pf_service ====================
[06:44:25] ================= xe_guc_g2g (2 subtests) ==================
[06:44:25] ============== xe_live_guc_g2g_kunit_default ==============
[06:44:25] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[06:44:25] ============== xe_live_guc_g2g_kunit_allmem ===============
[06:44:25] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[06:44:25] =================== [SKIPPED] xe_guc_g2g ===================
[06:44:25] =================== xe_mocs (2 subtests) ===================
[06:44:25] ================ xe_live_mocs_kernel_kunit ================
[06:44:25] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[06:44:25] ================ xe_live_mocs_reset_kunit =================
[06:44:25] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[06:44:25] ==================== [SKIPPED] xe_mocs =====================
[06:44:25] ================= xe_migrate (2 subtests) ==================
[06:44:25] ================= xe_migrate_sanity_kunit =================
[06:44:25] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[06:44:25] ================== xe_validate_ccs_kunit ==================
[06:44:25] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[06:44:25] =================== [SKIPPED] xe_migrate ===================
[06:44:25] ================== xe_dma_buf (1 subtest) ==================
[06:44:25] ==================== xe_dma_buf_kunit =====================
[06:44:25] ================ [SKIPPED] xe_dma_buf_kunit ================
[06:44:25] =================== [SKIPPED] xe_dma_buf ===================
[06:44:25] ================= xe_bo_shrink (1 subtest) =================
[06:44:25] =================== xe_bo_shrink_kunit ====================
[06:44:25] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[06:44:25] ================== [SKIPPED] xe_bo_shrink ==================
[06:44:25] ==================== xe_bo (2 subtests) ====================
[06:44:25] ================== xe_ccs_migrate_kunit ===================
[06:44:25] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[06:44:25] ==================== xe_bo_evict_kunit ====================
[06:44:25] =============== [SKIPPED] xe_bo_evict_kunit ================
[06:44:25] ===================== [SKIPPED] xe_bo ======================
[06:44:25] ==================== args (13 subtests) ====================
[06:44:25] [PASSED] count_args_test
[06:44:25] [PASSED] call_args_example
[06:44:25] [PASSED] call_args_test
[06:44:25] [PASSED] drop_first_arg_example
[06:44:25] [PASSED] drop_first_arg_test
[06:44:25] [PASSED] first_arg_example
[06:44:25] [PASSED] first_arg_test
[06:44:25] [PASSED] last_arg_example
[06:44:25] [PASSED] last_arg_test
[06:44:25] [PASSED] pick_arg_example
[06:44:25] [PASSED] if_args_example
[06:44:25] [PASSED] if_args_test
[06:44:25] [PASSED] sep_comma_example
[06:44:25] ====================== [PASSED] args =======================
[06:44:25] =================== xe_pci (3 subtests) ====================
[06:44:25] ==================== check_graphics_ip ====================
[06:44:25] [PASSED] 12.00 Xe_LP
[06:44:25] [PASSED] 12.10 Xe_LP+
[06:44:25] [PASSED] 12.55 Xe_HPG
[06:44:25] [PASSED] 12.60 Xe_HPC
[06:44:25] [PASSED] 12.70 Xe_LPG
[06:44:25] [PASSED] 12.71 Xe_LPG
[06:44:25] [PASSED] 12.74 Xe_LPG+
[06:44:25] [PASSED] 20.01 Xe2_HPG
[06:44:25] [PASSED] 20.02 Xe2_HPG
[06:44:25] [PASSED] 20.04 Xe2_LPG
[06:44:25] [PASSED] 30.00 Xe3_LPG
[06:44:25] [PASSED] 30.01 Xe3_LPG
[06:44:25] [PASSED] 30.03 Xe3_LPG
[06:44:25] [PASSED] 30.04 Xe3_LPG
[06:44:25] [PASSED] 30.05 Xe3_LPG
[06:44:25] [PASSED] 35.10 Xe3p_LPG
[06:44:25] [PASSED] 35.11 Xe3p_XPC
[06:44:25] ================ [PASSED] check_graphics_ip ================
[06:44:25] ===================== check_media_ip ======================
[06:44:25] [PASSED] 12.00 Xe_M
[06:44:25] [PASSED] 12.55 Xe_HPM
[06:44:25] [PASSED] 13.00 Xe_LPM+
[06:44:25] [PASSED] 13.01 Xe2_HPM
[06:44:25] [PASSED] 20.00 Xe2_LPM
[06:44:25] [PASSED] 30.00 Xe3_LPM
[06:44:25] [PASSED] 30.02 Xe3_LPM
[06:44:25] [PASSED] 35.00 Xe3p_LPM
[06:44:25] [PASSED] 35.03 Xe3p_HPM
[06:44:25] ================= [PASSED] check_media_ip ==================
[06:44:25] =================== check_platform_desc ===================
[06:44:25] [PASSED] 0x9A60 (TIGERLAKE)
[06:44:25] [PASSED] 0x9A68 (TIGERLAKE)
[06:44:25] [PASSED] 0x9A70 (TIGERLAKE)
[06:44:25] [PASSED] 0x9A40 (TIGERLAKE)
[06:44:25] [PASSED] 0x9A49 (TIGERLAKE)
[06:44:25] [PASSED] 0x9A59 (TIGERLAKE)
[06:44:25] [PASSED] 0x9A78 (TIGERLAKE)
[06:44:25] [PASSED] 0x9AC0 (TIGERLAKE)
[06:44:25] [PASSED] 0x9AC9 (TIGERLAKE)
[06:44:25] [PASSED] 0x9AD9 (TIGERLAKE)
[06:44:25] [PASSED] 0x9AF8 (TIGERLAKE)
[06:44:25] [PASSED] 0x4C80 (ROCKETLAKE)
[06:44:25] [PASSED] 0x4C8A (ROCKETLAKE)
[06:44:25] [PASSED] 0x4C8B (ROCKETLAKE)
[06:44:25] [PASSED] 0x4C8C (ROCKETLAKE)
[06:44:25] [PASSED] 0x4C90 (ROCKETLAKE)
[06:44:25] [PASSED] 0x4C9A (ROCKETLAKE)
[06:44:25] [PASSED] 0x4680 (ALDERLAKE_S)
[06:44:25] [PASSED] 0x4682 (ALDERLAKE_S)
[06:44:25] [PASSED] 0x4688 (ALDERLAKE_S)
[06:44:25] [PASSED] 0x468A (ALDERLAKE_S)
[06:44:25] [PASSED] 0x468B (ALDERLAKE_S)
[06:44:25] [PASSED] 0x4690 (ALDERLAKE_S)
[06:44:25] [PASSED] 0x4692 (ALDERLAKE_S)
[06:44:25] [PASSED] 0x4693 (ALDERLAKE_S)
[06:44:25] [PASSED] 0x46A0 (ALDERLAKE_P)
[06:44:25] [PASSED] 0x46A1 (ALDERLAKE_P)
[06:44:25] [PASSED] 0x46A2 (ALDERLAKE_P)
[06:44:25] [PASSED] 0x46A3 (ALDERLAKE_P)
[06:44:25] [PASSED] 0x46A6 (ALDERLAKE_P)
[06:44:25] [PASSED] 0x46A8 (ALDERLAKE_P)
[06:44:25] [PASSED] 0x46AA (ALDERLAKE_P)
[06:44:25] [PASSED] 0x462A (ALDERLAKE_P)
[06:44:25] [PASSED] 0x4626 (ALDERLAKE_P)
[06:44:25] [PASSED] 0x4628 (ALDERLAKE_P)
[06:44:25] [PASSED] 0x46B0 (ALDERLAKE_P)
[06:44:25] [PASSED] 0x46B1 (ALDERLAKE_P)
[06:44:25] [PASSED] 0x46B2 (ALDERLAKE_P)
[06:44:25] [PASSED] 0x46B3 (ALDERLAKE_P)
[06:44:25] [PASSED] 0x46C0 (ALDERLAKE_P)
[06:44:25] [PASSED] 0x46C1 (ALDERLAKE_P)
[06:44:25] [PASSED] 0x46C2 (ALDERLAKE_P)
[06:44:25] [PASSED] 0x46C3 (ALDERLAKE_P)
[06:44:25] [PASSED] 0x46D0 (ALDERLAKE_N)
[06:44:25] [PASSED] 0x46D1 (ALDERLAKE_N)
[06:44:25] [PASSED] 0x46D2 (ALDERLAKE_N)
[06:44:25] [PASSED] 0x46D3 (ALDERLAKE_N)
[06:44:25] [PASSED] 0x46D4 (ALDERLAKE_N)
[06:44:25] [PASSED] 0xA721 (ALDERLAKE_P)
[06:44:25] [PASSED] 0xA7A1 (ALDERLAKE_P)
[06:44:25] [PASSED] 0xA7A9 (ALDERLAKE_P)
[06:44:25] [PASSED] 0xA7AC (ALDERLAKE_P)
[06:44:25] [PASSED] 0xA7AD (ALDERLAKE_P)
[06:44:25] [PASSED] 0xA720 (ALDERLAKE_P)
[06:44:25] [PASSED] 0xA7A0 (ALDERLAKE_P)
[06:44:25] [PASSED] 0xA7A8 (ALDERLAKE_P)
[06:44:25] [PASSED] 0xA7AA (ALDERLAKE_P)
[06:44:25] [PASSED] 0xA7AB (ALDERLAKE_P)
[06:44:25] [PASSED] 0xA780 (ALDERLAKE_S)
[06:44:25] [PASSED] 0xA781 (ALDERLAKE_S)
[06:44:25] [PASSED] 0xA782 (ALDERLAKE_S)
[06:44:25] [PASSED] 0xA783 (ALDERLAKE_S)
[06:44:25] [PASSED] 0xA788 (ALDERLAKE_S)
[06:44:25] [PASSED] 0xA789 (ALDERLAKE_S)
[06:44:25] [PASSED] 0xA78A (ALDERLAKE_S)
[06:44:25] [PASSED] 0xA78B (ALDERLAKE_S)
[06:44:25] [PASSED] 0x4905 (DG1)
[06:44:25] [PASSED] 0x4906 (DG1)
[06:44:25] [PASSED] 0x4907 (DG1)
[06:44:25] [PASSED] 0x4908 (DG1)
[06:44:25] [PASSED] 0x4909 (DG1)
[06:44:25] [PASSED] 0x56C0 (DG2)
[06:44:25] [PASSED] 0x56C2 (DG2)
[06:44:25] [PASSED] 0x56C1 (DG2)
[06:44:25] [PASSED] 0x7D51 (METEORLAKE)
[06:44:25] [PASSED] 0x7DD1 (METEORLAKE)
[06:44:25] [PASSED] 0x7D41 (METEORLAKE)
[06:44:25] [PASSED] 0x7D67 (METEORLAKE)
[06:44:25] [PASSED] 0xB640 (METEORLAKE)
[06:44:25] [PASSED] 0x56A0 (DG2)
[06:44:25] [PASSED] 0x56A1 (DG2)
[06:44:25] [PASSED] 0x56A2 (DG2)
[06:44:25] [PASSED] 0x56BE (DG2)
[06:44:25] [PASSED] 0x56BF (DG2)
[06:44:25] [PASSED] 0x5690 (DG2)
[06:44:25] [PASSED] 0x5691 (DG2)
[06:44:25] [PASSED] 0x5692 (DG2)
[06:44:25] [PASSED] 0x56A5 (DG2)
[06:44:25] [PASSED] 0x56A6 (DG2)
[06:44:25] [PASSED] 0x56B0 (DG2)
[06:44:25] [PASSED] 0x56B1 (DG2)
[06:44:25] [PASSED] 0x56BA (DG2)
[06:44:25] [PASSED] 0x56BB (DG2)
[06:44:25] [PASSED] 0x56BC (DG2)
[06:44:25] [PASSED] 0x56BD (DG2)
[06:44:25] [PASSED] 0x5693 (DG2)
[06:44:25] [PASSED] 0x5694 (DG2)
[06:44:25] [PASSED] 0x5695 (DG2)
[06:44:25] [PASSED] 0x56A3 (DG2)
[06:44:25] [PASSED] 0x56A4 (DG2)
[06:44:25] [PASSED] 0x56B2 (DG2)
[06:44:25] [PASSED] 0x56B3 (DG2)
[06:44:25] [PASSED] 0x5696 (DG2)
[06:44:25] [PASSED] 0x5697 (DG2)
[06:44:25] [PASSED] 0xB69 (PVC)
[06:44:25] [PASSED] 0xB6E (PVC)
[06:44:25] [PASSED] 0xBD4 (PVC)
[06:44:25] [PASSED] 0xBD5 (PVC)
[06:44:25] [PASSED] 0xBD6 (PVC)
[06:44:25] [PASSED] 0xBD7 (PVC)
[06:44:25] [PASSED] 0xBD8 (PVC)
[06:44:25] [PASSED] 0xBD9 (PVC)
[06:44:25] [PASSED] 0xBDA (PVC)
[06:44:25] [PASSED] 0xBDB (PVC)
[06:44:25] [PASSED] 0xBE0 (PVC)
[06:44:25] [PASSED] 0xBE1 (PVC)
[06:44:25] [PASSED] 0xBE5 (PVC)
[06:44:25] [PASSED] 0x7D40 (METEORLAKE)
[06:44:25] [PASSED] 0x7D45 (METEORLAKE)
[06:44:25] [PASSED] 0x7D55 (METEORLAKE)
[06:44:25] [PASSED] 0x7D60 (METEORLAKE)
[06:44:25] [PASSED] 0x7DD5 (METEORLAKE)
[06:44:25] [PASSED] 0x6420 (LUNARLAKE)
[06:44:25] [PASSED] 0x64A0 (LUNARLAKE)
[06:44:25] [PASSED] 0x64B0 (LUNARLAKE)
[06:44:25] [PASSED] 0xE202 (BATTLEMAGE)
[06:44:25] [PASSED] 0xE209 (BATTLEMAGE)
[06:44:25] [PASSED] 0xE20B (BATTLEMAGE)
[06:44:25] [PASSED] 0xE20C (BATTLEMAGE)
[06:44:25] [PASSED] 0xE20D (BATTLEMAGE)
[06:44:25] [PASSED] 0xE210 (BATTLEMAGE)
[06:44:25] [PASSED] 0xE211 (BATTLEMAGE)
[06:44:25] [PASSED] 0xE212 (BATTLEMAGE)
[06:44:25] [PASSED] 0xE216 (BATTLEMAGE)
[06:44:25] [PASSED] 0xE220 (BATTLEMAGE)
[06:44:25] [PASSED] 0xE221 (BATTLEMAGE)
[06:44:25] [PASSED] 0xE222 (BATTLEMAGE)
[06:44:25] [PASSED] 0xE223 (BATTLEMAGE)
[06:44:25] [PASSED] 0xB080 (PANTHERLAKE)
[06:44:25] [PASSED] 0xB081 (PANTHERLAKE)
[06:44:25] [PASSED] 0xB082 (PANTHERLAKE)
[06:44:25] [PASSED] 0xB083 (PANTHERLAKE)
[06:44:25] [PASSED] 0xB084 (PANTHERLAKE)
[06:44:25] [PASSED] 0xB085 (PANTHERLAKE)
[06:44:25] [PASSED] 0xB086 (PANTHERLAKE)
[06:44:25] [PASSED] 0xB087 (PANTHERLAKE)
[06:44:25] [PASSED] 0xB08F (PANTHERLAKE)
[06:44:25] [PASSED] 0xB090 (PANTHERLAKE)
[06:44:25] [PASSED] 0xB0A0 (PANTHERLAKE)
[06:44:25] [PASSED] 0xB0B0 (PANTHERLAKE)
[06:44:25] [PASSED] 0xFD80 (PANTHERLAKE)
[06:44:25] [PASSED] 0xFD81 (PANTHERLAKE)
[06:44:25] [PASSED] 0xD740 (NOVALAKE_S)
[06:44:25] [PASSED] 0xD741 (NOVALAKE_S)
[06:44:25] [PASSED] 0xD742 (NOVALAKE_S)
[06:44:25] [PASSED] 0xD743 (NOVALAKE_S)
[06:44:25] [PASSED] 0xD744 (NOVALAKE_S)
[06:44:25] [PASSED] 0xD745 (NOVALAKE_S)
[06:44:25] [PASSED] 0x674C (CRESCENTISLAND)
[06:44:25] [PASSED] 0xD750 (NOVALAKE_P)
[06:44:25] [PASSED] 0xD751 (NOVALAKE_P)
[06:44:25] [PASSED] 0xD752 (NOVALAKE_P)
[06:44:25] [PASSED] 0xD753 (NOVALAKE_P)
[06:44:25] [PASSED] 0xD754 (NOVALAKE_P)
[06:44:25] [PASSED] 0xD755 (NOVALAKE_P)
[06:44:25] [PASSED] 0xD756 (NOVALAKE_P)
[06:44:25] [PASSED] 0xD757 (NOVALAKE_P)
[06:44:25] [PASSED] 0xD75F (NOVALAKE_P)
[06:44:25] =============== [PASSED] check_platform_desc ===============
[06:44:25] ===================== [PASSED] xe_pci ======================
[06:44:25] =================== xe_rtp (2 subtests) ====================
[06:44:25] =============== xe_rtp_process_to_sr_tests ================
[06:44:25] [PASSED] coalesce-same-reg
[06:44:25] [PASSED] no-match-no-add
[06:44:25] [PASSED] match-or
[06:44:25] [PASSED] match-or-xfail
[06:44:25] [PASSED] no-match-no-add-multiple-rules
[06:44:25] [PASSED] two-regs-two-entries
[06:44:25] [PASSED] clr-one-set-other
[06:44:25] [PASSED] set-field
[06:44:25] [PASSED] conflict-duplicate
[06:44:25] [PASSED] conflict-not-disjoint
[06:44:25] [PASSED] conflict-reg-type
[06:44:25] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[06:44:25] ================== xe_rtp_process_tests ===================
[06:44:25] [PASSED] active1
[06:44:25] [PASSED] active2
[06:44:25] [PASSED] active-inactive
[06:44:25] [PASSED] inactive-active
[06:44:25] [PASSED] inactive-1st_or_active-inactive
[06:44:25] [PASSED] inactive-2nd_or_active-inactive
[06:44:25] [PASSED] inactive-last_or_active-inactive
[06:44:25] [PASSED] inactive-no_or_active-inactive
[06:44:25] ============== [PASSED] xe_rtp_process_tests ===============
[06:44:25] ===================== [PASSED] xe_rtp ======================
[06:44:25] ==================== xe_wa (1 subtest) =====================
[06:44:25] ======================== xe_wa_gt =========================
[06:44:25] [PASSED] TIGERLAKE B0
[06:44:25] [PASSED] DG1 A0
[06:44:25] [PASSED] DG1 B0
[06:44:25] [PASSED] ALDERLAKE_S A0
[06:44:25] [PASSED] ALDERLAKE_S B0
[06:44:25] [PASSED] ALDERLAKE_S C0
[06:44:25] [PASSED] ALDERLAKE_S D0
[06:44:25] [PASSED] ALDERLAKE_P A0
[06:44:25] [PASSED] ALDERLAKE_P B0
[06:44:25] [PASSED] ALDERLAKE_P C0
[06:44:25] [PASSED] ALDERLAKE_S RPLS D0
[06:44:25] [PASSED] ALDERLAKE_P RPLU E0
[06:44:25] [PASSED] DG2 G10 C0
[06:44:25] [PASSED] DG2 G11 B1
[06:44:25] [PASSED] DG2 G12 A1
[06:44:25] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[06:44:25] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[06:44:25] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[06:44:25] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[06:44:25] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[06:44:25] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[06:44:25] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[06:44:25] ==================== [PASSED] xe_wa_gt =====================
[06:44:25] ====================== [PASSED] xe_wa ======================
[06:44:25] ============================================================
[06:44:25] Testing complete. Ran 597 tests: passed: 579, skipped: 18
[06:44:25] Elapsed time: 36.109s total, 4.191s configuring, 31.302s building, 0.604s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[06:44:25] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[06:44:27] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[06:44:51] Starting KUnit Kernel (1/1)...
[06:44:51] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[06:44:51] ============ drm_test_pick_cmdline (2 subtests) ============
[06:44:51] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[06:44:51] =============== drm_test_pick_cmdline_named ===============
[06:44:51] [PASSED] NTSC
[06:44:51] [PASSED] NTSC-J
[06:44:51] [PASSED] PAL
[06:44:51] [PASSED] PAL-M
[06:44:51] =========== [PASSED] drm_test_pick_cmdline_named ===========
[06:44:51] ============== [PASSED] drm_test_pick_cmdline ==============
[06:44:51] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[06:44:51] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[06:44:51] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[06:44:51] =========== drm_validate_clone_mode (2 subtests) ===========
[06:44:51] ============== drm_test_check_in_clone_mode ===============
[06:44:51] [PASSED] in_clone_mode
[06:44:51] [PASSED] not_in_clone_mode
[06:44:51] ========== [PASSED] drm_test_check_in_clone_mode ===========
[06:44:51] =============== drm_test_check_valid_clones ===============
[06:44:51] [PASSED] not_in_clone_mode
[06:44:51] [PASSED] valid_clone
[06:44:51] [PASSED] invalid_clone
[06:44:51] =========== [PASSED] drm_test_check_valid_clones ===========
[06:44:51] ============= [PASSED] drm_validate_clone_mode =============
[06:44:51] ============= drm_validate_modeset (1 subtest) =============
[06:44:51] [PASSED] drm_test_check_connector_changed_modeset
[06:44:51] ============== [PASSED] drm_validate_modeset ===============
[06:44:51] ====== drm_test_bridge_get_current_state (2 subtests) ======
[06:44:51] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[06:44:51] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[06:44:51] ======== [PASSED] drm_test_bridge_get_current_state ========
[06:44:51] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[06:44:51] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[06:44:51] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[06:44:51] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[06:44:51] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[06:44:51] ============== drm_bridge_alloc (2 subtests) ===============
[06:44:51] [PASSED] drm_test_drm_bridge_alloc_basic
[06:44:51] [PASSED] drm_test_drm_bridge_alloc_get_put
[06:44:51] ================ [PASSED] drm_bridge_alloc =================
[06:44:51] ============= drm_cmdline_parser (40 subtests) =============
[06:44:51] [PASSED] drm_test_cmdline_force_d_only
[06:44:51] [PASSED] drm_test_cmdline_force_D_only_dvi
[06:44:51] [PASSED] drm_test_cmdline_force_D_only_hdmi
[06:44:51] [PASSED] drm_test_cmdline_force_D_only_not_digital
[06:44:51] [PASSED] drm_test_cmdline_force_e_only
[06:44:51] [PASSED] drm_test_cmdline_res
[06:44:51] [PASSED] drm_test_cmdline_res_vesa
[06:44:51] [PASSED] drm_test_cmdline_res_vesa_rblank
[06:44:51] [PASSED] drm_test_cmdline_res_rblank
[06:44:51] [PASSED] drm_test_cmdline_res_bpp
[06:44:51] [PASSED] drm_test_cmdline_res_refresh
[06:44:51] [PASSED] drm_test_cmdline_res_bpp_refresh
[06:44:51] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[06:44:51] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[06:44:51] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[06:44:51] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[06:44:51] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[06:44:51] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[06:44:51] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[06:44:51] [PASSED] drm_test_cmdline_res_margins_force_on
[06:44:51] [PASSED] drm_test_cmdline_res_vesa_margins
[06:44:51] [PASSED] drm_test_cmdline_name
[06:44:51] [PASSED] drm_test_cmdline_name_bpp
[06:44:51] [PASSED] drm_test_cmdline_name_option
[06:44:51] [PASSED] drm_test_cmdline_name_bpp_option
[06:44:51] [PASSED] drm_test_cmdline_rotate_0
[06:44:51] [PASSED] drm_test_cmdline_rotate_90
[06:44:51] [PASSED] drm_test_cmdline_rotate_180
[06:44:51] [PASSED] drm_test_cmdline_rotate_270
[06:44:51] [PASSED] drm_test_cmdline_hmirror
[06:44:51] [PASSED] drm_test_cmdline_vmirror
[06:44:51] [PASSED] drm_test_cmdline_margin_options
[06:44:51] [PASSED] drm_test_cmdline_multiple_options
[06:44:51] [PASSED] drm_test_cmdline_bpp_extra_and_option
[06:44:51] [PASSED] drm_test_cmdline_extra_and_option
[06:44:51] [PASSED] drm_test_cmdline_freestanding_options
[06:44:51] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[06:44:51] [PASSED] drm_test_cmdline_panel_orientation
[06:44:51] ================ drm_test_cmdline_invalid =================
[06:44:51] [PASSED] margin_only
[06:44:51] [PASSED] interlace_only
[06:44:51] [PASSED] res_missing_x
[06:44:51] [PASSED] res_missing_y
[06:44:51] [PASSED] res_bad_y
[06:44:51] [PASSED] res_missing_y_bpp
[06:44:51] [PASSED] res_bad_bpp
[06:44:51] [PASSED] res_bad_refresh
[06:44:51] [PASSED] res_bpp_refresh_force_on_off
[06:44:51] [PASSED] res_invalid_mode
[06:44:51] [PASSED] res_bpp_wrong_place_mode
[06:44:51] [PASSED] name_bpp_refresh
[06:44:51] [PASSED] name_refresh
[06:44:51] [PASSED] name_refresh_wrong_mode
[06:44:51] [PASSED] name_refresh_invalid_mode
[06:44:51] [PASSED] rotate_multiple
[06:44:51] [PASSED] rotate_invalid_val
[06:44:51] [PASSED] rotate_truncated
[06:44:51] [PASSED] invalid_option
[06:44:51] [PASSED] invalid_tv_option
[06:44:51] [PASSED] truncated_tv_option
[06:44:51] ============ [PASSED] drm_test_cmdline_invalid =============
[06:44:51] =============== drm_test_cmdline_tv_options ===============
[06:44:51] [PASSED] NTSC
[06:44:51] [PASSED] NTSC_443
[06:44:51] [PASSED] NTSC_J
[06:44:51] [PASSED] PAL
[06:44:51] [PASSED] PAL_M
[06:44:51] [PASSED] PAL_N
[06:44:51] [PASSED] SECAM
[06:44:51] [PASSED] MONO_525
[06:44:51] [PASSED] MONO_625
[06:44:51] =========== [PASSED] drm_test_cmdline_tv_options ===========
[06:44:51] =============== [PASSED] drm_cmdline_parser ================
[06:44:51] ========== drmm_connector_hdmi_init (20 subtests) ==========
[06:44:51] [PASSED] drm_test_connector_hdmi_init_valid
[06:44:51] [PASSED] drm_test_connector_hdmi_init_bpc_8
[06:44:51] [PASSED] drm_test_connector_hdmi_init_bpc_10
[06:44:51] [PASSED] drm_test_connector_hdmi_init_bpc_12
[06:44:51] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[06:44:51] [PASSED] drm_test_connector_hdmi_init_bpc_null
[06:44:51] [PASSED] drm_test_connector_hdmi_init_formats_empty
[06:44:51] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[06:44:51] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[06:44:51] [PASSED] supported_formats=0x9 yuv420_allowed=1
[06:44:51] [PASSED] supported_formats=0x9 yuv420_allowed=0
[06:44:51] [PASSED] supported_formats=0x5 yuv420_allowed=1
[06:44:51] [PASSED] supported_formats=0x5 yuv420_allowed=0
[06:44:51] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[06:44:51] [PASSED] drm_test_connector_hdmi_init_null_ddc
[06:44:51] [PASSED] drm_test_connector_hdmi_init_null_product
[06:44:51] [PASSED] drm_test_connector_hdmi_init_null_vendor
[06:44:51] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[06:44:51] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[06:44:51] [PASSED] drm_test_connector_hdmi_init_product_valid
[06:44:51] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[06:44:51] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[06:44:51] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[06:44:51] ========= drm_test_connector_hdmi_init_type_valid =========
[06:44:51] [PASSED] HDMI-A
[06:44:51] [PASSED] HDMI-B
[06:44:51] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[06:44:51] ======== drm_test_connector_hdmi_init_type_invalid ========
[06:44:51] [PASSED] Unknown
[06:44:51] [PASSED] VGA
[06:44:51] [PASSED] DVI-I
[06:44:51] [PASSED] DVI-D
[06:44:51] [PASSED] DVI-A
[06:44:51] [PASSED] Composite
[06:44:51] [PASSED] SVIDEO
[06:44:51] [PASSED] LVDS
[06:44:51] [PASSED] Component
[06:44:51] [PASSED] DIN
[06:44:51] [PASSED] DP
[06:44:51] [PASSED] TV
[06:44:51] [PASSED] eDP
[06:44:51] [PASSED] Virtual
[06:44:51] [PASSED] DSI
[06:44:51] [PASSED] DPI
[06:44:51] [PASSED] Writeback
[06:44:51] [PASSED] SPI
[06:44:51] [PASSED] USB
[06:44:51] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[06:44:51] ============ [PASSED] drmm_connector_hdmi_init =============
[06:44:51] ============= drmm_connector_init (3 subtests) =============
[06:44:51] [PASSED] drm_test_drmm_connector_init
[06:44:51] [PASSED] drm_test_drmm_connector_init_null_ddc
[06:44:51] ========= drm_test_drmm_connector_init_type_valid =========
[06:44:51] [PASSED] Unknown
[06:44:51] [PASSED] VGA
[06:44:51] [PASSED] DVI-I
[06:44:51] [PASSED] DVI-D
[06:44:51] [PASSED] DVI-A
[06:44:51] [PASSED] Composite
[06:44:51] [PASSED] SVIDEO
[06:44:51] [PASSED] LVDS
[06:44:51] [PASSED] Component
[06:44:51] [PASSED] DIN
[06:44:51] [PASSED] DP
[06:44:51] [PASSED] HDMI-A
[06:44:51] [PASSED] HDMI-B
[06:44:51] [PASSED] TV
[06:44:51] [PASSED] eDP
[06:44:51] [PASSED] Virtual
[06:44:51] [PASSED] DSI
[06:44:51] [PASSED] DPI
[06:44:51] [PASSED] Writeback
[06:44:51] [PASSED] SPI
[06:44:51] [PASSED] USB
[06:44:51] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[06:44:51] =============== [PASSED] drmm_connector_init ===============
[06:44:51] ========= drm_connector_dynamic_init (6 subtests) ==========
[06:44:51] [PASSED] drm_test_drm_connector_dynamic_init
[06:44:51] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[06:44:51] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[06:44:51] [PASSED] drm_test_drm_connector_dynamic_init_properties
[06:44:51] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[06:44:51] [PASSED] Unknown
[06:44:51] [PASSED] VGA
[06:44:51] [PASSED] DVI-I
[06:44:51] [PASSED] DVI-D
[06:44:51] [PASSED] DVI-A
[06:44:51] [PASSED] Composite
[06:44:51] [PASSED] SVIDEO
[06:44:51] [PASSED] LVDS
[06:44:51] [PASSED] Component
[06:44:51] [PASSED] DIN
[06:44:51] [PASSED] DP
[06:44:51] [PASSED] HDMI-A
[06:44:51] [PASSED] HDMI-B
[06:44:51] [PASSED] TV
[06:44:51] [PASSED] eDP
[06:44:51] [PASSED] Virtual
[06:44:51] [PASSED] DSI
[06:44:51] [PASSED] DPI
[06:44:51] [PASSED] Writeback
[06:44:51] [PASSED] SPI
[06:44:51] [PASSED] USB
[06:44:51] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[06:44:51] ======== drm_test_drm_connector_dynamic_init_name =========
[06:44:51] [PASSED] Unknown
[06:44:51] [PASSED] VGA
[06:44:51] [PASSED] DVI-I
[06:44:51] [PASSED] DVI-D
[06:44:51] [PASSED] DVI-A
[06:44:51] [PASSED] Composite
[06:44:51] [PASSED] SVIDEO
[06:44:51] [PASSED] LVDS
[06:44:51] [PASSED] Component
[06:44:51] [PASSED] DIN
[06:44:51] [PASSED] DP
[06:44:51] [PASSED] HDMI-A
[06:44:51] [PASSED] HDMI-B
[06:44:51] [PASSED] TV
[06:44:51] [PASSED] eDP
[06:44:51] [PASSED] Virtual
[06:44:51] [PASSED] DSI
[06:44:51] [PASSED] DPI
[06:44:51] [PASSED] Writeback
[06:44:51] [PASSED] SPI
[06:44:51] [PASSED] USB
[06:44:51] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[06:44:51] =========== [PASSED] drm_connector_dynamic_init ============
[06:44:51] ==== drm_connector_dynamic_register_early (4 subtests) =====
[06:44:51] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[06:44:51] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[06:44:51] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[06:44:51] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[06:44:51] ====== [PASSED] drm_connector_dynamic_register_early =======
[06:44:51] ======= drm_connector_dynamic_register (7 subtests) ========
[06:44:51] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[06:44:51] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[06:44:51] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[06:44:51] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[06:44:51] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[06:44:51] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[06:44:51] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[06:44:51] ========= [PASSED] drm_connector_dynamic_register ==========
[06:44:51] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[06:44:51] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[06:44:51] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[06:44:51] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[06:44:51] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[06:44:51] ========== drm_test_get_tv_mode_from_name_valid ===========
[06:44:51] [PASSED] NTSC
[06:44:51] [PASSED] NTSC-443
[06:44:51] [PASSED] NTSC-J
[06:44:51] [PASSED] PAL
[06:44:51] [PASSED] PAL-M
[06:44:51] [PASSED] PAL-N
[06:44:51] [PASSED] SECAM
[06:44:51] [PASSED] Mono
[06:44:51] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[06:44:51] [PASSED] drm_test_get_tv_mode_from_name_truncated
[06:44:51] ============ [PASSED] drm_get_tv_mode_from_name ============
[06:44:51] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[06:44:51] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[06:44:51] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[06:44:51] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[06:44:51] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[06:44:51] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[06:44:51] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[06:44:51] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[06:44:51] [PASSED] VIC 96
[06:44:51] [PASSED] VIC 97
[06:44:51] [PASSED] VIC 101
[06:44:51] [PASSED] VIC 102
[06:44:51] [PASSED] VIC 106
[06:44:51] [PASSED] VIC 107
[06:44:51] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[06:44:51] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[06:44:51] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[06:44:51] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[06:44:51] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[06:44:51] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[06:44:51] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[06:44:51] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[06:44:51] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[06:44:51] [PASSED] Automatic
[06:44:51] [PASSED] Full
[06:44:51] [PASSED] Limited 16:235
[06:44:51] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[06:44:51] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[06:44:51] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[06:44:51] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[06:44:51] === drm_test_drm_hdmi_connector_get_output_format_name ====
[06:44:51] [PASSED] RGB
[06:44:51] [PASSED] YUV 4:2:0
[06:44:51] [PASSED] YUV 4:2:2
[06:44:51] [PASSED] YUV 4:4:4
[06:44:51] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[06:44:51] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[06:44:51] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[06:44:51] ============= drm_damage_helper (21 subtests) ==============
[06:44:51] [PASSED] drm_test_damage_iter_no_damage
[06:44:51] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[06:44:51] [PASSED] drm_test_damage_iter_no_damage_src_moved
[06:44:51] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[06:44:51] [PASSED] drm_test_damage_iter_no_damage_not_visible
[06:44:51] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[06:44:51] [PASSED] drm_test_damage_iter_no_damage_no_fb
[06:44:51] [PASSED] drm_test_damage_iter_simple_damage
[06:44:51] [PASSED] drm_test_damage_iter_single_damage
[06:44:51] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[06:44:51] [PASSED] drm_test_damage_iter_single_damage_outside_src
[06:44:51] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[06:44:51] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[06:44:51] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[06:44:51] [PASSED] drm_test_damage_iter_single_damage_src_moved
[06:44:51] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[06:44:51] [PASSED] drm_test_damage_iter_damage
[06:44:51] [PASSED] drm_test_damage_iter_damage_one_intersect
[06:44:51] [PASSED] drm_test_damage_iter_damage_one_outside
[06:44:51] [PASSED] drm_test_damage_iter_damage_src_moved
[06:44:51] [PASSED] drm_test_damage_iter_damage_not_visible
[06:44:51] ================ [PASSED] drm_damage_helper ================
[06:44:51] ============== drm_dp_mst_helper (3 subtests) ==============
[06:44:51] ============== drm_test_dp_mst_calc_pbn_mode ==============
[06:44:51] [PASSED] Clock 154000 BPP 30 DSC disabled
[06:44:51] [PASSED] Clock 234000 BPP 30 DSC disabled
[06:44:51] [PASSED] Clock 297000 BPP 24 DSC disabled
[06:44:51] [PASSED] Clock 332880 BPP 24 DSC enabled
[06:44:51] [PASSED] Clock 324540 BPP 24 DSC enabled
[06:44:51] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[06:44:51] ============== drm_test_dp_mst_calc_pbn_div ===============
[06:44:51] [PASSED] Link rate 2000000 lane count 4
[06:44:51] [PASSED] Link rate 2000000 lane count 2
[06:44:51] [PASSED] Link rate 2000000 lane count 1
[06:44:51] [PASSED] Link rate 1350000 lane count 4
[06:44:51] [PASSED] Link rate 1350000 lane count 2
[06:44:51] [PASSED] Link rate 1350000 lane count 1
[06:44:51] [PASSED] Link rate 1000000 lane count 4
[06:44:51] [PASSED] Link rate 1000000 lane count 2
[06:44:51] [PASSED] Link rate 1000000 lane count 1
[06:44:51] [PASSED] Link rate 810000 lane count 4
[06:44:51] [PASSED] Link rate 810000 lane count 2
[06:44:51] [PASSED] Link rate 810000 lane count 1
[06:44:51] [PASSED] Link rate 540000 lane count 4
[06:44:51] [PASSED] Link rate 540000 lane count 2
[06:44:51] [PASSED] Link rate 540000 lane count 1
[06:44:51] [PASSED] Link rate 270000 lane count 4
[06:44:51] [PASSED] Link rate 270000 lane count 2
[06:44:51] [PASSED] Link rate 270000 lane count 1
[06:44:51] [PASSED] Link rate 162000 lane count 4
[06:44:51] [PASSED] Link rate 162000 lane count 2
[06:44:51] [PASSED] Link rate 162000 lane count 1
[06:44:51] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[06:44:51] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[06:44:51] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[06:44:51] [PASSED] DP_POWER_UP_PHY with port number
[06:44:51] [PASSED] DP_POWER_DOWN_PHY with port number
[06:44:51] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[06:44:51] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[06:44:51] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[06:44:51] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[06:44:51] [PASSED] DP_QUERY_PAYLOAD with port number
[06:44:51] [PASSED] DP_QUERY_PAYLOAD with VCPI
[06:44:51] [PASSED] DP_REMOTE_DPCD_READ with port number
[06:44:51] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[06:44:51] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[06:44:51] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[06:44:51] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[06:44:51] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[06:44:51] [PASSED] DP_REMOTE_I2C_READ with port number
[06:44:51] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[06:44:51] [PASSED] DP_REMOTE_I2C_READ with transactions array
[06:44:51] [PASSED] DP_REMOTE_I2C_WRITE with port number
[06:44:51] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[06:44:51] [PASSED] DP_REMOTE_I2C_WRITE with data array
[06:44:51] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[06:44:51] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[06:44:51] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[06:44:51] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[06:44:51] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[06:44:51] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[06:44:51] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[06:44:51] ================ [PASSED] drm_dp_mst_helper ================
[06:44:51] ================== drm_exec (7 subtests) ===================
[06:44:51] [PASSED] sanitycheck
[06:44:51] [PASSED] test_lock
[06:44:51] [PASSED] test_lock_unlock
[06:44:51] [PASSED] test_duplicates
[06:44:51] [PASSED] test_prepare
[06:44:51] [PASSED] test_prepare_array
[06:44:51] [PASSED] test_multiple_loops
[06:44:51] ==================== [PASSED] drm_exec =====================
[06:44:51] =========== drm_format_helper_test (17 subtests) ===========
[06:44:51] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[06:44:51] [PASSED] single_pixel_source_buffer
[06:44:51] [PASSED] single_pixel_clip_rectangle
[06:44:51] [PASSED] well_known_colors
[06:44:51] [PASSED] destination_pitch
[06:44:51] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[06:44:51] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[06:44:51] [PASSED] single_pixel_source_buffer
[06:44:51] [PASSED] single_pixel_clip_rectangle
[06:44:51] [PASSED] well_known_colors
[06:44:51] [PASSED] destination_pitch
[06:44:51] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[06:44:51] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[06:44:51] [PASSED] single_pixel_source_buffer
[06:44:51] [PASSED] single_pixel_clip_rectangle
[06:44:51] [PASSED] well_known_colors
[06:44:51] [PASSED] destination_pitch
[06:44:51] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[06:44:51] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[06:44:51] [PASSED] single_pixel_source_buffer
[06:44:51] [PASSED] single_pixel_clip_rectangle
[06:44:51] [PASSED] well_known_colors
[06:44:51] [PASSED] destination_pitch
[06:44:51] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[06:44:51] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[06:44:51] [PASSED] single_pixel_source_buffer
[06:44:51] [PASSED] single_pixel_clip_rectangle
[06:44:51] [PASSED] well_known_colors
[06:44:51] [PASSED] destination_pitch
[06:44:51] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[06:44:51] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[06:44:51] [PASSED] single_pixel_source_buffer
[06:44:51] [PASSED] single_pixel_clip_rectangle
[06:44:51] [PASSED] well_known_colors
[06:44:51] [PASSED] destination_pitch
[06:44:51] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[06:44:51] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[06:44:51] [PASSED] single_pixel_source_buffer
[06:44:51] [PASSED] single_pixel_clip_rectangle
[06:44:51] [PASSED] well_known_colors
[06:44:51] [PASSED] destination_pitch
[06:44:51] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[06:44:51] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[06:44:51] [PASSED] single_pixel_source_buffer
[06:44:51] [PASSED] single_pixel_clip_rectangle
[06:44:51] [PASSED] well_known_colors
[06:44:51] [PASSED] destination_pitch
[06:44:51] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[06:44:51] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[06:44:51] [PASSED] single_pixel_source_buffer
[06:44:51] [PASSED] single_pixel_clip_rectangle
[06:44:51] [PASSED] well_known_colors
[06:44:51] [PASSED] destination_pitch
[06:44:51] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[06:44:51] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[06:44:51] [PASSED] single_pixel_source_buffer
[06:44:51] [PASSED] single_pixel_clip_rectangle
[06:44:51] [PASSED] well_known_colors
[06:44:51] [PASSED] destination_pitch
[06:44:51] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[06:44:51] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[06:44:51] [PASSED] single_pixel_source_buffer
[06:44:51] [PASSED] single_pixel_clip_rectangle
[06:44:51] [PASSED] well_known_colors
[06:44:51] [PASSED] destination_pitch
[06:44:51] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[06:44:51] ============== drm_test_fb_xrgb8888_to_mono ===============
[06:44:51] [PASSED] single_pixel_source_buffer
[06:44:51] [PASSED] single_pixel_clip_rectangle
[06:44:51] [PASSED] well_known_colors
[06:44:51] [PASSED] destination_pitch
[06:44:51] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[06:44:51] ==================== drm_test_fb_swab =====================
[06:44:51] [PASSED] single_pixel_source_buffer
[06:44:51] [PASSED] single_pixel_clip_rectangle
[06:44:51] [PASSED] well_known_colors
[06:44:51] [PASSED] destination_pitch
[06:44:51] ================ [PASSED] drm_test_fb_swab =================
[06:44:51] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[06:44:51] [PASSED] single_pixel_source_buffer
[06:44:51] [PASSED] single_pixel_clip_rectangle
[06:44:51] [PASSED] well_known_colors
[06:44:51] [PASSED] destination_pitch
[06:44:51] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[06:44:51] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[06:44:51] [PASSED] single_pixel_source_buffer
[06:44:51] [PASSED] single_pixel_clip_rectangle
[06:44:51] [PASSED] well_known_colors
[06:44:51] [PASSED] destination_pitch
[06:44:51] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[06:44:51] ================= drm_test_fb_clip_offset =================
[06:44:51] [PASSED] pass through
[06:44:51] [PASSED] horizontal offset
[06:44:51] [PASSED] vertical offset
[06:44:51] [PASSED] horizontal and vertical offset
[06:44:51] [PASSED] horizontal offset (custom pitch)
[06:44:51] [PASSED] vertical offset (custom pitch)
[06:44:51] [PASSED] horizontal and vertical offset (custom pitch)
[06:44:51] ============= [PASSED] drm_test_fb_clip_offset =============
[06:44:51] =================== drm_test_fb_memcpy ====================
[06:44:51] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[06:44:51] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[06:44:51] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[06:44:51] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[06:44:51] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[06:44:51] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[06:44:51] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[06:44:51] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[06:44:51] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[06:44:51] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[06:44:51] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[06:44:51] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[06:44:51] =============== [PASSED] drm_test_fb_memcpy ================
[06:44:51] ============= [PASSED] drm_format_helper_test ==============
[06:44:51] ================= drm_format (18 subtests) =================
[06:44:51] [PASSED] drm_test_format_block_width_invalid
[06:44:51] [PASSED] drm_test_format_block_width_one_plane
[06:44:51] [PASSED] drm_test_format_block_width_two_plane
[06:44:51] [PASSED] drm_test_format_block_width_three_plane
[06:44:51] [PASSED] drm_test_format_block_width_tiled
[06:44:51] [PASSED] drm_test_format_block_height_invalid
[06:44:51] [PASSED] drm_test_format_block_height_one_plane
[06:44:51] [PASSED] drm_test_format_block_height_two_plane
[06:44:51] [PASSED] drm_test_format_block_height_three_plane
[06:44:51] [PASSED] drm_test_format_block_height_tiled
[06:44:51] [PASSED] drm_test_format_min_pitch_invalid
[06:44:51] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[06:44:51] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[06:44:51] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[06:44:51] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[06:44:51] [PASSED] drm_test_format_min_pitch_two_plane
[06:44:51] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[06:44:51] [PASSED] drm_test_format_min_pitch_tiled
[06:44:51] =================== [PASSED] drm_format ====================
[06:44:51] ============== drm_framebuffer (10 subtests) ===============
[06:44:51] ========== drm_test_framebuffer_check_src_coords ==========
[06:44:51] [PASSED] Success: source fits into fb
[06:44:51] [PASSED] Fail: overflowing fb with x-axis coordinate
[06:44:51] [PASSED] Fail: overflowing fb with y-axis coordinate
[06:44:51] [PASSED] Fail: overflowing fb with source width
[06:44:51] [PASSED] Fail: overflowing fb with source height
[06:44:51] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[06:44:51] [PASSED] drm_test_framebuffer_cleanup
[06:44:51] =============== drm_test_framebuffer_create ===============
[06:44:51] [PASSED] ABGR8888 normal sizes
[06:44:51] [PASSED] ABGR8888 max sizes
[06:44:51] [PASSED] ABGR8888 pitch greater than min required
[06:44:51] [PASSED] ABGR8888 pitch less than min required
[06:44:51] [PASSED] ABGR8888 Invalid width
[06:44:51] [PASSED] ABGR8888 Invalid buffer handle
[06:44:51] [PASSED] No pixel format
[06:44:51] [PASSED] ABGR8888 Width 0
[06:44:51] [PASSED] ABGR8888 Height 0
[06:44:51] [PASSED] ABGR8888 Out of bound height * pitch combination
[06:44:51] [PASSED] ABGR8888 Large buffer offset
[06:44:51] [PASSED] ABGR8888 Buffer offset for inexistent plane
[06:44:51] [PASSED] ABGR8888 Invalid flag
[06:44:51] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[06:44:51] [PASSED] ABGR8888 Valid buffer modifier
[06:44:51] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[06:44:51] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[06:44:51] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[06:44:51] [PASSED] NV12 Normal sizes
[06:44:51] [PASSED] NV12 Max sizes
[06:44:51] [PASSED] NV12 Invalid pitch
[06:44:51] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[06:44:51] [PASSED] NV12 different modifier per-plane
[06:44:51] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[06:44:51] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[06:44:51] [PASSED] NV12 Modifier for inexistent plane
[06:44:51] [PASSED] NV12 Handle for inexistent plane
[06:44:51] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[06:44:51] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[06:44:51] [PASSED] YVU420 Normal sizes
[06:44:51] [PASSED] YVU420 Max sizes
[06:44:51] [PASSED] YVU420 Invalid pitch
[06:44:51] [PASSED] YVU420 Different pitches
[06:44:51] [PASSED] YVU420 Different buffer offsets/pitches
[06:44:51] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[06:44:51] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[06:44:51] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[06:44:51] [PASSED] YVU420 Valid modifier
[06:44:51] [PASSED] YVU420 Different modifiers per plane
[06:44:51] [PASSED] YVU420 Modifier for inexistent plane
[06:44:51] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[06:44:51] [PASSED] X0L2 Normal sizes
[06:44:51] [PASSED] X0L2 Max sizes
[06:44:51] [PASSED] X0L2 Invalid pitch
[06:44:51] [PASSED] X0L2 Pitch greater than minimum required
[06:44:51] [PASSED] X0L2 Handle for inexistent plane
[06:44:51] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[06:44:51] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[06:44:51] [PASSED] X0L2 Valid modifier
[06:44:51] [PASSED] X0L2 Modifier for inexistent plane
[06:44:51] =========== [PASSED] drm_test_framebuffer_create ===========
[06:44:51] [PASSED] drm_test_framebuffer_free
[06:44:51] [PASSED] drm_test_framebuffer_init
[06:44:51] [PASSED] drm_test_framebuffer_init_bad_format
[06:44:51] [PASSED] drm_test_framebuffer_init_dev_mismatch
[06:44:51] [PASSED] drm_test_framebuffer_lookup
[06:44:51] [PASSED] drm_test_framebuffer_lookup_inexistent
[06:44:51] [PASSED] drm_test_framebuffer_modifiers_not_supported
[06:44:51] ================= [PASSED] drm_framebuffer =================
[06:44:51] ================ drm_gem_shmem (8 subtests) ================
[06:44:51] [PASSED] drm_gem_shmem_test_obj_create
[06:44:51] [PASSED] drm_gem_shmem_test_obj_create_private
[06:44:51] [PASSED] drm_gem_shmem_test_pin_pages
[06:44:51] [PASSED] drm_gem_shmem_test_vmap
[06:44:51] [PASSED] drm_gem_shmem_test_get_sg_table
[06:44:51] [PASSED] drm_gem_shmem_test_get_pages_sgt
[06:44:51] [PASSED] drm_gem_shmem_test_madvise
[06:44:51] [PASSED] drm_gem_shmem_test_purge
[06:44:51] ================== [PASSED] drm_gem_shmem ==================
[06:44:51] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[06:44:51] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[06:44:51] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[06:44:51] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[06:44:51] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[06:44:51] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[06:44:51] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[06:44:51] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[06:44:51] [PASSED] Automatic
[06:44:51] [PASSED] Full
[06:44:51] [PASSED] Limited 16:235
[06:44:51] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[06:44:51] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[06:44:51] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[06:44:51] [PASSED] drm_test_check_disable_connector
[06:44:51] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[06:44:51] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[06:44:51] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[06:44:51] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[06:44:51] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[06:44:51] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[06:44:51] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[06:44:51] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[06:44:51] [PASSED] drm_test_check_output_bpc_dvi
[06:44:51] [PASSED] drm_test_check_output_bpc_format_vic_1
[06:44:51] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[06:44:51] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[06:44:51] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[06:44:51] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[06:44:51] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[06:44:51] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[06:44:51] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[06:44:51] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[06:44:51] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[06:44:51] [PASSED] drm_test_check_broadcast_rgb_value
[06:44:51] [PASSED] drm_test_check_bpc_8_value
[06:44:51] [PASSED] drm_test_check_bpc_10_value
[06:44:51] [PASSED] drm_test_check_bpc_12_value
[06:44:51] [PASSED] drm_test_check_format_value
[06:44:51] [PASSED] drm_test_check_tmds_char_value
[06:44:51] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[06:44:51] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[06:44:51] [PASSED] drm_test_check_mode_valid
[06:44:51] [PASSED] drm_test_check_mode_valid_reject
[06:44:51] [PASSED] drm_test_check_mode_valid_reject_rate
[06:44:51] [PASSED] drm_test_check_mode_valid_reject_max_clock
[06:44:51] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[06:44:51] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[06:44:51] [PASSED] drm_test_check_infoframes
[06:44:51] [PASSED] drm_test_check_reject_avi_infoframe
[06:44:51] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[06:44:51] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[06:44:51] [PASSED] drm_test_check_reject_audio_infoframe
[06:44:51] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[06:44:51] ================= drm_managed (2 subtests) =================
[06:44:51] [PASSED] drm_test_managed_release_action
[06:44:51] [PASSED] drm_test_managed_run_action
[06:44:51] =================== [PASSED] drm_managed ===================
[06:44:51] =================== drm_mm (6 subtests) ====================
[06:44:51] [PASSED] drm_test_mm_init
[06:44:51] [PASSED] drm_test_mm_debug
[06:44:51] [PASSED] drm_test_mm_align32
[06:44:51] [PASSED] drm_test_mm_align64
[06:44:51] [PASSED] drm_test_mm_lowest
[06:44:51] [PASSED] drm_test_mm_highest
[06:44:51] ===================== [PASSED] drm_mm ======================
[06:44:51] ============= drm_modes_analog_tv (5 subtests) =============
[06:44:51] [PASSED] drm_test_modes_analog_tv_mono_576i
[06:44:51] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[06:44:51] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[06:44:51] [PASSED] drm_test_modes_analog_tv_pal_576i
[06:44:51] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[06:44:51] =============== [PASSED] drm_modes_analog_tv ===============
[06:44:51] ============== drm_plane_helper (2 subtests) ===============
[06:44:51] =============== drm_test_check_plane_state ================
[06:44:51] [PASSED] clipping_simple
[06:44:51] [PASSED] clipping_rotate_reflect
[06:44:51] [PASSED] positioning_simple
[06:44:51] [PASSED] upscaling
[06:44:51] [PASSED] downscaling
[06:44:51] [PASSED] rounding1
[06:44:51] [PASSED] rounding2
[06:44:51] [PASSED] rounding3
[06:44:51] [PASSED] rounding4
[06:44:51] =========== [PASSED] drm_test_check_plane_state ============
[06:44:51] =========== drm_test_check_invalid_plane_state ============
[06:44:51] [PASSED] positioning_invalid
[06:44:51] [PASSED] upscaling_invalid
[06:44:51] [PASSED] downscaling_invalid
[06:44:51] ======= [PASSED] drm_test_check_invalid_plane_state ========
[06:44:51] ================ [PASSED] drm_plane_helper =================
[06:44:51] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[06:44:51] ====== drm_test_connector_helper_tv_get_modes_check =======
[06:44:51] [PASSED] None
[06:44:51] [PASSED] PAL
[06:44:51] [PASSED] NTSC
[06:44:51] [PASSED] Both, NTSC Default
[06:44:51] [PASSED] Both, PAL Default
[06:44:51] [PASSED] Both, NTSC Default, with PAL on command-line
[06:44:51] [PASSED] Both, PAL Default, with NTSC on command-line
[06:44:51] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[06:44:51] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[06:44:51] ================== drm_rect (9 subtests) ===================
[06:44:51] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[06:44:51] [PASSED] drm_test_rect_clip_scaled_not_clipped
[06:44:51] [PASSED] drm_test_rect_clip_scaled_clipped
[06:44:51] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[06:44:51] ================= drm_test_rect_intersect =================
[06:44:51] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[06:44:51] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[06:44:51] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[06:44:51] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[06:44:51] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[06:44:51] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[06:44:51] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[06:44:51] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[06:44:51] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[06:44:51] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[06:44:51] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[06:44:51] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[06:44:51] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[06:44:51] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[06:44:51] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[06:44:51] ============= [PASSED] drm_test_rect_intersect =============
[06:44:51] ================ drm_test_rect_calc_hscale ================
[06:44:51] [PASSED] normal use
[06:44:51] [PASSED] out of max range
[06:44:51] [PASSED] out of min range
[06:44:51] [PASSED] zero dst
[06:44:51] [PASSED] negative src
[06:44:51] [PASSED] negative dst
[06:44:51] ============ [PASSED] drm_test_rect_calc_hscale ============
[06:44:51] ================ drm_test_rect_calc_vscale ================
[06:44:51] [PASSED] normal use
[06:44:51] [PASSED] out of max range
[06:44:51] [PASSED] out of min range
[06:44:51] [PASSED] zero dst
[06:44:51] [PASSED] negative src
[06:44:51] [PASSED] negative dst
[06:44:51] ============ [PASSED] drm_test_rect_calc_vscale ============
[06:44:51] ================== drm_test_rect_rotate ===================
[06:44:51] [PASSED] reflect-x
[06:44:51] [PASSED] reflect-y
[06:44:51] [PASSED] rotate-0
[06:44:51] [PASSED] rotate-90
[06:44:51] [PASSED] rotate-180
[06:44:51] [PASSED] rotate-270
[06:44:51] ============== [PASSED] drm_test_rect_rotate ===============
[06:44:51] ================ drm_test_rect_rotate_inv =================
[06:44:51] [PASSED] reflect-x
[06:44:51] [PASSED] reflect-y
[06:44:51] [PASSED] rotate-0
[06:44:51] [PASSED] rotate-90
[06:44:51] [PASSED] rotate-180
[06:44:51] [PASSED] rotate-270
[06:44:51] ============ [PASSED] drm_test_rect_rotate_inv =============
[06:44:51] ==================== [PASSED] drm_rect =====================
[06:44:51] ============ drm_sysfb_modeset_test (1 subtest) ============
[06:44:51] ============ drm_test_sysfb_build_fourcc_list =============
[06:44:51] [PASSED] no native formats
[06:44:51] [PASSED] XRGB8888 as native format
[06:44:51] [PASSED] remove duplicates
[06:44:51] [PASSED] convert alpha formats
[06:44:51] [PASSED] random formats
[06:44:51] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[06:44:51] ============= [PASSED] drm_sysfb_modeset_test ==============
[06:44:51] ================== drm_fixp (2 subtests) ===================
[06:44:51] [PASSED] drm_test_int2fixp
[06:44:51] [PASSED] drm_test_sm2fixp
[06:44:51] ==================== [PASSED] drm_fixp =====================
[06:44:51] ============================================================
[06:44:51] Testing complete. Ran 621 tests: passed: 621
[06:44:52] Elapsed time: 26.065s total, 1.740s configuring, 24.160s building, 0.115s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[06:44:52] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[06:44:53] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[06:45:03] Starting KUnit Kernel (1/1)...
[06:45:03] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[06:45:03] ================= ttm_device (5 subtests) ==================
[06:45:03] [PASSED] ttm_device_init_basic
[06:45:03] [PASSED] ttm_device_init_multiple
[06:45:03] [PASSED] ttm_device_fini_basic
[06:45:03] [PASSED] ttm_device_init_no_vma_man
[06:45:03] ================== ttm_device_init_pools ==================
[06:45:03] [PASSED] No DMA allocations, no DMA32 required
[06:45:03] [PASSED] DMA allocations, DMA32 required
[06:45:03] [PASSED] No DMA allocations, DMA32 required
[06:45:03] [PASSED] DMA allocations, no DMA32 required
[06:45:03] ============== [PASSED] ttm_device_init_pools ==============
[06:45:03] =================== [PASSED] ttm_device ====================
[06:45:03] ================== ttm_pool (8 subtests) ===================
[06:45:03] ================== ttm_pool_alloc_basic ===================
[06:45:03] [PASSED] One page
[06:45:03] [PASSED] More than one page
[06:45:03] [PASSED] Above the allocation limit
[06:45:03] [PASSED] One page, with coherent DMA mappings enabled
[06:45:03] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[06:45:03] ============== [PASSED] ttm_pool_alloc_basic ===============
[06:45:03] ============== ttm_pool_alloc_basic_dma_addr ==============
[06:45:03] [PASSED] One page
[06:45:03] [PASSED] More than one page
[06:45:03] [PASSED] Above the allocation limit
[06:45:03] [PASSED] One page, with coherent DMA mappings enabled
[06:45:03] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[06:45:03] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[06:45:03] [PASSED] ttm_pool_alloc_order_caching_match
[06:45:03] [PASSED] ttm_pool_alloc_caching_mismatch
[06:45:03] [PASSED] ttm_pool_alloc_order_mismatch
[06:45:03] [PASSED] ttm_pool_free_dma_alloc
[06:45:03] [PASSED] ttm_pool_free_no_dma_alloc
[06:45:03] [PASSED] ttm_pool_fini_basic
[06:45:03] ==================== [PASSED] ttm_pool =====================
[06:45:03] ================ ttm_resource (8 subtests) =================
[06:45:03] ================= ttm_resource_init_basic =================
[06:45:03] [PASSED] Init resource in TTM_PL_SYSTEM
[06:45:03] [PASSED] Init resource in TTM_PL_VRAM
[06:45:03] [PASSED] Init resource in a private placement
[06:45:03] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[06:45:03] ============= [PASSED] ttm_resource_init_basic =============
[06:45:03] [PASSED] ttm_resource_init_pinned
[06:45:03] [PASSED] ttm_resource_fini_basic
[06:45:03] [PASSED] ttm_resource_manager_init_basic
[06:45:03] [PASSED] ttm_resource_manager_usage_basic
[06:45:03] [PASSED] ttm_resource_manager_set_used_basic
[06:45:03] [PASSED] ttm_sys_man_alloc_basic
[06:45:03] [PASSED] ttm_sys_man_free_basic
[06:45:03] ================== [PASSED] ttm_resource ===================
[06:45:03] =================== ttm_tt (15 subtests) ===================
[06:45:03] ==================== ttm_tt_init_basic ====================
[06:45:03] [PASSED] Page-aligned size
[06:45:03] [PASSED] Extra pages requested
[06:45:03] ================ [PASSED] ttm_tt_init_basic ================
[06:45:03] [PASSED] ttm_tt_init_misaligned
[06:45:03] [PASSED] ttm_tt_fini_basic
[06:45:03] [PASSED] ttm_tt_fini_sg
[06:45:03] [PASSED] ttm_tt_fini_shmem
[06:45:03] [PASSED] ttm_tt_create_basic
[06:45:03] [PASSED] ttm_tt_create_invalid_bo_type
[06:45:03] [PASSED] ttm_tt_create_ttm_exists
[06:45:03] [PASSED] ttm_tt_create_failed
[06:45:03] [PASSED] ttm_tt_destroy_basic
[06:45:03] [PASSED] ttm_tt_populate_null_ttm
[06:45:03] [PASSED] ttm_tt_populate_populated_ttm
[06:45:03] [PASSED] ttm_tt_unpopulate_basic
[06:45:03] [PASSED] ttm_tt_unpopulate_empty_ttm
[06:45:03] [PASSED] ttm_tt_swapin_basic
[06:45:03] ===================== [PASSED] ttm_tt ======================
[06:45:03] =================== ttm_bo (14 subtests) ===================
[06:45:03] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[06:45:03] [PASSED] Cannot be interrupted and sleeps
[06:45:03] [PASSED] Cannot be interrupted, locks straight away
[06:45:03] [PASSED] Can be interrupted, sleeps
[06:45:03] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[06:45:03] [PASSED] ttm_bo_reserve_locked_no_sleep
[06:45:03] [PASSED] ttm_bo_reserve_no_wait_ticket
[06:45:03] [PASSED] ttm_bo_reserve_double_resv
[06:45:03] [PASSED] ttm_bo_reserve_interrupted
[06:45:03] [PASSED] ttm_bo_reserve_deadlock
[06:45:03] [PASSED] ttm_bo_unreserve_basic
[06:45:03] [PASSED] ttm_bo_unreserve_pinned
[06:45:03] [PASSED] ttm_bo_unreserve_bulk
[06:45:03] [PASSED] ttm_bo_fini_basic
[06:45:03] [PASSED] ttm_bo_fini_shared_resv
[06:45:03] [PASSED] ttm_bo_pin_basic
[06:45:03] [PASSED] ttm_bo_pin_unpin_resource
[06:45:03] [PASSED] ttm_bo_multiple_pin_one_unpin
[06:45:03] ===================== [PASSED] ttm_bo ======================
[06:45:03] ============== ttm_bo_validate (22 subtests) ===============
[06:45:03] ============== ttm_bo_init_reserved_sys_man ===============
[06:45:03] [PASSED] Buffer object for userspace
[06:45:03] [PASSED] Kernel buffer object
[06:45:03] [PASSED] Shared buffer object
[06:45:03] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[06:45:03] ============== ttm_bo_init_reserved_mock_man ==============
[06:45:03] [PASSED] Buffer object for userspace
[06:45:03] [PASSED] Kernel buffer object
[06:45:03] [PASSED] Shared buffer object
[06:45:03] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[06:45:03] [PASSED] ttm_bo_init_reserved_resv
[06:45:03] ================== ttm_bo_validate_basic ==================
[06:45:03] [PASSED] Buffer object for userspace
[06:45:03] [PASSED] Kernel buffer object
[06:45:03] [PASSED] Shared buffer object
[06:45:03] ============== [PASSED] ttm_bo_validate_basic ==============
[06:45:03] [PASSED] ttm_bo_validate_invalid_placement
[06:45:03] ============= ttm_bo_validate_same_placement ==============
[06:45:03] [PASSED] System manager
[06:45:03] [PASSED] VRAM manager
[06:45:03] ========= [PASSED] ttm_bo_validate_same_placement ==========
[06:45:03] [PASSED] ttm_bo_validate_failed_alloc
[06:45:03] [PASSED] ttm_bo_validate_pinned
[06:45:03] [PASSED] ttm_bo_validate_busy_placement
[06:45:03] ================ ttm_bo_validate_multihop =================
[06:45:03] [PASSED] Buffer object for userspace
[06:45:03] [PASSED] Kernel buffer object
[06:45:03] [PASSED] Shared buffer object
[06:45:03] ============ [PASSED] ttm_bo_validate_multihop =============
[06:45:03] ========== ttm_bo_validate_no_placement_signaled ==========
[06:45:03] [PASSED] Buffer object in system domain, no page vector
[06:45:03] [PASSED] Buffer object in system domain with an existing page vector
[06:45:03] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[06:45:03] ======== ttm_bo_validate_no_placement_not_signaled ========
[06:45:03] [PASSED] Buffer object for userspace
[06:45:03] [PASSED] Kernel buffer object
[06:45:03] [PASSED] Shared buffer object
[06:45:03] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[06:45:03] [PASSED] ttm_bo_validate_move_fence_signaled
[06:45:03] ========= ttm_bo_validate_move_fence_not_signaled =========
[06:45:03] [PASSED] Waits for GPU
[06:45:03] [PASSED] Tries to lock straight away
[06:45:03] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[06:45:03] [PASSED] ttm_bo_validate_swapout
[06:45:03] [PASSED] ttm_bo_validate_happy_evict
[06:45:03] [PASSED] ttm_bo_validate_all_pinned_evict
[06:45:03] [PASSED] ttm_bo_validate_allowed_only_evict
[06:45:03] [PASSED] ttm_bo_validate_deleted_evict
[06:45:03] [PASSED] ttm_bo_validate_busy_domain_evict
[06:45:03] [PASSED] ttm_bo_validate_evict_gutting
[06:45:03] [PASSED] ttm_bo_validate_recrusive_evict
[06:45:03] ================= [PASSED] ttm_bo_validate =================
[06:45:03] ============================================================
[06:45:03] Testing complete. Ran 102 tests: passed: 102
[06:45:03] Elapsed time: 11.445s total, 1.702s configuring, 9.528s building, 0.185s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v5 0/6] Add get-error-counter and clear-error-counter support for CRI
@ 2026-05-04 6:56 Riana Tauro
2026-05-04 6:43 ` ✗ CI.checkpatch: warning for Add get-error-counter and clear-error-counter support for CRI (rev4) Patchwork
` (8 more replies)
0 siblings, 9 replies; 14+ messages in thread
From: Riana Tauro @ 2026-05-04 6:56 UTC (permalink / raw)
To: intel-xe
Cc: riana.tauro, anshuman.gupta, rodrigo.vivi, aravind.iddamsetty,
badal.nilawar, raag.jadav, ravi.kishore.koppuravuri,
mallesh.koujalagi, soham.purkait
Define request/response structures and helper functions to query system
controller to get/clear counter values for CRI.
Integrate get-error-counter with xe_drm_ras.
Usage:
Query all error counters using ynl
$ sudo ynl --family drm_ras --dump get-error-counter --json \
'{"node-id":0}'
[{'error-id': 1, 'error-name': 'core-compute', 'error-value': 0},
{'error-id': 2, 'error-name': 'soc-internal', 'error-value': 0},
{'error-id': 3, 'error-name': 'device-memory', 'error-value': 0},
{'error-id': 4, 'error-name': 'pcie', 'error-value': 0},
{'error-id': 5, 'error-name': 'fabric', 'error-value': 0}]
Query single error counter using ynl
$ sudo ynl --family drm_ras --do get-error-counter --json \
'{"node-id":1, "error-id":1}'
{'error-id': 1, 'error-name': 'core-compute', 'error-value': 2}
Clear counter using ynl
$ sudo ynl --family drm_ras --do clear-error-counter --json '\
{"node-id":1, "error-id":1}'
None
Rev2: add helper for clear counter
separate get error counter for other usecases
move commands to sysctrl layer
Rev3: integrate clear-error-counter with drm_ras
use drm_ras flag
move drm_ras registration to ras init flow
Rev4: rebase
Riana Tauro (6):
drm/xe/uapi: Add additional error components to xe drm_ras
drm/xe/xe_ras: Add support to get error counter in CRI
drm/xe/xe_ras: Add helper to clear error counter
drm/xe/xe_drm_ras: Wire get-error-counter and clear-error-counter
support for CRI
drm/xe/xe_ras: Move xe drm_ras registration
drm/xe/xe_ras: Control xe drm_ras registration with a flag
drivers/gpu/drm/xe/xe_device.c | 19 +-
drivers/gpu/drm/xe/xe_device_types.h | 2 +
drivers/gpu/drm/xe/xe_drm_ras.c | 39 ++--
drivers/gpu/drm/xe/xe_hw_error.c | 13 --
drivers/gpu/drm/xe/xe_pci.c | 3 +
drivers/gpu/drm/xe/xe_pci_types.h | 1 +
drivers/gpu/drm/xe/xe_ras.c | 187 ++++++++++++++++++
drivers/gpu/drm/xe/xe_ras.h | 7 +
drivers/gpu/drm/xe/xe_ras_types.h | 55 ++++++
drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h | 4 +
include/uapi/drm/xe_drm.h | 11 +-
11 files changed, 305 insertions(+), 36 deletions(-)
--
2.47.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v5 1/6] drm/xe/uapi: Add additional error components to xe drm_ras
2026-05-04 6:56 [PATCH v5 0/6] Add get-error-counter and clear-error-counter support for CRI Riana Tauro
2026-05-04 6:43 ` ✗ CI.checkpatch: warning for Add get-error-counter and clear-error-counter support for CRI (rev4) Patchwork
2026-05-04 6:45 ` ✓ CI.KUnit: success " Patchwork
@ 2026-05-04 6:56 ` Riana Tauro
2026-05-04 6:56 ` [PATCH v5 2/6] drm/xe/xe_ras: Add support to get error counter in CRI Riana Tauro
` (5 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: Riana Tauro @ 2026-05-04 6:56 UTC (permalink / raw)
To: intel-xe
Cc: riana.tauro, anshuman.gupta, rodrigo.vivi, aravind.iddamsetty,
badal.nilawar, raag.jadav, ravi.kishore.koppuravuri,
mallesh.koujalagi, soham.purkait
Add additional Error components supported by XE drm_ras (Reliability,
Availability and Serviceability).
Signed-off-by: Riana Tauro <riana.tauro@intel.com>
Reviewed-by: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
---
include/uapi/drm/xe_drm.h | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
index 48e9f1fdb78d..50c80af4ad4e 100644
--- a/include/uapi/drm/xe_drm.h
+++ b/include/uapi/drm/xe_drm.h
@@ -2589,6 +2589,12 @@ enum drm_xe_ras_error_component {
DRM_XE_RAS_ERR_COMP_CORE_COMPUTE = 1,
/** @DRM_XE_RAS_ERR_COMP_SOC_INTERNAL: SoC Internal Error */
DRM_XE_RAS_ERR_COMP_SOC_INTERNAL,
+ /** @DRM_XE_RAS_ERR_COMP_DEVICE_MEMORY: Device Memory Error */
+ DRM_XE_RAS_ERR_COMP_DEVICE_MEMORY,
+ /** @DRM_XE_RAS_ERR_COMP_PCIE: PCIe Subsystem Error */
+ DRM_XE_RAS_ERR_COMP_PCIE,
+ /** @DRM_XE_RAS_ERR_COMP_FABRIC: Fabric Subsystem Error */
+ DRM_XE_RAS_ERR_COMP_FABRIC,
/** @DRM_XE_RAS_ERR_COMP_MAX: Max Error */
DRM_XE_RAS_ERR_COMP_MAX /* non-ABI */
};
@@ -2606,7 +2612,10 @@ enum drm_xe_ras_error_component {
*/
#define DRM_XE_RAS_ERROR_COMPONENT_NAMES { \
[DRM_XE_RAS_ERR_COMP_CORE_COMPUTE] = "core-compute", \
- [DRM_XE_RAS_ERR_COMP_SOC_INTERNAL] = "soc-internal" \
+ [DRM_XE_RAS_ERR_COMP_SOC_INTERNAL] = "soc-internal", \
+ [DRM_XE_RAS_ERR_COMP_DEVICE_MEMORY] = "device-memory", \
+ [DRM_XE_RAS_ERR_COMP_PCIE] = "pcie", \
+ [DRM_XE_RAS_ERR_COMP_FABRIC] = "fabric", \
}
#if defined(__cplusplus)
--
2.47.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v5 2/6] drm/xe/xe_ras: Add support to get error counter in CRI
2026-05-04 6:56 [PATCH v5 0/6] Add get-error-counter and clear-error-counter support for CRI Riana Tauro
` (2 preceding siblings ...)
2026-05-04 6:56 ` [PATCH v5 1/6] drm/xe/uapi: Add additional error components to xe drm_ras Riana Tauro
@ 2026-05-04 6:56 ` Riana Tauro
2026-05-06 8:03 ` Mallesh, Koujalagi
2026-05-04 6:56 ` [PATCH v5 3/6] drm/xe/xe_ras: Add helper to clear error counter Riana Tauro
` (4 subsequent siblings)
8 siblings, 1 reply; 14+ messages in thread
From: Riana Tauro @ 2026-05-04 6:56 UTC (permalink / raw)
To: intel-xe
Cc: riana.tauro, anshuman.gupta, rodrigo.vivi, aravind.iddamsetty,
badal.nilawar, raag.jadav, ravi.kishore.koppuravuri,
mallesh.koujalagi, soham.purkait
Add request/response structures and helper functions to query system
controller to get error counter value.
Signed-off-by: Riana Tauro <riana.tauro@intel.com>
---
v2: add structures for clear counter
move commands to sysctrl file
split functions
fix commit message (Raag)
v3: fix log message
squash patches
change error code for sysctrl error (Raag)
v4: rename function
remove unecessary macro (Raag)
add documentation for enum
v5: rebase
---
drivers/gpu/drm/xe/xe_ras.c | 91 +++++++++++++++++++
drivers/gpu/drm/xe/xe_ras.h | 4 +
drivers/gpu/drm/xe/xe_ras_types.h | 30 ++++++
drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h | 2 +
4 files changed, 127 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
index 4cb16b419b0c..47a58ce3b3ca 100644
--- a/drivers/gpu/drm/xe/xe_ras.c
+++ b/drivers/gpu/drm/xe/xe_ras.c
@@ -4,11 +4,14 @@
*/
#include "xe_device.h"
+#include "xe_pm.h"
#include "xe_printk.h"
#include "xe_ras.h"
#include "xe_ras_types.h"
#include "xe_sysctrl.h"
#include "xe_sysctrl_event_types.h"
+#include "xe_sysctrl_mailbox.h"
+#include "xe_sysctrl_mailbox_types.h"
/* Severity of detected errors */
enum xe_ras_severity {
@@ -50,6 +53,23 @@ static const char *const xe_ras_components[] = {
};
static_assert(ARRAY_SIZE(xe_ras_components) == XE_RAS_COMP_MAX);
+/* Mapping from drm_xe_ras_error_component to xe_ras_component */
+static const int drm_to_xe_ras_component[] = {
+ [DRM_XE_RAS_ERR_COMP_CORE_COMPUTE] = XE_RAS_COMP_CORE_COMPUTE,
+ [DRM_XE_RAS_ERR_COMP_SOC_INTERNAL] = XE_RAS_COMP_SOC_INTERNAL,
+ [DRM_XE_RAS_ERR_COMP_DEVICE_MEMORY] = XE_RAS_COMP_DEVICE_MEMORY,
+ [DRM_XE_RAS_ERR_COMP_PCIE] = XE_RAS_COMP_PCIE,
+ [DRM_XE_RAS_ERR_COMP_FABRIC] = XE_RAS_COMP_FABRIC
+};
+static_assert(ARRAY_SIZE(drm_to_xe_ras_component) == DRM_XE_RAS_ERR_COMP_MAX);
+
+/* Mapping from drm_xe_ras_error_severity to xe_ras_severity */
+static const int drm_to_xe_ras_severity[] = {
+ [DRM_XE_RAS_ERR_SEV_CORRECTABLE] = XE_RAS_SEV_CORRECTABLE,
+ [DRM_XE_RAS_ERR_SEV_UNCORRECTABLE] = XE_RAS_SEV_UNCORRECTABLE
+};
+static_assert(ARRAY_SIZE(drm_to_xe_ras_severity) == DRM_XE_RAS_ERR_SEV_MAX);
+
static inline const char *sev_to_str(u8 severity)
{
if (severity >= XE_RAS_SEV_MAX)
@@ -66,6 +86,22 @@ static inline const char *comp_to_str(u8 component)
return xe_ras_components[component];
}
+static void prepare_ras_command(struct xe_sysctrl_mailbox_command *command,
+ u32 cmd, void *request, size_t request_len,
+ void *response, size_t response_len)
+{
+ struct xe_sysctrl_app_msg_hdr header = {0};
+
+ header.data = FIELD_PREP(APP_HDR_GROUP_ID_MASK, XE_SYSCTRL_GROUP_GFSP) |
+ FIELD_PREP(APP_HDR_COMMAND_MASK, cmd);
+
+ command->header = header;
+ command->data_in = request;
+ command->data_in_len = request_len;
+ command->data_out = response;
+ command->data_out_len = response_len;
+}
+
void xe_ras_counter_threshold_crossed(struct xe_device *xe,
struct xe_sysctrl_event_response *response)
{
@@ -91,3 +127,58 @@ void xe_ras_counter_threshold_crossed(struct xe_device *xe,
comp_to_str(component), sev_to_str(severity));
}
}
+
+static int get_counter(struct xe_device *xe, struct xe_ras_error_class *error_class,
+ u32 *value)
+{
+ struct xe_ras_get_counter_response response = {0};
+ struct xe_ras_get_counter_request request = {0};
+ struct xe_sysctrl_mailbox_command command = {0};
+ size_t rlen;
+ int ret;
+
+ request.error_class = *error_class;
+
+ prepare_ras_command(&command, XE_SYSCTRL_CMD_GET_COUNTER, &request, sizeof(request),
+ &response, sizeof(response));
+
+ ret = xe_sysctrl_send_command(&xe->sc, &command, &rlen);
+ if (ret) {
+ xe_err(xe, "sysctrl: failed to get counter %d\n", ret);
+ return ret;
+ }
+
+ if (rlen != sizeof(response)) {
+ xe_err(xe, "sysctrl: unexpected get counter response length %zu (expected %zu)\n",
+ rlen, sizeof(response));
+ return -EIO;
+ }
+
+ *value = response.counter_value;
+
+ return 0;
+}
+
+/**
+ * xe_ras_get_counter() - Get error counter value
+ * @xe: xe device instance
+ * @severity: Error severity level to be queried
+ * @error_id: Error component to be queried
+ * @value: Counter value
+ *
+ * This function retrieves the value of a specific error counter based on
+ * the error severity and component.
+ *
+ * Return: 0 on success, negative error code on failure.
+ */
+int xe_ras_get_counter(struct xe_device *xe, enum drm_xe_ras_error_severity severity,
+ u32 error_id, u32 *value)
+{
+ struct xe_ras_error_class error_class = {0};
+
+ error_class.common.severity = drm_to_xe_ras_severity[severity];
+ error_class.common.component = drm_to_xe_ras_component[error_id];
+
+ guard(xe_pm_runtime)(xe);
+ return get_counter(xe, &error_class, value);
+}
diff --git a/drivers/gpu/drm/xe/xe_ras.h b/drivers/gpu/drm/xe/xe_ras.h
index ea90593b62dc..74582c911b02 100644
--- a/drivers/gpu/drm/xe/xe_ras.h
+++ b/drivers/gpu/drm/xe/xe_ras.h
@@ -6,10 +6,14 @@
#ifndef _XE_RAS_H_
#define _XE_RAS_H_
+#include <uapi/drm/xe_drm.h>
+
struct xe_device;
struct xe_sysctrl_event_response;
void xe_ras_counter_threshold_crossed(struct xe_device *xe,
struct xe_sysctrl_event_response *response);
+int xe_ras_get_counter(struct xe_device *xe, enum drm_xe_ras_error_severity severity,
+ u32 error_id, u32 *value);
#endif
diff --git a/drivers/gpu/drm/xe/xe_ras_types.h b/drivers/gpu/drm/xe/xe_ras_types.h
index 4e63c67f806a..74d85875cd63 100644
--- a/drivers/gpu/drm/xe/xe_ras_types.h
+++ b/drivers/gpu/drm/xe/xe_ras_types.h
@@ -70,4 +70,34 @@ struct xe_ras_threshold_crossed {
struct xe_ras_error_class counters[XE_RAS_NUM_COUNTERS];
} __packed;
+/**
+ * struct xe_ras_get_counter_request - Request for get error counter
+ */
+struct xe_ras_get_counter_request {
+ /** @error_class: Error class counter to be queried */
+ struct xe_ras_error_class error_class;
+ /** @reserved: Reserved for future use */
+ u32 reserved;
+} __packed;
+
+/**
+ * struct xe_ras_get_counter_response - Response for get error counter
+ */
+struct xe_ras_get_counter_response {
+ /** @error_class: Error class counter that was queried */
+ struct xe_ras_error_class error_class;
+ /** @counter_value: Current counter value */
+ u32 counter_value;
+ /** @timestamp: Timestamp when counter was last updated */
+ u64 timestamp;
+ /** @threshold_value: Threshold value for the counter */
+ u32 threshold_value;
+ /** @counter_status: Status of the counter */
+ u32 counter_status:8;
+ /** @reserved: Reserved for future use */
+ u32 reserved:24;
+ /** @reserved1: Reserved for future use */
+ u32 reserved1[56];
+} __packed;
+
#endif
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
index 84d7c647e743..b315847cbf64 100644
--- a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
+++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
@@ -22,9 +22,11 @@ enum xe_sysctrl_group {
/**
* enum xe_sysctrl_gfsp_cmd - Commands supported by GFSP group
*
+ * @XE_SYSCTRL_CMD_GET_COUNTER: Get error counter value
* @XE_SYSCTRL_CMD_GET_PENDING_EVENT: Retrieve pending event
*/
enum xe_sysctrl_gfsp_cmd {
+ XE_SYSCTRL_CMD_GET_COUNTER = 0x03,
XE_SYSCTRL_CMD_GET_PENDING_EVENT = 0x07,
};
--
2.47.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v5 3/6] drm/xe/xe_ras: Add helper to clear error counter
2026-05-04 6:56 [PATCH v5 0/6] Add get-error-counter and clear-error-counter support for CRI Riana Tauro
` (3 preceding siblings ...)
2026-05-04 6:56 ` [PATCH v5 2/6] drm/xe/xe_ras: Add support to get error counter in CRI Riana Tauro
@ 2026-05-04 6:56 ` Riana Tauro
2026-05-04 6:56 ` [PATCH v5 4/6] drm/xe/xe_drm_ras: Wire get-error-counter and clear-error-counter support for CRI Riana Tauro
` (3 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: Riana Tauro @ 2026-05-04 6:56 UTC (permalink / raw)
To: intel-xe
Cc: riana.tauro, anshuman.gupta, rodrigo.vivi, aravind.iddamsetty,
badal.nilawar, raag.jadav, ravi.kishore.koppuravuri,
mallesh.koujalagi, soham.purkait
Add structures and helper function to clear error counter value.
Signed-off-by: Riana Tauro <riana.tauro@intel.com>
---
v2: add status codes (Aravind)
fix log message
squash structure patch (Raag)
v3: rename function
add comma to enum members to avoid
redundant churn
align with tabs (Raag)
v4: rebase
---
drivers/gpu/drm/xe/xe_ras.c | 76 +++++++++++++++++++
drivers/gpu/drm/xe/xe_ras.h | 2 +
drivers/gpu/drm/xe/xe_ras_types.h | 25 ++++++
drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h | 2 +
4 files changed, 105 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
index 47a58ce3b3ca..07f6837694e7 100644
--- a/drivers/gpu/drm/xe/xe_ras.c
+++ b/drivers/gpu/drm/xe/xe_ras.c
@@ -34,6 +34,17 @@ enum xe_ras_component {
XE_RAS_COMP_MAX
};
+/* RAS response status codes */
+enum xe_ras_response_status {
+ XE_RAS_STATUS_SUCCESS = 0,
+ XE_RAS_STATUS_INVALID_PARAM,
+ XE_RAS_STATUS_OP_NOT_SUPPORTED,
+ XE_RAS_STATUS_TIMEOUT,
+ XE_RAS_STATUS_HARDWARE_FAILURE,
+ XE_RAS_STATUS_INSUFFICIENT_RESOURCES,
+ XE_RAS_STATUS_UNKNOWN_ERROR
+};
+
static const char *const xe_ras_severities[] = {
[XE_RAS_SEV_NOT_SUPPORTED] = "Not Supported",
[XE_RAS_SEV_CORRECTABLE] = "Correctable Error",
@@ -53,6 +64,16 @@ static const char *const xe_ras_components[] = {
};
static_assert(ARRAY_SIZE(xe_ras_components) == XE_RAS_COMP_MAX);
+static const int ras_status_to_errno_map[] = {
+ [XE_RAS_STATUS_SUCCESS] = 0,
+ [XE_RAS_STATUS_INVALID_PARAM] = -EINVAL,
+ [XE_RAS_STATUS_OP_NOT_SUPPORTED] = -EOPNOTSUPP,
+ [XE_RAS_STATUS_TIMEOUT] = -ETIMEDOUT,
+ [XE_RAS_STATUS_HARDWARE_FAILURE] = -EIO,
+ [XE_RAS_STATUS_INSUFFICIENT_RESOURCES] = -ENAVAIL,
+ [XE_RAS_STATUS_UNKNOWN_ERROR] = -ENODATA
+};
+
/* Mapping from drm_xe_ras_error_component to xe_ras_component */
static const int drm_to_xe_ras_component[] = {
[DRM_XE_RAS_ERR_COMP_CORE_COMPUTE] = XE_RAS_COMP_CORE_COMPUTE,
@@ -70,6 +91,13 @@ static const int drm_to_xe_ras_severity[] = {
};
static_assert(ARRAY_SIZE(drm_to_xe_ras_severity) == DRM_XE_RAS_ERR_SEV_MAX);
+static int ras_status_to_errno(enum xe_ras_response_status status)
+{
+ if (status > XE_RAS_STATUS_UNKNOWN_ERROR)
+ status = XE_RAS_STATUS_UNKNOWN_ERROR;
+
+ return ras_status_to_errno_map[status];
+}
static inline const char *sev_to_str(u8 severity)
{
if (severity >= XE_RAS_SEV_MAX)
@@ -182,3 +210,51 @@ int xe_ras_get_counter(struct xe_device *xe, enum drm_xe_ras_error_severity seve
guard(xe_pm_runtime)(xe);
return get_counter(xe, &error_class, value);
}
+
+/**
+ * xe_ras_clear_counter() - Clear error counter value
+ * @xe: xe device instance
+ * @severity: Error severity level to be cleared
+ * @error_id: Error component to be cleared
+ *
+ * This function clears the value of a specific error counter based on
+ * the error severity and component.
+ *
+ * Return: 0 on success, negative error code on failure.
+ */
+int xe_ras_clear_counter(struct xe_device *xe, enum drm_xe_ras_error_severity severity,
+ u32 error_id)
+{
+ struct xe_ras_clear_counter_response response = {0};
+ struct xe_ras_clear_counter_request request = {0};
+ struct xe_sysctrl_mailbox_command command = {0};
+ struct xe_ras_error_class *error_class;
+ size_t rlen;
+ int ret;
+
+ error_class = &request.error_class;
+ error_class->common.severity = drm_to_xe_ras_severity[severity];
+ error_class->common.component = drm_to_xe_ras_component[error_id];
+
+ prepare_ras_command(&command, XE_SYSCTRL_CMD_CLEAR_COUNTER, &request, sizeof(request),
+ &response, sizeof(response));
+
+ guard(xe_pm_runtime)(xe);
+ ret = xe_sysctrl_send_command(&xe->sc, &command, &rlen);
+ if (ret) {
+ xe_err(xe, "sysctrl: failed to clear counter %d\n", ret);
+ return ret;
+ }
+
+ if (rlen != sizeof(response)) {
+ xe_err(xe, "sysctrl: unexpected clear counter response length %zu (expected %zu)\n",
+ rlen, sizeof(response));
+ return -EIO;
+ }
+
+ ret = ras_status_to_errno(response.status);
+ if (ret)
+ xe_err(xe, "sysctrl: clear counter command failed with status %d\n", ret);
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/xe/xe_ras.h b/drivers/gpu/drm/xe/xe_ras.h
index 74582c911b02..bbb9d42bd128 100644
--- a/drivers/gpu/drm/xe/xe_ras.h
+++ b/drivers/gpu/drm/xe/xe_ras.h
@@ -15,5 +15,7 @@ void xe_ras_counter_threshold_crossed(struct xe_device *xe,
struct xe_sysctrl_event_response *response);
int xe_ras_get_counter(struct xe_device *xe, enum drm_xe_ras_error_severity severity,
u32 error_id, u32 *value);
+int xe_ras_clear_counter(struct xe_device *xe, enum drm_xe_ras_error_severity severity,
+ u32 error_id);
#endif
diff --git a/drivers/gpu/drm/xe/xe_ras_types.h b/drivers/gpu/drm/xe/xe_ras_types.h
index 74d85875cd63..44369fc8ef03 100644
--- a/drivers/gpu/drm/xe/xe_ras_types.h
+++ b/drivers/gpu/drm/xe/xe_ras_types.h
@@ -100,4 +100,29 @@ struct xe_ras_get_counter_response {
u32 reserved1[56];
} __packed;
+/**
+ * struct xe_ras_clear_counter_request - Request for clearing an error counter
+ */
+struct xe_ras_clear_counter_request {
+ /** @error_class: Counter class to be cleared */
+ struct xe_ras_error_class error_class;
+ /** @reserved: Reserved for future use */
+ u32 reserved;
+} __packed;
+
+/**
+ * struct xe_ras_clear_counter_response - Response after clearing an error counter
+ */
+struct xe_ras_clear_counter_response {
+ /** @error_class: Counter class that was cleared */
+ struct xe_ras_error_class error_class;
+ /** @previous_counter_value: Counter value before clearing */
+ u32 previous_counter_value;
+ /** @clear_timestamp: Timestamp when the counter was cleared */
+ u64 clear_timestamp;
+ /** @status: Status of the clear operation */
+ u32 status;
+ /** @reserved: Reserved for future use */
+ u32 reserved[3];
+} __packed;
#endif
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
index b315847cbf64..6e3753554510 100644
--- a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
+++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
@@ -23,10 +23,12 @@ enum xe_sysctrl_group {
* enum xe_sysctrl_gfsp_cmd - Commands supported by GFSP group
*
* @XE_SYSCTRL_CMD_GET_COUNTER: Get error counter value
+ * @XE_SYSCTRL_CMD_CLEAR_COUNTER: Clear error counter value
* @XE_SYSCTRL_CMD_GET_PENDING_EVENT: Retrieve pending event
*/
enum xe_sysctrl_gfsp_cmd {
XE_SYSCTRL_CMD_GET_COUNTER = 0x03,
+ XE_SYSCTRL_CMD_CLEAR_COUNTER = 0x04,
XE_SYSCTRL_CMD_GET_PENDING_EVENT = 0x07,
};
--
2.47.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v5 4/6] drm/xe/xe_drm_ras: Wire get-error-counter and clear-error-counter support for CRI
2026-05-04 6:56 [PATCH v5 0/6] Add get-error-counter and clear-error-counter support for CRI Riana Tauro
` (4 preceding siblings ...)
2026-05-04 6:56 ` [PATCH v5 3/6] drm/xe/xe_ras: Add helper to clear error counter Riana Tauro
@ 2026-05-04 6:56 ` Riana Tauro
2026-05-04 6:56 ` [PATCH v5 5/6] drm/xe/xe_ras: Move xe drm_ras registration Riana Tauro
` (2 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: Riana Tauro @ 2026-05-04 6:56 UTC (permalink / raw)
To: intel-xe
Cc: riana.tauro, anshuman.gupta, rodrigo.vivi, aravind.iddamsetty,
badal.nilawar, raag.jadav, ravi.kishore.koppuravuri,
mallesh.koujalagi, soham.purkait
Hook CRI get-error-counter and clear-error-counter support to
xe_drm_ras to allow userspace to query and clear counters if supported.
When userspace requests for a drm_ras error counter, query the system
controller to get/clear the value.
Integrate this with xe_drm_ras.
Usage :
Query all error counter value using ynl
$ sudo ynl --family drm_ras --dump get-error-counter --json \
'{"node-id":0}'
[{'error-id': 1, 'error-name': 'core-compute', 'error-value': 0},
{'error-id': 2, 'error-name': 'soc-internal', 'error-value': 0},
{'error-id': 3, 'error-name': 'device-memory', 'error-value': 0},
{'error-id': 4, 'error-name': 'pcie', 'error-value': 0},
{'error-id': 5, 'error-name': 'fabric', 'error-value': 0}]
Query single error counter value using ynl
$ sudo ynl --family drm_ras --do get-error-counter --json \
'{"node-id":1, "error-id":1}'
{'error-id': 1, 'error-name': 'core-compute', 'error-value': 2}
Clear counter using ynl
$ sudo ynl --family drm_ras --do clear-error-counter --json '\
{"node-id":1, "error-id":1}'
None
Signed-off-by: Riana Tauro <riana.tauro@intel.com>
---
v2: split patches (Raag)
v3: fix early return
align spacing in commit message (Raag)
integrate clear counter with drm_ras
v4: rebase
---
drivers/gpu/drm/xe/xe_drm_ras.c | 39 +++++++++++++++++++++------------
1 file changed, 25 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_drm_ras.c b/drivers/gpu/drm/xe/xe_drm_ras.c
index c21c8b428de6..e7bd3f09a762 100644
--- a/drivers/gpu/drm/xe/xe_drm_ras.c
+++ b/drivers/gpu/drm/xe/xe_drm_ras.c
@@ -11,27 +11,46 @@
#include "xe_device_types.h"
#include "xe_drm_ras.h"
+#include "xe_ras.h"
static const char * const error_components[] = DRM_XE_RAS_ERROR_COMPONENT_NAMES;
static const char * const error_severity[] = DRM_XE_RAS_ERROR_SEVERITY_NAMES;
-static int hw_query_error_counter(struct xe_drm_ras_counter *info,
+static int hw_query_error_counter(struct xe_device *xe,
+ enum drm_xe_ras_error_severity severity,
u32 error_id, const char **name, u32 *val)
{
+ struct xe_drm_ras *ras = &xe->ras;
+ struct xe_drm_ras_counter *info = ras->info[severity];
+
if (!info || !info[error_id].name)
return -ENOENT;
*name = info[error_id].name;
+
+ /* Fetch counter from system controller if supported */
+ if (xe->info.has_sysctrl)
+ return xe_ras_get_counter(xe, severity, error_id, val);
+
*val = atomic_read(&info[error_id].counter);
return 0;
}
-static int hw_clear_error_counter(struct xe_drm_ras_counter *info, u32 error_id)
+static int hw_clear_error_counter(struct xe_device *xe,
+ enum drm_xe_ras_error_severity severity,
+ u32 error_id)
{
+ struct xe_drm_ras *ras = &xe->ras;
+ struct xe_drm_ras_counter *info = ras->info[severity];
+
if (!info || !info[error_id].name)
return -ENOENT;
+ /* Clear counter from system controller if supported */
+ if (xe->info.has_sysctrl)
+ return xe_ras_clear_counter(xe, severity, error_id);
+
atomic_set(&info[error_id].counter, 0);
return 0;
@@ -41,38 +60,30 @@ static int query_uncorrectable_error_counter(struct drm_ras_node *ep, u32 error_
const char **name, u32 *val)
{
struct xe_device *xe = ep->priv;
- struct xe_drm_ras *ras = &xe->ras;
- struct xe_drm_ras_counter *info = ras->info[DRM_XE_RAS_ERR_SEV_UNCORRECTABLE];
- return hw_query_error_counter(info, error_id, name, val);
+ return hw_query_error_counter(xe, DRM_XE_RAS_ERR_SEV_UNCORRECTABLE, error_id, name, val);
}
static int clear_uncorrectable_error_counter(struct drm_ras_node *node, u32 error_id)
{
struct xe_device *xe = node->priv;
- struct xe_drm_ras *ras = &xe->ras;
- struct xe_drm_ras_counter *info = ras->info[DRM_XE_RAS_ERR_SEV_UNCORRECTABLE];
- return hw_clear_error_counter(info, error_id);
+ return hw_clear_error_counter(xe, DRM_XE_RAS_ERR_SEV_UNCORRECTABLE, error_id);
}
static int query_correctable_error_counter(struct drm_ras_node *ep, u32 error_id,
const char **name, u32 *val)
{
struct xe_device *xe = ep->priv;
- struct xe_drm_ras *ras = &xe->ras;
- struct xe_drm_ras_counter *info = ras->info[DRM_XE_RAS_ERR_SEV_CORRECTABLE];
- return hw_query_error_counter(info, error_id, name, val);
+ return hw_query_error_counter(xe, DRM_XE_RAS_ERR_SEV_CORRECTABLE, error_id, name, val);
}
static int clear_correctable_error_counter(struct drm_ras_node *node, u32 error_id)
{
struct xe_device *xe = node->priv;
- struct xe_drm_ras *ras = &xe->ras;
- struct xe_drm_ras_counter *info = ras->info[DRM_XE_RAS_ERR_SEV_CORRECTABLE];
- return hw_clear_error_counter(info, error_id);
+ return hw_clear_error_counter(xe, DRM_XE_RAS_ERR_SEV_CORRECTABLE, error_id);
}
static struct xe_drm_ras_counter *allocate_and_copy_counters(struct xe_device *xe)
--
2.47.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v5 5/6] drm/xe/xe_ras: Move xe drm_ras registration
2026-05-04 6:56 [PATCH v5 0/6] Add get-error-counter and clear-error-counter support for CRI Riana Tauro
` (5 preceding siblings ...)
2026-05-04 6:56 ` [PATCH v5 4/6] drm/xe/xe_drm_ras: Wire get-error-counter and clear-error-counter support for CRI Riana Tauro
@ 2026-05-04 6:56 ` Riana Tauro
2026-05-04 10:53 ` Tauro, Riana
2026-05-04 6:56 ` [PATCH v5 6/6] drm/xe/xe_ras: Control xe drm_ras registration with a flag Riana Tauro
2026-05-04 8:00 ` ✓ Xe.CI.BAT: success for Add get-error-counter and clear-error-counter support for CRI (rev4) Patchwork
8 siblings, 1 reply; 14+ messages in thread
From: Riana Tauro @ 2026-05-04 6:56 UTC (permalink / raw)
To: intel-xe
Cc: riana.tauro, anshuman.gupta, rodrigo.vivi, aravind.iddamsetty,
badal.nilawar, raag.jadav, ravi.kishore.koppuravuri,
mallesh.koujalagi, soham.purkait, Anoop Vijay,
Umesh Nerlige Ramappa
Move xe drm_ras registration to RAS initialization flow and keep
hardware error initialization for processing errors reported
via irq.
Also reorder soc remapper and system controller initialization to
early probe as ras init is dependent on both.
Cc: Anoop Vijay <anoop.c.vijay@intel.com>
Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Signed-off-by: Riana Tauro <riana.tauro@intel.com>
---
drivers/gpu/drm/xe/xe_device.c | 19 +++++++++++--------
drivers/gpu/drm/xe/xe_hw_error.c | 13 -------------
drivers/gpu/drm/xe/xe_ras.c | 20 ++++++++++++++++++++
drivers/gpu/drm/xe/xe_ras.h | 1 +
4 files changed, 32 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index 4b45b617a039..041af7ffc8bb 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -62,6 +62,7 @@
#include "xe_psmi.h"
#include "xe_pxp.h"
#include "xe_query.h"
+#include "xe_ras.h"
#include "xe_shrinker.h"
#include "xe_soc_remapper.h"
#include "xe_survivability_mode.h"
@@ -962,6 +963,16 @@ int xe_device_probe(struct xe_device *xe)
if (err)
return err;
+ err = xe_soc_remapper_init(xe);
+ if (err)
+ return err;
+
+ err = xe_sysctrl_init(xe);
+ if (err)
+ return err;
+
+ xe_ras_init(xe);
+
/*
* Now that GT is initialized (TTM in particular),
* we can try to init display, and inherit the initial fb.
@@ -1002,10 +1013,6 @@ int xe_device_probe(struct xe_device *xe)
xe_nvm_init(xe);
- err = xe_soc_remapper_init(xe);
- if (err)
- return err;
-
err = xe_heci_gsc_init(xe);
if (err)
return err;
@@ -1044,10 +1051,6 @@ int xe_device_probe(struct xe_device *xe)
if (err)
goto err_unregister_display;
- err = xe_sysctrl_init(xe);
- if (err)
- goto err_unregister_display;
-
err = xe_device_sysfs_init(xe);
if (err)
goto err_unregister_display;
diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
index 2a31b430570e..c6836957dca7 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.c
+++ b/drivers/gpu/drm/xe/xe_hw_error.c
@@ -518,14 +518,6 @@ void xe_hw_error_irq_handler(struct xe_tile *tile, const u32 master_ctl)
}
}
-static int hw_error_info_init(struct xe_device *xe)
-{
- if (xe->info.platform != XE_PVC)
- return 0;
-
- return xe_drm_ras_init(xe);
-}
-
/*
* Process hardware errors during boot
*/
@@ -552,16 +544,11 @@ static void process_hw_errors(struct xe_device *xe)
void xe_hw_error_init(struct xe_device *xe)
{
struct xe_tile *tile = xe_device_get_root_tile(xe);
- int ret;
if (!IS_DGFX(xe) || IS_SRIOV_VF(xe))
return;
INIT_WORK(&tile->csc_hw_error_work, csc_hw_error_work);
- ret = hw_error_info_init(xe);
- if (ret)
- drm_err(&xe->drm, "Failed to initialize XE DRM RAS (%pe)\n", ERR_PTR(ret));
-
process_hw_errors(xe);
}
diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
index 07f6837694e7..7d2945bb819e 100644
--- a/drivers/gpu/drm/xe/xe_ras.c
+++ b/drivers/gpu/drm/xe/xe_ras.c
@@ -4,6 +4,7 @@
*/
#include "xe_device.h"
+#include "xe_drm_ras.h"
#include "xe_pm.h"
#include "xe_printk.h"
#include "xe_ras.h"
@@ -258,3 +259,22 @@ int xe_ras_clear_counter(struct xe_device *xe, enum drm_xe_ras_error_severity se
return ret;
}
+
+/**
+ * xe_ras_init - Initialize Xe RAS
+ * @xe: xe device instance
+ *
+ * Initialize Xe RAS
+ */
+void xe_ras_init(struct xe_device *xe)
+{
+ int ret;
+
+ if (xe->info.platform != XE_PVC)
+ return;
+
+ ret = xe_drm_ras_init(xe);
+ if (ret)
+ drm_err(&xe->drm, "Failed to initialize xe_drm_ras %d\n", ret);
+}
+
diff --git a/drivers/gpu/drm/xe/xe_ras.h b/drivers/gpu/drm/xe/xe_ras.h
index bbb9d42bd128..a06fb67dc882 100644
--- a/drivers/gpu/drm/xe/xe_ras.h
+++ b/drivers/gpu/drm/xe/xe_ras.h
@@ -17,5 +17,6 @@ int xe_ras_get_counter(struct xe_device *xe, enum drm_xe_ras_error_severity seve
u32 error_id, u32 *value);
int xe_ras_clear_counter(struct xe_device *xe, enum drm_xe_ras_error_severity severity,
u32 error_id);
+void xe_ras_init(struct xe_device *xe);
#endif
--
2.47.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v5 6/6] drm/xe/xe_ras: Control xe drm_ras registration with a flag
2026-05-04 6:56 [PATCH v5 0/6] Add get-error-counter and clear-error-counter support for CRI Riana Tauro
` (6 preceding siblings ...)
2026-05-04 6:56 ` [PATCH v5 5/6] drm/xe/xe_ras: Move xe drm_ras registration Riana Tauro
@ 2026-05-04 6:56 ` Riana Tauro
2026-05-04 8:00 ` ✓ Xe.CI.BAT: success for Add get-error-counter and clear-error-counter support for CRI (rev4) Patchwork
8 siblings, 0 replies; 14+ messages in thread
From: Riana Tauro @ 2026-05-04 6:56 UTC (permalink / raw)
To: intel-xe
Cc: riana.tauro, anshuman.gupta, rodrigo.vivi, aravind.iddamsetty,
badal.nilawar, raag.jadav, ravi.kishore.koppuravuri,
mallesh.koujalagi, soham.purkait
Add a flag to control xe drm_ras registration.
Enable this flag for PVC and CRI to support exposing RAS error counters via netlink.
Signed-off-by: Riana Tauro <riana.tauro@intel.com>
---
v2: rename flag to drm_ras
move drm_ras registration to ras_init (Raag)
---
drivers/gpu/drm/xe/xe_device_types.h | 2 ++
drivers/gpu/drm/xe/xe_pci.c | 3 +++
drivers/gpu/drm/xe/xe_pci_types.h | 1 +
drivers/gpu/drm/xe/xe_ras.c | 2 +-
4 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 89437de3001a..4ba3dffddaf3 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -155,6 +155,8 @@ struct xe_device {
u8 has_cached_pt:1;
/** @info.has_device_atomics_on_smem: Supports device atomics on SMEM */
u8 has_device_atomics_on_smem:1;
+ /** @info.has_drm_ras: Device supports drm_ras (Reliability, Availability, Serviceability) */
+ u8 has_drm_ras:1;
/** @info.has_fan_control: Device supports fan control */
u8 has_fan_control:1;
/** @info.has_flat_ccs: Whether flat CCS metadata is used */
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index d55e5af4f4b7..739cebef1200 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -355,6 +355,7 @@ static const __maybe_unused struct xe_device_desc pvc_desc = {
PLATFORM(PVC),
.dma_mask_size = 52,
.has_display = false,
+ .has_drm_ras = true,
.has_gsc_nvm = 1,
.has_heci_gscfi = 1,
.max_gt_per_tile = 1,
@@ -456,6 +457,7 @@ static const struct xe_device_desc cri_desc = {
PLATFORM(CRESCENTISLAND),
.dma_mask_size = 52,
.has_display = false,
+ .has_drm_ras = true,
.has_flat_ccs = false,
.has_gsc_nvm = 1,
.has_i2c = true,
@@ -747,6 +749,7 @@ static int xe_info_init_early(struct xe_device *xe,
xe->info.is_dgfx = desc->is_dgfx;
xe->info.has_cached_pt = desc->has_cached_pt;
+ xe->info.has_drm_ras = desc->has_drm_ras;
xe->info.has_fan_control = desc->has_fan_control;
/* runtime fusing may force flat_ccs to disabled later */
xe->info.has_flat_ccs = desc->has_flat_ccs;
diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
index 5b85e2c24b7b..24d4a3d00517 100644
--- a/drivers/gpu/drm/xe/xe_pci_types.h
+++ b/drivers/gpu/drm/xe/xe_pci_types.h
@@ -40,6 +40,7 @@ struct xe_device_desc {
u8 has_cached_pt:1;
u8 has_display:1;
+ u8 has_drm_ras:1;
u8 has_fan_control:1;
u8 has_flat_ccs:1;
u8 has_gsc_nvm:1;
diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
index 7d2945bb819e..44cea530f110 100644
--- a/drivers/gpu/drm/xe/xe_ras.c
+++ b/drivers/gpu/drm/xe/xe_ras.c
@@ -270,7 +270,7 @@ void xe_ras_init(struct xe_device *xe)
{
int ret;
- if (xe->info.platform != XE_PVC)
+ if (!xe->info.has_drm_ras)
return;
ret = xe_drm_ras_init(xe);
--
2.47.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* ✓ Xe.CI.BAT: success for Add get-error-counter and clear-error-counter support for CRI (rev4)
2026-05-04 6:56 [PATCH v5 0/6] Add get-error-counter and clear-error-counter support for CRI Riana Tauro
` (7 preceding siblings ...)
2026-05-04 6:56 ` [PATCH v5 6/6] drm/xe/xe_ras: Control xe drm_ras registration with a flag Riana Tauro
@ 2026-05-04 8:00 ` Patchwork
8 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2026-05-04 8:00 UTC (permalink / raw)
To: Tauro, Riana; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 982 bytes --]
== Series Details ==
Series: Add get-error-counter and clear-error-counter support for CRI (rev4)
URL : https://patchwork.freedesktop.org/series/164393/
State : success
== Summary ==
CI Bug Log - changes from xe-4969-9756f0821b775d39e62f2524aa3f7421f7a9e76c_BAT -> xe-pw-164393v4_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (13 -> 13)
------------------------------
No changes in participating hosts
Changes
-------
No changes found
Build changes
-------------
* Linux: xe-4969-9756f0821b775d39e62f2524aa3f7421f7a9e76c -> xe-pw-164393v4
IGT_8881: aa5853ef5b379b1e4558218c21ef4caeae112184 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-4969-9756f0821b775d39e62f2524aa3f7421f7a9e76c: 9756f0821b775d39e62f2524aa3f7421f7a9e76c
xe-pw-164393v4: 164393v4
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-164393v4/index.html
[-- Attachment #2: Type: text/html, Size: 1530 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v5 5/6] drm/xe/xe_ras: Move xe drm_ras registration
2026-05-04 6:56 ` [PATCH v5 5/6] drm/xe/xe_ras: Move xe drm_ras registration Riana Tauro
@ 2026-05-04 10:53 ` Tauro, Riana
2026-05-04 16:22 ` Raag Jadav
0 siblings, 1 reply; 14+ messages in thread
From: Tauro, Riana @ 2026-05-04 10:53 UTC (permalink / raw)
To: intel-xe
Cc: anshuman.gupta, rodrigo.vivi, aravind.iddamsetty, badal.nilawar,
raag.jadav, ravi.kishore.koppuravuri, mallesh.koujalagi,
soham.purkait, Anoop Vijay, Umesh Nerlige Ramappa
On 5/4/2026 12:26 PM, Riana Tauro wrote:
> Move xe drm_ras registration to RAS initialization flow and keep
> hardware error initialization for processing errors reported
> via irq.
>
> Also reorder soc remapper and system controller initialization to
> early probe as ras init is dependent on both.
>
> Cc: Anoop Vijay <anoop.c.vijay@intel.com>
> Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
> ---
> drivers/gpu/drm/xe/xe_device.c | 19 +++++++++++--------
> drivers/gpu/drm/xe/xe_hw_error.c | 13 -------------
> drivers/gpu/drm/xe/xe_ras.c | 20 ++++++++++++++++++++
> drivers/gpu/drm/xe/xe_ras.h | 1 +
> 4 files changed, 32 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
> index 4b45b617a039..041af7ffc8bb 100644
> --- a/drivers/gpu/drm/xe/xe_device.c
> +++ b/drivers/gpu/drm/xe/xe_device.c
> @@ -62,6 +62,7 @@
> #include "xe_psmi.h"
> #include "xe_pxp.h"
> #include "xe_query.h"
> +#include "xe_ras.h"
> #include "xe_shrinker.h"
> #include "xe_soc_remapper.h"
> #include "xe_survivability_mode.h"
> @@ -962,6 +963,16 @@ int xe_device_probe(struct xe_device *xe)
> if (err)
> return err;
>
> + err = xe_soc_remapper_init(xe);
> + if (err)
> + return err;
> +
> + err = xe_sysctrl_init(xe);
> + if (err)
> + return err;
> +
> + xe_ras_init(xe);
> +
> /*
> * Now that GT is initialized (TTM in particular),
> * we can try to init display, and inherit the initial fb.
> @@ -1002,10 +1013,6 @@ int xe_device_probe(struct xe_device *xe)
>
> xe_nvm_init(xe);
>
> - err = xe_soc_remapper_init(xe);
> - if (err)
> - return err;
> -
> err = xe_heci_gsc_init(xe);
> if (err)
> return err;
> @@ -1044,10 +1051,6 @@ int xe_device_probe(struct xe_device *xe)
> if (err)
> goto err_unregister_display;
>
> - err = xe_sysctrl_init(xe);
> - if (err)
> - goto err_unregister_display;
> -
> err = xe_device_sysfs_init(xe);
> if (err)
> goto err_unregister_display;
> diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
> index 2a31b430570e..c6836957dca7 100644
> --- a/drivers/gpu/drm/xe/xe_hw_error.c
> +++ b/drivers/gpu/drm/xe/xe_hw_error.c
> @@ -518,14 +518,6 @@ void xe_hw_error_irq_handler(struct xe_tile *tile, const u32 master_ctl)
> }
> }
>
> -static int hw_error_info_init(struct xe_device *xe)
> -{
> - if (xe->info.platform != XE_PVC)
> - return 0;
> -
> - return xe_drm_ras_init(xe);
> -}
> -
> /*
> * Process hardware errors during boot
> */
> @@ -552,16 +544,11 @@ static void process_hw_errors(struct xe_device *xe)
> void xe_hw_error_init(struct xe_device *xe)
> {
> struct xe_tile *tile = xe_device_get_root_tile(xe);
> - int ret;
>
> if (!IS_DGFX(xe) || IS_SRIOV_VF(xe))
> return;
>
> INIT_WORK(&tile->csc_hw_error_work, csc_hw_error_work);
>
> - ret = hw_error_info_init(xe);
> - if (ret)
> - drm_err(&xe->drm, "Failed to initialize XE DRM RAS (%pe)\n", ERR_PTR(ret));
> -
> process_hw_errors(xe);
> }
> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> index 07f6837694e7..7d2945bb819e 100644
> --- a/drivers/gpu/drm/xe/xe_ras.c
> +++ b/drivers/gpu/drm/xe/xe_ras.c
> @@ -4,6 +4,7 @@
> */
>
> #include "xe_device.h"
> +#include "xe_drm_ras.h"
> #include "xe_pm.h"
> #include "xe_printk.h"
> #include "xe_ras.h"
> @@ -258,3 +259,22 @@ int xe_ras_clear_counter(struct xe_device *xe, enum drm_xe_ras_error_severity se
>
> return ret;
> }
> +
> +/**
> + * xe_ras_init - Initialize Xe RAS
> + * @xe: xe device instance
> + *
> + * Initialize Xe RAS
> + */
> +void xe_ras_init(struct xe_device *xe)
> +{
> + int ret;
> +
Needs an SRIOV_VF check here. Will add it in next rev
Riana
> + if (xe->info.platform != XE_PVC)
> + return;
> +
> + ret = xe_drm_ras_init(xe);
> + if (ret)
> + drm_err(&xe->drm, "Failed to initialize xe_drm_ras %d\n", ret);
> +}
> +
> diff --git a/drivers/gpu/drm/xe/xe_ras.h b/drivers/gpu/drm/xe/xe_ras.h
> index bbb9d42bd128..a06fb67dc882 100644
> --- a/drivers/gpu/drm/xe/xe_ras.h
> +++ b/drivers/gpu/drm/xe/xe_ras.h
> @@ -17,5 +17,6 @@ int xe_ras_get_counter(struct xe_device *xe, enum drm_xe_ras_error_severity seve
> u32 error_id, u32 *value);
> int xe_ras_clear_counter(struct xe_device *xe, enum drm_xe_ras_error_severity severity,
> u32 error_id);
> +void xe_ras_init(struct xe_device *xe);
>
> #endif
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v5 5/6] drm/xe/xe_ras: Move xe drm_ras registration
2026-05-04 10:53 ` Tauro, Riana
@ 2026-05-04 16:22 ` Raag Jadav
0 siblings, 0 replies; 14+ messages in thread
From: Raag Jadav @ 2026-05-04 16:22 UTC (permalink / raw)
To: Tauro, Riana, michal.wajdeczko
Cc: intel-xe, anshuman.gupta, rodrigo.vivi, aravind.iddamsetty,
badal.nilawar, ravi.kishore.koppuravuri, mallesh.koujalagi,
soham.purkait, Anoop Vijay, Umesh Nerlige Ramappa
+ Michal
On Mon, May 04, 2026 at 04:23:14PM +0530, Tauro, Riana wrote:
> On 5/4/2026 12:26 PM, Riana Tauro wrote:
> > Move xe drm_ras registration to RAS initialization flow and keep
> > hardware error initialization for processing errors reported
> > via irq.
...
> > +void xe_ras_init(struct xe_device *xe)
> > +{
> > + int ret;
> > +
>
> Needs an SRIOV_VF check here. Will add it in next rev
Rather, reuse vf_update_device_info() (which I think also should've been
done for other sysctrl flags).
Raag
> > + if (xe->info.platform != XE_PVC)
> > + return;
> > +
> > + ret = xe_drm_ras_init(xe);
> > + if (ret)
> > + drm_err(&xe->drm, "Failed to initialize xe_drm_ras %d\n", ret);
> > +}
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v5 2/6] drm/xe/xe_ras: Add support to get error counter in CRI
2026-05-04 6:56 ` [PATCH v5 2/6] drm/xe/xe_ras: Add support to get error counter in CRI Riana Tauro
@ 2026-05-06 8:03 ` Mallesh, Koujalagi
2026-05-06 8:59 ` Tauro, Riana
0 siblings, 1 reply; 14+ messages in thread
From: Mallesh, Koujalagi @ 2026-05-06 8:03 UTC (permalink / raw)
To: Riana Tauro
Cc: anshuman.gupta, rodrigo.vivi, aravind.iddamsetty, badal.nilawar,
raag.jadav, ravi.kishore.koppuravuri, soham.purkait, intel-xe
On 04-05-2026 12:26 pm, Riana Tauro wrote:
> Add request/response structures and helper functions to query system
> controller to get error counter value.
>
> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
> ---
> v2: add structures for clear counter
> move commands to sysctrl file
> split functions
> fix commit message (Raag)
>
> v3: fix log message
> squash patches
> change error code for sysctrl error (Raag)
>
> v4: rename function
> remove unecessary macro (Raag)
> add documentation for enum
>
> v5: rebase
> ---
> drivers/gpu/drm/xe/xe_ras.c | 91 +++++++++++++++++++
> drivers/gpu/drm/xe/xe_ras.h | 4 +
> drivers/gpu/drm/xe/xe_ras_types.h | 30 ++++++
> drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h | 2 +
> 4 files changed, 127 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> index 4cb16b419b0c..47a58ce3b3ca 100644
> --- a/drivers/gpu/drm/xe/xe_ras.c
> +++ b/drivers/gpu/drm/xe/xe_ras.c
> @@ -4,11 +4,14 @@
> */
>
> #include "xe_device.h"
> +#include "xe_pm.h"
> #include "xe_printk.h"
> #include "xe_ras.h"
> #include "xe_ras_types.h"
> #include "xe_sysctrl.h"
> #include "xe_sysctrl_event_types.h"
> +#include "xe_sysctrl_mailbox.h"
> +#include "xe_sysctrl_mailbox_types.h"
>
> /* Severity of detected errors */
> enum xe_ras_severity {
> @@ -50,6 +53,23 @@ static const char *const xe_ras_components[] = {
> };
> static_assert(ARRAY_SIZE(xe_ras_components) == XE_RAS_COMP_MAX);
>
> +/* Mapping from drm_xe_ras_error_component to xe_ras_component */
> +static const int drm_to_xe_ras_component[] = {
> + [DRM_XE_RAS_ERR_COMP_CORE_COMPUTE] = XE_RAS_COMP_CORE_COMPUTE,
> + [DRM_XE_RAS_ERR_COMP_SOC_INTERNAL] = XE_RAS_COMP_SOC_INTERNAL,
> + [DRM_XE_RAS_ERR_COMP_DEVICE_MEMORY] = XE_RAS_COMP_DEVICE_MEMORY,
> + [DRM_XE_RAS_ERR_COMP_PCIE] = XE_RAS_COMP_PCIE,
> + [DRM_XE_RAS_ERR_COMP_FABRIC] = XE_RAS_COMP_FABRIC
> +};
> +static_assert(ARRAY_SIZE(drm_to_xe_ras_component) == DRM_XE_RAS_ERR_COMP_MAX);
Inconsistent component ordering like
In UAPI:
CORE_COMPUTE(1)
Internal order:
DEVICE_MEMORY(1)
CORE_COMPUTE(2)
can you please make consistent ordering to easy to maintenance and no
confusion.
Thanks,
-/Mallesh
> +
> +/* Mapping from drm_xe_ras_error_severity to xe_ras_severity */
> +static const int drm_to_xe_ras_severity[] = {
> + [DRM_XE_RAS_ERR_SEV_CORRECTABLE] = XE_RAS_SEV_CORRECTABLE,
> + [DRM_XE_RAS_ERR_SEV_UNCORRECTABLE] = XE_RAS_SEV_UNCORRECTABLE
> +};
> +static_assert(ARRAY_SIZE(drm_to_xe_ras_severity) == DRM_XE_RAS_ERR_SEV_MAX);
> +
> static inline const char *sev_to_str(u8 severity)
> {
> if (severity >= XE_RAS_SEV_MAX)
> @@ -66,6 +86,22 @@ static inline const char *comp_to_str(u8 component)
> return xe_ras_components[component];
> }
>
> +static void prepare_ras_command(struct xe_sysctrl_mailbox_command *command,
> + u32 cmd, void *request, size_t request_len,
> + void *response, size_t response_len)
> +{
> + struct xe_sysctrl_app_msg_hdr header = {0};
> +
> + header.data = FIELD_PREP(APP_HDR_GROUP_ID_MASK, XE_SYSCTRL_GROUP_GFSP) |
> + FIELD_PREP(APP_HDR_COMMAND_MASK, cmd);
> +
> + command->header = header;
> + command->data_in = request;
> + command->data_in_len = request_len;
> + command->data_out = response;
> + command->data_out_len = response_len;
> +}
> +
> void xe_ras_counter_threshold_crossed(struct xe_device *xe,
> struct xe_sysctrl_event_response *response)
> {
> @@ -91,3 +127,58 @@ void xe_ras_counter_threshold_crossed(struct xe_device *xe,
> comp_to_str(component), sev_to_str(severity));
> }
> }
> +
> +static int get_counter(struct xe_device *xe, struct xe_ras_error_class *error_class,
> + u32 *value)
> +{
> + struct xe_ras_get_counter_response response = {0};
> + struct xe_ras_get_counter_request request = {0};
> + struct xe_sysctrl_mailbox_command command = {0};
> + size_t rlen;
> + int ret;
> +
> + request.error_class = *error_class;
> +
> + prepare_ras_command(&command, XE_SYSCTRL_CMD_GET_COUNTER, &request, sizeof(request),
> + &response, sizeof(response));
> +
> + ret = xe_sysctrl_send_command(&xe->sc, &command, &rlen);
> + if (ret) {
> + xe_err(xe, "sysctrl: failed to get counter %d\n", ret);
> + return ret;
> + }
> +
> + if (rlen != sizeof(response)) {
> + xe_err(xe, "sysctrl: unexpected get counter response length %zu (expected %zu)\n",
> + rlen, sizeof(response));
> + return -EIO;
> + }
> +
> + *value = response.counter_value;
> +
> + return 0;
> +}
> +
> +/**
> + * xe_ras_get_counter() - Get error counter value
> + * @xe: xe device instance
> + * @severity: Error severity level to be queried
> + * @error_id: Error component to be queried
> + * @value: Counter value
> + *
> + * This function retrieves the value of a specific error counter based on
> + * the error severity and component.
> + *
> + * Return: 0 on success, negative error code on failure.
> + */
> +int xe_ras_get_counter(struct xe_device *xe, enum drm_xe_ras_error_severity severity,
> + u32 error_id, u32 *value)
> +{
> + struct xe_ras_error_class error_class = {0};
> +
> + error_class.common.severity = drm_to_xe_ras_severity[severity];
> + error_class.common.component = drm_to_xe_ras_component[error_id];
> +
> + guard(xe_pm_runtime)(xe);
> + return get_counter(xe, &error_class, value);
> +}
> diff --git a/drivers/gpu/drm/xe/xe_ras.h b/drivers/gpu/drm/xe/xe_ras.h
> index ea90593b62dc..74582c911b02 100644
> --- a/drivers/gpu/drm/xe/xe_ras.h
> +++ b/drivers/gpu/drm/xe/xe_ras.h
> @@ -6,10 +6,14 @@
> #ifndef _XE_RAS_H_
> #define _XE_RAS_H_
>
> +#include <uapi/drm/xe_drm.h>
> +
> struct xe_device;
> struct xe_sysctrl_event_response;
>
> void xe_ras_counter_threshold_crossed(struct xe_device *xe,
> struct xe_sysctrl_event_response *response);
> +int xe_ras_get_counter(struct xe_device *xe, enum drm_xe_ras_error_severity severity,
> + u32 error_id, u32 *value);
>
> #endif
> diff --git a/drivers/gpu/drm/xe/xe_ras_types.h b/drivers/gpu/drm/xe/xe_ras_types.h
> index 4e63c67f806a..74d85875cd63 100644
> --- a/drivers/gpu/drm/xe/xe_ras_types.h
> +++ b/drivers/gpu/drm/xe/xe_ras_types.h
> @@ -70,4 +70,34 @@ struct xe_ras_threshold_crossed {
> struct xe_ras_error_class counters[XE_RAS_NUM_COUNTERS];
> } __packed;
>
> +/**
> + * struct xe_ras_get_counter_request - Request for get error counter
> + */
> +struct xe_ras_get_counter_request {
> + /** @error_class: Error class counter to be queried */
> + struct xe_ras_error_class error_class;
> + /** @reserved: Reserved for future use */
> + u32 reserved;
> +} __packed;
> +
> +/**
> + * struct xe_ras_get_counter_response - Response for get error counter
> + */
> +struct xe_ras_get_counter_response {
> + /** @error_class: Error class counter that was queried */
> + struct xe_ras_error_class error_class;
> + /** @counter_value: Current counter value */
> + u32 counter_value;
> + /** @timestamp: Timestamp when counter was last updated */
> + u64 timestamp;
> + /** @threshold_value: Threshold value for the counter */
> + u32 threshold_value;
> + /** @counter_status: Status of the counter */
> + u32 counter_status:8;
> + /** @reserved: Reserved for future use */
> + u32 reserved:24;
> + /** @reserved1: Reserved for future use */
> + u32 reserved1[56];
> +} __packed;
> +
> #endif
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
> index 84d7c647e743..b315847cbf64 100644
> --- a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
> +++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
> @@ -22,9 +22,11 @@ enum xe_sysctrl_group {
> /**
> * enum xe_sysctrl_gfsp_cmd - Commands supported by GFSP group
> *
> + * @XE_SYSCTRL_CMD_GET_COUNTER: Get error counter value
> * @XE_SYSCTRL_CMD_GET_PENDING_EVENT: Retrieve pending event
> */
> enum xe_sysctrl_gfsp_cmd {
> + XE_SYSCTRL_CMD_GET_COUNTER = 0x03,
> XE_SYSCTRL_CMD_GET_PENDING_EVENT = 0x07,
> };
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v5 2/6] drm/xe/xe_ras: Add support to get error counter in CRI
2026-05-06 8:03 ` Mallesh, Koujalagi
@ 2026-05-06 8:59 ` Tauro, Riana
0 siblings, 0 replies; 14+ messages in thread
From: Tauro, Riana @ 2026-05-06 8:59 UTC (permalink / raw)
To: Mallesh, Koujalagi
Cc: anshuman.gupta, rodrigo.vivi, aravind.iddamsetty, badal.nilawar,
raag.jadav, ravi.kishore.koppuravuri, soham.purkait, intel-xe
On 5/6/2026 1:33 PM, Mallesh, Koujalagi wrote:
>
> On 04-05-2026 12:26 pm, Riana Tauro wrote:
>> Add request/response structures and helper functions to query system
>> controller to get error counter value.
>>
>> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
>> ---
>> v2: add structures for clear counter
>> move commands to sysctrl file
>> split functions
>> fix commit message (Raag)
>>
>> v3: fix log message
>> squash patches
>> change error code for sysctrl error (Raag)
>>
>> v4: rename function
>> remove unecessary macro (Raag)
>> add documentation for enum
>>
>> v5: rebase
>> ---
>> drivers/gpu/drm/xe/xe_ras.c | 91 +++++++++++++++++++
>> drivers/gpu/drm/xe/xe_ras.h | 4 +
>> drivers/gpu/drm/xe/xe_ras_types.h | 30 ++++++
>> drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h | 2 +
>> 4 files changed, 127 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
>> index 4cb16b419b0c..47a58ce3b3ca 100644
>> --- a/drivers/gpu/drm/xe/xe_ras.c
>> +++ b/drivers/gpu/drm/xe/xe_ras.c
>> @@ -4,11 +4,14 @@
>> */
>> #include "xe_device.h"
>> +#include "xe_pm.h"
>> #include "xe_printk.h"
>> #include "xe_ras.h"
>> #include "xe_ras_types.h"
>> #include "xe_sysctrl.h"
>> #include "xe_sysctrl_event_types.h"
>> +#include "xe_sysctrl_mailbox.h"
>> +#include "xe_sysctrl_mailbox_types.h"
>> /* Severity of detected errors */
>> enum xe_ras_severity {
>> @@ -50,6 +53,23 @@ static const char *const xe_ras_components[] = {
>> };
>> static_assert(ARRAY_SIZE(xe_ras_components) == XE_RAS_COMP_MAX);
>> +/* Mapping from drm_xe_ras_error_component to xe_ras_component */
>> +static const int drm_to_xe_ras_component[] = {
>> + [DRM_XE_RAS_ERR_COMP_CORE_COMPUTE] = XE_RAS_COMP_CORE_COMPUTE,
>> + [DRM_XE_RAS_ERR_COMP_SOC_INTERNAL] = XE_RAS_COMP_SOC_INTERNAL,
>> + [DRM_XE_RAS_ERR_COMP_DEVICE_MEMORY] = XE_RAS_COMP_DEVICE_MEMORY,
>> + [DRM_XE_RAS_ERR_COMP_PCIE] = XE_RAS_COMP_PCIE,
>> + [DRM_XE_RAS_ERR_COMP_FABRIC] = XE_RAS_COMP_FABRIC
>> +};
>> +static_assert(ARRAY_SIZE(drm_to_xe_ras_component) ==
>> DRM_XE_RAS_ERR_COMP_MAX);
>
> Inconsistent component ordering like
>
> In UAPI:
>
> CORE_COMPUTE(1)
>
> Internal order:
>
> DEVICE_MEMORY(1)
> CORE_COMPUTE(2)
>
The ordering here is intentional. Different devices expose the errors
using different mechanisms, PVC uses registers and CRI uses system
controller.
The uapi ordering was introduced when the initial netlink patch was
floated for PVC,
changing uapi will break PVC and changing system controller f/w ordering
is not possible.
That is the reason for having mappings for both.
Thanks
Riana
> can you please make consistent ordering to easy to maintenance and no
> confusion.
>
> Thanks,
>
> -/Mallesh
>
>> +
>> +/* Mapping from drm_xe_ras_error_severity to xe_ras_severity */
>> +static const int drm_to_xe_ras_severity[] = {
>> + [DRM_XE_RAS_ERR_SEV_CORRECTABLE] = XE_RAS_SEV_CORRECTABLE,
>> + [DRM_XE_RAS_ERR_SEV_UNCORRECTABLE] = XE_RAS_SEV_UNCORRECTABLE
>> +};
>> +static_assert(ARRAY_SIZE(drm_to_xe_ras_severity) ==
>> DRM_XE_RAS_ERR_SEV_MAX);
>> +
>> static inline const char *sev_to_str(u8 severity)
>> {
>> if (severity >= XE_RAS_SEV_MAX)
>> @@ -66,6 +86,22 @@ static inline const char *comp_to_str(u8 component)
>> return xe_ras_components[component];
>> }
>> +static void prepare_ras_command(struct xe_sysctrl_mailbox_command
>> *command,
>> + u32 cmd, void *request, size_t request_len,
>> + void *response, size_t response_len)
>> +{
>> + struct xe_sysctrl_app_msg_hdr header = {0};
>> +
>> + header.data = FIELD_PREP(APP_HDR_GROUP_ID_MASK,
>> XE_SYSCTRL_GROUP_GFSP) |
>> + FIELD_PREP(APP_HDR_COMMAND_MASK, cmd);
>> +
>> + command->header = header;
>> + command->data_in = request;
>> + command->data_in_len = request_len;
>> + command->data_out = response;
>> + command->data_out_len = response_len;
>> +}
>> +
>> void xe_ras_counter_threshold_crossed(struct xe_device *xe,
>> struct xe_sysctrl_event_response *response)
>> {
>> @@ -91,3 +127,58 @@ void xe_ras_counter_threshold_crossed(struct
>> xe_device *xe,
>> comp_to_str(component), sev_to_str(severity));
>> }
>> }
>> +
>> +static int get_counter(struct xe_device *xe, struct
>> xe_ras_error_class *error_class,
>> + u32 *value)
>> +{
>> + struct xe_ras_get_counter_response response = {0};
>> + struct xe_ras_get_counter_request request = {0};
>> + struct xe_sysctrl_mailbox_command command = {0};
>> + size_t rlen;
>> + int ret;
>> +
>> + request.error_class = *error_class;
>> +
>> + prepare_ras_command(&command, XE_SYSCTRL_CMD_GET_COUNTER,
>> &request, sizeof(request),
>> + &response, sizeof(response));
>> +
>> + ret = xe_sysctrl_send_command(&xe->sc, &command, &rlen);
>> + if (ret) {
>> + xe_err(xe, "sysctrl: failed to get counter %d\n", ret);
>> + return ret;
>> + }
>> +
>> + if (rlen != sizeof(response)) {
>> + xe_err(xe, "sysctrl: unexpected get counter response length
>> %zu (expected %zu)\n",
>> + rlen, sizeof(response));
>> + return -EIO;
>> + }
>> +
>> + *value = response.counter_value;
>> +
>> + return 0;
>> +}
>> +
>> +/**
>> + * xe_ras_get_counter() - Get error counter value
>> + * @xe: xe device instance
>> + * @severity: Error severity level to be queried
>> + * @error_id: Error component to be queried
>> + * @value: Counter value
>> + *
>> + * This function retrieves the value of a specific error counter
>> based on
>> + * the error severity and component.
>> + *
>> + * Return: 0 on success, negative error code on failure.
>> + */
>> +int xe_ras_get_counter(struct xe_device *xe, enum
>> drm_xe_ras_error_severity severity,
>> + u32 error_id, u32 *value)
>> +{
>> + struct xe_ras_error_class error_class = {0};
>> +
>> + error_class.common.severity = drm_to_xe_ras_severity[severity];
>> + error_class.common.component = drm_to_xe_ras_component[error_id];
>> +
>> + guard(xe_pm_runtime)(xe);
>> + return get_counter(xe, &error_class, value);
>> +}
>> diff --git a/drivers/gpu/drm/xe/xe_ras.h b/drivers/gpu/drm/xe/xe_ras.h
>> index ea90593b62dc..74582c911b02 100644
>> --- a/drivers/gpu/drm/xe/xe_ras.h
>> +++ b/drivers/gpu/drm/xe/xe_ras.h
>> @@ -6,10 +6,14 @@
>> #ifndef _XE_RAS_H_
>> #define _XE_RAS_H_
>> +#include <uapi/drm/xe_drm.h>
>> +
>> struct xe_device;
>> struct xe_sysctrl_event_response;
>> void xe_ras_counter_threshold_crossed(struct xe_device *xe,
>> struct xe_sysctrl_event_response *response);
>> +int xe_ras_get_counter(struct xe_device *xe, enum
>> drm_xe_ras_error_severity severity,
>> + u32 error_id, u32 *value);
>> #endif
>> diff --git a/drivers/gpu/drm/xe/xe_ras_types.h
>> b/drivers/gpu/drm/xe/xe_ras_types.h
>> index 4e63c67f806a..74d85875cd63 100644
>> --- a/drivers/gpu/drm/xe/xe_ras_types.h
>> +++ b/drivers/gpu/drm/xe/xe_ras_types.h
>> @@ -70,4 +70,34 @@ struct xe_ras_threshold_crossed {
>> struct xe_ras_error_class counters[XE_RAS_NUM_COUNTERS];
>> } __packed;
>> +/**
>> + * struct xe_ras_get_counter_request - Request for get error counter
>> + */
>> +struct xe_ras_get_counter_request {
>> + /** @error_class: Error class counter to be queried */
>> + struct xe_ras_error_class error_class;
>> + /** @reserved: Reserved for future use */
>> + u32 reserved;
>> +} __packed;
>> +
>> +/**
>> + * struct xe_ras_get_counter_response - Response for get error counter
>> + */
>> +struct xe_ras_get_counter_response {
>> + /** @error_class: Error class counter that was queried */
>> + struct xe_ras_error_class error_class;
>> + /** @counter_value: Current counter value */
>> + u32 counter_value;
>> + /** @timestamp: Timestamp when counter was last updated */
>> + u64 timestamp;
>> + /** @threshold_value: Threshold value for the counter */
>> + u32 threshold_value;
>> + /** @counter_status: Status of the counter */
>> + u32 counter_status:8;
>> + /** @reserved: Reserved for future use */
>> + u32 reserved:24;
>> + /** @reserved1: Reserved for future use */
>> + u32 reserved1[56];
>> +} __packed;
>> +
>> #endif
>> diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
>> b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
>> index 84d7c647e743..b315847cbf64 100644
>> --- a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
>> +++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
>> @@ -22,9 +22,11 @@ enum xe_sysctrl_group {
>> /**
>> * enum xe_sysctrl_gfsp_cmd - Commands supported by GFSP group
>> *
>> + * @XE_SYSCTRL_CMD_GET_COUNTER: Get error counter value
>> * @XE_SYSCTRL_CMD_GET_PENDING_EVENT: Retrieve pending event
>> */
>> enum xe_sysctrl_gfsp_cmd {
>> + XE_SYSCTRL_CMD_GET_COUNTER = 0x03,
>> XE_SYSCTRL_CMD_GET_PENDING_EVENT = 0x07,
>> };
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2026-05-06 8:59 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-05-04 6:56 [PATCH v5 0/6] Add get-error-counter and clear-error-counter support for CRI Riana Tauro
2026-05-04 6:43 ` ✗ CI.checkpatch: warning for Add get-error-counter and clear-error-counter support for CRI (rev4) Patchwork
2026-05-04 6:45 ` ✓ CI.KUnit: success " Patchwork
2026-05-04 6:56 ` [PATCH v5 1/6] drm/xe/uapi: Add additional error components to xe drm_ras Riana Tauro
2026-05-04 6:56 ` [PATCH v5 2/6] drm/xe/xe_ras: Add support to get error counter in CRI Riana Tauro
2026-05-06 8:03 ` Mallesh, Koujalagi
2026-05-06 8:59 ` Tauro, Riana
2026-05-04 6:56 ` [PATCH v5 3/6] drm/xe/xe_ras: Add helper to clear error counter Riana Tauro
2026-05-04 6:56 ` [PATCH v5 4/6] drm/xe/xe_drm_ras: Wire get-error-counter and clear-error-counter support for CRI Riana Tauro
2026-05-04 6:56 ` [PATCH v5 5/6] drm/xe/xe_ras: Move xe drm_ras registration Riana Tauro
2026-05-04 10:53 ` Tauro, Riana
2026-05-04 16:22 ` Raag Jadav
2026-05-04 6:56 ` [PATCH v5 6/6] drm/xe/xe_ras: Control xe drm_ras registration with a flag Riana Tauro
2026-05-04 8:00 ` ✓ Xe.CI.BAT: success for Add get-error-counter and clear-error-counter support for CRI (rev4) Patchwork
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