[PATCH 0/6] Optimize vrr.guardband

[PATCH 0/6] Optimize vrr.guardband

[Ankit Nautiyal]

Instead of setting vrr.guardband to vblank, use optimal guardband that
works for most of the cases. This will help in avoiding need of change
in guardband and fix the LRR feature that needs seamless switching to
a lower refresh rate.

-Patch [1-2] are squashed from series [1] and [2] and are not meant for
 review.
-Patch [3-6] are patches to check the guardband for prefill+PSR+SDP
 latencies and to use a static optimized guardband.

[1] "Preparatory patches for guardband optimization"
https://patchwork.freedesktop.org/series/155661/#rev7

[2] "Introduce helpers for prefill latency calculations"
https://patchwork.freedesktop.org/series/155629/#rev2

Ankit Nautiyal (5):
  [NOT FOR REVIEW] drm/i915/vrr: prep patches for guardband optimization
    squashed
  drm/i915/dp: Add SDP latency computation helper
  drm/i915/psr: Add function to compute max link-wake latency
  drm/i915/display: Add guardband check for feature latencies
  drm/i915/vrr: Use the min static optimized guardband

Ville Syrjälä (1):
  [NOT FOR REVIEW] drm/i915/prefill: Prefill latency calculations series
    squashed

 drivers/gpu/drm/i915/Makefile                |   1 +
 drivers/gpu/drm/i915/display/intel_cdclk.c   |  80 +++++-
 drivers/gpu/drm/i915/display/intel_cdclk.h   |   6 +
 drivers/gpu/drm/i915/display/intel_ddi.c     |   3 +
 drivers/gpu/drm/i915/display/intel_display.c |  82 +++++-
 drivers/gpu/drm/i915/display/intel_dp.c      |  42 +++
 drivers/gpu/drm/i915/display/intel_dp.h      |   4 +
 drivers/gpu/drm/i915/display/intel_psr.c     | 257 +++++++++++++------
 drivers/gpu/drm/i915/display/intel_psr.h     |   3 +
 drivers/gpu/drm/i915/display/intel_vblank.c  |  10 +
 drivers/gpu/drm/i915/display/intel_vblank.h  |   2 +
 drivers/gpu/drm/i915/display/intel_vdsc.c    |   8 +
 drivers/gpu/drm/i915/display/intel_vdsc.h    |   1 +
 drivers/gpu/drm/i915/display/intel_vrr.c     |  90 ++++++-
 drivers/gpu/drm/i915/display/intel_vrr.h     |   2 +-
 drivers/gpu/drm/i915/display/skl_prefill.c   | 157 +++++++++++
 drivers/gpu/drm/i915/display/skl_prefill.h   |  46 ++++
 drivers/gpu/drm/i915/display/skl_scaler.c    | 198 ++++++++++++++
 drivers/gpu/drm/i915/display/skl_scaler.h    |  15 ++
 drivers/gpu/drm/i915/display/skl_watermark.c | 156 +++++------
 drivers/gpu/drm/i915/display/skl_watermark.h |   3 +
 drivers/gpu/drm/xe/Makefile                  |   1 +
 22 files changed, 983 insertions(+), 184 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/skl_prefill.c
 create mode 100644 drivers/gpu/drm/i915/display/skl_prefill.h

-- 
2.45.2

[PATCH 1/6] [NOT FOR REVIEW] drm/i915/vrr: prep patches for guardband optimization squashed

[Ankit Nautiyal]

This is a squashed patch based on the preparatory series for guardband
optimization. It contains all the changes in the v7 of the series:
'Preparatory patches for guardband optimization' [1]

This handles few cases which will need changes when guardband will no
longer be matched to vblank length.
- Fix the vblank_start evaluation.
- Fix PSR wake latency checks wrt to guradband.

NOTE: This patch is not meant for review. Any review related to this
patch should be done on the original series. In order not to diverge
the discussion from the main series.

[1] https://patchwork.freedesktop.org/series/155661/#rev7

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c     |   3 +
 drivers/gpu/drm/i915/display/intel_display.c |  18 +-
 drivers/gpu/drm/i915/display/intel_dp.c      |   9 +
 drivers/gpu/drm/i915/display/intel_dp.h      |   3 +
 drivers/gpu/drm/i915/display/intel_psr.c     | 244 +++++++++++++------
 drivers/gpu/drm/i915/display/intel_psr.h     |   2 +
 drivers/gpu/drm/i915/display/intel_vblank.c  |  10 +
 drivers/gpu/drm/i915/display/intel_vblank.h  |   2 +
 drivers/gpu/drm/i915/display/intel_vrr.c     |  29 ++-
 drivers/gpu/drm/i915/display/intel_vrr.h     |   2 +-
 drivers/gpu/drm/i915/display/skl_watermark.c |   3 +-
 11 files changed, 236 insertions(+), 89 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index c09aa759f4d4..94c593bbedf4 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4560,6 +4560,9 @@ static int intel_ddi_compute_config_late(struct intel_encoder *encoder,
 	struct drm_connector *connector = conn_state->connector;
 	u8 port_sync_transcoders = 0;
 
+	if (intel_crtc_has_dp_encoder(crtc_state))
+		intel_dp_compute_config_late(encoder, crtc_state, conn_state);
+
 	drm_dbg_kms(display->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n",
 		    encoder->base.base.id, encoder->base.name,
 		    crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d5b2612d4ec2..65a7da694ef6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2410,11 +2410,11 @@ static int intel_crtc_compute_config(struct intel_atomic_state *state,
 		intel_atomic_get_new_crtc_state(state, crtc);
 	int ret;
 
-	ret = intel_crtc_compute_set_context_latency(state, crtc);
+	ret = intel_dpll_crtc_compute_clock(state, crtc);
 	if (ret)
 		return ret;
 
-	ret = intel_dpll_crtc_compute_clock(state, crtc);
+	ret = intel_crtc_compute_set_context_latency(state, crtc);
 	if (ret)
 		return ret;
 
@@ -2431,6 +2431,8 @@ static int intel_crtc_compute_config(struct intel_atomic_state *state,
 	if (crtc_state->has_pch_encoder)
 		return ilk_fdi_compute_config(crtc, crtc_state);
 
+	intel_vrr_compute_guardband(crtc_state);
+
 	return 0;
 }
 
@@ -4722,8 +4724,6 @@ intel_modeset_pipe_config_late(struct intel_atomic_state *state,
 	struct drm_connector *connector;
 	int i;
 
-	intel_vrr_compute_config_late(crtc_state);
-
 	for_each_new_connector_in_state(&state->base, connector,
 					conn_state, i) {
 		struct intel_encoder *encoder =
@@ -4958,9 +4958,15 @@ static bool allow_vblank_delay_fastset(const struct intel_crtc_state *old_crtc_s
 	 * Allow fastboot to fix up vblank delay (handled via LRR
 	 * codepaths), a bit dodgy as the registers aren't
 	 * double buffered but seems to be working more or less...
+	 *
+	 * Also allow this when the VRR timing generator is always on,
+	 * and optimized guardband is used. In such cases,
+	 * vblank delay may vary even without inherited state, but it's
+	 * still safe as VRR guardband is still same.
 	 */
-	return HAS_LRR(display) && old_crtc_state->inherited &&
-		!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI);
+	return HAS_LRR(display) &&
+	       (old_crtc_state->inherited || intel_vrr_always_use_vrr_tg(display)) &&
+	       !intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI);
 }
 
 bool
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index a723e846321f..e481ff4c4959 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6979,3 +6979,12 @@ void intel_dp_mst_resume(struct intel_display *display)
 		}
 	}
 }
+
+void intel_dp_compute_config_late(struct intel_encoder *encoder,
+				  struct intel_crtc_state *crtc_state,
+				  struct drm_connector_state *conn_state)
+{
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+	intel_psr_compute_config_late(intel_dp, crtc_state);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index b379443e0211..0d9573ca44cb 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -218,5 +218,8 @@ int intel_dp_compute_min_hblank(struct intel_crtc_state *crtc_state,
 int intel_dp_dsc_bpp_step_x16(const struct intel_connector *connector);
 void intel_dp_dpcd_set_probe(struct intel_dp *intel_dp, bool force_on_external);
 bool intel_dp_in_hdr_mode(const struct drm_connector_state *conn_state);
+void intel_dp_compute_config_late(struct intel_encoder *encoder,
+				  struct intel_crtc_state *crtc_state,
+				  struct drm_connector_state *conn_state);
 
 #endif /* __INTEL_DP_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 2131473cead6..703e5f6af04c 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1361,14 +1361,78 @@ static int intel_psr_entry_setup_frames(struct intel_dp *intel_dp,
 	return entry_setup_frames;
 }
 
+static
+int _intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state,
+				       bool needs_panel_replay,
+				       bool needs_sel_update)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	if (!crtc_state->has_psr)
+		return 0;
+
+	/* Wa_14015401596 */
+	if (intel_vrr_possible(crtc_state) && IS_DISPLAY_VER(display, 13, 14))
+		return 1;
+
+	/* Rest is for SRD_STATUS needed on LunarLake and onwards */
+	if (DISPLAY_VER(display) < 20)
+		return 0;
+
+	/*
+	 * Comment on SRD_STATUS register in Bspec for LunarLake and onwards:
+	 *
+	 * To deterministically capture the transition of the state machine
+	 * going from SRDOFFACK to IDLE, the delayed V. Blank should be at least
+	 * one line after the non-delayed V. Blank.
+	 *
+	 * Legacy TG: TRANS_SET_CONTEXT_LATENCY > 0
+	 * VRR TG: TRANS_VRR_CTL[ VRR Guardband ] < (TRANS_VRR_VMAX[ VRR Vmax ]
+	 * - TRANS_VTOTAL[ Vertical Active ])
+	 *
+	 * SRD_STATUS is used only by PSR1 on PantherLake.
+	 * SRD_STATUS is used by PSR1 and Panel Replay DP on LunarLake.
+	 */
+
+	if (DISPLAY_VER(display) >= 30 && (needs_panel_replay ||
+					   needs_sel_update))
+		return 0;
+	else if (DISPLAY_VER(display) < 30 && (needs_sel_update ||
+					       intel_crtc_has_type(crtc_state,
+								   INTEL_OUTPUT_EDP)))
+		return 0;
+	else
+		return 1;
+}
+
+static bool _wake_lines_fit_into_vblank(const struct intel_crtc_state *crtc_state,
+					int vblank,
+					int wake_lines)
+{
+	if (crtc_state->req_psr2_sdp_prior_scanline)
+		vblank -= 1;
+
+	/* Vblank >= PSR2_CTL Block Count Number maximum line count */
+	if (vblank < wake_lines)
+		return false;
+
+	return true;
+}
+
 static bool wake_lines_fit_into_vblank(struct intel_dp *intel_dp,
 				       const struct intel_crtc_state *crtc_state,
-				       bool aux_less)
+				       bool aux_less,
+				       bool needs_panel_replay,
+				       bool needs_sel_update)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 	int vblank = crtc_state->hw.adjusted_mode.crtc_vblank_end -
 		crtc_state->hw.adjusted_mode.crtc_vblank_start;
 	int wake_lines;
+	int scl = _intel_psr_min_set_context_latency(crtc_state,
+						     needs_panel_replay,
+						     needs_sel_update);
+	vblank -= scl;
 
 	if (aux_less)
 		wake_lines = crtc_state->alpm_state.aux_less_wake_lines;
@@ -1378,19 +1442,23 @@ static bool wake_lines_fit_into_vblank(struct intel_dp *intel_dp,
 					       crtc_state->alpm_state.fast_wake_lines) :
 			crtc_state->alpm_state.io_wake_lines;
 
-	if (crtc_state->req_psr2_sdp_prior_scanline)
-		vblank -= 1;
-
-	/* Vblank >= PSR2_CTL Block Count Number maximum line count */
-	if (vblank < wake_lines)
-		return false;
-
-	return true;
+	/*
+	 * Guardband has not been computed yet, so we conservatively check if the
+	 * full vblank duration is sufficient to accommodate wake line requirements
+	 * for PSR features like Panel Replay and Selective Update.
+	 *
+	 * Once the actual guardband is available, a more accurate validation is
+	 * performed in intel_psr_compute_config_late(), and PSR features are
+	 * disabled if wake lines exceed the available guardband.
+	 */
+	return _wake_lines_fit_into_vblank(crtc_state, vblank, wake_lines);
 }
 
 static bool alpm_config_valid(struct intel_dp *intel_dp,
 			      struct intel_crtc_state *crtc_state,
-			      bool aux_less)
+			      bool aux_less,
+			      bool needs_panel_replay,
+			      bool needs_sel_update)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 
@@ -1400,7 +1468,8 @@ static bool alpm_config_valid(struct intel_dp *intel_dp,
 		return false;
 	}
 
-	if (!wake_lines_fit_into_vblank(intel_dp, crtc_state, aux_less)) {
+	if (!wake_lines_fit_into_vblank(intel_dp, crtc_state, aux_less,
+					needs_panel_replay, needs_sel_update)) {
 		drm_dbg_kms(display->drm,
 			    "PSR2/Panel Replay not enabled, too short vblank time\n");
 		return false;
@@ -1492,7 +1561,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 		return false;
 	}
 
-	if (!alpm_config_valid(intel_dp, crtc_state, false))
+	if (!alpm_config_valid(intel_dp, crtc_state, false, false, true))
 		return false;
 
 	if (!crtc_state->enable_psr2_sel_fetch &&
@@ -1643,7 +1712,7 @@ _panel_replay_compute_config(struct intel_dp *intel_dp,
 		return false;
 	}
 
-	if (!alpm_config_valid(intel_dp, crtc_state, true))
+	if (!alpm_config_valid(intel_dp, crtc_state, true, true, false))
 		return false;
 
 	return true;
@@ -1658,15 +1727,40 @@ static bool intel_psr_needs_wa_18037818876(struct intel_dp *intel_dp,
 		!crtc_state->has_sel_update);
 }
 
+static
+void intel_psr_set_non_psr_pipes(struct intel_dp *intel_dp,
+				 struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(intel_dp);
+	struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
+	struct intel_crtc *crtc;
+	u8 active_pipes = 0;
+
+	/* Wa_16025596647 */
+	if (DISPLAY_VER(display) != 20 &&
+	    !IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0))
+		return;
+
+	/* Not needed by Panel Replay  */
+	if (crtc_state->has_panel_replay)
+		return;
+
+	/* We ignore possible secondary PSR/Panel Replay capable eDP */
+	for_each_intel_crtc(display->drm, crtc)
+		active_pipes |= crtc->active ? BIT(crtc->pipe) : 0;
+
+	active_pipes = intel_calc_active_pipes(state, active_pipes);
+
+	crtc_state->active_non_psr_pipes = active_pipes &
+		~BIT(to_intel_crtc(crtc_state->uapi.crtc)->pipe);
+}
+
 void intel_psr_compute_config(struct intel_dp *intel_dp,
 			      struct intel_crtc_state *crtc_state,
 			      struct drm_connector_state *conn_state)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
-	struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
-	struct intel_crtc *crtc;
-	u8 active_pipes = 0;
 
 	if (!psr_global_enabled(intel_dp)) {
 		drm_dbg_kms(display->drm, "PSR disabled by flag\n");
@@ -1707,31 +1801,6 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
 		return;
 
 	crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp, crtc_state);
-
-	/* Wa_18037818876 */
-	if (intel_psr_needs_wa_18037818876(intel_dp, crtc_state)) {
-		crtc_state->has_psr = false;
-		drm_dbg_kms(display->drm,
-			    "PSR disabled to workaround PSR FSM hang issue\n");
-	}
-
-	/* Rest is for Wa_16025596647 */
-	if (DISPLAY_VER(display) != 20 &&
-	    !IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0))
-		return;
-
-	/* Not needed by Panel Replay  */
-	if (crtc_state->has_panel_replay)
-		return;
-
-	/* We ignore possible secondary PSR/Panel Replay capable eDP */
-	for_each_intel_crtc(display->drm, crtc)
-		active_pipes |= crtc->active ? BIT(crtc->pipe) : 0;
-
-	active_pipes = intel_calc_active_pipes(state, active_pipes);
-
-	crtc_state->active_non_psr_pipes = active_pipes &
-		~BIT(to_intel_crtc(crtc_state->uapi.crtc)->pipe);
 }
 
 void intel_psr_get_config(struct intel_encoder *encoder,
@@ -2371,43 +2440,10 @@ void intel_psr_trigger_frame_change_event(struct intel_dsb *dsb,
  */
 int intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_display *display = to_intel_display(crtc_state);
-
-	if (!crtc_state->has_psr)
-		return 0;
-
-	/* Wa_14015401596 */
-	if (intel_vrr_possible(crtc_state) && IS_DISPLAY_VER(display, 13, 14))
-		return 1;
-
-	/* Rest is for SRD_STATUS needed on LunarLake and onwards */
-	if (DISPLAY_VER(display) < 20)
-		return 0;
-
-	/*
-	 * Comment on SRD_STATUS register in Bspec for LunarLake and onwards:
-	 *
-	 * To deterministically capture the transition of the state machine
-	 * going from SRDOFFACK to IDLE, the delayed V. Blank should be at least
-	 * one line after the non-delayed V. Blank.
-	 *
-	 * Legacy TG: TRANS_SET_CONTEXT_LATENCY > 0
-	 * VRR TG: TRANS_VRR_CTL[ VRR Guardband ] < (TRANS_VRR_VMAX[ VRR Vmax ]
-	 * - TRANS_VTOTAL[ Vertical Active ])
-	 *
-	 * SRD_STATUS is used only by PSR1 on PantherLake.
-	 * SRD_STATUS is used by PSR1 and Panel Replay DP on LunarLake.
-	 */
 
-	if (DISPLAY_VER(display) >= 30 && (crtc_state->has_panel_replay ||
-					   crtc_state->has_sel_update))
-		return 0;
-	else if (DISPLAY_VER(display) < 30 && (crtc_state->has_sel_update ||
-					       intel_crtc_has_type(crtc_state,
-								   INTEL_OUTPUT_EDP)))
-		return 0;
-	else
-		return 1;
+	return _intel_psr_min_set_context_latency(crtc_state,
+						  crtc_state->has_panel_replay,
+						  crtc_state->has_sel_update);
 }
 
 static u32 man_trk_ctl_enable_bit_get(struct intel_display *display)
@@ -4326,3 +4362,57 @@ bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
 {
 	return intel_dp_is_edp(intel_dp) && crtc_state->has_panel_replay;
 }
+
+void intel_psr_compute_config_late(struct intel_dp *intel_dp,
+				   struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(intel_dp);
+	int vblank = intel_crtc_vblank_length(crtc_state);
+	int wake_lines;
+
+	if (intel_psr_needs_alpm_aux_less(intel_dp, crtc_state))
+		wake_lines = crtc_state->alpm_state.aux_less_wake_lines;
+	else if (intel_psr_needs_alpm(intel_dp, crtc_state))
+		wake_lines = DISPLAY_VER(display) < 20 ?
+			     psr2_block_count_lines(crtc_state->alpm_state.io_wake_lines,
+						    crtc_state->alpm_state.fast_wake_lines) :
+			     crtc_state->alpm_state.io_wake_lines;
+	else
+		wake_lines = 0;
+
+	/*
+	 * Disable the PSR features if wake lines exceed the available vblank.
+	 * Though SCL is computed based on these PSR features, it is not reset
+	 * even if the PSR features are disabled to avoid changing vblank start
+	 * at this stage.
+	 */
+	if (wake_lines && !_wake_lines_fit_into_vblank(crtc_state, vblank, wake_lines)) {
+		drm_dbg_kms(display->drm,
+			    "Adjusting PSR/PR mode: vblank too short for wake lines = %d\n",
+			    wake_lines);
+
+		if (crtc_state->has_panel_replay) {
+			crtc_state->has_panel_replay = false;
+			/*
+			 * #TODO : Add fall back to PSR/PSR2
+			 * Since panel replay cannot be supported, we can fall back to PSR/PSR2.
+			 * This will require calling compute_config for psr and psr2 with check for
+			 * actual guardband instead of vblank_length.
+			 */
+			crtc_state->has_psr = false;
+		}
+
+		crtc_state->has_sel_update = false;
+		crtc_state->enable_psr2_su_region_et = false;
+		crtc_state->enable_psr2_sel_fetch = false;
+	}
+
+	/* Wa_18037818876 */
+	if (intel_psr_needs_wa_18037818876(intel_dp, crtc_state)) {
+		crtc_state->has_psr = false;
+		drm_dbg_kms(display->drm,
+			    "PSR disabled to workaround PSR FSM hang issue\n");
+	}
+
+	intel_psr_set_non_psr_pipes(intel_dp, crtc_state);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 9147996d6c9e..b17ce312dc37 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -83,5 +83,7 @@ void intel_psr_debugfs_register(struct intel_display *display);
 bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state);
 bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
 				   const struct intel_crtc_state *crtc_state);
+void intel_psr_compute_config_late(struct intel_dp *intel_dp,
+				   struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_PSR_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index 0b7fcc05e64c..2fc0c1c0bb87 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -767,3 +767,13 @@ int intel_vblank_evade(struct intel_vblank_evade_ctx *evade)
 
 	return scanline;
 }
+
+int intel_crtc_vblank_length(const struct intel_crtc_state *crtc_state)
+{
+	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+
+	if (crtc_state->vrr.enable)
+		return crtc_state->vrr.guardband;
+	else
+		return adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vblank_start;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.h b/drivers/gpu/drm/i915/display/intel_vblank.h
index 21fbb08d61d5..98d04cacd65f 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.h
+++ b/drivers/gpu/drm/i915/display/intel_vblank.h
@@ -48,4 +48,6 @@ const struct intel_crtc_state *
 intel_pre_commit_crtc_state(struct intel_atomic_state *state,
 			    struct intel_crtc *crtc);
 
+int intel_crtc_vblank_length(const struct intel_crtc_state *crtc_state);
+
 #endif /* __INTEL_VBLANK_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 190c51be5cbc..1cfcc31bd899 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -394,10 +394,10 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 	if (HAS_AS_SDP(display)) {
 		crtc_state->vrr.vsync_start =
 			(crtc_state->hw.adjusted_mode.crtc_vtotal -
-			 crtc_state->hw.adjusted_mode.vsync_start);
+			 crtc_state->hw.adjusted_mode.crtc_vsync_start);
 		crtc_state->vrr.vsync_end =
 			(crtc_state->hw.adjusted_mode.crtc_vtotal -
-			 crtc_state->hw.adjusted_mode.vsync_end);
+			 crtc_state->hw.adjusted_mode.crtc_vsync_end);
 	}
 }
 
@@ -433,10 +433,11 @@ intel_vrr_max_guardband(struct intel_crtc_state *crtc_state)
 		   intel_vrr_max_vblank_guardband(crtc_state));
 }
 
-void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
+void intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
-	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+	struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
 
 	if (!intel_vrr_possible(crtc_state))
 		return;
@@ -444,6 +445,13 @@ void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
 	crtc_state->vrr.guardband = min(crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay,
 					intel_vrr_max_guardband(crtc_state));
 
+	if (intel_vrr_always_use_vrr_tg(display)) {
+		adjusted_mode->crtc_vblank_start  =
+			adjusted_mode->crtc_vtotal - crtc_state->vrr.guardband;
+		pipe_mode->crtc_vblank_start =
+			adjusted_mode->crtc_vblank_start;
+	}
+
 	if (DISPLAY_VER(display) < 13)
 		crtc_state->vrr.pipeline_full =
 			intel_vrr_guardband_to_pipeline_full(crtc_state,
@@ -821,6 +829,19 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 	 */
 	if (crtc_state->vrr.enable)
 		crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
+
+	/*
+	 * For platforms that always use the VRR timing generator, we overwrite
+	 * crtc_vblank_start with vtotal - guardband to reflect the delayed
+	 * vblank start. This works for both default and optimized guardband values.
+	 * On other platforms, we keep the original value from
+	 * intel_get_transcoder_timings() and apply adjustments only in VRR-specific
+	 * paths as needed.
+	 */
+	if (intel_vrr_always_use_vrr_tg(display))
+		crtc_state->hw.adjusted_mode.crtc_vblank_start =
+			crtc_state->hw.adjusted_mode.crtc_vtotal -
+			crtc_state->vrr.guardband;
 }
 
 int intel_vrr_safe_window_start(const struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index 7317f8730089..bc9044621635 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -21,7 +21,7 @@ bool intel_vrr_possible(const struct intel_crtc_state *crtc_state);
 void intel_vrr_check_modeset(struct intel_atomic_state *state);
 void intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 			      struct drm_connector_state *conn_state);
-void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state);
+void intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state);
 void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
 void intel_vrr_enable(const struct intel_crtc_state *crtc_state);
 void intel_vrr_send_push(struct intel_dsb *dsb,
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 9df9ee137bf9..06e5e6c77d2e 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -28,6 +28,7 @@
 #include "intel_flipq.h"
 #include "intel_pcode.h"
 #include "intel_plane.h"
+#include "intel_vblank.h"
 #include "intel_wm.h"
 #include "skl_universal_plane_regs.h"
 #include "skl_watermark.h"
@@ -2241,7 +2242,7 @@ skl_is_vblank_too_short(const struct intel_crtc_state *crtc_state,
 		scaler_prefill_latency(crtc_state) +
 		dsc_prefill_latency(crtc_state) +
 		wm0_lines >
-		adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vblank_start;
+		intel_crtc_vblank_length(crtc_state);
 }
 
 static int skl_max_wm0_lines(const struct intel_crtc_state *crtc_state)
-- 
2.45.2

[PATCH 2/6] [NOT FOR REVIEW] drm/i915/prefill: Prefill latency calculations series squashed

[Ankit Nautiyal]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

This is a squashed patch based on the series from Ville Syrjälä
to introduce helpers for prefill latency calculations
'drm/i915/prefill: Introduce helpers for prefill latency calculations' [1]

Introduce skl_prefill and various accompanying helpers to do
pipe prefill latency related stuff (vblank/guardband length
checks, and in the future reduced guardband length).

NOTE: This patch is not meant for review. Any review related to this
patch should be done on the original series. In order not to diverge
the discussion from the main series.

[1] http://patchwork.freedesktop.org/series/155629/#rev2

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/Makefile                |   1 +
 drivers/gpu/drm/i915/display/intel_cdclk.c   |  80 +++++++-
 drivers/gpu/drm/i915/display/intel_cdclk.h   |   6 +
 drivers/gpu/drm/i915/display/intel_display.c |   8 +
 drivers/gpu/drm/i915/display/intel_vdsc.c    |   8 +
 drivers/gpu/drm/i915/display/intel_vdsc.h    |   1 +
 drivers/gpu/drm/i915/display/skl_prefill.c   | 157 +++++++++++++++
 drivers/gpu/drm/i915/display/skl_prefill.h   |  46 +++++
 drivers/gpu/drm/i915/display/skl_scaler.c    | 198 +++++++++++++++++++
 drivers/gpu/drm/i915/display/skl_scaler.h    |  15 ++
 drivers/gpu/drm/i915/display/skl_watermark.c | 155 ++++++---------
 drivers/gpu/drm/i915/display/skl_watermark.h |   3 +
 drivers/gpu/drm/xe/Makefile                  |   1 +
 13 files changed, 585 insertions(+), 94 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/skl_prefill.c
 create mode 100644 drivers/gpu/drm/i915/display/skl_prefill.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 6d7800e25e55..aa2f0fd95117 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -302,6 +302,7 @@ i915-y += \
 	display/intel_vblank.o \
 	display/intel_vga.o \
 	display/intel_wm.o \
+	display/skl_prefill.o \
 	display/skl_scaler.o \
 	display/skl_universal_plane.o \
 	display/skl_watermark.o \
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index f2e092f89ddd..bd45b719d4f8 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2806,16 +2806,20 @@ static int intel_cdclk_guardband(struct intel_display *display)
 		return 90;
 }
 
-static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
+static int _intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state, int pixel_rate)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	int ppc = intel_cdclk_ppc(display, crtc_state->double_wide);
 	int guardband = intel_cdclk_guardband(display);
-	int pixel_rate = crtc_state->pixel_rate;
 
 	return DIV_ROUND_UP(pixel_rate * 100, guardband * ppc);
 }
 
+static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
+{
+	return _intel_pixel_rate_to_cdclk(crtc_state, crtc_state->pixel_rate);
+}
+
 static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -4056,3 +4060,75 @@ void intel_cdclk_read_hw(struct intel_display *display)
 	cdclk_state->actual = display->cdclk.hw;
 	cdclk_state->logical = display->cdclk.hw;
 }
+
+static int calc_cdclk(const struct intel_crtc_state *crtc_state, int min_cdclk)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	if (DISPLAY_VER(display) >= 10 || display->platform.broxton) {
+		return bxt_calc_cdclk(display, min_cdclk);
+	} else if (DISPLAY_VER(display) == 9) {
+		int vco;
+
+		vco = display->cdclk.skl_preferred_vco_freq;
+		if (vco == 0)
+			vco = 8100000;
+
+		return skl_calc_cdclk(min_cdclk, vco);
+	} else if (display->platform.broadwell) {
+		return bdw_calc_cdclk(min_cdclk);
+	} else if (display->platform.cherryview || display->platform.valleyview) {
+		return vlv_calc_cdclk(display, min_cdclk);
+	} else {
+		return display->cdclk.max_cdclk_freq;
+	}
+}
+
+static unsigned int _intel_cdclk_prefill_adj(const struct intel_crtc_state *crtc_state,
+					     int clock, int min_cdclk)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	int ppc = intel_cdclk_ppc(display, crtc_state->double_wide);
+	int cdclk = calc_cdclk(crtc_state, min_cdclk);
+
+	return min(0x10000, DIV_ROUND_UP_ULL((u64)clock << 16, ppc * cdclk));
+}
+
+unsigned int intel_cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state)
+{
+	/* FIXME use the actual min_cdclk for the pipe here */
+	return intel_cdclk_prefill_adjustment_worst(crtc_state);
+}
+
+unsigned int intel_cdclk_prefill_adjustment_worst(const struct intel_crtc_state *crtc_state)
+{
+	int clock = crtc_state->hw.pipe_mode.crtc_clock;
+	int min_cdclk;
+
+	/*
+	 * FIXME could perhaps consider a few more of the factors
+	 * that go the per-crtc min_cdclk. Namely anything that
+	 * only changes during full modesets.
+	 *
+	 * FIXME this assumes 1:1 scaling, but the other _worst() stuff
+	 * assumes max downscaling, so the final result will be
+	 * unrealistically bad. Figure out where the actual maximum value
+	 * lies and use that to compute a more realistic worst case
+	 * estimate...
+	 */
+	min_cdclk = _intel_pixel_rate_to_cdclk(crtc_state, clock);
+
+	return _intel_cdclk_prefill_adj(crtc_state, clock, min_cdclk);
+}
+
+int intel_cdclk_min_cdclk_for_prefill(const struct intel_crtc_state *crtc_state,
+				      unsigned int prefill_lines_unadjusted,
+				      unsigned int prefill_lines_available)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
+	int ppc = intel_cdclk_ppc(display, crtc_state->double_wide);
+
+	return DIV_ROUND_UP_ULL(mul_u32_u32(pipe_mode->crtc_clock, prefill_lines_unadjusted),
+				ppc * prefill_lines_available);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index 72963f6f399a..1c1140b53b17 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -70,4 +70,10 @@ bool intel_cdclk_pmdemand_needs_update(struct intel_atomic_state *state);
 void intel_cdclk_force_min_cdclk(struct intel_cdclk_state *cdclk_state, int force_min_cdclk);
 void intel_cdclk_read_hw(struct intel_display *display);
 
+unsigned int intel_cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state);
+unsigned int intel_cdclk_prefill_adjustment_worst(const struct intel_crtc_state *crtc_state);
+int intel_cdclk_min_cdclk_for_prefill(const struct intel_crtc_state *crtc_state,
+				      unsigned int prefill_lines_unadjusted,
+				      unsigned int prefill_lines_available);
+
 #endif /* __INTEL_CDCLK_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 65a7da694ef6..4367ecfab2b3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7978,6 +7978,14 @@ enum drm_mode_status intel_mode_valid(struct drm_device *dev,
 	    mode->vtotal > vtotal_max)
 		return MODE_V_ILLEGAL;
 
+	/*
+	 * WM_LINETIME only goes up to (almost) 64 usec, and also
+	 * knowing that the linetime is always bounded will ease the
+	 * mind during various calculations.
+	 */
+	if (DIV_ROUND_UP(mode->htotal * 1000, mode->clock) > 64)
+		return MODE_H_ILLEGAL;
+
 	return MODE_OK;
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 8e799e225af1..bca747e24a7f 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -1077,3 +1077,11 @@ int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
 
 	return min_cdclk;
 }
+
+unsigned int intel_vdsc_prefill_lines(const struct intel_crtc_state *crtc_state)
+{
+	if (!crtc_state->dsc.compression_enable)
+		return 0;
+
+	return 0x18000; /* 1.5 */
+}
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h
index 9e2812f99dd7..2139391ff881 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
@@ -32,5 +32,6 @@ void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
 void intel_vdsc_state_dump(struct drm_printer *p, int indent,
 			   const struct intel_crtc_state *crtc_state);
 int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state);
+unsigned int intel_vdsc_prefill_lines(const struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_VDSC_H__ */
diff --git a/drivers/gpu/drm/i915/display/skl_prefill.c b/drivers/gpu/drm/i915/display/skl_prefill.c
new file mode 100644
index 000000000000..4707c2e7127a
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/skl_prefill.c
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#include <linux/debugfs.h>
+
+#include <drm/drm_print.h>
+
+#include "intel_cdclk.h"
+#include "intel_display_core.h"
+#include "intel_display_types.h"
+#include "intel_vblank.h"
+#include "intel_vdsc.h"
+#include "skl_prefill.h"
+#include "skl_scaler.h"
+#include "skl_watermark.h"
+
+static unsigned int prefill_usecs_to_lines(const struct intel_crtc_state *crtc_state,
+					   unsigned int usecs)
+{
+	const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
+
+	return DIV_ROUND_UP_ULL(mul_u32_u32(pipe_mode->crtc_clock, usecs << 16),
+				pipe_mode->crtc_htotal * 1000);
+}
+
+static void prefill_init(struct skl_prefill_ctx *ctx,
+			 const struct intel_crtc_state *crtc_state)
+{
+	memset(ctx, 0, sizeof(*ctx));
+
+	ctx->prefill.fixed = crtc_state->framestart_delay << 16;
+
+	/* 20 usec for translation walks/etc. */
+	ctx->prefill.fixed += prefill_usecs_to_lines(crtc_state, 20);
+
+	ctx->prefill.dsc = intel_vdsc_prefill_lines(crtc_state);
+}
+
+static void prefill_init_nocdclk_worst(struct skl_prefill_ctx *ctx,
+				       const struct intel_crtc_state *crtc_state)
+{
+	prefill_init(ctx, crtc_state);
+
+	ctx->prefill.wm0 = skl_wm0_prefill_lines_worst(crtc_state);
+	ctx->prefill.scaler_1st = skl_scaler_1st_prefill_lines_worst(crtc_state);
+	ctx->prefill.scaler_2nd = skl_scaler_2nd_prefill_lines_worst(crtc_state);
+
+	ctx->adj.scaler_1st = skl_scaler_1st_prefill_adjustment_worst(crtc_state);
+	ctx->adj.scaler_2nd = skl_scaler_2nd_prefill_adjustment_worst(crtc_state);
+}
+
+static void prefill_init_nocdclk(struct skl_prefill_ctx *ctx,
+				 const struct intel_crtc_state *crtc_state)
+{
+	prefill_init(ctx, crtc_state);
+
+	ctx->prefill.wm0 = skl_wm0_prefill_lines(crtc_state);
+	ctx->prefill.scaler_1st = skl_scaler_1st_prefill_lines(crtc_state);
+	ctx->prefill.scaler_2nd = skl_scaler_2nd_prefill_lines(crtc_state);
+
+	ctx->adj.scaler_1st = skl_scaler_1st_prefill_adjustment(crtc_state);
+	ctx->adj.scaler_2nd = skl_scaler_2nd_prefill_adjustment(crtc_state);
+}
+
+static unsigned int prefill_adjust(unsigned int value, unsigned int factor)
+{
+	return DIV_ROUND_UP_ULL(mul_u32_u32(value, factor), 0x10000);
+}
+
+static unsigned int prefill_lines_nocdclk(const struct skl_prefill_ctx *ctx)
+{
+	unsigned int prefill = 0;
+
+	prefill += ctx->prefill.dsc;
+	prefill = prefill_adjust(prefill, ctx->adj.scaler_2nd);
+
+	prefill += ctx->prefill.scaler_2nd;
+	prefill = prefill_adjust(prefill, ctx->adj.scaler_1st);
+
+	prefill += ctx->prefill.scaler_1st;
+	prefill += ctx->prefill.wm0;
+
+	return prefill;
+}
+
+static unsigned int prefill_lines_cdclk(const struct skl_prefill_ctx *ctx)
+{
+	return prefill_adjust(prefill_lines_nocdclk(ctx), ctx->adj.cdclk);
+}
+
+static unsigned int prefill_lines_full(const struct skl_prefill_ctx *ctx)
+{
+	return ctx->prefill.fixed + prefill_lines_cdclk(ctx);
+}
+
+void skl_prefill_init_worst(struct skl_prefill_ctx *ctx,
+			    const struct intel_crtc_state *crtc_state)
+{
+	prefill_init_nocdclk_worst(ctx, crtc_state);
+
+	ctx->adj.cdclk = intel_cdclk_prefill_adjustment_worst(crtc_state);
+
+	ctx->prefill.full = prefill_lines_full(ctx);
+}
+
+void skl_prefill_init(struct skl_prefill_ctx *ctx,
+		      const struct intel_crtc_state *crtc_state)
+{
+	prefill_init_nocdclk(ctx, crtc_state);
+
+	ctx->adj.cdclk = intel_cdclk_prefill_adjustment(crtc_state);
+
+	ctx->prefill.full = prefill_lines_full(ctx);
+}
+
+static unsigned int prefill_lines_with_latency(const struct skl_prefill_ctx *ctx,
+					       const struct intel_crtc_state *crtc_state,
+					       unsigned int latency_us)
+{
+	return ctx->prefill.full + prefill_usecs_to_lines(crtc_state, latency_us);
+}
+
+int skl_prefill_min_guardband(const struct skl_prefill_ctx *ctx,
+			      const struct intel_crtc_state *crtc_state,
+			      unsigned int latency_us)
+{
+	unsigned int prefill = prefill_lines_with_latency(ctx, crtc_state, latency_us);
+
+	return DIV_ROUND_UP(prefill, 0x10000);
+}
+
+static unsigned int prefill_guardband(const struct intel_crtc_state *crtc_state)
+{
+	return intel_crtc_vblank_length(crtc_state) << 16;
+}
+
+bool skl_prefill_vblank_too_short(const struct skl_prefill_ctx *ctx,
+				  const struct intel_crtc_state *crtc_state,
+				  unsigned int latency_us)
+{
+	unsigned int guardband = prefill_guardband(crtc_state);
+	unsigned int prefill = prefill_lines_with_latency(ctx, crtc_state, latency_us);
+
+	return guardband < prefill;
+}
+
+int skl_prefill_min_cdclk(const struct skl_prefill_ctx *ctx,
+			  const struct intel_crtc_state *crtc_state)
+{
+	unsigned int prefill_unadjusted = prefill_lines_nocdclk(ctx);
+	unsigned int prefill_available = prefill_guardband(crtc_state) - ctx->prefill.fixed;
+
+	return intel_cdclk_min_cdclk_for_prefill(crtc_state, prefill_unadjusted,
+						 prefill_available);
+}
diff --git a/drivers/gpu/drm/i915/display/skl_prefill.h b/drivers/gpu/drm/i915/display/skl_prefill.h
new file mode 100644
index 000000000000..028ee19b64ce
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/skl_prefill.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef __SKL_PREFILL_H__
+#define __SKL_PREFILL_H__
+
+#include <linux/types.h>
+
+struct intel_crtc_state;
+
+struct skl_prefill_ctx {
+	/* .16 scanlines */
+	struct {
+		unsigned int fixed;
+		unsigned int wm0;
+		unsigned int scaler_1st;
+		unsigned int scaler_2nd;
+		unsigned int dsc;
+		unsigned int full;
+	} prefill;
+
+	/* .16 adjustment factors */
+	struct {
+		unsigned int cdclk;
+		unsigned int scaler_1st;
+		unsigned int scaler_2nd;
+	} adj;
+};
+
+void skl_prefill_init_worst(struct skl_prefill_ctx *ctx,
+			    const struct intel_crtc_state *crtc_state);
+void skl_prefill_init(struct skl_prefill_ctx *ctx,
+		      const struct intel_crtc_state *crtc_state);
+
+bool skl_prefill_vblank_too_short(const struct skl_prefill_ctx *ctx,
+				  const struct intel_crtc_state *crtc_state,
+				  unsigned int latency_us);
+int skl_prefill_min_guardband(const struct skl_prefill_ctx *ctx,
+			      const struct intel_crtc_state *crtc_state,
+			      unsigned int latency_us);
+int skl_prefill_min_cdclk(const struct skl_prefill_ctx *ctx,
+			  const struct intel_crtc_state *crtc_state);
+
+#endif /* __SKL_PREFILL_H__ */
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
index c6cccf170ff1..65f2eb528161 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.c
+++ b/drivers/gpu/drm/i915/display/skl_scaler.c
@@ -968,3 +968,201 @@ void adl_scaler_ecc_unmask(const struct intel_crtc_state *crtc_state)
 			  1);
 	intel_de_write(display, XELPD_DISPLAY_ERR_FATAL_MASK, 0);
 }
+
+static unsigned int skl_scaler_scale(const struct intel_crtc_state *crtc_state, int i)
+{
+	const struct intel_crtc_scaler_state *scaler_state =
+		&crtc_state->scaler_state;
+
+	return DIV_ROUND_UP_ULL(mul_u32_u32(scaler_state->scalers[i].hscale,
+					    scaler_state->scalers[i].vscale),
+				0x10000);
+}
+
+static unsigned int skl_scaler_downscale(const struct intel_crtc_state *crtc_state, int i)
+{
+	return max(0x10000, skl_scaler_scale(crtc_state, i));
+}
+
+static unsigned int skl_plane_scaler_downscale(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	const struct intel_crtc_scaler_state *scaler_state =
+		&crtc_state->scaler_state;
+	unsigned int scale = 0x10000;
+	int i;
+
+	for (i = 0; i < crtc->num_scalers; i++) {
+		/* ignore pfit */
+		if (i == scaler_state->scaler_id)
+			continue;
+
+		if (!scaler_state->scalers[i].in_use)
+			continue;
+
+		scale = max(scale, skl_scaler_downscale(crtc_state, i));
+	}
+
+	return scale;
+}
+
+static unsigned int skl_pipe_scaler_downscale(const struct intel_crtc_state *crtc_state)
+{
+	const struct intel_crtc_scaler_state *scaler_state =
+		&crtc_state->scaler_state;
+
+	if (!crtc_state->pch_pfit.enabled)
+		return 0x10000;
+
+	return skl_scaler_downscale(crtc_state, scaler_state->scaler_id);
+}
+
+unsigned int skl_scaler_1st_prefill_adjustment(const struct intel_crtc_state *crtc_state)
+{
+	const struct intel_crtc_scaler_state *scaler_state =
+		&crtc_state->scaler_state;
+	int num_scalers = hweight32(scaler_state->scaler_users);
+
+	if (num_scalers < 1)
+		return 0x10000;
+
+	if (num_scalers == 1 && crtc_state->pch_pfit.enabled)
+		return skl_pipe_scaler_downscale(crtc_state);
+	else
+		return skl_plane_scaler_downscale(crtc_state);
+}
+
+unsigned int skl_scaler_2nd_prefill_adjustment(const struct intel_crtc_state *crtc_state)
+{
+	const struct intel_crtc_scaler_state *scaler_state =
+		&crtc_state->scaler_state;
+	int num_scalers = hweight32(scaler_state->scaler_users);
+
+	if (num_scalers < 2)
+		return 0x10000;
+
+	return skl_pipe_scaler_downscale(crtc_state);
+}
+
+unsigned int skl_scaler_1st_prefill_lines(const struct intel_crtc_state *crtc_state)
+{
+	const struct intel_crtc_scaler_state *scaler_state =
+		&crtc_state->scaler_state;
+	int num_scalers = hweight32(scaler_state->scaler_users);
+
+	if (num_scalers > 0)
+		return 4 << 16;
+
+	return 0;
+}
+
+unsigned int skl_scaler_2nd_prefill_lines(const struct intel_crtc_state *crtc_state)
+{
+	const struct intel_crtc_scaler_state *scaler_state =
+		&crtc_state->scaler_state;
+	int num_scalers = hweight32(scaler_state->scaler_users);
+
+	if (num_scalers > 1 && crtc_state->pch_pfit.enabled)
+		return 4 << 16;
+
+	return 0;
+}
+
+static unsigned int _skl_scaler_max_scale(const struct intel_crtc_state *crtc_state,
+					  unsigned int max_scale)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	/*
+	 * Downscaling requires increasing cdclk, so max scale
+	 * factor is limited to the max_dotclock/dotclock ratio.
+	 *
+	 * FIXME find out the max downscale factors properly
+	 */
+	return min(max_scale, DIV_ROUND_UP_ULL((u64)display->cdclk.max_dotclk_freq << 16,
+					       crtc_state->hw.pipe_mode.crtc_clock));
+}
+
+unsigned int skl_scaler_max_total_scale(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	unsigned int max_scale;
+
+	if (crtc->num_scalers < 1)
+		return 0x10000;
+
+	/* FIXME find out the max downscale factors properly */
+	max_scale = 9 << 16;
+	if (crtc->num_scalers > 1)
+		max_scale *= 9;
+
+	return _skl_scaler_max_scale(crtc_state, max_scale);
+}
+
+unsigned int skl_scaler_max_hscale(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	unsigned int max_scale;
+
+	if (crtc->num_scalers < 1)
+		return 0x10000;
+
+	/* FIXME find out the max downscale factors properly */
+	max_scale = 3 << 16;
+
+	return _skl_scaler_max_scale(crtc_state, max_scale);
+}
+
+unsigned int skl_scaler_max_scale(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	unsigned int max_scale;
+
+	if (crtc->num_scalers < 1)
+		return 0x10000;
+
+	/* FIXME find out the max downscale factors properly */
+	max_scale = 9 << 16;
+
+	return _skl_scaler_max_scale(crtc_state, max_scale);
+}
+
+unsigned int skl_scaler_1st_prefill_adjustment_worst(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+	if (crtc->num_scalers > 0)
+		return skl_scaler_max_scale(crtc_state);
+	else
+		return 0x10000;
+}
+
+unsigned int skl_scaler_2nd_prefill_adjustment_worst(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+	if (crtc->num_scalers > 1)
+		return skl_scaler_max_scale(crtc_state);
+	else
+		return 0x10000;
+}
+
+unsigned int skl_scaler_1st_prefill_lines_worst(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+	if (crtc->num_scalers > 0)
+		return 4 << 16;
+	else
+		return 0;
+}
+
+unsigned int skl_scaler_2nd_prefill_lines_worst(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+	if (crtc->num_scalers > 1)
+		return 4 << 16;
+	else
+		return 0;
+}
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.h b/drivers/gpu/drm/i915/display/skl_scaler.h
index 12a19016c5f6..5deabca909e6 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.h
+++ b/drivers/gpu/drm/i915/display/skl_scaler.h
@@ -45,4 +45,19 @@ skl_scaler_mode_valid(struct intel_display *display,
 void adl_scaler_ecc_mask(const struct intel_crtc_state *crtc_state);
 
 void adl_scaler_ecc_unmask(const struct intel_crtc_state *crtc_state);
+
+unsigned int skl_scaler_max_total_scale(const struct intel_crtc_state *crtc_state);
+unsigned int skl_scaler_max_scale(const struct intel_crtc_state *crtc_state);
+unsigned int skl_scaler_max_hscale(const struct intel_crtc_state *crtc_state);
+
+unsigned int skl_scaler_1st_prefill_adjustment_worst(const struct intel_crtc_state *crtc_state);
+unsigned int skl_scaler_2nd_prefill_adjustment_worst(const struct intel_crtc_state *crtc_state);
+unsigned int skl_scaler_1st_prefill_lines_worst(const struct intel_crtc_state *crtc_state);
+unsigned int skl_scaler_2nd_prefill_lines_worst(const struct intel_crtc_state *crtc_state);
+
+unsigned int skl_scaler_1st_prefill_adjustment(const struct intel_crtc_state *crtc_state);
+unsigned int skl_scaler_2nd_prefill_adjustment(const struct intel_crtc_state *crtc_state);
+unsigned int skl_scaler_1st_prefill_lines(const struct intel_crtc_state *crtc_state);
+unsigned int skl_scaler_2nd_prefill_lines(const struct intel_crtc_state *crtc_state);
+
 #endif
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 06e5e6c77d2e..256162da9afc 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -30,6 +30,8 @@
 #include "intel_plane.h"
 #include "intel_vblank.h"
 #include "intel_wm.h"
+#include "skl_prefill.h"
+#include "skl_scaler.h"
 #include "skl_universal_plane_regs.h"
 #include "skl_watermark.h"
 #include "skl_watermark_regs.h"
@@ -2146,103 +2148,55 @@ static int icl_build_plane_wm(struct intel_crtc_state *crtc_state,
 	return 0;
 }
 
-static int
-cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state)
+unsigned int skl_wm0_prefill_lines_worst(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
-	struct intel_atomic_state *state =
-		to_intel_atomic_state(crtc_state->uapi.state);
-	const struct intel_cdclk_state *cdclk_state;
-
-	cdclk_state = intel_atomic_get_cdclk_state(state);
-	if (IS_ERR(cdclk_state)) {
-		drm_WARN_ON(display->drm, PTR_ERR(cdclk_state));
-		return 1;
-	}
-
-	return min(1, DIV_ROUND_UP(crtc_state->pixel_rate,
-				   2 * intel_cdclk_logical(cdclk_state)));
-}
-
-static int
-dsc_prefill_latency(const struct intel_crtc_state *crtc_state)
-{
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	const struct intel_crtc_scaler_state *scaler_state =
-					&crtc_state->scaler_state;
-	int linetime = DIV_ROUND_UP(1000 * crtc_state->hw.adjusted_mode.htotal,
-				    crtc_state->hw.adjusted_mode.clock);
-	int num_scaler_users = hweight32(scaler_state->scaler_users);
-	int chroma_downscaling_factor =
-		crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1;
-	u32 dsc_prefill_latency = 0;
-
-	if (!crtc_state->dsc.compression_enable ||
-	    !num_scaler_users ||
-	    num_scaler_users > crtc->num_scalers)
-		return dsc_prefill_latency;
-
-	dsc_prefill_latency = DIV_ROUND_UP(15 * linetime * chroma_downscaling_factor, 10);
-
-	for (int i = 0; i < num_scaler_users; i++) {
-		u64 hscale_k, vscale_k;
-
-		hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[i].hscale, 1000) >> 16);
-		vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[i].vscale, 1000) >> 16);
-		dsc_prefill_latency = DIV_ROUND_UP_ULL(dsc_prefill_latency * hscale_k * vscale_k,
-						       1000000);
-	}
-
-	dsc_prefill_latency *= cdclk_prefill_adjustment(crtc_state);
+	struct intel_plane *plane = to_intel_plane(crtc_state->uapi.crtc->primary);
+	const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
+	int ret, pixel_rate, width, level = 0;
+	const struct drm_format_info *info;
+	struct skl_wm_level wm = {};
+	struct skl_wm_params wp;
+	unsigned int latency;
+	u64 modifier;
+	u32 format;
 
-	return intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, dsc_prefill_latency);
-}
+	/* only expected to be used for VRR guardband calculation */
+	drm_WARN_ON(display->drm, !HAS_VRR(display));
 
-static int
-scaler_prefill_latency(const struct intel_crtc_state *crtc_state)
-{
-	const struct intel_crtc_scaler_state *scaler_state =
-					&crtc_state->scaler_state;
-	int num_scaler_users = hweight32(scaler_state->scaler_users);
-	int scaler_prefill_latency = 0;
-	int linetime = DIV_ROUND_UP(1000 * crtc_state->hw.adjusted_mode.htotal,
-				    crtc_state->hw.adjusted_mode.clock);
+	/* FIXME rather ugly to pick this by hand but maybe no better way? */
+	format = DRM_FORMAT_XBGR16161616F;
+	if (HAS_4TILE(display))
+		modifier = I915_FORMAT_MOD_4_TILED;
+	else
+		modifier = I915_FORMAT_MOD_Y_TILED;
 
-	if (!num_scaler_users)
-		return scaler_prefill_latency;
+	info = drm_get_format_info(display->drm, format, modifier);
 
-	scaler_prefill_latency = 4 * linetime;
+	pixel_rate = DIV_ROUND_UP_ULL(mul_u32_u32(skl_scaler_max_total_scale(crtc_state),
+						  pipe_mode->crtc_clock),
+				      0x10000);
 
-	if (num_scaler_users > 1) {
-		u64 hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].hscale, 1000) >> 16);
-		u64 vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].vscale, 1000) >> 16);
-		int chroma_downscaling_factor =
-			crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1;
-		int latency;
+	/* FIXME limit to max plane width? */
+	width = DIV_ROUND_UP_ULL(mul_u32_u32(skl_scaler_max_hscale(crtc_state),
+					     pipe_mode->crtc_hdisplay),
+				 0x10000);
 
-		latency = DIV_ROUND_UP_ULL((4 * linetime * hscale_k * vscale_k *
-					    chroma_downscaling_factor), 1000000);
-		scaler_prefill_latency += latency;
-	}
+	/* FIXME is 90/270 rotation worse than 0/180? */
+	ret = skl_compute_wm_params(crtc_state, width, info,
+				    modifier, DRM_MODE_ROTATE_0,
+				    pixel_rate, &wp, 0, 1);
+	drm_WARN_ON(display->drm, ret);
 
-	scaler_prefill_latency *= cdclk_prefill_adjustment(crtc_state);
+	latency = skl_wm_latency(display, level, &wp);
 
-	return intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, scaler_prefill_latency);
-}
+	skl_compute_plane_wm(crtc_state, plane, level, latency, &wp, &wm, &wm);
 
-static bool
-skl_is_vblank_too_short(const struct intel_crtc_state *crtc_state,
-			int wm0_lines, int latency)
-{
-	const struct drm_display_mode *adjusted_mode =
-		&crtc_state->hw.adjusted_mode;
+	/* FIXME is this sane? */
+	if (wm.min_ddb_alloc == U16_MAX)
+		wm.lines = skl_wm_max_lines(display);
 
-	return crtc_state->framestart_delay +
-		intel_usecs_to_scanlines(adjusted_mode, latency) +
-		scaler_prefill_latency(crtc_state) +
-		dsc_prefill_latency(crtc_state) +
-		wm0_lines >
-		intel_crtc_vblank_length(crtc_state);
+	return wm.lines << 16;
 }
 
 static int skl_max_wm0_lines(const struct intel_crtc_state *crtc_state)
@@ -2261,15 +2215,21 @@ static int skl_max_wm0_lines(const struct intel_crtc_state *crtc_state)
 	return wm0_lines;
 }
 
+unsigned int skl_wm0_prefill_lines(const struct intel_crtc_state *crtc_state)
+{
+	return skl_max_wm0_lines(crtc_state) << 16;
+}
+
 /*
  * TODO: In case we use PKG_C_LATENCY to allow C-states when the delayed vblank
  * size is too small for the package C exit latency we need to notify PSR about
  * the scenario to apply Wa_16025596647.
  */
 static int skl_max_wm_level_for_vblank(struct intel_crtc_state *crtc_state,
-				       int wm0_lines)
+				       const struct skl_prefill_ctx *ctx)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	int level;
 
 	for (level = display->wm.num_levels - 1; level >= 0; level--) {
@@ -2284,10 +2244,13 @@ static int skl_max_wm_level_for_vblank(struct intel_crtc_state *crtc_state,
 		if (level == 0)
 			latency = 0;
 
-		if (!skl_is_vblank_too_short(crtc_state, wm0_lines, latency))
+		if (!skl_prefill_vblank_too_short(ctx, crtc_state, latency))
 			return level;
 	}
 
+	drm_dbg_kms(display->drm, "[CRTC:%d:%s] Not enough time in vblank for prefill\n",
+		    crtc->base.base.id, crtc->base.name);
+
 	return -EINVAL;
 }
 
@@ -2295,14 +2258,15 @@ static int skl_wm_check_vblank(struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	int wm0_lines, level;
+	struct skl_prefill_ctx ctx;
+	int level;
 
 	if (!crtc_state->hw.active)
 		return 0;
 
-	wm0_lines = skl_max_wm0_lines(crtc_state);
+	skl_prefill_init(&ctx, crtc_state);
 
-	level = skl_max_wm_level_for_vblank(crtc_state, wm0_lines);
+	level = skl_max_wm_level_for_vblank(crtc_state, &ctx);
 	if (level < 0)
 		return level;
 
@@ -2312,6 +2276,13 @@ static int skl_wm_check_vblank(struct intel_crtc_state *crtc_state)
 	 */
 	crtc_state->wm_level_disabled = level < display->wm.num_levels - 1;
 
+	/*
+	 * TODO: assert that we are in fact using the maximum guardband
+	 * if we end up disabling any WM levels here. Otherwise we clearly
+	 * failed in using a realistic worst case prefill estimate when
+	 * determining the guardband size.
+	 */
+
 	for (level++; level < display->wm.num_levels; level++) {
 		enum plane_id plane_id;
 
@@ -2330,8 +2301,8 @@ static int skl_wm_check_vblank(struct intel_crtc_state *crtc_state)
 
 	if (DISPLAY_VER(display) >= 12 &&
 	    display->sagv.block_time_us &&
-	    skl_is_vblank_too_short(crtc_state, wm0_lines,
-				    display->sagv.block_time_us)) {
+	    skl_prefill_vblank_too_short(&ctx, crtc_state,
+					 display->sagv.block_time_us)) {
 		enum plane_id plane_id;
 
 		for_each_plane_id_on_crtc(crtc, plane_id) {
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h
index 62790816f030..6bc2ec9164bf 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.h
+++ b/drivers/gpu/drm/i915/display/skl_watermark.h
@@ -79,5 +79,8 @@ void intel_program_dpkgc_latency(struct intel_atomic_state *state);
 
 bool intel_dbuf_pmdemand_needs_update(struct intel_atomic_state *state);
 
+unsigned int skl_wm0_prefill_lines_worst(const struct intel_crtc_state *crtc_state);
+unsigned int skl_wm0_prefill_lines(const struct intel_crtc_state *crtc_state);
+
 #endif /* __SKL_WATERMARK_H__ */
 
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 84321fad3265..6f5964f1a04d 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -311,6 +311,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
 	i915-display/intel_vga.o \
 	i915-display/intel_vrr.o \
 	i915-display/intel_wm.o \
+	i915-display/skl_prefill.o \
 	i915-display/skl_scaler.o \
 	i915-display/skl_universal_plane.o \
 	i915-display/skl_watermark.o
-- 
2.45.2

[PATCH 3/6] drm/i915/dp: Add SDP latency computation helper

[Ankit Nautiyal]

Add a helper to compute vblank time needed for transmitting specific
DisplayPort SDPs like PPS, GAMUT_METADATA, and VSC_EXT. Latency is
based on line count per packet type and current line time.

This will be used to ensure adequate guardband when features like DSC/HDR
are enabled.

Bspec: 70151
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 33 +++++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dp.h |  1 +
 2 files changed, 34 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index e481ff4c4959..54d31d02ba50 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6988,3 +6988,36 @@ void intel_dp_compute_config_late(struct intel_encoder *encoder,
 
 	intel_psr_compute_config_late(intel_dp, crtc_state);
 }
+
+static
+int intel_dp_get_sdp_latency(u32 type)
+{
+	switch (type) {
+	case DP_SDP_VSC_EXT_VESA:
+	case DP_SDP_VSC_EXT_CEA:
+		return 10;
+	case HDMI_PACKET_TYPE_GAMUT_METADATA:
+		return 8;
+	case DP_SDP_PPS:
+		return 6;
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+int intel_dp_compute_sdp_latency(const struct intel_crtc_state *crtc_state)
+{
+	int sdp_latency = 0;
+
+	if (crtc_state->infoframes.enable &
+	    intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
+		sdp_latency = max(sdp_latency,
+				  intel_dp_get_sdp_latency(HDMI_PACKET_TYPE_GAMUT_METADATA));
+
+	if (crtc_state->dsc.compression_enable)
+		sdp_latency = max(sdp_latency, intel_dp_get_sdp_latency(DP_SDP_PPS));
+
+	return sdp_latency;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 0d9573ca44cb..27089cef86d8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -221,5 +221,6 @@ bool intel_dp_in_hdr_mode(const struct drm_connector_state *conn_state);
 void intel_dp_compute_config_late(struct intel_encoder *encoder,
 				  struct intel_crtc_state *crtc_state,
 				  struct drm_connector_state *conn_state);
+int intel_dp_compute_sdp_latency(const struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_DP_H__ */
-- 
2.45.2

[PATCH 4/6] drm/i915/psr: Add function to compute max link-wake latency

[Ankit Nautiyal]

Introduce a helper to compute the max link wake latency when using
Auxless/Aux wake mechanism for PSR/Panel Replay/LOBF features.

This will be used to compute the minimum guardband so that the link wake
latencies are accounted and these features work smoothly for higher
refresh rate panels.

Bspec: 70151, 71477
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 13 +++++++++++++
 drivers/gpu/drm/i915/display/intel_psr.h |  1 +
 2 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 703e5f6af04c..03695aff1b22 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -4416,3 +4416,16 @@ void intel_psr_compute_config_late(struct intel_dp *intel_dp,
 
 	intel_psr_set_non_psr_pipes(intel_dp, crtc_state);
 }
+
+int intel_psr_max_link_wake_latency(struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	int auxless_wake_lines = crtc_state->alpm_state.aux_less_wake_lines;
+	int wake_lines = DISPLAY_VER(display) < 20 ?
+			 psr2_block_count_lines(crtc_state->alpm_state.io_wake_lines,
+						crtc_state->alpm_state.fast_wake_lines) :
+			 crtc_state->alpm_state.io_wake_lines;
+
+	return max(auxless_wake_lines, wake_lines);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index b17ce312dc37..baec7e8399f7 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -85,5 +85,6 @@ bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
 				   const struct intel_crtc_state *crtc_state);
 void intel_psr_compute_config_late(struct intel_dp *intel_dp,
 				   struct intel_crtc_state *crtc_state);
+int intel_psr_max_link_wake_latency(struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_PSR_H__ */
-- 
2.45.2

[PATCH 5/6] drm/i915/display: Add guardband check for feature latencies

[Ankit Nautiyal]

Add a check during atomic crtc check phase to ensure the programmed
guardband is sufficient to cover latencies introduced by enabled features
such as DSC, PSR/PR, scalers, and DP SDPs.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 56 ++++++++++++++++++++
 1 file changed, 56 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 4367ecfab2b3..4e3f08a8cd9c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -126,6 +126,7 @@
 #include "intel_vga.h"
 #include "intel_vrr.h"
 #include "intel_wm.h"
+#include "skl_prefill.h"
 #include "skl_scaler.h"
 #include "skl_universal_plane.h"
 #include "skl_watermark.h"
@@ -4191,6 +4192,57 @@ static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
 	return 0;
 }
 
+static int intel_crtc_guardband_atomic_check(struct intel_atomic_state *state,
+					     struct intel_crtc *crtc)
+{
+	struct intel_display *display = to_intel_display(crtc);
+	struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
+	const struct drm_display_mode *adjusted_mode =
+		&crtc_state->hw.adjusted_mode;
+	struct skl_prefill_ctx prefill_ctx;
+	int prefill_framestart_delay = 1;
+	int prefill_min_guardband;
+	int prefill_latency_us;
+	int prefill_wm0_lines;
+	int prefill_sagv_us;
+	int psr_latency = 0;
+	int sdp_latency = 0;
+	int min_guardband;
+	int guardband;
+
+	skl_prefill_init(&prefill_ctx, crtc_state);
+	prefill_wm0_lines = skl_wm0_prefill_lines(crtc_state);
+	prefill_sagv_us = display->sagv.block_time_us;
+	prefill_latency_us = prefill_sagv_us +
+			     intel_scanlines_to_usecs(adjusted_mode,
+						      prefill_framestart_delay +
+						      prefill_wm0_lines);
+	prefill_min_guardband =
+		skl_prefill_min_guardband(&prefill_ctx,
+					  crtc_state,
+					  prefill_latency_us);
+
+	if (intel_crtc_has_dp_encoder(crtc_state)) {
+		psr_latency = intel_psr_max_link_wake_latency(crtc_state);
+		sdp_latency = intel_dp_compute_sdp_latency(crtc_state);
+	}
+
+	min_guardband = max(sdp_latency, psr_latency);
+
+	min_guardband = max(min_guardband, prefill_min_guardband);
+
+	guardband = intel_crtc_vblank_length(crtc_state);
+
+	if (guardband < min_guardband) {
+		drm_dbg_kms(display->drm, "actual guardband: %d shorter than min guardband: %d\n",
+			    guardband, min_guardband);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
 static int intel_crtc_atomic_check(struct intel_atomic_state *state,
 				   struct intel_crtc *crtc)
 {
@@ -4253,6 +4305,10 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
 	if (ret)
 		return ret;
 
+	ret = intel_crtc_guardband_atomic_check(state, crtc);
+	if (ret)
+		return ret;
+
 	return 0;
 }
 
-- 
2.45.2

[PATCH 6/6] drm/i915/vrr: Use the min static optimized guardband

[Ankit Nautiyal]

In the current VRR implementation, vrr.vmin and vrr.guardband are set such
that they do not need to change when switching from fixed refresh rate to
variable refresh rate. Specifically, vrr.guardband is always set to match
the vblank length. This approach works for most cases, but not for LRR,
where the guardband would need to change while the VRR timing generator is
still active.

With the VRR TG always active, live updates to guardband are unsafe and not
recommended. To ensure hardware safety, guardband was moved out of the
!fastset block, meaning any change now requires a full modeset.
This breaks seamless LRR switching, which was previously supported.

Since the problem arises from guardband being matched to the vblank length,
solution is to use a minimal, sufficient static value, instead. So we use a
static guardband defined during mode-set that fits within the smallest
expected vblank and remains unchanged in case of features like LRR where
vtotal changes. To compute this minimum guardband we take into account
latencies/delays due to different features as mentioned in the Bspec.

Introduce a helper to compute the minimal sufficient guardband.
On platforms where the VRR timing generator is always ON, we optimize the
guardband regardless of whether the display is operating in fixed or
variable refresh rate mode.
On platforms where the VRR timing generator is not always ON, we optimize
the guardband only when VRR is enabled.

Bspec: 70151
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 61 +++++++++++++++++++++++-
 1 file changed, 59 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 1cfcc31bd899..4d96aad93dba 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -6,12 +6,16 @@
 
 #include <drm/drm_print.h>
 
+#include "intel_crtc.h"
 #include "intel_de.h"
 #include "intel_display_regs.h"
 #include "intel_display_types.h"
 #include "intel_dp.h"
+#include "intel_psr.h"
 #include "intel_vrr.h"
 #include "intel_vrr_regs.h"
+#include "skl_prefill.h"
+#include "skl_watermark.h"
 
 #define FIXED_POINT_PRECISION		100
 #define CMRR_PRECISION_TOLERANCE	10
@@ -433,17 +437,70 @@ intel_vrr_max_guardband(struct intel_crtc_state *crtc_state)
 		   intel_vrr_max_vblank_guardband(crtc_state));
 }
 
+static
+int intel_vrr_compute_optimized_guardband(struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	const struct drm_display_mode *adjusted_mode =
+		&crtc_state->hw.adjusted_mode;
+	struct skl_prefill_ctx prefill_ctx;
+	int prefill_framestart_delay = 1;
+	int prefill_min_guardband;
+	int prefill_latency_us;
+	int prefill_wm0_lines;
+	int prefill_sagv_us;
+	int psr_latency = 0;
+	int sdp_latency = 0;
+	int guardband;
+
+	skl_prefill_init_worst(&prefill_ctx, crtc_state);
+	prefill_wm0_lines = skl_wm0_prefill_lines_worst(crtc_state);
+	prefill_sagv_us = display->sagv.block_time_us;
+
+	prefill_latency_us = prefill_sagv_us +
+			     intel_scanlines_to_usecs(adjusted_mode,
+						      prefill_framestart_delay +
+						      prefill_wm0_lines);
+	prefill_min_guardband =
+		skl_prefill_min_guardband(&prefill_ctx,
+					  crtc_state,
+					  prefill_latency_us);
+
+	if (intel_crtc_has_dp_encoder(crtc_state)) {
+		psr_latency = intel_psr_max_link_wake_latency(crtc_state);
+		sdp_latency = intel_dp_compute_sdp_latency(crtc_state);
+	}
+
+	guardband = max(sdp_latency, psr_latency);
+
+	guardband = max(guardband, prefill_min_guardband);
+
+	return guardband;
+}
+
+static bool intel_vrr_use_optimized_guardband(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	return intel_vrr_always_use_vrr_tg(display) || crtc_state->vrr.enable;
+}
+
 void intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
 	struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
+	int guardband;
 
 	if (!intel_vrr_possible(crtc_state))
 		return;
 
-	crtc_state->vrr.guardband = min(crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay,
-					intel_vrr_max_guardband(crtc_state));
+	if (intel_vrr_use_optimized_guardband(crtc_state))
+		guardband = intel_vrr_compute_optimized_guardband(crtc_state);
+	else
+		guardband = crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay;
+
+	crtc_state->vrr.guardband = min(guardband, intel_vrr_max_guardband(crtc_state));
 
 	if (intel_vrr_always_use_vrr_tg(display)) {
 		adjusted_mode->crtc_vblank_start  =
-- 
2.45.2

Re: [PATCH 5/6] drm/i915/display: Add guardband check for feature latencies

[Ville Syrjälä]

On Wed, Oct 15, 2025 at 03:52:40PM +0530, Ankit Nautiyal wrote:
> Add a check during atomic crtc check phase to ensure the programmed
> guardband is sufficient to cover latencies introduced by enabled features
> such as DSC, PSR/PR, scalers, and DP SDPs.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 56 ++++++++++++++++++++
>  1 file changed, 56 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 4367ecfab2b3..4e3f08a8cd9c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -126,6 +126,7 @@
>  #include "intel_vga.h"
>  #include "intel_vrr.h"
>  #include "intel_wm.h"
> +#include "skl_prefill.h"
>  #include "skl_scaler.h"
>  #include "skl_universal_plane.h"
>  #include "skl_watermark.h"
> @@ -4191,6 +4192,57 @@ static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
>  	return 0;
>  }
>  
> +static int intel_crtc_guardband_atomic_check(struct intel_atomic_state *state,
> +					     struct intel_crtc *crtc)

Not sure why you're adding this. We already have the
compute_guardband().

> +{
> +	struct intel_display *display = to_intel_display(crtc);
> +	struct intel_crtc_state *crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
> +	const struct drm_display_mode *adjusted_mode =
> +		&crtc_state->hw.adjusted_mode;
> +	struct skl_prefill_ctx prefill_ctx;
> +	int prefill_framestart_delay = 1;
> +	int prefill_min_guardband;
> +	int prefill_latency_us;
> +	int prefill_wm0_lines;
> +	int prefill_sagv_us;
> +	int psr_latency = 0;
> +	int sdp_latency = 0;
> +	int min_guardband;
> +	int guardband;
> +
> +	skl_prefill_init(&prefill_ctx, crtc_state);
> +	prefill_wm0_lines = skl_wm0_prefill_lines(crtc_state);
> +	prefill_sagv_us = display->sagv.block_time_us;
> +	prefill_latency_us = prefill_sagv_us +
> +			     intel_scanlines_to_usecs(adjusted_mode,
> +						      prefill_framestart_delay +
> +						      prefill_wm0_lines);

All of that should pretty much just be skl_prefill_init_worst()

> +	prefill_min_guardband =
> +		skl_prefill_min_guardband(&prefill_ctx,
> +					  crtc_state,
> +					  prefill_latency_us);

The only question really is what use as the latency here.
I think we want it to be:
 max(sagv_block_time, skl_watermark_max_latency(1))
which should guarantee that we get the max power savings.

> +
> +	if (intel_crtc_has_dp_encoder(crtc_state)) {
> +		psr_latency = intel_psr_max_link_wake_latency(crtc_state);
> +		sdp_latency = intel_dp_compute_sdp_latency(crtc_state);
> +	}
> +
> +	min_guardband = max(sdp_latency, psr_latency);
> +
> +	min_guardband = max(min_guardband, prefill_min_guardband);
> +
> +	guardband = intel_crtc_vblank_length(crtc_state);
> +
> +	if (guardband < min_guardband) {
> +		drm_dbg_kms(display->drm, "actual guardband: %d shorter than min guardband: %d\n",
> +			    guardband, min_guardband);
> +		return -EINVAL;
> +	}

I don't think we want to do any checks here. This whole thing
should just be something like:

guardband = prefill_min_guardband()
guardband = max(guardband, psr_min_guardband())
guardband = max(guardband, sdp_min_guardband())

crtc_state->vrr.guardband = min(guardband, intel_vrr_max_guardband())

And then we need to check the final value against 
sdp_min_guardband() in .compute_config_late() to make sure
we got enough for the SDPs. So quite similar to PSR, except
we just want .compute_config_late() to fail if we don't have
enough for the SDPs.

I think that should be good enough for now. It may force a modeset
if the SDPs change though, so later we might want to think about
using a better worst case estimate here, eg. assume HDR metadata may
get enabled later, which we'd like to do without changing the guardband.

> +
> +	return 0;
> +}
> +
>  static int intel_crtc_atomic_check(struct intel_atomic_state *state,
>  				   struct intel_crtc *crtc)
>  {
> @@ -4253,6 +4305,10 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
>  	if (ret)
>  		return ret;
>  
> +	ret = intel_crtc_guardband_atomic_check(state, crtc);
> +	if (ret)
> +		return ret;
> +
>  	return 0;
>  }
>  
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

✗ CI.checkpatch: warning for Optimize vrr.guardband

[Patchwork]

== Series Details ==

Series: Optimize vrr.guardband
URL   : https://patchwork.freedesktop.org/series/155979/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
fbd08a78c3a3bb17964db2a326514c69c1dca660
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit d3c12cc7e1fb4aa72226d5be2da3f96c2fdcbef8
Author: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Date:   Wed Oct 15 15:52:41 2025 +0530

    drm/i915/vrr: Use the min static optimized guardband
    
    In the current VRR implementation, vrr.vmin and vrr.guardband are set such
    that they do not need to change when switching from fixed refresh rate to
    variable refresh rate. Specifically, vrr.guardband is always set to match
    the vblank length. This approach works for most cases, but not for LRR,
    where the guardband would need to change while the VRR timing generator is
    still active.
    
    With the VRR TG always active, live updates to guardband are unsafe and not
    recommended. To ensure hardware safety, guardband was moved out of the
    !fastset block, meaning any change now requires a full modeset.
    This breaks seamless LRR switching, which was previously supported.
    
    Since the problem arises from guardband being matched to the vblank length,
    solution is to use a minimal, sufficient static value, instead. So we use a
    static guardband defined during mode-set that fits within the smallest
    expected vblank and remains unchanged in case of features like LRR where
    vtotal changes. To compute this minimum guardband we take into account
    latencies/delays due to different features as mentioned in the Bspec.
    
    Introduce a helper to compute the minimal sufficient guardband.
    On platforms where the VRR timing generator is always ON, we optimize the
    guardband regardless of whether the display is operating in fixed or
    variable refresh rate mode.
    On platforms where the VRR timing generator is not always ON, we optimize
    the guardband only when VRR is enabled.
    
    Bspec: 70151
    Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
+ /mt/dim checkpatch 69ca30df000b382e7657f300148be505083377f2 drm-intel
a991e98bae14 drm/i915/vrr: prep patches for guardband optimization squashed
44a5d7e8af0f drm/i915/prefill: Prefill latency calculations series squashed
-:204: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#204: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 808 lines checked
ef0af6f6f6ee drm/i915/dp: Add SDP latency computation helper
826fcefc1eaa drm/i915/psr: Add function to compute max link-wake latency
987af8fe93fd drm/i915/display: Add guardband check for feature latencies
d3c12cc7e1fb drm/i915/vrr: Use the min static optimized guardband

✓ CI.KUnit: success for Optimize vrr.guardband

[Patchwork]

== Series Details ==

Series: Optimize vrr.guardband
URL   : https://patchwork.freedesktop.org/series/155979/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[17:00:44] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:00:48] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[17:01:18] Starting KUnit Kernel (1/1)...
[17:01:18] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:01:19] ================== guc_buf (11 subtests) ===================
[17:01:19] [PASSED] test_smallest
[17:01:19] [PASSED] test_largest
[17:01:19] [PASSED] test_granular
[17:01:19] [PASSED] test_unique
[17:01:19] [PASSED] test_overlap
[17:01:19] [PASSED] test_reusable
[17:01:19] [PASSED] test_too_big
[17:01:19] [PASSED] test_flush
[17:01:19] [PASSED] test_lookup
[17:01:19] [PASSED] test_data
[17:01:19] [PASSED] test_class
[17:01:19] ===================== [PASSED] guc_buf =====================
[17:01:19] =================== guc_dbm (7 subtests) ===================
[17:01:19] [PASSED] test_empty
[17:01:19] [PASSED] test_default
[17:01:19] ======================== test_size  ========================
[17:01:19] [PASSED] 4
[17:01:19] [PASSED] 8
[17:01:19] [PASSED] 32
[17:01:19] [PASSED] 256
[17:01:19] ==================== [PASSED] test_size ====================
[17:01:19] ======================= test_reuse  ========================
[17:01:19] [PASSED] 4
[17:01:19] [PASSED] 8
[17:01:19] [PASSED] 32
[17:01:19] [PASSED] 256
[17:01:19] =================== [PASSED] test_reuse ====================
[17:01:19] =================== test_range_overlap  ====================
[17:01:19] [PASSED] 4
[17:01:19] [PASSED] 8
[17:01:19] [PASSED] 32
[17:01:19] [PASSED] 256
[17:01:19] =============== [PASSED] test_range_overlap ================
[17:01:19] =================== test_range_compact  ====================
[17:01:19] [PASSED] 4
[17:01:19] [PASSED] 8
[17:01:19] [PASSED] 32
[17:01:19] [PASSED] 256
[17:01:19] =============== [PASSED] test_range_compact ================
[17:01:19] ==================== test_range_spare  =====================
[17:01:19] [PASSED] 4
[17:01:19] [PASSED] 8
[17:01:19] [PASSED] 32
[17:01:19] [PASSED] 256
[17:01:19] ================ [PASSED] test_range_spare =================
[17:01:19] ===================== [PASSED] guc_dbm =====================
[17:01:19] =================== guc_idm (6 subtests) ===================
[17:01:19] [PASSED] bad_init
[17:01:19] [PASSED] no_init
[17:01:19] [PASSED] init_fini
[17:01:19] [PASSED] check_used
[17:01:19] [PASSED] check_quota
[17:01:19] [PASSED] check_all
[17:01:19] ===================== [PASSED] guc_idm =====================
[17:01:19] ================== no_relay (3 subtests) ===================
[17:01:19] [PASSED] xe_drops_guc2pf_if_not_ready
[17:01:19] [PASSED] xe_drops_guc2vf_if_not_ready
[17:01:19] [PASSED] xe_rejects_send_if_not_ready
[17:01:19] ==================== [PASSED] no_relay =====================
[17:01:19] ================== pf_relay (14 subtests) ==================
[17:01:19] [PASSED] pf_rejects_guc2pf_too_short
[17:01:19] [PASSED] pf_rejects_guc2pf_too_long
[17:01:19] [PASSED] pf_rejects_guc2pf_no_payload
[17:01:19] [PASSED] pf_fails_no_payload
[17:01:19] [PASSED] pf_fails_bad_origin
[17:01:19] [PASSED] pf_fails_bad_type
[17:01:19] [PASSED] pf_txn_reports_error
[17:01:19] [PASSED] pf_txn_sends_pf2guc
[17:01:19] [PASSED] pf_sends_pf2guc
[17:01:19] [SKIPPED] pf_loopback_nop
[17:01:19] [SKIPPED] pf_loopback_echo
[17:01:19] [SKIPPED] pf_loopback_fail
[17:01:19] [SKIPPED] pf_loopback_busy
[17:01:19] [SKIPPED] pf_loopback_retry
[17:01:19] ==================== [PASSED] pf_relay =====================
[17:01:19] ================== vf_relay (3 subtests) ===================
[17:01:19] [PASSED] vf_rejects_guc2vf_too_short
[17:01:19] [PASSED] vf_rejects_guc2vf_too_long
[17:01:19] [PASSED] vf_rejects_guc2vf_no_payload
[17:01:19] ==================== [PASSED] vf_relay =====================
[17:01:19] ===================== lmtt (1 subtest) =====================
[17:01:19] ======================== test_ops  =========================
[17:01:19] [PASSED] 2-level
[17:01:19] [PASSED] multi-level
[17:01:19] ==================== [PASSED] test_ops =====================
[17:01:19] ====================== [PASSED] lmtt =======================
[17:01:19] ================= pf_service (11 subtests) =================
[17:01:19] [PASSED] pf_negotiate_any
[17:01:19] [PASSED] pf_negotiate_base_match
[17:01:19] [PASSED] pf_negotiate_base_newer
[17:01:19] [PASSED] pf_negotiate_base_next
[17:01:19] [SKIPPED] pf_negotiate_base_older
[17:01:19] [PASSED] pf_negotiate_base_prev
[17:01:19] [PASSED] pf_negotiate_latest_match
[17:01:19] [PASSED] pf_negotiate_latest_newer
[17:01:19] [PASSED] pf_negotiate_latest_next
[17:01:19] [SKIPPED] pf_negotiate_latest_older
[17:01:19] [SKIPPED] pf_negotiate_latest_prev
[17:01:19] =================== [PASSED] pf_service ====================
[17:01:19] ================= xe_guc_g2g (2 subtests) ==================
[17:01:19] ============== xe_live_guc_g2g_kunit_default  ==============
[17:01:19] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[17:01:19] ============== xe_live_guc_g2g_kunit_allmem  ===============
[17:01:19] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[17:01:19] =================== [SKIPPED] xe_guc_g2g ===================
[17:01:19] =================== xe_mocs (2 subtests) ===================
[17:01:19] ================ xe_live_mocs_kernel_kunit  ================
[17:01:19] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[17:01:19] ================ xe_live_mocs_reset_kunit  =================
[17:01:19] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[17:01:19] ==================== [SKIPPED] xe_mocs =====================
[17:01:19] ================= xe_migrate (2 subtests) ==================
[17:01:19] ================= xe_migrate_sanity_kunit  =================
[17:01:19] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[17:01:19] ================== xe_validate_ccs_kunit  ==================
[17:01:19] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[17:01:19] =================== [SKIPPED] xe_migrate ===================
[17:01:19] ================== xe_dma_buf (1 subtest) ==================
[17:01:19] ==================== xe_dma_buf_kunit  =====================
[17:01:19] ================ [SKIPPED] xe_dma_buf_kunit ================
[17:01:19] =================== [SKIPPED] xe_dma_buf ===================
[17:01:19] ================= xe_bo_shrink (1 subtest) =================
[17:01:19] =================== xe_bo_shrink_kunit  ====================
[17:01:19] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[17:01:19] ================== [SKIPPED] xe_bo_shrink ==================
[17:01:19] ==================== xe_bo (2 subtests) ====================
[17:01:19] ================== xe_ccs_migrate_kunit  ===================
[17:01:19] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[17:01:19] ==================== xe_bo_evict_kunit  ====================
[17:01:19] =============== [SKIPPED] xe_bo_evict_kunit ================
[17:01:19] ===================== [SKIPPED] xe_bo ======================
[17:01:19] ==================== args (11 subtests) ====================
[17:01:19] [PASSED] count_args_test
[17:01:19] [PASSED] call_args_example
[17:01:19] [PASSED] call_args_test
[17:01:19] [PASSED] drop_first_arg_example
[17:01:19] [PASSED] drop_first_arg_test
[17:01:19] [PASSED] first_arg_example
[17:01:19] [PASSED] first_arg_test
[17:01:19] [PASSED] last_arg_example
[17:01:19] [PASSED] last_arg_test
[17:01:19] [PASSED] pick_arg_example
[17:01:19] [PASSED] sep_comma_example
[17:01:19] ====================== [PASSED] args =======================
[17:01:19] =================== xe_pci (3 subtests) ====================
[17:01:19] ==================== check_graphics_ip  ====================
[17:01:19] [PASSED] 12.00 Xe_LP
[17:01:19] [PASSED] 12.10 Xe_LP+
[17:01:19] [PASSED] 12.55 Xe_HPG
[17:01:19] [PASSED] 12.60 Xe_HPC
[17:01:19] [PASSED] 12.70 Xe_LPG
[17:01:19] [PASSED] 12.71 Xe_LPG
[17:01:19] [PASSED] 12.74 Xe_LPG+
[17:01:19] [PASSED] 20.01 Xe2_HPG
[17:01:19] [PASSED] 20.02 Xe2_HPG
[17:01:19] [PASSED] 20.04 Xe2_LPG
[17:01:19] [PASSED] 30.00 Xe3_LPG
[17:01:19] [PASSED] 30.01 Xe3_LPG
[17:01:19] [PASSED] 30.03 Xe3_LPG
[17:01:19] ================ [PASSED] check_graphics_ip ================
[17:01:19] ===================== check_media_ip  ======================
[17:01:19] [PASSED] 12.00 Xe_M
[17:01:19] [PASSED] 12.55 Xe_HPM
[17:01:19] [PASSED] 13.00 Xe_LPM+
[17:01:19] [PASSED] 13.01 Xe2_HPM
[17:01:19] [PASSED] 20.00 Xe2_LPM
[17:01:19] [PASSED] 30.00 Xe3_LPM
[17:01:19] [PASSED] 30.02 Xe3_LPM
[17:01:19] ================= [PASSED] check_media_ip ==================
[17:01:19] ================= check_platform_gt_count  =================
[17:01:19] [PASSED] 0x9A60 (TIGERLAKE)
[17:01:19] [PASSED] 0x9A68 (TIGERLAKE)
[17:01:19] [PASSED] 0x9A70 (TIGERLAKE)
[17:01:19] [PASSED] 0x9A40 (TIGERLAKE)
[17:01:19] [PASSED] 0x9A49 (TIGERLAKE)
[17:01:19] [PASSED] 0x9A59 (TIGERLAKE)
[17:01:19] [PASSED] 0x9A78 (TIGERLAKE)
[17:01:19] [PASSED] 0x9AC0 (TIGERLAKE)
[17:01:19] [PASSED] 0x9AC9 (TIGERLAKE)
[17:01:19] [PASSED] 0x9AD9 (TIGERLAKE)
[17:01:19] [PASSED] 0x9AF8 (TIGERLAKE)
[17:01:19] [PASSED] 0x4C80 (ROCKETLAKE)
[17:01:19] [PASSED] 0x4C8A (ROCKETLAKE)
[17:01:19] [PASSED] 0x4C8B (ROCKETLAKE)
[17:01:19] [PASSED] 0x4C8C (ROCKETLAKE)
[17:01:19] [PASSED] 0x4C90 (ROCKETLAKE)
[17:01:19] [PASSED] 0x4C9A (ROCKETLAKE)
[17:01:19] [PASSED] 0x4680 (ALDERLAKE_S)
[17:01:19] [PASSED] 0x4682 (ALDERLAKE_S)
[17:01:19] [PASSED] 0x4688 (ALDERLAKE_S)
[17:01:19] [PASSED] 0x468A (ALDERLAKE_S)
[17:01:19] [PASSED] 0x468B (ALDERLAKE_S)
[17:01:19] [PASSED] 0x4690 (ALDERLAKE_S)
[17:01:19] [PASSED] 0x4692 (ALDERLAKE_S)
[17:01:19] [PASSED] 0x4693 (ALDERLAKE_S)
[17:01:19] [PASSED] 0x46A0 (ALDERLAKE_P)
[17:01:19] [PASSED] 0x46A1 (ALDERLAKE_P)
[17:01:19] [PASSED] 0x46A2 (ALDERLAKE_P)
[17:01:19] [PASSED] 0x46A3 (ALDERLAKE_P)
[17:01:19] [PASSED] 0x46A6 (ALDERLAKE_P)
[17:01:19] [PASSED] 0x46A8 (ALDERLAKE_P)
[17:01:19] [PASSED] 0x46AA (ALDERLAKE_P)
[17:01:19] [PASSED] 0x462A (ALDERLAKE_P)
[17:01:19] [PASSED] 0x4626 (ALDERLAKE_P)
[17:01:19] [PASSED] 0x4628 (ALDERLAKE_P)
[17:01:19] [PASSED] 0x46B0 (ALDERLAKE_P)
[17:01:19] [PASSED] 0x46B1 (ALDERLAKE_P)
[17:01:19] [PASSED] 0x46B2 (ALDERLAKE_P)
[17:01:19] [PASSED] 0x46B3 (ALDERLAKE_P)
[17:01:19] [PASSED] 0x46C0 (ALDERLAKE_P)
[17:01:19] [PASSED] 0x46C1 (ALDERLAKE_P)
[17:01:19] [PASSED] 0x46C2 (ALDERLAKE_P)
[17:01:19] [PASSED] 0x46C3 (ALDERLAKE_P)
[17:01:19] [PASSED] 0x46D0 (ALDERLAKE_N)
[17:01:19] [PASSED] 0x46D1 (ALDERLAKE_N)
[17:01:19] [PASSED] 0x46D2 (ALDERLAKE_N)
[17:01:19] [PASSED] 0x46D3 (ALDERLAKE_N)
[17:01:19] [PASSED] 0x46D4 (ALDERLAKE_N)
[17:01:19] [PASSED] 0xA721 (ALDERLAKE_P)
[17:01:19] [PASSED] 0xA7A1 (ALDERLAKE_P)
[17:01:19] [PASSED] 0xA7A9 (ALDERLAKE_P)
[17:01:19] [PASSED] 0xA7AC (ALDERLAKE_P)
[17:01:19] [PASSED] 0xA7AD (ALDERLAKE_P)
[17:01:19] [PASSED] 0xA720 (ALDERLAKE_P)
[17:01:19] [PASSED] 0xA7A0 (ALDERLAKE_P)
[17:01:19] [PASSED] 0xA7A8 (ALDERLAKE_P)
[17:01:19] [PASSED] 0xA7AA (ALDERLAKE_P)
[17:01:19] [PASSED] 0xA7AB (ALDERLAKE_P)
[17:01:19] [PASSED] 0xA780 (ALDERLAKE_S)
[17:01:19] [PASSED] 0xA781 (ALDERLAKE_S)
[17:01:19] [PASSED] 0xA782 (ALDERLAKE_S)
[17:01:19] [PASSED] 0xA783 (ALDERLAKE_S)
[17:01:19] [PASSED] 0xA788 (ALDERLAKE_S)
[17:01:19] [PASSED] 0xA789 (ALDERLAKE_S)
[17:01:19] [PASSED] 0xA78A (ALDERLAKE_S)
[17:01:19] [PASSED] 0xA78B (ALDERLAKE_S)
[17:01:19] [PASSED] 0x4905 (DG1)
[17:01:19] [PASSED] 0x4906 (DG1)
[17:01:19] [PASSED] 0x4907 (DG1)
[17:01:19] [PASSED] 0x4908 (DG1)
[17:01:19] [PASSED] 0x4909 (DG1)
[17:01:19] [PASSED] 0x56C0 (DG2)
[17:01:19] [PASSED] 0x56C2 (DG2)
[17:01:19] [PASSED] 0x56C1 (DG2)
[17:01:19] [PASSED] 0x7D51 (METEORLAKE)
[17:01:19] [PASSED] 0x7DD1 (METEORLAKE)
[17:01:19] [PASSED] 0x7D41 (METEORLAKE)
[17:01:19] [PASSED] 0x7D67 (METEORLAKE)
[17:01:19] [PASSED] 0xB640 (METEORLAKE)
[17:01:19] [PASSED] 0x56A0 (DG2)
[17:01:19] [PASSED] 0x56A1 (DG2)
[17:01:19] [PASSED] 0x56A2 (DG2)
[17:01:19] [PASSED] 0x56BE (DG2)
[17:01:19] [PASSED] 0x56BF (DG2)
[17:01:19] [PASSED] 0x5690 (DG2)
[17:01:19] [PASSED] 0x5691 (DG2)
[17:01:19] [PASSED] 0x5692 (DG2)
[17:01:19] [PASSED] 0x56A5 (DG2)
[17:01:19] [PASSED] 0x56A6 (DG2)
[17:01:19] [PASSED] 0x56B0 (DG2)
[17:01:19] [PASSED] 0x56B1 (DG2)
[17:01:19] [PASSED] 0x56BA (DG2)
[17:01:19] [PASSED] 0x56BB (DG2)
[17:01:19] [PASSED] 0x56BC (DG2)
[17:01:19] [PASSED] 0x56BD (DG2)
[17:01:19] [PASSED] 0x5693 (DG2)
[17:01:19] [PASSED] 0x5694 (DG2)
[17:01:19] [PASSED] 0x5695 (DG2)
[17:01:19] [PASSED] 0x56A3 (DG2)
[17:01:19] [PASSED] 0x56A4 (DG2)
[17:01:19] [PASSED] 0x56B2 (DG2)
[17:01:19] [PASSED] 0x56B3 (DG2)
[17:01:19] [PASSED] 0x5696 (DG2)
[17:01:19] [PASSED] 0x5697 (DG2)
[17:01:19] [PASSED] 0xB69 (PVC)
[17:01:19] [PASSED] 0xB6E (PVC)
[17:01:19] [PASSED] 0xBD4 (PVC)
[17:01:19] [PASSED] 0xBD5 (PVC)
[17:01:19] [PASSED] 0xBD6 (PVC)
[17:01:19] [PASSED] 0xBD7 (PVC)
[17:01:19] [PASSED] 0xBD8 (PVC)
[17:01:19] [PASSED] 0xBD9 (PVC)
[17:01:19] [PASSED] 0xBDA (PVC)
[17:01:19] [PASSED] 0xBDB (PVC)
[17:01:19] [PASSED] 0xBE0 (PVC)
[17:01:19] [PASSED] 0xBE1 (PVC)
[17:01:19] [PASSED] 0xBE5 (PVC)
[17:01:19] [PASSED] 0x7D40 (METEORLAKE)
[17:01:19] [PASSED] 0x7D45 (METEORLAKE)
[17:01:19] [PASSED] 0x7D55 (METEORLAKE)
[17:01:19] [PASSED] 0x7D60 (METEORLAKE)
[17:01:19] [PASSED] 0x7DD5 (METEORLAKE)
[17:01:19] [PASSED] 0x6420 (LUNARLAKE)
[17:01:19] [PASSED] 0x64A0 (LUNARLAKE)
[17:01:19] [PASSED] 0x64B0 (LUNARLAKE)
[17:01:19] [PASSED] 0xE202 (BATTLEMAGE)
[17:01:19] [PASSED] 0xE209 (BATTLEMAGE)
[17:01:19] [PASSED] 0xE20B (BATTLEMAGE)
[17:01:19] [PASSED] 0xE20C (BATTLEMAGE)
[17:01:19] [PASSED] 0xE20D (BATTLEMAGE)
[17:01:19] [PASSED] 0xE210 (BATTLEMAGE)
[17:01:19] [PASSED] 0xE211 (BATTLEMAGE)
[17:01:19] [PASSED] 0xE212 (BATTLEMAGE)
[17:01:19] [PASSED] 0xE216 (BATTLEMAGE)
[17:01:19] [PASSED] 0xE220 (BATTLEMAGE)
[17:01:19] [PASSED] 0xE221 (BATTLEMAGE)
[17:01:19] [PASSED] 0xE222 (BATTLEMAGE)
[17:01:19] [PASSED] 0xE223 (BATTLEMAGE)
[17:01:19] [PASSED] 0xB080 (PANTHERLAKE)
[17:01:19] [PASSED] 0xB081 (PANTHERLAKE)
[17:01:19] [PASSED] 0xB082 (PANTHERLAKE)
[17:01:19] [PASSED] 0xB083 (PANTHERLAKE)
[17:01:19] [PASSED] 0xB084 (PANTHERLAKE)
[17:01:19] [PASSED] 0xB085 (PANTHERLAKE)
[17:01:19] [PASSED] 0xB086 (PANTHERLAKE)
[17:01:19] [PASSED] 0xB087 (PANTHERLAKE)
[17:01:19] [PASSED] 0xB08F (PANTHERLAKE)
[17:01:19] [PASSED] 0xB090 (PANTHERLAKE)
[17:01:19] [PASSED] 0xB0A0 (PANTHERLAKE)
[17:01:19] [PASSED] 0xB0B0 (PANTHERLAKE)
[17:01:19] [PASSED] 0xFD80 (PANTHERLAKE)
[17:01:19] [PASSED] 0xFD81 (PANTHERLAKE)
[17:01:19] ============= [PASSED] check_platform_gt_count =============
[17:01:19] ===================== [PASSED] xe_pci ======================
[17:01:19] =================== xe_rtp (2 subtests) ====================
[17:01:19] =============== xe_rtp_process_to_sr_tests  ================
[17:01:19] [PASSED] coalesce-same-reg
[17:01:19] [PASSED] no-match-no-add
[17:01:19] [PASSED] match-or
[17:01:19] [PASSED] match-or-xfail
[17:01:19] [PASSED] no-match-no-add-multiple-rules
[17:01:19] [PASSED] two-regs-two-entries
[17:01:19] [PASSED] clr-one-set-other
[17:01:19] [PASSED] set-field
[17:01:19] [PASSED] conflict-duplicate
[17:01:19] [PASSED] conflict-not-disjoint
[17:01:19] [PASSED] conflict-reg-type
[17:01:19] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[17:01:19] ================== xe_rtp_process_tests  ===================
[17:01:19] [PASSED] active1
[17:01:19] [PASSED] active2
[17:01:19] [PASSED] active-inactive
[17:01:19] [PASSED] inactive-active
[17:01:19] [PASSED] inactive-1st_or_active-inactive
[17:01:19] [PASSED] inactive-2nd_or_active-inactive
[17:01:19] [PASSED] inactive-last_or_active-inactive
[17:01:19] [PASSED] inactive-no_or_active-inactive
[17:01:19] ============== [PASSED] xe_rtp_process_tests ===============
[17:01:19] ===================== [PASSED] xe_rtp ======================
[17:01:19] ==================== xe_wa (1 subtest) =====================
[17:01:19] ======================== xe_wa_gt  =========================
[17:01:19] [PASSED] TIGERLAKE B0
[17:01:19] [PASSED] DG1 A0
[17:01:19] [PASSED] DG1 B0
[17:01:19] [PASSED] ALDERLAKE_S A0
[17:01:19] [PASSED] ALDERLAKE_S B0
stty: 'standard input': Inappropriate ioctl for device
[17:01:19] [PASSED] ALDERLAKE_S C0
[17:01:19] [PASSED] ALDERLAKE_S D0
[17:01:19] [PASSED] ALDERLAKE_P A0
[17:01:19] [PASSED] ALDERLAKE_P B0
[17:01:19] [PASSED] ALDERLAKE_P C0
[17:01:19] [PASSED] ALDERLAKE_S RPLS D0
[17:01:19] [PASSED] ALDERLAKE_P RPLU E0
[17:01:19] [PASSED] DG2 G10 C0
[17:01:19] [PASSED] DG2 G11 B1
[17:01:19] [PASSED] DG2 G12 A1
[17:01:19] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[17:01:19] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[17:01:19] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[17:01:19] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[17:01:19] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[17:01:19] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[17:01:19] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[17:01:19] ==================== [PASSED] xe_wa_gt =====================
[17:01:19] ====================== [PASSED] xe_wa ======================
[17:01:19] ============================================================
[17:01:19] Testing complete. Ran 306 tests: passed: 288, skipped: 18
[17:01:19] Elapsed time: 35.005s total, 4.251s configuring, 30.387s building, 0.336s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[17:01:19] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:01:20] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[17:01:45] Starting KUnit Kernel (1/1)...
[17:01:45] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:01:45] ============ drm_test_pick_cmdline (2 subtests) ============
[17:01:45] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[17:01:45] =============== drm_test_pick_cmdline_named  ===============
[17:01:45] [PASSED] NTSC
[17:01:45] [PASSED] NTSC-J
[17:01:45] [PASSED] PAL
[17:01:45] [PASSED] PAL-M
[17:01:45] =========== [PASSED] drm_test_pick_cmdline_named ===========
[17:01:45] ============== [PASSED] drm_test_pick_cmdline ==============
[17:01:45] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[17:01:45] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[17:01:45] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[17:01:45] =========== drm_validate_clone_mode (2 subtests) ===========
[17:01:45] ============== drm_test_check_in_clone_mode  ===============
[17:01:45] [PASSED] in_clone_mode
[17:01:45] [PASSED] not_in_clone_mode
[17:01:45] ========== [PASSED] drm_test_check_in_clone_mode ===========
[17:01:45] =============== drm_test_check_valid_clones  ===============
[17:01:45] [PASSED] not_in_clone_mode
[17:01:45] [PASSED] valid_clone
[17:01:45] [PASSED] invalid_clone
[17:01:45] =========== [PASSED] drm_test_check_valid_clones ===========
[17:01:45] ============= [PASSED] drm_validate_clone_mode =============
[17:01:45] ============= drm_validate_modeset (1 subtest) =============
[17:01:45] [PASSED] drm_test_check_connector_changed_modeset
[17:01:45] ============== [PASSED] drm_validate_modeset ===============
[17:01:45] ====== drm_test_bridge_get_current_state (2 subtests) ======
[17:01:45] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[17:01:45] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[17:01:45] ======== [PASSED] drm_test_bridge_get_current_state ========
[17:01:45] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[17:01:45] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[17:01:45] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[17:01:45] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[17:01:45] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[17:01:45] ============== drm_bridge_alloc (2 subtests) ===============
[17:01:45] [PASSED] drm_test_drm_bridge_alloc_basic
[17:01:45] [PASSED] drm_test_drm_bridge_alloc_get_put
[17:01:45] ================ [PASSED] drm_bridge_alloc =================
[17:01:45] ================== drm_buddy (8 subtests) ==================
[17:01:45] [PASSED] drm_test_buddy_alloc_limit
[17:01:45] [PASSED] drm_test_buddy_alloc_optimistic
[17:01:45] [PASSED] drm_test_buddy_alloc_pessimistic
[17:01:45] [PASSED] drm_test_buddy_alloc_pathological
[17:01:45] [PASSED] drm_test_buddy_alloc_contiguous
[17:01:45] [PASSED] drm_test_buddy_alloc_clear
[17:01:45] [PASSED] drm_test_buddy_alloc_range_bias
[17:01:46] [PASSED] drm_test_buddy_fragmentation_performance
[17:01:46] ==================== [PASSED] drm_buddy ====================
[17:01:46] ============= drm_cmdline_parser (40 subtests) =============
[17:01:46] [PASSED] drm_test_cmdline_force_d_only
[17:01:46] [PASSED] drm_test_cmdline_force_D_only_dvi
[17:01:46] [PASSED] drm_test_cmdline_force_D_only_hdmi
[17:01:46] [PASSED] drm_test_cmdline_force_D_only_not_digital
[17:01:46] [PASSED] drm_test_cmdline_force_e_only
[17:01:46] [PASSED] drm_test_cmdline_res
[17:01:46] [PASSED] drm_test_cmdline_res_vesa
[17:01:46] [PASSED] drm_test_cmdline_res_vesa_rblank
[17:01:46] [PASSED] drm_test_cmdline_res_rblank
[17:01:46] [PASSED] drm_test_cmdline_res_bpp
[17:01:46] [PASSED] drm_test_cmdline_res_refresh
[17:01:46] [PASSED] drm_test_cmdline_res_bpp_refresh
[17:01:46] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[17:01:46] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[17:01:46] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[17:01:46] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[17:01:46] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[17:01:46] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[17:01:46] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[17:01:46] [PASSED] drm_test_cmdline_res_margins_force_on
[17:01:46] [PASSED] drm_test_cmdline_res_vesa_margins
[17:01:46] [PASSED] drm_test_cmdline_name
[17:01:46] [PASSED] drm_test_cmdline_name_bpp
[17:01:46] [PASSED] drm_test_cmdline_name_option
[17:01:46] [PASSED] drm_test_cmdline_name_bpp_option
[17:01:46] [PASSED] drm_test_cmdline_rotate_0
[17:01:46] [PASSED] drm_test_cmdline_rotate_90
[17:01:46] [PASSED] drm_test_cmdline_rotate_180
[17:01:46] [PASSED] drm_test_cmdline_rotate_270
[17:01:46] [PASSED] drm_test_cmdline_hmirror
[17:01:46] [PASSED] drm_test_cmdline_vmirror
[17:01:46] [PASSED] drm_test_cmdline_margin_options
[17:01:46] [PASSED] drm_test_cmdline_multiple_options
[17:01:46] [PASSED] drm_test_cmdline_bpp_extra_and_option
[17:01:46] [PASSED] drm_test_cmdline_extra_and_option
[17:01:46] [PASSED] drm_test_cmdline_freestanding_options
[17:01:46] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[17:01:46] [PASSED] drm_test_cmdline_panel_orientation
[17:01:46] ================ drm_test_cmdline_invalid  =================
[17:01:46] [PASSED] margin_only
[17:01:46] [PASSED] interlace_only
[17:01:46] [PASSED] res_missing_x
[17:01:46] [PASSED] res_missing_y
[17:01:46] [PASSED] res_bad_y
[17:01:46] [PASSED] res_missing_y_bpp
[17:01:46] [PASSED] res_bad_bpp
[17:01:46] [PASSED] res_bad_refresh
[17:01:46] [PASSED] res_bpp_refresh_force_on_off
[17:01:46] [PASSED] res_invalid_mode
[17:01:46] [PASSED] res_bpp_wrong_place_mode
[17:01:46] [PASSED] name_bpp_refresh
[17:01:46] [PASSED] name_refresh
[17:01:46] [PASSED] name_refresh_wrong_mode
[17:01:46] [PASSED] name_refresh_invalid_mode
[17:01:46] [PASSED] rotate_multiple
[17:01:46] [PASSED] rotate_invalid_val
[17:01:46] [PASSED] rotate_truncated
[17:01:46] [PASSED] invalid_option
[17:01:46] [PASSED] invalid_tv_option
[17:01:46] [PASSED] truncated_tv_option
[17:01:46] ============ [PASSED] drm_test_cmdline_invalid =============
[17:01:46] =============== drm_test_cmdline_tv_options  ===============
[17:01:46] [PASSED] NTSC
[17:01:46] [PASSED] NTSC_443
[17:01:46] [PASSED] NTSC_J
[17:01:46] [PASSED] PAL
[17:01:46] [PASSED] PAL_M
[17:01:46] [PASSED] PAL_N
[17:01:46] [PASSED] SECAM
[17:01:46] [PASSED] MONO_525
[17:01:46] [PASSED] MONO_625
[17:01:46] =========== [PASSED] drm_test_cmdline_tv_options ===========
[17:01:46] =============== [PASSED] drm_cmdline_parser ================
[17:01:46] ========== drmm_connector_hdmi_init (20 subtests) ==========
[17:01:46] [PASSED] drm_test_connector_hdmi_init_valid
[17:01:46] [PASSED] drm_test_connector_hdmi_init_bpc_8
[17:01:46] [PASSED] drm_test_connector_hdmi_init_bpc_10
[17:01:46] [PASSED] drm_test_connector_hdmi_init_bpc_12
[17:01:46] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[17:01:46] [PASSED] drm_test_connector_hdmi_init_bpc_null
[17:01:46] [PASSED] drm_test_connector_hdmi_init_formats_empty
[17:01:46] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[17:01:46] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[17:01:46] [PASSED] supported_formats=0x9 yuv420_allowed=1
[17:01:46] [PASSED] supported_formats=0x9 yuv420_allowed=0
[17:01:46] [PASSED] supported_formats=0x3 yuv420_allowed=1
[17:01:46] [PASSED] supported_formats=0x3 yuv420_allowed=0
[17:01:46] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[17:01:46] [PASSED] drm_test_connector_hdmi_init_null_ddc
[17:01:46] [PASSED] drm_test_connector_hdmi_init_null_product
[17:01:46] [PASSED] drm_test_connector_hdmi_init_null_vendor
[17:01:46] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[17:01:46] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[17:01:46] [PASSED] drm_test_connector_hdmi_init_product_valid
[17:01:46] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[17:01:46] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[17:01:46] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[17:01:46] ========= drm_test_connector_hdmi_init_type_valid  =========
[17:01:46] [PASSED] HDMI-A
[17:01:46] [PASSED] HDMI-B
[17:01:46] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[17:01:46] ======== drm_test_connector_hdmi_init_type_invalid  ========
[17:01:46] [PASSED] Unknown
[17:01:46] [PASSED] VGA
[17:01:46] [PASSED] DVI-I
[17:01:46] [PASSED] DVI-D
[17:01:46] [PASSED] DVI-A
[17:01:46] [PASSED] Composite
[17:01:46] [PASSED] SVIDEO
[17:01:46] [PASSED] LVDS
[17:01:46] [PASSED] Component
[17:01:46] [PASSED] DIN
[17:01:46] [PASSED] DP
[17:01:46] [PASSED] TV
[17:01:46] [PASSED] eDP
[17:01:46] [PASSED] Virtual
[17:01:46] [PASSED] DSI
[17:01:46] [PASSED] DPI
[17:01:46] [PASSED] Writeback
[17:01:46] [PASSED] SPI
[17:01:46] [PASSED] USB
[17:01:46] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[17:01:46] ============ [PASSED] drmm_connector_hdmi_init =============
[17:01:46] ============= drmm_connector_init (3 subtests) =============
[17:01:46] [PASSED] drm_test_drmm_connector_init
[17:01:46] [PASSED] drm_test_drmm_connector_init_null_ddc
[17:01:46] ========= drm_test_drmm_connector_init_type_valid  =========
[17:01:46] [PASSED] Unknown
[17:01:46] [PASSED] VGA
[17:01:46] [PASSED] DVI-I
[17:01:46] [PASSED] DVI-D
[17:01:46] [PASSED] DVI-A
[17:01:46] [PASSED] Composite
[17:01:46] [PASSED] SVIDEO
[17:01:46] [PASSED] LVDS
[17:01:46] [PASSED] Component
[17:01:46] [PASSED] DIN
[17:01:46] [PASSED] DP
[17:01:46] [PASSED] HDMI-A
[17:01:46] [PASSED] HDMI-B
[17:01:46] [PASSED] TV
[17:01:46] [PASSED] eDP
[17:01:46] [PASSED] Virtual
[17:01:46] [PASSED] DSI
[17:01:46] [PASSED] DPI
[17:01:46] [PASSED] Writeback
[17:01:46] [PASSED] SPI
[17:01:46] [PASSED] USB
[17:01:46] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[17:01:46] =============== [PASSED] drmm_connector_init ===============
[17:01:46] ========= drm_connector_dynamic_init (6 subtests) ==========
[17:01:46] [PASSED] drm_test_drm_connector_dynamic_init
[17:01:46] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[17:01:46] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[17:01:46] [PASSED] drm_test_drm_connector_dynamic_init_properties
[17:01:46] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[17:01:46] [PASSED] Unknown
[17:01:46] [PASSED] VGA
[17:01:46] [PASSED] DVI-I
[17:01:46] [PASSED] DVI-D
[17:01:46] [PASSED] DVI-A
[17:01:46] [PASSED] Composite
[17:01:46] [PASSED] SVIDEO
[17:01:46] [PASSED] LVDS
[17:01:46] [PASSED] Component
[17:01:46] [PASSED] DIN
[17:01:46] [PASSED] DP
[17:01:46] [PASSED] HDMI-A
[17:01:46] [PASSED] HDMI-B
[17:01:46] [PASSED] TV
[17:01:46] [PASSED] eDP
[17:01:46] [PASSED] Virtual
[17:01:46] [PASSED] DSI
[17:01:46] [PASSED] DPI
[17:01:46] [PASSED] Writeback
[17:01:46] [PASSED] SPI
[17:01:46] [PASSED] USB
[17:01:46] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[17:01:46] ======== drm_test_drm_connector_dynamic_init_name  =========
[17:01:46] [PASSED] Unknown
[17:01:46] [PASSED] VGA
[17:01:46] [PASSED] DVI-I
[17:01:46] [PASSED] DVI-D
[17:01:46] [PASSED] DVI-A
[17:01:46] [PASSED] Composite
[17:01:46] [PASSED] SVIDEO
[17:01:46] [PASSED] LVDS
[17:01:46] [PASSED] Component
[17:01:46] [PASSED] DIN
[17:01:46] [PASSED] DP
[17:01:46] [PASSED] HDMI-A
[17:01:46] [PASSED] HDMI-B
[17:01:46] [PASSED] TV
[17:01:46] [PASSED] eDP
[17:01:46] [PASSED] Virtual
[17:01:46] [PASSED] DSI
[17:01:46] [PASSED] DPI
[17:01:46] [PASSED] Writeback
[17:01:46] [PASSED] SPI
[17:01:46] [PASSED] USB
[17:01:46] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[17:01:46] =========== [PASSED] drm_connector_dynamic_init ============
[17:01:46] ==== drm_connector_dynamic_register_early (4 subtests) =====
[17:01:46] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[17:01:46] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[17:01:46] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[17:01:46] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[17:01:46] ====== [PASSED] drm_connector_dynamic_register_early =======
[17:01:46] ======= drm_connector_dynamic_register (7 subtests) ========
[17:01:46] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[17:01:46] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[17:01:46] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[17:01:46] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[17:01:46] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[17:01:46] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[17:01:46] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[17:01:46] ========= [PASSED] drm_connector_dynamic_register ==========
[17:01:46] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[17:01:46] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[17:01:46] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[17:01:46] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[17:01:46] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[17:01:46] ========== drm_test_get_tv_mode_from_name_valid  ===========
[17:01:46] [PASSED] NTSC
[17:01:46] [PASSED] NTSC-443
[17:01:46] [PASSED] NTSC-J
[17:01:46] [PASSED] PAL
[17:01:46] [PASSED] PAL-M
[17:01:46] [PASSED] PAL-N
[17:01:46] [PASSED] SECAM
[17:01:46] [PASSED] Mono
[17:01:46] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[17:01:46] [PASSED] drm_test_get_tv_mode_from_name_truncated
[17:01:46] ============ [PASSED] drm_get_tv_mode_from_name ============
[17:01:46] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[17:01:46] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[17:01:46] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[17:01:46] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[17:01:46] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[17:01:46] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[17:01:46] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[17:01:46] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[17:01:46] [PASSED] VIC 96
[17:01:46] [PASSED] VIC 97
[17:01:46] [PASSED] VIC 101
[17:01:46] [PASSED] VIC 102
[17:01:46] [PASSED] VIC 106
[17:01:46] [PASSED] VIC 107
[17:01:46] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[17:01:46] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[17:01:46] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[17:01:46] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[17:01:46] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[17:01:46] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[17:01:46] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[17:01:46] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[17:01:46] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[17:01:46] [PASSED] Automatic
[17:01:46] [PASSED] Full
[17:01:46] [PASSED] Limited 16:235
[17:01:46] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[17:01:46] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[17:01:46] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[17:01:46] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[17:01:46] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[17:01:46] [PASSED] RGB
[17:01:46] [PASSED] YUV 4:2:0
[17:01:46] [PASSED] YUV 4:2:2
[17:01:46] [PASSED] YUV 4:4:4
[17:01:46] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[17:01:46] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[17:01:46] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[17:01:46] ============= drm_damage_helper (21 subtests) ==============
[17:01:46] [PASSED] drm_test_damage_iter_no_damage
[17:01:46] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[17:01:46] [PASSED] drm_test_damage_iter_no_damage_src_moved
[17:01:46] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[17:01:46] [PASSED] drm_test_damage_iter_no_damage_not_visible
[17:01:46] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[17:01:46] [PASSED] drm_test_damage_iter_no_damage_no_fb
[17:01:46] [PASSED] drm_test_damage_iter_simple_damage
[17:01:46] [PASSED] drm_test_damage_iter_single_damage
[17:01:46] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[17:01:46] [PASSED] drm_test_damage_iter_single_damage_outside_src
[17:01:46] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[17:01:46] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[17:01:46] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[17:01:46] [PASSED] drm_test_damage_iter_single_damage_src_moved
[17:01:46] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[17:01:46] [PASSED] drm_test_damage_iter_damage
[17:01:46] [PASSED] drm_test_damage_iter_damage_one_intersect
[17:01:46] [PASSED] drm_test_damage_iter_damage_one_outside
[17:01:46] [PASSED] drm_test_damage_iter_damage_src_moved
[17:01:46] [PASSED] drm_test_damage_iter_damage_not_visible
[17:01:46] ================ [PASSED] drm_damage_helper ================
[17:01:46] ============== drm_dp_mst_helper (3 subtests) ==============
[17:01:46] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[17:01:46] [PASSED] Clock 154000 BPP 30 DSC disabled
[17:01:46] [PASSED] Clock 234000 BPP 30 DSC disabled
[17:01:46] [PASSED] Clock 297000 BPP 24 DSC disabled
[17:01:46] [PASSED] Clock 332880 BPP 24 DSC enabled
[17:01:46] [PASSED] Clock 324540 BPP 24 DSC enabled
[17:01:46] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[17:01:46] ============== drm_test_dp_mst_calc_pbn_div  ===============
[17:01:46] [PASSED] Link rate 2000000 lane count 4
[17:01:46] [PASSED] Link rate 2000000 lane count 2
[17:01:46] [PASSED] Link rate 2000000 lane count 1
[17:01:46] [PASSED] Link rate 1350000 lane count 4
[17:01:46] [PASSED] Link rate 1350000 lane count 2
[17:01:46] [PASSED] Link rate 1350000 lane count 1
[17:01:46] [PASSED] Link rate 1000000 lane count 4
[17:01:46] [PASSED] Link rate 1000000 lane count 2
[17:01:46] [PASSED] Link rate 1000000 lane count 1
[17:01:46] [PASSED] Link rate 810000 lane count 4
[17:01:46] [PASSED] Link rate 810000 lane count 2
[17:01:46] [PASSED] Link rate 810000 lane count 1
[17:01:46] [PASSED] Link rate 540000 lane count 4
[17:01:46] [PASSED] Link rate 540000 lane count 2
[17:01:46] [PASSED] Link rate 540000 lane count 1
[17:01:46] [PASSED] Link rate 270000 lane count 4
[17:01:46] [PASSED] Link rate 270000 lane count 2
[17:01:46] [PASSED] Link rate 270000 lane count 1
[17:01:46] [PASSED] Link rate 162000 lane count 4
[17:01:46] [PASSED] Link rate 162000 lane count 2
[17:01:46] [PASSED] Link rate 162000 lane count 1
[17:01:46] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[17:01:46] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[17:01:46] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[17:01:46] [PASSED] DP_POWER_UP_PHY with port number
[17:01:46] [PASSED] DP_POWER_DOWN_PHY with port number
[17:01:46] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[17:01:46] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[17:01:46] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[17:01:46] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[17:01:46] [PASSED] DP_QUERY_PAYLOAD with port number
[17:01:46] [PASSED] DP_QUERY_PAYLOAD with VCPI
[17:01:46] [PASSED] DP_REMOTE_DPCD_READ with port number
[17:01:46] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[17:01:46] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[17:01:46] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[17:01:46] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[17:01:46] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[17:01:46] [PASSED] DP_REMOTE_I2C_READ with port number
[17:01:46] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[17:01:46] [PASSED] DP_REMOTE_I2C_READ with transactions array
[17:01:46] [PASSED] DP_REMOTE_I2C_WRITE with port number
[17:01:46] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[17:01:46] [PASSED] DP_REMOTE_I2C_WRITE with data array
[17:01:46] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[17:01:46] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[17:01:46] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[17:01:46] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[17:01:46] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[17:01:46] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[17:01:46] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[17:01:46] ================ [PASSED] drm_dp_mst_helper ================
[17:01:46] ================== drm_exec (7 subtests) ===================
[17:01:46] [PASSED] sanitycheck
[17:01:46] [PASSED] test_lock
[17:01:46] [PASSED] test_lock_unlock
[17:01:46] [PASSED] test_duplicates
[17:01:46] [PASSED] test_prepare
[17:01:46] [PASSED] test_prepare_array
[17:01:46] [PASSED] test_multiple_loops
[17:01:46] ==================== [PASSED] drm_exec =====================
[17:01:46] =========== drm_format_helper_test (17 subtests) ===========
[17:01:46] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[17:01:46] [PASSED] single_pixel_source_buffer
[17:01:46] [PASSED] single_pixel_clip_rectangle
[17:01:46] [PASSED] well_known_colors
[17:01:46] [PASSED] destination_pitch
[17:01:46] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[17:01:46] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[17:01:46] [PASSED] single_pixel_source_buffer
[17:01:46] [PASSED] single_pixel_clip_rectangle
[17:01:46] [PASSED] well_known_colors
[17:01:46] [PASSED] destination_pitch
[17:01:46] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[17:01:46] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[17:01:46] [PASSED] single_pixel_source_buffer
[17:01:46] [PASSED] single_pixel_clip_rectangle
[17:01:46] [PASSED] well_known_colors
[17:01:46] [PASSED] destination_pitch
[17:01:46] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[17:01:46] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[17:01:46] [PASSED] single_pixel_source_buffer
[17:01:46] [PASSED] single_pixel_clip_rectangle
[17:01:46] [PASSED] well_known_colors
[17:01:46] [PASSED] destination_pitch
[17:01:46] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[17:01:46] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[17:01:46] [PASSED] single_pixel_source_buffer
[17:01:46] [PASSED] single_pixel_clip_rectangle
[17:01:46] [PASSED] well_known_colors
[17:01:46] [PASSED] destination_pitch
[17:01:46] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[17:01:46] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[17:01:46] [PASSED] single_pixel_source_buffer
[17:01:46] [PASSED] single_pixel_clip_rectangle
[17:01:46] [PASSED] well_known_colors
[17:01:46] [PASSED] destination_pitch
[17:01:46] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[17:01:46] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[17:01:46] [PASSED] single_pixel_source_buffer
[17:01:46] [PASSED] single_pixel_clip_rectangle
[17:01:46] [PASSED] well_known_colors
[17:01:46] [PASSED] destination_pitch
[17:01:46] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[17:01:46] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[17:01:46] [PASSED] single_pixel_source_buffer
[17:01:46] [PASSED] single_pixel_clip_rectangle
[17:01:46] [PASSED] well_known_colors
[17:01:46] [PASSED] destination_pitch
[17:01:46] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[17:01:46] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[17:01:46] [PASSED] single_pixel_source_buffer
[17:01:46] [PASSED] single_pixel_clip_rectangle
[17:01:46] [PASSED] well_known_colors
[17:01:46] [PASSED] destination_pitch
[17:01:46] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[17:01:46] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[17:01:46] [PASSED] single_pixel_source_buffer
[17:01:46] [PASSED] single_pixel_clip_rectangle
[17:01:46] [PASSED] well_known_colors
[17:01:46] [PASSED] destination_pitch
[17:01:46] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[17:01:46] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[17:01:46] [PASSED] single_pixel_source_buffer
[17:01:46] [PASSED] single_pixel_clip_rectangle
[17:01:46] [PASSED] well_known_colors
[17:01:46] [PASSED] destination_pitch
[17:01:46] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[17:01:46] ============== drm_test_fb_xrgb8888_to_mono  ===============
[17:01:46] [PASSED] single_pixel_source_buffer
[17:01:46] [PASSED] single_pixel_clip_rectangle
[17:01:46] [PASSED] well_known_colors
[17:01:46] [PASSED] destination_pitch
[17:01:46] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[17:01:46] ==================== drm_test_fb_swab  =====================
[17:01:46] [PASSED] single_pixel_source_buffer
[17:01:46] [PASSED] single_pixel_clip_rectangle
[17:01:46] [PASSED] well_known_colors
[17:01:46] [PASSED] destination_pitch
[17:01:46] ================ [PASSED] drm_test_fb_swab =================
[17:01:46] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[17:01:46] [PASSED] single_pixel_source_buffer
[17:01:46] [PASSED] single_pixel_clip_rectangle
[17:01:46] [PASSED] well_known_colors
[17:01:46] [PASSED] destination_pitch
[17:01:46] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[17:01:46] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[17:01:46] [PASSED] single_pixel_source_buffer
[17:01:46] [PASSED] single_pixel_clip_rectangle
[17:01:46] [PASSED] well_known_colors
[17:01:46] [PASSED] destination_pitch
[17:01:46] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[17:01:46] ================= drm_test_fb_clip_offset  =================
[17:01:46] [PASSED] pass through
[17:01:46] [PASSED] horizontal offset
[17:01:46] [PASSED] vertical offset
[17:01:46] [PASSED] horizontal and vertical offset
[17:01:46] [PASSED] horizontal offset (custom pitch)
[17:01:46] [PASSED] vertical offset (custom pitch)
[17:01:46] [PASSED] horizontal and vertical offset (custom pitch)
[17:01:46] ============= [PASSED] drm_test_fb_clip_offset =============
[17:01:46] =================== drm_test_fb_memcpy  ====================
[17:01:46] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[17:01:46] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[17:01:46] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[17:01:46] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[17:01:46] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[17:01:46] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[17:01:46] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[17:01:46] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[17:01:46] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[17:01:46] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[17:01:46] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[17:01:46] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[17:01:46] =============== [PASSED] drm_test_fb_memcpy ================
[17:01:46] ============= [PASSED] drm_format_helper_test ==============
[17:01:46] ================= drm_format (18 subtests) =================
[17:01:46] [PASSED] drm_test_format_block_width_invalid
[17:01:46] [PASSED] drm_test_format_block_width_one_plane
[17:01:46] [PASSED] drm_test_format_block_width_two_plane
[17:01:46] [PASSED] drm_test_format_block_width_three_plane
[17:01:46] [PASSED] drm_test_format_block_width_tiled
[17:01:46] [PASSED] drm_test_format_block_height_invalid
[17:01:46] [PASSED] drm_test_format_block_height_one_plane
[17:01:46] [PASSED] drm_test_format_block_height_two_plane
[17:01:46] [PASSED] drm_test_format_block_height_three_plane
[17:01:46] [PASSED] drm_test_format_block_height_tiled
[17:01:46] [PASSED] drm_test_format_min_pitch_invalid
[17:01:46] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[17:01:46] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[17:01:46] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[17:01:46] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[17:01:46] [PASSED] drm_test_format_min_pitch_two_plane
[17:01:46] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[17:01:46] [PASSED] drm_test_format_min_pitch_tiled
[17:01:46] =================== [PASSED] drm_format ====================
[17:01:46] ============== drm_framebuffer (10 subtests) ===============
[17:01:46] ========== drm_test_framebuffer_check_src_coords  ==========
[17:01:46] [PASSED] Success: source fits into fb
[17:01:46] [PASSED] Fail: overflowing fb with x-axis coordinate
[17:01:46] [PASSED] Fail: overflowing fb with y-axis coordinate
[17:01:46] [PASSED] Fail: overflowing fb with source width
[17:01:46] [PASSED] Fail: overflowing fb with source height
[17:01:46] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[17:01:46] [PASSED] drm_test_framebuffer_cleanup
[17:01:46] =============== drm_test_framebuffer_create  ===============
[17:01:46] [PASSED] ABGR8888 normal sizes
[17:01:46] [PASSED] ABGR8888 max sizes
[17:01:46] [PASSED] ABGR8888 pitch greater than min required
[17:01:46] [PASSED] ABGR8888 pitch less than min required
[17:01:46] [PASSED] ABGR8888 Invalid width
[17:01:46] [PASSED] ABGR8888 Invalid buffer handle
[17:01:46] [PASSED] No pixel format
[17:01:46] [PASSED] ABGR8888 Width 0
[17:01:46] [PASSED] ABGR8888 Height 0
[17:01:46] [PASSED] ABGR8888 Out of bound height * pitch combination
[17:01:46] [PASSED] ABGR8888 Large buffer offset
[17:01:46] [PASSED] ABGR8888 Buffer offset for inexistent plane
[17:01:46] [PASSED] ABGR8888 Invalid flag
[17:01:46] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[17:01:46] [PASSED] ABGR8888 Valid buffer modifier
[17:01:46] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[17:01:46] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[17:01:46] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[17:01:46] [PASSED] NV12 Normal sizes
[17:01:46] [PASSED] NV12 Max sizes
[17:01:46] [PASSED] NV12 Invalid pitch
[17:01:46] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[17:01:46] [PASSED] NV12 different  modifier per-plane
[17:01:46] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[17:01:46] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[17:01:46] [PASSED] NV12 Modifier for inexistent plane
[17:01:46] [PASSED] NV12 Handle for inexistent plane
[17:01:46] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[17:01:46] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[17:01:46] [PASSED] YVU420 Normal sizes
[17:01:46] [PASSED] YVU420 Max sizes
[17:01:46] [PASSED] YVU420 Invalid pitch
[17:01:46] [PASSED] YVU420 Different pitches
[17:01:46] [PASSED] YVU420 Different buffer offsets/pitches
[17:01:46] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[17:01:46] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[17:01:46] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[17:01:46] [PASSED] YVU420 Valid modifier
[17:01:46] [PASSED] YVU420 Different modifiers per plane
[17:01:46] [PASSED] YVU420 Modifier for inexistent plane
[17:01:46] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[17:01:46] [PASSED] X0L2 Normal sizes
[17:01:46] [PASSED] X0L2 Max sizes
[17:01:46] [PASSED] X0L2 Invalid pitch
[17:01:46] [PASSED] X0L2 Pitch greater than minimum required
[17:01:46] [PASSED] X0L2 Handle for inexistent plane
[17:01:46] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[17:01:46] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[17:01:46] [PASSED] X0L2 Valid modifier
[17:01:46] [PASSED] X0L2 Modifier for inexistent plane
[17:01:46] =========== [PASSED] drm_test_framebuffer_create ===========
[17:01:46] [PASSED] drm_test_framebuffer_free
[17:01:46] [PASSED] drm_test_framebuffer_init
[17:01:46] [PASSED] drm_test_framebuffer_init_bad_format
[17:01:46] [PASSED] drm_test_framebuffer_init_dev_mismatch
[17:01:46] [PASSED] drm_test_framebuffer_lookup
[17:01:46] [PASSED] drm_test_framebuffer_lookup_inexistent
[17:01:46] [PASSED] drm_test_framebuffer_modifiers_not_supported
[17:01:46] ================= [PASSED] drm_framebuffer =================
[17:01:46] ================ drm_gem_shmem (8 subtests) ================
[17:01:46] [PASSED] drm_gem_shmem_test_obj_create
[17:01:46] [PASSED] drm_gem_shmem_test_obj_create_private
[17:01:46] [PASSED] drm_gem_shmem_test_pin_pages
[17:01:46] [PASSED] drm_gem_shmem_test_vmap
[17:01:46] [PASSED] drm_gem_shmem_test_get_pages_sgt
[17:01:46] [PASSED] drm_gem_shmem_test_get_sg_table
[17:01:46] [PASSED] drm_gem_shmem_test_madvise
[17:01:46] [PASSED] drm_gem_shmem_test_purge
[17:01:46] ================== [PASSED] drm_gem_shmem ==================
[17:01:46] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[17:01:46] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[17:01:46] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[17:01:46] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[17:01:46] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[17:01:46] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[17:01:46] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[17:01:46] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[17:01:46] [PASSED] Automatic
[17:01:46] [PASSED] Full
[17:01:46] [PASSED] Limited 16:235
[17:01:46] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[17:01:46] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[17:01:46] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[17:01:46] [PASSED] drm_test_check_disable_connector
[17:01:46] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[17:01:46] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[17:01:46] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[17:01:46] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[17:01:46] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[17:01:46] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[17:01:46] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[17:01:46] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[17:01:46] [PASSED] drm_test_check_output_bpc_dvi
[17:01:46] [PASSED] drm_test_check_output_bpc_format_vic_1
[17:01:46] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[17:01:46] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[17:01:46] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[17:01:46] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[17:01:46] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[17:01:46] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[17:01:46] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[17:01:46] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[17:01:46] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[17:01:46] [PASSED] drm_test_check_broadcast_rgb_value
[17:01:46] [PASSED] drm_test_check_bpc_8_value
[17:01:46] [PASSED] drm_test_check_bpc_10_value
[17:01:46] [PASSED] drm_test_check_bpc_12_value
[17:01:46] [PASSED] drm_test_check_format_value
[17:01:46] [PASSED] drm_test_check_tmds_char_value
[17:01:46] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[17:01:46] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[17:01:46] [PASSED] drm_test_check_mode_valid
[17:01:46] [PASSED] drm_test_check_mode_valid_reject
[17:01:46] [PASSED] drm_test_check_mode_valid_reject_rate
[17:01:46] [PASSED] drm_test_check_mode_valid_reject_max_clock
[17:01:46] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[17:01:46] ================= drm_managed (2 subtests) =================
[17:01:46] [PASSED] drm_test_managed_release_action
[17:01:46] [PASSED] drm_test_managed_run_action
[17:01:46] =================== [PASSED] drm_managed ===================
[17:01:46] =================== drm_mm (6 subtests) ====================
[17:01:46] [PASSED] drm_test_mm_init
[17:01:46] [PASSED] drm_test_mm_debug
[17:01:46] [PASSED] drm_test_mm_align32
[17:01:46] [PASSED] drm_test_mm_align64
[17:01:46] [PASSED] drm_test_mm_lowest
[17:01:46] [PASSED] drm_test_mm_highest
[17:01:46] ===================== [PASSED] drm_mm ======================
[17:01:46] ============= drm_modes_analog_tv (5 subtests) =============
[17:01:46] [PASSED] drm_test_modes_analog_tv_mono_576i
[17:01:46] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[17:01:46] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[17:01:46] [PASSED] drm_test_modes_analog_tv_pal_576i
[17:01:46] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[17:01:46] =============== [PASSED] drm_modes_analog_tv ===============
[17:01:46] ============== drm_plane_helper (2 subtests) ===============
[17:01:46] =============== drm_test_check_plane_state  ================
[17:01:46] [PASSED] clipping_simple
[17:01:46] [PASSED] clipping_rotate_reflect
[17:01:46] [PASSED] positioning_simple
[17:01:46] [PASSED] upscaling
[17:01:46] [PASSED] downscaling
[17:01:46] [PASSED] rounding1
[17:01:46] [PASSED] rounding2
[17:01:46] [PASSED] rounding3
[17:01:46] [PASSED] rounding4
[17:01:46] =========== [PASSED] drm_test_check_plane_state ============
[17:01:46] =========== drm_test_check_invalid_plane_state  ============
[17:01:46] [PASSED] positioning_invalid
[17:01:46] [PASSED] upscaling_invalid
[17:01:46] [PASSED] downscaling_invalid
[17:01:46] ======= [PASSED] drm_test_check_invalid_plane_state ========
[17:01:46] ================ [PASSED] drm_plane_helper =================
[17:01:46] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[17:01:46] ====== drm_test_connector_helper_tv_get_modes_check  =======
[17:01:46] [PASSED] None
[17:01:46] [PASSED] PAL
[17:01:46] [PASSED] NTSC
[17:01:46] [PASSED] Both, NTSC Default
[17:01:46] [PASSED] Both, PAL Default
[17:01:46] [PASSED] Both, NTSC Default, with PAL on command-line
[17:01:46] [PASSED] Both, PAL Default, with NTSC on command-line
[17:01:46] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[17:01:46] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[17:01:46] ================== drm_rect (9 subtests) ===================
[17:01:46] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[17:01:46] [PASSED] drm_test_rect_clip_scaled_not_clipped
[17:01:46] [PASSED] drm_test_rect_clip_scaled_clipped
[17:01:46] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[17:01:46] ================= drm_test_rect_intersect  =================
[17:01:46] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[17:01:46] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[17:01:46] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[17:01:46] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[17:01:46] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[17:01:46] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[17:01:46] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[17:01:46] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[17:01:46] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[17:01:46] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[17:01:46] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[17:01:46] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[17:01:46] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[17:01:46] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[17:01:46] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[17:01:46] ============= [PASSED] drm_test_rect_intersect =============
[17:01:46] ================ drm_test_rect_calc_hscale  ================
[17:01:46] [PASSED] normal use
[17:01:46] [PASSED] out of max range
[17:01:46] [PASSED] out of min range
[17:01:46] [PASSED] zero dst
[17:01:46] [PASSED] negative src
[17:01:46] [PASSED] negative dst
[17:01:46] ============ [PASSED] drm_test_rect_calc_hscale ============
[17:01:46] ================ drm_test_rect_calc_vscale  ================
[17:01:46] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[17:01:46] [PASSED] out of max range
[17:01:46] [PASSED] out of min range
[17:01:46] [PASSED] zero dst
[17:01:46] [PASSED] negative src
[17:01:46] [PASSED] negative dst
[17:01:46] ============ [PASSED] drm_test_rect_calc_vscale ============
[17:01:46] ================== drm_test_rect_rotate  ===================
[17:01:46] [PASSED] reflect-x
[17:01:46] [PASSED] reflect-y
[17:01:46] [PASSED] rotate-0
[17:01:46] [PASSED] rotate-90
[17:01:46] [PASSED] rotate-180
[17:01:46] [PASSED] rotate-270
[17:01:46] ============== [PASSED] drm_test_rect_rotate ===============
[17:01:46] ================ drm_test_rect_rotate_inv  =================
[17:01:46] [PASSED] reflect-x
[17:01:46] [PASSED] reflect-y
[17:01:46] [PASSED] rotate-0
[17:01:46] [PASSED] rotate-90
[17:01:46] [PASSED] rotate-180
[17:01:46] [PASSED] rotate-270
[17:01:46] ============ [PASSED] drm_test_rect_rotate_inv =============
[17:01:46] ==================== [PASSED] drm_rect =====================
[17:01:46] ============ drm_sysfb_modeset_test (1 subtest) ============
[17:01:46] ============ drm_test_sysfb_build_fourcc_list  =============
[17:01:46] [PASSED] no native formats
[17:01:46] [PASSED] XRGB8888 as native format
[17:01:46] [PASSED] remove duplicates
[17:01:46] [PASSED] convert alpha formats
[17:01:46] [PASSED] random formats
[17:01:46] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[17:01:46] ============= [PASSED] drm_sysfb_modeset_test ==============
[17:01:46] ============================================================
[17:01:46] Testing complete. Ran 622 tests: passed: 622
[17:01:46] Elapsed time: 26.827s total, 1.703s configuring, 24.707s building, 0.379s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[17:01:46] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:01:47] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[17:01:57] Starting KUnit Kernel (1/1)...
[17:01:57] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:01:57] ================= ttm_device (5 subtests) ==================
[17:01:57] [PASSED] ttm_device_init_basic
[17:01:57] [PASSED] ttm_device_init_multiple
[17:01:57] [PASSED] ttm_device_fini_basic
[17:01:57] [PASSED] ttm_device_init_no_vma_man
[17:01:57] ================== ttm_device_init_pools  ==================
[17:01:57] [PASSED] No DMA allocations, no DMA32 required
[17:01:57] [PASSED] DMA allocations, DMA32 required
[17:01:57] [PASSED] No DMA allocations, DMA32 required
[17:01:57] [PASSED] DMA allocations, no DMA32 required
[17:01:57] ============== [PASSED] ttm_device_init_pools ==============
[17:01:57] =================== [PASSED] ttm_device ====================
[17:01:57] ================== ttm_pool (8 subtests) ===================
[17:01:57] ================== ttm_pool_alloc_basic  ===================
[17:01:57] [PASSED] One page
[17:01:57] [PASSED] More than one page
[17:01:57] [PASSED] Above the allocation limit
[17:01:57] [PASSED] One page, with coherent DMA mappings enabled
[17:01:57] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[17:01:57] ============== [PASSED] ttm_pool_alloc_basic ===============
[17:01:57] ============== ttm_pool_alloc_basic_dma_addr  ==============
[17:01:57] [PASSED] One page
[17:01:57] [PASSED] More than one page
[17:01:57] [PASSED] Above the allocation limit
[17:01:57] [PASSED] One page, with coherent DMA mappings enabled
[17:01:57] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[17:01:57] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[17:01:57] [PASSED] ttm_pool_alloc_order_caching_match
[17:01:57] [PASSED] ttm_pool_alloc_caching_mismatch
[17:01:57] [PASSED] ttm_pool_alloc_order_mismatch
[17:01:57] [PASSED] ttm_pool_free_dma_alloc
[17:01:57] [PASSED] ttm_pool_free_no_dma_alloc
[17:01:57] [PASSED] ttm_pool_fini_basic
[17:01:57] ==================== [PASSED] ttm_pool =====================
[17:01:57] ================ ttm_resource (8 subtests) =================
[17:01:57] ================= ttm_resource_init_basic  =================
[17:01:57] [PASSED] Init resource in TTM_PL_SYSTEM
[17:01:57] [PASSED] Init resource in TTM_PL_VRAM
[17:01:57] [PASSED] Init resource in a private placement
[17:01:57] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[17:01:57] ============= [PASSED] ttm_resource_init_basic =============
[17:01:57] [PASSED] ttm_resource_init_pinned
[17:01:57] [PASSED] ttm_resource_fini_basic
[17:01:57] [PASSED] ttm_resource_manager_init_basic
[17:01:57] [PASSED] ttm_resource_manager_usage_basic
[17:01:57] [PASSED] ttm_resource_manager_set_used_basic
[17:01:57] [PASSED] ttm_sys_man_alloc_basic
[17:01:57] [PASSED] ttm_sys_man_free_basic
[17:01:57] ================== [PASSED] ttm_resource ===================
[17:01:57] =================== ttm_tt (15 subtests) ===================
[17:01:57] ==================== ttm_tt_init_basic  ====================
[17:01:57] [PASSED] Page-aligned size
[17:01:57] [PASSED] Extra pages requested
[17:01:57] ================ [PASSED] ttm_tt_init_basic ================
[17:01:57] [PASSED] ttm_tt_init_misaligned
[17:01:57] [PASSED] ttm_tt_fini_basic
[17:01:57] [PASSED] ttm_tt_fini_sg
[17:01:57] [PASSED] ttm_tt_fini_shmem
[17:01:57] [PASSED] ttm_tt_create_basic
[17:01:57] [PASSED] ttm_tt_create_invalid_bo_type
[17:01:57] [PASSED] ttm_tt_create_ttm_exists
[17:01:57] [PASSED] ttm_tt_create_failed
[17:01:57] [PASSED] ttm_tt_destroy_basic
[17:01:57] [PASSED] ttm_tt_populate_null_ttm
[17:01:57] [PASSED] ttm_tt_populate_populated_ttm
[17:01:57] [PASSED] ttm_tt_unpopulate_basic
[17:01:57] [PASSED] ttm_tt_unpopulate_empty_ttm
[17:01:57] [PASSED] ttm_tt_swapin_basic
[17:01:57] ===================== [PASSED] ttm_tt ======================
[17:01:57] =================== ttm_bo (14 subtests) ===================
[17:01:57] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[17:01:57] [PASSED] Cannot be interrupted and sleeps
[17:01:57] [PASSED] Cannot be interrupted, locks straight away
[17:01:57] [PASSED] Can be interrupted, sleeps
[17:01:57] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[17:01:57] [PASSED] ttm_bo_reserve_locked_no_sleep
[17:01:57] [PASSED] ttm_bo_reserve_no_wait_ticket
[17:01:57] [PASSED] ttm_bo_reserve_double_resv
[17:01:57] [PASSED] ttm_bo_reserve_interrupted
[17:01:57] [PASSED] ttm_bo_reserve_deadlock
[17:01:57] [PASSED] ttm_bo_unreserve_basic
[17:01:57] [PASSED] ttm_bo_unreserve_pinned
[17:01:57] [PASSED] ttm_bo_unreserve_bulk
[17:01:57] [PASSED] ttm_bo_fini_basic
[17:01:57] [PASSED] ttm_bo_fini_shared_resv
[17:01:57] [PASSED] ttm_bo_pin_basic
[17:01:57] [PASSED] ttm_bo_pin_unpin_resource
[17:01:57] [PASSED] ttm_bo_multiple_pin_one_unpin
[17:01:57] ===================== [PASSED] ttm_bo ======================
[17:01:57] ============== ttm_bo_validate (21 subtests) ===============
[17:01:57] ============== ttm_bo_init_reserved_sys_man  ===============
[17:01:57] [PASSED] Buffer object for userspace
[17:01:57] [PASSED] Kernel buffer object
[17:01:57] [PASSED] Shared buffer object
[17:01:57] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[17:01:57] ============== ttm_bo_init_reserved_mock_man  ==============
[17:01:57] [PASSED] Buffer object for userspace
[17:01:57] [PASSED] Kernel buffer object
[17:01:57] [PASSED] Shared buffer object
[17:01:57] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[17:01:57] [PASSED] ttm_bo_init_reserved_resv
[17:01:57] ================== ttm_bo_validate_basic  ==================
[17:01:57] [PASSED] Buffer object for userspace
[17:01:57] [PASSED] Kernel buffer object
[17:01:57] [PASSED] Shared buffer object
[17:01:57] ============== [PASSED] ttm_bo_validate_basic ==============
[17:01:57] [PASSED] ttm_bo_validate_invalid_placement
[17:01:57] ============= ttm_bo_validate_same_placement  ==============
[17:01:57] [PASSED] System manager
[17:01:57] [PASSED] VRAM manager
[17:01:57] ========= [PASSED] ttm_bo_validate_same_placement ==========
[17:01:57] [PASSED] ttm_bo_validate_failed_alloc
[17:01:57] [PASSED] ttm_bo_validate_pinned
[17:01:57] [PASSED] ttm_bo_validate_busy_placement
[17:01:57] ================ ttm_bo_validate_multihop  =================
[17:01:57] [PASSED] Buffer object for userspace
[17:01:57] [PASSED] Kernel buffer object
[17:01:57] [PASSED] Shared buffer object
[17:01:57] ============ [PASSED] ttm_bo_validate_multihop =============
[17:01:57] ========== ttm_bo_validate_no_placement_signaled  ==========
[17:01:57] [PASSED] Buffer object in system domain, no page vector
[17:01:57] [PASSED] Buffer object in system domain with an existing page vector
[17:01:57] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[17:01:57] ======== ttm_bo_validate_no_placement_not_signaled  ========
[17:01:57] [PASSED] Buffer object for userspace
[17:01:57] [PASSED] Kernel buffer object
[17:01:57] [PASSED] Shared buffer object
[17:01:57] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[17:01:57] [PASSED] ttm_bo_validate_move_fence_signaled
[17:01:57] ========= ttm_bo_validate_move_fence_not_signaled  =========
[17:01:57] [PASSED] Waits for GPU
[17:01:57] [PASSED] Tries to lock straight away
[17:01:57] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[17:01:57] [PASSED] ttm_bo_validate_happy_evict
[17:01:57] [PASSED] ttm_bo_validate_all_pinned_evict
[17:01:57] [PASSED] ttm_bo_validate_allowed_only_evict
[17:01:57] [PASSED] ttm_bo_validate_deleted_evict
[17:01:57] [PASSED] ttm_bo_validate_busy_domain_evict
[17:01:57] [PASSED] ttm_bo_validate_evict_gutting
[17:01:57] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[17:01:57] ================= [PASSED] ttm_bo_validate =================
[17:01:57] ============================================================
[17:01:57] Testing complete. Ran 101 tests: passed: 101
[17:01:57] Elapsed time: 11.328s total, 1.683s configuring, 9.380s building, 0.225s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✗ CI.checksparse: warning for Optimize vrr.guardband

[Patchwork]

== Series Details ==

Series: Optimize vrr.guardband
URL   : https://patchwork.freedesktop.org/series/155979/
State : warning

== Summary ==

+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast 69ca30df000b382e7657f300148be505083377f2
Sparse version: 0.6.4 (Ubuntu: 0.6.4-4ubuntu3)
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_alpm.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_cdclk.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_ddi.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2055:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2055:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2055:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_hdcp.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_hotplug.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_pps.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_psr.c: note: in included file:
+drivers/gpu/drm/i915/intel_uncore.c:1928:1: warning: context imbalance in 'fwtable_read8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1929:1: warning: context imbalance in 'fwtable_read16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1930:1: warning: context imbalance in 'fwtable_read32' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1931:1: warning: context imbalance in 'fwtable_read64' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1996:1: warning: context imbalance in 'gen6_write8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1997:1: warning: context imbalance in 'gen6_write16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1998:1: warning: context imbalance in 'gen6_write32' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2018:1: warning: context imbalance in 'fwtable_write8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2019:1: warning: context imbalance in 'fwtable_write16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2020:1: warning: context imbalance in 'fwtable_write32' - unexpected unlock

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✗ Xe.CI.BAT: failure for Optimize vrr.guardband

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 4585 bytes --]

== Series Details ==

Series: Optimize vrr.guardband
URL   : https://patchwork.freedesktop.org/series/155979/
State : failure

== Summary ==

CI Bug Log - changes from xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554_BAT -> xe-pw-155979v1_BAT
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-155979v1_BAT absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-155979v1_BAT, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (11 -> 10)
------------------------------

  Missing    (1): bat-adlp-vm 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-155979v1_BAT:

### IGT changes ###

#### Possible regressions ####

  * igt@xe_module_load@load:
    - bat-ptl-1:          [PASS][1] -> [ABORT][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/bat-ptl-1/igt@xe_module_load@load.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/bat-ptl-1/igt@xe_module_load@load.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@core_debugfs@read-all-entries}:
    - bat-adlp-7:         [PASS][3] -> [ABORT][4]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/bat-adlp-7/igt@core_debugfs@read-all-entries.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/bat-adlp-7/igt@core_debugfs@read-all-entries.html
    - bat-bmg-1:          [PASS][5] -> [ABORT][6]
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/bat-bmg-1/igt@core_debugfs@read-all-entries.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/bat-bmg-1/igt@core_debugfs@read-all-entries.html
    - bat-ptl-2:          [PASS][7] -> [ABORT][8]
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/bat-ptl-2/igt@core_debugfs@read-all-entries.html
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/bat-ptl-2/igt@core_debugfs@read-all-entries.html
    - bat-dg2-oem2:       [PASS][9] -> [ABORT][10]
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/bat-dg2-oem2/igt@core_debugfs@read-all-entries.html
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/bat-dg2-oem2/igt@core_debugfs@read-all-entries.html
    - bat-lnl-1:          [PASS][11] -> [ABORT][12]
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/bat-lnl-1/igt@core_debugfs@read-all-entries.html
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/bat-lnl-1/igt@core_debugfs@read-all-entries.html

  
Known issues
------------

  Here are the changes found in xe-pw-155979v1_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@xe_module_load@load:
    - bat-bmg-2:          [PASS][13] -> [ABORT][14] ([Intel XE#5087])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/bat-bmg-2/igt@xe_module_load@load.html
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/bat-bmg-2/igt@xe_module_load@load.html
    - bat-lnl-2:          [PASS][15] -> [ABORT][16] ([Intel XE#5087])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/bat-lnl-2/igt@xe_module_load@load.html
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/bat-lnl-2/igt@xe_module_load@load.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#5087]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5087


Build changes
-------------

  * IGT: IGT_8585 -> IGT_8586
  * Linux: xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554 -> xe-pw-155979v1

  IGT_8585: 8585
  IGT_8586: dbda1336c5c99d0faa88397d5c312be72301cd94 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554: ed00bdb0008276b3497a4c811e160f18d1218554
  xe-pw-155979v1: 155979v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/index.html

[-- Attachment #2: Type: text/html, Size: 5349 bytes --]

Re: [PATCH 5/6] drm/i915/display: Add guardband check for feature latencies

[Nautiyal, Ankit K]

On 10/15/2025 10:06 PM, Ville Syrjälä wrote:
> On Wed, Oct 15, 2025 at 03:52:40PM +0530, Ankit Nautiyal wrote:
>> Add a check during atomic crtc check phase to ensure the programmed
>> guardband is sufficient to cover latencies introduced by enabled features
>> such as DSC, PSR/PR, scalers, and DP SDPs.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_display.c | 56 ++++++++++++++++++++
>>   1 file changed, 56 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index 4367ecfab2b3..4e3f08a8cd9c 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -126,6 +126,7 @@
>>   #include "intel_vga.h"
>>   #include "intel_vrr.h"
>>   #include "intel_wm.h"
>> +#include "skl_prefill.h"
>>   #include "skl_scaler.h"
>>   #include "skl_universal_plane.h"
>>   #include "skl_watermark.h"
>> @@ -4191,6 +4192,57 @@ static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
>>   	return 0;
>>   }
>>   
>> +static int intel_crtc_guardband_atomic_check(struct intel_atomic_state *state,
>> +					     struct intel_crtc *crtc)
> Not sure why you're adding this. We already have the
> compute_guardband().

For computing optimizing guardband, I have the next patch where I am 
using skl_prefill_init_worst() and sdp, psr guardband and taking max of 
(prefill_guardband, sdp, psr).

Here I was trying to finally check at last if the guardband is 
sufficient with the actual values of prefill guardband, sdp, psr.

But now I think we dont need this check.

As suggested I will just check for SDP min guardband in compute_config_late.

Regards,

Ankit

>
>> +{
>> +	struct intel_display *display = to_intel_display(crtc);
>> +	struct intel_crtc_state *crtc_state =
>> +		intel_atomic_get_new_crtc_state(state, crtc);
>> +	const struct drm_display_mode *adjusted_mode =
>> +		&crtc_state->hw.adjusted_mode;
>> +	struct skl_prefill_ctx prefill_ctx;
>> +	int prefill_framestart_delay = 1;
>> +	int prefill_min_guardband;
>> +	int prefill_latency_us;
>> +	int prefill_wm0_lines;
>> +	int prefill_sagv_us;
>> +	int psr_latency = 0;
>> +	int sdp_latency = 0;
>> +	int min_guardband;
>> +	int guardband;
>> +
>> +	skl_prefill_init(&prefill_ctx, crtc_state);
>> +	prefill_wm0_lines = skl_wm0_prefill_lines(crtc_state);
>> +	prefill_sagv_us = display->sagv.block_time_us;
>> +	prefill_latency_us = prefill_sagv_us +
>> +			     intel_scanlines_to_usecs(adjusted_mode,
>> +						      prefill_framestart_delay +
>> +						      prefill_wm0_lines);
> All of that should pretty much just be skl_prefill_init_worst()
>
>> +	prefill_min_guardband =
>> +		skl_prefill_min_guardband(&prefill_ctx,
>> +					  crtc_state,
>> +					  prefill_latency_us);
> The only question really is what use as the latency here.
> I think we want it to be:
>   max(sagv_block_time, skl_watermark_max_latency(1))
> which should guarantee that we get the max power savings.
>
>> +
>> +	if (intel_crtc_has_dp_encoder(crtc_state)) {
>> +		psr_latency = intel_psr_max_link_wake_latency(crtc_state);
>> +		sdp_latency = intel_dp_compute_sdp_latency(crtc_state);
>> +	}
>> +
>> +	min_guardband = max(sdp_latency, psr_latency);
>> +
>> +	min_guardband = max(min_guardband, prefill_min_guardband);
>> +
>> +	guardband = intel_crtc_vblank_length(crtc_state);
>> +
>> +	if (guardband < min_guardband) {
>> +		drm_dbg_kms(display->drm, "actual guardband: %d shorter than min guardband: %d\n",
>> +			    guardband, min_guardband);
>> +		return -EINVAL;
>> +	}
> I don't think we want to do any checks here. This whole thing
> should just be something like:
>
> guardband = prefill_min_guardband()
> guardband = max(guardband, psr_min_guardband())
> guardband = max(guardband, sdp_min_guardband())
>
> crtc_state->vrr.guardband = min(guardband, intel_vrr_max_guardband())
>
> And then we need to check the final value against
> sdp_min_guardband() in .compute_config_late() to make sure
> we got enough for the SDPs. So quite similar to PSR, except
> we just want .compute_config_late() to fail if we don't have
> enough for the SDPs.
>
> I think that should be good enough for now. It may force a modeset
> if the SDPs change though, so later we might want to think about
> using a better worst case estimate here, eg. assume HDR metadata may
> get enabled later, which we'd like to do without changing the guardband.
>
>> +
>> +	return 0;
>> +}
>> +
>>   static int intel_crtc_atomic_check(struct intel_atomic_state *state,
>>   				   struct intel_crtc *crtc)
>>   {
>> @@ -4253,6 +4305,10 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
>>   	if (ret)
>>   		return ret;
>>   
>> +	ret = intel_crtc_guardband_atomic_check(state, crtc);
>> +	if (ret)
>> +		return ret;
>> +
>>   	return 0;
>>   }
>>   
>> -- 
>> 2.45.2

✗ Xe.CI.Full: failure for Optimize vrr.guardband

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 50526 bytes --]

== Series Details ==

Series: Optimize vrr.guardband
URL   : https://patchwork.freedesktop.org/series/155979/
State : failure

== Summary ==

CI Bug Log - changes from xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554_FULL -> xe-pw-155979v1_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-155979v1_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-155979v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-155979v1_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0:
    - shard-adlp:         [PASS][1] -> [ABORT][2] +3 other tests abort
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-adlp-2/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-adlp-2/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0.html
    - shard-bmg:          NOTRUN -> [ABORT][3] +7 other tests abort
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-2/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0.html

  * igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc:
    - shard-adlp:         NOTRUN -> [ABORT][4] +6 other tests abort
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-adlp-2/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_cursor_legacy@forked-bo@pipe-c:
    - shard-lnl:          [PASS][5] -> [FAIL][6] +6 other tests fail
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-lnl-2/igt@kms_cursor_legacy@forked-bo@pipe-c.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-lnl-5/igt@kms_cursor_legacy@forked-bo@pipe-c.html

  * igt@kms_invalid_mode@uint-max-clock:
    - shard-lnl:          NOTRUN -> [ABORT][7] +4 other tests abort
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-lnl-4/igt@kms_invalid_mode@uint-max-clock.html

  * igt@kms_invalid_mode@uint-max-clock@pipe-a-dp-2:
    - shard-bmg:          [PASS][8] -> [ABORT][9] +21 other tests abort
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-bmg-3/igt@kms_invalid_mode@uint-max-clock@pipe-a-dp-2.html
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-3/igt@kms_invalid_mode@uint-max-clock@pipe-a-dp-2.html

  * igt@kms_pipe_crc_basic@nonblocking-crc:
    - shard-adlp:         [PASS][10] -> [FAIL][11] +4 other tests fail
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-adlp-6/igt@kms_pipe_crc_basic@nonblocking-crc.html
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-adlp-2/igt@kms_pipe_crc_basic@nonblocking-crc.html
    - shard-bmg:          [PASS][12] -> [FAIL][13] +18 other tests fail
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-bmg-5/igt@kms_pipe_crc_basic@nonblocking-crc.html
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-2/igt@kms_pipe_crc_basic@nonblocking-crc.html

  * igt@kms_plane_multiple@2x-tiling-4@pipe-a-dp-2-pipe-c-hdmi-a-3:
    - shard-bmg:          [PASS][14] -> [SKIP][15] +6 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-bmg-7/igt@kms_plane_multiple@2x-tiling-4@pipe-a-dp-2-pipe-c-hdmi-a-3.html
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-7/igt@kms_plane_multiple@2x-tiling-4@pipe-a-dp-2-pipe-c-hdmi-a-3.html

  * igt@kms_vrr@flip-basic:
    - shard-lnl:          [PASS][16] -> [ABORT][17] +26 other tests abort
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-lnl-4/igt@kms_vrr@flip-basic.html
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-lnl-3/igt@kms_vrr@flip-basic.html

  * igt@xe_gt_freq@freq_suspend:
    - shard-bmg:          [PASS][18] -> [INCOMPLETE][19] +1 other test incomplete
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-bmg-2/igt@xe_gt_freq@freq_suspend.html
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-6/igt@xe_gt_freq@freq_suspend.html

  
#### Warnings ####

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs:
    - shard-lnl:          [SKIP][20] ([Intel XE#3432]) -> [ABORT][21]
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-lnl-3/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs.html
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-lnl-3/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs.html

  * igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs:
    - shard-bmg:          [SKIP][22] ([Intel XE#2887]) -> [ABORT][23] +1 other test abort
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-bmg-4/igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs.html
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-5/igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs.html
    - shard-lnl:          [SKIP][24] ([Intel XE#2887]) -> [ABORT][25]
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-lnl-4/igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs.html
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-lnl-8/igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs:
    - shard-bmg:          [SKIP][26] ([Intel XE#2652] / [Intel XE#787]) -> [ABORT][27] +1 other test abort
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-bmg-4/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-1/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html

  * igt@kms_cdclk@plane-scaling:
    - shard-lnl:          [SKIP][28] ([Intel XE#4416]) -> [ABORT][29] +1 other test abort
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-lnl-7/igt@kms_cdclk@plane-scaling.html
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-lnl-5/igt@kms_cdclk@plane-scaling.html

  * igt@kms_dp_link_training@uhbr-sst:
    - shard-bmg:          [SKIP][30] ([Intel XE#4354]) -> [ABORT][31]
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-bmg-2/igt@kms_dp_link_training@uhbr-sst.html
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-8/igt@kms_dp_link_training@uhbr-sst.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf:
    - shard-lnl:          [SKIP][32] ([Intel XE#1406] / [Intel XE#2893] / [Intel XE#4608]) -> [FAIL][33]
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-lnl-1/igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf.html
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-lnl-8/igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf.html

  * igt@xe_pm@d3hot-mmap-vram:
    - shard-adlp:         [SKIP][34] ([Intel XE#1948]) -> [ABORT][35]
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-adlp-9/igt@xe_pm@d3hot-mmap-vram.html
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-adlp-1/igt@xe_pm@d3hot-mmap-vram.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@kms_async_flips@async-flip-dpms}:
    - shard-lnl:          [PASS][36] -> [ABORT][37]
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-lnl-7/igt@kms_async_flips@async-flip-dpms.html
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-lnl-1/igt@kms_async_flips@async-flip-dpms.html

  
New tests
---------

  New tests have been introduced between xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554_FULL and xe-pw-155979v1_FULL:

### New IGT tests (1) ###

  * igt@kms_chamelium_frames:
    - Statuses :
    - Exec time: [None] s

  

Known issues
------------

  Here are the changes found in xe-pw-155979v1_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_async_flips@test-time-stamp:
    - shard-bmg:          [PASS][38] -> [INCOMPLETE][39] ([Intel XE#4912])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-bmg-4/igt@kms_async_flips@test-time-stamp.html
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-4/igt@kms_async_flips@test-time-stamp.html

  * igt@kms_bw@connected-linear-tiling-1-displays-1920x1080p:
    - shard-bmg:          [PASS][40] -> [SKIP][41] ([Intel XE#367])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-bmg-8/igt@kms_bw@connected-linear-tiling-1-displays-1920x1080p.html
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-2/igt@kms_bw@connected-linear-tiling-1-displays-1920x1080p.html
    - shard-lnl:          [PASS][42] -> [SKIP][43] ([Intel XE#367])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-lnl-1/igt@kms_bw@connected-linear-tiling-1-displays-1920x1080p.html
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-lnl-3/igt@kms_bw@connected-linear-tiling-1-displays-1920x1080p.html

  * igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p:
    - shard-bmg:          [PASS][44] -> [SKIP][45] ([Intel XE#2314] / [Intel XE#2894])
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-bmg-1/igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p.html
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-6/igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p.html

  * igt@kms_bw@linear-tiling-3-displays-2160x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][46] ([Intel XE#367])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-1/igt@kms_bw@linear-tiling-3-displays-2160x1440p.html

  * igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-1:
    - shard-adlp:         NOTRUN -> [SKIP][47] ([Intel XE#787]) +1 other test skip
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-adlp-2/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-1.html

  * igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc@pipe-d-hdmi-a-1:
    - shard-adlp:         NOTRUN -> [SKIP][48] ([Intel XE#455] / [Intel XE#787])
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-adlp-2/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc@pipe-d-hdmi-a-1.html

  * igt@kms_cursor_crc@cursor-size-change@pipe-a-edp-1:
    - shard-lnl:          [PASS][49] -> [FAIL][50] ([Intel XE#4445])
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-lnl-2/igt@kms_cursor_crc@cursor-size-change@pipe-a-edp-1.html
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-lnl-2/igt@kms_cursor_crc@cursor-size-change@pipe-a-edp-1.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size:
    - shard-bmg:          [PASS][51] -> [INCOMPLETE][52] ([Intel XE#3226])
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-bmg-2/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-3/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic:
    - shard-lnl:          [PASS][53] -> [FAIL][54] ([Intel XE#4427])
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-lnl-5/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-lnl-4/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html

  * igt@kms_dp_link_training@uhbr-sst:
    - shard-adlp:         NOTRUN -> [SKIP][55] ([Intel XE#4356])
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-adlp-8/igt@kms_dp_link_training@uhbr-sst.html

  * igt@kms_flip@2x-busy-flip:
    - shard-bmg:          [PASS][56] -> [SKIP][57] ([Intel XE#2316])
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-bmg-2/igt@kms_flip@2x-busy-flip.html
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-6/igt@kms_flip@2x-busy-flip.html

  * igt@kms_flip@2x-flip-vs-wf_vblank:
    - shard-adlp:         NOTRUN -> [SKIP][58] ([Intel XE#310]) +1 other test skip
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-adlp-2/igt@kms_flip@2x-flip-vs-wf_vblank.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-shrfb-plflip-blt:
    - shard-adlp:         NOTRUN -> [SKIP][59] ([Intel XE#651])
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-adlp-6/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-shrfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-move:
    - shard-bmg:          NOTRUN -> [SKIP][60] ([Intel XE#2311])
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc:
    - shard-adlp:         NOTRUN -> [SKIP][61] ([Intel XE#653]) +1 other test skip
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-adlp-9/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][62] ([Intel XE#2313]) +2 other tests skip
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-blt:
    - shard-adlp:         NOTRUN -> [SKIP][63] ([Intel XE#656])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-adlp-6/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-blt.html

  * igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][64] ([Intel XE#4090])
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-8/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html
    - shard-adlp:         NOTRUN -> [SKIP][65] ([Intel XE#2925])
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-adlp-6/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html

  * igt@kms_plane@plane-panning-top-left:
    - shard-bmg:          [PASS][66] -> [SKIP][67] ([Intel XE#5377])
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-bmg-4/igt@kms_plane@plane-panning-top-left.html
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-6/igt@kms_plane@plane-panning-top-left.html

  * igt@kms_plane_multiple@2x-tiling-4:
    - shard-adlp:         NOTRUN -> [SKIP][68] ([Intel XE#4596])
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-adlp-9/igt@kms_plane_multiple@2x-tiling-4.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-75-with-modifiers@pipe-a:
    - shard-lnl:          [PASS][69] -> [SKIP][70] ([Intel XE#2763]) +2 other tests skip
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-lnl-2/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-modifiers@pipe-a.html
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-lnl-4/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-modifiers@pipe-a.html

  * igt@kms_psr@pr-sprite-blt:
    - shard-bmg:          NOTRUN -> [SKIP][71] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850])
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-6/igt@kms_psr@pr-sprite-blt.html

  * igt@xe_eu_stall@non-blocking-re-enable:
    - shard-adlp:         NOTRUN -> [SKIP][72] ([Intel XE#5626])
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-adlp-2/igt@xe_eu_stall@non-blocking-re-enable.html

  * igt@xe_eudebug@basic-vm-access-parameters-faultable:
    - shard-adlp:         NOTRUN -> [SKIP][73] ([Intel XE#4837] / [Intel XE#5565])
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-adlp-9/igt@xe_eudebug@basic-vm-access-parameters-faultable.html

  * igt@xe_eudebug_online@writes-caching-vram-bb-vram-target-sram:
    - shard-bmg:          NOTRUN -> [SKIP][74] ([Intel XE#4837])
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-3/igt@xe_eudebug_online@writes-caching-vram-bb-vram-target-sram.html

  * igt@xe_evict@evict-cm-threads-large-multi-vm:
    - shard-adlp:         NOTRUN -> [SKIP][75] ([Intel XE#261])
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-adlp-6/igt@xe_evict@evict-cm-threads-large-multi-vm.html

  * igt@xe_exec_basic@multigpu-no-exec-null-defer-mmap:
    - shard-adlp:         NOTRUN -> [SKIP][76] ([Intel XE#1392] / [Intel XE#5575])
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-adlp-1/igt@xe_exec_basic@multigpu-no-exec-null-defer-mmap.html

  * igt@xe_exec_system_allocator@many-execqueues-mmap-new-huge-nomemset:
    - shard-lnl:          NOTRUN -> [SKIP][77] ([Intel XE#4943])
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-lnl-4/igt@xe_exec_system_allocator@many-execqueues-mmap-new-huge-nomemset.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-execqueues-free-nomemset:
    - shard-adlp:         NOTRUN -> [SKIP][78] ([Intel XE#4915]) +4 other tests skip
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-adlp-1/igt@xe_exec_system_allocator@threads-shared-vm-many-execqueues-free-nomemset.html

  * igt@xe_pm@d3hot-mmap-vram:
    - shard-bmg:          [PASS][79] -> [FAIL][80] ([Intel XE#6301])
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-bmg-5/igt@xe_pm@d3hot-mmap-vram.html
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-6/igt@xe_pm@d3hot-mmap-vram.html

  * igt@xe_pm@s2idle-vm-bind-userptr:
    - shard-bmg:          [PASS][81] -> [INCOMPLETE][82] ([Intel XE#4504])
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-bmg-5/igt@xe_pm@s2idle-vm-bind-userptr.html
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-2/igt@xe_pm@s2idle-vm-bind-userptr.html
    - shard-adlp:         [PASS][83] -> [INCOMPLETE][84] ([Intel XE#4504])
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-adlp-6/igt@xe_pm@s2idle-vm-bind-userptr.html
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-adlp-1/igt@xe_pm@s2idle-vm-bind-userptr.html
    - shard-lnl:          [PASS][85] -> [INCOMPLETE][86] ([Intel XE#4504])
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-lnl-1/igt@xe_pm@s2idle-vm-bind-userptr.html
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-lnl-5/igt@xe_pm@s2idle-vm-bind-userptr.html

  * igt@xe_pxp@pxp-stale-bo-exec-post-rpm:
    - shard-bmg:          NOTRUN -> [SKIP][87] ([Intel XE#4733])
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-6/igt@xe_pxp@pxp-stale-bo-exec-post-rpm.html

  
#### Possible fixes ####

  * igt@xe_module_load@load:
    - shard-lnl:          ([PASS][88], [PASS][89], [PASS][90], [SKIP][91], [PASS][92], [PASS][93], [PASS][94], [PASS][95], [PASS][96], [PASS][97], [PASS][98], [PASS][99], [PASS][100], [PASS][101], [PASS][102], [PASS][103], [PASS][104], [PASS][105], [PASS][106], [PASS][107], [PASS][108], [PASS][109], [PASS][110], [PASS][111], [PASS][112], [PASS][113]) ([Intel XE#378]) -> ([PASS][114], [PASS][115], [PASS][116], [PASS][117], [PASS][118], [PASS][119], [PASS][120], [PASS][121], [PASS][122], [PASS][123], [PASS][124], [PASS][125], [PASS][126], [PASS][127], [PASS][128], [PASS][129], [PASS][130], [PASS][131], [PASS][132], [PASS][133], [PASS][134], [PASS][135], [PASS][136], [PASS][137], [PASS][138])
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-lnl-7/igt@xe_module_load@load.html
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-lnl-8/igt@xe_module_load@load.html
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-lnl-7/igt@xe_module_load@load.html
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-lnl-8/igt@xe_module_load@load.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-lnl-4/igt@xe_module_load@load.html
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-lnl-4/igt@xe_module_load@load.html
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-lnl-4/igt@xe_module_load@load.html
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-lnl-8/igt@xe_module_load@load.html
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-lnl-8/igt@xe_module_load@load.html
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-lnl-7/igt@xe_module_load@load.html
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-lnl-4/igt@xe_module_load@load.html
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-lnl-7/igt@xe_module_load@load.html
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-lnl-5/igt@xe_module_load@load.html
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-lnl-5/igt@xe_module_load@load.html
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-lnl-5/igt@xe_module_load@load.html
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-lnl-2/igt@xe_module_load@load.html
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-lnl-5/igt@xe_module_load@load.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-lnl-2/igt@xe_module_load@load.html
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-lnl-2/igt@xe_module_load@load.html
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-lnl-2/igt@xe_module_load@load.html
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-lnl-1/igt@xe_module_load@load.html
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-lnl-3/igt@xe_module_load@load.html
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-lnl-1/igt@xe_module_load@load.html
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-lnl-1/igt@xe_module_load@load.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-lnl-3/igt@xe_module_load@load.html
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-lnl-3/igt@xe_module_load@load.html
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-lnl-3/igt@xe_module_load@load.html
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-lnl-2/igt@xe_module_load@load.html
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-lnl-2/igt@xe_module_load@load.html
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-lnl-5/igt@xe_module_load@load.html
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-lnl-8/igt@xe_module_load@load.html
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-lnl-8/igt@xe_module_load@load.html
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-lnl-8/igt@xe_module_load@load.html
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-lnl-7/igt@xe_module_load@load.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-lnl-3/igt@xe_module_load@load.html
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-lnl-7/igt@xe_module_load@load.html
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-lnl-1/igt@xe_module_load@load.html
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-lnl-4/igt@xe_module_load@load.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-lnl-2/igt@xe_module_load@load.html
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-lnl-4/igt@xe_module_load@load.html
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-lnl-4/igt@xe_module_load@load.html
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-lnl-4/igt@xe_module_load@load.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-lnl-1/igt@xe_module_load@load.html
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-lnl-8/igt@xe_module_load@load.html
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-lnl-7/igt@xe_module_load@load.html
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-lnl-5/igt@xe_module_load@load.html
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-lnl-5/igt@xe_module_load@load.html
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-lnl-5/igt@xe_module_load@load.html
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-lnl-1/igt@xe_module_load@load.html
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-lnl-3/igt@xe_module_load@load.html
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-lnl-3/igt@xe_module_load@load.html
    - shard-bmg:          ([PASS][139], [PASS][140], [PASS][141], [PASS][142], [PASS][143], [SKIP][144], [PASS][145], [PASS][146], [PASS][147], [PASS][148], [PASS][149], [PASS][150], [PASS][151], [PASS][152], [PASS][153], [PASS][154], [PASS][155], [PASS][156], [PASS][157], [PASS][158], [PASS][159], [PASS][160], [PASS][161], [PASS][162], [PASS][163], [PASS][164]) ([Intel XE#2457]) -> ([PASS][165], [PASS][166], [PASS][167], [PASS][168], [PASS][169], [PASS][170], [PASS][171], [PASS][172], [PASS][173], [PASS][174], [PASS][175], [PASS][176], [PASS][177], [PASS][178], [PASS][179], [PASS][180], [PASS][181], [PASS][182], [PASS][183], [PASS][184], [PASS][185], [PASS][186], [PASS][187], [PASS][188], [PASS][189])
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-bmg-1/igt@xe_module_load@load.html
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-bmg-7/igt@xe_module_load@load.html
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-bmg-7/igt@xe_module_load@load.html
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-bmg-7/igt@xe_module_load@load.html
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-bmg-4/igt@xe_module_load@load.html
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-bmg-3/igt@xe_module_load@load.html
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-bmg-3/igt@xe_module_load@load.html
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-bmg-3/igt@xe_module_load@load.html
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-bmg-1/igt@xe_module_load@load.html
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-bmg-1/igt@xe_module_load@load.html
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-bmg-4/igt@xe_module_load@load.html
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-bmg-4/igt@xe_module_load@load.html
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-bmg-4/igt@xe_module_load@load.html
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-bmg-3/igt@xe_module_load@load.html
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-bmg-2/igt@xe_module_load@load.html
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-bmg-6/igt@xe_module_load@load.html
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-bmg-2/igt@xe_module_load@load.html
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-bmg-2/igt@xe_module_load@load.html
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-bmg-8/igt@xe_module_load@load.html
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-bmg-2/igt@xe_module_load@load.html
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-bmg-5/igt@xe_module_load@load.html
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-bmg-5/igt@xe_module_load@load.html
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-bmg-5/igt@xe_module_load@load.html
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-bmg-6/igt@xe_module_load@load.html
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-bmg-8/igt@xe_module_load@load.html
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-bmg-6/igt@xe_module_load@load.html
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-4/igt@xe_module_load@load.html
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-1/igt@xe_module_load@load.html
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-3/igt@xe_module_load@load.html
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-7/igt@xe_module_load@load.html
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-2/igt@xe_module_load@load.html
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-4/igt@xe_module_load@load.html
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-4/igt@xe_module_load@load.html
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-8/igt@xe_module_load@load.html
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-8/igt@xe_module_load@load.html
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-8/igt@xe_module_load@load.html
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-2/igt@xe_module_load@load.html
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-7/igt@xe_module_load@load.html
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-7/igt@xe_module_load@load.html
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-6/igt@xe_module_load@load.html
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-5/igt@xe_module_load@load.html
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-6/igt@xe_module_load@load.html
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-6/igt@xe_module_load@load.html
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-6/igt@xe_module_load@load.html
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-5/igt@xe_module_load@load.html
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-1/igt@xe_module_load@load.html
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-3/igt@xe_module_load@load.html
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-3/igt@xe_module_load@load.html
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-2/igt@xe_module_load@load.html
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-5/igt@xe_module_load@load.html
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-1/igt@xe_module_load@load.html
    - shard-adlp:         ([PASS][190], [PASS][191], [PASS][192], [PASS][193], [SKIP][194], [PASS][195], [PASS][196], [PASS][197], [PASS][198], [PASS][199], [PASS][200], [PASS][201], [PASS][202], [PASS][203], [PASS][204]) ([Intel XE#378] / [Intel XE#5612]) -> ([PASS][205], [PASS][206], [PASS][207], [PASS][208], [PASS][209], [PASS][210], [PASS][211], [PASS][212], [PASS][213], [PASS][214], [PASS][215])
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-adlp-6/igt@xe_module_load@load.html
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-adlp-6/igt@xe_module_load@load.html
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-adlp-6/igt@xe_module_load@load.html
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-adlp-9/igt@xe_module_load@load.html
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-adlp-9/igt@xe_module_load@load.html
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-adlp-1/igt@xe_module_load@load.html
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-adlp-1/igt@xe_module_load@load.html
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-adlp-9/igt@xe_module_load@load.html
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-adlp-9/igt@xe_module_load@load.html
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-adlp-8/igt@xe_module_load@load.html
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-adlp-8/igt@xe_module_load@load.html
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-adlp-8/igt@xe_module_load@load.html
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-adlp-2/igt@xe_module_load@load.html
   [203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-adlp-2/igt@xe_module_load@load.html
   [204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-adlp-1/igt@xe_module_load@load.html
   [205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-adlp-6/igt@xe_module_load@load.html
   [206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-adlp-9/igt@xe_module_load@load.html
   [207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-adlp-2/igt@xe_module_load@load.html
   [208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-adlp-8/igt@xe_module_load@load.html
   [209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-adlp-2/igt@xe_module_load@load.html
   [210]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-adlp-8/igt@xe_module_load@load.html
   [211]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-adlp-1/igt@xe_module_load@load.html
   [212]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-adlp-1/igt@xe_module_load@load.html
   [213]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-adlp-1/igt@xe_module_load@load.html
   [214]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-adlp-9/igt@xe_module_load@load.html
   [215]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-adlp-6/igt@xe_module_load@load.html

  
#### Warnings ####

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-plflip-blt:
    - shard-bmg:          [SKIP][216] ([Intel XE#5390]) -> [SKIP][217] ([Intel XE#2312])
   [216]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-plflip-blt.html
   [217]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-plflip-blt.html

  * igt@xe_module_load@load:
    - shard-dg2-set2:     ([SKIP][218], [PASS][219], [PASS][220], [PASS][221], [PASS][222], [PASS][223], [PASS][224], [PASS][225], [PASS][226], [PASS][227], [PASS][228], [PASS][229], [PASS][230], [PASS][231], [PASS][232], [PASS][233], [PASS][234], [PASS][235], [PASS][236], [PASS][237], [PASS][238], [PASS][239], [PASS][240], [PASS][241], [PASS][242]) ([Intel XE#378]) -> ([ABORT][243], [ABORT][244], [ABORT][245], [ABORT][246], [ABORT][247], [ABORT][248], [ABORT][249], [ABORT][250], [ABORT][251], [ABORT][252], [ABORT][253], [ABORT][254], [ABORT][255], [ABORT][256], [ABORT][257], [ABORT][258], [ABORT][259], [ABORT][260], [ABORT][261], [ABORT][262], [ABORT][263], [ABORT][264], [ABORT][265], [ABORT][266], [ABORT][267]) ([Intel XE#5087])
   [218]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-dg2-432/igt@xe_module_load@load.html
   [219]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-dg2-434/igt@xe_module_load@load.html
   [220]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-dg2-434/igt@xe_module_load@load.html
   [221]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-dg2-432/igt@xe_module_load@load.html
   [222]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-dg2-434/igt@xe_module_load@load.html
   [223]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554/shard-dg2-435/igt@xe_module_load@load.html
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   [267]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/shard-dg2-432/igt@xe_module_load@load.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1948]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1948
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2457]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2457
  [Intel XE#261]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/261
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
  [Intel XE#2925]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2925
  [Intel XE#310]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/310
  [Intel XE#3226]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3226
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
  [Intel XE#4090]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4090
  [Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
  [Intel XE#4356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4356
  [Intel XE#4416]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4416
  [Intel XE#4427]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4427
  [Intel XE#4445]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4445
  [Intel XE#4504]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4504
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
  [Intel XE#4608]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4608
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#4912]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4912
  [Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
  [Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
  [Intel XE#5087]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5087
  [Intel XE#5377]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5377
  [Intel XE#5390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5390
  [Intel XE#5565]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5565
  [Intel XE#5575]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5575
  [Intel XE#5612]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5612
  [Intel XE#5626]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5626
  [Intel XE#6301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6301
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787


Build changes
-------------

  * IGT: IGT_8585 -> IGT_8586
  * Linux: xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554 -> xe-pw-155979v1

  IGT_8585: 8585
  IGT_8586: dbda1336c5c99d0faa88397d5c312be72301cd94 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-3925-ed00bdb0008276b3497a4c811e160f18d1218554: ed00bdb0008276b3497a4c811e160f18d1218554
  xe-pw-155979v1: 155979v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v1/index.html

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