From: "Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com>
To: "Jouni Högander" <jouni.hogander@intel.com>,
intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Cc: <stable@vger.kernel.org>
Subject: Re: [PATCH v2 1/4] drm/i915/psr: Repeat Selective Update area alignment
Date: Wed, 4 Mar 2026 13:14:56 +0530 [thread overview]
Message-ID: <8eaea8de-23cd-48ca-81e0-896815adfbb6@intel.com> (raw)
In-Reply-To: <20260303125409.503148-2-jouni.hogander@intel.com>
On 3/3/2026 6:24 PM, Jouni Högander wrote:
> Currently we are aligning Selective Update area to cover cursor fully if
> needed only once. It may happen that cursor is in Selective Update area
> after pipe alignment and after that covering cursor plane only
> partially. Fix this by looping alignment as long as alignment isn't needed
> anymore.
>
> v2:
> - do not unecessarily loop if cursor was already fully covered
> - rename aligned as su_area_changed
>
> Fixes: 1bff93b8bc27 ("drm/i915/psr: Extend SU area to cover cursor fully if needed")
> Cc: <stable@vger.kernel.org> # v6.9+
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 50 ++++++++++++++++++------
> 1 file changed, 38 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 5bea2eda744b..7b197e84e77d 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -2688,11 +2688,12 @@ static void clip_area_update(struct drm_rect *overlap_damage_area,
> overlap_damage_area->y2 = damage_area->y2;
> }
>
> -static void intel_psr2_sel_fetch_pipe_alignment(struct intel_crtc_state *crtc_state)
> +static bool intel_psr2_sel_fetch_pipe_alignment(struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
> const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
> u16 y_alignment;
> + bool su_area_changed = false;
>
> /* ADLP aligns the SU region to vdsc slice height in case dsc is enabled */
> if (crtc_state->dsc.compression_enable &&
> @@ -2701,10 +2702,18 @@ static void intel_psr2_sel_fetch_pipe_alignment(struct intel_crtc_state *crtc_st
> else
> y_alignment = crtc_state->su_y_granularity;
>
> - crtc_state->psr2_su_area.y1 -= crtc_state->psr2_su_area.y1 % y_alignment;
> - if (crtc_state->psr2_su_area.y2 % y_alignment)
> + if (crtc_state->psr2_su_area.y1 % y_alignment) {
> + crtc_state->psr2_su_area.y1 -= crtc_state->psr2_su_area.y1 % y_alignment;
> + su_area_changed = true;
> + }
> +
> + if (crtc_state->psr2_su_area.y2 % y_alignment) {
> crtc_state->psr2_su_area.y2 = ((crtc_state->psr2_su_area.y2 /
> y_alignment) + 1) * y_alignment;
> + su_area_changed = true;
> + }
> +
> + return su_area_changed;
> }
>
> /*
> @@ -2838,7 +2847,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
> struct intel_plane_state *new_plane_state, *old_plane_state;
> struct intel_plane *plane;
> - bool full_update = false, cursor_in_su_area = false;
> + bool full_update = false, su_area_changed;
> int i, ret;
>
> if (!crtc_state->enable_psr2_sel_fetch)
> @@ -2945,15 +2954,32 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> if (ret)
> return ret;
>
> - /*
> - * Adjust su area to cover cursor fully as necessary (early
> - * transport). This needs to be done after
> - * drm_atomic_add_affected_planes to ensure visible cursor is added into
> - * affected planes even when cursor is not updated by itself.
> - */
> - intel_psr2_sel_fetch_et_alignment(state, crtc, &cursor_in_su_area);
> + do {
> + bool cursor_in_su_area;
>
> - intel_psr2_sel_fetch_pipe_alignment(crtc_state);
> + /*
> + * Adjust su area to cover cursor fully as necessary
> + * (early transport). This needs to be done after
> + * drm_atomic_add_affected_planes to ensure visible
> + * cursor is added into affected planes even when
> + * cursor is not updated by itself.
> + */
> + intel_psr2_sel_fetch_et_alignment(state, crtc, &cursor_in_su_area);
> +
> + su_area_changed = intel_psr2_sel_fetch_pipe_alignment(crtc_state);
> +
> + /*
> + * If the cursor was outside the SU area before
> + * alignment, the alignment step (which only expands
> + * SU) may pull the cursor partially inside, so we
> + * must run ET alignment again to fully cover it. But
> + * if the cursor was already fully inside before
> + * alignment, expanding the SU area won't change that,
> + * so no further work is needed.
> + */
> + if (cursor_in_su_area)
> + break;
> + } while (su_area_changed);
>
> /*
> * Now that we have the pipe damaged area check if it intersect with
next prev parent reply other threads:[~2026-03-04 7:45 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-03 12:54 [PATCH v2 0/4] PSR/PR Selective Fetch Early Transport fixes Jouni Högander
2026-03-03 12:54 ` [PATCH v2 1/4] drm/i915/psr: Repeat Selective Update area alignment Jouni Högander
2026-03-04 7:44 ` Nautiyal, Ankit K [this message]
2026-03-03 12:54 ` [PATCH v2 2/4] drm/i915/dsc: Add Selective Update register definitions Jouni Högander
2026-03-04 7:56 ` Nautiyal, Ankit K
2026-03-03 12:54 ` [PATCH v2 3/4] drm/i915/dsc: Add helper for writing DSC Selective Update ET parameters Jouni Högander
2026-03-04 8:36 ` Nautiyal, Ankit K
2026-03-04 9:13 ` Hogander, Jouni
2026-03-04 10:26 ` Nautiyal, Ankit K
2026-03-04 10:44 ` Hogander, Jouni
2026-03-03 12:54 ` [PATCH v2 4/4] drm/i915/psr: Write DSC parameters on Selective Update in ET mode Jouni Högander
2026-03-04 10:28 ` Nautiyal, Ankit K
2026-03-03 14:23 ` ✗ CI.checkpatch: warning for PSR/PR Selective Fetch Early Transport fixes (rev2) Patchwork
2026-03-03 14:24 ` ✓ CI.KUnit: success " Patchwork
2026-03-03 15:20 ` ✓ Xe.CI.BAT: " Patchwork
2026-03-04 1:53 ` ✗ Xe.CI.FULL: failure " Patchwork
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