Re: [PATCH v2 4/4] drm/i915/psr: Write DSC parameters on Selective Update in ET mode

["Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com>]

On 3/3/2026 6:24 PM, Jouni Högander wrote:
> There are slice row per frame and pic height parameters in DSC that needs
> to be configured on every Selective Update in Early Transport mode. Use
> helper provided by DSC code to configure these on Selective Update when in
> Early Transport mode. Also fill crtc_state->psr2_su_area with full frame
> area on full frame update for DSC calculation.
>
> Bspec: 68927, 71709
> Fixes: 467e4e061c44 ("drm/i915/psr: Enable psr2 early transport as possible")
> Cc: <stable@vger.kernel.org> # v6.9+
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>

LGTM.

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

> ---
>   drivers/gpu/drm/i915/display/intel_psr.c | 11 ++++++++++-
>   1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 7b197e84e77d..adcfd3dd8f20 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -2618,6 +2618,12 @@ void intel_psr2_program_trans_man_trk_ctl(struct intel_dsb *dsb,
>   
>   	intel_de_write_dsb(display, dsb, PIPE_SRCSZ_ERLY_TPT(crtc->pipe),
>   			   crtc_state->pipe_srcsz_early_tpt);
> +
> +	if (!crtc_state->dsc.compression_enable)
> +		return;
> +
> +	intel_dsc_su_et_parameters_configure(dsb, encoder, crtc_state,
> +					     drm_rect_height(&crtc_state->psr2_su_area));
>   }
>   
>   static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
> @@ -2945,8 +2951,11 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>   		full_update = true;
>   	}
>   
> -	if (full_update)
> +	if (full_update) {
> +		clip_area_update(&crtc_state->psr2_su_area, &crtc_state->pipe_src,
> +				 &crtc_state->pipe_src);
>   		goto skip_sel_fetch_set_loop;
> +	}
>   
>   	intel_psr_apply_su_area_workarounds(crtc_state);
>