* [PATCH v7 0/1] drm/xe/guc_ads: allocate UM queues in a separate UC BO
@ 2026-08-03 20:08 Jia Yao
2026-08-03 20:08 ` [PATCH v7 1/3] drm/xe/guc_ads: allocate UM queues in a separate BO Jia Yao
` (5 more replies)
0 siblings, 6 replies; 14+ messages in thread
From: Jia Yao @ 2026-08-03 20:08 UTC (permalink / raw)
To: intel-xe; +Cc: Jia Yao
== Problem ==
On platforms with Unified Shared Memory (USM), the xe driver maintains
three hardware page-fault queues (PAGE_FAULT, PAGE_FAULT_RESPONSE,
ACCESS_COUNTER) inside the GuC Additional Data Structures (ADS) blob.
xe_guc_ads_populate() is called on every GT reset to reprogram the ADS
blob; it begins with a full memset() of the blob to zero.
GAM hardware writes fault descriptors to the queue via DPA - a
non-coherent path that bypasses the cache and writes directly to memory.
GuC reads the queue via GGTT (WB), which hit the cacheline polluted by CPU.
As a result GuC sees the stale zeroed data from the cache instead
of the descriptor written to DRAM by GAM. The driver then receives an
all-zero fault descriptor and returns -EINVAL, causing an unnecessary
engine reset.
This is documented in HSD as:
"When Fault queue is updated by the SW (Buffer zeroed), it can reside
in the CPU cache (L4:WB). A non coherent write from GAM HW would not
consult the CPU cache and it will eventually get written into the
memory (depends upon eviction/flushes) and CPU cache has stale data.
When GUC HW reads the fault queue it gets it from the CPU cache,
which is stale data."
== Reproduction ==
# Requires a platform with has_usm (e.g. Xe3 iGFX)
sudo xe_exec_reset --run-subtest gt-reset
sudo xe_exec_system_allocator \
--run-subtest threads-many-execqueues-mmap-new-race
Symptom in dmesg:
[xe] ASID: 0, Faulted Address: 0x0000000000000000, FaultType: 0
The all-zero fault descriptor is the tell-tale sign of the stale
cacheline race.
== Fix ==
Move the UM queues into a dedicated UC BO (ads->um_queue_bo) and avoid
CPU memset operations on it, which eliminates the CPU as a potential
cacheline-polluting agent and helps maintain consistency between GAM
writes and GuC reads.
On iGPU, the UM queue BO is allocated in system memory. On dGFX, the BO
was previously created in system memory and later reallocated in
xe_guc_realloc_post_hwconfig(). Allocate the UM queue BO directly in
VRAM on dGFX, where it is ultimately required.
On Pre-Xe3p platform, the GAM write the UM queue through DPA using UC.
if GuC reads the queue via GGTT (WB), stale data may be observed
when the cacheline has been polluted by another agent.
Why not just flush the cache after memset?
An earlier approach called drm_clflush_virt_range() on the UM queue
region immediately after the memset to evict the stale zero lines from
LLC. This reduces the failure rate significantly but does not fully
eliminate the race for two reasons.
First, the Linux kernel maintains a WB direct mapping (linear map) that
covers all physical memory. Even after flushing the vmap alias, the
CPU can speculatively prefetch the same physical page through the WB
direct-map alias, silently repopulating the cache with zeros. LNL is
known to be particularly susceptible to this speculative prefetch
behaviour. XE_BO_FLAG_NEEDS_UC calls set_memory_uc() which updates
both the vmap PTE and the direct-map PTE to UC, closing this aliasing
window entirely.
Second, the flush approach leaves the memory mapped WB on the CPU side
permanently. Any future SW access - a debug read, a tracing hook, an
inadvertent touch - can re-dirty the cacheline and reintroduce the
race. UC mapping makes the correct behaviour unconditional and
self-documenting.
Changes in v4:
- Split the single v3 patch into three logically independent patches:
1. Separate BO allocation
2. VRAM placement on dGFX
3. UC mapping
Changes in v5:
- Fix the patch conflict
- Update the ASCII block diagram of ads
- Simplify the contiguous memory check
- Improve code comments
Changes in v6:
- Only round up UM queue size for iGPU
- Revise commit message
Changes in v7:
- Move specify round-up only on iGPU from patch 1 to patch 2
Jia Yao (3):
drm/xe/guc_ads: allocate UM queues in a separate BO
drm/xe/guc_ads: allocate UM queues in VRAM on dGFX
drm/xe/guc_ads: use uncached mapping for UM queue BO
drivers/gpu/drm/xe/xe_guc_ads.c | 100 +++++++++++++++++---------
drivers/gpu/drm/xe/xe_guc_ads_types.h | 5 ++
2 files changed, 73 insertions(+), 32 deletions(-)
--
2.43.0
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v7 1/3] drm/xe/guc_ads: allocate UM queues in a separate BO
2026-08-03 20:08 [PATCH v7 0/1] drm/xe/guc_ads: allocate UM queues in a separate UC BO Jia Yao
@ 2026-08-03 20:08 ` Jia Yao
2026-08-04 7:43 ` Matthew Auld
2026-08-04 8:00 ` Matthew Auld
2026-08-03 20:08 ` [PATCH v7 2/3] drm/xe/guc_ads: allocate UM queues in VRAM on dGFX Jia Yao
` (4 subsequent siblings)
5 siblings, 2 replies; 14+ messages in thread
From: Jia Yao @ 2026-08-03 20:08 UTC (permalink / raw)
To: intel-xe; +Cc: Jia Yao, Gwan-gyeong Mun, Matthew Auld, stable
Move the UM queues into a dedicated UC BO (ads->um_queue_bo) and avoid
CPU memset operations on it, which eliminates the CPU as a potential
cacheline-polluting agent and helps maintain consistency between GAM
writes and GuC reads.
Fixes: 9c57bc08652a ("drm/xe/lnl: Drop force_probe requirement")
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: <stable@vger.kernel.org> # v6.12+
Signed-off-by: Jia Yao <jia.yao@intel.com>
---
drivers/gpu/drm/xe/xe_guc.c | 6 ++
drivers/gpu/drm/xe/xe_guc_ads.c | 89 +++++++++++++++++----------
drivers/gpu/drm/xe/xe_guc_ads_types.h | 5 ++
3 files changed, 68 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index 4286bd05c686..4f132bf8539d 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -732,6 +732,12 @@ static int xe_guc_realloc_post_hwconfig(struct xe_guc *guc)
if (ret)
return ret;
+ if (guc->ads.um_queue_bo) {
+ ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->ads.um_queue_bo);
+ if (ret)
+ return ret;
+ }
+
return 0;
}
diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index f0ac00586d3a..ef8e9cc35c8c 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -8,6 +8,7 @@
#include <linux/fault-inject.h>
#include <drm/drm_managed.h>
+#include <drm/drm_prime.h>
#include <generated/xe_wa_oob.h>
@@ -64,10 +65,14 @@ ads_to_map(struct xe_guc_ads *ads)
/*
* The Additional Data Struct (ADS) has pointers for different buffers used by
- * the GuC. One single gem object contains the ADS struct itself (guc_ads) and
- * all the extra buffers indirectly linked via the ADS struct's entries.
+ * the GuC. One gem object (ads->bo) contains the ADS struct itself (guc_ads)
+ * and most of the extra buffers linked via the ADS struct's entries. The UM
+ * fault queues (PAGE_FAULT, PAGE_FAULT_RESPONSE, ACCESS_COUNTER rings) are
+ * kept in a separate BO (ads->um_queue_bo) so that the full memset of ads->bo
+ * performed on every GT reset does not discard fault descriptors already
+ * written into the rings by the GPU.
*
- * Layout of the ADS blob allocated for the GuC:
+ * Layout of the ADS blob (ads->bo):
*
* +---------------------------------------+ <== base
* | guc_ads |
@@ -99,10 +104,6 @@ ads_to_map(struct xe_guc_ads *ads)
* +---------------------------------------+
* | padding |
* +---------------------------------------+ <== 4K aligned
- * | UM queues |
- * +---------------------------------------+
- * | padding |
- * +---------------------------------------+ <== 4K aligned
* | private data |
* +---------------------------------------+
* | padding |
@@ -156,16 +157,6 @@ static size_t guc_ads_capture_size(struct xe_guc_ads *ads)
return PAGE_ALIGN(ads->capture_size);
}
-static size_t guc_ads_um_queues_size(struct xe_guc_ads *ads)
-{
- struct xe_device *xe = ads_to_xe(ads);
-
- if (!xe->info.has_usm)
- return 0;
-
- return GUC_UM_QUEUE_SIZE * GUC_UM_HW_QUEUE_MAX;
-}
-
static size_t guc_ads_private_data_size(struct xe_guc_ads *ads)
{
return PAGE_ALIGN(ads_to_guc(ads)->fw.private_data_size);
@@ -206,22 +197,12 @@ static size_t guc_ads_capture_offset(struct xe_guc_ads *ads)
return PAGE_ALIGN(offset);
}
-static size_t guc_ads_um_queues_offset(struct xe_guc_ads *ads)
-{
- u32 offset;
-
- offset = guc_ads_capture_offset(ads) +
- guc_ads_capture_size(ads);
-
- return PAGE_ALIGN(offset);
-}
-
static size_t guc_ads_private_data_offset(struct xe_guc_ads *ads)
{
size_t offset;
- offset = guc_ads_um_queues_offset(ads) +
- guc_ads_um_queues_size(ads);
+ offset = guc_ads_capture_offset(ads) +
+ guc_ads_capture_size(ads);
return PAGE_ALIGN(offset);
}
@@ -461,6 +442,44 @@ int xe_guc_ads_init(struct xe_guc_ads *ads)
ads->bo = bo;
+ if (xe->info.has_usm) {
+ /*
+ * Allocate a separate BO for the HW fault ring (UM queues).
+ *
+ * Round the size up to the next power of two so that
+ * (system memory, no IOMMU) the TTM pool issues a single
+ * alloc_pages(order=N) call, maximising the chance of getting
+ * a physically contiguous block. GuC requires contiguous DPA.
+ */
+ size_t um_size = roundup_pow_of_two(GUC_UM_QUEUE_SIZE *
+ GUC_UM_HW_QUEUE_MAX);
+
+ bo = xe_managed_bo_create_pin_map(xe, tile, um_size,
+ XE_BO_FLAG_SYSTEM |
+ XE_BO_FLAG_GGTT |
+ XE_BO_FLAG_GGTT_INVALIDATE |
+ XE_BO_FLAG_PINNED_NORESTORE);
+ if (IS_ERR(bo))
+ return PTR_ERR(bo);
+
+ /*
+ * On pre-Xe3p platforms, GAM (not GuC) accesses the UM queue
+ * ring via base_dpa, which must be a contiguous DMA address
+ * range. Verify that the allocated pages are contiguous in
+ * DMA address space.
+ */
+ if (xe_bo_sg(bo) &&
+ !xe_guc_using_main_gamctrl_queues(ads_to_guc(ads)) &&
+ unlikely(drm_prime_get_contiguous_size(xe_bo_sg(bo)) <
+ GUC_UM_QUEUE_SIZE * GUC_UM_HW_QUEUE_MAX)) {
+ drm_err(&xe->drm,
+ "UM fault queue memory is not contiguous in DMA address space; GAM requires contiguous DPA\n");
+ return -ENOMEM;
+ }
+
+ ads->um_queue_bo = bo;
+ }
+
return 0;
}
ALLOW_ERROR_INJECTION(xe_guc_ads_init, ERRNO); /* See xe_pci_probe() */
@@ -893,7 +912,7 @@ static void guc_mmio_reg_state_init(struct xe_guc_ads *ads)
static void guc_um_init_params(struct xe_guc_ads *ads)
{
- u32 um_queue_offset = guc_ads_um_queues_offset(ads);
+ struct xe_bo *um_bo = ads->um_queue_bo;
struct xe_guc *guc = ads_to_guc(ads);
struct xe_device *xe = ads_to_xe(ads);
u64 base_dpa;
@@ -903,8 +922,14 @@ static void guc_um_init_params(struct xe_guc_ads *ads)
with_dpa = !xe_guc_using_main_gamctrl_queues(guc);
- base_ggtt = xe_bo_ggtt_addr(ads->bo) + um_queue_offset;
- base_dpa = xe_bo_main_addr(ads->bo, PAGE_SIZE) + um_queue_offset;
+ if (um_bo) {
+ /* All USM platforms: UM queues in dedicated um_queue_bo */
+ base_ggtt = xe_bo_ggtt_addr(um_bo);
+ base_dpa = xe_bo_main_addr(um_bo, PAGE_SIZE);
+ } else {
+ /* Platform does not support USM: no UM queues, nothing to do */
+ return;
+ }
for (i = 0; i < GUC_UM_HW_QUEUE_MAX; ++i) {
/*
diff --git a/drivers/gpu/drm/xe/xe_guc_ads_types.h b/drivers/gpu/drm/xe/xe_guc_ads_types.h
index 48a8e092023f..845c1fbd93a4 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads_types.h
+++ b/drivers/gpu/drm/xe/xe_guc_ads_types.h
@@ -16,6 +16,11 @@ struct xe_bo;
struct xe_guc_ads {
/** @bo: Xe BO for GuC ads blob */
struct xe_bo *bo;
+ /**
+ * @um_queue_bo: Dedicated BO for the HW fault ring (UM queues).
+ * NULL if the platform does not support USM.
+ */
+ struct xe_bo *um_queue_bo;
/** @golden_lrc_size: golden LRC size */
size_t golden_lrc_size;
/** @regset_size: size of register set passed to GuC for save/restore */
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v7 2/3] drm/xe/guc_ads: allocate UM queues in VRAM on dGFX
2026-08-03 20:08 [PATCH v7 0/1] drm/xe/guc_ads: allocate UM queues in a separate UC BO Jia Yao
2026-08-03 20:08 ` [PATCH v7 1/3] drm/xe/guc_ads: allocate UM queues in a separate BO Jia Yao
@ 2026-08-03 20:08 ` Jia Yao
2026-08-04 7:45 ` Matthew Auld
2026-08-03 20:08 ` [PATCH v7 3/3] drm/xe/guc_ads: use uncached mapping for UM queue BO Jia Yao
` (3 subsequent siblings)
5 siblings, 1 reply; 14+ messages in thread
From: Jia Yao @ 2026-08-03 20:08 UTC (permalink / raw)
To: intel-xe; +Cc: Jia Yao, Gwan-gyeong Mun, Matthew Auld, stable
On iGPU, the UM queue BO is allocated in system memory. On dGFX, the BO
was previously created in system memory and later reallocated in
xe_guc_realloc_post_hwconfig(). Allocate the UM queue BO directly in
VRAM on dGFX, where it is ultimately required.
Fixes: 9c57bc08652a ("drm/xe/lnl: Drop force_probe requirement")
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: <stable@vger.kernel.org> # v6.12+
Signed-off-by: Jia Yao <jia.yao@intel.com>
---
drivers/gpu/drm/xe/xe_guc.c | 6 ------
drivers/gpu/drm/xe/xe_guc_ads.c | 17 ++++++++++-------
2 files changed, 10 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index 4f132bf8539d..4286bd05c686 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -732,12 +732,6 @@ static int xe_guc_realloc_post_hwconfig(struct xe_guc *guc)
if (ret)
return ret;
- if (guc->ads.um_queue_bo) {
- ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->ads.um_queue_bo);
- if (ret)
- return ret;
- }
-
return 0;
}
diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index ef8e9cc35c8c..a69ec584cc0f 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -446,19 +446,22 @@ int xe_guc_ads_init(struct xe_guc_ads *ads)
/*
* Allocate a separate BO for the HW fault ring (UM queues).
*
- * Round the size up to the next power of two so that
+ * Round the size up to the next power of two so that on iGPU
* (system memory, no IOMMU) the TTM pool issues a single
* alloc_pages(order=N) call, maximising the chance of getting
* a physically contiguous block. GuC requires contiguous DPA.
*/
- size_t um_size = roundup_pow_of_two(GUC_UM_QUEUE_SIZE *
+ size_t um_size = IS_DGFX(xe) ?
+ GUC_UM_QUEUE_SIZE * GUC_UM_HW_QUEUE_MAX :
+ roundup_pow_of_two(GUC_UM_QUEUE_SIZE *
GUC_UM_HW_QUEUE_MAX);
- bo = xe_managed_bo_create_pin_map(xe, tile, um_size,
- XE_BO_FLAG_SYSTEM |
- XE_BO_FLAG_GGTT |
- XE_BO_FLAG_GGTT_INVALIDATE |
- XE_BO_FLAG_PINNED_NORESTORE);
+ u32 um_flags = XE_BO_FLAG_VRAM_IF_DGFX(tile) |
+ XE_BO_FLAG_GGTT |
+ XE_BO_FLAG_GGTT_INVALIDATE |
+ XE_BO_FLAG_PINNED_NORESTORE;
+
+ bo = xe_managed_bo_create_pin_map(xe, tile, um_size, um_flags);
if (IS_ERR(bo))
return PTR_ERR(bo);
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v7 3/3] drm/xe/guc_ads: use uncached mapping for UM queue BO
2026-08-03 20:08 [PATCH v7 0/1] drm/xe/guc_ads: allocate UM queues in a separate UC BO Jia Yao
2026-08-03 20:08 ` [PATCH v7 1/3] drm/xe/guc_ads: allocate UM queues in a separate BO Jia Yao
2026-08-03 20:08 ` [PATCH v7 2/3] drm/xe/guc_ads: allocate UM queues in VRAM on dGFX Jia Yao
@ 2026-08-03 20:08 ` Jia Yao
2026-08-03 20:15 ` ✓ CI.KUnit: success for drm/xe/guc_ads: allocate UM queues in a separate UC BO (rev5) Patchwork
` (2 subsequent siblings)
5 siblings, 0 replies; 14+ messages in thread
From: Jia Yao @ 2026-08-03 20:08 UTC (permalink / raw)
To: intel-xe; +Cc: Jia Yao, Gwan-gyeong Mun, Matthew Auld, stable
On Pre-Xe3p platform, the GAM write the UM queue through DPA using UC.
if GuC GuC reads the queue via GGTT (WB), stale data may be observed
when the cacheline has been polluted by another agent.
To match the GAM's UC writes, configure the GuC mapping as UC as well.
Fixes: 9c57bc08652a ("drm/xe/lnl: Drop force_probe requirement")
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: <stable@vger.kernel.org> # v6.12+
Signed-off-by: Jia Yao <jia.yao@intel.com>
Reviewed by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/xe/xe_guc_ads.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index a69ec584cc0f..97a2dbb03558 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -459,7 +459,8 @@ int xe_guc_ads_init(struct xe_guc_ads *ads)
u32 um_flags = XE_BO_FLAG_VRAM_IF_DGFX(tile) |
XE_BO_FLAG_GGTT |
XE_BO_FLAG_GGTT_INVALIDATE |
- XE_BO_FLAG_PINNED_NORESTORE;
+ XE_BO_FLAG_PINNED_NORESTORE |
+ XE_BO_FLAG_NEEDS_UC;
bo = xe_managed_bo_create_pin_map(xe, tile, um_size, um_flags);
if (IS_ERR(bo))
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* ✓ CI.KUnit: success for drm/xe/guc_ads: allocate UM queues in a separate UC BO (rev5)
2026-08-03 20:08 [PATCH v7 0/1] drm/xe/guc_ads: allocate UM queues in a separate UC BO Jia Yao
` (2 preceding siblings ...)
2026-08-03 20:08 ` [PATCH v7 3/3] drm/xe/guc_ads: use uncached mapping for UM queue BO Jia Yao
@ 2026-08-03 20:15 ` Patchwork
2026-08-03 22:41 ` ✓ Xe.CI.FULL: " Patchwork
2026-08-04 12:23 ` ✓ CI.KUnit: " Patchwork
5 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2026-08-03 20:15 UTC (permalink / raw)
To: Jia Yao; +Cc: intel-xe
== Series Details ==
Series: drm/xe/guc_ads: allocate UM queues in a separate UC BO (rev5)
URL : https://patchwork.freedesktop.org/series/169535/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[20:14:15] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[20:14:19] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[20:14:51] Starting KUnit Kernel (1/1)...
[20:14:51] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[20:14:51] ================== guc_buf (11 subtests) ===================
[20:14:51] [PASSED] test_smallest
[20:14:51] [PASSED] test_largest
[20:14:51] [PASSED] test_granular
[20:14:51] [PASSED] test_unique
[20:14:51] [PASSED] test_overlap
[20:14:51] [PASSED] test_reusable
[20:14:51] [PASSED] test_too_big
[20:14:51] [PASSED] test_flush
[20:14:51] [PASSED] test_lookup
[20:14:51] [PASSED] test_data
[20:14:51] [PASSED] test_class
[20:14:51] ===================== [PASSED] guc_buf =====================
[20:14:51] =================== guc_dbm (7 subtests) ===================
[20:14:51] [PASSED] test_empty
[20:14:51] [PASSED] test_default
[20:14:51] ======================== test_size ========================
[20:14:51] [PASSED] 4
[20:14:51] [PASSED] 8
[20:14:51] [PASSED] 32
[20:14:51] [PASSED] 256
[20:14:51] ==================== [PASSED] test_size ====================
[20:14:51] ======================= test_reuse ========================
[20:14:51] [PASSED] 4
[20:14:51] [PASSED] 8
[20:14:51] [PASSED] 32
[20:14:51] [PASSED] 256
[20:14:51] =================== [PASSED] test_reuse ====================
[20:14:51] =================== test_range_overlap ====================
[20:14:51] [PASSED] 4
[20:14:51] [PASSED] 8
[20:14:51] [PASSED] 32
[20:14:51] [PASSED] 256
[20:14:51] =============== [PASSED] test_range_overlap ================
[20:14:51] =================== test_range_compact ====================
[20:14:51] [PASSED] 4
[20:14:51] [PASSED] 8
[20:14:51] [PASSED] 32
[20:14:51] [PASSED] 256
[20:14:51] =============== [PASSED] test_range_compact ================
[20:14:51] ==================== test_range_spare =====================
[20:14:51] [PASSED] 4
[20:14:51] [PASSED] 8
[20:14:51] [PASSED] 32
[20:14:51] [PASSED] 256
[20:14:51] ================ [PASSED] test_range_spare =================
[20:14:51] ===================== [PASSED] guc_dbm =====================
[20:14:51] =================== guc_idm (6 subtests) ===================
[20:14:51] [PASSED] bad_init
[20:14:51] [PASSED] no_init
[20:14:51] [PASSED] init_fini
[20:14:51] [PASSED] check_used
[20:14:51] [PASSED] check_quota
[20:14:51] [PASSED] check_all
[20:14:51] ===================== [PASSED] guc_idm =====================
[20:14:51] =============== guc_klv_helpers (9 subtests) ===============
[20:14:51] [PASSED] test_count
[20:14:51] [PASSED] test_encode_u32
[20:14:51] [PASSED] test_encode_u64
[20:14:51] [PASSED] test_encode_string
[20:14:51] [PASSED] test_encode_object_raw
[20:14:51] [PASSED] test_encode_object_klv
[20:14:51] [PASSED] test_encode_object_nested
[20:14:51] [PASSED] test_encode_object_basic
[20:14:51] [PASSED] test_print
[20:14:51] ================= [PASSED] guc_klv_helpers =================
[20:14:51] ================== no_relay (3 subtests) ===================
[20:14:51] [PASSED] xe_drops_guc2pf_if_not_ready
[20:14:51] [PASSED] xe_drops_guc2vf_if_not_ready
[20:14:51] [PASSED] xe_rejects_send_if_not_ready
[20:14:51] ==================== [PASSED] no_relay =====================
[20:14:51] ================== pf_relay (14 subtests) ==================
[20:14:51] [PASSED] pf_rejects_guc2pf_too_short
[20:14:51] [PASSED] pf_rejects_guc2pf_too_long
[20:14:51] [PASSED] pf_rejects_guc2pf_no_payload
[20:14:51] [PASSED] pf_fails_no_payload
[20:14:51] [PASSED] pf_fails_bad_origin
[20:14:51] [PASSED] pf_fails_bad_type
[20:14:51] [PASSED] pf_txn_reports_error
[20:14:51] [PASSED] pf_txn_sends_pf2guc
[20:14:51] [PASSED] pf_sends_pf2guc
[20:14:51] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[20:14:51] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[20:14:51] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[20:14:51] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[20:14:51] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[20:14:51] ==================== [PASSED] pf_relay =====================
[20:14:51] ================== vf_relay (3 subtests) ===================
[20:14:51] [PASSED] vf_rejects_guc2vf_too_short
[20:14:51] [PASSED] vf_rejects_guc2vf_too_long
[20:14:51] [PASSED] vf_rejects_guc2vf_no_payload
[20:14:51] ==================== [PASSED] vf_relay =====================
[20:14:51] ================ pf_gt_config (9 subtests) =================
[20:14:51] [PASSED] fair_contexts_1vf
[20:14:51] [PASSED] fair_doorbells_1vf
[20:14:51] [PASSED] fair_ggtt_1vf
[20:14:51] ====================== fair_vram_1vf ======================
[20:14:51] [PASSED] 3.50 GiB
[20:14:51] [PASSED] 11.5 GiB
[20:14:51] [PASSED] 15.5 GiB
[20:14:51] [PASSED] 31.5 GiB
[20:14:51] [PASSED] 63.5 GiB
[20:14:51] [PASSED] 1.91 GiB
[20:14:51] ================== [PASSED] fair_vram_1vf ==================
[20:14:51] ================ fair_vram_1vf_admin_only =================
[20:14:51] [PASSED] 3.50 GiB
[20:14:51] [PASSED] 11.5 GiB
[20:14:51] [PASSED] 15.5 GiB
[20:14:51] [PASSED] 31.5 GiB
[20:14:51] [PASSED] 63.5 GiB
[20:14:51] [PASSED] 1.91 GiB
[20:14:51] ============ [PASSED] fair_vram_1vf_admin_only =============
[20:14:51] ====================== fair_contexts ======================
[20:14:51] [PASSED] 1 VF
[20:14:51] [PASSED] 2 VFs
[20:14:51] [PASSED] 3 VFs
[20:14:51] [PASSED] 4 VFs
[20:14:51] [PASSED] 5 VFs
[20:14:51] [PASSED] 6 VFs
[20:14:51] [PASSED] 7 VFs
[20:14:51] [PASSED] 8 VFs
[20:14:51] [PASSED] 9 VFs
[20:14:51] [PASSED] 10 VFs
[20:14:51] [PASSED] 11 VFs
[20:14:51] [PASSED] 12 VFs
[20:14:51] [PASSED] 13 VFs
[20:14:51] [PASSED] 14 VFs
[20:14:51] [PASSED] 15 VFs
[20:14:51] [PASSED] 16 VFs
[20:14:51] [PASSED] 17 VFs
[20:14:51] [PASSED] 18 VFs
[20:14:51] [PASSED] 19 VFs
[20:14:51] [PASSED] 20 VFs
[20:14:51] [PASSED] 21 VFs
[20:14:51] [PASSED] 22 VFs
[20:14:51] [PASSED] 23 VFs
[20:14:51] [PASSED] 24 VFs
[20:14:51] [PASSED] 25 VFs
[20:14:51] [PASSED] 26 VFs
[20:14:51] [PASSED] 27 VFs
[20:14:51] [PASSED] 28 VFs
[20:14:51] [PASSED] 29 VFs
[20:14:51] [PASSED] 30 VFs
[20:14:51] [PASSED] 31 VFs
[20:14:51] [PASSED] 32 VFs
[20:14:51] [PASSED] 33 VFs
[20:14:51] [PASSED] 34 VFs
[20:14:51] [PASSED] 35 VFs
[20:14:51] [PASSED] 36 VFs
[20:14:51] [PASSED] 37 VFs
[20:14:51] [PASSED] 38 VFs
[20:14:51] [PASSED] 39 VFs
[20:14:51] [PASSED] 40 VFs
[20:14:51] [PASSED] 41 VFs
[20:14:51] [PASSED] 42 VFs
[20:14:51] [PASSED] 43 VFs
[20:14:51] [PASSED] 44 VFs
[20:14:51] [PASSED] 45 VFs
[20:14:51] [PASSED] 46 VFs
[20:14:51] [PASSED] 47 VFs
[20:14:51] [PASSED] 48 VFs
[20:14:51] [PASSED] 49 VFs
[20:14:51] [PASSED] 50 VFs
[20:14:51] [PASSED] 51 VFs
[20:14:51] [PASSED] 52 VFs
[20:14:51] [PASSED] 53 VFs
[20:14:51] [PASSED] 54 VFs
[20:14:51] [PASSED] 55 VFs
[20:14:51] [PASSED] 56 VFs
[20:14:51] [PASSED] 57 VFs
[20:14:51] [PASSED] 58 VFs
[20:14:51] [PASSED] 59 VFs
[20:14:51] [PASSED] 60 VFs
[20:14:51] [PASSED] 61 VFs
[20:14:51] [PASSED] 62 VFs
[20:14:51] [PASSED] 63 VFs
[20:14:51] ================== [PASSED] fair_contexts ==================
[20:14:51] ===================== fair_doorbells ======================
[20:14:51] [PASSED] 1 VF
[20:14:51] [PASSED] 2 VFs
[20:14:51] [PASSED] 3 VFs
[20:14:51] [PASSED] 4 VFs
[20:14:51] [PASSED] 5 VFs
[20:14:51] [PASSED] 6 VFs
[20:14:51] [PASSED] 7 VFs
[20:14:51] [PASSED] 8 VFs
[20:14:51] [PASSED] 9 VFs
[20:14:51] [PASSED] 10 VFs
[20:14:51] [PASSED] 11 VFs
[20:14:51] [PASSED] 12 VFs
[20:14:51] [PASSED] 13 VFs
[20:14:51] [PASSED] 14 VFs
[20:14:51] [PASSED] 15 VFs
[20:14:51] [PASSED] 16 VFs
[20:14:51] [PASSED] 17 VFs
[20:14:51] [PASSED] 18 VFs
[20:14:51] [PASSED] 19 VFs
[20:14:51] [PASSED] 20 VFs
[20:14:51] [PASSED] 21 VFs
[20:14:51] [PASSED] 22 VFs
[20:14:51] [PASSED] 23 VFs
[20:14:51] [PASSED] 24 VFs
[20:14:51] [PASSED] 25 VFs
[20:14:51] [PASSED] 26 VFs
[20:14:51] [PASSED] 27 VFs
[20:14:51] [PASSED] 28 VFs
[20:14:51] [PASSED] 29 VFs
[20:14:51] [PASSED] 30 VFs
[20:14:51] [PASSED] 31 VFs
[20:14:51] [PASSED] 32 VFs
[20:14:51] [PASSED] 33 VFs
[20:14:51] [PASSED] 34 VFs
[20:14:51] [PASSED] 35 VFs
[20:14:51] [PASSED] 36 VFs
[20:14:51] [PASSED] 37 VFs
[20:14:51] [PASSED] 38 VFs
[20:14:51] [PASSED] 39 VFs
[20:14:51] [PASSED] 40 VFs
[20:14:51] [PASSED] 41 VFs
[20:14:51] [PASSED] 42 VFs
[20:14:51] [PASSED] 43 VFs
[20:14:51] [PASSED] 44 VFs
[20:14:51] [PASSED] 45 VFs
[20:14:51] [PASSED] 46 VFs
[20:14:51] [PASSED] 47 VFs
[20:14:51] [PASSED] 48 VFs
[20:14:51] [PASSED] 49 VFs
[20:14:51] [PASSED] 50 VFs
[20:14:51] [PASSED] 51 VFs
[20:14:51] [PASSED] 52 VFs
[20:14:51] [PASSED] 53 VFs
[20:14:51] [PASSED] 54 VFs
[20:14:51] [PASSED] 55 VFs
[20:14:51] [PASSED] 56 VFs
[20:14:51] [PASSED] 57 VFs
[20:14:51] [PASSED] 58 VFs
[20:14:51] [PASSED] 59 VFs
[20:14:51] [PASSED] 60 VFs
[20:14:51] [PASSED] 61 VFs
[20:14:51] [PASSED] 62 VFs
[20:14:51] [PASSED] 63 VFs
[20:14:51] ================= [PASSED] fair_doorbells ==================
[20:14:51] ======================== fair_ggtt ========================
[20:14:51] [PASSED] 1 VF
[20:14:51] [PASSED] 2 VFs
[20:14:51] [PASSED] 3 VFs
[20:14:51] [PASSED] 4 VFs
[20:14:51] [PASSED] 5 VFs
[20:14:51] [PASSED] 6 VFs
[20:14:51] [PASSED] 7 VFs
[20:14:51] [PASSED] 8 VFs
[20:14:51] [PASSED] 9 VFs
[20:14:51] [PASSED] 10 VFs
[20:14:51] [PASSED] 11 VFs
[20:14:51] [PASSED] 12 VFs
[20:14:51] [PASSED] 13 VFs
[20:14:51] [PASSED] 14 VFs
[20:14:51] [PASSED] 15 VFs
[20:14:51] [PASSED] 16 VFs
[20:14:51] [PASSED] 17 VFs
[20:14:51] [PASSED] 18 VFs
[20:14:51] [PASSED] 19 VFs
[20:14:51] [PASSED] 20 VFs
[20:14:51] [PASSED] 21 VFs
[20:14:51] [PASSED] 22 VFs
[20:14:51] [PASSED] 23 VFs
[20:14:51] [PASSED] 24 VFs
[20:14:51] [PASSED] 25 VFs
[20:14:51] [PASSED] 26 VFs
[20:14:51] [PASSED] 27 VFs
[20:14:51] [PASSED] 28 VFs
[20:14:51] [PASSED] 29 VFs
[20:14:51] [PASSED] 30 VFs
[20:14:51] [PASSED] 31 VFs
[20:14:51] [PASSED] 32 VFs
[20:14:51] [PASSED] 33 VFs
[20:14:51] [PASSED] 34 VFs
[20:14:51] [PASSED] 35 VFs
[20:14:51] [PASSED] 36 VFs
[20:14:51] [PASSED] 37 VFs
[20:14:51] [PASSED] 38 VFs
[20:14:51] [PASSED] 39 VFs
[20:14:51] [PASSED] 40 VFs
[20:14:51] [PASSED] 41 VFs
[20:14:51] [PASSED] 42 VFs
[20:14:51] [PASSED] 43 VFs
[20:14:51] [PASSED] 44 VFs
[20:14:51] [PASSED] 45 VFs
[20:14:51] [PASSED] 46 VFs
[20:14:51] [PASSED] 47 VFs
[20:14:51] [PASSED] 48 VFs
[20:14:51] [PASSED] 49 VFs
[20:14:51] [PASSED] 50 VFs
[20:14:51] [PASSED] 51 VFs
[20:14:51] [PASSED] 52 VFs
[20:14:51] [PASSED] 53 VFs
[20:14:51] [PASSED] 54 VFs
[20:14:51] [PASSED] 55 VFs
[20:14:51] [PASSED] 56 VFs
[20:14:51] [PASSED] 57 VFs
[20:14:51] [PASSED] 58 VFs
[20:14:51] [PASSED] 59 VFs
[20:14:51] [PASSED] 60 VFs
[20:14:51] [PASSED] 61 VFs
[20:14:51] [PASSED] 62 VFs
[20:14:51] [PASSED] 63 VFs
[20:14:51] ==================== [PASSED] fair_ggtt ====================
[20:14:51] ======================== fair_vram ========================
[20:14:51] [PASSED] 1 VF
[20:14:51] [PASSED] 2 VFs
[20:14:51] [PASSED] 3 VFs
[20:14:51] [PASSED] 4 VFs
[20:14:51] [PASSED] 5 VFs
[20:14:51] [PASSED] 6 VFs
[20:14:51] [PASSED] 7 VFs
[20:14:51] [PASSED] 8 VFs
[20:14:51] [PASSED] 9 VFs
[20:14:51] [PASSED] 10 VFs
[20:14:51] [PASSED] 11 VFs
[20:14:51] [PASSED] 12 VFs
[20:14:51] [PASSED] 13 VFs
[20:14:51] [PASSED] 14 VFs
[20:14:51] [PASSED] 15 VFs
[20:14:51] [PASSED] 16 VFs
[20:14:51] [PASSED] 17 VFs
[20:14:51] [PASSED] 18 VFs
[20:14:51] [PASSED] 19 VFs
[20:14:51] [PASSED] 20 VFs
[20:14:51] [PASSED] 21 VFs
[20:14:51] [PASSED] 22 VFs
[20:14:51] [PASSED] 23 VFs
[20:14:51] [PASSED] 24 VFs
[20:14:51] [PASSED] 25 VFs
[20:14:51] [PASSED] 26 VFs
[20:14:51] [PASSED] 27 VFs
[20:14:51] [PASSED] 28 VFs
[20:14:51] [PASSED] 29 VFs
[20:14:51] [PASSED] 30 VFs
[20:14:51] [PASSED] 31 VFs
[20:14:51] [PASSED] 32 VFs
[20:14:51] [PASSED] 33 VFs
[20:14:51] [PASSED] 34 VFs
[20:14:51] [PASSED] 35 VFs
[20:14:51] [PASSED] 36 VFs
[20:14:51] [PASSED] 37 VFs
[20:14:51] [PASSED] 38 VFs
[20:14:51] [PASSED] 39 VFs
[20:14:51] [PASSED] 40 VFs
[20:14:51] [PASSED] 41 VFs
[20:14:51] [PASSED] 42 VFs
[20:14:51] [PASSED] 43 VFs
[20:14:51] [PASSED] 44 VFs
[20:14:51] [PASSED] 45 VFs
[20:14:51] [PASSED] 46 VFs
[20:14:51] [PASSED] 47 VFs
[20:14:51] [PASSED] 48 VFs
[20:14:51] [PASSED] 49 VFs
[20:14:51] [PASSED] 50 VFs
[20:14:51] [PASSED] 51 VFs
[20:14:51] [PASSED] 52 VFs
[20:14:51] [PASSED] 53 VFs
[20:14:51] [PASSED] 54 VFs
[20:14:51] [PASSED] 55 VFs
[20:14:51] [PASSED] 56 VFs
[20:14:51] [PASSED] 57 VFs
[20:14:51] [PASSED] 58 VFs
[20:14:51] [PASSED] 59 VFs
[20:14:51] [PASSED] 60 VFs
[20:14:51] [PASSED] 61 VFs
[20:14:51] [PASSED] 62 VFs
[20:14:51] [PASSED] 63 VFs
[20:14:51] ==================== [PASSED] fair_vram ====================
[20:14:51] ================== [PASSED] pf_gt_config ===================
[20:14:51] ===================== lmtt (1 subtest) =====================
[20:14:51] ======================== test_ops =========================
[20:14:51] [PASSED] 2-level
[20:14:51] [PASSED] multi-level
[20:14:51] ==================== [PASSED] test_ops =====================
[20:14:51] ====================== [PASSED] lmtt =======================
[20:14:51] ================= sriov_packet (1 subtest) =================
[20:14:51] [PASSED] test_descriptor_init
[20:14:51] ================== [PASSED] sriov_packet ===================
[20:14:51] ================= pf_service (11 subtests) =================
[20:14:51] [PASSED] pf_negotiate_any
[20:14:51] [PASSED] pf_negotiate_base_match
[20:14:51] [PASSED] pf_negotiate_base_newer
[20:14:51] [PASSED] pf_negotiate_base_next
[20:14:51] [SKIPPED] pf_negotiate_base_older (no older minor)
[20:14:51] [PASSED] pf_negotiate_base_prev
[20:14:51] [PASSED] pf_negotiate_latest_match
[20:14:51] [PASSED] pf_negotiate_latest_newer
[20:14:51] [PASSED] pf_negotiate_latest_next
[20:14:51] [SKIPPED] pf_negotiate_latest_older (no older minor)
[20:14:51] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[20:14:51] =================== [PASSED] pf_service ====================
[20:14:51] ================= xe_guc_g2g (2 subtests) ==================
[20:14:51] ============== xe_live_guc_g2g_kunit_default ==============
[20:14:51] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[20:14:51] ============== xe_live_guc_g2g_kunit_allmem ===============
[20:14:51] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[20:14:51] =================== [SKIPPED] xe_guc_g2g ===================
[20:14:51] =================== xe_mocs (2 subtests) ===================
[20:14:51] ================ xe_live_mocs_kernel_kunit ================
[20:14:51] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[20:14:51] ================ xe_live_mocs_reset_kunit =================
[20:14:51] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[20:14:51] ==================== [SKIPPED] xe_mocs =====================
[20:14:51] ================= xe_migrate (2 subtests) ==================
[20:14:51] ================= xe_migrate_sanity_kunit =================
[20:14:51] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[20:14:51] ================== xe_validate_ccs_kunit ==================
[20:14:51] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[20:14:51] =================== [SKIPPED] xe_migrate ===================
[20:14:51] ================== xe_dma_buf (1 subtest) ==================
[20:14:51] ==================== xe_dma_buf_kunit =====================
[20:14:51] ================ [SKIPPED] xe_dma_buf_kunit ================
[20:14:51] =================== [SKIPPED] xe_dma_buf ===================
[20:14:51] ================= xe_bo_shrink (1 subtest) =================
[20:14:51] =================== xe_bo_shrink_kunit ====================
[20:14:51] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[20:14:51] ================== [SKIPPED] xe_bo_shrink ==================
[20:14:51] ==================== xe_bo (2 subtests) ====================
[20:14:51] ================== xe_ccs_migrate_kunit ===================
[20:14:51] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[20:14:51] ==================== xe_bo_evict_kunit ====================
[20:14:51] =============== [SKIPPED] xe_bo_evict_kunit ================
[20:14:51] ===================== [SKIPPED] xe_bo ======================
[20:14:51] ==================== args (13 subtests) ====================
[20:14:51] [PASSED] count_args_test
[20:14:51] [PASSED] call_args_example
[20:14:51] [PASSED] call_args_test
[20:14:51] [PASSED] drop_first_arg_example
[20:14:51] [PASSED] drop_first_arg_test
[20:14:51] [PASSED] first_arg_example
[20:14:51] [PASSED] first_arg_test
[20:14:51] [PASSED] last_arg_example
[20:14:51] [PASSED] last_arg_test
[20:14:51] [PASSED] pick_arg_example
[20:14:51] [PASSED] if_args_example
[20:14:51] [PASSED] if_args_test
[20:14:51] [PASSED] sep_comma_example
[20:14:51] ====================== [PASSED] args =======================
[20:14:51] =================== xe_pci (3 subtests) ====================
[20:14:51] ==================== check_graphics_ip ====================
[20:14:51] [PASSED] 12.00 Xe_LP
[20:14:51] [PASSED] 12.10 Xe_LP+
[20:14:51] [PASSED] 12.55 Xe_HPG
[20:14:51] [PASSED] 12.60 Xe_HPC
[20:14:51] [PASSED] 12.70 Xe_LPG
[20:14:51] [PASSED] 12.71 Xe_LPG
[20:14:51] [PASSED] 12.74 Xe_LPG+
[20:14:51] [PASSED] 20.01 Xe2_HPG
[20:14:51] [PASSED] 20.02 Xe2_HPG
[20:14:51] [PASSED] 20.04 Xe2_LPG
[20:14:51] [PASSED] 30.00 Xe3_LPG
[20:14:51] [PASSED] 30.01 Xe3_LPG
[20:14:51] [PASSED] 30.03 Xe3_LPG
[20:14:51] [PASSED] 30.04 Xe3_LPG
[20:14:51] [PASSED] 30.05 Xe3_LPG
[20:14:51] [PASSED] 35.10 Xe3p_LPG
[20:14:51] [PASSED] 35.11 Xe3p_XPC
[20:14:51] ================ [PASSED] check_graphics_ip ================
[20:14:51] ===================== check_media_ip ======================
[20:14:51] [PASSED] 12.00 Xe_M
[20:14:51] [PASSED] 12.55 Xe_HPM
[20:14:51] [PASSED] 13.00 Xe_LPM+
[20:14:51] [PASSED] 13.01 Xe2_HPM
[20:14:51] [PASSED] 20.00 Xe2_LPM
[20:14:51] [PASSED] 30.00 Xe3_LPM
[20:14:51] [PASSED] 30.02 Xe3_LPM
[20:14:51] [PASSED] 35.00 Xe3p_LPM
[20:14:51] [PASSED] 35.03 Xe3p_HPM
[20:14:51] ================= [PASSED] check_media_ip ==================
[20:14:51] =================== check_platform_desc ===================
[20:14:51] [PASSED] 0x9A60 (TIGERLAKE)
[20:14:51] [PASSED] 0x9A68 (TIGERLAKE)
[20:14:51] [PASSED] 0x9A70 (TIGERLAKE)
[20:14:51] [PASSED] 0x9A40 (TIGERLAKE)
[20:14:51] [PASSED] 0x9A49 (TIGERLAKE)
[20:14:51] [PASSED] 0x9A59 (TIGERLAKE)
[20:14:51] [PASSED] 0x9A78 (TIGERLAKE)
[20:14:51] [PASSED] 0x9AC0 (TIGERLAKE)
[20:14:51] [PASSED] 0x9AC9 (TIGERLAKE)
[20:14:51] [PASSED] 0x9AD9 (TIGERLAKE)
[20:14:51] [PASSED] 0x9AF8 (TIGERLAKE)
[20:14:51] [PASSED] 0x4C80 (ROCKETLAKE)
[20:14:51] [PASSED] 0x4C8A (ROCKETLAKE)
[20:14:51] [PASSED] 0x4C8B (ROCKETLAKE)
[20:14:51] [PASSED] 0x4C8C (ROCKETLAKE)
[20:14:51] [PASSED] 0x4C90 (ROCKETLAKE)
[20:14:51] [PASSED] 0x4C9A (ROCKETLAKE)
[20:14:51] [PASSED] 0x4680 (ALDERLAKE_S)
[20:14:51] [PASSED] 0x4682 (ALDERLAKE_S)
[20:14:51] [PASSED] 0x4688 (ALDERLAKE_S)
[20:14:51] [PASSED] 0x468A (ALDERLAKE_S)
[20:14:51] [PASSED] 0x468B (ALDERLAKE_S)
[20:14:51] [PASSED] 0x4690 (ALDERLAKE_S)
[20:14:51] [PASSED] 0x4692 (ALDERLAKE_S)
[20:14:51] [PASSED] 0x4693 (ALDERLAKE_S)
[20:14:51] [PASSED] 0x46A0 (ALDERLAKE_P)
[20:14:51] [PASSED] 0x46A1 (ALDERLAKE_P)
[20:14:51] [PASSED] 0x46A2 (ALDERLAKE_P)
[20:14:51] [PASSED] 0x46A3 (ALDERLAKE_P)
[20:14:51] [PASSED] 0x46A6 (ALDERLAKE_P)
[20:14:51] [PASSED] 0x46A8 (ALDERLAKE_P)
[20:14:51] [PASSED] 0x46AA (ALDERLAKE_P)
[20:14:51] [PASSED] 0x462A (ALDERLAKE_P)
[20:14:51] [PASSED] 0x4626 (ALDERLAKE_P)
[20:14:51] [PASSED] 0x4628 (ALDERLAKE_P)
[20:14:51] [PASSED] 0x46B0 (ALDERLAKE_P)
[20:14:51] [PASSED] 0x46B1 (ALDERLAKE_P)
[20:14:51] [PASSED] 0x46B2 (ALDERLAKE_P)
[20:14:51] [PASSED] 0x46B3 (ALDERLAKE_P)
[20:14:51] [PASSED] 0x46C0 (ALDERLAKE_P)
[20:14:51] [PASSED] 0x46C1 (ALDERLAKE_P)
[20:14:51] [PASSED] 0x46C2 (ALDERLAKE_P)
[20:14:51] [PASSED] 0x46C3 (ALDERLAKE_P)
[20:14:51] [PASSED] 0x46D0 (ALDERLAKE_N)
[20:14:51] [PASSED] 0x46D1 (ALDERLAKE_N)
[20:14:51] [PASSED] 0x46D2 (ALDERLAKE_N)
[20:14:51] [PASSED] 0x46D3 (ALDERLAKE_N)
[20:14:51] [PASSED] 0x46D4 (ALDERLAKE_N)
[20:14:51] [PASSED] 0xA721 (ALDERLAKE_P)
[20:14:51] [PASSED] 0xA7A1 (ALDERLAKE_P)
[20:14:51] [PASSED] 0xA7A9 (ALDERLAKE_P)
[20:14:51] [PASSED] 0xA7AC (ALDERLAKE_P)
[20:14:51] [PASSED] 0xA7AD (ALDERLAKE_P)
[20:14:51] [PASSED] 0xA720 (ALDERLAKE_P)
[20:14:51] [PASSED] 0xA7A0 (ALDERLAKE_P)
[20:14:51] [PASSED] 0xA7A8 (ALDERLAKE_P)
[20:14:51] [PASSED] 0xA7AA (ALDERLAKE_P)
[20:14:51] [PASSED] 0xA7AB (ALDERLAKE_P)
[20:14:51] [PASSED] 0xA780 (ALDERLAKE_S)
[20:14:51] [PASSED] 0xA781 (ALDERLAKE_S)
[20:14:51] [PASSED] 0xA782 (ALDERLAKE_S)
[20:14:51] [PASSED] 0xA783 (ALDERLAKE_S)
[20:14:51] [PASSED] 0xA788 (ALDERLAKE_S)
[20:14:51] [PASSED] 0xA789 (ALDERLAKE_S)
[20:14:51] [PASSED] 0xA78A (ALDERLAKE_S)
[20:14:51] [PASSED] 0xA78B (ALDERLAKE_S)
[20:14:51] [PASSED] 0x4905 (DG1)
[20:14:51] [PASSED] 0x4906 (DG1)
[20:14:51] [PASSED] 0x4907 (DG1)
[20:14:51] [PASSED] 0x4908 (DG1)
[20:14:51] [PASSED] 0x4909 (DG1)
[20:14:51] [PASSED] 0x56C0 (DG2)
[20:14:51] [PASSED] 0x56C2 (DG2)
[20:14:51] [PASSED] 0x56C1 (DG2)
[20:14:51] [PASSED] 0x7D51 (METEORLAKE)
[20:14:51] [PASSED] 0x7DD1 (METEORLAKE)
[20:14:51] [PASSED] 0x7D41 (METEORLAKE)
[20:14:51] [PASSED] 0x7D67 (METEORLAKE)
[20:14:51] [PASSED] 0xB640 (METEORLAKE)
[20:14:51] [PASSED] 0x56A0 (DG2)
[20:14:51] [PASSED] 0x56A1 (DG2)
[20:14:51] [PASSED] 0x56A2 (DG2)
[20:14:51] [PASSED] 0x56BE (DG2)
[20:14:51] [PASSED] 0x56BF (DG2)
[20:14:51] [PASSED] 0x5690 (DG2)
[20:14:51] [PASSED] 0x5691 (DG2)
[20:14:51] [PASSED] 0x5692 (DG2)
[20:14:51] [PASSED] 0x56A5 (DG2)
[20:14:51] [PASSED] 0x56A6 (DG2)
[20:14:51] [PASSED] 0x56B0 (DG2)
[20:14:51] [PASSED] 0x56B1 (DG2)
[20:14:51] [PASSED] 0x56BA (DG2)
[20:14:51] [PASSED] 0x56BB (DG2)
[20:14:51] [PASSED] 0x56BC (DG2)
[20:14:51] [PASSED] 0x56BD (DG2)
[20:14:51] [PASSED] 0x5693 (DG2)
[20:14:51] [PASSED] 0x5694 (DG2)
[20:14:51] [PASSED] 0x5695 (DG2)
[20:14:51] [PASSED] 0x56A3 (DG2)
[20:14:51] [PASSED] 0x56A4 (DG2)
[20:14:51] [PASSED] 0x56B2 (DG2)
[20:14:51] [PASSED] 0x56B3 (DG2)
[20:14:51] [PASSED] 0x5696 (DG2)
[20:14:51] [PASSED] 0x5697 (DG2)
[20:14:51] [PASSED] 0xB69 (PVC)
[20:14:51] [PASSED] 0xB6E (PVC)
[20:14:51] [PASSED] 0xBD4 (PVC)
[20:14:51] [PASSED] 0xBD5 (PVC)
[20:14:51] [PASSED] 0xBD6 (PVC)
[20:14:51] [PASSED] 0xBD7 (PVC)
[20:14:51] [PASSED] 0xBD8 (PVC)
[20:14:51] [PASSED] 0xBD9 (PVC)
[20:14:51] [PASSED] 0xBDA (PVC)
[20:14:51] [PASSED] 0xBDB (PVC)
[20:14:51] [PASSED] 0xBE0 (PVC)
[20:14:51] [PASSED] 0xBE1 (PVC)
[20:14:51] [PASSED] 0xBE5 (PVC)
[20:14:51] [PASSED] 0x7D40 (METEORLAKE)
[20:14:51] [PASSED] 0x7D45 (METEORLAKE)
[20:14:51] [PASSED] 0x7D55 (METEORLAKE)
[20:14:51] [PASSED] 0x7D60 (METEORLAKE)
[20:14:51] [PASSED] 0x7DD5 (METEORLAKE)
[20:14:51] [PASSED] 0x6420 (LUNARLAKE)
[20:14:51] [PASSED] 0x64A0 (LUNARLAKE)
[20:14:51] [PASSED] 0x64B0 (LUNARLAKE)
[20:14:51] [PASSED] 0xE202 (BATTLEMAGE)
[20:14:51] [PASSED] 0xE209 (BATTLEMAGE)
[20:14:51] [PASSED] 0xE20B (BATTLEMAGE)
[20:14:51] [PASSED] 0xE20C (BATTLEMAGE)
[20:14:51] [PASSED] 0xE20D (BATTLEMAGE)
[20:14:51] [PASSED] 0xE210 (BATTLEMAGE)
[20:14:51] [PASSED] 0xE211 (BATTLEMAGE)
[20:14:51] [PASSED] 0xE212 (BATTLEMAGE)
[20:14:51] [PASSED] 0xE216 (BATTLEMAGE)
[20:14:51] [PASSED] 0xE220 (BATTLEMAGE)
[20:14:51] [PASSED] 0xE221 (BATTLEMAGE)
[20:14:51] [PASSED] 0xE222 (BATTLEMAGE)
[20:14:51] [PASSED] 0xE223 (BATTLEMAGE)
[20:14:51] [PASSED] 0xB080 (PANTHERLAKE)
[20:14:51] [PASSED] 0xB081 (PANTHERLAKE)
[20:14:51] [PASSED] 0xB082 (PANTHERLAKE)
[20:14:51] [PASSED] 0xB083 (PANTHERLAKE)
[20:14:51] [PASSED] 0xB084 (PANTHERLAKE)
[20:14:51] [PASSED] 0xB085 (PANTHERLAKE)
[20:14:51] [PASSED] 0xB086 (PANTHERLAKE)
[20:14:51] [PASSED] 0xB087 (PANTHERLAKE)
[20:14:51] [PASSED] 0xB08F (PANTHERLAKE)
[20:14:51] [PASSED] 0xB090 (PANTHERLAKE)
[20:14:51] [PASSED] 0xB0A0 (PANTHERLAKE)
[20:14:51] [PASSED] 0xB0B0 (PANTHERLAKE)
[20:14:51] [PASSED] 0xFD80 (PANTHERLAKE)
[20:14:51] [PASSED] 0xFD81 (PANTHERLAKE)
[20:14:51] [PASSED] 0xD740 (NOVALAKE_S)
[20:14:51] [PASSED] 0xD741 (NOVALAKE_S)
[20:14:51] [PASSED] 0xD742 (NOVALAKE_S)
[20:14:51] [PASSED] 0xD743 (NOVALAKE_S)
[20:14:51] [PASSED] 0xD745 (NOVALAKE_S)
[20:14:51] [PASSED] 0xD74A (NOVALAKE_S)
[20:14:51] [PASSED] 0xD74B (NOVALAKE_S)
[20:14:51] [PASSED] 0x674C (CRESCENTISLAND)
[20:14:51] [PASSED] 0x674D (CRESCENTISLAND)
[20:14:51] [PASSED] 0x674E (CRESCENTISLAND)
[20:14:51] [PASSED] 0x674F (CRESCENTISLAND)
[20:14:51] [PASSED] 0x6750 (CRESCENTISLAND)
[20:14:51] [PASSED] 0xD750 (NOVALAKE_P)
[20:14:51] [PASSED] 0xD751 (NOVALAKE_P)
[20:14:51] [PASSED] 0xD752 (NOVALAKE_P)
[20:14:51] [PASSED] 0xD753 (NOVALAKE_P)
[20:14:51] [PASSED] 0xD754 (NOVALAKE_P)
[20:14:51] [PASSED] 0xD755 (NOVALAKE_P)
[20:14:51] [PASSED] 0xD756 (NOVALAKE_P)
[20:14:51] [PASSED] 0xD757 (NOVALAKE_P)
[20:14:51] [PASSED] 0xD75F (NOVALAKE_P)
[20:14:51] =============== [PASSED] check_platform_desc ===============
[20:14:51] ===================== [PASSED] xe_pci ======================
[20:14:51] ============= xe_rtp_tables_test (5 subtests) ==============
[20:14:51] ================== xe_rtp_table_gt_test ===================
[20:14:51] [PASSED] gt_was/14011060649
[20:14:51] [PASSED] gt_was/14011059788
[20:14:51] [PASSED] gt_was/14015795083
[20:14:51] [PASSED] gt_was/16021867713
[20:14:51] [PASSED] gt_was/14019449301
[20:14:51] [PASSED] gt_was/16028005424
[20:14:51] [PASSED] gt_was/14026578760
[20:14:51] [PASSED] gt_was/1409420604
[20:14:51] [PASSED] gt_was/1408615072
[20:14:51] [PASSED] gt_was/22010523718
[20:14:51] [PASSED] gt_was/14011006942
[20:14:51] [PASSED] gt_was/14014830051
[20:14:51] [PASSED] gt_was/18018781329
[20:14:51] [PASSED] gt_was/1509235366
[20:14:51] [PASSED] gt_was/18018781329
[20:14:51] [PASSED] gt_was/16016694945
[20:14:51] [PASSED] gt_was/14018575942
[20:14:51] [PASSED] gt_was/22016670082
[20:14:51] [PASSED] gt_was/22016670082
[20:14:51] [PASSED] gt_was/14017421178
[20:14:51] [PASSED] gt_was/16025250150
[20:14:51] [PASSED] gt_was/14021871409
[20:14:51] [PASSED] gt_was/16021865536
[20:14:51] [PASSED] gt_was/14021486841
[20:14:51] [PASSED] gt_was/14025160223
[20:14:51] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[20:14:51] [PASSED] gt_was/14025635424
[20:14:51] [PASSED] gt_was/16028005424
[20:14:51] ============== [PASSED] xe_rtp_table_gt_test ===============
[20:14:51] ================== xe_rtp_table_gt_test ===================
[20:14:51] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[20:14:51] [PASSED] gt_tunings/Tuning: 32B Access Enable
[20:14:51] [PASSED] gt_tunings/Tuning: L3 cache
[20:14:51] [PASSED] gt_tunings/Tuning: L3 cache - media
[20:14:51] [PASSED] gt_tunings/Tuning: Compression Overfetch
[20:14:51] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[20:14:51] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[20:14:51] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[20:14:51] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[20:14:51] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[20:14:51] [PASSED] gt_tunings/Tuning: Stateless compression control
[20:14:51] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[20:14:51] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[20:14:51] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[20:14:51] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[20:14:51] ============== [PASSED] xe_rtp_table_gt_test ===============
[20:14:51] ================== xe_rtp_table_oob_test ==================
[20:14:51] [PASSED] oob_was/1607983814
[20:14:51] [PASSED] oob_was/16010904313
[20:14:51] [PASSED] oob_was/18022495364
[20:14:51] [PASSED] oob_was/22012773006
[20:14:51] [PASSED] oob_was/14014475959
[20:14:51] [PASSED] oob_was/22011391025
[20:14:51] [PASSED] oob_was/22012727170
[20:14:51] [PASSED] oob_was/22012727685
[20:14:51] [PASSED] oob_was/22016596838
[20:14:51] [PASSED] oob_was/18020744125
[20:14:51] [PASSED] oob_was/1409600907
[20:14:51] [PASSED] oob_was/22014953428
[20:14:51] [PASSED] oob_was/16017236439
[20:14:51] [PASSED] oob_was/14019821291
[20:14:51] [PASSED] oob_was/14015076503
[20:14:51] [PASSED] oob_was/14018913170
[20:14:51] [PASSED] oob_was/14018094691
[20:14:51] [PASSED] oob_was/18024947630
[20:14:51] [PASSED] oob_was/16022287689
[20:14:51] [PASSED] oob_was/13011645652
[20:14:51] [PASSED] oob_was/14022293748
[20:14:51] [PASSED] oob_was/22019794406
[20:14:51] [PASSED] oob_was/22019338487
[20:14:51] [PASSED] oob_was/16023588340
[20:14:51] [PASSED] oob_was/14019789679
[20:14:51] [PASSED] oob_was/14022866841
[20:14:51] [PASSED] oob_was/16021333562
[20:14:51] [PASSED] oob_was/14016712196
[20:14:51] [PASSED] oob_was/14015568240
[20:14:51] [PASSED] oob_was/18013179988
[20:14:51] [PASSED] oob_was/1508761755
[20:14:51] [PASSED] oob_was/16023105232
[20:14:51] [PASSED] oob_was/16026508708
[20:14:51] [PASSED] oob_was/14020001231
[20:14:51] [PASSED] oob_was/16023683509
[20:14:51] [PASSED] oob_was/14025515070
[20:14:51] [PASSED] oob_was/15015404425_disable
[20:14:51] [PASSED] oob_was/16026007364
[20:14:51] [PASSED] oob_was/14020316580
[20:14:51] [PASSED] oob_was/14025883347
[20:14:51] [PASSED] oob_was/16029380221
[20:14:51] [PASSED] oob_was/22022079272
[20:14:51] [PASSED] oob_was/16029897822
[20:14:51] [PASSED] oob_was/14027054324
[20:14:51] ============== [PASSED] xe_rtp_table_oob_test ==============
[20:14:51] ================ xe_rtp_table_dev_oob_test ================
[20:14:51] [PASSED] device_oob_was/22010954014
[20:14:51] [PASSED] device_oob_was/15015404425
[20:14:51] [PASSED] device_oob_was/22019338487_display
[20:14:51] [PASSED] device_oob_was/14022085890
[20:14:51] [PASSED] device_oob_was/14026539277
[20:14:51] [PASSED] device_oob_was/14026633728
[20:14:51] [PASSED] device_oob_was/14026746987
[20:14:51] [PASSED] device_oob_was/14026779378
[20:14:51] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[20:14:51] ========== xe_rtp_table_missing_upper_bound_test ==========
[20:14:51] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[20:14:51] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[20:14:51] [PASSED] register_whitelist/1806527549
[20:14:51] [PASSED] register_whitelist/allow_read_ctx_timestamp
[20:14:51] [PASSED] register_whitelist/allow_read_queue_timestamp
[20:14:51] [PASSED] register_whitelist/16014440446
[20:14:51] [PASSED] register_whitelist/16017236439
[20:14:51] [PASSED] register_whitelist/16020183090
[20:14:51] [PASSED] register_whitelist/14024997852
[20:14:51] [PASSED] register_whitelist/14024997852
[20:14:51] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[20:14:51] =============== [PASSED] xe_rtp_tables_test ================
[20:14:51] =================== xe_rtp (3 subtests) ====================
[20:14:51] =================== xe_rtp_rules_tests ====================
[20:14:51] [PASSED] no
[20:14:51] [PASSED] yes
[20:14:51] [PASSED] no-and-no
[20:14:51] [PASSED] no-and-yes
[20:14:51] [PASSED] yes-and-no
[20:14:51] [PASSED] yes-and-yes
[20:14:51] [PASSED] no-or-no
[20:14:51] [PASSED] no-or-yes
[20:14:51] [PASSED] yes-or-no
[20:14:51] [PASSED] yes-or-yes
[20:14:51] [PASSED] no-yes-or-yes-no
[20:14:51] [PASSED] no-yes-or-yes-yes
[20:14:51] [PASSED] yes-yes-or-no-yes
[20:14:51] [PASSED] yes-yes-or-yes-yes
[20:14:51] [PASSED] no-no-or-yes-or-no
[20:14:51] [PASSED] or
[20:14:51] [PASSED] or-yes
[20:14:51] [PASSED] or-no
[20:14:51] [PASSED] yes-or
[20:14:51] [PASSED] no-or
[20:14:51] [PASSED] no-or-or-yes
[20:14:51] [PASSED] yes-or-or-no
[20:14:51] [PASSED] no-or-or-no
[20:14:51] [PASSED] missing-context-engine-class
[20:14:51] [PASSED] missing-context-engine-class-or-yes
[20:14:51] [PASSED] missing-context-engine-class-or-or-yes
[20:14:51] =============== [PASSED] xe_rtp_rules_tests ================
[20:14:51] =============== xe_rtp_process_to_sr_tests ================
[20:14:51] [PASSED] coalesce-same-reg
[20:14:51] [PASSED] coalesce-same-reg-literal-and-func
[20:14:51] [PASSED] no-match-no-add
[20:14:51] [PASSED] two-regs-two-entries
[20:14:51] [PASSED] clr-one-set-other
[20:14:51] [PASSED] set-field
[20:14:51] [PASSED] conflict-duplicate
[20:14:51] [PASSED] conflict-not-disjoint
[20:14:51] [PASSED] conflict-not-disjoint-literal-and-func
[20:14:51] [PASSED] conflict-reg-type
[20:14:51] [PASSED] bad-mcr-reg-forced-to-regular
[20:14:51] [PASSED] bad-regular-reg-forced-to-mcr
[20:14:51] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[20:14:51] ================== xe_rtp_process_tests ===================
[20:14:51] [PASSED] active1
[20:14:51] [PASSED] active2
[20:14:51] [PASSED] active-inactive
[20:14:51] [PASSED] inactive-active
[20:14:51] [PASSED] inactive-active-inactive
[20:14:51] [PASSED] inactive-inactive-inactive
[20:14:51] ============== [PASSED] xe_rtp_process_tests ===============
[20:14:51] ===================== [PASSED] xe_rtp ======================
[20:14:51] ==================== xe_wa (1 subtest) =====================
[20:14:51] ======================== xe_wa_gt =========================
[20:14:51] [PASSED] TIGERLAKE B0
[20:14:51] [PASSED] DG1 A0
[20:14:51] [PASSED] DG1 B0
[20:14:51] [PASSED] ALDERLAKE_S A0
[20:14:51] [PASSED] ALDERLAKE_S B0
[20:14:51] [PASSED] ALDERLAKE_S C0
[20:14:51] [PASSED] ALDERLAKE_S D0
[20:14:51] [PASSED] ALDERLAKE_P A0
[20:14:51] [PASSED] ALDERLAKE_P B0
[20:14:51] [PASSED] ALDERLAKE_P C0
[20:14:51] [PASSED] ALDERLAKE_S RPLS D0
[20:14:51] [PASSED] ALDERLAKE_P RPLU E0
[20:14:51] [PASSED] DG2 G10 C0
[20:14:51] [PASSED] DG2 G11 B1
[20:14:51] [PASSED] DG2 G12 A1
[20:14:51] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[20:14:51] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[20:14:52] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[20:14:52] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[20:14:52] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[20:14:52] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[20:14:52] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[20:14:52] ==================== [PASSED] xe_wa_gt =====================
[20:14:52] ====================== [PASSED] xe_wa ======================
[20:14:52] ============================================================
[20:14:52] Testing complete. Ran 742 tests: passed: 724, skipped: 18
[20:14:52] Elapsed time: 36.909s total, 4.412s configuring, 31.831s building, 0.635s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[20:14:52] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[20:14:53] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[20:15:18] Starting KUnit Kernel (1/1)...
[20:15:18] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[20:15:18] ============ drm_test_pick_cmdline (2 subtests) ============
[20:15:18] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[20:15:18] =============== drm_test_pick_cmdline_named ===============
[20:15:18] [PASSED] NTSC
[20:15:18] [PASSED] NTSC-J
[20:15:18] [PASSED] PAL
[20:15:18] [PASSED] PAL-M
[20:15:18] =========== [PASSED] drm_test_pick_cmdline_named ===========
[20:15:18] ============== [PASSED] drm_test_pick_cmdline ==============
[20:15:18] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[20:15:18] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[20:15:18] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[20:15:18] =========== drm_validate_clone_mode (2 subtests) ===========
[20:15:18] ============== drm_test_check_in_clone_mode ===============
[20:15:18] [PASSED] in_clone_mode
[20:15:18] [PASSED] not_in_clone_mode
[20:15:18] ========== [PASSED] drm_test_check_in_clone_mode ===========
[20:15:18] =============== drm_test_check_valid_clones ===============
[20:15:18] [PASSED] not_in_clone_mode
[20:15:18] [PASSED] valid_clone
[20:15:18] [PASSED] invalid_clone
[20:15:18] =========== [PASSED] drm_test_check_valid_clones ===========
[20:15:18] ============= [PASSED] drm_validate_clone_mode =============
[20:15:18] ============= drm_validate_modeset (1 subtest) =============
[20:15:18] [PASSED] drm_test_check_connector_changed_modeset
[20:15:18] ============== [PASSED] drm_validate_modeset ===============
[20:15:18] ====== drm_test_bridge_get_current_state (1 subtest) =======
[20:15:18] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[20:15:18] ======== [PASSED] drm_test_bridge_get_current_state ========
[20:15:18] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[20:15:18] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[20:15:18] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[20:15:18] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[20:15:18] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[20:15:18] ============== drm_bridge_alloc (2 subtests) ===============
[20:15:18] [PASSED] drm_test_drm_bridge_alloc_basic
[20:15:18] [PASSED] drm_test_drm_bridge_alloc_get_put
[20:15:18] ================ [PASSED] drm_bridge_alloc =================
[20:15:18] ============= drm_bridge_bus_fmt (5 subtests) ==============
[20:15:18] [PASSED] drm_test_bridge_rgb_yuv_rgb
[20:15:18] [PASSED] drm_test_bridge_must_convert_to_yuv444
[20:15:18] [PASSED] drm_test_bridge_hdmi_auto_rgb
[20:15:18] [PASSED] drm_test_bridge_auto_first
[20:15:18] [PASSED] drm_test_bridge_rgb_yuv_no_path
[20:15:18] =============== [PASSED] drm_bridge_bus_fmt ================
[20:15:18] ============= drm_cmdline_parser (40 subtests) =============
[20:15:18] [PASSED] drm_test_cmdline_force_d_only
[20:15:18] [PASSED] drm_test_cmdline_force_D_only_dvi
[20:15:18] [PASSED] drm_test_cmdline_force_D_only_hdmi
[20:15:18] [PASSED] drm_test_cmdline_force_D_only_not_digital
[20:15:18] [PASSED] drm_test_cmdline_force_e_only
[20:15:18] [PASSED] drm_test_cmdline_res
[20:15:18] [PASSED] drm_test_cmdline_res_vesa
[20:15:18] [PASSED] drm_test_cmdline_res_vesa_rblank
[20:15:18] [PASSED] drm_test_cmdline_res_rblank
[20:15:18] [PASSED] drm_test_cmdline_res_bpp
[20:15:18] [PASSED] drm_test_cmdline_res_refresh
[20:15:18] [PASSED] drm_test_cmdline_res_bpp_refresh
[20:15:18] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[20:15:18] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[20:15:18] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[20:15:18] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[20:15:18] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[20:15:18] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[20:15:18] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[20:15:18] [PASSED] drm_test_cmdline_res_margins_force_on
[20:15:18] [PASSED] drm_test_cmdline_res_vesa_margins
[20:15:18] [PASSED] drm_test_cmdline_name
[20:15:18] [PASSED] drm_test_cmdline_name_bpp
[20:15:18] [PASSED] drm_test_cmdline_name_option
[20:15:18] [PASSED] drm_test_cmdline_name_bpp_option
[20:15:18] [PASSED] drm_test_cmdline_rotate_0
[20:15:18] [PASSED] drm_test_cmdline_rotate_90
[20:15:18] [PASSED] drm_test_cmdline_rotate_180
[20:15:18] [PASSED] drm_test_cmdline_rotate_270
[20:15:18] [PASSED] drm_test_cmdline_hmirror
[20:15:18] [PASSED] drm_test_cmdline_vmirror
[20:15:18] [PASSED] drm_test_cmdline_margin_options
[20:15:18] [PASSED] drm_test_cmdline_multiple_options
[20:15:18] [PASSED] drm_test_cmdline_bpp_extra_and_option
[20:15:18] [PASSED] drm_test_cmdline_extra_and_option
[20:15:18] [PASSED] drm_test_cmdline_freestanding_options
[20:15:18] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[20:15:18] [PASSED] drm_test_cmdline_panel_orientation
[20:15:18] ================ drm_test_cmdline_invalid =================
[20:15:18] [PASSED] margin_only
[20:15:18] [PASSED] interlace_only
[20:15:18] [PASSED] res_missing_x
[20:15:18] [PASSED] res_missing_y
[20:15:18] [PASSED] res_bad_y
[20:15:18] [PASSED] res_missing_y_bpp
[20:15:18] [PASSED] res_bad_bpp
[20:15:18] [PASSED] res_bad_refresh
[20:15:18] [PASSED] res_bpp_refresh_force_on_off
[20:15:18] [PASSED] res_invalid_mode
[20:15:18] [PASSED] res_bpp_wrong_place_mode
[20:15:18] [PASSED] name_bpp_refresh
[20:15:18] [PASSED] name_refresh
[20:15:18] [PASSED] name_refresh_wrong_mode
[20:15:18] [PASSED] name_refresh_invalid_mode
[20:15:18] [PASSED] rotate_multiple
[20:15:18] [PASSED] rotate_invalid_val
[20:15:18] [PASSED] rotate_truncated
[20:15:18] [PASSED] invalid_option
[20:15:18] [PASSED] invalid_tv_option
[20:15:18] [PASSED] truncated_tv_option
[20:15:18] ============ [PASSED] drm_test_cmdline_invalid =============
[20:15:18] =============== drm_test_cmdline_tv_options ===============
[20:15:18] [PASSED] NTSC
[20:15:18] [PASSED] NTSC_443
[20:15:18] [PASSED] NTSC_J
[20:15:18] [PASSED] PAL
[20:15:18] [PASSED] PAL_M
[20:15:18] [PASSED] PAL_N
[20:15:18] [PASSED] SECAM
[20:15:18] [PASSED] MONO_525
[20:15:18] [PASSED] MONO_625
[20:15:18] =========== [PASSED] drm_test_cmdline_tv_options ===========
[20:15:18] =============== [PASSED] drm_cmdline_parser ================
[20:15:18] ========== drmm_connector_hdmi_init (20 subtests) ==========
[20:15:18] [PASSED] drm_test_connector_hdmi_init_valid
[20:15:18] [PASSED] drm_test_connector_hdmi_init_bpc_8
[20:15:18] [PASSED] drm_test_connector_hdmi_init_bpc_10
[20:15:18] [PASSED] drm_test_connector_hdmi_init_bpc_12
[20:15:18] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[20:15:18] [PASSED] drm_test_connector_hdmi_init_bpc_null
[20:15:18] [PASSED] drm_test_connector_hdmi_init_formats_empty
[20:15:18] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[20:15:18] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[20:15:18] [PASSED] supported_formats=0x9 yuv420_allowed=1
[20:15:18] [PASSED] supported_formats=0x9 yuv420_allowed=0
[20:15:18] [PASSED] supported_formats=0x5 yuv420_allowed=1
[20:15:18] [PASSED] supported_formats=0x5 yuv420_allowed=0
[20:15:18] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[20:15:18] [PASSED] drm_test_connector_hdmi_init_null_ddc
[20:15:18] [PASSED] drm_test_connector_hdmi_init_null_product
[20:15:18] [PASSED] drm_test_connector_hdmi_init_null_vendor
[20:15:18] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[20:15:18] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[20:15:18] [PASSED] drm_test_connector_hdmi_init_product_valid
[20:15:18] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[20:15:18] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[20:15:18] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[20:15:18] ========= drm_test_connector_hdmi_init_type_valid =========
[20:15:18] [PASSED] HDMI-A
[20:15:18] [PASSED] HDMI-B
[20:15:18] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[20:15:18] ======== drm_test_connector_hdmi_init_type_invalid ========
[20:15:18] [PASSED] Unknown
[20:15:18] [PASSED] VGA
[20:15:18] [PASSED] DVI-I
[20:15:18] [PASSED] DVI-D
[20:15:18] [PASSED] DVI-A
[20:15:18] [PASSED] Composite
[20:15:18] [PASSED] SVIDEO
[20:15:18] [PASSED] LVDS
[20:15:18] [PASSED] Component
[20:15:18] [PASSED] DIN
[20:15:18] [PASSED] DP
[20:15:18] [PASSED] TV
[20:15:18] [PASSED] eDP
[20:15:18] [PASSED] Virtual
[20:15:18] [PASSED] DSI
[20:15:18] [PASSED] DPI
[20:15:18] [PASSED] Writeback
[20:15:18] [PASSED] SPI
[20:15:18] [PASSED] USB
[20:15:18] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[20:15:18] ============ [PASSED] drmm_connector_hdmi_init =============
[20:15:18] ============= drmm_connector_init (3 subtests) =============
[20:15:18] [PASSED] drm_test_drmm_connector_init
[20:15:18] [PASSED] drm_test_drmm_connector_init_null_ddc
[20:15:18] ========= drm_test_drmm_connector_init_type_valid =========
[20:15:18] [PASSED] Unknown
[20:15:18] [PASSED] VGA
[20:15:18] [PASSED] DVI-I
[20:15:18] [PASSED] DVI-D
[20:15:18] [PASSED] DVI-A
[20:15:18] [PASSED] Composite
[20:15:18] [PASSED] SVIDEO
[20:15:18] [PASSED] LVDS
[20:15:18] [PASSED] Component
[20:15:18] [PASSED] DIN
[20:15:18] [PASSED] DP
[20:15:18] [PASSED] HDMI-A
[20:15:18] [PASSED] HDMI-B
[20:15:18] [PASSED] TV
[20:15:18] [PASSED] eDP
[20:15:18] [PASSED] Virtual
[20:15:18] [PASSED] DSI
[20:15:18] [PASSED] DPI
[20:15:18] [PASSED] Writeback
[20:15:18] [PASSED] SPI
[20:15:18] [PASSED] USB
[20:15:18] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[20:15:18] =============== [PASSED] drmm_connector_init ===============
[20:15:18] ========= drm_connector_dynamic_init (6 subtests) ==========
[20:15:18] [PASSED] drm_test_drm_connector_dynamic_init
[20:15:18] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[20:15:18] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[20:15:18] [PASSED] drm_test_drm_connector_dynamic_init_properties
[20:15:18] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[20:15:18] [PASSED] Unknown
[20:15:18] [PASSED] VGA
[20:15:18] [PASSED] DVI-I
[20:15:18] [PASSED] DVI-D
[20:15:18] [PASSED] DVI-A
[20:15:18] [PASSED] Composite
[20:15:18] [PASSED] SVIDEO
[20:15:18] [PASSED] LVDS
[20:15:18] [PASSED] Component
[20:15:18] [PASSED] DIN
[20:15:18] [PASSED] DP
[20:15:18] [PASSED] HDMI-A
[20:15:18] [PASSED] HDMI-B
[20:15:18] [PASSED] TV
[20:15:18] [PASSED] eDP
[20:15:18] [PASSED] Virtual
[20:15:18] [PASSED] DSI
[20:15:18] [PASSED] DPI
[20:15:18] [PASSED] Writeback
[20:15:18] [PASSED] SPI
[20:15:18] [PASSED] USB
[20:15:18] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[20:15:18] ======== drm_test_drm_connector_dynamic_init_name =========
[20:15:18] [PASSED] Unknown
[20:15:18] [PASSED] VGA
[20:15:18] [PASSED] DVI-I
[20:15:18] [PASSED] DVI-D
[20:15:18] [PASSED] DVI-A
[20:15:18] [PASSED] Composite
[20:15:18] [PASSED] SVIDEO
[20:15:18] [PASSED] LVDS
[20:15:18] [PASSED] Component
[20:15:18] [PASSED] DIN
[20:15:18] [PASSED] DP
[20:15:18] [PASSED] HDMI-A
[20:15:18] [PASSED] HDMI-B
[20:15:18] [PASSED] TV
[20:15:18] [PASSED] eDP
[20:15:18] [PASSED] Virtual
[20:15:18] [PASSED] DSI
[20:15:18] [PASSED] DPI
[20:15:18] [PASSED] Writeback
[20:15:18] [PASSED] SPI
[20:15:18] [PASSED] USB
[20:15:18] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[20:15:18] =========== [PASSED] drm_connector_dynamic_init ============
[20:15:18] ==== drm_connector_dynamic_register_early (4 subtests) =====
[20:15:18] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[20:15:18] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[20:15:18] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[20:15:18] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[20:15:18] ====== [PASSED] drm_connector_dynamic_register_early =======
[20:15:18] ======= drm_connector_dynamic_register (7 subtests) ========
[20:15:18] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[20:15:18] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[20:15:18] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[20:15:18] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[20:15:18] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[20:15:18] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[20:15:18] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[20:15:18] ========= [PASSED] drm_connector_dynamic_register ==========
[20:15:18] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[20:15:18] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[20:15:18] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[20:15:18] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[20:15:18] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[20:15:18] ========== drm_test_get_tv_mode_from_name_valid ===========
[20:15:18] [PASSED] NTSC
[20:15:18] [PASSED] NTSC-443
[20:15:18] [PASSED] NTSC-J
[20:15:18] [PASSED] PAL
[20:15:18] [PASSED] PAL-M
[20:15:18] [PASSED] PAL-N
[20:15:18] [PASSED] SECAM
[20:15:18] [PASSED] Mono
[20:15:18] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[20:15:18] [PASSED] drm_test_get_tv_mode_from_name_truncated
[20:15:18] ============ [PASSED] drm_get_tv_mode_from_name ============
[20:15:18] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[20:15:18] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[20:15:18] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[20:15:18] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[20:15:18] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[20:15:18] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[20:15:18] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[20:15:18] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[20:15:18] [PASSED] VIC 96
[20:15:18] [PASSED] VIC 97
[20:15:18] [PASSED] VIC 101
[20:15:18] [PASSED] VIC 102
[20:15:18] [PASSED] VIC 106
[20:15:18] [PASSED] VIC 107
[20:15:18] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[20:15:18] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[20:15:18] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[20:15:18] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[20:15:18] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[20:15:18] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[20:15:18] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[20:15:18] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[20:15:18] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[20:15:18] [PASSED] Automatic
[20:15:18] [PASSED] Full
[20:15:18] [PASSED] Limited 16:235
[20:15:18] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[20:15:18] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[20:15:18] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[20:15:18] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[20:15:18] === drm_test_drm_hdmi_connector_get_output_format_name ====
[20:15:18] [PASSED] RGB
[20:15:18] [PASSED] YUV 4:2:0
[20:15:18] [PASSED] YUV 4:2:2
[20:15:18] [PASSED] YUV 4:4:4
[20:15:18] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[20:15:18] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[20:15:18] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[20:15:18] ============= drm_damage_helper (21 subtests) ==============
[20:15:18] [PASSED] drm_test_damage_iter_no_damage
[20:15:18] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[20:15:18] [PASSED] drm_test_damage_iter_no_damage_src_moved
[20:15:18] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[20:15:18] [PASSED] drm_test_damage_iter_no_damage_not_visible
[20:15:18] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[20:15:18] [PASSED] drm_test_damage_iter_no_damage_no_fb
[20:15:18] [PASSED] drm_test_damage_iter_simple_damage
[20:15:18] [PASSED] drm_test_damage_iter_single_damage
[20:15:18] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[20:15:18] [PASSED] drm_test_damage_iter_single_damage_outside_src
[20:15:18] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[20:15:18] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[20:15:18] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[20:15:18] [PASSED] drm_test_damage_iter_single_damage_src_moved
[20:15:18] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[20:15:18] [PASSED] drm_test_damage_iter_damage
[20:15:18] [PASSED] drm_test_damage_iter_damage_one_intersect
[20:15:18] [PASSED] drm_test_damage_iter_damage_one_outside
[20:15:18] [PASSED] drm_test_damage_iter_damage_src_moved
[20:15:18] [PASSED] drm_test_damage_iter_damage_not_visible
[20:15:18] ================ [PASSED] drm_damage_helper ================
[20:15:18] ============== drm_dp_mst_helper (3 subtests) ==============
[20:15:18] ============== drm_test_dp_mst_calc_pbn_mode ==============
[20:15:18] [PASSED] Clock 154000 BPP 30 DSC disabled
[20:15:18] [PASSED] Clock 234000 BPP 30 DSC disabled
[20:15:18] [PASSED] Clock 297000 BPP 24 DSC disabled
[20:15:18] [PASSED] Clock 332880 BPP 24 DSC enabled
[20:15:18] [PASSED] Clock 324540 BPP 24 DSC enabled
[20:15:18] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[20:15:18] ============== drm_test_dp_mst_calc_pbn_div ===============
[20:15:18] [PASSED] Link rate 2000000 lane count 4
[20:15:18] [PASSED] Link rate 2000000 lane count 2
[20:15:18] [PASSED] Link rate 2000000 lane count 1
[20:15:18] [PASSED] Link rate 1350000 lane count 4
[20:15:18] [PASSED] Link rate 1350000 lane count 2
[20:15:18] [PASSED] Link rate 1350000 lane count 1
[20:15:18] [PASSED] Link rate 1000000 lane count 4
[20:15:18] [PASSED] Link rate 1000000 lane count 2
[20:15:18] [PASSED] Link rate 1000000 lane count 1
[20:15:18] [PASSED] Link rate 810000 lane count 4
[20:15:18] [PASSED] Link rate 810000 lane count 2
[20:15:18] [PASSED] Link rate 810000 lane count 1
[20:15:18] [PASSED] Link rate 540000 lane count 4
[20:15:18] [PASSED] Link rate 540000 lane count 2
[20:15:18] [PASSED] Link rate 540000 lane count 1
[20:15:18] [PASSED] Link rate 270000 lane count 4
[20:15:18] [PASSED] Link rate 270000 lane count 2
[20:15:18] [PASSED] Link rate 270000 lane count 1
[20:15:18] [PASSED] Link rate 162000 lane count 4
[20:15:18] [PASSED] Link rate 162000 lane count 2
[20:15:18] [PASSED] Link rate 162000 lane count 1
[20:15:18] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[20:15:18] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[20:15:18] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[20:15:18] [PASSED] DP_POWER_UP_PHY with port number
[20:15:18] [PASSED] DP_POWER_DOWN_PHY with port number
[20:15:18] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[20:15:18] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[20:15:18] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[20:15:18] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[20:15:18] [PASSED] DP_QUERY_PAYLOAD with port number
[20:15:18] [PASSED] DP_QUERY_PAYLOAD with VCPI
[20:15:18] [PASSED] DP_REMOTE_DPCD_READ with port number
[20:15:18] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[20:15:18] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[20:15:18] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[20:15:18] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[20:15:18] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[20:15:18] [PASSED] DP_REMOTE_I2C_READ with port number
[20:15:18] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[20:15:18] [PASSED] DP_REMOTE_I2C_READ with transactions array
[20:15:18] [PASSED] DP_REMOTE_I2C_WRITE with port number
[20:15:18] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[20:15:18] [PASSED] DP_REMOTE_I2C_WRITE with data array
[20:15:18] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[20:15:18] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[20:15:18] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[20:15:18] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[20:15:18] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[20:15:18] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[20:15:18] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[20:15:18] ================ [PASSED] drm_dp_mst_helper ================
[20:15:18] ================== drm_exec (7 subtests) ===================
[20:15:18] [PASSED] sanitycheck
[20:15:18] [PASSED] test_lock
[20:15:18] [PASSED] test_lock_unlock
[20:15:18] [PASSED] test_duplicates
[20:15:18] [PASSED] test_prepare
[20:15:18] [PASSED] test_prepare_array
[20:15:18] [PASSED] test_multiple_loops
[20:15:18] ==================== [PASSED] drm_exec =====================
[20:15:18] =========== drm_format_helper_test (17 subtests) ===========
[20:15:18] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[20:15:18] [PASSED] single_pixel_source_buffer
[20:15:18] [PASSED] single_pixel_clip_rectangle
[20:15:18] [PASSED] well_known_colors
[20:15:18] [PASSED] destination_pitch
[20:15:18] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[20:15:18] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[20:15:18] [PASSED] single_pixel_source_buffer
[20:15:18] [PASSED] single_pixel_clip_rectangle
[20:15:18] [PASSED] well_known_colors
[20:15:18] [PASSED] destination_pitch
[20:15:18] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[20:15:18] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[20:15:18] [PASSED] single_pixel_source_buffer
[20:15:18] [PASSED] single_pixel_clip_rectangle
[20:15:18] [PASSED] well_known_colors
[20:15:18] [PASSED] destination_pitch
[20:15:18] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[20:15:18] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[20:15:18] [PASSED] single_pixel_source_buffer
[20:15:18] [PASSED] single_pixel_clip_rectangle
[20:15:18] [PASSED] well_known_colors
[20:15:18] [PASSED] destination_pitch
[20:15:18] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[20:15:18] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[20:15:18] [PASSED] single_pixel_source_buffer
[20:15:18] [PASSED] single_pixel_clip_rectangle
[20:15:18] [PASSED] well_known_colors
[20:15:18] [PASSED] destination_pitch
[20:15:18] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[20:15:18] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[20:15:18] [PASSED] single_pixel_source_buffer
[20:15:18] [PASSED] single_pixel_clip_rectangle
[20:15:18] [PASSED] well_known_colors
[20:15:18] [PASSED] destination_pitch
[20:15:18] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[20:15:18] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[20:15:18] [PASSED] single_pixel_source_buffer
[20:15:18] [PASSED] single_pixel_clip_rectangle
[20:15:18] [PASSED] well_known_colors
[20:15:18] [PASSED] destination_pitch
[20:15:18] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[20:15:18] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[20:15:18] [PASSED] single_pixel_source_buffer
[20:15:18] [PASSED] single_pixel_clip_rectangle
[20:15:18] [PASSED] well_known_colors
[20:15:18] [PASSED] destination_pitch
[20:15:18] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[20:15:18] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[20:15:18] [PASSED] single_pixel_source_buffer
[20:15:18] [PASSED] single_pixel_clip_rectangle
[20:15:18] [PASSED] well_known_colors
[20:15:18] [PASSED] destination_pitch
[20:15:18] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[20:15:18] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[20:15:18] [PASSED] single_pixel_source_buffer
[20:15:18] [PASSED] single_pixel_clip_rectangle
[20:15:18] [PASSED] well_known_colors
[20:15:18] [PASSED] destination_pitch
[20:15:18] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[20:15:18] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[20:15:18] [PASSED] single_pixel_source_buffer
[20:15:18] [PASSED] single_pixel_clip_rectangle
[20:15:18] [PASSED] well_known_colors
[20:15:18] [PASSED] destination_pitch
[20:15:18] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[20:15:18] ============== drm_test_fb_xrgb8888_to_mono ===============
[20:15:18] [PASSED] single_pixel_source_buffer
[20:15:18] [PASSED] single_pixel_clip_rectangle
[20:15:18] [PASSED] well_known_colors
[20:15:18] [PASSED] destination_pitch
[20:15:18] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[20:15:18] ==================== drm_test_fb_swab =====================
[20:15:18] [PASSED] single_pixel_source_buffer
[20:15:18] [PASSED] single_pixel_clip_rectangle
[20:15:18] [PASSED] well_known_colors
[20:15:18] [PASSED] destination_pitch
[20:15:18] ================ [PASSED] drm_test_fb_swab =================
[20:15:18] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[20:15:18] [PASSED] single_pixel_source_buffer
[20:15:18] [PASSED] single_pixel_clip_rectangle
[20:15:18] [PASSED] well_known_colors
[20:15:18] [PASSED] destination_pitch
[20:15:18] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[20:15:18] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[20:15:18] [PASSED] single_pixel_source_buffer
[20:15:18] [PASSED] single_pixel_clip_rectangle
[20:15:18] [PASSED] well_known_colors
[20:15:18] [PASSED] destination_pitch
[20:15:18] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[20:15:18] ================= drm_test_fb_clip_offset =================
[20:15:18] [PASSED] pass through
[20:15:18] [PASSED] horizontal offset
[20:15:18] [PASSED] vertical offset
[20:15:18] [PASSED] horizontal and vertical offset
[20:15:18] [PASSED] horizontal offset (custom pitch)
[20:15:18] [PASSED] vertical offset (custom pitch)
[20:15:18] [PASSED] horizontal and vertical offset (custom pitch)
[20:15:18] ============= [PASSED] drm_test_fb_clip_offset =============
[20:15:18] =================== drm_test_fb_memcpy ====================
[20:15:18] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[20:15:18] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[20:15:18] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[20:15:18] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[20:15:18] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[20:15:18] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[20:15:18] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[20:15:18] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[20:15:18] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[20:15:18] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[20:15:18] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[20:15:18] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[20:15:18] =============== [PASSED] drm_test_fb_memcpy ================
[20:15:18] ============= [PASSED] drm_format_helper_test ==============
[20:15:18] ================= drm_format (18 subtests) =================
[20:15:18] [PASSED] drm_test_format_block_width_invalid
[20:15:18] [PASSED] drm_test_format_block_width_one_plane
[20:15:18] [PASSED] drm_test_format_block_width_two_plane
[20:15:18] [PASSED] drm_test_format_block_width_three_plane
[20:15:18] [PASSED] drm_test_format_block_width_tiled
[20:15:18] [PASSED] drm_test_format_block_height_invalid
[20:15:18] [PASSED] drm_test_format_block_height_one_plane
[20:15:18] [PASSED] drm_test_format_block_height_two_plane
[20:15:18] [PASSED] drm_test_format_block_height_three_plane
[20:15:18] [PASSED] drm_test_format_block_height_tiled
[20:15:18] [PASSED] drm_test_format_min_pitch_invalid
[20:15:18] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[20:15:18] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[20:15:18] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[20:15:18] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[20:15:18] [PASSED] drm_test_format_min_pitch_two_plane
[20:15:18] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[20:15:18] [PASSED] drm_test_format_min_pitch_tiled
[20:15:18] =================== [PASSED] drm_format ====================
[20:15:18] ============== drm_framebuffer (10 subtests) ===============
[20:15:18] ========== drm_test_framebuffer_check_src_coords ==========
[20:15:18] [PASSED] Success: source fits into fb
[20:15:18] [PASSED] Fail: overflowing fb with x-axis coordinate
[20:15:18] [PASSED] Fail: overflowing fb with y-axis coordinate
[20:15:18] [PASSED] Fail: overflowing fb with source width
[20:15:18] [PASSED] Fail: overflowing fb with source height
[20:15:18] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[20:15:18] [PASSED] drm_test_framebuffer_cleanup
[20:15:18] =============== drm_test_framebuffer_create ===============
[20:15:18] [PASSED] ABGR8888 normal sizes
[20:15:18] [PASSED] ABGR8888 max sizes
[20:15:18] [PASSED] ABGR8888 pitch greater than min required
[20:15:18] [PASSED] ABGR8888 pitch less than min required
[20:15:18] [PASSED] ABGR8888 Invalid width
[20:15:18] [PASSED] ABGR8888 Invalid buffer handle
[20:15:18] [PASSED] No pixel format
[20:15:18] [PASSED] ABGR8888 Width 0
[20:15:18] [PASSED] ABGR8888 Height 0
[20:15:18] [PASSED] ABGR8888 Out of bound height * pitch combination
[20:15:18] [PASSED] ABGR8888 Large buffer offset
[20:15:18] [PASSED] ABGR8888 Buffer offset for inexistent plane
[20:15:18] [PASSED] ABGR8888 Invalid flag
[20:15:18] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[20:15:18] [PASSED] ABGR8888 Valid buffer modifier
[20:15:18] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[20:15:18] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[20:15:18] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[20:15:18] [PASSED] NV12 Normal sizes
[20:15:18] [PASSED] NV12 Max sizes
[20:15:18] [PASSED] NV12 Invalid pitch
[20:15:18] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[20:15:18] [PASSED] NV12 different modifier per-plane
[20:15:18] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[20:15:18] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[20:15:18] [PASSED] NV12 Modifier for inexistent plane
[20:15:18] [PASSED] NV12 Handle for inexistent plane
[20:15:18] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[20:15:18] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[20:15:18] [PASSED] YVU420 Normal sizes
[20:15:18] [PASSED] YVU420 Max sizes
[20:15:18] [PASSED] YVU420 Invalid pitch
[20:15:18] [PASSED] YVU420 Different pitches
[20:15:18] [PASSED] YVU420 Different buffer offsets/pitches
[20:15:18] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[20:15:18] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[20:15:18] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[20:15:18] [PASSED] YVU420 Valid modifier
[20:15:18] [PASSED] YVU420 Different modifiers per plane
[20:15:18] [PASSED] YVU420 Modifier for inexistent plane
[20:15:18] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[20:15:18] [PASSED] X0L2 Normal sizes
[20:15:18] [PASSED] X0L2 Max sizes
[20:15:18] [PASSED] X0L2 Invalid pitch
[20:15:18] [PASSED] X0L2 Pitch greater than minimum required
[20:15:18] [PASSED] X0L2 Handle for inexistent plane
[20:15:18] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[20:15:18] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[20:15:18] [PASSED] X0L2 Valid modifier
[20:15:18] [PASSED] X0L2 Modifier for inexistent plane
[20:15:18] =========== [PASSED] drm_test_framebuffer_create ===========
[20:15:18] [PASSED] drm_test_framebuffer_free
[20:15:18] [PASSED] drm_test_framebuffer_init
[20:15:18] [PASSED] drm_test_framebuffer_init_bad_format
[20:15:18] [PASSED] drm_test_framebuffer_init_dev_mismatch
[20:15:18] [PASSED] drm_test_framebuffer_lookup
[20:15:18] [PASSED] drm_test_framebuffer_lookup_inexistent
[20:15:18] [PASSED] drm_test_framebuffer_modifiers_not_supported
[20:15:18] ================= [PASSED] drm_framebuffer =================
[20:15:18] ================ drm_gem_shmem (8 subtests) ================
[20:15:18] [PASSED] drm_gem_shmem_test_obj_create
[20:15:18] [PASSED] drm_gem_shmem_test_obj_create_private
[20:15:18] [PASSED] drm_gem_shmem_test_pin_pages
[20:15:18] [PASSED] drm_gem_shmem_test_vmap
[20:15:18] [PASSED] drm_gem_shmem_test_get_sg_table
[20:15:18] [PASSED] drm_gem_shmem_test_get_pages_sgt
[20:15:18] [PASSED] drm_gem_shmem_test_madvise
[20:15:18] [PASSED] drm_gem_shmem_test_purge
[20:15:18] ================== [PASSED] drm_gem_shmem ==================
[20:15:18] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[20:15:18] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[20:15:18] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[20:15:18] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[20:15:18] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[20:15:18] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[20:15:18] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[20:15:18] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[20:15:18] [PASSED] Automatic
[20:15:18] [PASSED] Full
[20:15:18] [PASSED] Limited 16:235
[20:15:18] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[20:15:18] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[20:15:18] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[20:15:18] [PASSED] drm_test_check_disable_connector
[20:15:18] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[20:15:18] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[20:15:18] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[20:15:18] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[20:15:18] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[20:15:18] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[20:15:18] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[20:15:18] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[20:15:18] [PASSED] drm_test_check_output_bpc_dvi
[20:15:18] [PASSED] drm_test_check_output_bpc_format_vic_1
[20:15:18] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[20:15:18] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[20:15:18] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[20:15:18] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[20:15:18] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[20:15:18] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[20:15:18] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[20:15:18] ============ drm_test_check_hdmi_color_format =============
[20:15:18] [PASSED] AUTO -> RGB
[20:15:18] [PASSED] YCBCR422 -> YUV422
[20:15:18] [PASSED] YCBCR420 -> YUV420
[20:15:18] [PASSED] YCBCR444 -> YUV444
[20:15:18] [PASSED] RGB -> RGB
[20:15:18] ======== [PASSED] drm_test_check_hdmi_color_format =========
[20:15:18] ======== drm_test_check_hdmi_color_format_420_only ========
[20:15:18] [PASSED] RGB should fail
[20:15:18] [PASSED] YUV444 should fail
[20:15:18] [PASSED] YUV422 should fail
[20:15:18] [PASSED] YUV420 should work
[20:15:18] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[20:15:18] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[20:15:18] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[20:15:18] [PASSED] drm_test_check_broadcast_rgb_value
[20:15:18] [PASSED] drm_test_check_bpc_8_value
[20:15:18] [PASSED] drm_test_check_bpc_10_value
[20:15:18] [PASSED] drm_test_check_bpc_12_value
[20:15:18] [PASSED] drm_test_check_format_value
[20:15:18] [PASSED] drm_test_check_tmds_char_value
[20:15:18] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[20:15:18] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[20:15:18] [PASSED] drm_test_check_mode_valid
[20:15:18] [PASSED] drm_test_check_mode_valid_reject
[20:15:18] [PASSED] drm_test_check_mode_valid_reject_rate
[20:15:18] [PASSED] drm_test_check_mode_valid_reject_max_clock
[20:15:18] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[20:15:19] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[20:15:19] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[20:15:19] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[20:15:19] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[20:15:19] [PASSED] drm_test_check_infoframes
[20:15:19] [PASSED] drm_test_check_reject_avi_infoframe
[20:15:19] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[20:15:19] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[20:15:19] [PASSED] drm_test_check_reject_audio_infoframe
[20:15:19] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[20:15:19] ================= drm_managed (2 subtests) =================
[20:15:19] [PASSED] drm_test_managed_release_action
[20:15:19] [PASSED] drm_test_managed_run_action
[20:15:19] =================== [PASSED] drm_managed ===================
[20:15:19] =================== drm_mm (6 subtests) ====================
[20:15:19] [PASSED] drm_test_mm_init
[20:15:19] [PASSED] drm_test_mm_debug
[20:15:19] [PASSED] drm_test_mm_align32
[20:15:19] [PASSED] drm_test_mm_align64
[20:15:19] [PASSED] drm_test_mm_lowest
[20:15:19] [PASSED] drm_test_mm_highest
[20:15:19] ===================== [PASSED] drm_mm ======================
[20:15:19] ============= drm_modes_analog_tv (5 subtests) =============
[20:15:19] [PASSED] drm_test_modes_analog_tv_mono_576i
[20:15:19] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[20:15:19] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[20:15:19] [PASSED] drm_test_modes_analog_tv_pal_576i
[20:15:19] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[20:15:19] =============== [PASSED] drm_modes_analog_tv ===============
[20:15:19] ============== drm_plane_helper (2 subtests) ===============
[20:15:19] =============== drm_test_check_plane_state ================
[20:15:19] [PASSED] clipping_simple
[20:15:19] [PASSED] clipping_rotate_reflect
[20:15:19] [PASSED] positioning_simple
[20:15:19] [PASSED] upscaling
[20:15:19] [PASSED] downscaling
[20:15:19] [PASSED] rounding1
[20:15:19] [PASSED] rounding2
[20:15:19] [PASSED] rounding3
[20:15:19] [PASSED] rounding4
[20:15:19] =========== [PASSED] drm_test_check_plane_state ============
[20:15:19] =========== drm_test_check_invalid_plane_state ============
[20:15:19] [PASSED] positioning_invalid
[20:15:19] [PASSED] upscaling_invalid
[20:15:19] [PASSED] downscaling_invalid
[20:15:19] ======= [PASSED] drm_test_check_invalid_plane_state ========
[20:15:19] ================ [PASSED] drm_plane_helper =================
[20:15:19] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[20:15:19] ====== drm_test_connector_helper_tv_get_modes_check =======
[20:15:19] [PASSED] None
[20:15:19] [PASSED] PAL
[20:15:19] [PASSED] NTSC
[20:15:19] [PASSED] Both, NTSC Default
[20:15:19] [PASSED] Both, PAL Default
[20:15:19] [PASSED] Both, NTSC Default, with PAL on command-line
[20:15:19] [PASSED] Both, PAL Default, with NTSC on command-line
[20:15:19] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[20:15:19] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[20:15:19] ================== drm_rect (9 subtests) ===================
[20:15:19] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[20:15:19] [PASSED] drm_test_rect_clip_scaled_not_clipped
[20:15:19] [PASSED] drm_test_rect_clip_scaled_clipped
[20:15:19] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[20:15:19] ================= drm_test_rect_intersect =================
[20:15:19] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[20:15:19] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[20:15:19] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[20:15:19] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[20:15:19] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[20:15:19] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[20:15:19] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[20:15:19] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[20:15:19] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[20:15:19] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[20:15:19] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[20:15:19] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[20:15:19] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[20:15:19] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[20:15:19] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[20:15:19] ============= [PASSED] drm_test_rect_intersect =============
[20:15:19] ================ drm_test_rect_calc_hscale ================
[20:15:19] [PASSED] normal use
[20:15:19] [PASSED] out of max range
[20:15:19] [PASSED] out of min range
[20:15:19] [PASSED] zero dst
[20:15:19] [PASSED] negative src
[20:15:19] [PASSED] negative dst
[20:15:19] ============ [PASSED] drm_test_rect_calc_hscale ============
[20:15:19] ================ drm_test_rect_calc_vscale ================
[20:15:19] [PASSED] normal use
[20:15:19] [PASSED] out of max range
[20:15:19] [PASSED] out of min range
[20:15:19] [PASSED] zero dst
[20:15:19] [PASSED] negative src
[20:15:19] [PASSED] negative dst
[20:15:19] ============ [PASSED] drm_test_rect_calc_vscale ============
[20:15:19] ================== drm_test_rect_rotate ===================
[20:15:19] [PASSED] reflect-x
[20:15:19] [PASSED] reflect-y
[20:15:19] [PASSED] rotate-0
[20:15:19] [PASSED] rotate-90
[20:15:19] [PASSED] rotate-180
[20:15:19] [PASSED] rotate-270
[20:15:19] ============== [PASSED] drm_test_rect_rotate ===============
[20:15:19] ================ drm_test_rect_rotate_inv =================
[20:15:19] [PASSED] reflect-x
[20:15:19] [PASSED] reflect-y
[20:15:19] [PASSED] rotate-0
[20:15:19] [PASSED] rotate-90
[20:15:19] [PASSED] rotate-180
[20:15:19] [PASSED] rotate-270
[20:15:19] ============ [PASSED] drm_test_rect_rotate_inv =============
[20:15:19] ==================== [PASSED] drm_rect =====================
[20:15:19] ============ drm_sysfb_modeset_test (1 subtest) ============
[20:15:19] ============ drm_test_sysfb_build_fourcc_list =============
[20:15:19] [PASSED] no native formats
[20:15:19] [PASSED] XRGB8888 as native format
[20:15:19] [PASSED] remove duplicates
[20:15:19] [PASSED] convert alpha formats
[20:15:19] [PASSED] random formats
[20:15:19] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[20:15:19] ============= [PASSED] drm_sysfb_modeset_test ==============
[20:15:19] ================== drm_fixp (2 subtests) ===================
[20:15:19] [PASSED] drm_test_int2fixp
[20:15:19] [PASSED] drm_test_sm2fixp
[20:15:19] ==================== [PASSED] drm_fixp =====================
[20:15:19] ============================================================
[20:15:19] Testing complete. Ran 637 tests: passed: 637
[20:15:19] Elapsed time: 26.865s total, 1.815s configuring, 24.832s building, 0.193s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[20:15:19] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[20:15:20] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[20:15:30] Starting KUnit Kernel (1/1)...
[20:15:30] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[20:15:30] ================= ttm_device (5 subtests) ==================
[20:15:30] [PASSED] ttm_device_init_basic
[20:15:30] [PASSED] ttm_device_init_multiple
[20:15:30] [PASSED] ttm_device_fini_basic
[20:15:30] [PASSED] ttm_device_init_no_vma_man
[20:15:30] ================== ttm_device_init_pools ==================
[20:15:30] [PASSED] No DMA allocations, no DMA32 required
[20:15:30] [PASSED] DMA allocations, DMA32 required
[20:15:30] [PASSED] No DMA allocations, DMA32 required
[20:15:30] [PASSED] DMA allocations, no DMA32 required
[20:15:30] ============== [PASSED] ttm_device_init_pools ==============
[20:15:30] =================== [PASSED] ttm_device ====================
[20:15:30] ================== ttm_pool (8 subtests) ===================
[20:15:30] ================== ttm_pool_alloc_basic ===================
[20:15:30] [PASSED] One page
[20:15:30] [PASSED] More than one page
[20:15:30] [PASSED] Above the allocation limit
[20:15:30] [PASSED] One page, with coherent DMA mappings enabled
[20:15:30] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[20:15:30] ============== [PASSED] ttm_pool_alloc_basic ===============
[20:15:30] ============== ttm_pool_alloc_basic_dma_addr ==============
[20:15:30] [PASSED] One page
[20:15:30] [PASSED] More than one page
[20:15:30] [PASSED] Above the allocation limit
[20:15:30] [PASSED] One page, with coherent DMA mappings enabled
[20:15:30] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[20:15:30] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[20:15:30] [PASSED] ttm_pool_alloc_order_caching_match
[20:15:30] [PASSED] ttm_pool_alloc_caching_mismatch
[20:15:30] [PASSED] ttm_pool_alloc_order_mismatch
[20:15:30] [PASSED] ttm_pool_free_dma_alloc
[20:15:30] [PASSED] ttm_pool_free_no_dma_alloc
[20:15:30] [PASSED] ttm_pool_fini_basic
[20:15:30] ==================== [PASSED] ttm_pool =====================
[20:15:30] ================ ttm_resource (8 subtests) =================
[20:15:30] ================= ttm_resource_init_basic =================
[20:15:30] [PASSED] Init resource in TTM_PL_SYSTEM
[20:15:30] [PASSED] Init resource in TTM_PL_VRAM
[20:15:30] [PASSED] Init resource in a private placement
[20:15:30] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[20:15:30] ============= [PASSED] ttm_resource_init_basic =============
[20:15:30] [PASSED] ttm_resource_init_pinned
[20:15:30] [PASSED] ttm_resource_fini_basic
[20:15:30] [PASSED] ttm_resource_manager_init_basic
[20:15:30] [PASSED] ttm_resource_manager_usage_basic
[20:15:30] [PASSED] ttm_resource_manager_set_used_basic
[20:15:30] [PASSED] ttm_sys_man_alloc_basic
[20:15:30] [PASSED] ttm_sys_man_free_basic
[20:15:30] ================== [PASSED] ttm_resource ===================
[20:15:30] =================== ttm_tt (15 subtests) ===================
[20:15:30] ==================== ttm_tt_init_basic ====================
[20:15:30] [PASSED] Page-aligned size
[20:15:30] [PASSED] Extra pages requested
[20:15:30] ================ [PASSED] ttm_tt_init_basic ================
[20:15:30] [PASSED] ttm_tt_init_misaligned
[20:15:30] [PASSED] ttm_tt_fini_basic
[20:15:30] [PASSED] ttm_tt_fini_sg
[20:15:30] [PASSED] ttm_tt_fini_shmem
[20:15:30] [PASSED] ttm_tt_create_basic
[20:15:30] [PASSED] ttm_tt_create_invalid_bo_type
[20:15:30] [PASSED] ttm_tt_create_ttm_exists
[20:15:30] [PASSED] ttm_tt_create_failed
[20:15:30] [PASSED] ttm_tt_destroy_basic
[20:15:30] [PASSED] ttm_tt_populate_null_ttm
[20:15:30] [PASSED] ttm_tt_populate_populated_ttm
[20:15:30] [PASSED] ttm_tt_unpopulate_basic
[20:15:30] [PASSED] ttm_tt_unpopulate_empty_ttm
[20:15:30] [PASSED] ttm_tt_swapin_basic
[20:15:30] ===================== [PASSED] ttm_tt ======================
[20:15:30] =================== ttm_bo (14 subtests) ===================
[20:15:30] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[20:15:30] [PASSED] Cannot be interrupted and sleeps
[20:15:30] [PASSED] Cannot be interrupted, locks straight away
[20:15:30] [PASSED] Can be interrupted, sleeps
[20:15:30] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[20:15:30] [PASSED] ttm_bo_reserve_locked_no_sleep
[20:15:30] [PASSED] ttm_bo_reserve_no_wait_ticket
[20:15:30] [PASSED] ttm_bo_reserve_double_resv
[20:15:30] [PASSED] ttm_bo_reserve_interrupted
[20:15:30] [PASSED] ttm_bo_reserve_deadlock
[20:15:30] [PASSED] ttm_bo_unreserve_basic
[20:15:30] [PASSED] ttm_bo_unreserve_pinned
[20:15:30] [PASSED] ttm_bo_unreserve_bulk
[20:15:30] [PASSED] ttm_bo_fini_basic
[20:15:30] [PASSED] ttm_bo_fini_shared_resv
[20:15:30] [PASSED] ttm_bo_pin_basic
[20:15:30] [PASSED] ttm_bo_pin_unpin_resource
[20:15:30] [PASSED] ttm_bo_multiple_pin_one_unpin
[20:15:30] ===================== [PASSED] ttm_bo ======================
[20:15:30] ============== ttm_bo_validate (22 subtests) ===============
[20:15:30] ============== ttm_bo_init_reserved_sys_man ===============
[20:15:30] [PASSED] Buffer object for userspace
[20:15:30] [PASSED] Kernel buffer object
[20:15:30] [PASSED] Shared buffer object
[20:15:30] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[20:15:30] ============== ttm_bo_init_reserved_mock_man ==============
[20:15:30] [PASSED] Buffer object for userspace
[20:15:30] [PASSED] Kernel buffer object
[20:15:30] [PASSED] Shared buffer object
[20:15:30] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[20:15:30] [PASSED] ttm_bo_init_reserved_resv
[20:15:30] ================== ttm_bo_validate_basic ==================
[20:15:30] [PASSED] Buffer object for userspace
[20:15:30] [PASSED] Kernel buffer object
[20:15:30] [PASSED] Shared buffer object
[20:15:30] ============== [PASSED] ttm_bo_validate_basic ==============
[20:15:30] [PASSED] ttm_bo_validate_invalid_placement
[20:15:30] ============= ttm_bo_validate_same_placement ==============
[20:15:30] [PASSED] System manager
[20:15:30] [PASSED] VRAM manager
[20:15:30] ========= [PASSED] ttm_bo_validate_same_placement ==========
[20:15:30] [PASSED] ttm_bo_validate_failed_alloc
[20:15:30] [PASSED] ttm_bo_validate_pinned
[20:15:30] [PASSED] ttm_bo_validate_busy_placement
[20:15:30] ================ ttm_bo_validate_multihop =================
[20:15:30] [PASSED] Buffer object for userspace
[20:15:30] [PASSED] Kernel buffer object
[20:15:30] [PASSED] Shared buffer object
[20:15:30] ============ [PASSED] ttm_bo_validate_multihop =============
[20:15:30] ========== ttm_bo_validate_no_placement_signaled ==========
[20:15:30] [PASSED] Buffer object in system domain, no page vector
[20:15:30] [PASSED] Buffer object in system domain with an existing page vector
[20:15:30] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[20:15:30] ======== ttm_bo_validate_no_placement_not_signaled ========
[20:15:30] [PASSED] Buffer object for userspace
[20:15:30] [PASSED] Kernel buffer object
[20:15:30] [PASSED] Shared buffer object
[20:15:30] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[20:15:30] [PASSED] ttm_bo_validate_move_fence_signaled
[20:15:30] ========= ttm_bo_validate_move_fence_not_signaled =========
[20:15:30] [PASSED] Waits for GPU
[20:15:30] [PASSED] Tries to lock straight away
[20:15:31] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[20:15:31] [PASSED] ttm_bo_validate_swapout
[20:15:31] [PASSED] ttm_bo_validate_happy_evict
[20:15:31] [PASSED] ttm_bo_validate_all_pinned_evict
[20:15:31] [PASSED] ttm_bo_validate_allowed_only_evict
[20:15:31] [PASSED] ttm_bo_validate_deleted_evict
[20:15:31] [PASSED] ttm_bo_validate_busy_domain_evict
[20:15:31] [PASSED] ttm_bo_validate_evict_gutting
[20:15:31] [PASSED] ttm_bo_validate_recrusive_evict
[20:15:31] ================= [PASSED] ttm_bo_validate =================
[20:15:31] ============================================================
[20:15:31] Testing complete. Ran 102 tests: passed: 102
[20:15:31] Elapsed time: 11.867s total, 1.827s configuring, 9.824s building, 0.182s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 14+ messages in thread
* ✓ Xe.CI.FULL: success for drm/xe/guc_ads: allocate UM queues in a separate UC BO (rev5)
2026-08-03 20:08 [PATCH v7 0/1] drm/xe/guc_ads: allocate UM queues in a separate UC BO Jia Yao
` (3 preceding siblings ...)
2026-08-03 20:15 ` ✓ CI.KUnit: success for drm/xe/guc_ads: allocate UM queues in a separate UC BO (rev5) Patchwork
@ 2026-08-03 22:41 ` Patchwork
2026-08-04 12:23 ` ✓ CI.KUnit: " Patchwork
5 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2026-08-03 22:41 UTC (permalink / raw)
To: Jia Yao; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 884 bytes --]
== Series Details ==
Series: drm/xe/guc_ads: allocate UM queues in a separate UC BO (rev5)
URL : https://patchwork.freedesktop.org/series/169535/
State : success
== Summary ==
CI Bug Log - changes from xe-5522-6c9c07af6c046bba0eb99704274f74038fc5e6a8_FULL -> xe-pw-169535v5_FULL
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (0 -> 0)
------------------------------
No changes in participating hosts
Changes
-------
No changes found
Build changes
-------------
* Linux: xe-5522-6c9c07af6c046bba0eb99704274f74038fc5e6a8 -> xe-pw-169535v5
IGT_9036: 9036
xe-5522-6c9c07af6c046bba0eb99704274f74038fc5e6a8: 6c9c07af6c046bba0eb99704274f74038fc5e6a8
xe-pw-169535v5: 169535v5
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169535v5/index.html
[-- Attachment #2: Type: text/html, Size: 1432 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v7 1/3] drm/xe/guc_ads: allocate UM queues in a separate BO
2026-08-03 20:08 ` [PATCH v7 1/3] drm/xe/guc_ads: allocate UM queues in a separate BO Jia Yao
@ 2026-08-04 7:43 ` Matthew Auld
2026-08-04 8:00 ` Matthew Auld
1 sibling, 0 replies; 14+ messages in thread
From: Matthew Auld @ 2026-08-04 7:43 UTC (permalink / raw)
To: Jia Yao, intel-xe; +Cc: Gwan-gyeong Mun, stable
On 03/08/2026 21:08, Jia Yao wrote:
> Move the UM queues into a dedicated UC BO (ads->um_queue_bo) and avoid
> CPU memset operations on it, which eliminates the CPU as a potential
> cacheline-polluting agent and helps maintain consistency between GAM
> writes and GuC reads.
>
> Fixes: 9c57bc08652a ("drm/xe/lnl: Drop force_probe requirement")
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Cc: <stable@vger.kernel.org> # v6.12+
> Signed-off-by: Jia Yao <jia.yao@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
> ---
> drivers/gpu/drm/xe/xe_guc.c | 6 ++
> drivers/gpu/drm/xe/xe_guc_ads.c | 89 +++++++++++++++++----------
> drivers/gpu/drm/xe/xe_guc_ads_types.h | 5 ++
> 3 files changed, 68 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> index 4286bd05c686..4f132bf8539d 100644
> --- a/drivers/gpu/drm/xe/xe_guc.c
> +++ b/drivers/gpu/drm/xe/xe_guc.c
> @@ -732,6 +732,12 @@ static int xe_guc_realloc_post_hwconfig(struct xe_guc *guc)
> if (ret)
> return ret;
>
> + if (guc->ads.um_queue_bo) {
> + ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->ads.um_queue_bo);
> + if (ret)
> + return ret;
> + }
> +
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
> index f0ac00586d3a..ef8e9cc35c8c 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ads.c
> +++ b/drivers/gpu/drm/xe/xe_guc_ads.c
> @@ -8,6 +8,7 @@
> #include <linux/fault-inject.h>
>
> #include <drm/drm_managed.h>
> +#include <drm/drm_prime.h>
>
> #include <generated/xe_wa_oob.h>
>
> @@ -64,10 +65,14 @@ ads_to_map(struct xe_guc_ads *ads)
>
> /*
> * The Additional Data Struct (ADS) has pointers for different buffers used by
> - * the GuC. One single gem object contains the ADS struct itself (guc_ads) and
> - * all the extra buffers indirectly linked via the ADS struct's entries.
> + * the GuC. One gem object (ads->bo) contains the ADS struct itself (guc_ads)
> + * and most of the extra buffers linked via the ADS struct's entries. The UM
> + * fault queues (PAGE_FAULT, PAGE_FAULT_RESPONSE, ACCESS_COUNTER rings) are
> + * kept in a separate BO (ads->um_queue_bo) so that the full memset of ads->bo
> + * performed on every GT reset does not discard fault descriptors already
> + * written into the rings by the GPU.
> *
> - * Layout of the ADS blob allocated for the GuC:
> + * Layout of the ADS blob (ads->bo):
> *
> * +---------------------------------------+ <== base
> * | guc_ads |
> @@ -99,10 +104,6 @@ ads_to_map(struct xe_guc_ads *ads)
> * +---------------------------------------+
> * | padding |
> * +---------------------------------------+ <== 4K aligned
> - * | UM queues |
> - * +---------------------------------------+
> - * | padding |
> - * +---------------------------------------+ <== 4K aligned
> * | private data |
> * +---------------------------------------+
> * | padding |
> @@ -156,16 +157,6 @@ static size_t guc_ads_capture_size(struct xe_guc_ads *ads)
> return PAGE_ALIGN(ads->capture_size);
> }
>
> -static size_t guc_ads_um_queues_size(struct xe_guc_ads *ads)
> -{
> - struct xe_device *xe = ads_to_xe(ads);
> -
> - if (!xe->info.has_usm)
> - return 0;
> -
> - return GUC_UM_QUEUE_SIZE * GUC_UM_HW_QUEUE_MAX;
> -}
> -
> static size_t guc_ads_private_data_size(struct xe_guc_ads *ads)
> {
> return PAGE_ALIGN(ads_to_guc(ads)->fw.private_data_size);
> @@ -206,22 +197,12 @@ static size_t guc_ads_capture_offset(struct xe_guc_ads *ads)
> return PAGE_ALIGN(offset);
> }
>
> -static size_t guc_ads_um_queues_offset(struct xe_guc_ads *ads)
> -{
> - u32 offset;
> -
> - offset = guc_ads_capture_offset(ads) +
> - guc_ads_capture_size(ads);
> -
> - return PAGE_ALIGN(offset);
> -}
> -
> static size_t guc_ads_private_data_offset(struct xe_guc_ads *ads)
> {
> size_t offset;
>
> - offset = guc_ads_um_queues_offset(ads) +
> - guc_ads_um_queues_size(ads);
> + offset = guc_ads_capture_offset(ads) +
> + guc_ads_capture_size(ads);
>
> return PAGE_ALIGN(offset);
> }
> @@ -461,6 +442,44 @@ int xe_guc_ads_init(struct xe_guc_ads *ads)
>
> ads->bo = bo;
>
> + if (xe->info.has_usm) {
> + /*
> + * Allocate a separate BO for the HW fault ring (UM queues).
> + *
> + * Round the size up to the next power of two so that
> + * (system memory, no IOMMU) the TTM pool issues a single
> + * alloc_pages(order=N) call, maximising the chance of getting
> + * a physically contiguous block. GuC requires contiguous DPA.
> + */
> + size_t um_size = roundup_pow_of_two(GUC_UM_QUEUE_SIZE *
> + GUC_UM_HW_QUEUE_MAX);
> +
> + bo = xe_managed_bo_create_pin_map(xe, tile, um_size,
> + XE_BO_FLAG_SYSTEM |
> + XE_BO_FLAG_GGTT |
> + XE_BO_FLAG_GGTT_INVALIDATE |
> + XE_BO_FLAG_PINNED_NORESTORE);
> + if (IS_ERR(bo))
> + return PTR_ERR(bo);
> +
> + /*
> + * On pre-Xe3p platforms, GAM (not GuC) accesses the UM queue
> + * ring via base_dpa, which must be a contiguous DMA address
> + * range. Verify that the allocated pages are contiguous in
> + * DMA address space.
> + */
> + if (xe_bo_sg(bo) &&
> + !xe_guc_using_main_gamctrl_queues(ads_to_guc(ads)) &&
> + unlikely(drm_prime_get_contiguous_size(xe_bo_sg(bo)) <
> + GUC_UM_QUEUE_SIZE * GUC_UM_HW_QUEUE_MAX)) {
> + drm_err(&xe->drm,
> + "UM fault queue memory is not contiguous in DMA address space; GAM requires contiguous DPA\n");
> + return -ENOMEM;
> + }
> +
> + ads->um_queue_bo = bo;
> + }
> +
> return 0;
> }
> ALLOW_ERROR_INJECTION(xe_guc_ads_init, ERRNO); /* See xe_pci_probe() */
> @@ -893,7 +912,7 @@ static void guc_mmio_reg_state_init(struct xe_guc_ads *ads)
>
> static void guc_um_init_params(struct xe_guc_ads *ads)
> {
> - u32 um_queue_offset = guc_ads_um_queues_offset(ads);
> + struct xe_bo *um_bo = ads->um_queue_bo;
> struct xe_guc *guc = ads_to_guc(ads);
> struct xe_device *xe = ads_to_xe(ads);
> u64 base_dpa;
> @@ -903,8 +922,14 @@ static void guc_um_init_params(struct xe_guc_ads *ads)
>
> with_dpa = !xe_guc_using_main_gamctrl_queues(guc);
>
> - base_ggtt = xe_bo_ggtt_addr(ads->bo) + um_queue_offset;
> - base_dpa = xe_bo_main_addr(ads->bo, PAGE_SIZE) + um_queue_offset;
> + if (um_bo) {
> + /* All USM platforms: UM queues in dedicated um_queue_bo */
> + base_ggtt = xe_bo_ggtt_addr(um_bo);
> + base_dpa = xe_bo_main_addr(um_bo, PAGE_SIZE);
> + } else {
> + /* Platform does not support USM: no UM queues, nothing to do */
> + return;
> + }
>
> for (i = 0; i < GUC_UM_HW_QUEUE_MAX; ++i) {
> /*
> diff --git a/drivers/gpu/drm/xe/xe_guc_ads_types.h b/drivers/gpu/drm/xe/xe_guc_ads_types.h
> index 48a8e092023f..845c1fbd93a4 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ads_types.h
> +++ b/drivers/gpu/drm/xe/xe_guc_ads_types.h
> @@ -16,6 +16,11 @@ struct xe_bo;
> struct xe_guc_ads {
> /** @bo: Xe BO for GuC ads blob */
> struct xe_bo *bo;
> + /**
> + * @um_queue_bo: Dedicated BO for the HW fault ring (UM queues).
> + * NULL if the platform does not support USM.
> + */
> + struct xe_bo *um_queue_bo;
> /** @golden_lrc_size: golden LRC size */
> size_t golden_lrc_size;
> /** @regset_size: size of register set passed to GuC for save/restore */
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v7 2/3] drm/xe/guc_ads: allocate UM queues in VRAM on dGFX
2026-08-03 20:08 ` [PATCH v7 2/3] drm/xe/guc_ads: allocate UM queues in VRAM on dGFX Jia Yao
@ 2026-08-04 7:45 ` Matthew Auld
0 siblings, 0 replies; 14+ messages in thread
From: Matthew Auld @ 2026-08-04 7:45 UTC (permalink / raw)
To: Jia Yao, intel-xe; +Cc: Gwan-gyeong Mun, stable
On 03/08/2026 21:08, Jia Yao wrote:
> On iGPU, the UM queue BO is allocated in system memory. On dGFX, the BO
> was previously created in system memory and later reallocated in
> xe_guc_realloc_post_hwconfig(). Allocate the UM queue BO directly in
> VRAM on dGFX, where it is ultimately required.
>
> Fixes: 9c57bc08652a ("drm/xe/lnl: Drop force_probe requirement")
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Cc: <stable@vger.kernel.org> # v6.12+
> Signed-off-by: Jia Yao <jia.yao@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
> ---
> drivers/gpu/drm/xe/xe_guc.c | 6 ------
> drivers/gpu/drm/xe/xe_guc_ads.c | 17 ++++++++++-------
> 2 files changed, 10 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> index 4f132bf8539d..4286bd05c686 100644
> --- a/drivers/gpu/drm/xe/xe_guc.c
> +++ b/drivers/gpu/drm/xe/xe_guc.c
> @@ -732,12 +732,6 @@ static int xe_guc_realloc_post_hwconfig(struct xe_guc *guc)
> if (ret)
> return ret;
>
> - if (guc->ads.um_queue_bo) {
> - ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->ads.um_queue_bo);
> - if (ret)
> - return ret;
> - }
> -
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
> index ef8e9cc35c8c..a69ec584cc0f 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ads.c
> +++ b/drivers/gpu/drm/xe/xe_guc_ads.c
> @@ -446,19 +446,22 @@ int xe_guc_ads_init(struct xe_guc_ads *ads)
> /*
> * Allocate a separate BO for the HW fault ring (UM queues).
> *
> - * Round the size up to the next power of two so that
> + * Round the size up to the next power of two so that on iGPU
> * (system memory, no IOMMU) the TTM pool issues a single
> * alloc_pages(order=N) call, maximising the chance of getting
> * a physically contiguous block. GuC requires contiguous DPA.
> */
> - size_t um_size = roundup_pow_of_two(GUC_UM_QUEUE_SIZE *
> + size_t um_size = IS_DGFX(xe) ?
> + GUC_UM_QUEUE_SIZE * GUC_UM_HW_QUEUE_MAX :
> + roundup_pow_of_two(GUC_UM_QUEUE_SIZE *
> GUC_UM_HW_QUEUE_MAX);
>
> - bo = xe_managed_bo_create_pin_map(xe, tile, um_size,
> - XE_BO_FLAG_SYSTEM |
> - XE_BO_FLAG_GGTT |
> - XE_BO_FLAG_GGTT_INVALIDATE |
> - XE_BO_FLAG_PINNED_NORESTORE);
> + u32 um_flags = XE_BO_FLAG_VRAM_IF_DGFX(tile) |
> + XE_BO_FLAG_GGTT |
> + XE_BO_FLAG_GGTT_INVALIDATE |
> + XE_BO_FLAG_PINNED_NORESTORE;
> +
> + bo = xe_managed_bo_create_pin_map(xe, tile, um_size, um_flags);
> if (IS_ERR(bo))
> return PTR_ERR(bo);
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v7 1/3] drm/xe/guc_ads: allocate UM queues in a separate BO
2026-08-03 20:08 ` [PATCH v7 1/3] drm/xe/guc_ads: allocate UM queues in a separate BO Jia Yao
2026-08-04 7:43 ` Matthew Auld
@ 2026-08-04 8:00 ` Matthew Auld
2026-08-04 8:54 ` Matthew Brost
1 sibling, 1 reply; 14+ messages in thread
From: Matthew Auld @ 2026-08-04 8:00 UTC (permalink / raw)
To: Jia Yao, intel-xe; +Cc: Gwan-gyeong Mun, stable
On 03/08/2026 21:08, Jia Yao wrote:
> Move the UM queues into a dedicated UC BO (ads->um_queue_bo) and avoid
> CPU memset operations on it, which eliminates the CPU as a potential
> cacheline-polluting agent and helps maintain consistency between GAM
> writes and GuC reads.
>
> Fixes: 9c57bc08652a ("drm/xe/lnl: Drop force_probe requirement")
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Cc: <stable@vger.kernel.org> # v6.12+
> Signed-off-by: Jia Yao <jia.yao@intel.com>
> ---
> drivers/gpu/drm/xe/xe_guc.c | 6 ++
> drivers/gpu/drm/xe/xe_guc_ads.c | 89 +++++++++++++++++----------
> drivers/gpu/drm/xe/xe_guc_ads_types.h | 5 ++
> 3 files changed, 68 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> index 4286bd05c686..4f132bf8539d 100644
> --- a/drivers/gpu/drm/xe/xe_guc.c
> +++ b/drivers/gpu/drm/xe/xe_guc.c
> @@ -732,6 +732,12 @@ static int xe_guc_realloc_post_hwconfig(struct xe_guc *guc)
> if (ret)
> return ret;
>
> + if (guc->ads.um_queue_bo) {
> + ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->ads.um_queue_bo);
> + if (ret)
> + return ret;
> + }
> +
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
> index f0ac00586d3a..ef8e9cc35c8c 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ads.c
> +++ b/drivers/gpu/drm/xe/xe_guc_ads.c
> @@ -8,6 +8,7 @@
> #include <linux/fault-inject.h>
>
> #include <drm/drm_managed.h>
> +#include <drm/drm_prime.h>
>
> #include <generated/xe_wa_oob.h>
>
> @@ -64,10 +65,14 @@ ads_to_map(struct xe_guc_ads *ads)
>
> /*
> * The Additional Data Struct (ADS) has pointers for different buffers used by
> - * the GuC. One single gem object contains the ADS struct itself (guc_ads) and
> - * all the extra buffers indirectly linked via the ADS struct's entries.
> + * the GuC. One gem object (ads->bo) contains the ADS struct itself (guc_ads)
> + * and most of the extra buffers linked via the ADS struct's entries. The UM
> + * fault queues (PAGE_FAULT, PAGE_FAULT_RESPONSE, ACCESS_COUNTER rings) are
> + * kept in a separate BO (ads->um_queue_bo) so that the full memset of ads->bo
> + * performed on every GT reset does not discard fault descriptors already
> + * written into the rings by the GPU.
> *
> - * Layout of the ADS blob allocated for the GuC:
> + * Layout of the ADS blob (ads->bo):
> *
> * +---------------------------------------+ <== base
> * | guc_ads |
> @@ -99,10 +104,6 @@ ads_to_map(struct xe_guc_ads *ads)
> * +---------------------------------------+
> * | padding |
> * +---------------------------------------+ <== 4K aligned
> - * | UM queues |
> - * +---------------------------------------+
> - * | padding |
> - * +---------------------------------------+ <== 4K aligned
> * | private data |
> * +---------------------------------------+
> * | padding |
> @@ -156,16 +157,6 @@ static size_t guc_ads_capture_size(struct xe_guc_ads *ads)
> return PAGE_ALIGN(ads->capture_size);
> }
>
> -static size_t guc_ads_um_queues_size(struct xe_guc_ads *ads)
> -{
> - struct xe_device *xe = ads_to_xe(ads);
> -
> - if (!xe->info.has_usm)
> - return 0;
> -
> - return GUC_UM_QUEUE_SIZE * GUC_UM_HW_QUEUE_MAX;
> -}
> -
> static size_t guc_ads_private_data_size(struct xe_guc_ads *ads)
> {
> return PAGE_ALIGN(ads_to_guc(ads)->fw.private_data_size);
> @@ -206,22 +197,12 @@ static size_t guc_ads_capture_offset(struct xe_guc_ads *ads)
> return PAGE_ALIGN(offset);
> }
>
> -static size_t guc_ads_um_queues_offset(struct xe_guc_ads *ads)
> -{
> - u32 offset;
> -
> - offset = guc_ads_capture_offset(ads) +
> - guc_ads_capture_size(ads);
> -
> - return PAGE_ALIGN(offset);
> -}
> -
> static size_t guc_ads_private_data_offset(struct xe_guc_ads *ads)
> {
> size_t offset;
>
> - offset = guc_ads_um_queues_offset(ads) +
> - guc_ads_um_queues_size(ads);
> + offset = guc_ads_capture_offset(ads) +
> + guc_ads_capture_size(ads);
>
> return PAGE_ALIGN(offset);
> }
> @@ -461,6 +442,44 @@ int xe_guc_ads_init(struct xe_guc_ads *ads)
>
> ads->bo = bo;
>
> + if (xe->info.has_usm) {
> + /*
> + * Allocate a separate BO for the HW fault ring (UM queues).
> + *
> + * Round the size up to the next power of two so that
> + * (system memory, no IOMMU) the TTM pool issues a single
> + * alloc_pages(order=N) call, maximising the chance of getting
> + * a physically contiguous block. GuC requires contiguous DPA.
> + */
> + size_t um_size = roundup_pow_of_two(GUC_UM_QUEUE_SIZE *
> + GUC_UM_HW_QUEUE_MAX);
> +
> + bo = xe_managed_bo_create_pin_map(xe, tile, um_size,
> + XE_BO_FLAG_SYSTEM |
> + XE_BO_FLAG_GGTT |
> + XE_BO_FLAG_GGTT_INVALIDATE |
> + XE_BO_FLAG_PINNED_NORESTORE);
> + if (IS_ERR(bo))
> + return PTR_ERR(bo);
> +
> + /*
> + * On pre-Xe3p platforms, GAM (not GuC) accesses the UM queue
> + * ring via base_dpa, which must be a contiguous DMA address
> + * range. Verify that the allocated pages are contiguous in
> + * DMA address space.
> + */
> + if (xe_bo_sg(bo) &&
There is a comment from Sashiko that there might not be a valid tt for
vram buffers, so perhaps just make this check !xe_bo_is_vram() instead?
> + !xe_guc_using_main_gamctrl_queues(ads_to_guc(ads)) &&
> + unlikely(drm_prime_get_contiguous_size(xe_bo_sg(bo)) <
> + GUC_UM_QUEUE_SIZE * GUC_UM_HW_QUEUE_MAX)) {
> + drm_err(&xe->drm,
> + "UM fault queue memory is not contiguous in DMA address space; GAM requires contiguous DPA\n");
> + return -ENOMEM;
> + }
> +
> + ads->um_queue_bo = bo;
> + }
> +
> return 0;
> }
> ALLOW_ERROR_INJECTION(xe_guc_ads_init, ERRNO); /* See xe_pci_probe() */
> @@ -893,7 +912,7 @@ static void guc_mmio_reg_state_init(struct xe_guc_ads *ads)
>
> static void guc_um_init_params(struct xe_guc_ads *ads)
> {
> - u32 um_queue_offset = guc_ads_um_queues_offset(ads);
> + struct xe_bo *um_bo = ads->um_queue_bo;
> struct xe_guc *guc = ads_to_guc(ads);
> struct xe_device *xe = ads_to_xe(ads);
> u64 base_dpa;
> @@ -903,8 +922,14 @@ static void guc_um_init_params(struct xe_guc_ads *ads)
>
> with_dpa = !xe_guc_using_main_gamctrl_queues(guc);
>
> - base_ggtt = xe_bo_ggtt_addr(ads->bo) + um_queue_offset;
> - base_dpa = xe_bo_main_addr(ads->bo, PAGE_SIZE) + um_queue_offset;
> + if (um_bo) {
> + /* All USM platforms: UM queues in dedicated um_queue_bo */
> + base_ggtt = xe_bo_ggtt_addr(um_bo);
> + base_dpa = xe_bo_main_addr(um_bo, PAGE_SIZE);
> + } else {
> + /* Platform does not support USM: no UM queues, nothing to do */
> + return;
> + }
>
> for (i = 0; i < GUC_UM_HW_QUEUE_MAX; ++i) {
> /*
> diff --git a/drivers/gpu/drm/xe/xe_guc_ads_types.h b/drivers/gpu/drm/xe/xe_guc_ads_types.h
> index 48a8e092023f..845c1fbd93a4 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ads_types.h
> +++ b/drivers/gpu/drm/xe/xe_guc_ads_types.h
> @@ -16,6 +16,11 @@ struct xe_bo;
> struct xe_guc_ads {
> /** @bo: Xe BO for GuC ads blob */
> struct xe_bo *bo;
> + /**
> + * @um_queue_bo: Dedicated BO for the HW fault ring (UM queues).
> + * NULL if the platform does not support USM.
> + */
> + struct xe_bo *um_queue_bo;
> /** @golden_lrc_size: golden LRC size */
> size_t golden_lrc_size;
> /** @regset_size: size of register set passed to GuC for save/restore */
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v7 1/3] drm/xe/guc_ads: allocate UM queues in a separate BO
2026-08-04 8:00 ` Matthew Auld
@ 2026-08-04 8:54 ` Matthew Brost
2026-08-04 9:16 ` Matthew Auld
0 siblings, 1 reply; 14+ messages in thread
From: Matthew Brost @ 2026-08-04 8:54 UTC (permalink / raw)
To: Matthew Auld; +Cc: Jia Yao, intel-xe, Gwan-gyeong Mun, stable
On Tue, Aug 04, 2026 at 09:00:19AM +0100, Matthew Auld wrote:
> On 03/08/2026 21:08, Jia Yao wrote:
> > Move the UM queues into a dedicated UC BO (ads->um_queue_bo) and avoid
> > CPU memset operations on it, which eliminates the CPU as a potential
> > cacheline-polluting agent and helps maintain consistency between GAM
> > writes and GuC reads.
> >
> > Fixes: 9c57bc08652a ("drm/xe/lnl: Drop force_probe requirement")
> > Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > Cc: Matthew Auld <matthew.auld@intel.com>
> > Cc: <stable@vger.kernel.org> # v6.12+
> > Signed-off-by: Jia Yao <jia.yao@intel.com>
> > ---
> > drivers/gpu/drm/xe/xe_guc.c | 6 ++
> > drivers/gpu/drm/xe/xe_guc_ads.c | 89 +++++++++++++++++----------
> > drivers/gpu/drm/xe/xe_guc_ads_types.h | 5 ++
> > 3 files changed, 68 insertions(+), 32 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> > index 4286bd05c686..4f132bf8539d 100644
> > --- a/drivers/gpu/drm/xe/xe_guc.c
> > +++ b/drivers/gpu/drm/xe/xe_guc.c
> > @@ -732,6 +732,12 @@ static int xe_guc_realloc_post_hwconfig(struct xe_guc *guc)
> > if (ret)
> > return ret;
Add a newline here.
> > + if (guc->ads.um_queue_bo) {
> > + ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->ads.um_queue_bo);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > return 0;
> > }
> > diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
> > index f0ac00586d3a..ef8e9cc35c8c 100644
> > --- a/drivers/gpu/drm/xe/xe_guc_ads.c
> > +++ b/drivers/gpu/drm/xe/xe_guc_ads.c
> > @@ -8,6 +8,7 @@
> > #include <linux/fault-inject.h>
> > #include <drm/drm_managed.h>
> > +#include <drm/drm_prime.h>
> > #include <generated/xe_wa_oob.h>
> > @@ -64,10 +65,14 @@ ads_to_map(struct xe_guc_ads *ads)
> > /*
> > * The Additional Data Struct (ADS) has pointers for different buffers used by
> > - * the GuC. One single gem object contains the ADS struct itself (guc_ads) and
> > - * all the extra buffers indirectly linked via the ADS struct's entries.
> > + * the GuC. One gem object (ads->bo) contains the ADS struct itself (guc_ads)
> > + * and most of the extra buffers linked via the ADS struct's entries. The UM
> > + * fault queues (PAGE_FAULT, PAGE_FAULT_RESPONSE, ACCESS_COUNTER rings) are
> > + * kept in a separate BO (ads->um_queue_bo) so that the full memset of ads->bo
> > + * performed on every GT reset does not discard fault descriptors already
> > + * written into the rings by the GPU.
> > *
> > - * Layout of the ADS blob allocated for the GuC:
> > + * Layout of the ADS blob (ads->bo):
> > *
> > * +---------------------------------------+ <== base
> > * | guc_ads |
> > @@ -99,10 +104,6 @@ ads_to_map(struct xe_guc_ads *ads)
> > * +---------------------------------------+
> > * | padding |
> > * +---------------------------------------+ <== 4K aligned
> > - * | UM queues |
> > - * +---------------------------------------+
> > - * | padding |
> > - * +---------------------------------------+ <== 4K aligned
> > * | private data |
> > * +---------------------------------------+
> > * | padding |
> > @@ -156,16 +157,6 @@ static size_t guc_ads_capture_size(struct xe_guc_ads *ads)
> > return PAGE_ALIGN(ads->capture_size);
> > }
> > -static size_t guc_ads_um_queues_size(struct xe_guc_ads *ads)
> > -{
> > - struct xe_device *xe = ads_to_xe(ads);
> > -
> > - if (!xe->info.has_usm)
> > - return 0;
> > -
> > - return GUC_UM_QUEUE_SIZE * GUC_UM_HW_QUEUE_MAX;
> > -}
> > -
> > static size_t guc_ads_private_data_size(struct xe_guc_ads *ads)
> > {
> > return PAGE_ALIGN(ads_to_guc(ads)->fw.private_data_size);
> > @@ -206,22 +197,12 @@ static size_t guc_ads_capture_offset(struct xe_guc_ads *ads)
> > return PAGE_ALIGN(offset);
> > }
> > -static size_t guc_ads_um_queues_offset(struct xe_guc_ads *ads)
> > -{
> > - u32 offset;
> > -
> > - offset = guc_ads_capture_offset(ads) +
> > - guc_ads_capture_size(ads);
> > -
> > - return PAGE_ALIGN(offset);
> > -}
> > -
> > static size_t guc_ads_private_data_offset(struct xe_guc_ads *ads)
> > {
> > size_t offset;
> > - offset = guc_ads_um_queues_offset(ads) +
> > - guc_ads_um_queues_size(ads);
> > + offset = guc_ads_capture_offset(ads) +
> > + guc_ads_capture_size(ads);
> > return PAGE_ALIGN(offset);
> > }
> > @@ -461,6 +442,44 @@ int xe_guc_ads_init(struct xe_guc_ads *ads)
> > ads->bo = bo;
> > + if (xe->info.has_usm) {
> > + /*
> > + * Allocate a separate BO for the HW fault ring (UM queues).
> > + *
> > + * Round the size up to the next power of two so that
> > + * (system memory, no IOMMU) the TTM pool issues a single
> > + * alloc_pages(order=N) call, maximising the chance of getting
> > + * a physically contiguous block. GuC requires contiguous DPA.
> > + */
> > + size_t um_size = roundup_pow_of_two(GUC_UM_QUEUE_SIZE *
> > + GUC_UM_HW_QUEUE_MAX);
> > +
> > + bo = xe_managed_bo_create_pin_map(xe, tile, um_size,
> > + XE_BO_FLAG_SYSTEM |
> > + XE_BO_FLAG_GGTT |
> > + XE_BO_FLAG_GGTT_INVALIDATE |
> > + XE_BO_FLAG_PINNED_NORESTORE);
> > + if (IS_ERR(bo))
> > + return PTR_ERR(bo);
> > +
> > + /*
> > + * On pre-Xe3p platforms, GAM (not GuC) accesses the UM queue
> > + * ring via base_dpa, which must be a contiguous DMA address
> > + * range. Verify that the allocated pages are contiguous in
> > + * DMA address space.
> > + */
> > + if (xe_bo_sg(bo) &&
>
>
> There is a comment from Sashiko that there might not be a valid tt for vram
> buffers, so perhaps just make this check !xe_bo_is_vram() instead?
>
> > + !xe_guc_using_main_gamctrl_queues(ads_to_guc(ads)) &&
> > + unlikely(drm_prime_get_contiguous_size(xe_bo_sg(bo)) <
Using drm_prime_* really is the wrong layering. Either this helper
should be some drm or sg generic or IMO we implement this helper
ourselves until we have a proper one in drm or sg generic.
e.g., for SG specific BOs, something like this should work.
xe_bo_sg_is_contigous(struct xe_bo *bo)
{
struct xe_res_cursor cur;
xe_assert(xe_bo_device(bo), xe_bo_sg(bo));
xe_res_first_sg(xe_bo_sg(bo), 0, xe_bo_size(bo), &cur);
return cur.size == xe_bo_size(bo);
}
Matt
> > + GUC_UM_QUEUE_SIZE * GUC_UM_HW_QUEUE_MAX)) {
> > + drm_err(&xe->drm,
> > + "UM fault queue memory is not contiguous in DMA address space; GAM requires contiguous DPA\n");
> > + return -ENOMEM;
> > + }
> > +
> > + ads->um_queue_bo = bo;
> > + }
> > +
> > return 0;
> > }
> > ALLOW_ERROR_INJECTION(xe_guc_ads_init, ERRNO); /* See xe_pci_probe() */
> > @@ -893,7 +912,7 @@ static void guc_mmio_reg_state_init(struct xe_guc_ads *ads)
> > static void guc_um_init_params(struct xe_guc_ads *ads)
> > {
> > - u32 um_queue_offset = guc_ads_um_queues_offset(ads);
> > + struct xe_bo *um_bo = ads->um_queue_bo;
> > struct xe_guc *guc = ads_to_guc(ads);
> > struct xe_device *xe = ads_to_xe(ads);
> > u64 base_dpa;
> > @@ -903,8 +922,14 @@ static void guc_um_init_params(struct xe_guc_ads *ads)
> > with_dpa = !xe_guc_using_main_gamctrl_queues(guc);
> > - base_ggtt = xe_bo_ggtt_addr(ads->bo) + um_queue_offset;
> > - base_dpa = xe_bo_main_addr(ads->bo, PAGE_SIZE) + um_queue_offset;
> > + if (um_bo) {
> > + /* All USM platforms: UM queues in dedicated um_queue_bo */
> > + base_ggtt = xe_bo_ggtt_addr(um_bo);
> > + base_dpa = xe_bo_main_addr(um_bo, PAGE_SIZE);
> > + } else {
> > + /* Platform does not support USM: no UM queues, nothing to do */
> > + return;
> > + }
> > for (i = 0; i < GUC_UM_HW_QUEUE_MAX; ++i) {
> > /*
> > diff --git a/drivers/gpu/drm/xe/xe_guc_ads_types.h b/drivers/gpu/drm/xe/xe_guc_ads_types.h
> > index 48a8e092023f..845c1fbd93a4 100644
> > --- a/drivers/gpu/drm/xe/xe_guc_ads_types.h
> > +++ b/drivers/gpu/drm/xe/xe_guc_ads_types.h
> > @@ -16,6 +16,11 @@ struct xe_bo;
> > struct xe_guc_ads {
> > /** @bo: Xe BO for GuC ads blob */
> > struct xe_bo *bo;
> > + /**
> > + * @um_queue_bo: Dedicated BO for the HW fault ring (UM queues).
> > + * NULL if the platform does not support USM.
> > + */
> > + struct xe_bo *um_queue_bo;
> > /** @golden_lrc_size: golden LRC size */
> > size_t golden_lrc_size;
> > /** @regset_size: size of register set passed to GuC for save/restore */
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v7 1/3] drm/xe/guc_ads: allocate UM queues in a separate BO
2026-08-04 8:54 ` Matthew Brost
@ 2026-08-04 9:16 ` Matthew Auld
2026-08-04 9:25 ` Matthew Brost
0 siblings, 1 reply; 14+ messages in thread
From: Matthew Auld @ 2026-08-04 9:16 UTC (permalink / raw)
To: Matthew Brost; +Cc: Jia Yao, intel-xe, Gwan-gyeong Mun, stable
On 04/08/2026 09:54, Matthew Brost wrote:
> On Tue, Aug 04, 2026 at 09:00:19AM +0100, Matthew Auld wrote:
>> On 03/08/2026 21:08, Jia Yao wrote:
>>> Move the UM queues into a dedicated UC BO (ads->um_queue_bo) and avoid
>>> CPU memset operations on it, which eliminates the CPU as a potential
>>> cacheline-polluting agent and helps maintain consistency between GAM
>>> writes and GuC reads.
>>>
>>> Fixes: 9c57bc08652a ("drm/xe/lnl: Drop force_probe requirement")
>>> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>>> Cc: Matthew Auld <matthew.auld@intel.com>
>>> Cc: <stable@vger.kernel.org> # v6.12+
>>> Signed-off-by: Jia Yao <jia.yao@intel.com>
>>> ---
>>> drivers/gpu/drm/xe/xe_guc.c | 6 ++
>>> drivers/gpu/drm/xe/xe_guc_ads.c | 89 +++++++++++++++++----------
>>> drivers/gpu/drm/xe/xe_guc_ads_types.h | 5 ++
>>> 3 files changed, 68 insertions(+), 32 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
>>> index 4286bd05c686..4f132bf8539d 100644
>>> --- a/drivers/gpu/drm/xe/xe_guc.c
>>> +++ b/drivers/gpu/drm/xe/xe_guc.c
>>> @@ -732,6 +732,12 @@ static int xe_guc_realloc_post_hwconfig(struct xe_guc *guc)
>>> if (ret)
>>> return ret;
>
> Add a newline here.
>
>>> + if (guc->ads.um_queue_bo) {
>>> + ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->ads.um_queue_bo);
>>> + if (ret)
>>> + return ret;
>>> + }
>>> +
>>> return 0;
>>> }
>>> diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
>>> index f0ac00586d3a..ef8e9cc35c8c 100644
>>> --- a/drivers/gpu/drm/xe/xe_guc_ads.c
>>> +++ b/drivers/gpu/drm/xe/xe_guc_ads.c
>>> @@ -8,6 +8,7 @@
>>> #include <linux/fault-inject.h>
>>> #include <drm/drm_managed.h>
>>> +#include <drm/drm_prime.h>
>>> #include <generated/xe_wa_oob.h>
>>> @@ -64,10 +65,14 @@ ads_to_map(struct xe_guc_ads *ads)
>>> /*
>>> * The Additional Data Struct (ADS) has pointers for different buffers used by
>>> - * the GuC. One single gem object contains the ADS struct itself (guc_ads) and
>>> - * all the extra buffers indirectly linked via the ADS struct's entries.
>>> + * the GuC. One gem object (ads->bo) contains the ADS struct itself (guc_ads)
>>> + * and most of the extra buffers linked via the ADS struct's entries. The UM
>>> + * fault queues (PAGE_FAULT, PAGE_FAULT_RESPONSE, ACCESS_COUNTER rings) are
>>> + * kept in a separate BO (ads->um_queue_bo) so that the full memset of ads->bo
>>> + * performed on every GT reset does not discard fault descriptors already
>>> + * written into the rings by the GPU.
>>> *
>>> - * Layout of the ADS blob allocated for the GuC:
>>> + * Layout of the ADS blob (ads->bo):
>>> *
>>> * +---------------------------------------+ <== base
>>> * | guc_ads |
>>> @@ -99,10 +104,6 @@ ads_to_map(struct xe_guc_ads *ads)
>>> * +---------------------------------------+
>>> * | padding |
>>> * +---------------------------------------+ <== 4K aligned
>>> - * | UM queues |
>>> - * +---------------------------------------+
>>> - * | padding |
>>> - * +---------------------------------------+ <== 4K aligned
>>> * | private data |
>>> * +---------------------------------------+
>>> * | padding |
>>> @@ -156,16 +157,6 @@ static size_t guc_ads_capture_size(struct xe_guc_ads *ads)
>>> return PAGE_ALIGN(ads->capture_size);
>>> }
>>> -static size_t guc_ads_um_queues_size(struct xe_guc_ads *ads)
>>> -{
>>> - struct xe_device *xe = ads_to_xe(ads);
>>> -
>>> - if (!xe->info.has_usm)
>>> - return 0;
>>> -
>>> - return GUC_UM_QUEUE_SIZE * GUC_UM_HW_QUEUE_MAX;
>>> -}
>>> -
>>> static size_t guc_ads_private_data_size(struct xe_guc_ads *ads)
>>> {
>>> return PAGE_ALIGN(ads_to_guc(ads)->fw.private_data_size);
>>> @@ -206,22 +197,12 @@ static size_t guc_ads_capture_offset(struct xe_guc_ads *ads)
>>> return PAGE_ALIGN(offset);
>>> }
>>> -static size_t guc_ads_um_queues_offset(struct xe_guc_ads *ads)
>>> -{
>>> - u32 offset;
>>> -
>>> - offset = guc_ads_capture_offset(ads) +
>>> - guc_ads_capture_size(ads);
>>> -
>>> - return PAGE_ALIGN(offset);
>>> -}
>>> -
>>> static size_t guc_ads_private_data_offset(struct xe_guc_ads *ads)
>>> {
>>> size_t offset;
>>> - offset = guc_ads_um_queues_offset(ads) +
>>> - guc_ads_um_queues_size(ads);
>>> + offset = guc_ads_capture_offset(ads) +
>>> + guc_ads_capture_size(ads);
>>> return PAGE_ALIGN(offset);
>>> }
>>> @@ -461,6 +442,44 @@ int xe_guc_ads_init(struct xe_guc_ads *ads)
>>> ads->bo = bo;
>>> + if (xe->info.has_usm) {
>>> + /*
>>> + * Allocate a separate BO for the HW fault ring (UM queues).
>>> + *
>>> + * Round the size up to the next power of two so that
>>> + * (system memory, no IOMMU) the TTM pool issues a single
>>> + * alloc_pages(order=N) call, maximising the chance of getting
>>> + * a physically contiguous block. GuC requires contiguous DPA.
>>> + */
>>> + size_t um_size = roundup_pow_of_two(GUC_UM_QUEUE_SIZE *
>>> + GUC_UM_HW_QUEUE_MAX);
>>> +
>>> + bo = xe_managed_bo_create_pin_map(xe, tile, um_size,
>>> + XE_BO_FLAG_SYSTEM |
>>> + XE_BO_FLAG_GGTT |
>>> + XE_BO_FLAG_GGTT_INVALIDATE |
>>> + XE_BO_FLAG_PINNED_NORESTORE);
>>> + if (IS_ERR(bo))
>>> + return PTR_ERR(bo);
>>> +
>>> + /*
>>> + * On pre-Xe3p platforms, GAM (not GuC) accesses the UM queue
>>> + * ring via base_dpa, which must be a contiguous DMA address
>>> + * range. Verify that the allocated pages are contiguous in
>>> + * DMA address space.
>>> + */
>>> + if (xe_bo_sg(bo) &&
>>
>>
>> There is a comment from Sashiko that there might not be a valid tt for vram
>> buffers, so perhaps just make this check !xe_bo_is_vram() instead?
>>
>>> + !xe_guc_using_main_gamctrl_queues(ads_to_guc(ads)) &&
>>> + unlikely(drm_prime_get_contiguous_size(xe_bo_sg(bo)) <
>
> Using drm_prime_* really is the wrong layering. Either this helper
> should be some drm or sg generic or IMO we implement this helper
> ourselves until we have a proper one in drm or sg generic.
>
> e.g., for SG specific BOs, something like this should work.
>
> xe_bo_sg_is_contigous(struct xe_bo *bo)
> {
> struct xe_res_cursor cur;
>
> xe_assert(xe_bo_device(bo), xe_bo_sg(bo));
> xe_res_first_sg(xe_bo_sg(bo), 0, xe_bo_size(bo), &cur);
>
> return cur.size == xe_bo_size(bo);
> }
AFAICT I don't think it's the same since you could potentially get
multiple sg entries underneath, where they still occupy something contig
as a whole, and xe_res_first_sg() doesn't try to coalesce. Maybe it
should? The !xe_bo_sg_is_contigous() will be fatal, so I think we should
try as hard as possible for the check.
Agreed drm_prime_get_contiguous_size() is a bit odd, but essentially we
were previously implementing the same thing.
>
> Matt
>
>>> + GUC_UM_QUEUE_SIZE * GUC_UM_HW_QUEUE_MAX)) {
>>> + drm_err(&xe->drm,
>>> + "UM fault queue memory is not contiguous in DMA address space; GAM requires contiguous DPA\n");
>>> + return -ENOMEM;
>>> + }
>>> +
>>> + ads->um_queue_bo = bo;
>>> + }
>>> +
>>> return 0;
>>> }
>>> ALLOW_ERROR_INJECTION(xe_guc_ads_init, ERRNO); /* See xe_pci_probe() */
>>> @@ -893,7 +912,7 @@ static void guc_mmio_reg_state_init(struct xe_guc_ads *ads)
>>> static void guc_um_init_params(struct xe_guc_ads *ads)
>>> {
>>> - u32 um_queue_offset = guc_ads_um_queues_offset(ads);
>>> + struct xe_bo *um_bo = ads->um_queue_bo;
>>> struct xe_guc *guc = ads_to_guc(ads);
>>> struct xe_device *xe = ads_to_xe(ads);
>>> u64 base_dpa;
>>> @@ -903,8 +922,14 @@ static void guc_um_init_params(struct xe_guc_ads *ads)
>>> with_dpa = !xe_guc_using_main_gamctrl_queues(guc);
>>> - base_ggtt = xe_bo_ggtt_addr(ads->bo) + um_queue_offset;
>>> - base_dpa = xe_bo_main_addr(ads->bo, PAGE_SIZE) + um_queue_offset;
>>> + if (um_bo) {
>>> + /* All USM platforms: UM queues in dedicated um_queue_bo */
>>> + base_ggtt = xe_bo_ggtt_addr(um_bo);
>>> + base_dpa = xe_bo_main_addr(um_bo, PAGE_SIZE);
>>> + } else {
>>> + /* Platform does not support USM: no UM queues, nothing to do */
>>> + return;
>>> + }
>>> for (i = 0; i < GUC_UM_HW_QUEUE_MAX; ++i) {
>>> /*
>>> diff --git a/drivers/gpu/drm/xe/xe_guc_ads_types.h b/drivers/gpu/drm/xe/xe_guc_ads_types.h
>>> index 48a8e092023f..845c1fbd93a4 100644
>>> --- a/drivers/gpu/drm/xe/xe_guc_ads_types.h
>>> +++ b/drivers/gpu/drm/xe/xe_guc_ads_types.h
>>> @@ -16,6 +16,11 @@ struct xe_bo;
>>> struct xe_guc_ads {
>>> /** @bo: Xe BO for GuC ads blob */
>>> struct xe_bo *bo;
>>> + /**
>>> + * @um_queue_bo: Dedicated BO for the HW fault ring (UM queues).
>>> + * NULL if the platform does not support USM.
>>> + */
>>> + struct xe_bo *um_queue_bo;
>>> /** @golden_lrc_size: golden LRC size */
>>> size_t golden_lrc_size;
>>> /** @regset_size: size of register set passed to GuC for save/restore */
>>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v7 1/3] drm/xe/guc_ads: allocate UM queues in a separate BO
2026-08-04 9:16 ` Matthew Auld
@ 2026-08-04 9:25 ` Matthew Brost
2026-08-04 9:36 ` Matthew Auld
0 siblings, 1 reply; 14+ messages in thread
From: Matthew Brost @ 2026-08-04 9:25 UTC (permalink / raw)
To: Matthew Auld; +Cc: Jia Yao, intel-xe, Gwan-gyeong Mun, stable
On Tue, Aug 04, 2026 at 10:16:07AM +0100, Matthew Auld wrote:
> On 04/08/2026 09:54, Matthew Brost wrote:
> > On Tue, Aug 04, 2026 at 09:00:19AM +0100, Matthew Auld wrote:
> > > On 03/08/2026 21:08, Jia Yao wrote:
> > > > Move the UM queues into a dedicated UC BO (ads->um_queue_bo) and avoid
> > > > CPU memset operations on it, which eliminates the CPU as a potential
> > > > cacheline-polluting agent and helps maintain consistency between GAM
> > > > writes and GuC reads.
> > > >
> > > > Fixes: 9c57bc08652a ("drm/xe/lnl: Drop force_probe requirement")
> > > > Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > > > Cc: Matthew Auld <matthew.auld@intel.com>
> > > > Cc: <stable@vger.kernel.org> # v6.12+
> > > > Signed-off-by: Jia Yao <jia.yao@intel.com>
> > > > ---
> > > > drivers/gpu/drm/xe/xe_guc.c | 6 ++
> > > > drivers/gpu/drm/xe/xe_guc_ads.c | 89 +++++++++++++++++----------
> > > > drivers/gpu/drm/xe/xe_guc_ads_types.h | 5 ++
> > > > 3 files changed, 68 insertions(+), 32 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> > > > index 4286bd05c686..4f132bf8539d 100644
> > > > --- a/drivers/gpu/drm/xe/xe_guc.c
> > > > +++ b/drivers/gpu/drm/xe/xe_guc.c
> > > > @@ -732,6 +732,12 @@ static int xe_guc_realloc_post_hwconfig(struct xe_guc *guc)
> > > > if (ret)
> > > > return ret;
> >
> > Add a newline here.
> >
> > > > + if (guc->ads.um_queue_bo) {
> > > > + ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->ads.um_queue_bo);
> > > > + if (ret)
> > > > + return ret;
> > > > + }
> > > > +
> > > > return 0;
> > > > }
> > > > diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
> > > > index f0ac00586d3a..ef8e9cc35c8c 100644
> > > > --- a/drivers/gpu/drm/xe/xe_guc_ads.c
> > > > +++ b/drivers/gpu/drm/xe/xe_guc_ads.c
> > > > @@ -8,6 +8,7 @@
> > > > #include <linux/fault-inject.h>
> > > > #include <drm/drm_managed.h>
> > > > +#include <drm/drm_prime.h>
> > > > #include <generated/xe_wa_oob.h>
> > > > @@ -64,10 +65,14 @@ ads_to_map(struct xe_guc_ads *ads)
> > > > /*
> > > > * The Additional Data Struct (ADS) has pointers for different buffers used by
> > > > - * the GuC. One single gem object contains the ADS struct itself (guc_ads) and
> > > > - * all the extra buffers indirectly linked via the ADS struct's entries.
> > > > + * the GuC. One gem object (ads->bo) contains the ADS struct itself (guc_ads)
> > > > + * and most of the extra buffers linked via the ADS struct's entries. The UM
> > > > + * fault queues (PAGE_FAULT, PAGE_FAULT_RESPONSE, ACCESS_COUNTER rings) are
> > > > + * kept in a separate BO (ads->um_queue_bo) so that the full memset of ads->bo
> > > > + * performed on every GT reset does not discard fault descriptors already
> > > > + * written into the rings by the GPU.
> > > > *
> > > > - * Layout of the ADS blob allocated for the GuC:
> > > > + * Layout of the ADS blob (ads->bo):
> > > > *
> > > > * +---------------------------------------+ <== base
> > > > * | guc_ads |
> > > > @@ -99,10 +104,6 @@ ads_to_map(struct xe_guc_ads *ads)
> > > > * +---------------------------------------+
> > > > * | padding |
> > > > * +---------------------------------------+ <== 4K aligned
> > > > - * | UM queues |
> > > > - * +---------------------------------------+
> > > > - * | padding |
> > > > - * +---------------------------------------+ <== 4K aligned
> > > > * | private data |
> > > > * +---------------------------------------+
> > > > * | padding |
> > > > @@ -156,16 +157,6 @@ static size_t guc_ads_capture_size(struct xe_guc_ads *ads)
> > > > return PAGE_ALIGN(ads->capture_size);
> > > > }
> > > > -static size_t guc_ads_um_queues_size(struct xe_guc_ads *ads)
> > > > -{
> > > > - struct xe_device *xe = ads_to_xe(ads);
> > > > -
> > > > - if (!xe->info.has_usm)
> > > > - return 0;
> > > > -
> > > > - return GUC_UM_QUEUE_SIZE * GUC_UM_HW_QUEUE_MAX;
> > > > -}
> > > > -
> > > > static size_t guc_ads_private_data_size(struct xe_guc_ads *ads)
> > > > {
> > > > return PAGE_ALIGN(ads_to_guc(ads)->fw.private_data_size);
> > > > @@ -206,22 +197,12 @@ static size_t guc_ads_capture_offset(struct xe_guc_ads *ads)
> > > > return PAGE_ALIGN(offset);
> > > > }
> > > > -static size_t guc_ads_um_queues_offset(struct xe_guc_ads *ads)
> > > > -{
> > > > - u32 offset;
> > > > -
> > > > - offset = guc_ads_capture_offset(ads) +
> > > > - guc_ads_capture_size(ads);
> > > > -
> > > > - return PAGE_ALIGN(offset);
> > > > -}
> > > > -
> > > > static size_t guc_ads_private_data_offset(struct xe_guc_ads *ads)
> > > > {
> > > > size_t offset;
> > > > - offset = guc_ads_um_queues_offset(ads) +
> > > > - guc_ads_um_queues_size(ads);
> > > > + offset = guc_ads_capture_offset(ads) +
> > > > + guc_ads_capture_size(ads);
> > > > return PAGE_ALIGN(offset);
> > > > }
> > > > @@ -461,6 +442,44 @@ int xe_guc_ads_init(struct xe_guc_ads *ads)
> > > > ads->bo = bo;
> > > > + if (xe->info.has_usm) {
> > > > + /*
> > > > + * Allocate a separate BO for the HW fault ring (UM queues).
> > > > + *
> > > > + * Round the size up to the next power of two so that
> > > > + * (system memory, no IOMMU) the TTM pool issues a single
> > > > + * alloc_pages(order=N) call, maximising the chance of getting
> > > > + * a physically contiguous block. GuC requires contiguous DPA.
> > > > + */
> > > > + size_t um_size = roundup_pow_of_two(GUC_UM_QUEUE_SIZE *
> > > > + GUC_UM_HW_QUEUE_MAX);
> > > > +
> > > > + bo = xe_managed_bo_create_pin_map(xe, tile, um_size,
> > > > + XE_BO_FLAG_SYSTEM |
> > > > + XE_BO_FLAG_GGTT |
> > > > + XE_BO_FLAG_GGTT_INVALIDATE |
> > > > + XE_BO_FLAG_PINNED_NORESTORE);
> > > > + if (IS_ERR(bo))
> > > > + return PTR_ERR(bo);
> > > > +
> > > > + /*
> > > > + * On pre-Xe3p platforms, GAM (not GuC) accesses the UM queue
> > > > + * ring via base_dpa, which must be a contiguous DMA address
> > > > + * range. Verify that the allocated pages are contiguous in
> > > > + * DMA address space.
> > > > + */
> > > > + if (xe_bo_sg(bo) &&
> > >
> > >
> > > There is a comment from Sashiko that there might not be a valid tt for vram
> > > buffers, so perhaps just make this check !xe_bo_is_vram() instead?
> > >
> > > > + !xe_guc_using_main_gamctrl_queues(ads_to_guc(ads)) &&
> > > > + unlikely(drm_prime_get_contiguous_size(xe_bo_sg(bo)) <
> >
> > Using drm_prime_* really is the wrong layering. Either this helper
> > should be some drm or sg generic or IMO we implement this helper
> > ourselves until we have a proper one in drm or sg generic.
> >
> > e.g., for SG specific BOs, something like this should work.
> >
> > xe_bo_sg_is_contigous(struct xe_bo *bo)
> > {
> > struct xe_res_cursor cur;
> >
> > xe_assert(xe_bo_device(bo), xe_bo_sg(bo));
> > xe_res_first_sg(xe_bo_sg(bo), 0, xe_bo_size(bo), &cur);
> >
> > return cur.size == xe_bo_size(bo);
> > }
>
> AFAICT I don't think it's the same since you could potentially get multiple
> sg entries underneath, where they still occupy something contig as a whole,
Yes, that is possible but SG segment in Xe is 1 or 2G iirc.
> and xe_res_first_sg() doesn't try to coalesce. Maybe it should? The
As long as segment is at least 1G then it doesn't really matter for
existing use cases.
> !xe_bo_sg_is_contigous() will be fatal, so I think we should try as hard as
> possible for the check.
>
> Agreed drm_prime_get_contiguous_size() is a bit odd, but essentially we were
> previously implementing the same thing.
Maybe move this into xe_bo helper to make this slighly more palatable
(i.e., at least only BO layer is looking at prime).
e.g.,
xe_bo_sg_is_contigous(bo, len)
return drm_prime_get_contiguous_size(xe_bo_sg(bo)) >= len;
or
xe_bo_sg_is_contigous(bo)
return drm_prime_get_contiguous_size(xe_bo_sg(bo)) == xe_bo_size(bo);
Matt
>
> >
> > Matt
> >
> > > > + GUC_UM_QUEUE_SIZE * GUC_UM_HW_QUEUE_MAX)) {
> > > > + drm_err(&xe->drm,
> > > > + "UM fault queue memory is not contiguous in DMA address space; GAM requires contiguous DPA\n");
> > > > + return -ENOMEM;
> > > > + }
> > > > +
> > > > + ads->um_queue_bo = bo;
> > > > + }
> > > > +
> > > > return 0;
> > > > }
> > > > ALLOW_ERROR_INJECTION(xe_guc_ads_init, ERRNO); /* See xe_pci_probe() */
> > > > @@ -893,7 +912,7 @@ static void guc_mmio_reg_state_init(struct xe_guc_ads *ads)
> > > > static void guc_um_init_params(struct xe_guc_ads *ads)
> > > > {
> > > > - u32 um_queue_offset = guc_ads_um_queues_offset(ads);
> > > > + struct xe_bo *um_bo = ads->um_queue_bo;
> > > > struct xe_guc *guc = ads_to_guc(ads);
> > > > struct xe_device *xe = ads_to_xe(ads);
> > > > u64 base_dpa;
> > > > @@ -903,8 +922,14 @@ static void guc_um_init_params(struct xe_guc_ads *ads)
> > > > with_dpa = !xe_guc_using_main_gamctrl_queues(guc);
> > > > - base_ggtt = xe_bo_ggtt_addr(ads->bo) + um_queue_offset;
> > > > - base_dpa = xe_bo_main_addr(ads->bo, PAGE_SIZE) + um_queue_offset;
> > > > + if (um_bo) {
> > > > + /* All USM platforms: UM queues in dedicated um_queue_bo */
> > > > + base_ggtt = xe_bo_ggtt_addr(um_bo);
> > > > + base_dpa = xe_bo_main_addr(um_bo, PAGE_SIZE);
> > > > + } else {
> > > > + /* Platform does not support USM: no UM queues, nothing to do */
> > > > + return;
> > > > + }
> > > > for (i = 0; i < GUC_UM_HW_QUEUE_MAX; ++i) {
> > > > /*
> > > > diff --git a/drivers/gpu/drm/xe/xe_guc_ads_types.h b/drivers/gpu/drm/xe/xe_guc_ads_types.h
> > > > index 48a8e092023f..845c1fbd93a4 100644
> > > > --- a/drivers/gpu/drm/xe/xe_guc_ads_types.h
> > > > +++ b/drivers/gpu/drm/xe/xe_guc_ads_types.h
> > > > @@ -16,6 +16,11 @@ struct xe_bo;
> > > > struct xe_guc_ads {
> > > > /** @bo: Xe BO for GuC ads blob */
> > > > struct xe_bo *bo;
> > > > + /**
> > > > + * @um_queue_bo: Dedicated BO for the HW fault ring (UM queues).
> > > > + * NULL if the platform does not support USM.
> > > > + */
> > > > + struct xe_bo *um_queue_bo;
> > > > /** @golden_lrc_size: golden LRC size */
> > > > size_t golden_lrc_size;
> > > > /** @regset_size: size of register set passed to GuC for save/restore */
> > >
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v7 1/3] drm/xe/guc_ads: allocate UM queues in a separate BO
2026-08-04 9:25 ` Matthew Brost
@ 2026-08-04 9:36 ` Matthew Auld
0 siblings, 0 replies; 14+ messages in thread
From: Matthew Auld @ 2026-08-04 9:36 UTC (permalink / raw)
To: Matthew Brost; +Cc: Jia Yao, intel-xe, Gwan-gyeong Mun, stable
On 04/08/2026 10:25, Matthew Brost wrote:
> On Tue, Aug 04, 2026 at 10:16:07AM +0100, Matthew Auld wrote:
>> On 04/08/2026 09:54, Matthew Brost wrote:
>>> On Tue, Aug 04, 2026 at 09:00:19AM +0100, Matthew Auld wrote:
>>>> On 03/08/2026 21:08, Jia Yao wrote:
>>>>> Move the UM queues into a dedicated UC BO (ads->um_queue_bo) and avoid
>>>>> CPU memset operations on it, which eliminates the CPU as a potential
>>>>> cacheline-polluting agent and helps maintain consistency between GAM
>>>>> writes and GuC reads.
>>>>>
>>>>> Fixes: 9c57bc08652a ("drm/xe/lnl: Drop force_probe requirement")
>>>>> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>>>>> Cc: Matthew Auld <matthew.auld@intel.com>
>>>>> Cc: <stable@vger.kernel.org> # v6.12+
>>>>> Signed-off-by: Jia Yao <jia.yao@intel.com>
>>>>> ---
>>>>> drivers/gpu/drm/xe/xe_guc.c | 6 ++
>>>>> drivers/gpu/drm/xe/xe_guc_ads.c | 89 +++++++++++++++++----------
>>>>> drivers/gpu/drm/xe/xe_guc_ads_types.h | 5 ++
>>>>> 3 files changed, 68 insertions(+), 32 deletions(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
>>>>> index 4286bd05c686..4f132bf8539d 100644
>>>>> --- a/drivers/gpu/drm/xe/xe_guc.c
>>>>> +++ b/drivers/gpu/drm/xe/xe_guc.c
>>>>> @@ -732,6 +732,12 @@ static int xe_guc_realloc_post_hwconfig(struct xe_guc *guc)
>>>>> if (ret)
>>>>> return ret;
>>>
>>> Add a newline here.
>>>
>>>>> + if (guc->ads.um_queue_bo) {
>>>>> + ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->ads.um_queue_bo);
>>>>> + if (ret)
>>>>> + return ret;
>>>>> + }
>>>>> +
>>>>> return 0;
>>>>> }
>>>>> diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
>>>>> index f0ac00586d3a..ef8e9cc35c8c 100644
>>>>> --- a/drivers/gpu/drm/xe/xe_guc_ads.c
>>>>> +++ b/drivers/gpu/drm/xe/xe_guc_ads.c
>>>>> @@ -8,6 +8,7 @@
>>>>> #include <linux/fault-inject.h>
>>>>> #include <drm/drm_managed.h>
>>>>> +#include <drm/drm_prime.h>
>>>>> #include <generated/xe_wa_oob.h>
>>>>> @@ -64,10 +65,14 @@ ads_to_map(struct xe_guc_ads *ads)
>>>>> /*
>>>>> * The Additional Data Struct (ADS) has pointers for different buffers used by
>>>>> - * the GuC. One single gem object contains the ADS struct itself (guc_ads) and
>>>>> - * all the extra buffers indirectly linked via the ADS struct's entries.
>>>>> + * the GuC. One gem object (ads->bo) contains the ADS struct itself (guc_ads)
>>>>> + * and most of the extra buffers linked via the ADS struct's entries. The UM
>>>>> + * fault queues (PAGE_FAULT, PAGE_FAULT_RESPONSE, ACCESS_COUNTER rings) are
>>>>> + * kept in a separate BO (ads->um_queue_bo) so that the full memset of ads->bo
>>>>> + * performed on every GT reset does not discard fault descriptors already
>>>>> + * written into the rings by the GPU.
>>>>> *
>>>>> - * Layout of the ADS blob allocated for the GuC:
>>>>> + * Layout of the ADS blob (ads->bo):
>>>>> *
>>>>> * +---------------------------------------+ <== base
>>>>> * | guc_ads |
>>>>> @@ -99,10 +104,6 @@ ads_to_map(struct xe_guc_ads *ads)
>>>>> * +---------------------------------------+
>>>>> * | padding |
>>>>> * +---------------------------------------+ <== 4K aligned
>>>>> - * | UM queues |
>>>>> - * +---------------------------------------+
>>>>> - * | padding |
>>>>> - * +---------------------------------------+ <== 4K aligned
>>>>> * | private data |
>>>>> * +---------------------------------------+
>>>>> * | padding |
>>>>> @@ -156,16 +157,6 @@ static size_t guc_ads_capture_size(struct xe_guc_ads *ads)
>>>>> return PAGE_ALIGN(ads->capture_size);
>>>>> }
>>>>> -static size_t guc_ads_um_queues_size(struct xe_guc_ads *ads)
>>>>> -{
>>>>> - struct xe_device *xe = ads_to_xe(ads);
>>>>> -
>>>>> - if (!xe->info.has_usm)
>>>>> - return 0;
>>>>> -
>>>>> - return GUC_UM_QUEUE_SIZE * GUC_UM_HW_QUEUE_MAX;
>>>>> -}
>>>>> -
>>>>> static size_t guc_ads_private_data_size(struct xe_guc_ads *ads)
>>>>> {
>>>>> return PAGE_ALIGN(ads_to_guc(ads)->fw.private_data_size);
>>>>> @@ -206,22 +197,12 @@ static size_t guc_ads_capture_offset(struct xe_guc_ads *ads)
>>>>> return PAGE_ALIGN(offset);
>>>>> }
>>>>> -static size_t guc_ads_um_queues_offset(struct xe_guc_ads *ads)
>>>>> -{
>>>>> - u32 offset;
>>>>> -
>>>>> - offset = guc_ads_capture_offset(ads) +
>>>>> - guc_ads_capture_size(ads);
>>>>> -
>>>>> - return PAGE_ALIGN(offset);
>>>>> -}
>>>>> -
>>>>> static size_t guc_ads_private_data_offset(struct xe_guc_ads *ads)
>>>>> {
>>>>> size_t offset;
>>>>> - offset = guc_ads_um_queues_offset(ads) +
>>>>> - guc_ads_um_queues_size(ads);
>>>>> + offset = guc_ads_capture_offset(ads) +
>>>>> + guc_ads_capture_size(ads);
>>>>> return PAGE_ALIGN(offset);
>>>>> }
>>>>> @@ -461,6 +442,44 @@ int xe_guc_ads_init(struct xe_guc_ads *ads)
>>>>> ads->bo = bo;
>>>>> + if (xe->info.has_usm) {
>>>>> + /*
>>>>> + * Allocate a separate BO for the HW fault ring (UM queues).
>>>>> + *
>>>>> + * Round the size up to the next power of two so that
>>>>> + * (system memory, no IOMMU) the TTM pool issues a single
>>>>> + * alloc_pages(order=N) call, maximising the chance of getting
>>>>> + * a physically contiguous block. GuC requires contiguous DPA.
>>>>> + */
>>>>> + size_t um_size = roundup_pow_of_two(GUC_UM_QUEUE_SIZE *
>>>>> + GUC_UM_HW_QUEUE_MAX);
>>>>> +
>>>>> + bo = xe_managed_bo_create_pin_map(xe, tile, um_size,
>>>>> + XE_BO_FLAG_SYSTEM |
>>>>> + XE_BO_FLAG_GGTT |
>>>>> + XE_BO_FLAG_GGTT_INVALIDATE |
>>>>> + XE_BO_FLAG_PINNED_NORESTORE);
>>>>> + if (IS_ERR(bo))
>>>>> + return PTR_ERR(bo);
>>>>> +
>>>>> + /*
>>>>> + * On pre-Xe3p platforms, GAM (not GuC) accesses the UM queue
>>>>> + * ring via base_dpa, which must be a contiguous DMA address
>>>>> + * range. Verify that the allocated pages are contiguous in
>>>>> + * DMA address space.
>>>>> + */
>>>>> + if (xe_bo_sg(bo) &&
>>>>
>>>>
>>>> There is a comment from Sashiko that there might not be a valid tt for vram
>>>> buffers, so perhaps just make this check !xe_bo_is_vram() instead?
>>>>
>>>>> + !xe_guc_using_main_gamctrl_queues(ads_to_guc(ads)) &&
>>>>> + unlikely(drm_prime_get_contiguous_size(xe_bo_sg(bo)) <
>>>
>>> Using drm_prime_* really is the wrong layering. Either this helper
>>> should be some drm or sg generic or IMO we implement this helper
>>> ourselves until we have a proper one in drm or sg generic.
>>>
>>> e.g., for SG specific BOs, something like this should work.
>>>
>>> xe_bo_sg_is_contigous(struct xe_bo *bo)
>>> {
>>> struct xe_res_cursor cur;
>>>
>>> xe_assert(xe_bo_device(bo), xe_bo_sg(bo));
>>> xe_res_first_sg(xe_bo_sg(bo), 0, xe_bo_size(bo), &cur);
>>>
>>> return cur.size == xe_bo_size(bo);
>>> }
>>
>> AFAICT I don't think it's the same since you could potentially get multiple
>> sg entries underneath, where they still occupy something contig as a whole,
>
> Yes, that is possible but SG segment in Xe is 1 or 2G iirc.
>
>> and xe_res_first_sg() doesn't try to coalesce. Maybe it should? The
>
> As long as segment is at least 1G then it doesn't really matter for
> existing use cases.
>
>> !xe_bo_sg_is_contigous() will be fatal, so I think we should try as hard as
>> possible for the check.
>>
>> Agreed drm_prime_get_contiguous_size() is a bit odd, but essentially we were
>> previously implementing the same thing.
>
> Maybe move this into xe_bo helper to make this slighly more palatable
> (i.e., at least only BO layer is looking at prime).
>
> e.g.,
>
> xe_bo_sg_is_contigous(bo, len)
> return drm_prime_get_contiguous_size(xe_bo_sg(bo)) >= len;
+1
Sounds good to me.
>
> or
>
> xe_bo_sg_is_contigous(bo)
> return drm_prime_get_contiguous_size(xe_bo_sg(bo)) == xe_bo_size(bo);
>
> Matt
>
>>
>>>
>>> Matt
>>>
>>>>> + GUC_UM_QUEUE_SIZE * GUC_UM_HW_QUEUE_MAX)) {
>>>>> + drm_err(&xe->drm,
>>>>> + "UM fault queue memory is not contiguous in DMA address space; GAM requires contiguous DPA\n");
>>>>> + return -ENOMEM;
>>>>> + }
>>>>> +
>>>>> + ads->um_queue_bo = bo;
>>>>> + }
>>>>> +
>>>>> return 0;
>>>>> }
>>>>> ALLOW_ERROR_INJECTION(xe_guc_ads_init, ERRNO); /* See xe_pci_probe() */
>>>>> @@ -893,7 +912,7 @@ static void guc_mmio_reg_state_init(struct xe_guc_ads *ads)
>>>>> static void guc_um_init_params(struct xe_guc_ads *ads)
>>>>> {
>>>>> - u32 um_queue_offset = guc_ads_um_queues_offset(ads);
>>>>> + struct xe_bo *um_bo = ads->um_queue_bo;
>>>>> struct xe_guc *guc = ads_to_guc(ads);
>>>>> struct xe_device *xe = ads_to_xe(ads);
>>>>> u64 base_dpa;
>>>>> @@ -903,8 +922,14 @@ static void guc_um_init_params(struct xe_guc_ads *ads)
>>>>> with_dpa = !xe_guc_using_main_gamctrl_queues(guc);
>>>>> - base_ggtt = xe_bo_ggtt_addr(ads->bo) + um_queue_offset;
>>>>> - base_dpa = xe_bo_main_addr(ads->bo, PAGE_SIZE) + um_queue_offset;
>>>>> + if (um_bo) {
>>>>> + /* All USM platforms: UM queues in dedicated um_queue_bo */
>>>>> + base_ggtt = xe_bo_ggtt_addr(um_bo);
>>>>> + base_dpa = xe_bo_main_addr(um_bo, PAGE_SIZE);
>>>>> + } else {
>>>>> + /* Platform does not support USM: no UM queues, nothing to do */
>>>>> + return;
>>>>> + }
>>>>> for (i = 0; i < GUC_UM_HW_QUEUE_MAX; ++i) {
>>>>> /*
>>>>> diff --git a/drivers/gpu/drm/xe/xe_guc_ads_types.h b/drivers/gpu/drm/xe/xe_guc_ads_types.h
>>>>> index 48a8e092023f..845c1fbd93a4 100644
>>>>> --- a/drivers/gpu/drm/xe/xe_guc_ads_types.h
>>>>> +++ b/drivers/gpu/drm/xe/xe_guc_ads_types.h
>>>>> @@ -16,6 +16,11 @@ struct xe_bo;
>>>>> struct xe_guc_ads {
>>>>> /** @bo: Xe BO for GuC ads blob */
>>>>> struct xe_bo *bo;
>>>>> + /**
>>>>> + * @um_queue_bo: Dedicated BO for the HW fault ring (UM queues).
>>>>> + * NULL if the platform does not support USM.
>>>>> + */
>>>>> + struct xe_bo *um_queue_bo;
>>>>> /** @golden_lrc_size: golden LRC size */
>>>>> size_t golden_lrc_size;
>>>>> /** @regset_size: size of register set passed to GuC for save/restore */
>>>>
>>
^ permalink raw reply [flat|nested] 14+ messages in thread
* ✓ CI.KUnit: success for drm/xe/guc_ads: allocate UM queues in a separate UC BO (rev5)
2026-08-03 20:08 [PATCH v7 0/1] drm/xe/guc_ads: allocate UM queues in a separate UC BO Jia Yao
` (4 preceding siblings ...)
2026-08-03 22:41 ` ✓ Xe.CI.FULL: " Patchwork
@ 2026-08-04 12:23 ` Patchwork
5 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2026-08-04 12:23 UTC (permalink / raw)
To: Jia Yao; +Cc: intel-xe
== Series Details ==
Series: drm/xe/guc_ads: allocate UM queues in a separate UC BO (rev5)
URL : https://patchwork.freedesktop.org/series/169535/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[12:22:03] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[12:22:07] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[12:22:39] Starting KUnit Kernel (1/1)...
[12:22:39] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[12:22:39] ================== guc_buf (11 subtests) ===================
[12:22:39] [PASSED] test_smallest
[12:22:39] [PASSED] test_largest
[12:22:39] [PASSED] test_granular
[12:22:39] [PASSED] test_unique
[12:22:39] [PASSED] test_overlap
[12:22:39] [PASSED] test_reusable
[12:22:39] [PASSED] test_too_big
[12:22:39] [PASSED] test_flush
[12:22:39] [PASSED] test_lookup
[12:22:39] [PASSED] test_data
[12:22:39] [PASSED] test_class
[12:22:39] ===================== [PASSED] guc_buf =====================
[12:22:39] =================== guc_dbm (7 subtests) ===================
[12:22:39] [PASSED] test_empty
[12:22:39] [PASSED] test_default
[12:22:39] ======================== test_size ========================
[12:22:39] [PASSED] 4
[12:22:39] [PASSED] 8
[12:22:39] [PASSED] 32
[12:22:39] [PASSED] 256
[12:22:39] ==================== [PASSED] test_size ====================
[12:22:39] ======================= test_reuse ========================
[12:22:39] [PASSED] 4
[12:22:39] [PASSED] 8
[12:22:39] [PASSED] 32
[12:22:39] [PASSED] 256
[12:22:39] =================== [PASSED] test_reuse ====================
[12:22:39] =================== test_range_overlap ====================
[12:22:39] [PASSED] 4
[12:22:39] [PASSED] 8
[12:22:39] [PASSED] 32
[12:22:39] [PASSED] 256
[12:22:39] =============== [PASSED] test_range_overlap ================
[12:22:39] =================== test_range_compact ====================
[12:22:39] [PASSED] 4
[12:22:39] [PASSED] 8
[12:22:39] [PASSED] 32
[12:22:39] [PASSED] 256
[12:22:39] =============== [PASSED] test_range_compact ================
[12:22:39] ==================== test_range_spare =====================
[12:22:39] [PASSED] 4
[12:22:39] [PASSED] 8
[12:22:39] [PASSED] 32
[12:22:39] [PASSED] 256
[12:22:39] ================ [PASSED] test_range_spare =================
[12:22:39] ===================== [PASSED] guc_dbm =====================
[12:22:39] =================== guc_idm (6 subtests) ===================
[12:22:39] [PASSED] bad_init
[12:22:39] [PASSED] no_init
[12:22:39] [PASSED] init_fini
[12:22:39] [PASSED] check_used
[12:22:39] [PASSED] check_quota
[12:22:39] [PASSED] check_all
[12:22:39] ===================== [PASSED] guc_idm =====================
[12:22:39] =============== guc_klv_helpers (9 subtests) ===============
[12:22:39] [PASSED] test_count
[12:22:39] [PASSED] test_encode_u32
[12:22:39] [PASSED] test_encode_u64
[12:22:39] [PASSED] test_encode_string
[12:22:39] [PASSED] test_encode_object_raw
[12:22:39] [PASSED] test_encode_object_klv
[12:22:39] [PASSED] test_encode_object_nested
[12:22:39] [PASSED] test_encode_object_basic
[12:22:39] [PASSED] test_print
[12:22:39] ================= [PASSED] guc_klv_helpers =================
[12:22:39] ================== no_relay (3 subtests) ===================
[12:22:39] [PASSED] xe_drops_guc2pf_if_not_ready
[12:22:39] [PASSED] xe_drops_guc2vf_if_not_ready
[12:22:39] [PASSED] xe_rejects_send_if_not_ready
[12:22:39] ==================== [PASSED] no_relay =====================
[12:22:39] ================== pf_relay (14 subtests) ==================
[12:22:39] [PASSED] pf_rejects_guc2pf_too_short
[12:22:39] [PASSED] pf_rejects_guc2pf_too_long
[12:22:39] [PASSED] pf_rejects_guc2pf_no_payload
[12:22:39] [PASSED] pf_fails_no_payload
[12:22:39] [PASSED] pf_fails_bad_origin
[12:22:39] [PASSED] pf_fails_bad_type
[12:22:39] [PASSED] pf_txn_reports_error
[12:22:39] [PASSED] pf_txn_sends_pf2guc
[12:22:39] [PASSED] pf_sends_pf2guc
[12:22:39] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[12:22:39] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[12:22:39] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[12:22:39] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[12:22:39] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[12:22:39] ==================== [PASSED] pf_relay =====================
[12:22:39] ================== vf_relay (3 subtests) ===================
[12:22:39] [PASSED] vf_rejects_guc2vf_too_short
[12:22:39] [PASSED] vf_rejects_guc2vf_too_long
[12:22:39] [PASSED] vf_rejects_guc2vf_no_payload
[12:22:39] ==================== [PASSED] vf_relay =====================
[12:22:39] ================ pf_gt_config (9 subtests) =================
[12:22:39] [PASSED] fair_contexts_1vf
[12:22:39] [PASSED] fair_doorbells_1vf
[12:22:39] [PASSED] fair_ggtt_1vf
[12:22:39] ====================== fair_vram_1vf ======================
[12:22:39] [PASSED] 3.50 GiB
[12:22:39] [PASSED] 11.5 GiB
[12:22:39] [PASSED] 15.5 GiB
[12:22:39] [PASSED] 31.5 GiB
[12:22:39] [PASSED] 63.5 GiB
[12:22:39] [PASSED] 1.91 GiB
[12:22:39] ================== [PASSED] fair_vram_1vf ==================
[12:22:39] ================ fair_vram_1vf_admin_only =================
[12:22:39] [PASSED] 3.50 GiB
[12:22:39] [PASSED] 11.5 GiB
[12:22:39] [PASSED] 15.5 GiB
[12:22:39] [PASSED] 31.5 GiB
[12:22:39] [PASSED] 63.5 GiB
[12:22:39] [PASSED] 1.91 GiB
[12:22:39] ============ [PASSED] fair_vram_1vf_admin_only =============
[12:22:39] ====================== fair_contexts ======================
[12:22:39] [PASSED] 1 VF
[12:22:39] [PASSED] 2 VFs
[12:22:39] [PASSED] 3 VFs
[12:22:39] [PASSED] 4 VFs
[12:22:39] [PASSED] 5 VFs
[12:22:39] [PASSED] 6 VFs
[12:22:39] [PASSED] 7 VFs
[12:22:39] [PASSED] 8 VFs
[12:22:39] [PASSED] 9 VFs
[12:22:39] [PASSED] 10 VFs
[12:22:39] [PASSED] 11 VFs
[12:22:39] [PASSED] 12 VFs
[12:22:39] [PASSED] 13 VFs
[12:22:39] [PASSED] 14 VFs
[12:22:39] [PASSED] 15 VFs
[12:22:39] [PASSED] 16 VFs
[12:22:39] [PASSED] 17 VFs
[12:22:39] [PASSED] 18 VFs
[12:22:39] [PASSED] 19 VFs
[12:22:39] [PASSED] 20 VFs
[12:22:39] [PASSED] 21 VFs
[12:22:39] [PASSED] 22 VFs
[12:22:39] [PASSED] 23 VFs
[12:22:39] [PASSED] 24 VFs
[12:22:39] [PASSED] 25 VFs
[12:22:39] [PASSED] 26 VFs
[12:22:39] [PASSED] 27 VFs
[12:22:39] [PASSED] 28 VFs
[12:22:39] [PASSED] 29 VFs
[12:22:39] [PASSED] 30 VFs
[12:22:39] [PASSED] 31 VFs
[12:22:39] [PASSED] 32 VFs
[12:22:39] [PASSED] 33 VFs
[12:22:39] [PASSED] 34 VFs
[12:22:39] [PASSED] 35 VFs
[12:22:39] [PASSED] 36 VFs
[12:22:39] [PASSED] 37 VFs
[12:22:39] [PASSED] 38 VFs
[12:22:39] [PASSED] 39 VFs
[12:22:39] [PASSED] 40 VFs
[12:22:39] [PASSED] 41 VFs
[12:22:39] [PASSED] 42 VFs
[12:22:39] [PASSED] 43 VFs
[12:22:39] [PASSED] 44 VFs
[12:22:39] [PASSED] 45 VFs
[12:22:39] [PASSED] 46 VFs
[12:22:39] [PASSED] 47 VFs
[12:22:39] [PASSED] 48 VFs
[12:22:39] [PASSED] 49 VFs
[12:22:39] [PASSED] 50 VFs
[12:22:39] [PASSED] 51 VFs
[12:22:39] [PASSED] 52 VFs
[12:22:39] [PASSED] 53 VFs
[12:22:39] [PASSED] 54 VFs
[12:22:39] [PASSED] 55 VFs
[12:22:39] [PASSED] 56 VFs
[12:22:39] [PASSED] 57 VFs
[12:22:39] [PASSED] 58 VFs
[12:22:39] [PASSED] 59 VFs
[12:22:39] [PASSED] 60 VFs
[12:22:39] [PASSED] 61 VFs
[12:22:39] [PASSED] 62 VFs
[12:22:39] [PASSED] 63 VFs
[12:22:39] ================== [PASSED] fair_contexts ==================
[12:22:39] ===================== fair_doorbells ======================
[12:22:39] [PASSED] 1 VF
[12:22:39] [PASSED] 2 VFs
[12:22:39] [PASSED] 3 VFs
[12:22:39] [PASSED] 4 VFs
[12:22:39] [PASSED] 5 VFs
[12:22:39] [PASSED] 6 VFs
[12:22:39] [PASSED] 7 VFs
[12:22:39] [PASSED] 8 VFs
[12:22:39] [PASSED] 9 VFs
[12:22:39] [PASSED] 10 VFs
[12:22:39] [PASSED] 11 VFs
[12:22:39] [PASSED] 12 VFs
[12:22:39] [PASSED] 13 VFs
[12:22:39] [PASSED] 14 VFs
[12:22:39] [PASSED] 15 VFs
[12:22:39] [PASSED] 16 VFs
[12:22:39] [PASSED] 17 VFs
[12:22:39] [PASSED] 18 VFs
[12:22:39] [PASSED] 19 VFs
[12:22:39] [PASSED] 20 VFs
[12:22:39] [PASSED] 21 VFs
[12:22:39] [PASSED] 22 VFs
[12:22:39] [PASSED] 23 VFs
[12:22:39] [PASSED] 24 VFs
[12:22:39] [PASSED] 25 VFs
[12:22:39] [PASSED] 26 VFs
[12:22:39] [PASSED] 27 VFs
[12:22:39] [PASSED] 28 VFs
[12:22:39] [PASSED] 29 VFs
[12:22:39] [PASSED] 30 VFs
[12:22:39] [PASSED] 31 VFs
[12:22:39] [PASSED] 32 VFs
[12:22:39] [PASSED] 33 VFs
[12:22:39] [PASSED] 34 VFs
[12:22:39] [PASSED] 35 VFs
[12:22:39] [PASSED] 36 VFs
[12:22:39] [PASSED] 37 VFs
[12:22:39] [PASSED] 38 VFs
[12:22:39] [PASSED] 39 VFs
[12:22:39] [PASSED] 40 VFs
[12:22:39] [PASSED] 41 VFs
[12:22:39] [PASSED] 42 VFs
[12:22:39] [PASSED] 43 VFs
[12:22:39] [PASSED] 44 VFs
[12:22:39] [PASSED] 45 VFs
[12:22:39] [PASSED] 46 VFs
[12:22:39] [PASSED] 47 VFs
[12:22:39] [PASSED] 48 VFs
[12:22:39] [PASSED] 49 VFs
[12:22:39] [PASSED] 50 VFs
[12:22:39] [PASSED] 51 VFs
[12:22:39] [PASSED] 52 VFs
[12:22:39] [PASSED] 53 VFs
[12:22:39] [PASSED] 54 VFs
[12:22:39] [PASSED] 55 VFs
[12:22:39] [PASSED] 56 VFs
[12:22:39] [PASSED] 57 VFs
[12:22:39] [PASSED] 58 VFs
[12:22:39] [PASSED] 59 VFs
[12:22:39] [PASSED] 60 VFs
[12:22:39] [PASSED] 61 VFs
[12:22:39] [PASSED] 62 VFs
[12:22:39] [PASSED] 63 VFs
[12:22:39] ================= [PASSED] fair_doorbells ==================
[12:22:39] ======================== fair_ggtt ========================
[12:22:39] [PASSED] 1 VF
[12:22:39] [PASSED] 2 VFs
[12:22:39] [PASSED] 3 VFs
[12:22:39] [PASSED] 4 VFs
[12:22:39] [PASSED] 5 VFs
[12:22:39] [PASSED] 6 VFs
[12:22:39] [PASSED] 7 VFs
[12:22:39] [PASSED] 8 VFs
[12:22:39] [PASSED] 9 VFs
[12:22:39] [PASSED] 10 VFs
[12:22:39] [PASSED] 11 VFs
[12:22:39] [PASSED] 12 VFs
[12:22:39] [PASSED] 13 VFs
[12:22:39] [PASSED] 14 VFs
[12:22:39] [PASSED] 15 VFs
[12:22:39] [PASSED] 16 VFs
[12:22:39] [PASSED] 17 VFs
[12:22:39] [PASSED] 18 VFs
[12:22:39] [PASSED] 19 VFs
[12:22:39] [PASSED] 20 VFs
[12:22:39] [PASSED] 21 VFs
[12:22:39] [PASSED] 22 VFs
[12:22:39] [PASSED] 23 VFs
[12:22:39] [PASSED] 24 VFs
[12:22:39] [PASSED] 25 VFs
[12:22:39] [PASSED] 26 VFs
[12:22:39] [PASSED] 27 VFs
[12:22:39] [PASSED] 28 VFs
[12:22:39] [PASSED] 29 VFs
[12:22:39] [PASSED] 30 VFs
[12:22:39] [PASSED] 31 VFs
[12:22:39] [PASSED] 32 VFs
[12:22:39] [PASSED] 33 VFs
[12:22:39] [PASSED] 34 VFs
[12:22:39] [PASSED] 35 VFs
[12:22:39] [PASSED] 36 VFs
[12:22:39] [PASSED] 37 VFs
[12:22:39] [PASSED] 38 VFs
[12:22:39] [PASSED] 39 VFs
[12:22:39] [PASSED] 40 VFs
[12:22:39] [PASSED] 41 VFs
[12:22:39] [PASSED] 42 VFs
[12:22:39] [PASSED] 43 VFs
[12:22:39] [PASSED] 44 VFs
[12:22:39] [PASSED] 45 VFs
[12:22:39] [PASSED] 46 VFs
[12:22:39] [PASSED] 47 VFs
[12:22:39] [PASSED] 48 VFs
[12:22:39] [PASSED] 49 VFs
[12:22:39] [PASSED] 50 VFs
[12:22:39] [PASSED] 51 VFs
[12:22:39] [PASSED] 52 VFs
[12:22:39] [PASSED] 53 VFs
[12:22:39] [PASSED] 54 VFs
[12:22:39] [PASSED] 55 VFs
[12:22:39] [PASSED] 56 VFs
[12:22:39] [PASSED] 57 VFs
[12:22:39] [PASSED] 58 VFs
[12:22:39] [PASSED] 59 VFs
[12:22:39] [PASSED] 60 VFs
[12:22:39] [PASSED] 61 VFs
[12:22:39] [PASSED] 62 VFs
[12:22:39] [PASSED] 63 VFs
[12:22:39] ==================== [PASSED] fair_ggtt ====================
[12:22:39] ======================== fair_vram ========================
[12:22:39] [PASSED] 1 VF
[12:22:39] [PASSED] 2 VFs
[12:22:39] [PASSED] 3 VFs
[12:22:39] [PASSED] 4 VFs
[12:22:39] [PASSED] 5 VFs
[12:22:39] [PASSED] 6 VFs
[12:22:39] [PASSED] 7 VFs
[12:22:39] [PASSED] 8 VFs
[12:22:39] [PASSED] 9 VFs
[12:22:39] [PASSED] 10 VFs
[12:22:39] [PASSED] 11 VFs
[12:22:39] [PASSED] 12 VFs
[12:22:39] [PASSED] 13 VFs
[12:22:39] [PASSED] 14 VFs
[12:22:39] [PASSED] 15 VFs
[12:22:39] [PASSED] 16 VFs
[12:22:39] [PASSED] 17 VFs
[12:22:39] [PASSED] 18 VFs
[12:22:39] [PASSED] 19 VFs
[12:22:39] [PASSED] 20 VFs
[12:22:39] [PASSED] 21 VFs
[12:22:39] [PASSED] 22 VFs
[12:22:39] [PASSED] 23 VFs
[12:22:39] [PASSED] 24 VFs
[12:22:39] [PASSED] 25 VFs
[12:22:39] [PASSED] 26 VFs
[12:22:39] [PASSED] 27 VFs
[12:22:39] [PASSED] 28 VFs
[12:22:39] [PASSED] 29 VFs
[12:22:39] [PASSED] 30 VFs
[12:22:39] [PASSED] 31 VFs
[12:22:39] [PASSED] 32 VFs
[12:22:39] [PASSED] 33 VFs
[12:22:39] [PASSED] 34 VFs
[12:22:39] [PASSED] 35 VFs
[12:22:39] [PASSED] 36 VFs
[12:22:39] [PASSED] 37 VFs
[12:22:39] [PASSED] 38 VFs
[12:22:39] [PASSED] 39 VFs
[12:22:39] [PASSED] 40 VFs
[12:22:39] [PASSED] 41 VFs
[12:22:39] [PASSED] 42 VFs
[12:22:39] [PASSED] 43 VFs
[12:22:39] [PASSED] 44 VFs
[12:22:39] [PASSED] 45 VFs
[12:22:39] [PASSED] 46 VFs
[12:22:39] [PASSED] 47 VFs
[12:22:39] [PASSED] 48 VFs
[12:22:39] [PASSED] 49 VFs
[12:22:39] [PASSED] 50 VFs
[12:22:39] [PASSED] 51 VFs
[12:22:39] [PASSED] 52 VFs
[12:22:39] [PASSED] 53 VFs
[12:22:39] [PASSED] 54 VFs
[12:22:39] [PASSED] 55 VFs
[12:22:39] [PASSED] 56 VFs
[12:22:39] [PASSED] 57 VFs
[12:22:39] [PASSED] 58 VFs
[12:22:39] [PASSED] 59 VFs
[12:22:39] [PASSED] 60 VFs
[12:22:39] [PASSED] 61 VFs
[12:22:39] [PASSED] 62 VFs
[12:22:39] [PASSED] 63 VFs
[12:22:39] ==================== [PASSED] fair_vram ====================
[12:22:39] ================== [PASSED] pf_gt_config ===================
[12:22:39] ===================== lmtt (1 subtest) =====================
[12:22:39] ======================== test_ops =========================
[12:22:39] [PASSED] 2-level
[12:22:39] [PASSED] multi-level
[12:22:39] ==================== [PASSED] test_ops =====================
[12:22:39] ====================== [PASSED] lmtt =======================
[12:22:39] ================= sriov_packet (1 subtest) =================
[12:22:39] [PASSED] test_descriptor_init
[12:22:39] ================== [PASSED] sriov_packet ===================
[12:22:39] ================= pf_service (11 subtests) =================
[12:22:39] [PASSED] pf_negotiate_any
[12:22:39] [PASSED] pf_negotiate_base_match
[12:22:39] [PASSED] pf_negotiate_base_newer
[12:22:39] [PASSED] pf_negotiate_base_next
[12:22:39] [SKIPPED] pf_negotiate_base_older (no older minor)
[12:22:39] [PASSED] pf_negotiate_base_prev
[12:22:39] [PASSED] pf_negotiate_latest_match
[12:22:39] [PASSED] pf_negotiate_latest_newer
[12:22:39] [PASSED] pf_negotiate_latest_next
[12:22:39] [SKIPPED] pf_negotiate_latest_older (no older minor)
[12:22:39] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[12:22:39] =================== [PASSED] pf_service ====================
[12:22:39] ================= xe_guc_g2g (2 subtests) ==================
[12:22:39] ============== xe_live_guc_g2g_kunit_default ==============
[12:22:39] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[12:22:39] ============== xe_live_guc_g2g_kunit_allmem ===============
[12:22:39] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[12:22:39] =================== [SKIPPED] xe_guc_g2g ===================
[12:22:39] =================== xe_mocs (2 subtests) ===================
[12:22:39] ================ xe_live_mocs_kernel_kunit ================
[12:22:39] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[12:22:39] ================ xe_live_mocs_reset_kunit =================
[12:22:39] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[12:22:39] ==================== [SKIPPED] xe_mocs =====================
[12:22:39] ================= xe_migrate (2 subtests) ==================
[12:22:39] ================= xe_migrate_sanity_kunit =================
[12:22:39] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[12:22:39] ================== xe_validate_ccs_kunit ==================
[12:22:39] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[12:22:39] =================== [SKIPPED] xe_migrate ===================
[12:22:39] ================== xe_dma_buf (1 subtest) ==================
[12:22:39] ==================== xe_dma_buf_kunit =====================
[12:22:39] ================ [SKIPPED] xe_dma_buf_kunit ================
[12:22:39] =================== [SKIPPED] xe_dma_buf ===================
[12:22:39] ================= xe_bo_shrink (1 subtest) =================
[12:22:39] =================== xe_bo_shrink_kunit ====================
[12:22:39] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[12:22:39] ================== [SKIPPED] xe_bo_shrink ==================
[12:22:39] ==================== xe_bo (2 subtests) ====================
[12:22:39] ================== xe_ccs_migrate_kunit ===================
[12:22:39] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[12:22:39] ==================== xe_bo_evict_kunit ====================
[12:22:39] =============== [SKIPPED] xe_bo_evict_kunit ================
[12:22:39] ===================== [SKIPPED] xe_bo ======================
[12:22:39] ==================== args (13 subtests) ====================
[12:22:39] [PASSED] count_args_test
[12:22:39] [PASSED] call_args_example
[12:22:39] [PASSED] call_args_test
[12:22:39] [PASSED] drop_first_arg_example
[12:22:39] [PASSED] drop_first_arg_test
[12:22:39] [PASSED] first_arg_example
[12:22:39] [PASSED] first_arg_test
[12:22:39] [PASSED] last_arg_example
[12:22:39] [PASSED] last_arg_test
[12:22:39] [PASSED] pick_arg_example
[12:22:39] [PASSED] if_args_example
[12:22:39] [PASSED] if_args_test
[12:22:39] [PASSED] sep_comma_example
[12:22:39] ====================== [PASSED] args =======================
[12:22:39] =================== xe_pci (3 subtests) ====================
[12:22:39] ==================== check_graphics_ip ====================
[12:22:39] [PASSED] 12.00 Xe_LP
[12:22:39] [PASSED] 12.10 Xe_LP+
[12:22:39] [PASSED] 12.55 Xe_HPG
[12:22:39] [PASSED] 12.60 Xe_HPC
[12:22:39] [PASSED] 12.70 Xe_LPG
[12:22:39] [PASSED] 12.71 Xe_LPG
[12:22:39] [PASSED] 12.74 Xe_LPG+
[12:22:39] [PASSED] 20.01 Xe2_HPG
[12:22:39] [PASSED] 20.02 Xe2_HPG
[12:22:39] [PASSED] 20.04 Xe2_LPG
[12:22:39] [PASSED] 30.00 Xe3_LPG
[12:22:39] [PASSED] 30.01 Xe3_LPG
[12:22:39] [PASSED] 30.03 Xe3_LPG
[12:22:39] [PASSED] 30.04 Xe3_LPG
[12:22:39] [PASSED] 30.05 Xe3_LPG
[12:22:39] [PASSED] 35.10 Xe3p_LPG
[12:22:39] [PASSED] 35.11 Xe3p_XPC
[12:22:39] ================ [PASSED] check_graphics_ip ================
[12:22:39] ===================== check_media_ip ======================
[12:22:39] [PASSED] 12.00 Xe_M
[12:22:39] [PASSED] 12.55 Xe_HPM
[12:22:39] [PASSED] 13.00 Xe_LPM+
[12:22:39] [PASSED] 13.01 Xe2_HPM
[12:22:39] [PASSED] 20.00 Xe2_LPM
[12:22:39] [PASSED] 30.00 Xe3_LPM
[12:22:39] [PASSED] 30.02 Xe3_LPM
[12:22:39] [PASSED] 35.00 Xe3p_LPM
[12:22:39] [PASSED] 35.03 Xe3p_HPM
[12:22:39] ================= [PASSED] check_media_ip ==================
[12:22:39] =================== check_platform_desc ===================
[12:22:39] [PASSED] 0x9A60 (TIGERLAKE)
[12:22:39] [PASSED] 0x9A68 (TIGERLAKE)
[12:22:39] [PASSED] 0x9A70 (TIGERLAKE)
[12:22:39] [PASSED] 0x9A40 (TIGERLAKE)
[12:22:39] [PASSED] 0x9A49 (TIGERLAKE)
[12:22:39] [PASSED] 0x9A59 (TIGERLAKE)
[12:22:39] [PASSED] 0x9A78 (TIGERLAKE)
[12:22:39] [PASSED] 0x9AC0 (TIGERLAKE)
[12:22:39] [PASSED] 0x9AC9 (TIGERLAKE)
[12:22:39] [PASSED] 0x9AD9 (TIGERLAKE)
[12:22:39] [PASSED] 0x9AF8 (TIGERLAKE)
[12:22:39] [PASSED] 0x4C80 (ROCKETLAKE)
[12:22:39] [PASSED] 0x4C8A (ROCKETLAKE)
[12:22:39] [PASSED] 0x4C8B (ROCKETLAKE)
[12:22:39] [PASSED] 0x4C8C (ROCKETLAKE)
[12:22:39] [PASSED] 0x4C90 (ROCKETLAKE)
[12:22:39] [PASSED] 0x4C9A (ROCKETLAKE)
[12:22:39] [PASSED] 0x4680 (ALDERLAKE_S)
[12:22:39] [PASSED] 0x4682 (ALDERLAKE_S)
[12:22:39] [PASSED] 0x4688 (ALDERLAKE_S)
[12:22:39] [PASSED] 0x468A (ALDERLAKE_S)
[12:22:39] [PASSED] 0x468B (ALDERLAKE_S)
[12:22:39] [PASSED] 0x4690 (ALDERLAKE_S)
[12:22:39] [PASSED] 0x4692 (ALDERLAKE_S)
[12:22:39] [PASSED] 0x4693 (ALDERLAKE_S)
[12:22:39] [PASSED] 0x46A0 (ALDERLAKE_P)
[12:22:39] [PASSED] 0x46A1 (ALDERLAKE_P)
[12:22:39] [PASSED] 0x46A2 (ALDERLAKE_P)
[12:22:39] [PASSED] 0x46A3 (ALDERLAKE_P)
[12:22:39] [PASSED] 0x46A6 (ALDERLAKE_P)
[12:22:39] [PASSED] 0x46A8 (ALDERLAKE_P)
[12:22:39] [PASSED] 0x46AA (ALDERLAKE_P)
[12:22:39] [PASSED] 0x462A (ALDERLAKE_P)
[12:22:39] [PASSED] 0x4626 (ALDERLAKE_P)
[12:22:39] [PASSED] 0x4628 (ALDERLAKE_P)
[12:22:39] [PASSED] 0x46B0 (ALDERLAKE_P)
[12:22:39] [PASSED] 0x46B1 (ALDERLAKE_P)
[12:22:39] [PASSED] 0x46B2 (ALDERLAKE_P)
[12:22:39] [PASSED] 0x46B3 (ALDERLAKE_P)
[12:22:39] [PASSED] 0x46C0 (ALDERLAKE_P)
[12:22:39] [PASSED] 0x46C1 (ALDERLAKE_P)
[12:22:39] [PASSED] 0x46C2 (ALDERLAKE_P)
[12:22:39] [PASSED] 0x46C3 (ALDERLAKE_P)
[12:22:39] [PASSED] 0x46D0 (ALDERLAKE_N)
[12:22:39] [PASSED] 0x46D1 (ALDERLAKE_N)
[12:22:39] [PASSED] 0x46D2 (ALDERLAKE_N)
[12:22:39] [PASSED] 0x46D3 (ALDERLAKE_N)
[12:22:39] [PASSED] 0x46D4 (ALDERLAKE_N)
[12:22:39] [PASSED] 0xA721 (ALDERLAKE_P)
[12:22:39] [PASSED] 0xA7A1 (ALDERLAKE_P)
[12:22:39] [PASSED] 0xA7A9 (ALDERLAKE_P)
[12:22:39] [PASSED] 0xA7AC (ALDERLAKE_P)
[12:22:39] [PASSED] 0xA7AD (ALDERLAKE_P)
[12:22:39] [PASSED] 0xA720 (ALDERLAKE_P)
[12:22:39] [PASSED] 0xA7A0 (ALDERLAKE_P)
[12:22:39] [PASSED] 0xA7A8 (ALDERLAKE_P)
[12:22:39] [PASSED] 0xA7AA (ALDERLAKE_P)
[12:22:39] [PASSED] 0xA7AB (ALDERLAKE_P)
[12:22:39] [PASSED] 0xA780 (ALDERLAKE_S)
[12:22:39] [PASSED] 0xA781 (ALDERLAKE_S)
[12:22:39] [PASSED] 0xA782 (ALDERLAKE_S)
[12:22:39] [PASSED] 0xA783 (ALDERLAKE_S)
[12:22:39] [PASSED] 0xA788 (ALDERLAKE_S)
[12:22:39] [PASSED] 0xA789 (ALDERLAKE_S)
[12:22:39] [PASSED] 0xA78A (ALDERLAKE_S)
[12:22:39] [PASSED] 0xA78B (ALDERLAKE_S)
[12:22:39] [PASSED] 0x4905 (DG1)
[12:22:39] [PASSED] 0x4906 (DG1)
[12:22:39] [PASSED] 0x4907 (DG1)
[12:22:39] [PASSED] 0x4908 (DG1)
[12:22:39] [PASSED] 0x4909 (DG1)
[12:22:39] [PASSED] 0x56C0 (DG2)
[12:22:39] [PASSED] 0x56C2 (DG2)
[12:22:39] [PASSED] 0x56C1 (DG2)
[12:22:39] [PASSED] 0x7D51 (METEORLAKE)
[12:22:39] [PASSED] 0x7DD1 (METEORLAKE)
[12:22:39] [PASSED] 0x7D41 (METEORLAKE)
[12:22:39] [PASSED] 0x7D67 (METEORLAKE)
[12:22:39] [PASSED] 0xB640 (METEORLAKE)
[12:22:39] [PASSED] 0x56A0 (DG2)
[12:22:39] [PASSED] 0x56A1 (DG2)
[12:22:39] [PASSED] 0x56A2 (DG2)
[12:22:39] [PASSED] 0x56BE (DG2)
[12:22:39] [PASSED] 0x56BF (DG2)
[12:22:39] [PASSED] 0x5690 (DG2)
[12:22:39] [PASSED] 0x5691 (DG2)
[12:22:39] [PASSED] 0x5692 (DG2)
[12:22:39] [PASSED] 0x56A5 (DG2)
[12:22:39] [PASSED] 0x56A6 (DG2)
[12:22:39] [PASSED] 0x56B0 (DG2)
[12:22:39] [PASSED] 0x56B1 (DG2)
[12:22:39] [PASSED] 0x56BA (DG2)
[12:22:39] [PASSED] 0x56BB (DG2)
[12:22:39] [PASSED] 0x56BC (DG2)
[12:22:39] [PASSED] 0x56BD (DG2)
[12:22:39] [PASSED] 0x5693 (DG2)
[12:22:39] [PASSED] 0x5694 (DG2)
[12:22:39] [PASSED] 0x5695 (DG2)
[12:22:39] [PASSED] 0x56A3 (DG2)
[12:22:39] [PASSED] 0x56A4 (DG2)
[12:22:39] [PASSED] 0x56B2 (DG2)
[12:22:39] [PASSED] 0x56B3 (DG2)
[12:22:39] [PASSED] 0x5696 (DG2)
[12:22:39] [PASSED] 0x5697 (DG2)
[12:22:39] [PASSED] 0xB69 (PVC)
[12:22:39] [PASSED] 0xB6E (PVC)
[12:22:39] [PASSED] 0xBD4 (PVC)
[12:22:39] [PASSED] 0xBD5 (PVC)
[12:22:39] [PASSED] 0xBD6 (PVC)
[12:22:39] [PASSED] 0xBD7 (PVC)
[12:22:39] [PASSED] 0xBD8 (PVC)
[12:22:39] [PASSED] 0xBD9 (PVC)
[12:22:39] [PASSED] 0xBDA (PVC)
[12:22:39] [PASSED] 0xBDB (PVC)
[12:22:39] [PASSED] 0xBE0 (PVC)
[12:22:39] [PASSED] 0xBE1 (PVC)
[12:22:39] [PASSED] 0xBE5 (PVC)
[12:22:39] [PASSED] 0x7D40 (METEORLAKE)
[12:22:39] [PASSED] 0x7D45 (METEORLAKE)
[12:22:39] [PASSED] 0x7D55 (METEORLAKE)
[12:22:39] [PASSED] 0x7D60 (METEORLAKE)
[12:22:39] [PASSED] 0x7DD5 (METEORLAKE)
[12:22:39] [PASSED] 0x6420 (LUNARLAKE)
[12:22:39] [PASSED] 0x64A0 (LUNARLAKE)
[12:22:39] [PASSED] 0x64B0 (LUNARLAKE)
[12:22:39] [PASSED] 0xE202 (BATTLEMAGE)
[12:22:39] [PASSED] 0xE209 (BATTLEMAGE)
[12:22:39] [PASSED] 0xE20B (BATTLEMAGE)
[12:22:39] [PASSED] 0xE20C (BATTLEMAGE)
[12:22:39] [PASSED] 0xE20D (BATTLEMAGE)
[12:22:39] [PASSED] 0xE210 (BATTLEMAGE)
[12:22:39] [PASSED] 0xE211 (BATTLEMAGE)
[12:22:39] [PASSED] 0xE212 (BATTLEMAGE)
[12:22:39] [PASSED] 0xE216 (BATTLEMAGE)
[12:22:39] [PASSED] 0xE220 (BATTLEMAGE)
[12:22:39] [PASSED] 0xE221 (BATTLEMAGE)
[12:22:39] [PASSED] 0xE222 (BATTLEMAGE)
[12:22:39] [PASSED] 0xE223 (BATTLEMAGE)
[12:22:39] [PASSED] 0xB080 (PANTHERLAKE)
[12:22:39] [PASSED] 0xB081 (PANTHERLAKE)
[12:22:39] [PASSED] 0xB082 (PANTHERLAKE)
[12:22:39] [PASSED] 0xB083 (PANTHERLAKE)
[12:22:39] [PASSED] 0xB084 (PANTHERLAKE)
[12:22:39] [PASSED] 0xB085 (PANTHERLAKE)
[12:22:39] [PASSED] 0xB086 (PANTHERLAKE)
[12:22:39] [PASSED] 0xB087 (PANTHERLAKE)
[12:22:39] [PASSED] 0xB08F (PANTHERLAKE)
[12:22:39] [PASSED] 0xB090 (PANTHERLAKE)
[12:22:39] [PASSED] 0xB0A0 (PANTHERLAKE)
[12:22:39] [PASSED] 0xB0B0 (PANTHERLAKE)
[12:22:39] [PASSED] 0xFD80 (PANTHERLAKE)
[12:22:39] [PASSED] 0xFD81 (PANTHERLAKE)
[12:22:39] [PASSED] 0xD740 (NOVALAKE_S)
[12:22:39] [PASSED] 0xD741 (NOVALAKE_S)
[12:22:39] [PASSED] 0xD742 (NOVALAKE_S)
[12:22:39] [PASSED] 0xD743 (NOVALAKE_S)
[12:22:39] [PASSED] 0xD745 (NOVALAKE_S)
[12:22:39] [PASSED] 0xD74A (NOVALAKE_S)
[12:22:39] [PASSED] 0xD74B (NOVALAKE_S)
[12:22:39] [PASSED] 0x674C (CRESCENTISLAND)
[12:22:39] [PASSED] 0x674D (CRESCENTISLAND)
[12:22:39] [PASSED] 0x674E (CRESCENTISLAND)
[12:22:39] [PASSED] 0x674F (CRESCENTISLAND)
[12:22:39] [PASSED] 0x6750 (CRESCENTISLAND)
[12:22:39] [PASSED] 0xD750 (NOVALAKE_P)
[12:22:39] [PASSED] 0xD751 (NOVALAKE_P)
[12:22:39] [PASSED] 0xD752 (NOVALAKE_P)
[12:22:39] [PASSED] 0xD753 (NOVALAKE_P)
[12:22:39] [PASSED] 0xD754 (NOVALAKE_P)
[12:22:39] [PASSED] 0xD755 (NOVALAKE_P)
[12:22:39] [PASSED] 0xD756 (NOVALAKE_P)
[12:22:39] [PASSED] 0xD757 (NOVALAKE_P)
[12:22:39] [PASSED] 0xD75F (NOVALAKE_P)
[12:22:39] =============== [PASSED] check_platform_desc ===============
[12:22:39] ===================== [PASSED] xe_pci ======================
[12:22:39] ============= xe_rtp_tables_test (5 subtests) ==============
[12:22:39] ================== xe_rtp_table_gt_test ===================
[12:22:39] [PASSED] gt_was/14011060649
[12:22:39] [PASSED] gt_was/14011059788
[12:22:39] [PASSED] gt_was/14015795083
[12:22:39] [PASSED] gt_was/16021867713
[12:22:39] [PASSED] gt_was/14019449301
[12:22:39] [PASSED] gt_was/16028005424
[12:22:39] [PASSED] gt_was/14026578760
[12:22:39] [PASSED] gt_was/1409420604
[12:22:39] [PASSED] gt_was/1408615072
[12:22:39] [PASSED] gt_was/22010523718
[12:22:39] [PASSED] gt_was/14011006942
[12:22:39] [PASSED] gt_was/14014830051
[12:22:39] [PASSED] gt_was/18018781329
[12:22:39] [PASSED] gt_was/1509235366
[12:22:39] [PASSED] gt_was/18018781329
[12:22:39] [PASSED] gt_was/16016694945
[12:22:39] [PASSED] gt_was/14018575942
[12:22:39] [PASSED] gt_was/22016670082
[12:22:39] [PASSED] gt_was/22016670082
[12:22:39] [PASSED] gt_was/14017421178
[12:22:39] [PASSED] gt_was/16025250150
[12:22:39] [PASSED] gt_was/14021871409
[12:22:39] [PASSED] gt_was/16021865536
[12:22:39] [PASSED] gt_was/14021486841
[12:22:39] [PASSED] gt_was/14025160223
[12:22:39] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[12:22:39] [PASSED] gt_was/14025635424
[12:22:39] [PASSED] gt_was/16028005424
[12:22:39] ============== [PASSED] xe_rtp_table_gt_test ===============
[12:22:39] ================== xe_rtp_table_gt_test ===================
[12:22:39] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[12:22:39] [PASSED] gt_tunings/Tuning: 32B Access Enable
[12:22:39] [PASSED] gt_tunings/Tuning: L3 cache
[12:22:39] [PASSED] gt_tunings/Tuning: L3 cache - media
[12:22:39] [PASSED] gt_tunings/Tuning: Compression Overfetch
[12:22:39] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[12:22:39] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[12:22:39] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[12:22:39] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[12:22:39] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[12:22:39] [PASSED] gt_tunings/Tuning: Stateless compression control
[12:22:39] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[12:22:39] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[12:22:39] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[12:22:39] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[12:22:39] ============== [PASSED] xe_rtp_table_gt_test ===============
[12:22:39] ================== xe_rtp_table_oob_test ==================
[12:22:39] [PASSED] oob_was/1607983814
[12:22:39] [PASSED] oob_was/16010904313
[12:22:39] [PASSED] oob_was/18022495364
[12:22:39] [PASSED] oob_was/22012773006
[12:22:39] [PASSED] oob_was/14014475959
[12:22:39] [PASSED] oob_was/22011391025
[12:22:39] [PASSED] oob_was/22012727170
[12:22:39] [PASSED] oob_was/22012727685
[12:22:39] [PASSED] oob_was/22016596838
[12:22:39] [PASSED] oob_was/18020744125
[12:22:39] [PASSED] oob_was/1409600907
[12:22:39] [PASSED] oob_was/22014953428
[12:22:39] [PASSED] oob_was/16017236439
[12:22:39] [PASSED] oob_was/14019821291
[12:22:39] [PASSED] oob_was/14015076503
[12:22:39] [PASSED] oob_was/14018913170
[12:22:39] [PASSED] oob_was/14018094691
[12:22:39] [PASSED] oob_was/18024947630
[12:22:39] [PASSED] oob_was/16022287689
[12:22:39] [PASSED] oob_was/13011645652
[12:22:39] [PASSED] oob_was/14022293748
[12:22:39] [PASSED] oob_was/22019794406
[12:22:39] [PASSED] oob_was/22019338487
[12:22:39] [PASSED] oob_was/16023588340
[12:22:39] [PASSED] oob_was/14019789679
[12:22:39] [PASSED] oob_was/14022866841
[12:22:39] [PASSED] oob_was/16021333562
[12:22:39] [PASSED] oob_was/14016712196
[12:22:39] [PASSED] oob_was/14015568240
[12:22:39] [PASSED] oob_was/18013179988
[12:22:39] [PASSED] oob_was/1508761755
[12:22:39] [PASSED] oob_was/16023105232
[12:22:39] [PASSED] oob_was/16026508708
[12:22:39] [PASSED] oob_was/14020001231
[12:22:39] [PASSED] oob_was/16023683509
[12:22:39] [PASSED] oob_was/14025515070
[12:22:39] [PASSED] oob_was/15015404425_disable
[12:22:39] [PASSED] oob_was/16026007364
[12:22:39] [PASSED] oob_was/14020316580
[12:22:39] [PASSED] oob_was/14025883347
[12:22:39] [PASSED] oob_was/16029380221
[12:22:39] [PASSED] oob_was/22022079272
[12:22:39] [PASSED] oob_was/16029897822
[12:22:39] [PASSED] oob_was/14027054324
[12:22:39] ============== [PASSED] xe_rtp_table_oob_test ==============
[12:22:39] ================ xe_rtp_table_dev_oob_test ================
[12:22:39] [PASSED] device_oob_was/22010954014
[12:22:39] [PASSED] device_oob_was/15015404425
[12:22:39] [PASSED] device_oob_was/22019338487_display
[12:22:39] [PASSED] device_oob_was/14022085890
[12:22:39] [PASSED] device_oob_was/14026539277
[12:22:39] [PASSED] device_oob_was/14026633728
[12:22:39] [PASSED] device_oob_was/14026746987
[12:22:39] [PASSED] device_oob_was/14026779378
[12:22:39] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[12:22:39] ========== xe_rtp_table_missing_upper_bound_test ==========
[12:22:39] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[12:22:39] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[12:22:39] [PASSED] register_whitelist/1806527549
[12:22:39] [PASSED] register_whitelist/allow_read_ctx_timestamp
[12:22:39] [PASSED] register_whitelist/allow_read_queue_timestamp
[12:22:39] [PASSED] register_whitelist/16014440446
[12:22:39] [PASSED] register_whitelist/16017236439
[12:22:39] [PASSED] register_whitelist/16020183090
[12:22:39] [PASSED] register_whitelist/14024997852
[12:22:39] [PASSED] register_whitelist/14024997852
[12:22:39] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[12:22:39] =============== [PASSED] xe_rtp_tables_test ================
[12:22:39] =================== xe_rtp (3 subtests) ====================
[12:22:39] =================== xe_rtp_rules_tests ====================
[12:22:39] [PASSED] no
[12:22:39] [PASSED] yes
[12:22:39] [PASSED] no-and-no
[12:22:39] [PASSED] no-and-yes
[12:22:39] [PASSED] yes-and-no
[12:22:39] [PASSED] yes-and-yes
[12:22:39] [PASSED] no-or-no
[12:22:39] [PASSED] no-or-yes
[12:22:39] [PASSED] yes-or-no
[12:22:39] [PASSED] yes-or-yes
[12:22:39] [PASSED] no-yes-or-yes-no
[12:22:39] [PASSED] no-yes-or-yes-yes
[12:22:39] [PASSED] yes-yes-or-no-yes
[12:22:39] [PASSED] yes-yes-or-yes-yes
[12:22:39] [PASSED] no-no-or-yes-or-no
[12:22:39] [PASSED] or
[12:22:39] [PASSED] or-yes
[12:22:39] [PASSED] or-no
[12:22:39] [PASSED] yes-or
[12:22:39] [PASSED] no-or
[12:22:39] [PASSED] no-or-or-yes
[12:22:39] [PASSED] yes-or-or-no
[12:22:39] [PASSED] no-or-or-no
[12:22:39] [PASSED] missing-context-engine-class
[12:22:39] [PASSED] missing-context-engine-class-or-yes
[12:22:39] [PASSED] missing-context-engine-class-or-or-yes
[12:22:39] =============== [PASSED] xe_rtp_rules_tests ================
[12:22:39] =============== xe_rtp_process_to_sr_tests ================
[12:22:39] [PASSED] coalesce-same-reg
[12:22:39] [PASSED] coalesce-same-reg-literal-and-func
[12:22:39] [PASSED] no-match-no-add
[12:22:39] [PASSED] two-regs-two-entries
[12:22:39] [PASSED] clr-one-set-other
[12:22:39] [PASSED] set-field
[12:22:39] [PASSED] conflict-duplicate
[12:22:39] [PASSED] conflict-not-disjoint
[12:22:39] [PASSED] conflict-not-disjoint-literal-and-func
[12:22:39] [PASSED] conflict-reg-type
[12:22:39] [PASSED] bad-mcr-reg-forced-to-regular
[12:22:39] [PASSED] bad-regular-reg-forced-to-mcr
[12:22:39] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[12:22:39] ================== xe_rtp_process_tests ===================
[12:22:39] [PASSED] active1
[12:22:39] [PASSED] active2
[12:22:39] [PASSED] active-inactive
[12:22:39] [PASSED] inactive-active
[12:22:39] [PASSED] inactive-active-inactive
[12:22:39] [PASSED] inactive-inactive-inactive
[12:22:39] ============== [PASSED] xe_rtp_process_tests ===============
[12:22:39] ===================== [PASSED] xe_rtp ======================
[12:22:39] ==================== xe_wa (1 subtest) =====================
[12:22:39] ======================== xe_wa_gt =========================
[12:22:39] [PASSED] TIGERLAKE B0
[12:22:39] [PASSED] DG1 A0
[12:22:39] [PASSED] DG1 B0
[12:22:39] [PASSED] ALDERLAKE_S A0
[12:22:39] [PASSED] ALDERLAKE_S B0
[12:22:39] [PASSED] ALDERLAKE_S C0
[12:22:39] [PASSED] ALDERLAKE_S D0
[12:22:39] [PASSED] ALDERLAKE_P A0
[12:22:39] [PASSED] ALDERLAKE_P B0
[12:22:39] [PASSED] ALDERLAKE_P C0
[12:22:39] [PASSED] ALDERLAKE_S RPLS D0
[12:22:39] [PASSED] ALDERLAKE_P RPLU E0
[12:22:39] [PASSED] DG2 G10 C0
[12:22:39] [PASSED] DG2 G11 B1
[12:22:39] [PASSED] DG2 G12 A1
[12:22:39] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[12:22:39] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[12:22:39] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[12:22:39] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[12:22:39] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[12:22:39] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[12:22:39] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[12:22:39] ==================== [PASSED] xe_wa_gt =====================
[12:22:39] ====================== [PASSED] xe_wa ======================
[12:22:39] ============================================================
[12:22:39] Testing complete. Ran 742 tests: passed: 724, skipped: 18
[12:22:39] Elapsed time: 36.691s total, 4.425s configuring, 31.600s building, 0.627s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[12:22:39] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[12:22:41] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[12:23:06] Starting KUnit Kernel (1/1)...
[12:23:06] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[12:23:06] ============ drm_test_pick_cmdline (2 subtests) ============
[12:23:06] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[12:23:06] =============== drm_test_pick_cmdline_named ===============
[12:23:06] [PASSED] NTSC
[12:23:06] [PASSED] NTSC-J
[12:23:06] [PASSED] PAL
[12:23:06] [PASSED] PAL-M
[12:23:06] =========== [PASSED] drm_test_pick_cmdline_named ===========
[12:23:06] ============== [PASSED] drm_test_pick_cmdline ==============
[12:23:06] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[12:23:06] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[12:23:06] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[12:23:06] =========== drm_validate_clone_mode (2 subtests) ===========
[12:23:06] ============== drm_test_check_in_clone_mode ===============
[12:23:06] [PASSED] in_clone_mode
[12:23:06] [PASSED] not_in_clone_mode
[12:23:06] ========== [PASSED] drm_test_check_in_clone_mode ===========
[12:23:06] =============== drm_test_check_valid_clones ===============
[12:23:06] [PASSED] not_in_clone_mode
[12:23:06] [PASSED] valid_clone
[12:23:06] [PASSED] invalid_clone
[12:23:06] =========== [PASSED] drm_test_check_valid_clones ===========
[12:23:06] ============= [PASSED] drm_validate_clone_mode =============
[12:23:06] ============= drm_validate_modeset (1 subtest) =============
[12:23:06] [PASSED] drm_test_check_connector_changed_modeset
[12:23:06] ============== [PASSED] drm_validate_modeset ===============
[12:23:06] ====== drm_test_bridge_get_current_state (1 subtest) =======
[12:23:06] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[12:23:06] ======== [PASSED] drm_test_bridge_get_current_state ========
[12:23:06] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[12:23:06] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[12:23:06] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[12:23:06] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[12:23:06] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[12:23:06] ============== drm_bridge_alloc (2 subtests) ===============
[12:23:06] [PASSED] drm_test_drm_bridge_alloc_basic
[12:23:06] [PASSED] drm_test_drm_bridge_alloc_get_put
[12:23:06] ================ [PASSED] drm_bridge_alloc =================
[12:23:06] ============= drm_bridge_bus_fmt (5 subtests) ==============
[12:23:06] [PASSED] drm_test_bridge_rgb_yuv_rgb
[12:23:06] [PASSED] drm_test_bridge_must_convert_to_yuv444
[12:23:06] [PASSED] drm_test_bridge_hdmi_auto_rgb
[12:23:06] [PASSED] drm_test_bridge_auto_first
[12:23:06] [PASSED] drm_test_bridge_rgb_yuv_no_path
[12:23:06] =============== [PASSED] drm_bridge_bus_fmt ================
[12:23:06] ============= drm_cmdline_parser (40 subtests) =============
[12:23:06] [PASSED] drm_test_cmdline_force_d_only
[12:23:06] [PASSED] drm_test_cmdline_force_D_only_dvi
[12:23:06] [PASSED] drm_test_cmdline_force_D_only_hdmi
[12:23:06] [PASSED] drm_test_cmdline_force_D_only_not_digital
[12:23:06] [PASSED] drm_test_cmdline_force_e_only
[12:23:06] [PASSED] drm_test_cmdline_res
[12:23:06] [PASSED] drm_test_cmdline_res_vesa
[12:23:06] [PASSED] drm_test_cmdline_res_vesa_rblank
[12:23:06] [PASSED] drm_test_cmdline_res_rblank
[12:23:06] [PASSED] drm_test_cmdline_res_bpp
[12:23:06] [PASSED] drm_test_cmdline_res_refresh
[12:23:06] [PASSED] drm_test_cmdline_res_bpp_refresh
[12:23:06] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[12:23:06] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[12:23:06] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[12:23:06] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[12:23:06] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[12:23:06] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[12:23:06] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[12:23:06] [PASSED] drm_test_cmdline_res_margins_force_on
[12:23:06] [PASSED] drm_test_cmdline_res_vesa_margins
[12:23:06] [PASSED] drm_test_cmdline_name
[12:23:06] [PASSED] drm_test_cmdline_name_bpp
[12:23:06] [PASSED] drm_test_cmdline_name_option
[12:23:06] [PASSED] drm_test_cmdline_name_bpp_option
[12:23:06] [PASSED] drm_test_cmdline_rotate_0
[12:23:06] [PASSED] drm_test_cmdline_rotate_90
[12:23:06] [PASSED] drm_test_cmdline_rotate_180
[12:23:06] [PASSED] drm_test_cmdline_rotate_270
[12:23:06] [PASSED] drm_test_cmdline_hmirror
[12:23:06] [PASSED] drm_test_cmdline_vmirror
[12:23:06] [PASSED] drm_test_cmdline_margin_options
[12:23:06] [PASSED] drm_test_cmdline_multiple_options
[12:23:06] [PASSED] drm_test_cmdline_bpp_extra_and_option
[12:23:06] [PASSED] drm_test_cmdline_extra_and_option
[12:23:06] [PASSED] drm_test_cmdline_freestanding_options
[12:23:06] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[12:23:06] [PASSED] drm_test_cmdline_panel_orientation
[12:23:06] ================ drm_test_cmdline_invalid =================
[12:23:06] [PASSED] margin_only
[12:23:06] [PASSED] interlace_only
[12:23:06] [PASSED] res_missing_x
[12:23:06] [PASSED] res_missing_y
[12:23:06] [PASSED] res_bad_y
[12:23:06] [PASSED] res_missing_y_bpp
[12:23:06] [PASSED] res_bad_bpp
[12:23:06] [PASSED] res_bad_refresh
[12:23:06] [PASSED] res_bpp_refresh_force_on_off
[12:23:06] [PASSED] res_invalid_mode
[12:23:06] [PASSED] res_bpp_wrong_place_mode
[12:23:06] [PASSED] name_bpp_refresh
[12:23:06] [PASSED] name_refresh
[12:23:06] [PASSED] name_refresh_wrong_mode
[12:23:06] [PASSED] name_refresh_invalid_mode
[12:23:06] [PASSED] rotate_multiple
[12:23:06] [PASSED] rotate_invalid_val
[12:23:06] [PASSED] rotate_truncated
[12:23:06] [PASSED] invalid_option
[12:23:06] [PASSED] invalid_tv_option
[12:23:06] [PASSED] truncated_tv_option
[12:23:06] ============ [PASSED] drm_test_cmdline_invalid =============
[12:23:06] =============== drm_test_cmdline_tv_options ===============
[12:23:06] [PASSED] NTSC
[12:23:06] [PASSED] NTSC_443
[12:23:06] [PASSED] NTSC_J
[12:23:06] [PASSED] PAL
[12:23:06] [PASSED] PAL_M
[12:23:06] [PASSED] PAL_N
[12:23:06] [PASSED] SECAM
[12:23:06] [PASSED] MONO_525
[12:23:06] [PASSED] MONO_625
[12:23:06] =========== [PASSED] drm_test_cmdline_tv_options ===========
[12:23:06] =============== [PASSED] drm_cmdline_parser ================
[12:23:06] ========== drmm_connector_hdmi_init (20 subtests) ==========
[12:23:06] [PASSED] drm_test_connector_hdmi_init_valid
[12:23:06] [PASSED] drm_test_connector_hdmi_init_bpc_8
[12:23:06] [PASSED] drm_test_connector_hdmi_init_bpc_10
[12:23:06] [PASSED] drm_test_connector_hdmi_init_bpc_12
[12:23:06] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[12:23:06] [PASSED] drm_test_connector_hdmi_init_bpc_null
[12:23:06] [PASSED] drm_test_connector_hdmi_init_formats_empty
[12:23:06] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[12:23:06] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[12:23:06] [PASSED] supported_formats=0x9 yuv420_allowed=1
[12:23:06] [PASSED] supported_formats=0x9 yuv420_allowed=0
[12:23:06] [PASSED] supported_formats=0x5 yuv420_allowed=1
[12:23:06] [PASSED] supported_formats=0x5 yuv420_allowed=0
[12:23:06] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[12:23:06] [PASSED] drm_test_connector_hdmi_init_null_ddc
[12:23:06] [PASSED] drm_test_connector_hdmi_init_null_product
[12:23:06] [PASSED] drm_test_connector_hdmi_init_null_vendor
[12:23:06] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[12:23:06] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[12:23:06] [PASSED] drm_test_connector_hdmi_init_product_valid
[12:23:06] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[12:23:06] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[12:23:06] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[12:23:06] ========= drm_test_connector_hdmi_init_type_valid =========
[12:23:06] [PASSED] HDMI-A
[12:23:06] [PASSED] HDMI-B
[12:23:06] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[12:23:06] ======== drm_test_connector_hdmi_init_type_invalid ========
[12:23:06] [PASSED] Unknown
[12:23:06] [PASSED] VGA
[12:23:06] [PASSED] DVI-I
[12:23:06] [PASSED] DVI-D
[12:23:06] [PASSED] DVI-A
[12:23:06] [PASSED] Composite
[12:23:06] [PASSED] SVIDEO
[12:23:06] [PASSED] LVDS
[12:23:06] [PASSED] Component
[12:23:06] [PASSED] DIN
[12:23:06] [PASSED] DP
[12:23:06] [PASSED] TV
[12:23:06] [PASSED] eDP
[12:23:06] [PASSED] Virtual
[12:23:06] [PASSED] DSI
[12:23:06] [PASSED] DPI
[12:23:06] [PASSED] Writeback
[12:23:06] [PASSED] SPI
[12:23:06] [PASSED] USB
[12:23:06] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[12:23:06] ============ [PASSED] drmm_connector_hdmi_init =============
[12:23:06] ============= drmm_connector_init (3 subtests) =============
[12:23:06] [PASSED] drm_test_drmm_connector_init
[12:23:06] [PASSED] drm_test_drmm_connector_init_null_ddc
[12:23:06] ========= drm_test_drmm_connector_init_type_valid =========
[12:23:06] [PASSED] Unknown
[12:23:06] [PASSED] VGA
[12:23:06] [PASSED] DVI-I
[12:23:06] [PASSED] DVI-D
[12:23:06] [PASSED] DVI-A
[12:23:06] [PASSED] Composite
[12:23:06] [PASSED] SVIDEO
[12:23:06] [PASSED] LVDS
[12:23:06] [PASSED] Component
[12:23:06] [PASSED] DIN
[12:23:06] [PASSED] DP
[12:23:06] [PASSED] HDMI-A
[12:23:06] [PASSED] HDMI-B
[12:23:06] [PASSED] TV
[12:23:06] [PASSED] eDP
[12:23:06] [PASSED] Virtual
[12:23:06] [PASSED] DSI
[12:23:06] [PASSED] DPI
[12:23:06] [PASSED] Writeback
[12:23:06] [PASSED] SPI
[12:23:06] [PASSED] USB
[12:23:06] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[12:23:06] =============== [PASSED] drmm_connector_init ===============
[12:23:06] ========= drm_connector_dynamic_init (6 subtests) ==========
[12:23:06] [PASSED] drm_test_drm_connector_dynamic_init
[12:23:06] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[12:23:06] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[12:23:06] [PASSED] drm_test_drm_connector_dynamic_init_properties
[12:23:06] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[12:23:06] [PASSED] Unknown
[12:23:06] [PASSED] VGA
[12:23:06] [PASSED] DVI-I
[12:23:06] [PASSED] DVI-D
[12:23:06] [PASSED] DVI-A
[12:23:06] [PASSED] Composite
[12:23:06] [PASSED] SVIDEO
[12:23:06] [PASSED] LVDS
[12:23:06] [PASSED] Component
[12:23:06] [PASSED] DIN
[12:23:06] [PASSED] DP
[12:23:06] [PASSED] HDMI-A
[12:23:06] [PASSED] HDMI-B
[12:23:06] [PASSED] TV
[12:23:06] [PASSED] eDP
[12:23:06] [PASSED] Virtual
[12:23:06] [PASSED] DSI
[12:23:06] [PASSED] DPI
[12:23:06] [PASSED] Writeback
[12:23:06] [PASSED] SPI
[12:23:06] [PASSED] USB
[12:23:06] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[12:23:06] ======== drm_test_drm_connector_dynamic_init_name =========
[12:23:06] [PASSED] Unknown
[12:23:06] [PASSED] VGA
[12:23:06] [PASSED] DVI-I
[12:23:06] [PASSED] DVI-D
[12:23:06] [PASSED] DVI-A
[12:23:06] [PASSED] Composite
[12:23:06] [PASSED] SVIDEO
[12:23:06] [PASSED] LVDS
[12:23:06] [PASSED] Component
[12:23:06] [PASSED] DIN
[12:23:06] [PASSED] DP
[12:23:06] [PASSED] HDMI-A
[12:23:06] [PASSED] HDMI-B
[12:23:06] [PASSED] TV
[12:23:06] [PASSED] eDP
[12:23:06] [PASSED] Virtual
[12:23:06] [PASSED] DSI
[12:23:06] [PASSED] DPI
[12:23:06] [PASSED] Writeback
[12:23:06] [PASSED] SPI
[12:23:06] [PASSED] USB
[12:23:06] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[12:23:06] =========== [PASSED] drm_connector_dynamic_init ============
[12:23:06] ==== drm_connector_dynamic_register_early (4 subtests) =====
[12:23:06] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[12:23:06] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[12:23:06] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[12:23:06] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[12:23:06] ====== [PASSED] drm_connector_dynamic_register_early =======
[12:23:06] ======= drm_connector_dynamic_register (7 subtests) ========
[12:23:06] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[12:23:06] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[12:23:06] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[12:23:06] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[12:23:06] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[12:23:06] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[12:23:06] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[12:23:06] ========= [PASSED] drm_connector_dynamic_register ==========
[12:23:06] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[12:23:06] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[12:23:06] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[12:23:06] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[12:23:06] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[12:23:06] ========== drm_test_get_tv_mode_from_name_valid ===========
[12:23:06] [PASSED] NTSC
[12:23:06] [PASSED] NTSC-443
[12:23:06] [PASSED] NTSC-J
[12:23:06] [PASSED] PAL
[12:23:06] [PASSED] PAL-M
[12:23:06] [PASSED] PAL-N
[12:23:06] [PASSED] SECAM
[12:23:06] [PASSED] Mono
[12:23:06] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[12:23:06] [PASSED] drm_test_get_tv_mode_from_name_truncated
[12:23:06] ============ [PASSED] drm_get_tv_mode_from_name ============
[12:23:06] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[12:23:06] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[12:23:06] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[12:23:06] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[12:23:06] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[12:23:06] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[12:23:06] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[12:23:06] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[12:23:06] [PASSED] VIC 96
[12:23:06] [PASSED] VIC 97
[12:23:06] [PASSED] VIC 101
[12:23:06] [PASSED] VIC 102
[12:23:06] [PASSED] VIC 106
[12:23:06] [PASSED] VIC 107
[12:23:06] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[12:23:06] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[12:23:06] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[12:23:06] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[12:23:06] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[12:23:06] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[12:23:06] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[12:23:06] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[12:23:06] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[12:23:06] [PASSED] Automatic
[12:23:06] [PASSED] Full
[12:23:06] [PASSED] Limited 16:235
[12:23:06] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[12:23:06] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[12:23:06] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[12:23:06] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[12:23:06] === drm_test_drm_hdmi_connector_get_output_format_name ====
[12:23:06] [PASSED] RGB
[12:23:06] [PASSED] YUV 4:2:0
[12:23:06] [PASSED] YUV 4:2:2
[12:23:06] [PASSED] YUV 4:4:4
[12:23:06] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[12:23:06] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[12:23:06] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[12:23:06] ============= drm_damage_helper (21 subtests) ==============
[12:23:06] [PASSED] drm_test_damage_iter_no_damage
[12:23:06] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[12:23:06] [PASSED] drm_test_damage_iter_no_damage_src_moved
[12:23:06] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[12:23:06] [PASSED] drm_test_damage_iter_no_damage_not_visible
[12:23:06] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[12:23:06] [PASSED] drm_test_damage_iter_no_damage_no_fb
[12:23:06] [PASSED] drm_test_damage_iter_simple_damage
[12:23:06] [PASSED] drm_test_damage_iter_single_damage
[12:23:06] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[12:23:06] [PASSED] drm_test_damage_iter_single_damage_outside_src
[12:23:06] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[12:23:06] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[12:23:06] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[12:23:06] [PASSED] drm_test_damage_iter_single_damage_src_moved
[12:23:06] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[12:23:06] [PASSED] drm_test_damage_iter_damage
[12:23:06] [PASSED] drm_test_damage_iter_damage_one_intersect
[12:23:06] [PASSED] drm_test_damage_iter_damage_one_outside
[12:23:06] [PASSED] drm_test_damage_iter_damage_src_moved
[12:23:06] [PASSED] drm_test_damage_iter_damage_not_visible
[12:23:06] ================ [PASSED] drm_damage_helper ================
[12:23:06] ============== drm_dp_mst_helper (3 subtests) ==============
[12:23:06] ============== drm_test_dp_mst_calc_pbn_mode ==============
[12:23:06] [PASSED] Clock 154000 BPP 30 DSC disabled
[12:23:06] [PASSED] Clock 234000 BPP 30 DSC disabled
[12:23:06] [PASSED] Clock 297000 BPP 24 DSC disabled
[12:23:06] [PASSED] Clock 332880 BPP 24 DSC enabled
[12:23:06] [PASSED] Clock 324540 BPP 24 DSC enabled
[12:23:06] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[12:23:06] ============== drm_test_dp_mst_calc_pbn_div ===============
[12:23:06] [PASSED] Link rate 2000000 lane count 4
[12:23:06] [PASSED] Link rate 2000000 lane count 2
[12:23:06] [PASSED] Link rate 2000000 lane count 1
[12:23:06] [PASSED] Link rate 1350000 lane count 4
[12:23:06] [PASSED] Link rate 1350000 lane count 2
[12:23:06] [PASSED] Link rate 1350000 lane count 1
[12:23:06] [PASSED] Link rate 1000000 lane count 4
[12:23:06] [PASSED] Link rate 1000000 lane count 2
[12:23:06] [PASSED] Link rate 1000000 lane count 1
[12:23:06] [PASSED] Link rate 810000 lane count 4
[12:23:06] [PASSED] Link rate 810000 lane count 2
[12:23:06] [PASSED] Link rate 810000 lane count 1
[12:23:06] [PASSED] Link rate 540000 lane count 4
[12:23:06] [PASSED] Link rate 540000 lane count 2
[12:23:06] [PASSED] Link rate 540000 lane count 1
[12:23:06] [PASSED] Link rate 270000 lane count 4
[12:23:06] [PASSED] Link rate 270000 lane count 2
[12:23:06] [PASSED] Link rate 270000 lane count 1
[12:23:06] [PASSED] Link rate 162000 lane count 4
[12:23:06] [PASSED] Link rate 162000 lane count 2
[12:23:06] [PASSED] Link rate 162000 lane count 1
[12:23:06] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[12:23:06] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[12:23:06] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[12:23:06] [PASSED] DP_POWER_UP_PHY with port number
[12:23:06] [PASSED] DP_POWER_DOWN_PHY with port number
[12:23:06] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[12:23:06] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[12:23:06] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[12:23:06] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[12:23:06] [PASSED] DP_QUERY_PAYLOAD with port number
[12:23:06] [PASSED] DP_QUERY_PAYLOAD with VCPI
[12:23:06] [PASSED] DP_REMOTE_DPCD_READ with port number
[12:23:06] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[12:23:06] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[12:23:06] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[12:23:06] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[12:23:06] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[12:23:06] [PASSED] DP_REMOTE_I2C_READ with port number
[12:23:06] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[12:23:06] [PASSED] DP_REMOTE_I2C_READ with transactions array
[12:23:06] [PASSED] DP_REMOTE_I2C_WRITE with port number
[12:23:06] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[12:23:06] [PASSED] DP_REMOTE_I2C_WRITE with data array
[12:23:06] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[12:23:06] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[12:23:06] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[12:23:06] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[12:23:06] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[12:23:06] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[12:23:06] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[12:23:06] ================ [PASSED] drm_dp_mst_helper ================
[12:23:06] ================== drm_exec (7 subtests) ===================
[12:23:06] [PASSED] sanitycheck
[12:23:06] [PASSED] test_lock
[12:23:06] [PASSED] test_lock_unlock
[12:23:06] [PASSED] test_duplicates
[12:23:06] [PASSED] test_prepare
[12:23:06] [PASSED] test_prepare_array
[12:23:06] [PASSED] test_multiple_loops
[12:23:06] ==================== [PASSED] drm_exec =====================
[12:23:06] =========== drm_format_helper_test (17 subtests) ===========
[12:23:06] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[12:23:06] [PASSED] single_pixel_source_buffer
[12:23:06] [PASSED] single_pixel_clip_rectangle
[12:23:06] [PASSED] well_known_colors
[12:23:06] [PASSED] destination_pitch
[12:23:06] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[12:23:06] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[12:23:06] [PASSED] single_pixel_source_buffer
[12:23:06] [PASSED] single_pixel_clip_rectangle
[12:23:06] [PASSED] well_known_colors
[12:23:06] [PASSED] destination_pitch
[12:23:06] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[12:23:06] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[12:23:06] [PASSED] single_pixel_source_buffer
[12:23:06] [PASSED] single_pixel_clip_rectangle
[12:23:06] [PASSED] well_known_colors
[12:23:06] [PASSED] destination_pitch
[12:23:06] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[12:23:06] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[12:23:06] [PASSED] single_pixel_source_buffer
[12:23:06] [PASSED] single_pixel_clip_rectangle
[12:23:06] [PASSED] well_known_colors
[12:23:06] [PASSED] destination_pitch
[12:23:06] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[12:23:06] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[12:23:06] [PASSED] single_pixel_source_buffer
[12:23:06] [PASSED] single_pixel_clip_rectangle
[12:23:06] [PASSED] well_known_colors
[12:23:06] [PASSED] destination_pitch
[12:23:06] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[12:23:06] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[12:23:06] [PASSED] single_pixel_source_buffer
[12:23:06] [PASSED] single_pixel_clip_rectangle
[12:23:06] [PASSED] well_known_colors
[12:23:06] [PASSED] destination_pitch
[12:23:06] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[12:23:06] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[12:23:06] [PASSED] single_pixel_source_buffer
[12:23:06] [PASSED] single_pixel_clip_rectangle
[12:23:06] [PASSED] well_known_colors
[12:23:06] [PASSED] destination_pitch
[12:23:06] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[12:23:06] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[12:23:06] [PASSED] single_pixel_source_buffer
[12:23:06] [PASSED] single_pixel_clip_rectangle
[12:23:06] [PASSED] well_known_colors
[12:23:06] [PASSED] destination_pitch
[12:23:06] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[12:23:06] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[12:23:06] [PASSED] single_pixel_source_buffer
[12:23:06] [PASSED] single_pixel_clip_rectangle
[12:23:06] [PASSED] well_known_colors
[12:23:06] [PASSED] destination_pitch
[12:23:06] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[12:23:06] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[12:23:06] [PASSED] single_pixel_source_buffer
[12:23:06] [PASSED] single_pixel_clip_rectangle
[12:23:06] [PASSED] well_known_colors
[12:23:06] [PASSED] destination_pitch
[12:23:06] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[12:23:06] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[12:23:06] [PASSED] single_pixel_source_buffer
[12:23:06] [PASSED] single_pixel_clip_rectangle
[12:23:06] [PASSED] well_known_colors
[12:23:06] [PASSED] destination_pitch
[12:23:06] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[12:23:06] ============== drm_test_fb_xrgb8888_to_mono ===============
[12:23:06] [PASSED] single_pixel_source_buffer
[12:23:06] [PASSED] single_pixel_clip_rectangle
[12:23:06] [PASSED] well_known_colors
[12:23:06] [PASSED] destination_pitch
[12:23:06] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[12:23:06] ==================== drm_test_fb_swab =====================
[12:23:06] [PASSED] single_pixel_source_buffer
[12:23:06] [PASSED] single_pixel_clip_rectangle
[12:23:06] [PASSED] well_known_colors
[12:23:06] [PASSED] destination_pitch
[12:23:06] ================ [PASSED] drm_test_fb_swab =================
[12:23:06] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[12:23:06] [PASSED] single_pixel_source_buffer
[12:23:06] [PASSED] single_pixel_clip_rectangle
[12:23:06] [PASSED] well_known_colors
[12:23:06] [PASSED] destination_pitch
[12:23:06] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[12:23:06] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[12:23:06] [PASSED] single_pixel_source_buffer
[12:23:06] [PASSED] single_pixel_clip_rectangle
[12:23:06] [PASSED] well_known_colors
[12:23:06] [PASSED] destination_pitch
[12:23:06] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[12:23:06] ================= drm_test_fb_clip_offset =================
[12:23:06] [PASSED] pass through
[12:23:06] [PASSED] horizontal offset
[12:23:06] [PASSED] vertical offset
[12:23:06] [PASSED] horizontal and vertical offset
[12:23:06] [PASSED] horizontal offset (custom pitch)
[12:23:06] [PASSED] vertical offset (custom pitch)
[12:23:06] [PASSED] horizontal and vertical offset (custom pitch)
[12:23:06] ============= [PASSED] drm_test_fb_clip_offset =============
[12:23:06] =================== drm_test_fb_memcpy ====================
[12:23:06] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[12:23:06] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[12:23:06] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[12:23:06] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[12:23:06] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[12:23:06] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[12:23:06] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[12:23:06] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[12:23:06] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[12:23:06] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[12:23:06] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[12:23:06] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[12:23:06] =============== [PASSED] drm_test_fb_memcpy ================
[12:23:06] ============= [PASSED] drm_format_helper_test ==============
[12:23:06] ================= drm_format (18 subtests) =================
[12:23:06] [PASSED] drm_test_format_block_width_invalid
[12:23:06] [PASSED] drm_test_format_block_width_one_plane
[12:23:06] [PASSED] drm_test_format_block_width_two_plane
[12:23:06] [PASSED] drm_test_format_block_width_three_plane
[12:23:06] [PASSED] drm_test_format_block_width_tiled
[12:23:06] [PASSED] drm_test_format_block_height_invalid
[12:23:06] [PASSED] drm_test_format_block_height_one_plane
[12:23:06] [PASSED] drm_test_format_block_height_two_plane
[12:23:06] [PASSED] drm_test_format_block_height_three_plane
[12:23:06] [PASSED] drm_test_format_block_height_tiled
[12:23:06] [PASSED] drm_test_format_min_pitch_invalid
[12:23:06] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[12:23:06] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[12:23:06] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[12:23:06] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[12:23:06] [PASSED] drm_test_format_min_pitch_two_plane
[12:23:06] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[12:23:06] [PASSED] drm_test_format_min_pitch_tiled
[12:23:06] =================== [PASSED] drm_format ====================
[12:23:06] ============== drm_framebuffer (10 subtests) ===============
[12:23:06] ========== drm_test_framebuffer_check_src_coords ==========
[12:23:06] [PASSED] Success: source fits into fb
[12:23:06] [PASSED] Fail: overflowing fb with x-axis coordinate
[12:23:06] [PASSED] Fail: overflowing fb with y-axis coordinate
[12:23:06] [PASSED] Fail: overflowing fb with source width
[12:23:06] [PASSED] Fail: overflowing fb with source height
[12:23:06] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[12:23:06] [PASSED] drm_test_framebuffer_cleanup
[12:23:06] =============== drm_test_framebuffer_create ===============
[12:23:06] [PASSED] ABGR8888 normal sizes
[12:23:06] [PASSED] ABGR8888 max sizes
[12:23:06] [PASSED] ABGR8888 pitch greater than min required
[12:23:06] [PASSED] ABGR8888 pitch less than min required
[12:23:06] [PASSED] ABGR8888 Invalid width
[12:23:06] [PASSED] ABGR8888 Invalid buffer handle
[12:23:06] [PASSED] No pixel format
[12:23:06] [PASSED] ABGR8888 Width 0
[12:23:06] [PASSED] ABGR8888 Height 0
[12:23:06] [PASSED] ABGR8888 Out of bound height * pitch combination
[12:23:06] [PASSED] ABGR8888 Large buffer offset
[12:23:06] [PASSED] ABGR8888 Buffer offset for inexistent plane
[12:23:06] [PASSED] ABGR8888 Invalid flag
[12:23:06] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[12:23:06] [PASSED] ABGR8888 Valid buffer modifier
[12:23:06] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[12:23:06] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[12:23:06] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[12:23:06] [PASSED] NV12 Normal sizes
[12:23:06] [PASSED] NV12 Max sizes
[12:23:06] [PASSED] NV12 Invalid pitch
[12:23:06] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[12:23:06] [PASSED] NV12 different modifier per-plane
[12:23:06] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[12:23:06] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[12:23:06] [PASSED] NV12 Modifier for inexistent plane
[12:23:06] [PASSED] NV12 Handle for inexistent plane
[12:23:06] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[12:23:06] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[12:23:06] [PASSED] YVU420 Normal sizes
[12:23:06] [PASSED] YVU420 Max sizes
[12:23:06] [PASSED] YVU420 Invalid pitch
[12:23:06] [PASSED] YVU420 Different pitches
[12:23:06] [PASSED] YVU420 Different buffer offsets/pitches
[12:23:06] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[12:23:06] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[12:23:06] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[12:23:06] [PASSED] YVU420 Valid modifier
[12:23:06] [PASSED] YVU420 Different modifiers per plane
[12:23:06] [PASSED] YVU420 Modifier for inexistent plane
[12:23:06] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[12:23:06] [PASSED] X0L2 Normal sizes
[12:23:06] [PASSED] X0L2 Max sizes
[12:23:06] [PASSED] X0L2 Invalid pitch
[12:23:06] [PASSED] X0L2 Pitch greater than minimum required
[12:23:06] [PASSED] X0L2 Handle for inexistent plane
[12:23:06] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[12:23:06] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[12:23:06] [PASSED] X0L2 Valid modifier
[12:23:06] [PASSED] X0L2 Modifier for inexistent plane
[12:23:06] =========== [PASSED] drm_test_framebuffer_create ===========
[12:23:06] [PASSED] drm_test_framebuffer_free
[12:23:06] [PASSED] drm_test_framebuffer_init
[12:23:06] [PASSED] drm_test_framebuffer_init_bad_format
[12:23:06] [PASSED] drm_test_framebuffer_init_dev_mismatch
[12:23:06] [PASSED] drm_test_framebuffer_lookup
[12:23:06] [PASSED] drm_test_framebuffer_lookup_inexistent
[12:23:06] [PASSED] drm_test_framebuffer_modifiers_not_supported
[12:23:06] ================= [PASSED] drm_framebuffer =================
[12:23:06] ================ drm_gem_shmem (8 subtests) ================
[12:23:06] [PASSED] drm_gem_shmem_test_obj_create
[12:23:06] [PASSED] drm_gem_shmem_test_obj_create_private
[12:23:06] [PASSED] drm_gem_shmem_test_pin_pages
[12:23:06] [PASSED] drm_gem_shmem_test_vmap
[12:23:06] [PASSED] drm_gem_shmem_test_get_sg_table
[12:23:06] [PASSED] drm_gem_shmem_test_get_pages_sgt
[12:23:06] [PASSED] drm_gem_shmem_test_madvise
[12:23:06] [PASSED] drm_gem_shmem_test_purge
[12:23:06] ================== [PASSED] drm_gem_shmem ==================
[12:23:06] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[12:23:06] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[12:23:06] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[12:23:06] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[12:23:06] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[12:23:06] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[12:23:06] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[12:23:06] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[12:23:06] [PASSED] Automatic
[12:23:06] [PASSED] Full
[12:23:06] [PASSED] Limited 16:235
[12:23:06] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[12:23:06] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[12:23:06] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[12:23:06] [PASSED] drm_test_check_disable_connector
[12:23:06] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[12:23:06] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[12:23:06] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[12:23:06] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[12:23:06] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[12:23:06] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[12:23:06] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[12:23:06] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[12:23:06] [PASSED] drm_test_check_output_bpc_dvi
[12:23:06] [PASSED] drm_test_check_output_bpc_format_vic_1
[12:23:06] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[12:23:06] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[12:23:06] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[12:23:06] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[12:23:06] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[12:23:06] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[12:23:06] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[12:23:06] ============ drm_test_check_hdmi_color_format =============
[12:23:06] [PASSED] AUTO -> RGB
[12:23:06] [PASSED] YCBCR422 -> YUV422
[12:23:06] [PASSED] YCBCR420 -> YUV420
[12:23:06] [PASSED] YCBCR444 -> YUV444
[12:23:06] [PASSED] RGB -> RGB
[12:23:06] ======== [PASSED] drm_test_check_hdmi_color_format =========
[12:23:06] ======== drm_test_check_hdmi_color_format_420_only ========
[12:23:06] [PASSED] RGB should fail
[12:23:06] [PASSED] YUV444 should fail
[12:23:06] [PASSED] YUV422 should fail
[12:23:06] [PASSED] YUV420 should work
[12:23:06] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[12:23:06] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[12:23:06] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[12:23:06] [PASSED] drm_test_check_broadcast_rgb_value
[12:23:06] [PASSED] drm_test_check_bpc_8_value
[12:23:06] [PASSED] drm_test_check_bpc_10_value
[12:23:06] [PASSED] drm_test_check_bpc_12_value
[12:23:06] [PASSED] drm_test_check_format_value
[12:23:06] [PASSED] drm_test_check_tmds_char_value
[12:23:06] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[12:23:06] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[12:23:06] [PASSED] drm_test_check_mode_valid
[12:23:06] [PASSED] drm_test_check_mode_valid_reject
[12:23:06] [PASSED] drm_test_check_mode_valid_reject_rate
[12:23:06] [PASSED] drm_test_check_mode_valid_reject_max_clock
[12:23:06] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[12:23:06] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[12:23:06] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[12:23:06] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[12:23:06] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[12:23:06] [PASSED] drm_test_check_infoframes
[12:23:06] [PASSED] drm_test_check_reject_avi_infoframe
[12:23:06] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[12:23:06] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[12:23:06] [PASSED] drm_test_check_reject_audio_infoframe
[12:23:06] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[12:23:06] ================= drm_managed (2 subtests) =================
[12:23:06] [PASSED] drm_test_managed_release_action
[12:23:06] [PASSED] drm_test_managed_run_action
[12:23:06] =================== [PASSED] drm_managed ===================
[12:23:06] =================== drm_mm (6 subtests) ====================
[12:23:06] [PASSED] drm_test_mm_init
[12:23:06] [PASSED] drm_test_mm_debug
[12:23:06] [PASSED] drm_test_mm_align32
[12:23:06] [PASSED] drm_test_mm_align64
[12:23:06] [PASSED] drm_test_mm_lowest
[12:23:06] [PASSED] drm_test_mm_highest
[12:23:06] ===================== [PASSED] drm_mm ======================
[12:23:06] ============= drm_modes_analog_tv (5 subtests) =============
[12:23:06] [PASSED] drm_test_modes_analog_tv_mono_576i
[12:23:06] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[12:23:06] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[12:23:06] [PASSED] drm_test_modes_analog_tv_pal_576i
[12:23:06] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[12:23:06] =============== [PASSED] drm_modes_analog_tv ===============
[12:23:06] ============== drm_plane_helper (2 subtests) ===============
[12:23:06] =============== drm_test_check_plane_state ================
[12:23:06] [PASSED] clipping_simple
[12:23:06] [PASSED] clipping_rotate_reflect
[12:23:06] [PASSED] positioning_simple
[12:23:06] [PASSED] upscaling
[12:23:06] [PASSED] downscaling
[12:23:06] [PASSED] rounding1
[12:23:06] [PASSED] rounding2
[12:23:06] [PASSED] rounding3
[12:23:06] [PASSED] rounding4
[12:23:06] =========== [PASSED] drm_test_check_plane_state ============
[12:23:06] =========== drm_test_check_invalid_plane_state ============
[12:23:06] [PASSED] positioning_invalid
[12:23:06] [PASSED] upscaling_invalid
[12:23:06] [PASSED] downscaling_invalid
[12:23:06] ======= [PASSED] drm_test_check_invalid_plane_state ========
[12:23:06] ================ [PASSED] drm_plane_helper =================
[12:23:06] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[12:23:06] ====== drm_test_connector_helper_tv_get_modes_check =======
[12:23:06] [PASSED] None
[12:23:06] [PASSED] PAL
[12:23:06] [PASSED] NTSC
[12:23:06] [PASSED] Both, NTSC Default
[12:23:06] [PASSED] Both, PAL Default
[12:23:06] [PASSED] Both, NTSC Default, with PAL on command-line
[12:23:06] [PASSED] Both, PAL Default, with NTSC on command-line
[12:23:06] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[12:23:06] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[12:23:06] ================== drm_rect (9 subtests) ===================
[12:23:06] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[12:23:06] [PASSED] drm_test_rect_clip_scaled_not_clipped
[12:23:06] [PASSED] drm_test_rect_clip_scaled_clipped
[12:23:06] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[12:23:06] ================= drm_test_rect_intersect =================
[12:23:06] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[12:23:06] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[12:23:06] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[12:23:06] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[12:23:06] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[12:23:06] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[12:23:06] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[12:23:06] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[12:23:06] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[12:23:06] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[12:23:06] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[12:23:06] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[12:23:06] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[12:23:06] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[12:23:06] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[12:23:06] ============= [PASSED] drm_test_rect_intersect =============
[12:23:06] ================ drm_test_rect_calc_hscale ================
[12:23:06] [PASSED] normal use
[12:23:06] [PASSED] out of max range
[12:23:06] [PASSED] out of min range
[12:23:06] [PASSED] zero dst
[12:23:06] [PASSED] negative src
[12:23:06] [PASSED] negative dst
[12:23:06] ============ [PASSED] drm_test_rect_calc_hscale ============
[12:23:06] ================ drm_test_rect_calc_vscale ================
[12:23:06] [PASSED] normal use
[12:23:06] [PASSED] out of max range
[12:23:06] [PASSED] out of min range
[12:23:06] [PASSED] zero dst
[12:23:06] [PASSED] negative src
[12:23:06] [PASSED] negative dst
[12:23:06] ============ [PASSED] drm_test_rect_calc_vscale ============
[12:23:06] ================== drm_test_rect_rotate ===================
[12:23:06] [PASSED] reflect-x
[12:23:06] [PASSED] reflect-y
[12:23:06] [PASSED] rotate-0
[12:23:06] [PASSED] rotate-90
[12:23:06] [PASSED] rotate-180
[12:23:06] [PASSED] rotate-270
[12:23:06] ============== [PASSED] drm_test_rect_rotate ===============
[12:23:06] ================ drm_test_rect_rotate_inv =================
[12:23:06] [PASSED] reflect-x
[12:23:06] [PASSED] reflect-y
[12:23:06] [PASSED] rotate-0
[12:23:06] [PASSED] rotate-90
[12:23:06] [PASSED] rotate-180
[12:23:06] [PASSED] rotate-270
[12:23:06] ============ [PASSED] drm_test_rect_rotate_inv =============
[12:23:06] ==================== [PASSED] drm_rect =====================
[12:23:06] ============ drm_sysfb_modeset_test (1 subtest) ============
[12:23:06] ============ drm_test_sysfb_build_fourcc_list =============
[12:23:06] [PASSED] no native formats
[12:23:06] [PASSED] XRGB8888 as native format
[12:23:06] [PASSED] remove duplicates
[12:23:06] [PASSED] convert alpha formats
[12:23:06] [PASSED] random formats
[12:23:06] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[12:23:06] ============= [PASSED] drm_sysfb_modeset_test ==============
[12:23:06] ================== drm_fixp (2 subtests) ===================
[12:23:06] [PASSED] drm_test_int2fixp
[12:23:06] [PASSED] drm_test_sm2fixp
[12:23:06] ==================== [PASSED] drm_fixp =====================
[12:23:06] ============================================================
[12:23:06] Testing complete. Ran 637 tests: passed: 637
[12:23:06] Elapsed time: 26.572s total, 1.826s configuring, 24.576s building, 0.151s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[12:23:06] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[12:23:08] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[12:23:18] Starting KUnit Kernel (1/1)...
[12:23:18] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[12:23:18] ================= ttm_device (5 subtests) ==================
[12:23:18] [PASSED] ttm_device_init_basic
[12:23:18] [PASSED] ttm_device_init_multiple
[12:23:18] [PASSED] ttm_device_fini_basic
[12:23:18] [PASSED] ttm_device_init_no_vma_man
[12:23:18] ================== ttm_device_init_pools ==================
[12:23:18] [PASSED] No DMA allocations, no DMA32 required
[12:23:18] [PASSED] DMA allocations, DMA32 required
[12:23:18] [PASSED] No DMA allocations, DMA32 required
[12:23:18] [PASSED] DMA allocations, no DMA32 required
[12:23:18] ============== [PASSED] ttm_device_init_pools ==============
[12:23:18] =================== [PASSED] ttm_device ====================
[12:23:18] ================== ttm_pool (8 subtests) ===================
[12:23:18] ================== ttm_pool_alloc_basic ===================
[12:23:18] [PASSED] One page
[12:23:18] [PASSED] More than one page
[12:23:18] [PASSED] Above the allocation limit
[12:23:18] [PASSED] One page, with coherent DMA mappings enabled
[12:23:18] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[12:23:18] ============== [PASSED] ttm_pool_alloc_basic ===============
[12:23:18] ============== ttm_pool_alloc_basic_dma_addr ==============
[12:23:18] [PASSED] One page
[12:23:18] [PASSED] More than one page
[12:23:18] [PASSED] Above the allocation limit
[12:23:18] [PASSED] One page, with coherent DMA mappings enabled
[12:23:18] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[12:23:18] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[12:23:18] [PASSED] ttm_pool_alloc_order_caching_match
[12:23:18] [PASSED] ttm_pool_alloc_caching_mismatch
[12:23:18] [PASSED] ttm_pool_alloc_order_mismatch
[12:23:18] [PASSED] ttm_pool_free_dma_alloc
[12:23:18] [PASSED] ttm_pool_free_no_dma_alloc
[12:23:18] [PASSED] ttm_pool_fini_basic
[12:23:18] ==================== [PASSED] ttm_pool =====================
[12:23:18] ================ ttm_resource (8 subtests) =================
[12:23:18] ================= ttm_resource_init_basic =================
[12:23:18] [PASSED] Init resource in TTM_PL_SYSTEM
[12:23:18] [PASSED] Init resource in TTM_PL_VRAM
[12:23:18] [PASSED] Init resource in a private placement
[12:23:18] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[12:23:18] ============= [PASSED] ttm_resource_init_basic =============
[12:23:18] [PASSED] ttm_resource_init_pinned
[12:23:18] [PASSED] ttm_resource_fini_basic
[12:23:18] [PASSED] ttm_resource_manager_init_basic
[12:23:18] [PASSED] ttm_resource_manager_usage_basic
[12:23:18] [PASSED] ttm_resource_manager_set_used_basic
[12:23:18] [PASSED] ttm_sys_man_alloc_basic
[12:23:18] [PASSED] ttm_sys_man_free_basic
[12:23:18] ================== [PASSED] ttm_resource ===================
[12:23:18] =================== ttm_tt (15 subtests) ===================
[12:23:18] ==================== ttm_tt_init_basic ====================
[12:23:18] [PASSED] Page-aligned size
[12:23:18] [PASSED] Extra pages requested
[12:23:18] ================ [PASSED] ttm_tt_init_basic ================
[12:23:18] [PASSED] ttm_tt_init_misaligned
[12:23:18] [PASSED] ttm_tt_fini_basic
[12:23:18] [PASSED] ttm_tt_fini_sg
[12:23:18] [PASSED] ttm_tt_fini_shmem
[12:23:18] [PASSED] ttm_tt_create_basic
[12:23:18] [PASSED] ttm_tt_create_invalid_bo_type
[12:23:18] [PASSED] ttm_tt_create_ttm_exists
[12:23:18] [PASSED] ttm_tt_create_failed
[12:23:18] [PASSED] ttm_tt_destroy_basic
[12:23:18] [PASSED] ttm_tt_populate_null_ttm
[12:23:18] [PASSED] ttm_tt_populate_populated_ttm
[12:23:18] [PASSED] ttm_tt_unpopulate_basic
[12:23:18] [PASSED] ttm_tt_unpopulate_empty_ttm
[12:23:18] [PASSED] ttm_tt_swapin_basic
[12:23:18] ===================== [PASSED] ttm_tt ======================
[12:23:18] =================== ttm_bo (14 subtests) ===================
[12:23:18] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[12:23:18] [PASSED] Cannot be interrupted and sleeps
[12:23:18] [PASSED] Cannot be interrupted, locks straight away
[12:23:18] [PASSED] Can be interrupted, sleeps
[12:23:18] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[12:23:18] [PASSED] ttm_bo_reserve_locked_no_sleep
[12:23:18] [PASSED] ttm_bo_reserve_no_wait_ticket
[12:23:18] [PASSED] ttm_bo_reserve_double_resv
[12:23:18] [PASSED] ttm_bo_reserve_interrupted
[12:23:18] [PASSED] ttm_bo_reserve_deadlock
[12:23:18] [PASSED] ttm_bo_unreserve_basic
[12:23:18] [PASSED] ttm_bo_unreserve_pinned
[12:23:18] [PASSED] ttm_bo_unreserve_bulk
[12:23:18] [PASSED] ttm_bo_fini_basic
[12:23:18] [PASSED] ttm_bo_fini_shared_resv
[12:23:18] [PASSED] ttm_bo_pin_basic
[12:23:18] [PASSED] ttm_bo_pin_unpin_resource
[12:23:18] [PASSED] ttm_bo_multiple_pin_one_unpin
[12:23:18] ===================== [PASSED] ttm_bo ======================
[12:23:18] ============== ttm_bo_validate (22 subtests) ===============
[12:23:18] ============== ttm_bo_init_reserved_sys_man ===============
[12:23:18] [PASSED] Buffer object for userspace
[12:23:18] [PASSED] Kernel buffer object
[12:23:18] [PASSED] Shared buffer object
[12:23:18] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[12:23:18] ============== ttm_bo_init_reserved_mock_man ==============
[12:23:18] [PASSED] Buffer object for userspace
[12:23:18] [PASSED] Kernel buffer object
[12:23:18] [PASSED] Shared buffer object
[12:23:18] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[12:23:18] [PASSED] ttm_bo_init_reserved_resv
[12:23:18] ================== ttm_bo_validate_basic ==================
[12:23:18] [PASSED] Buffer object for userspace
[12:23:18] [PASSED] Kernel buffer object
[12:23:18] [PASSED] Shared buffer object
[12:23:18] ============== [PASSED] ttm_bo_validate_basic ==============
[12:23:18] [PASSED] ttm_bo_validate_invalid_placement
[12:23:18] ============= ttm_bo_validate_same_placement ==============
[12:23:18] [PASSED] System manager
[12:23:18] [PASSED] VRAM manager
[12:23:18] ========= [PASSED] ttm_bo_validate_same_placement ==========
[12:23:18] [PASSED] ttm_bo_validate_failed_alloc
[12:23:18] [PASSED] ttm_bo_validate_pinned
[12:23:18] [PASSED] ttm_bo_validate_busy_placement
[12:23:18] ================ ttm_bo_validate_multihop =================
[12:23:18] [PASSED] Buffer object for userspace
[12:23:18] [PASSED] Kernel buffer object
[12:23:18] [PASSED] Shared buffer object
[12:23:18] ============ [PASSED] ttm_bo_validate_multihop =============
[12:23:18] ========== ttm_bo_validate_no_placement_signaled ==========
[12:23:18] [PASSED] Buffer object in system domain, no page vector
[12:23:18] [PASSED] Buffer object in system domain with an existing page vector
[12:23:18] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[12:23:18] ======== ttm_bo_validate_no_placement_not_signaled ========
[12:23:18] [PASSED] Buffer object for userspace
[12:23:18] [PASSED] Kernel buffer object
[12:23:18] [PASSED] Shared buffer object
[12:23:18] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[12:23:18] [PASSED] ttm_bo_validate_move_fence_signaled
[12:23:18] ========= ttm_bo_validate_move_fence_not_signaled =========
[12:23:18] [PASSED] Waits for GPU
[12:23:18] [PASSED] Tries to lock straight away
[12:23:18] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[12:23:18] [PASSED] ttm_bo_validate_swapout
[12:23:18] [PASSED] ttm_bo_validate_happy_evict
[12:23:18] [PASSED] ttm_bo_validate_all_pinned_evict
[12:23:18] [PASSED] ttm_bo_validate_allowed_only_evict
[12:23:18] [PASSED] ttm_bo_validate_deleted_evict
[12:23:18] [PASSED] ttm_bo_validate_busy_domain_evict
[12:23:18] [PASSED] ttm_bo_validate_evict_gutting
[12:23:18] [PASSED] ttm_bo_validate_recrusive_evict
[12:23:18] ================= [PASSED] ttm_bo_validate =================
[12:23:18] ============================================================
[12:23:18] Testing complete. Ran 102 tests: passed: 102
[12:23:18] Elapsed time: 11.955s total, 1.806s configuring, 9.935s building, 0.175s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2026-08-04 12:23 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-08-03 20:08 [PATCH v7 0/1] drm/xe/guc_ads: allocate UM queues in a separate UC BO Jia Yao
2026-08-03 20:08 ` [PATCH v7 1/3] drm/xe/guc_ads: allocate UM queues in a separate BO Jia Yao
2026-08-04 7:43 ` Matthew Auld
2026-08-04 8:00 ` Matthew Auld
2026-08-04 8:54 ` Matthew Brost
2026-08-04 9:16 ` Matthew Auld
2026-08-04 9:25 ` Matthew Brost
2026-08-04 9:36 ` Matthew Auld
2026-08-03 20:08 ` [PATCH v7 2/3] drm/xe/guc_ads: allocate UM queues in VRAM on dGFX Jia Yao
2026-08-04 7:45 ` Matthew Auld
2026-08-03 20:08 ` [PATCH v7 3/3] drm/xe/guc_ads: use uncached mapping for UM queue BO Jia Yao
2026-08-03 20:15 ` ✓ CI.KUnit: success for drm/xe/guc_ads: allocate UM queues in a separate UC BO (rev5) Patchwork
2026-08-03 22:41 ` ✓ Xe.CI.FULL: " Patchwork
2026-08-04 12:23 ` ✓ CI.KUnit: " Patchwork
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