From: Andi Shyti <andi.shyti@linux.intel.com>
To: Matthew Brost <matthew.brost@intel.com>
Cc: linux-hwmon@vger.kernel.org, intel-xe@lists.freedesktop.org,
linux@roeck-us.net
Subject: Re: [Intel-xe] [PATCH v2 2/6] drm/xe/hwmon: Expose power attributes
Date: Thu, 29 Jun 2023 16:09:31 +0200 [thread overview]
Message-ID: <ZJ2Qm0UcAidCEArX@ashyti-mobl2.lan> (raw)
In-Reply-To: <ZJzNuq/WaxjZ8YH/@DUT025-TGLU.fm.intel.com>
Hi Matt and Badal,
[...]
> > +};
> > +
> > +enum hwm_reg_operation {
> > + reg_read,
> > + reg_write,
> > + reg_rmw,
>
> Upper case?
>
> > +};
> > +
>
> s/hwm_reg/xe_hwm_reg
I agree with Matt here... throughout this series of patches the
naming is very confusing, sometimes starting with xe_*, sometimes
with hwm_*, sometimes with hwmon_*... there is no consistency.
Please, Badal, choos a consistent prefix and stick with it for
every function and global definition.
Matt suggested xe_hwmon_*, I'm fine with it.
[...]
> > struct hwm_drvdata {
> > struct xe_hwmon *hwmon;
> > struct device *hwmon_dev;
> > + struct xe_gt *gt;
> > char name[12];
> > + bool reset_in_progress;
> > + wait_queue_head_t waitq;
> > };
> >
> > struct xe_hwmon {
> > struct hwm_drvdata ddat;
> > struct mutex hwmon_lock;
> > + int scl_shift_power;
> > };
> >
>
> Same as previous patch, 1 struct seems like a better idea to me.
I made the same comment in the previous patch.
[...]
> > + switch (reg_name) {
> > + case pkg_rapl_limit:
> > + if (xe->info.platform == XE_DG2)
> > + return PCU_CR_PACKAGE_RAPL_LIMIT;
> > + else if (xe->info.platform == XE_PVC)
> > + return PVC_GT0_PACKAGE_RAPL_LIMIT;
> > + break;
> > + case pkg_power_sku:
> > + if (xe->info.platform == XE_DG2)
> > + return PCU_CR_PACKAGE_POWER_SKU;
> > + else if (xe->info.platform == XE_PVC)
> > + return PVC_GT0_PACKAGE_POWER_SKU;
> > + break;
> > + case pkg_power_sku_unit:
> > + if (xe->info.platform == XE_DG2)
> > + return PCU_CR_PACKAGE_POWER_SKU_UNIT;
> > + else if (xe->info.platform == XE_PVC)
> > + return PVC_GT0_PACKAGE_POWER_SKU_UNIT;
> > + break;
> > + default:
>
> BUG_ON or WARN_ON saying not possible?
MISSING_CASE() is in i915_utils.h, perhaps we can move it to a
more generic place... it would be at handy here.
> > +static int hwm_power_max_read(struct hwm_drvdata *ddat, long *value)
>
> The return value is always 0, why not return value?
>
> s/hwm_power_max_read/xe_hwmon_power_max_read
>
> > +{
> > + struct xe_hwmon *hwmon = ddat->hwmon;
> > + u32 reg_val;
> > + u64 r, min, max;
> > +
> > + xe_device_mem_access_get(gt_to_xe(ddat->gt));
> > +
>
> Same as above, use xe_device_assert_mem_access.
>
> > + process_hwmon_reg(ddat, pkg_rapl_limit, reg_read, ®_val, 0, 0);
> > + /* Check if PL1 limit is disabled */
> > + if (!(reg_val & PKG_PWR_LIM_1_EN)) {
> > + *value = PL1_DISABLE;
> > + xe_device_mem_access_put(gt_to_xe(ddat->gt));
> > + return 0;
> > + }
> > +
> > + reg_val = REG_FIELD_GET(PKG_PWR_LIM_1, reg_val);
> > + *value = mul_u64_u32_shr(reg_val, SF_POWER, hwmon->scl_shift_power);
> > +
> > + process_hwmon_reg_read64(ddat, pkg_power_sku, &r);
> > + min = REG_FIELD_GET(PKG_MIN_PWR, r);
> > + min = mul_u64_u32_shr(min, SF_POWER, hwmon->scl_shift_power);
> > + max = REG_FIELD_GET(PKG_MAX_PWR, r);
> > + max = mul_u64_u32_shr(max, SF_POWER, hwmon->scl_shift_power);
> > +
> > + if (min && max)
> > + *value = clamp_t(u64, *value, min, max);
> > +
> > + xe_device_mem_access_put(gt_to_xe(ddat->gt));
> > + return 0;
> > +}
> > +
> > +static int hwm_power_max_write(struct hwm_drvdata *ddat, long value)
> > +{
> > + struct xe_hwmon *hwmon = ddat->hwmon;
> > + DEFINE_WAIT(wait);
> > + int ret = 0;
> > + u32 nval;
> > +
> > + /* Block waiting for GuC reset to complete when needed */
> > + for (;;) {
with a do...while() you shouldn't need a for(;;)... your choice,
not going to beat on that.
> > + mutex_lock(&hwmon->hwmon_lock);
> > +
> > + prepare_to_wait(&ddat->waitq, &wait, TASK_INTERRUPTIBLE);
> > +
> > + if (!hwmon->ddat.reset_in_progress)
> > + break;
> > +
> > + if (signal_pending(current)) {
> > + ret = -EINTR;
> > + break;
cough! cough! unlock! cough! cough!
> > + }
> > +
> > + mutex_unlock(&hwmon->hwmon_lock);
> > +
> > + schedule();
> > + }
> > + finish_wait(&ddat->waitq, &wait);
> > + if (ret)
> > + goto unlock;
>
> Anyway to not open code this? We similar in with
> xe_guc_submit_reset_wait, could we expose a global reset in progress in
> function which we can expose at the gt level?
>
> > +
> > + xe_device_mem_access_get(gt_to_xe(ddat->gt));
> > +
>
> This certainly is an outer most thing, e.g. doing this under
> hwmon->hwmon_lock seems dangerous. Again the upper levels of the stack
> should do the xe_device_mem_access_get, which it does. Just pointing out
> doing xe_device_mem_access_get/put under a lock isn't a good idea.
>
> Also the the loop which acquires hwmon->hwmon_lock is confusing too.
>
> > + /* Disable PL1 limit and verify, as limit cannot be disabled on all platforms */
> > + if (value == PL1_DISABLE) {
> > + process_hwmon_reg(ddat, pkg_rapl_limit, reg_rmw, &nval,
> > + PKG_PWR_LIM_1_EN, 0);
> > + process_hwmon_reg(ddat, pkg_rapl_limit, reg_read, &nval,
> > + PKG_PWR_LIM_1_EN, 0);
> > +
> > + if (nval & PKG_PWR_LIM_1_EN)
> > + ret = -ENODEV;
> > + goto exit;
cough! cough! lock! cough! cough!
> > + }
> > +
> > + /* Computation in 64-bits to avoid overflow. Round to nearest. */
> > + nval = DIV_ROUND_CLOSEST_ULL((u64)value << hwmon->scl_shift_power, SF_POWER);
> > + nval = PKG_PWR_LIM_1_EN | REG_FIELD_PREP(PKG_PWR_LIM_1, nval);
> > +
> > + process_hwmon_reg(ddat, pkg_rapl_limit, reg_rmw, &nval,
> > + PKG_PWR_LIM_1_EN | PKG_PWR_LIM_1, nval);
> > +exit:
> > + xe_device_mem_access_put(gt_to_xe(ddat->gt));
> > +unlock:
> > + mutex_unlock(&hwmon->hwmon_lock);
> > +
mmhhh???... jokes apart this is so error prone that it will
deadlock as soon as someone will think of editing this file :)
It worried me already at the first part.
Please, as Matt said, have a more linear locking here.
[...]
Andi
next prev parent reply other threads:[~2023-06-29 14:23 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-27 18:30 [Intel-xe] [PATCH v2 0/6] Add HWMON support for DGFX Badal Nilawar
2023-06-27 18:27 ` [Intel-xe] ✓ CI.Patch_applied: success for Add HWMON support for DGFX (rev2) Patchwork
2023-06-27 18:27 ` [Intel-xe] ✗ CI.checkpatch: warning " Patchwork
2023-06-27 18:29 ` [Intel-xe] ✓ CI.KUnit: success " Patchwork
2023-06-27 18:30 ` [Intel-xe] [PATCH v2 1/6] drm/xe/hwmon: Add HWMON infrastructure Badal Nilawar
2023-06-28 22:50 ` Matthew Brost
2023-07-05 18:30 ` Nilawar, Badal
2023-06-29 13:49 ` Andi Shyti
2023-07-07 14:23 ` Nilawar, Badal
2023-06-27 18:30 ` [Intel-xe] [PATCH v2 2/6] drm/xe/hwmon: Expose power attributes Badal Nilawar
2023-06-29 0:18 ` Matthew Brost
2023-06-29 14:09 ` Andi Shyti [this message]
2023-08-15 23:20 ` Dixit, Ashutosh
2023-08-18 4:03 ` Nilawar, Badal
2023-08-18 13:55 ` Andi Shyti
2023-07-06 10:36 ` Nilawar, Badal
2023-06-27 18:30 ` [Intel-xe] [PATCH v2 3/6] drm/xe/hwmon: Expose card reactive critical power Badal Nilawar
2023-06-28 15:52 ` Nilawar, Badal
2023-06-29 14:40 ` Andi Shyti
2023-07-06 19:05 ` Dixit, Ashutosh
2023-06-27 18:30 ` [Intel-xe] [PATCH v2 4/6] drm/xe/hwmon: Expose input voltage attribute Badal Nilawar
2023-06-29 14:58 ` Andi Shyti
2023-06-27 18:30 ` [Intel-xe] [PATCH v2 5/6] drm/xe/hwmon: Expose hwmon energy attribute Badal Nilawar
2023-06-29 15:09 ` Andi Shyti
2023-06-27 18:30 ` [Intel-xe] [PATCH v2 6/6] drm/xe/hwmon: Expose power1_max_interval Badal Nilawar
2023-06-27 18:32 ` [Intel-xe] ✓ CI.Build: success for Add HWMON support for DGFX (rev2) Patchwork
2023-06-27 18:33 ` [Intel-xe] ✗ CI.Hooks: failure " Patchwork
2023-07-02 1:31 ` [Intel-xe] [PATCH v2 0/6] Add HWMON support for DGFX Dixit, Ashutosh
2023-07-02 3:02 ` Guenter Roeck
2023-07-02 15:57 ` Dixit, Ashutosh
2023-07-02 17:01 ` Guenter Roeck
2023-07-02 20:29 ` Dixit, Ashutosh
2023-07-02 20:51 ` Guenter Roeck
2023-07-03 1:48 ` Dixit, Ashutosh
2023-07-03 2:37 ` Guenter Roeck
2023-07-14 20:21 ` Rodrigo Vivi
2023-07-14 22:26 ` Guenter Roeck
2023-07-19 17:01 ` Rodrigo Vivi
2023-07-03 8:55 ` Andi Shyti
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