Re: [Intel-xe] ttm_bo and multiple backing store segments

[Rodrigo Vivi <rodrigo.vivi@intel.com>]

On Thu, Jun 29, 2023 at 02:10:58PM -0700, Welty, Brian wrote:
> 
> Hi Christian / Thomas,
> 
> Wanted to ask if you have explored or thought about adding support in TTM
> such that a ttm_bo could have more than one underlying backing store segment
> (that is, to have a tree of ttm_resources)?
> We are considering to support such BOs for Intel Xe driver.

They are indeed the best one to give an opinion here.
I just have some dummy questions and comments below.

> 
> Some of the benefits:
>  * devices with page fault support can fault (and migrate) backing store
>    at finer granularity than the entire BO

what advantage does this bring? to each workload?
is it a performance on huge bo?

>  * BOs can support having multiple backing store segments, which can be
>    in different memory domains/regions

what locking challenges would this bring?
is this more targeting gpu + cpu? or only for our multi-tile platforms?
and what's the advantage this is bringing to real use cases?
(probably the svm/hmm question below answers my questions, but...)

>  * BO eviction could operate on smaller granularity than entire BO

I believe all the previous doubts apply to this item as well...

> 
> Or is the thinking that workloads should use SVM/HMM instead of GEM_CREATE
> if they want above benefits?
> 
> Is this something you are open to seeing an RFC series that starts perhaps
> with just extending ttm_bo_validate() to see how this might shape up?

Imho the RFC always help... a piece of code to see the idea usually draws
more attention from devs than ask in text mode. But more text explaining
the reasons behind are also helpful even with the RFC.

Thanks,
Rodrigo.

> 
> -Brian