[Intel-xe] [PATCH 00/11] Supporting CSC and SOC HARDWARE ERROR HANDLING on PVC

[Intel-xe] [PATCH 00/11] Supporting CSC and SOC HARDWARE ERROR HANDLING on PVC

[Himal Prasad Ghimiray]

The patches in this series covers errors from  SOC, GSC/CSC.

Depends-on:https://patchwork.freedesktop.org/series/122257/
The patches of this series are part of this series to ensure CI
validation.

Himal Prasad Ghimiray (11):
  drm/xe: Handle errors from various components.
  drm/xe: Log and count the GT hardware errors.
  drm/xe: Support GT hardware error reporting for PVC.
  drm/xe: Process fatal hardware errors.
  drm/xe: Support GSC hardware error reporting for PVC.
  drm/xe: Notify userspace about GSC HW errors.
  drm/xe: Support SOC FATAL error handling for PVC.
  drm/xe: Support SOC NONFATAL error handling for PVC.
  drm/xe: Handle MDFI error severity.
  drm/xe: Clear SOC CORRECTABLE error registers.
  drm/xe: Clear all SoC errors post warm reset.

 drivers/gpu/drm/xe/Makefile                  |   1 +
 drivers/gpu/drm/xe/regs/xe_gt_error_regs.h   |  29 +
 drivers/gpu/drm/xe/regs/xe_regs.h            |   5 +-
 drivers/gpu/drm/xe/regs/xe_tile_error_regs.h |  58 ++
 drivers/gpu/drm/xe/xe_device_types.h         |  15 +
 drivers/gpu/drm/xe/xe_gt_types.h             |   7 +
 drivers/gpu/drm/xe/xe_hw_error.c             | 889 +++++++++++++++++++
 drivers/gpu/drm/xe/xe_hw_error.h             | 223 +++++
 drivers/gpu/drm/xe/xe_irq.c                  |  10 +
 include/uapi/drm/xe_drm.h                    |   9 +
 10 files changed, 1245 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/xe/regs/xe_gt_error_regs.h
 create mode 100644 drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
 create mode 100644 drivers/gpu/drm/xe/xe_hw_error.c
 create mode 100644 drivers/gpu/drm/xe/xe_hw_error.h

-- 
2.25.1

[Intel-xe] ✓ CI.Patch_applied: success for Supporting CSC and SOC HARDWARE ERROR HANDLING on PVC

[Patchwork]

== Series Details ==

Series: Supporting CSC and SOC HARDWARE ERROR HANDLING on PVC
URL   : https://patchwork.freedesktop.org/series/124331/
State : success

== Summary ==

=== Applying kernel patches on branch 'drm-xe-next' with base: ===
Base commit: fc8ec3c56 drm/xe: Add Wa_18028616096
=== git am output follows ===
Applying: drm/xe: Handle errors from various components.
Applying: drm/xe: Log and count the GT hardware errors.
Applying: drm/xe: Support GT hardware error reporting for PVC.
Applying: drm/xe: Process fatal hardware errors.
Applying: drm/xe: Support GSC hardware error reporting for PVC.
Applying: drm/xe: Notify userspace about GSC HW errors.
Applying: drm/xe: Support SOC FATAL error handling for PVC.
Applying: drm/xe: Support SOC NONFATAL error handling for PVC.
Applying: drm/xe: Handle MDFI error severity.
Applying: drm/xe: Clear SOC CORRECTABLE error registers.
Applying: drm/xe: Clear all SoC errors post warm reset.

[Intel-xe] ✗ CI.checkpatch: warning for Supporting CSC and SOC HARDWARE ERROR HANDLING on PVC

[Patchwork]

== Series Details ==

Series: Supporting CSC and SOC HARDWARE ERROR HANDLING on PVC
URL   : https://patchwork.freedesktop.org/series/124331/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
63c2b6b160bca2df6efc7bc4cea6f442097d7854
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 0709f8f34847542c9b558217fce47f40b36238c4
Author: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Date:   Wed Sep 27 17:16:27 2023 +0530

    drm/xe: Clear all SoC errors post warm reset.
    
    There are scenarios where there are no fatal errors reported
    but Non-fatal/correctable errors being reported from the SoC
    uncore to IEH and not propogated to SG unit. Clear all previous
    SoC errors post warm reset.
    
    Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
+ /mt/dim checkpatch fc8ec3c56efa5c15b630ddc17c89100440fe03ef drm-intel
edab64e93 drm/xe: Handle errors from various components.
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in <module>
    from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in <module>
    from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in <module>
    from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:57: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#57: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 351 lines checked
5531034ec drm/xe: Log and count the GT hardware errors.
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in <module>
    from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:20: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#20: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 204 lines checked
7fdc8cb45 drm/xe: Support GT hardware error reporting for PVC.
-:42: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'hw_err' may be better as '(hw_err)' to avoid precedence issues
#42: FILE: drivers/gpu/drm/xe/regs/xe_gt_error_regs.h:26:
+#define ERR_STAT_GT_VCTR_REG(hw_err, x) (hw_err == HARDWARE_ERROR_CORRECTABLE ? \
+						ERR_STAT_GT_COR_VCTR_REG(x) : \
+						ERR_STAT_GT_FATAL_VCTR_REG(x))

-:42: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'x' - possible side-effects?
#42: FILE: drivers/gpu/drm/xe/regs/xe_gt_error_regs.h:26:
+#define ERR_STAT_GT_VCTR_REG(hw_err, x) (hw_err == HARDWARE_ERROR_CORRECTABLE ? \
+						ERR_STAT_GT_COR_VCTR_REG(x) : \
+						ERR_STAT_GT_FATAL_VCTR_REG(x))

total: 0 errors, 0 warnings, 2 checks, 216 lines checked
2be90df70 drm/xe: Process fatal hardware errors.
-:30: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#30: FILE: drivers/gpu/drm/xe/regs/xe_regs.h:97:
+#define   DEV_PCIEERR_IS_FATAL(x)		REG_BIT(x * 4 + 2)

total: 0 errors, 0 warnings, 1 checks, 69 lines checked
2557d92dc drm/xe: Support GSC hardware error reporting for PVC.
-:24: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'base' - possible side-effects?
#24: FILE: drivers/gpu/drm/xe/regs/xe_tile_error_regs.h:20:
+#define GSC_HEC_ERR_STAT_REG(base, x)                  XE_REG(_PICK_EVEN((x), \
+								(base) + _GSC_HEC_CORR_ERR_STATUS, \
+								(base) + _GSC_HEC_UNCOR_ERR_STATUS))

total: 0 errors, 0 warnings, 1 checks, 149 lines checked
ab84692ac drm/xe: Notify userspace about GSC HW errors.
6c0ed0898 drm/xe: Support SOC FATAL error handling for PVC.
-:24: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'base' - possible side-effects?
#24: FILE: drivers/gpu/drm/xe/regs/xe_tile_error_regs.h:28:
+#define SOC_LOCAL_ERR_STAT_SLAVE_REG(base, x)		XE_REG((x) > HARDWARE_ERROR_CORRECTABLE ? \
+								(base) + _SOC_LERRUNCSTS : \
+								(base) + _SOC_LERRCORSTS)

-:28: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'base' - possible side-effects?
#28: FILE: drivers/gpu/drm/xe/regs/xe_tile_error_regs.h:32:
+#define SOC_LOCAL_ERR_STAT_MASTER_REG(base, x)		XE_REG((x) > HARDWARE_ERROR_CORRECTABLE ? \
+								(base) + _SOC_LERRUNCSTS : \
+								(base) + _SOC_LERRCORSTS)

-:33: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'slave_base' may be better as '(slave_base)' to avoid precedence issues
#33: FILE: drivers/gpu/drm/xe/regs/xe_tile_error_regs.h:37:
+#define SOC_GSYSEVTCTL_REG(base, slave_base, x)		XE_REG(_PICK_EVEN((x), \
+								(base) + _SOC_GSYSEVTCTL, \
+								slave_base + _SOC_GSYSEVTCTL))

-:39: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'base' - possible side-effects?
#39: FILE: drivers/gpu/drm/xe/regs/xe_tile_error_regs.h:43:
+#define SOC_GLOBAL_ERR_STAT_SLAVE_REG(base, x)		XE_REG(_PICK_EVEN((x), \
+								(base) + _SOC_GCOERRSTS, \
+								(base) + _SOC_GNFERRSTS))

-:43: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'base' - possible side-effects?
#43: FILE: drivers/gpu/drm/xe/regs/xe_tile_error_regs.h:47:
+#define SOC_GLOBAL_ERR_STAT_MASTER_REG(base, x)		XE_REG(_PICK_EVEN((x), \
+								(base) + _SOC_GCOERRSTS, \
+								(base) + _SOC_GNFERRSTS))

total: 0 errors, 0 warnings, 5 checks, 290 lines checked
fc4c1730f drm/xe: Support SOC NONFATAL error handling for PVC.
155799e73 drm/xe: Handle MDFI error severity.
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one

total: 0 errors, 1 warnings, 0 checks, 41 lines checked
5c92b3139 drm/xe: Clear SOC CORRECTABLE error registers.
0709f8f34 drm/xe: Clear all SoC errors post warm reset.

[Intel-xe] ✓ CI.KUnit: success for Supporting CSC and SOC HARDWARE ERROR HANDLING on PVC

[Patchwork]

== Series Details ==

Series: Supporting CSC and SOC HARDWARE ERROR HANDLING on PVC
URL   : https://patchwork.freedesktop.org/series/124331/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
stty: 'standard input': Inappropriate ioctl for device
[11:43:33] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:43:37] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make ARCH=um O=.kunit --jobs=48
[11:43:57] Starting KUnit Kernel (1/1)...
[11:43:57] ============================================================
[11:43:57] ==================== xe_bo (2 subtests) ====================
[11:43:57] [SKIPPED] xe_ccs_migrate_kunit
[11:43:57] [SKIPPED] xe_bo_evict_kunit
[11:43:57] ===================== [SKIPPED] xe_bo ======================
[11:43:57] ================== xe_dma_buf (1 subtest) ==================
[11:43:57] [SKIPPED] xe_dma_buf_kunit
[11:43:57] =================== [SKIPPED] xe_dma_buf ===================
[11:43:57] ================== xe_migrate (1 subtest) ==================
[11:43:57] [SKIPPED] xe_migrate_sanity_kunit
[11:43:57] =================== [SKIPPED] xe_migrate ===================
[11:43:57] =================== xe_pci (2 subtests) ====================
[11:43:57] [PASSED] xe_gmdid_graphics_ip
[11:43:57] [PASSED] xe_gmdid_media_ip
[11:43:57] ===================== [PASSED] xe_pci ======================
[11:43:57] ==================== xe_rtp (1 subtest) ====================
[11:43:57] ================== xe_rtp_process_tests  ===================
[11:43:57] [PASSED] coalesce-same-reg
[11:43:57] [PASSED] no-match-no-add
[11:43:57] [PASSED] no-match-no-add-multiple-rules
[11:43:57] [PASSED] two-regs-two-entries
[11:43:57] [PASSED] clr-one-set-other
[11:43:57] [PASSED] set-field
[11:43:57] [PASSED] conflict-duplicate
[11:43:57] [PASSED] conflict-not-disjoint
[11:43:57] [PASSED] conflict-reg-type
[11:43:57] ============== [PASSED] xe_rtp_process_tests ===============
[11:43:57] ===================== [PASSED] xe_rtp ======================
[11:43:57] ==================== xe_wa (1 subtest) =====================
[11:43:57] ======================== xe_wa_gt  =========================
[11:43:57] [PASSED] TIGERLAKE (B0)
[11:43:57] [PASSED] DG1 (A0)
[11:43:57] [PASSED] DG1 (B0)
[11:43:57] [PASSED] ALDERLAKE_S (A0)
[11:43:57] [PASSED] ALDERLAKE_S (B0)
[11:43:57] [PASSED] ALDERLAKE_S (C0)
[11:43:57] [PASSED] ALDERLAKE_S (D0)
[11:43:57] [PASSED] ALDERLAKE_P (A0)
[11:43:57] [PASSED] ALDERLAKE_P (B0)
[11:43:57] [PASSED] ALDERLAKE_P (C0)
[11:43:57] [PASSED] DG2_G10 (A0)
[11:43:57] [PASSED] DG2_G10 (A1)
[11:43:57] [PASSED] DG2_G10 (B0)
[11:43:57] [PASSED] DG2_G10 (C0)
[11:43:57] [PASSED] DG2_G11 (A0)
[11:43:57] [PASSED] DG2_G11 (B0)
[11:43:57] [PASSED] DG2_G11 (B1)
[11:43:57] [PASSED] DG2_G12 (A0)
[11:43:57] [PASSED] DG2_G12 (A1)
[11:43:57] [PASSED] PVC (B0)
[11:43:57] [PASSED] PVC (B1)
[11:43:57] [PASSED] PVC (C0)
[11:43:57] ==================== [PASSED] xe_wa_gt =====================
[11:43:57] ====================== [PASSED] xe_wa ======================
[11:43:57] ============================================================
[11:43:57] Testing complete. Ran 37 tests: passed: 33, skipped: 4
[11:43:57] Elapsed time: 24.147s total, 4.233s configuring, 19.794s building, 0.100s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[11:43:57] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:43:59] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make ARCH=um O=.kunit --jobs=48
[11:44:18] Starting KUnit Kernel (1/1)...
[11:44:18] ============================================================
[11:44:18] ============ drm_test_pick_cmdline (2 subtests) ============
[11:44:18] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[11:44:18] =============== drm_test_pick_cmdline_named  ===============
[11:44:18] [PASSED] NTSC
[11:44:18] [PASSED] NTSC-J
[11:44:18] [PASSED] PAL
[11:44:18] [PASSED] PAL-M
[11:44:18] =========== [PASSED] drm_test_pick_cmdline_named ===========
[11:44:18] ============== [PASSED] drm_test_pick_cmdline ==============
[11:44:18] ================== drm_buddy (6 subtests) ==================
[11:44:18] [PASSED] drm_test_buddy_alloc_limit
[11:44:18] [PASSED] drm_test_buddy_alloc_range
[11:44:18] [PASSED] drm_test_buddy_alloc_optimistic
[11:44:19] [PASSED] drm_test_buddy_alloc_pessimistic
[11:44:19] [PASSED] drm_test_buddy_alloc_smoke
[11:44:19] [PASSED] drm_test_buddy_alloc_pathological
[11:44:19] ==================== [PASSED] drm_buddy ====================
[11:44:19] ============= drm_cmdline_parser (40 subtests) =============
[11:44:19] [PASSED] drm_test_cmdline_force_d_only
[11:44:19] [PASSED] drm_test_cmdline_force_D_only_dvi
[11:44:19] [PASSED] drm_test_cmdline_force_D_only_hdmi
[11:44:19] [PASSED] drm_test_cmdline_force_D_only_not_digital
[11:44:19] [PASSED] drm_test_cmdline_force_e_only
[11:44:19] [PASSED] drm_test_cmdline_res
[11:44:19] [PASSED] drm_test_cmdline_res_vesa
[11:44:19] [PASSED] drm_test_cmdline_res_vesa_rblank
[11:44:19] [PASSED] drm_test_cmdline_res_rblank
[11:44:19] [PASSED] drm_test_cmdline_res_bpp
[11:44:19] [PASSED] drm_test_cmdline_res_refresh
[11:44:19] [PASSED] drm_test_cmdline_res_bpp_refresh
[11:44:19] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[11:44:19] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[11:44:19] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[11:44:19] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[11:44:19] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[11:44:19] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[11:44:19] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[11:44:19] [PASSED] drm_test_cmdline_res_margins_force_on
[11:44:19] [PASSED] drm_test_cmdline_res_vesa_margins
[11:44:19] [PASSED] drm_test_cmdline_name
[11:44:19] [PASSED] drm_test_cmdline_name_bpp
[11:44:19] [PASSED] drm_test_cmdline_name_option
[11:44:19] [PASSED] drm_test_cmdline_name_bpp_option
[11:44:19] [PASSED] drm_test_cmdline_rotate_0
[11:44:19] [PASSED] drm_test_cmdline_rotate_90
[11:44:19] [PASSED] drm_test_cmdline_rotate_180
[11:44:19] [PASSED] drm_test_cmdline_rotate_270
[11:44:19] [PASSED] drm_test_cmdline_hmirror
[11:44:19] [PASSED] drm_test_cmdline_vmirror
[11:44:19] [PASSED] drm_test_cmdline_margin_options
[11:44:19] [PASSED] drm_test_cmdline_multiple_options
[11:44:19] [PASSED] drm_test_cmdline_bpp_extra_and_option
[11:44:19] [PASSED] drm_test_cmdline_extra_and_option
[11:44:19] [PASSED] drm_test_cmdline_freestanding_options
[11:44:19] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[11:44:19] [PASSED] drm_test_cmdline_panel_orientation
[11:44:19] ================ drm_test_cmdline_invalid  =================
[11:44:19] [PASSED] margin_only
[11:44:19] [PASSED] interlace_only
[11:44:19] [PASSED] res_missing_x
[11:44:19] [PASSED] res_missing_y
[11:44:19] [PASSED] res_bad_y
[11:44:19] [PASSED] res_missing_y_bpp
[11:44:19] [PASSED] res_bad_bpp
[11:44:19] [PASSED] res_bad_refresh
[11:44:19] [PASSED] res_bpp_refresh_force_on_off
[11:44:19] [PASSED] res_invalid_mode
[11:44:19] [PASSED] res_bpp_wrong_place_mode
[11:44:19] [PASSED] name_bpp_refresh
[11:44:19] [PASSED] name_refresh
[11:44:19] [PASSED] name_refresh_wrong_mode
[11:44:19] [PASSED] name_refresh_invalid_mode
[11:44:19] [PASSED] rotate_multiple
[11:44:19] [PASSED] rotate_invalid_val
[11:44:19] [PASSED] rotate_truncated
[11:44:19] [PASSED] invalid_option
[11:44:19] [PASSED] invalid_tv_option
[11:44:19] [PASSED] truncated_tv_option
[11:44:19] ============ [PASSED] drm_test_cmdline_invalid =============
[11:44:19] =============== drm_test_cmdline_tv_options  ===============
[11:44:19] [PASSED] NTSC
[11:44:19] [PASSED] NTSC_443
[11:44:19] [PASSED] NTSC_J
[11:44:19] [PASSED] PAL
[11:44:19] [PASSED] PAL_M
[11:44:19] [PASSED] PAL_N
[11:44:19] [PASSED] SECAM
[11:44:19] =========== [PASSED] drm_test_cmdline_tv_options ===========
[11:44:19] =============== [PASSED] drm_cmdline_parser ================
[11:44:19] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[11:44:19] ========== drm_test_get_tv_mode_from_name_valid  ===========
[11:44:19] [PASSED] NTSC
[11:44:19] [PASSED] NTSC-443
[11:44:19] [PASSED] NTSC-J
[11:44:19] [PASSED] PAL
[11:44:19] [PASSED] PAL-M
[11:44:19] [PASSED] PAL-N
[11:44:19] [PASSED] SECAM
[11:44:19] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[11:44:19] [PASSED] drm_test_get_tv_mode_from_name_truncated
[11:44:19] ============ [PASSED] drm_get_tv_mode_from_name ============
[11:44:19] ============= drm_damage_helper (21 subtests) ==============
[11:44:19] [PASSED] drm_test_damage_iter_no_damage
[11:44:19] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[11:44:19] [PASSED] drm_test_damage_iter_no_damage_src_moved
[11:44:19] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[11:44:19] [PASSED] drm_test_damage_iter_no_damage_not_visible
[11:44:19] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[11:44:19] [PASSED] drm_test_damage_iter_no_damage_no_fb
[11:44:19] [PASSED] drm_test_damage_iter_simple_damage
[11:44:19] [PASSED] drm_test_damage_iter_single_damage
[11:44:19] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[11:44:19] [PASSED] drm_test_damage_iter_single_damage_outside_src
[11:44:19] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[11:44:19] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[11:44:19] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[11:44:19] [PASSED] drm_test_damage_iter_single_damage_src_moved
[11:44:19] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[11:44:19] [PASSED] drm_test_damage_iter_damage
[11:44:19] [PASSED] drm_test_damage_iter_damage_one_intersect
[11:44:19] [PASSED] drm_test_damage_iter_damage_one_outside
[11:44:19] [PASSED] drm_test_damage_iter_damage_src_moved
[11:44:19] [PASSED] drm_test_damage_iter_damage_not_visible
[11:44:19] ================ [PASSED] drm_damage_helper ================
[11:44:19] ============== drm_dp_mst_helper (2 subtests) ==============
[11:44:19] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[11:44:19] [PASSED] Clock 154000 BPP 30 DSC disabled
[11:44:19] [PASSED] Clock 234000 BPP 30 DSC disabled
[11:44:19] [PASSED] Clock 297000 BPP 24 DSC disabled
[11:44:19] [PASSED] Clock 332880 BPP 24 DSC enabled
[11:44:19] [PASSED] Clock 324540 BPP 24 DSC enabled
[11:44:19] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[11:44:19] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[11:44:19] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[11:44:19] [PASSED] DP_POWER_UP_PHY with port number
[11:44:19] [PASSED] DP_POWER_DOWN_PHY with port number
[11:44:19] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[11:44:19] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[11:44:19] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[11:44:19] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[11:44:19] [PASSED] DP_QUERY_PAYLOAD with port number
[11:44:19] [PASSED] DP_QUERY_PAYLOAD with VCPI
[11:44:19] [PASSED] DP_REMOTE_DPCD_READ with port number
[11:44:19] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[11:44:19] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[11:44:19] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[11:44:19] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[11:44:19] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[11:44:19] [PASSED] DP_REMOTE_I2C_READ with port number
[11:44:19] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[11:44:19] [PASSED] DP_REMOTE_I2C_READ with transactions array
[11:44:19] [PASSED] DP_REMOTE_I2C_WRITE with port number
[11:44:19] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[11:44:19] [PASSED] DP_REMOTE_I2C_WRITE with data array
[11:44:19] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[11:44:19] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[11:44:19] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[11:44:19] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[11:44:19] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[11:44:19] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[11:44:19] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[11:44:19] ================ [PASSED] drm_dp_mst_helper ================
[11:44:19] =========== drm_format_helper_test (11 subtests) ===========
[11:44:19] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[11:44:19] [PASSED] single_pixel_source_buffer
[11:44:19] [PASSED] single_pixel_clip_rectangle
[11:44:19] [PASSED] well_known_colors
[11:44:19] [PASSED] destination_pitch
[11:44:19] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[11:44:19] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[11:44:19] [PASSED] single_pixel_source_buffer
[11:44:19] [PASSED] single_pixel_clip_rectangle
[11:44:19] [PASSED] well_known_colors
[11:44:19] [PASSED] destination_pitch
[11:44:19] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[11:44:19] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[11:44:19] [PASSED] single_pixel_source_buffer
[11:44:19] [PASSED] single_pixel_clip_rectangle
[11:44:19] [PASSED] well_known_colors
[11:44:19] [PASSED] destination_pitch
[11:44:19] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[11:44:19] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[11:44:19] [PASSED] single_pixel_source_buffer
[11:44:19] [PASSED] single_pixel_clip_rectangle
[11:44:19] [PASSED] well_known_colors
[11:44:19] [PASSED] destination_pitch
[11:44:19] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[11:44:19] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[11:44:19] [PASSED] single_pixel_source_buffer
[11:44:19] [PASSED] single_pixel_clip_rectangle
[11:44:19] [PASSED] well_known_colors
[11:44:19] [PASSED] destination_pitch
[11:44:19] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[11:44:19] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[11:44:19] [PASSED] single_pixel_source_buffer
[11:44:19] [PASSED] single_pixel_clip_rectangle
[11:44:19] [PASSED] well_known_colors
[11:44:19] [PASSED] destination_pitch
[11:44:19] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[11:44:19] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[11:44:19] [PASSED] single_pixel_source_buffer
[11:44:19] [PASSED] single_pixel_clip_rectangle
[11:44:19] [PASSED] well_known_colors
[11:44:19] [PASSED] destination_pitch
[11:44:19] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[11:44:19] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[11:44:19] [PASSED] single_pixel_source_buffer
[11:44:19] [PASSED] single_pixel_clip_rectangle
[11:44:19] [PASSED] well_known_colors
[11:44:19] [PASSED] destination_pitch
[11:44:19] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[11:44:19] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[11:44:19] [PASSED] single_pixel_source_buffer
[11:44:19] [PASSED] single_pixel_clip_rectangle
[11:44:19] [PASSED] well_known_colors
[11:44:19] [PASSED] destination_pitch
[11:44:19] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[11:44:19] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[11:44:19] [PASSED] single_pixel_source_buffer
[11:44:19] [PASSED] single_pixel_clip_rectangle
[11:44:19] [PASSED] well_known_colors
[11:44:19] [PASSED] destination_pitch
[11:44:19] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[11:44:19] ============== drm_test_fb_xrgb8888_to_mono  ===============
[11:44:19] [PASSED] single_pixel_source_buffer
[11:44:19] [PASSED] single_pixel_clip_rectangle
[11:44:19] [PASSED] well_known_colors
[11:44:19] [PASSED] destination_pitch
[11:44:19] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[11:44:19] ============= [PASSED] drm_format_helper_test ==============
[11:44:19] ================= drm_format (18 subtests) =================
[11:44:19] [PASSED] drm_test_format_block_width_invalid
[11:44:19] [PASSED] drm_test_format_block_width_one_plane
[11:44:19] [PASSED] drm_test_format_block_width_two_plane
[11:44:19] [PASSED] drm_test_format_block_width_three_plane
[11:44:19] [PASSED] drm_test_format_block_width_tiled
[11:44:19] [PASSED] drm_test_format_block_height_invalid
[11:44:19] [PASSED] drm_test_format_block_height_one_plane
[11:44:19] [PASSED] drm_test_format_block_height_two_plane
[11:44:19] [PASSED] drm_test_format_block_height_three_plane
[11:44:19] [PASSED] drm_test_format_block_height_tiled
[11:44:19] [PASSED] drm_test_format_min_pitch_invalid
[11:44:19] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[11:44:19] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[11:44:19] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[11:44:19] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[11:44:19] [PASSED] drm_test_format_min_pitch_two_plane
[11:44:19] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[11:44:19] [PASSED] drm_test_format_min_pitch_tiled
[11:44:19] =================== [PASSED] drm_format ====================
[11:44:19] =============== drm_framebuffer (1 subtest) ================
[11:44:19] =============== drm_test_framebuffer_create  ===============
[11:44:19] [PASSED] ABGR8888 normal sizes
[11:44:19] [PASSED] ABGR8888 max sizes
[11:44:19] [PASSED] ABGR8888 pitch greater than min required
[11:44:19] [PASSED] ABGR8888 pitch less than min required
[11:44:19] [PASSED] ABGR8888 Invalid width
[11:44:19] [PASSED] ABGR8888 Invalid buffer handle
[11:44:19] [PASSED] No pixel format
[11:44:19] [PASSED] ABGR8888 Width 0
[11:44:19] [PASSED] ABGR8888 Height 0
[11:44:19] [PASSED] ABGR8888 Out of bound height * pitch combination
[11:44:19] [PASSED] ABGR8888 Large buffer offset
[11:44:19] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[11:44:19] [PASSED] ABGR8888 Valid buffer modifier
[11:44:19] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[11:44:19] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[11:44:19] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[11:44:19] [PASSED] NV12 Normal sizes
[11:44:19] [PASSED] NV12 Max sizes
[11:44:19] [PASSED] NV12 Invalid pitch
[11:44:19] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[11:44:19] [PASSED] NV12 different  modifier per-plane
[11:44:19] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[11:44:19] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[11:44:19] [PASSED] NV12 Modifier for inexistent plane
[11:44:19] [PASSED] NV12 Handle for inexistent plane
[11:44:19] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[11:44:19] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[11:44:19] [PASSED] YVU420 Normal sizes
[11:44:19] [PASSED] YVU420 Max sizes
[11:44:19] [PASSED] YVU420 Invalid pitch
[11:44:19] [PASSED] YVU420 Different pitches
[11:44:19] [PASSED] YVU420 Different buffer offsets/pitches
[11:44:19] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[11:44:19] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[11:44:19] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[11:44:19] [PASSED] YVU420 Valid modifier
[11:44:19] [PASSED] YVU420 Different modifiers per plane
[11:44:19] [PASSED] YVU420 Modifier for inexistent plane
[11:44:19] [PASSED] X0L2 Normal sizes
[11:44:19] [PASSED] X0L2 Max sizes
[11:44:19] [PASSED] X0L2 Invalid pitch
[11:44:19] [PASSED] X0L2 Pitch greater than minimum required
stty: 'standard input': Inappropriate ioctl for device
[11:44:19] [PASSED] X0L2 Handle for inexistent plane
[11:44:19] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[11:44:19] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[11:44:19] [PASSED] X0L2 Valid modifier
[11:44:19] [PASSED] X0L2 Modifier for inexistent plane
[11:44:19] =========== [PASSED] drm_test_framebuffer_create ===========
[11:44:19] ================= [PASSED] drm_framebuffer =================
[11:44:19] =============== drm-test-managed (1 subtest) ===============
[11:44:19] [PASSED] drm_test_managed_run_action
[11:44:19] ================ [PASSED] drm-test-managed =================
[11:44:19] =================== drm_mm (19 subtests) ===================
[11:44:19] [PASSED] drm_test_mm_init
[11:44:19] [PASSED] drm_test_mm_debug
[11:44:29] [PASSED] drm_test_mm_reserve
[11:44:38] [PASSED] drm_test_mm_insert
[11:44:39] [PASSED] drm_test_mm_replace
[11:44:39] [PASSED] drm_test_mm_insert_range
[11:44:39] [PASSED] drm_test_mm_frag
[11:44:39] [PASSED] drm_test_mm_align
[11:44:39] [PASSED] drm_test_mm_align32
[11:44:40] [PASSED] drm_test_mm_align64
[11:44:40] [PASSED] drm_test_mm_evict
[11:44:40] [PASSED] drm_test_mm_evict_range
[11:44:40] [PASSED] drm_test_mm_topdown
[11:44:40] [PASSED] drm_test_mm_bottomup
[11:44:40] [PASSED] drm_test_mm_lowest
[11:44:40] [PASSED] drm_test_mm_highest
[11:44:41] [PASSED] drm_test_mm_color
[11:44:41] [PASSED] drm_test_mm_color_evict
[11:44:41] [PASSED] drm_test_mm_color_evict_range
[11:44:41] ===================== [PASSED] drm_mm ======================
[11:44:41] ============= drm_modes_analog_tv (4 subtests) =============
[11:44:41] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[11:44:41] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[11:44:41] [PASSED] drm_test_modes_analog_tv_pal_576i
[11:44:41] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[11:44:41] =============== [PASSED] drm_modes_analog_tv ===============
[11:44:41] ============== drm_plane_helper (2 subtests) ===============
[11:44:41] =============== drm_test_check_plane_state  ================
[11:44:41] [PASSED] clipping_simple
[11:44:41] [PASSED] clipping_rotate_reflect
[11:44:41] [PASSED] positioning_simple
[11:44:41] [PASSED] upscaling
[11:44:41] [PASSED] downscaling
[11:44:41] [PASSED] rounding1
[11:44:41] [PASSED] rounding2
[11:44:41] [PASSED] rounding3
[11:44:41] [PASSED] rounding4
[11:44:41] =========== [PASSED] drm_test_check_plane_state ============
[11:44:41] =========== drm_test_check_invalid_plane_state  ============
[11:44:41] [PASSED] positioning_invalid
[11:44:41] [PASSED] upscaling_invalid
[11:44:41] [PASSED] downscaling_invalid
[11:44:41] ======= [PASSED] drm_test_check_invalid_plane_state ========
[11:44:41] ================ [PASSED] drm_plane_helper =================
[11:44:41] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[11:44:41] ====== drm_test_connector_helper_tv_get_modes_check  =======
[11:44:41] [PASSED] None
[11:44:41] [PASSED] PAL
[11:44:41] [PASSED] NTSC
[11:44:41] [PASSED] Both, NTSC Default
[11:44:41] [PASSED] Both, PAL Default
[11:44:41] [PASSED] Both, NTSC Default, with PAL on command-line
[11:44:41] [PASSED] Both, PAL Default, with NTSC on command-line
[11:44:41] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[11:44:41] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[11:44:41] ================== drm_rect (9 subtests) ===================
[11:44:41] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[11:44:41] [PASSED] drm_test_rect_clip_scaled_not_clipped
[11:44:41] [PASSED] drm_test_rect_clip_scaled_clipped
[11:44:41] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[11:44:41] ================= drm_test_rect_intersect  =================
[11:44:41] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[11:44:41] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[11:44:41] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[11:44:41] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[11:44:41] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[11:44:41] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[11:44:41] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[11:44:41] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[11:44:41] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[11:44:41] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[11:44:41] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[11:44:41] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[11:44:41] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[11:44:41] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[11:44:41] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[11:44:41] ============= [PASSED] drm_test_rect_intersect =============
[11:44:41] ================ drm_test_rect_calc_hscale  ================
[11:44:41] [PASSED] normal use
[11:44:41] [PASSED] out of max range
[11:44:41] [PASSED] out of min range
[11:44:41] [PASSED] zero dst
[11:44:41] [PASSED] negative src
[11:44:41] [PASSED] negative dst
[11:44:41] ============ [PASSED] drm_test_rect_calc_hscale ============
[11:44:41] ================ drm_test_rect_calc_vscale  ================
[11:44:41] [PASSED] normal use
[11:44:41] [PASSED] out of max range
[11:44:41] [PASSED] out of min range
[11:44:41] [PASSED] zero dst
[11:44:41] [PASSED] negative src
[11:44:41] [PASSED] negative dst
[11:44:41] ============ [PASSED] drm_test_rect_calc_vscale ============
[11:44:41] ================== drm_test_rect_rotate  ===================
[11:44:41] [PASSED] reflect-x
[11:44:41] [PASSED] reflect-y
[11:44:41] [PASSED] rotate-0
[11:44:41] [PASSED] rotate-90
[11:44:41] [PASSED] rotate-180
[11:44:41] [PASSED] rotate-270
[11:44:41] ============== [PASSED] drm_test_rect_rotate ===============
[11:44:41] ================ drm_test_rect_rotate_inv  =================
[11:44:41] [PASSED] reflect-x
[11:44:41] [PASSED] reflect-y
[11:44:41] [PASSED] rotate-0
[11:44:41] [PASSED] rotate-90
[11:44:41] [PASSED] rotate-180
[11:44:41] [PASSED] rotate-270
[11:44:41] ============ [PASSED] drm_test_rect_rotate_inv =============
[11:44:41] ==================== [PASSED] drm_rect =====================
[11:44:41] ================== drm_exec (7 subtests) ===================
[11:44:41] [PASSED] sanitycheck
[11:44:41] [PASSED] test_lock
[11:44:41] [PASSED] test_lock_unlock
[11:44:41] [PASSED] test_duplicates
[11:44:41] [PASSED] test_prepare
[11:44:41] [PASSED] test_prepare_array
[11:44:41] [PASSED] test_multiple_loops
[11:44:41] ==================== [PASSED] drm_exec =====================
[11:44:41] ============================================================
[11:44:41] Testing complete. Ran 340 tests: passed: 340
[11:44:41] Elapsed time: 44.054s total, 1.681s configuring, 19.137s building, 23.177s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

[Intel-xe] [PATCH 01/11] drm/xe: Handle errors from various components.

[Himal Prasad Ghimiray]

The GFX device can generate numbers of classes of error under the new
infrastructure: correctable, non-fatal, and fatal errors.

The non-fatal and fatal error classes distinguish between levels of
severity for uncorrectable errors. Driver will only handle logging
of errors and updating counters from various components within the
graphics device. Anything more will be handled at system level.

For errors that will route as interrupts, three bits in the Master
Interrupt Register will be used to convey the class of error.

For each class of error: Determine source of error (IP block) by reading
the Device Error Source Register (RW1C) that
corresponds to the class of error being serviced.

Bspec: 50875, 53073, 53074, 53075

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
 drivers/gpu/drm/xe/Makefile                  |   1 +
 drivers/gpu/drm/xe/regs/xe_regs.h            |   2 +-
 drivers/gpu/drm/xe/regs/xe_tile_error_regs.h |  15 ++
 drivers/gpu/drm/xe/xe_device_types.h         |  11 +
 drivers/gpu/drm/xe/xe_hw_error.c             | 211 +++++++++++++++++++
 drivers/gpu/drm/xe/xe_hw_error.h             |  64 ++++++
 drivers/gpu/drm/xe/xe_irq.c                  |   5 +
 7 files changed, 308 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
 create mode 100644 drivers/gpu/drm/xe/xe_hw_error.c
 create mode 100644 drivers/gpu/drm/xe/xe_hw_error.h

diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index b1681d1416eb..be1f3afec3dc 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -76,6 +76,7 @@ xe-y += xe_bb.o \
 	xe_guc_submit.o \
 	xe_hw_engine.o \
 	xe_hw_engine_class_sysfs.o \
+	xe_hw_error.o \
 	xe_hw_fence.o \
 	xe_huc.o \
 	xe_huc_debugfs.o \
diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h
index 8a93ab169e04..863df80d69bf 100644
--- a/drivers/gpu/drm/xe/regs/xe_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_regs.h
@@ -91,7 +91,7 @@
 #define   GU_MISC_IRQ				REG_BIT(29)
 #define   DISPLAY_IRQ				REG_BIT(16)
 #define   GT_DW_IRQ(x)				REG_BIT(x)
+#define   XE_ERROR_IRQ(x)			REG_BIT(26 + (x))
 
 #define PVC_RP_STATE_CAP			XE_REG(0x281014)
-
 #endif
diff --git a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
new file mode 100644
index 000000000000..db78d6687213
--- /dev/null
+++ b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+#ifndef XE_TILE_ERROR_REGS_H_
+#define XE_TILE_ERROR_REGS_H_
+
+#include <linux/stddef.h>
+
+#define _DEV_ERR_STAT_NONFATAL                         0x100178
+#define _DEV_ERR_STAT_CORRECTABLE                      0x10017c
+#define DEV_ERR_STAT_REG(x)                            XE_REG(_PICK_EVEN((x), \
+								_DEV_ERR_STAT_CORRECTABLE, \
+								_DEV_ERR_STAT_NONFATAL))
+#endif
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 32ab0fea04ee..4d8b0724d1fe 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -14,6 +14,7 @@
 
 #include "xe_devcoredump_types.h"
 #include "xe_gt_types.h"
+#include "xe_hw_error.h"
 #include "xe_platform_types.h"
 #include "xe_pmu.h"
 #include "xe_step_types.h"
@@ -173,6 +174,11 @@ struct xe_tile {
 
 	/** @sysfs: sysfs' kobj used by xe_tile_sysfs */
 	struct kobject *sysfs;
+
+	/** @tile_hw_errors: hardware errors reported for the tile */
+	struct tile_hw_errors {
+		unsigned long count[XE_TILE_HW_ERROR_MAX];
+	} errors;
 };
 
 /**
@@ -365,6 +371,11 @@ struct xe_device {
 	/** @pmu: performance monitoring unit */
 	struct xe_pmu pmu;
 
+	/** @hardware_errors_regs: list of hw error regs*/
+	struct hardware_errors_regs {
+		const struct err_msg_cntr_pair *dev_err_stat[HARDWARE_ERROR_MAX];
+	} hw_err_regs;
+
 	/* private: */
 
 #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
new file mode 100644
index 000000000000..357d0f962d91
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_hw_error.c
@@ -0,0 +1,211 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#include "xe_hw_error.h"
+
+#include "regs/xe_regs.h"
+#include "regs/xe_tile_error_regs.h"
+#include "xe_device.h"
+#include "xe_mmio.h"
+
+static const char *
+hardware_error_type_to_str(const enum hardware_error hw_err)
+{
+	switch (hw_err) {
+	case HARDWARE_ERROR_CORRECTABLE:
+		return "CORRECTABLE";
+	case HARDWARE_ERROR_NONFATAL:
+		return "NONFATAL";
+	case HARDWARE_ERROR_FATAL:
+		return "FATAL";
+	default:
+		return "UNKNOWN";
+	}
+}
+
+static const struct err_msg_cntr_pair dg2_err_stat_fatal_reg[] = {
+	[0]         = {"GT",			XE_TILE_HW_ERR_GT_FATAL},
+	[1 ... 3]   = {"Undefined",		XE_TILE_HW_ERR_UNKNOWN_FATAL},
+	[4]         = {"DISPLAY",		XE_TILE_HW_ERR_DISPLAY_FATAL},
+	[5 ... 7]   = {"Undefined",		XE_TILE_HW_ERR_UNKNOWN_FATAL},
+	[8]         = {"GSC error",		XE_TILE_HW_ERR_GSC_FATAL},
+	[9 ... 11]  = {"Undefined",		XE_TILE_HW_ERR_UNKNOWN_FATAL},
+	[12]        = {"SGUNIT",		XE_TILE_HW_ERR_SGUNIT_FATAL},
+	[13 ... 15] = {"Undefined",             XE_TILE_HW_ERR_UNKNOWN_FATAL},
+	[16]        = {"SOC",			XE_TILE_HW_ERR_SOC_FATAL},
+	[17 ... 31] = {"Undefined",             XE_TILE_HW_ERR_UNKNOWN_FATAL},
+};
+
+static const struct err_msg_cntr_pair dg2_err_stat_nonfatal_reg[] = {
+	[0]         = {"GT",			XE_TILE_HW_ERR_GT_NONFATAL},
+	[1 ... 3]   = {"Undefined",		XE_TILE_HW_ERR_UNKNOWN_NONFATAL},
+	[4]         = {"DISPLAY",		XE_TILE_HW_ERR_DISPLAY_NONFATAL},
+	[5 ... 7]   = {"Undefined",		XE_TILE_HW_ERR_UNKNOWN_NONFATAL},
+	[8]         = {"GSC error",		XE_TILE_HW_ERR_GSC_NONFATAL},
+	[9 ... 11]  = {"Undefined",		XE_TILE_HW_ERR_UNKNOWN_NONFATAL},
+	[12]        = {"SGUNIT",		XE_TILE_HW_ERR_SGUNIT_NONFATAL},
+	[13 ... 15] = {"Undefined",             XE_TILE_HW_ERR_UNKNOWN_NONFATAL},
+	[16]        = {"SOC",			XE_TILE_HW_ERR_SOC_NONFATAL},
+	[17 ... 19] = {"Undefined",             XE_TILE_HW_ERR_UNKNOWN_NONFATAL},
+	[20]        = {"MERT",			XE_TILE_HW_ERR_MERT_NONFATAL},
+	[21 ... 31] = {"Undefined",             XE_TILE_HW_ERR_UNKNOWN_NONFATAL},
+};
+
+static const struct err_msg_cntr_pair dg2_err_stat_correctable_reg[] = {
+	[0]         = {"GT",			XE_TILE_HW_ERR_GT_CORR},
+	[1 ... 3]   = {"Undefined",		XE_TILE_HW_ERR_UNKNOWN_CORR},
+	[4]         = {"DISPLAY",		XE_TILE_HW_ERR_DISPLAY_CORR},
+	[5 ... 7]   = {"Undefined",		XE_TILE_HW_ERR_UNKNOWN_CORR},
+	[8]         = {"GSC error",		XE_TILE_HW_ERR_GSC_CORR},
+	[9 ... 11]  = {"Undefined",		XE_TILE_HW_ERR_UNKNOWN_CORR},
+	[12]        = {"SGUNIT",		XE_TILE_HW_ERR_SGUNIT_CORR},
+	[13 ... 15] = {"Undefined",             XE_TILE_HW_ERR_UNKNOWN_CORR},
+	[16]        = {"SOC",			XE_TILE_HW_ERR_SOC_CORR},
+	[17 ... 31] = {"Undefined",             XE_TILE_HW_ERR_UNKNOWN_CORR},
+};
+
+static const struct err_msg_cntr_pair pvc_err_stat_fatal_reg[] = {
+	[0]         =  {"GT",			XE_TILE_HW_ERR_GT_FATAL},
+	[1]         =  {"SGGI Cmd Parity",	XE_TILE_HW_ERR_SGGI_FATAL},
+	[2 ... 7]   =  {"Undefined",		XE_TILE_HW_ERR_UNKNOWN_FATAL},
+	[8]         =  {"GSC error",		XE_TILE_HW_ERR_GSC_FATAL},
+	[9]         =  {"SGLI Cmd Parity",	XE_TILE_HW_ERR_SGLI_FATAL},
+	[10 ... 12] =  {"Undefined",		XE_TILE_HW_ERR_UNKNOWN_FATAL},
+	[13]        =  {"SGCI Cmd Parity",	XE_TILE_HW_ERR_SGCI_FATAL},
+	[14 ... 15] =  {"Undefined",		XE_TILE_HW_ERR_UNKNOWN_FATAL},
+	[16]        =  {"SOC ERROR",		XE_TILE_HW_ERR_SOC_FATAL},
+	[17 ... 19] =  {"Undefined",		XE_TILE_HW_ERR_UNKNOWN_FATAL},
+	[20]        =  {"MERT Cmd Parity",	XE_TILE_HW_ERR_MERT_FATAL},
+	[21 ... 31] =  {"Undefined",		XE_TILE_HW_ERR_UNKNOWN_FATAL},
+};
+
+static const struct err_msg_cntr_pair pvc_err_stat_nonfatal_reg[] = {
+	[0]         =  {"GT",			XE_TILE_HW_ERR_GT_NONFATAL},
+	[1]         =  {"SGGI Data Parity",	XE_TILE_HW_ERR_SGGI_NONFATAL},
+	[2 ... 7]   =  {"Undefined",		XE_TILE_HW_ERR_UNKNOWN_NONFATAL},
+	[8]         =  {"GSC",			XE_TILE_HW_ERR_GSC_NONFATAL},
+	[9]         =  {"SGLI Data Parity",	XE_TILE_HW_ERR_SGLI_NONFATAL},
+	[10 ... 12] =  {"Undefined",		XE_TILE_HW_ERR_UNKNOWN_NONFATAL},
+	[13]        =  {"SGCI Data Parity",	XE_TILE_HW_ERR_SGCI_NONFATAL},
+	[14 ... 15] =  {"Undefined",		XE_TILE_HW_ERR_UNKNOWN_NONFATAL},
+	[16]        =  {"SOC",			XE_TILE_HW_ERR_SOC_NONFATAL},
+	[17 ... 19] =  {"Undefined",		XE_TILE_HW_ERR_UNKNOWN_NONFATAL},
+	[20]        =  {"MERT Data Parity",	XE_TILE_HW_ERR_MERT_NONFATAL},
+	[21 ... 31] =  {"Undefined",            XE_TILE_HW_ERR_UNKNOWN_NONFATAL},
+};
+
+static const struct err_msg_cntr_pair pvc_err_stat_correctable_reg[] = {
+	[0]         =  {"GT",			XE_TILE_HW_ERR_GT_CORR},
+	[1 ... 7]   =  {"Undefined",		XE_TILE_HW_ERR_UNKNOWN_CORR},
+	[8]         =  {"GSC",			XE_TILE_HW_ERR_GSC_CORR},
+	[9 ... 31]  =  {"Undefined",		XE_TILE_HW_ERR_UNKNOWN_CORR},
+};
+
+static const struct err_msg_cntr_pair dev_err_stat_fatal_reg[] = {
+	[0]         =  {"GT",			XE_TILE_HW_ERR_GT_FATAL},
+	[1 ... 31]  =  {"Undefined",		XE_TILE_HW_ERR_UNKNOWN_FATAL},
+};
+
+static const struct err_msg_cntr_pair dev_err_stat_nonfatal_reg[] = {
+	[0]         =  {"GT",			XE_TILE_HW_ERR_GT_NONFATAL},
+	[1 ... 31]  =  {"Undefined",            XE_TILE_HW_ERR_UNKNOWN_NONFATAL},
+};
+
+static const struct err_msg_cntr_pair dev_err_stat_correctable_reg[] = {
+	[0]         =  {"GT",			XE_TILE_HW_ERR_GT_CORR},
+	[1 ... 31]  =  {"Undefined",		XE_TILE_HW_ERR_UNKNOWN_CORR},
+};
+
+void xe_assign_hw_err_regs(struct xe_device *xe)
+{
+	const struct err_msg_cntr_pair **dev_err_stat = xe->hw_err_regs.dev_err_stat;
+
+	if (xe->info.platform == XE_DG2) {
+		dev_err_stat[HARDWARE_ERROR_CORRECTABLE] = dg2_err_stat_correctable_reg;
+		dev_err_stat[HARDWARE_ERROR_NONFATAL] = dg2_err_stat_nonfatal_reg;
+		dev_err_stat[HARDWARE_ERROR_FATAL] = dg2_err_stat_fatal_reg;
+	} else if (xe->info.platform == XE_PVC) {
+		dev_err_stat[HARDWARE_ERROR_CORRECTABLE] = pvc_err_stat_correctable_reg;
+		dev_err_stat[HARDWARE_ERROR_NONFATAL] = pvc_err_stat_nonfatal_reg;
+		dev_err_stat[HARDWARE_ERROR_FATAL] = pvc_err_stat_fatal_reg;
+	} else {
+		/* For other platforms report only GT errors */
+		dev_err_stat[HARDWARE_ERROR_CORRECTABLE] = dev_err_stat_correctable_reg;
+		dev_err_stat[HARDWARE_ERROR_NONFATAL] = dev_err_stat_nonfatal_reg;
+		dev_err_stat[HARDWARE_ERROR_FATAL] = dev_err_stat_fatal_reg;
+	}
+}
+
+static void
+xe_hw_error_source_handler(struct xe_tile *tile, const enum hardware_error hw_err)
+{
+	const char *hw_err_str = hardware_error_type_to_str(hw_err);
+	const struct hardware_errors_regs *err_regs;
+	const struct err_msg_cntr_pair *errstat;
+	unsigned long errsrc;
+	unsigned long flags;
+	const char *errmsg;
+	struct xe_gt *mmio;
+	u32 indx;
+	u32 errbit;
+
+	spin_lock_irqsave(&tile_to_xe(tile)->irq.lock, flags);
+	err_regs = &tile_to_xe(tile)->hw_err_regs;
+	errstat = err_regs->dev_err_stat[hw_err];
+	mmio = tile->primary_gt;
+	errsrc = xe_mmio_read32(mmio, DEV_ERR_STAT_REG(hw_err));
+	if (!errsrc) {
+		drm_err_ratelimited(&tile_to_xe(tile)->drm, HW_ERR
+				    "TILE%d detected DEV_ERR_STAT_REG_%s blank!\n",
+				    tile->id, hw_err_str);
+		goto unlock;
+	}
+
+	drm_info(&tile_to_xe(tile)->drm, HW_ERR
+		 "TILE%d DEV_ERR_STAT_REG_%s=0x%08lx\n", tile->id, hw_err_str, errsrc);
+
+	for_each_set_bit(errbit, &errsrc, 32) {
+		errmsg = errstat[errbit].errmsg;
+		indx = errstat[errbit].cntr_indx;
+
+		if (hw_err == HARDWARE_ERROR_CORRECTABLE)
+			drm_warn(&tile_to_xe(tile)->drm,
+				 HW_ERR "TILE%d detected %s %s error, bit[%d] is set\n",
+				 tile->id, errmsg, hw_err_str, errbit);
+
+		else
+			drm_err_ratelimited(&tile_to_xe(tile)->drm,
+					    HW_ERR "TILE%d detected %s %s error, bit[%d] is set\n",
+					    tile->id, errmsg, hw_err_str, errbit);
+		tile->errors.count[indx]++;
+	}
+
+	xe_mmio_write32(mmio, DEV_ERR_STAT_REG(hw_err), errsrc);
+unlock:
+	spin_unlock_irqrestore(&tile_to_xe(tile)->irq.lock, flags);
+}
+
+/*
+ * XE Platforms adds three Error bits to the Master Interrupt
+ * Register to support error handling. These three bits are
+ * used to convey the class of error:
+ * FATAL, NONFATAL, or CORRECTABLE.
+ *
+ * To process an interrupt:
+ *       Determine source of error (IP block) by reading
+ *	 the Device Error Source Register (RW1C) that
+ *	 corresponds to the class of error being serviced
+ *	 and log the error.
+ */
+void
+xe_hw_error_irq_handler(struct xe_tile *tile, const u32 master_ctl)
+{
+	enum hardware_error hw_err;
+
+	for (hw_err = 0; hw_err < HARDWARE_ERROR_MAX; hw_err++) {
+		if (master_ctl & XE_ERROR_IRQ(hw_err))
+			xe_hw_error_source_handler(tile, hw_err);
+	}
+}
diff --git a/drivers/gpu/drm/xe/xe_hw_error.h b/drivers/gpu/drm/xe/xe_hw_error.h
new file mode 100644
index 000000000000..c0c05b9130eb
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_hw_error.h
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+#ifndef XE_HW_ERRORS_H_
+#define XE_HW_ERRORS_H_
+
+#include <linux/stddef.h>
+#include <linux/types.h>
+
+/* Error categories reported by hardware */
+enum hardware_error {
+	HARDWARE_ERROR_CORRECTABLE = 0,
+	HARDWARE_ERROR_NONFATAL = 1,
+	HARDWARE_ERROR_FATAL = 2,
+	HARDWARE_ERROR_MAX,
+};
+
+/* Count of  Correctable and Uncorrectable errors reported on tile */
+enum xe_tile_hw_errors {
+	XE_TILE_HW_ERR_GT_FATAL = 0,
+	XE_TILE_HW_ERR_SGGI_FATAL,
+	XE_TILE_HW_ERR_DISPLAY_FATAL,
+	XE_TILE_HW_ERR_SGDI_FATAL,
+	XE_TILE_HW_ERR_SGLI_FATAL,
+	XE_TILE_HW_ERR_SGUNIT_FATAL,
+	XE_TILE_HW_ERR_SGCI_FATAL,
+	XE_TILE_HW_ERR_GSC_FATAL,
+	XE_TILE_HW_ERR_SOC_FATAL,
+	XE_TILE_HW_ERR_MERT_FATAL,
+	XE_TILE_HW_ERR_SGMI_FATAL,
+	XE_TILE_HW_ERR_UNKNOWN_FATAL,
+	XE_TILE_HW_ERR_SGGI_NONFATAL,
+	XE_TILE_HW_ERR_DISPLAY_NONFATAL,
+	XE_TILE_HW_ERR_SGDI_NONFATAL,
+	XE_TILE_HW_ERR_SGLI_NONFATAL,
+	XE_TILE_HW_ERR_GT_NONFATAL,
+	XE_TILE_HW_ERR_SGUNIT_NONFATAL,
+	XE_TILE_HW_ERR_SGCI_NONFATAL,
+	XE_TILE_HW_ERR_GSC_NONFATAL,
+	XE_TILE_HW_ERR_SOC_NONFATAL,
+	XE_TILE_HW_ERR_MERT_NONFATAL,
+	XE_TILE_HW_ERR_SGMI_NONFATAL,
+	XE_TILE_HW_ERR_UNKNOWN_NONFATAL,
+	XE_TILE_HW_ERR_GT_CORR,
+	XE_TILE_HW_ERR_DISPLAY_CORR,
+	XE_TILE_HW_ERR_SGUNIT_CORR,
+	XE_TILE_HW_ERR_GSC_CORR,
+	XE_TILE_HW_ERR_SOC_CORR,
+	XE_TILE_HW_ERR_UNKNOWN_CORR,
+	XE_TILE_HW_ERROR_MAX,
+};
+
+struct err_msg_cntr_pair {
+	const char *errmsg;
+	const u32 cntr_indx;
+};
+
+struct xe_device;
+struct xe_tile;
+
+void xe_hw_error_irq_handler(struct xe_tile *tile, const u32 master_ctl);
+void xe_assign_hw_err_regs(struct xe_device *xe);
+#endif
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index 504cb94d0ee8..68f5f7b6a74e 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -434,6 +434,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
 		xe_mmio_write32(mmio, GFX_MSTR_IRQ, master_ctl);
 
 		gt_irq_handler(tile, master_ctl, intr_dw, identity);
+		xe_hw_error_irq_handler(tile, master_ctl);
 
 		/*
 		 * Display interrupts (including display backlight operations
@@ -591,6 +592,10 @@ int xe_irq_install(struct xe_device *xe)
 		return -EINVAL;
 	}
 
+	xe_assign_hw_err_regs(xe);
+
+	xe->irq.enabled = true;
+
 	xe_irq_reset(xe);
 
 	err = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI | PCI_IRQ_MSIX);
-- 
2.25.1

[Intel-xe] [PATCH 02/11] drm/xe: Log and count the GT hardware errors.

[Himal Prasad Ghimiray]

For the errors reported by GT unit, read the GT error register.
Log and count these errors and clear the error register.

Bspec: 53088, 53089, 53090

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_gt_error_regs.h | 13 +++
 drivers/gpu/drm/xe/xe_device_types.h       |  1 +
 drivers/gpu/drm/xe/xe_gt_types.h           |  7 ++
 drivers/gpu/drm/xe/xe_hw_error.c           | 96 +++++++++++++++++++++-
 drivers/gpu/drm/xe/xe_hw_error.h           | 24 ++++++
 5 files changed, 140 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/xe/regs/xe_gt_error_regs.h

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_error_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_error_regs.h
new file mode 100644
index 000000000000..6180704a6149
--- /dev/null
+++ b/drivers/gpu/drm/xe/regs/xe_gt_error_regs.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+#ifndef XE_GT_ERROR_REGS_H_
+#define XE_GT_ERROR_REGS_H_
+
+#define _ERR_STAT_GT_COR                0x100160
+#define _ERR_STAT_GT_NONFATAL           0x100164
+#define ERR_STAT_GT_REG(x)              XE_REG(_PICK_EVEN((x), \
+						_ERR_STAT_GT_COR, \
+						_ERR_STAT_GT_NONFATAL))
+#endif
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 4d8b0724d1fe..6aa4f4801d81 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -374,6 +374,7 @@ struct xe_device {
 	/** @hardware_errors_regs: list of hw error regs*/
 	struct hardware_errors_regs {
 		const struct err_msg_cntr_pair *dev_err_stat[HARDWARE_ERROR_MAX];
+		const struct err_msg_cntr_pair *err_stat_gt[HARDWARE_ERROR_MAX];
 	} hw_err_regs;
 
 	/* private: */
diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
index d4310be3e1e7..9243cd384c03 100644
--- a/drivers/gpu/drm/xe/xe_gt_types.h
+++ b/drivers/gpu/drm/xe/xe_gt_types.h
@@ -9,10 +9,12 @@
 #include "xe_force_wake_types.h"
 #include "xe_gt_idle_sysfs_types.h"
 #include "xe_hw_engine_types.h"
+#include "xe_hw_error.h"
 #include "xe_hw_fence_types.h"
 #include "xe_reg_sr_types.h"
 #include "xe_sa_types.h"
 #include "xe_uc_types.h"
+#include "regs/xe_gt_error_regs.h"
 
 struct xe_exec_queue_ops;
 struct xe_migrate;
@@ -347,6 +349,11 @@ struct xe_gt {
 		/** @oob: bitmap with active OOB workaroudns */
 		unsigned long *oob;
 	} wa_active;
+
+	/** @gt_hw_errors: hardware errors reported for the gt */
+	struct gt_hw_errors {
+		 unsigned long count[XE_GT_HW_ERROR_MAX];
+	} errors;
 };
 
 #endif
diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
index 357d0f962d91..10aad0c396fb 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.c
+++ b/drivers/gpu/drm/xe/xe_hw_error.c
@@ -118,14 +118,48 @@ static const struct err_msg_cntr_pair dev_err_stat_correctable_reg[] = {
 	[1 ... 31]  =  {"Undefined",		XE_TILE_HW_ERR_UNKNOWN_CORR},
 };
 
+static const struct err_msg_cntr_pair err_stat_gt_fatal_reg[] = {
+	[0]         =  {"Undefined",		XE_GT_HW_ERR_UNKNOWN_FATAL},
+	[1]         =  {"Array BIST",		XE_GT_HW_ERR_ARR_BIST_FATAL},
+	[2]         =  {"Undefined",		XE_GT_HW_ERR_UNKNOWN_FATAL},
+	[3]         =  {"FPU",			XE_GT_HW_ERR_FPU_FATAL},
+	[4]         =  {"L3 Double",		XE_GT_HW_ERR_L3_DOUB_FATAL},
+	[5]         =  {"L3 ECC Checker",	XE_GT_HW_ERR_L3_ECC_CHK_FATAL},
+	[6]         =  {"GUC SRAM",		XE_GT_HW_ERR_GUC_FATAL},
+	[7]         =  {"Undefined",		XE_GT_HW_ERR_UNKNOWN_FATAL},
+	[8]         =  {"IDI PARITY",		XE_GT_HW_ERR_IDI_PAR_FATAL},
+	[9]	    =  {"SQIDI",		XE_GT_HW_ERR_SQIDI_FATAL},
+	[10 ... 11] =  {"Undefined",		XE_GT_HW_ERR_UNKNOWN_FATAL},
+	[12]        =  {"SAMPLER",		XE_GT_HW_ERR_SAMPLER_FATAL},
+	[13]        =  {"SLM",			XE_GT_HW_ERR_SLM_FATAL},
+	[14]        =  {"EU IC",		XE_GT_HW_ERR_EU_IC_FATAL},
+	[15]        =  {"EU GRF",		XE_GT_HW_ERR_EU_GRF_FATAL},
+	[16 ... 31] =  {"Undefined",            XE_GT_HW_ERR_UNKNOWN_FATAL},
+};
+
+static const struct err_msg_cntr_pair err_stat_gt_correctable_reg[] = {
+	[0]         = {"L3 SINGLE",		XE_GT_HW_ERR_L3_SNG_CORR},
+	[1]         = {"SINGLE BIT GUC SRAM",	XE_GT_HW_ERR_GUC_CORR},
+	[2 ... 11]  = {"Undefined",		XE_GT_HW_ERR_UNKNOWN_CORR},
+	[12]        = {"SINGLE BIT SAMPLER",	XE_GT_HW_ERR_SAMPLER_CORR},
+	[13]        = {"SINGLE BIT SLM",	XE_GT_HW_ERR_SLM_CORR},
+	[14]        = {"SINGLE BIT EU IC",	XE_GT_HW_ERR_EU_IC_CORR},
+	[15]        = {"SINGLE BIT EU GRF",	XE_GT_HW_ERR_EU_GRF_CORR},
+	[16 ... 31] = {"Undefined",             XE_GT_HW_ERR_UNKNOWN_CORR},
+};
+
 void xe_assign_hw_err_regs(struct xe_device *xe)
 {
 	const struct err_msg_cntr_pair **dev_err_stat = xe->hw_err_regs.dev_err_stat;
+	const struct err_msg_cntr_pair **err_stat_gt = xe->hw_err_regs.err_stat_gt;
 
 	if (xe->info.platform == XE_DG2) {
 		dev_err_stat[HARDWARE_ERROR_CORRECTABLE] = dg2_err_stat_correctable_reg;
 		dev_err_stat[HARDWARE_ERROR_NONFATAL] = dg2_err_stat_nonfatal_reg;
 		dev_err_stat[HARDWARE_ERROR_FATAL] = dg2_err_stat_fatal_reg;
+
+		err_stat_gt[HARDWARE_ERROR_CORRECTABLE] = err_stat_gt_correctable_reg;
+		err_stat_gt[HARDWARE_ERROR_FATAL] = err_stat_gt_fatal_reg;
 	} else if (xe->info.platform == XE_PVC) {
 		dev_err_stat[HARDWARE_ERROR_CORRECTABLE] = pvc_err_stat_correctable_reg;
 		dev_err_stat[HARDWARE_ERROR_NONFATAL] = pvc_err_stat_nonfatal_reg;
@@ -135,9 +169,67 @@ void xe_assign_hw_err_regs(struct xe_device *xe)
 		dev_err_stat[HARDWARE_ERROR_CORRECTABLE] = dev_err_stat_correctable_reg;
 		dev_err_stat[HARDWARE_ERROR_NONFATAL] = dev_err_stat_nonfatal_reg;
 		dev_err_stat[HARDWARE_ERROR_FATAL] = dev_err_stat_fatal_reg;
+
+		err_stat_gt[HARDWARE_ERROR_CORRECTABLE] = err_stat_gt_correctable_reg;
+		err_stat_gt[HARDWARE_ERROR_FATAL] = err_stat_gt_fatal_reg;
 	}
 }
 
+static void
+xe_gt_hw_error_handler(struct xe_gt *gt, const enum hardware_error hw_err)
+{
+	const char *hw_err_str = hardware_error_type_to_str(hw_err);
+	const struct err_msg_cntr_pair *errstat;
+	struct hardware_errors_regs *err_regs;
+	unsigned long errsrc;
+	const char *errmsg;
+	u32 indx;
+	u32 errbit;
+
+	if (gt_to_xe(gt)->info.platform == XE_PVC)
+		return;
+
+	lockdep_assert_held(&gt_to_xe(gt)->irq.lock);
+	err_regs = &gt_to_xe(gt)->hw_err_regs;
+	errsrc = xe_mmio_read32(gt, ERR_STAT_GT_REG(hw_err));
+	if (!errsrc) {
+		drm_err_ratelimited(&gt_to_xe(gt)->drm, HW_ERR
+				    "GT%d detected ERR_STAT_GT_REG_%s blank!\n",
+				    gt->info.id, hw_err_str);
+		return;
+	}
+
+	drm_info(&gt_to_xe(gt)->drm, HW_ERR "GT%d ERR_STAT_GT_REG_%s=0x%08lx\n",
+		 gt->info.id, hw_err_str, errsrc);
+
+	if (hw_err == HARDWARE_ERROR_NONFATAL) {
+		/*  The GT Non Fatal Error Status Register has only reserved bits
+		 *  Nothing to service.
+		 */
+		drm_err_ratelimited(&gt_to_xe(gt)->drm, HW_ERR "GT%d detected %s error\n",
+				    gt->info.id, hw_err_str);
+		goto clear_reg;
+	}
+
+	errstat = err_regs->err_stat_gt[hw_err];
+	for_each_set_bit(errbit, &errsrc, 32) {
+		errmsg = errstat[errbit].errmsg;
+		indx = errstat[errbit].cntr_indx;
+
+		if (hw_err == HARDWARE_ERROR_FATAL)
+			drm_err_ratelimited(&gt_to_xe(gt)->drm, HW_ERR
+					    "GT%d detected %s %s error, bit[%d] is set\n",
+					    gt->info.id, errmsg, hw_err_str, errbit);
+		else
+			drm_warn(&gt_to_xe(gt)->drm, HW_ERR
+				 "GT%d detected %s %s error, bit[%d] is set\n",
+				 gt->info.id, errmsg, hw_err_str, errbit);
+
+		gt->errors.count[indx]++;
+	}
+clear_reg: xe_mmio_write32(gt, ERR_STAT_GT_REG(hw_err), errsrc);
+}
+
 static void
 xe_hw_error_source_handler(struct xe_tile *tile, const enum hardware_error hw_err)
 {
@@ -174,7 +266,6 @@ xe_hw_error_source_handler(struct xe_tile *tile, const enum hardware_error hw_er
 			drm_warn(&tile_to_xe(tile)->drm,
 				 HW_ERR "TILE%d detected %s %s error, bit[%d] is set\n",
 				 tile->id, errmsg, hw_err_str, errbit);
-
 		else
 			drm_err_ratelimited(&tile_to_xe(tile)->drm,
 					    HW_ERR "TILE%d detected %s %s error, bit[%d] is set\n",
@@ -182,6 +273,9 @@ xe_hw_error_source_handler(struct xe_tile *tile, const enum hardware_error hw_er
 		tile->errors.count[indx]++;
 	}
 
+	if (errsrc & REG_BIT(0))
+		xe_gt_hw_error_handler(tile->primary_gt, hw_err);
+
 	xe_mmio_write32(mmio, DEV_ERR_STAT_REG(hw_err), errsrc);
 unlock:
 	spin_unlock_irqrestore(&tile_to_xe(tile)->irq.lock, flags);
diff --git a/drivers/gpu/drm/xe/xe_hw_error.h b/drivers/gpu/drm/xe/xe_hw_error.h
index c0c05b9130eb..82c947247c27 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.h
+++ b/drivers/gpu/drm/xe/xe_hw_error.h
@@ -51,6 +51,30 @@ enum xe_tile_hw_errors {
 	XE_TILE_HW_ERROR_MAX,
 };
 
+/* Count of GT Correctable and FATAL HW ERRORS */
+enum xe_gt_hw_errors {
+	XE_GT_HW_ERR_L3_SNG_CORR,
+	XE_GT_HW_ERR_GUC_CORR,
+	XE_GT_HW_ERR_SAMPLER_CORR,
+	XE_GT_HW_ERR_SLM_CORR,
+	XE_GT_HW_ERR_EU_IC_CORR,
+	XE_GT_HW_ERR_EU_GRF_CORR,
+	XE_GT_HW_ERR_UNKNOWN_CORR,
+	XE_GT_HW_ERR_ARR_BIST_FATAL,
+	XE_GT_HW_ERR_FPU_FATAL,
+	XE_GT_HW_ERR_L3_DOUB_FATAL,
+	XE_GT_HW_ERR_L3_ECC_CHK_FATAL,
+	XE_GT_HW_ERR_GUC_FATAL,
+	XE_GT_HW_ERR_IDI_PAR_FATAL,
+	XE_GT_HW_ERR_SQIDI_FATAL,
+	XE_GT_HW_ERR_SAMPLER_FATAL,
+	XE_GT_HW_ERR_SLM_FATAL,
+	XE_GT_HW_ERR_EU_IC_FATAL,
+	XE_GT_HW_ERR_EU_GRF_FATAL,
+	XE_GT_HW_ERR_UNKNOWN_FATAL,
+	XE_GT_HW_ERROR_MAX,
+};
+
 struct err_msg_cntr_pair {
 	const char *errmsg;
 	const u32 cntr_indx;
-- 
2.25.1

[Intel-xe] [PATCH 03/11] drm/xe: Support GT hardware error reporting for PVC.

[Himal Prasad Ghimiray]

PVC supports GT error reporting via vector registers alongwith
error status register. Add support to report these errors and
update respective counters.
Incase of Subslice error reported by vector register, process the
error status register for applicable bits.

Bspec: 54179, 54177, 53088, 53089

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_gt_error_regs.h |  16 +++
 drivers/gpu/drm/xe/xe_hw_error.c           | 122 ++++++++++++++++++++-
 drivers/gpu/drm/xe/xe_hw_error.h           |  20 ++++
 3 files changed, 154 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_error_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_error_regs.h
index 6180704a6149..39ea87914465 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_error_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_error_regs.h
@@ -10,4 +10,20 @@
 #define ERR_STAT_GT_REG(x)              XE_REG(_PICK_EVEN((x), \
 						_ERR_STAT_GT_COR, \
 						_ERR_STAT_GT_NONFATAL))
+
+#define _ERR_STAT_GT_COR_VCTR_0         0x1002a0
+#define _ERR_STAT_GT_COR_VCTR_1         0x1002a4
+#define ERR_STAT_GT_COR_VCTR_REG(x)     XE_REG(_PICK_EVEN((x), \
+						_ERR_STAT_GT_COR_VCTR_0, \
+						_ERR_STAT_GT_COR_VCTR_1))
+
+#define _ERR_STAT_GT_FATAL_VCTR_0       0x100260
+#define _ERR_STAT_GT_FATAL_VCTR_1       0x100264
+#define ERR_STAT_GT_FATAL_VCTR_REG(x)   XE_REG(_PICK_EVEN((x), \
+						_ERR_STAT_GT_FATAL_VCTR_0, \
+						_ERR_STAT_GT_FATAL_VCTR_1))
+
+#define ERR_STAT_GT_VCTR_REG(hw_err, x) (hw_err == HARDWARE_ERROR_CORRECTABLE ? \
+						ERR_STAT_GT_COR_VCTR_REG(x) : \
+						ERR_STAT_GT_FATAL_VCTR_REG(x))
 #endif
diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
index 10aad0c396fb..deb020a509d2 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.c
+++ b/drivers/gpu/drm/xe/xe_hw_error.c
@@ -148,6 +148,41 @@ static const struct err_msg_cntr_pair err_stat_gt_correctable_reg[] = {
 	[16 ... 31] = {"Undefined",             XE_GT_HW_ERR_UNKNOWN_CORR},
 };
 
+static const struct err_msg_cntr_pair pvc_err_stat_gt_fatal_reg[] = {
+	[0 ... 2]   =  {"Undefined",		XE_GT_HW_ERR_UNKNOWN_FATAL},
+	[3]         =  {"FPU",			XE_GT_HW_ERR_FPU_FATAL},
+	[4 ... 5]   =  {"Undefined",            XE_GT_HW_ERR_UNKNOWN_FATAL},
+	[6]         =  {"GUC SRAM",		XE_GT_HW_ERR_GUC_FATAL},
+	[7 ... 12]  =  {"Undefined",		XE_GT_HW_ERR_UNKNOWN_FATAL},
+	[13]        =  {"SLM",			XE_GT_HW_ERR_SLM_FATAL},
+	[14]        =  {"Undefined",		XE_GT_HW_ERR_UNKNOWN_FATAL},
+	[15]        =  {"EU GRF",		XE_GT_HW_ERR_EU_GRF_FATAL},
+	[16 ... 31] =  {"Undefined",            XE_GT_HW_ERR_UNKNOWN_FATAL},
+};
+
+static const struct err_msg_cntr_pair pvc_err_stat_gt_correctable_reg[] = {
+	[0]         = {"Undefined",             XE_GT_HW_ERR_UNKNOWN_CORR},
+	[1]         = {"SINGLE BIT GUC SRAM",	XE_GT_HW_ERR_GUC_CORR},
+	[2 ... 12]  = {"Undefined",		XE_GT_HW_ERR_UNKNOWN_CORR},
+	[13]        = {"SINGLE BIT SLM",	XE_GT_HW_ERR_SLM_CORR},
+	[14]        = {"SINGLE BIT EU IC",	XE_GT_HW_ERR_EU_IC_CORR},
+	[15]        = {"SINGLE BIT EU GRF",	XE_GT_HW_ERR_EU_GRF_CORR},
+	[16 ... 31] = {"Undefined",             XE_GT_HW_ERR_UNKNOWN_CORR},
+};
+
+static const struct err_msg_cntr_pair err_stat_gt_fatal_vectr_reg[] = {
+	[0 ... 1]         = {"SUBSLICE",	XE_GT_HW_ERR_SUBSLICE_FATAL},
+	[2 ... 3]         = {"L3BANK",		XE_GT_HW_ERR_L3BANK_FATAL},
+	[4 ... 5]         = {"Undefined",	XE_GT_HW_ERR_UNKNOWN_FATAL},
+	[6]               = {"TLB",		XE_GT_HW_ERR_TLB_FATAL},
+	[7]               = {"L3 FABRIC",	XE_GT_HW_ERR_L3_FABRIC_FATAL},
+};
+
+static const struct err_msg_cntr_pair err_stat_gt_correctable_vectr_reg[] = {
+	[0 ... 1]         = {"SUBSLICE",	XE_GT_HW_ERR_SUBSLICE_CORR},
+	[2 ... 3]         = {"L3BANK",		XE_GT_HW_ERR_L3BANK_CORR},
+};
+
 void xe_assign_hw_err_regs(struct xe_device *xe)
 {
 	const struct err_msg_cntr_pair **dev_err_stat = xe->hw_err_regs.dev_err_stat;
@@ -164,6 +199,8 @@ void xe_assign_hw_err_regs(struct xe_device *xe)
 		dev_err_stat[HARDWARE_ERROR_CORRECTABLE] = pvc_err_stat_correctable_reg;
 		dev_err_stat[HARDWARE_ERROR_NONFATAL] = pvc_err_stat_nonfatal_reg;
 		dev_err_stat[HARDWARE_ERROR_FATAL] = pvc_err_stat_fatal_reg;
+		err_stat_gt[HARDWARE_ERROR_CORRECTABLE] = pvc_err_stat_gt_correctable_reg;
+		err_stat_gt[HARDWARE_ERROR_FATAL] = pvc_err_stat_gt_fatal_reg;
 	} else {
 		/* For other platforms report only GT errors */
 		dev_err_stat[HARDWARE_ERROR_CORRECTABLE] = dev_err_stat_correctable_reg;
@@ -176,7 +213,7 @@ void xe_assign_hw_err_regs(struct xe_device *xe)
 }
 
 static void
-xe_gt_hw_error_handler(struct xe_gt *gt, const enum hardware_error hw_err)
+xe_gt_hw_error_status_reg_handler(struct xe_gt *gt, const enum hardware_error hw_err)
 {
 	const char *hw_err_str = hardware_error_type_to_str(hw_err);
 	const struct err_msg_cntr_pair *errstat;
@@ -186,9 +223,6 @@ xe_gt_hw_error_handler(struct xe_gt *gt, const enum hardware_error hw_err)
 	u32 indx;
 	u32 errbit;
 
-	if (gt_to_xe(gt)->info.platform == XE_PVC)
-		return;
-
 	lockdep_assert_held(&gt_to_xe(gt)->irq.lock);
 	err_regs = &gt_to_xe(gt)->hw_err_regs;
 	errsrc = xe_mmio_read32(gt, ERR_STAT_GT_REG(hw_err));
@@ -230,6 +264,86 @@ xe_gt_hw_error_handler(struct xe_gt *gt, const enum hardware_error hw_err)
 clear_reg: xe_mmio_write32(gt, ERR_STAT_GT_REG(hw_err), errsrc);
 }
 
+static void
+xe_gt_hw_error_vectr_reg_handler(struct xe_gt *gt, const enum hardware_error hw_err)
+{
+	const char *hw_err_str = hardware_error_type_to_str(hw_err);
+	const struct err_msg_cntr_pair *errvctr;
+	const char *errmsg;
+	bool errstat_read;
+	u32 num_vctr_reg;
+	u32 indx;
+	u32 vctr;
+	u32 i;
+
+	switch (hw_err) {
+	case HARDWARE_ERROR_FATAL:
+		num_vctr_reg = ERR_STAT_GT_FATAL_VCTR_LEN;
+		errvctr = err_stat_gt_fatal_vectr_reg;
+		break;
+	case HARDWARE_ERROR_NONFATAL:
+		/*  The GT Non Fatal Error Status Register has only reserved bits
+		 *  Nothing to service.
+		 */
+		drm_err_ratelimited(&gt_to_xe(gt)->drm, HW_ERR "GT%d detected %s error\n",
+				    gt->info.id, hw_err_str);
+		return;
+	case HARDWARE_ERROR_CORRECTABLE:
+		num_vctr_reg = ERR_STAT_GT_COR_VCTR_LEN;
+		errvctr = err_stat_gt_correctable_vectr_reg;
+		break;
+	default:
+		return;
+	}
+
+	errstat_read = false;
+
+	for (i = 0 ; i < num_vctr_reg; i++) {
+		vctr = xe_mmio_read32(gt, ERR_STAT_GT_VCTR_REG(hw_err, i));
+		if (!vctr)
+			continue;
+
+		errmsg = errvctr[i].errmsg;
+		indx = errvctr[i].cntr_indx;
+
+		if (hw_err == HARDWARE_ERROR_FATAL)
+			drm_err_ratelimited(&gt_to_xe(gt)->drm, HW_ERR
+					    "GT%d detected %s %s error. ERR_VECT_GT_%s[%d]:0x%08x\n",
+					    gt->info.id, errmsg, hw_err_str, hw_err_str, i, vctr);
+		else
+			drm_warn(&gt_to_xe(gt)->drm, HW_ERR
+				 "GT%d detected %s %s error. ERR_VECT_GT_%s[%d]:0x%08x\n",
+				 gt->info.id, errmsg, hw_err_str, hw_err_str, i, vctr);
+
+		if (i < ERR_STAT_GT_VCTR4)
+			gt->errors.count[indx] += hweight32(vctr);
+
+		if (i == ERR_STAT_GT_VCTR6)
+			gt->errors.count[indx] += hweight16(vctr);
+
+		if (i == ERR_STAT_GT_VCTR7)
+			gt->errors.count[indx] += hweight8(vctr);
+
+		if (i < ERR_STAT_GT_VCTR2 && !errstat_read) {
+			xe_gt_hw_error_status_reg_handler(gt, hw_err);
+			errstat_read = true;
+		}
+
+		xe_mmio_write32(gt, ERR_STAT_GT_VCTR_REG(hw_err, i), vctr);
+	}
+}
+
+static void
+xe_gt_hw_error_handler(struct xe_gt *gt, const enum hardware_error hw_err)
+{
+	lockdep_assert_held(&gt_to_xe(gt)->irq.lock);
+
+	if (gt_to_xe(gt)->info.platform == XE_PVC)
+		xe_gt_hw_error_vectr_reg_handler(gt, hw_err);
+	else
+		xe_gt_hw_error_status_reg_handler(gt, hw_err);
+}
+
 static void
 xe_hw_error_source_handler(struct xe_tile *tile, const enum hardware_error hw_err)
 {
diff --git a/drivers/gpu/drm/xe/xe_hw_error.h b/drivers/gpu/drm/xe/xe_hw_error.h
index 82c947247c27..3fcbbcc338fe 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.h
+++ b/drivers/gpu/drm/xe/xe_hw_error.h
@@ -51,8 +51,21 @@ enum xe_tile_hw_errors {
 	XE_TILE_HW_ERROR_MAX,
 };
 
+enum gt_vctr_registers {
+	ERR_STAT_GT_VCTR0 = 0,
+	ERR_STAT_GT_VCTR1,
+	ERR_STAT_GT_VCTR2,
+	ERR_STAT_GT_VCTR3,
+	ERR_STAT_GT_VCTR4,
+	ERR_STAT_GT_VCTR5,
+	ERR_STAT_GT_VCTR6,
+	ERR_STAT_GT_VCTR7,
+};
+
 /* Count of GT Correctable and FATAL HW ERRORS */
 enum xe_gt_hw_errors {
+	XE_GT_HW_ERR_SUBSLICE_CORR,
+	XE_GT_HW_ERR_L3BANK_CORR,
 	XE_GT_HW_ERR_L3_SNG_CORR,
 	XE_GT_HW_ERR_GUC_CORR,
 	XE_GT_HW_ERR_SAMPLER_CORR,
@@ -60,6 +73,8 @@ enum xe_gt_hw_errors {
 	XE_GT_HW_ERR_EU_IC_CORR,
 	XE_GT_HW_ERR_EU_GRF_CORR,
 	XE_GT_HW_ERR_UNKNOWN_CORR,
+	XE_GT_HW_ERR_SUBSLICE_FATAL,
+	XE_GT_HW_ERR_L3BANK_FATAL,
 	XE_GT_HW_ERR_ARR_BIST_FATAL,
 	XE_GT_HW_ERR_FPU_FATAL,
 	XE_GT_HW_ERR_L3_DOUB_FATAL,
@@ -71,10 +86,15 @@ enum xe_gt_hw_errors {
 	XE_GT_HW_ERR_SLM_FATAL,
 	XE_GT_HW_ERR_EU_IC_FATAL,
 	XE_GT_HW_ERR_EU_GRF_FATAL,
+	XE_GT_HW_ERR_TLB_FATAL,
+	XE_GT_HW_ERR_L3_FABRIC_FATAL,
 	XE_GT_HW_ERR_UNKNOWN_FATAL,
 	XE_GT_HW_ERROR_MAX,
 };
 
+#define ERR_STAT_GT_COR_VCTR_LEN (4)
+#define ERR_STAT_GT_FATAL_VCTR_LEN (8)
+
 struct err_msg_cntr_pair {
 	const char *errmsg;
 	const u32 cntr_indx;
-- 
2.25.1

[Intel-xe] [PATCH 04/11] drm/xe: Process fatal hardware errors.

[Himal Prasad Ghimiray]

Fatal errors are reported as PCIe errors. When a PCIe error is asserted,
the OS will perform a device warm reset which causes the driver to reload.
The error registers are sticky and the values are maintained through a
warm reset. We read these registers during the boot flow of the driver and
increment the respective error counters.

Bspec: 53076

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_regs.h |  3 +++
 drivers/gpu/drm/xe/xe_hw_error.c  | 37 ++++++++++++++++++++++++++++++-
 drivers/gpu/drm/xe/xe_hw_error.h  |  3 ++-
 drivers/gpu/drm/xe/xe_irq.c       |  2 +-
 4 files changed, 42 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h
index 863df80d69bf..68bdb218bbe0 100644
--- a/drivers/gpu/drm/xe/regs/xe_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_regs.h
@@ -93,5 +93,8 @@
 #define   GT_DW_IRQ(x)				REG_BIT(x)
 #define   XE_ERROR_IRQ(x)			REG_BIT(26 + (x))
 
+#define DEV_PCIEERR_STATUS			XE_REG(0x100180)
+#define   DEV_PCIEERR_IS_FATAL(x)		REG_BIT(x * 4 + 2)
+
 #define PVC_RP_STATE_CAP			XE_REG(0x281014)
 #endif
diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
index deb020a509d2..9595e3369656 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.c
+++ b/drivers/gpu/drm/xe/xe_hw_error.c
@@ -183,7 +183,7 @@ static const struct err_msg_cntr_pair err_stat_gt_correctable_vectr_reg[] = {
 	[2 ... 3]         = {"L3BANK",		XE_GT_HW_ERR_L3BANK_CORR},
 };
 
-void xe_assign_hw_err_regs(struct xe_device *xe)
+static void xe_assign_hw_err_regs(struct xe_device *xe)
 {
 	const struct err_msg_cntr_pair **dev_err_stat = xe->hw_err_regs.dev_err_stat;
 	const struct err_msg_cntr_pair **err_stat_gt = xe->hw_err_regs.err_stat_gt;
@@ -417,3 +417,38 @@ xe_hw_error_irq_handler(struct xe_tile *tile, const u32 master_ctl)
 			xe_hw_error_source_handler(tile, hw_err);
 	}
 }
+
+/**
+ * process_hw_errors - checks for the occurrence of HW errors
+ *
+ * This checks for the HW Errors including FATAL errors that might
+ * have occurred in the previous boot of the driver which will
+ * initiate PCIe FLR reset of the device and cause the
+ * driver to reload.
+ */
+void xe_process_hw_errors(struct xe_device *xe)
+{
+	struct xe_tile *root_tile = xe_device_get_root_tile(xe);
+	struct xe_gt *root_mmio = root_tile->primary_gt;
+
+	u32 dev_pcieerr_status, master_ctl;
+	struct xe_tile *tile;
+	int i;
+
+	xe_assign_hw_err_regs(xe);
+
+	dev_pcieerr_status = xe_mmio_read32(root_mmio, DEV_PCIEERR_STATUS);
+
+	for_each_tile(tile, xe, i) {
+		struct xe_gt *mmio = tile->primary_gt;
+
+		if (dev_pcieerr_status & DEV_PCIEERR_IS_FATAL(i))
+			xe_hw_error_source_handler(tile, HARDWARE_ERROR_FATAL);
+
+		master_ctl = xe_mmio_read32(mmio, GFX_MSTR_IRQ);
+		xe_hw_error_irq_handler(tile, master_ctl);
+		xe_mmio_write32(mmio, GFX_MSTR_IRQ, master_ctl);
+	}
+	if (dev_pcieerr_status)
+		xe_mmio_write32(root_mmio, DEV_PCIEERR_STATUS, dev_pcieerr_status);
+}
diff --git a/drivers/gpu/drm/xe/xe_hw_error.h b/drivers/gpu/drm/xe/xe_hw_error.h
index 3fcbbcc338fe..2812407dd4bf 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.h
+++ b/drivers/gpu/drm/xe/xe_hw_error.h
@@ -104,5 +104,6 @@ struct xe_device;
 struct xe_tile;
 
 void xe_hw_error_irq_handler(struct xe_tile *tile, const u32 master_ctl);
-void xe_assign_hw_err_regs(struct xe_device *xe);
+void xe_process_hw_errors(struct xe_device *xe);
+
 #endif
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index 68f5f7b6a74e..06c9b43e2c71 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -592,7 +592,7 @@ int xe_irq_install(struct xe_device *xe)
 		return -EINVAL;
 	}
 
-	xe_assign_hw_err_regs(xe);
+	xe_process_hw_errors(xe);
 
 	xe->irq.enabled = true;
 
-- 
2.25.1

[Intel-xe] [PATCH 05/11] drm/xe: Support GSC hardware error reporting for PVC.

[Himal Prasad Ghimiray]

Add support to report GSC hw errors and counter update in case
of correctable errors.

Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_tile_error_regs.h |  8 ++
 drivers/gpu/drm/xe/xe_hw_error.c             | 96 +++++++++++++++++++-
 drivers/gpu/drm/xe/xe_hw_error.h             | 16 ++++
 3 files changed, 117 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
index db78d6687213..fa16eaf9436b 100644
--- a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
@@ -12,4 +12,12 @@
 #define DEV_ERR_STAT_REG(x)                            XE_REG(_PICK_EVEN((x), \
 								_DEV_ERR_STAT_CORRECTABLE, \
 								_DEV_ERR_STAT_NONFATAL))
+
+#define PVC_GSC_HECI1_BASE                             0x00284000
+#define PVC_GSC_HECI2_BASE                             0x00285000
+#define _GSC_HEC_CORR_ERR_STATUS                       0x128
+#define _GSC_HEC_UNCOR_ERR_STATUS                     0x118
+#define GSC_HEC_ERR_STAT_REG(base, x)                  XE_REG(_PICK_EVEN((x), \
+								(base) + _GSC_HEC_CORR_ERR_STATUS, \
+								(base) + _GSC_HEC_UNCOR_ERR_STATUS))
 #endif
diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
index 9595e3369656..eb76b8e6a338 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.c
+++ b/drivers/gpu/drm/xe/xe_hw_error.c
@@ -183,6 +183,28 @@ static const struct err_msg_cntr_pair err_stat_gt_correctable_vectr_reg[] = {
 	[2 ... 3]         = {"L3BANK",		XE_GT_HW_ERR_L3BANK_CORR},
 };
 
+static const struct err_msg_cntr_pair gsc_nonfatal_err_reg[] = {
+	[0]         = {"MinuteIA Unexpected Shutdown",		XE_GSC_HW_ERR_MIA_SHUTDOWN_UNCOR},
+	[1]         = {"MinuteIA Internal Error",		XE_GSC_HW_ERR_MIA_INTERNAL_UNCOR},
+	[2]         = {"Double bit error on SRAM",		XE_GSC_HW_ERR_SRAM_UNCOR},
+	[3]         = {"WDT 2nd Timeout",			XE_GSC_HW_ERR_WDG_UNCOR},
+	[4]         = {"ROM has a parity error",		XE_GSC_HW_ERR_ROM_PARITY_UNCOR},
+	[5]         = {"Ucode has a parity error",		XE_GSC_HW_ERR_UCODE_PARITY_UNCOR},
+	[6]         = {"Errors Reported to and Detected by FW",	XE_GSC_HW_ERR_FW_UNCOR},
+	[7]         = {"Glitch is detected on voltage rail",	XE_GSC_HW_ERR_VLT_GLITCH_UNCOR},
+	[8]         = {"Fuse Pull Error",			XE_GSC_HW_ERR_FUSE_PULL_UNCOR},
+	[9]         = {"Fuse CRC Check Failed on Fuse Pull",	XE_GSC_HW_ERR_FUSE_CRC_UNCOR},
+	[10]        = {"Self Mbist Failed",			XE_GSC_HW_ERR_SELF_MBIST_UNCOR},
+	[11]        = {"AON RF has parity error",		XE_GSC_HW_ERR_AON_RF_PARITY_UNCOR},
+	[12 ... 31] = {"Undefined",				XE_GSC_HW_ERR_UNKNOWN_UNCOR},
+};
+
+static const struct err_msg_cntr_pair gsc_correctable_err_reg[] = {
+	[0]        = {"Single bit error on SRAM",			XE_GSC_HW_ERR_SRAM_CORR},
+	[1]        = {"Errors Reported to FW and Detected by FW",	XE_GSC_HW_ERR_FW_CORR},
+	[2 ... 31] = {"Undefined",					XE_GSC_HW_ERR_UNKNOWN_CORR},
+};
+
 static void xe_assign_hw_err_regs(struct xe_device *xe)
 {
 	const struct err_msg_cntr_pair **dev_err_stat = xe->hw_err_regs.dev_err_stat;
@@ -344,6 +366,71 @@ xe_gt_hw_error_handler(struct xe_gt *gt, const enum hardware_error hw_err)
 		xe_gt_hw_error_status_reg_handler(gt, hw_err);
 }
 
+static void
+xe_gsc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
+{
+	const char *hw_err_str = hardware_error_type_to_str(hw_err);
+	const struct err_msg_cntr_pair *errstat;
+	struct xe_gt *mmio;
+	unsigned long errsrc;
+	const char *errmsg;
+	u32 indx;
+	u32 errbit;
+	u32 base;
+
+	if ((tile_to_xe(tile)->info.platform != XE_PVC))
+		return;
+
+	/* GSC errors are valid only on root tile and for NONFATAL and
+	 * CORRECTABLE type.For non root tiles or FATAL type it should
+	 * be categorized as undefined GSC HARDWARE ERROR
+	 */
+	base = PVC_GSC_HECI1_BASE;
+
+	if (tile->id || hw_err == HARDWARE_ERROR_FATAL) {
+		drm_err_ratelimited(&tile_to_xe(tile)->drm, HW_ERR
+				    "Undefined GSC %s error on tile%d\n", hw_err_str, tile->id);
+		return;
+	}
+
+	lockdep_assert_held(&tile_to_xe(tile)->irq.lock);
+	if (hw_err == HARDWARE_ERROR_CORRECTABLE)
+		errstat = gsc_correctable_err_reg;
+	else
+		errstat = gsc_nonfatal_err_reg;
+
+	mmio = tile->primary_gt;
+	errsrc = xe_mmio_read32(mmio, GSC_HEC_ERR_STAT_REG(base, hw_err));
+	if (!errsrc) {
+		drm_err_ratelimited(&tile_to_xe(tile)->drm, HW_ERR
+				    "GSC detected GSC_HEC_ERR_STAT_REG_%s blank!\n",  hw_err_str);
+		goto clear_reg;
+	}
+
+	drm_info(&tile_to_xe(tile)->drm, HW_ERR
+		 "GSC_HEC_ERR_STAT_REG_%s=0x%08lx\n", hw_err_str, errsrc);
+
+	for_each_set_bit(errbit, &errsrc, 32) {
+		errmsg = errstat[errbit].errmsg;
+		indx = errstat[errbit].cntr_indx;
+
+		if (hw_err == HARDWARE_ERROR_CORRECTABLE) {
+			drm_warn(&tile_to_xe(tile)->drm,
+				 HW_ERR "GSC detected %s %s error, bit[%d] is set\n",
+				 errmsg, hw_err_str, errbit);
+
+		} else {
+			drm_err_ratelimited(&tile_to_xe(tile)->drm,
+					    HW_ERR "GSC detected %s %s error, bit[%d] is set\n",
+					    errmsg, hw_err_str, errbit);
+		}
+		tile->errors.count[indx]++;
+	}
+
+clear_reg:
+	xe_mmio_write32(mmio, GSC_HEC_ERR_STAT_REG(base, hw_err), errsrc);
+}
+
 static void
 xe_hw_error_source_handler(struct xe_tile *tile, const enum hardware_error hw_err)
 {
@@ -385,10 +472,13 @@ xe_hw_error_source_handler(struct xe_tile *tile, const enum hardware_error hw_er
 					    HW_ERR "TILE%d detected %s %s error, bit[%d] is set\n",
 					    tile->id, errmsg, hw_err_str, errbit);
 		tile->errors.count[indx]++;
-	}
 
-	if (errsrc & REG_BIT(0))
-		xe_gt_hw_error_handler(tile->primary_gt, hw_err);
+		if (errbit == 0)
+			xe_gt_hw_error_handler(tile->primary_gt, hw_err);
+
+		if (errbit == 8)
+			xe_gsc_hw_error_handler(tile, hw_err);
+	}
 
 	xe_mmio_write32(mmio, DEV_ERR_STAT_REG(hw_err), errsrc);
 unlock:
diff --git a/drivers/gpu/drm/xe/xe_hw_error.h b/drivers/gpu/drm/xe/xe_hw_error.h
index 2812407dd4bf..155722a0af4c 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.h
+++ b/drivers/gpu/drm/xe/xe_hw_error.h
@@ -48,6 +48,22 @@ enum xe_tile_hw_errors {
 	XE_TILE_HW_ERR_GSC_CORR,
 	XE_TILE_HW_ERR_SOC_CORR,
 	XE_TILE_HW_ERR_UNKNOWN_CORR,
+	XE_GSC_HW_ERR_SRAM_CORR,
+	XE_GSC_HW_ERR_FW_CORR,
+	XE_GSC_HW_ERR_UNKNOWN_CORR,
+	XE_GSC_HW_ERR_MIA_SHUTDOWN_UNCOR,
+	XE_GSC_HW_ERR_MIA_INTERNAL_UNCOR,
+	XE_GSC_HW_ERR_SRAM_UNCOR,
+	XE_GSC_HW_ERR_WDG_UNCOR,
+	XE_GSC_HW_ERR_ROM_PARITY_UNCOR,
+	XE_GSC_HW_ERR_UCODE_PARITY_UNCOR,
+	XE_GSC_HW_ERR_FW_UNCOR,
+	XE_GSC_HW_ERR_VLT_GLITCH_UNCOR,
+	XE_GSC_HW_ERR_FUSE_PULL_UNCOR,
+	XE_GSC_HW_ERR_FUSE_CRC_UNCOR,
+	XE_GSC_HW_ERR_SELF_MBIST_UNCOR,
+	XE_GSC_HW_ERR_AON_RF_PARITY_UNCOR,
+	XE_GSC_HW_ERR_UNKNOWN_UNCOR,
 	XE_TILE_HW_ERROR_MAX,
 };
 
-- 
2.25.1

Re: [Intel-xe] [PATCH 05/11] drm/xe: Support GSC hardware error reporting for PVC.

[Aravind Iddamsetty]

On 27/09/23 17:16, Himal Prasad Ghimiray wrote:
> Add support to report GSC hw errors and counter update in case
> of correctable errors.
>
> Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_tile_error_regs.h |  8 ++
>  drivers/gpu/drm/xe/xe_hw_error.c             | 96 +++++++++++++++++++-
>  drivers/gpu/drm/xe/xe_hw_error.h             | 16 ++++
>  3 files changed, 117 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
> index db78d6687213..fa16eaf9436b 100644
> --- a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
> @@ -12,4 +12,12 @@
>  #define DEV_ERR_STAT_REG(x)                            XE_REG(_PICK_EVEN((x), \
>  								_DEV_ERR_STAT_CORRECTABLE, \
>  								_DEV_ERR_STAT_NONFATAL))
> +
> +#define PVC_GSC_HECI1_BASE                             0x00284000
> +#define PVC_GSC_HECI2_BASE                             0x00285000
please maintain the order of register definition as per address in this file.
> +#define _GSC_HEC_CORR_ERR_STATUS                       0x128
> +#define _GSC_HEC_UNCOR_ERR_STATUS                     0x118
> +#define GSC_HEC_ERR_STAT_REG(base, x)                  XE_REG(_PICK_EVEN((x), \
> +								(base) + _GSC_HEC_CORR_ERR_STATUS, \
> +								(base) + _GSC_HEC_UNCOR_ERR_STATUS))
>  #endif
> diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
> index 9595e3369656..eb76b8e6a338 100644
> --- a/drivers/gpu/drm/xe/xe_hw_error.c
> +++ b/drivers/gpu/drm/xe/xe_hw_error.c
> @@ -183,6 +183,28 @@ static const struct err_msg_cntr_pair err_stat_gt_correctable_vectr_reg[] = {
>  	[2 ... 3]         = {"L3BANK",		XE_GT_HW_ERR_L3BANK_CORR},
>  };
>  
> +static const struct err_msg_cntr_pair gsc_nonfatal_err_reg[] = {
> +	[0]         = {"MinuteIA Unexpected Shutdown",		XE_GSC_HW_ERR_MIA_SHUTDOWN_UNCOR},
> +	[1]         = {"MinuteIA Internal Error",		XE_GSC_HW_ERR_MIA_INTERNAL_UNCOR},
> +	[2]         = {"Double bit error on SRAM",		XE_GSC_HW_ERR_SRAM_UNCOR},
> +	[3]         = {"WDT 2nd Timeout",			XE_GSC_HW_ERR_WDG_UNCOR},
> +	[4]         = {"ROM has a parity error",		XE_GSC_HW_ERR_ROM_PARITY_UNCOR},
> +	[5]         = {"Ucode has a parity error",		XE_GSC_HW_ERR_UCODE_PARITY_UNCOR},
> +	[6]         = {"Errors Reported to and Detected by FW",	XE_GSC_HW_ERR_FW_UNCOR},
> +	[7]         = {"Glitch is detected on voltage rail",	XE_GSC_HW_ERR_VLT_GLITCH_UNCOR},
> +	[8]         = {"Fuse Pull Error",			XE_GSC_HW_ERR_FUSE_PULL_UNCOR},
> +	[9]         = {"Fuse CRC Check Failed on Fuse Pull",	XE_GSC_HW_ERR_FUSE_CRC_UNCOR},
> +	[10]        = {"Self Mbist Failed",			XE_GSC_HW_ERR_SELF_MBIST_UNCOR},
> +	[11]        = {"AON RF has parity error",		XE_GSC_HW_ERR_AON_RF_PARITY_UNCOR},
> +	[12 ... 31] = {"Undefined",				XE_GSC_HW_ERR_UNKNOWN_UNCOR},
> +};
> +
> +static const struct err_msg_cntr_pair gsc_correctable_err_reg[] = {
> +	[0]        = {"Single bit error on SRAM",			XE_GSC_HW_ERR_SRAM_CORR},
> +	[1]        = {"Errors Reported to FW and Detected by FW",	XE_GSC_HW_ERR_FW_CORR},
> +	[2 ... 31] = {"Undefined",					XE_GSC_HW_ERR_UNKNOWN_CORR},
> +};
> +
>  static void xe_assign_hw_err_regs(struct xe_device *xe)
>  {
>  	const struct err_msg_cntr_pair **dev_err_stat = xe->hw_err_regs.dev_err_stat;
> @@ -344,6 +366,71 @@ xe_gt_hw_error_handler(struct xe_gt *gt, const enum hardware_error hw_err)
>  		xe_gt_hw_error_status_reg_handler(gt, hw_err);
>  }
>  
> +static void
> +xe_gsc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
> +{
> +	const char *hw_err_str = hardware_error_type_to_str(hw_err);
> +	const struct err_msg_cntr_pair *errstat;
> +	struct xe_gt *mmio;
better name this as gt, as it really holds a struct xe_gt and not a struct mmio in tile
> +	unsigned long errsrc;
> +	const char *errmsg;
> +	u32 indx;
> +	u32 errbit;
> +	u32 base;
> +
> +	if ((tile_to_xe(tile)->info.platform != XE_PVC))
> +		return;
> +
> +	/* GSC errors are valid only on root tile and for NONFATAL and
> +	 * CORRECTABLE type.For non root tiles or FATAL type it should
> +	 * be categorized as undefined GSC HARDWARE ERROR
> +	 */
> +	base = PVC_GSC_HECI1_BASE;
> +
> +	if (tile->id || hw_err == HARDWARE_ERROR_FATAL) {
> +		drm_err_ratelimited(&tile_to_xe(tile)->drm, HW_ERR
> +				    "Undefined GSC %s error on tile%d\n", hw_err_str, tile->id);
> +		return;
> +	}
> +
> +	lockdep_assert_held(&tile_to_xe(tile)->irq.lock);
> +	if (hw_err == HARDWARE_ERROR_CORRECTABLE)
> +		errstat = gsc_correctable_err_reg;
> +	else
> +		errstat = gsc_nonfatal_err_reg;
let's have one common design of initializing all error registers at once during driver load.
> +
> +	mmio = tile->primary_gt;
> +	errsrc = xe_mmio_read32(mmio, GSC_HEC_ERR_STAT_REG(base, hw_err));
> +	if (!errsrc) {
> +		drm_err_ratelimited(&tile_to_xe(tile)->drm, HW_ERR
> +				    "GSC detected GSC_HEC_ERR_STAT_REG_%s blank!\n",  hw_err_str);
> +		goto clear_reg;
> +	}
> +
> +	drm_info(&tile_to_xe(tile)->drm, HW_ERR
> +		 "GSC_HEC_ERR_STAT_REG_%s=0x%08lx\n", hw_err_str, errsrc);
> +
> +	for_each_set_bit(errbit, &errsrc, 32) {
> +		errmsg = errstat[errbit].errmsg;
> +		indx = errstat[errbit].cntr_indx;
> +
> +		if (hw_err == HARDWARE_ERROR_CORRECTABLE) {
> +			drm_warn(&tile_to_xe(tile)->drm,
> +				 HW_ERR "GSC detected %s %s error, bit[%d] is set\n",
> +				 errmsg, hw_err_str, errbit);
the message should have common convention , like "TileN reported XXX" for all the errors we log
> +
> +		} else {
> +			drm_err_ratelimited(&tile_to_xe(tile)->drm,
> +					    HW_ERR "GSC detected %s %s error, bit[%d] is set\n",
> +					    errmsg, hw_err_str, errbit);
> +		}
may be you want to skip FW_ERR here, see below.
> +		tile->errors.count[indx]++;
> +	}
> +
> +clear_reg:
> +	xe_mmio_write32(mmio, GSC_HEC_ERR_STAT_REG(base, hw_err), errsrc);
> +}
> +
>  static void
>  xe_hw_error_source_handler(struct xe_tile *tile, const enum hardware_error hw_err)
>  {
> @@ -385,10 +472,13 @@ xe_hw_error_source_handler(struct xe_tile *tile, const enum hardware_error hw_er
>  					    HW_ERR "TILE%d detected %s %s error, bit[%d] is set\n",
>  					    tile->id, errmsg, hw_err_str, errbit);
>  		tile->errors.count[indx]++;
> -	}
>  
> -	if (errsrc & REG_BIT(0))
> -		xe_gt_hw_error_handler(tile->primary_gt, hw_err);
> +		if (errbit == 0)
> +			xe_gt_hw_error_handler(tile->primary_gt, hw_err);
> +
> +		if (errbit == 8)
> +			xe_gsc_hw_error_handler(tile, hw_err);
please define what 0 and 8 are.
> +	}
>  
>  	xe_mmio_write32(mmio, DEV_ERR_STAT_REG(hw_err), errsrc);
>  unlock:
> diff --git a/drivers/gpu/drm/xe/xe_hw_error.h b/drivers/gpu/drm/xe/xe_hw_error.h
> index 2812407dd4bf..155722a0af4c 100644
> --- a/drivers/gpu/drm/xe/xe_hw_error.h
> +++ b/drivers/gpu/drm/xe/xe_hw_error.h
> @@ -48,6 +48,22 @@ enum xe_tile_hw_errors {
>  	XE_TILE_HW_ERR_GSC_CORR,
>  	XE_TILE_HW_ERR_SOC_CORR,
>  	XE_TILE_HW_ERR_UNKNOWN_CORR,
> +	XE_GSC_HW_ERR_SRAM_CORR,
> +	XE_GSC_HW_ERR_FW_CORR,
I don't think counting FW_CORR is correct as the acutal count is maintained and reported by CSC via HECI
> +	XE_GSC_HW_ERR_UNKNOWN_CORR,
> +	XE_GSC_HW_ERR_MIA_SHUTDOWN_UNCOR,
> +	XE_GSC_HW_ERR_MIA_INTERNAL_UNCOR,
> +	XE_GSC_HW_ERR_SRAM_UNCOR,
> +	XE_GSC_HW_ERR_WDG_UNCOR,
> +	XE_GSC_HW_ERR_ROM_PARITY_UNCOR,
> +	XE_GSC_HW_ERR_UCODE_PARITY_UNCOR,
> +	XE_GSC_HW_ERR_FW_UNCOR,
> +	XE_GSC_HW_ERR_VLT_GLITCH_UNCOR,
> +	XE_GSC_HW_ERR_FUSE_PULL_UNCOR,
> +	XE_GSC_HW_ERR_FUSE_CRC_UNCOR,
> +	XE_GSC_HW_ERR_SELF_MBIST_UNCOR,
> +	XE_GSC_HW_ERR_AON_RF_PARITY_UNCOR,
we shall maintain uniform naming,
everywhere it is mentioned as NONFATAL, here is just UNCOR
> +	XE_GSC_HW_ERR_UNKNOWN_UNCOR,
>  	XE_TILE_HW_ERROR_MAX,
>  };
Thanks,
Aravind,
>  

[Intel-xe] [PATCH 06/11] drm/xe: Notify userspace about GSC HW errors.

[Himal Prasad Ghimiray]

Send uevent incase of nonfatal errors reported by gsc.

Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
 drivers/gpu/drm/xe/xe_device_types.h |  3 +++
 drivers/gpu/drm/xe/xe_hw_error.c     | 20 ++++++++++++++++++++
 drivers/gpu/drm/xe/xe_hw_error.h     |  3 ++-
 drivers/gpu/drm/xe/xe_irq.c          |  4 ++++
 include/uapi/drm/xe_drm.h            |  9 +++++++++
 5 files changed, 38 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 6aa4f4801d81..ff476a167be4 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -179,6 +179,9 @@ struct xe_tile {
 	struct tile_hw_errors {
 		unsigned long count[XE_TILE_HW_ERROR_MAX];
 	} errors;
+
+	/** @gsc_hw_err_work: worker for uevent to report GSC HW errors */
+	struct work_struct gsc_hw_err_work;
 };
 
 /**
diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
index eb76b8e6a338..76ae12df013c 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.c
+++ b/drivers/gpu/drm/xe/xe_hw_error.c
@@ -3,6 +3,8 @@
  * Copyright © 2023 Intel Corporation
  */
 
+#include <drm/xe_drm.h>
+
 #include "xe_hw_error.h"
 
 #include "regs/xe_regs.h"
@@ -366,6 +368,22 @@ xe_gt_hw_error_handler(struct xe_gt *gt, const enum hardware_error hw_err)
 		xe_gt_hw_error_status_reg_handler(gt, hw_err);
 }
 
+void xe_gsc_hw_error_work(struct work_struct *work)
+{
+	struct xe_tile *tile = container_of(work, typeof(*tile), gsc_hw_err_work);
+	char *csc_hw_error_event[4];
+
+	csc_hw_error_event[0] = XE_GSC_HW_HEALTH_UEVENT "=1";
+	csc_hw_error_event[1] = "RESET_REQUIRED=1";
+	csc_hw_error_event[2] = kasprintf(GFP_KERNEL, "TILE_ID=%d", tile->id);
+	csc_hw_error_event[3] = NULL;
+
+	kobject_uevent_env(&tile->xe->drm.primary->kdev->kobj, KOBJ_CHANGE,
+			   csc_hw_error_event);
+
+	kfree(csc_hw_error_event[2]);
+}
+
 static void
 xe_gsc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
 {
@@ -423,6 +441,8 @@ xe_gsc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
 			drm_err_ratelimited(&tile_to_xe(tile)->drm,
 					    HW_ERR "GSC detected %s %s error, bit[%d] is set\n",
 					    errmsg, hw_err_str, errbit);
+
+			schedule_work(&tile->gsc_hw_err_work);
 		}
 		tile->errors.count[indx]++;
 	}
diff --git a/drivers/gpu/drm/xe/xe_hw_error.h b/drivers/gpu/drm/xe/xe_hw_error.h
index 155722a0af4c..ee7705b3343b 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.h
+++ b/drivers/gpu/drm/xe/xe_hw_error.h
@@ -7,6 +7,7 @@
 
 #include <linux/stddef.h>
 #include <linux/types.h>
+#include <linux/workqueue.h>
 
 /* Error categories reported by hardware */
 enum hardware_error {
@@ -121,5 +122,5 @@ struct xe_tile;
 
 void xe_hw_error_irq_handler(struct xe_tile *tile, const u32 master_ctl);
 void xe_process_hw_errors(struct xe_device *xe);
-
+void xe_gsc_hw_error_work(struct work_struct *work);
 #endif
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index 06c9b43e2c71..285c657cc789 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -586,6 +586,10 @@ int xe_irq_install(struct xe_device *xe)
 	irq_handler_t irq_handler;
 	int err, irq;
 
+	struct xe_tile *tile = xe_device_get_root_tile(xe);
+
+	INIT_WORK(&tile->gsc_hw_err_work, xe_gsc_hw_error_work);
+
 	irq_handler = xe_irq_handler(xe);
 	if (!irq_handler) {
 		drm_err(&xe->drm, "No supported interrupt handler");
diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
index d48d8e3c898c..c45833defcc7 100644
--- a/include/uapi/drm/xe_drm.h
+++ b/include/uapi/drm/xe_drm.h
@@ -16,6 +16,15 @@ extern "C" {
  * subject to backwards-compatibility constraints.
  */
 
+/**
+ * DOC: uevent generated by xe on it's tile node.
+ *
+ * XE_GSC_HW_HEALTH_UEVENT - Event is generated when GSC reports HW
+ * errors. The value supplied with the event is always "RESET_REQUIRED=1".
+ * Additional information supplied is tile id on which error is reported.
+ */
+#define XE_GSC_HW_HEALTH_UEVENT "DEVICE_STATUS"
+
 /**
  * DOC: uevent generated by xe on it's pci node.
  *
-- 
2.25.1

Re: [Intel-xe] [PATCH 06/11] drm/xe: Notify userspace about GSC HW errors.

[Aravind Iddamsetty]

On 27/09/23 17:16, Himal Prasad Ghimiray wrote:
> Send uevent incase of nonfatal errors reported by gsc.
>
> Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_device_types.h |  3 +++
>  drivers/gpu/drm/xe/xe_hw_error.c     | 20 ++++++++++++++++++++
>  drivers/gpu/drm/xe/xe_hw_error.h     |  3 ++-
>  drivers/gpu/drm/xe/xe_irq.c          |  4 ++++
>  include/uapi/drm/xe_drm.h            |  9 +++++++++
>  5 files changed, 38 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index 6aa4f4801d81..ff476a167be4 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -179,6 +179,9 @@ struct xe_tile {
>  	struct tile_hw_errors {
>  		unsigned long count[XE_TILE_HW_ERROR_MAX];
>  	} errors;
> +
> +	/** @gsc_hw_err_work: worker for uevent to report GSC HW errors */
> +	struct work_struct gsc_hw_err_work;
>  };
>  
>  /**
> diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
> index eb76b8e6a338..76ae12df013c 100644
> --- a/drivers/gpu/drm/xe/xe_hw_error.c
> +++ b/drivers/gpu/drm/xe/xe_hw_error.c
> @@ -3,6 +3,8 @@
>   * Copyright © 2023 Intel Corporation
>   */
>  
> +#include <drm/xe_drm.h>
> +
>  #include "xe_hw_error.h"
>  
>  #include "regs/xe_regs.h"
> @@ -366,6 +368,22 @@ xe_gt_hw_error_handler(struct xe_gt *gt, const enum hardware_error hw_err)
>  		xe_gt_hw_error_status_reg_handler(gt, hw_err);
>  }
>  
> +void xe_gsc_hw_error_work(struct work_struct *work)
> +{
> +	struct xe_tile *tile = container_of(work, typeof(*tile), gsc_hw_err_work);
> +	char *csc_hw_error_event[4];
> +
> +	csc_hw_error_event[0] = XE_GSC_HW_HEALTH_UEVENT "=1";
> +	csc_hw_error_event[1] = "RESET_REQUIRED=1";
> +	csc_hw_error_event[2] = kasprintf(GFP_KERNEL, "TILE_ID=%d", tile->id);
> +	csc_hw_error_event[3] = NULL;
> +
> +	kobject_uevent_env(&tile->xe->drm.primary->kdev->kobj, KOBJ_CHANGE,
> +			   csc_hw_error_event);
> +
> +	kfree(csc_hw_error_event[2]);
> +}
> +
>  static void
>  xe_gsc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
>  {
> @@ -423,6 +441,8 @@ xe_gsc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
>  			drm_err_ratelimited(&tile_to_xe(tile)->drm,
>  					    HW_ERR "GSC detected %s %s error, bit[%d] is set\n",
>  					    errmsg, hw_err_str, errbit);
> +
> +			schedule_work(&tile->gsc_hw_err_work);
>  		}
>  		tile->errors.count[indx]++;
>  	}
> diff --git a/drivers/gpu/drm/xe/xe_hw_error.h b/drivers/gpu/drm/xe/xe_hw_error.h
> index 155722a0af4c..ee7705b3343b 100644
> --- a/drivers/gpu/drm/xe/xe_hw_error.h
> +++ b/drivers/gpu/drm/xe/xe_hw_error.h
> @@ -7,6 +7,7 @@
>  
>  #include <linux/stddef.h>
>  #include <linux/types.h>
> +#include <linux/workqueue.h>
>  
>  /* Error categories reported by hardware */
>  enum hardware_error {
> @@ -121,5 +122,5 @@ struct xe_tile;
>  
>  void xe_hw_error_irq_handler(struct xe_tile *tile, const u32 master_ctl);
>  void xe_process_hw_errors(struct xe_device *xe);
> -
> +void xe_gsc_hw_error_work(struct work_struct *work);
>  #endif
> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> index 06c9b43e2c71..285c657cc789 100644
> --- a/drivers/gpu/drm/xe/xe_irq.c
> +++ b/drivers/gpu/drm/xe/xe_irq.c
> @@ -586,6 +586,10 @@ int xe_irq_install(struct xe_device *xe)
>  	irq_handler_t irq_handler;
>  	int err, irq;
>  
> +	struct xe_tile *tile = xe_device_get_root_tile(xe);
> +
> +	INIT_WORK(&tile->gsc_hw_err_work, xe_gsc_hw_error_work);
> +
>  	irq_handler = xe_irq_handler(xe);
>  	if (!irq_handler) {
>  		drm_err(&xe->drm, "No supported interrupt handler");
> diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
> index d48d8e3c898c..c45833defcc7 100644
> --- a/include/uapi/drm/xe_drm.h
> +++ b/include/uapi/drm/xe_drm.h
> @@ -16,6 +16,15 @@ extern "C" {
>   * subject to backwards-compatibility constraints.
>   */
>  
> +/**
> + * DOC: uevent generated by xe on it's tile node.
> + *
> + * XE_GSC_HW_HEALTH_UEVENT - Event is generated when GSC reports HW
> + * errors. The value supplied with the event is always "RESET_REQUIRED=1".
> + * Additional information supplied is tile id on which error is reported.
what is the relevance of tile id if it always reported on tile 0 only.

Thanks,

Aravind
> + */
> +#define XE_GSC_HW_HEALTH_UEVENT "DEVICE_STATUS"
> +
>  /**
>   * DOC: uevent generated by xe on it's pci node.
>   *

Re: [Intel-xe] [PATCH 06/11] drm/xe: Notify userspace about GSC HW errors.

[Ghimiray, Himal Prasad]

> -----Original Message-----
> From: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
> Sent: 11 October 2023 12:53
> To: Ghimiray, Himal Prasad <himal.prasad.ghimiray@intel.com>; intel-
> xe@lists.freedesktop.org
> Subject: Re: [Intel-xe] [PATCH 06/11] drm/xe: Notify userspace about GSC
> HW errors.
> 
> 
> On 27/09/23 17:16, Himal Prasad Ghimiray wrote:
> > Send uevent incase of nonfatal errors reported by gsc.
> >
> > Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
> > ---
> >  drivers/gpu/drm/xe/xe_device_types.h |  3 +++
> >  drivers/gpu/drm/xe/xe_hw_error.c     | 20 ++++++++++++++++++++
> >  drivers/gpu/drm/xe/xe_hw_error.h     |  3 ++-
> >  drivers/gpu/drm/xe/xe_irq.c          |  4 ++++
> >  include/uapi/drm/xe_drm.h            |  9 +++++++++
> >  5 files changed, 38 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/xe/xe_device_types.h
> > b/drivers/gpu/drm/xe/xe_device_types.h
> > index 6aa4f4801d81..ff476a167be4 100644
> > --- a/drivers/gpu/drm/xe/xe_device_types.h
> > +++ b/drivers/gpu/drm/xe/xe_device_types.h
> > @@ -179,6 +179,9 @@ struct xe_tile {
> >  	struct tile_hw_errors {
> >  		unsigned long count[XE_TILE_HW_ERROR_MAX];
> >  	} errors;
> > +
> > +	/** @gsc_hw_err_work: worker for uevent to report GSC HW errors
> */
> > +	struct work_struct gsc_hw_err_work;
> >  };
> >
> >  /**
> > diff --git a/drivers/gpu/drm/xe/xe_hw_error.c
> > b/drivers/gpu/drm/xe/xe_hw_error.c
> > index eb76b8e6a338..76ae12df013c 100644
> > --- a/drivers/gpu/drm/xe/xe_hw_error.c
> > +++ b/drivers/gpu/drm/xe/xe_hw_error.c
> > @@ -3,6 +3,8 @@
> >   * Copyright © 2023 Intel Corporation
> >   */
> >
> > +#include <drm/xe_drm.h>
> > +
> >  #include "xe_hw_error.h"
> >
> >  #include "regs/xe_regs.h"
> > @@ -366,6 +368,22 @@ xe_gt_hw_error_handler(struct xe_gt *gt, const
> enum hardware_error hw_err)
> >  		xe_gt_hw_error_status_reg_handler(gt, hw_err);  }
> >
> > +void xe_gsc_hw_error_work(struct work_struct *work) {
> > +	struct xe_tile *tile = container_of(work, typeof(*tile),
> gsc_hw_err_work);
> > +	char *csc_hw_error_event[4];
> > +
> > +	csc_hw_error_event[0] = XE_GSC_HW_HEALTH_UEVENT "=1";
> > +	csc_hw_error_event[1] = "RESET_REQUIRED=1";
> > +	csc_hw_error_event[2] = kasprintf(GFP_KERNEL, "TILE_ID=%d", tile-
> >id);
> > +	csc_hw_error_event[3] = NULL;
> > +
> > +	kobject_uevent_env(&tile->xe->drm.primary->kdev->kobj,
> KOBJ_CHANGE,
> > +			   csc_hw_error_event);
> > +
> > +	kfree(csc_hw_error_event[2]);
> > +}
> > +
> >  static void
> >  xe_gsc_hw_error_handler(struct xe_tile *tile, const enum
> > hardware_error hw_err)  { @@ -423,6 +441,8 @@
> > xe_gsc_hw_error_handler(struct xe_tile *tile, const enum hardware_error
> hw_err)
> >  			drm_err_ratelimited(&tile_to_xe(tile)->drm,
> >  					    HW_ERR "GSC detected %s %s
> error, bit[%d] is set\n",
> >  					    errmsg, hw_err_str, errbit);
> > +
> > +			schedule_work(&tile->gsc_hw_err_work);
> >  		}
> >  		tile->errors.count[indx]++;
> >  	}
> > diff --git a/drivers/gpu/drm/xe/xe_hw_error.h
> > b/drivers/gpu/drm/xe/xe_hw_error.h
> > index 155722a0af4c..ee7705b3343b 100644
> > --- a/drivers/gpu/drm/xe/xe_hw_error.h
> > +++ b/drivers/gpu/drm/xe/xe_hw_error.h
> > @@ -7,6 +7,7 @@
> >
> >  #include <linux/stddef.h>
> >  #include <linux/types.h>
> > +#include <linux/workqueue.h>
> >
> >  /* Error categories reported by hardware */  enum hardware_error { @@
> > -121,5 +122,5 @@ struct xe_tile;
> >
> >  void xe_hw_error_irq_handler(struct xe_tile *tile, const u32
> > master_ctl);  void xe_process_hw_errors(struct xe_device *xe);
> > -
> > +void xe_gsc_hw_error_work(struct work_struct *work);
> >  #endif
> > diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> > index 06c9b43e2c71..285c657cc789 100644
> > --- a/drivers/gpu/drm/xe/xe_irq.c
> > +++ b/drivers/gpu/drm/xe/xe_irq.c
> > @@ -586,6 +586,10 @@ int xe_irq_install(struct xe_device *xe)
> >  	irq_handler_t irq_handler;
> >  	int err, irq;
> >
> > +	struct xe_tile *tile = xe_device_get_root_tile(xe);
> > +
> > +	INIT_WORK(&tile->gsc_hw_err_work, xe_gsc_hw_error_work);
> > +
> >  	irq_handler = xe_irq_handler(xe);
> >  	if (!irq_handler) {
> >  		drm_err(&xe->drm, "No supported interrupt handler"); diff --
> git
> > a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h index
> > d48d8e3c898c..c45833defcc7 100644
> > --- a/include/uapi/drm/xe_drm.h
> > +++ b/include/uapi/drm/xe_drm.h
> > @@ -16,6 +16,15 @@ extern "C" {
> >   * subject to backwards-compatibility constraints.
> >   */
> >
> > +/**
> > + * DOC: uevent generated by xe on it's tile node.
> > + *
> > + * XE_GSC_HW_HEALTH_UEVENT - Event is generated when GSC reports
> HW
> > + * errors. The value supplied with the event is always
> "RESET_REQUIRED=1".
> > + * Additional information supplied is tile id on which error is reported.
> what is the relevance of tile id if it always reported on tile 0 only.

Hmm. Ya right. Any other information we would like to send ?
Instead of DEVICE_STATUS is it ok to send GSC_HW_STATUS ?
> 
> Thanks,
> 
> Aravind
> > + */
> > +#define XE_GSC_HW_HEALTH_UEVENT "DEVICE_STATUS"
> > +
> >  /**
> >   * DOC: uevent generated by xe on it's pci node.
> >   *

Re: [Intel-xe] [PATCH 06/11] drm/xe: Notify userspace about GSC HW errors.

[Aravind Iddamsetty]

On 11/10/23 12:55, Ghimiray, Himal Prasad wrote:
>
>> -----Original Message-----
>> From: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
>> Sent: 11 October 2023 12:53
>> To: Ghimiray, Himal Prasad <himal.prasad.ghimiray@intel.com>; intel-
>> xe@lists.freedesktop.org
>> Subject: Re: [Intel-xe] [PATCH 06/11] drm/xe: Notify userspace about GSC
>> HW errors.
>>
>>
>> On 27/09/23 17:16, Himal Prasad Ghimiray wrote:
>>> Send uevent incase of nonfatal errors reported by gsc.
>>>
>>> Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
>>> ---
>>>  drivers/gpu/drm/xe/xe_device_types.h |  3 +++
>>>  drivers/gpu/drm/xe/xe_hw_error.c     | 20 ++++++++++++++++++++
>>>  drivers/gpu/drm/xe/xe_hw_error.h     |  3 ++-
>>>  drivers/gpu/drm/xe/xe_irq.c          |  4 ++++
>>>  include/uapi/drm/xe_drm.h            |  9 +++++++++
>>>  5 files changed, 38 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/xe/xe_device_types.h
>>> b/drivers/gpu/drm/xe/xe_device_types.h
>>> index 6aa4f4801d81..ff476a167be4 100644
>>> --- a/drivers/gpu/drm/xe/xe_device_types.h
>>> +++ b/drivers/gpu/drm/xe/xe_device_types.h
>>> @@ -179,6 +179,9 @@ struct xe_tile {
>>>  	struct tile_hw_errors {
>>>  		unsigned long count[XE_TILE_HW_ERROR_MAX];
>>>  	} errors;
>>> +
>>> +	/** @gsc_hw_err_work: worker for uevent to report GSC HW errors
>> */
>>> +	struct work_struct gsc_hw_err_work;
>>>  };
>>>
>>>  /**
>>> diff --git a/drivers/gpu/drm/xe/xe_hw_error.c
>>> b/drivers/gpu/drm/xe/xe_hw_error.c
>>> index eb76b8e6a338..76ae12df013c 100644
>>> --- a/drivers/gpu/drm/xe/xe_hw_error.c
>>> +++ b/drivers/gpu/drm/xe/xe_hw_error.c
>>> @@ -3,6 +3,8 @@
>>>   * Copyright © 2023 Intel Corporation
>>>   */
>>>
>>> +#include <drm/xe_drm.h>
>>> +
>>>  #include "xe_hw_error.h"
>>>
>>>  #include "regs/xe_regs.h"
>>> @@ -366,6 +368,22 @@ xe_gt_hw_error_handler(struct xe_gt *gt, const
>> enum hardware_error hw_err)
>>>  		xe_gt_hw_error_status_reg_handler(gt, hw_err);  }
>>>
>>> +void xe_gsc_hw_error_work(struct work_struct *work) {
>>> +	struct xe_tile *tile = container_of(work, typeof(*tile),
>> gsc_hw_err_work);
>>> +	char *csc_hw_error_event[4];
>>> +
>>> +	csc_hw_error_event[0] = XE_GSC_HW_HEALTH_UEVENT "=1";
>>> +	csc_hw_error_event[1] = "RESET_REQUIRED=1";
>>> +	csc_hw_error_event[2] = kasprintf(GFP_KERNEL, "TILE_ID=%d", tile-
>>> id);
>>> +	csc_hw_error_event[3] = NULL;
>>> +
>>> +	kobject_uevent_env(&tile->xe->drm.primary->kdev->kobj,
>> KOBJ_CHANGE,
>>> +			   csc_hw_error_event);
>>> +
>>> +	kfree(csc_hw_error_event[2]);
>>> +}
>>> +
>>>  static void
>>>  xe_gsc_hw_error_handler(struct xe_tile *tile, const enum
>>> hardware_error hw_err)  { @@ -423,6 +441,8 @@
>>> xe_gsc_hw_error_handler(struct xe_tile *tile, const enum hardware_error
>> hw_err)
>>>  			drm_err_ratelimited(&tile_to_xe(tile)->drm,
>>>  					    HW_ERR "GSC detected %s %s
>> error, bit[%d] is set\n",
>>>  					    errmsg, hw_err_str, errbit);
>>> +
>>> +			schedule_work(&tile->gsc_hw_err_work);
>>>  		}
>>>  		tile->errors.count[indx]++;
>>>  	}
>>> diff --git a/drivers/gpu/drm/xe/xe_hw_error.h
>>> b/drivers/gpu/drm/xe/xe_hw_error.h
>>> index 155722a0af4c..ee7705b3343b 100644
>>> --- a/drivers/gpu/drm/xe/xe_hw_error.h
>>> +++ b/drivers/gpu/drm/xe/xe_hw_error.h
>>> @@ -7,6 +7,7 @@
>>>
>>>  #include <linux/stddef.h>
>>>  #include <linux/types.h>
>>> +#include <linux/workqueue.h>
>>>
>>>  /* Error categories reported by hardware */  enum hardware_error { @@
>>> -121,5 +122,5 @@ struct xe_tile;
>>>
>>>  void xe_hw_error_irq_handler(struct xe_tile *tile, const u32
>>> master_ctl);  void xe_process_hw_errors(struct xe_device *xe);
>>> -
>>> +void xe_gsc_hw_error_work(struct work_struct *work);
>>>  #endif
>>> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
>>> index 06c9b43e2c71..285c657cc789 100644
>>> --- a/drivers/gpu/drm/xe/xe_irq.c
>>> +++ b/drivers/gpu/drm/xe/xe_irq.c
>>> @@ -586,6 +586,10 @@ int xe_irq_install(struct xe_device *xe)
>>>  	irq_handler_t irq_handler;
>>>  	int err, irq;
>>>
>>> +	struct xe_tile *tile = xe_device_get_root_tile(xe);
>>> +
>>> +	INIT_WORK(&tile->gsc_hw_err_work, xe_gsc_hw_error_work);
>>> +
>>>  	irq_handler = xe_irq_handler(xe);
>>>  	if (!irq_handler) {
>>>  		drm_err(&xe->drm, "No supported interrupt handler"); diff --
>> git
>>> a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h index
>>> d48d8e3c898c..c45833defcc7 100644
>>> --- a/include/uapi/drm/xe_drm.h
>>> +++ b/include/uapi/drm/xe_drm.h
>>> @@ -16,6 +16,15 @@ extern "C" {
>>>   * subject to backwards-compatibility constraints.
>>>   */
>>>
>>> +/**
>>> + * DOC: uevent generated by xe on it's tile node.
>>> + *
>>> + * XE_GSC_HW_HEALTH_UEVENT - Event is generated when GSC reports
>> HW
>>> + * errors. The value supplied with the event is always
>> "RESET_REQUIRED=1".
>>> + * Additional information supplied is tile id on which error is reported.
>> what is the relevance of tile id if it always reported on tile 0 only.
> Hmm. Ya right. Any other information we would like to send ?
> Instead of DEVICE_STATUS is it ok to send GSC_HW_STATUS ?
I think RESET_REQUIRED is sufficient but may be you have to add more details
to UAPI DOC why RESET is needed.

Thanks,

Aravind.
>> Thanks,
>>
>> Aravind
>>> + */
>>> +#define XE_GSC_HW_HEALTH_UEVENT "DEVICE_STATUS"
>>> +
>>>  /**
>>>   * DOC: uevent generated by xe on it's pci node.
>>>   *

[Intel-xe] [PATCH 07/11] drm/xe: Support SOC FATAL error handling for PVC.

[Himal Prasad Ghimiray]

Report the SOC fatal hardware error and update the counters which will
increment incase of error.

Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_tile_error_regs.h |  28 +++
 drivers/gpu/drm/xe/xe_hw_error.c             | 170 +++++++++++++++++++
 drivers/gpu/drm/xe/xe_hw_error.h             |  58 ++++++-
 3 files changed, 254 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
index fa16eaf9436b..04701c62f0d9 100644
--- a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
@@ -20,4 +20,32 @@
 #define GSC_HEC_ERR_STAT_REG(base, x)                  XE_REG(_PICK_EVEN((x), \
 								(base) + _GSC_HEC_CORR_ERR_STATUS, \
 								(base) + _GSC_HEC_UNCOR_ERR_STATUS))
+#define SOC_PVC_BASE	               0x00282000
+#define SOC_PVC_SLAVE_BASE             0x00283000
+
+#define _SOC_LERRCORSTS		       0x000294
+#define _SOC_LERRUNCSTS		       0x000280
+#define SOC_LOCAL_ERR_STAT_SLAVE_REG(base, x)		XE_REG((x) > HARDWARE_ERROR_CORRECTABLE ? \
+								(base) + _SOC_LERRUNCSTS : \
+								(base) + _SOC_LERRCORSTS)
+
+#define SOC_LOCAL_ERR_STAT_MASTER_REG(base, x)		XE_REG((x) > HARDWARE_ERROR_CORRECTABLE ? \
+								(base) + _SOC_LERRUNCSTS : \
+								(base) + _SOC_LERRCORSTS)
+#define _SOC_GSYSEVTCTL		        0x000264
+
+#define SOC_GSYSEVTCTL_REG(base, slave_base, x)		XE_REG(_PICK_EVEN((x), \
+								(base) + _SOC_GSYSEVTCTL, \
+								slave_base + _SOC_GSYSEVTCTL))
+#define _SOC_GCOERRSTS		        0x000200
+#define _SOC_GNFERRSTS		        0x000210
+#define _SOC_GFAERRSTS		        0x000220
+#define SOC_GLOBAL_ERR_STAT_SLAVE_REG(base, x)		XE_REG(_PICK_EVEN((x), \
+								(base) + _SOC_GCOERRSTS, \
+								(base) + _SOC_GNFERRSTS))
+
+#define SOC_GLOBAL_ERR_STAT_MASTER_REG(base, x)		XE_REG(_PICK_EVEN((x), \
+								(base) + _SOC_GCOERRSTS, \
+								(base) + _SOC_GNFERRSTS))
+
 #endif
diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
index 76ae12df013c..fa05bad5e684 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.c
+++ b/drivers/gpu/drm/xe/xe_hw_error.c
@@ -207,6 +207,75 @@ static const struct err_msg_cntr_pair gsc_correctable_err_reg[] = {
 	[2 ... 31] = {"Undefined",					XE_GSC_HW_ERR_UNKNOWN_CORR},
 };
 
+static const struct err_msg_cntr_pair soc_mstr_glbl_err_reg_fatal[] = {
+	[0]         = {"MASTER LOCAL Reported",			XE_SOC_HW_ERR_MSTR_LCL_FATAL},
+	[1]         = {"SLAVE GLOBAL Reported",			XE_SOC_HW_ERR_SLAVE_GLBL_FATAL},
+	[2]         = {"HBM SS0: Channel0",			XE_SOC_HW_ERR_HBM0_CHNL0_FATAL},
+	[3]         = {"HBM SS0: Channel1",			XE_SOC_HW_ERR_HBM0_CHNL1_FATAL},
+	[4]         = {"HBM SS0: Channel2",			XE_SOC_HW_ERR_HBM0_CHNL2_FATAL},
+	[5]         = {"HBM SS0: Channel3",			XE_SOC_HW_ERR_HBM0_CHNL3_FATAL},
+	[6]         = {"HBM SS0: Channel4",			XE_SOC_HW_ERR_HBM0_CHNL4_FATAL},
+	[7]         = {"HBM SS0: Channel5",			XE_SOC_HW_ERR_HBM0_CHNL5_FATAL},
+	[8]         = {"HBM SS0: Channel6",                     XE_SOC_HW_ERR_HBM0_CHNL6_FATAL},
+	[9]         = {"HBM SS0: Channel7",                     XE_SOC_HW_ERR_HBM0_CHNL7_FATAL},
+	[10]        = {"HBM SS1: Channel0",                     XE_SOC_HW_ERR_HBM1_CHNL0_FATAL},
+	[11]        = {"HBM SS1: Channel1",                     XE_SOC_HW_ERR_HBM1_CHNL1_FATAL},
+	[12]        = {"HBM SS1: Channel2",                     XE_SOC_HW_ERR_HBM1_CHNL2_FATAL},
+	[13]        = {"HBM SS1: Channel3",                     XE_SOC_HW_ERR_HBM1_CHNL3_FATAL},
+	[14]        = {"HBM SS1: Channel4",                     XE_SOC_HW_ERR_HBM1_CHNL4_FATAL},
+	[15]        = {"HBM SS1: Channel5",                     XE_SOC_HW_ERR_HBM1_CHNL5_FATAL},
+	[16]        = {"HBM SS1: Channel6",                     XE_SOC_HW_ERR_HBM1_CHNL6_FATAL},
+	[17]        = {"HBM SS1: Channel7",                     XE_SOC_HW_ERR_HBM1_CHNL7_FATAL},
+	[18]	    = {"PUNIT",					XE_SOC_HW_ERR_PUNIT_FATAL},
+	[19 ... 31] = {"Undefined",				XE_SOC_HW_ERR_UNKNOWN_FATAL},
+};
+
+static const struct err_msg_cntr_pair soc_slave_glbl_err_reg_fatal[] = {
+	[0]         = {"SLAVE LOCAL Reported",			XE_SOC_HW_ERR_SLAVE_LCL_FATAL},
+	[1]         = {"HBM SS2: Channel0",			XE_SOC_HW_ERR_HBM2_CHNL0_FATAL},
+	[2]         = {"HBM SS2: Channel1",			XE_SOC_HW_ERR_HBM2_CHNL1_FATAL},
+	[3]         = {"HBM SS2: Channel2",			XE_SOC_HW_ERR_HBM2_CHNL2_FATAL},
+	[4]         = {"HBM SS2: Channel3",			XE_SOC_HW_ERR_HBM2_CHNL3_FATAL},
+	[5]         = {"HBM SS2: Channel4",			XE_SOC_HW_ERR_HBM2_CHNL4_FATAL},
+	[6]         = {"HBM SS2: Channel5",			XE_SOC_HW_ERR_HBM2_CHNL5_FATAL},
+	[7]         = {"HBM SS2: Channel6",                     XE_SOC_HW_ERR_HBM2_CHNL6_FATAL},
+	[8]         = {"HBM SS2: Channel7",                     XE_SOC_HW_ERR_HBM2_CHNL7_FATAL},
+	[9]         = {"HBM SS3: Channel0",                     XE_SOC_HW_ERR_HBM3_CHNL0_FATAL},
+	[10]        = {"HBM SS3: Channel1",                     XE_SOC_HW_ERR_HBM3_CHNL1_FATAL},
+	[11]        = {"HBM SS3: Channel2",                     XE_SOC_HW_ERR_HBM3_CHNL2_FATAL},
+	[12]        = {"HBM SS3: Channel3",                     XE_SOC_HW_ERR_HBM3_CHNL3_FATAL},
+	[13]        = {"HBM SS3: Channel4",                     XE_SOC_HW_ERR_HBM3_CHNL4_FATAL},
+	[14]        = {"HBM SS3: Channel5",                     XE_SOC_HW_ERR_HBM3_CHNL5_FATAL},
+	[15]        = {"HBM SS3: Channel6",                     XE_SOC_HW_ERR_HBM3_CHNL6_FATAL},
+	[16]        = {"HBM SS3: Channel7",                     XE_SOC_HW_ERR_HBM3_CHNL7_FATAL},
+	[18]	    = {"ANR MDFI",				XE_SOC_HW_ERR_ANR_MDFI_FATAL},
+	[17]        = {"Undefined",                             XE_SOC_HW_ERR_UNKNOWN_FATAL},
+	[19 ... 31] = {"Undefined",				XE_SOC_HW_ERR_UNKNOWN_FATAL},
+};
+
+static const struct err_msg_cntr_pair soc_slave_lcl_err_reg_fatal[] = {
+	[0]         = {"Local IEH Internal: Malformed PCIe AER",     XE_SOC_HW_ERR_PCIE_AER_FATAL},
+	[1]         = {"Local IEH Internal: Malformed PCIe ERR",     XE_SOC_HW_ERR_PCIE_ERR_FATAL},
+	[2]         = {"Local IEH Internal: UR CONDITIONS IN IEH",   XE_SOC_HW_ERR_UR_COND_FATAL},
+	[3]         = {"Local IEH Internal: FROM SERR SOURCES",      XE_SOC_HW_ERR_SERR_SRCS_FATAL},
+	[4 ... 31]  = {"Undefined",				     XE_SOC_HW_ERR_UNKNOWN_FATAL},
+};
+
+static const struct err_msg_cntr_pair soc_mstr_lcl_err_reg_fatal[] = {
+	[0 ... 3]   = {"Undefined",				XE_SOC_HW_ERR_UNKNOWN_FATAL},
+	[4]         = {"Base Die MDFI T2T",			XE_SOC_HW_ERR_MDFI_T2T_FATAL},
+	[5]         = {"Undefined",				XE_SOC_HW_ERR_UNKNOWN_FATAL},
+	[6]         = {"Base Die MDFI T2C",			XE_SOC_HW_ERR_MDFI_T2C_FATAL},
+	[7]         = {"Undefined",				XE_SOC_HW_ERR_UNKNOWN_FATAL},
+	[8]         = {"Invalid CSC PSF Command Parity",	XE_SOC_HW_ERR_CSC_PSF_CMD_FATAL},
+	[9]         = {"Invalid CSC PSF Unexpected Completion",	XE_SOC_HW_ERR_CSC_PSF_CMP_FATAL},
+	[10]        = {"Invalid CSC PSF Unsupported Request",	XE_SOC_HW_ERR_CSC_PSF_REQ_FATAL},
+	[11]        = {"Invalid PCIe PSF Command Parity",	XE_SOC_HW_ERR_PCIE_PSF_CMD_FATAL},
+	[12]        = {"PCIe PSF Unexpected Completion",	XE_SOC_HW_ERR_PCIE_PSF_CMP_FATAL},
+	[13]        = {"PCIe PSF Unsupported Request",		XE_SOC_HW_ERR_PCIE_PSF_REQ_FATAL},
+	[14 ... 31] = {"Undefined",				XE_SOC_HW_ERR_UNKNOWN_FATAL},
+};
+
 static void xe_assign_hw_err_regs(struct xe_device *xe)
 {
 	const struct err_msg_cntr_pair **dev_err_stat = xe->hw_err_regs.dev_err_stat;
@@ -451,6 +520,104 @@ xe_gsc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
 	xe_mmio_write32(mmio, GSC_HEC_ERR_STAT_REG(base, hw_err), errsrc);
 }
 
+static void
+xe_soc_log_err_update_cntr(struct xe_tile *tile,
+			   u32 errbit, const struct err_msg_cntr_pair *reg_info)
+{
+	const char *errmsg;
+	u32 indx;
+
+	errmsg = reg_info[errbit].errmsg;
+	indx = reg_info[errbit].cntr_indx;
+
+	drm_err_ratelimited(&tile_to_xe(tile)->drm, HW_ERR
+			    "Tile%d %s SOC FATAL error, bit[%d] is set\n",
+			    tile->id, errmsg, errbit);
+	tile->errors.count[indx]++;
+}
+
+static void
+xe_soc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
+{
+	unsigned long mst_glb_errstat, slv_glb_errstat, lcl_errstat;
+	u32 errbit, base, slave_base;
+	int i;
+	struct xe_gt *gt = tile->primary_gt;
+
+	lockdep_assert_held(&tile_to_xe(tile)->irq.lock);
+
+	if ((tile_to_xe(tile)->info.platform != XE_PVC) && hw_err != HARDWARE_ERROR_FATAL)
+		return;
+
+	base = SOC_PVC_BASE;
+	slave_base = SOC_PVC_SLAVE_BASE;
+
+	/*
+	 * Mask error type in GSYSEVTCTL so that no new errors of the type
+	 * will be reported. Read the master global IEH error register if
+	 * BIT 1 is set then process the slave IEH first. If BIT 0 in
+	 * global error register is set then process the corresponding
+	 * Local error registers
+	 */
+	for (i = 0; i < PVC_NUM_IEH; i++)
+		xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base, i), ~REG_BIT(hw_err));
+
+	mst_glb_errstat = xe_mmio_read32(gt, SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err));
+	drm_info(&tile_to_xe(tile)->drm, HW_ERR
+		 "Tile%d SOC_GLOBAL_ERR_STAT_MASTER_REG_FATAL:0x%08lx\n",
+		 tile->id, mst_glb_errstat);
+
+	if (mst_glb_errstat & REG_BIT(SOC_SLAVE_IEH)) {
+		slv_glb_errstat = xe_mmio_read32(gt,
+						 SOC_GLOBAL_ERR_STAT_SLAVE_REG(slave_base, hw_err));
+		 drm_info(&tile_to_xe(tile)->drm, HW_ERR
+			  "Tile%d SOC_GLOBAL_ERR_STAT_SLAVE_REG_FATAL:0x%08lx\n",
+			  tile->id, slv_glb_errstat);
+
+		if (slv_glb_errstat & REG_BIT(SOC_IEH1_LOCAL_ERR_STATUS)) {
+			lcl_errstat = xe_mmio_read32(gt, SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base,
+										      hw_err));
+			 drm_info(&tile_to_xe(tile)->drm, HW_ERR
+				  "Tile%d SOC_LOCAL_ERR_STAT_SLAVE_REG_FATAL:0x%08lx\n",
+				  tile->id, lcl_errstat);
+
+			for_each_set_bit(errbit, &lcl_errstat, 32)
+				xe_soc_log_err_update_cntr(tile, errbit,
+							   soc_slave_lcl_err_reg_fatal);
+
+			xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
+					lcl_errstat);
+		}
+
+		for_each_set_bit(errbit, &slv_glb_errstat, 32)
+			xe_soc_log_err_update_cntr(tile, errbit, soc_slave_glbl_err_reg_fatal);
+
+		xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
+				slv_glb_errstat);
+	}
+
+	if (mst_glb_errstat & REG_BIT(SOC_IEH0_LOCAL_ERR_STATUS)) {
+		lcl_errstat = xe_mmio_read32(gt, SOC_LOCAL_ERR_STAT_MASTER_REG(base, hw_err));
+		drm_info(&tile_to_xe(tile)->drm, HW_ERR "SOC_LOCAL_ERR_STAT_MASTER_REG_FATAL:0x%08lx\n",
+			 lcl_errstat);
+
+		for_each_set_bit(errbit, &lcl_errstat, 32)
+			xe_soc_log_err_update_cntr(tile, errbit, soc_mstr_lcl_err_reg_fatal);
+
+		xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_MASTER_REG(base, hw_err), lcl_errstat);
+	}
+
+	for_each_set_bit(errbit, &mst_glb_errstat, 32)
+		xe_soc_log_err_update_cntr(tile, errbit, soc_mstr_glbl_err_reg_fatal);
+
+	xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err),
+			mst_glb_errstat);
+
+	for (i = 0; i < PVC_NUM_IEH; i++)
+		xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base, i),
+				(HARDWARE_ERROR_MAX << 1) + 1);
+}
+
 static void
 xe_hw_error_source_handler(struct xe_tile *tile, const enum hardware_error hw_err)
 {
@@ -498,6 +665,9 @@ xe_hw_error_source_handler(struct xe_tile *tile, const enum hardware_error hw_er
 
 		if (errbit == 8)
 			xe_gsc_hw_error_handler(tile, hw_err);
+
+		if (errbit == 16)
+			xe_soc_hw_error_handler(tile, hw_err);
 	}
 
 	xe_mmio_write32(mmio, DEV_ERR_STAT_REG(hw_err), errsrc);
diff --git a/drivers/gpu/drm/xe/xe_hw_error.h b/drivers/gpu/drm/xe/xe_hw_error.h
index ee7705b3343b..05838e082abd 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.h
+++ b/drivers/gpu/drm/xe/xe_hw_error.h
@@ -65,6 +65,56 @@ enum xe_tile_hw_errors {
 	XE_GSC_HW_ERR_SELF_MBIST_UNCOR,
 	XE_GSC_HW_ERR_AON_RF_PARITY_UNCOR,
 	XE_GSC_HW_ERR_UNKNOWN_UNCOR,
+	XE_SOC_HW_ERR_MSTR_LCL_FATAL,
+	XE_SOC_HW_ERR_SLAVE_GLBL_FATAL,
+	XE_SOC_HW_ERR_HBM0_CHNL0_FATAL,
+	XE_SOC_HW_ERR_HBM0_CHNL1_FATAL,
+	XE_SOC_HW_ERR_HBM0_CHNL2_FATAL,
+	XE_SOC_HW_ERR_HBM0_CHNL3_FATAL,
+	XE_SOC_HW_ERR_HBM0_CHNL4_FATAL,
+	XE_SOC_HW_ERR_HBM0_CHNL5_FATAL,
+	XE_SOC_HW_ERR_HBM0_CHNL6_FATAL,
+	XE_SOC_HW_ERR_HBM0_CHNL7_FATAL,
+	XE_SOC_HW_ERR_HBM1_CHNL0_FATAL,
+	XE_SOC_HW_ERR_HBM1_CHNL1_FATAL,
+	XE_SOC_HW_ERR_HBM1_CHNL2_FATAL,
+	XE_SOC_HW_ERR_HBM1_CHNL3_FATAL,
+	XE_SOC_HW_ERR_HBM1_CHNL4_FATAL,
+	XE_SOC_HW_ERR_HBM1_CHNL5_FATAL,
+	XE_SOC_HW_ERR_HBM1_CHNL6_FATAL,
+	XE_SOC_HW_ERR_HBM1_CHNL7_FATAL,
+	XE_SOC_HW_ERR_PUNIT_FATAL,
+	XE_SOC_HW_ERR_UNKNOWN_FATAL,
+	XE_SOC_HW_ERR_SLAVE_LCL_FATAL,
+	XE_SOC_HW_ERR_HBM2_CHNL0_FATAL,
+	XE_SOC_HW_ERR_HBM2_CHNL1_FATAL,
+	XE_SOC_HW_ERR_HBM2_CHNL2_FATAL,
+	XE_SOC_HW_ERR_HBM2_CHNL3_FATAL,
+	XE_SOC_HW_ERR_HBM2_CHNL4_FATAL,
+	XE_SOC_HW_ERR_HBM2_CHNL5_FATAL,
+	XE_SOC_HW_ERR_HBM2_CHNL6_FATAL,
+	XE_SOC_HW_ERR_HBM2_CHNL7_FATAL,
+	XE_SOC_HW_ERR_HBM3_CHNL0_FATAL,
+	XE_SOC_HW_ERR_HBM3_CHNL1_FATAL,
+	XE_SOC_HW_ERR_HBM3_CHNL2_FATAL,
+	XE_SOC_HW_ERR_HBM3_CHNL3_FATAL,
+	XE_SOC_HW_ERR_HBM3_CHNL4_FATAL,
+	XE_SOC_HW_ERR_HBM3_CHNL5_FATAL,
+	XE_SOC_HW_ERR_HBM3_CHNL6_FATAL,
+	XE_SOC_HW_ERR_HBM3_CHNL7_FATAL,
+	XE_SOC_HW_ERR_ANR_MDFI_FATAL,
+	XE_SOC_HW_ERR_PCIE_AER_FATAL,
+	XE_SOC_HW_ERR_PCIE_ERR_FATAL,
+	XE_SOC_HW_ERR_UR_COND_FATAL,
+	XE_SOC_HW_ERR_SERR_SRCS_FATAL,
+	XE_SOC_HW_ERR_MDFI_T2T_FATAL,
+	XE_SOC_HW_ERR_MDFI_T2C_FATAL,
+	XE_SOC_HW_ERR_CSC_PSF_CMD_FATAL,
+	XE_SOC_HW_ERR_CSC_PSF_CMP_FATAL,
+	XE_SOC_HW_ERR_CSC_PSF_REQ_FATAL,
+	XE_SOC_HW_ERR_PCIE_PSF_CMD_FATAL,
+	XE_SOC_HW_ERR_PCIE_PSF_CMP_FATAL,
+	XE_SOC_HW_ERR_PCIE_PSF_REQ_FATAL,
 	XE_TILE_HW_ERROR_MAX,
 };
 
@@ -109,8 +159,12 @@ enum xe_gt_hw_errors {
 	XE_GT_HW_ERROR_MAX,
 };
 
-#define ERR_STAT_GT_COR_VCTR_LEN (4)
-#define ERR_STAT_GT_FATAL_VCTR_LEN (8)
+#define ERR_STAT_GT_COR_VCTR_LEN	(4)
+#define ERR_STAT_GT_FATAL_VCTR_LEN	(8)
+#define PVC_NUM_IEH			(1)
+#define SOC_SLAVE_IEH                   (1)
+#define SOC_IEH0_LOCAL_ERR_STATUS       (0)
+#define SOC_IEH1_LOCAL_ERR_STATUS       (0)
 
 struct err_msg_cntr_pair {
 	const char *errmsg;
-- 
2.25.1

Re: [Intel-xe] [PATCH 07/11] drm/xe: Support SOC FATAL error handling for PVC.

[Aravind Iddamsetty]

On 27/09/23 17:16, Himal Prasad Ghimiray wrote:
Hi Himal,

I'm yet to review the full patch but sharing a few initial comments.

> Report the SOC fatal hardware error and update the counters which will
> increment incase of error.
>
> Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_tile_error_regs.h |  28 +++
>  drivers/gpu/drm/xe/xe_hw_error.c             | 170 +++++++++++++++++++
>  drivers/gpu/drm/xe/xe_hw_error.h             |  58 ++++++-
>  3 files changed, 254 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
> index fa16eaf9436b..04701c62f0d9 100644
> --- a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
> @@ -20,4 +20,32 @@
>  #define GSC_HEC_ERR_STAT_REG(base, x)                  XE_REG(_PICK_EVEN((x), \
>  								(base) + _GSC_HEC_CORR_ERR_STATUS, \
>  								(base) + _GSC_HEC_UNCOR_ERR_STATUS))
> +#define SOC_PVC_BASE	               0x00282000
> +#define SOC_PVC_SLAVE_BASE             0x00283000
> +
> +#define _SOC_LERRCORSTS		       0x000294
> +#define _SOC_LERRUNCSTS		       0x000280
> +#define SOC_LOCAL_ERR_STAT_SLAVE_REG(base, x)		XE_REG((x) > HARDWARE_ERROR_CORRECTABLE ? \
> +								(base) + _SOC_LERRUNCSTS : \
> +								(base) + _SOC_LERRCORSTS)
> +
> +#define SOC_LOCAL_ERR_STAT_MASTER_REG(base, x)		XE_REG((x) > HARDWARE_ERROR_CORRECTABLE ? \
> +								(base) + _SOC_LERRUNCSTS : \
> +								(base) + _SOC_LERRCORSTS)
> +#define _SOC_GSYSEVTCTL		        0x000264
> +
> +#define SOC_GSYSEVTCTL_REG(base, slave_base, x)		XE_REG(_PICK_EVEN((x), \
> +								(base) + _SOC_GSYSEVTCTL, \
> +								slave_base + _SOC_GSYSEVTCTL))
> +#define _SOC_GCOERRSTS		        0x000200
> +#define _SOC_GNFERRSTS		        0x000210
> +#define _SOC_GFAERRSTS		        0x000220
> +#define SOC_GLOBAL_ERR_STAT_SLAVE_REG(base, x)		XE_REG(_PICK_EVEN((x), \
> +								(base) + _SOC_GCOERRSTS, \
> +								(base) + _SOC_GNFERRSTS))
> +
> +#define SOC_GLOBAL_ERR_STAT_MASTER_REG(base, x)		XE_REG(_PICK_EVEN((x), \
> +								(base) + _SOC_GCOERRSTS, \
> +								(base) + _SOC_GNFERRSTS))
> +
>  #endif
> diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
> index 76ae12df013c..fa05bad5e684 100644
> --- a/drivers/gpu/drm/xe/xe_hw_error.c
> +++ b/drivers/gpu/drm/xe/xe_hw_error.c
> @@ -207,6 +207,75 @@ static const struct err_msg_cntr_pair gsc_correctable_err_reg[] = {
>  	[2 ... 31] = {"Undefined",					XE_GSC_HW_ERR_UNKNOWN_CORR},
>  };
>  
> +static const struct err_msg_cntr_pair soc_mstr_glbl_err_reg_fatal[] = {
> +	[0]         = {"MASTER LOCAL Reported",			XE_SOC_HW_ERR_MSTR_LCL_FATAL},
> +	[1]         = {"SLAVE GLOBAL Reported",			XE_SOC_HW_ERR_SLAVE_GLBL_FATAL},
> +	[2]         = {"HBM SS0: Channel0",			XE_SOC_HW_ERR_HBM0_CHNL0_FATAL},
> +	[3]         = {"HBM SS0: Channel1",			XE_SOC_HW_ERR_HBM0_CHNL1_FATAL},
> +	[4]         = {"HBM SS0: Channel2",			XE_SOC_HW_ERR_HBM0_CHNL2_FATAL},
> +	[5]         = {"HBM SS0: Channel3",			XE_SOC_HW_ERR_HBM0_CHNL3_FATAL},
> +	[6]         = {"HBM SS0: Channel4",			XE_SOC_HW_ERR_HBM0_CHNL4_FATAL},
> +	[7]         = {"HBM SS0: Channel5",			XE_SOC_HW_ERR_HBM0_CHNL5_FATAL},
> +	[8]         = {"HBM SS0: Channel6",                     XE_SOC_HW_ERR_HBM0_CHNL6_FATAL},
> +	[9]         = {"HBM SS0: Channel7",                     XE_SOC_HW_ERR_HBM0_CHNL7_FATAL},
> +	[10]        = {"HBM SS1: Channel0",                     XE_SOC_HW_ERR_HBM1_CHNL0_FATAL},
> +	[11]        = {"HBM SS1: Channel1",                     XE_SOC_HW_ERR_HBM1_CHNL1_FATAL},
> +	[12]        = {"HBM SS1: Channel2",                     XE_SOC_HW_ERR_HBM1_CHNL2_FATAL},
> +	[13]        = {"HBM SS1: Channel3",                     XE_SOC_HW_ERR_HBM1_CHNL3_FATAL},
> +	[14]        = {"HBM SS1: Channel4",                     XE_SOC_HW_ERR_HBM1_CHNL4_FATAL},
> +	[15]        = {"HBM SS1: Channel5",                     XE_SOC_HW_ERR_HBM1_CHNL5_FATAL},
> +	[16]        = {"HBM SS1: Channel6",                     XE_SOC_HW_ERR_HBM1_CHNL6_FATAL},
> +	[17]        = {"HBM SS1: Channel7",                     XE_SOC_HW_ERR_HBM1_CHNL7_FATAL},
> +	[18]	    = {"PUNIT",					XE_SOC_HW_ERR_PUNIT_FATAL},
> +	[19 ... 31] = {"Undefined",				XE_SOC_HW_ERR_UNKNOWN_FATAL},
> +};
> +
> +static const struct err_msg_cntr_pair soc_slave_glbl_err_reg_fatal[] = {
> +	[0]         = {"SLAVE LOCAL Reported",			XE_SOC_HW_ERR_SLAVE_LCL_FATAL},
> +	[1]         = {"HBM SS2: Channel0",			XE_SOC_HW_ERR_HBM2_CHNL0_FATAL},
> +	[2]         = {"HBM SS2: Channel1",			XE_SOC_HW_ERR_HBM2_CHNL1_FATAL},
> +	[3]         = {"HBM SS2: Channel2",			XE_SOC_HW_ERR_HBM2_CHNL2_FATAL},
> +	[4]         = {"HBM SS2: Channel3",			XE_SOC_HW_ERR_HBM2_CHNL3_FATAL},
> +	[5]         = {"HBM SS2: Channel4",			XE_SOC_HW_ERR_HBM2_CHNL4_FATAL},
> +	[6]         = {"HBM SS2: Channel5",			XE_SOC_HW_ERR_HBM2_CHNL5_FATAL},
> +	[7]         = {"HBM SS2: Channel6",                     XE_SOC_HW_ERR_HBM2_CHNL6_FATAL},
> +	[8]         = {"HBM SS2: Channel7",                     XE_SOC_HW_ERR_HBM2_CHNL7_FATAL},
> +	[9]         = {"HBM SS3: Channel0",                     XE_SOC_HW_ERR_HBM3_CHNL0_FATAL},
> +	[10]        = {"HBM SS3: Channel1",                     XE_SOC_HW_ERR_HBM3_CHNL1_FATAL},
> +	[11]        = {"HBM SS3: Channel2",                     XE_SOC_HW_ERR_HBM3_CHNL2_FATAL},
> +	[12]        = {"HBM SS3: Channel3",                     XE_SOC_HW_ERR_HBM3_CHNL3_FATAL},
> +	[13]        = {"HBM SS3: Channel4",                     XE_SOC_HW_ERR_HBM3_CHNL4_FATAL},
> +	[14]        = {"HBM SS3: Channel5",                     XE_SOC_HW_ERR_HBM3_CHNL5_FATAL},
> +	[15]        = {"HBM SS3: Channel6",                     XE_SOC_HW_ERR_HBM3_CHNL6_FATAL},
> +	[16]        = {"HBM SS3: Channel7",                     XE_SOC_HW_ERR_HBM3_CHNL7_FATAL},
> +	[18]	    = {"ANR MDFI",				XE_SOC_HW_ERR_ANR_MDFI_FATAL},
> +	[17]        = {"Undefined",                             XE_SOC_HW_ERR_UNKNOWN_FATAL},
> +	[19 ... 31] = {"Undefined",				XE_SOC_HW_ERR_UNKNOWN_FATAL},
> +};
> +
> +static const struct err_msg_cntr_pair soc_slave_lcl_err_reg_fatal[] = {
> +	[0]         = {"Local IEH Internal: Malformed PCIe AER",     XE_SOC_HW_ERR_PCIE_AER_FATAL},
> +	[1]         = {"Local IEH Internal: Malformed PCIe ERR",     XE_SOC_HW_ERR_PCIE_ERR_FATAL},
> +	[2]         = {"Local IEH Internal: UR CONDITIONS IN IEH",   XE_SOC_HW_ERR_UR_COND_FATAL},
> +	[3]         = {"Local IEH Internal: FROM SERR SOURCES",      XE_SOC_HW_ERR_SERR_SRCS_FATAL},
> +	[4 ... 31]  = {"Undefined",				     XE_SOC_HW_ERR_UNKNOWN_FATAL},
> +};
> +
> +static const struct err_msg_cntr_pair soc_mstr_lcl_err_reg_fatal[] = {
> +	[0 ... 3]   = {"Undefined",				XE_SOC_HW_ERR_UNKNOWN_FATAL},
> +	[4]         = {"Base Die MDFI T2T",			XE_SOC_HW_ERR_MDFI_T2T_FATAL},
> +	[5]         = {"Undefined",				XE_SOC_HW_ERR_UNKNOWN_FATAL},
> +	[6]         = {"Base Die MDFI T2C",			XE_SOC_HW_ERR_MDFI_T2C_FATAL},
> +	[7]         = {"Undefined",				XE_SOC_HW_ERR_UNKNOWN_FATAL},
> +	[8]         = {"Invalid CSC PSF Command Parity",	XE_SOC_HW_ERR_CSC_PSF_CMD_FATAL},
> +	[9]         = {"Invalid CSC PSF Unexpected Completion",	XE_SOC_HW_ERR_CSC_PSF_CMP_FATAL},
> +	[10]        = {"Invalid CSC PSF Unsupported Request",	XE_SOC_HW_ERR_CSC_PSF_REQ_FATAL},
> +	[11]        = {"Invalid PCIe PSF Command Parity",	XE_SOC_HW_ERR_PCIE_PSF_CMD_FATAL},
> +	[12]        = {"PCIe PSF Unexpected Completion",	XE_SOC_HW_ERR_PCIE_PSF_CMP_FATAL},
> +	[13]        = {"PCIe PSF Unsupported Request",		XE_SOC_HW_ERR_PCIE_PSF_REQ_FATAL},
> +	[14 ... 31] = {"Undefined",				XE_SOC_HW_ERR_UNKNOWN_FATAL},
> +};
> +

we shall think of future extensibility, like we do in xe_assign_hw_err_regs depending on platform for
other registers.
>  static void xe_assign_hw_err_regs(struct xe_device *xe)
>  {
>  	const struct err_msg_cntr_pair **dev_err_stat = xe->hw_err_regs.dev_err_stat;
> @@ -451,6 +520,104 @@ xe_gsc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
>  	xe_mmio_write32(mmio, GSC_HEC_ERR_STAT_REG(base, hw_err), errsrc);
>  }
>  
> +static void
> +xe_soc_log_err_update_cntr(struct xe_tile *tile,
> +			   u32 errbit, const struct err_msg_cntr_pair *reg_info)
> +{
> +	const char *errmsg;
> +	u32 indx;
> +
> +	errmsg = reg_info[errbit].errmsg;
> +	indx = reg_info[errbit].cntr_indx;
> +
> +	drm_err_ratelimited(&tile_to_xe(tile)->drm, HW_ERR
> +			    "Tile%d %s SOC FATAL error, bit[%d] is set\n",
> +			    tile->id, errmsg, errbit);
> +	tile->errors.count[indx]++;
> +}
> +
> +static void
> +xe_soc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
> +{
> +	unsigned long mst_glb_errstat, slv_glb_errstat, lcl_errstat;
> +	u32 errbit, base, slave_base;
> +	int i;
> +	struct xe_gt *gt = tile->primary_gt;
> +
> +	lockdep_assert_held(&tile_to_xe(tile)->irq.lock);
> +
> +	if ((tile_to_xe(tile)->info.platform != XE_PVC) && hw_err != HARDWARE_ERROR_FATAL)
> +		return;
> +
> +	base = SOC_PVC_BASE;
> +	slave_base = SOC_PVC_SLAVE_BASE;
> +
> +	/*
> +	 * Mask error type in GSYSEVTCTL so that no new errors of the type
> +	 * will be reported. Read the master global IEH error register if
> +	 * BIT 1 is set then process the slave IEH first. If BIT 0 in
> +	 * global error register is set then process the corresponding
> +	 * Local error registers
> +	 */
> +	for (i = 0; i < PVC_NUM_IEH; i++)
> +		xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base, i), ~REG_BIT(hw_err));
> +
> +	mst_glb_errstat = xe_mmio_read32(gt, SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err));
> +	drm_info(&tile_to_xe(tile)->drm, HW_ERR
> +		 "Tile%d SOC_GLOBAL_ERR_STAT_MASTER_REG_FATAL:0x%08lx\n",
> +		 tile->id, mst_glb_errstat);
> +
> +	if (mst_glb_errstat & REG_BIT(SOC_SLAVE_IEH)) {
> +		slv_glb_errstat = xe_mmio_read32(gt,
> +						 SOC_GLOBAL_ERR_STAT_SLAVE_REG(slave_base, hw_err));
> +		 drm_info(&tile_to_xe(tile)->drm, HW_ERR
> +			  "Tile%d SOC_GLOBAL_ERR_STAT_SLAVE_REG_FATAL:0x%08lx\n",
> +			  tile->id, slv_glb_errstat);
> +
> +		if (slv_glb_errstat & REG_BIT(SOC_IEH1_LOCAL_ERR_STATUS)) {
> +			lcl_errstat = xe_mmio_read32(gt, SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base,
> +										      hw_err));
> +			 drm_info(&tile_to_xe(tile)->drm, HW_ERR
> +				  "Tile%d SOC_LOCAL_ERR_STAT_SLAVE_REG_FATAL:0x%08lx\n",
> +				  tile->id, lcl_errstat);
> +
> +			for_each_set_bit(errbit, &lcl_errstat, 32)
> +				xe_soc_log_err_update_cntr(tile, errbit,
> +							   soc_slave_lcl_err_reg_fatal);
> +
> +			xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
> +					lcl_errstat);
> +		}
> +
> +		for_each_set_bit(errbit, &slv_glb_errstat, 32)
> +			xe_soc_log_err_update_cntr(tile, errbit, soc_slave_glbl_err_reg_fatal);
> +
> +		xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
> +				slv_glb_errstat);
> +	}
> +
> +	if (mst_glb_errstat & REG_BIT(SOC_IEH0_LOCAL_ERR_STATUS)) {
> +		lcl_errstat = xe_mmio_read32(gt, SOC_LOCAL_ERR_STAT_MASTER_REG(base, hw_err));
> +		drm_info(&tile_to_xe(tile)->drm, HW_ERR "SOC_LOCAL_ERR_STAT_MASTER_REG_FATAL:0x%08lx\n",
> +			 lcl_errstat);
> +
> +		for_each_set_bit(errbit, &lcl_errstat, 32)
> +			xe_soc_log_err_update_cntr(tile, errbit, soc_mstr_lcl_err_reg_fatal);
> +
> +		xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_MASTER_REG(base, hw_err), lcl_errstat);
> +	}
> +
> +	for_each_set_bit(errbit, &mst_glb_errstat, 32)
> +		xe_soc_log_err_update_cntr(tile, errbit, soc_mstr_glbl_err_reg_fatal);
> +
> +	xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err),
> +			mst_glb_errstat);
> +
> +	for (i = 0; i < PVC_NUM_IEH; i++)
> +		xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base, i),
> +				(HARDWARE_ERROR_MAX << 1) + 1);
> +}
> +
>  static void
>  xe_hw_error_source_handler(struct xe_tile *tile, const enum hardware_error hw_err)
>  {
> @@ -498,6 +665,9 @@ xe_hw_error_source_handler(struct xe_tile *tile, const enum hardware_error hw_er
>  
>  		if (errbit == 8)
>  			xe_gsc_hw_error_handler(tile, hw_err);
> +
> +		if (errbit == 16)
> +			xe_soc_hw_error_handler(tile, hw_err);
>  	}
>  
>  	xe_mmio_write32(mmio, DEV_ERR_STAT_REG(hw_err), errsrc);
> diff --git a/drivers/gpu/drm/xe/xe_hw_error.h b/drivers/gpu/drm/xe/xe_hw_error.h
> index ee7705b3343b..05838e082abd 100644
> --- a/drivers/gpu/drm/xe/xe_hw_error.h
> +++ b/drivers/gpu/drm/xe/xe_hw_error.h
> @@ -65,6 +65,56 @@ enum xe_tile_hw_errors {
>  	XE_GSC_HW_ERR_SELF_MBIST_UNCOR,
>  	XE_GSC_HW_ERR_AON_RF_PARITY_UNCOR,
>  	XE_GSC_HW_ERR_UNKNOWN_UNCOR,
> +	XE_SOC_HW_ERR_MSTR_LCL_FATAL,
> +	XE_SOC_HW_ERR_SLAVE_GLBL_FATAL,
> +	XE_SOC_HW_ERR_HBM0_CHNL0_FATAL,
> +	XE_SOC_HW_ERR_HBM0_CHNL1_FATAL,
> +	XE_SOC_HW_ERR_HBM0_CHNL2_FATAL,
> +	XE_SOC_HW_ERR_HBM0_CHNL3_FATAL,
> +	XE_SOC_HW_ERR_HBM0_CHNL4_FATAL,
> +	XE_SOC_HW_ERR_HBM0_CHNL5_FATAL,
> +	XE_SOC_HW_ERR_HBM0_CHNL6_FATAL,
> +	XE_SOC_HW_ERR_HBM0_CHNL7_FATAL,
> +	XE_SOC_HW_ERR_HBM1_CHNL0_FATAL,
> +	XE_SOC_HW_ERR_HBM1_CHNL1_FATAL,
> +	XE_SOC_HW_ERR_HBM1_CHNL2_FATAL,
> +	XE_SOC_HW_ERR_HBM1_CHNL3_FATAL,
> +	XE_SOC_HW_ERR_HBM1_CHNL4_FATAL,
> +	XE_SOC_HW_ERR_HBM1_CHNL5_FATAL,
> +	XE_SOC_HW_ERR_HBM1_CHNL6_FATAL,
> +	XE_SOC_HW_ERR_HBM1_CHNL7_FATAL,
> +	XE_SOC_HW_ERR_PUNIT_FATAL,
> +	XE_SOC_HW_ERR_UNKNOWN_FATAL,
> +	XE_SOC_HW_ERR_SLAVE_LCL_FATAL,
> +	XE_SOC_HW_ERR_HBM2_CHNL0_FATAL,
> +	XE_SOC_HW_ERR_HBM2_CHNL1_FATAL,
> +	XE_SOC_HW_ERR_HBM2_CHNL2_FATAL,
> +	XE_SOC_HW_ERR_HBM2_CHNL3_FATAL,
> +	XE_SOC_HW_ERR_HBM2_CHNL4_FATAL,
> +	XE_SOC_HW_ERR_HBM2_CHNL5_FATAL,
> +	XE_SOC_HW_ERR_HBM2_CHNL6_FATAL,
> +	XE_SOC_HW_ERR_HBM2_CHNL7_FATAL,
> +	XE_SOC_HW_ERR_HBM3_CHNL0_FATAL,
> +	XE_SOC_HW_ERR_HBM3_CHNL1_FATAL,
> +	XE_SOC_HW_ERR_HBM3_CHNL2_FATAL,
> +	XE_SOC_HW_ERR_HBM3_CHNL3_FATAL,
> +	XE_SOC_HW_ERR_HBM3_CHNL4_FATAL,
> +	XE_SOC_HW_ERR_HBM3_CHNL5_FATAL,
> +	XE_SOC_HW_ERR_HBM3_CHNL6_FATAL,
> +	XE_SOC_HW_ERR_HBM3_CHNL7_FATAL,
> +	XE_SOC_HW_ERR_ANR_MDFI_FATAL,
> +	XE_SOC_HW_ERR_PCIE_AER_FATAL,
> +	XE_SOC_HW_ERR_PCIE_ERR_FATAL,
> +	XE_SOC_HW_ERR_UR_COND_FATAL,
> +	XE_SOC_HW_ERR_SERR_SRCS_FATAL,
> +	XE_SOC_HW_ERR_MDFI_T2T_FATAL,
> +	XE_SOC_HW_ERR_MDFI_T2C_FATAL,
> +	XE_SOC_HW_ERR_CSC_PSF_CMD_FATAL,
> +	XE_SOC_HW_ERR_CSC_PSF_CMP_FATAL,
> +	XE_SOC_HW_ERR_CSC_PSF_REQ_FATAL,
> +	XE_SOC_HW_ERR_PCIE_PSF_CMD_FATAL,
> +	XE_SOC_HW_ERR_PCIE_PSF_CMP_FATAL,
> +	XE_SOC_HW_ERR_PCIE_PSF_REQ_FATAL,
even though soc errors fall under a tile it is better if we shall have a
separate enum for soc errors for 2 reasons, the other errors in
xe_tile_hw_errors are from top level registers while SOC are from second level
and also because these errors are most likely different on different platforms.
so, we shall extend struct tile_hw_errors to have separate entry for soc.


Also, I'm thinking if we shall use xarray types for all members in error counters under tile and gt
with the enum list being big and which will increase with each new platform.

Thanks,
Aravind.

>  	XE_TILE_HW_ERROR_MAX,
>  };
>  
> @@ -109,8 +159,12 @@ enum xe_gt_hw_errors {
>  	XE_GT_HW_ERROR_MAX,
>  };
>  
> -#define ERR_STAT_GT_COR_VCTR_LEN (4)
> -#define ERR_STAT_GT_FATAL_VCTR_LEN (8)
> +#define ERR_STAT_GT_COR_VCTR_LEN	(4)
> +#define ERR_STAT_GT_FATAL_VCTR_LEN	(8)
> +#define PVC_NUM_IEH			(1)
> +#define SOC_SLAVE_IEH                   (1)
> +#define SOC_IEH0_LOCAL_ERR_STATUS       (0)
> +#define SOC_IEH1_LOCAL_ERR_STATUS       (0)
>  
>  struct err_msg_cntr_pair {
>  	const char *errmsg;

Re: [Intel-xe] [PATCH 07/11] drm/xe: Support SOC FATAL error handling for PVC.

[Ghimiray, Himal Prasad]

[-- Attachment #1: Type: text/plain, Size: 16470 bytes --]


On 04-10-2023 12:08, Aravind Iddamsetty wrote:
> On 27/09/23 17:16, Himal Prasad Ghimiray wrote:
> Hi Himal,
>
> I'm yet to review the full patch but sharing a few initial comments.

Hi Aravind,

Thanks for the review comments.

>
>> Report the SOC fatal hardware error and update the counters which will
>> increment incase of error.
>>
>> Signed-off-by: Himal Prasad Ghimiray<himal.prasad.ghimiray@intel.com>
>> ---
>>   drivers/gpu/drm/xe/regs/xe_tile_error_regs.h |  28 +++
>>   drivers/gpu/drm/xe/xe_hw_error.c             | 170 +++++++++++++++++++
>>   drivers/gpu/drm/xe/xe_hw_error.h             |  58 ++++++-
>>   3 files changed, 254 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
>> index fa16eaf9436b..04701c62f0d9 100644
>> --- a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
>> +++ b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
>> @@ -20,4 +20,32 @@
>>   #define GSC_HEC_ERR_STAT_REG(base, x)                  XE_REG(_PICK_EVEN((x), \
>>   								(base) + _GSC_HEC_CORR_ERR_STATUS, \
>>   								(base) + _GSC_HEC_UNCOR_ERR_STATUS))
>> +#define SOC_PVC_BASE	               0x00282000
>> +#define SOC_PVC_SLAVE_BASE             0x00283000
>> +
>> +#define _SOC_LERRCORSTS		       0x000294
>> +#define _SOC_LERRUNCSTS		       0x000280
>> +#define SOC_LOCAL_ERR_STAT_SLAVE_REG(base, x)		XE_REG((x) > HARDWARE_ERROR_CORRECTABLE ? \
>> +								(base) + _SOC_LERRUNCSTS : \
>> +								(base) + _SOC_LERRCORSTS)
>> +
>> +#define SOC_LOCAL_ERR_STAT_MASTER_REG(base, x)		XE_REG((x) > HARDWARE_ERROR_CORRECTABLE ? \
>> +								(base) + _SOC_LERRUNCSTS : \
>> +								(base) + _SOC_LERRCORSTS)
>> +#define _SOC_GSYSEVTCTL		        0x000264
>> +
>> +#define SOC_GSYSEVTCTL_REG(base, slave_base, x)		XE_REG(_PICK_EVEN((x), \
>> +								(base) + _SOC_GSYSEVTCTL, \
>> +								slave_base + _SOC_GSYSEVTCTL))
>> +#define _SOC_GCOERRSTS		        0x000200
>> +#define _SOC_GNFERRSTS		        0x000210
>> +#define _SOC_GFAERRSTS		        0x000220
>> +#define SOC_GLOBAL_ERR_STAT_SLAVE_REG(base, x)		XE_REG(_PICK_EVEN((x), \
>> +								(base) + _SOC_GCOERRSTS, \
>> +								(base) + _SOC_GNFERRSTS))
>> +
>> +#define SOC_GLOBAL_ERR_STAT_MASTER_REG(base, x)		XE_REG(_PICK_EVEN((x), \
>> +								(base) + _SOC_GCOERRSTS, \
>> +								(base) + _SOC_GNFERRSTS))
>> +
>>   #endif
>> diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
>> index 76ae12df013c..fa05bad5e684 100644
>> --- a/drivers/gpu/drm/xe/xe_hw_error.c
>> +++ b/drivers/gpu/drm/xe/xe_hw_error.c
>> @@ -207,6 +207,75 @@ static const struct err_msg_cntr_pair gsc_correctable_err_reg[] = {
>>   	[2 ... 31] = {"Undefined",					XE_GSC_HW_ERR_UNKNOWN_CORR},
>>   };
>>   
>> +static const struct err_msg_cntr_pair soc_mstr_glbl_err_reg_fatal[] = {
>> +	[0]         = {"MASTER LOCAL Reported",			XE_SOC_HW_ERR_MSTR_LCL_FATAL},
>> +	[1]         = {"SLAVE GLOBAL Reported",			XE_SOC_HW_ERR_SLAVE_GLBL_FATAL},
>> +	[2]         = {"HBM SS0: Channel0",			XE_SOC_HW_ERR_HBM0_CHNL0_FATAL},
>> +	[3]         = {"HBM SS0: Channel1",			XE_SOC_HW_ERR_HBM0_CHNL1_FATAL},
>> +	[4]         = {"HBM SS0: Channel2",			XE_SOC_HW_ERR_HBM0_CHNL2_FATAL},
>> +	[5]         = {"HBM SS0: Channel3",			XE_SOC_HW_ERR_HBM0_CHNL3_FATAL},
>> +	[6]         = {"HBM SS0: Channel4",			XE_SOC_HW_ERR_HBM0_CHNL4_FATAL},
>> +	[7]         = {"HBM SS0: Channel5",			XE_SOC_HW_ERR_HBM0_CHNL5_FATAL},
>> +	[8]         = {"HBM SS0: Channel6",                     XE_SOC_HW_ERR_HBM0_CHNL6_FATAL},
>> +	[9]         = {"HBM SS0: Channel7",                     XE_SOC_HW_ERR_HBM0_CHNL7_FATAL},
>> +	[10]        = {"HBM SS1: Channel0",                     XE_SOC_HW_ERR_HBM1_CHNL0_FATAL},
>> +	[11]        = {"HBM SS1: Channel1",                     XE_SOC_HW_ERR_HBM1_CHNL1_FATAL},
>> +	[12]        = {"HBM SS1: Channel2",                     XE_SOC_HW_ERR_HBM1_CHNL2_FATAL},
>> +	[13]        = {"HBM SS1: Channel3",                     XE_SOC_HW_ERR_HBM1_CHNL3_FATAL},
>> +	[14]        = {"HBM SS1: Channel4",                     XE_SOC_HW_ERR_HBM1_CHNL4_FATAL},
>> +	[15]        = {"HBM SS1: Channel5",                     XE_SOC_HW_ERR_HBM1_CHNL5_FATAL},
>> +	[16]        = {"HBM SS1: Channel6",                     XE_SOC_HW_ERR_HBM1_CHNL6_FATAL},
>> +	[17]        = {"HBM SS1: Channel7",                     XE_SOC_HW_ERR_HBM1_CHNL7_FATAL},
>> +	[18]	    = {"PUNIT",					XE_SOC_HW_ERR_PUNIT_FATAL},
>> +	[19 ... 31] = {"Undefined",				XE_SOC_HW_ERR_UNKNOWN_FATAL},
>> +};
>> +
>> +static const struct err_msg_cntr_pair soc_slave_glbl_err_reg_fatal[] = {
>> +	[0]         = {"SLAVE LOCAL Reported",			XE_SOC_HW_ERR_SLAVE_LCL_FATAL},
>> +	[1]         = {"HBM SS2: Channel0",			XE_SOC_HW_ERR_HBM2_CHNL0_FATAL},
>> +	[2]         = {"HBM SS2: Channel1",			XE_SOC_HW_ERR_HBM2_CHNL1_FATAL},
>> +	[3]         = {"HBM SS2: Channel2",			XE_SOC_HW_ERR_HBM2_CHNL2_FATAL},
>> +	[4]         = {"HBM SS2: Channel3",			XE_SOC_HW_ERR_HBM2_CHNL3_FATAL},
>> +	[5]         = {"HBM SS2: Channel4",			XE_SOC_HW_ERR_HBM2_CHNL4_FATAL},
>> +	[6]         = {"HBM SS2: Channel5",			XE_SOC_HW_ERR_HBM2_CHNL5_FATAL},
>> +	[7]         = {"HBM SS2: Channel6",                     XE_SOC_HW_ERR_HBM2_CHNL6_FATAL},
>> +	[8]         = {"HBM SS2: Channel7",                     XE_SOC_HW_ERR_HBM2_CHNL7_FATAL},
>> +	[9]         = {"HBM SS3: Channel0",                     XE_SOC_HW_ERR_HBM3_CHNL0_FATAL},
>> +	[10]        = {"HBM SS3: Channel1",                     XE_SOC_HW_ERR_HBM3_CHNL1_FATAL},
>> +	[11]        = {"HBM SS3: Channel2",                     XE_SOC_HW_ERR_HBM3_CHNL2_FATAL},
>> +	[12]        = {"HBM SS3: Channel3",                     XE_SOC_HW_ERR_HBM3_CHNL3_FATAL},
>> +	[13]        = {"HBM SS3: Channel4",                     XE_SOC_HW_ERR_HBM3_CHNL4_FATAL},
>> +	[14]        = {"HBM SS3: Channel5",                     XE_SOC_HW_ERR_HBM3_CHNL5_FATAL},
>> +	[15]        = {"HBM SS3: Channel6",                     XE_SOC_HW_ERR_HBM3_CHNL6_FATAL},
>> +	[16]        = {"HBM SS3: Channel7",                     XE_SOC_HW_ERR_HBM3_CHNL7_FATAL},
>> +	[18]	    = {"ANR MDFI",				XE_SOC_HW_ERR_ANR_MDFI_FATAL},
>> +	[17]        = {"Undefined",                             XE_SOC_HW_ERR_UNKNOWN_FATAL},
>> +	[19 ... 31] = {"Undefined",				XE_SOC_HW_ERR_UNKNOWN_FATAL},
>> +};
>> +
>> +static const struct err_msg_cntr_pair soc_slave_lcl_err_reg_fatal[] = {
>> +	[0]         = {"Local IEH Internal: Malformed PCIe AER",     XE_SOC_HW_ERR_PCIE_AER_FATAL},
>> +	[1]         = {"Local IEH Internal: Malformed PCIe ERR",     XE_SOC_HW_ERR_PCIE_ERR_FATAL},
>> +	[2]         = {"Local IEH Internal: UR CONDITIONS IN IEH",   XE_SOC_HW_ERR_UR_COND_FATAL},
>> +	[3]         = {"Local IEH Internal: FROM SERR SOURCES",      XE_SOC_HW_ERR_SERR_SRCS_FATAL},
>> +	[4 ... 31]  = {"Undefined",				     XE_SOC_HW_ERR_UNKNOWN_FATAL},
>> +};
>> +
>> +static const struct err_msg_cntr_pair soc_mstr_lcl_err_reg_fatal[] = {
>> +	[0 ... 3]   = {"Undefined",				XE_SOC_HW_ERR_UNKNOWN_FATAL},
>> +	[4]         = {"Base Die MDFI T2T",			XE_SOC_HW_ERR_MDFI_T2T_FATAL},
>> +	[5]         = {"Undefined",				XE_SOC_HW_ERR_UNKNOWN_FATAL},
>> +	[6]         = {"Base Die MDFI T2C",			XE_SOC_HW_ERR_MDFI_T2C_FATAL},
>> +	[7]         = {"Undefined",				XE_SOC_HW_ERR_UNKNOWN_FATAL},
>> +	[8]         = {"Invalid CSC PSF Command Parity",	XE_SOC_HW_ERR_CSC_PSF_CMD_FATAL},
>> +	[9]         = {"Invalid CSC PSF Unexpected Completion",	XE_SOC_HW_ERR_CSC_PSF_CMP_FATAL},
>> +	[10]        = {"Invalid CSC PSF Unsupported Request",	XE_SOC_HW_ERR_CSC_PSF_REQ_FATAL},
>> +	[11]        = {"Invalid PCIe PSF Command Parity",	XE_SOC_HW_ERR_PCIE_PSF_CMD_FATAL},
>> +	[12]        = {"PCIe PSF Unexpected Completion",	XE_SOC_HW_ERR_PCIE_PSF_CMP_FATAL},
>> +	[13]        = {"PCIe PSF Unsupported Request",		XE_SOC_HW_ERR_PCIE_PSF_REQ_FATAL},
>> +	[14 ... 31] = {"Undefined",				XE_SOC_HW_ERR_UNKNOWN_FATAL},
>> +};
>> +
> we shall think of future extensibility, like we do in xe_assign_hw_err_regs depending on platform for
> other registers.

Yes that is in my mind. I was planing to move this struct under 
xe_assign_hw_err_regs once new platform support is added for SOC error 
handling.

But to make things aligned can be taken care rightnow as well. Will 
address in next patch.

>>   static void xe_assign_hw_err_regs(struct xe_device *xe)
>>   {
>>   	const struct err_msg_cntr_pair **dev_err_stat = xe->hw_err_regs.dev_err_stat;
>> @@ -451,6 +520,104 @@ xe_gsc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
>>   	xe_mmio_write32(mmio, GSC_HEC_ERR_STAT_REG(base, hw_err), errsrc);
>>   }
>>   
>> +static void
>> +xe_soc_log_err_update_cntr(struct xe_tile *tile,
>> +			   u32 errbit, const struct err_msg_cntr_pair *reg_info)
>> +{
>> +	const char *errmsg;
>> +	u32 indx;
>> +
>> +	errmsg = reg_info[errbit].errmsg;
>> +	indx = reg_info[errbit].cntr_indx;
>> +
>> +	drm_err_ratelimited(&tile_to_xe(tile)->drm, HW_ERR
>> +			    "Tile%d %s SOC FATAL error, bit[%d] is set\n",
>> +			    tile->id, errmsg, errbit);
>> +	tile->errors.count[indx]++;
>> +}
>> +
>> +static void
>> +xe_soc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
>> +{
>> +	unsigned long mst_glb_errstat, slv_glb_errstat, lcl_errstat;
>> +	u32 errbit, base, slave_base;
>> +	int i;
>> +	struct xe_gt *gt = tile->primary_gt;
>> +
>> +	lockdep_assert_held(&tile_to_xe(tile)->irq.lock);
>> +
>> +	if ((tile_to_xe(tile)->info.platform != XE_PVC) && hw_err != HARDWARE_ERROR_FATAL)
>> +		return;
>> +
>> +	base = SOC_PVC_BASE;
>> +	slave_base = SOC_PVC_SLAVE_BASE;
>> +
>> +	/*
>> +	 * Mask error type in GSYSEVTCTL so that no new errors of the type
>> +	 * will be reported. Read the master global IEH error register if
>> +	 * BIT 1 is set then process the slave IEH first. If BIT 0 in
>> +	 * global error register is set then process the corresponding
>> +	 * Local error registers
>> +	 */
>> +	for (i = 0; i < PVC_NUM_IEH; i++)
>> +		xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base, i), ~REG_BIT(hw_err));
>> +
>> +	mst_glb_errstat = xe_mmio_read32(gt, SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err));
>> +	drm_info(&tile_to_xe(tile)->drm, HW_ERR
>> +		 "Tile%d SOC_GLOBAL_ERR_STAT_MASTER_REG_FATAL:0x%08lx\n",
>> +		 tile->id, mst_glb_errstat);
>> +
>> +	if (mst_glb_errstat & REG_BIT(SOC_SLAVE_IEH)) {
>> +		slv_glb_errstat = xe_mmio_read32(gt,
>> +						 SOC_GLOBAL_ERR_STAT_SLAVE_REG(slave_base, hw_err));
>> +		 drm_info(&tile_to_xe(tile)->drm, HW_ERR
>> +			  "Tile%d SOC_GLOBAL_ERR_STAT_SLAVE_REG_FATAL:0x%08lx\n",
>> +			  tile->id, slv_glb_errstat);
>> +
>> +		if (slv_glb_errstat & REG_BIT(SOC_IEH1_LOCAL_ERR_STATUS)) {
>> +			lcl_errstat = xe_mmio_read32(gt, SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base,
>> +										      hw_err));
>> +			 drm_info(&tile_to_xe(tile)->drm, HW_ERR
>> +				  "Tile%d SOC_LOCAL_ERR_STAT_SLAVE_REG_FATAL:0x%08lx\n",
>> +				  tile->id, lcl_errstat);
>> +
>> +			for_each_set_bit(errbit, &lcl_errstat, 32)
>> +				xe_soc_log_err_update_cntr(tile, errbit,
>> +							   soc_slave_lcl_err_reg_fatal);
>> +
>> +			xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
>> +					lcl_errstat);
>> +		}
>> +
>> +		for_each_set_bit(errbit, &slv_glb_errstat, 32)
>> +			xe_soc_log_err_update_cntr(tile, errbit, soc_slave_glbl_err_reg_fatal);
>> +
>> +		xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
>> +				slv_glb_errstat);
>> +	}
>> +
>> +	if (mst_glb_errstat & REG_BIT(SOC_IEH0_LOCAL_ERR_STATUS)) {
>> +		lcl_errstat = xe_mmio_read32(gt, SOC_LOCAL_ERR_STAT_MASTER_REG(base, hw_err));
>> +		drm_info(&tile_to_xe(tile)->drm, HW_ERR "SOC_LOCAL_ERR_STAT_MASTER_REG_FATAL:0x%08lx\n",
>> +			 lcl_errstat);
>> +
>> +		for_each_set_bit(errbit, &lcl_errstat, 32)
>> +			xe_soc_log_err_update_cntr(tile, errbit, soc_mstr_lcl_err_reg_fatal);
>> +
>> +		xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_MASTER_REG(base, hw_err), lcl_errstat);
>> +	}
>> +
>> +	for_each_set_bit(errbit, &mst_glb_errstat, 32)
>> +		xe_soc_log_err_update_cntr(tile, errbit, soc_mstr_glbl_err_reg_fatal);
>> +
>> +	xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err),
>> +			mst_glb_errstat);
>> +
>> +	for (i = 0; i < PVC_NUM_IEH; i++)
>> +		xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base, i),
>> +				(HARDWARE_ERROR_MAX << 1) + 1);
>> +}
>> +
>>   static void
>>   xe_hw_error_source_handler(struct xe_tile *tile, const enum hardware_error hw_err)
>>   {
>> @@ -498,6 +665,9 @@ xe_hw_error_source_handler(struct xe_tile *tile, const enum hardware_error hw_er
>>   
>>   		if (errbit == 8)
>>   			xe_gsc_hw_error_handler(tile, hw_err);
>> +
>> +		if (errbit == 16)
>> +			xe_soc_hw_error_handler(tile, hw_err);
>>   	}
>>   
>>   	xe_mmio_write32(mmio, DEV_ERR_STAT_REG(hw_err), errsrc);
>> diff --git a/drivers/gpu/drm/xe/xe_hw_error.h b/drivers/gpu/drm/xe/xe_hw_error.h
>> index ee7705b3343b..05838e082abd 100644
>> --- a/drivers/gpu/drm/xe/xe_hw_error.h
>> +++ b/drivers/gpu/drm/xe/xe_hw_error.h
>> @@ -65,6 +65,56 @@ enum xe_tile_hw_errors {
>>   	XE_GSC_HW_ERR_SELF_MBIST_UNCOR,
>>   	XE_GSC_HW_ERR_AON_RF_PARITY_UNCOR,
>>   	XE_GSC_HW_ERR_UNKNOWN_UNCOR,
>> +	XE_SOC_HW_ERR_MSTR_LCL_FATAL,
>> +	XE_SOC_HW_ERR_SLAVE_GLBL_FATAL,
>> +	XE_SOC_HW_ERR_HBM0_CHNL0_FATAL,
>> +	XE_SOC_HW_ERR_HBM0_CHNL1_FATAL,
>> +	XE_SOC_HW_ERR_HBM0_CHNL2_FATAL,
>> +	XE_SOC_HW_ERR_HBM0_CHNL3_FATAL,
>> +	XE_SOC_HW_ERR_HBM0_CHNL4_FATAL,
>> +	XE_SOC_HW_ERR_HBM0_CHNL5_FATAL,
>> +	XE_SOC_HW_ERR_HBM0_CHNL6_FATAL,
>> +	XE_SOC_HW_ERR_HBM0_CHNL7_FATAL,
>> +	XE_SOC_HW_ERR_HBM1_CHNL0_FATAL,
>> +	XE_SOC_HW_ERR_HBM1_CHNL1_FATAL,
>> +	XE_SOC_HW_ERR_HBM1_CHNL2_FATAL,
>> +	XE_SOC_HW_ERR_HBM1_CHNL3_FATAL,
>> +	XE_SOC_HW_ERR_HBM1_CHNL4_FATAL,
>> +	XE_SOC_HW_ERR_HBM1_CHNL5_FATAL,
>> +	XE_SOC_HW_ERR_HBM1_CHNL6_FATAL,
>> +	XE_SOC_HW_ERR_HBM1_CHNL7_FATAL,
>> +	XE_SOC_HW_ERR_PUNIT_FATAL,
>> +	XE_SOC_HW_ERR_UNKNOWN_FATAL,
>> +	XE_SOC_HW_ERR_SLAVE_LCL_FATAL,
>> +	XE_SOC_HW_ERR_HBM2_CHNL0_FATAL,
>> +	XE_SOC_HW_ERR_HBM2_CHNL1_FATAL,
>> +	XE_SOC_HW_ERR_HBM2_CHNL2_FATAL,
>> +	XE_SOC_HW_ERR_HBM2_CHNL3_FATAL,
>> +	XE_SOC_HW_ERR_HBM2_CHNL4_FATAL,
>> +	XE_SOC_HW_ERR_HBM2_CHNL5_FATAL,
>> +	XE_SOC_HW_ERR_HBM2_CHNL6_FATAL,
>> +	XE_SOC_HW_ERR_HBM2_CHNL7_FATAL,
>> +	XE_SOC_HW_ERR_HBM3_CHNL0_FATAL,
>> +	XE_SOC_HW_ERR_HBM3_CHNL1_FATAL,
>> +	XE_SOC_HW_ERR_HBM3_CHNL2_FATAL,
>> +	XE_SOC_HW_ERR_HBM3_CHNL3_FATAL,
>> +	XE_SOC_HW_ERR_HBM3_CHNL4_FATAL,
>> +	XE_SOC_HW_ERR_HBM3_CHNL5_FATAL,
>> +	XE_SOC_HW_ERR_HBM3_CHNL6_FATAL,
>> +	XE_SOC_HW_ERR_HBM3_CHNL7_FATAL,
>> +	XE_SOC_HW_ERR_ANR_MDFI_FATAL,
>> +	XE_SOC_HW_ERR_PCIE_AER_FATAL,
>> +	XE_SOC_HW_ERR_PCIE_ERR_FATAL,
>> +	XE_SOC_HW_ERR_UR_COND_FATAL,
>> +	XE_SOC_HW_ERR_SERR_SRCS_FATAL,
>> +	XE_SOC_HW_ERR_MDFI_T2T_FATAL,
>> +	XE_SOC_HW_ERR_MDFI_T2C_FATAL,
>> +	XE_SOC_HW_ERR_CSC_PSF_CMD_FATAL,
>> +	XE_SOC_HW_ERR_CSC_PSF_CMP_FATAL,
>> +	XE_SOC_HW_ERR_CSC_PSF_REQ_FATAL,
>> +	XE_SOC_HW_ERR_PCIE_PSF_CMD_FATAL,
>> +	XE_SOC_HW_ERR_PCIE_PSF_CMP_FATAL,
>> +	XE_SOC_HW_ERR_PCIE_PSF_REQ_FATAL,
> even though soc errors fall under a tile it is better if we shall have a
> separate enum for soc errors for 2 reasons, the other errors in
> xe_tile_hw_errors are from top level registers while SOC are from second level
> and also because these errors are most likely different on different platforms.
> so, we shall extend struct tile_hw_errors to have separate entry for soc.
Makes sense. WIll address in next patch.
>
>
> Also, I'm thinking if we shall use xarray types for all members in error counters under tile and gt
> with the enum list being big and which will increase with each new platform.

My initial thought was also to use xarray for soc error counters. But 
even if we use xarray we need to have separate identifiers to identify 
which indexes in xarray are actually valid hardware error and which are 
spurious interrupt. Hence found no use of using xarray, if we still need 
to maintain all valid indexes.

BR

Himal Ghimiray

>
> Thanks,
> Aravind.
>
>>   	XE_TILE_HW_ERROR_MAX,
>>   };
>>   
>> @@ -109,8 +159,12 @@ enum xe_gt_hw_errors {
>>   	XE_GT_HW_ERROR_MAX,
>>   };
>>   
>> -#define ERR_STAT_GT_COR_VCTR_LEN (4)
>> -#define ERR_STAT_GT_FATAL_VCTR_LEN (8)
>> +#define ERR_STAT_GT_COR_VCTR_LEN	(4)
>> +#define ERR_STAT_GT_FATAL_VCTR_LEN	(8)
>> +#define PVC_NUM_IEH			(1)
>> +#define SOC_SLAVE_IEH                   (1)
>> +#define SOC_IEH0_LOCAL_ERR_STATUS       (0)
>> +#define SOC_IEH1_LOCAL_ERR_STATUS       (0)
>>   
>>   struct err_msg_cntr_pair {
>>   	const char *errmsg;

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Re: [Intel-xe] [PATCH 07/11] drm/xe: Support SOC FATAL error handling for PVC.

[Aravind Iddamsetty]

On 04/10/23 12:20, Ghimiray, Himal Prasad wrote:
>
> On 04-10-2023 12:08, Aravind Iddamsetty wrote:
>> On 27/09/23 17:16, Himal Prasad Ghimiray wrote:
>> Hi Himal,
>>
>> I'm yet to review the full patch but sharing a few initial comments.
>
> Hi Aravind,
>
> Thanks for the review comments.
>
>>
>>> Report the SOC fatal hardware error and update the counters which will
>>> increment incase of error.
>>>
>>> Signed-off-by: Himal Prasad Ghimiray<himal.prasad.ghimiray@intel.com>
>>> ---
>>>   drivers/gpu/drm/xe/regs/xe_tile_error_regs.h |  28 +++
>>>   drivers/gpu/drm/xe/xe_hw_error.c             | 170 +++++++++++++++++++
>>>   drivers/gpu/drm/xe/xe_hw_error.h             |  58 ++++++-
>>>   3 files changed, 254 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
>>> index fa16eaf9436b..04701c62f0d9 100644
>>> --- a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
>>> +++ b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
>>> @@ -20,4 +20,32 @@
>>>   #define GSC_HEC_ERR_STAT_REG(base, x)                  XE_REG(_PICK_EVEN((x), \
>>>                                   (base) + _GSC_HEC_CORR_ERR_STATUS, \
>>>                                   (base) + _GSC_HEC_UNCOR_ERR_STATUS))
>>> +#define SOC_PVC_BASE                   0x00282000
>>> +#define SOC_PVC_SLAVE_BASE             0x00283000
>>> +
>>> +#define _SOC_LERRCORSTS               0x000294
>>> +#define _SOC_LERRUNCSTS               0x000280
>>> +#define SOC_LOCAL_ERR_STAT_SLAVE_REG(base, x)        XE_REG((x) > HARDWARE_ERROR_CORRECTABLE ? \
>>> +                                (base) + _SOC_LERRUNCSTS : \
>>> +                                (base) + _SOC_LERRCORSTS)
>>> +
>>> +#define SOC_LOCAL_ERR_STAT_MASTER_REG(base, x)        XE_REG((x) > HARDWARE_ERROR_CORRECTABLE ? \
>>> +                                (base) + _SOC_LERRUNCSTS : \
>>> +                                (base) + _SOC_LERRCORSTS)
>>> +#define _SOC_GSYSEVTCTL                0x000264
>>> +
>>> +#define SOC_GSYSEVTCTL_REG(base, slave_base, x)        XE_REG(_PICK_EVEN((x), \
>>> +                                (base) + _SOC_GSYSEVTCTL, \
>>> +                                slave_base + _SOC_GSYSEVTCTL))
>>> +#define _SOC_GCOERRSTS                0x000200
>>> +#define _SOC_GNFERRSTS                0x000210
>>> +#define _SOC_GFAERRSTS                0x000220
>>> +#define SOC_GLOBAL_ERR_STAT_SLAVE_REG(base, x)        XE_REG(_PICK_EVEN((x), \
>>> +                                (base) + _SOC_GCOERRSTS, \
>>> +                                (base) + _SOC_GNFERRSTS))
>>> +
>>> +#define SOC_GLOBAL_ERR_STAT_MASTER_REG(base, x)        XE_REG(_PICK_EVEN((x), \
>>> +                                (base) + _SOC_GCOERRSTS, \
>>> +                                (base) + _SOC_GNFERRSTS))
>>> +
>>>   #endif
>>> diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
>>> index 76ae12df013c..fa05bad5e684 100644
>>> --- a/drivers/gpu/drm/xe/xe_hw_error.c
>>> +++ b/drivers/gpu/drm/xe/xe_hw_error.c
>>> @@ -207,6 +207,75 @@ static const struct err_msg_cntr_pair gsc_correctable_err_reg[] = {
>>>       [2 ... 31] = {"Undefined",                    XE_GSC_HW_ERR_UNKNOWN_CORR},
>>>   };
>>>   +static const struct err_msg_cntr_pair soc_mstr_glbl_err_reg_fatal[] = {
>>> +    [0]         = {"MASTER LOCAL Reported",            XE_SOC_HW_ERR_MSTR_LCL_FATAL},
>>> +    [1]         = {"SLAVE GLOBAL Reported",            XE_SOC_HW_ERR_SLAVE_GLBL_FATAL},
>>> +    [2]         = {"HBM SS0: Channel0",            XE_SOC_HW_ERR_HBM0_CHNL0_FATAL},
>>> +    [3]         = {"HBM SS0: Channel1",            XE_SOC_HW_ERR_HBM0_CHNL1_FATAL},
>>> +    [4]         = {"HBM SS0: Channel2",            XE_SOC_HW_ERR_HBM0_CHNL2_FATAL},
>>> +    [5]         = {"HBM SS0: Channel3",            XE_SOC_HW_ERR_HBM0_CHNL3_FATAL},
>>> +    [6]         = {"HBM SS0: Channel4",            XE_SOC_HW_ERR_HBM0_CHNL4_FATAL},
>>> +    [7]         = {"HBM SS0: Channel5",            XE_SOC_HW_ERR_HBM0_CHNL5_FATAL},
>>> +    [8]         = {"HBM SS0: Channel6",                     XE_SOC_HW_ERR_HBM0_CHNL6_FATAL},
>>> +    [9]         = {"HBM SS0: Channel7",                     XE_SOC_HW_ERR_HBM0_CHNL7_FATAL},
>>> +    [10]        = {"HBM SS1: Channel0",                     XE_SOC_HW_ERR_HBM1_CHNL0_FATAL},
>>> +    [11]        = {"HBM SS1: Channel1",                     XE_SOC_HW_ERR_HBM1_CHNL1_FATAL},
>>> +    [12]        = {"HBM SS1: Channel2",                     XE_SOC_HW_ERR_HBM1_CHNL2_FATAL},
>>> +    [13]        = {"HBM SS1: Channel3",                     XE_SOC_HW_ERR_HBM1_CHNL3_FATAL},
>>> +    [14]        = {"HBM SS1: Channel4",                     XE_SOC_HW_ERR_HBM1_CHNL4_FATAL},
>>> +    [15]        = {"HBM SS1: Channel5",                     XE_SOC_HW_ERR_HBM1_CHNL5_FATAL},
>>> +    [16]        = {"HBM SS1: Channel6",                     XE_SOC_HW_ERR_HBM1_CHNL6_FATAL},
>>> +    [17]        = {"HBM SS1: Channel7",                     XE_SOC_HW_ERR_HBM1_CHNL7_FATAL},
>>> +    [18]        = {"PUNIT",                    XE_SOC_HW_ERR_PUNIT_FATAL},
>>> +    [19 ... 31] = {"Undefined",                XE_SOC_HW_ERR_UNKNOWN_FATAL},
>>> +};
>>> +
>>> +static const struct err_msg_cntr_pair soc_slave_glbl_err_reg_fatal[] = {
>>> +    [0]         = {"SLAVE LOCAL Reported",            XE_SOC_HW_ERR_SLAVE_LCL_FATAL},
>>> +    [1]         = {"HBM SS2: Channel0",            XE_SOC_HW_ERR_HBM2_CHNL0_FATAL},
>>> +    [2]         = {"HBM SS2: Channel1",            XE_SOC_HW_ERR_HBM2_CHNL1_FATAL},
>>> +    [3]         = {"HBM SS2: Channel2",            XE_SOC_HW_ERR_HBM2_CHNL2_FATAL},
>>> +    [4]         = {"HBM SS2: Channel3",            XE_SOC_HW_ERR_HBM2_CHNL3_FATAL},
>>> +    [5]         = {"HBM SS2: Channel4",            XE_SOC_HW_ERR_HBM2_CHNL4_FATAL},
>>> +    [6]         = {"HBM SS2: Channel5",            XE_SOC_HW_ERR_HBM2_CHNL5_FATAL},
>>> +    [7]         = {"HBM SS2: Channel6",                     XE_SOC_HW_ERR_HBM2_CHNL6_FATAL},
>>> +    [8]         = {"HBM SS2: Channel7",                     XE_SOC_HW_ERR_HBM2_CHNL7_FATAL},
>>> +    [9]         = {"HBM SS3: Channel0",                     XE_SOC_HW_ERR_HBM3_CHNL0_FATAL},
>>> +    [10]        = {"HBM SS3: Channel1",                     XE_SOC_HW_ERR_HBM3_CHNL1_FATAL},
>>> +    [11]        = {"HBM SS3: Channel2",                     XE_SOC_HW_ERR_HBM3_CHNL2_FATAL},
>>> +    [12]        = {"HBM SS3: Channel3",                     XE_SOC_HW_ERR_HBM3_CHNL3_FATAL},
>>> +    [13]        = {"HBM SS3: Channel4",                     XE_SOC_HW_ERR_HBM3_CHNL4_FATAL},
>>> +    [14]        = {"HBM SS3: Channel5",                     XE_SOC_HW_ERR_HBM3_CHNL5_FATAL},
>>> +    [15]        = {"HBM SS3: Channel6",                     XE_SOC_HW_ERR_HBM3_CHNL6_FATAL},
>>> +    [16]        = {"HBM SS3: Channel7",                     XE_SOC_HW_ERR_HBM3_CHNL7_FATAL},
>>> +    [18]        = {"ANR MDFI",                XE_SOC_HW_ERR_ANR_MDFI_FATAL},
>>> +    [17]        = {"Undefined",                             XE_SOC_HW_ERR_UNKNOWN_FATAL},
>>> +    [19 ... 31] = {"Undefined",                XE_SOC_HW_ERR_UNKNOWN_FATAL},
>>> +};
>>> +
>>> +static const struct err_msg_cntr_pair soc_slave_lcl_err_reg_fatal[] = {
>>> +    [0]         = {"Local IEH Internal: Malformed PCIe AER",     XE_SOC_HW_ERR_PCIE_AER_FATAL},
>>> +    [1]         = {"Local IEH Internal: Malformed PCIe ERR",     XE_SOC_HW_ERR_PCIE_ERR_FATAL},
>>> +    [2]         = {"Local IEH Internal: UR CONDITIONS IN IEH",   XE_SOC_HW_ERR_UR_COND_FATAL},
>>> +    [3]         = {"Local IEH Internal: FROM SERR SOURCES",      XE_SOC_HW_ERR_SERR_SRCS_FATAL},
>>> +    [4 ... 31]  = {"Undefined",                     XE_SOC_HW_ERR_UNKNOWN_FATAL},
>>> +};
>>> +
>>> +static const struct err_msg_cntr_pair soc_mstr_lcl_err_reg_fatal[] = {
>>> +    [0 ... 3]   = {"Undefined",                XE_SOC_HW_ERR_UNKNOWN_FATAL},
>>> +    [4]         = {"Base Die MDFI T2T",            XE_SOC_HW_ERR_MDFI_T2T_FATAL},
>>> +    [5]         = {"Undefined",                XE_SOC_HW_ERR_UNKNOWN_FATAL},
>>> +    [6]         = {"Base Die MDFI T2C",            XE_SOC_HW_ERR_MDFI_T2C_FATAL},
>>> +    [7]         = {"Undefined",                XE_SOC_HW_ERR_UNKNOWN_FATAL},
>>> +    [8]         = {"Invalid CSC PSF Command Parity",    XE_SOC_HW_ERR_CSC_PSF_CMD_FATAL},
>>> +    [9]         = {"Invalid CSC PSF Unexpected Completion",    XE_SOC_HW_ERR_CSC_PSF_CMP_FATAL},
>>> +    [10]        = {"Invalid CSC PSF Unsupported Request",    XE_SOC_HW_ERR_CSC_PSF_REQ_FATAL},
>>> +    [11]        = {"Invalid PCIe PSF Command Parity",    XE_SOC_HW_ERR_PCIE_PSF_CMD_FATAL},
>>> +    [12]        = {"PCIe PSF Unexpected Completion",    XE_SOC_HW_ERR_PCIE_PSF_CMP_FATAL},
>>> +    [13]        = {"PCIe PSF Unsupported Request",        XE_SOC_HW_ERR_PCIE_PSF_REQ_FATAL},
>>> +    [14 ... 31] = {"Undefined",                XE_SOC_HW_ERR_UNKNOWN_FATAL},
>>> +};
>>> +
>> we shall think of future extensibility, like we do in xe_assign_hw_err_regs depending on platform for
>> other registers.
>
> Yes that is in my mind. I was planing to move this struct under xe_assign_hw_err_regs once new platform support is added for SOC error handling.
>
> But to make things aligned can be taken care rightnow as well. Will address in next patch.
>
>>>   static void xe_assign_hw_err_regs(struct xe_device *xe)
>>>   {
>>>       const struct err_msg_cntr_pair **dev_err_stat = xe->hw_err_regs.dev_err_stat;
>>> @@ -451,6 +520,104 @@ xe_gsc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
>>>       xe_mmio_write32(mmio, GSC_HEC_ERR_STAT_REG(base, hw_err), errsrc);
>>>   }
>>>   +static void
>>> +xe_soc_log_err_update_cntr(struct xe_tile *tile,
>>> +               u32 errbit, const struct err_msg_cntr_pair *reg_info)
>>> +{
>>> +    const char *errmsg;
>>> +    u32 indx;
>>> +
>>> +    errmsg = reg_info[errbit].errmsg;
>>> +    indx = reg_info[errbit].cntr_indx;
>>> +
>>> +    drm_err_ratelimited(&tile_to_xe(tile)->drm, HW_ERR
>>> +                "Tile%d %s SOC FATAL error, bit[%d] is set\n",
>>> +                tile->id, errmsg, errbit);
>>> +    tile->errors.count[indx]++;
>>> +}
>>> +
>>> +static void
>>> +xe_soc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
>>> +{
>>> +    unsigned long mst_glb_errstat, slv_glb_errstat, lcl_errstat;
>>> +    u32 errbit, base, slave_base;
>>> +    int i;
>>> +    struct xe_gt *gt = tile->primary_gt;
>>> +
>>> +    lockdep_assert_held(&tile_to_xe(tile)->irq.lock);
>>> +
>>> +    if ((tile_to_xe(tile)->info.platform != XE_PVC) && hw_err != HARDWARE_ERROR_FATAL)
>>> +        return;
>>> +
>>> +    base = SOC_PVC_BASE;
>>> +    slave_base = SOC_PVC_SLAVE_BASE;
>>> +
>>> +    /*
>>> +     * Mask error type in GSYSEVTCTL so that no new errors of the type
>>> +     * will be reported. Read the master global IEH error register if
>>> +     * BIT 1 is set then process the slave IEH first. If BIT 0 in
>>> +     * global error register is set then process the corresponding
>>> +     * Local error registers
>>> +     */
>>> +    for (i = 0; i < PVC_NUM_IEH; i++)
>>> +        xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base, i), ~REG_BIT(hw_err));
>>> +
>>> +    mst_glb_errstat = xe_mmio_read32(gt, SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err));
>>> +    drm_info(&tile_to_xe(tile)->drm, HW_ERR
>>> +         "Tile%d SOC_GLOBAL_ERR_STAT_MASTER_REG_FATAL:0x%08lx\n",
>>> +         tile->id, mst_glb_errstat);
>>> +
>>> +    if (mst_glb_errstat & REG_BIT(SOC_SLAVE_IEH)) {
>>> +        slv_glb_errstat = xe_mmio_read32(gt,
>>> +                         SOC_GLOBAL_ERR_STAT_SLAVE_REG(slave_base, hw_err));
>>> +         drm_info(&tile_to_xe(tile)->drm, HW_ERR
>>> +              "Tile%d SOC_GLOBAL_ERR_STAT_SLAVE_REG_FATAL:0x%08lx\n",
>>> +              tile->id, slv_glb_errstat);
>>> +
>>> +        if (slv_glb_errstat & REG_BIT(SOC_IEH1_LOCAL_ERR_STATUS)) {
>>> +            lcl_errstat = xe_mmio_read32(gt, SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base,
>>> +                                              hw_err));
>>> +             drm_info(&tile_to_xe(tile)->drm, HW_ERR
>>> +                  "Tile%d SOC_LOCAL_ERR_STAT_SLAVE_REG_FATAL:0x%08lx\n",
>>> +                  tile->id, lcl_errstat);
>>> +
>>> +            for_each_set_bit(errbit, &lcl_errstat, 32)
>>> +                xe_soc_log_err_update_cntr(tile, errbit,
>>> +                               soc_slave_lcl_err_reg_fatal);
>>> +
>>> +            xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
>>> +                    lcl_errstat);
>>> +        }
>>> +
>>> +        for_each_set_bit(errbit, &slv_glb_errstat, 32)
>>> +            xe_soc_log_err_update_cntr(tile, errbit, soc_slave_glbl_err_reg_fatal);
>>> +
>>> +        xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
>>> +                slv_glb_errstat);
>>> +    }
>>> +
>>> +    if (mst_glb_errstat & REG_BIT(SOC_IEH0_LOCAL_ERR_STATUS)) {
>>> +        lcl_errstat = xe_mmio_read32(gt, SOC_LOCAL_ERR_STAT_MASTER_REG(base, hw_err));
>>> +        drm_info(&tile_to_xe(tile)->drm, HW_ERR "SOC_LOCAL_ERR_STAT_MASTER_REG_FATAL:0x%08lx\n",
>>> +             lcl_errstat);
>>> +
>>> +        for_each_set_bit(errbit, &lcl_errstat, 32)
>>> +            xe_soc_log_err_update_cntr(tile, errbit, soc_mstr_lcl_err_reg_fatal);
>>> +
>>> +        xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_MASTER_REG(base, hw_err), lcl_errstat);
>>> +    }
>>> +
>>> +    for_each_set_bit(errbit, &mst_glb_errstat, 32)
>>> +        xe_soc_log_err_update_cntr(tile, errbit, soc_mstr_glbl_err_reg_fatal);
>>> +
>>> +    xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err),
>>> +            mst_glb_errstat);
>>> +
>>> +    for (i = 0; i < PVC_NUM_IEH; i++)
>>> +        xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base, i),
>>> +                (HARDWARE_ERROR_MAX << 1) + 1);
>>> +}
>>> +
>>>   static void
>>>   xe_hw_error_source_handler(struct xe_tile *tile, const enum hardware_error hw_err)
>>>   {
>>> @@ -498,6 +665,9 @@ xe_hw_error_source_handler(struct xe_tile *tile, const enum hardware_error hw_er
>>>             if (errbit == 8)
>>>               xe_gsc_hw_error_handler(tile, hw_err);
>>> +
>>> +        if (errbit == 16)
>>> +            xe_soc_hw_error_handler(tile, hw_err);
>>>       }
>>>         xe_mmio_write32(mmio, DEV_ERR_STAT_REG(hw_err), errsrc);
>>> diff --git a/drivers/gpu/drm/xe/xe_hw_error.h b/drivers/gpu/drm/xe/xe_hw_error.h
>>> index ee7705b3343b..05838e082abd 100644
>>> --- a/drivers/gpu/drm/xe/xe_hw_error.h
>>> +++ b/drivers/gpu/drm/xe/xe_hw_error.h
>>> @@ -65,6 +65,56 @@ enum xe_tile_hw_errors {
>>>       XE_GSC_HW_ERR_SELF_MBIST_UNCOR,
>>>       XE_GSC_HW_ERR_AON_RF_PARITY_UNCOR,
>>>       XE_GSC_HW_ERR_UNKNOWN_UNCOR,
>>> +    XE_SOC_HW_ERR_MSTR_LCL_FATAL,
>>> +    XE_SOC_HW_ERR_SLAVE_GLBL_FATAL,
>>> +    XE_SOC_HW_ERR_HBM0_CHNL0_FATAL,
>>> +    XE_SOC_HW_ERR_HBM0_CHNL1_FATAL,
>>> +    XE_SOC_HW_ERR_HBM0_CHNL2_FATAL,
>>> +    XE_SOC_HW_ERR_HBM0_CHNL3_FATAL,
>>> +    XE_SOC_HW_ERR_HBM0_CHNL4_FATAL,
>>> +    XE_SOC_HW_ERR_HBM0_CHNL5_FATAL,
>>> +    XE_SOC_HW_ERR_HBM0_CHNL6_FATAL,
>>> +    XE_SOC_HW_ERR_HBM0_CHNL7_FATAL,
>>> +    XE_SOC_HW_ERR_HBM1_CHNL0_FATAL,
>>> +    XE_SOC_HW_ERR_HBM1_CHNL1_FATAL,
>>> +    XE_SOC_HW_ERR_HBM1_CHNL2_FATAL,
>>> +    XE_SOC_HW_ERR_HBM1_CHNL3_FATAL,
>>> +    XE_SOC_HW_ERR_HBM1_CHNL4_FATAL,
>>> +    XE_SOC_HW_ERR_HBM1_CHNL5_FATAL,
>>> +    XE_SOC_HW_ERR_HBM1_CHNL6_FATAL,
>>> +    XE_SOC_HW_ERR_HBM1_CHNL7_FATAL,
>>> +    XE_SOC_HW_ERR_PUNIT_FATAL,
>>> +    XE_SOC_HW_ERR_UNKNOWN_FATAL,
>>> +    XE_SOC_HW_ERR_SLAVE_LCL_FATAL,
>>> +    XE_SOC_HW_ERR_HBM2_CHNL0_FATAL,
>>> +    XE_SOC_HW_ERR_HBM2_CHNL1_FATAL,
>>> +    XE_SOC_HW_ERR_HBM2_CHNL2_FATAL,
>>> +    XE_SOC_HW_ERR_HBM2_CHNL3_FATAL,
>>> +    XE_SOC_HW_ERR_HBM2_CHNL4_FATAL,
>>> +    XE_SOC_HW_ERR_HBM2_CHNL5_FATAL,
>>> +    XE_SOC_HW_ERR_HBM2_CHNL6_FATAL,
>>> +    XE_SOC_HW_ERR_HBM2_CHNL7_FATAL,
>>> +    XE_SOC_HW_ERR_HBM3_CHNL0_FATAL,
>>> +    XE_SOC_HW_ERR_HBM3_CHNL1_FATAL,
>>> +    XE_SOC_HW_ERR_HBM3_CHNL2_FATAL,
>>> +    XE_SOC_HW_ERR_HBM3_CHNL3_FATAL,
>>> +    XE_SOC_HW_ERR_HBM3_CHNL4_FATAL,
>>> +    XE_SOC_HW_ERR_HBM3_CHNL5_FATAL,
>>> +    XE_SOC_HW_ERR_HBM3_CHNL6_FATAL,
>>> +    XE_SOC_HW_ERR_HBM3_CHNL7_FATAL,
>>> +    XE_SOC_HW_ERR_ANR_MDFI_FATAL,
>>> +    XE_SOC_HW_ERR_PCIE_AER_FATAL,
>>> +    XE_SOC_HW_ERR_PCIE_ERR_FATAL,
>>> +    XE_SOC_HW_ERR_UR_COND_FATAL,
>>> +    XE_SOC_HW_ERR_SERR_SRCS_FATAL,
>>> +    XE_SOC_HW_ERR_MDFI_T2T_FATAL,
>>> +    XE_SOC_HW_ERR_MDFI_T2C_FATAL,
>>> +    XE_SOC_HW_ERR_CSC_PSF_CMD_FATAL,
>>> +    XE_SOC_HW_ERR_CSC_PSF_CMP_FATAL,
>>> +    XE_SOC_HW_ERR_CSC_PSF_REQ_FATAL,
>>> +    XE_SOC_HW_ERR_PCIE_PSF_CMD_FATAL,
>>> +    XE_SOC_HW_ERR_PCIE_PSF_CMP_FATAL,
>>> +    XE_SOC_HW_ERR_PCIE_PSF_REQ_FATAL,
>> even though soc errors fall under a tile it is better if we shall have a
>> separate enum for soc errors for 2 reasons, the other errors in
>> xe_tile_hw_errors are from top level registers while SOC are from second level
>> and also because these errors are most likely different on different platforms.
>> so, we shall extend struct tile_hw_errors to have separate entry for soc.
> Makes sense. WIll address in next patch.
>>
>>
>> Also, I'm thinking if we shall use xarray types for all members in error counters under tile and gt
>> with the enum list being big and which will increase with each new platform.
>
> My initial thought was also to use xarray for soc error counters. But even if we use xarray we need to have separate identifiers to identify which indexes in xarray are actually valid hardware error and which are spurious interrupt. Hence found no use of using xarray, if we still need to maintain all valid indexes.

xarray is supposedly be more memory efficient with large arrays, IIUC the allocation for an index position will only be done when the index is used for the first time.

Thanks,
Aravind.
>
> BR
>
> Himal Ghimiray
>
>>
>> Thanks,
>> Aravind.
>>
>>>       XE_TILE_HW_ERROR_MAX,
>>>   };
>>>   @@ -109,8 +159,12 @@ enum xe_gt_hw_errors {
>>>       XE_GT_HW_ERROR_MAX,
>>>   };
>>>   -#define ERR_STAT_GT_COR_VCTR_LEN (4)
>>> -#define ERR_STAT_GT_FATAL_VCTR_LEN (8)
>>> +#define ERR_STAT_GT_COR_VCTR_LEN    (4)
>>> +#define ERR_STAT_GT_FATAL_VCTR_LEN    (8)
>>> +#define PVC_NUM_IEH            (1)
>>> +#define SOC_SLAVE_IEH                   (1)
>>> +#define SOC_IEH0_LOCAL_ERR_STATUS       (0)
>>> +#define SOC_IEH1_LOCAL_ERR_STATUS       (0)
>>>     struct err_msg_cntr_pair {
>>>       const char *errmsg;

Re: [Intel-xe] [PATCH 07/11] drm/xe: Support SOC FATAL error handling for PVC.

[Ghimiray, Himal Prasad]

> -----Original Message-----
> From: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
> Sent: 08 October 2023 15:03
> To: Ghimiray, Himal Prasad <himal.prasad.ghimiray@intel.com>; intel-
> xe@lists.freedesktop.org
> Subject: Re: [Intel-xe] [PATCH 07/11] drm/xe: Support SOC FATAL error
> handling for PVC.
> 
> 
> On 04/10/23 12:20, Ghimiray, Himal Prasad wrote:
> >
> > On 04-10-2023 12:08, Aravind Iddamsetty wrote:
> >> On 27/09/23 17:16, Himal Prasad Ghimiray wrote:
> >> Hi Himal,
> >>
> >> I'm yet to review the full patch but sharing a few initial comments.
> >
> > Hi Aravind,
> >
> > Thanks for the review comments.
> >
> >>
> >>> Report the SOC fatal hardware error and update the counters which
> >>> will increment incase of error.
> >>>
> >>> Signed-off-by: Himal Prasad
> >>> Ghimiray<himal.prasad.ghimiray@intel.com>
> >>> ---
> >>>   drivers/gpu/drm/xe/regs/xe_tile_error_regs.h |  28 +++
> >>>   drivers/gpu/drm/xe/xe_hw_error.c             | 170
> >>> +++++++++++++++++++
> >>>   drivers/gpu/drm/xe/xe_hw_error.h             |  58 ++++++-
> >>>   3 files changed, 254 insertions(+), 2 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
> >>> b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
> >>> index fa16eaf9436b..04701c62f0d9 100644
> >>> --- a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
> >>> +++ b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
> >>> @@ -20,4 +20,32 @@
> >>>   #define GSC_HEC_ERR_STAT_REG(base, x)
> >>> XE_REG(_PICK_EVEN((x), \
> >>>                                   (base) + _GSC_HEC_CORR_ERR_STATUS,
> >>> \
> >>>                                   (base) +
> >>> _GSC_HEC_UNCOR_ERR_STATUS))
> >>> +#define SOC_PVC_BASE                   0x00282000 #define
> >>> +SOC_PVC_SLAVE_BASE             0x00283000
> >>> +
> >>> +#define _SOC_LERRCORSTS               0x000294 #define
> >>> +_SOC_LERRUNCSTS               0x000280 #define
> >>> +SOC_LOCAL_ERR_STAT_SLAVE_REG(base, x)        XE_REG((x) >
> >>> +HARDWARE_ERROR_CORRECTABLE ? \
> >>> +                                (base) + _SOC_LERRUNCSTS : \
> >>> +                                (base) + _SOC_LERRCORSTS)
> >>> +
> >>> +#define SOC_LOCAL_ERR_STAT_MASTER_REG(base, x)        XE_REG((x)
> >
> >>> +HARDWARE_ERROR_CORRECTABLE ? \
> >>> +                                (base) + _SOC_LERRUNCSTS : \
> >>> +                                (base) + _SOC_LERRCORSTS) #define
> >>> +_SOC_GSYSEVTCTL                0x000264
> >>> +
> >>> +#define SOC_GSYSEVTCTL_REG(base, slave_base, x)
> >>> +XE_REG(_PICK_EVEN((x), \
> >>> +                                (base) + _SOC_GSYSEVTCTL, \
> >>> +                                slave_base + _SOC_GSYSEVTCTL))
> >>> +#define _SOC_GCOERRSTS                0x000200 #define
> >>> +_SOC_GNFERRSTS                0x000210 #define _SOC_GFAERRSTS
> >>> +0x000220 #define SOC_GLOBAL_ERR_STAT_SLAVE_REG(base, x)
> >>> +XE_REG(_PICK_EVEN((x), \
> >>> +                                (base) + _SOC_GCOERRSTS, \
> >>> +                                (base) + _SOC_GNFERRSTS))
> >>> +
> >>> +#define SOC_GLOBAL_ERR_STAT_MASTER_REG(base, x)
> >>> +XE_REG(_PICK_EVEN((x), \
> >>> +                                (base) + _SOC_GCOERRSTS, \
> >>> +                                (base) + _SOC_GNFERRSTS))
> >>> +
> >>>   #endif
> >>> diff --git a/drivers/gpu/drm/xe/xe_hw_error.c
> >>> b/drivers/gpu/drm/xe/xe_hw_error.c
> >>> index 76ae12df013c..fa05bad5e684 100644
> >>> --- a/drivers/gpu/drm/xe/xe_hw_error.c
> >>> +++ b/drivers/gpu/drm/xe/xe_hw_error.c
> >>> @@ -207,6 +207,75 @@ static const struct err_msg_cntr_pair
> >>> gsc_correctable_err_reg[] = {
> >>>       [2 ... 31] = {"Undefined",
> >>> XE_GSC_HW_ERR_UNKNOWN_CORR},
> >>>   };
> >>>   +static const struct err_msg_cntr_pair
> >>> soc_mstr_glbl_err_reg_fatal[] = {
> >>> +    [0]         = {"MASTER LOCAL Reported",
> >>> +XE_SOC_HW_ERR_MSTR_LCL_FATAL},
> >>> +    [1]         = {"SLAVE GLOBAL Reported",
> >>> +XE_SOC_HW_ERR_SLAVE_GLBL_FATAL},
> >>> +    [2]         = {"HBM SS0: Channel0",
> >>> +XE_SOC_HW_ERR_HBM0_CHNL0_FATAL},
> >>> +    [3]         = {"HBM SS0: Channel1",
> >>> +XE_SOC_HW_ERR_HBM0_CHNL1_FATAL},
> >>> +    [4]         = {"HBM SS0: Channel2",
> >>> +XE_SOC_HW_ERR_HBM0_CHNL2_FATAL},
> >>> +    [5]         = {"HBM SS0: Channel3",
> >>> +XE_SOC_HW_ERR_HBM0_CHNL3_FATAL},
> >>> +    [6]         = {"HBM SS0: Channel4",
> >>> +XE_SOC_HW_ERR_HBM0_CHNL4_FATAL},
> >>> +    [7]         = {"HBM SS0: Channel5",
> >>> +XE_SOC_HW_ERR_HBM0_CHNL5_FATAL},
> >>> +    [8]         = {"HBM SS0: Channel6",
> >>> +XE_SOC_HW_ERR_HBM0_CHNL6_FATAL},
> >>> +    [9]         = {"HBM SS0: Channel7",
> >>> +XE_SOC_HW_ERR_HBM0_CHNL7_FATAL},
> >>> +    [10]        = {"HBM SS1: Channel0",
> >>> +XE_SOC_HW_ERR_HBM1_CHNL0_FATAL},
> >>> +    [11]        = {"HBM SS1: Channel1",
> >>> +XE_SOC_HW_ERR_HBM1_CHNL1_FATAL},
> >>> +    [12]        = {"HBM SS1: Channel2",
> >>> +XE_SOC_HW_ERR_HBM1_CHNL2_FATAL},
> >>> +    [13]        = {"HBM SS1: Channel3",
> >>> +XE_SOC_HW_ERR_HBM1_CHNL3_FATAL},
> >>> +    [14]        = {"HBM SS1: Channel4",
> >>> +XE_SOC_HW_ERR_HBM1_CHNL4_FATAL},
> >>> +    [15]        = {"HBM SS1: Channel5",
> >>> +XE_SOC_HW_ERR_HBM1_CHNL5_FATAL},
> >>> +    [16]        = {"HBM SS1: Channel6",
> >>> +XE_SOC_HW_ERR_HBM1_CHNL6_FATAL},
> >>> +    [17]        = {"HBM SS1: Channel7",
> >>> +XE_SOC_HW_ERR_HBM1_CHNL7_FATAL},
> >>> +    [18]        = {"PUNIT",
> >>> +XE_SOC_HW_ERR_PUNIT_FATAL},
> >>> +    [19 ... 31] = {"Undefined",
> >>> +XE_SOC_HW_ERR_UNKNOWN_FATAL}, };
> >>> +
> >>> +static const struct err_msg_cntr_pair
> >>> +soc_slave_glbl_err_reg_fatal[] = {
> >>> +    [0]         = {"SLAVE LOCAL Reported",
> >>> +XE_SOC_HW_ERR_SLAVE_LCL_FATAL},
> >>> +    [1]         = {"HBM SS2: Channel0",
> >>> +XE_SOC_HW_ERR_HBM2_CHNL0_FATAL},
> >>> +    [2]         = {"HBM SS2: Channel1",
> >>> +XE_SOC_HW_ERR_HBM2_CHNL1_FATAL},
> >>> +    [3]         = {"HBM SS2: Channel2",
> >>> +XE_SOC_HW_ERR_HBM2_CHNL2_FATAL},
> >>> +    [4]         = {"HBM SS2: Channel3",
> >>> +XE_SOC_HW_ERR_HBM2_CHNL3_FATAL},
> >>> +    [5]         = {"HBM SS2: Channel4",
> >>> +XE_SOC_HW_ERR_HBM2_CHNL4_FATAL},
> >>> +    [6]         = {"HBM SS2: Channel5",
> >>> +XE_SOC_HW_ERR_HBM2_CHNL5_FATAL},
> >>> +    [7]         = {"HBM SS2: Channel6",
> >>> +XE_SOC_HW_ERR_HBM2_CHNL6_FATAL},
> >>> +    [8]         = {"HBM SS2: Channel7",
> >>> +XE_SOC_HW_ERR_HBM2_CHNL7_FATAL},
> >>> +    [9]         = {"HBM SS3: Channel0",
> >>> +XE_SOC_HW_ERR_HBM3_CHNL0_FATAL},
> >>> +    [10]        = {"HBM SS3: Channel1",
> >>> +XE_SOC_HW_ERR_HBM3_CHNL1_FATAL},
> >>> +    [11]        = {"HBM SS3: Channel2",
> >>> +XE_SOC_HW_ERR_HBM3_CHNL2_FATAL},
> >>> +    [12]        = {"HBM SS3: Channel3",
> >>> +XE_SOC_HW_ERR_HBM3_CHNL3_FATAL},
> >>> +    [13]        = {"HBM SS3: Channel4",
> >>> +XE_SOC_HW_ERR_HBM3_CHNL4_FATAL},
> >>> +    [14]        = {"HBM SS3: Channel5",
> >>> +XE_SOC_HW_ERR_HBM3_CHNL5_FATAL},
> >>> +    [15]        = {"HBM SS3: Channel6",
> >>> +XE_SOC_HW_ERR_HBM3_CHNL6_FATAL},
> >>> +    [16]        = {"HBM SS3: Channel7",
> >>> +XE_SOC_HW_ERR_HBM3_CHNL7_FATAL},
> >>> +    [18]        = {"ANR MDFI",
> >>> +XE_SOC_HW_ERR_ANR_MDFI_FATAL},
> >>> +    [17]        = {"Undefined",
> >>> +XE_SOC_HW_ERR_UNKNOWN_FATAL},
> >>> +    [19 ... 31] = {"Undefined",
> >>> +XE_SOC_HW_ERR_UNKNOWN_FATAL}, };
> >>> +
> >>> +static const struct err_msg_cntr_pair soc_slave_lcl_err_reg_fatal[]
> >>> += {
> >>> +    [0]         = {"Local IEH Internal: Malformed PCIe AER",
> >>> +XE_SOC_HW_ERR_PCIE_AER_FATAL},
> >>> +    [1]         = {"Local IEH Internal: Malformed PCIe ERR",
> >>> +XE_SOC_HW_ERR_PCIE_ERR_FATAL},
> >>> +    [2]         = {"Local IEH Internal: UR CONDITIONS IN IEH",
> >>> +XE_SOC_HW_ERR_UR_COND_FATAL},
> >>> +    [3]         = {"Local IEH Internal: FROM SERR SOURCES",
> >>> +XE_SOC_HW_ERR_SERR_SRCS_FATAL},
> >>> +    [4 ... 31]  = {"Undefined",
> >>> +XE_SOC_HW_ERR_UNKNOWN_FATAL}, };
> >>> +
> >>> +static const struct err_msg_cntr_pair soc_mstr_lcl_err_reg_fatal[]
> >>> += {
> >>> +    [0 ... 3]   = {"Undefined",
> >>> +XE_SOC_HW_ERR_UNKNOWN_FATAL},
> >>> +    [4]         = {"Base Die MDFI T2T",
> >>> +XE_SOC_HW_ERR_MDFI_T2T_FATAL},
> >>> +    [5]         = {"Undefined",
> >>> +XE_SOC_HW_ERR_UNKNOWN_FATAL},
> >>> +    [6]         = {"Base Die MDFI T2C",
> >>> +XE_SOC_HW_ERR_MDFI_T2C_FATAL},
> >>> +    [7]         = {"Undefined",
> >>> +XE_SOC_HW_ERR_UNKNOWN_FATAL},
> >>> +    [8]         = {"Invalid CSC PSF Command Parity",
> >>> +XE_SOC_HW_ERR_CSC_PSF_CMD_FATAL},
> >>> +    [9]         = {"Invalid CSC PSF Unexpected Completion",
> >>> +XE_SOC_HW_ERR_CSC_PSF_CMP_FATAL},
> >>> +    [10]        = {"Invalid CSC PSF Unsupported Request",
> >>> +XE_SOC_HW_ERR_CSC_PSF_REQ_FATAL},
> >>> +    [11]        = {"Invalid PCIe PSF Command Parity",
> >>> +XE_SOC_HW_ERR_PCIE_PSF_CMD_FATAL},
> >>> +    [12]        = {"PCIe PSF Unexpected Completion",
> >>> +XE_SOC_HW_ERR_PCIE_PSF_CMP_FATAL},
> >>> +    [13]        = {"PCIe PSF Unsupported Request",
> >>> +XE_SOC_HW_ERR_PCIE_PSF_REQ_FATAL},
> >>> +    [14 ... 31] = {"Undefined",
> >>> +XE_SOC_HW_ERR_UNKNOWN_FATAL}, };
> >>> +
> >> we shall think of future extensibility, like we do in
> >> xe_assign_hw_err_regs depending on platform for other registers.
> >
> > Yes that is in my mind. I was planing to move this struct under
> xe_assign_hw_err_regs once new platform support is added for SOC error
> handling.
> >
> > But to make things aligned can be taken care rightnow as well. Will address
> in next patch.
> >
> >>>   static void xe_assign_hw_err_regs(struct xe_device *xe)
> >>>   {
> >>>       const struct err_msg_cntr_pair **dev_err_stat =
> >>> xe->hw_err_regs.dev_err_stat; @@ -451,6 +520,104 @@
> >>> xe_gsc_hw_error_handler(struct xe_tile *tile, const enum
> >>> hardware_error hw_err)
> >>>       xe_mmio_write32(mmio, GSC_HEC_ERR_STAT_REG(base, hw_err),
> >>> errsrc);
> >>>   }
> >>>   +static void
> >>> +xe_soc_log_err_update_cntr(struct xe_tile *tile,
> >>> +               u32 errbit, const struct err_msg_cntr_pair
> >>> +*reg_info) {
> >>> +    const char *errmsg;
> >>> +    u32 indx;
> >>> +
> >>> +    errmsg = reg_info[errbit].errmsg;
> >>> +    indx = reg_info[errbit].cntr_indx;
> >>> +
> >>> +    drm_err_ratelimited(&tile_to_xe(tile)->drm, HW_ERR
> >>> +                "Tile%d %s SOC FATAL error, bit[%d] is set\n",
> >>> +                tile->id, errmsg, errbit);
> >>> +    tile->errors.count[indx]++;
> >>> +}
> >>> +
> >>> +static void
> >>> +xe_soc_hw_error_handler(struct xe_tile *tile, const enum
> >>> +hardware_error hw_err) {
> >>> +    unsigned long mst_glb_errstat, slv_glb_errstat, lcl_errstat;
> >>> +    u32 errbit, base, slave_base;
> >>> +    int i;
> >>> +    struct xe_gt *gt = tile->primary_gt;
> >>> +
> >>> +    lockdep_assert_held(&tile_to_xe(tile)->irq.lock);
> >>> +
> >>> +    if ((tile_to_xe(tile)->info.platform != XE_PVC) && hw_err !=
> >>> +HARDWARE_ERROR_FATAL)
> >>> +        return;
> >>> +
> >>> +    base = SOC_PVC_BASE;
> >>> +    slave_base = SOC_PVC_SLAVE_BASE;
> >>> +
> >>> +    /*
> >>> +     * Mask error type in GSYSEVTCTL so that no new errors of the
> >>> +type
> >>> +     * will be reported. Read the master global IEH error register
> >>> +if
> >>> +     * BIT 1 is set then process the slave IEH first. If BIT 0 in
> >>> +     * global error register is set then process the corresponding
> >>> +     * Local error registers
> >>> +     */
> >>> +    for (i = 0; i < PVC_NUM_IEH; i++)
> >>> +        xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base,
> >>> +i), ~REG_BIT(hw_err));
> >>> +
> >>> +    mst_glb_errstat = xe_mmio_read32(gt,
> >>> +SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err));
> >>> +    drm_info(&tile_to_xe(tile)->drm, HW_ERR
> >>> +         "Tile%d
> SOC_GLOBAL_ERR_STAT_MASTER_REG_FATAL:0x%08lx\n",
> >>> +         tile->id, mst_glb_errstat);
> >>> +
> >>> +    if (mst_glb_errstat & REG_BIT(SOC_SLAVE_IEH)) {
> >>> +        slv_glb_errstat = xe_mmio_read32(gt,
> >>> +                         SOC_GLOBAL_ERR_STAT_SLAVE_REG(slave_base,
> >>> +hw_err));
> >>> +         drm_info(&tile_to_xe(tile)->drm, HW_ERR
> >>> +              "Tile%d
> >>> +SOC_GLOBAL_ERR_STAT_SLAVE_REG_FATAL:0x%08lx\n",
> >>> +              tile->id, slv_glb_errstat);
> >>> +
> >>> +        if (slv_glb_errstat & REG_BIT(SOC_IEH1_LOCAL_ERR_STATUS)) {
> >>> +            lcl_errstat = xe_mmio_read32(gt,
> >>> +SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base,
> >>> +                                              hw_err));
> >>> +             drm_info(&tile_to_xe(tile)->drm, HW_ERR
> >>> +                  "Tile%d
> >>> +SOC_LOCAL_ERR_STAT_SLAVE_REG_FATAL:0x%08lx\n",
> >>> +                  tile->id, lcl_errstat);
> >>> +
> >>> +            for_each_set_bit(errbit, &lcl_errstat, 32)
> >>> +                xe_soc_log_err_update_cntr(tile, errbit,
> >>> +                               soc_slave_lcl_err_reg_fatal);
> >>> +
> >>> +            xe_mmio_write32(gt,
> >>> +SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
> >>> +                    lcl_errstat);
> >>> +        }
> >>> +
> >>> +        for_each_set_bit(errbit, &slv_glb_errstat, 32)
> >>> +            xe_soc_log_err_update_cntr(tile, errbit,
> >>> +soc_slave_glbl_err_reg_fatal);
> >>> +
> >>> +        xe_mmio_write32(gt,
> >>> +SOC_GLOBAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
> >>> +                slv_glb_errstat);
> >>> +    }
> >>> +
> >>> +    if (mst_glb_errstat & REG_BIT(SOC_IEH0_LOCAL_ERR_STATUS)) {
> >>> +        lcl_errstat = xe_mmio_read32(gt,
> >>> +SOC_LOCAL_ERR_STAT_MASTER_REG(base, hw_err));
> >>> +        drm_info(&tile_to_xe(tile)->drm, HW_ERR
> >>> +"SOC_LOCAL_ERR_STAT_MASTER_REG_FATAL:0x%08lx\n",
> >>> +             lcl_errstat);
> >>> +
> >>> +        for_each_set_bit(errbit, &lcl_errstat, 32)
> >>> +            xe_soc_log_err_update_cntr(tile, errbit,
> >>> +soc_mstr_lcl_err_reg_fatal);
> >>> +
> >>> +        xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_MASTER_REG(base,
> >>> +hw_err), lcl_errstat);
> >>> +    }
> >>> +
> >>> +    for_each_set_bit(errbit, &mst_glb_errstat, 32)
> >>> +        xe_soc_log_err_update_cntr(tile, errbit,
> >>> +soc_mstr_glbl_err_reg_fatal);
> >>> +
> >>> +    xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_MASTER_REG(base,
> >>> +hw_err),
> >>> +            mst_glb_errstat);
> >>> +
> >>> +    for (i = 0; i < PVC_NUM_IEH; i++)
> >>> +        xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base,
> >>> +i),
> >>> +                (HARDWARE_ERROR_MAX << 1) + 1); }
> >>> +
> >>>   static void
> >>>   xe_hw_error_source_handler(struct xe_tile *tile, const enum
> >>> hardware_error hw_err)
> >>>   {
> >>> @@ -498,6 +665,9 @@ xe_hw_error_source_handler(struct xe_tile
> *tile,
> >>> const enum hardware_error hw_er
> >>>             if (errbit == 8)
> >>>               xe_gsc_hw_error_handler(tile, hw_err);
> >>> +
> >>> +        if (errbit == 16)
> >>> +            xe_soc_hw_error_handler(tile, hw_err);
> >>>       }
> >>>         xe_mmio_write32(mmio, DEV_ERR_STAT_REG(hw_err), errsrc);
> >>> diff --git a/drivers/gpu/drm/xe/xe_hw_error.h
> >>> b/drivers/gpu/drm/xe/xe_hw_error.h
> >>> index ee7705b3343b..05838e082abd 100644
> >>> --- a/drivers/gpu/drm/xe/xe_hw_error.h
> >>> +++ b/drivers/gpu/drm/xe/xe_hw_error.h
> >>> @@ -65,6 +65,56 @@ enum xe_tile_hw_errors {
> >>>       XE_GSC_HW_ERR_SELF_MBIST_UNCOR,
> >>>       XE_GSC_HW_ERR_AON_RF_PARITY_UNCOR,
> >>>       XE_GSC_HW_ERR_UNKNOWN_UNCOR,
> >>> +    XE_SOC_HW_ERR_MSTR_LCL_FATAL,
> >>> +    XE_SOC_HW_ERR_SLAVE_GLBL_FATAL,
> >>> +    XE_SOC_HW_ERR_HBM0_CHNL0_FATAL,
> >>> +    XE_SOC_HW_ERR_HBM0_CHNL1_FATAL,
> >>> +    XE_SOC_HW_ERR_HBM0_CHNL2_FATAL,
> >>> +    XE_SOC_HW_ERR_HBM0_CHNL3_FATAL,
> >>> +    XE_SOC_HW_ERR_HBM0_CHNL4_FATAL,
> >>> +    XE_SOC_HW_ERR_HBM0_CHNL5_FATAL,
> >>> +    XE_SOC_HW_ERR_HBM0_CHNL6_FATAL,
> >>> +    XE_SOC_HW_ERR_HBM0_CHNL7_FATAL,
> >>> +    XE_SOC_HW_ERR_HBM1_CHNL0_FATAL,
> >>> +    XE_SOC_HW_ERR_HBM1_CHNL1_FATAL,
> >>> +    XE_SOC_HW_ERR_HBM1_CHNL2_FATAL,
> >>> +    XE_SOC_HW_ERR_HBM1_CHNL3_FATAL,
> >>> +    XE_SOC_HW_ERR_HBM1_CHNL4_FATAL,
> >>> +    XE_SOC_HW_ERR_HBM1_CHNL5_FATAL,
> >>> +    XE_SOC_HW_ERR_HBM1_CHNL6_FATAL,
> >>> +    XE_SOC_HW_ERR_HBM1_CHNL7_FATAL,
> >>> +    XE_SOC_HW_ERR_PUNIT_FATAL,
> >>> +    XE_SOC_HW_ERR_UNKNOWN_FATAL,
> >>> +    XE_SOC_HW_ERR_SLAVE_LCL_FATAL,
> >>> +    XE_SOC_HW_ERR_HBM2_CHNL0_FATAL,
> >>> +    XE_SOC_HW_ERR_HBM2_CHNL1_FATAL,
> >>> +    XE_SOC_HW_ERR_HBM2_CHNL2_FATAL,
> >>> +    XE_SOC_HW_ERR_HBM2_CHNL3_FATAL,
> >>> +    XE_SOC_HW_ERR_HBM2_CHNL4_FATAL,
> >>> +    XE_SOC_HW_ERR_HBM2_CHNL5_FATAL,
> >>> +    XE_SOC_HW_ERR_HBM2_CHNL6_FATAL,
> >>> +    XE_SOC_HW_ERR_HBM2_CHNL7_FATAL,
> >>> +    XE_SOC_HW_ERR_HBM3_CHNL0_FATAL,
> >>> +    XE_SOC_HW_ERR_HBM3_CHNL1_FATAL,
> >>> +    XE_SOC_HW_ERR_HBM3_CHNL2_FATAL,
> >>> +    XE_SOC_HW_ERR_HBM3_CHNL3_FATAL,
> >>> +    XE_SOC_HW_ERR_HBM3_CHNL4_FATAL,
> >>> +    XE_SOC_HW_ERR_HBM3_CHNL5_FATAL,
> >>> +    XE_SOC_HW_ERR_HBM3_CHNL6_FATAL,
> >>> +    XE_SOC_HW_ERR_HBM3_CHNL7_FATAL,
> >>> +    XE_SOC_HW_ERR_ANR_MDFI_FATAL,
> >>> +    XE_SOC_HW_ERR_PCIE_AER_FATAL,
> >>> +    XE_SOC_HW_ERR_PCIE_ERR_FATAL,
> >>> +    XE_SOC_HW_ERR_UR_COND_FATAL,
> >>> +    XE_SOC_HW_ERR_SERR_SRCS_FATAL,
> >>> +    XE_SOC_HW_ERR_MDFI_T2T_FATAL,
> >>> +    XE_SOC_HW_ERR_MDFI_T2C_FATAL,
> >>> +    XE_SOC_HW_ERR_CSC_PSF_CMD_FATAL,
> >>> +    XE_SOC_HW_ERR_CSC_PSF_CMP_FATAL,
> >>> +    XE_SOC_HW_ERR_CSC_PSF_REQ_FATAL,
> >>> +    XE_SOC_HW_ERR_PCIE_PSF_CMD_FATAL,
> >>> +    XE_SOC_HW_ERR_PCIE_PSF_CMP_FATAL,
> >>> +    XE_SOC_HW_ERR_PCIE_PSF_REQ_FATAL,
> >> even though soc errors fall under a tile it is better if we shall
> >> have a separate enum for soc errors for 2 reasons, the other errors
> >> in xe_tile_hw_errors are from top level registers while SOC are from
> >> second level and also because these errors are most likely different on
> different platforms.
> >> so, we shall extend struct tile_hw_errors to have separate entry for soc.
> > Makes sense. WIll address in next patch.
> >>
> >>
> >> Also, I'm thinking if we shall use xarray types for all members in
> >> error counters under tile and gt with the enum list being big and which will
> increase with each new platform.
> >
> > My initial thought was also to use xarray for soc error counters. But even if
> we use xarray we need to have separate identifiers to identify which indexes
> in xarray are actually valid hardware error and which are spurious interrupt.
> Hence found no use of using xarray, if we still need to maintain all valid
> indexes.
> 
> xarray is supposedly be more memory efficient with large arrays, IIUC the
> allocation for an index position will only be done when the index is used for
> the first time.

Hmm. With current approach, for soc counters we might end up allocating int array of 
[32] [ 2] [3] [2] = 384 elements (considering we have only 1 slave ieh and all bits signify some error) and I am not sure whether 
On further platform we will have more slaves IEH or not.

With xarray the allocation will be dynamic and above array can be avoided. If recommendation is not to allocate this big arrays,  xarray will be better option.
If array size is of no concern, we can avoid overhead of xarray referencing and dereferencing while storing and reading the counter values from respective index.

BR
Himal 

> 
> Thanks,
> Aravind.
> >
> > BR
> >
> > Himal Ghimiray
> >
> >>
> >> Thanks,
> >> Aravind.
> >>
> >>>       XE_TILE_HW_ERROR_MAX,
> >>>   };
> >>>   @@ -109,8 +159,12 @@ enum xe_gt_hw_errors {
> >>>       XE_GT_HW_ERROR_MAX,
> >>>   };
> >>>   -#define ERR_STAT_GT_COR_VCTR_LEN (4) -#define
> >>> ERR_STAT_GT_FATAL_VCTR_LEN (8)
> >>> +#define ERR_STAT_GT_COR_VCTR_LEN    (4) #define
> >>> +ERR_STAT_GT_FATAL_VCTR_LEN    (8) #define PVC_NUM_IEH
> >>> +(1) #define SOC_SLAVE_IEH                   (1) #define
> >>> +SOC_IEH0_LOCAL_ERR_STATUS       (0) #define
> >>> +SOC_IEH1_LOCAL_ERR_STATUS       (0)
> >>>     struct err_msg_cntr_pair {
> >>>       const char *errmsg;

Re: [Intel-xe] [PATCH 07/11] drm/xe: Support SOC FATAL error handling for PVC.

[Aravind Iddamsetty]

On 09/10/23 09:41, Ghimiray, Himal Prasad wrote:
>
>> -----Original Message-----
>> From: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
>> Sent: 08 October 2023 15:03
>> To: Ghimiray, Himal Prasad <himal.prasad.ghimiray@intel.com>; intel-
>> xe@lists.freedesktop.org
>> Subject: Re: [Intel-xe] [PATCH 07/11] drm/xe: Support SOC FATAL error
>> handling for PVC.
>>
>>
>> On 04/10/23 12:20, Ghimiray, Himal Prasad wrote:
>>> On 04-10-2023 12:08, Aravind Iddamsetty wrote:
>>>> On 27/09/23 17:16, Himal Prasad Ghimiray wrote:
>>>> Hi Himal,
>>>>
>>>> I'm yet to review the full patch but sharing a few initial comments.
>>> Hi Aravind,
>>>
>>> Thanks for the review comments.
>>>
>>>>> Report the SOC fatal hardware error and update the counters which
>>>>> will increment incase of error.
>>>>>
>>>>> Signed-off-by: Himal Prasad
>>>>> Ghimiray<himal.prasad.ghimiray@intel.com>
>>>>> ---
>>>>>   drivers/gpu/drm/xe/regs/xe_tile_error_regs.h |  28 +++
>>>>>   drivers/gpu/drm/xe/xe_hw_error.c             | 170
>>>>> +++++++++++++++++++
>>>>>   drivers/gpu/drm/xe/xe_hw_error.h             |  58 ++++++-
>>>>>   3 files changed, 254 insertions(+), 2 deletions(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
>>>>> b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
>>>>> index fa16eaf9436b..04701c62f0d9 100644
>>>>> --- a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
>>>>> +++ b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
>>>>> @@ -20,4 +20,32 @@
>>>>>   #define GSC_HEC_ERR_STAT_REG(base, x)
>>>>> XE_REG(_PICK_EVEN((x), \
>>>>>                                   (base) + _GSC_HEC_CORR_ERR_STATUS,
>>>>> \
>>>>>                                   (base) +
>>>>> _GSC_HEC_UNCOR_ERR_STATUS))
>>>>> +#define SOC_PVC_BASE                   0x00282000 #define
>>>>> +SOC_PVC_SLAVE_BASE             0x00283000
>>>>> +
>>>>> +#define _SOC_LERRCORSTS               0x000294 #define
>>>>> +_SOC_LERRUNCSTS               0x000280 #define
>>>>> +SOC_LOCAL_ERR_STAT_SLAVE_REG(base, x)        XE_REG((x) >
>>>>> +HARDWARE_ERROR_CORRECTABLE ? \
>>>>> +                                (base) + _SOC_LERRUNCSTS : \
>>>>> +                                (base) + _SOC_LERRCORSTS)
>>>>> +
>>>>> +#define SOC_LOCAL_ERR_STAT_MASTER_REG(base, x)        XE_REG((x)
>>>>> +HARDWARE_ERROR_CORRECTABLE ? \
>>>>> +                                (base) + _SOC_LERRUNCSTS : \
>>>>> +                                (base) + _SOC_LERRCORSTS) #define
>>>>> +_SOC_GSYSEVTCTL                0x000264
>>>>> +
>>>>> +#define SOC_GSYSEVTCTL_REG(base, slave_base, x)
>>>>> +XE_REG(_PICK_EVEN((x), \
>>>>> +                                (base) + _SOC_GSYSEVTCTL, \
>>>>> +                                slave_base + _SOC_GSYSEVTCTL))
>>>>> +#define _SOC_GCOERRSTS                0x000200 #define
>>>>> +_SOC_GNFERRSTS                0x000210 #define _SOC_GFAERRSTS
>>>>> +0x000220 #define SOC_GLOBAL_ERR_STAT_SLAVE_REG(base, x)
>>>>> +XE_REG(_PICK_EVEN((x), \
>>>>> +                                (base) + _SOC_GCOERRSTS, \
>>>>> +                                (base) + _SOC_GNFERRSTS))
>>>>> +
>>>>> +#define SOC_GLOBAL_ERR_STAT_MASTER_REG(base, x)
>>>>> +XE_REG(_PICK_EVEN((x), \
>>>>> +                                (base) + _SOC_GCOERRSTS, \
>>>>> +                                (base) + _SOC_GNFERRSTS))
>>>>> +
>>>>>   #endif
>>>>> diff --git a/drivers/gpu/drm/xe/xe_hw_error.c
>>>>> b/drivers/gpu/drm/xe/xe_hw_error.c
>>>>> index 76ae12df013c..fa05bad5e684 100644
>>>>> --- a/drivers/gpu/drm/xe/xe_hw_error.c
>>>>> +++ b/drivers/gpu/drm/xe/xe_hw_error.c
>>>>> @@ -207,6 +207,75 @@ static const struct err_msg_cntr_pair
>>>>> gsc_correctable_err_reg[] = {
>>>>>       [2 ... 31] = {"Undefined",
>>>>> XE_GSC_HW_ERR_UNKNOWN_CORR},
>>>>>   };
>>>>>   +static const struct err_msg_cntr_pair
>>>>> soc_mstr_glbl_err_reg_fatal[] = {
>>>>> +    [0]         = {"MASTER LOCAL Reported",
>>>>> +XE_SOC_HW_ERR_MSTR_LCL_FATAL},
>>>>> +    [1]         = {"SLAVE GLOBAL Reported",
>>>>> +XE_SOC_HW_ERR_SLAVE_GLBL_FATAL},
>>>>> +    [2]         = {"HBM SS0: Channel0",
>>>>> +XE_SOC_HW_ERR_HBM0_CHNL0_FATAL},
>>>>> +    [3]         = {"HBM SS0: Channel1",
>>>>> +XE_SOC_HW_ERR_HBM0_CHNL1_FATAL},
>>>>> +    [4]         = {"HBM SS0: Channel2",
>>>>> +XE_SOC_HW_ERR_HBM0_CHNL2_FATAL},
>>>>> +    [5]         = {"HBM SS0: Channel3",
>>>>> +XE_SOC_HW_ERR_HBM0_CHNL3_FATAL},
>>>>> +    [6]         = {"HBM SS0: Channel4",
>>>>> +XE_SOC_HW_ERR_HBM0_CHNL4_FATAL},
>>>>> +    [7]         = {"HBM SS0: Channel5",
>>>>> +XE_SOC_HW_ERR_HBM0_CHNL5_FATAL},
>>>>> +    [8]         = {"HBM SS0: Channel6",
>>>>> +XE_SOC_HW_ERR_HBM0_CHNL6_FATAL},
>>>>> +    [9]         = {"HBM SS0: Channel7",
>>>>> +XE_SOC_HW_ERR_HBM0_CHNL7_FATAL},
>>>>> +    [10]        = {"HBM SS1: Channel0",
>>>>> +XE_SOC_HW_ERR_HBM1_CHNL0_FATAL},
>>>>> +    [11]        = {"HBM SS1: Channel1",
>>>>> +XE_SOC_HW_ERR_HBM1_CHNL1_FATAL},
>>>>> +    [12]        = {"HBM SS1: Channel2",
>>>>> +XE_SOC_HW_ERR_HBM1_CHNL2_FATAL},
>>>>> +    [13]        = {"HBM SS1: Channel3",
>>>>> +XE_SOC_HW_ERR_HBM1_CHNL3_FATAL},
>>>>> +    [14]        = {"HBM SS1: Channel4",
>>>>> +XE_SOC_HW_ERR_HBM1_CHNL4_FATAL},
>>>>> +    [15]        = {"HBM SS1: Channel5",
>>>>> +XE_SOC_HW_ERR_HBM1_CHNL5_FATAL},
>>>>> +    [16]        = {"HBM SS1: Channel6",
>>>>> +XE_SOC_HW_ERR_HBM1_CHNL6_FATAL},
>>>>> +    [17]        = {"HBM SS1: Channel7",
>>>>> +XE_SOC_HW_ERR_HBM1_CHNL7_FATAL},
>>>>> +    [18]        = {"PUNIT",
>>>>> +XE_SOC_HW_ERR_PUNIT_FATAL},
>>>>> +    [19 ... 31] = {"Undefined",
>>>>> +XE_SOC_HW_ERR_UNKNOWN_FATAL}, };
>>>>> +
>>>>> +static const struct err_msg_cntr_pair
>>>>> +soc_slave_glbl_err_reg_fatal[] = {
>>>>> +    [0]         = {"SLAVE LOCAL Reported",
>>>>> +XE_SOC_HW_ERR_SLAVE_LCL_FATAL},
>>>>> +    [1]         = {"HBM SS2: Channel0",
>>>>> +XE_SOC_HW_ERR_HBM2_CHNL0_FATAL},
>>>>> +    [2]         = {"HBM SS2: Channel1",
>>>>> +XE_SOC_HW_ERR_HBM2_CHNL1_FATAL},
>>>>> +    [3]         = {"HBM SS2: Channel2",
>>>>> +XE_SOC_HW_ERR_HBM2_CHNL2_FATAL},
>>>>> +    [4]         = {"HBM SS2: Channel3",
>>>>> +XE_SOC_HW_ERR_HBM2_CHNL3_FATAL},
>>>>> +    [5]         = {"HBM SS2: Channel4",
>>>>> +XE_SOC_HW_ERR_HBM2_CHNL4_FATAL},
>>>>> +    [6]         = {"HBM SS2: Channel5",
>>>>> +XE_SOC_HW_ERR_HBM2_CHNL5_FATAL},
>>>>> +    [7]         = {"HBM SS2: Channel6",
>>>>> +XE_SOC_HW_ERR_HBM2_CHNL6_FATAL},
>>>>> +    [8]         = {"HBM SS2: Channel7",
>>>>> +XE_SOC_HW_ERR_HBM2_CHNL7_FATAL},
>>>>> +    [9]         = {"HBM SS3: Channel0",
>>>>> +XE_SOC_HW_ERR_HBM3_CHNL0_FATAL},
>>>>> +    [10]        = {"HBM SS3: Channel1",
>>>>> +XE_SOC_HW_ERR_HBM3_CHNL1_FATAL},
>>>>> +    [11]        = {"HBM SS3: Channel2",
>>>>> +XE_SOC_HW_ERR_HBM3_CHNL2_FATAL},
>>>>> +    [12]        = {"HBM SS3: Channel3",
>>>>> +XE_SOC_HW_ERR_HBM3_CHNL3_FATAL},
>>>>> +    [13]        = {"HBM SS3: Channel4",
>>>>> +XE_SOC_HW_ERR_HBM3_CHNL4_FATAL},
>>>>> +    [14]        = {"HBM SS3: Channel5",
>>>>> +XE_SOC_HW_ERR_HBM3_CHNL5_FATAL},
>>>>> +    [15]        = {"HBM SS3: Channel6",
>>>>> +XE_SOC_HW_ERR_HBM3_CHNL6_FATAL},
>>>>> +    [16]        = {"HBM SS3: Channel7",
>>>>> +XE_SOC_HW_ERR_HBM3_CHNL7_FATAL},
>>>>> +    [18]        = {"ANR MDFI",
>>>>> +XE_SOC_HW_ERR_ANR_MDFI_FATAL},
>>>>> +    [17]        = {"Undefined",
>>>>> +XE_SOC_HW_ERR_UNKNOWN_FATAL},
>>>>> +    [19 ... 31] = {"Undefined",
>>>>> +XE_SOC_HW_ERR_UNKNOWN_FATAL}, };
>>>>> +
>>>>> +static const struct err_msg_cntr_pair soc_slave_lcl_err_reg_fatal[]
>>>>> += {
>>>>> +    [0]         = {"Local IEH Internal: Malformed PCIe AER",
>>>>> +XE_SOC_HW_ERR_PCIE_AER_FATAL},
>>>>> +    [1]         = {"Local IEH Internal: Malformed PCIe ERR",
>>>>> +XE_SOC_HW_ERR_PCIE_ERR_FATAL},
>>>>> +    [2]         = {"Local IEH Internal: UR CONDITIONS IN IEH",
>>>>> +XE_SOC_HW_ERR_UR_COND_FATAL},
>>>>> +    [3]         = {"Local IEH Internal: FROM SERR SOURCES",
>>>>> +XE_SOC_HW_ERR_SERR_SRCS_FATAL},
>>>>> +    [4 ... 31]  = {"Undefined",
>>>>> +XE_SOC_HW_ERR_UNKNOWN_FATAL}, };
>>>>> +
>>>>> +static const struct err_msg_cntr_pair soc_mstr_lcl_err_reg_fatal[]
>>>>> += {
>>>>> +    [0 ... 3]   = {"Undefined",
>>>>> +XE_SOC_HW_ERR_UNKNOWN_FATAL},
>>>>> +    [4]         = {"Base Die MDFI T2T",
>>>>> +XE_SOC_HW_ERR_MDFI_T2T_FATAL},
>>>>> +    [5]         = {"Undefined",
>>>>> +XE_SOC_HW_ERR_UNKNOWN_FATAL},
>>>>> +    [6]         = {"Base Die MDFI T2C",
>>>>> +XE_SOC_HW_ERR_MDFI_T2C_FATAL},
>>>>> +    [7]         = {"Undefined",
>>>>> +XE_SOC_HW_ERR_UNKNOWN_FATAL},
>>>>> +    [8]         = {"Invalid CSC PSF Command Parity",
>>>>> +XE_SOC_HW_ERR_CSC_PSF_CMD_FATAL},
>>>>> +    [9]         = {"Invalid CSC PSF Unexpected Completion",
>>>>> +XE_SOC_HW_ERR_CSC_PSF_CMP_FATAL},
>>>>> +    [10]        = {"Invalid CSC PSF Unsupported Request",
>>>>> +XE_SOC_HW_ERR_CSC_PSF_REQ_FATAL},
>>>>> +    [11]        = {"Invalid PCIe PSF Command Parity",
>>>>> +XE_SOC_HW_ERR_PCIE_PSF_CMD_FATAL},
>>>>> +    [12]        = {"PCIe PSF Unexpected Completion",
>>>>> +XE_SOC_HW_ERR_PCIE_PSF_CMP_FATAL},
>>>>> +    [13]        = {"PCIe PSF Unsupported Request",
>>>>> +XE_SOC_HW_ERR_PCIE_PSF_REQ_FATAL},
>>>>> +    [14 ... 31] = {"Undefined",
>>>>> +XE_SOC_HW_ERR_UNKNOWN_FATAL}, };
>>>>> +
>>>> we shall think of future extensibility, like we do in
>>>> xe_assign_hw_err_regs depending on platform for other registers.
>>> Yes that is in my mind. I was planing to move this struct under
>> xe_assign_hw_err_regs once new platform support is added for SOC error
>> handling.
>>> But to make things aligned can be taken care rightnow as well. Will address
>> in next patch.
>>>>>   static void xe_assign_hw_err_regs(struct xe_device *xe)
>>>>>   {
>>>>>       const struct err_msg_cntr_pair **dev_err_stat =
>>>>> xe->hw_err_regs.dev_err_stat; @@ -451,6 +520,104 @@
>>>>> xe_gsc_hw_error_handler(struct xe_tile *tile, const enum
>>>>> hardware_error hw_err)
>>>>>       xe_mmio_write32(mmio, GSC_HEC_ERR_STAT_REG(base, hw_err),
>>>>> errsrc);
>>>>>   }
>>>>>   +static void
>>>>> +xe_soc_log_err_update_cntr(struct xe_tile *tile,
>>>>> +               u32 errbit, const struct err_msg_cntr_pair
>>>>> +*reg_info) {
>>>>> +    const char *errmsg;
>>>>> +    u32 indx;
>>>>> +
>>>>> +    errmsg = reg_info[errbit].errmsg;
>>>>> +    indx = reg_info[errbit].cntr_indx;
>>>>> +
>>>>> +    drm_err_ratelimited(&tile_to_xe(tile)->drm, HW_ERR
>>>>> +                "Tile%d %s SOC FATAL error, bit[%d] is set\n",
>>>>> +                tile->id, errmsg, errbit);
>>>>> +    tile->errors.count[indx]++;
>>>>> +}
>>>>> +
>>>>> +static void
>>>>> +xe_soc_hw_error_handler(struct xe_tile *tile, const enum
>>>>> +hardware_error hw_err) {
>>>>> +    unsigned long mst_glb_errstat, slv_glb_errstat, lcl_errstat;
>>>>> +    u32 errbit, base, slave_base;
>>>>> +    int i;
>>>>> +    struct xe_gt *gt = tile->primary_gt;
>>>>> +
>>>>> +    lockdep_assert_held(&tile_to_xe(tile)->irq.lock);
>>>>> +
>>>>> +    if ((tile_to_xe(tile)->info.platform != XE_PVC) && hw_err !=
>>>>> +HARDWARE_ERROR_FATAL)
>>>>> +        return;
>>>>> +
>>>>> +    base = SOC_PVC_BASE;
>>>>> +    slave_base = SOC_PVC_SLAVE_BASE;
>>>>> +
>>>>> +    /*
>>>>> +     * Mask error type in GSYSEVTCTL so that no new errors of the
>>>>> +type
>>>>> +     * will be reported. Read the master global IEH error register
>>>>> +if
>>>>> +     * BIT 1 is set then process the slave IEH first. If BIT 0 in
>>>>> +     * global error register is set then process the corresponding
>>>>> +     * Local error registers
>>>>> +     */
>>>>> +    for (i = 0; i < PVC_NUM_IEH; i++)
>>>>> +        xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base,
>>>>> +i), ~REG_BIT(hw_err));
>>>>> +
>>>>> +    mst_glb_errstat = xe_mmio_read32(gt,
>>>>> +SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err));
>>>>> +    drm_info(&tile_to_xe(tile)->drm, HW_ERR
>>>>> +         "Tile%d
>> SOC_GLOBAL_ERR_STAT_MASTER_REG_FATAL:0x%08lx\n",
>>>>> +         tile->id, mst_glb_errstat);
>>>>> +
>>>>> +    if (mst_glb_errstat & REG_BIT(SOC_SLAVE_IEH)) {
>>>>> +        slv_glb_errstat = xe_mmio_read32(gt,
>>>>> +                         SOC_GLOBAL_ERR_STAT_SLAVE_REG(slave_base,
>>>>> +hw_err));
>>>>> +         drm_info(&tile_to_xe(tile)->drm, HW_ERR
>>>>> +              "Tile%d
>>>>> +SOC_GLOBAL_ERR_STAT_SLAVE_REG_FATAL:0x%08lx\n",
>>>>> +              tile->id, slv_glb_errstat);
>>>>> +
>>>>> +        if (slv_glb_errstat & REG_BIT(SOC_IEH1_LOCAL_ERR_STATUS)) {
>>>>> +            lcl_errstat = xe_mmio_read32(gt,
>>>>> +SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base,
>>>>> +                                              hw_err));
>>>>> +             drm_info(&tile_to_xe(tile)->drm, HW_ERR
>>>>> +                  "Tile%d
>>>>> +SOC_LOCAL_ERR_STAT_SLAVE_REG_FATAL:0x%08lx\n",
>>>>> +                  tile->id, lcl_errstat);
>>>>> +
>>>>> +            for_each_set_bit(errbit, &lcl_errstat, 32)
>>>>> +                xe_soc_log_err_update_cntr(tile, errbit,
>>>>> +                               soc_slave_lcl_err_reg_fatal);
>>>>> +
>>>>> +            xe_mmio_write32(gt,
>>>>> +SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
>>>>> +                    lcl_errstat);
>>>>> +        }
>>>>> +
>>>>> +        for_each_set_bit(errbit, &slv_glb_errstat, 32)
>>>>> +            xe_soc_log_err_update_cntr(tile, errbit,
>>>>> +soc_slave_glbl_err_reg_fatal);
>>>>> +
>>>>> +        xe_mmio_write32(gt,
>>>>> +SOC_GLOBAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
>>>>> +                slv_glb_errstat);
>>>>> +    }
>>>>> +
>>>>> +    if (mst_glb_errstat & REG_BIT(SOC_IEH0_LOCAL_ERR_STATUS)) {
>>>>> +        lcl_errstat = xe_mmio_read32(gt,
>>>>> +SOC_LOCAL_ERR_STAT_MASTER_REG(base, hw_err));
>>>>> +        drm_info(&tile_to_xe(tile)->drm, HW_ERR
>>>>> +"SOC_LOCAL_ERR_STAT_MASTER_REG_FATAL:0x%08lx\n",
>>>>> +             lcl_errstat);
>>>>> +
>>>>> +        for_each_set_bit(errbit, &lcl_errstat, 32)
>>>>> +            xe_soc_log_err_update_cntr(tile, errbit,
>>>>> +soc_mstr_lcl_err_reg_fatal);
>>>>> +
>>>>> +        xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_MASTER_REG(base,
>>>>> +hw_err), lcl_errstat);
>>>>> +    }
>>>>> +
>>>>> +    for_each_set_bit(errbit, &mst_glb_errstat, 32)
>>>>> +        xe_soc_log_err_update_cntr(tile, errbit,
>>>>> +soc_mstr_glbl_err_reg_fatal);
>>>>> +
>>>>> +    xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_MASTER_REG(base,
>>>>> +hw_err),
>>>>> +            mst_glb_errstat);
>>>>> +
>>>>> +    for (i = 0; i < PVC_NUM_IEH; i++)
>>>>> +        xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base,
>>>>> +i),
>>>>> +                (HARDWARE_ERROR_MAX << 1) + 1); }
>>>>> +
>>>>>   static void
>>>>>   xe_hw_error_source_handler(struct xe_tile *tile, const enum
>>>>> hardware_error hw_err)
>>>>>   {
>>>>> @@ -498,6 +665,9 @@ xe_hw_error_source_handler(struct xe_tile
>> *tile,
>>>>> const enum hardware_error hw_er
>>>>>             if (errbit == 8)
>>>>>               xe_gsc_hw_error_handler(tile, hw_err);
>>>>> +
>>>>> +        if (errbit == 16)
>>>>> +            xe_soc_hw_error_handler(tile, hw_err);
>>>>>       }
>>>>>         xe_mmio_write32(mmio, DEV_ERR_STAT_REG(hw_err), errsrc);
>>>>> diff --git a/drivers/gpu/drm/xe/xe_hw_error.h
>>>>> b/drivers/gpu/drm/xe/xe_hw_error.h
>>>>> index ee7705b3343b..05838e082abd 100644
>>>>> --- a/drivers/gpu/drm/xe/xe_hw_error.h
>>>>> +++ b/drivers/gpu/drm/xe/xe_hw_error.h
>>>>> @@ -65,6 +65,56 @@ enum xe_tile_hw_errors {
>>>>>       XE_GSC_HW_ERR_SELF_MBIST_UNCOR,
>>>>>       XE_GSC_HW_ERR_AON_RF_PARITY_UNCOR,
>>>>>       XE_GSC_HW_ERR_UNKNOWN_UNCOR,
>>>>> +    XE_SOC_HW_ERR_MSTR_LCL_FATAL,
>>>>> +    XE_SOC_HW_ERR_SLAVE_GLBL_FATAL,
>>>>> +    XE_SOC_HW_ERR_HBM0_CHNL0_FATAL,
>>>>> +    XE_SOC_HW_ERR_HBM0_CHNL1_FATAL,
>>>>> +    XE_SOC_HW_ERR_HBM0_CHNL2_FATAL,
>>>>> +    XE_SOC_HW_ERR_HBM0_CHNL3_FATAL,
>>>>> +    XE_SOC_HW_ERR_HBM0_CHNL4_FATAL,
>>>>> +    XE_SOC_HW_ERR_HBM0_CHNL5_FATAL,
>>>>> +    XE_SOC_HW_ERR_HBM0_CHNL6_FATAL,
>>>>> +    XE_SOC_HW_ERR_HBM0_CHNL7_FATAL,
>>>>> +    XE_SOC_HW_ERR_HBM1_CHNL0_FATAL,
>>>>> +    XE_SOC_HW_ERR_HBM1_CHNL1_FATAL,
>>>>> +    XE_SOC_HW_ERR_HBM1_CHNL2_FATAL,
>>>>> +    XE_SOC_HW_ERR_HBM1_CHNL3_FATAL,
>>>>> +    XE_SOC_HW_ERR_HBM1_CHNL4_FATAL,
>>>>> +    XE_SOC_HW_ERR_HBM1_CHNL5_FATAL,
>>>>> +    XE_SOC_HW_ERR_HBM1_CHNL6_FATAL,
>>>>> +    XE_SOC_HW_ERR_HBM1_CHNL7_FATAL,
>>>>> +    XE_SOC_HW_ERR_PUNIT_FATAL,
>>>>> +    XE_SOC_HW_ERR_UNKNOWN_FATAL,
>>>>> +    XE_SOC_HW_ERR_SLAVE_LCL_FATAL,
>>>>> +    XE_SOC_HW_ERR_HBM2_CHNL0_FATAL,
>>>>> +    XE_SOC_HW_ERR_HBM2_CHNL1_FATAL,
>>>>> +    XE_SOC_HW_ERR_HBM2_CHNL2_FATAL,
>>>>> +    XE_SOC_HW_ERR_HBM2_CHNL3_FATAL,
>>>>> +    XE_SOC_HW_ERR_HBM2_CHNL4_FATAL,
>>>>> +    XE_SOC_HW_ERR_HBM2_CHNL5_FATAL,
>>>>> +    XE_SOC_HW_ERR_HBM2_CHNL6_FATAL,
>>>>> +    XE_SOC_HW_ERR_HBM2_CHNL7_FATAL,
>>>>> +    XE_SOC_HW_ERR_HBM3_CHNL0_FATAL,
>>>>> +    XE_SOC_HW_ERR_HBM3_CHNL1_FATAL,
>>>>> +    XE_SOC_HW_ERR_HBM3_CHNL2_FATAL,
>>>>> +    XE_SOC_HW_ERR_HBM3_CHNL3_FATAL,
>>>>> +    XE_SOC_HW_ERR_HBM3_CHNL4_FATAL,
>>>>> +    XE_SOC_HW_ERR_HBM3_CHNL5_FATAL,
>>>>> +    XE_SOC_HW_ERR_HBM3_CHNL6_FATAL,
>>>>> +    XE_SOC_HW_ERR_HBM3_CHNL7_FATAL,
>>>>> +    XE_SOC_HW_ERR_ANR_MDFI_FATAL,
>>>>> +    XE_SOC_HW_ERR_PCIE_AER_FATAL,
>>>>> +    XE_SOC_HW_ERR_PCIE_ERR_FATAL,
>>>>> +    XE_SOC_HW_ERR_UR_COND_FATAL,
>>>>> +    XE_SOC_HW_ERR_SERR_SRCS_FATAL,
>>>>> +    XE_SOC_HW_ERR_MDFI_T2T_FATAL,
>>>>> +    XE_SOC_HW_ERR_MDFI_T2C_FATAL,
>>>>> +    XE_SOC_HW_ERR_CSC_PSF_CMD_FATAL,
>>>>> +    XE_SOC_HW_ERR_CSC_PSF_CMP_FATAL,
>>>>> +    XE_SOC_HW_ERR_CSC_PSF_REQ_FATAL,
>>>>> +    XE_SOC_HW_ERR_PCIE_PSF_CMD_FATAL,
>>>>> +    XE_SOC_HW_ERR_PCIE_PSF_CMP_FATAL,
>>>>> +    XE_SOC_HW_ERR_PCIE_PSF_REQ_FATAL,
>>>> even though soc errors fall under a tile it is better if we shall
>>>> have a separate enum for soc errors for 2 reasons, the other errors
>>>> in xe_tile_hw_errors are from top level registers while SOC are from
>>>> second level and also because these errors are most likely different on
>> different platforms.
>>>> so, we shall extend struct tile_hw_errors to have separate entry for soc.
>>> Makes sense. WIll address in next patch.
>>>>
>>>> Also, I'm thinking if we shall use xarray types for all members in
>>>> error counters under tile and gt with the enum list being big and which will
>> increase with each new platform.
>>> My initial thought was also to use xarray for soc error counters. But even if
>> we use xarray we need to have separate identifiers to identify which indexes
>> in xarray are actually valid hardware error and which are spurious interrupt.
>> Hence found no use of using xarray, if we still need to maintain all valid
>> indexes.
>>
>> xarray is supposedly be more memory efficient with large arrays, IIUC the
>> allocation for an index position will only be done when the index is used for
>> the first time.
> Hmm. With current approach, for soc counters we might end up allocating int array of 
> [32] [ 2] [3] [2] = 384 elements (considering we have only 1 slave ieh and all bits signify some error) and I am not sure whether 
> On further platform we will have more slaves IEH or not.
>
> With xarray the allocation will be dynamic and above array can be avoided. If recommendation is not to allocate this big arrays,  xarray will be better option.
> If array size is of no concern, we can avoid overhead of xarray referencing and dereferencing while storing and reading the counter values from respective index.

 I do not think that should be an issue in our present usecase which is not time critical and we have used this i915 as well with no known latency issues.

Thanks,

Aravind,

>
> BR
> Himal 
>
>> Thanks,
>> Aravind.
>>> BR
>>>
>>> Himal Ghimiray
>>>
>>>> Thanks,
>>>> Aravind.
>>>>
>>>>>       XE_TILE_HW_ERROR_MAX,
>>>>>   };
>>>>>   @@ -109,8 +159,12 @@ enum xe_gt_hw_errors {
>>>>>       XE_GT_HW_ERROR_MAX,
>>>>>   };
>>>>>   -#define ERR_STAT_GT_COR_VCTR_LEN (4) -#define
>>>>> ERR_STAT_GT_FATAL_VCTR_LEN (8)
>>>>> +#define ERR_STAT_GT_COR_VCTR_LEN    (4) #define
>>>>> +ERR_STAT_GT_FATAL_VCTR_LEN    (8) #define PVC_NUM_IEH
>>>>> +(1) #define SOC_SLAVE_IEH                   (1) #define
>>>>> +SOC_IEH0_LOCAL_ERR_STATUS       (0) #define
>>>>> +SOC_IEH1_LOCAL_ERR_STATUS       (0)
>>>>>     struct err_msg_cntr_pair {
>>>>>       const char *errmsg;

Re: [Intel-xe] [PATCH 07/11] drm/xe: Support SOC FATAL error handling for PVC.

[Ghimiray, Himal Prasad]

On 09-10-2023 14:30, Aravind Iddamsetty wrote:
> On 09/10/23 09:41, Ghimiray, Himal Prasad wrote:
>>> -----Original Message-----
>>> From: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
>>> Sent: 08 October 2023 15:03
>>> To: Ghimiray, Himal Prasad <himal.prasad.ghimiray@intel.com>; intel-
>>> xe@lists.freedesktop.org
>>> Subject: Re: [Intel-xe] [PATCH 07/11] drm/xe: Support SOC FATAL error
>>> handling for PVC.
>>>
>>>
>>> On 04/10/23 12:20, Ghimiray, Himal Prasad wrote:
>>>> On 04-10-2023 12:08, Aravind Iddamsetty wrote:
>>>>> On 27/09/23 17:16, Himal Prasad Ghimiray wrote:
>>>>> Hi Himal,
>>>>>
>>>>> I'm yet to review the full patch but sharing a few initial comments.
>>>> Hi Aravind,
>>>>
>>>> Thanks for the review comments.
>>>>
>>>>>> Report the SOC fatal hardware error and update the counters which
>>>>>> will increment incase of error.
>>>>>>
>>>>>> Signed-off-by: Himal Prasad
>>>>>> Ghimiray<himal.prasad.ghimiray@intel.com>
>>>>>> ---
>>>>>>    drivers/gpu/drm/xe/regs/xe_tile_error_regs.h |  28 +++
>>>>>>    drivers/gpu/drm/xe/xe_hw_error.c             | 170
>>>>>> +++++++++++++++++++
>>>>>>    drivers/gpu/drm/xe/xe_hw_error.h             |  58 ++++++-
>>>>>>    3 files changed, 254 insertions(+), 2 deletions(-)
>>>>>>
>>>>>> diff --git a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
>>>>>> b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
>>>>>> index fa16eaf9436b..04701c62f0d9 100644
>>>>>> --- a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
>>>>>> +++ b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
>>>>>> @@ -20,4 +20,32 @@
>>>>>>    #define GSC_HEC_ERR_STAT_REG(base, x)
>>>>>> XE_REG(_PICK_EVEN((x), \
>>>>>>                                    (base) + _GSC_HEC_CORR_ERR_STATUS,
>>>>>> \
>>>>>>                                    (base) +
>>>>>> _GSC_HEC_UNCOR_ERR_STATUS))
>>>>>> +#define SOC_PVC_BASE                   0x00282000 #define
>>>>>> +SOC_PVC_SLAVE_BASE             0x00283000
>>>>>> +
>>>>>> +#define _SOC_LERRCORSTS               0x000294 #define
>>>>>> +_SOC_LERRUNCSTS               0x000280 #define
>>>>>> +SOC_LOCAL_ERR_STAT_SLAVE_REG(base, x)        XE_REG((x) >
>>>>>> +HARDWARE_ERROR_CORRECTABLE ? \
>>>>>> +                                (base) + _SOC_LERRUNCSTS : \
>>>>>> +                                (base) + _SOC_LERRCORSTS)
>>>>>> +
>>>>>> +#define SOC_LOCAL_ERR_STAT_MASTER_REG(base, x)        XE_REG((x)
>>>>>> +HARDWARE_ERROR_CORRECTABLE ? \
>>>>>> +                                (base) + _SOC_LERRUNCSTS : \
>>>>>> +                                (base) + _SOC_LERRCORSTS) #define
>>>>>> +_SOC_GSYSEVTCTL                0x000264
>>>>>> +
>>>>>> +#define SOC_GSYSEVTCTL_REG(base, slave_base, x)
>>>>>> +XE_REG(_PICK_EVEN((x), \
>>>>>> +                                (base) + _SOC_GSYSEVTCTL, \
>>>>>> +                                slave_base + _SOC_GSYSEVTCTL))
>>>>>> +#define _SOC_GCOERRSTS                0x000200 #define
>>>>>> +_SOC_GNFERRSTS                0x000210 #define _SOC_GFAERRSTS
>>>>>> +0x000220 #define SOC_GLOBAL_ERR_STAT_SLAVE_REG(base, x)
>>>>>> +XE_REG(_PICK_EVEN((x), \
>>>>>> +                                (base) + _SOC_GCOERRSTS, \
>>>>>> +                                (base) + _SOC_GNFERRSTS))
>>>>>> +
>>>>>> +#define SOC_GLOBAL_ERR_STAT_MASTER_REG(base, x)
>>>>>> +XE_REG(_PICK_EVEN((x), \
>>>>>> +                                (base) + _SOC_GCOERRSTS, \
>>>>>> +                                (base) + _SOC_GNFERRSTS))
>>>>>> +
>>>>>>    #endif
>>>>>> diff --git a/drivers/gpu/drm/xe/xe_hw_error.c
>>>>>> b/drivers/gpu/drm/xe/xe_hw_error.c
>>>>>> index 76ae12df013c..fa05bad5e684 100644
>>>>>> --- a/drivers/gpu/drm/xe/xe_hw_error.c
>>>>>> +++ b/drivers/gpu/drm/xe/xe_hw_error.c
>>>>>> @@ -207,6 +207,75 @@ static const struct err_msg_cntr_pair
>>>>>> gsc_correctable_err_reg[] = {
>>>>>>        [2 ... 31] = {"Undefined",
>>>>>> XE_GSC_HW_ERR_UNKNOWN_CORR},
>>>>>>    };
>>>>>>    +static const struct err_msg_cntr_pair
>>>>>> soc_mstr_glbl_err_reg_fatal[] = {
>>>>>> +    [0]         = {"MASTER LOCAL Reported",
>>>>>> +XE_SOC_HW_ERR_MSTR_LCL_FATAL},
>>>>>> +    [1]         = {"SLAVE GLOBAL Reported",
>>>>>> +XE_SOC_HW_ERR_SLAVE_GLBL_FATAL},
>>>>>> +    [2]         = {"HBM SS0: Channel0",
>>>>>> +XE_SOC_HW_ERR_HBM0_CHNL0_FATAL},
>>>>>> +    [3]         = {"HBM SS0: Channel1",
>>>>>> +XE_SOC_HW_ERR_HBM0_CHNL1_FATAL},
>>>>>> +    [4]         = {"HBM SS0: Channel2",
>>>>>> +XE_SOC_HW_ERR_HBM0_CHNL2_FATAL},
>>>>>> +    [5]         = {"HBM SS0: Channel3",
>>>>>> +XE_SOC_HW_ERR_HBM0_CHNL3_FATAL},
>>>>>> +    [6]         = {"HBM SS0: Channel4",
>>>>>> +XE_SOC_HW_ERR_HBM0_CHNL4_FATAL},
>>>>>> +    [7]         = {"HBM SS0: Channel5",
>>>>>> +XE_SOC_HW_ERR_HBM0_CHNL5_FATAL},
>>>>>> +    [8]         = {"HBM SS0: Channel6",
>>>>>> +XE_SOC_HW_ERR_HBM0_CHNL6_FATAL},
>>>>>> +    [9]         = {"HBM SS0: Channel7",
>>>>>> +XE_SOC_HW_ERR_HBM0_CHNL7_FATAL},
>>>>>> +    [10]        = {"HBM SS1: Channel0",
>>>>>> +XE_SOC_HW_ERR_HBM1_CHNL0_FATAL},
>>>>>> +    [11]        = {"HBM SS1: Channel1",
>>>>>> +XE_SOC_HW_ERR_HBM1_CHNL1_FATAL},
>>>>>> +    [12]        = {"HBM SS1: Channel2",
>>>>>> +XE_SOC_HW_ERR_HBM1_CHNL2_FATAL},
>>>>>> +    [13]        = {"HBM SS1: Channel3",
>>>>>> +XE_SOC_HW_ERR_HBM1_CHNL3_FATAL},
>>>>>> +    [14]        = {"HBM SS1: Channel4",
>>>>>> +XE_SOC_HW_ERR_HBM1_CHNL4_FATAL},
>>>>>> +    [15]        = {"HBM SS1: Channel5",
>>>>>> +XE_SOC_HW_ERR_HBM1_CHNL5_FATAL},
>>>>>> +    [16]        = {"HBM SS1: Channel6",
>>>>>> +XE_SOC_HW_ERR_HBM1_CHNL6_FATAL},
>>>>>> +    [17]        = {"HBM SS1: Channel7",
>>>>>> +XE_SOC_HW_ERR_HBM1_CHNL7_FATAL},
>>>>>> +    [18]        = {"PUNIT",
>>>>>> +XE_SOC_HW_ERR_PUNIT_FATAL},
>>>>>> +    [19 ... 31] = {"Undefined",
>>>>>> +XE_SOC_HW_ERR_UNKNOWN_FATAL}, };
>>>>>> +
>>>>>> +static const struct err_msg_cntr_pair
>>>>>> +soc_slave_glbl_err_reg_fatal[] = {
>>>>>> +    [0]         = {"SLAVE LOCAL Reported",
>>>>>> +XE_SOC_HW_ERR_SLAVE_LCL_FATAL},
>>>>>> +    [1]         = {"HBM SS2: Channel0",
>>>>>> +XE_SOC_HW_ERR_HBM2_CHNL0_FATAL},
>>>>>> +    [2]         = {"HBM SS2: Channel1",
>>>>>> +XE_SOC_HW_ERR_HBM2_CHNL1_FATAL},
>>>>>> +    [3]         = {"HBM SS2: Channel2",
>>>>>> +XE_SOC_HW_ERR_HBM2_CHNL2_FATAL},
>>>>>> +    [4]         = {"HBM SS2: Channel3",
>>>>>> +XE_SOC_HW_ERR_HBM2_CHNL3_FATAL},
>>>>>> +    [5]         = {"HBM SS2: Channel4",
>>>>>> +XE_SOC_HW_ERR_HBM2_CHNL4_FATAL},
>>>>>> +    [6]         = {"HBM SS2: Channel5",
>>>>>> +XE_SOC_HW_ERR_HBM2_CHNL5_FATAL},
>>>>>> +    [7]         = {"HBM SS2: Channel6",
>>>>>> +XE_SOC_HW_ERR_HBM2_CHNL6_FATAL},
>>>>>> +    [8]         = {"HBM SS2: Channel7",
>>>>>> +XE_SOC_HW_ERR_HBM2_CHNL7_FATAL},
>>>>>> +    [9]         = {"HBM SS3: Channel0",
>>>>>> +XE_SOC_HW_ERR_HBM3_CHNL0_FATAL},
>>>>>> +    [10]        = {"HBM SS3: Channel1",
>>>>>> +XE_SOC_HW_ERR_HBM3_CHNL1_FATAL},
>>>>>> +    [11]        = {"HBM SS3: Channel2",
>>>>>> +XE_SOC_HW_ERR_HBM3_CHNL2_FATAL},
>>>>>> +    [12]        = {"HBM SS3: Channel3",
>>>>>> +XE_SOC_HW_ERR_HBM3_CHNL3_FATAL},
>>>>>> +    [13]        = {"HBM SS3: Channel4",
>>>>>> +XE_SOC_HW_ERR_HBM3_CHNL4_FATAL},
>>>>>> +    [14]        = {"HBM SS3: Channel5",
>>>>>> +XE_SOC_HW_ERR_HBM3_CHNL5_FATAL},
>>>>>> +    [15]        = {"HBM SS3: Channel6",
>>>>>> +XE_SOC_HW_ERR_HBM3_CHNL6_FATAL},
>>>>>> +    [16]        = {"HBM SS3: Channel7",
>>>>>> +XE_SOC_HW_ERR_HBM3_CHNL7_FATAL},
>>>>>> +    [18]        = {"ANR MDFI",
>>>>>> +XE_SOC_HW_ERR_ANR_MDFI_FATAL},
>>>>>> +    [17]        = {"Undefined",
>>>>>> +XE_SOC_HW_ERR_UNKNOWN_FATAL},
>>>>>> +    [19 ... 31] = {"Undefined",
>>>>>> +XE_SOC_HW_ERR_UNKNOWN_FATAL}, };
>>>>>> +
>>>>>> +static const struct err_msg_cntr_pair soc_slave_lcl_err_reg_fatal[]
>>>>>> += {
>>>>>> +    [0]         = {"Local IEH Internal: Malformed PCIe AER",
>>>>>> +XE_SOC_HW_ERR_PCIE_AER_FATAL},
>>>>>> +    [1]         = {"Local IEH Internal: Malformed PCIe ERR",
>>>>>> +XE_SOC_HW_ERR_PCIE_ERR_FATAL},
>>>>>> +    [2]         = {"Local IEH Internal: UR CONDITIONS IN IEH",
>>>>>> +XE_SOC_HW_ERR_UR_COND_FATAL},
>>>>>> +    [3]         = {"Local IEH Internal: FROM SERR SOURCES",
>>>>>> +XE_SOC_HW_ERR_SERR_SRCS_FATAL},
>>>>>> +    [4 ... 31]  = {"Undefined",
>>>>>> +XE_SOC_HW_ERR_UNKNOWN_FATAL}, };
>>>>>> +
>>>>>> +static const struct err_msg_cntr_pair soc_mstr_lcl_err_reg_fatal[]
>>>>>> += {
>>>>>> +    [0 ... 3]   = {"Undefined",
>>>>>> +XE_SOC_HW_ERR_UNKNOWN_FATAL},
>>>>>> +    [4]         = {"Base Die MDFI T2T",
>>>>>> +XE_SOC_HW_ERR_MDFI_T2T_FATAL},
>>>>>> +    [5]         = {"Undefined",
>>>>>> +XE_SOC_HW_ERR_UNKNOWN_FATAL},
>>>>>> +    [6]         = {"Base Die MDFI T2C",
>>>>>> +XE_SOC_HW_ERR_MDFI_T2C_FATAL},
>>>>>> +    [7]         = {"Undefined",
>>>>>> +XE_SOC_HW_ERR_UNKNOWN_FATAL},
>>>>>> +    [8]         = {"Invalid CSC PSF Command Parity",
>>>>>> +XE_SOC_HW_ERR_CSC_PSF_CMD_FATAL},
>>>>>> +    [9]         = {"Invalid CSC PSF Unexpected Completion",
>>>>>> +XE_SOC_HW_ERR_CSC_PSF_CMP_FATAL},
>>>>>> +    [10]        = {"Invalid CSC PSF Unsupported Request",
>>>>>> +XE_SOC_HW_ERR_CSC_PSF_REQ_FATAL},
>>>>>> +    [11]        = {"Invalid PCIe PSF Command Parity",
>>>>>> +XE_SOC_HW_ERR_PCIE_PSF_CMD_FATAL},
>>>>>> +    [12]        = {"PCIe PSF Unexpected Completion",
>>>>>> +XE_SOC_HW_ERR_PCIE_PSF_CMP_FATAL},
>>>>>> +    [13]        = {"PCIe PSF Unsupported Request",
>>>>>> +XE_SOC_HW_ERR_PCIE_PSF_REQ_FATAL},
>>>>>> +    [14 ... 31] = {"Undefined",
>>>>>> +XE_SOC_HW_ERR_UNKNOWN_FATAL}, };
>>>>>> +
>>>>> we shall think of future extensibility, like we do in
>>>>> xe_assign_hw_err_regs depending on platform for other registers.
>>>> Yes that is in my mind. I was planing to move this struct under
>>> xe_assign_hw_err_regs once new platform support is added for SOC error
>>> handling.
>>>> But to make things aligned can be taken care rightnow as well. Will address
>>> in next patch.
>>>>>>    static void xe_assign_hw_err_regs(struct xe_device *xe)
>>>>>>    {
>>>>>>        const struct err_msg_cntr_pair **dev_err_stat =
>>>>>> xe->hw_err_regs.dev_err_stat; @@ -451,6 +520,104 @@
>>>>>> xe_gsc_hw_error_handler(struct xe_tile *tile, const enum
>>>>>> hardware_error hw_err)
>>>>>>        xe_mmio_write32(mmio, GSC_HEC_ERR_STAT_REG(base, hw_err),
>>>>>> errsrc);
>>>>>>    }
>>>>>>    +static void
>>>>>> +xe_soc_log_err_update_cntr(struct xe_tile *tile,
>>>>>> +               u32 errbit, const struct err_msg_cntr_pair
>>>>>> +*reg_info) {
>>>>>> +    const char *errmsg;
>>>>>> +    u32 indx;
>>>>>> +
>>>>>> +    errmsg = reg_info[errbit].errmsg;
>>>>>> +    indx = reg_info[errbit].cntr_indx;
>>>>>> +
>>>>>> +    drm_err_ratelimited(&tile_to_xe(tile)->drm, HW_ERR
>>>>>> +                "Tile%d %s SOC FATAL error, bit[%d] is set\n",
>>>>>> +                tile->id, errmsg, errbit);
>>>>>> +    tile->errors.count[indx]++;
>>>>>> +}
>>>>>> +
>>>>>> +static void
>>>>>> +xe_soc_hw_error_handler(struct xe_tile *tile, const enum
>>>>>> +hardware_error hw_err) {
>>>>>> +    unsigned long mst_glb_errstat, slv_glb_errstat, lcl_errstat;
>>>>>> +    u32 errbit, base, slave_base;
>>>>>> +    int i;
>>>>>> +    struct xe_gt *gt = tile->primary_gt;
>>>>>> +
>>>>>> +    lockdep_assert_held(&tile_to_xe(tile)->irq.lock);
>>>>>> +
>>>>>> +    if ((tile_to_xe(tile)->info.platform != XE_PVC) && hw_err !=
>>>>>> +HARDWARE_ERROR_FATAL)
>>>>>> +        return;
>>>>>> +
>>>>>> +    base = SOC_PVC_BASE;
>>>>>> +    slave_base = SOC_PVC_SLAVE_BASE;
>>>>>> +
>>>>>> +    /*
>>>>>> +     * Mask error type in GSYSEVTCTL so that no new errors of the
>>>>>> +type
>>>>>> +     * will be reported. Read the master global IEH error register
>>>>>> +if
>>>>>> +     * BIT 1 is set then process the slave IEH first. If BIT 0 in
>>>>>> +     * global error register is set then process the corresponding
>>>>>> +     * Local error registers
>>>>>> +     */
>>>>>> +    for (i = 0; i < PVC_NUM_IEH; i++)
>>>>>> +        xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base,
>>>>>> +i), ~REG_BIT(hw_err));
>>>>>> +
>>>>>> +    mst_glb_errstat = xe_mmio_read32(gt,
>>>>>> +SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err));
>>>>>> +    drm_info(&tile_to_xe(tile)->drm, HW_ERR
>>>>>> +         "Tile%d
>>> SOC_GLOBAL_ERR_STAT_MASTER_REG_FATAL:0x%08lx\n",
>>>>>> +         tile->id, mst_glb_errstat);
>>>>>> +
>>>>>> +    if (mst_glb_errstat & REG_BIT(SOC_SLAVE_IEH)) {
>>>>>> +        slv_glb_errstat = xe_mmio_read32(gt,
>>>>>> +                         SOC_GLOBAL_ERR_STAT_SLAVE_REG(slave_base,
>>>>>> +hw_err));
>>>>>> +         drm_info(&tile_to_xe(tile)->drm, HW_ERR
>>>>>> +              "Tile%d
>>>>>> +SOC_GLOBAL_ERR_STAT_SLAVE_REG_FATAL:0x%08lx\n",
>>>>>> +              tile->id, slv_glb_errstat);
>>>>>> +
>>>>>> +        if (slv_glb_errstat & REG_BIT(SOC_IEH1_LOCAL_ERR_STATUS)) {
>>>>>> +            lcl_errstat = xe_mmio_read32(gt,
>>>>>> +SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base,
>>>>>> +                                              hw_err));
>>>>>> +             drm_info(&tile_to_xe(tile)->drm, HW_ERR
>>>>>> +                  "Tile%d
>>>>>> +SOC_LOCAL_ERR_STAT_SLAVE_REG_FATAL:0x%08lx\n",
>>>>>> +                  tile->id, lcl_errstat);
>>>>>> +
>>>>>> +            for_each_set_bit(errbit, &lcl_errstat, 32)
>>>>>> +                xe_soc_log_err_update_cntr(tile, errbit,
>>>>>> +                               soc_slave_lcl_err_reg_fatal);
>>>>>> +
>>>>>> +            xe_mmio_write32(gt,
>>>>>> +SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
>>>>>> +                    lcl_errstat);
>>>>>> +        }
>>>>>> +
>>>>>> +        for_each_set_bit(errbit, &slv_glb_errstat, 32)
>>>>>> +            xe_soc_log_err_update_cntr(tile, errbit,
>>>>>> +soc_slave_glbl_err_reg_fatal);
>>>>>> +
>>>>>> +        xe_mmio_write32(gt,
>>>>>> +SOC_GLOBAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
>>>>>> +                slv_glb_errstat);
>>>>>> +    }
>>>>>> +
>>>>>> +    if (mst_glb_errstat & REG_BIT(SOC_IEH0_LOCAL_ERR_STATUS)) {
>>>>>> +        lcl_errstat = xe_mmio_read32(gt,
>>>>>> +SOC_LOCAL_ERR_STAT_MASTER_REG(base, hw_err));
>>>>>> +        drm_info(&tile_to_xe(tile)->drm, HW_ERR
>>>>>> +"SOC_LOCAL_ERR_STAT_MASTER_REG_FATAL:0x%08lx\n",
>>>>>> +             lcl_errstat);
>>>>>> +
>>>>>> +        for_each_set_bit(errbit, &lcl_errstat, 32)
>>>>>> +            xe_soc_log_err_update_cntr(tile, errbit,
>>>>>> +soc_mstr_lcl_err_reg_fatal);
>>>>>> +
>>>>>> +        xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_MASTER_REG(base,
>>>>>> +hw_err), lcl_errstat);
>>>>>> +    }
>>>>>> +
>>>>>> +    for_each_set_bit(errbit, &mst_glb_errstat, 32)
>>>>>> +        xe_soc_log_err_update_cntr(tile, errbit,
>>>>>> +soc_mstr_glbl_err_reg_fatal);
>>>>>> +
>>>>>> +    xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_MASTER_REG(base,
>>>>>> +hw_err),
>>>>>> +            mst_glb_errstat);
>>>>>> +
>>>>>> +    for (i = 0; i < PVC_NUM_IEH; i++)
>>>>>> +        xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base,
>>>>>> +i),
>>>>>> +                (HARDWARE_ERROR_MAX << 1) + 1); }
>>>>>> +
>>>>>>    static void
>>>>>>    xe_hw_error_source_handler(struct xe_tile *tile, const enum
>>>>>> hardware_error hw_err)
>>>>>>    {
>>>>>> @@ -498,6 +665,9 @@ xe_hw_error_source_handler(struct xe_tile
>>> *tile,
>>>>>> const enum hardware_error hw_er
>>>>>>              if (errbit == 8)
>>>>>>                xe_gsc_hw_error_handler(tile, hw_err);
>>>>>> +
>>>>>> +        if (errbit == 16)
>>>>>> +            xe_soc_hw_error_handler(tile, hw_err);
>>>>>>        }
>>>>>>          xe_mmio_write32(mmio, DEV_ERR_STAT_REG(hw_err), errsrc);
>>>>>> diff --git a/drivers/gpu/drm/xe/xe_hw_error.h
>>>>>> b/drivers/gpu/drm/xe/xe_hw_error.h
>>>>>> index ee7705b3343b..05838e082abd 100644
>>>>>> --- a/drivers/gpu/drm/xe/xe_hw_error.h
>>>>>> +++ b/drivers/gpu/drm/xe/xe_hw_error.h
>>>>>> @@ -65,6 +65,56 @@ enum xe_tile_hw_errors {
>>>>>>        XE_GSC_HW_ERR_SELF_MBIST_UNCOR,
>>>>>>        XE_GSC_HW_ERR_AON_RF_PARITY_UNCOR,
>>>>>>        XE_GSC_HW_ERR_UNKNOWN_UNCOR,
>>>>>> +    XE_SOC_HW_ERR_MSTR_LCL_FATAL,
>>>>>> +    XE_SOC_HW_ERR_SLAVE_GLBL_FATAL,
>>>>>> +    XE_SOC_HW_ERR_HBM0_CHNL0_FATAL,
>>>>>> +    XE_SOC_HW_ERR_HBM0_CHNL1_FATAL,
>>>>>> +    XE_SOC_HW_ERR_HBM0_CHNL2_FATAL,
>>>>>> +    XE_SOC_HW_ERR_HBM0_CHNL3_FATAL,
>>>>>> +    XE_SOC_HW_ERR_HBM0_CHNL4_FATAL,
>>>>>> +    XE_SOC_HW_ERR_HBM0_CHNL5_FATAL,
>>>>>> +    XE_SOC_HW_ERR_HBM0_CHNL6_FATAL,
>>>>>> +    XE_SOC_HW_ERR_HBM0_CHNL7_FATAL,
>>>>>> +    XE_SOC_HW_ERR_HBM1_CHNL0_FATAL,
>>>>>> +    XE_SOC_HW_ERR_HBM1_CHNL1_FATAL,
>>>>>> +    XE_SOC_HW_ERR_HBM1_CHNL2_FATAL,
>>>>>> +    XE_SOC_HW_ERR_HBM1_CHNL3_FATAL,
>>>>>> +    XE_SOC_HW_ERR_HBM1_CHNL4_FATAL,
>>>>>> +    XE_SOC_HW_ERR_HBM1_CHNL5_FATAL,
>>>>>> +    XE_SOC_HW_ERR_HBM1_CHNL6_FATAL,
>>>>>> +    XE_SOC_HW_ERR_HBM1_CHNL7_FATAL,
>>>>>> +    XE_SOC_HW_ERR_PUNIT_FATAL,
>>>>>> +    XE_SOC_HW_ERR_UNKNOWN_FATAL,
>>>>>> +    XE_SOC_HW_ERR_SLAVE_LCL_FATAL,
>>>>>> +    XE_SOC_HW_ERR_HBM2_CHNL0_FATAL,
>>>>>> +    XE_SOC_HW_ERR_HBM2_CHNL1_FATAL,
>>>>>> +    XE_SOC_HW_ERR_HBM2_CHNL2_FATAL,
>>>>>> +    XE_SOC_HW_ERR_HBM2_CHNL3_FATAL,
>>>>>> +    XE_SOC_HW_ERR_HBM2_CHNL4_FATAL,
>>>>>> +    XE_SOC_HW_ERR_HBM2_CHNL5_FATAL,
>>>>>> +    XE_SOC_HW_ERR_HBM2_CHNL6_FATAL,
>>>>>> +    XE_SOC_HW_ERR_HBM2_CHNL7_FATAL,
>>>>>> +    XE_SOC_HW_ERR_HBM3_CHNL0_FATAL,
>>>>>> +    XE_SOC_HW_ERR_HBM3_CHNL1_FATAL,
>>>>>> +    XE_SOC_HW_ERR_HBM3_CHNL2_FATAL,
>>>>>> +    XE_SOC_HW_ERR_HBM3_CHNL3_FATAL,
>>>>>> +    XE_SOC_HW_ERR_HBM3_CHNL4_FATAL,
>>>>>> +    XE_SOC_HW_ERR_HBM3_CHNL5_FATAL,
>>>>>> +    XE_SOC_HW_ERR_HBM3_CHNL6_FATAL,
>>>>>> +    XE_SOC_HW_ERR_HBM3_CHNL7_FATAL,
>>>>>> +    XE_SOC_HW_ERR_ANR_MDFI_FATAL,
>>>>>> +    XE_SOC_HW_ERR_PCIE_AER_FATAL,
>>>>>> +    XE_SOC_HW_ERR_PCIE_ERR_FATAL,
>>>>>> +    XE_SOC_HW_ERR_UR_COND_FATAL,
>>>>>> +    XE_SOC_HW_ERR_SERR_SRCS_FATAL,
>>>>>> +    XE_SOC_HW_ERR_MDFI_T2T_FATAL,
>>>>>> +    XE_SOC_HW_ERR_MDFI_T2C_FATAL,
>>>>>> +    XE_SOC_HW_ERR_CSC_PSF_CMD_FATAL,
>>>>>> +    XE_SOC_HW_ERR_CSC_PSF_CMP_FATAL,
>>>>>> +    XE_SOC_HW_ERR_CSC_PSF_REQ_FATAL,
>>>>>> +    XE_SOC_HW_ERR_PCIE_PSF_CMD_FATAL,
>>>>>> +    XE_SOC_HW_ERR_PCIE_PSF_CMP_FATAL,
>>>>>> +    XE_SOC_HW_ERR_PCIE_PSF_REQ_FATAL,
>>>>> even though soc errors fall under a tile it is better if we shall
>>>>> have a separate enum for soc errors for 2 reasons, the other errors
>>>>> in xe_tile_hw_errors are from top level registers while SOC are from
>>>>> second level and also because these errors are most likely different on
>>> different platforms.
>>>>> so, we shall extend struct tile_hw_errors to have separate entry for soc.
>>>> Makes sense. WIll address in next patch.
>>>>> Also, I'm thinking if we shall use xarray types for all members in
>>>>> error counters under tile and gt with the enum list being big and which will
>>> increase with each new platform.
>>>> My initial thought was also to use xarray for soc error counters. But even if
>>> we use xarray we need to have separate identifiers to identify which indexes
>>> in xarray are actually valid hardware error and which are spurious interrupt.
>>> Hence found no use of using xarray, if we still need to maintain all valid
>>> indexes.
>>>
>>> xarray is supposedly be more memory efficient with large arrays, IIUC the
>>> allocation for an index position will only be done when the index is used for
>>> the first time.
>> Hmm. With current approach, for soc counters we might end up allocating int array of
>> [32] [ 2] [3] [2] = 384 elements (considering we have only 1 slave ieh and all bits signify some error) and I am not sure whether
>> On further platform we will have more slaves IEH or not.
>>
>> With xarray the allocation will be dynamic and above array can be avoided. If recommendation is not to allocate this big arrays,  xarray will be better option.
>> If array size is of no concern, we can avoid overhead of xarray referencing and dereferencing while storing and reading the counter values from respective index.
>   I do not think that should be an issue in our present usecase which is not time critical and we have used this i915 as well with no known latency issues.

Ok. In that case will update the counters using xarray instead of array 
in next patch.  Shall we use xarray for only socs counters or all other 
error types too ?

IMO other categories have very less counters hence using xarray doesn't 
seem logical.

>
> Thanks,
>
> Aravind,
>
>> BR
>> Himal
>>
>>> Thanks,
>>> Aravind.
>>>> BR
>>>>
>>>> Himal Ghimiray
>>>>
>>>>> Thanks,
>>>>> Aravind.
>>>>>
>>>>>>        XE_TILE_HW_ERROR_MAX,
>>>>>>    };
>>>>>>    @@ -109,8 +159,12 @@ enum xe_gt_hw_errors {
>>>>>>        XE_GT_HW_ERROR_MAX,
>>>>>>    };
>>>>>>    -#define ERR_STAT_GT_COR_VCTR_LEN (4) -#define
>>>>>> ERR_STAT_GT_FATAL_VCTR_LEN (8)
>>>>>> +#define ERR_STAT_GT_COR_VCTR_LEN    (4) #define
>>>>>> +ERR_STAT_GT_FATAL_VCTR_LEN    (8) #define PVC_NUM_IEH
>>>>>> +(1) #define SOC_SLAVE_IEH                   (1) #define
>>>>>> +SOC_IEH0_LOCAL_ERR_STATUS       (0) #define
>>>>>> +SOC_IEH1_LOCAL_ERR_STATUS       (0)
>>>>>>      struct err_msg_cntr_pair {
>>>>>>        const char *errmsg;

Re: [Intel-xe] [PATCH 07/11] drm/xe: Support SOC FATAL error handling for PVC.

[Aravind Iddamsetty]

On 09/10/23 14:45, Ghimiray, Himal Prasad wrote:
>
> On 09-10-2023 14:30, Aravind Iddamsetty wrote:
>> On 09/10/23 09:41, Ghimiray, Himal Prasad wrote:
>>>> -----Original Message-----
>>>> From: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
>>>> Sent: 08 October 2023 15:03
>>>> To: Ghimiray, Himal Prasad <himal.prasad.ghimiray@intel.com>; intel-
>>>> xe@lists.freedesktop.org
>>>> Subject: Re: [Intel-xe] [PATCH 07/11] drm/xe: Support SOC FATAL error
>>>> handling for PVC.
>>>>
>>>>
>>>> On 04/10/23 12:20, Ghimiray, Himal Prasad wrote:
>>>>> On 04-10-2023 12:08, Aravind Iddamsetty wrote:
>>>>>> On 27/09/23 17:16, Himal Prasad Ghimiray wrote:
>>>>>> Hi Himal,
>>>>>>
>>>>>> I'm yet to review the full patch but sharing a few initial comments.
>>>>> Hi Aravind,
>>>>>
>>>>> Thanks for the review comments.
>>>>>
>>>>>>> Report the SOC fatal hardware error and update the counters which
>>>>>>> will increment incase of error.
>>>>>>>
>>>>>>> Signed-off-by: Himal Prasad
>>>>>>> Ghimiray<himal.prasad.ghimiray@intel.com>
>>>>>>> ---
>>>>>>>    drivers/gpu/drm/xe/regs/xe_tile_error_regs.h |  28 +++
>>>>>>>    drivers/gpu/drm/xe/xe_hw_error.c             | 170
>>>>>>> +++++++++++++++++++
>>>>>>>    drivers/gpu/drm/xe/xe_hw_error.h             |  58 ++++++-
>>>>>>>    3 files changed, 254 insertions(+), 2 deletions(-)
>>>>>>>
>>>>>>> diff --git a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
>>>>>>> b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
>>>>>>> index fa16eaf9436b..04701c62f0d9 100644
>>>>>>> --- a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
>>>>>>> +++ b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
>>>>>>> @@ -20,4 +20,32 @@
>>>>>>>    #define GSC_HEC_ERR_STAT_REG(base, x)
>>>>>>> XE_REG(_PICK_EVEN((x), \
>>>>>>>                                    (base) + _GSC_HEC_CORR_ERR_STATUS,
>>>>>>> \
>>>>>>>                                    (base) +
>>>>>>> _GSC_HEC_UNCOR_ERR_STATUS))
>>>>>>> +#define SOC_PVC_BASE                   0x00282000 #define
>>>>>>> +SOC_PVC_SLAVE_BASE             0x00283000
>>>>>>> +
>>>>>>> +#define _SOC_LERRCORSTS               0x000294 #define
>>>>>>> +_SOC_LERRUNCSTS               0x000280 #define
>>>>>>> +SOC_LOCAL_ERR_STAT_SLAVE_REG(base, x)        XE_REG((x) >
>>>>>>> +HARDWARE_ERROR_CORRECTABLE ? \
>>>>>>> +                                (base) + _SOC_LERRUNCSTS : \
>>>>>>> +                                (base) + _SOC_LERRCORSTS)
>>>>>>> +
>>>>>>> +#define SOC_LOCAL_ERR_STAT_MASTER_REG(base, x)        XE_REG((x)
>>>>>>> +HARDWARE_ERROR_CORRECTABLE ? \
>>>>>>> +                                (base) + _SOC_LERRUNCSTS : \
>>>>>>> +                                (base) + _SOC_LERRCORSTS) #define
>>>>>>> +_SOC_GSYSEVTCTL                0x000264
>>>>>>> +
>>>>>>> +#define SOC_GSYSEVTCTL_REG(base, slave_base, x)
>>>>>>> +XE_REG(_PICK_EVEN((x), \
>>>>>>> +                                (base) + _SOC_GSYSEVTCTL, \
>>>>>>> +                                slave_base + _SOC_GSYSEVTCTL))
>>>>>>> +#define _SOC_GCOERRSTS                0x000200 #define
>>>>>>> +_SOC_GNFERRSTS                0x000210 #define _SOC_GFAERRSTS
>>>>>>> +0x000220 #define SOC_GLOBAL_ERR_STAT_SLAVE_REG(base, x)
>>>>>>> +XE_REG(_PICK_EVEN((x), \
>>>>>>> +                                (base) + _SOC_GCOERRSTS, \
>>>>>>> +                                (base) + _SOC_GNFERRSTS))
>>>>>>> +
>>>>>>> +#define SOC_GLOBAL_ERR_STAT_MASTER_REG(base, x)
>>>>>>> +XE_REG(_PICK_EVEN((x), \
>>>>>>> +                                (base) + _SOC_GCOERRSTS, \
>>>>>>> +                                (base) + _SOC_GNFERRSTS))
>>>>>>> +
>>>>>>>    #endif
>>>>>>> diff --git a/drivers/gpu/drm/xe/xe_hw_error.c
>>>>>>> b/drivers/gpu/drm/xe/xe_hw_error.c
>>>>>>> index 76ae12df013c..fa05bad5e684 100644
>>>>>>> --- a/drivers/gpu/drm/xe/xe_hw_error.c
>>>>>>> +++ b/drivers/gpu/drm/xe/xe_hw_error.c
>>>>>>> @@ -207,6 +207,75 @@ static const struct err_msg_cntr_pair
>>>>>>> gsc_correctable_err_reg[] = {
>>>>>>>        [2 ... 31] = {"Undefined",
>>>>>>> XE_GSC_HW_ERR_UNKNOWN_CORR},
>>>>>>>    };
>>>>>>>    +static const struct err_msg_cntr_pair
>>>>>>> soc_mstr_glbl_err_reg_fatal[] = {
>>>>>>> +    [0]         = {"MASTER LOCAL Reported",
>>>>>>> +XE_SOC_HW_ERR_MSTR_LCL_FATAL},
>>>>>>> +    [1]         = {"SLAVE GLOBAL Reported",
>>>>>>> +XE_SOC_HW_ERR_SLAVE_GLBL_FATAL},
>>>>>>> +    [2]         = {"HBM SS0: Channel0",
>>>>>>> +XE_SOC_HW_ERR_HBM0_CHNL0_FATAL},
>>>>>>> +    [3]         = {"HBM SS0: Channel1",
>>>>>>> +XE_SOC_HW_ERR_HBM0_CHNL1_FATAL},
>>>>>>> +    [4]         = {"HBM SS0: Channel2",
>>>>>>> +XE_SOC_HW_ERR_HBM0_CHNL2_FATAL},
>>>>>>> +    [5]         = {"HBM SS0: Channel3",
>>>>>>> +XE_SOC_HW_ERR_HBM0_CHNL3_FATAL},
>>>>>>> +    [6]         = {"HBM SS0: Channel4",
>>>>>>> +XE_SOC_HW_ERR_HBM0_CHNL4_FATAL},
>>>>>>> +    [7]         = {"HBM SS0: Channel5",
>>>>>>> +XE_SOC_HW_ERR_HBM0_CHNL5_FATAL},
>>>>>>> +    [8]         = {"HBM SS0: Channel6",
>>>>>>> +XE_SOC_HW_ERR_HBM0_CHNL6_FATAL},
>>>>>>> +    [9]         = {"HBM SS0: Channel7",
>>>>>>> +XE_SOC_HW_ERR_HBM0_CHNL7_FATAL},
>>>>>>> +    [10]        = {"HBM SS1: Channel0",
>>>>>>> +XE_SOC_HW_ERR_HBM1_CHNL0_FATAL},
>>>>>>> +    [11]        = {"HBM SS1: Channel1",
>>>>>>> +XE_SOC_HW_ERR_HBM1_CHNL1_FATAL},
>>>>>>> +    [12]        = {"HBM SS1: Channel2",
>>>>>>> +XE_SOC_HW_ERR_HBM1_CHNL2_FATAL},
>>>>>>> +    [13]        = {"HBM SS1: Channel3",
>>>>>>> +XE_SOC_HW_ERR_HBM1_CHNL3_FATAL},
>>>>>>> +    [14]        = {"HBM SS1: Channel4",
>>>>>>> +XE_SOC_HW_ERR_HBM1_CHNL4_FATAL},
>>>>>>> +    [15]        = {"HBM SS1: Channel5",
>>>>>>> +XE_SOC_HW_ERR_HBM1_CHNL5_FATAL},
>>>>>>> +    [16]        = {"HBM SS1: Channel6",
>>>>>>> +XE_SOC_HW_ERR_HBM1_CHNL6_FATAL},
>>>>>>> +    [17]        = {"HBM SS1: Channel7",
>>>>>>> +XE_SOC_HW_ERR_HBM1_CHNL7_FATAL},
>>>>>>> +    [18]        = {"PUNIT",
>>>>>>> +XE_SOC_HW_ERR_PUNIT_FATAL},
>>>>>>> +    [19 ... 31] = {"Undefined",
>>>>>>> +XE_SOC_HW_ERR_UNKNOWN_FATAL}, };
>>>>>>> +
>>>>>>> +static const struct err_msg_cntr_pair
>>>>>>> +soc_slave_glbl_err_reg_fatal[] = {
>>>>>>> +    [0]         = {"SLAVE LOCAL Reported",
>>>>>>> +XE_SOC_HW_ERR_SLAVE_LCL_FATAL},
>>>>>>> +    [1]         = {"HBM SS2: Channel0",
>>>>>>> +XE_SOC_HW_ERR_HBM2_CHNL0_FATAL},
>>>>>>> +    [2]         = {"HBM SS2: Channel1",
>>>>>>> +XE_SOC_HW_ERR_HBM2_CHNL1_FATAL},
>>>>>>> +    [3]         = {"HBM SS2: Channel2",
>>>>>>> +XE_SOC_HW_ERR_HBM2_CHNL2_FATAL},
>>>>>>> +    [4]         = {"HBM SS2: Channel3",
>>>>>>> +XE_SOC_HW_ERR_HBM2_CHNL3_FATAL},
>>>>>>> +    [5]         = {"HBM SS2: Channel4",
>>>>>>> +XE_SOC_HW_ERR_HBM2_CHNL4_FATAL},
>>>>>>> +    [6]         = {"HBM SS2: Channel5",
>>>>>>> +XE_SOC_HW_ERR_HBM2_CHNL5_FATAL},
>>>>>>> +    [7]         = {"HBM SS2: Channel6",
>>>>>>> +XE_SOC_HW_ERR_HBM2_CHNL6_FATAL},
>>>>>>> +    [8]         = {"HBM SS2: Channel7",
>>>>>>> +XE_SOC_HW_ERR_HBM2_CHNL7_FATAL},
>>>>>>> +    [9]         = {"HBM SS3: Channel0",
>>>>>>> +XE_SOC_HW_ERR_HBM3_CHNL0_FATAL},
>>>>>>> +    [10]        = {"HBM SS3: Channel1",
>>>>>>> +XE_SOC_HW_ERR_HBM3_CHNL1_FATAL},
>>>>>>> +    [11]        = {"HBM SS3: Channel2",
>>>>>>> +XE_SOC_HW_ERR_HBM3_CHNL2_FATAL},
>>>>>>> +    [12]        = {"HBM SS3: Channel3",
>>>>>>> +XE_SOC_HW_ERR_HBM3_CHNL3_FATAL},
>>>>>>> +    [13]        = {"HBM SS3: Channel4",
>>>>>>> +XE_SOC_HW_ERR_HBM3_CHNL4_FATAL},
>>>>>>> +    [14]        = {"HBM SS3: Channel5",
>>>>>>> +XE_SOC_HW_ERR_HBM3_CHNL5_FATAL},
>>>>>>> +    [15]        = {"HBM SS3: Channel6",
>>>>>>> +XE_SOC_HW_ERR_HBM3_CHNL6_FATAL},
>>>>>>> +    [16]        = {"HBM SS3: Channel7",
>>>>>>> +XE_SOC_HW_ERR_HBM3_CHNL7_FATAL},
>>>>>>> +    [18]        = {"ANR MDFI",
>>>>>>> +XE_SOC_HW_ERR_ANR_MDFI_FATAL},
>>>>>>> +    [17]        = {"Undefined",
>>>>>>> +XE_SOC_HW_ERR_UNKNOWN_FATAL},
>>>>>>> +    [19 ... 31] = {"Undefined",
>>>>>>> +XE_SOC_HW_ERR_UNKNOWN_FATAL}, };
>>>>>>> +
>>>>>>> +static const struct err_msg_cntr_pair soc_slave_lcl_err_reg_fatal[]
>>>>>>> += {
>>>>>>> +    [0]         = {"Local IEH Internal: Malformed PCIe AER",
>>>>>>> +XE_SOC_HW_ERR_PCIE_AER_FATAL},
>>>>>>> +    [1]         = {"Local IEH Internal: Malformed PCIe ERR",
>>>>>>> +XE_SOC_HW_ERR_PCIE_ERR_FATAL},
>>>>>>> +    [2]         = {"Local IEH Internal: UR CONDITIONS IN IEH",
>>>>>>> +XE_SOC_HW_ERR_UR_COND_FATAL},
>>>>>>> +    [3]         = {"Local IEH Internal: FROM SERR SOURCES",
>>>>>>> +XE_SOC_HW_ERR_SERR_SRCS_FATAL},
>>>>>>> +    [4 ... 31]  = {"Undefined",
>>>>>>> +XE_SOC_HW_ERR_UNKNOWN_FATAL}, };
>>>>>>> +
>>>>>>> +static const struct err_msg_cntr_pair soc_mstr_lcl_err_reg_fatal[]
>>>>>>> += {
>>>>>>> +    [0 ... 3]   = {"Undefined",
>>>>>>> +XE_SOC_HW_ERR_UNKNOWN_FATAL},
>>>>>>> +    [4]         = {"Base Die MDFI T2T",
>>>>>>> +XE_SOC_HW_ERR_MDFI_T2T_FATAL},
>>>>>>> +    [5]         = {"Undefined",
>>>>>>> +XE_SOC_HW_ERR_UNKNOWN_FATAL},
>>>>>>> +    [6]         = {"Base Die MDFI T2C",
>>>>>>> +XE_SOC_HW_ERR_MDFI_T2C_FATAL},
>>>>>>> +    [7]         = {"Undefined",
>>>>>>> +XE_SOC_HW_ERR_UNKNOWN_FATAL},
>>>>>>> +    [8]         = {"Invalid CSC PSF Command Parity",
>>>>>>> +XE_SOC_HW_ERR_CSC_PSF_CMD_FATAL},
>>>>>>> +    [9]         = {"Invalid CSC PSF Unexpected Completion",
>>>>>>> +XE_SOC_HW_ERR_CSC_PSF_CMP_FATAL},
>>>>>>> +    [10]        = {"Invalid CSC PSF Unsupported Request",
>>>>>>> +XE_SOC_HW_ERR_CSC_PSF_REQ_FATAL},
>>>>>>> +    [11]        = {"Invalid PCIe PSF Command Parity",
>>>>>>> +XE_SOC_HW_ERR_PCIE_PSF_CMD_FATAL},
>>>>>>> +    [12]        = {"PCIe PSF Unexpected Completion",
>>>>>>> +XE_SOC_HW_ERR_PCIE_PSF_CMP_FATAL},
>>>>>>> +    [13]        = {"PCIe PSF Unsupported Request",
>>>>>>> +XE_SOC_HW_ERR_PCIE_PSF_REQ_FATAL},
>>>>>>> +    [14 ... 31] = {"Undefined",
>>>>>>> +XE_SOC_HW_ERR_UNKNOWN_FATAL}, };
>>>>>>> +
>>>>>> we shall think of future extensibility, like we do in
>>>>>> xe_assign_hw_err_regs depending on platform for other registers.
>>>>> Yes that is in my mind. I was planing to move this struct under
>>>> xe_assign_hw_err_regs once new platform support is added for SOC error
>>>> handling.
>>>>> But to make things aligned can be taken care rightnow as well. Will address
>>>> in next patch.
>>>>>>>    static void xe_assign_hw_err_regs(struct xe_device *xe)
>>>>>>>    {
>>>>>>>        const struct err_msg_cntr_pair **dev_err_stat =
>>>>>>> xe->hw_err_regs.dev_err_stat; @@ -451,6 +520,104 @@
>>>>>>> xe_gsc_hw_error_handler(struct xe_tile *tile, const enum
>>>>>>> hardware_error hw_err)
>>>>>>>        xe_mmio_write32(mmio, GSC_HEC_ERR_STAT_REG(base, hw_err),
>>>>>>> errsrc);
>>>>>>>    }
>>>>>>>    +static void
>>>>>>> +xe_soc_log_err_update_cntr(struct xe_tile *tile,
>>>>>>> +               u32 errbit, const struct err_msg_cntr_pair
>>>>>>> +*reg_info) {
>>>>>>> +    const char *errmsg;
>>>>>>> +    u32 indx;
>>>>>>> +
>>>>>>> +    errmsg = reg_info[errbit].errmsg;
>>>>>>> +    indx = reg_info[errbit].cntr_indx;
>>>>>>> +
>>>>>>> +    drm_err_ratelimited(&tile_to_xe(tile)->drm, HW_ERR
>>>>>>> +                "Tile%d %s SOC FATAL error, bit[%d] is set\n",
>>>>>>> +                tile->id, errmsg, errbit);
>>>>>>> +    tile->errors.count[indx]++;
>>>>>>> +}
>>>>>>> +
>>>>>>> +static void
>>>>>>> +xe_soc_hw_error_handler(struct xe_tile *tile, const enum
>>>>>>> +hardware_error hw_err) {
>>>>>>> +    unsigned long mst_glb_errstat, slv_glb_errstat, lcl_errstat;
>>>>>>> +    u32 errbit, base, slave_base;
>>>>>>> +    int i;
>>>>>>> +    struct xe_gt *gt = tile->primary_gt;
>>>>>>> +
>>>>>>> +    lockdep_assert_held(&tile_to_xe(tile)->irq.lock);
>>>>>>> +
>>>>>>> +    if ((tile_to_xe(tile)->info.platform != XE_PVC) && hw_err !=
>>>>>>> +HARDWARE_ERROR_FATAL)
>>>>>>> +        return;
>>>>>>> +
>>>>>>> +    base = SOC_PVC_BASE;
>>>>>>> +    slave_base = SOC_PVC_SLAVE_BASE;
>>>>>>> +
>>>>>>> +    /*
>>>>>>> +     * Mask error type in GSYSEVTCTL so that no new errors of the
>>>>>>> +type
>>>>>>> +     * will be reported. Read the master global IEH error register
>>>>>>> +if
>>>>>>> +     * BIT 1 is set then process the slave IEH first. If BIT 0 in
>>>>>>> +     * global error register is set then process the corresponding
>>>>>>> +     * Local error registers
>>>>>>> +     */
>>>>>>> +    for (i = 0; i < PVC_NUM_IEH; i++)
>>>>>>> +        xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base,
>>>>>>> +i), ~REG_BIT(hw_err));
>>>>>>> +
>>>>>>> +    mst_glb_errstat = xe_mmio_read32(gt,
>>>>>>> +SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err));
>>>>>>> +    drm_info(&tile_to_xe(tile)->drm, HW_ERR
>>>>>>> +         "Tile%d
>>>> SOC_GLOBAL_ERR_STAT_MASTER_REG_FATAL:0x%08lx\n",
>>>>>>> +         tile->id, mst_glb_errstat);
>>>>>>> +
>>>>>>> +    if (mst_glb_errstat & REG_BIT(SOC_SLAVE_IEH)) {
>>>>>>> +        slv_glb_errstat = xe_mmio_read32(gt,
>>>>>>> +                         SOC_GLOBAL_ERR_STAT_SLAVE_REG(slave_base,
>>>>>>> +hw_err));
>>>>>>> +         drm_info(&tile_to_xe(tile)->drm, HW_ERR
>>>>>>> +              "Tile%d
>>>>>>> +SOC_GLOBAL_ERR_STAT_SLAVE_REG_FATAL:0x%08lx\n",
>>>>>>> +              tile->id, slv_glb_errstat);
>>>>>>> +
>>>>>>> +        if (slv_glb_errstat & REG_BIT(SOC_IEH1_LOCAL_ERR_STATUS)) {
>>>>>>> +            lcl_errstat = xe_mmio_read32(gt,
>>>>>>> +SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base,
>>>>>>> +                                              hw_err));
>>>>>>> +             drm_info(&tile_to_xe(tile)->drm, HW_ERR
>>>>>>> +                  "Tile%d
>>>>>>> +SOC_LOCAL_ERR_STAT_SLAVE_REG_FATAL:0x%08lx\n",
>>>>>>> +                  tile->id, lcl_errstat);
>>>>>>> +
>>>>>>> +            for_each_set_bit(errbit, &lcl_errstat, 32)
>>>>>>> +                xe_soc_log_err_update_cntr(tile, errbit,
>>>>>>> +                               soc_slave_lcl_err_reg_fatal);
>>>>>>> +
>>>>>>> +            xe_mmio_write32(gt,
>>>>>>> +SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
>>>>>>> +                    lcl_errstat);
>>>>>>> +        }
>>>>>>> +
>>>>>>> +        for_each_set_bit(errbit, &slv_glb_errstat, 32)
>>>>>>> +            xe_soc_log_err_update_cntr(tile, errbit,
>>>>>>> +soc_slave_glbl_err_reg_fatal);
>>>>>>> +
>>>>>>> +        xe_mmio_write32(gt,
>>>>>>> +SOC_GLOBAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
>>>>>>> +                slv_glb_errstat);
>>>>>>> +    }
>>>>>>> +
>>>>>>> +    if (mst_glb_errstat & REG_BIT(SOC_IEH0_LOCAL_ERR_STATUS)) {
>>>>>>> +        lcl_errstat = xe_mmio_read32(gt,
>>>>>>> +SOC_LOCAL_ERR_STAT_MASTER_REG(base, hw_err));
>>>>>>> +        drm_info(&tile_to_xe(tile)->drm, HW_ERR
>>>>>>> +"SOC_LOCAL_ERR_STAT_MASTER_REG_FATAL:0x%08lx\n",
>>>>>>> +             lcl_errstat);
>>>>>>> +
>>>>>>> +        for_each_set_bit(errbit, &lcl_errstat, 32)
>>>>>>> +            xe_soc_log_err_update_cntr(tile, errbit,
>>>>>>> +soc_mstr_lcl_err_reg_fatal);
>>>>>>> +
>>>>>>> +        xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_MASTER_REG(base,
>>>>>>> +hw_err), lcl_errstat);
>>>>>>> +    }
>>>>>>> +
>>>>>>> +    for_each_set_bit(errbit, &mst_glb_errstat, 32)
>>>>>>> +        xe_soc_log_err_update_cntr(tile, errbit,
>>>>>>> +soc_mstr_glbl_err_reg_fatal);
>>>>>>> +
>>>>>>> +    xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_MASTER_REG(base,
>>>>>>> +hw_err),
>>>>>>> +            mst_glb_errstat);
>>>>>>> +
>>>>>>> +    for (i = 0; i < PVC_NUM_IEH; i++)
>>>>>>> +        xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base,
>>>>>>> +i),
>>>>>>> +                (HARDWARE_ERROR_MAX << 1) + 1); }
>>>>>>> +
>>>>>>>    static void
>>>>>>>    xe_hw_error_source_handler(struct xe_tile *tile, const enum
>>>>>>> hardware_error hw_err)
>>>>>>>    {
>>>>>>> @@ -498,6 +665,9 @@ xe_hw_error_source_handler(struct xe_tile
>>>> *tile,
>>>>>>> const enum hardware_error hw_er
>>>>>>>              if (errbit == 8)
>>>>>>>                xe_gsc_hw_error_handler(tile, hw_err);
>>>>>>> +
>>>>>>> +        if (errbit == 16)
>>>>>>> +            xe_soc_hw_error_handler(tile, hw_err);
>>>>>>>        }
>>>>>>>          xe_mmio_write32(mmio, DEV_ERR_STAT_REG(hw_err), errsrc);
>>>>>>> diff --git a/drivers/gpu/drm/xe/xe_hw_error.h
>>>>>>> b/drivers/gpu/drm/xe/xe_hw_error.h
>>>>>>> index ee7705b3343b..05838e082abd 100644
>>>>>>> --- a/drivers/gpu/drm/xe/xe_hw_error.h
>>>>>>> +++ b/drivers/gpu/drm/xe/xe_hw_error.h
>>>>>>> @@ -65,6 +65,56 @@ enum xe_tile_hw_errors {
>>>>>>>        XE_GSC_HW_ERR_SELF_MBIST_UNCOR,
>>>>>>>        XE_GSC_HW_ERR_AON_RF_PARITY_UNCOR,
>>>>>>>        XE_GSC_HW_ERR_UNKNOWN_UNCOR,
>>>>>>> +    XE_SOC_HW_ERR_MSTR_LCL_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_SLAVE_GLBL_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_HBM0_CHNL0_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_HBM0_CHNL1_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_HBM0_CHNL2_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_HBM0_CHNL3_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_HBM0_CHNL4_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_HBM0_CHNL5_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_HBM0_CHNL6_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_HBM0_CHNL7_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_HBM1_CHNL0_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_HBM1_CHNL1_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_HBM1_CHNL2_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_HBM1_CHNL3_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_HBM1_CHNL4_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_HBM1_CHNL5_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_HBM1_CHNL6_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_HBM1_CHNL7_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_PUNIT_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_UNKNOWN_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_SLAVE_LCL_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_HBM2_CHNL0_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_HBM2_CHNL1_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_HBM2_CHNL2_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_HBM2_CHNL3_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_HBM2_CHNL4_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_HBM2_CHNL5_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_HBM2_CHNL6_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_HBM2_CHNL7_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_HBM3_CHNL0_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_HBM3_CHNL1_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_HBM3_CHNL2_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_HBM3_CHNL3_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_HBM3_CHNL4_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_HBM3_CHNL5_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_HBM3_CHNL6_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_HBM3_CHNL7_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_ANR_MDFI_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_PCIE_AER_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_PCIE_ERR_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_UR_COND_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_SERR_SRCS_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_MDFI_T2T_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_MDFI_T2C_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_CSC_PSF_CMD_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_CSC_PSF_CMP_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_CSC_PSF_REQ_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_PCIE_PSF_CMD_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_PCIE_PSF_CMP_FATAL,
>>>>>>> +    XE_SOC_HW_ERR_PCIE_PSF_REQ_FATAL,
>>>>>> even though soc errors fall under a tile it is better if we shall
>>>>>> have a separate enum for soc errors for 2 reasons, the other errors
>>>>>> in xe_tile_hw_errors are from top level registers while SOC are from
>>>>>> second level and also because these errors are most likely different on
>>>> different platforms.
>>>>>> so, we shall extend struct tile_hw_errors to have separate entry for soc.
>>>>> Makes sense. WIll address in next patch.
>>>>>> Also, I'm thinking if we shall use xarray types for all members in
>>>>>> error counters under tile and gt with the enum list being big and which will
>>>> increase with each new platform.
>>>>> My initial thought was also to use xarray for soc error counters. But even if
>>>> we use xarray we need to have separate identifiers to identify which indexes
>>>> in xarray are actually valid hardware error and which are spurious interrupt.
>>>> Hence found no use of using xarray, if we still need to maintain all valid
>>>> indexes.
>>>>
>>>> xarray is supposedly be more memory efficient with large arrays, IIUC the
>>>> allocation for an index position will only be done when the index is used for
>>>> the first time.
>>> Hmm. With current approach, for soc counters we might end up allocating int array of
>>> [32] [ 2] [3] [2] = 384 elements (considering we have only 1 slave ieh and all bits signify some error) and I am not sure whether
>>> On further platform we will have more slaves IEH or not.
>>>
>>> With xarray the allocation will be dynamic and above array can be avoided. If recommendation is not to allocate this big arrays,  xarray will be better option.
>>> If array size is of no concern, we can avoid overhead of xarray referencing and dereferencing while storing and reading the counter values from respective index.
>>   I do not think that should be an issue in our present usecase which is not time critical and we have used this i915 as well with no known latency issues.
>
> Ok. In that case will update the counters using xarray instead of array in next patch.  Shall we use xarray for only socs counters or all other error types too ?

we only have two counters right tile->errors.count and gt->errors.count so make them xarray.

Thanks,
Aravind.
>
> IMO other categories have very less counters hence using xarray doesn't seem logical.
>
>>
>> Thanks,
>>
>> Aravind,
>>
>>> BR
>>> Himal
>>>
>>>> Thanks,
>>>> Aravind.
>>>>> BR
>>>>>
>>>>> Himal Ghimiray
>>>>>
>>>>>> Thanks,
>>>>>> Aravind.
>>>>>>
>>>>>>>        XE_TILE_HW_ERROR_MAX,
>>>>>>>    };
>>>>>>>    @@ -109,8 +159,12 @@ enum xe_gt_hw_errors {
>>>>>>>        XE_GT_HW_ERROR_MAX,
>>>>>>>    };
>>>>>>>    -#define ERR_STAT_GT_COR_VCTR_LEN (4) -#define
>>>>>>> ERR_STAT_GT_FATAL_VCTR_LEN (8)
>>>>>>> +#define ERR_STAT_GT_COR_VCTR_LEN    (4) #define
>>>>>>> +ERR_STAT_GT_FATAL_VCTR_LEN    (8) #define PVC_NUM_IEH
>>>>>>> +(1) #define SOC_SLAVE_IEH                   (1) #define
>>>>>>> +SOC_IEH0_LOCAL_ERR_STATUS       (0) #define
>>>>>>> +SOC_IEH1_LOCAL_ERR_STATUS       (0)
>>>>>>>      struct err_msg_cntr_pair {
>>>>>>>        const char *errmsg;

Re: [Intel-xe] [PATCH 07/11] drm/xe: Support SOC FATAL error handling for PVC.

[Aravind Iddamsetty]

On 27/09/23 17:16, Himal Prasad Ghimiray wrote:
> Report the SOC fatal hardware error and update the counters which will
> increment incase of error.
>
> Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_tile_error_regs.h |  28 +++
>  drivers/gpu/drm/xe/xe_hw_error.c             | 170 +++++++++++++++++++
>  drivers/gpu/drm/xe/xe_hw_error.h             |  58 ++++++-
>  3 files changed, 254 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
> index fa16eaf9436b..04701c62f0d9 100644
> --- a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
> @@ -20,4 +20,32 @@
>  #define GSC_HEC_ERR_STAT_REG(base, x)                  XE_REG(_PICK_EVEN((x), \
>  								(base) + _GSC_HEC_CORR_ERR_STATUS, \
>  								(base) + _GSC_HEC_UNCOR_ERR_STATUS))
> +#define SOC_PVC_BASE	               0x00282000
> +#define SOC_PVC_SLAVE_BASE             0x00283000

why do we need to prepend the register defines with 0s ?.

> +
> +#define _SOC_LERRCORSTS		       0x000294
> +#define _SOC_LERRUNCSTS		       0x000280
> +#define SOC_LOCAL_ERR_STAT_SLAVE_REG(base, x)		XE_REG((x) > HARDWARE_ERROR_CORRECTABLE ? \
> +								(base) + _SOC_LERRUNCSTS : \
> +								(base) + _SOC_LERRCORSTS)
> +
> +#define SOC_LOCAL_ERR_STAT_MASTER_REG(base, x)		XE_REG((x) > HARDWARE_ERROR_CORRECTABLE ? \
> +								(base) + _SOC_LERRUNCSTS : \
> +								(base) + _SOC_LERRCORSTS)
> +#define _SOC_GSYSEVTCTL		        0x000264
> +
> +#define SOC_GSYSEVTCTL_REG(base, slave_base, x)		XE_REG(_PICK_EVEN((x), \
> +								(base) + _SOC_GSYSEVTCTL, \
> +								slave_base + _SOC_GSYSEVTCTL))
> +#define _SOC_GCOERRSTS		        0x000200
> +#define _SOC_GNFERRSTS		        0x000210
> +#define _SOC_GFAERRSTS		        0x000220
> +#define SOC_GLOBAL_ERR_STAT_SLAVE_REG(base, x)		XE_REG(_PICK_EVEN((x), \
> +								(base) + _SOC_GCOERRSTS, \
> +								(base) + _SOC_GNFERRSTS))
> +
> +#define SOC_GLOBAL_ERR_STAT_MASTER_REG(base, x)		XE_REG(_PICK_EVEN((x), \
> +								(base) + _SOC_GCOERRSTS, \
> +								(base) + _SOC_GNFERRSTS))
> +
>  #endif
> diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
> index 76ae12df013c..fa05bad5e684 100644
> --- a/drivers/gpu/drm/xe/xe_hw_error.c
> +++ b/drivers/gpu/drm/xe/xe_hw_error.c
> @@ -207,6 +207,75 @@ static const struct err_msg_cntr_pair gsc_correctable_err_reg[] = {
>  	[2 ... 31] = {"Undefined",					XE_GSC_HW_ERR_UNKNOWN_CORR},
>  };
>  
> +static const struct err_msg_cntr_pair soc_mstr_glbl_err_reg_fatal[] = {
> +	[0]         = {"MASTER LOCAL Reported",			XE_SOC_HW_ERR_MSTR_LCL_FATAL},
> +	[1]         = {"SLAVE GLOBAL Reported",			XE_SOC_HW_ERR_SLAVE_GLBL_FATAL},
I don't think we shall count the first 2 bits as they just specify which IEH reported error and not
the error itself.

May be you can introduce an enum XE_HW_ERR_UNSPEC before the max and use it to identify anything
that we do not want to count.
> +	[2]         = {"HBM SS0: Channel0",			XE_SOC_HW_ERR_HBM0_CHNL0_FATAL},
> +	[3]         = {"HBM SS0: Channel1",			XE_SOC_HW_ERR_HBM0_CHNL1_FATAL},
> +	[4]         = {"HBM SS0: Channel2",			XE_SOC_HW_ERR_HBM0_CHNL2_FATAL},
> +	[5]         = {"HBM SS0: Channel3",			XE_SOC_HW_ERR_HBM0_CHNL3_FATAL},
> +	[6]         = {"HBM SS0: Channel4",			XE_SOC_HW_ERR_HBM0_CHNL4_FATAL},
> +	[7]         = {"HBM SS0: Channel5",			XE_SOC_HW_ERR_HBM0_CHNL5_FATAL},
> +	[8]         = {"HBM SS0: Channel6",                     XE_SOC_HW_ERR_HBM0_CHNL6_FATAL},
> +	[9]         = {"HBM SS0: Channel7",                     XE_SOC_HW_ERR_HBM0_CHNL7_FATAL},
> +	[10]        = {"HBM SS1: Channel0",                     XE_SOC_HW_ERR_HBM1_CHNL0_FATAL},
> +	[11]        = {"HBM SS1: Channel1",                     XE_SOC_HW_ERR_HBM1_CHNL1_FATAL},
> +	[12]        = {"HBM SS1: Channel2",                     XE_SOC_HW_ERR_HBM1_CHNL2_FATAL},
> +	[13]        = {"HBM SS1: Channel3",                     XE_SOC_HW_ERR_HBM1_CHNL3_FATAL},
> +	[14]        = {"HBM SS1: Channel4",                     XE_SOC_HW_ERR_HBM1_CHNL4_FATAL},
> +	[15]        = {"HBM SS1: Channel5",                     XE_SOC_HW_ERR_HBM1_CHNL5_FATAL},
> +	[16]        = {"HBM SS1: Channel6",                     XE_SOC_HW_ERR_HBM1_CHNL6_FATAL},
> +	[17]        = {"HBM SS1: Channel7",                     XE_SOC_HW_ERR_HBM1_CHNL7_FATAL},
> +	[18]	    = {"PUNIT",					XE_SOC_HW_ERR_PUNIT_FATAL},
> +	[19 ... 31] = {"Undefined",				XE_SOC_HW_ERR_UNKNOWN_FATAL},
> +};
> +
> +static const struct err_msg_cntr_pair soc_slave_glbl_err_reg_fatal[] = {
> +	[0]         = {"SLAVE LOCAL Reported",			XE_SOC_HW_ERR_SLAVE_LCL_FATAL},

same here as above.

> +	[1]         = {"HBM SS2: Channel0",			XE_SOC_HW_ERR_HBM2_CHNL0_FATAL},
> +	[2]         = {"HBM SS2: Channel1",			XE_SOC_HW_ERR_HBM2_CHNL1_FATAL},
> +	[3]         = {"HBM SS2: Channel2",			XE_SOC_HW_ERR_HBM2_CHNL2_FATAL},
> +	[4]         = {"HBM SS2: Channel3",			XE_SOC_HW_ERR_HBM2_CHNL3_FATAL},
> +	[5]         = {"HBM SS2: Channel4",			XE_SOC_HW_ERR_HBM2_CHNL4_FATAL},
> +	[6]         = {"HBM SS2: Channel5",			XE_SOC_HW_ERR_HBM2_CHNL5_FATAL},
> +	[7]         = {"HBM SS2: Channel6",                     XE_SOC_HW_ERR_HBM2_CHNL6_FATAL},
> +	[8]         = {"HBM SS2: Channel7",                     XE_SOC_HW_ERR_HBM2_CHNL7_FATAL},
> +	[9]         = {"HBM SS3: Channel0",                     XE_SOC_HW_ERR_HBM3_CHNL0_FATAL},
> +	[10]        = {"HBM SS3: Channel1",                     XE_SOC_HW_ERR_HBM3_CHNL1_FATAL},
> +	[11]        = {"HBM SS3: Channel2",                     XE_SOC_HW_ERR_HBM3_CHNL2_FATAL},
> +	[12]        = {"HBM SS3: Channel3",                     XE_SOC_HW_ERR_HBM3_CHNL3_FATAL},
> +	[13]        = {"HBM SS3: Channel4",                     XE_SOC_HW_ERR_HBM3_CHNL4_FATAL},
> +	[14]        = {"HBM SS3: Channel5",                     XE_SOC_HW_ERR_HBM3_CHNL5_FATAL},
> +	[15]        = {"HBM SS3: Channel6",                     XE_SOC_HW_ERR_HBM3_CHNL6_FATAL},
> +	[16]        = {"HBM SS3: Channel7",                     XE_SOC_HW_ERR_HBM3_CHNL7_FATAL},
> +	[18]	    = {"ANR MDFI",				XE_SOC_HW_ERR_ANR_MDFI_FATAL},
> +	[17]        = {"Undefined",                             XE_SOC_HW_ERR_UNKNOWN_FATAL},
> +	[19 ... 31] = {"Undefined",				XE_SOC_HW_ERR_UNKNOWN_FATAL},
> +};
> +
> +static const struct err_msg_cntr_pair soc_slave_lcl_err_reg_fatal[] = {
> +	[0]         = {"Local IEH Internal: Malformed PCIe AER",     XE_SOC_HW_ERR_PCIE_AER_FATAL},
> +	[1]         = {"Local IEH Internal: Malformed PCIe ERR",     XE_SOC_HW_ERR_PCIE_ERR_FATAL},
> +	[2]         = {"Local IEH Internal: UR CONDITIONS IN IEH",   XE_SOC_HW_ERR_UR_COND_FATAL},
> +	[3]         = {"Local IEH Internal: FROM SERR SOURCES",      XE_SOC_HW_ERR_SERR_SRCS_FATAL},
> +	[4 ... 31]  = {"Undefined",				     XE_SOC_HW_ERR_UNKNOWN_FATAL},
> +};
> +
> +static const struct err_msg_cntr_pair soc_mstr_lcl_err_reg_fatal[] = {
> +	[0 ... 3]   = {"Undefined",				XE_SOC_HW_ERR_UNKNOWN_FATAL},
> +	[4]         = {"Base Die MDFI T2T",			XE_SOC_HW_ERR_MDFI_T2T_FATAL},
> +	[5]         = {"Undefined",				XE_SOC_HW_ERR_UNKNOWN_FATAL},
> +	[6]         = {"Base Die MDFI T2C",			XE_SOC_HW_ERR_MDFI_T2C_FATAL},
> +	[7]         = {"Undefined",				XE_SOC_HW_ERR_UNKNOWN_FATAL},
> +	[8]         = {"Invalid CSC PSF Command Parity",	XE_SOC_HW_ERR_CSC_PSF_CMD_FATAL},
> +	[9]         = {"Invalid CSC PSF Unexpected Completion",	XE_SOC_HW_ERR_CSC_PSF_CMP_FATAL},
> +	[10]        = {"Invalid CSC PSF Unsupported Request",	XE_SOC_HW_ERR_CSC_PSF_REQ_FATAL},
> +	[11]        = {"Invalid PCIe PSF Command Parity",	XE_SOC_HW_ERR_PCIE_PSF_CMD_FATAL},
> +	[12]        = {"PCIe PSF Unexpected Completion",	XE_SOC_HW_ERR_PCIE_PSF_CMP_FATAL},
> +	[13]        = {"PCIe PSF Unsupported Request",		XE_SOC_HW_ERR_PCIE_PSF_REQ_FATAL},
> +	[14 ... 31] = {"Undefined",				XE_SOC_HW_ERR_UNKNOWN_FATAL},
> +};
> +
>  static void xe_assign_hw_err_regs(struct xe_device *xe)
>  {
>  	const struct err_msg_cntr_pair **dev_err_stat = xe->hw_err_regs.dev_err_stat;
> @@ -451,6 +520,104 @@ xe_gsc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
>  	xe_mmio_write32(mmio, GSC_HEC_ERR_STAT_REG(base, hw_err), errsrc);
>  }
>  
> +static void
> +xe_soc_log_err_update_cntr(struct xe_tile *tile,
> +			   u32 errbit, const struct err_msg_cntr_pair *reg_info)
> +{
> +	const char *errmsg;
> +	u32 indx;
> +
> +	errmsg = reg_info[errbit].errmsg;
> +	indx = reg_info[errbit].cntr_indx;
> +
> +	drm_err_ratelimited(&tile_to_xe(tile)->drm, HW_ERR
> +			    "Tile%d %s SOC FATAL error, bit[%d] is set\n",
> +			    tile->id, errmsg, errbit);
> +	tile->errors.count[indx]++;
> +}
> +
> +static void
> +xe_soc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
> +{
> +	unsigned long mst_glb_errstat, slv_glb_errstat, lcl_errstat;
> +	u32 errbit, base, slave_base;
> +	int i;
> +	struct xe_gt *gt = tile->primary_gt;
> +
> +	lockdep_assert_held(&tile_to_xe(tile)->irq.lock);
> +
> +	if ((tile_to_xe(tile)->info.platform != XE_PVC) && hw_err != HARDWARE_ERROR_FATAL)
> +		return;
> +
> +	base = SOC_PVC_BASE;
> +	slave_base = SOC_PVC_SLAVE_BASE;
> +
> +	/*
> +	 * Mask error type in GSYSEVTCTL so that no new errors of the type
> +	 * will be reported. Read the master global IEH error register if
> +	 * BIT 1 is set then process the slave IEH first. If BIT 0 in
> +	 * global error register is set then process the corresponding
> +	 * Local error registers
> +	 */
> +	for (i = 0; i < PVC_NUM_IEH; i++)

PVC_NUM_IEH is defined as 1 so this will not process IEH1,
check below.
> +		xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base, i), ~REG_BIT(hw_err));
> +
> +	mst_glb_errstat = xe_mmio_read32(gt, SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err));
> +	drm_info(&tile_to_xe(tile)->drm, HW_ERR
> +		 "Tile%d SOC_GLOBAL_ERR_STAT_MASTER_REG_FATAL:0x%08lx\n",
> +		 tile->id, mst_glb_errstat);
> +
> +	if (mst_glb_errstat & REG_BIT(SOC_SLAVE_IEH)) {
> +		slv_glb_errstat = xe_mmio_read32(gt,
> +						 SOC_GLOBAL_ERR_STAT_SLAVE_REG(slave_base, hw_err));
> +		 drm_info(&tile_to_xe(tile)->drm, HW_ERR
> +			  "Tile%d SOC_GLOBAL_ERR_STAT_SLAVE_REG_FATAL:0x%08lx\n",
> +			  tile->id, slv_glb_errstat);
> +
> +		if (slv_glb_errstat & REG_BIT(SOC_IEH1_LOCAL_ERR_STATUS)) {
> +			lcl_errstat = xe_mmio_read32(gt, SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base,
> +										      hw_err));
> +			 drm_info(&tile_to_xe(tile)->drm, HW_ERR
> +				  "Tile%d SOC_LOCAL_ERR_STAT_SLAVE_REG_FATAL:0x%08lx\n",
> +				  tile->id, lcl_errstat);
> +
> +			for_each_set_bit(errbit, &lcl_errstat, 32)
> +				xe_soc_log_err_update_cntr(tile, errbit,
> +							   soc_slave_lcl_err_reg_fatal);
> +
> +			xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
> +					lcl_errstat);
> +		}
> +
> +		for_each_set_bit(errbit, &slv_glb_errstat, 32)
> +			xe_soc_log_err_update_cntr(tile, errbit, soc_slave_glbl_err_reg_fatal);
> +
> +		xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
> +				slv_glb_errstat);
> +	}
> +
> +	if (mst_glb_errstat & REG_BIT(SOC_IEH0_LOCAL_ERR_STATUS)) {
> +		lcl_errstat = xe_mmio_read32(gt, SOC_LOCAL_ERR_STAT_MASTER_REG(base, hw_err));
> +		drm_info(&tile_to_xe(tile)->drm, HW_ERR "SOC_LOCAL_ERR_STAT_MASTER_REG_FATAL:0x%08lx\n",
> +			 lcl_errstat);
> +
> +		for_each_set_bit(errbit, &lcl_errstat, 32)
> +			xe_soc_log_err_update_cntr(tile, errbit, soc_mstr_lcl_err_reg_fatal);
> +
> +		xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_MASTER_REG(base, hw_err), lcl_errstat);
> +	}
> +
> +	for_each_set_bit(errbit, &mst_glb_errstat, 32)
> +		xe_soc_log_err_update_cntr(tile, errbit, soc_mstr_glbl_err_reg_fatal);
> +
> +	xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err),
> +			mst_glb_errstat);
> +
> +	for (i = 0; i < PVC_NUM_IEH; i++)

same here

> +		xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base, i),
> +				(HARDWARE_ERROR_MAX << 1) + 1);
> +}
> +
>  static void
>  xe_hw_error_source_handler(struct xe_tile *tile, const enum hardware_error hw_err)
>  {
> @@ -498,6 +665,9 @@ xe_hw_error_source_handler(struct xe_tile *tile, const enum hardware_error hw_er
>  
>  		if (errbit == 8)
>  			xe_gsc_hw_error_handler(tile, hw_err);
> +
> +		if (errbit == 16)

Please define the bits along with respective register and use here.
> +			xe_soc_hw_error_handler(tile, hw_err);
>  	}
>  
>  	xe_mmio_write32(mmio, DEV_ERR_STAT_REG(hw_err), errsrc);
> diff --git a/drivers/gpu/drm/xe/xe_hw_error.h b/drivers/gpu/drm/xe/xe_hw_error.h
> index ee7705b3343b..05838e082abd 100644
> --- a/drivers/gpu/drm/xe/xe_hw_error.h
> +++ b/drivers/gpu/drm/xe/xe_hw_error.h
> @@ -65,6 +65,56 @@ enum xe_tile_hw_errors {
>  	XE_GSC_HW_ERR_SELF_MBIST_UNCOR,
>  	XE_GSC_HW_ERR_AON_RF_PARITY_UNCOR,
>  	XE_GSC_HW_ERR_UNKNOWN_UNCOR,
> +	XE_SOC_HW_ERR_MSTR_LCL_FATAL,
> +	XE_SOC_HW_ERR_SLAVE_GLBL_FATAL,
> +	XE_SOC_HW_ERR_HBM0_CHNL0_FATAL,
> +	XE_SOC_HW_ERR_HBM0_CHNL1_FATAL,
> +	XE_SOC_HW_ERR_HBM0_CHNL2_FATAL,
> +	XE_SOC_HW_ERR_HBM0_CHNL3_FATAL,
> +	XE_SOC_HW_ERR_HBM0_CHNL4_FATAL,
> +	XE_SOC_HW_ERR_HBM0_CHNL5_FATAL,
> +	XE_SOC_HW_ERR_HBM0_CHNL6_FATAL,
> +	XE_SOC_HW_ERR_HBM0_CHNL7_FATAL,
> +	XE_SOC_HW_ERR_HBM1_CHNL0_FATAL,
> +	XE_SOC_HW_ERR_HBM1_CHNL1_FATAL,
> +	XE_SOC_HW_ERR_HBM1_CHNL2_FATAL,
> +	XE_SOC_HW_ERR_HBM1_CHNL3_FATAL,
> +	XE_SOC_HW_ERR_HBM1_CHNL4_FATAL,
> +	XE_SOC_HW_ERR_HBM1_CHNL5_FATAL,
> +	XE_SOC_HW_ERR_HBM1_CHNL6_FATAL,
> +	XE_SOC_HW_ERR_HBM1_CHNL7_FATAL,
> +	XE_SOC_HW_ERR_PUNIT_FATAL,
> +	XE_SOC_HW_ERR_UNKNOWN_FATAL,
> +	XE_SOC_HW_ERR_SLAVE_LCL_FATAL,
> +	XE_SOC_HW_ERR_HBM2_CHNL0_FATAL,
> +	XE_SOC_HW_ERR_HBM2_CHNL1_FATAL,
> +	XE_SOC_HW_ERR_HBM2_CHNL2_FATAL,
> +	XE_SOC_HW_ERR_HBM2_CHNL3_FATAL,
> +	XE_SOC_HW_ERR_HBM2_CHNL4_FATAL,
> +	XE_SOC_HW_ERR_HBM2_CHNL5_FATAL,
> +	XE_SOC_HW_ERR_HBM2_CHNL6_FATAL,
> +	XE_SOC_HW_ERR_HBM2_CHNL7_FATAL,
> +	XE_SOC_HW_ERR_HBM3_CHNL0_FATAL,
> +	XE_SOC_HW_ERR_HBM3_CHNL1_FATAL,
> +	XE_SOC_HW_ERR_HBM3_CHNL2_FATAL,
> +	XE_SOC_HW_ERR_HBM3_CHNL3_FATAL,
> +	XE_SOC_HW_ERR_HBM3_CHNL4_FATAL,
> +	XE_SOC_HW_ERR_HBM3_CHNL5_FATAL,
> +	XE_SOC_HW_ERR_HBM3_CHNL6_FATAL,
> +	XE_SOC_HW_ERR_HBM3_CHNL7_FATAL,
> +	XE_SOC_HW_ERR_ANR_MDFI_FATAL,
> +	XE_SOC_HW_ERR_PCIE_AER_FATAL,
> +	XE_SOC_HW_ERR_PCIE_ERR_FATAL,
> +	XE_SOC_HW_ERR_UR_COND_FATAL,
> +	XE_SOC_HW_ERR_SERR_SRCS_FATAL,
> +	XE_SOC_HW_ERR_MDFI_T2T_FATAL,
> +	XE_SOC_HW_ERR_MDFI_T2C_FATAL,
> +	XE_SOC_HW_ERR_CSC_PSF_CMD_FATAL,
> +	XE_SOC_HW_ERR_CSC_PSF_CMP_FATAL,
> +	XE_SOC_HW_ERR_CSC_PSF_REQ_FATAL,
> +	XE_SOC_HW_ERR_PCIE_PSF_CMD_FATAL,
> +	XE_SOC_HW_ERR_PCIE_PSF_CMP_FATAL,
> +	XE_SOC_HW_ERR_PCIE_PSF_REQ_FATAL,
we have convention in naming, it shall be source_typeoferror_errorname
this we shall follow everywhere even when we expose these counter to userspace.

eg: XE_HW_ERR_SOC_FATAL_CSC_PSF_CMD


>  	XE_TILE_HW_ERROR_MAX,
>  };
>  
> @@ -109,8 +159,12 @@ enum xe_gt_hw_errors {
>  	XE_GT_HW_ERROR_MAX,
>  };
>  
> -#define ERR_STAT_GT_COR_VCTR_LEN (4)
> -#define ERR_STAT_GT_FATAL_VCTR_LEN (8)
> +#define ERR_STAT_GT_COR_VCTR_LEN	(4)
> +#define ERR_STAT_GT_FATAL_VCTR_LEN	(8)
> +#define PVC_NUM_IEH			(1)

ideally this shall be defined with 2, as we have 2 IEHs

you can define something like:

enum xe_soc_num_ieh {
    XE_SOC_MASTER_IEH = 0,
    XE_SOC_SLAVE_IEH,
    XE_SOC_NUM_IEH
}
> +#define SOC_SLAVE_IEH                   (1)
> +#define SOC_IEH0_LOCAL_ERR_STATUS       (0)
> +#define SOC_IEH1_LOCAL_ERR_STATUS       (0)
there ERR_STATUS be better defined with registers as
>  
>  struct err_msg_cntr_pair {
>  	const char *errmsg;
Thanks,
Aravind.

Re: [Intel-xe] [PATCH 07/11] drm/xe: Support SOC FATAL error handling for PVC.

[Ghimiray, Himal Prasad]

On 09-10-2023 15:22, Aravind Iddamsetty wrote:
> On 27/09/23 17:16, Himal Prasad Ghimiray wrote:
>> Report the SOC fatal hardware error and update the counters which will
>> increment incase of error.
>>
>> Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
>> ---
>>   drivers/gpu/drm/xe/regs/xe_tile_error_regs.h |  28 +++
>>   drivers/gpu/drm/xe/xe_hw_error.c             | 170 +++++++++++++++++++
>>   drivers/gpu/drm/xe/xe_hw_error.h             |  58 ++++++-
>>   3 files changed, 254 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
>> index fa16eaf9436b..04701c62f0d9 100644
>> --- a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
>> +++ b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
>> @@ -20,4 +20,32 @@
>>   #define GSC_HEC_ERR_STAT_REG(base, x)                  XE_REG(_PICK_EVEN((x), \
>>   								(base) + _GSC_HEC_CORR_ERR_STATUS, \
>>   								(base) + _GSC_HEC_UNCOR_ERR_STATUS))
>> +#define SOC_PVC_BASE	               0x00282000
>> +#define SOC_PVC_SLAVE_BASE             0x00283000
> why do we need to prepend the register defines with 0s ?.
We dont need to. Will fix in next patch.
>
>> +
>> +#define _SOC_LERRCORSTS		       0x000294
>> +#define _SOC_LERRUNCSTS		       0x000280
>> +#define SOC_LOCAL_ERR_STAT_SLAVE_REG(base, x)		XE_REG((x) > HARDWARE_ERROR_CORRECTABLE ? \
>> +								(base) + _SOC_LERRUNCSTS : \
>> +								(base) + _SOC_LERRCORSTS)
>> +
>> +#define SOC_LOCAL_ERR_STAT_MASTER_REG(base, x)		XE_REG((x) > HARDWARE_ERROR_CORRECTABLE ? \
>> +								(base) + _SOC_LERRUNCSTS : \
>> +								(base) + _SOC_LERRCORSTS)
>> +#define _SOC_GSYSEVTCTL		        0x000264
>> +
>> +#define SOC_GSYSEVTCTL_REG(base, slave_base, x)		XE_REG(_PICK_EVEN((x), \
>> +								(base) + _SOC_GSYSEVTCTL, \
>> +								slave_base + _SOC_GSYSEVTCTL))
>> +#define _SOC_GCOERRSTS		        0x000200
>> +#define _SOC_GNFERRSTS		        0x000210
>> +#define _SOC_GFAERRSTS		        0x000220
>> +#define SOC_GLOBAL_ERR_STAT_SLAVE_REG(base, x)		XE_REG(_PICK_EVEN((x), \
>> +								(base) + _SOC_GCOERRSTS, \
>> +								(base) + _SOC_GNFERRSTS))
>> +
>> +#define SOC_GLOBAL_ERR_STAT_MASTER_REG(base, x)		XE_REG(_PICK_EVEN((x), \
>> +								(base) + _SOC_GCOERRSTS, \
>> +								(base) + _SOC_GNFERRSTS))
>> +
>>   #endif
>> diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
>> index 76ae12df013c..fa05bad5e684 100644
>> --- a/drivers/gpu/drm/xe/xe_hw_error.c
>> +++ b/drivers/gpu/drm/xe/xe_hw_error.c
>> @@ -207,6 +207,75 @@ static const struct err_msg_cntr_pair gsc_correctable_err_reg[] = {
>>   	[2 ... 31] = {"Undefined",					XE_GSC_HW_ERR_UNKNOWN_CORR},
>>   };
>>   
>> +static const struct err_msg_cntr_pair soc_mstr_glbl_err_reg_fatal[] = {
>> +	[0]         = {"MASTER LOCAL Reported",			XE_SOC_HW_ERR_MSTR_LCL_FATAL},
>> +	[1]         = {"SLAVE GLOBAL Reported",			XE_SOC_HW_ERR_SLAVE_GLBL_FATAL},
> I don't think we shall count the first 2 bits as they just specify which IEH reported error and not
> the error itself.
>
> May be you can introduce an enum XE_HW_ERR_UNSPEC before the max and use it to identify anything
> that we do not want to count.
Sure. Will address in next patch.
>> +	[2]         = {"HBM SS0: Channel0",			XE_SOC_HW_ERR_HBM0_CHNL0_FATAL},
>> +	[3]         = {"HBM SS0: Channel1",			XE_SOC_HW_ERR_HBM0_CHNL1_FATAL},
>> +	[4]         = {"HBM SS0: Channel2",			XE_SOC_HW_ERR_HBM0_CHNL2_FATAL},
>> +	[5]         = {"HBM SS0: Channel3",			XE_SOC_HW_ERR_HBM0_CHNL3_FATAL},
>> +	[6]         = {"HBM SS0: Channel4",			XE_SOC_HW_ERR_HBM0_CHNL4_FATAL},
>> +	[7]         = {"HBM SS0: Channel5",			XE_SOC_HW_ERR_HBM0_CHNL5_FATAL},
>> +	[8]         = {"HBM SS0: Channel6",                     XE_SOC_HW_ERR_HBM0_CHNL6_FATAL},
>> +	[9]         = {"HBM SS0: Channel7",                     XE_SOC_HW_ERR_HBM0_CHNL7_FATAL},
>> +	[10]        = {"HBM SS1: Channel0",                     XE_SOC_HW_ERR_HBM1_CHNL0_FATAL},
>> +	[11]        = {"HBM SS1: Channel1",                     XE_SOC_HW_ERR_HBM1_CHNL1_FATAL},
>> +	[12]        = {"HBM SS1: Channel2",                     XE_SOC_HW_ERR_HBM1_CHNL2_FATAL},
>> +	[13]        = {"HBM SS1: Channel3",                     XE_SOC_HW_ERR_HBM1_CHNL3_FATAL},
>> +	[14]        = {"HBM SS1: Channel4",                     XE_SOC_HW_ERR_HBM1_CHNL4_FATAL},
>> +	[15]        = {"HBM SS1: Channel5",                     XE_SOC_HW_ERR_HBM1_CHNL5_FATAL},
>> +	[16]        = {"HBM SS1: Channel6",                     XE_SOC_HW_ERR_HBM1_CHNL6_FATAL},
>> +	[17]        = {"HBM SS1: Channel7",                     XE_SOC_HW_ERR_HBM1_CHNL7_FATAL},
>> +	[18]	    = {"PUNIT",					XE_SOC_HW_ERR_PUNIT_FATAL},
>> +	[19 ... 31] = {"Undefined",				XE_SOC_HW_ERR_UNKNOWN_FATAL},
>> +};
>> +
>> +static const struct err_msg_cntr_pair soc_slave_glbl_err_reg_fatal[] = {
>> +	[0]         = {"SLAVE LOCAL Reported",			XE_SOC_HW_ERR_SLAVE_LCL_FATAL},
> same here as above.
>
>> +	[1]         = {"HBM SS2: Channel0",			XE_SOC_HW_ERR_HBM2_CHNL0_FATAL},
>> +	[2]         = {"HBM SS2: Channel1",			XE_SOC_HW_ERR_HBM2_CHNL1_FATAL},
>> +	[3]         = {"HBM SS2: Channel2",			XE_SOC_HW_ERR_HBM2_CHNL2_FATAL},
>> +	[4]         = {"HBM SS2: Channel3",			XE_SOC_HW_ERR_HBM2_CHNL3_FATAL},
>> +	[5]         = {"HBM SS2: Channel4",			XE_SOC_HW_ERR_HBM2_CHNL4_FATAL},
>> +	[6]         = {"HBM SS2: Channel5",			XE_SOC_HW_ERR_HBM2_CHNL5_FATAL},
>> +	[7]         = {"HBM SS2: Channel6",                     XE_SOC_HW_ERR_HBM2_CHNL6_FATAL},
>> +	[8]         = {"HBM SS2: Channel7",                     XE_SOC_HW_ERR_HBM2_CHNL7_FATAL},
>> +	[9]         = {"HBM SS3: Channel0",                     XE_SOC_HW_ERR_HBM3_CHNL0_FATAL},
>> +	[10]        = {"HBM SS3: Channel1",                     XE_SOC_HW_ERR_HBM3_CHNL1_FATAL},
>> +	[11]        = {"HBM SS3: Channel2",                     XE_SOC_HW_ERR_HBM3_CHNL2_FATAL},
>> +	[12]        = {"HBM SS3: Channel3",                     XE_SOC_HW_ERR_HBM3_CHNL3_FATAL},
>> +	[13]        = {"HBM SS3: Channel4",                     XE_SOC_HW_ERR_HBM3_CHNL4_FATAL},
>> +	[14]        = {"HBM SS3: Channel5",                     XE_SOC_HW_ERR_HBM3_CHNL5_FATAL},
>> +	[15]        = {"HBM SS3: Channel6",                     XE_SOC_HW_ERR_HBM3_CHNL6_FATAL},
>> +	[16]        = {"HBM SS3: Channel7",                     XE_SOC_HW_ERR_HBM3_CHNL7_FATAL},
>> +	[18]	    = {"ANR MDFI",				XE_SOC_HW_ERR_ANR_MDFI_FATAL},
>> +	[17]        = {"Undefined",                             XE_SOC_HW_ERR_UNKNOWN_FATAL},
>> +	[19 ... 31] = {"Undefined",				XE_SOC_HW_ERR_UNKNOWN_FATAL},
>> +};
>> +
>> +static const struct err_msg_cntr_pair soc_slave_lcl_err_reg_fatal[] = {
>> +	[0]         = {"Local IEH Internal: Malformed PCIe AER",     XE_SOC_HW_ERR_PCIE_AER_FATAL},
>> +	[1]         = {"Local IEH Internal: Malformed PCIe ERR",     XE_SOC_HW_ERR_PCIE_ERR_FATAL},
>> +	[2]         = {"Local IEH Internal: UR CONDITIONS IN IEH",   XE_SOC_HW_ERR_UR_COND_FATAL},
>> +	[3]         = {"Local IEH Internal: FROM SERR SOURCES",      XE_SOC_HW_ERR_SERR_SRCS_FATAL},
>> +	[4 ... 31]  = {"Undefined",				     XE_SOC_HW_ERR_UNKNOWN_FATAL},
>> +};
>> +
>> +static const struct err_msg_cntr_pair soc_mstr_lcl_err_reg_fatal[] = {
>> +	[0 ... 3]   = {"Undefined",				XE_SOC_HW_ERR_UNKNOWN_FATAL},
>> +	[4]         = {"Base Die MDFI T2T",			XE_SOC_HW_ERR_MDFI_T2T_FATAL},
>> +	[5]         = {"Undefined",				XE_SOC_HW_ERR_UNKNOWN_FATAL},
>> +	[6]         = {"Base Die MDFI T2C",			XE_SOC_HW_ERR_MDFI_T2C_FATAL},
>> +	[7]         = {"Undefined",				XE_SOC_HW_ERR_UNKNOWN_FATAL},
>> +	[8]         = {"Invalid CSC PSF Command Parity",	XE_SOC_HW_ERR_CSC_PSF_CMD_FATAL},
>> +	[9]         = {"Invalid CSC PSF Unexpected Completion",	XE_SOC_HW_ERR_CSC_PSF_CMP_FATAL},
>> +	[10]        = {"Invalid CSC PSF Unsupported Request",	XE_SOC_HW_ERR_CSC_PSF_REQ_FATAL},
>> +	[11]        = {"Invalid PCIe PSF Command Parity",	XE_SOC_HW_ERR_PCIE_PSF_CMD_FATAL},
>> +	[12]        = {"PCIe PSF Unexpected Completion",	XE_SOC_HW_ERR_PCIE_PSF_CMP_FATAL},
>> +	[13]        = {"PCIe PSF Unsupported Request",		XE_SOC_HW_ERR_PCIE_PSF_REQ_FATAL},
>> +	[14 ... 31] = {"Undefined",				XE_SOC_HW_ERR_UNKNOWN_FATAL},
>> +};
>> +
>>   static void xe_assign_hw_err_regs(struct xe_device *xe)
>>   {
>>   	const struct err_msg_cntr_pair **dev_err_stat = xe->hw_err_regs.dev_err_stat;
>> @@ -451,6 +520,104 @@ xe_gsc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
>>   	xe_mmio_write32(mmio, GSC_HEC_ERR_STAT_REG(base, hw_err), errsrc);
>>   }
>>   
>> +static void
>> +xe_soc_log_err_update_cntr(struct xe_tile *tile,
>> +			   u32 errbit, const struct err_msg_cntr_pair *reg_info)
>> +{
>> +	const char *errmsg;
>> +	u32 indx;
>> +
>> +	errmsg = reg_info[errbit].errmsg;
>> +	indx = reg_info[errbit].cntr_indx;
>> +
>> +	drm_err_ratelimited(&tile_to_xe(tile)->drm, HW_ERR
>> +			    "Tile%d %s SOC FATAL error, bit[%d] is set\n",
>> +			    tile->id, errmsg, errbit);
>> +	tile->errors.count[indx]++;
>> +}
>> +
>> +static void
>> +xe_soc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
>> +{
>> +	unsigned long mst_glb_errstat, slv_glb_errstat, lcl_errstat;
>> +	u32 errbit, base, slave_base;
>> +	int i;
>> +	struct xe_gt *gt = tile->primary_gt;
>> +
>> +	lockdep_assert_held(&tile_to_xe(tile)->irq.lock);
>> +
>> +	if ((tile_to_xe(tile)->info.platform != XE_PVC) && hw_err != HARDWARE_ERROR_FATAL)
>> +		return;
>> +
>> +	base = SOC_PVC_BASE;
>> +	slave_base = SOC_PVC_SLAVE_BASE;
>> +
>> +	/*
>> +	 * Mask error type in GSYSEVTCTL so that no new errors of the type
>> +	 * will be reported. Read the master global IEH error register if
>> +	 * BIT 1 is set then process the slave IEH first. If BIT 0 in
>> +	 * global error register is set then process the corresponding
>> +	 * Local error registers
>> +	 */
>> +	for (i = 0; i < PVC_NUM_IEH; i++)
> PVC_NUM_IEH is defined as 1 so this will not process IEH1,
> check below.
Bad miss. Will address in next patch.
>> +		xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base, i), ~REG_BIT(hw_err));
>> +
>> +	mst_glb_errstat = xe_mmio_read32(gt, SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err));
>> +	drm_info(&tile_to_xe(tile)->drm, HW_ERR
>> +		 "Tile%d SOC_GLOBAL_ERR_STAT_MASTER_REG_FATAL:0x%08lx\n",
>> +		 tile->id, mst_glb_errstat);
>> +
>> +	if (mst_glb_errstat & REG_BIT(SOC_SLAVE_IEH)) {
>> +		slv_glb_errstat = xe_mmio_read32(gt,
>> +						 SOC_GLOBAL_ERR_STAT_SLAVE_REG(slave_base, hw_err));
>> +		 drm_info(&tile_to_xe(tile)->drm, HW_ERR
>> +			  "Tile%d SOC_GLOBAL_ERR_STAT_SLAVE_REG_FATAL:0x%08lx\n",
>> +			  tile->id, slv_glb_errstat);
>> +
>> +		if (slv_glb_errstat & REG_BIT(SOC_IEH1_LOCAL_ERR_STATUS)) {
>> +			lcl_errstat = xe_mmio_read32(gt, SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base,
>> +										      hw_err));
>> +			 drm_info(&tile_to_xe(tile)->drm, HW_ERR
>> +				  "Tile%d SOC_LOCAL_ERR_STAT_SLAVE_REG_FATAL:0x%08lx\n",
>> +				  tile->id, lcl_errstat);
>> +
>> +			for_each_set_bit(errbit, &lcl_errstat, 32)
>> +				xe_soc_log_err_update_cntr(tile, errbit,
>> +							   soc_slave_lcl_err_reg_fatal);
>> +
>> +			xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
>> +					lcl_errstat);
>> +		}
>> +
>> +		for_each_set_bit(errbit, &slv_glb_errstat, 32)
>> +			xe_soc_log_err_update_cntr(tile, errbit, soc_slave_glbl_err_reg_fatal);
>> +
>> +		xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
>> +				slv_glb_errstat);
>> +	}
>> +
>> +	if (mst_glb_errstat & REG_BIT(SOC_IEH0_LOCAL_ERR_STATUS)) {
>> +		lcl_errstat = xe_mmio_read32(gt, SOC_LOCAL_ERR_STAT_MASTER_REG(base, hw_err));
>> +		drm_info(&tile_to_xe(tile)->drm, HW_ERR "SOC_LOCAL_ERR_STAT_MASTER_REG_FATAL:0x%08lx\n",
>> +			 lcl_errstat);
>> +
>> +		for_each_set_bit(errbit, &lcl_errstat, 32)
>> +			xe_soc_log_err_update_cntr(tile, errbit, soc_mstr_lcl_err_reg_fatal);
>> +
>> +		xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_MASTER_REG(base, hw_err), lcl_errstat);
>> +	}
>> +
>> +	for_each_set_bit(errbit, &mst_glb_errstat, 32)
>> +		xe_soc_log_err_update_cntr(tile, errbit, soc_mstr_glbl_err_reg_fatal);
>> +
>> +	xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err),
>> +			mst_glb_errstat);
>> +
>> +	for (i = 0; i < PVC_NUM_IEH; i++)
> same here
>
>> +		xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base, i),
>> +				(HARDWARE_ERROR_MAX << 1) + 1);
>> +}
>> +
>>   static void
>>   xe_hw_error_source_handler(struct xe_tile *tile, const enum hardware_error hw_err)
>>   {
>> @@ -498,6 +665,9 @@ xe_hw_error_source_handler(struct xe_tile *tile, const enum hardware_error hw_er
>>   
>>   		if (errbit == 8)
>>   			xe_gsc_hw_error_handler(tile, hw_err);
>> +
>> +		if (errbit == 16)
> Please define the bits along with respective register and use here.
>> +			xe_soc_hw_error_handler(tile, hw_err);
>>   	}
>>   
>>   	xe_mmio_write32(mmio, DEV_ERR_STAT_REG(hw_err), errsrc);
>> diff --git a/drivers/gpu/drm/xe/xe_hw_error.h b/drivers/gpu/drm/xe/xe_hw_error.h
>> index ee7705b3343b..05838e082abd 100644
>> --- a/drivers/gpu/drm/xe/xe_hw_error.h
>> +++ b/drivers/gpu/drm/xe/xe_hw_error.h
>> @@ -65,6 +65,56 @@ enum xe_tile_hw_errors {
>>   	XE_GSC_HW_ERR_SELF_MBIST_UNCOR,
>>   	XE_GSC_HW_ERR_AON_RF_PARITY_UNCOR,
>>   	XE_GSC_HW_ERR_UNKNOWN_UNCOR,
>> +	XE_SOC_HW_ERR_MSTR_LCL_FATAL,
>> +	XE_SOC_HW_ERR_SLAVE_GLBL_FATAL,
>> +	XE_SOC_HW_ERR_HBM0_CHNL0_FATAL,
>> +	XE_SOC_HW_ERR_HBM0_CHNL1_FATAL,
>> +	XE_SOC_HW_ERR_HBM0_CHNL2_FATAL,
>> +	XE_SOC_HW_ERR_HBM0_CHNL3_FATAL,
>> +	XE_SOC_HW_ERR_HBM0_CHNL4_FATAL,
>> +	XE_SOC_HW_ERR_HBM0_CHNL5_FATAL,
>> +	XE_SOC_HW_ERR_HBM0_CHNL6_FATAL,
>> +	XE_SOC_HW_ERR_HBM0_CHNL7_FATAL,
>> +	XE_SOC_HW_ERR_HBM1_CHNL0_FATAL,
>> +	XE_SOC_HW_ERR_HBM1_CHNL1_FATAL,
>> +	XE_SOC_HW_ERR_HBM1_CHNL2_FATAL,
>> +	XE_SOC_HW_ERR_HBM1_CHNL3_FATAL,
>> +	XE_SOC_HW_ERR_HBM1_CHNL4_FATAL,
>> +	XE_SOC_HW_ERR_HBM1_CHNL5_FATAL,
>> +	XE_SOC_HW_ERR_HBM1_CHNL6_FATAL,
>> +	XE_SOC_HW_ERR_HBM1_CHNL7_FATAL,
>> +	XE_SOC_HW_ERR_PUNIT_FATAL,
>> +	XE_SOC_HW_ERR_UNKNOWN_FATAL,
>> +	XE_SOC_HW_ERR_SLAVE_LCL_FATAL,
>> +	XE_SOC_HW_ERR_HBM2_CHNL0_FATAL,
>> +	XE_SOC_HW_ERR_HBM2_CHNL1_FATAL,
>> +	XE_SOC_HW_ERR_HBM2_CHNL2_FATAL,
>> +	XE_SOC_HW_ERR_HBM2_CHNL3_FATAL,
>> +	XE_SOC_HW_ERR_HBM2_CHNL4_FATAL,
>> +	XE_SOC_HW_ERR_HBM2_CHNL5_FATAL,
>> +	XE_SOC_HW_ERR_HBM2_CHNL6_FATAL,
>> +	XE_SOC_HW_ERR_HBM2_CHNL7_FATAL,
>> +	XE_SOC_HW_ERR_HBM3_CHNL0_FATAL,
>> +	XE_SOC_HW_ERR_HBM3_CHNL1_FATAL,
>> +	XE_SOC_HW_ERR_HBM3_CHNL2_FATAL,
>> +	XE_SOC_HW_ERR_HBM3_CHNL3_FATAL,
>> +	XE_SOC_HW_ERR_HBM3_CHNL4_FATAL,
>> +	XE_SOC_HW_ERR_HBM3_CHNL5_FATAL,
>> +	XE_SOC_HW_ERR_HBM3_CHNL6_FATAL,
>> +	XE_SOC_HW_ERR_HBM3_CHNL7_FATAL,
>> +	XE_SOC_HW_ERR_ANR_MDFI_FATAL,
>> +	XE_SOC_HW_ERR_PCIE_AER_FATAL,
>> +	XE_SOC_HW_ERR_PCIE_ERR_FATAL,
>> +	XE_SOC_HW_ERR_UR_COND_FATAL,
>> +	XE_SOC_HW_ERR_SERR_SRCS_FATAL,
>> +	XE_SOC_HW_ERR_MDFI_T2T_FATAL,
>> +	XE_SOC_HW_ERR_MDFI_T2C_FATAL,
>> +	XE_SOC_HW_ERR_CSC_PSF_CMD_FATAL,
>> +	XE_SOC_HW_ERR_CSC_PSF_CMP_FATAL,
>> +	XE_SOC_HW_ERR_CSC_PSF_REQ_FATAL,
>> +	XE_SOC_HW_ERR_PCIE_PSF_CMD_FATAL,
>> +	XE_SOC_HW_ERR_PCIE_PSF_CMP_FATAL,
>> +	XE_SOC_HW_ERR_PCIE_PSF_REQ_FATAL,
> we have convention in naming, it shall be source_typeoferror_errorname
> this we shall follow everywhere even when we expose these counter to userspace.
>
> eg: XE_HW_ERR_SOC_FATAL_CSC_PSF_CMD
>
Ok. Makes sense will update in next patch.
>>   	XE_TILE_HW_ERROR_MAX,
>>   };
>>   
>> @@ -109,8 +159,12 @@ enum xe_gt_hw_errors {
>>   	XE_GT_HW_ERROR_MAX,
>>   };
>>   
>> -#define ERR_STAT_GT_COR_VCTR_LEN (4)
>> -#define ERR_STAT_GT_FATAL_VCTR_LEN (8)
>> +#define ERR_STAT_GT_COR_VCTR_LEN	(4)
>> +#define ERR_STAT_GT_FATAL_VCTR_LEN	(8)
>> +#define PVC_NUM_IEH			(1)
> ideally this shall be defined with 2, as we have 2 IEHs
>
> you can define something like:
>
> enum xe_soc_num_ieh {
>      XE_SOC_MASTER_IEH = 0,
>      XE_SOC_SLAVE_IEH,
>      XE_SOC_NUM_IEH
> }
Ok.
>> +#define SOC_SLAVE_IEH                   (1)
>> +#define SOC_IEH0_LOCAL_ERR_STATUS       (0)
>> +#define SOC_IEH1_LOCAL_ERR_STATUS       (0)
> there ERR_STATUS be better defined with registers as
Sure.
>>   
>>   struct err_msg_cntr_pair {
>>   	const char *errmsg;
> Thanks,
> Aravind.

[Intel-xe] [PATCH 08/11] drm/xe: Support SOC NONFATAL error handling for PVC.

[Himal Prasad Ghimiray]

Report the SOC nonfatal hardware error and update the counters which
will increment incase of error.

Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
 drivers/gpu/drm/xe/xe_hw_error.c | 118 ++++++++++++++++++++++++++-----
 drivers/gpu/drm/xe/xe_hw_error.h |  42 +++++++++++
 2 files changed, 143 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
index fa05bad5e684..aeece9e705dc 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.c
+++ b/drivers/gpu/drm/xe/xe_hw_error.c
@@ -276,6 +276,67 @@ static const struct err_msg_cntr_pair soc_mstr_lcl_err_reg_fatal[] = {
 	[14 ... 31] = {"Undefined",				XE_SOC_HW_ERR_UNKNOWN_FATAL},
 };
 
+static const struct err_msg_cntr_pair soc_mstr_glbl_err_reg_nonfatal[] = {
+	[0]         = {"MASTER LOCAL Reported",			XE_SOC_HW_ERR_MSTR_LCL_NONFATAL},
+	[1]         = {"SLAVE GLOBAL Reported",			XE_SOC_HW_ERR_SLAVE_GLBL_NONFATAL},
+	[2]         = {"HBM SS0: Channel0",			XE_SOC_HW_ERR_HBM0_CHNL0_NONFATAL},
+	[3]         = {"HBM SS0: Channel1",			XE_SOC_HW_ERR_HBM0_CHNL1_NONFATAL},
+	[4]         = {"HBM SS0: Channel2",			XE_SOC_HW_ERR_HBM0_CHNL2_NONFATAL},
+	[5]         = {"HBM SS0: Channel3",			XE_SOC_HW_ERR_HBM0_CHNL3_NONFATAL},
+	[6]         = {"HBM SS0: Channel4",			XE_SOC_HW_ERR_HBM0_CHNL4_NONFATAL},
+	[7]         = {"HBM SS0: Channel5",			XE_SOC_HW_ERR_HBM0_CHNL5_NONFATAL},
+	[8]         = {"HBM SS0: Channel6",                     XE_SOC_HW_ERR_HBM0_CHNL6_NONFATAL},
+	[9]         = {"HBM SS0: Channel7",                     XE_SOC_HW_ERR_HBM0_CHNL7_NONFATAL},
+	[10]        = {"HBM SS1: Channel0",                     XE_SOC_HW_ERR_HBM1_CHNL0_NONFATAL},
+	[11]        = {"HBM SS1: Channel1",                     XE_SOC_HW_ERR_HBM1_CHNL1_NONFATAL},
+	[12]        = {"HBM SS1: Channel2",                     XE_SOC_HW_ERR_HBM1_CHNL2_NONFATAL},
+	[13]        = {"HBM SS1: Channel3",                     XE_SOC_HW_ERR_HBM1_CHNL3_NONFATAL},
+	[14]        = {"HBM SS1: Channel4",                     XE_SOC_HW_ERR_HBM1_CHNL4_NONFATAL},
+	[15]        = {"HBM SS1: Channel5",                     XE_SOC_HW_ERR_HBM1_CHNL5_NONFATAL},
+	[16]        = {"HBM SS1: Channel6",                     XE_SOC_HW_ERR_HBM1_CHNL6_NONFATAL},
+	[17]        = {"HBM SS1: Channel7",                     XE_SOC_HW_ERR_HBM1_CHNL7_NONFATAL},
+	[18 ... 31] = {"Undefined",				XE_SOC_HW_ERR_UNKNOWN_FATAL},
+};
+
+static const struct err_msg_cntr_pair soc_slave_glbl_err_reg_nonfatal[] = {
+	[0]         = {"SLAVE LOCAL Reported",			XE_SOC_HW_ERR_SLAVE_LCL_NONFATAL},
+	[1]         = {"HBM SS2: Channel0",			XE_SOC_HW_ERR_HBM2_CHNL0_NONFATAL},
+	[2]         = {"HBM SS2: Channel1",			XE_SOC_HW_ERR_HBM2_CHNL1_NONFATAL},
+	[3]         = {"HBM SS2: Channel2",			XE_SOC_HW_ERR_HBM2_CHNL2_NONFATAL},
+	[4]         = {"HBM SS2: Channel3",			XE_SOC_HW_ERR_HBM2_CHNL3_NONFATAL},
+	[5]         = {"HBM SS2: Channel4",			XE_SOC_HW_ERR_HBM2_CHNL4_NONFATAL},
+	[6]         = {"HBM SS2: Channel5",			XE_SOC_HW_ERR_HBM2_CHNL5_NONFATAL},
+	[7]         = {"HBM SS2: Channel6",                     XE_SOC_HW_ERR_HBM2_CHNL6_NONFATAL},
+	[8]         = {"HBM SS2: Channel7",                     XE_SOC_HW_ERR_HBM2_CHNL7_NONFATAL},
+	[9]         = {"HBM SS3: Channel0",                     XE_SOC_HW_ERR_HBM3_CHNL0_NONFATAL},
+	[10]        = {"HBM SS3: Channel1",                     XE_SOC_HW_ERR_HBM3_CHNL1_NONFATAL},
+	[11]        = {"HBM SS3: Channel2",                     XE_SOC_HW_ERR_HBM3_CHNL2_NONFATAL},
+	[12]        = {"HBM SS3: Channel3",                     XE_SOC_HW_ERR_HBM3_CHNL3_NONFATAL},
+	[13]        = {"HBM SS3: Channel4",                     XE_SOC_HW_ERR_HBM3_CHNL4_NONFATAL},
+	[14]        = {"HBM SS3: Channel5",                     XE_SOC_HW_ERR_HBM3_CHNL5_NONFATAL},
+	[15]        = {"HBM SS3: Channel6",                     XE_SOC_HW_ERR_HBM3_CHNL6_NONFATAL},
+	[16]        = {"HBM SS3: Channel7",                     XE_SOC_HW_ERR_HBM3_CHNL7_NONFATAL},
+	[18]	    = {"ANR MDFI",				XE_SOC_HW_ERR_ANR_MDFI_NONFATAL},
+	[17]        = {"Undefined",                             XE_SOC_HW_ERR_UNKNOWN_NONFATAL},
+	[19 ... 31] = {"Undefined",				XE_SOC_HW_ERR_UNKNOWN_FATAL},
+};
+
+static const struct err_msg_cntr_pair soc_slave_lcl_err_reg_nonfatal[] = {
+	[0 ... 31]  = {"Undefined",			XE_SOC_HW_ERR_UNKNOWN_NONFATAL},
+};
+
+static const struct err_msg_cntr_pair soc_mstr_lcl_err_reg_nonfatal[] = {
+	[0 ... 3]   = {"Undefined",				XE_SOC_HW_ERR_UNKNOWN_NONFATAL},
+	[4]         = {"Base Die MDFI T2T",			XE_SOC_HW_ERR_MDFI_T2T_NONFATAL},
+	[5]         = {"Undefined",				XE_SOC_HW_ERR_UNKNOWN_NONFATAL},
+	[6]         = {"Base Die MDFI T2C",			XE_SOC_HW_ERR_MDFI_T2C_NONFATAL},
+	[7]         = {"Undefined",				XE_SOC_HW_ERR_UNKNOWN_NONFATAL},
+	[8]         = {"Invalid CSC PSF Command Parity",	XE_SOC_HW_ERR_CSC_PSF_CMD_NONFATAL},
+	[9]         = {"Invalid CSC PSF Unexpected Completion",	XE_SOC_HW_ERR_CSC_PSF_CMP_NONFATAL},
+	[10]        = {"Invalid CSC PSF Unsupported Request",	XE_SOC_HW_ERR_CSC_PSF_REQ_NONFATAL},
+	[11 ... 31] = {"Undefined",				XE_SOC_HW_ERR_UNKNOWN_FATAL},
+};
+
 static void xe_assign_hw_err_regs(struct xe_device *xe)
 {
 	const struct err_msg_cntr_pair **dev_err_stat = xe->hw_err_regs.dev_err_stat;
@@ -521,18 +582,20 @@ xe_gsc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
 }
 
 static void
-xe_soc_log_err_update_cntr(struct xe_tile *tile,
+xe_soc_log_err_update_cntr(struct xe_tile *tile, const enum hardware_error hw_err,
 			   u32 errbit, const struct err_msg_cntr_pair *reg_info)
 {
 	const char *errmsg;
 	u32 indx;
 
+	const char *hwerr_to_str = hardware_error_type_to_str(hw_err);
+
 	errmsg = reg_info[errbit].errmsg;
 	indx = reg_info[errbit].cntr_indx;
 
 	drm_err_ratelimited(&tile_to_xe(tile)->drm, HW_ERR
-			    "Tile%d %s SOC FATAL error, bit[%d] is set\n",
-			    tile->id, errmsg, errbit);
+			    "Tile%d %s SOC %s error, bit[%d] is set\n",
+			    tile->id, hwerr_to_str, errmsg, errbit);
 	tile->errors.count[indx]++;
 }
 
@@ -540,15 +603,34 @@ static void
 xe_soc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
 {
 	unsigned long mst_glb_errstat, slv_glb_errstat, lcl_errstat;
+
+	const struct err_msg_cntr_pair *soc_mstr_glbl_err_reg;
+	const struct err_msg_cntr_pair *soc_mstr_lcl_err_reg;
+	const struct err_msg_cntr_pair *soc_slave_glbl_err_reg;
+	const struct err_msg_cntr_pair *soc_slave_lcl_err_reg;
 	u32 errbit, base, slave_base;
 	int i;
+
+	const char *hwerr_to_str = hardware_error_type_to_str(hw_err);
 	struct xe_gt *gt = tile->primary_gt;
 
 	lockdep_assert_held(&tile_to_xe(tile)->irq.lock);
 
-	if ((tile_to_xe(tile)->info.platform != XE_PVC) && hw_err != HARDWARE_ERROR_FATAL)
+	if ((tile_to_xe(tile)->info.platform != XE_PVC) && hw_err == HARDWARE_ERROR_CORRECTABLE)
 		return;
 
+	if (hw_err == HARDWARE_ERROR_FATAL) {
+		soc_mstr_glbl_err_reg = soc_mstr_glbl_err_reg_fatal;
+		soc_mstr_lcl_err_reg = soc_mstr_lcl_err_reg_fatal;
+		soc_slave_glbl_err_reg = soc_slave_glbl_err_reg_fatal;
+		soc_slave_lcl_err_reg = soc_slave_lcl_err_reg_fatal;
+	} else if (hw_err == HARDWARE_ERROR_NONFATAL) {
+		soc_mstr_glbl_err_reg = soc_mstr_glbl_err_reg_nonfatal;
+		soc_mstr_lcl_err_reg = soc_mstr_lcl_err_reg_nonfatal;
+		soc_slave_glbl_err_reg = soc_slave_glbl_err_reg_nonfatal;
+		soc_slave_lcl_err_reg = soc_slave_lcl_err_reg_nonfatal;
+	}
+
 	base = SOC_PVC_BASE;
 	slave_base = SOC_PVC_SLAVE_BASE;
 
@@ -564,33 +646,34 @@ xe_soc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
 
 	mst_glb_errstat = xe_mmio_read32(gt, SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err));
 	drm_info(&tile_to_xe(tile)->drm, HW_ERR
-		 "Tile%d SOC_GLOBAL_ERR_STAT_MASTER_REG_FATAL:0x%08lx\n",
-		 tile->id, mst_glb_errstat);
+		 "Tile%d SOC_GLOBAL_ERR_STAT_MASTER_REG_%s:0x%08lx\n",
+		 tile->id, hwerr_to_str, mst_glb_errstat);
 
 	if (mst_glb_errstat & REG_BIT(SOC_SLAVE_IEH)) {
 		slv_glb_errstat = xe_mmio_read32(gt,
 						 SOC_GLOBAL_ERR_STAT_SLAVE_REG(slave_base, hw_err));
 		 drm_info(&tile_to_xe(tile)->drm, HW_ERR
-			  "Tile%d SOC_GLOBAL_ERR_STAT_SLAVE_REG_FATAL:0x%08lx\n",
-			  tile->id, slv_glb_errstat);
+			  "Tile%d SOC_GLOBAL_ERR_STAT_SLAVE_REG_%s:0x%08lx\n",
+			  tile->id, hwerr_to_str, slv_glb_errstat);
 
 		if (slv_glb_errstat & REG_BIT(SOC_IEH1_LOCAL_ERR_STATUS)) {
 			lcl_errstat = xe_mmio_read32(gt, SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base,
 										      hw_err));
 			 drm_info(&tile_to_xe(tile)->drm, HW_ERR
-				  "Tile%d SOC_LOCAL_ERR_STAT_SLAVE_REG_FATAL:0x%08lx\n",
-				  tile->id, lcl_errstat);
+				  "Tile%d SOC_LOCAL_ERR_STAT_SLAVE_REG_%s:0x%08lx\n",
+				  tile->id, hwerr_to_str, lcl_errstat);
 
 			for_each_set_bit(errbit, &lcl_errstat, 32)
-				xe_soc_log_err_update_cntr(tile, errbit,
-							   soc_slave_lcl_err_reg_fatal);
+				xe_soc_log_err_update_cntr(tile, hw_err, errbit,
+							   soc_slave_lcl_err_reg);
 
 			xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
 					lcl_errstat);
 		}
 
 		for_each_set_bit(errbit, &slv_glb_errstat, 32)
-			xe_soc_log_err_update_cntr(tile, errbit, soc_slave_glbl_err_reg_fatal);
+			xe_soc_log_err_update_cntr(tile, errbit, hw_err,
+						   soc_slave_glbl_err_reg);
 
 		xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
 				slv_glb_errstat);
@@ -598,17 +681,18 @@ xe_soc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
 
 	if (mst_glb_errstat & REG_BIT(SOC_IEH0_LOCAL_ERR_STATUS)) {
 		lcl_errstat = xe_mmio_read32(gt, SOC_LOCAL_ERR_STAT_MASTER_REG(base, hw_err));
-		drm_info(&tile_to_xe(tile)->drm, HW_ERR "SOC_LOCAL_ERR_STAT_MASTER_REG_FATAL:0x%08lx\n",
-			 lcl_errstat);
+		drm_info(&tile_to_xe(tile)->drm, HW_ERR "Tile%d SOC_LOCAL_ERR_STAT_MASTER_REG_%s:0x%08lx\n",
+			 tile->id, hwerr_to_str, lcl_errstat);
 
 		for_each_set_bit(errbit, &lcl_errstat, 32)
-			xe_soc_log_err_update_cntr(tile, errbit, soc_mstr_lcl_err_reg_fatal);
+			xe_soc_log_err_update_cntr(tile, hw_err, errbit,
+						   soc_mstr_lcl_err_reg);
 
 		xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_MASTER_REG(base, hw_err), lcl_errstat);
 	}
 
 	for_each_set_bit(errbit, &mst_glb_errstat, 32)
-		xe_soc_log_err_update_cntr(tile, errbit, soc_mstr_glbl_err_reg_fatal);
+		xe_soc_log_err_update_cntr(tile, errbit, hw_err, soc_mstr_glbl_err_reg);
 
 	xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err),
 			mst_glb_errstat);
diff --git a/drivers/gpu/drm/xe/xe_hw_error.h b/drivers/gpu/drm/xe/xe_hw_error.h
index 05838e082abd..a458a90b34a2 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.h
+++ b/drivers/gpu/drm/xe/xe_hw_error.h
@@ -115,6 +115,48 @@ enum xe_tile_hw_errors {
 	XE_SOC_HW_ERR_PCIE_PSF_CMD_FATAL,
 	XE_SOC_HW_ERR_PCIE_PSF_CMP_FATAL,
 	XE_SOC_HW_ERR_PCIE_PSF_REQ_FATAL,
+	XE_SOC_HW_ERR_MSTR_LCL_NONFATAL,
+	XE_SOC_HW_ERR_SLAVE_GLBL_NONFATAL,
+	XE_SOC_HW_ERR_HBM0_CHNL0_NONFATAL,
+	XE_SOC_HW_ERR_HBM0_CHNL1_NONFATAL,
+	XE_SOC_HW_ERR_HBM0_CHNL2_NONFATAL,
+	XE_SOC_HW_ERR_HBM0_CHNL3_NONFATAL,
+	XE_SOC_HW_ERR_HBM0_CHNL4_NONFATAL,
+	XE_SOC_HW_ERR_HBM0_CHNL5_NONFATAL,
+	XE_SOC_HW_ERR_HBM0_CHNL6_NONFATAL,
+	XE_SOC_HW_ERR_HBM0_CHNL7_NONFATAL,
+	XE_SOC_HW_ERR_HBM1_CHNL0_NONFATAL,
+	XE_SOC_HW_ERR_HBM1_CHNL1_NONFATAL,
+	XE_SOC_HW_ERR_HBM1_CHNL2_NONFATAL,
+	XE_SOC_HW_ERR_HBM1_CHNL3_NONFATAL,
+	XE_SOC_HW_ERR_HBM1_CHNL4_NONFATAL,
+	XE_SOC_HW_ERR_HBM1_CHNL5_NONFATAL,
+	XE_SOC_HW_ERR_HBM1_CHNL6_NONFATAL,
+	XE_SOC_HW_ERR_HBM1_CHNL7_NONFATAL,
+	XE_SOC_HW_ERR_UNKNOWN_NONFATAL,
+	XE_SOC_HW_ERR_SLAVE_LCL_NONFATAL,
+	XE_SOC_HW_ERR_HBM2_CHNL0_NONFATAL,
+	XE_SOC_HW_ERR_HBM2_CHNL1_NONFATAL,
+	XE_SOC_HW_ERR_HBM2_CHNL2_NONFATAL,
+	XE_SOC_HW_ERR_HBM2_CHNL3_NONFATAL,
+	XE_SOC_HW_ERR_HBM2_CHNL4_NONFATAL,
+	XE_SOC_HW_ERR_HBM2_CHNL5_NONFATAL,
+	XE_SOC_HW_ERR_HBM2_CHNL6_NONFATAL,
+	XE_SOC_HW_ERR_HBM2_CHNL7_NONFATAL,
+	XE_SOC_HW_ERR_HBM3_CHNL0_NONFATAL,
+	XE_SOC_HW_ERR_HBM3_CHNL1_NONFATAL,
+	XE_SOC_HW_ERR_HBM3_CHNL2_NONFATAL,
+	XE_SOC_HW_ERR_HBM3_CHNL3_NONFATAL,
+	XE_SOC_HW_ERR_HBM3_CHNL4_NONFATAL,
+	XE_SOC_HW_ERR_HBM3_CHNL5_NONFATAL,
+	XE_SOC_HW_ERR_HBM3_CHNL6_NONFATAL,
+	XE_SOC_HW_ERR_HBM3_CHNL7_NONFATAL,
+	XE_SOC_HW_ERR_ANR_MDFI_NONFATAL,
+	XE_SOC_HW_ERR_MDFI_T2T_NONFATAL,
+	XE_SOC_HW_ERR_MDFI_T2C_NONFATAL,
+	XE_SOC_HW_ERR_CSC_PSF_CMD_NONFATAL,
+	XE_SOC_HW_ERR_CSC_PSF_CMP_NONFATAL,
+	XE_SOC_HW_ERR_CSC_PSF_REQ_NONFATAL,
 	XE_TILE_HW_ERROR_MAX,
 };
 
-- 
2.25.1

Re: [Intel-xe] [PATCH 08/11] drm/xe: Support SOC NONFATAL error handling for PVC.

[Aravind Iddamsetty]

On 27/09/23 17:16, Himal Prasad Ghimiray wrote:
> Report the SOC nonfatal hardware error and update the counters which
> will increment incase of error.
>
> Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_hw_error.c | 118 ++++++++++++++++++++++++++-----
>  drivers/gpu/drm/xe/xe_hw_error.h |  42 +++++++++++
>  2 files changed, 143 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
> index fa05bad5e684..aeece9e705dc 100644
> --- a/drivers/gpu/drm/xe/xe_hw_error.c
> +++ b/drivers/gpu/drm/xe/xe_hw_error.c
> @@ -276,6 +276,67 @@ static const struct err_msg_cntr_pair soc_mstr_lcl_err_reg_fatal[] = {
>  	[14 ... 31] = {"Undefined",				XE_SOC_HW_ERR_UNKNOWN_FATAL},
>  };
>  
> +static const struct err_msg_cntr_pair soc_mstr_glbl_err_reg_nonfatal[] = {
> +	[0]         = {"MASTER LOCAL Reported",			XE_SOC_HW_ERR_MSTR_LCL_NONFATAL},
> +	[1]         = {"SLAVE GLOBAL Reported",			XE_SOC_HW_ERR_SLAVE_GLBL_NONFATAL},
same as mentioned in earlier patch no need to count these
> +	[2]         = {"HBM SS0: Channel0",			XE_SOC_HW_ERR_HBM0_CHNL0_NONFATAL},
> +	[3]         = {"HBM SS0: Channel1",			XE_SOC_HW_ERR_HBM0_CHNL1_NONFATAL},
> +	[4]         = {"HBM SS0: Channel2",			XE_SOC_HW_ERR_HBM0_CHNL2_NONFATAL},
> +	[5]         = {"HBM SS0: Channel3",			XE_SOC_HW_ERR_HBM0_CHNL3_NONFATAL},
> +	[6]         = {"HBM SS0: Channel4",			XE_SOC_HW_ERR_HBM0_CHNL4_NONFATAL},
> +	[7]         = {"HBM SS0: Channel5",			XE_SOC_HW_ERR_HBM0_CHNL5_NONFATAL},
> +	[8]         = {"HBM SS0: Channel6",                     XE_SOC_HW_ERR_HBM0_CHNL6_NONFATAL},
> +	[9]         = {"HBM SS0: Channel7",                     XE_SOC_HW_ERR_HBM0_CHNL7_NONFATAL},
> +	[10]        = {"HBM SS1: Channel0",                     XE_SOC_HW_ERR_HBM1_CHNL0_NONFATAL},
> +	[11]        = {"HBM SS1: Channel1",                     XE_SOC_HW_ERR_HBM1_CHNL1_NONFATAL},
> +	[12]        = {"HBM SS1: Channel2",                     XE_SOC_HW_ERR_HBM1_CHNL2_NONFATAL},
> +	[13]        = {"HBM SS1: Channel3",                     XE_SOC_HW_ERR_HBM1_CHNL3_NONFATAL},
> +	[14]        = {"HBM SS1: Channel4",                     XE_SOC_HW_ERR_HBM1_CHNL4_NONFATAL},
> +	[15]        = {"HBM SS1: Channel5",                     XE_SOC_HW_ERR_HBM1_CHNL5_NONFATAL},
> +	[16]        = {"HBM SS1: Channel6",                     XE_SOC_HW_ERR_HBM1_CHNL6_NONFATAL},
> +	[17]        = {"HBM SS1: Channel7",                     XE_SOC_HW_ERR_HBM1_CHNL7_NONFATAL},
> +	[18 ... 31] = {"Undefined",				XE_SOC_HW_ERR_UNKNOWN_FATAL},
> +};
> +
> +static const struct err_msg_cntr_pair soc_slave_glbl_err_reg_nonfatal[] = {
> +	[0]         = {"SLAVE LOCAL Reported",			XE_SOC_HW_ERR_SLAVE_LCL_NONFATAL},
same here
> +	[1]         = {"HBM SS2: Channel0",			XE_SOC_HW_ERR_HBM2_CHNL0_NONFATAL},
> +	[2]         = {"HBM SS2: Channel1",			XE_SOC_HW_ERR_HBM2_CHNL1_NONFATAL},
> +	[3]         = {"HBM SS2: Channel2",			XE_SOC_HW_ERR_HBM2_CHNL2_NONFATAL},
> +	[4]         = {"HBM SS2: Channel3",			XE_SOC_HW_ERR_HBM2_CHNL3_NONFATAL},
> +	[5]         = {"HBM SS2: Channel4",			XE_SOC_HW_ERR_HBM2_CHNL4_NONFATAL},
> +	[6]         = {"HBM SS2: Channel5",			XE_SOC_HW_ERR_HBM2_CHNL5_NONFATAL},
> +	[7]         = {"HBM SS2: Channel6",                     XE_SOC_HW_ERR_HBM2_CHNL6_NONFATAL},
> +	[8]         = {"HBM SS2: Channel7",                     XE_SOC_HW_ERR_HBM2_CHNL7_NONFATAL},
> +	[9]         = {"HBM SS3: Channel0",                     XE_SOC_HW_ERR_HBM3_CHNL0_NONFATAL},
> +	[10]        = {"HBM SS3: Channel1",                     XE_SOC_HW_ERR_HBM3_CHNL1_NONFATAL},
> +	[11]        = {"HBM SS3: Channel2",                     XE_SOC_HW_ERR_HBM3_CHNL2_NONFATAL},
> +	[12]        = {"HBM SS3: Channel3",                     XE_SOC_HW_ERR_HBM3_CHNL3_NONFATAL},
> +	[13]        = {"HBM SS3: Channel4",                     XE_SOC_HW_ERR_HBM3_CHNL4_NONFATAL},
> +	[14]        = {"HBM SS3: Channel5",                     XE_SOC_HW_ERR_HBM3_CHNL5_NONFATAL},
> +	[15]        = {"HBM SS3: Channel6",                     XE_SOC_HW_ERR_HBM3_CHNL6_NONFATAL},
> +	[16]        = {"HBM SS3: Channel7",                     XE_SOC_HW_ERR_HBM3_CHNL7_NONFATAL},
> +	[18]	    = {"ANR MDFI",				XE_SOC_HW_ERR_ANR_MDFI_NONFATAL},
> +	[17]        = {"Undefined",                             XE_SOC_HW_ERR_UNKNOWN_NONFATAL},
> +	[19 ... 31] = {"Undefined",				XE_SOC_HW_ERR_UNKNOWN_FATAL},
> +};
> +
> +static const struct err_msg_cntr_pair soc_slave_lcl_err_reg_nonfatal[] = {
> +	[0 ... 31]  = {"Undefined",			XE_SOC_HW_ERR_UNKNOWN_NONFATAL},
> +};
> +
> +static const struct err_msg_cntr_pair soc_mstr_lcl_err_reg_nonfatal[] = {
> +	[0 ... 3]   = {"Undefined",				XE_SOC_HW_ERR_UNKNOWN_NONFATAL},
> +	[4]         = {"Base Die MDFI T2T",			XE_SOC_HW_ERR_MDFI_T2T_NONFATAL},
> +	[5]         = {"Undefined",				XE_SOC_HW_ERR_UNKNOWN_NONFATAL},
> +	[6]         = {"Base Die MDFI T2C",			XE_SOC_HW_ERR_MDFI_T2C_NONFATAL},
> +	[7]         = {"Undefined",				XE_SOC_HW_ERR_UNKNOWN_NONFATAL},
> +	[8]         = {"Invalid CSC PSF Command Parity",	XE_SOC_HW_ERR_CSC_PSF_CMD_NONFATAL},
> +	[9]         = {"Invalid CSC PSF Unexpected Completion",	XE_SOC_HW_ERR_CSC_PSF_CMP_NONFATAL},
> +	[10]        = {"Invalid CSC PSF Unsupported Request",	XE_SOC_HW_ERR_CSC_PSF_REQ_NONFATAL},
> +	[11 ... 31] = {"Undefined",				XE_SOC_HW_ERR_UNKNOWN_FATAL},
> +};
> +
>  static void xe_assign_hw_err_regs(struct xe_device *xe)
>  {
>  	const struct err_msg_cntr_pair **dev_err_stat = xe->hw_err_regs.dev_err_stat;
> @@ -521,18 +582,20 @@ xe_gsc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
>  }
>  
>  static void
> -xe_soc_log_err_update_cntr(struct xe_tile *tile,
> +xe_soc_log_err_update_cntr(struct xe_tile *tile, const enum hardware_error hw_err,
>  			   u32 errbit, const struct err_msg_cntr_pair *reg_info)
>  {
>  	const char *errmsg;
>  	u32 indx;
>  
> +	const char *hwerr_to_str = hardware_error_type_to_str(hw_err);
> +
>  	errmsg = reg_info[errbit].errmsg;
>  	indx = reg_info[errbit].cntr_indx;
>  
>  	drm_err_ratelimited(&tile_to_xe(tile)->drm, HW_ERR
> -			    "Tile%d %s SOC FATAL error, bit[%d] is set\n",
> -			    tile->id, errmsg, errbit);
> +			    "Tile%d %s SOC %s error, bit[%d] is set\n",
> +			    tile->id, hwerr_to_str, errmsg, errbit);
in the prints as well let's maintain same reporting source error category error name.
and also let have some meaningful message like Tile0 reported SOC NONFATAL errorname
and don't need to error again at the end as HW_ERR will anyways prepend with "HARDWARE_ERROR".
will bit ID add any value as we will print the registers.
>  	tile->errors.count[indx]++;
>  }
>  
> @@ -540,15 +603,34 @@ static void
>  xe_soc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
>  {
>  	unsigned long mst_glb_errstat, slv_glb_errstat, lcl_errstat;
> +
> +	const struct err_msg_cntr_pair *soc_mstr_glbl_err_reg;
> +	const struct err_msg_cntr_pair *soc_mstr_lcl_err_reg;
> +	const struct err_msg_cntr_pair *soc_slave_glbl_err_reg;
> +	const struct err_msg_cntr_pair *soc_slave_lcl_err_reg;
>  	u32 errbit, base, slave_base;
>  	int i;
> +
> +	const char *hwerr_to_str = hardware_error_type_to_str(hw_err);
>  	struct xe_gt *gt = tile->primary_gt;
>  
>  	lockdep_assert_held(&tile_to_xe(tile)->irq.lock);
>  
> -	if ((tile_to_xe(tile)->info.platform != XE_PVC) && hw_err != HARDWARE_ERROR_FATAL)
> +	if ((tile_to_xe(tile)->info.platform != XE_PVC) && hw_err == HARDWARE_ERROR_CORRECTABLE)
>  		return;
>  
> +	if (hw_err == HARDWARE_ERROR_FATAL) {
> +		soc_mstr_glbl_err_reg = soc_mstr_glbl_err_reg_fatal;
> +		soc_mstr_lcl_err_reg = soc_mstr_lcl_err_reg_fatal;
> +		soc_slave_glbl_err_reg = soc_slave_glbl_err_reg_fatal;
> +		soc_slave_lcl_err_reg = soc_slave_lcl_err_reg_fatal;
> +	} else if (hw_err == HARDWARE_ERROR_NONFATAL) {
> +		soc_mstr_glbl_err_reg = soc_mstr_glbl_err_reg_nonfatal;
> +		soc_mstr_lcl_err_reg = soc_mstr_lcl_err_reg_nonfatal;
> +		soc_slave_glbl_err_reg = soc_slave_glbl_err_reg_nonfatal;
> +		soc_slave_lcl_err_reg = soc_slave_lcl_err_reg_nonfatal;
> +	}
i guess this we agreed to do once like we did for GT errors
> +
>  	base = SOC_PVC_BASE;
>  	slave_base = SOC_PVC_SLAVE_BASE;
>  
> @@ -564,33 +646,34 @@ xe_soc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
>  
>  	mst_glb_errstat = xe_mmio_read32(gt, SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err));
>  	drm_info(&tile_to_xe(tile)->drm, HW_ERR
> -		 "Tile%d SOC_GLOBAL_ERR_STAT_MASTER_REG_FATAL:0x%08lx\n",
> -		 tile->id, mst_glb_errstat);
> +		 "Tile%d SOC_GLOBAL_ERR_STAT_MASTER_REG_%s:0x%08lx\n",
> +		 tile->id, hwerr_to_str, mst_glb_errstat);
for the register dumps let's use drm_dbg
>  
>  	if (mst_glb_errstat & REG_BIT(SOC_SLAVE_IEH)) {
>  		slv_glb_errstat = xe_mmio_read32(gt,
>  						 SOC_GLOBAL_ERR_STAT_SLAVE_REG(slave_base, hw_err));
>  		 drm_info(&tile_to_xe(tile)->drm, HW_ERR
> -			  "Tile%d SOC_GLOBAL_ERR_STAT_SLAVE_REG_FATAL:0x%08lx\n",
> -			  tile->id, slv_glb_errstat);
> +			  "Tile%d SOC_GLOBAL_ERR_STAT_SLAVE_REG_%s:0x%08lx\n",
> +			  tile->id, hwerr_to_str, slv_glb_errstat);
>  
>  		if (slv_glb_errstat & REG_BIT(SOC_IEH1_LOCAL_ERR_STATUS)) {
>  			lcl_errstat = xe_mmio_read32(gt, SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base,
>  										      hw_err));
>  			 drm_info(&tile_to_xe(tile)->drm, HW_ERR
> -				  "Tile%d SOC_LOCAL_ERR_STAT_SLAVE_REG_FATAL:0x%08lx\n",
> -				  tile->id, lcl_errstat);
> +				  "Tile%d SOC_LOCAL_ERR_STAT_SLAVE_REG_%s:0x%08lx\n",
> +				  tile->id, hwerr_to_str, lcl_errstat);
>  
>  			for_each_set_bit(errbit, &lcl_errstat, 32)
define what 32 is
> -				xe_soc_log_err_update_cntr(tile, errbit,
> -							   soc_slave_lcl_err_reg_fatal);
> +				xe_soc_log_err_update_cntr(tile, hw_err, errbit,
> +							   soc_slave_lcl_err_reg);
>  
>  			xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
>  					lcl_errstat);
>  		}
>  
>  		for_each_set_bit(errbit, &slv_glb_errstat, 32)
> -			xe_soc_log_err_update_cntr(tile, errbit, soc_slave_glbl_err_reg_fatal);
> +			xe_soc_log_err_update_cntr(tile, errbit, hw_err,
> +						   soc_slave_glbl_err_reg);
>  
>  		xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
>  				slv_glb_errstat);
> @@ -598,17 +681,18 @@ xe_soc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
>  
>  	if (mst_glb_errstat & REG_BIT(SOC_IEH0_LOCAL_ERR_STATUS)) {
>  		lcl_errstat = xe_mmio_read32(gt, SOC_LOCAL_ERR_STAT_MASTER_REG(base, hw_err));
> -		drm_info(&tile_to_xe(tile)->drm, HW_ERR "SOC_LOCAL_ERR_STAT_MASTER_REG_FATAL:0x%08lx\n",
> -			 lcl_errstat);
> +		drm_info(&tile_to_xe(tile)->drm, HW_ERR "Tile%d SOC_LOCAL_ERR_STAT_MASTER_REG_%s:0x%08lx\n",
> +			 tile->id, hwerr_to_str, lcl_errstat);
>  
>  		for_each_set_bit(errbit, &lcl_errstat, 32)
> -			xe_soc_log_err_update_cntr(tile, errbit, soc_mstr_lcl_err_reg_fatal);
> +			xe_soc_log_err_update_cntr(tile, hw_err, errbit,
> +						   soc_mstr_lcl_err_reg);
>  
>  		xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_MASTER_REG(base, hw_err), lcl_errstat);
>  	}
>  
>  	for_each_set_bit(errbit, &mst_glb_errstat, 32)
> -		xe_soc_log_err_update_cntr(tile, errbit, soc_mstr_glbl_err_reg_fatal);
> +		xe_soc_log_err_update_cntr(tile, errbit, hw_err, soc_mstr_glbl_err_reg);
>  
>  	xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err),
>  			mst_glb_errstat);
> diff --git a/drivers/gpu/drm/xe/xe_hw_error.h b/drivers/gpu/drm/xe/xe_hw_error.h
> index 05838e082abd..a458a90b34a2 100644
> --- a/drivers/gpu/drm/xe/xe_hw_error.h
> +++ b/drivers/gpu/drm/xe/xe_hw_error.h
> @@ -115,6 +115,48 @@ enum xe_tile_hw_errors {
>  	XE_SOC_HW_ERR_PCIE_PSF_CMD_FATAL,
>  	XE_SOC_HW_ERR_PCIE_PSF_CMP_FATAL,
>  	XE_SOC_HW_ERR_PCIE_PSF_REQ_FATAL,
> +	XE_SOC_HW_ERR_MSTR_LCL_NONFATAL,
> +	XE_SOC_HW_ERR_SLAVE_GLBL_NONFATAL,
> +	XE_SOC_HW_ERR_HBM0_CHNL0_NONFATAL,
> +	XE_SOC_HW_ERR_HBM0_CHNL1_NONFATAL,
> +	XE_SOC_HW_ERR_HBM0_CHNL2_NONFATAL,
> +	XE_SOC_HW_ERR_HBM0_CHNL3_NONFATAL,
> +	XE_SOC_HW_ERR_HBM0_CHNL4_NONFATAL,
> +	XE_SOC_HW_ERR_HBM0_CHNL5_NONFATAL,
> +	XE_SOC_HW_ERR_HBM0_CHNL6_NONFATAL,
> +	XE_SOC_HW_ERR_HBM0_CHNL7_NONFATAL,
> +	XE_SOC_HW_ERR_HBM1_CHNL0_NONFATAL,
> +	XE_SOC_HW_ERR_HBM1_CHNL1_NONFATAL,
> +	XE_SOC_HW_ERR_HBM1_CHNL2_NONFATAL,
> +	XE_SOC_HW_ERR_HBM1_CHNL3_NONFATAL,
> +	XE_SOC_HW_ERR_HBM1_CHNL4_NONFATAL,
> +	XE_SOC_HW_ERR_HBM1_CHNL5_NONFATAL,
> +	XE_SOC_HW_ERR_HBM1_CHNL6_NONFATAL,
> +	XE_SOC_HW_ERR_HBM1_CHNL7_NONFATAL,
> +	XE_SOC_HW_ERR_UNKNOWN_NONFATAL,
> +	XE_SOC_HW_ERR_SLAVE_LCL_NONFATAL,
> +	XE_SOC_HW_ERR_HBM2_CHNL0_NONFATAL,
> +	XE_SOC_HW_ERR_HBM2_CHNL1_NONFATAL,
> +	XE_SOC_HW_ERR_HBM2_CHNL2_NONFATAL,
> +	XE_SOC_HW_ERR_HBM2_CHNL3_NONFATAL,
> +	XE_SOC_HW_ERR_HBM2_CHNL4_NONFATAL,
> +	XE_SOC_HW_ERR_HBM2_CHNL5_NONFATAL,
> +	XE_SOC_HW_ERR_HBM2_CHNL6_NONFATAL,
> +	XE_SOC_HW_ERR_HBM2_CHNL7_NONFATAL,
> +	XE_SOC_HW_ERR_HBM3_CHNL0_NONFATAL,
> +	XE_SOC_HW_ERR_HBM3_CHNL1_NONFATAL,
> +	XE_SOC_HW_ERR_HBM3_CHNL2_NONFATAL,
> +	XE_SOC_HW_ERR_HBM3_CHNL3_NONFATAL,
> +	XE_SOC_HW_ERR_HBM3_CHNL4_NONFATAL,
> +	XE_SOC_HW_ERR_HBM3_CHNL5_NONFATAL,
> +	XE_SOC_HW_ERR_HBM3_CHNL6_NONFATAL,
> +	XE_SOC_HW_ERR_HBM3_CHNL7_NONFATAL,
> +	XE_SOC_HW_ERR_ANR_MDFI_NONFATAL,
> +	XE_SOC_HW_ERR_MDFI_T2T_NONFATAL,
> +	XE_SOC_HW_ERR_MDFI_T2C_NONFATAL,
> +	XE_SOC_HW_ERR_CSC_PSF_CMD_NONFATAL,
> +	XE_SOC_HW_ERR_CSC_PSF_CMP_NONFATAL,
> +	XE_SOC_HW_ERR_CSC_PSF_REQ_NONFATAL,
>  	XE_TILE_HW_ERROR_MAX,
>  };

Thanks,

Aravind.

>  

[Intel-xe] [PATCH 09/11] drm/xe: Handle MDFI error severity.

[Himal Prasad Ghimiray]

Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_tile_error_regs.h |  7 +++++++
 drivers/gpu/drm/xe/xe_hw_error.c             | 16 ++++++++++++++--
 2 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
index 04701c62f0d9..8a5f6cd29304 100644
--- a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
@@ -48,4 +48,11 @@
 								(base) + _SOC_GCOERRSTS, \
 								(base) + _SOC_GNFERRSTS))
 
+#define LOCAL_FIRST_IEH_HEADER_LOG_REG			XE_REG(0x2822b0)
+#define MDFI_SEVERITY_FATAL		0x00330000
+#define MDFI_SEVERITY_NONFATAL		0x00310000
+#define MDFI_SEVERITY(x)				((x) == HARDWARE_ERROR_FATAL ? \
+								MDFI_SEVERITY_FATAL : \
+								MDFI_SEVERITY_NONFATAL)
+
 #endif
diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
index aeece9e705dc..dcf395bd985f 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.c
+++ b/drivers/gpu/drm/xe/xe_hw_error.c
@@ -608,7 +608,7 @@ xe_soc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
 	const struct err_msg_cntr_pair *soc_mstr_lcl_err_reg;
 	const struct err_msg_cntr_pair *soc_slave_glbl_err_reg;
 	const struct err_msg_cntr_pair *soc_slave_lcl_err_reg;
-	u32 errbit, base, slave_base;
+	u32 errbit, base, slave_base, ieh_header;
 	int i;
 
 	const char *hwerr_to_str = hardware_error_type_to_str(hw_err);
@@ -684,9 +684,21 @@ xe_soc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
 		drm_info(&tile_to_xe(tile)->drm, HW_ERR "Tile%d SOC_LOCAL_ERR_STAT_MASTER_REG_%s:0x%08lx\n",
 			 tile->id, hwerr_to_str, lcl_errstat);
 
-		for_each_set_bit(errbit, &lcl_errstat, 32)
+		for_each_set_bit(errbit, &lcl_errstat, 32) {
+			if (errbit == 4 || errbit == 6) {
+				ieh_header = xe_mmio_read32(gt, LOCAL_FIRST_IEH_HEADER_LOG_REG);
+				drm_info(&tile_to_xe(tile)->drm, HW_ERR "Tile%d LOCAL_FIRST_IEH_HEADER_LOG_REG:0x%08x\n",
+					 tile->id, ieh_header);
+
+				if (ieh_header != MDFI_SEVERITY(hw_err)) {
+					lcl_errstat &= ~REG_BIT(errbit);
+					continue;
+				}
+			}
+
 			xe_soc_log_err_update_cntr(tile, hw_err, errbit,
 						   soc_mstr_lcl_err_reg);
+		}
 
 		xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_MASTER_REG(base, hw_err), lcl_errstat);
 	}
-- 
2.25.1

Re: [Intel-xe] [PATCH 09/11] drm/xe: Handle MDFI error severity.

[Aravind Iddamsetty]

On 27/09/23 17:16, Himal Prasad Ghimiray wrote:

missing commit message.

Thanks,
Aravind.
> Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_tile_error_regs.h |  7 +++++++
>  drivers/gpu/drm/xe/xe_hw_error.c             | 16 ++++++++++++++--
>  2 files changed, 21 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
> index 04701c62f0d9..8a5f6cd29304 100644
> --- a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
> @@ -48,4 +48,11 @@
>  								(base) + _SOC_GCOERRSTS, \
>  								(base) + _SOC_GNFERRSTS))
>  
> +#define LOCAL_FIRST_IEH_HEADER_LOG_REG			XE_REG(0x2822b0)
> +#define MDFI_SEVERITY_FATAL		0x00330000
> +#define MDFI_SEVERITY_NONFATAL		0x00310000
> +#define MDFI_SEVERITY(x)				((x) == HARDWARE_ERROR_FATAL ? \
> +								MDFI_SEVERITY_FATAL : \
> +								MDFI_SEVERITY_NONFATAL)
> +
>  #endif
> diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
> index aeece9e705dc..dcf395bd985f 100644
> --- a/drivers/gpu/drm/xe/xe_hw_error.c
> +++ b/drivers/gpu/drm/xe/xe_hw_error.c
> @@ -608,7 +608,7 @@ xe_soc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
>  	const struct err_msg_cntr_pair *soc_mstr_lcl_err_reg;
>  	const struct err_msg_cntr_pair *soc_slave_glbl_err_reg;
>  	const struct err_msg_cntr_pair *soc_slave_lcl_err_reg;
> -	u32 errbit, base, slave_base;
> +	u32 errbit, base, slave_base, ieh_header;
>  	int i;
>  
>  	const char *hwerr_to_str = hardware_error_type_to_str(hw_err);
> @@ -684,9 +684,21 @@ xe_soc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
>  		drm_info(&tile_to_xe(tile)->drm, HW_ERR "Tile%d SOC_LOCAL_ERR_STAT_MASTER_REG_%s:0x%08lx\n",
>  			 tile->id, hwerr_to_str, lcl_errstat);
>  
> -		for_each_set_bit(errbit, &lcl_errstat, 32)
> +		for_each_set_bit(errbit, &lcl_errstat, 32) {
> +			if (errbit == 4 || errbit == 6) {
> +				ieh_header = xe_mmio_read32(gt, LOCAL_FIRST_IEH_HEADER_LOG_REG);
> +				drm_info(&tile_to_xe(tile)->drm, HW_ERR "Tile%d LOCAL_FIRST_IEH_HEADER_LOG_REG:0x%08x\n",
> +					 tile->id, ieh_header);
> +
> +				if (ieh_header != MDFI_SEVERITY(hw_err)) {
> +					lcl_errstat &= ~REG_BIT(errbit);
> +					continue;
> +				}
> +			}
> +
>  			xe_soc_log_err_update_cntr(tile, hw_err, errbit,
>  						   soc_mstr_lcl_err_reg);
> +		}
>  
>  		xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_MASTER_REG(base, hw_err), lcl_errstat);
>  	}

[Intel-xe] [PATCH 10/11] drm/xe: Clear SOC CORRECTABLE error registers.

[Himal Prasad Ghimiray]

PVC doesn't support correctable SOC errors, if we receive MSI due to
correctable error, classify them as Undefined and clear the registers.

Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
 drivers/gpu/drm/xe/xe_hw_error.c | 24 +++++++++++++++++++++++-
 1 file changed, 23 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
index dcf395bd985f..0bcb1bea7ffb 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.c
+++ b/drivers/gpu/drm/xe/xe_hw_error.c
@@ -616,9 +616,30 @@ xe_soc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
 
 	lockdep_assert_held(&tile_to_xe(tile)->irq.lock);
 
-	if ((tile_to_xe(tile)->info.platform != XE_PVC) && hw_err == HARDWARE_ERROR_CORRECTABLE)
+	if ((tile_to_xe(tile)->info.platform != XE_PVC))
 		return;
 
+	if (hw_err == HARDWARE_ERROR_CORRECTABLE) {
+		for (i = 0; i < PVC_NUM_IEH; i++)
+			xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base, i),
+					~REG_BIT(hw_err));
+
+		xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err),
+				REG_GENMASK(31, 0));
+		xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_MASTER_REG(base, hw_err),
+				REG_GENMASK(31, 0));
+		xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
+				REG_GENMASK(31, 0));
+		xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
+				REG_GENMASK(31, 0));
+
+		drm_info(&tile_to_xe(tile)->drm, HW_ERR
+			  "Tile%d Undefine SOC %s error.",
+			  tile->id, hwerr_to_str);
+
+		goto unmask_gsysevtctl;
+	}
+
 	if (hw_err == HARDWARE_ERROR_FATAL) {
 		soc_mstr_glbl_err_reg = soc_mstr_glbl_err_reg_fatal;
 		soc_mstr_lcl_err_reg = soc_mstr_lcl_err_reg_fatal;
@@ -709,6 +730,7 @@ xe_soc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
 	xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err),
 			mst_glb_errstat);
 
+unmask_gsysevtctl:
 	for (i = 0; i < PVC_NUM_IEH; i++)
 		xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base, i),
 				(HARDWARE_ERROR_MAX << 1) + 1);
-- 
2.25.1

Re: [Intel-xe] [PATCH 10/11] drm/xe: Clear SOC CORRECTABLE error registers.

[Aravind Iddamsetty]

On 27/09/23 17:16, Himal Prasad Ghimiray wrote:
> PVC doesn't support correctable SOC errors, if we receive MSI due to
> correctable error, classify them as Undefined and clear the registers.
>
> Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_hw_error.c | 24 +++++++++++++++++++++++-
>  1 file changed, 23 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
> index dcf395bd985f..0bcb1bea7ffb 100644
> --- a/drivers/gpu/drm/xe/xe_hw_error.c
> +++ b/drivers/gpu/drm/xe/xe_hw_error.c
> @@ -616,9 +616,30 @@ xe_soc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
>  
>  	lockdep_assert_held(&tile_to_xe(tile)->irq.lock);
>  
> -	if ((tile_to_xe(tile)->info.platform != XE_PVC) && hw_err == HARDWARE_ERROR_CORRECTABLE)
> +	if ((tile_to_xe(tile)->info.platform != XE_PVC))
change in the patch that introduced it.
>  		return;
>  
> +	if (hw_err == HARDWARE_ERROR_CORRECTABLE) {
> +		for (i = 0; i < PVC_NUM_IEH; i++)
update PVC_NUM_IEH correctly.
> +			xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base, i),
> +					~REG_BIT(hw_err));
> +
> +		xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err),
> +				REG_GENMASK(31, 0));
> +		xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_MASTER_REG(base, hw_err),
> +				REG_GENMASK(31, 0));
> +		xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
> +				REG_GENMASK(31, 0));
> +		xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
> +				REG_GENMASK(31, 0));
> +
> +		drm_info(&tile_to_xe(tile)->drm, HW_ERR
> +			  "Tile%d Undefine SOC %s error.",
> +			  tile->id, hwerr_to_str);
> +
> +		goto unmask_gsysevtctl;
> +	}
> +
>  	if (hw_err == HARDWARE_ERROR_FATAL) {
>  		soc_mstr_glbl_err_reg = soc_mstr_glbl_err_reg_fatal;
>  		soc_mstr_lcl_err_reg = soc_mstr_lcl_err_reg_fatal;
> @@ -709,6 +730,7 @@ xe_soc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
>  	xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err),
>  			mst_glb_errstat);
>  
> +unmask_gsysevtctl:
>  	for (i = 0; i < PVC_NUM_IEH; i++)
same here.
>  		xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base, i),
>  				(HARDWARE_ERROR_MAX << 1) + 1);
Thanks,
Aravind.

Re: [Intel-xe] [PATCH 10/11] drm/xe: Clear SOC CORRECTABLE error registers.

[Aravind Iddamsetty]

On 27/09/23 17:16, Himal Prasad Ghimiray wrote:
> PVC doesn't support correctable SOC errors, if we receive MSI due to

statement looks incomplete/inappropriate,

better rephrase to "PVC doesn't support correctable SOC error reporting"

Thanks,
Aravind.
> correctable error, classify them as Undefined and clear the registers.
>
> Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_hw_error.c | 24 +++++++++++++++++++++++-
>  1 file changed, 23 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
> index dcf395bd985f..0bcb1bea7ffb 100644
> --- a/drivers/gpu/drm/xe/xe_hw_error.c
> +++ b/drivers/gpu/drm/xe/xe_hw_error.c
> @@ -616,9 +616,30 @@ xe_soc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
>  
>  	lockdep_assert_held(&tile_to_xe(tile)->irq.lock);
>  
> -	if ((tile_to_xe(tile)->info.platform != XE_PVC) && hw_err == HARDWARE_ERROR_CORRECTABLE)
> +	if ((tile_to_xe(tile)->info.platform != XE_PVC))
>  		return;
>  
> +	if (hw_err == HARDWARE_ERROR_CORRECTABLE) {
> +		for (i = 0; i < PVC_NUM_IEH; i++)
> +			xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base, i),
> +					~REG_BIT(hw_err));
> +
> +		xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err),
> +				REG_GENMASK(31, 0));
> +		xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_MASTER_REG(base, hw_err),
> +				REG_GENMASK(31, 0));
> +		xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
> +				REG_GENMASK(31, 0));
> +		xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
> +				REG_GENMASK(31, 0));
> +
> +		drm_info(&tile_to_xe(tile)->drm, HW_ERR
> +			  "Tile%d Undefine SOC %s error.",
> +			  tile->id, hwerr_to_str);
I still feel in this scenarios at least we shall flag this as drm_err, since even though
it is correctable and corrected by HW, aren't they spurious as we don't expect to receive them
and a HW misbehaviour. Thoughts?


Thanks,
Aravind.
> +
> +		goto unmask_gsysevtctl;
> +	}
> +
>  	if (hw_err == HARDWARE_ERROR_FATAL) {
>  		soc_mstr_glbl_err_reg = soc_mstr_glbl_err_reg_fatal;
>  		soc_mstr_lcl_err_reg = soc_mstr_lcl_err_reg_fatal;
> @@ -709,6 +730,7 @@ xe_soc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
>  	xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err),
>  			mst_glb_errstat);
>  
> +unmask_gsysevtctl:
>  	for (i = 0; i < PVC_NUM_IEH; i++)
>  		xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base, i),
>  				(HARDWARE_ERROR_MAX << 1) + 1);

Re: [Intel-xe] [PATCH 10/11] drm/xe: Clear SOC CORRECTABLE error registers.

[Ghimiray, Himal Prasad]

On 11-10-2023 12:18, Aravind Iddamsetty wrote:
> On 27/09/23 17:16, Himal Prasad Ghimiray wrote:
>> PVC doesn't support correctable SOC errors, if we receive MSI due to
> statement looks incomplete/inappropriate,
>
> better rephrase to "PVC doesn't support correctable SOC error reporting"
ok.
>
> Thanks,
> Aravind.
>> correctable error, classify them as Undefined and clear the registers.
>>
>> Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
>> ---
>>   drivers/gpu/drm/xe/xe_hw_error.c | 24 +++++++++++++++++++++++-
>>   1 file changed, 23 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
>> index dcf395bd985f..0bcb1bea7ffb 100644
>> --- a/drivers/gpu/drm/xe/xe_hw_error.c
>> +++ b/drivers/gpu/drm/xe/xe_hw_error.c
>> @@ -616,9 +616,30 @@ xe_soc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
>>   
>>   	lockdep_assert_held(&tile_to_xe(tile)->irq.lock);
>>   
>> -	if ((tile_to_xe(tile)->info.platform != XE_PVC) && hw_err == HARDWARE_ERROR_CORRECTABLE)
>> +	if ((tile_to_xe(tile)->info.platform != XE_PVC))
>>   		return;
>>   
>> +	if (hw_err == HARDWARE_ERROR_CORRECTABLE) {
>> +		for (i = 0; i < PVC_NUM_IEH; i++)
>> +			xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base, i),
>> +					~REG_BIT(hw_err));
>> +
>> +		xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err),
>> +				REG_GENMASK(31, 0));
>> +		xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_MASTER_REG(base, hw_err),
>> +				REG_GENMASK(31, 0));
>> +		xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
>> +				REG_GENMASK(31, 0));
>> +		xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
>> +				REG_GENMASK(31, 0));
>> +
>> +		drm_info(&tile_to_xe(tile)->drm, HW_ERR
>> +			  "Tile%d Undefine SOC %s error.",
>> +			  tile->id, hwerr_to_str);
> I still feel in this scenarios at least we shall flag this as drm_err, since even though
> it is correctable and corrected by HW, aren't they spurious as we don't expect to receive them
> and a HW misbehaviour. Thoughts?

Agreed. IMO this change should be part of low driver error reporting. 
Not only SOC, we need to report other gt and tile errors

too as spurious interrupt errors when they are undefined irrespective of 
error classes(correctable/uncorrectable).

>
>
> Thanks,
> Aravind.
>> +
>> +		goto unmask_gsysevtctl;
>> +	}
>> +
>>   	if (hw_err == HARDWARE_ERROR_FATAL) {
>>   		soc_mstr_glbl_err_reg = soc_mstr_glbl_err_reg_fatal;
>>   		soc_mstr_lcl_err_reg = soc_mstr_lcl_err_reg_fatal;
>> @@ -709,6 +730,7 @@ xe_soc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
>>   	xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err),
>>   			mst_glb_errstat);
>>   
>> +unmask_gsysevtctl:
>>   	for (i = 0; i < PVC_NUM_IEH; i++)
>>   		xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base, i),
>>   				(HARDWARE_ERROR_MAX << 1) + 1);

Re: [Intel-xe] [PATCH 10/11] drm/xe: Clear SOC CORRECTABLE error registers.

[Aravind Iddamsetty]

On 11/10/23 12:22, Ghimiray, Himal Prasad wrote:
>
> On 11-10-2023 12:18, Aravind Iddamsetty wrote:
>> On 27/09/23 17:16, Himal Prasad Ghimiray wrote:
>>> PVC doesn't support correctable SOC errors, if we receive MSI due to
>> statement looks incomplete/inappropriate,
>>
>> better rephrase to "PVC doesn't support correctable SOC error reporting"
> ok.
>>
>> Thanks,
>> Aravind.
>>> correctable error, classify them as Undefined and clear the registers.
>>>
>>> Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
>>> ---
>>>   drivers/gpu/drm/xe/xe_hw_error.c | 24 +++++++++++++++++++++++-
>>>   1 file changed, 23 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
>>> index dcf395bd985f..0bcb1bea7ffb 100644
>>> --- a/drivers/gpu/drm/xe/xe_hw_error.c
>>> +++ b/drivers/gpu/drm/xe/xe_hw_error.c
>>> @@ -616,9 +616,30 @@ xe_soc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
>>>         lockdep_assert_held(&tile_to_xe(tile)->irq.lock);
>>>   -    if ((tile_to_xe(tile)->info.platform != XE_PVC) && hw_err == HARDWARE_ERROR_CORRECTABLE)
>>> +    if ((tile_to_xe(tile)->info.platform != XE_PVC))
>>>           return;
>>>   +    if (hw_err == HARDWARE_ERROR_CORRECTABLE) {
>>> +        for (i = 0; i < PVC_NUM_IEH; i++)
>>> +            xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base, i),
>>> +                    ~REG_BIT(hw_err));
>>> +
>>> +        xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err),
>>> +                REG_GENMASK(31, 0));
>>> +        xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_MASTER_REG(base, hw_err),
>>> +                REG_GENMASK(31, 0));
>>> +        xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
>>> +                REG_GENMASK(31, 0));
>>> +        xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
>>> +                REG_GENMASK(31, 0));
>>> +
>>> +        drm_info(&tile_to_xe(tile)->drm, HW_ERR
>>> +              "Tile%d Undefine SOC %s error.",
>>> +              tile->id, hwerr_to_str);
>> I still feel in this scenarios at least we shall flag this as drm_err, since even though
>> it is correctable and corrected by HW, aren't they spurious as we don't expect to receive them
>> and a HW misbehaviour. Thoughts?
>
> Agreed. IMO this change should be part of low driver error reporting. Not only SOC, we need to report other gt and tile errors

the category will be added as part of low level driver error, but the since you are adding the print, suggesting to change to drm_err

Thanks,

Aravind.

>
> too as spurious interrupt errors when they are undefined irrespective of error classes(correctable/uncorrectable).
>
>>
>>
>> Thanks,
>> Aravind.
>>> +
>>> +        goto unmask_gsysevtctl;
>>> +    }
>>> +
>>>       if (hw_err == HARDWARE_ERROR_FATAL) {
>>>           soc_mstr_glbl_err_reg = soc_mstr_glbl_err_reg_fatal;
>>>           soc_mstr_lcl_err_reg = soc_mstr_lcl_err_reg_fatal;
>>> @@ -709,6 +730,7 @@ xe_soc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
>>>       xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err),
>>>               mst_glb_errstat);
>>>   +unmask_gsysevtctl:
>>>       for (i = 0; i < PVC_NUM_IEH; i++)
>>>           xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base, i),
>>>                   (HARDWARE_ERROR_MAX << 1) + 1);

Re: [Intel-xe] [PATCH 10/11] drm/xe: Clear SOC CORRECTABLE error registers.

[Ghimiray, Himal Prasad]

> -----Original Message-----
> From: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
> Sent: 12 October 2023 08:30
> To: Ghimiray, Himal Prasad <himal.prasad.ghimiray@intel.com>; intel-
> xe@lists.freedesktop.org
> Subject: Re: [Intel-xe] [PATCH 10/11] drm/xe: Clear SOC CORRECTABLE error
> registers.
> 
> 
> On 11/10/23 12:22, Ghimiray, Himal Prasad wrote:
> >
> > On 11-10-2023 12:18, Aravind Iddamsetty wrote:
> >> On 27/09/23 17:16, Himal Prasad Ghimiray wrote:
> >>> PVC doesn't support correctable SOC errors, if we receive MSI due to
> >> statement looks incomplete/inappropriate,
> >>
> >> better rephrase to "PVC doesn't support correctable SOC error reporting"
> > ok.
> >>
> >> Thanks,
> >> Aravind.
> >>> correctable error, classify them as Undefined and clear the registers.
> >>>
> >>> Signed-off-by: Himal Prasad Ghimiray
> >>> <himal.prasad.ghimiray@intel.com>
> >>> ---
> >>>   drivers/gpu/drm/xe/xe_hw_error.c | 24 +++++++++++++++++++++++-
> >>>   1 file changed, 23 insertions(+), 1 deletion(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/xe/xe_hw_error.c
> >>> b/drivers/gpu/drm/xe/xe_hw_error.c
> >>> index dcf395bd985f..0bcb1bea7ffb 100644
> >>> --- a/drivers/gpu/drm/xe/xe_hw_error.c
> >>> +++ b/drivers/gpu/drm/xe/xe_hw_error.c
> >>> @@ -616,9 +616,30 @@ xe_soc_hw_error_handler(struct xe_tile *tile,
> >>> const enum hardware_error hw_err)
> >>>         lockdep_assert_held(&tile_to_xe(tile)->irq.lock);
> >>>   -    if ((tile_to_xe(tile)->info.platform != XE_PVC) && hw_err ==
> >>> HARDWARE_ERROR_CORRECTABLE)
> >>> +    if ((tile_to_xe(tile)->info.platform != XE_PVC))
> >>>           return;
> >>>   +    if (hw_err == HARDWARE_ERROR_CORRECTABLE) {
> >>> +        for (i = 0; i < PVC_NUM_IEH; i++)
> >>> +            xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base,
> >>> +slave_base, i),
> >>> +                    ~REG_BIT(hw_err));
> >>> +
> >>> +        xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_MASTER_REG(base,
> >>> +hw_err),
> >>> +                REG_GENMASK(31, 0));
> >>> +        xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_MASTER_REG(base,
> >>> +hw_err),
> >>> +                REG_GENMASK(31, 0));
> >>> +        xe_mmio_write32(gt,
> >>> +SOC_GLOBAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
> >>> +                REG_GENMASK(31, 0));
> >>> +        xe_mmio_write32(gt,
> >>> +SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
> >>> +                REG_GENMASK(31, 0));
> >>> +
> >>> +        drm_info(&tile_to_xe(tile)->drm, HW_ERR
> >>> +              "Tile%d Undefine SOC %s error.",
> >>> +              tile->id, hwerr_to_str);
> >> I still feel in this scenarios at least we shall flag this as
> >> drm_err, since even though it is correctable and corrected by HW,
> >> aren't they spurious as we don't expect to receive them and a HW
> misbehaviour. Thoughts?
> >
> > Agreed. IMO this change should be part of low driver error reporting.
> > Not only SOC, we need to report other gt and tile errors
> 
> the category will be added as part of low level driver error, but the since you
> are adding the print, suggesting to change to drm_err

Ok

> 
> Thanks,
> 
> Aravind.
> 
> >
> > too as spurious interrupt errors when they are undefined irrespective of
> error classes(correctable/uncorrectable).
> >
> >>
> >>
> >> Thanks,
> >> Aravind.
> >>> +
> >>> +        goto unmask_gsysevtctl;
> >>> +    }
> >>> +
> >>>       if (hw_err == HARDWARE_ERROR_FATAL) {
> >>>           soc_mstr_glbl_err_reg = soc_mstr_glbl_err_reg_fatal;
> >>>           soc_mstr_lcl_err_reg = soc_mstr_lcl_err_reg_fatal; @@
> >>> -709,6 +730,7 @@ xe_soc_hw_error_handler(struct xe_tile *tile, const
> >>> enum hardware_error hw_err)
> >>>       xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_MASTER_REG(base,
> >>> hw_err),
> >>>               mst_glb_errstat);
> >>>   +unmask_gsysevtctl:
> >>>       for (i = 0; i < PVC_NUM_IEH; i++)
> >>>           xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base,
> >>> i),
> >>>                   (HARDWARE_ERROR_MAX << 1) + 1);

[Intel-xe] [PATCH 11/11] drm/xe: Clear all SoC errors post warm reset.

[Himal Prasad Ghimiray]

There are scenarios where there are no fatal errors reported
but Non-fatal/correctable errors being reported from the SoC
uncore to IEH and not propogated to SG unit. Clear all previous
SoC errors post warm reset.

Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
 drivers/gpu/drm/xe/xe_hw_error.c | 37 ++++++++++++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_hw_error.h |  1 +
 drivers/gpu/drm/xe/xe_irq.c      |  1 +
 3 files changed, 39 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
index 0bcb1bea7ffb..a777c887a7be 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.c
+++ b/drivers/gpu/drm/xe/xe_hw_error.c
@@ -366,6 +366,43 @@ static void xe_assign_hw_err_regs(struct xe_device *xe)
 	}
 }
 
+void xe_clear_all_soc_errors(struct xe_device *xe)
+{
+	enum hardware_error hw_err;
+	u32 base, slave_base;
+	struct xe_tile *tile;
+	struct xe_gt *gt;
+	unsigned int i;
+
+	base = SOC_PVC_BASE;
+	slave_base = SOC_PVC_SLAVE_BASE;
+
+	hw_err = HARDWARE_ERROR_CORRECTABLE;
+
+	for_each_tile(tile, xe, i) {
+		gt = tile->primary_gt;
+
+		while (hw_err < HARDWARE_ERROR_MAX) {
+			for (i = 0; i < PVC_NUM_IEH; i++)
+				xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base, i),
+						~REG_BIT(hw_err));
+
+			xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err),
+					REG_GENMASK(31, 0));
+			xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_MASTER_REG(base, hw_err),
+					REG_GENMASK(31, 0));
+			xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
+					REG_GENMASK(31, 0));
+			xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
+					REG_GENMASK(31, 0));
+			hw_err++;
+		}
+		for (i = 0; i < PVC_NUM_IEH; i++)
+			xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base, i),
+					(HARDWARE_ERROR_MAX << 1) + 1);
+	}
+}
+
 static void
 xe_gt_hw_error_status_reg_handler(struct xe_gt *gt, const enum hardware_error hw_err)
 {
diff --git a/drivers/gpu/drm/xe/xe_hw_error.h b/drivers/gpu/drm/xe/xe_hw_error.h
index a458a90b34a2..7ada7c97c939 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.h
+++ b/drivers/gpu/drm/xe/xe_hw_error.h
@@ -219,4 +219,5 @@ struct xe_tile;
 void xe_hw_error_irq_handler(struct xe_tile *tile, const u32 master_ctl);
 void xe_process_hw_errors(struct xe_device *xe);
 void xe_gsc_hw_error_work(struct work_struct *work);
+void xe_clear_all_soc_errors(struct xe_device *xe);
 #endif
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index 285c657cc789..42a6bb45acba 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -597,6 +597,7 @@ int xe_irq_install(struct xe_device *xe)
 	}
 
 	xe_process_hw_errors(xe);
+	xe_clear_all_soc_errors(xe);
 
 	xe->irq.enabled = true;
 
-- 
2.25.1

Re: [Intel-xe] [PATCH 11/11] drm/xe: Clear all SoC errors post warm reset.

[Aravind Iddamsetty]

On 27/09/23 17:16, Himal Prasad Ghimiray wrote:
> There are scenarios where there are no fatal errors reported
> but Non-fatal/correctable errors being reported from the SoC
> uncore to IEH and not propogated to SG unit. Clear all previous
> SoC errors post warm reset.

the commit msg is not very clear, how fatal error reporting is related to other errors.

Thanks,
Aravind.
>
> Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_hw_error.c | 37 ++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/xe/xe_hw_error.h |  1 +
>  drivers/gpu/drm/xe/xe_irq.c      |  1 +
>  3 files changed, 39 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
> index 0bcb1bea7ffb..a777c887a7be 100644
> --- a/drivers/gpu/drm/xe/xe_hw_error.c
> +++ b/drivers/gpu/drm/xe/xe_hw_error.c
> @@ -366,6 +366,43 @@ static void xe_assign_hw_err_regs(struct xe_device *xe)
>  	}
>  }
>  
> +void xe_clear_all_soc_errors(struct xe_device *xe)
> +{
> +	enum hardware_error hw_err;
> +	u32 base, slave_base;
> +	struct xe_tile *tile;
> +	struct xe_gt *gt;
> +	unsigned int i;
> +
> +	base = SOC_PVC_BASE;
> +	slave_base = SOC_PVC_SLAVE_BASE;
> +
> +	hw_err = HARDWARE_ERROR_CORRECTABLE;
> +
> +	for_each_tile(tile, xe, i) {
> +		gt = tile->primary_gt;
> +
> +		while (hw_err < HARDWARE_ERROR_MAX) {
> +			for (i = 0; i < PVC_NUM_IEH; i++)
> +				xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base, i),
> +						~REG_BIT(hw_err));
> +
> +			xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err),
> +					REG_GENMASK(31, 0));
> +			xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_MASTER_REG(base, hw_err),
> +					REG_GENMASK(31, 0));
> +			xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
> +					REG_GENMASK(31, 0));
> +			xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
> +					REG_GENMASK(31, 0));
> +			hw_err++;
> +		}
> +		for (i = 0; i < PVC_NUM_IEH; i++)
> +			xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base, i),
> +					(HARDWARE_ERROR_MAX << 1) + 1);
> +	}
> +}
> +
>  static void
>  xe_gt_hw_error_status_reg_handler(struct xe_gt *gt, const enum hardware_error hw_err)
>  {
> diff --git a/drivers/gpu/drm/xe/xe_hw_error.h b/drivers/gpu/drm/xe/xe_hw_error.h
> index a458a90b34a2..7ada7c97c939 100644
> --- a/drivers/gpu/drm/xe/xe_hw_error.h
> +++ b/drivers/gpu/drm/xe/xe_hw_error.h
> @@ -219,4 +219,5 @@ struct xe_tile;
>  void xe_hw_error_irq_handler(struct xe_tile *tile, const u32 master_ctl);
>  void xe_process_hw_errors(struct xe_device *xe);
>  void xe_gsc_hw_error_work(struct work_struct *work);
> +void xe_clear_all_soc_errors(struct xe_device *xe);
>  #endif
> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> index 285c657cc789..42a6bb45acba 100644
> --- a/drivers/gpu/drm/xe/xe_irq.c
> +++ b/drivers/gpu/drm/xe/xe_irq.c
> @@ -597,6 +597,7 @@ int xe_irq_install(struct xe_device *xe)
>  	}
>  
>  	xe_process_hw_errors(xe);
> +	xe_clear_all_soc_errors(xe);
>  
>  	xe->irq.enabled = true;
>  

Re: [Intel-xe] [PATCH 11/11] drm/xe: Clear all SoC errors post warm reset.

[Ghimiray, Himal Prasad]

On 11-10-2023 12:26, Aravind Iddamsetty wrote:
> On 27/09/23 17:16, Himal Prasad Ghimiray wrote:
>> There are scenarios where there are no fatal errors reported
>> but Non-fatal/correctable errors being reported from the SoC
>> uncore to IEH and not propogated to SG unit. Clear all previous
>> SoC errors post warm reset.
> the commit msg is not very clear, how fatal error reporting is related to other errors.
Will rephrase it as

There are scenarios where there are errors being reported from the SoC
uncore to IEH and not propagated to SG unit. Since these errors are not propagated to SG unit,
driver wont be able to clean them as part of xe_process_hw_error. Hence clear all SoC register post
xe_process_hw_error.

Is it ok ?

>
> Thanks,
> Aravind.
>> Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
>> ---
>>   drivers/gpu/drm/xe/xe_hw_error.c | 37 ++++++++++++++++++++++++++++++++
>>   drivers/gpu/drm/xe/xe_hw_error.h |  1 +
>>   drivers/gpu/drm/xe/xe_irq.c      |  1 +
>>   3 files changed, 39 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
>> index 0bcb1bea7ffb..a777c887a7be 100644
>> --- a/drivers/gpu/drm/xe/xe_hw_error.c
>> +++ b/drivers/gpu/drm/xe/xe_hw_error.c
>> @@ -366,6 +366,43 @@ static void xe_assign_hw_err_regs(struct xe_device *xe)
>>   	}
>>   }
>>   
>> +void xe_clear_all_soc_errors(struct xe_device *xe)
>> +{
>> +	enum hardware_error hw_err;
>> +	u32 base, slave_base;
>> +	struct xe_tile *tile;
>> +	struct xe_gt *gt;
>> +	unsigned int i;
>> +
>> +	base = SOC_PVC_BASE;
>> +	slave_base = SOC_PVC_SLAVE_BASE;
>> +
>> +	hw_err = HARDWARE_ERROR_CORRECTABLE;
>> +
>> +	for_each_tile(tile, xe, i) {
>> +		gt = tile->primary_gt;
>> +
>> +		while (hw_err < HARDWARE_ERROR_MAX) {
>> +			for (i = 0; i < PVC_NUM_IEH; i++)
>> +				xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base, i),
>> +						~REG_BIT(hw_err));
>> +
>> +			xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err),
>> +					REG_GENMASK(31, 0));
>> +			xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_MASTER_REG(base, hw_err),
>> +					REG_GENMASK(31, 0));
>> +			xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
>> +					REG_GENMASK(31, 0));
>> +			xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
>> +					REG_GENMASK(31, 0));
>> +			hw_err++;
>> +		}
>> +		for (i = 0; i < PVC_NUM_IEH; i++)
>> +			xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base, i),
>> +					(HARDWARE_ERROR_MAX << 1) + 1);
>> +	}
>> +}
>> +
>>   static void
>>   xe_gt_hw_error_status_reg_handler(struct xe_gt *gt, const enum hardware_error hw_err)
>>   {
>> diff --git a/drivers/gpu/drm/xe/xe_hw_error.h b/drivers/gpu/drm/xe/xe_hw_error.h
>> index a458a90b34a2..7ada7c97c939 100644
>> --- a/drivers/gpu/drm/xe/xe_hw_error.h
>> +++ b/drivers/gpu/drm/xe/xe_hw_error.h
>> @@ -219,4 +219,5 @@ struct xe_tile;
>>   void xe_hw_error_irq_handler(struct xe_tile *tile, const u32 master_ctl);
>>   void xe_process_hw_errors(struct xe_device *xe);
>>   void xe_gsc_hw_error_work(struct work_struct *work);
>> +void xe_clear_all_soc_errors(struct xe_device *xe);
>>   #endif
>> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
>> index 285c657cc789..42a6bb45acba 100644
>> --- a/drivers/gpu/drm/xe/xe_irq.c
>> +++ b/drivers/gpu/drm/xe/xe_irq.c
>> @@ -597,6 +597,7 @@ int xe_irq_install(struct xe_device *xe)
>>   	}
>>   
>>   	xe_process_hw_errors(xe);
>> +	xe_clear_all_soc_errors(xe);
>>   
>>   	xe->irq.enabled = true;
>>   

Re: [Intel-xe] [PATCH 11/11] drm/xe: Clear all SoC errors post warm reset.

[Aravind Iddamsetty]

On 11/10/23 12:29, Ghimiray, Himal Prasad wrote:
>
> On 11-10-2023 12:26, Aravind Iddamsetty wrote:
>> On 27/09/23 17:16, Himal Prasad Ghimiray wrote:
>>> There are scenarios where there are no fatal errors reported
>>> but Non-fatal/correctable errors being reported from the SoC
>>> uncore to IEH and not propogated to SG unit. Clear all previous
>>> SoC errors post warm reset.
>> the commit msg is not very clear, how fatal error reporting is related to other errors.
> Will rephrase it as
>
> There are scenarios where there are errors being reported from the SoC
> uncore to IEH and not propagated to SG unit. Since these errors are not propagated to SG unit,
> driver wont be able to clean them as part of xe_process_hw_error. Hence clear all SoC register post
> xe_process_hw_error.
>
the scenario this patch address is only during boot up so let's mention that.

Thanks,

Aravind.

> Is it ok ?
>
>>
>> Thanks,
>> Aravind.
>>> Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
>>> ---
>>>   drivers/gpu/drm/xe/xe_hw_error.c | 37 ++++++++++++++++++++++++++++++++
>>>   drivers/gpu/drm/xe/xe_hw_error.h |  1 +
>>>   drivers/gpu/drm/xe/xe_irq.c      |  1 +
>>>   3 files changed, 39 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
>>> index 0bcb1bea7ffb..a777c887a7be 100644
>>> --- a/drivers/gpu/drm/xe/xe_hw_error.c
>>> +++ b/drivers/gpu/drm/xe/xe_hw_error.c
>>> @@ -366,6 +366,43 @@ static void xe_assign_hw_err_regs(struct xe_device *xe)
>>>       }
>>>   }
>>>   +void xe_clear_all_soc_errors(struct xe_device *xe)
>>> +{
>>> +    enum hardware_error hw_err;
>>> +    u32 base, slave_base;
>>> +    struct xe_tile *tile;
>>> +    struct xe_gt *gt;
>>> +    unsigned int i;
>>> +
>>> +    base = SOC_PVC_BASE;
>>> +    slave_base = SOC_PVC_SLAVE_BASE;
>>> +
>>> +    hw_err = HARDWARE_ERROR_CORRECTABLE;
>>> +
>>> +    for_each_tile(tile, xe, i) {
>>> +        gt = tile->primary_gt;
>>> +
>>> +        while (hw_err < HARDWARE_ERROR_MAX) {
>>> +            for (i = 0; i < PVC_NUM_IEH; i++)
>>> +                xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base, i),
>>> +                        ~REG_BIT(hw_err));
>>> +
>>> +            xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err),
>>> +                    REG_GENMASK(31, 0));
>>> +            xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_MASTER_REG(base, hw_err),
>>> +                    REG_GENMASK(31, 0));
>>> +            xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
>>> +                    REG_GENMASK(31, 0));
>>> +            xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
>>> +                    REG_GENMASK(31, 0));
>>> +            hw_err++;
>>> +        }
>>> +        for (i = 0; i < PVC_NUM_IEH; i++)
>>> +            xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base, i),
>>> +                    (HARDWARE_ERROR_MAX << 1) + 1);
>>> +    }
>>> +}
>>> +
>>>   static void
>>>   xe_gt_hw_error_status_reg_handler(struct xe_gt *gt, const enum hardware_error hw_err)
>>>   {
>>> diff --git a/drivers/gpu/drm/xe/xe_hw_error.h b/drivers/gpu/drm/xe/xe_hw_error.h
>>> index a458a90b34a2..7ada7c97c939 100644
>>> --- a/drivers/gpu/drm/xe/xe_hw_error.h
>>> +++ b/drivers/gpu/drm/xe/xe_hw_error.h
>>> @@ -219,4 +219,5 @@ struct xe_tile;
>>>   void xe_hw_error_irq_handler(struct xe_tile *tile, const u32 master_ctl);
>>>   void xe_process_hw_errors(struct xe_device *xe);
>>>   void xe_gsc_hw_error_work(struct work_struct *work);
>>> +void xe_clear_all_soc_errors(struct xe_device *xe);
>>>   #endif
>>> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
>>> index 285c657cc789..42a6bb45acba 100644
>>> --- a/drivers/gpu/drm/xe/xe_irq.c
>>> +++ b/drivers/gpu/drm/xe/xe_irq.c
>>> @@ -597,6 +597,7 @@ int xe_irq_install(struct xe_device *xe)
>>>       }
>>>         xe_process_hw_errors(xe);
>>> +    xe_clear_all_soc_errors(xe);
>>>         xe->irq.enabled = true;
>>>   

[Intel-xe] ✓ CI.Build: success for Supporting CSC and SOC HARDWARE ERROR HANDLING on PVC

[Patchwork]

== Series Details ==

Series: Supporting CSC and SOC HARDWARE ERROR HANDLING on PVC
URL   : https://patchwork.freedesktop.org/series/124331/
State : success

== Summary ==

+ trap cleanup EXIT
+ cd /kernel
+ git clone https://gitlab.freedesktop.org/drm/xe/ci.git .ci
Cloning into '.ci'...
++ date +%s
^[[0Ksection_start:1695815092:build_x86_64[collapsed=true]
^[[0KBuild x86-64
+ echo -e '\e[0Ksection_start:1695815092:build_x86_64[collapsed=true]\r\e[0KBuild x86-64'
+ mkdir -p build64-default
+ cp .ci/kernel/kconfig build64-default/.config
+ make O=build64-default olddefconfig
make[1]: Entering directory '/kernel/build64-default'
  GEN     Makefile
  HOSTCC  scripts/basic/fixdep
  HOSTCC  scripts/kconfig/conf.o
  HOSTCC  scripts/kconfig/confdata.o
  HOSTCC  scripts/kconfig/expr.o
  LEX     scripts/kconfig/lexer.lex.c
  YACC    scripts/kconfig/parser.tab.[ch]
  HOSTCC  scripts/kconfig/lexer.lex.o
  HOSTCC  scripts/kconfig/menu.o
  HOSTCC  scripts/kconfig/parser.tab.o
  HOSTCC  scripts/kconfig/preprocess.o
  HOSTCC  scripts/kconfig/symbol.o
  HOSTCC  scripts/kconfig/util.o
  HOSTLD  scripts/kconfig/conf
#
# configuration written to .config
#
make[1]: Leaving directory '/kernel/build64-default'
++ nproc
+ make O=build64-default -j48
make[1]: Entering directory '/kernel/build64-default'
  GEN     Makefile
  WRAP    arch/x86/include/generated/uapi/asm/bpf_perf_event.h
  WRAP    arch/x86/include/generated/uapi/asm/errno.h
  SYSHDR  arch/x86/include/generated/uapi/asm/unistd_32.h
  WRAP    arch/x86/include/generated/uapi/asm/fcntl.h
  WRAP    arch/x86/include/generated/uapi/asm/ioctl.h
  GEN     arch/x86/include/generated/asm/orc_hash.h
  SYSHDR  arch/x86/include/generated/uapi/asm/unistd_64.h
  WRAP    arch/x86/include/generated/uapi/asm/ioctls.h
  SYSHDR  arch/x86/include/generated/uapi/asm/unistd_x32.h
  SYSTBL  arch/x86/include/generated/asm/syscalls_32.h
  WRAP    arch/x86/include/generated/uapi/asm/ipcbuf.h
  SYSHDR  arch/x86/include/generated/asm/unistd_32_ia32.h
  WRAP    arch/x86/include/generated/uapi/asm/param.h
  SYSHDR  arch/x86/include/generated/asm/unistd_64_x32.h
  SYSTBL  arch/x86/include/generated/asm/syscalls_64.h
  WRAP    arch/x86/include/generated/uapi/asm/poll.h
  WRAP    arch/x86/include/generated/uapi/asm/resource.h
  WRAP    arch/x86/include/generated/uapi/asm/socket.h
  WRAP    arch/x86/include/generated/uapi/asm/sockios.h
  WRAP    arch/x86/include/generated/uapi/asm/termbits.h
  WRAP    arch/x86/include/generated/uapi/asm/types.h
  WRAP    arch/x86/include/generated/uapi/asm/termios.h
  HOSTCC  arch/x86/tools/relocs_32.o
  HOSTCC  arch/x86/tools/relocs_64.o
  HOSTCC  arch/x86/tools/relocs_common.o
  WRAP    arch/x86/include/generated/asm/early_ioremap.h
  WRAP    arch/x86/include/generated/asm/export.h
  WRAP    arch/x86/include/generated/asm/mcs_spinlock.h
  WRAP    arch/x86/include/generated/asm/irq_regs.h
  WRAP    arch/x86/include/generated/asm/kmap_size.h
  WRAP    arch/x86/include/generated/asm/local64.h
  WRAP    arch/x86/include/generated/asm/mmiowb.h
  UPD     include/generated/uapi/linux/version.h
  WRAP    arch/x86/include/generated/asm/module.lds.h
  WRAP    arch/x86/include/generated/asm/rwonce.h
  WRAP    arch/x86/include/generated/asm/unaligned.h
  UPD     include/config/kernel.release
  UPD     include/generated/compile.h
  HOSTCC  scripts/kallsyms
  HOSTCC  scripts/sorttable
  HOSTCC  scripts/asn1_compiler
  HOSTCC  scripts/unifdef
  UPD     include/generated/utsrelease.h
  DESCEND objtool
  HOSTCC  /kernel/build64-default/tools/objtool/fixdep.o
  HOSTLD  /kernel/build64-default/tools/objtool/fixdep-in.o
  LINK    /kernel/build64-default/tools/objtool/fixdep
  INSTALL /kernel/build64-default/tools/objtool/libsubcmd/include/subcmd/exec-cmd.h
  INSTALL /kernel/build64-default/tools/objtool/libsubcmd/include/subcmd/help.h
  INSTALL /kernel/build64-default/tools/objtool/libsubcmd/include/subcmd/pager.h
  INSTALL /kernel/build64-default/tools/objtool/libsubcmd/include/subcmd/parse-options.h
  INSTALL /kernel/build64-default/tools/objtool/libsubcmd/include/subcmd/run-command.h
  CC      /kernel/build64-default/tools/objtool/libsubcmd/exec-cmd.o
  CC      /kernel/build64-default/tools/objtool/libsubcmd/help.o
  HOSTLD  arch/x86/tools/relocs
  INSTALL libsubcmd_headers
  CC      /kernel/build64-default/tools/objtool/libsubcmd/pager.o
  CC      /kernel/build64-default/tools/objtool/libsubcmd/parse-options.o
  CC      /kernel/build64-default/tools/objtool/libsubcmd/run-command.o
  CC      /kernel/build64-default/tools/objtool/libsubcmd/subcmd-config.o
  CC      /kernel/build64-default/tools/objtool/libsubcmd/sigchain.o
  CC      scripts/mod/empty.o
  HOSTCC  scripts/mod/mk_elfconfig
  CC      scripts/mod/devicetable-offsets.s
  HDRINST usr/include/video/edid.h
  HDRINST usr/include/video/sisfb.h
  HDRINST usr/include/video/uvesafb.h
  HDRINST usr/include/drm/amdgpu_drm.h
  HDRINST usr/include/drm/qaic_accel.h
  HDRINST usr/include/drm/i915_drm.h
  HDRINST usr/include/drm/vgem_drm.h
  HDRINST usr/include/drm/virtgpu_drm.h
  HDRINST usr/include/drm/xe_drm.h
  HDRINST usr/include/drm/omap_drm.h
  HDRINST usr/include/drm/radeon_drm.h
  HDRINST usr/include/drm/tegra_drm.h
  HDRINST usr/include/drm/drm_mode.h
  HDRINST usr/include/drm/ivpu_accel.h
  HDRINST usr/include/drm/exynos_drm.h
  HDRINST usr/include/drm/drm_sarea.h
  HDRINST usr/include/drm/v3d_drm.h
  HDRINST usr/include/drm/qxl_drm.h
  HDRINST usr/include/drm/drm_fourcc.h
  HDRINST usr/include/drm/nouveau_drm.h
  HDRINST usr/include/drm/habanalabs_accel.h
  HDRINST usr/include/drm/vmwgfx_drm.h
  HDRINST usr/include/drm/etnaviv_drm.h
  HDRINST usr/include/drm/msm_drm.h
  HDRINST usr/include/drm/vc4_drm.h
  HDRINST usr/include/drm/panfrost_drm.h
  HDRINST usr/include/drm/lima_drm.h
  HDRINST usr/include/drm/armada_drm.h
  HDRINST usr/include/drm/drm.h
  HDRINST usr/include/mtd/inftl-user.h
  UPD     scripts/mod/devicetable-offsets.h
  HDRINST usr/include/mtd/nftl-user.h
  HDRINST usr/include/mtd/mtd-user.h
  HDRINST usr/include/mtd/ubi-user.h
  HDRINST usr/include/mtd/mtd-abi.h
  HDRINST usr/include/xen/gntdev.h
  HDRINST usr/include/xen/gntalloc.h
  HDRINST usr/include/xen/evtchn.h
  HDRINST usr/include/xen/privcmd.h
  HDRINST usr/include/asm-generic/auxvec.h
  HDRINST usr/include/asm-generic/bitsperlong.h
  HDRINST usr/include/asm-generic/posix_types.h
  HDRINST usr/include/asm-generic/ioctls.h
  HDRINST usr/include/asm-generic/mman.h
  HDRINST usr/include/asm-generic/shmbuf.h
  HDRINST usr/include/asm-generic/bpf_perf_event.h
  HDRINST usr/include/asm-generic/types.h
  HDRINST usr/include/asm-generic/poll.h
  HDRINST usr/include/asm-generic/msgbuf.h
  HDRINST usr/include/asm-generic/swab.h
  HDRINST usr/include/asm-generic/statfs.h
  HDRINST usr/include/asm-generic/unistd.h
  HDRINST usr/include/asm-generic/hugetlb_encode.h
  HDRINST usr/include/asm-generic/resource.h
  HDRINST usr/include/asm-generic/param.h
  HDRINST usr/include/asm-generic/termbits-common.h
  HDRINST usr/include/asm-generic/sockios.h
  HDRINST usr/include/asm-generic/kvm_para.h
  HDRINST usr/include/asm-generic/errno.h
  HDRINST usr/include/asm-generic/termios.h
  HDRINST usr/include/asm-generic/mman-common.h
  HDRINST usr/include/asm-generic/ioctl.h
  HDRINST usr/include/asm-generic/socket.h
  HDRINST usr/include/asm-generic/signal-defs.h
  HDRINST usr/include/asm-generic/termbits.h
  HDRINST usr/include/asm-generic/int-ll64.h
  HDRINST usr/include/asm-generic/signal.h
  HDRINST usr/include/asm-generic/siginfo.h
  HDRINST usr/include/asm-generic/stat.h
  HDRINST usr/include/asm-generic/int-l64.h
  HDRINST usr/include/asm-generic/errno-base.h
  HDRINST usr/include/asm-generic/fcntl.h
  HDRINST usr/include/asm-generic/setup.h
  HDRINST usr/include/asm-generic/ipcbuf.h
  HDRINST usr/include/asm-generic/sembuf.h
  MKELF   scripts/mod/elfconfig.h
  HDRINST usr/include/asm-generic/ucontext.h
  HDRINST usr/include/rdma/mlx5_user_ioctl_cmds.h
  HDRINST usr/include/rdma/irdma-abi.h
  HDRINST usr/include/rdma/mana-abi.h
  HOSTCC  scripts/mod/modpost.o
  HDRINST usr/include/rdma/hfi/hfi1_user.h
  HOSTCC  scripts/mod/file2alias.o
  HDRINST usr/include/rdma/hfi/hfi1_ioctl.h
  HDRINST usr/include/rdma/rdma_user_rxe.h
  HOSTCC  scripts/mod/sumversion.o
  HDRINST usr/include/rdma/rdma_user_ioctl.h
  HDRINST usr/include/rdma/mlx5_user_ioctl_verbs.h
  HDRINST usr/include/rdma/bnxt_re-abi.h
  HDRINST usr/include/rdma/hns-abi.h
  HDRINST usr/include/rdma/qedr-abi.h
  HDRINST usr/include/rdma/ib_user_ioctl_cmds.h
  HDRINST usr/include/rdma/vmw_pvrdma-abi.h
  HDRINST usr/include/rdma/ib_user_sa.h
  HDRINST usr/include/rdma/ib_user_ioctl_verbs.h
  HDRINST usr/include/rdma/rvt-abi.h
  HDRINST usr/include/rdma/mlx5-abi.h
  HDRINST usr/include/rdma/rdma_netlink.h
  HDRINST usr/include/rdma/erdma-abi.h
  HDRINST usr/include/rdma/rdma_user_ioctl_cmds.h
  HDRINST usr/include/rdma/rdma_user_cm.h
  HDRINST usr/include/rdma/ib_user_verbs.h
  HDRINST usr/include/rdma/efa-abi.h
  HDRINST usr/include/rdma/siw-abi.h
  HDRINST usr/include/rdma/mlx4-abi.h
  HDRINST usr/include/rdma/mthca-abi.h
  HDRINST usr/include/rdma/ib_user_mad.h
  HDRINST usr/include/rdma/ocrdma-abi.h
  HDRINST usr/include/rdma/cxgb4-abi.h
  HDRINST usr/include/misc/xilinx_sdfec.h
  HDRINST usr/include/misc/uacce/hisi_qm.h
  HDRINST usr/include/misc/uacce/uacce.h
  HDRINST usr/include/misc/cxl.h
  HDRINST usr/include/misc/ocxl.h
  HDRINST usr/include/misc/fastrpc.h
  HDRINST usr/include/misc/pvpanic.h
  HDRINST usr/include/linux/i8k.h
  HDRINST usr/include/linux/acct.h
  HDRINST usr/include/linux/atmmpc.h
  HDRINST usr/include/linux/fs.h
  HDRINST usr/include/linux/cifs/cifs_netlink.h
  HDRINST usr/include/linux/cifs/cifs_mount.h
  HDRINST usr/include/linux/if_packet.h
  HDRINST usr/include/linux/route.h
  HDRINST usr/include/linux/patchkey.h
  HDRINST usr/include/linux/tc_ematch/tc_em_cmp.h
  HDRINST usr/include/linux/tc_ematch/tc_em_ipt.h
  HDRINST usr/include/linux/tc_ematch/tc_em_meta.h
  HDRINST usr/include/linux/tc_ematch/tc_em_nbyte.h
  HDRINST usr/include/linux/tc_ematch/tc_em_text.h
  HDRINST usr/include/linux/virtio_pmem.h
  HDRINST usr/include/linux/rkisp1-config.h
  HDRINST usr/include/linux/vhost.h
  HDRINST usr/include/linux/cec-funcs.h
  HDRINST usr/include/linux/ppdev.h
  HDRINST usr/include/linux/isdn/capicmd.h
  HDRINST usr/include/linux/virtio_fs.h
  HDRINST usr/include/linux/netfilter_ipv6.h
  HDRINST usr/include/linux/lirc.h
  HDRINST usr/include/linux/mroute6.h
  HDRINST usr/include/linux/nl80211-vnd-intel.h
  HDRINST usr/include/linux/ivtvfb.h
  HDRINST usr/include/linux/auxvec.h
  HDRINST usr/include/linux/dm-log-userspace.h
  HDRINST usr/include/linux/dccp.h
  HDRINST usr/include/linux/virtio_scmi.h
  HDRINST usr/include/linux/atmarp.h
  HDRINST usr/include/linux/arcfb.h
  HDRINST usr/include/linux/nbd-netlink.h
  HDRINST usr/include/linux/sched/types.h
  HDRINST usr/include/linux/tcp.h
  HDRINST usr/include/linux/neighbour.h
  HDRINST usr/include/linux/dlm_device.h
  HDRINST usr/include/linux/wmi.h
  HDRINST usr/include/linux/btrfs_tree.h
  HDRINST usr/include/linux/virtio_crypto.h
  HDRINST usr/include/linux/vbox_err.h
  HDRINST usr/include/linux/edd.h
  HDRINST usr/include/linux/loop.h
  HDRINST usr/include/linux/nvme_ioctl.h
  HDRINST usr/include/linux/mmtimer.h
  HDRINST usr/include/linux/if_pppol2tp.h
  HDRINST usr/include/linux/mtio.h
  HDRINST usr/include/linux/if_arcnet.h
  HDRINST usr/include/linux/romfs_fs.h
  HDRINST usr/include/linux/posix_types.h
  HDRINST usr/include/linux/rtc.h
  HDRINST usr/include/linux/landlock.h
  HDRINST usr/include/linux/gpio.h
  HDRINST usr/include/linux/selinux_netlink.h
  HDRINST usr/include/linux/pps.h
  HDRINST usr/include/linux/ndctl.h
  HDRINST usr/include/linux/virtio_gpu.h
  HDRINST usr/include/linux/android/binderfs.h
  HDRINST usr/include/linux/android/binder.h
  HDRINST usr/include/linux/virtio_vsock.h
  HDRINST usr/include/linux/sound.h
  HDRINST usr/include/linux/vtpm_proxy.h
  HDRINST usr/include/linux/nfs_fs.h
  HDRINST usr/include/linux/elf-fdpic.h
  HDRINST usr/include/linux/adfs_fs.h
  HDRINST usr/include/linux/target_core_user.h
  HDRINST usr/include/linux/netlink_diag.h
  HDRINST usr/include/linux/const.h
  HDRINST usr/include/linux/firewire-cdev.h
  HDRINST usr/include/linux/vdpa.h
  HDRINST usr/include/linux/if_infiniband.h
  HDRINST usr/include/linux/serial.h
  HDRINST usr/include/linux/iio/types.h
  HDRINST usr/include/linux/iio/buffer.h
  HDRINST usr/include/linux/iio/events.h
  HDRINST usr/include/linux/major.h
  HDRINST usr/include/linux/baycom.h
  HDRINST usr/include/linux/atmppp.h
  HDRINST usr/include/linux/ipv6_route.h
  HDRINST usr/include/linux/spi/spidev.h
  HDRINST usr/include/linux/spi/spi.h
  HDRINST usr/include/linux/virtio_ring.h
  HDRINST usr/include/linux/hdlc/ioctl.h
  HDRINST usr/include/linux/remoteproc_cdev.h
  HDRINST usr/include/linux/hyperv.h
  HDRINST usr/include/linux/rpl_iptunnel.h
  HDRINST usr/include/linux/sync_file.h
  HDRINST usr/include/linux/igmp.h
  HDRINST usr/include/linux/v4l2-dv-timings.h
  HDRINST usr/include/linux/virtio_i2c.h
  HDRINST usr/include/linux/xfrm.h
  HDRINST usr/include/linux/capability.h
  HDRINST usr/include/linux/gtp.h
  HDRINST usr/include/linux/xdp_diag.h
  HDRINST usr/include/linux/pkt_cls.h
  HDRINST usr/include/linux/suspend_ioctls.h
  HDRINST usr/include/linux/vt.h
  HDRINST usr/include/linux/loadpin.h
  HDRINST usr/include/linux/dlm_plock.h
  HDRINST usr/include/linux/fb.h
  HDRINST usr/include/linux/max2175.h
  HDRINST usr/include/linux/sunrpc/debug.h
  HDRINST usr/include/linux/gsmmux.h
  HDRINST usr/include/linux/watchdog.h
  HDRINST usr/include/linux/vhost_types.h
  HDRINST usr/include/linux/vduse.h
  HDRINST usr/include/linux/ila.h
  HDRINST usr/include/linux/tdx-guest.h
  HDRINST usr/include/linux/close_range.h
  HDRINST usr/include/linux/ivtv.h
  HDRINST usr/include/linux/cryptouser.h
  HDRINST usr/include/linux/netfilter/xt_string.h
  HDRINST usr/include/linux/netfilter/nfnetlink_compat.h
  HDRINST usr/include/linux/netfilter/nf_nat.h
  HDRINST usr/include/linux/netfilter/xt_recent.h
  HDRINST usr/include/linux/netfilter/xt_addrtype.h
  HDRINST usr/include/linux/netfilter/nf_conntrack_tcp.h
  HDRINST usr/include/linux/netfilter/xt_MARK.h
  HDRINST usr/include/linux/netfilter/xt_SYNPROXY.h
  HDRINST usr/include/linux/netfilter/xt_multiport.h
  HDRINST usr/include/linux/netfilter/nfnetlink.h
  HDRINST usr/include/linux/netfilter/xt_cgroup.h
  HDRINST usr/include/linux/netfilter/nf_synproxy.h
  HDRINST usr/include/linux/netfilter/xt_TCPOPTSTRIP.h
  HDRINST usr/include/linux/netfilter/nfnetlink_log.h
  HDRINST usr/include/linux/netfilter/xt_TPROXY.h
  HDRINST usr/include/linux/netfilter/xt_u32.h
  HDRINST usr/include/linux/netfilter/nfnetlink_osf.h
  HDRINST usr/include/linux/netfilter/xt_ecn.h
  HDRINST usr/include/linux/netfilter/xt_esp.h
  HDRINST usr/include/linux/netfilter/nfnetlink_hook.h
  HDRINST usr/include/linux/netfilter/xt_mac.h
  HDRINST usr/include/linux/netfilter/xt_NFQUEUE.h
  HDRINST usr/include/linux/netfilter/xt_comment.h
  HDRINST usr/include/linux/netfilter/xt_osf.h
  HDRINST usr/include/linux/netfilter/xt_hashlimit.h
  HDRINST usr/include/linux/netfilter/nf_conntrack_sctp.h
  HDRINST usr/include/linux/netfilter/xt_socket.h
  HDRINST usr/include/linux/netfilter/xt_connmark.h
  HDRINST usr/include/linux/netfilter/xt_sctp.h
  HDRINST usr/include/linux/netfilter/xt_tcpudp.h
  HDRINST usr/include/linux/netfilter/xt_DSCP.h
  HDRINST usr/include/linux/netfilter/xt_time.h
  HDRINST usr/include/linux/netfilter/xt_IDLETIMER.h
  HDRINST usr/include/linux/netfilter/xt_policy.h
  HDRINST usr/include/linux/netfilter/xt_rpfilter.h
  HDRINST usr/include/linux/netfilter/xt_nfacct.h
  HDRINST usr/include/linux/netfilter/xt_SECMARK.h
  HDRINST usr/include/linux/netfilter/xt_length.h
  HDRINST usr/include/linux/netfilter/nfnetlink_cthelper.h
  HDRINST usr/include/linux/netfilter/xt_quota.h
  HDRINST usr/include/linux/netfilter/xt_CLASSIFY.h
  HDRINST usr/include/linux/netfilter/xt_ipcomp.h
  HDRINST usr/include/linux/netfilter/xt_iprange.h
  HDRINST usr/include/linux/netfilter/xt_bpf.h
  HDRINST usr/include/linux/netfilter/xt_LOG.h
  HDRINST usr/include/linux/netfilter/xt_rateest.h
  HDRINST usr/include/linux/netfilter/xt_CONNSECMARK.h
  HDRINST usr/include/linux/netfilter/xt_HMARK.h
  HDRINST usr/include/linux/netfilter/xt_CONNMARK.h
  HDRINST usr/include/linux/netfilter/xt_pkttype.h
  HDRINST usr/include/linux/netfilter/xt_devgroup.h
  HDRINST usr/include/linux/netfilter/xt_ipvs.h
  HDRINST usr/include/linux/netfilter/xt_realm.h
  HDRINST usr/include/linux/netfilter/xt_AUDIT.h
  HDRINST usr/include/linux/netfilter/nf_conntrack_common.h
  HDRINST usr/include/linux/netfilter/xt_set.h
  HDRINST usr/include/linux/netfilter/xt_LED.h
  HDRINST usr/include/linux/netfilter/xt_connlabel.h
  HDRINST usr/include/linux/netfilter/xt_owner.h
  HDRINST usr/include/linux/netfilter/xt_dccp.h
  HDRINST usr/include/linux/netfilter/xt_limit.h
  HDRINST usr/include/linux/netfilter/xt_conntrack.h
  HDRINST usr/include/linux/netfilter/xt_TEE.h
  HDRINST usr/include/linux/netfilter/xt_RATEEST.h
  HDRINST usr/include/linux/netfilter/xt_connlimit.h
  HDRINST usr/include/linux/netfilter/ipset/ip_set.h
  HDRINST usr/include/linux/netfilter/ipset/ip_set_list.h
  HDRINST usr/include/linux/netfilter/ipset/ip_set_hash.h
  HDRINST usr/include/linux/netfilter/ipset/ip_set_bitmap.h
  HDRINST usr/include/linux/netfilter/x_tables.h
  HDRINST usr/include/linux/netfilter/xt_dscp.h
  HDRINST usr/include/linux/netfilter/nf_conntrack_ftp.h
  HDRINST usr/include/linux/netfilter/xt_cluster.h
  HDRINST usr/include/linux/netfilter/nf_conntrack_tuple_common.h
  HDRINST usr/include/linux/netfilter/nf_log.h
  HDRINST usr/include/linux/netfilter/xt_tcpmss.h
  HDRINST usr/include/linux/netfilter/xt_NFLOG.h
  HDRINST usr/include/linux/netfilter/xt_l2tp.h
  HDRINST usr/include/linux/netfilter/xt_helper.h
  HDRINST usr/include/linux/netfilter/xt_statistic.h
  HDRINST usr/include/linux/netfilter/nfnetlink_queue.h
  HDRINST usr/include/linux/netfilter/nfnetlink_cttimeout.h
  HDRINST usr/include/linux/netfilter/xt_CT.h
  HDRINST usr/include/linux/netfilter/xt_CHECKSUM.h
  HDRINST usr/include/linux/netfilter/xt_connbytes.h
  HDRINST usr/include/linux/netfilter/xt_state.h
  HDRINST usr/include/linux/netfilter/nf_tables.h
  HDRINST usr/include/linux/netfilter/xt_mark.h
  HDRINST usr/include/linux/netfilter/xt_cpu.h
  HDRINST usr/include/linux/netfilter/nf_tables_compat.h
  HDRINST usr/include/linux/netfilter/xt_physdev.h
  HDRINST usr/include/linux/netfilter/nfnetlink_conntrack.h
  HDRINST usr/include/linux/netfilter/nfnetlink_acct.h
  HDRINST usr/include/linux/netfilter/xt_TCPMSS.h
  HDRINST usr/include/linux/tty_flags.h
  HDRINST usr/include/linux/if_phonet.h
  HDRINST usr/include/linux/elf-em.h
  HDRINST usr/include/linux/vm_sockets.h
  HDRINST usr/include/linux/dlmconstants.h
  HDRINST usr/include/linux/bsg.h
  HDRINST usr/include/linux/matroxfb.h
  HDRINST usr/include/linux/sysctl.h
  HDRINST usr/include/linux/unix_diag.h
  HDRINST usr/include/linux/pcitest.h
  HDRINST usr/include/linux/mman.h
  HDRINST usr/include/linux/if_plip.h
  HDRINST usr/include/linux/virtio_balloon.h
  HDRINST usr/include/linux/pidfd.h
  HDRINST usr/include/linux/f2fs.h
  HDRINST usr/include/linux/x25.h
  HDRINST usr/include/linux/if_cablemodem.h
  HDRINST usr/include/linux/utsname.h
  HDRINST usr/include/linux/counter.h
  HDRINST usr/include/linux/atm_tcp.h
  HDRINST usr/include/linux/atalk.h
  HDRINST usr/include/linux/virtio_rng.h
  HDRINST usr/include/linux/vboxguest.h
  HDRINST usr/include/linux/bpf_perf_event.h
  HDRINST usr/include/linux/ipmi_ssif_bmc.h
  HDRINST usr/include/linux/sonet.h
  HDRINST usr/include/linux/nfs_mount.h
  HDRINST usr/include/linux/netfilter.h
  HDRINST usr/include/linux/keyctl.h
  HDRINST usr/include/linux/nl80211.h
  HDRINST usr/include/linux/misc/bcm_vk.h
  HDRINST usr/include/linux/audit.h
  HDRINST usr/include/linux/tipc_config.h
  HDRINST usr/include/linux/tipc_sockets_diag.h
  HDRINST usr/include/linux/futex.h
  HDRINST usr/include/linux/sev-guest.h
  HDRINST usr/include/linux/ublk_cmd.h
  HDRINST usr/include/linux/types.h
  HDRINST usr/include/linux/virtio_input.h
  HDRINST usr/include/linux/if_slip.h
  HDRINST usr/include/linux/personality.h
  HDRINST usr/include/linux/openat2.h
  HDRINST usr/include/linux/poll.h
  HDRINST usr/include/linux/posix_acl.h
  HDRINST usr/include/linux/smc_diag.h
  HDRINST usr/include/linux/snmp.h
  HDRINST usr/include/linux/errqueue.h
  HDRINST usr/include/linux/if_tunnel.h
  HDRINST usr/include/linux/fanotify.h
  HDRINST usr/include/linux/kernel.h
  HDRINST usr/include/linux/rtnetlink.h
  HDRINST usr/include/linux/rpl.h
  HDRINST usr/include/linux/memfd.h
  HDRINST usr/include/linux/serial_core.h
  HDRINST usr/include/linux/dns_resolver.h
  HDRINST usr/include/linux/pr.h
  HDRINST usr/include/linux/atm_eni.h
  HDRINST usr/include/linux/lp.h
  HDRINST usr/include/linux/virtio_mem.h
  HDRINST usr/include/linux/ultrasound.h
  HDRINST usr/include/linux/sctp.h
  HDRINST usr/include/linux/uio.h
  HDRINST usr/include/linux/tcp_metrics.h
  HDRINST usr/include/linux/wwan.h
  HDRINST usr/include/linux/atmbr2684.h
  HDRINST usr/include/linux/in_route.h
  HDRINST usr/include/linux/qemu_fw_cfg.h
  HDRINST usr/include/linux/if_macsec.h
  HDRINST usr/include/linux/usb/charger.h
  HDRINST usr/include/linux/usb/g_uvc.h
  HDRINST usr/include/linux/usb/gadgetfs.h
  HDRINST usr/include/linux/usb/raw_gadget.h
  HDRINST usr/include/linux/usb/cdc-wdm.h
  HDRINST usr/include/linux/usb/g_printer.h
  HDRINST usr/include/linux/usb/midi.h
  HDRINST usr/include/linux/usb/tmc.h
  HDRINST usr/include/linux/usb/video.h
  HDRINST usr/include/linux/usb/functionfs.h
  HDRINST usr/include/linux/usb/audio.h
  HDRINST usr/include/linux/usb/ch11.h
  HDRINST usr/include/linux/usb/ch9.h
  HDRINST usr/include/linux/usb/cdc.h
  HDRINST usr/include/linux/jffs2.h
  HDRINST usr/include/linux/ax25.h
  HDRINST usr/include/linux/auto_fs.h
  HDRINST usr/include/linux/tiocl.h
  HDRINST usr/include/linux/scc.h
  HDRINST usr/include/linux/psci.h
  HDRINST usr/include/linux/swab.h
  HDRINST usr/include/linux/cec.h
  HDRINST usr/include/linux/kfd_ioctl.h
  HDRINST usr/include/linux/smc.h
  HDRINST usr/include/linux/qrtr.h
  HDRINST usr/include/linux/screen_info.h
  HDRINST usr/include/linux/nfsacl.h
  HDRINST usr/include/linux/seg6_hmac.h
  HDRINST usr/include/linux/gameport.h
  HDRINST usr/include/linux/wireless.h
  HDRINST usr/include/linux/fdreg.h
  HDRINST usr/include/linux/cciss_defs.h
  HDRINST usr/include/linux/serial_reg.h
  HDRINST usr/include/linux/perf_event.h
  HDRINST usr/include/linux/in6.h
  HDRINST usr/include/linux/hid.h
  HDRINST usr/include/linux/netlink.h
  HDRINST usr/include/linux/fuse.h
  HDRINST usr/include/linux/magic.h
  HDRINST usr/include/linux/ioam6_iptunnel.h
  HDRINST usr/include/linux/stm.h
  HDRINST usr/include/linux/vsockmon.h
  HDRINST usr/include/linux/seg6.h
  HDRINST usr/include/linux/idxd.h
  HDRINST usr/include/linux/nitro_enclaves.h
  HDRINST usr/include/linux/ptrace.h
  HDRINST usr/include/linux/ioam6_genl.h
  HDRINST usr/include/linux/qnx4_fs.h
  HDRINST usr/include/linux/fsl_mc.h
  HDRINST usr/include/linux/net_tstamp.h
  HDRINST usr/include/linux/msg.h
  HDRINST usr/include/linux/netfilter_ipv4/ipt_TTL.h
  HDRINST usr/include/linux/netfilter_ipv4/ipt_ttl.h
  HDRINST usr/include/linux/netfilter_ipv4/ipt_ah.h
  HDRINST usr/include/linux/netfilter_ipv4/ipt_ECN.h
  HDRINST usr/include/linux/netfilter_ipv4/ip_tables.h
  HDRINST usr/include/linux/netfilter_ipv4/ipt_ecn.h
  HDRINST usr/include/linux/netfilter_ipv4/ipt_CLUSTERIP.h
  HDRINST usr/include/linux/netfilter_ipv4/ipt_REJECT.h
  HDRINST usr/include/linux/netfilter_ipv4/ipt_LOG.h
  HDRINST usr/include/linux/sem.h
  HDRINST usr/include/linux/net_namespace.h
  HDRINST usr/include/linux/radeonfb.h
  HDRINST usr/include/linux/tee.h
  HDRINST usr/include/linux/udp.h
  HDRINST usr/include/linux/virtio_bt.h
  HDRINST usr/include/linux/v4l2-subdev.h
  HDRINST usr/include/linux/posix_acl_xattr.h
  HDRINST usr/include/linux/v4l2-mediabus.h
  HDRINST usr/include/linux/atmapi.h
  HDRINST usr/include/linux/raid/md_p.h
  HDRINST usr/include/linux/raid/md_u.h
  HDRINST usr/include/linux/zorro_ids.h
  HDRINST usr/include/linux/nbd.h
  HDRINST usr/include/linux/isst_if.h
  HDRINST usr/include/linux/rxrpc.h
  HDRINST usr/include/linux/unistd.h
  HDRINST usr/include/linux/if_arp.h
  HDRINST usr/include/linux/atm_zatm.h
  HDRINST usr/include/linux/io_uring.h
  HDRINST usr/include/linux/if_fddi.h
  HDRINST usr/include/linux/bpqether.h
  HDRINST usr/include/linux/sysinfo.h
  HDRINST usr/include/linux/auto_dev-ioctl.h
  HDRINST usr/include/linux/nfs4_mount.h
  HDRINST usr/include/linux/keyboard.h
  HDRINST usr/include/linux/virtio_mmio.h
  HDRINST usr/include/linux/input.h
  HDRINST usr/include/linux/qnxtypes.h
  HDRINST usr/include/linux/mdio.h
  HDRINST usr/include/linux/lwtunnel.h
  HDRINST usr/include/linux/gfs2_ondisk.h
  HDRINST usr/include/linux/eventfd.h
  HDRINST usr/include/linux/nfs4.h
  HDRINST usr/include/linux/ptp_clock.h
  HDRINST usr/include/linux/nubus.h
  HDRINST usr/include/linux/if_bonding.h
  HDRINST usr/include/linux/kcov.h
  HDRINST usr/include/linux/fadvise.h
  HDRINST usr/include/linux/taskstats.h
  HDRINST usr/include/linux/veth.h
  HDRINST usr/include/linux/atm.h
  HDRINST usr/include/linux/ipmi.h
  HDRINST usr/include/linux/kdev_t.h
  HDRINST usr/include/linux/mount.h
  HDRINST usr/include/linux/shm.h
  HDRINST usr/include/linux/resource.h
  HDRINST usr/include/linux/prctl.h
  HDRINST usr/include/linux/watch_queue.h
  HDRINST usr/include/linux/sched.h
  HDRINST usr/include/linux/phonet.h
  HDRINST usr/include/linux/random.h
  HDRINST usr/include/linux/tty.h
  HDRINST usr/include/linux/apm_bios.h
  HDRINST usr/include/linux/fd.h
  HDRINST usr/include/linux/um_timetravel.h
  HDRINST usr/include/linux/tls.h
  HDRINST usr/include/linux/rpmsg_types.h
  HDRINST usr/include/linux/pfrut.h
  HDRINST usr/include/linux/mei.h
  HDRINST usr/include/linux/fsi.h
  HDRINST usr/include/linux/rds.h
  HDRINST usr/include/linux/if_x25.h
  HDRINST usr/include/linux/param.h
  HDRINST usr/include/linux/netdevice.h
  HDRINST usr/include/linux/binfmts.h
  HDRINST usr/include/linux/if_pppox.h
  HDRINST usr/include/linux/sockios.h
  HDRINST usr/include/linux/kcm.h
  HDRINST usr/include/linux/virtio_9p.h
  HDRINST usr/include/linux/genwqe/genwqe_card.h
  HDRINST usr/include/linux/if_tun.h
  HDRINST usr/include/linux/ext4.h
  HDRINST usr/include/linux/if_ether.h
  HDRINST usr/include/linux/kvm_para.h
  HDRINST usr/include/linux/kernel-page-flags.h
  HDRINST usr/include/linux/cdrom.h
  HDRINST usr/include/linux/un.h
  HDRINST usr/include/linux/module.h
  HDRINST usr/include/linux/mqueue.h
  HDRINST usr/include/linux/a.out.h
  HDRINST usr/include/linux/input-event-codes.h
  HDRINST usr/include/linux/coda.h
  HDRINST usr/include/linux/rio_mport_cdev.h
  HDRINST usr/include/linux/ipsec.h
  HDRINST usr/include/linux/blkpg.h
  HDRINST usr/include/linux/blkzoned.h
  HDRINST usr/include/linux/netfilter_bridge/ebt_arpreply.h
  HDRINST usr/include/linux/netfilter_bridge/ebt_redirect.h
  HDRINST usr/include/linux/netfilter_bridge/ebt_nflog.h
  HDRINST usr/include/linux/netfilter_bridge/ebt_802_3.h
  HDRINST usr/include/linux/netfilter_bridge/ebt_nat.h
  HDRINST usr/include/linux/netfilter_bridge/ebt_mark_m.h
  HDRINST usr/include/linux/netfilter_bridge/ebtables.h
  HDRINST usr/include/linux/netfilter_bridge/ebt_vlan.h
  HDRINST usr/include/linux/netfilter_bridge/ebt_limit.h
  HDRINST usr/include/linux/netfilter_bridge/ebt_log.h
  HDRINST usr/include/linux/netfilter_bridge/ebt_stp.h
  HDRINST usr/include/linux/netfilter_bridge/ebt_pkttype.h
  HDRINST usr/include/linux/netfilter_bridge/ebt_ip.h
  HDRINST usr/include/linux/netfilter_bridge/ebt_ip6.h
  HDRINST usr/include/linux/netfilter_bridge/ebt_mark_t.h
  HDRINST usr/include/linux/netfilter_bridge/ebt_arp.h
  HDRINST usr/include/linux/netfilter_bridge/ebt_among.h
  HDRINST usr/include/linux/reiserfs_fs.h
  HDRINST usr/include/linux/cciss_ioctl.h
  HDRINST usr/include/linux/fsmap.h
  HDRINST usr/include/linux/smiapp.h
  HDRINST usr/include/linux/switchtec_ioctl.h
  HDRINST usr/include/linux/atmdev.h
  HDRINST usr/include/linux/hpet.h
  HDRINST usr/include/linux/virtio_config.h
  HDRINST usr/include/linux/string.h
  HDRINST usr/include/linux/kfd_sysfs.h
  HDRINST usr/include/linux/inet_diag.h
  HDRINST usr/include/linux/netdev.h
  HDRINST usr/include/linux/xattr.h
  HDRINST usr/include/linux/iommufd.h
  HDRINST usr/include/linux/user_events.h
  HDRINST usr/include/linux/errno.h
  HDRINST usr/include/linux/icmp.h
  HDRINST usr/include/linux/i2o-dev.h
  HDRINST usr/include/linux/pg.h
  HDRINST usr/include/linux/if_bridge.h
  HDRINST usr/include/linux/thermal.h
  HDRINST usr/include/linux/uinput.h
  HDRINST usr/include/linux/handshake.h
  HDRINST usr/include/linux/dqblk_xfs.h
  HDRINST usr/include/linux/v4l2-common.h
  HDRINST usr/include/linux/nvram.h
  HDRINST usr/include/linux/if_vlan.h
  HDRINST usr/include/linux/uhid.h
  HDRINST usr/include/linux/omap3isp.h
  HDRINST usr/include/linux/rose.h
  HDRINST usr/include/linux/phantom.h
  HDRINST usr/include/linux/ipmi_msgdefs.h
  HDRINST usr/include/linux/bcm933xx_hcs.h
  HDRINST usr/include/linux/bpf.h
  HDRINST usr/include/linux/mempolicy.h
  HDRINST usr/include/linux/efs_fs_sb.h
  HDRINST usr/include/linux/nexthop.h
  HDRINST usr/include/linux/net_dropmon.h
  HDRINST usr/include/linux/surface_aggregator/cdev.h
  HDRINST usr/include/linux/surface_aggregator/dtx.h
  HDRINST usr/include/linux/net.h
  HDRINST usr/include/linux/mii.h
  HDRINST usr/include/linux/virtio_pcidev.h
  HDRINST usr/include/linux/termios.h
  HDRINST usr/include/linux/cgroupstats.h
  HDRINST usr/include/linux/mpls.h
  HDRINST usr/include/linux/iommu.h
  HDRINST usr/include/linux/toshiba.h
  HDRINST usr/include/linux/virtio_scsi.h
  HDRINST usr/include/linux/zorro.h
  LD      /kernel/build64-default/tools/objtool/libsubcmd/libsubcmd-in.o
  HDRINST usr/include/linux/chio.h
  HDRINST usr/include/linux/pkt_sched.h
  HDRINST usr/include/linux/cramfs_fs.h
  HDRINST usr/include/linux/nfs3.h
  HDRINST usr/include/linux/vfio_ccw.h
  HDRINST usr/include/linux/atm_nicstar.h
  HDRINST usr/include/linux/ncsi.h
  HDRINST usr/include/linux/virtio_net.h
  HDRINST usr/include/linux/ioctl.h
  HDRINST usr/include/linux/stddef.h
  HDRINST usr/include/linux/limits.h
  HDRINST usr/include/linux/ipmi_bmc.h
  HDRINST usr/include/linux/netfilter_arp.h
  HDRINST usr/include/linux/if_addr.h
  HDRINST usr/include/linux/rpmsg.h
  HDRINST usr/include/linux/media-bus-format.h
  HDRINST usr/include/linux/kernelcapi.h
  HDRINST usr/include/linux/ppp_defs.h
  HDRINST usr/include/linux/ethtool.h
  HDRINST usr/include/linux/aspeed-video.h
  HDRINST usr/include/linux/hdlc.h
  HDRINST usr/include/linux/fscrypt.h
  HDRINST usr/include/linux/batadv_packet.h
  HDRINST usr/include/linux/uuid.h
  HDRINST usr/include/linux/capi.h
  HDRINST usr/include/linux/mptcp.h
  HDRINST usr/include/linux/hidraw.h
  HDRINST usr/include/linux/virtio_console.h
  HDRINST usr/include/linux/irqnr.h
  HDRINST usr/include/linux/coresight-stm.h
  HDRINST usr/include/linux/cxl_mem.h
  AR      /kernel/build64-default/tools/objtool/libsubcmd/libsubcmd.a
  HDRINST usr/include/linux/iso_fs.h
  HDRINST usr/include/linux/virtio_blk.h
  HDRINST usr/include/linux/udf_fs_i.h
  HDRINST usr/include/linux/coff.h
  HDRINST usr/include/linux/ife.h
  HDRINST usr/include/linux/dma-buf.h
  HDRINST usr/include/linux/agpgart.h
  HDRINST usr/include/linux/socket.h
  HDRINST usr/include/linux/nilfs2_ondisk.h
  HDRINST usr/include/linux/connector.h
  HDRINST usr/include/linux/auto_fs4.h
  HDRINST usr/include/linux/bt-bmc.h
  HDRINST usr/include/linux/map_to_7segment.h
  HDRINST usr/include/linux/tc_act/tc_skbedit.h
  HDRINST usr/include/linux/tc_act/tc_ctinfo.h
  HDRINST usr/include/linux/tc_act/tc_defact.h
  HDRINST usr/include/linux/tc_act/tc_gact.h
  HDRINST usr/include/linux/tc_act/tc_vlan.h
  HDRINST usr/include/linux/tc_act/tc_skbmod.h
  HDRINST usr/include/linux/tc_act/tc_sample.h
  HDRINST usr/include/linux/tc_act/tc_tunnel_key.h
  HDRINST usr/include/linux/tc_act/tc_gate.h
  HDRINST usr/include/linux/tc_act/tc_mirred.h
  HDRINST usr/include/linux/tc_act/tc_nat.h
  HDRINST usr/include/linux/tc_act/tc_csum.h
  HDRINST usr/include/linux/tc_act/tc_connmark.h
  HDRINST usr/include/linux/tc_act/tc_ife.h
  HDRINST usr/include/linux/tc_act/tc_ct.h
  HDRINST usr/include/linux/tc_act/tc_mpls.h
  HDRINST usr/include/linux/tc_act/tc_pedit.h
  HDRINST usr/include/linux/tc_act/tc_bpf.h
  HDRINST usr/include/linux/tc_act/tc_ipt.h
  HDRINST usr/include/linux/netrom.h
  HDRINST usr/include/linux/joystick.h
  HDRINST usr/include/linux/falloc.h
  HDRINST usr/include/linux/cycx_cfm.h
  HDRINST usr/include/linux/omapfb.h
  HDRINST usr/include/linux/msdos_fs.h
  HDRINST usr/include/linux/virtio_types.h
  HDRINST usr/include/linux/mroute.h
  HDRINST usr/include/linux/psample.h
  HDRINST usr/include/linux/ipv6.h
  HDRINST usr/include/linux/dw100.h
  HDRINST usr/include/linux/psp-sev.h
  HDRINST usr/include/linux/vfio.h
  HDRINST usr/include/linux/if_ppp.h
  HDRINST usr/include/linux/byteorder/big_endian.h
  HDRINST usr/include/linux/byteorder/little_endian.h
  HDRINST usr/include/linux/comedi.h
  HDRINST usr/include/linux/scif_ioctl.h
  HDRINST usr/include/linux/timerfd.h
  HDRINST usr/include/linux/time_types.h
  HDRINST usr/include/linux/firewire-constants.h
  HDRINST usr/include/linux/virtio_snd.h
  HDRINST usr/include/linux/ppp-ioctl.h
  HDRINST usr/include/linux/fib_rules.h
  HDRINST usr/include/linux/gen_stats.h
  HDRINST usr/include/linux/virtio_iommu.h
  HDRINST usr/include/linux/genetlink.h
  HDRINST usr/include/linux/uvcvideo.h
  HDRINST usr/include/linux/pfkeyv2.h
  CC      /kernel/build64-default/tools/objtool/weak.o
  HDRINST usr/include/linux/soundcard.h
  HDRINST usr/include/linux/times.h
  CC      /kernel/build64-default/tools/objtool/check.o
  HDRINST usr/include/linux/nfc.h
  HDRINST usr/include/linux/affs_hardblocks.h
  MKDIR   /kernel/build64-default/tools/objtool/arch/x86/
  CC      /kernel/build64-default/tools/objtool/special.o
  HDRINST usr/include/linux/nilfs2_api.h
  CC      /kernel/build64-default/tools/objtool/builtin-check.o
  MKDIR   /kernel/build64-default/tools/objtool/arch/x86/lib/
  HDRINST usr/include/linux/rseq.h
  CC      /kernel/build64-default/tools/objtool/elf.o
  HDRINST usr/include/linux/caif/caif_socket.h
  CC      /kernel/build64-default/tools/objtool/arch/x86/special.o
  CC      /kernel/build64-default/tools/objtool/objtool.o
  CC      /kernel/build64-default/tools/objtool/orc_gen.o
  HDRINST usr/include/linux/caif/if_caif.h
  GEN     /kernel/build64-default/tools/objtool/arch/x86/lib/inat-tables.c
  CC      /kernel/build64-default/tools/objtool/orc_dump.o
  HDRINST usr/include/linux/i2c-dev.h
  HDRINST usr/include/linux/cuda.h
  HDRINST usr/include/linux/mei_uuid.h
  HDRINST usr/include/linux/cn_proc.h
  HDRINST usr/include/linux/parport.h
  CC      /kernel/build64-default/tools/objtool/libstring.o
  HDRINST usr/include/linux/v4l2-controls.h
  HDRINST usr/include/linux/hsi/cs-protocol.h
  CC      /kernel/build64-default/tools/objtool/libctype.o
  HDRINST usr/include/linux/hsi/hsi_char.h
  HDRINST usr/include/linux/seg6_genl.h
  CC      /kernel/build64-default/tools/objtool/str_error_r.o
  HDRINST usr/include/linux/am437x-vpfe.h
  CC      /kernel/build64-default/tools/objtool/librbtree.o
  HDRINST usr/include/linux/amt.h
  HDRINST usr/include/linux/netconf.h
  HDRINST usr/include/linux/erspan.h
  HDRINST usr/include/linux/nsfs.h
  HDRINST usr/include/linux/xilinx-v4l2-controls.h
  HDRINST usr/include/linux/aspeed-p2a-ctrl.h
  HDRINST usr/include/linux/vfio_zdev.h
  HDRINST usr/include/linux/serio.h
  HDRINST usr/include/linux/acrn.h
  HDRINST usr/include/linux/nfs2.h
  HDRINST usr/include/linux/virtio_pci.h
  HDRINST usr/include/linux/ipc.h
  HDRINST usr/include/linux/ethtool_netlink.h
  HDRINST usr/include/linux/kd.h
  HDRINST usr/include/linux/elf.h
  HDRINST usr/include/linux/videodev2.h
  HDRINST usr/include/linux/if_alg.h
  HDRINST usr/include/linux/sonypi.h
  HDRINST usr/include/linux/fsverity.h
  HDRINST usr/include/linux/if.h
  HDRINST usr/include/linux/btrfs.h
  HDRINST usr/include/linux/vm_sockets_diag.h
  HDRINST usr/include/linux/netfilter_bridge.h
  HDRINST usr/include/linux/packet_diag.h
  HDRINST usr/include/linux/netfilter_ipv4.h
  HDRINST usr/include/linux/kvm.h
  HDRINST usr/include/linux/pci.h
  HDRINST usr/include/linux/if_addrlabel.h
  HDRINST usr/include/linux/hdlcdrv.h
  HDRINST usr/include/linux/cfm_bridge.h
  HDRINST usr/include/linux/fiemap.h
  HDRINST usr/include/linux/dm-ioctl.h
  HDRINST usr/include/linux/aspeed-lpc-ctrl.h
  HDRINST usr/include/linux/atmioc.h
  HDRINST usr/include/linux/dlm.h
  HDRINST usr/include/linux/pci_regs.h
  HDRINST usr/include/linux/cachefiles.h
  HDRINST usr/include/linux/membarrier.h
  HDRINST usr/include/linux/nfs_idmap.h
  HDRINST usr/include/linux/ip.h
  HDRINST usr/include/linux/atm_he.h
  HDRINST usr/include/linux/nfsd/export.h
  HDRINST usr/include/linux/nfsd/stats.h
  HDRINST usr/include/linux/nfsd/debug.h
  HDRINST usr/include/linux/nfsd/cld.h
  HDRINST usr/include/linux/ip_vs.h
  HDRINST usr/include/linux/vmcore.h
  HDRINST usr/include/linux/vbox_vmmdev_types.h
  HDRINST usr/include/linux/dvb/osd.h
  HDRINST usr/include/linux/dvb/dmx.h
  HDRINST usr/include/linux/dvb/net.h
  HDRINST usr/include/linux/dvb/frontend.h
  HDRINST usr/include/linux/dvb/ca.h
  HDRINST usr/include/linux/dvb/version.h
  HDRINST usr/include/linux/dvb/video.h
  HDRINST usr/include/linux/dvb/audio.h
  HDRINST usr/include/linux/nfs.h
  HDRINST usr/include/linux/if_link.h
  HDRINST usr/include/linux/wait.h
  HDRINST usr/include/linux/icmpv6.h
  HDRINST usr/include/linux/media.h
  HDRINST usr/include/linux/seg6_local.h
  HDRINST usr/include/linux/tps6594_pfsm.h
  HDRINST usr/include/linux/openvswitch.h
  HDRINST usr/include/linux/atmsap.h
  HDRINST usr/include/linux/bpfilter.h
  HDRINST usr/include/linux/fpga-dfl.h
  HDRINST usr/include/linux/userio.h
  CC      /kernel/build64-default/tools/objtool/arch/x86/decode.o
  HDRINST usr/include/linux/signal.h
  HDRINST usr/include/linux/map_to_14segment.h
  HDRINST usr/include/linux/hdreg.h
  HDRINST usr/include/linux/utime.h
  HDRINST usr/include/linux/usbdevice_fs.h
  HDRINST usr/include/linux/timex.h
  HDRINST usr/include/linux/if_fc.h
  HDRINST usr/include/linux/reiserfs_xattr.h
  HDRINST usr/include/linux/hw_breakpoint.h
  HDRINST usr/include/linux/quota.h
  HDRINST usr/include/linux/ioprio.h
  HDRINST usr/include/linux/eventpoll.h
  HDRINST usr/include/linux/atmclip.h
  HDRINST usr/include/linux/can.h
  HDRINST usr/include/linux/if_team.h
  HDRINST usr/include/linux/usbip.h
  HDRINST usr/include/linux/stat.h
  HDRINST usr/include/linux/fou.h
  HDRINST usr/include/linux/hash_info.h
  HDRINST usr/include/linux/ppp-comp.h
  HDRINST usr/include/linux/ip6_tunnel.h
  HDRINST usr/include/linux/tipc_netlink.h
  HDRINST usr/include/linux/in.h
  HDRINST usr/include/linux/wireguard.h
  HDRINST usr/include/linux/btf.h
  HDRINST usr/include/linux/batman_adv.h
  HDRINST usr/include/linux/fcntl.h
  HDRINST usr/include/linux/if_ltalk.h
  HDRINST usr/include/linux/i2c.h
  HDRINST usr/include/linux/atm_idt77105.h
  HDRINST usr/include/linux/kexec.h
  HDRINST usr/include/linux/arm_sdei.h
  HDRINST usr/include/linux/netfilter_ipv6/ip6_tables.h
  HDRINST usr/include/linux/netfilter_ipv6/ip6t_ah.h
  HDRINST usr/include/linux/netfilter_ipv6/ip6t_NPT.h
  HDRINST usr/include/linux/netfilter_ipv6/ip6t_rt.h
  HDRINST usr/include/linux/netfilter_ipv6/ip6t_REJECT.h
  HDRINST usr/include/linux/netfilter_ipv6/ip6t_opts.h
  HDRINST usr/include/linux/netfilter_ipv6/ip6t_srh.h
  HDRINST usr/include/linux/netfilter_ipv6/ip6t_LOG.h
  HDRINST usr/include/linux/netfilter_ipv6/ip6t_mh.h
  HDRINST usr/include/linux/netfilter_ipv6/ip6t_HL.h
  HDRINST usr/include/linux/netfilter_ipv6/ip6t_hl.h
  HDRINST usr/include/linux/netfilter_ipv6/ip6t_frag.h
  HDRINST usr/include/linux/netfilter_ipv6/ip6t_ipv6header.h
  HDRINST usr/include/linux/minix_fs.h
  HDRINST usr/include/linux/aio_abi.h
  HDRINST usr/include/linux/pktcdvd.h
  HDRINST usr/include/linux/libc-compat.h
  HDRINST usr/include/linux/atmlec.h
  HDRINST usr/include/linux/signalfd.h
  HDRINST usr/include/linux/bpf_common.h
  HDRINST usr/include/linux/seg6_iptunnel.h
  HDRINST usr/include/linux/synclink.h
  HDRINST usr/include/linux/mpls_iptunnel.h
  HDRINST usr/include/linux/mctp.h
  HDRINST usr/include/linux/if_xdp.h
  HDRINST usr/include/linux/llc.h
  HDRINST usr/include/linux/atmsvc.h
  HDRINST usr/include/linux/sed-opal.h
  HDRINST usr/include/linux/sock_diag.h
  HDRINST usr/include/linux/time.h
  HDRINST usr/include/linux/securebits.h
  HDRINST usr/include/linux/fsl_hypervisor.h
  HDRINST usr/include/linux/if_hippi.h
  HDRINST usr/include/linux/seccomp.h
  HDRINST usr/include/linux/oom.h
  HDRINST usr/include/linux/filter.h
  HDRINST usr/include/linux/inotify.h
  HDRINST usr/include/linux/rfkill.h
  HDRINST usr/include/linux/reboot.h
  HDRINST usr/include/linux/can/vxcan.h
  HDRINST usr/include/linux/can/j1939.h
  HDRINST usr/include/linux/can/netlink.h
  HDRINST usr/include/linux/can/bcm.h
  HDRINST usr/include/linux/can/raw.h
  HDRINST usr/include/linux/can/gw.h
  HDRINST usr/include/linux/can/error.h
  HDRINST usr/include/linux/can/isotp.h
  HDRINST usr/include/linux/if_eql.h
  HDRINST usr/include/linux/hiddev.h
  HDRINST usr/include/linux/blktrace_api.h
  HDRINST usr/include/linux/ccs.h
  HDRINST usr/include/linux/ioam6.h
  HDRINST usr/include/linux/hsr_netlink.h
  HDRINST usr/include/linux/mmc/ioctl.h
  HDRINST usr/include/linux/bfs_fs.h
  HDRINST usr/include/linux/rio_cm_cdev.h
  HDRINST usr/include/linux/uleds.h
  HDRINST usr/include/linux/mrp_bridge.h
  HDRINST usr/include/linux/adb.h
  HDRINST usr/include/linux/pmu.h
  HDRINST usr/include/linux/udmabuf.h
  HDRINST usr/include/linux/kcmp.h
  HDRINST usr/include/linux/dma-heap.h
  HDRINST usr/include/linux/userfaultfd.h
  HDRINST usr/include/linux/netfilter_arp/arpt_mangle.h
  HDRINST usr/include/linux/netfilter_arp/arp_tables.h
  HDRINST usr/include/linux/tipc.h
  HDRINST usr/include/linux/virtio_ids.h
  HDRINST usr/include/linux/l2tp.h
  HDRINST usr/include/linux/devlink.h
  HDRINST usr/include/linux/virtio_gpio.h
  HDRINST usr/include/linux/dcbnl.h
  HDRINST usr/include/linux/cyclades.h
  HDRINST usr/include/sound/intel/avs/tokens.h
  HDRINST usr/include/sound/sof/fw.h
  HDRINST usr/include/sound/sof/abi.h
  HDRINST usr/include/sound/sof/tokens.h
  HDRINST usr/include/sound/sof/header.h
  HDRINST usr/include/sound/usb_stream.h
  HDRINST usr/include/sound/sfnt_info.h
  HDRINST usr/include/sound/asequencer.h
  HDRINST usr/include/sound/tlv.h
  HDRINST usr/include/sound/asound.h
  HDRINST usr/include/sound/asoc.h
  HDRINST usr/include/sound/sb16_csp.h
  HDRINST usr/include/sound/compress_offload.h
  HDRINST usr/include/sound/hdsp.h
  HDRINST usr/include/sound/emu10k1.h
  HDRINST usr/include/sound/snd_ar_tokens.h
  HDRINST usr/include/sound/snd_sst_tokens.h
  HDRINST usr/include/sound/asound_fm.h
  HDRINST usr/include/sound/hdspm.h
  HDRINST usr/include/sound/compress_params.h
  HDRINST usr/include/sound/firewire.h
  HDRINST usr/include/sound/skl-tplg-interface.h
  HDRINST usr/include/scsi/scsi_bsg_ufs.h
  HDRINST usr/include/scsi/scsi_netlink_fc.h
  HDRINST usr/include/scsi/scsi_bsg_mpi3mr.h
  HDRINST usr/include/scsi/fc/fc_ns.h
  HDRINST usr/include/scsi/fc/fc_fs.h
  HDRINST usr/include/scsi/fc/fc_els.h
  HDRINST usr/include/scsi/fc/fc_gs.h
  HDRINST usr/include/scsi/scsi_bsg_fc.h
  HDRINST usr/include/scsi/cxlflash_ioctl.h
  HDRINST usr/include/scsi/scsi_netlink.h
  HDRINST usr/include/linux/version.h
  HDRINST usr/include/asm/processor-flags.h
  HDRINST usr/include/asm/auxvec.h
  HDRINST usr/include/asm/svm.h
  HDRINST usr/include/asm/bitsperlong.h
  HDRINST usr/include/asm/kvm_perf.h
  HDRINST usr/include/asm/mce.h
  HDRINST usr/include/asm/posix_types.h
  HDRINST usr/include/asm/msr.h
  HDRINST usr/include/asm/sigcontext32.h
  HDRINST usr/include/asm/mman.h
  HDRINST usr/include/asm/shmbuf.h
  HDRINST usr/include/asm/e820.h
  HDRINST usr/include/asm/posix_types_64.h
  HDRINST usr/include/asm/vsyscall.h
  HDRINST usr/include/asm/msgbuf.h
  HDRINST usr/include/asm/swab.h
  HDRINST usr/include/asm/statfs.h
  HDRINST usr/include/asm/posix_types_x32.h
  HDRINST usr/include/asm/ptrace.h
  HDRINST usr/include/asm/unistd.h
  HDRINST usr/include/asm/ist.h
  HDRINST usr/include/asm/prctl.h
  HDRINST usr/include/asm/boot.h
  HDRINST usr/include/asm/sigcontext.h
  HDRINST usr/include/asm/posix_types_32.h
  HDRINST usr/include/asm/kvm_para.h
  HDRINST usr/include/asm/a.out.h
  HDRINST usr/include/asm/mtrr.h
  HDRINST usr/include/asm/amd_hsmp.h
  HDRINST usr/include/asm/hwcap2.h
  HDRINST usr/include/asm/ptrace-abi.h
  HDRINST usr/include/asm/vm86.h
  HDRINST usr/include/asm/vmx.h
  HDRINST usr/include/asm/ldt.h
  HDRINST usr/include/asm/perf_regs.h
  HDRINST usr/include/asm/debugreg.h
  HDRINST usr/include/asm/kvm.h
  HDRINST usr/include/asm/signal.h
  HDRINST usr/include/asm/bootparam.h
  HDRINST usr/include/asm/siginfo.h
  HDRINST usr/include/asm/hw_breakpoint.h
  HDRINST usr/include/asm/stat.h
  HDRINST usr/include/asm/setup.h
  HDRINST usr/include/asm/sembuf.h
  HDRINST usr/include/asm/sgx.h
  HDRINST usr/include/asm/ucontext.h
  HDRINST usr/include/asm/byteorder.h
  HDRINST usr/include/asm/unistd_64.h
  HDRINST usr/include/asm/ioctls.h
  HDRINST usr/include/asm/bpf_perf_event.h
  HDRINST usr/include/asm/types.h
  HDRINST usr/include/asm/poll.h
  HDRINST usr/include/asm/resource.h
  HDRINST usr/include/asm/param.h
  HDRINST usr/include/asm/sockios.h
  HDRINST usr/include/asm/errno.h
  HDRINST usr/include/asm/unistd_x32.h
  HDRINST usr/include/asm/termios.h
  HDRINST usr/include/asm/ioctl.h
  HDRINST usr/include/asm/socket.h
  HDRINST usr/include/asm/unistd_32.h
  HDRINST usr/include/asm/termbits.h
  HDRINST usr/include/asm/fcntl.h
  HDRINST usr/include/asm/ipcbuf.h
  HOSTLD  scripts/mod/modpost
  CC      kernel/bounds.s
  CHKSHA1 ../include/linux/atomic/atomic-arch-fallback.h
  CHKSHA1 ../include/linux/atomic/atomic-instrumented.h
  CHKSHA1 ../include/linux/atomic/atomic-long.h
  UPD     include/generated/timeconst.h
  UPD     include/generated/bounds.h
  CC      arch/x86/kernel/asm-offsets.s
  LD      /kernel/build64-default/tools/objtool/arch/x86/objtool-in.o
  UPD     include/generated/asm-offsets.h
  CALL    ../scripts/checksyscalls.sh
  LD      /kernel/build64-default/tools/objtool/objtool-in.o
  LINK    /kernel/build64-default/tools/objtool/objtool
  LDS     scripts/module.lds
  CC      ipc/compat.o
  CC      ipc/util.o
  CC      ipc/msgutil.o
  CC      ipc/msg.o
  AR      certs/built-in.a
  HOSTCC  usr/gen_init_cpio
  CC      ipc/sem.o
  CC      ipc/shm.o
  CC      ipc/syscall.o
  CC      block/bdev.o
  CC      init/main.o
  CC      ipc/ipc_sysctl.o
  AS      arch/x86/lib/clear_page_64.o
  CC      security/commoncap.o
  CC      io_uring/io_uring.o
  CC      ipc/mqueue.o
  AR      arch/x86/video/built-in.a
  CC      block/fops.o
  CC      security/min_addr.o
  CC      arch/x86/lib/cmdline.o
  CC      ipc/namespace.o
  CC      security/inode.o
  CC      arch/x86/power/cpu.o
  CC      arch/x86/pci/i386.o
  CC      arch/x86/realmode/init.o
  UPD     init/utsversion-tmp.h
  CC      security/keys/gc.o
  CC [M]  arch/x86/video/fbdev.o
  AR      virt/lib/built-in.a
  CC      block/partitions/core.o
  CC      net/llc/llc_core.o
  AR      arch/x86/ia32/built-in.a
  AS      arch/x86/crypto/aesni-intel_asm.o
  CC      net/ethernet/eth.o
  CC      net/core/sock.o
  AR      drivers/irqchip/built-in.a
  CC [M]  virt/lib/irqbypass.o
  CC      arch/x86/mm/pat/set_memory.o
  CC      fs/notify/dnotify/dnotify.o
  CC      block/bio.o
  AR      sound/i2c/other/built-in.a
  AR      sound/drivers/opl3/built-in.a
  AR      arch/x86/platform/atom/built-in.a
  CC      sound/core/seq/seq.o
  AR      sound/drivers/opl4/built-in.a
  AR      sound/isa/ad1816a/built-in.a
  CC      arch/x86/events/amd/core.o
  AR      sound/i2c/built-in.a
  CC      arch/x86/kernel/fpu/init.o
  AR      arch/x86/platform/ce4100/built-in.a
  AR      drivers/bus/mhi/built-in.a
  AR      sound/drivers/mpu401/built-in.a
  AR      drivers/phy/allwinner/built-in.a
  AR      sound/isa/ad1848/built-in.a
  CC      lib/kunit/test.o
  AR      drivers/pinctrl/actions/built-in.a
  CC      lib/math/div64.o
  AR      drivers/phy/amlogic/built-in.a
  AR      drivers/bus/built-in.a
  CC      arch/x86/platform/efi/memmap.o
  CC      arch/x86/entry/vdso/vma.o
  AR      sound/drivers/vx/built-in.a
  CC      kernel/sched/core.o
  CC      mm/kasan/common.o
  AR      sound/isa/cs423x/built-in.a
  AR      drivers/pinctrl/bcm/built-in.a
  CC      arch/x86/crypto/aesni-intel_glue.o
  AR      sound/drivers/pcsp/built-in.a
  AR      drivers/phy/broadcom/built-in.a
  AR      sound/isa/es1688/built-in.a
  AR      sound/drivers/built-in.a
  AR      drivers/pinctrl/cirrus/built-in.a
  AR      sound/pci/ac97/built-in.a
  AR      drivers/phy/cadence/built-in.a
  CC      crypto/api.o
  AR      sound/isa/galaxy/built-in.a
  AR      sound/pci/ali5451/built-in.a
  AR      drivers/pinctrl/freescale/built-in.a
  AR      drivers/phy/freescale/built-in.a
  AR      sound/isa/gus/built-in.a
  CC      sound/core/sound.o
  AR      sound/pci/asihpi/built-in.a
  AS      arch/x86/lib/cmpxchg16b_emu.o
  AR      drivers/phy/hisilicon/built-in.a
  CC      drivers/pinctrl/intel/pinctrl-baytrail.o
  AR      sound/pci/au88x0/built-in.a
  AR      sound/isa/msnd/built-in.a
  CC      lib/math/gcd.o
  AR      drivers/phy/ingenic/built-in.a
  AR      sound/pci/aw2/built-in.a
  CC      arch/x86/lib/copy_mc.o
  AR      sound/isa/opti9xx/built-in.a
  AR      drivers/phy/intel/built-in.a
  AR      sound/isa/sb/built-in.a
  AR      sound/pci/ctxfi/built-in.a
  AR      drivers/phy/lantiq/built-in.a
  AR      sound/isa/wavefront/built-in.a
  AR      sound/pci/ca0106/built-in.a
  AR      drivers/phy/marvell/built-in.a
  AR      sound/isa/wss/built-in.a
  AR      sound/pci/cs46xx/built-in.a
  AR      sound/isa/built-in.a
  AR      drivers/phy/mediatek/built-in.a
  AR      sound/pci/cs5535audio/built-in.a
  CC      lib/math/lcm.o
  AR      drivers/phy/microchip/built-in.a
  AR      sound/pci/lola/built-in.a
  AS      arch/x86/realmode/rm/header.o
  AR      sound/pci/lx6464es/built-in.a
  AR      drivers/phy/motorola/built-in.a
  AR      sound/pci/echoaudio/built-in.a
  AR      drivers/phy/mscc/built-in.a
  AS      arch/x86/realmode/rm/trampoline_64.o
  AR      sound/pci/emu10k1/built-in.a
  AR      drivers/phy/qualcomm/built-in.a
  CC      lib/math/int_pow.o
  AR      sound/pci/hda/built-in.a
  AR      drivers/phy/ralink/built-in.a
  CC [M]  sound/pci/hda/hda_bind.o
  AR      drivers/phy/renesas/built-in.a
  AS      arch/x86/realmode/rm/stack.o
  AR      drivers/phy/rockchip/built-in.a
  AS      arch/x86/realmode/rm/reboot.o
  GEN     usr/initramfs_data.cpio
  AR      drivers/phy/samsung/built-in.a
  CC      lib/math/int_sqrt.o
  COPY    usr/initramfs_inc_data
  AS      usr/initramfs_data.o
  AR      drivers/phy/socionext/built-in.a
  AS      arch/x86/realmode/rm/wakeup_asm.o
  AR      drivers/phy/st/built-in.a
  AR      usr/built-in.a
  AR      drivers/phy/sunplus/built-in.a
  CC      arch/x86/pci/init.o
  AR      drivers/phy/tegra/built-in.a
  CC      arch/x86/realmode/rm/wakemain.o
  AR      drivers/phy/ti/built-in.a
  CC      lib/math/reciprocal_div.o
  AR      drivers/phy/xilinx/built-in.a
  CC      drivers/phy/phy-core.o
  CC      arch/x86/realmode/rm/video-mode.o
  CC      arch/x86/kernel/fpu/bugs.o
  AS      arch/x86/lib/copy_mc_64.o
  CC      lib/math/rational.o
  AR      virt/built-in.a
  AS      arch/x86/lib/copy_page_64.o
  CC      arch/x86/mm/init.o
  AS      arch/x86/lib/copy_user_64.o
  CC      mm/filemap.o
  AS      arch/x86/lib/copy_user_uncached_64.o
  AS      arch/x86/realmode/rm/copy.o
  CC      init/do_mounts.o
  CC      arch/x86/lib/cpu.o
  CC      sound/core/seq/seq_lock.o
  AS      arch/x86/realmode/rm/bioscall.o
  CC      arch/x86/mm/init_64.o
  CC      mm/kasan/report.o
  CC      arch/x86/realmode/rm/regs.o
  CC      drivers/gpio/gpiolib.o
  CC      arch/x86/kernel/fpu/core.o
  CC      drivers/gpio/gpiolib-devres.o
  CC      arch/x86/realmode/rm/video-vga.o
  CC      drivers/gpio/gpiolib-legacy.o
  CC      security/keys/key.o
  CC      mm/mempool.o
  AR      fs/notify/dnotify/built-in.a
  CC      fs/notify/inotify/inotify_fsnotify.o
  CC      mm/oom_kill.o
  CC      arch/x86/mm/fault.o
  CC      arch/x86/realmode/rm/video-vesa.o
  CC      fs/notify/fanotify/fanotify.o
  CC      lib/kunit/resource.o
  CC      arch/x86/platform/efi/quirks.o
  CC      arch/x86/realmode/rm/video-bios.o
  CC      net/llc/llc_input.o
  CC [M]  lib/math/prime_numbers.o
  CC      arch/x86/power/hibernate_64.o
  CC      arch/x86/events/amd/lbr.o
  CC      arch/x86/entry/vdso/extable.o
  PASYMS  arch/x86/realmode/rm/pasyms.h
  CC      block/partitions/ldm.o
  LDS     arch/x86/realmode/rm/realmode.lds
  LD      arch/x86/realmode/rm/realmode.elf
  RELOCS  arch/x86/realmode/rm/realmode.relocs
  OBJCOPY arch/x86/realmode/rm/realmode.bin
  AS      arch/x86/realmode/rmpiggy.o
  CC      arch/x86/pci/mmconfig_64.o
  CC      crypto/cipher.o
  CC      arch/x86/lib/delay.o
  AR      arch/x86/realmode/built-in.a
  CC [M]  sound/pci/hda/hda_codec.o
  CC      sound/core/seq/seq_clientmgr.o
  CC      block/elevator.o
  CC [M]  sound/pci/hda/hda_jack.o
  CC      arch/x86/mm/pat/memtype.o
  AS      arch/x86/crypto/aesni-intel_avx-x86_64.o
  CC      arch/x86/mm/pat/memtype_interval.o
  CC      fs/notify/fsnotify.o
  CC      drivers/pinctrl/intel/pinctrl-intel.o
  CC [M]  drivers/pinctrl/intel/pinctrl-cherryview.o
  CC      arch/x86/events/amd/ibs.o
  AS      arch/x86/crypto/aes_ctrby8_avx-x86_64.o
  CC      arch/x86/entry/vdso/vdso32-setup.o
  AR      net/ethernet/built-in.a
  CC      fs/notify/inotify/inotify_user.o
  AS      arch/x86/lib/getuser.o
  CC      fs/nfs_common/grace.o
  GEN     arch/x86/lib/inat-tables.c
  CC      net/802/p8022.o
  CC      lib/kunit/static_stub.o
  CC      arch/x86/lib/insn-eval.o
  AS [M]  arch/x86/crypto/ghash-clmulni-intel_asm.o
  CC [M]  arch/x86/crypto/ghash-clmulni-intel_glue.o
  CC      mm/kasan/init.o
  AR      lib/math/built-in.a
  CC      net/802/psnap.o
  AR      drivers/phy/built-in.a
  CC      block/partitions/msdos.o
  CC [M]  drivers/pinctrl/intel/pinctrl-broxton.o
  CC      arch/x86/lib/insn.o
  CC      init/do_mounts_initrd.o
  CC      ipc/mq_sysctl.o
  LDS     arch/x86/entry/vdso/vdso.lds
  AS      arch/x86/entry/vdso/vdso-note.o
  CC      crypto/compress.o
  CC      arch/x86/entry/vdso/vclock_gettime.o
  CC      net/sched/sch_generic.o
  AS      arch/x86/power/hibernate_asm_64.o
  CC      arch/x86/power/hibernate.o
  CC      security/keys/keyring.o
  CC      net/802/stp.o
  CC      arch/x86/pci/direct.o
  CC      arch/x86/platform/efi/efi.o
  CC      crypto/algapi.o
  CC      net/llc/llc_output.o
  CC      arch/x86/kernel/fpu/regset.o
  CC      mm/fadvise.o
  CC      fs/notify/fanotify/fanotify_user.o
  CC      kernel/locking/mutex.o
  CC [M]  sound/pci/hda/hda_auto_parser.o
  CC      lib/kunit/string-stream.o
  CC      kernel/locking/semaphore.o
  CC      mm/maccess.o
  CC      arch/x86/kernel/fpu/signal.o
  AS [M]  arch/x86/crypto/crc32-pclmul_asm.o
  CC [M]  arch/x86/crypto/crc32-pclmul_glue.o
  AR      arch/x86/mm/pat/built-in.a
  CC [M]  sound/pci/hda/hda_sysfs.o
  AR      fs/nfs_common/built-in.a
  CC      block/blk-core.o
  CC      arch/x86/kernel/fpu/xstate.o
  AR      arch/x86/net/built-in.a
  CC      kernel/locking/rwsem.o
  AS [M]  arch/x86/crypto/crct10dif-pcl-asm_64.o
  CC      arch/x86/platform/efi/efi_64.o
  CC [M]  arch/x86/crypto/crct10dif-pclmul_glue.o
  CC      arch/x86/mm/ioremap.o
  CC      block/blk-sysfs.o
  CC      io_uring/xattr.o
  CC      kernel/power/qos.o
  CC      arch/x86/entry/vdso/vgetcpu.o
  CC      kernel/power/main.o
  AR      ipc/built-in.a
  CC      arch/x86/mm/extable.o
  HOSTCC  arch/x86/entry/vdso/vdso2c
  CC      init/initramfs.o
  CC      mm/kasan/generic.o
  CC      mm/page-writeback.o
  AS      arch/x86/lib/memcpy_64.o
  CC      block/partitions/efi.o
  AS      arch/x86/lib/memmove_64.o
  AR      fs/notify/inotify/built-in.a
  LD [M]  arch/x86/crypto/ghash-clmulni-intel.o
  AS      arch/x86/lib/memset_64.o
  AR      arch/x86/crypto/built-in.a
  CC      arch/x86/events/amd/uncore.o
  CC      security/device_cgroup.o
  CC      lib/kunit/assert.o
  CC      arch/x86/pci/mmconfig-shared.o
  CC      arch/x86/lib/misc.o
  AR      arch/x86/power/built-in.a
  CC      lib/kunit/try-catch.o
  CC      block/blk-flush.o
  CC      arch/x86/lib/pc-conf-reg.o
  CC      arch/x86/mm/mmap.o
  CC      sound/core/seq/seq_memory.o
  AR      net/802/built-in.a
  CC      security/keys/keyctl.o
  CC [M]  drivers/pinctrl/intel/pinctrl-geminilake.o
  AR      net/llc/built-in.a
  CC      lib/kunit/executor.o
  CC      arch/x86/pci/fixup.o
  CC      kernel/printk/printk.o
  LD [M]  arch/x86/crypto/crc32-pclmul.o
  LD [M]  arch/x86/crypto/crct10dif-pclmul.o
  CC      io_uring/nop.o
  LDS     arch/x86/entry/vdso/vdso32/vdso32.lds
  CC      mm/folio-compat.o
  AS      arch/x86/entry/vdso/vdso32/note.o
  AS      arch/x86/lib/putuser.o
  AS      arch/x86/entry/vdso/vdso32/system_call.o
  CC      lib/kunit/hooks.o
  AS      arch/x86/lib/retpoline.o
  AS      arch/x86/entry/vdso/vdso32/sigreturn.o
  CC [M]  sound/pci/hda/hda_controller.o
  CC      sound/core/init.o
  CC      arch/x86/lib/usercopy.o
  CC      arch/x86/entry/vdso/vdso32/vclock_gettime.o
  CC      mm/readahead.o
  CC      mm/swap.o
  CC      kernel/irq/irqdesc.o
  CC      security/keys/permission.o
  CC      kernel/irq/handle.o
  CC      kernel/locking/percpu-rwsem.o
  CC [M]  sound/pci/hda/hda_proc.o
  CC      crypto/scatterwalk.o
  CC      security/keys/process_keys.o
  AS      arch/x86/platform/efi/efi_stub_64.o
  CC      arch/x86/entry/vdso/vdso32/vgetcpu.o
  CC      arch/x86/lib/usercopy_64.o
  AR      arch/x86/platform/efi/built-in.a
  AR      lib/kunit/built-in.a
  CC [M]  drivers/pinctrl/intel/pinctrl-sunrisepoint.o
  AR      arch/x86/platform/geode/built-in.a
  AR      arch/x86/platform/iris/built-in.a
  CC      kernel/irq/manage.o
  CC      arch/x86/platform/intel/iosf_mbi.o
  CC      lib/crypto/memneq.o
  CC      kernel/rcu/update.o
  CC      arch/x86/mm/pgtable.o
  AR      sound/ppc/built-in.a
  CC      kernel/rcu/sync.o
  CC      init/calibrate.o
  CC      arch/x86/mm/physaddr.o
  CC      mm/kasan/report_generic.o
  CC      kernel/power/console.o
  AR      block/partitions/built-in.a
  CC      arch/x86/pci/acpi.o
  AR      arch/x86/platform/intel-mid/built-in.a
  CC      kernel/power/process.o
  CC      init/init_task.o
  CC      kernel/printk/printk_safe.o
  AR      fs/notify/fanotify/built-in.a
  CC      fs/notify/notification.o
  CC      sound/core/seq/seq_queue.o
  AR      arch/x86/events/amd/built-in.a
  AR      arch/x86/kernel/fpu/built-in.a
  CC      arch/x86/events/intel/core.o
  CC      fs/notify/group.o
  VDSO    arch/x86/entry/vdso/vdso64.so.dbg
  CC      drivers/gpio/gpiolib-cdev.o
  CC      arch/x86/kernel/cpu/mce/core.o
  VDSO    arch/x86/entry/vdso/vdso32.so.dbg
  OBJCOPY arch/x86/entry/vdso/vdso64.so
  OBJCOPY arch/x86/entry/vdso/vdso32.so
  VDSO2C  arch/x86/entry/vdso/vdso-image-64.c
  VDSO2C  arch/x86/entry/vdso/vdso-image-32.c
  CC      arch/x86/kernel/cpu/mtrr/mtrr.o
  CC      arch/x86/entry/vdso/vdso-image-64.o
  CC      arch/x86/kernel/cpu/mtrr/if.o
  CC      fs/notify/mark.o
  CC      arch/x86/events/intel/bts.o
  CC      arch/x86/mm/tlb.o
  CC      lib/crypto/utils.o
  CC      arch/x86/kernel/cpu/mtrr/generic.o
  CC      kernel/rcu/srcutree.o
  AR      drivers/pinctrl/intel/built-in.a
  AR      drivers/pinctrl/mediatek/built-in.a
  CC      kernel/power/suspend.o
  AR      drivers/pinctrl/mvebu/built-in.a
  AR      drivers/pinctrl/nomadik/built-in.a
  AR      arch/x86/platform/intel-quark/built-in.a
  CC      crypto/proc.o
  AR      drivers/pinctrl/nuvoton/built-in.a
  AR      drivers/pinctrl/nxp/built-in.a
  CC      net/core/request_sock.o
  AR      drivers/pinctrl/qcom/built-in.a
  CC      arch/x86/kernel/acpi/boot.o
  AR      kernel/livepatch/built-in.a
  AR      drivers/pinctrl/sprd/built-in.a
  CC      arch/x86/lib/msr-smp.o
  AR      drivers/pinctrl/ti/built-in.a
  AR      drivers/pinctrl/sunplus/built-in.a
  CC      arch/x86/entry/vdso/vdso-image-32.o
  CC      drivers/pinctrl/core.o
  CC      init/version.o
  CC      net/core/skbuff.o
  CC      mm/truncate.o
  CC      net/sched/sch_mq.o
  AR      arch/x86/platform/olpc/built-in.a
  CC      net/sched/sch_frag.o
  CC      kernel/printk/printk_ringbuffer.o
  AR      arch/x86/platform/intel/built-in.a
  AR      arch/x86/platform/scx200/built-in.a
  AR      arch/x86/platform/ts5500/built-in.a
  AR      arch/x86/platform/uv/built-in.a
  AR      arch/x86/platform/built-in.a
  CC      arch/x86/pci/legacy.o
  CC      lib/crypto/chacha.o
  CC      kernel/locking/irqflag-debug.o
  AR      arch/x86/entry/vdso/built-in.a
  CC      arch/x86/entry/vsyscall/vsyscall_64.o
  CC      kernel/locking/mutex-debug.o
  CC      arch/x86/lib/cache-smp.o
  CC      mm/kasan/shadow.o
  CC      fs/notify/fdinfo.o
  CC      arch/x86/kernel/apic/apic.o
  CC      kernel/power/hibernate.o
  CC      arch/x86/kernel/apic/apic_common.o
  AR      init/built-in.a
  CC      arch/x86/lib/msr.o
  CC      mm/kasan/quarantine.o
  CC      lib/crypto/aes.o
  CC      crypto/aead.o
  AR      sound/pci/ice1712/built-in.a
  CC      security/keys/request_key.o
  AR      sound/pci/korg1212/built-in.a
  AS      arch/x86/entry/vsyscall/vsyscall_emu_64.o
  CC      crypto/geniv.o
  CC      crypto/skcipher.o
  CC      crypto/seqiv.o
  CC      sound/core/seq/seq_fifo.o
  AS      arch/x86/lib/msr-reg.o
  CC [M]  sound/pci/hda/hda_hwdep.o
  CC      mm/vmscan.o
  CC      arch/x86/kernel/kprobes/core.o
  CC      arch/x86/mm/cpu_entry_area.o
  AR      sound/pci/mixart/built-in.a
  AR      sound/pci/nm256/built-in.a
  AR      sound/pci/oxygen/built-in.a
  AR      sound/pci/pcxhr/built-in.a
  CC      security/keys/request_key_auth.o
  AR      sound/pci/riptide/built-in.a
  CC      crypto/echainiv.o
  CC      kernel/dma/mapping.o
  CC      block/blk-settings.o
  CC      kernel/dma/direct.o
  CC      mm/shmem.o
  CC      arch/x86/events/intel/ds.o
  CC      block/blk-ioc.o
  CC      arch/x86/pci/irq.o
  CC      arch/x86/kernel/cpu/mtrr/cleanup.o
  CC      kernel/irq/spurious.o
  CC      kernel/locking/lockdep.o
  CC      block/blk-map.o
  CC      block/blk-merge.o
  CC      drivers/gpio/gpiolib-sysfs.o
  AR      fs/notify/built-in.a
  CC      kernel/printk/sysctl.o
  CC      fs/iomap/trace.o
  CC      mm/util.o
  CC      lib/crypto/gf128mul.o
  CC      fs/iomap/iter.o
  CC      net/sched/sch_api.o
  AR      arch/x86/entry/vsyscall/built-in.a
  CC      crypto/ahash.o
  AS      arch/x86/entry/entry.o
  CC      sound/core/seq/seq_prioq.o
  CC [M]  sound/pci/hda/hda_generic.o
  AS      arch/x86/entry/entry_64.o
  CC      kernel/rcu/tree.o
  CC      arch/x86/mm/maccess.o
  CC      arch/x86/lib/msr-reg-export.o
  CC      lib/crypto/blake2s.o
  AR      mm/kasan/built-in.a
  CC      kernel/rcu/rcu_segcblist.o
  CC      arch/x86/kernel/acpi/sleep.o
  CC      fs/iomap/buffered-io.o
  CC      drivers/gpio/gpiolib-acpi.o
  CC      arch/x86/entry/syscall_64.o
  AR      kernel/printk/built-in.a
  AS      arch/x86/lib/hweight.o
  CC      security/keys/user_defined.o
  AR      fs/quota/built-in.a
  CC      drivers/gpio/gpiolib-swnode.o
  CC      crypto/shash.o
  CC      net/sched/sch_blackhole.o
  CC      arch/x86/lib/iomem.o
  CC      io_uring/fs.o
  CC      drivers/pinctrl/pinctrl-utils.o
  CC      arch/x86/mm/pgprot.o
  CC      fs/proc/task_mmu.o
  CC      fs/kernfs/mount.o
  CC      kernel/irq/resend.o
  CC      arch/x86/kernel/cpu/mce/severity.o
  CC      fs/kernfs/inode.o
  CC      arch/x86/kernel/kprobes/opt.o
  CC      arch/x86/pci/common.o
  CC      kernel/power/snapshot.o
  CC      arch/x86/kernel/cpu/cacheinfo.o
  CC      mm/mmzone.o
  AS      arch/x86/lib/iomap_copy_64.o
  CC      arch/x86/kernel/apic/apic_noop.o
  CC      arch/x86/lib/inat.o
  AR      sound/arm/built-in.a
  CC      lib/crypto/blake2s-generic.o
  CC      fs/iomap/direct-io.o
  CC      arch/x86/kernel/apic/ipi.o
  CC      kernel/dma/ops_helpers.o
  CC      mm/vmstat.o
  CC      sound/core/seq/seq_timer.o
  CC      security/keys/compat.o
  AR      arch/x86/lib/built-in.a
  CC      arch/x86/entry/common.o
  CC      arch/x86/kernel/cpu/scattered.o
  CC      block/blk-timeout.o
  AR      arch/x86/lib/lib.a
  CC      arch/x86/pci/early.o
  AR      arch/x86/kernel/cpu/mtrr/built-in.a
  CC      io_uring/splice.o
  CC      drivers/pinctrl/pinmux.o
  CC      sound/core/seq/seq_system.o
  AS      arch/x86/kernel/acpi/wakeup_64.o
  CC      arch/x86/mm/hugetlbpage.o
  CC      arch/x86/kernel/apic/vector.o
  CC      arch/x86/kernel/acpi/apei.o
  CC      kernel/irq/chip.o
  CC      arch/x86/events/intel/knc.o
  CC      arch/x86/mm/kasan_init_64.o
  AR      drivers/pwm/built-in.a
  CC      lib/zlib_inflate/inffast.o
  CC      arch/x86/events/intel/lbr.o
  CC      drivers/pci/msi/pcidev_msi.o
  CC      arch/x86/events/intel/p4.o
  CC      arch/x86/kernel/apic/hw_nmi.o
  CC      lib/crypto/blake2s-selftest.o
  CC      drivers/pci/msi/api.o
  CC      io_uring/sync.o
  CC      lib/crypto/des.o
  CC      arch/x86/kernel/cpu/mce/genpool.o
  CC      fs/kernfs/dir.o
  CC      crypto/akcipher.o
  CC      io_uring/advise.o
  AR      drivers/gpio/built-in.a
  CC      lib/zlib_inflate/inflate.o
  CC      drivers/pci/pcie/portdrv.o
  CC      arch/x86/kernel/kprobes/ftrace.o
  CC      drivers/pci/pcie/rcec.o
  CC      kernel/dma/dummy.o
  CC      lib/crypto/sha1.o
  CC      arch/x86/kernel/cpu/mce/intel.o
  CC      security/keys/proc.o
  CC      block/blk-lib.o
  CC      arch/x86/pci/bus_numa.o
  CC      lib/zlib_inflate/infutil.o
  CC      sound/core/seq/seq_ports.o
  CC      arch/x86/kernel/cpu/topology.o
  AS      arch/x86/entry/thunk_64.o
  AS      arch/x86/entry/entry_64_compat.o
  CC      arch/x86/kernel/acpi/cppc.o
  CC      drivers/pci/msi/msi.o
  CC      arch/x86/entry/syscall_32.o
  CC      net/sched/sch_fifo.o
  LDS     arch/x86/kernel/vmlinux.lds
  CC      drivers/pinctrl/pinconf.o
  AS      arch/x86/kernel/head_64.o
  CC      fs/proc/inode.o
  CC      arch/x86/kernel/apic/io_apic.o
  CC      arch/x86/mm/numa.o
  CC      arch/x86/events/intel/p6.o
  CC      kernel/irq/dummychip.o
  CC      drivers/pci/msi/irqdomain.o
  CC      net/core/datagram.o
  CC      io_uring/filetable.o
  CC      arch/x86/mm/numa_64.o
  CC      block/blk-mq.o
  CC      arch/x86/kernel/apic/msi.o
  AR      arch/x86/kernel/kprobes/built-in.a
  CC      mm/backing-dev.o
  CC      fs/sysfs/file.o
  CC      fs/configfs/inode.o
  CC      kernel/dma/contiguous.o
  CC      fs/configfs/file.o
  CC      crypto/sig.o
  CC      lib/zlib_inflate/inftrees.o
  CC      fs/sysfs/dir.o
  CC      kernel/power/swap.o
  CC      fs/configfs/dir.o
  CC      block/blk-mq-tag.o
  CC      drivers/pci/pcie/aspm.o
  CC      arch/x86/kernel/cpu/mce/threshold.o
  CC      security/keys/sysctl.o
  CC      arch/x86/pci/amd_bus.o
  CC      arch/x86/kernel/acpi/cstate.o
  CC      fs/iomap/fiemap.o
  CC      lib/zlib_inflate/inflate_syms.o
  AR      arch/x86/entry/built-in.a
  CC      arch/x86/events/intel/pt.o
  CC      kernel/irq/devres.o
  CC [M]  arch/x86/kvm/../../../virt/kvm/kvm_main.o
  CC      arch/x86/events/intel/uncore.o
  CC      lib/crypto/sha256.o
  CC      arch/x86/kernel/apic/x2apic_phys.o
  CC      arch/x86/events/intel/uncore_nhmex.o
  CC      sound/core/seq/seq_info.o
  CC      mm/mm_init.o
  CC      drivers/pinctrl/pinconf-generic.o
  CC      block/blk-stat.o
  CC      kernel/power/user.o
  CC      fs/kernfs/file.o
  CC      kernel/sched/fair.o
  CC      lib/zlib_deflate/deflate.o
  AR      lib/zlib_inflate/built-in.a
  CC      kernel/sched/build_policy.o
  CC      fs/kernfs/symlink.o
  CC      fs/proc/root.o
  CC      lib/zlib_deflate/deftree.o
  AR      net/sched/built-in.a
  AR      drivers/pci/msi/built-in.a
  CC      arch/x86/events/intel/uncore_snb.o
  CC      arch/x86/events/intel/uncore_snbep.o
  CC      kernel/dma/swiotlb.o
  CC      kernel/sched/build_utility.o
  CC      fs/configfs/symlink.o
  AR      security/keys/built-in.a
  CC      arch/x86/kernel/cpu/mce/apei.o
  AR      security/built-in.a
  CC      drivers/pci/hotplug/pci_hotplug_core.o
  AR      drivers/pci/controller/dwc/built-in.a
  CC      crypto/kpp.o
  AR      drivers/pci/controller/mobiveil/built-in.a
  CC      drivers/pci/controller/vmd.o
  CC      kernel/irq/autoprobe.o
  AR      arch/x86/kernel/acpi/built-in.a
  CC      fs/sysfs/symlink.o
  CC      kernel/dma/remap.o
  CC      arch/x86/mm/amdtopology.o
  CC      fs/iomap/seek.o
  AR      sound/core/seq/built-in.a
  AR      arch/x86/pci/built-in.a
  CC      sound/core/memory.o
  CC      io_uring/openclose.o
  CC      net/netlink/af_netlink.o
  CC      io_uring/uring_cmd.o
  CC      net/netlink/genetlink.o
  CC [M]  lib/crypto/arc4.o
  AR      drivers/pinctrl/built-in.a
  CC      fs/configfs/mount.o
  CC      block/blk-mq-sysfs.o
  CC      block/blk-mq-cpumap.o
  CC      block/blk-mq-sched.o
  CC      arch/x86/events/intel/uncore_discovery.o
  CC      sound/core/control.o
  CC      drivers/pci/pcie/aer.o
  CC      fs/proc/base.o
  AR      net/bpf/built-in.a
  CC      arch/x86/events/intel/cstate.o
  CC      fs/configfs/item.o
  CC      kernel/irq/irqdomain.o
  CC      kernel/power/poweroff.o
  AR      arch/x86/kernel/cpu/mce/built-in.a
  CC      arch/x86/kernel/cpu/common.o
  CC      fs/sysfs/mount.o
  CC      net/core/stream.o
  CC      fs/proc/generic.o
  AR      lib/crypto/built-in.a
  LD [M]  lib/crypto/libarc4.o
  CC      io_uring/epoll.o
  CC      sound/core/misc.o
  CC      crypto/acompress.o
  AR      fs/kernfs/built-in.a
  CC      mm/percpu.o
  CC      fs/sysfs/group.o
  CC      lib/zlib_deflate/deflate_syms.o
  CC      kernel/irq/proc.o
  CC      arch/x86/kernel/apic/x2apic_cluster.o
  AR      kernel/power/built-in.a
  CC      drivers/video/console/dummycon.o
  CC      arch/x86/mm/srat.o
  CC      drivers/pci/hotplug/acpi_pcihp.o
  CC      drivers/video/logo/logo.o
  CC      drivers/pci/hotplug/pciehp_core.o
  CC      fs/iomap/swapfile.o
  CC      drivers/video/console/vgacon.o
  CC      mm/slab_common.o
  AR      drivers/pci/controller/built-in.a
  AR      drivers/pci/switch/built-in.a
  CC      drivers/pci/access.o
  AR      fs/configfs/built-in.a
  CC      fs/devpts/inode.o
  CC      drivers/pci/bus.o
  CC      block/ioctl.o
  CC      kernel/locking/lockdep_proc.o
  AR      lib/zlib_deflate/built-in.a
  AR      kernel/dma/built-in.a
  CC      mm/compaction.o
  CC      lib/lzo/lzo1x_compress.o
  CC      lib/lzo/lzo1x_decompress_safe.o
  CC [M]  sound/pci/hda/patch_realtek.o
  HOSTCC  drivers/video/logo/pnmtologo
  CC      arch/x86/kernel/head64.o
  CC      drivers/pci/hotplug/pciehp_ctrl.o
  AR      sound/pci/rme9652/built-in.a
  CC      kernel/irq/migration.o
  CC      fs/ext4/balloc.o
  CC      fs/jbd2/transaction.o
  CC      fs/ramfs/inode.o
  CC      io_uring/statx.o
  AR      fs/sysfs/built-in.a
  CC      fs/ramfs/file-mmu.o
  CC      crypto/scompress.o
  CC      fs/jbd2/commit.o
  CC      fs/hugetlbfs/inode.o
  CC      arch/x86/mm/pkeys.o
  CC      arch/x86/mm/pti.o
  CC      arch/x86/kernel/apic/apic_flat_64.o
  LOGO    drivers/video/logo/logo_linux_clut224.c
  CC      drivers/video/logo/logo_linux_clut224.o
  CC      sound/core/device.o
  CC      crypto/algboss.o
  AR      drivers/video/logo/built-in.a
  CC      mm/show_mem.o
  CC      net/core/scm.o
  CC      fs/ext4/bitmap.o
  AR      fs/iomap/built-in.a
  CC      sound/core/info.o
  CC      drivers/video/backlight/backlight.o
  CC      fs/proc/array.o
  AR      lib/lzo/built-in.a
  CC      lib/lz4/lz4_compress.o
  CC      lib/zstd/zstd_compress_module.o
  CC      drivers/pci/pcie/err.o
  CC      kernel/locking/spinlock.o
  CC      kernel/irq/cpuhotplug.o
  CC      lib/lz4/lz4hc_compress.o
  AR      fs/devpts/built-in.a
  CC      lib/lz4/lz4_decompress.o
  CC      crypto/testmgr.o
  CC      drivers/pci/probe.o
  CC      drivers/idle/intel_idle.o
  CC      drivers/pci/host-bridge.o
  CC      drivers/pci/remove.o
  AR      drivers/video/console/built-in.a
  CC      drivers/pci/hotplug/pciehp_pci.o
  CC      arch/x86/kernel/apic/probe_64.o
  AR      sound/pci/trident/built-in.a
  CC      mm/interval_tree.o
  AR      drivers/char/ipmi/built-in.a
  CC      sound/core/isadma.o
  CC      arch/x86/kernel/cpu/rdrand.o
  CC      fs/jbd2/recovery.o
  AR      fs/ramfs/built-in.a
  CC      fs/proc/fd.o
  CC      sound/core/vmaster.o
  CC      io_uring/net.o
  AR      kernel/rcu/built-in.a
  AR      arch/x86/events/intel/built-in.a
  CC      arch/x86/events/zhaoxin/core.o
  CC      drivers/acpi/acpica/dsargs.o
  CC      lib/zstd/compress/fse_compress.o
  AR      arch/x86/mm/built-in.a
  CC      kernel/locking/osq_lock.o
  CC      drivers/acpi/acpica/dscontrol.o
  CC      drivers/acpi/acpica/dsdebug.o
  CC      arch/x86/kernel/cpu/match.o
  CC      lib/zstd/compress/hist.o
  AR      arch/x86/kernel/apic/built-in.a
  CC      drivers/acpi/numa/srat.o
  CC      drivers/acpi/apei/apei-base.o
  CC      sound/core/ctljack.o
  CC      arch/x86/events/core.o
  CC      kernel/irq/pm.o
  CC      drivers/pci/pcie/aer_inject.o
  CC      mm/list_lru.o
  CC      fs/fat/cache.o
  CC      kernel/locking/qspinlock.o
  CC      arch/x86/kernel/ebda.o
  AR      drivers/video/backlight/built-in.a
  CC      lib/zstd/compress/huf_compress.o
  CC      drivers/video/fbdev/core/fb_notify.o
  AR      drivers/video/fbdev/omap/built-in.a
  CC      fs/fat/dir.o
  CC      fs/fat/fatent.o
  CC      sound/core/jack.o
  CC      drivers/video/aperture.o
  CC      fs/ext4/block_validity.o
  CC      drivers/acpi/acpica/dsfield.o
  CC      arch/x86/kernel/cpu/bugs.o
  CC      net/core/gen_stats.o
  CC [M]  drivers/video/fbdev/core/fb_info.o
  CC      drivers/pci/hotplug/pciehp_hpc.o
  CC      sound/core/timer.o
  CC      drivers/pnp/pnpacpi/core.o
  AR      fs/hugetlbfs/built-in.a
  AR      drivers/amba/built-in.a
  CC      sound/core/hrtimer.o
  CC      fs/proc/proc_tty.o
  AR      drivers/clk/actions/built-in.a
  AR      drivers/clk/analogbits/built-in.a
  AR      drivers/clk/bcm/built-in.a
  AR      drivers/clk/imgtec/built-in.a
  CC      drivers/dma/dw/core.o
  CC      drivers/dma/hsu/hsu.o
  AR      drivers/clk/imx/built-in.a
  CC      drivers/dma/dw/dw.o
  AR      drivers/clk/ingenic/built-in.a
  AR      drivers/clk/mediatek/built-in.a
  AR      drivers/clk/microchip/built-in.a
  AR      drivers/clk/mstar/built-in.a
  CC      drivers/dma/dw/idma32.o
  AR      arch/x86/events/zhaoxin/built-in.a
  AR      drivers/clk/mvebu/built-in.a
  CC      drivers/dma/dw/acpi.o
  AR      drivers/clk/ralink/built-in.a
  AR      drivers/clk/renesas/built-in.a
  CC      kernel/locking/rtmutex_api.o
  CC      fs/jbd2/checkpoint.o
  AR      drivers/clk/socfpga/built-in.a
  CC      block/genhd.o
  AR      drivers/clk/sprd/built-in.a
  CC      fs/proc/cmdline.o
  AR      drivers/clk/starfive/built-in.a
  AR      drivers/clk/sunxi-ng/built-in.a
  AR      drivers/idle/built-in.a
  AR      drivers/clk/ti/built-in.a
  AR      drivers/acpi/numa/built-in.a
  CC      net/netlink/policy.o
  CC      fs/ext4/dir.o
  CC      fs/ext4/ext4_jbd2.o
  AR      drivers/clk/versatile/built-in.a
  CC      drivers/clk/x86/clk-lpss-atom.o
  CC      lib/xz/xz_dec_syms.o
  CC      io_uring/msg_ring.o
  CC      kernel/irq/msi.o
  CC      drivers/acpi/acpica/dsinit.o
  CC      drivers/acpi/apei/hest.o
  CC      drivers/pci/pcie/pme.o
  CC      fs/proc/consoles.o
  CC      drivers/pci/pcie/dpc.o
  AR      lib/lz4/built-in.a
  CC      kernel/locking/spinlock_debug.o
  CC      drivers/clk/x86/clk-pmc-atom.o
  AR      drivers/clk/xilinx/built-in.a
  CC      drivers/clk/clk-devres.o
  CC      sound/core/seq_device.o
  AR      drivers/acpi/pmic/built-in.a
  CC      drivers/pnp/pnpacpi/rsparser.o
  CC [M]  drivers/video/fbdev/core/fbmem.o
  CC      drivers/video/cmdline.o
  CC      lib/xz/xz_dec_stream.o
  CC      fs/jbd2/revoke.o
  CC      lib/xz/xz_dec_lzma2.o
  CC      lib/raid6/algos.o
  CC      io_uring/timeout.o
  CC      drivers/dma/dw/pci.o
  CC      lib/xz/xz_dec_bcj.o
  CC      lib/raid6/recov.o
  CC      drivers/acpi/acpica/dsmethod.o
  CC      fs/ext4/extents.o
  CC      net/core/gen_estimator.o
  CC      net/core/net_namespace.o
  CC      io_uring/sqpoll.o
  CC [M]  sound/core/control_led.o
  AR      drivers/dma/hsu/built-in.a
  CC      fs/proc/cpuinfo.o
  CC      drivers/pci/hotplug/acpiphp_core.o
  AR      drivers/dma/idxd/built-in.a
  AR      drivers/dma/mediatek/built-in.a
  CC      drivers/clk/clk-bulk.o
  CC [M]  sound/pci/hda/patch_analog.o
  CC      drivers/clk/clkdev.o
  CC      io_uring/fdinfo.o
  AR      drivers/clk/x86/built-in.a
  CC      kernel/locking/qrwlock.o
  CC      net/netlink/diag.o
  CC      drivers/acpi/apei/erst.o
  CC [M]  drivers/video/fbdev/core/fbcmap.o
  CC      fs/fat/file.o
  AR      drivers/pci/pcie/built-in.a
  CC      fs/proc/devices.o
  CC      block/ioprio.o
  CC      lib/zstd/compress/zstd_compress.o
  CC      drivers/acpi/dptf/int340x_thermal.o
  CC      mm/workingset.o
  CC [M]  drivers/video/fbdev/core/modedb.o
  CC      fs/fat/inode.o
  CC      fs/fat/misc.o
  CC      drivers/acpi/acpica/dsmthdat.o
  CC      fs/proc/interrupts.o
  CC      fs/proc/loadavg.o
  CC      mm/debug.o
  AR      drivers/dma/dw/built-in.a
  AR      drivers/dma/qcom/built-in.a
  AR      drivers/dma/ti/built-in.a
  CC      crypto/cmac.o
  AR      drivers/dma/xilinx/built-in.a
  HOSTCC  lib/raid6/mktables
  CC [M]  drivers/dma/ioat/init.o
  CC      arch/x86/kernel/cpu/aperfmperf.o
  AR      lib/xz/built-in.a
  CC [M]  drivers/dma/ioat/dma.o
  CC      crypto/hmac.o
  CC      arch/x86/events/probe.o
  CC      drivers/dma/dmaengine.o
  CC      crypto/vmac.o
  CC      kernel/irq/affinity.o
  CC [M]  arch/x86/kvm/../../../virt/kvm/eventfd.o
  CC      net/core/secure_seq.o
  CC      fs/jbd2/journal.o
  CC      fs/proc/meminfo.o
  AR      drivers/pnp/pnpacpi/built-in.a
  CC      drivers/pnp/core.o
  CC      drivers/clk/clk.o
  AR      kernel/locking/built-in.a
  CC      drivers/pci/hotplug/acpiphp_glue.o
  UNROLL  lib/raid6/int1.c
  CC      kernel/irq/matrix.o
  UNROLL  lib/raid6/int2.c
  UNROLL  lib/raid6/int4.c
  UNROLL  lib/raid6/int8.c
  UNROLL  lib/raid6/int16.c
  UNROLL  lib/raid6/int32.c
  CC      net/core/flow_dissector.o
  CC      lib/raid6/recov_ssse3.o
  CC      drivers/video/nomodeset.o
  AR      drivers/acpi/dptf/built-in.a
  CC      arch/x86/kernel/cpu/cpuid-deps.o
  CC [M]  sound/core/hwdep.o
  CC      io_uring/tctx.o
  CC      fs/proc/stat.o
  CC [M]  drivers/dma/ioat/prep.o
  CC [M]  sound/pci/hda/patch_hdmi.o
  CC      io_uring/poll.o
  CC      fs/ext4/extents_status.o
  CC      drivers/acpi/acpica/dsobject.o
  CC      arch/x86/events/utils.o
  CC      arch/x86/kernel/cpu/umwait.o
  CC      fs/fat/nfs.o
  CC      fs/nfs/client.o
  CC      fs/exportfs/expfs.o
  CC      io_uring/cancel.o
  CC      crypto/xcbc.o
  CC      block/badblocks.o
  CC      crypto/crypto_null.o
  CC      crypto/md5.o
  AR      net/netlink/built-in.a
  CC      block/blk-rq-qos.o
  CC      lib/zstd/compress/zstd_compress_literals.o
  CC      fs/ext4/file.o
  CC      drivers/clk/clk-divider.o
  CC      io_uring/kbuf.o
  CC      drivers/acpi/apei/bert.o
  CC [M]  drivers/video/fbdev/core/fbcvt.o
  CC      mm/gup.o
  CC      arch/x86/kernel/cpu/proc.o
  CC      drivers/pnp/card.o
  CC      net/ethtool/ioctl.o
  CC      lib/raid6/recov_avx2.o
  CC      net/ethtool/common.o
  CC      drivers/acpi/apei/ghes.o
  CC      drivers/acpi/acpica/dsopcode.o
  CC      net/ethtool/netlink.o
  CC      drivers/video/hdmi.o
  CC      fs/proc/uptime.o
  AR      drivers/soc/apple/built-in.a
  AR      drivers/soc/aspeed/built-in.a
  AR      drivers/soc/bcm/bcm63xx/built-in.a
  AR      drivers/soc/bcm/built-in.a
  CC [M]  sound/core/pcm.o
  AR      drivers/soc/fsl/built-in.a
  CC      arch/x86/events/rapl.o
  AR      drivers/soc/fujitsu/built-in.a
  CC      crypto/sha1_generic.o
  AR      drivers/soc/imx/built-in.a
  AR      drivers/soc/ixp4xx/built-in.a
  CC [M]  drivers/video/fbdev/core/fb_cmdline.o
  AR      drivers/soc/loongson/built-in.a
  AR      drivers/soc/mediatek/built-in.a
  CC [M]  drivers/video/fbdev/core/fb_io_fops.o
  CC      net/core/sysctl_net_core.o
  AR      drivers/soc/microchip/built-in.a
  AR      kernel/sched/built-in.a
  CC      fs/fat/namei_vfat.o
  AR      fs/exportfs/built-in.a
  AR      drivers/soc/nuvoton/built-in.a
  CC      drivers/acpi/tables.o
  MKCAP   arch/x86/kernel/cpu/capflags.c
  AR      drivers/soc/pxa/built-in.a
  CC      arch/x86/kernel/cpu/powerflags.o
  AR      drivers/soc/amlogic/built-in.a
  CC [M]  drivers/dma/ioat/dca.o
  AR      drivers/soc/qcom/built-in.a
  AR      drivers/soc/renesas/built-in.a
  CC [M]  drivers/dma/ioat/sysfs.o
  AR      drivers/pci/hotplug/built-in.a
  AR      drivers/soc/rockchip/built-in.a
  CC      drivers/pci/pci.o
  CC      drivers/clk/clk-fixed-factor.o
  AR      drivers/soc/sifive/built-in.a
  AR      drivers/soc/sunxi/built-in.a
  AR      drivers/soc/ti/built-in.a
  CC      arch/x86/kernel/cpu/feat_ctl.o
  AR      drivers/soc/xilinx/built-in.a
  AR      drivers/soc/built-in.a
  CC      block/disk-events.o
  CC      drivers/dma/virt-dma.o
  AR      drivers/video/fbdev/omap2/omapfb/dss/built-in.a
  AR      drivers/video/fbdev/omap2/omapfb/displays/built-in.a
  AR      drivers/video/fbdev/omap2/omapfb/built-in.a
  CC      drivers/dma/acpi-dma.o
  AR      drivers/video/fbdev/omap2/built-in.a
  CC      drivers/clk/clk-fixed-rate.o
  CC [M]  arch/x86/kvm/../../../virt/kvm/binary_stats.o
  CC      drivers/acpi/acpica/dspkginit.o
  CC      fs/proc/util.o
  CC      io_uring/rsrc.o
  AR      kernel/irq/built-in.a
  CC      drivers/virtio/virtio.o
  CC      kernel/entry/common.o
  CC      kernel/entry/syscall_user_dispatch.o
  CC      kernel/module/main.o
  CC      lib/raid6/mmx.o
  CC      kernel/entry/kvm.o
  CC      lib/raid6/sse1.o
  CC      kernel/module/strict_rwx.o
  CC      lib/raid6/sse2.o
  CC      drivers/pnp/driver.o
  CC      arch/x86/kernel/cpu/intel.o
  CC      mm/mmap_lock.o
  CC      crypto/sha256_generic.o
  CC [M]  sound/pci/hda/hda_eld.o
  CC      fs/fat/namei_msdos.o
  CC      net/ethtool/bitset.o
  CC      fs/ext4/fsmap.o
  CC      drivers/clk/clk-gate.o
  CC [M]  net/netfilter/ipvs/ip_vs_conn.o
  CC      io_uring/rw.o
  CC      drivers/acpi/acpica/dsutils.o
  CC      fs/proc/version.o
  CC      net/netfilter/core.o
  CC      drivers/acpi/acpica/dswexec.o
  CC [M]  drivers/video/fbdev/core/fb_backlight.o
  LD [M]  drivers/dma/ioat/ioatdma.o
  CC [M]  sound/core/pcm_native.o
  CC      net/netfilter/nf_log.o
  CC      arch/x86/events/msr.o
  CC      crypto/sha512_generic.o
  CC      arch/x86/kernel/cpu/intel_pconfig.o
  AR      drivers/acpi/apei/built-in.a
  CC      mm/highmem.o
  CC      fs/proc/softirqs.o
  CC      kernel/module/kmod.o
  CC      block/blk-ia-ranges.o
  AR      drivers/dma/built-in.a
  CC      kernel/time/time.o
  CC      drivers/pnp/resource.o
  CC [M]  arch/x86/kvm/../../../virt/kvm/vfio.o
  CC      mm/memory.o
  CC      drivers/virtio/virtio_ring.o
  CC      kernel/time/timer.o
  CC      lib/raid6/avx2.o
  CC      drivers/acpi/acpica/dswload.o
  CC [M]  arch/x86/kvm/../../../virt/kvm/coalesced_mmio.o
  CC      fs/nfs/dir.o
  CC      arch/x86/kernel/platform-quirks.o
  CC      lib/raid6/avx512.o
  CC      net/core/dev.o
  CC      net/netfilter/nf_queue.o
  CC      io_uring/opdef.o
  CC      fs/ext4/fsync.o
  AR      kernel/entry/built-in.a
  CC      net/core/dev_addr_lists.o
  CC      lib/raid6/recov_avx512.o
  CC [M]  drivers/video/fbdev/uvesafb.o
  CC      net/core/dst.o
  CC      fs/proc/namespaces.o
  CC [M]  sound/pci/hda/hda_intel.o
  AR      fs/fat/built-in.a
  CC [M]  drivers/video/fbdev/core/fbmon.o
  AR      sound/pci/ymfpci/built-in.a
  AR      sound/pci/vx222/built-in.a
  LD [M]  sound/pci/hda/snd-hda-codec.o
  CC [M]  sound/core/pcm_lib.o
  CC [M]  arch/x86/kvm/../../../virt/kvm/async_pf.o
  CC      drivers/pnp/manager.o
  AR      arch/x86/events/built-in.a
  CC      drivers/virtio/virtio_anchor.o
  CC      fs/nfs/file.o
  CC      drivers/virtio/virtio_pci_modern_dev.o
  CC      drivers/acpi/acpica/dswload2.o
  CC      crypto/sha3_generic.o
  CC      block/early-lookup.o
  CC      kernel/module/tree_lookup.o
  CC      lib/zstd/compress/zstd_compress_sequences.o
  AR      fs/jbd2/built-in.a
  CC      block/bsg.o
  CC      net/ethtool/strset.o
  CC      drivers/pci/pci-driver.o
  CC      drivers/virtio/virtio_pci_legacy_dev.o
  CC      drivers/virtio/virtio_pci_modern.o
  TABLE   lib/raid6/tables.c
  CC      drivers/clk/clk-multiplier.o
  CC      lib/raid6/int1.o
  LD [M]  sound/pci/hda/snd-hda-codec-generic.o
  CC      arch/x86/kernel/process_64.o
  CC      kernel/time/hrtimer.o
  CC      drivers/virtio/virtio_pci_common.o
  AR      net/ipv4/netfilter/built-in.a
  CC      net/xfrm/xfrm_policy.o
  CC [M]  net/ipv4/netfilter/nf_defrag_ipv4.o
  CC      drivers/virtio/virtio_pci_legacy.o
  CC [M]  net/ipv4/netfilter/nf_reject_ipv4.o
  CC      lib/zstd/compress/zstd_compress_superblock.o
  CC      drivers/pnp/support.o
  CC      net/ipv4/route.o
  CC      drivers/acpi/acpica/dswscope.o
  CC      net/xfrm/xfrm_state.o
  CC      fs/proc/self.o
  LD [M]  sound/pci/hda/snd-hda-codec-realtek.o
  CC      net/ipv4/inetpeer.o
  CC      crypto/blake2b_generic.o
  CC      fs/ext4/hash.o
  CC      drivers/acpi/acpica/dswstate.o
  CC      net/unix/af_unix.o
  CC      io_uring/notif.o
  CC      drivers/acpi/acpica/evevent.o
  CC [M]  drivers/video/fbdev/simplefb.o
  CC      block/bsg-lib.o
  CC      net/netfilter/nf_sockopt.o
  CC      lib/zstd/compress/zstd_double_fast.o
  CC      drivers/clk/clk-mux.o
  CC      net/unix/garbage.o
  CC [M]  arch/x86/kvm/../../../virt/kvm/irqchip.o
  CC      fs/ext4/ialloc.o
  CC      block/blk-cgroup.o
  CC [M]  net/netfilter/ipvs/ip_vs_core.o
  CC      lib/raid6/int2.o
  CC      fs/nfs/getroot.o
  CC      drivers/acpi/acpica/evgpe.o
  CC      net/ethtool/linkinfo.o
  CC      drivers/pnp/interface.o
  CC      block/blk-cgroup-rwstat.o
  CC      kernel/module/debug_kmemleak.o
  CC      fs/proc/thread_self.o
  CC      kernel/module/kallsyms.o
  CC      drivers/clk/clk-composite.o
  CC [M]  drivers/video/fbdev/core/fb_defio.o
  CC      drivers/acpi/blacklist.o
  CC [M]  drivers/virtio/virtio_mem.o
  CC      net/ethtool/linkmodes.o
  CC      net/ipv4/protocol.o
  CC      block/blk-throttle.o
  AR      net/ipv6/netfilter/built-in.a
  CC [M]  net/ipv6/netfilter/nf_defrag_ipv6_hooks.o
  CC [M]  net/ipv6/netfilter/nf_conntrack_reasm.o
  LD [M]  sound/pci/hda/snd-hda-codec-analog.o
  CC      arch/x86/kernel/signal.o
  CC      arch/x86/kernel/cpu/tsx.o
  CC      mm/mincore.o
  LD [M]  sound/pci/hda/snd-hda-codec-hdmi.o
  CC      drivers/acpi/acpica/evgpeblk.o
  LD [M]  sound/pci/hda/snd-hda-intel.o
  CC      drivers/pci/search.o
  CC [M]  net/netfilter/ipvs/ip_vs_ctl.o
  CC      crypto/ecb.o
  CC      mm/mlock.o
  CC [M]  net/netfilter/ipvs/ip_vs_sched.o
  AR      sound/pci/built-in.a
  CC      lib/raid6/int4.o
  CC      net/unix/sysctl_net_unix.o
  CC      kernel/futex/core.o
  CC      drivers/pnp/quirks.o
  CC      kernel/cgroup/cgroup.o
  CC      fs/proc/proc_sysctl.o
  CC      kernel/cgroup/rstat.o
  CC      io_uring/io-wq.o
  CC      fs/ext4/indirect.o
  CC      net/ipv4/ip_input.o
  CC [M]  arch/x86/kvm/../../../virt/kvm/dirty_ring.o
  CC      block/mq-deadline.o
  CC      net/netfilter/utils.o
  CC      drivers/clk/clk-fractional-divider.o
  CC      kernel/time/timekeeping.o
  CC [M]  net/netfilter/nfnetlink.o
  CC [M]  net/ipv4/netfilter/ip_tables.o
  CC      net/ethtool/rss.o
  CC      kernel/time/ntp.o
  CC      arch/x86/kernel/cpu/intel_epb.o
  CC      kernel/module/procfs.o
  CC      crypto/cbc.o
  CC      drivers/acpi/acpica/evgpeinit.o
  CC [M]  drivers/video/fbdev/core/fb_chrdev.o
  CC [M]  sound/core/pcm_misc.o
  CC      net/ipv4/ip_fragment.o
  CC      drivers/pci/pci-sysfs.o
  CC      lib/raid6/int8.o
  CC [M]  drivers/video/fbdev/core/fb_procfs.o
  CC [M]  net/ipv4/netfilter/iptable_filter.o
  CC [M]  net/ipv4/netfilter/iptable_mangle.o
  CC      drivers/pnp/system.o
  CC      arch/x86/kernel/cpu/amd.o
  CC      drivers/clk/clk-gpio.o
  CC      net/ipv6/af_inet6.o
  CC      drivers/acpi/acpica/evgpeutil.o
  CC      fs/nfs/inode.o
  CC      crypto/pcbc.o
  CC      kernel/module/sysfs.o
  AR      sound/sh/built-in.a
  CC      drivers/acpi/acpica/evglock.o
  CC      kernel/futex/syscalls.o
  CC [M]  net/netfilter/ipvs/ip_vs_xmit.o
  CC      drivers/acpi/acpica/evhandler.o
  CC [M]  arch/x86/kvm/../../../virt/kvm/pfncache.o
  CC      kernel/time/clocksource.o
  CC      block/kyber-iosched.o
  CC      net/ethtool/linkstate.o
  AR      drivers/pnp/built-in.a
  CC      crypto/cts.o
  CC      drivers/acpi/acpica/evmisc.o
  AR      drivers/clk/built-in.a
  LD [M]  net/ipv6/netfilter/nf_defrag_ipv6.o
  AR      drivers/virtio/built-in.a
  CC      crypto/lrw.o
  CC      drivers/acpi/acpica/evregion.o
  CC      net/ethtool/debug.o
  CC      kernel/futex/pi.o
  CC [M]  sound/core/pcm_memory.o
  CC      net/ipv6/anycast.o
  CC      lib/raid6/int16.o
  CC      fs/ext4/inline.o
  CC      fs/nfs/super.o
  CC [M]  drivers/video/fbdev/core/fbsysfs.o
  CC [M]  arch/x86/kvm/x86.o
  CC      net/ipv4/ip_forward.o
  CC [M]  arch/x86/kvm/emulate.o
  CC      net/ethtool/wol.o
  CC      lib/fonts/fonts.o
  CC      net/ipv4/ip_options.o
  CC      lib/fonts/font_8x8.o
  CC      fs/proc/proc_net.o
  CC [M]  net/ipv4/netfilter/iptable_nat.o
  AR      io_uring/built-in.a
  CC      drivers/acpi/acpica/evrgnini.o
  CC      lib/zstd/compress/zstd_fast.o
  AR      kernel/module/built-in.a
  CC [M]  arch/x86/kvm/i8259.o
  CC      kernel/cgroup/namespace.o
  CC      fs/lockd/clntlock.o
  CC      fs/nls/nls_base.o
  CC      net/unix/diag.o
  CC      fs/ext4/inode.o
  CC      fs/lockd/clntproc.o
  CC      fs/nls/nls_cp437.o
  CC      arch/x86/kernel/cpu/hygon.o
  CC      drivers/pci/rom.o
  CC      lib/fonts/font_8x16.o
  CC      arch/x86/kernel/signal_64.o
  CC      drivers/acpi/acpica/evsci.o
  CC      net/ipv4/ip_output.o
  CC      lib/raid6/int32.o
  CC [M]  net/netfilter/ipvs/ip_vs_app.o
  CC      kernel/futex/requeue.o
  CC [M]  sound/core/memalloc.o
  CC [M]  net/netfilter/nf_conntrack_core.o
  CC      kernel/time/jiffies.o
  CC      crypto/xts.o
  CC      net/ipv4/ip_sockglue.o
  CC      fs/lockd/clntxdr.o
  CC      fs/lockd/host.o
  CC      mm/mmap.o
  CC      fs/nls/nls_ascii.o
  CC [M]  arch/x86/kvm/irq.o
  CC      net/ethtool/features.o
  AR      lib/fonts/built-in.a
  CC      lib/argv_split.o
  CC [M]  drivers/video/fbdev/core/fbcon.o
  CC      drivers/acpi/acpica/evxface.o
  CC      arch/x86/kernel/cpu/centaur.o
  CC      crypto/ctr.o
  CC      net/ethtool/privflags.o
  CC      fs/proc/kcore.o
  CC      kernel/time/timer_list.o
  CC [M]  arch/x86/kvm/lapic.o
  CC      drivers/pci/setup-res.o
  CC      lib/raid6/tables.o
  CC      mm/mmu_gather.o
  CC      kernel/futex/waitwake.o
  CC      fs/nls/nls_iso8859-1.o
  CC      net/ipv6/ip6_output.o
  CC [M]  net/ipv4/netfilter/ipt_REJECT.o
  CC      lib/bug.o
  CC      net/xfrm/xfrm_hash.o
  CC      block/bfq-iosched.o
  CC      net/ipv4/inet_hashtables.o
  CC      net/unix/scm.o
  CC      drivers/acpi/osi.o
  CC      drivers/pci/irq.o
  CC      block/bfq-wf2q.o
  CC      kernel/trace/trace_clock.o
  CC [M]  net/netfilter/ipvs/ip_vs_sync.o
  CC      drivers/acpi/acpica/evxfevnt.o
  CC      arch/x86/kernel/cpu/zhaoxin.o
  CC      fs/lockd/svc.o
  CC      crypto/gcm.o
  CC      drivers/acpi/acpica/evxfgpe.o
  CC      fs/nls/nls_utf8.o
  CC      net/ethtool/rings.o
  CC [M]  sound/core/pcm_timer.o
  CC      lib/zstd/compress/zstd_lazy.o
  CC      kernel/time/timeconv.o
  CC      fs/lockd/svclock.o
  CC      arch/x86/kernel/cpu/perfctr-watchdog.o
  CC      kernel/trace/ftrace.o
  AR      kernel/futex/built-in.a
  LD [M]  sound/core/snd-ctl-led.o
  AR      lib/raid6/built-in.a
  CC      fs/nfs/io.o
  CC      arch/x86/kernel/traps.o
  CC      arch/x86/kernel/idt.o
  CC      fs/ext4/ioctl.o
  CC      net/xfrm/xfrm_input.o
  CC      drivers/pci/vpd.o
  CC      kernel/bpf/core.o
  CC      fs/proc/kmsg.o
  CC      drivers/acpi/osl.o
  CC      lib/buildid.o
  CC      net/xfrm/xfrm_output.o
  CC      lib/zstd/compress/zstd_ldm.o
  CC      kernel/events/core.o
  CC      lib/zstd/compress/zstd_opt.o
  AR      fs/nls/built-in.a
  CC      kernel/fork.o
  CC      net/ethtool/channels.o
  CC      arch/x86/kernel/irq.o
  CC      drivers/acpi/acpica/evxfregn.o
  CC      kernel/events/ring_buffer.o
  AR      fs/unicode/built-in.a
  CC      kernel/trace/ring_buffer.o
  CC      kernel/time/timecounter.o
  CC      kernel/time/alarmtimer.o
  LD [M]  sound/core/snd-hwdep.o
  LD [M]  sound/core/snd-pcm.o
  AR      sound/core/built-in.a
  AR      sound/synth/emux/built-in.a
  AR      sound/synth/built-in.a
  CC      kernel/time/posix-timers.o
  AR      sound/usb/misc/built-in.a
  AR      net/unix/built-in.a
  AR      sound/usb/usx2y/built-in.a
  CC      kernel/trace/trace.o
  AR      sound/usb/caiaq/built-in.a
  AR      sound/usb/6fire/built-in.a
  AR      sound/usb/hiface/built-in.a
  AR      sound/usb/bcd2000/built-in.a
  AR      sound/usb/built-in.a
  AR      sound/firewire/built-in.a
  AR      sound/sparc/built-in.a
  CC      arch/x86/kernel/cpu/vmware.o
  CC      fs/proc/page.o
  AR      sound/spi/built-in.a
  AR      sound/parisc/built-in.a
  AR      sound/pcmcia/vx/built-in.a
  AR      sound/pcmcia/pdaudiocf/built-in.a
  AR      sound/pcmcia/built-in.a
  CC      drivers/acpi/acpica/exconcat.o
  AR      sound/mips/built-in.a
  CC      arch/x86/kernel/irq_64.o
  AR      sound/soc/built-in.a
  AR      sound/atmel/built-in.a
  AR      sound/hda/built-in.a
  AR      sound/x86/built-in.a
  CC [M]  sound/hda/hda_bus_type.o
  CC      drivers/tty/vt/vt_ioctl.o
  CC      drivers/tty/hvc/hvc_console.o
  CC      drivers/tty/serial/8250/8250_core.o
  CC      drivers/tty/serial/serial_core.o
  CC      crypto/pcrypt.o
  CC      drivers/pci/setup-bus.o
  CC      drivers/tty/serial/8250/8250_pnp.o
  CC      net/ethtool/coalesce.o
  CC [M]  drivers/video/fbdev/core/bitblit.o
  CC      fs/nfs/direct.o
  CC      arch/x86/kernel/dumpstack_64.o
  CC      drivers/acpi/acpica/exconfig.o
  CC [M]  arch/x86/kvm/i8254.o
  CC      arch/x86/kernel/cpu/hypervisor.o
  CC      fs/lockd/svcshare.o
  CC      net/ipv4/inet_timewait_sock.o
  CC      kernel/cgroup/cgroup-v1.o
  CC      fs/nfs/pagelist.o
  CC [M]  sound/hda/hdac_bus.o
  CC      crypto/cryptd.o
  CC      net/core/netevent.o
  CC      arch/x86/kernel/cpu/mshyperv.o
  AR      drivers/tty/ipwireless/built-in.a
  CC      drivers/tty/tty_io.o
  CC [M]  net/netfilter/ipvs/ip_vs_est.o
  AR      fs/proc/built-in.a
  CC      drivers/acpi/utils.o
  CC      kernel/time/posix-cpu-timers.o
  CC      drivers/tty/serial/8250/8250_port.o
  CC      drivers/acpi/acpica/exconvrt.o
  CC [M]  arch/x86/kvm/ioapic.o
  CC      arch/x86/kernel/time.o
  AR      drivers/tty/hvc/built-in.a
  CC      crypto/des_generic.o
  CC      drivers/acpi/acpica/excreate.o
  CC      fs/ntfs/aops.o
  CC      drivers/tty/vt/vc_screen.o
  CC      fs/ntfs/attrib.o
  CC      drivers/tty/serial/8250/8250_dma.o
  CC      fs/ext4/mballoc.o
  CC      net/xfrm/xfrm_sysctl.o
  CC      crypto/aes_generic.o
  CC [M]  drivers/video/fbdev/core/softcursor.o
  CC      kernel/cgroup/freezer.o
  CC      fs/ntfs/collate.o
  CC      net/ethtool/pause.o
  CC      fs/ext4/migrate.o
  CC [M]  sound/hda/hdac_device.o
  CC      mm/mprotect.o
  CC [M]  net/netfilter/ipvs/ip_vs_proto.o
  CC      lib/zstd/zstd_decompress_module.o
  CC      drivers/acpi/reboot.o
  CC      mm/mremap.o
  CC      drivers/acpi/acpica/exdebug.o
  CC      net/core/neighbour.o
  CC      fs/lockd/svcproc.o
  CC      kernel/time/posix-clock.o
  CC      arch/x86/kernel/cpu/capflags.o
  AR      arch/x86/kernel/cpu/built-in.a
  CC      arch/x86/kernel/ioport.o
  CC [M]  net/netfilter/nf_conntrack_standalone.o
  CC      crypto/deflate.o
  CC      net/ipv4/inet_connection_sock.o
  CC      drivers/pci/vc.o
  CC      net/xfrm/xfrm_replay.o
  CC      net/ethtool/eee.o
  CC [M]  net/netfilter/ipvs/ip_vs_pe.o
  CC      net/ipv6/ip6_input.o
  AR      kernel/bpf/built-in.a
  CC [M]  sound/hda/hdac_sysfs.o
  CC      drivers/acpi/acpica/exdump.o
  CC      block/bfq-cgroup.o
  CC [M]  drivers/video/fbdev/core/tileblit.o
  CC      drivers/tty/vt/selection.o
  CC      drivers/acpi/acpica/exfield.o
  CC [M]  arch/x86/kvm/irq_comm.o
  CC      net/xfrm/xfrm_device.o
  CC [M]  net/netfilter/nf_conntrack_expect.o
  CC      kernel/cgroup/legacy_freezer.o
  CC [M]  net/netfilter/nf_conntrack_helper.o
  CC      arch/x86/kernel/dumpstack.o
  CC      net/ipv6/addrconf.o
  CC      fs/ntfs/compress.o
  CC      drivers/acpi/acpica/exfldio.o
  CC      net/ethtool/tsinfo.o
  CC [M]  sound/hda/hdac_regmap.o
  CC      kernel/time/itimer.o
  CC      fs/ext4/mmp.o
  CC [M]  sound/hda/hdac_controller.o
  CC      lib/cmdline.o
  CC [M]  sound/hda/hdac_stream.o
  CC      crypto/crc32c_generic.o
  CC      fs/nfs/read.o
  CC      drivers/tty/serial/serial_base_bus.o
  CC      fs/lockd/svcsubs.o
  CC      arch/x86/kernel/nmi.o
  CC      lib/cpumask.o
  CC      fs/ext4/move_extent.o
  CC      drivers/pci/mmap.o
  CC      fs/lockd/mon.o
  CC      drivers/acpi/nvs.o
  CC      lib/ctype.o
  CC      drivers/char/hw_random/core.o
  CC      lib/dec_and_lock.o
  CC      drivers/char/agp/backend.o
  CC      mm/msync.o
  CC      drivers/char/agp/generic.o
  CC      crypto/crct10dif_common.o
  CC      drivers/tty/vt/keyboard.o
  CC      drivers/acpi/acpica/exmisc.o
  CC [M]  drivers/video/fbdev/core/cfbfillrect.o
  CC      drivers/char/agp/isoch.o
  CC      drivers/tty/serial/8250/8250_dwlib.o
  CC      fs/ext4/namei.o
  CC      drivers/acpi/acpica/exmutex.o
  CC      lib/zstd/decompress/huf_decompress.o
  CC [M]  net/netfilter/ipvs/ip_vs_proto_tcp.o
  CC      block/blk-mq-pci.o
  CC      kernel/cgroup/pids.o
  CC [M]  drivers/video/fbdev/core/cfbcopyarea.o
  CC      fs/ext4/page-io.o
  CC      drivers/char/tpm/tpm-chip.o
  CC      drivers/char/mem.o
  CC [M]  drivers/video/fbdev/core/cfbimgblt.o
  CC      crypto/crct10dif_generic.o
  CC      kernel/time/clockevents.o
  CC [M]  sound/hda/array.o
  CC      net/ethtool/cabletest.o
  CC [M]  arch/x86/kvm/cpuid.o
  CC [M]  sound/hda/hdmi_chmap.o
  CC      kernel/time/tick-common.o
  CC      drivers/pci/setup-irq.o
  CC      lib/decompress.o
  CC [M]  net/netfilter/nf_conntrack_proto.o
  CC      drivers/tty/serial/serial_ctrl.o
  CC      net/xfrm/xfrm_algo.o
  CC      arch/x86/kernel/ldt.o
  CC      drivers/acpi/acpica/exnames.o
  CC      fs/ntfs/debug.o
  AR      fs/hostfs/built-in.a
  CC      fs/debugfs/inode.o
  CC [M]  net/netfilter/nf_conntrack_proto_generic.o
  CC      mm/page_vma_mapped.o
  CC      fs/debugfs/file.o
  CC [M]  net/netfilter/nf_conntrack_proto_tcp.o
  CC      drivers/char/hw_random/intel-rng.o
  CC      drivers/tty/serial/8250/8250_pcilib.o
  CC      crypto/authenc.o
  CC      drivers/tty/serial/serial_port.o
  CC      block/blk-mq-virtio.o
  CC      drivers/char/random.o
  CC      fs/tracefs/inode.o
  CC      kernel/cgroup/cpuset.o
  CC      drivers/tty/n_tty.o
  CC      drivers/char/tpm/tpm-dev-common.o
  CC [M]  arch/x86/kvm/pmu.o
  CC      fs/lockd/trace.o
  CC      kernel/trace/trace_output.o
  CC      fs/nfs/symlink.o
  CC      drivers/pci/proc.o
  CC      drivers/acpi/acpica/exoparg1.o
  CC [M]  arch/x86/kvm/mtrr.o
  CC      fs/ntfs/dir.o
  CC      drivers/tty/tty_ioctl.o
  CC      drivers/char/agp/intel-agp.o
  CC [M]  drivers/video/fbdev/core/sysfillrect.o
  CC      drivers/char/tpm/tpm-dev.o
  CC      fs/btrfs/super.o
  CC      net/ipv4/tcp.o
  CC      fs/nfs/unlink.o
  CC [M]  arch/x86/kvm/hyperv.o
  CC [M]  sound/hda/trace.o
  CC      kernel/time/tick-broadcast.o
  CC      crypto/authencesn.o
  CC      drivers/tty/serial/8250/8250_pci.o
  AR      drivers/char/hw_random/built-in.a
  CC      fs/ntfs/file.o
  CC      block/blk-mq-debugfs.o
  CC [M]  net/netfilter/ipvs/ip_vs_proto_udp.o
  CC      net/ethtool/tunnels.o
  CC      arch/x86/kernel/setup.o
  CC      arch/x86/kernel/x86_init.o
  AR      fs/tracefs/built-in.a
  CC      kernel/time/tick-broadcast-hrtimer.o
  CC      drivers/tty/vt/consolemap.o
  CC      mm/pagewalk.o
  CC      fs/ntfs/index.o
  CC      net/xfrm/xfrm_user.o
  CC      drivers/acpi/acpica/exoparg2.o
  CC [M]  net/netfilter/nf_conntrack_proto_udp.o
  AR      fs/debugfs/built-in.a
  CC      fs/ext4/readpage.o
  CC      net/ethtool/fec.o
  CC      drivers/char/tpm/tpm-interface.o
  CC      drivers/pci/slot.o
  CC [M]  net/netfilter/nf_conntrack_proto_icmp.o
  CC      drivers/char/agp/intel-gtt.o
  CC      kernel/events/callchain.o
  CC [M]  drivers/video/fbdev/core/syscopyarea.o
  CC      net/core/rtnetlink.o
  HOSTCC  drivers/tty/vt/conmakehash
  CC      fs/nfs/write.o
  CC      fs/lockd/xdr.o
  CC      kernel/events/hw_breakpoint.o
  CC      drivers/pci/pci-acpi.o
  CC      kernel/time/tick-oneshot.o
  CC      drivers/acpi/acpica/exoparg3.o
  CC [M]  sound/hda/hdac_component.o
  CC [M]  arch/x86/kvm/debugfs.o
  CC      fs/nfs/namespace.o
  CC [M]  arch/x86/kvm/mmu/mmu.o
  CC      fs/ntfs/inode.o
  CC      block/blk-pm.o
  CC      crypto/lzo.o
  CC      block/holder.o
  CC      drivers/tty/vt/vt.o
  CC      fs/ext4/resize.o
  CC      drivers/pci/quirks.o
  CC      kernel/trace/trace_seq.o
  CC      net/core/utils.o
  CC      mm/pgtable-generic.o
  CC      arch/x86/kernel/i8259.o
  CC      kernel/time/tick-sched.o
  AR      drivers/iommu/amd/built-in.a
  CC      drivers/iommu/intel/dmar.o
  CC      drivers/acpi/acpica/exoparg6.o
  CC      drivers/iommu/intel/iommu.o
  CC      drivers/char/tpm/tpm1-cmd.o
  CC      fs/ext4/super.o
  CC [M]  net/netfilter/ipvs/ip_vs_nfct.o
  CC      kernel/time/vsyscall.o
  CC      drivers/tty/serial/8250/8250_exar.o
  CC      drivers/char/misc.o
  CC      net/ethtool/eeprom.o
  CC      fs/nfs/mount_clnt.o
  CC      fs/ext4/symlink.o
  CC [M]  drivers/video/fbdev/core/sysimgblt.o
  CC [M]  sound/hda/hdac_i915.o
  CC      crypto/lzo-rle.o
  CC      crypto/lz4.o
  AR      drivers/char/agp/built-in.a
  CC      drivers/char/virtio_console.o
  CC      fs/nfs/nfstrace.o
  CC      drivers/acpi/acpica/exprep.o
  AR      block/built-in.a
  CC [M]  drivers/video/fbdev/core/fb_sys_fops.o
  CC      kernel/trace/trace_stat.o
  CC      net/core/link_watch.o
  CC      crypto/lz4hc.o
  CC      arch/x86/kernel/irqinit.o
  CC      drivers/iommu/intel/pasid.o
  CC      net/ipv4/tcp_input.o
  CC      fs/lockd/clnt4xdr.o
  CC      mm/rmap.o
  CC      lib/zstd/decompress/zstd_ddict.o
  CC      fs/ntfs/mft.o
  CC      net/core/filter.o
  CC      crypto/xxhash_generic.o
  CC      drivers/pci/ats.o
  CC      net/ipv4/tcp_output.o
  CC      crypto/rng.o
  CC      fs/ext4/sysfs.o
  CC      drivers/acpi/acpica/exregion.o
  CC      drivers/char/tpm/tpm2-cmd.o
  CC      drivers/pci/iov.o
  CC      drivers/tty/serial/8250/8250_early.o
  CC      kernel/events/uprobes.o
  CC [M]  sound/hda/intel-dsp-config.o
  CC      drivers/char/tpm/tpmrm-dev.o
  CC      kernel/time/timekeeping_debug.o
  AR      kernel/cgroup/built-in.a
  CC      fs/ext4/xattr.o
  CC [M]  arch/x86/kvm/mmu/page_track.o
  CC      net/ethtool/stats.o
  CC [M]  net/netfilter/ipvs/ip_vs_rr.o
  LD [M]  drivers/video/fbdev/core/fb.o
  CC      fs/ntfs/mst.o
  CC [M]  arch/x86/kvm/mmu/spte.o
  CC      net/ethtool/phc_vclocks.o
  CC      kernel/trace/trace_printk.o
  CC      drivers/tty/serial/earlycon.o
  AR      drivers/video/fbdev/core/built-in.a
  CC      crypto/drbg.o
  AR      drivers/video/fbdev/built-in.a
  AR      drivers/video/built-in.a
  CC      arch/x86/kernel/jump_label.o
  CC      kernel/trace/pid_list.o
  CC      drivers/acpi/acpica/exresnte.o
  CC      net/ipv6/addrlabel.o
  CC      drivers/iommu/intel/trace.o
  CC      net/ethtool/mm.o
  CC      drivers/tty/serial/serial_mctrl_gpio.o
  CC [M]  arch/x86/kvm/mmu/tdp_iter.o
  CC      arch/x86/kernel/irq_work.o
  CC      net/ipv6/route.o
  CC      drivers/tty/serial/8250/8250_dw.o
  AR      net/xfrm/built-in.a
  CC [M]  sound/hda/intel-nhlt.o
  CC      net/core/sock_diag.o
  CC      kernel/time/namespace.o
  CC      fs/ext4/xattr_hurd.o
  CC      fs/lockd/xdr4.o
  CC      drivers/char/tpm/tpm2-space.o
  CC      fs/ext4/xattr_trusted.o
  CC      fs/ntfs/namei.o
  CC      drivers/acpi/acpica/exresolv.o
  CC      fs/pstore/inode.o
  CC      arch/x86/kernel/probe_roms.o
  CC      fs/efivarfs/inode.o
  CC      drivers/acpi/acpica/exresop.o
  CC      arch/x86/kernel/sys_ia32.o
  CC      fs/efivarfs/file.o
  CC      kernel/trace/trace_sched_switch.o
  CC      fs/pstore/platform.o
  CC      drivers/pci/pci-label.o
  CC      net/core/dev_ioctl.o
  CC      net/ipv4/tcp_timer.o
  LD [M]  net/netfilter/ipvs/ip_vs.o
  CC      net/ipv4/tcp_ipv4.o
  CC      drivers/acpi/acpica/exserial.o
  CC [M]  sound/hda/intel-sdw-acpi.o
  CC      fs/efivarfs/super.o
  CC [M]  net/netfilter/nf_conntrack_extend.o
  CC      drivers/tty/tty_ldisc.o
  CC      kernel/trace/trace_functions.o
  COPY    drivers/tty/vt/defkeymap.c
  CONMK   drivers/tty/vt/consolemap_deftbl.c
  CC      drivers/tty/vt/defkeymap.o
  CC      drivers/tty/serial/8250/8250_lpss.o
  AR      kernel/time/built-in.a
  CC      drivers/char/tpm/tpm-sysfs.o
  CC      kernel/exec_domain.o
  CC      kernel/panic.o
  CC      fs/nfs/export.o
  CC      drivers/acpi/acpica/exstore.o
  CC      arch/x86/kernel/signal_32.o
  CC      fs/ntfs/runlist.o
  AR      drivers/gpu/host1x/built-in.a
  CC      drivers/connector/cn_queue.o
  AR      drivers/gpu/drm/tests/built-in.a
  CC      drivers/tty/vt/consolemap_deftbl.o
  CC      lib/zstd/decompress/zstd_decompress.o
  CC [M]  drivers/gpu/drm/tests/drm_kunit_helpers.o
  CC      net/ethtool/module.o
  AR      drivers/iommu/arm/arm-smmu/built-in.a
  AR      drivers/iommu/arm/arm-smmu-v3/built-in.a
  CC      lib/zstd/decompress/zstd_decompress_block.o
  AR      drivers/iommu/arm/built-in.a
  AR      drivers/tty/vt/built-in.a
  AR      drivers/gpu/drm/arm/built-in.a
  CC      fs/lockd/svc4proc.o
  CC      fs/efivarfs/vars.o
  AR      drivers/gpu/vga/built-in.a
  CC      fs/pstore/pmsg.o
  CC      drivers/base/power/sysfs.o
  CC      crypto/jitterentropy.o
  CC      net/ethtool/pse-pd.o
  CC      drivers/block/loop.o
  CC      crypto/jitterentropy-kcapi.o
  CC      drivers/pci/pci-stub.o
  CC [M]  drivers/block/nbd.o
  AR      kernel/events/built-in.a
  CC [M]  fs/netfs/buffered_read.o
  LD [M]  sound/hda/snd-hda-core.o
  CC [M]  fs/fscache/cache.o
  LD [M]  sound/hda/snd-intel-dspcfg.o
  CC      drivers/base/firmware_loader/builtin/main.o
  LD [M]  sound/hda/snd-intel-sdw-acpi.o
  CC [M]  fs/netfs/io.o
  CC      drivers/acpi/acpica/exstoren.o
  AR      sound/xen/built-in.a
  AR      sound/virtio/built-in.a
  CC      sound/sound_core.o
  CC      drivers/iommu/intel/cap_audit.o
  CC      drivers/base/firmware_loader/main.o
  CC      mm/vmalloc.o
  AR      drivers/iommu/iommufd/built-in.a
  CC      fs/ntfs/super.o
  CC [M]  fs/smb/common/cifs_arc4.o
  CC      drivers/tty/serial/8250/8250_mid.o
  AR      fs/pstore/built-in.a
  CC [M]  fs/smb/common/cifs_md4.o
  AR      drivers/base/firmware_loader/builtin/built-in.a
  CC      drivers/tty/tty_buffer.o
  CC      sound/last.o
  CC      drivers/char/tpm/eventlog/common.o
  CC [M]  drivers/gpu/drm/tests/drm_buddy_test.o
  CC      arch/x86/kernel/sys_x86_64.o
  CC      fs/ntfs/sysctl.o
  CC      crypto/ghash-generic.o
  CC      kernel/trace/trace_preemptirq.o
  CC      drivers/acpi/acpica/exstorob.o
  CC      drivers/base/power/generic_ops.o
  CC [M]  drivers/gpu/drm/tests/drm_cmdline_parser_test.o
  CC [M]  net/netfilter/nf_conntrack_acct.o
  CC      drivers/pci/vgaarb.o
  CC      drivers/tty/serial/8250/8250_pericom.o
  CC      crypto/af_alg.o
  AR      fs/efivarfs/built-in.a
  CC      drivers/char/tpm/eventlog/tpm1.o
  CC      lib/zstd/zstd_common_module.o
  CC      kernel/trace/trace_nop.o
  CC      fs/ntfs/unistr.o
  CC      drivers/connector/connector.o
  CC [M]  drivers/gpu/drm/tests/drm_connector_test.o
  CC      kernel/cpu.o
  CC      drivers/char/tpm/eventlog/tpm2.o
  AR      sound/built-in.a
  CC [M]  arch/x86/kvm/mmu/tdp_mmu.o
  CC [M]  fs/smb/client/trace.o
  CC      net/ethtool/plca.o
  CC      fs/lockd/procfs.o
  CC      drivers/acpi/acpica/exsystem.o
  CC [M]  fs/smb/client/cifsfs.o
  CC      lib/zstd/common/debug.o
  CC      net/core/tso.o
  CC      drivers/base/power/common.o
  CC [M]  fs/fscache/cookie.o
  CC      lib/zstd/common/entropy_common.o
  CC      net/ipv4/tcp_minisocks.o
  CC      fs/nfs/sysfs.o
  CC      net/ipv6/ip6_fib.o
  CC      mm/page_alloc.o
  CC      drivers/tty/tty_port.o
  CC      arch/x86/kernel/espfix_64.o
  CC      drivers/iommu/intel/irq_remapping.o
  CC [M]  fs/fscache/io.o
  CC      net/core/sock_reuseport.o
  AR      drivers/tty/serial/8250/built-in.a
  AR      drivers/base/firmware_loader/built-in.a
  AR      drivers/tty/serial/built-in.a
  CC [M]  fs/netfs/iterator.o
  CC [M]  arch/x86/kvm/smm.o
  CC [M]  arch/x86/kvm/vmx/vmx.o
  CC      drivers/base/power/qos.o
  CC      drivers/iommu/intel/perfmon.o
  CC      kernel/trace/trace_functions_graph.o
  CC      drivers/acpi/acpica/extrace.o
  CC      net/core/fib_notifier.o
  CC      drivers/char/tpm/tpm_ppi.o
  CC      crypto/algif_hash.o
  CC [M]  net/netfilter/nf_conntrack_seqadj.o
  CC      drivers/base/power/runtime.o
  AR      fs/lockd/built-in.a
  CC      fs/ext4/xattr_user.o
  CC      fs/ntfs/upcase.o
  CC      fs/btrfs/ctree.o
  CC      drivers/connector/cn_proc.o
  CC [M]  fs/netfs/main.o
  AR      drivers/pci/built-in.a
  CC      net/ipv4/tcp_cong.o
  CC      net/ipv6/ipv6_sockglue.o
  CC      drivers/acpi/acpica/exutils.o
  CC      fs/nfs/fs_context.o
  AR      net/ethtool/built-in.a
  CC [M]  net/netfilter/nf_conntrack_proto_icmpv6.o
  CC      arch/x86/kernel/ksysfs.o
  CC      net/core/xdp.o
  CC      drivers/base/power/wakeirq.o
  CC      drivers/tty/tty_mutex.o
  CC      fs/btrfs/extent-tree.o
  CC      drivers/base/regmap/regmap.o
  CC      drivers/char/tpm/eventlog/acpi.o
  AR      fs/ntfs/built-in.a
  CC      drivers/base/regmap/regcache.o
  CC [M]  drivers/gpu/drm/tests/drm_damage_helper_test.o
  AR      drivers/block/built-in.a
  CC      fs/ext4/fast_commit.o
  CC      drivers/acpi/acpica/hwacpi.o
  CC      drivers/base/power/main.o
  CC      fs/nfs/sysctl.o
  CC      drivers/char/tpm/eventlog/efi.o
  CC [M]  fs/fscache/main.o
  CC      drivers/tty/tty_ldsem.o
  CC      kernel/trace/fgraph.o
  CC [M]  arch/x86/kvm/kvm-asm-offsets.s
  CC      crypto/algif_skcipher.o
  AR      drivers/misc/eeprom/built-in.a
  AR      drivers/misc/cb710/built-in.a
  CC      drivers/mfd/mfd-core.o
  AR      drivers/misc/ti-st/built-in.a
  AR      drivers/misc/lis3lv02d/built-in.a
  CC      crypto/xor.o
  AR      drivers/misc/cardreader/built-in.a
  AR      drivers/iommu/intel/built-in.a
  CC      drivers/iommu/iommu.o
  CC [M]  drivers/misc/mei/hdcp/mei_hdcp.o
  CC      arch/x86/kernel/bootflag.o
  CC      fs/ext4/orphan.o
  CC [M]  fs/fscache/volume.o
  CC      drivers/mfd/intel-lpss.o
  CC [M]  fs/netfs/objects.o
  AR      drivers/misc/built-in.a
  CC      drivers/acpi/acpica/hwesleep.o
  CC      drivers/base/power/wakeup.o
  CC      drivers/iommu/iommu-traces.o
  AR      drivers/connector/built-in.a
  CC      net/packet/af_packet.o
  AR      drivers/nfc/built-in.a
  CC      lib/decompress_bunzip2.o
  CC      net/packet/diag.o
  CC      drivers/iommu/iommu-sysfs.o
  CC      drivers/acpi/acpica/hwgpe.o
  CC [M]  arch/x86/kvm/vmx/pmu_intel.o
  CC      drivers/char/tpm/tpm_crb.o
  CC      fs/nfs/nfs2super.o
  CC      crypto/hash_info.o
  CC [M]  net/netfilter/nf_conntrack_proto_dccp.o
  CC      lib/decompress_inflate.o
  CC      crypto/simd.o
  CC      drivers/tty/tty_baudrate.o
  CC      kernel/exit.o
  CC      net/ipv4/tcp_metrics.o
  CC      arch/x86/kernel/e820.o
  CC      fs/nfs/proc.o
  CC      drivers/acpi/acpica/hwregs.o
  CC      lib/decompress_unlz4.o
  CC      drivers/iommu/dma-iommu.o
  CC [M]  drivers/gpu/drm/tests/drm_dp_mst_helper_test.o
  CC      drivers/mfd/intel-lpss-pci.o
  CC      fs/nfs/nfs2xdr.o
  LD [M]  fs/netfs/netfs.o
  CC      drivers/acpi/acpica/hwsleep.o
  CC [M]  fs/fuse/dev.o
  CC      kernel/softirq.o
  CC [M]  drivers/gpu/drm/tests/drm_format_helper_test.o
  CC [M]  drivers/misc/mei/pxp/mei_pxp.o
  CC      kernel/trace/blktrace.o
  CC      mm/init-mm.o
  CC      kernel/resource.o
  CC      drivers/acpi/acpica/hwvalid.o
  CC      lib/decompress_unlzma.o
  CC [M]  fs/fscache/proc.o
  CC      fs/nfs/nfs3super.o
  CC      drivers/mfd/intel-lpss-acpi.o
  CC [M]  fs/fuse/dir.o
  CC      drivers/char/hpet.o
  CC      drivers/acpi/acpica/hwxface.o
  CC [M]  fs/smb/client/cifs_debug.o
  CC      drivers/tty/tty_jobctrl.o
  CC [M]  crypto/md4.o
  CC      net/core/flow_offload.o
  CC      net/key/af_key.o
  CC      net/core/gro.o
  AR      drivers/char/tpm/built-in.a
  CC      drivers/char/nvram.o
  CC      drivers/acpi/acpica/hwxfsleep.o
  CC [M]  fs/fuse/file.o
  CC      fs/btrfs/print-tree.o
  CC      fs/nfs/nfs3client.o
  CC      net/core/netdev-genl.o
  CC      mm/memblock.o
  CC [M]  crypto/ccm.o
  CC [M]  fs/smb/client/connect.o
  CC      drivers/mfd/intel_soc_pmic_crc.o
  CC [M]  drivers/misc/mei/init.o
  CC      net/ipv6/ndisc.o
  CC      drivers/base/power/wakeup_stats.o
  CC [M]  net/netfilter/nf_conntrack_proto_sctp.o
  LD [M]  fs/fscache/fscache.o
  CC      drivers/iommu/iova.o
  CC [M]  crypto/arc4.o
  CC      drivers/acpi/acpica/hwpci.o
  CC      mm/memory_hotplug.o
  CC      kernel/trace/trace_events.o
  CC      arch/x86/kernel/pci-dma.o
  CC [M]  net/netfilter/nf_conntrack_netlink.o
  CC [M]  drivers/gpu/drm/tests/drm_format_test.o
  CC [M]  drivers/gpu/drm/tests/drm_framebuffer_test.o
  CC      net/ipv6/udp.o
  CC      lib/zstd/common/error_private.o
  CC      drivers/tty/n_null.o
  CC      mm/madvise.o
  CC      kernel/trace/trace_export.o
  CC      lib/zstd/common/fse_decompress.o
  CC      drivers/base/power/domain.o
  AR      drivers/char/built-in.a
  CC      drivers/iommu/irq_remapping.o
  AR      drivers/dax/hmem/built-in.a
  CC      drivers/dax/super.o
  CC      drivers/dax/bus.o
  CC      drivers/dma-buf/dma-buf.o
  CC      drivers/acpi/acpica/nsaccess.o
  CC      net/ipv6/udplite.o
  CC      drivers/dma-buf/dma-fence.o
  CC [M]  drivers/misc/mei/hbm.o
  CC      net/ipv4/tcp_fastopen.o
  CC      fs/nfs/nfs3proc.o
  CC [M]  drivers/mfd/lpc_sch.o
  CC      drivers/base/regmap/regcache-rbtree.o
  CC      kernel/sysctl.o
  CC      drivers/acpi/acpica/nsalloc.o
  CC [M]  crypto/ecc.o
  CC      arch/x86/kernel/quirks.o
  CC      mm/page_io.o
  CC [M]  crypto/essiv.o
  CC      kernel/capability.o
  CC      net/ipv4/tcp_rate.o
  CC      fs/btrfs/root-tree.o
  CC      drivers/tty/pty.o
  CC [M]  drivers/mfd/lpc_ich.o
  CC      arch/x86/kernel/topology.o
  CC      drivers/dma-buf/dma-fence-array.o
  AR      drivers/gpu/drm/display/built-in.a
  CC [M]  drivers/gpu/drm/display/drm_display_helper_mod.o
  CC      drivers/dma-buf/dma-fence-chain.o
  CC [M]  drivers/gpu/drm/display/drm_dp_dual_mode_helper.o
  CC [M]  drivers/gpu/drm/tests/drm_managed_test.o
  CC [M]  fs/overlayfs/super.o
  AR      drivers/iommu/built-in.a
  CC      fs/open.o
  CC      lib/zstd/common/zstd_common.o
  CC      drivers/acpi/acpica/nsarguments.o
  CC      mm/swap_state.o
  CC      drivers/base/regmap/regcache-flat.o
  CC [M]  drivers/gpu/drm/tests/drm_mm_test.o
  CC [M]  crypto/ecdh.o
  AR      lib/zstd/built-in.a
  CC      lib/decompress_unlzo.o
  CC [M]  arch/x86/kvm/vmx/vmcs12.o
  CC      net/core/netdev-genl-gen.o
  CC      drivers/base/regmap/regcache-maple.o
  AR      drivers/gpu/drm/renesas/rcar-du/built-in.a
  AR      drivers/gpu/drm/renesas/built-in.a
  AR      drivers/gpu/drm/omapdrm/built-in.a
  AR      drivers/gpu/drm/tilcdc/built-in.a
  AR      drivers/gpu/drm/imx/built-in.a
  AR      drivers/gpu/drm/i2c/built-in.a
  AR      drivers/gpu/drm/panel/built-in.a
  CC      arch/x86/kernel/kdebugfs.o
  AR      drivers/gpu/drm/bridge/analogix/built-in.a
  AR      drivers/gpu/drm/bridge/cadence/built-in.a
  AR      drivers/gpu/drm/bridge/imx/built-in.a
  CC [M]  fs/overlayfs/namei.o
  AR      drivers/gpu/drm/bridge/synopsys/built-in.a
  CC [M]  fs/overlayfs/util.o
  AR      drivers/gpu/drm/bridge/built-in.a
  CC [M]  crypto/ecdh_helper.o
  AR      drivers/gpu/drm/hisilicon/built-in.a
  CC [M]  drivers/gpu/drm/tests/drm_modes_test.o
  CC      drivers/dma-buf/dma-fence-unwrap.o
  CC      arch/x86/kernel/alternative.o
  CC      drivers/acpi/acpica/nsconvert.o
  CC [M]  fs/smb/client/dir.o
  AR      drivers/dax/built-in.a
  CC [M]  drivers/misc/mei/interrupt.o
  CC [M]  net/netfilter/nf_nat_core.o
  CC      drivers/dma-buf/dma-resv.o
  CC      net/ipv6/raw.o
  CC [M]  drivers/gpu/drm/tests/drm_plane_helper_test.o
  AR      drivers/cxl/core/built-in.a
  CC      kernel/ptrace.o
  AR      drivers/cxl/built-in.a
  CC      fs/btrfs/dir-item.o
  CC      mm/swapfile.o
  CC [M]  fs/overlayfs/inode.o
  CC      drivers/tty/sysrq.o
  CC      lib/decompress_unxz.o
  AR      drivers/mfd/built-in.a
  CC      net/ipv6/icmp.o
  CC      drivers/acpi/acpica/nsdump.o
  CC      arch/x86/kernel/i8253.o
  CC [M]  fs/fuse/inode.o
  CC [M]  drivers/gpu/drm/display/drm_dp_helper.o
  CC      drivers/base/power/domain_governor.o
  CC [M]  fs/fuse/control.o
  AR      fs/ext4/built-in.a
  CC      fs/nfs/nfs3xdr.o
  CC      net/core/gso.o
  CC [M]  drivers/misc/mei/client.o
  AR      drivers/macintosh/built-in.a
  AR      net/packet/built-in.a
  CC      net/ipv4/tcp_recovery.o
  CC      arch/x86/kernel/hw_breakpoint.o
  CC      net/ipv4/tcp_ulp.o
  CC      arch/x86/kernel/tsc.o
  CC [M]  fs/fuse/xattr.o
  CC      drivers/acpi/acpica/nseval.o
  CC [M]  fs/overlayfs/file.o
  CC      drivers/base/regmap/regmap-debugfs.o
  AR      net/key/built-in.a
  CC [M]  arch/x86/kvm/vmx/hyperv.o
  CC      fs/btrfs/file-item.o
  CC      arch/x86/kernel/tsc_msr.o
  CC [M]  fs/smb/client/file.o
  CC [M]  drivers/gpu/drm/tests/drm_probe_helper_test.o
  CC      fs/read_write.o
  CC      net/core/net-sysfs.o
  CC      lib/decompress_unzstd.o
  CC      drivers/dma-buf/sync_file.o
  CC      kernel/trace/trace_event_perf.o
  CC      mm/swap_slots.o
  CC [M]  drivers/gpu/drm/tests/drm_rect_test.o
  CC      drivers/base/power/clock_ops.o
  CC      kernel/user.o
  LD [M]  crypto/ecdh_generic.o
  AR      crypto/built-in.a
  CC      fs/btrfs/inode-item.o
  CC      drivers/acpi/acpica/nsinit.o
  CC      drivers/scsi/scsi.o
  CC      fs/btrfs/disk-io.o
  AR      net/bridge/netfilter/built-in.a
  CC      net/bridge/br.o
  CC      drivers/acpi/acpica/nsload.o
  CC      drivers/nvme/host/core.o
  CC      drivers/ata/libata-core.o
  CC      drivers/spi/spi.o
  CC      drivers/ata/libata-scsi.o
  CC      fs/file_table.o
  CC      drivers/ata/libata-eh.o
  AR      drivers/tty/built-in.a
  CC      lib/dump_stack.o
  CC [M]  arch/x86/kvm/vmx/nested.o
  AR      drivers/nvme/target/built-in.a
  AR      drivers/base/test/built-in.a
  CC      drivers/base/component.o
  CC      drivers/base/regmap/regmap-i2c.o
  CC      mm/dmapool.o
  CC      net/bridge/br_device.o
  CC [M]  drivers/gpu/drm/tests/drm_exec_test.o
  CC      arch/x86/kernel/io_delay.o
  CC      drivers/dma-buf/sw_sync.o
  CC [M]  fs/overlayfs/dir.o
  CC      drivers/base/core.o
  AR      drivers/gpu/drm/mxsfb/built-in.a
  CC      drivers/base/bus.o
  CC      arch/x86/kernel/rtc.o
  CC      fs/super.o
  CC      net/ipv6/mcast.o
  CC      drivers/acpi/acpica/nsnames.o
  CC [M]  arch/x86/kvm/vmx/posted_intr.o
  AR      drivers/base/power/built-in.a
  CC      net/bridge/br_fdb.o
  AR      drivers/gpu/drm/tiny/built-in.a
  CC      fs/char_dev.o
  AR      drivers/gpu/drm/xlnx/built-in.a
  CC      net/ipv6/reassembly.o
  CC      drivers/acpi/acpica/nsobject.o
  CC      net/ipv4/tcp_offload.o
  CC      drivers/acpi/acpica/nsparse.o
  CC      kernel/trace/trace_events_filter.o
  CC [M]  net/netfilter/nf_nat_proto.o
  CC      arch/x86/kernel/resource.o
  CC [M]  fs/fuse/acl.o
  CC      kernel/signal.o
  CC      lib/earlycpio.o
  CC      lib/extable.o
  AS      arch/x86/kernel/irqflags.o
  CC      arch/x86/kernel/static_call.o
  AR      drivers/gpu/drm/gud/built-in.a
  CC      lib/flex_proportions.o
  LD [M]  arch/x86/kvm/kvm.o
  CC [M]  fs/fuse/readdir.o
  CC      arch/x86/kernel/process.o
  CC      drivers/acpi/acpica/nspredef.o
  CC      net/bridge/br_forward.o
  CC      lib/idr.o
  UPD     arch/x86/kvm/kvm-asm-offsets.h
  CC      lib/irq_regs.o
  AS [M]  arch/x86/kvm/vmx/vmenter.o
  CC      drivers/base/regmap/regmap-irq.o
  CC      drivers/base/dd.o
  CC      net/ipv6/tcp_ipv6.o
  CC      lib/is_single_threaded.o
  CC      net/ipv6/ping.o
  CC [M]  drivers/gpu/drm/display/drm_dp_mst_topology.o
  CC [M]  drivers/misc/mei/main.o
  CC      drivers/acpi/wakeup.o
  CC      kernel/trace/trace_events_trigger.o
  CC      mm/hugetlb.o
  CC      drivers/scsi/hosts.o
  CC      drivers/dma-buf/sync_debug.o
  AR      drivers/gpu/drm/solomon/built-in.a
  AR      fs/nfs/built-in.a
  CC [M]  drivers/dma-buf/selftest.o
  CC      fs/stat.o
  CC      fs/btrfs/transaction.o
  CC      drivers/acpi/sleep.o
  CC      mm/hugetlb_vmemmap.o
  CC      net/ipv6/exthdrs.o
  CC [M]  drivers/gpu/drm/ttm/ttm_tt.o
  CC      net/core/page_pool.o
  CC      kernel/trace/trace_eprobe.o
  CC      fs/exec.o
  CC      drivers/acpi/acpica/nsprepkg.o
  CC [M]  fs/overlayfs/readdir.o
  CC      fs/btrfs/inode.o
  CC      net/bridge/br_if.o
  CC      drivers/base/syscore.o
  CC      lib/klist.o
  CC [M]  drivers/misc/mei/dma-ring.o
  CC      drivers/acpi/device_sysfs.o
  CC      kernel/trace/trace_kprobe.o
  CC      drivers/acpi/acpica/nsrepair.o
  CC [M]  drivers/dma-buf/st-dma-fence.o
  CC [M]  fs/fuse/ioctl.o
  CC      net/ipv4/tcp_plb.o
  CC      drivers/acpi/acpica/nsrepair2.o
  CC [M]  drivers/gpu/drm/scheduler/sched_main.o
  CC      net/ipv6/datagram.o
  CC [M]  drivers/gpu/drm/scheduler/sched_fence.o
  CC      drivers/scsi/scsi_ioctl.o
  CC      lib/kobject.o
  CC [M]  net/netfilter/nf_nat_helper.o
  AR      drivers/base/regmap/built-in.a
  CC      drivers/base/driver.o
  CC      mm/mempolicy.o
  CC      net/ipv4/datagram.o
  CC [M]  drivers/gpu/drm/ttm/ttm_bo.o
  CC [M]  drivers/misc/mei/bus.o
  CC      net/bridge/br_input.o
  CC      net/bridge/br_ioctl.o
  CC [M]  drivers/gpu/drm/scheduler/sched_entity.o
  CC      arch/x86/kernel/ptrace.o
  CC      drivers/acpi/device_pm.o
  CC      lib/kobject_uevent.o
  CC      fs/pipe.o
  CC      kernel/trace/error_report-traces.o
  CC      drivers/acpi/acpica/nssearch.o
  CC      drivers/base/class.o
  CC [M]  drivers/dma-buf/st-dma-fence-chain.o
  CC [M]  drivers/gpu/drm/ttm/ttm_bo_util.o
  CC [M]  fs/overlayfs/copy_up.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.o
  CC      net/core/net-procfs.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_device.o
  LD [M]  fs/fuse/fuse.o
  CC      fs/namei.o
  CC      kernel/trace/power-traces.o
  CC      lib/logic_pio.o
  CC [M]  drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.o
  CC      drivers/acpi/acpica/nsutils.o
  AR      drivers/spi/built-in.a
  CC      drivers/net/phy/mdio-boardinfo.o
  CC      kernel/sys.o
  CC      drivers/net/phy/mdio_devres.o
  CC      drivers/acpi/acpica/nswalk.o
  CC      drivers/scsi/scsicam.o
  CC      drivers/net/phy/phy.o
  CC      drivers/nvme/host/ioctl.o
  CC      drivers/nvme/host/sysfs.o
  CC      lib/maple_tree.o
  CC      drivers/base/platform.o
  CC [M]  net/netfilter/nf_nat_redirect.o
  LD [M]  drivers/gpu/drm/amd/amdxcp/amdxcp.o
  CC [M]  drivers/misc/mei/bus-fixup.o
  CC      net/ipv4/raw.o
  CC      lib/memcat_p.o
  LD [M]  drivers/gpu/drm/scheduler/gpu-sched.o
  CC      drivers/scsi/scsi_error.o
  CC      kernel/trace/rpm-traces.o
  CC      arch/x86/kernel/tls.o
  CC [M]  drivers/gpu/drm/ttm/ttm_bo_vm.o
  CC [M]  drivers/gpu/drm/i915/i915_driver.o
  CC      net/ipv6/ip6_flowlabel.o
  CC      drivers/acpi/acpica/nsxfeval.o
  CC      kernel/trace/trace_dynevent.o
  CC [M]  drivers/misc/mei/debugfs.o
  CC      net/ipv4/udp.o
  AR      drivers/net/pse-pd/built-in.a
  CC      lib/nmi_backtrace.o
  CC      drivers/acpi/proc.o
  CC [M]  drivers/dma-buf/st-dma-fence-unwrap.o
  CC [M]  drivers/gpu/drm/xe/tests/xe_bo_test.o
  CC      net/core/netpoll.o
  CC [M]  drivers/gpu/drm/xe/tests/xe_dma_buf_test.o
  CC      lib/plist.o
  CC      net/bridge/br_stp.o
  CC [M]  fs/overlayfs/export.o
  CC [M]  drivers/dma-buf/st-dma-resv.o
  CC      lib/radix-tree.o
  CC      drivers/scsi/scsi_lib.o
  CC      net/ipv6/inet6_connection_sock.o
  CC      lib/ratelimit.o
  CC      drivers/scsi/scsi_lib_dma.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.o
  CC      net/core/fib_rules.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_kms.o
  CC [M]  drivers/misc/mei/mei-trace.o
  CC [M]  drivers/gpu/drm/xe/tests/xe_migrate_test.o
  CC      drivers/acpi/acpica/nsxfname.o
  CC      lib/rbtree.o
  CC [M]  fs/smb/client/inode.o
  CC [M]  drivers/gpu/drm/i915/i915_drm_client.o
  CC [M]  fs/overlayfs/params.o
  CC      fs/btrfs/file.o
  CC      drivers/base/cpu.o
  CC      drivers/acpi/bus.o
  CC [M]  drivers/gpu/drm/ttm/ttm_module.o
  AR      drivers/dma-buf/built-in.a
  LD [M]  drivers/dma-buf/dmabuf_selftests.o
  CC      arch/x86/kernel/step.o
  CC      kernel/umh.o
  CC [M]  drivers/gpu/drm/display/drm_dsc_helper.o
  AR      drivers/firewire/built-in.a
  CC      net/ipv4/udplite.o
  CC      net/ipv4/udp_offload.o
  CC      kernel/trace/trace_probe.o
  CC      kernel/workqueue.o
  CC      drivers/nvme/host/pr.o
  CC      net/ipv6/udp_offload.o
  CC [M]  drivers/gpu/drm/xe/tests/xe_pci_test.o
  CC      fs/btrfs/defrag.o
  CC      arch/x86/kernel/i8237.o
  CC      fs/fcntl.o
  CC [M]  net/netfilter/nf_nat_masquerade.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.o
  CC      lib/seq_buf.o
  CC      drivers/net/phy/phy-c45.o
  CC      drivers/acpi/acpica/nsxfobj.o
  CC      drivers/ata/libata-transport.o
  CC [M]  drivers/gpu/drm/ttm/ttm_execbuf_util.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/atombios_crtc.o
  CC [M]  drivers/misc/mei/pci-me.o
  CC      arch/x86/kernel/stacktrace.o
  CC      drivers/base/firmware.o
  CC      drivers/nvme/host/trace.o
  CC      arch/x86/kernel/reboot.o
  CC      drivers/net/phy/phy-core.o
  CC      fs/ioctl.o
  CC      drivers/acpi/acpica/psargs.o
  CC      kernel/trace/trace_uprobe.o
  LD [M]  fs/overlayfs/overlay.o
  CC      net/bridge/br_stp_bpdu.o
  CC [M]  drivers/gpu/drm/xe/tests/xe_rtp_test.o
  CC      lib/siphash.o
  CC      drivers/net/phy/phy_device.o
  CC      net/ipv6/seg6.o
  CC      drivers/nvme/host/fault_inject.o
  CC [M]  drivers/gpu/drm/display/drm_hdcp_helper.o
  CC      drivers/base/init.o
  CC [M]  drivers/gpu/drm/i915/i915_config.o
  CC      drivers/net/mdio/acpi_mdio.o
  CC [M]  drivers/gpu/drm/xe/tests/xe_wa_test.o
  CC      drivers/net/mdio/fwnode_mdio.o
  CC      net/ipv6/fib6_notifier.o
  CC      net/bridge/br_stp_if.o
  CC      drivers/acpi/glue.o
  CC [M]  fs/smb/client/link.o
  CC [M]  drivers/gpu/drm/ttm/ttm_range_manager.o
  LD [M]  arch/x86/kvm/kvm-intel.o
  CC      net/ipv6/rpl.o
  CC [M]  drivers/misc/mei/hw-me.o
  CC      lib/string.o
  CC      drivers/ata/libata-trace.o
  CC      net/core/net-traces.o
  CC [M]  drivers/gpu/drm/i915/i915_getparam.o
  AR      net/dsa/built-in.a
  CC      drivers/acpi/acpica/psloop.o
  CC      kernel/trace/rethook.o
  CC [M]  net/sunrpc/auth_gss/auth_gss.o
  CC [M]  drivers/misc/mei/gsc-me.o
  CC      drivers/scsi/scsi_scan.o
  CC      lib/timerqueue.o
  CC      drivers/nvme/host/pci.o
  CC [M]  drivers/gpu/drm/xe/xe_bb.o
  CC      net/8021q/vlan_core.o
  CC [M]  net/netfilter/x_tables.o
  CC      drivers/base/map.o
  CC      drivers/base/devres.o
  CC [M]  drivers/gpu/drm/display/drm_hdmi_helper.o
  CC [M]  drivers/gpu/drm/vgem/vgem_drv.o
  CC      lib/vsprintf.o
  CC [M]  drivers/gpu/drm/display/drm_scdc_helper.o
  CC      arch/x86/kernel/msr.o
  CC      mm/sparse.o
  CC [M]  drivers/gpu/drm/vgem/vgem_fence.o
  CC [M]  drivers/gpu/drm/xe/xe_bo.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.o
  CC      net/dcb/dcbnl.o
  CC      net/l3mdev/l3mdev.o
  CC      lib/win_minmax.o
  AR      drivers/net/mdio/built-in.a
  CC      drivers/acpi/acpica/psobject.o
  CC [M]  drivers/gpu/drm/ttm/ttm_resource.o
  CC      net/dcb/dcbevent.o
  CC [M]  drivers/gpu/drm/nouveau/nvif/object.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/atom.o
  CC      drivers/acpi/acpica/psopcode.o
  CC      net/ipv6/ioam6.o
  CC [M]  drivers/gpu/drm/nouveau/nvif/client.o
  CC      mm/sparse-vmemmap.o
  CC      lib/xarray.o
  CC      drivers/acpi/scan.o
  LD [M]  drivers/misc/mei/mei.o
  AR      drivers/net/pcs/built-in.a
  AR      drivers/net/ethernet/adi/built-in.a
  AR      drivers/net/ethernet/alacritech/built-in.a
  LD [M]  drivers/misc/mei/mei-gsc.o
  AR      drivers/net/ethernet/amazon/built-in.a
  CC      drivers/base/attribute_container.o
  AR      drivers/net/ethernet/aquantia/built-in.a
  CC      mm/mmu_notifier.o
  AR      drivers/net/ethernet/asix/built-in.a
  AR      drivers/net/ethernet/cadence/built-in.a
  CC      drivers/ata/libata-sata.o
  AR      drivers/net/ethernet/broadcom/built-in.a
  CC [M]  drivers/net/ethernet/broadcom/b44.o
  CC      mm/ksm.o
  CC      drivers/base/transport_class.o
  CC      net/ipv4/arp.o
  CC [M]  drivers/gpu/drm/i915/i915_ioctl.o
  CC [M]  net/8021q/vlan.o
  CC      arch/x86/kernel/cpuid.o
  CC      net/bridge/br_stp_timer.o
  CC      fs/btrfs/extent_map.o
  CC [M]  drivers/net/ethernet/broadcom/bnx2.o
  LD [M]  drivers/gpu/drm/vgem/vgem.o
  CC      drivers/acpi/acpica/psopinfo.o
  CC      net/sunrpc/clnt.o
  CC [M]  drivers/gpu/drm/display/drm_dp_aux_dev.o
  CC      drivers/base/topology.o
  CC      drivers/base/container.o
  CC [M]  drivers/gpu/drm/i915/i915_irq.o
  GEN     drivers/scsi/scsi_devinfo_tbl.c
  CC      drivers/scsi/scsi_devinfo.o
  CC      fs/btrfs/sysfs.o
  CC      mm/slub.o
  AR      kernel/trace/built-in.a
  CC      kernel/pid.o
  AR      net/l3mdev/built-in.a
  CC [M]  drivers/gpu/drm/i915/i915_mitigations.o
  CC      net/handshake/genl.o
  CC [M]  drivers/gpu/drm/i915/i915_module.o
  CC      fs/readdir.o
  CC      drivers/net/phy/linkmode.o
  CC      mm/migrate.o
  CC      fs/select.o
  CC [M]  drivers/gpu/drm/ttm/ttm_pool.o
  CC      drivers/acpi/acpica/psparse.o
  CC [M]  drivers/gpu/drm/nouveau/nvif/conn.o
  CC [M]  drivers/gpu/drm/ast/ast_drv.o
  CC      arch/x86/kernel/early-quirks.o
  CC [M]  fs/smb/client/misc.o
  LD [M]  drivers/misc/mei/mei-me.o
  CC [M]  drivers/gpu/drm/ast/ast_i2c.o
  CC [M]  drivers/gpu/drm/xe/xe_bo_evict.o
  CC      mm/memory-tiers.o
  CC      drivers/base/property.o
  CC [M]  drivers/gpu/drm/i915/i915_params.o
  CC      drivers/acpi/acpica/psscope.o
  LD [M]  drivers/gpu/drm/display/drm_display_helper.o
  CC      drivers/ata/libata-sff.o
  CC      net/handshake/netlink.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_fence.o
  CC      drivers/scsi/scsi_sysctl.o
  CC      net/handshake/request.o
  CC      drivers/net/phy/mdio_bus.o
  CC [M]  net/8021q/vlan_dev.o
  CC [M]  net/netfilter/xt_tcpudp.o
  CC      drivers/acpi/acpica/pstree.o
  CC      net/bridge/br_netlink.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.o
  CC [M]  drivers/gpu/drm/nouveau/nvif/device.o
  CC [M]  drivers/gpu/drm/nouveau/nvif/disp.o
  CC      drivers/acpi/resource.o
  CC      kernel/task_work.o
  CC [M]  net/sunrpc/auth_gss/gss_generic_token.o
  AR      net/dcb/built-in.a
  CC [M]  net/8021q/vlan_netlink.o
  CC [M]  net/netfilter/xt_mark.o
  CC      net/ipv6/sysctl_net_ipv6.o
  CC [M]  drivers/gpu/drm/i915/i915_pci.o
  CC      arch/x86/kernel/smp.o
  CC [M]  drivers/gpu/drm/ttm/ttm_device.o
  CC      drivers/acpi/acpi_processor.o
  CC [M]  drivers/gpu/drm/ast/ast_main.o
  CC      drivers/net/phy/mdio_device.o
  CC [M]  net/netfilter/xt_nat.o
  CC      net/handshake/tlshd.o
  AR      drivers/nvme/host/built-in.a
  AR      drivers/nvme/built-in.a
  CC      drivers/scsi/scsi_debugfs.o
  CC [M]  fs/smb/client/netmisc.o
  CC      drivers/acpi/acpica/psutils.o
  CC      kernel/extable.o
  CC [M]  drivers/gpu/drm/nouveau/nvif/driver.o
  CC      net/ipv4/icmp.o
  CC      lib/lockref.o
  CC [M]  net/sunrpc/auth_gss/gss_mech_switch.o
  CC [M]  net/8021q/vlanproc.o
  CC      lib/bcd.o
  CC [M]  fs/smb/client/smbencrypt.o
  AR      drivers/cdrom/built-in.a
  CC [M]  drivers/gpu/drm/i915/i915_scatterlist.o
  CC [M]  drivers/gpu/drm/xe/xe_debugfs.o
  AR      drivers/auxdisplay/built-in.a
  CC [M]  drivers/gpu/drm/i915/i915_suspend.o
  CC      lib/sort.o
  CC      drivers/base/cacheinfo.o
  CC [M]  fs/smb/client/transport.o
  CC [M]  drivers/gpu/drm/nouveau/nvif/event.o
  CC      drivers/acpi/acpica/pswalk.o
  AR      drivers/net/usb/built-in.a
  CC [M]  drivers/net/usb/pegasus.o
  CC      lib/parser.o
  CC [M]  drivers/net/ipvlan/ipvlan_core.o
  CC      lib/debug_locks.o
  CC [M]  drivers/gpu/drm/ttm/ttm_sys_manager.o
  CC      lib/random32.o
  CC      drivers/acpi/processor_core.o
  CC [M]  net/sunrpc/auth_gss/svcauth_gss.o
  CC      drivers/scsi/scsi_trace.o
  CC      net/handshake/trace.o
  CC      fs/btrfs/accessors.o
  CC      fs/btrfs/xattr.o
  CC [M]  drivers/gpu/drm/i915/i915_switcheroo.o
  CC      net/ipv6/xfrm6_policy.o
  CC [M]  drivers/net/vxlan/vxlan_core.o
  CC [M]  drivers/gpu/drm/ast/ast_mm.o
  CC [M]  drivers/net/vxlan/vxlan_multicast.o
  CC      drivers/net/phy/swphy.o
  CC      arch/x86/kernel/smpboot.o
  CC [M]  drivers/gpu/drm/ast/ast_mode.o
  CC [M]  fs/smb/client/cached_dir.o
  CC      drivers/acpi/processor_pdc.o
  CC      drivers/acpi/acpica/psxface.o
  CC      drivers/acpi/acpica/rsaddr.o
  CC [M]  drivers/gpu/drm/ast/ast_post.o
  CC      drivers/net/loopback.o
  CC [M]  fs/smb/client/cifs_unicode.o
  CC [M]  net/netfilter/xt_REDIRECT.o
  CC      lib/bust_spinlocks.o
  CC [M]  drivers/gpu/drm/i915/i915_sysfs.o
  CC      kernel/params.o
  CC      drivers/net/phy/fixed_phy.o
  CC [M]  drivers/gpu/drm/ttm/ttm_agp_backend.o
  AR      net/8021q/built-in.a
  LD [M]  net/8021q/8021q.o
  CC [M]  net/bluetooth/af_bluetooth.o
  CC      drivers/base/swnode.o
  CC [M]  net/bluetooth/hci_core.o
  CC [M]  drivers/gpu/drm/nouveau/nvif/fifo.o
  CC [M]  drivers/gpu/drm/xe/xe_devcoredump.o
  CC [M]  drivers/gpu/drm/i915/i915_utils.o
  CC      mm/migrate_device.o
  CC      drivers/acpi/ec.o
  CC      drivers/acpi/acpica/rscalc.o
  CC      drivers/scsi/scsi_logging.o
  CC [M]  net/sunrpc/auth_gss/gss_rpc_upcall.o
  CC [M]  net/netfilter/xt_MASQUERADE.o
  CC      drivers/acpi/dock.o
  CC [M]  drivers/net/phy/phylink.o
  CC      mm/huge_memory.o
  CC      drivers/scsi/scsi_pm.o
  CC [M]  net/bluetooth/hci_conn.o
  CC      lib/kasprintf.o
  CC      net/bridge/br_netlink_tunnel.o
  CC      drivers/ata/libata-pmp.o
  CC      net/sunrpc/xprt.o
  CC      net/core/selftests.o
  LD [M]  drivers/gpu/drm/ttm/ttm.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_object.o
  CC [M]  drivers/gpu/drm/xe/xe_device.o
  CC [M]  net/dns_resolver/dns_key.o
  AR      net/handshake/built-in.a
  CC      net/bridge/br_arp_nd_proxy.o
  CC [M]  drivers/net/usb/rtl8150.o
  CC      drivers/acpi/acpica/rscreate.o
  CC      net/ipv6/xfrm6_state.o
  CC [M]  drivers/net/ipvlan/ipvlan_main.o
  CC      lib/bitmap.o
  CC [M]  net/bluetooth/hci_event.o
  CC      lib/scatterlist.o
  CC      drivers/scsi/scsi_bsg.o
  CC      kernel/kthread.o
  CC      fs/btrfs/ordered-data.o
  CC [M]  drivers/gpu/drm/xe/xe_device_sysfs.o
  CC [M]  drivers/net/ipvlan/ipvlan_l3s.o
  CC [M]  net/bluetooth/mgmt.o
  CC [M]  drivers/gpu/drm/nouveau/nvif/head.o
  CC      net/ipv4/devinet.o
  CC      kernel/sys_ni.o
  CC      drivers/base/auxiliary.o
  CC [M]  drivers/net/phy/aquantia_main.o
  CC      arch/x86/kernel/tsc_sync.o
  CC      drivers/scsi/scsi_common.o
  CC      drivers/gpu/drm/drm_mipi_dsi.o
  CC      drivers/scsi/sd.o
  CC [M]  drivers/gpu/drm/i915/intel_clock_gating.o
  CC      net/ipv4/af_inet.o
  CC      drivers/acpi/acpica/rsdumpinfo.o
  CC [M]  fs/smb/client/nterr.o
  CC [M]  net/dns_resolver/dns_query.o
  CC [M]  drivers/gpu/drm/ast/ast_dp501.o
  CC      fs/btrfs/extent_io.o
  CC [M]  net/netfilter/xt_addrtype.o
  CC [M]  drivers/net/phy/aquantia_hwmon.o
  CC [M]  drivers/gpu/drm/i915/intel_device_info.o
  CC      drivers/scsi/sg.o
  CC      drivers/base/devtmpfs.o
  CC      drivers/acpi/pci_root.o
  CC [M]  drivers/gpu/drm/nouveau/nvif/mem.o
  CC      drivers/ata/libata-acpi.o
  CC      lib/list_sort.o
  CC      arch/x86/kernel/setup_percpu.o
  CC      drivers/acpi/acpica/rsinfo.o
  CC [M]  drivers/gpu/drm/i915/intel_memory_region.o
  CC [M]  net/sunrpc/auth_gss/gss_rpc_xdr.o
  CC [M]  drivers/gpu/drm/nouveau/nvif/mmu.o
  CC      lib/uuid.o
  CC [M]  fs/smb/client/cifsencrypt.o
  CC      drivers/acpi/acpica/rsio.o
  CC      net/ipv6/xfrm6_input.o
  CC [M]  drivers/gpu/drm/xe/xe_dma_buf.o
  CC [M]  drivers/gpu/drm/i915/intel_pcode.o
  CC      drivers/acpi/pci_link.o
  CC      net/core/ptp_classifier.o
  CC      lib/iov_iter.o
  CC      net/core/netprio_cgroup.o
  CC [M]  drivers/net/phy/ax88796b.o
  CC [M]  drivers/gpu/drm/xe/xe_drm_client.o
  CC      net/bridge/br_sysfs_if.o
  CC [M]  drivers/net/usb/r8152.o
  CC [M]  drivers/gpu/drm/ast/ast_dp.o
  LD [M]  net/dns_resolver/dns_resolver.o
  CC [M]  drivers/net/ethernet/broadcom/cnic.o
  CC      net/ipv4/igmp.o
  CC      drivers/acpi/pci_irq.o
  CC      drivers/scsi/scsi_sysfs.o
  CC [M]  net/netfilter/xt_conntrack.o
  CC      drivers/acpi/acpica/rsirq.o
  CC      kernel/nsproxy.o
  CC      drivers/acpi/acpica/rslist.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_gart.o
  LD [M]  drivers/net/ipvlan/ipvlan.o
  CC      arch/x86/kernel/ftrace.o
  CC [M]  drivers/gpu/drm/drm_aperture.o
  CC      drivers/base/node.o
  CC      net/devres.o
  CC [M]  drivers/gpu/drm/i915/intel_region_ttm.o
  CC      net/bridge/br_sysfs_br.o
  CC [M]  drivers/gpu/drm/nouveau/nvif/outp.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.o
  CC [M]  drivers/net/phy/bcm7xxx.o
  CC [M]  drivers/net/phy/bcm87xx.o
  CC      net/socket.o
  CC      drivers/ata/libata-pata-timings.o
  CC      net/ipv4/fib_frontend.o
  CC      net/bridge/br_nf_core.o
  CC      drivers/acpi/acpica/rsmemory.o
  CC      net/bridge/br_multicast.o
  CC [M]  net/sunrpc/auth_gss/trace.o
  CC [M]  drivers/net/usb/asix_devices.o
  CC      drivers/usb/common/common.o
  CC      drivers/input/serio/serio.o
  CC      drivers/usb/core/usb.o
  LD [M]  drivers/gpu/drm/ast/ast.o
  AR      drivers/usb/phy/built-in.a
  CC [M]  drivers/gpu/drm/i915/intel_runtime_pm.o
  CC [M]  drivers/gpu/drm/xe/xe_exec.o
  CC      drivers/usb/common/debug.o
  CC      net/core/dst_cache.o
  CC      net/ipv6/xfrm6_output.o
  CC      net/sunrpc/socklib.o
  CC [M]  net/bluetooth/hci_sock.o
  CC      drivers/usb/core/hub.o
  CC [M]  drivers/gpu/drm/drm_atomic.o
  CC      drivers/acpi/acpica/rsmisc.o
  CC      net/core/gro_cells.o
  CC      mm/khugepaged.o
  AS      arch/x86/kernel/ftrace_64.o
  CC      arch/x86/kernel/trace_clock.o
  CC      arch/x86/kernel/trace.o
  CC      kernel/notifier.o
  CC [M]  net/netfilter/xt_ipvs.o
  CC [M]  fs/smb/client/readdir.o
  CC      drivers/base/memory.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_display.o
  CC      net/bridge/br_mdb.o
  CC      net/ipv4/fib_semantics.o
  CC [M]  net/bluetooth/hci_sysfs.o
  CC [M]  net/bluetooth/l2cap_core.o
  CC [M]  drivers/gpu/drm/nouveau/nvif/timer.o
  CC [M]  drivers/net/phy/bcm-phy-lib.o
  CC      drivers/ata/ahci.o
  CC      drivers/acpi/acpica/rsserial.o
  CC [M]  drivers/gpu/drm/drm_atomic_uapi.o
  CC [M]  drivers/gpu/drm/nouveau/nvif/vmm.o
  AR      drivers/scsi/built-in.a
  CC [M]  fs/smb/client/ioctl.o
  AR      drivers/usb/common/built-in.a
  CC [M]  net/bluetooth/l2cap_sock.o
  CC      drivers/input/serio/i8042.o
  CC [M]  drivers/gpu/drm/i915/intel_sbi.o
  CC      drivers/ata/libahci.o
  CC      drivers/acpi/acpica/rsutils.o
  CC      drivers/input/serio/libps2.o
  CC      arch/x86/kernel/rethook.o
  CC      drivers/usb/core/hcd.o
  CC      drivers/input/keyboard/atkbd.o
  CC      drivers/rtc/lib.o
  CC [M]  drivers/gpu/drm/xe/xe_execlist.o
  CC      drivers/usb/core/urb.o
  AR      net/core/built-in.a
  CC      arch/x86/kernel/crash_core_64.o
  AR      drivers/i2c/algos/built-in.a
  CC [M]  drivers/i2c/algos/i2c-algo-bit.o
  CC [M]  drivers/net/vxlan/vxlan_vnifilter.o
  CC [M]  drivers/net/usb/asix_common.o
  CC      drivers/i2c/busses/i2c-designware-common.o
  CC      mm/page_counter.o
  CC      drivers/base/module.o
  CC      drivers/i2c/busses/i2c-designware-master.o
  CC      kernel/ksysfs.o
  CC      drivers/acpi/acpica/rsxface.o
  CC      net/ipv6/xfrm6_protocol.o
  CC      drivers/rtc/class.o
  CC      lib/clz_ctz.o
  CC [M]  net/bluetooth/smp.o
  CC      lib/bsearch.o
  CC [M]  drivers/gpu/drm/nouveau/nvif/user.o
  LD [M]  net/netfilter/nf_conntrack.o
  LD [M]  net/netfilter/nf_nat.o
  CC      mm/memcontrol.o
  AR      net/netfilter/built-in.a
  CC [M]  drivers/gpu/drm/xe/xe_exec_queue.o
  CC      net/ipv4/fib_trie.o
  AR      drivers/input/mouse/built-in.a
  CC      drivers/rtc/interface.o
  CC      arch/x86/kernel/module.o
  CC      net/compat.o
  CC [M]  drivers/net/vxlan/vxlan_mdb.o
  CC      drivers/base/pinctrl.o
  CC [M]  drivers/net/phy/broadcom.o
  CC [M]  drivers/gpu/drm/i915/intel_step.o
  CC      net/ipv4/fib_notifier.o
  CC      drivers/acpi/acpica/tbdata.o
  CC      fs/btrfs/volumes.o
  CC      net/sunrpc/xprtsock.o
  CC      kernel/cred.o
  CC      lib/find_bit.o
  CC      drivers/usb/core/message.o
  AR      drivers/input/serio/built-in.a
  CC      net/sysctl_net.o
  CC      lib/llist.o
  CC      drivers/rtc/nvmem.o
  CC      mm/vmpressure.o
  CC [M]  net/bluetooth/lib.o
  CC [M]  drivers/gpu/drm/xe/xe_force_wake.o
  CC [M]  net/sunrpc/auth_gss/gss_krb5_mech.o
  CC      drivers/usb/host/pci-quirks.o
  AR      drivers/input/keyboard/built-in.a
  CC      drivers/input/input.o
  CC      drivers/rtc/dev.o
  CC      drivers/base/devcoredump.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.o
  CC      lib/memweight.o
  CC [M]  fs/smb/client/sess.o
  CC      drivers/ata/ata_piix.o
  CC      arch/x86/kernel/early_printk.o
  CC [M]  drivers/gpu/drm/nouveau/nvif/userc361.o
  CC [M]  drivers/net/phy/lxt.o
  CC      lib/kfifo.o
  CC [M]  drivers/gpu/drm/xe/xe_ggtt.o
  CC      drivers/i2c/busses/i2c-designware-platdrv.o
  CC [M]  net/bluetooth/ecdh_helper.o
  CC      drivers/acpi/acpica/tbfadt.o
  CC      net/ipv6/netfilter.o
  CC      drivers/rtc/proc.o
  CC [M]  fs/smb/client/export.o
  CC      drivers/usb/host/ehci-hcd.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/core/client.o
  CC      arch/x86/kernel/hpet.o
  CC      net/bridge/br_multicast_eht.o
  CC      net/ipv4/inet_fragment.o
  CC [M]  drivers/gpu/drm/i915/intel_uncore.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_gem.o
  CC      drivers/base/platform-msi.o
  CC      kernel/reboot.o
  CC      drivers/acpi/acpica/tbfind.o
  CC      drivers/acpi/acpica/tbinstal.o
  CC      arch/x86/kernel/amd_nb.o
  CC [M]  net/sunrpc/auth_gss/gss_krb5_seal.o
  CC      drivers/usb/core/driver.o
  CC      mm/swap_cgroup.o
  CC      drivers/base/physical_location.o
  CC [M]  fs/smb/client/unc.o
  CC      net/ipv4/ping.o
  CC      drivers/rtc/sysfs.o
  CC      kernel/async.o
  CC [M]  drivers/gpu/drm/i915/intel_wakeref.o
  CC      drivers/rtc/rtc-mc146818-lib.o
  CC      lib/percpu-refcount.o
  CC      drivers/base/trace.o
  CC      mm/hugetlb_cgroup.o
  CC [M]  drivers/net/phy/realtek.o
  CC      drivers/i2c/busses/i2c-designware-baytrail.o
  CC [M]  net/bluetooth/hci_request.o
  CC [M]  drivers/net/ethernet/broadcom/tg3.o
  CC      drivers/usb/host/ehci-pci.o
  CC [M]  drivers/net/phy/smsc.o
  CC      drivers/acpi/acpica/tbprint.o
  CC [M]  drivers/gpu/drm/xe/xe_gt.o
  AR      drivers/ata/built-in.a
  AR      drivers/i3c/built-in.a
  CC [M]  drivers/gpu/drm/i915/vlv_sideband.o
  AR      drivers/i2c/muxes/built-in.a
  CC [M]  drivers/i2c/muxes/i2c-mux-gpio.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/core/engine.o
  CC [M]  fs/smb/client/winucase.o
  CC      fs/btrfs/async-thread.o
  CC [M]  net/bluetooth/mgmt_util.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_ring.o
  CC      net/ipv6/fib6_rules.o
  CC [M]  net/sunrpc/auth_gss/gss_krb5_unseal.o
  CC      kernel/range.o
  CC [M]  drivers/gpu/drm/i915/vlv_suspend.o
  CC      drivers/usb/core/config.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/core/enum.o
  CC      arch/x86/kernel/kvm.o
  CC      drivers/input/input-compat.o
  CC      drivers/rtc/rtc-cmos.o
  LD [M]  drivers/net/vxlan/vxlan.o
  CC      drivers/usb/storage/scsiglue.o
  CC      drivers/acpi/acpica/tbutils.o
  CC      drivers/usb/storage/protocol.o
  CC      kernel/smpboot.o
  CC      lib/rhashtable.o
  CC      net/ipv6/proc.o
  AR      drivers/base/built-in.a
  CC [M]  drivers/i2c/busses/i2c-scmi.o
  CC      drivers/usb/serial/usb-serial.o
  CC [M]  drivers/gpu/drm/drm_auth.o
  CC      drivers/net/netconsole.o
  CC [M]  drivers/gpu/drm/xe/xe_gt_clock.o
  CC      fs/dcache.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.o
  CC      net/ipv4/ip_tunnel_core.o
  CC      net/bridge/br_vlan.o
  CC [M]  net/bluetooth/mgmt_config.o
  CC      net/sunrpc/sched.o
  CC [M]  drivers/net/usb/ax88172a.o
  CC      drivers/input/input-mt.o
  CC      drivers/usb/core/file.o
  CC [M]  drivers/net/dummy.o
  LD [M]  drivers/net/phy/aquantia.o
  CC      drivers/acpi/acpica/tbxface.o
  CC      drivers/usb/serial/generic.o
  CC      drivers/usb/host/ohci-hcd.o
  AR      drivers/net/phy/built-in.a
  CC      net/ipv4/gre_offload.o
  CC [M]  net/sunrpc/auth_gss/gss_krb5_seqnum.o
  CC [M]  fs/smb/client/smb2ops.o
  CC      arch/x86/kernel/kvmclock.o
  CC      net/ipv6/syncookies.o
  CC      kernel/ucount.o
  CC      fs/inode.o
  CC [M]  drivers/gpu/drm/drm_blend.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/core/event.o
  CC [M]  net/bluetooth/hci_codec.o
  CC      drivers/usb/host/ohci-pci.o
  CC      drivers/usb/storage/transport.o
  CC      drivers/usb/core/buffer.o
  CC [M]  drivers/i2c/busses/i2c-ccgx-ucsi.o
  CC [M]  drivers/net/macvlan.o
  CC      mm/kmemleak.o
  CC [M]  drivers/gpu/drm/drm_bridge.o
  AR      drivers/rtc/built-in.a
  CC      drivers/acpi/acpica/tbxfload.o
  CC [M]  fs/smb/client/smb2maperror.o
  CC      kernel/regset.o
  CC      fs/btrfs/ioctl.o
  CC [M]  drivers/gpu/drm/xe/xe_gt_debugfs.o
  CC      drivers/usb/core/sysfs.o
  CC [M]  drivers/i2c/busses/i2c-i801.o
  AR      drivers/media/i2c/built-in.a
  AR      drivers/media/tuners/built-in.a
  AR      drivers/ptp/built-in.a
  CC      drivers/input/input-poller.o
  CC [M]  drivers/ptp/ptp_clock.o
  AR      drivers/media/rc/keymaps/built-in.a
  AR      drivers/media/rc/built-in.a
  AR      drivers/media/common/b2c2/built-in.a
  CC [M]  net/sunrpc/auth_gss/gss_krb5_wrap.o
  AR      drivers/media/common/saa7146/built-in.a
  AR      drivers/media/common/siano/built-in.a
  AR      drivers/media/common/v4l2-tpg/built-in.a
  AR      drivers/media/common/videobuf2/built-in.a
  AR      drivers/media/common/built-in.a
  AR      drivers/media/platform/allegro-dvt/built-in.a
  CC      kernel/ksyms_common.o
  CC [M]  net/sunrpc/auth_gss/gss_krb5_crypto.o
  AR      drivers/media/platform/amlogic/meson-ge2d/built-in.a
  AR      drivers/media/platform/amlogic/built-in.a
  CC      arch/x86/kernel/paravirt.o
  AR      drivers/media/platform/amphion/built-in.a
  AR      drivers/media/platform/aspeed/built-in.a
  AR      drivers/media/platform/atmel/built-in.a
  AR      drivers/media/pci/ttpci/built-in.a
  CC [M]  drivers/net/usb/ax88179_178a.o
  CC [M]  drivers/net/usb/cdc_ether.o
  AR      drivers/media/platform/cadence/built-in.a
  AR      drivers/media/pci/b2c2/built-in.a
  AR      drivers/media/platform/chips-media/built-in.a
  AR      drivers/media/pci/pluto2/built-in.a
  AR      drivers/media/platform/intel/built-in.a
  AR      drivers/media/pci/dm1105/built-in.a
  AR      drivers/usb/misc/built-in.a
  AR      drivers/media/platform/marvell/built-in.a
  AR      drivers/media/pci/pt1/built-in.a
  AR      drivers/media/usb/b2c2/built-in.a
  AR      drivers/media/platform/mediatek/jpeg/built-in.a
  AR      drivers/media/pci/pt3/built-in.a
  AR      drivers/media/usb/dvb-usb/built-in.a
  AR      drivers/media/pci/mantis/built-in.a
  AR      drivers/media/platform/mediatek/mdp/built-in.a
  AR      drivers/media/usb/dvb-usb-v2/built-in.a
  AR      drivers/media/platform/mediatek/vcodec/built-in.a
  AR      drivers/media/pci/ngene/built-in.a
  AR      drivers/media/usb/s2255/built-in.a
  AR      drivers/media/platform/mediatek/vpu/built-in.a
  CC [M]  drivers/usb/class/usbtmc.o
  AR      drivers/media/pci/ddbridge/built-in.a
  AR      drivers/media/usb/siano/built-in.a
  CC      drivers/usb/gadget/udc/core.o
  AR      drivers/media/platform/mediatek/mdp3/built-in.a
  AR      drivers/media/usb/ttusb-budget/built-in.a
  AR      drivers/media/mmc/siano/built-in.a
  AR      drivers/media/platform/mediatek/built-in.a
  AR      drivers/media/pci/saa7146/built-in.a
  AR      drivers/media/mmc/built-in.a
  CC      lib/base64.o
  AR      drivers/media/usb/ttusb-dec/built-in.a
  CC      drivers/acpi/acpica/tbxfroot.o
  AR      drivers/media/pci/smipcie/built-in.a
  AR      drivers/media/usb/built-in.a
  AR      drivers/media/platform/microchip/built-in.a
  CC      net/ipv4/metrics.o
  AR      drivers/media/pci/netup_unidvb/built-in.a
  AR      drivers/media/platform/nvidia/tegra-vde/built-in.a
  CC      kernel/groups.o
  CC      drivers/usb/serial/bus.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/core/firmware.o
  AR      drivers/media/platform/nvidia/built-in.a
  AR      drivers/media/pci/intel/ipu3/built-in.a
  AR      drivers/media/pci/intel/built-in.a
  AR      drivers/media/platform/nxp/dw100/built-in.a
  AR      drivers/media/pci/built-in.a
  AR      drivers/media/platform/nxp/imx-jpeg/built-in.a
  AR      drivers/media/platform/nxp/imx8-isi/built-in.a
  CC      fs/btrfs/locking.o
  AR      drivers/media/platform/nxp/built-in.a
  AR      drivers/usb/gadget/function/built-in.a
  CC [M]  net/sunrpc/auth_gss/gss_krb5_keys.o
  CC      lib/once.o
  CC [M]  net/bluetooth/eir.o
  AR      drivers/media/platform/qcom/camss/built-in.a
  AR      drivers/media/platform/qcom/venus/built-in.a
  AR      drivers/media/platform/qcom/built-in.a
  AR      drivers/media/platform/renesas/rcar-vin/built-in.a
  AR      drivers/media/platform/renesas/rzg2l-cru/built-in.a
  CC      drivers/usb/core/endpoint.o
  AR      drivers/media/platform/renesas/vsp1/built-in.a
  AR      drivers/media/platform/renesas/built-in.a
  AR      drivers/media/platform/rockchip/rga/built-in.a
  AR      drivers/media/platform/rockchip/rkisp1/built-in.a
  CC [M]  drivers/gpu/drm/nouveau/nvkm/core/gpuobj.o
  AR      drivers/media/platform/rockchip/built-in.a
  AR      drivers/media/platform/samsung/exynos-gsc/built-in.a
  CC      net/ipv4/netlink.o
  AR      drivers/media/platform/samsung/exynos4-is/built-in.a
  AR      drivers/media/platform/samsung/s3c-camif/built-in.a
  CC      drivers/input/ff-core.o
  AR      drivers/media/platform/samsung/s5p-g2d/built-in.a
  AR      drivers/media/platform/samsung/s5p-jpeg/built-in.a
  AR      drivers/media/platform/samsung/s5p-mfc/built-in.a
  AR      drivers/media/platform/samsung/built-in.a
  AR      drivers/media/platform/st/sti/bdisp/built-in.a
  CC      net/ipv4/nexthop.o
  AR      drivers/media/platform/st/sti/c8sectpfe/built-in.a
  AR      drivers/media/platform/st/sti/delta/built-in.a
  AR      drivers/media/firewire/built-in.a
  AR      drivers/media/platform/st/sti/hva/built-in.a
  CC      drivers/usb/serial/console.o
  AR      drivers/media/platform/st/stm32/built-in.a
  AR      drivers/media/platform/st/built-in.a
  AR      drivers/media/platform/sunxi/sun4i-csi/built-in.a
  AR      drivers/media/platform/sunxi/sun6i-csi/built-in.a
  CC      drivers/usb/storage/usb.o
  AR      drivers/media/platform/sunxi/sun6i-mipi-csi2/built-in.a
  CC      drivers/acpi/acpica/utaddress.o
  CC      drivers/usb/storage/initializers.o
  CC      drivers/usb/storage/sierra_ms.o
  AR      drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/built-in.a
  CC      net/ipv6/mip6.o
  AR      drivers/media/platform/sunxi/sun8i-di/built-in.a
  AR      drivers/media/platform/sunxi/sun8i-rotate/built-in.a
  CC [M]  drivers/gpu/drm/xe/xe_gt_idle_sysfs.o
  AR      drivers/media/platform/sunxi/built-in.a
  CC [M]  net/bluetooth/hci_sync.o
  AR      drivers/media/platform/ti/am437x/built-in.a
  AR      drivers/media/platform/ti/cal/built-in.a
  AR      drivers/media/platform/ti/vpe/built-in.a
  AR      drivers/media/platform/ti/davinci/built-in.a
  AR      drivers/media/platform/ti/omap/built-in.a
  CC      lib/refcount.o
  AR      drivers/media/platform/ti/omap3isp/built-in.a
  AR      drivers/media/platform/ti/built-in.a
  CC      arch/x86/kernel/pvclock.o
  CC [M]  net/bluetooth/coredump.o
  AR      drivers/media/platform/verisilicon/built-in.a
  AR      drivers/media/platform/via/built-in.a
  CC [M]  drivers/ptp/ptp_chardev.o
  AR      drivers/media/platform/xilinx/built-in.a
  AR      drivers/media/platform/built-in.a
  AR      drivers/media/spi/built-in.a
  CC [M]  net/bluetooth/sco.o
  CC      drivers/usb/serial/ftdi_sio.o
  AR      drivers/media/test-drivers/built-in.a
  AR      drivers/media/built-in.a
  CC [M]  drivers/gpu/drm/i915/soc/intel_dram.o
  CC      arch/x86/kernel/pcspeaker.o
  CC      drivers/usb/core/devio.o
  CC      mm/page_isolation.o
  CC      lib/rcuref.o
  CC      kernel/vhost_task.o
  CC      net/ipv4/udp_tunnel_stub.o
  CC [M]  net/bluetooth/iso.o
  CC      drivers/acpi/acpica/utalloc.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_bios.o
  AR      drivers/power/reset/built-in.a
  CC      drivers/power/supply/power_supply_core.o
  CC      drivers/input/touchscreen.o
  CC      drivers/power/supply/power_supply_sysfs.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.o
  LD [M]  net/sunrpc/auth_gss/auth_rpcgss.o
  CC      lib/usercopy.o
  LD [M]  net/sunrpc/auth_gss/rpcsec_gss_krb5.o
  CC [M]  drivers/i2c/busses/i2c-isch.o
  CC      fs/attr.o
  CC      drivers/power/supply/power_supply_leds.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/atombios_dp.o
  CC      drivers/input/ff-memless.o
  CC      drivers/usb/storage/option_ms.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_afmt.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/core/intr.o
  CC      drivers/acpi/acpica/utascii.o
  AR      drivers/usb/gadget/legacy/built-in.a
  CC [M]  net/bluetooth/a2mp.o
  CC      arch/x86/kernel/check.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_trace_points.o
  CC [M]  drivers/gpu/drm/xe/xe_gt_mcr.o
  CC [M]  drivers/net/usb/cdc_eem.o
  CC      drivers/hwmon/hwmon.o
  CC      kernel/kcmp.o
  CC      drivers/usb/core/notify.o
  CC      lib/errseq.o
  CC      mm/early_ioremap.o
  CC      fs/bad_inode.o
  CC [M]  drivers/gpu/drm/drm_cache.o
  AR      drivers/net/ethernet/cavium/common/built-in.a
  AR      drivers/net/ethernet/cavium/thunder/built-in.a
  CC [M]  drivers/net/usb/smsc75xx.o
  AR      drivers/net/ethernet/cavium/liquidio/built-in.a
  AR      drivers/net/ethernet/cavium/octeon/built-in.a
  AR      drivers/net/ethernet/cavium/built-in.a
  CC [M]  drivers/ptp/ptp_sysfs.o
  CC      lib/bucket_locks.o
  CC [M]  drivers/gpu/drm/drm_client.o
  CC      drivers/usb/gadget/udc/trace.o
  CC      drivers/usb/host/uhci-hcd.o
  AR      drivers/thermal/broadcom/built-in.a
  AR      drivers/thermal/samsung/built-in.a
  CC      drivers/thermal/intel/intel_tcc.o
  CC      drivers/thermal/intel/therm_throt.o
  AR      drivers/thermal/st/built-in.a
  AR      drivers/thermal/qcom/built-in.a
  CC      drivers/acpi/acpica/utbuffer.o
  CC [M]  drivers/thermal/intel/x86_pkg_temp_thermal.o
  AR      drivers/thermal/tegra/built-in.a
  AR      drivers/thermal/mediatek/built-in.a
  CC      net/bridge/br_vlan_tunnel.o
  CC      net/bridge/br_vlan_options.o
  CC [M]  net/bluetooth/amp.o
  CC      drivers/power/supply/power_supply_hwmon.o
  CC      net/ipv6/addrconf_core.o
  CC      drivers/usb/storage/usual-tables.o
  CC      arch/x86/kernel/uprobes.o
  CC      fs/file.o
  CC      drivers/input/vivaldi-fmap.o
  CC      net/bridge/br_mst.o
  CC [M]  drivers/i2c/busses/i2c-ismt.o
  CC      net/sunrpc/auth.o
  CC [M]  drivers/gpu/drm/i915/soc/intel_gmch.o
  CC [M]  drivers/gpu/drm/i915/soc/intel_pch.o
  CC      arch/x86/kernel/perf_regs.o
  CC      net/ipv4/sysctl_net_ipv4.o
  CC [M]  net/bluetooth/hci_debugfs.o
  CC      drivers/usb/serial/pl2303.o
  CC      kernel/freezer.o
  CC      lib/generic-radix-tree.o
  CC      drivers/acpi/acpica/utcksum.o
  CC      drivers/usb/host/xhci.o
  CC [M]  drivers/gpu/drm/i915/i915_memcpy.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/atombios_encoders.o
  CC      mm/cma.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/core/ioctl.o
  CC      drivers/watchdog/watchdog_core.o
  CC [M]  drivers/gpu/drm/xe/xe_gt_pagefault.o
  CC [M]  drivers/i2c/busses/i2c-piix4.o
  CC      drivers/input/input-leds.o
  AR      drivers/power/supply/built-in.a
  AR      drivers/power/built-in.a
  CC      mm/secretmem.o
  CC [M]  drivers/gpu/drm/drm_client_modeset.o
  CC [M]  drivers/gpu/drm/drm_color_mgmt.o
  CC [M]  drivers/gpu/drm/xe/xe_gt_sysfs.o
  CC [M]  drivers/ptp/ptp_vclock.o
  AR      drivers/usb/storage/built-in.a
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_sa.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/atombios_i2c.o
  CC      lib/string_helpers.o
  CC      drivers/acpi/acpica/utcopy.o
  CC [M]  drivers/hwmon/acpi_power_meter.o
  AR      drivers/thermal/intel/built-in.a
  CC      drivers/thermal/thermal_core.o
  CC      arch/x86/kernel/tracepoint.o
  CC [M]  drivers/gpu/drm/drm_connector.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.o
  CC [M]  drivers/md/persistent-data/dm-array.o
  AR      drivers/usb/gadget/udc/built-in.a
  CC      drivers/usb/gadget/usbstring.o
  CC      fs/btrfs/orphan.o
  CC      kernel/stacktrace.o
  CC      net/ipv6/exthdrs_core.o
  CC      drivers/input/mousedev.o
  CC [M]  drivers/md/persistent-data/dm-bitset.o
  CC [M]  drivers/i2c/busses/i2c-designware-pcidrv.o
  CC      drivers/usb/core/generic.o
  AR      drivers/usb/serial/built-in.a
  CC [M]  drivers/gpu/drm/drm_crtc.o
  CC      drivers/usb/gadget/config.o
  CC      arch/x86/kernel/itmt.o
  CC      drivers/acpi/acpica/utexcep.o
  CC [M]  drivers/ptp/ptp_kvm_x86.o
  CC      drivers/input/evdev.o
  CC      net/ipv6/ip6_checksum.o
  CC [M]  drivers/gpu/drm/i915/i915_mm.o
  CC [M]  net/bridge/br_netfilter_hooks.o
  CC [M]  net/bridge/br_netfilter_ipv6.o
  CC      drivers/usb/core/quirks.o
  CC      drivers/watchdog/watchdog_dev.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/core/memory.o
  CC      net/ipv6/ip6_icmp.o
  CC [M]  drivers/net/usb/smsc95xx.o
  CC      net/ipv4/proc.o
  CC      lib/hexdump.o
  CC [M]  drivers/hwmon/coretemp.o
  CC      net/ipv4/syncookies.o
  CC [M]  drivers/gpu/drm/xe/xe_gt_tlb_invalidation.o
  CC      drivers/usb/gadget/epautoconf.o
  CC      drivers/acpi/acpica/utdebug.o
  CC      mm/userfaultfd.o
  CC      kernel/dma.o
  CC      lib/kstrtox.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/core/mm.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/core/object.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/core/oproxy.o
  CC [M]  drivers/gpu/drm/drm_displayid.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.o
  AR      drivers/i2c/busses/built-in.a
  CC      mm/memremap.o
  CC [M]  drivers/md/persistent-data/dm-block-manager.o
  CC      arch/x86/kernel/umip.o
  CC [M]  drivers/gpu/drm/i915/i915_sw_fence.o
  CC [M]  drivers/gpu/drm/xe/xe_gt_topology.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.o
  CC      drivers/opp/core.o
  CC [M]  fs/smb/client/smb2transport.o
  CC      drivers/opp/cpu.o
  CC [M]  drivers/ptp/ptp_kvm_common.o
  CC      drivers/acpi/acpica/utdecode.o
  CC [M]  fs/smb/client/smb2misc.o
  LD [M]  drivers/i2c/busses/i2c-designware-pci.o
  CC      drivers/usb/gadget/composite.o
  CC      net/sunrpc/auth_null.o
  CC      drivers/i2c/i2c-boardinfo.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_ib.o
  CC      drivers/usb/core/devices.o
  CC      fs/btrfs/export.o
  CC [M]  fs/smb/client/smb2pdu.o
  CC      kernel/smp.o
  CC      lib/debug_info.o
  CC [M]  drivers/md/persistent-data/dm-space-map-common.o
  CC [M]  drivers/gpu/drm/i915/i915_sw_fence_work.o
  CC      drivers/i2c/i2c-core-base.o
  CC [M]  drivers/gpu/drm/drm_drv.o
  CC      drivers/thermal/thermal_sysfs.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_pll.o
  CC      drivers/watchdog/softdog.o
  CC      lib/iomap.o
  LD [M]  drivers/ptp/ptp.o
  CC [M]  drivers/gpu/drm/i915/i915_syncmap.o
  CC      net/ipv6/output_core.o
  AR      drivers/input/built-in.a
  CC      drivers/opp/debugfs.o
  AR      drivers/hwmon/built-in.a
  CC      drivers/usb/gadget/functions.o
  CC      drivers/acpi/acpica/utdelete.o
  CC [M]  drivers/md/persistent-data/dm-space-map-disk.o
  CC [M]  drivers/net/mii.o
  LD [M]  net/bluetooth/bluetooth.o
  CC      fs/btrfs/tree-log.o
  CC      arch/x86/kernel/unwind_orc.o
  CC      kernel/uid16.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/core/option.o
  CC [M]  drivers/net/mdio.o
  CC      drivers/acpi/acpica/uterror.o
  CC      drivers/i2c/i2c-core-smbus.o
  LD [M]  drivers/ptp/ptp_kvm.o
  CC [M]  drivers/net/tun.o
  CC      net/ipv6/protocol.o
  HOSTCC  drivers/gpu/drm/xe/xe_gen_wa_oob
  AR      drivers/watchdog/built-in.a
  CC      drivers/i2c/i2c-core-acpi.o
  CC [M]  drivers/gpu/drm/i915/i915_user_extensions.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.o
  CC      arch/x86/kernel/callthunks.o
  CC      drivers/usb/core/phy.o
  CC      mm/hmm.o
  CC [M]  drivers/gpu/drm/xe/xe_guc_ads.o
  CC      net/ipv4/esp4.o
  CC      net/sunrpc/auth_tls.o
  CC      drivers/acpi/acpica/uteval.o
  CC      net/ipv6/ip6_offload.o
  AR      drivers/net/ethernet/cortina/built-in.a
  AR      drivers/net/ethernet/engleder/built-in.a
  AR      drivers/net/ethernet/ezchip/built-in.a
  CC      drivers/usb/gadget/configfs.o
  AR      drivers/net/ethernet/fungible/built-in.a
  AR      drivers/net/ethernet/huawei/built-in.a
  CC      drivers/thermal/thermal_trip.o
  CC      net/ipv4/esp4_offload.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.o
  CC [M]  drivers/net/usb/mcs7830.o
  CC      net/sunrpc/auth_unix.o
  CC      arch/x86/kernel/mmconf-fam10h_64.o
  CC [M]  drivers/md/persistent-data/dm-space-map-metadata.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/core/ramht.o
  CC      drivers/usb/gadget/u_f.o
  CC      net/sunrpc/svc.o
  CC      net/ipv6/tcpv6_offload.o
  AR      net/bridge/built-in.a
  CC      lib/pci_iomap.o
  CC      lib/iomap_copy.o
  CC [M]  drivers/gpu/drm/i915/i915_ioc32.o
  CC      net/ipv4/netfilter.o
  CC      drivers/acpi/acpica/utglobal.o
  CC [M]  drivers/gpu/drm/drm_dumb_buffers.o
  CC [M]  drivers/net/ethernet/intel/e1000/e1000_main.o
  CC [M]  drivers/net/ethernet/intel/e1000e/82571.o
  AR      drivers/opp/built-in.a
  CC [M]  drivers/net/ethernet/intel/igb/igb_main.o
  CC [M]  drivers/net/ethernet/intel/igc/igc_main.o
  CC [M]  drivers/gpu/drm/i915/i915_debugfs.o
  CC      kernel/kallsyms.o
  LD [M]  net/bridge/br_netfilter.o
  CC [M]  drivers/net/ethernet/intel/igc/igc_mac.o
  CC      drivers/usb/host/xhci-mem.o
  CC [M]  drivers/net/ethernet/intel/igb/igb_ethtool.o
  CC      drivers/thermal/thermal_helpers.o
  CC      drivers/usb/core/port.o
  CC [M]  drivers/net/ethernet/intel/igc/igc_i225.o
  CC [M]  fs/smb/client/smb2inode.o
  CC [M]  drivers/net/ethernet/intel/igb/e1000_82575.o
  CC [M]  drivers/net/ethernet/intel/igbvf/vf.o
  CC      drivers/usb/core/hcd-pci.o
  CC      drivers/i2c/i2c-core-slave.o
  CC      kernel/acct.o
  CC      drivers/thermal/thermal_hwmon.o
  CC      drivers/acpi/acpica/uthex.o
  CC      arch/x86/kernel/vsmp_64.o
  CC      mm/memfd.o
  CC      lib/devres.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.o
  CC [M]  drivers/md/persistent-data/dm-transaction-manager.o
  CC [M]  drivers/md/persistent-data/dm-btree.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/core/subdev.o
  CC [M]  drivers/gpu/drm/i915/i915_debugfs_params.o
  CC [M]  drivers/net/veth.o
  CC [M]  drivers/net/usb/usbnet.o
  CC      kernel/crash_core.o
  CC      lib/check_signature.o
  CC [M]  drivers/net/ethernet/intel/e1000/e1000_hw.o
  CC [M]  drivers/net/ethernet/intel/igc/igc_base.o
  CC      drivers/usb/core/usb-acpi.o
  CC      mm/bootmem_info.o
  CC      drivers/acpi/acpica/utids.o
  CC [M]  drivers/gpu/drm/xe/xe_guc_ct.o
  CC [M]  drivers/net/ethernet/intel/igb/e1000_mac.o
  AR      arch/x86/kernel/built-in.a
  CC      net/ipv6/exthdrs_offload.o
  CC      net/sunrpc/svcsock.o
  AR      arch/x86/built-in.a
  CC      net/ipv6/inet6_hashtables.o
  CC      drivers/thermal/gov_fair_share.o
  CC      drivers/thermal/gov_step_wise.o
  AR      drivers/usb/gadget/built-in.a
  CC      drivers/thermal/gov_user_space.o
  CC      net/ipv6/mcast_snoop.o
  CC      net/ipv4/inet_diag.o
  CC [M]  drivers/gpu/drm/xe/xe_guc_debugfs.o
  CC      kernel/compat.o
  CC [M]  drivers/net/ethernet/intel/igbvf/mbx.o
  CC [M]  drivers/net/usb/cdc_ncm.o
  CC      net/ipv4/tcp_diag.o
  CC [M]  drivers/net/ethernet/intel/igc/igc_nvm.o
  CC      drivers/i2c/i2c-dev.o
  CC      lib/interval_tree.o
  CC      drivers/acpi/acpica/utinit.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/core/uevent.o
  CC [M]  net/ipv6/ip6_udp_tunnel.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_sync.o
  CC      net/ipv4/udp_diag.o
  CC [M]  drivers/net/ethernet/intel/igb/e1000_nvm.o
  CC [M]  drivers/gpu/drm/i915/display/intel_display_debugfs.o
  CC      lib/assoc_array.o
  CC [M]  drivers/net/ethernet/intel/e1000e/ich8lan.o
  AR      drivers/thermal/built-in.a
  CC [M]  drivers/gpu/drm/xe/xe_guc_hwconfig.o
  AR      mm/built-in.a
  CC [M]  fs/smb/client/smb2file.o
  CC [M]  drivers/net/ethernet/intel/e1000e/80003es2lan.o
  AR      drivers/usb/core/built-in.a
  CC      net/ipv4/tcp_cubic.o
  CC      kernel/utsname.o
  CC [M]  drivers/gpu/drm/i915/display/intel_pipe_crc.o
  CC [M]  drivers/gpu/drm/i915/i915_pmu.o
  CC      drivers/acpi/acpica/utlock.o
  CC      drivers/usb/host/xhci-ext-caps.o
  CC      net/sunrpc/svcauth.o
  CC [M]  drivers/net/ethernet/intel/e1000e/mac.o
  CC      drivers/acpi/acpica/utmath.o
  CC [M]  drivers/md/persistent-data/dm-btree-remove.o
  CC [M]  drivers/net/ethernet/intel/igbvf/ethtool.o
  CC      kernel/user_namespace.o
  CC [M]  drivers/gpu/drm/drm_edid.o
  CC [M]  drivers/gpu/drm/i915/gt/gen2_engine_cs.o
  CC [M]  drivers/net/ethernet/intel/igc/igc_phy.o
  CC [M]  drivers/net/ethernet/intel/e1000e/manage.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/nvfw/fw.o
  CC [M]  drivers/gpu/drm/xe/xe_guc_log.o
  CC [M]  drivers/net/ethernet/intel/ixgbe/ixgbe_main.o
  CC [M]  drivers/net/ethernet/intel/ixgbevf/vf.o
  CC [M]  drivers/i2c/i2c-smbus.o
  CC [M]  drivers/net/ethernet/intel/ixgbevf/mbx.o
  CC      drivers/acpi/acpica/utmisc.o
  CC [M]  drivers/i2c/i2c-mux.o
  CC      drivers/usb/host/xhci-ring.o
  CC      lib/list_debug.o
  CC      drivers/usb/host/xhci-hub.o
  AR      net/ipv6/built-in.a
  CC [M]  drivers/net/ethernet/intel/igc/igc_diag.o
  CC [M]  drivers/net/ethernet/intel/e1000e/nvm.o
  AR      drivers/net/ethernet/intel/built-in.a
  CC [M]  drivers/net/ethernet/intel/e100.o
  CC      lib/debugobjects.o
  AR      drivers/i2c/built-in.a
  CC [M]  drivers/net/ethernet/intel/igb/e1000_phy.o
  CC [M]  drivers/net/ethernet/intel/igc/igc_ethtool.o
  CC      drivers/acpi/acpica/utmutex.o
  CC [M]  fs/smb/client/cifsacl.o
  CC [M]  drivers/gpu/drm/drm_encoder.o
  CC [M]  drivers/md/persistent-data/dm-btree-spine.o
  CC      drivers/acpi/acpica/utnonansi.o
  CC      drivers/usb/host/xhci-dbg.o
  CC      net/ipv4/xfrm4_policy.o
  CC [M]  drivers/net/ethernet/intel/igbvf/netdev.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/nvfw/hs.o
  CC [M]  drivers/net/usb/r8153_ecm.o
  CC      lib/bitrev.o
  CC [M]  fs/smb/client/fs_context.o
  CC [M]  drivers/net/ethernet/intel/igc/igc_ptp.o
  CC [M]  drivers/gpu/drm/xe/xe_guc_pc.o
  CC      kernel/pid_namespace.o
  CC      drivers/acpi/acpica/utobject.o
  CC      net/ipv4/xfrm4_state.o
  CC [M]  fs/smb/client/dns_resolve.o
  CC [M]  drivers/gpu/drm/i915/gt/gen6_engine_cs.o
  CC [M]  drivers/gpu/drm/xe/xe_guc_submit.o
  CC      fs/btrfs/free-space-cache.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.o
  CC [M]  drivers/net/ethernet/intel/e1000e/phy.o
  CC      drivers/usb/host/xhci-trace.o
  CC      drivers/acpi/acpica/utosi.o
  CC      fs/btrfs/zlib.o
  CC [M]  drivers/net/ethernet/intel/ixgbe/ixgbe_common.o
  CC      drivers/cpufreq/cpufreq.o
  CC [M]  drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.o
  CC      lib/crc16.o
  CC      drivers/cpufreq/freq_table.o
  CC [M]  drivers/net/ethernet/intel/igc/igc_dump.o
  CC [M]  drivers/net/ethernet/intel/ixgbevf/ethtool.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.o
  CC [M]  drivers/net/ethernet/intel/e1000/e1000_ethtool.o
  AR      drivers/net/ethernet/i825xx/built-in.a
  AR      drivers/net/ethernet/microsoft/built-in.a
  ASN.1   fs/smb/client/cifs_spnego_negtokeninit.asn1.[ch]
  CC [M]  drivers/net/ethernet/intel/igc/igc_tsn.o
  CC [M]  drivers/net/ethernet/intel/igc/igc_xdp.o
  AR      drivers/net/ethernet/litex/built-in.a
  CC [M]  fs/smb/client/smb1ops.o
  CC [M]  drivers/net/ethernet/intel/e1000/e1000_param.o
  CC      net/sunrpc/svcauth_unix.o
  LD [M]  drivers/md/persistent-data/dm-persistent-data.o
  CC      drivers/md/md.o
  CC      drivers/cpufreq/cpufreq_performance.o
  CC      drivers/acpi/acpica/utownerid.o
  CC      lib/crc-t10dif.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_virt.o
  CC      drivers/acpi/acpi_lpss.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/nvfw/ls.o
  LD [M]  drivers/net/usb/asix.o
  CC      fs/btrfs/lzo.o
  CC      fs/btrfs/zstd.o
  AR      drivers/net/ethernet/microchip/built-in.a
  AR      drivers/net/ethernet/mscc/built-in.a
  AR      drivers/net/ethernet/neterion/built-in.a
  AR      drivers/net/ethernet/netronome/built-in.a
  AR      drivers/net/ethernet/ni/built-in.a
  AR      drivers/net/ethernet/packetengines/built-in.a
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.o
  UPD     kernel/config_data
  CC      kernel/stop_machine.o
  CC      drivers/acpi/acpi_apd.o
  CC      drivers/acpi/acpica/utpredef.o
  CC      drivers/acpi/acpica/utresdecode.o
  CC [M]  drivers/net/ethernet/intel/e1000e/param.o
  CC      net/ipv4/xfrm4_input.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/nvfw/acr.o
  CC [M]  fs/smb/client/cifssmb.o
  HOSTCC  lib/gen_crc32table
  CC [M]  drivers/gpu/drm/xe/xe_hw_engine.o
  CC      drivers/cpufreq/cpufreq_ondemand.o
  CC [M]  drivers/net/ethernet/intel/igb/e1000_mbx.o
  CC [M]  drivers/net/ethernet/intel/igb/e1000_i210.o
  CC [M]  fs/smb/client/cifs_spnego_negtokeninit.asn1.o
  CC      lib/libcrc32c.o
  CC      fs/btrfs/compression.o
  CC      drivers/acpi/acpi_platform.o
  CC [M]  drivers/net/ethernet/intel/igb/igb_ptp.o
  CC [M]  drivers/gpu/drm/i915/gt/gen6_ppgtt.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_vf_error.o
  CC      kernel/kprobes.o
  CC [M]  fs/smb/client/asn1.o
  LD [M]  drivers/net/ethernet/intel/igc/igc.o
  CC      drivers/acpi/acpica/utresrc.o
  CC      net/sunrpc/addr.o
  CC [M]  drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.o
  CC [M]  drivers/gpu/drm/xe/xe_hw_engine_class_sysfs.o
  CC [M]  drivers/gpu/drm/xe/xe_hw_error.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_sched.o
  CC [M]  drivers/gpu/drm/i915/gt/gen7_renderclear.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/falcon/base.o
  CC      lib/xxhash.o
  CC      drivers/cpuidle/governors/menu.o
  CC      drivers/cpuidle/cpuidle.o
  CC      drivers/acpi/acpica/utstate.o
  CC      fs/btrfs/delayed-ref.o
  LD [M]  drivers/net/ethernet/intel/igbvf/igbvf.o
  CC      drivers/usb/host/xhci-debugfs.o
  CC      net/sunrpc/rpcb_clnt.o
  CC      lib/genalloc.o
  CC      drivers/mmc/core/core.o
  CC      drivers/mmc/host/sdhci.o
  CC      drivers/cpufreq/cpufreq_governor.o
  CC [M]  drivers/net/ethernet/intel/e1000e/ethtool.o
  CC      drivers/mmc/core/bus.o
  CC      drivers/mmc/host/sdhci-pci-core.o
  CC      drivers/cpufreq/cpufreq_governor_attr_set.o
  CC      drivers/mmc/core/host.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.o
  CC      net/ipv4/xfrm4_output.o
  LD [M]  drivers/net/ethernet/intel/e1000/e1000.o
  CC      drivers/mmc/host/sdhci-pci-o2micro.o
  CC      drivers/acpi/acpi_pnp.o
  AR      drivers/net/ethernet/realtek/built-in.a
  CC [M]  drivers/net/ethernet/realtek/8139cp.o
  CC [M]  drivers/gpu/drm/drm_file.o
  CC [M]  drivers/net/ethernet/realtek/8139too.o
  CC      drivers/cpuidle/governors/haltpoll.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_ids.o
  CC [M]  drivers/net/ethernet/intel/e1000e/netdev.o
  CC      drivers/acpi/acpica/utstring.o
  CC [M]  drivers/gpu/drm/xe/xe_hw_fence.o
  CC      drivers/cpufreq/acpi-cpufreq.o
  CC      fs/btrfs/relocation.o
  CC [M]  drivers/net/ethernet/intel/ixgbe/ixgbe_82599.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.o
  CC [M]  drivers/net/ethernet/intel/e1000e/ptp.o
  CC      drivers/md/md-bitmap.o
  CC      lib/percpu_counter.o
  CC      drivers/acpi/acpica/utstrsuppt.o
  CC [M]  drivers/net/ethernet/intel/ixgbe/ixgbe_82598.o
  CC      drivers/usb/host/xhci-pci.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/falcon/cmdq.o
  CC [M]  drivers/net/ethernet/intel/igb/igb_hwmon.o
  CC      drivers/md/md-autodetect.o
  CC      lib/fault-inject.o
  CC [M]  drivers/gpu/drm/drm_fourcc.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/falcon/fw.o
  AR      drivers/ufs/built-in.a
  CC      drivers/cpufreq/intel_pstate.o
  CC      lib/syscall.o
  AR      drivers/leds/trigger/built-in.a
  CC [M]  drivers/leds/trigger/ledtrig-audio.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/falcon/msgq.o
  CC [M]  drivers/gpu/drm/i915/gt/gen8_engine_cs.o
  CC      lib/dynamic_debug.o
  CC      fs/btrfs/delayed-inode.o
  CC [M]  drivers/gpu/drm/drm_framebuffer.o
  AR      drivers/leds/blink/built-in.a
  AR      drivers/leds/simple/built-in.a
  CC      drivers/leds/led-core.o
  CC      drivers/leds/led-class.o
  CC      drivers/acpi/acpica/utstrtoul64.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/falcon/qmgr.o
  AR      drivers/cpuidle/governors/built-in.a
  CC      drivers/cpuidle/driver.o
  CC      drivers/md/dm-uevent.o
  CC      kernel/hung_task.o
  CC      drivers/mmc/host/sdhci-pci-arasan.o
  CC      drivers/mmc/core/mmc.o
  CC [M]  drivers/gpu/drm/drm_gem.o
  CC      net/ipv4/xfrm4_protocol.o
  CC [M]  drivers/gpu/drm/xe/xe_huc.o
  CC      lib/errname.o
  CC      lib/nlattr.o
  CC [M]  drivers/net/ethernet/intel/ixgbevf/ipsec.o
  CC      lib/checksum.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/falcon/v1.o
  CC      drivers/acpi/acpica/utxface.o
  CC      drivers/acpi/acpica/utxfinit.o
  CC      drivers/acpi/power.o
  CC      fs/btrfs/scrub.o
  CC      drivers/cpuidle/governor.o
  CC      drivers/leds/led-triggers.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.o
  CC      lib/cpu_rmap.o
  CC [M]  drivers/gpu/drm/drm_ioctl.o
  CC      drivers/acpi/event.o
  LD [M]  drivers/net/ethernet/intel/igb/igb.o
  CC [M]  drivers/net/ethernet/intel/ixgbe/ixgbe_phy.o
  CC      net/sunrpc/timer.o
  CC      fs/btrfs/backref.o
  CC      drivers/mmc/host/sdhci-pci-dwc-mshc.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/falcon/gm200.o
  CC      kernel/watchdog.o
  CC      fs/filesystems.o
  CC      drivers/acpi/evged.o
  CC [M]  drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.o
  CC      net/sunrpc/xdr.o
  AR      drivers/usb/host/built-in.a
  AR      drivers/usb/built-in.a
  CC      drivers/cpuidle/sysfs.o
  CC      drivers/mmc/host/sdhci-pci-gli.o
  CC      kernel/watchdog_perf.o
  CC      drivers/acpi/acpica/utxferror.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/falcon/gp102.o
  CC [M]  drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.o
  CC [M]  drivers/net/ethernet/intel/ixgbe/ixgbe_x540.o
  AR      drivers/net/ethernet/renesas/built-in.a
  AR      drivers/net/ethernet/sfc/built-in.a
  AR      drivers/net/ethernet/smsc/built-in.a
  CC      drivers/mmc/host/sdhci-acpi.o
  CC [M]  net/ipv4/ip_tunnel.o
  CC [M]  drivers/net/ethernet/smsc/smsc9420.o
  CC [M]  drivers/gpu/drm/xe/xe_huc_debugfs.o
  CC [M]  drivers/gpu/drm/drm_lease.o
  CC [M]  drivers/net/ethernet/realtek/r8169_main.o
  CC      drivers/md/dm.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/falcon/ga100.o
  CC      drivers/acpi/sysfs.o
  CC      drivers/mmc/core/mmc_ops.o
  AR      drivers/leds/built-in.a
  CC      drivers/acpi/acpica/utxfmutex.o
  CC [M]  drivers/gpu/drm/xe/xe_irq.o
  CC [M]  drivers/net/ethernet/realtek/r8169_firmware.o
  CC [M]  drivers/gpu/drm/i915/gt/gen8_ppgtt.o
  CC      drivers/acpi/property.o
  CC [M]  drivers/gpu/drm/xe/xe_lrc.o
  CC      lib/dynamic_queue_limits.o
  CC [M]  drivers/net/ethernet/intel/ixgbe/ixgbe_x550.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.o
  CC      drivers/cpuidle/poll_state.o
  CC      fs/btrfs/ulist.o
  CC      kernel/seccomp.o
  CC [M]  drivers/net/ethernet/realtek/r8169_phy_config.o
  CC      kernel/relay.o
  CC [M]  drivers/gpu/drm/drm_managed.o
  CC [M]  drivers/net/ethernet/intel/ixgbe/ixgbe_lib.o
  CC      lib/glob.o
  CC      fs/btrfs/qgroup.o
  CC      drivers/mmc/host/cqhci-core.o
  AR      drivers/cpufreq/built-in.a
  LD [M]  drivers/net/ethernet/intel/ixgbevf/ixgbevf.o
  CC      drivers/md/dm-table.o
  CC [M]  net/ipv4/udp_tunnel_core.o
  AR      drivers/acpi/acpica/built-in.a
  CC      drivers/mmc/core/sd.o
  CC      drivers/cpuidle/cpuidle-haltpoll.o
  CC      net/sunrpc/sunrpc_syms.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/falcon/ga102.o
  CC      drivers/mmc/core/sd_ops.o
  CC      kernel/utsname_sysctl.o
  CC      drivers/md/dm-target.o
  CC [M]  drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.o
  LD [M]  fs/smb/client/cifs.o
  CC [M]  drivers/mmc/host/sdhci-pltfm.o
  CC      fs/namespace.o
  CC      lib/strncpy_from_user.o
  CC      fs/btrfs/send.o
  CC      net/sunrpc/cache.o
  CC      drivers/mmc/core/sdio.o
  AR      drivers/net/ethernet/socionext/built-in.a
  CC      kernel/delayacct.o
  CC      fs/seq_file.o
  AR      drivers/cpuidle/built-in.a
  CC [M]  net/ipv4/udp_tunnel_nic.o
  AR      drivers/net/ethernet/vertexcom/built-in.a
  AR      drivers/net/ethernet/wangxun/built-in.a
  CC      fs/btrfs/dev-replace.o
  CC      drivers/acpi/acpi_cmos_rtc.o
  AR      drivers/net/ethernet/xilinx/built-in.a
  CC      kernel/taskstats.o
  CC      drivers/md/dm-linear.o
  CC      fs/xattr.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.o
  AR      net/ipv4/built-in.a
  CC [M]  drivers/net/ethernet/intel/ixgbe/ixgbe_xsk.o
  CC      drivers/mmc/core/sdio_ops.o
  CC      drivers/mmc/core/sdio_bus.o
  CC [M]  drivers/net/ethernet/intel/ixgbe/ixgbe_dcb.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_breadcrumbs.o
  CC      drivers/md/dm-stripe.o
  CC      net/sunrpc/rpc_pipe.o
  CC      lib/strnlen_user.o
  CC      drivers/md/dm-ioctl.o
  AR      drivers/net/ethernet/synopsys/built-in.a
  AR      drivers/net/ethernet/pensando/built-in.a
  CC      drivers/md/dm-io.o
  GEN     xe_wa_oob.c xe_wa_oob.h
  GEN     xe_wa_oob.c xe_wa_oob.h
  CC [M]  drivers/gpu/drm/xe/xe_mmio.o
  AR      drivers/firmware/arm_ffa/built-in.a
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.o
  AR      drivers/firmware/arm_scmi/built-in.a
  AR      drivers/firmware/broadcom/built-in.a
  CC      drivers/md/dm-kcopyd.o
  AR      drivers/firmware/cirrus/built-in.a
  AR      drivers/firmware/meson/built-in.a
  CC      drivers/md/dm-sysfs.o
  AR      drivers/firmware/imx/built-in.a
  CC      drivers/md/dm-stats.o
  CC      drivers/firmware/efi/efi-bgrt.o
  CC      drivers/firmware/efi/libstub/efi-stub-helper.o
  CC      drivers/firmware/efi/efi.o
  CC [M]  drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.o
  CC      drivers/acpi/x86/apple.o
  CC      kernel/tsacct.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_context.o
  CC      drivers/firmware/efi/libstub/gop.o
  AR      drivers/mmc/host/built-in.a
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_csa.o
  CC      drivers/mmc/core/sdio_cis.o
  CC [M]  drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.o
  CC      lib/net_utils.o
  CC      drivers/mmc/core/sdio_io.o
  CC      net/sunrpc/sysfs.o
  CC [M]  drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_nl.o
  CC      kernel/tracepoint.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_context_sseu.o
  CC      drivers/firmware/efi/vars.o
  AR      drivers/crypto/stm32/built-in.a
  CC      drivers/clocksource/acpi_pm.o
  AR      drivers/crypto/xilinx/built-in.a
  CC      drivers/hid/usbhid/hid-core.o
  AR      drivers/crypto/hisilicon/built-in.a
  AR      drivers/crypto/intel/keembay/built-in.a
  AR      drivers/crypto/intel/ixp4xx/built-in.a
  AR      drivers/staging/media/built-in.a
  AR      drivers/crypto/intel/built-in.a
  AR      drivers/staging/built-in.a
  CC      net/sunrpc/svc_xprt.o
  CC      drivers/hid/hid-core.o
  CC      drivers/hid/usbhid/hiddev.o
  AR      drivers/crypto/starfive/built-in.a
  AR      drivers/crypto/built-in.a
  CC      drivers/clocksource/i8253.o
  CC      drivers/hid/hid-input.o
  CC      fs/btrfs/raid56.o
  CC      drivers/md/dm-rq.o
  CC      drivers/acpi/x86/utils.o
  CC [M]  drivers/net/ethernet/intel/ixgbe/ixgbe_sysfs.o
  CC      drivers/mmc/core/sdio_irq.o
  CC      net/sunrpc/xprtmultipath.o
  CC      drivers/firmware/efi/libstub/secureboot.o
  CC      fs/libfs.o
  AR      drivers/platform/x86/amd/built-in.a
  CC      drivers/platform/x86/intel/pmc/core.o
  CC [M]  drivers/platform/x86/intel/pmt/class.o
  CC [M]  drivers/gpu/drm/xe/xe_mocs.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/acr/lsfw.o
  CC      drivers/platform/x86/intel/turbo_max_3.o
  CC      drivers/firmware/efi/libstub/tpm.o
  CC      lib/sg_pool.o
  AR      drivers/platform/surface/built-in.a
  CC      drivers/firmware/efi/libstub/file.o
  LD [M]  net/ipv4/udp_tunnel.o
  CC      fs/fs-writeback.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm200.o
  LD [M]  drivers/net/ethernet/intel/e1000e/e1000e.o
  CC      drivers/platform/x86/p2sb.o
  CC      drivers/firmware/efi/reboot.o
  CC      lib/stackdepot.o
  CC      drivers/firmware/efi/libstub/mem.o
  CC      drivers/platform/x86/intel/pmc/core_ssram.o
  CC [M]  drivers/platform/x86/intel/vsec.o
  CC      lib/ucs2_string.o
  AR      drivers/clocksource/built-in.a
  CC      drivers/hid/hid-quirks.o
  CC      kernel/latencytop.o
  CC      drivers/acpi/x86/s2idle.o
  CC      drivers/mmc/core/slot-gpio.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_ras.o
  LD [M]  drivers/net/ethernet/realtek/r8169.o
  CC      net/sunrpc/stats.o
  CC      drivers/firmware/efi/libstub/random.o
  CC      drivers/md/dm-io-rewind.o
  CC      kernel/irq_work.o
  CC      drivers/firmware/efi/memattr.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm20b.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_engine_cs.o
  CC      drivers/firmware/efi/libstub/randomalloc.o
  CC      fs/pnode.o
  CC      net/sunrpc/sysctl.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.o
  CC      kernel/static_call.o
  CC      drivers/firmware/efi/tpm.o
  CC      lib/sbitmap.o
  CC      drivers/mailbox/mailbox.o
  CC [M]  drivers/gpu/drm/drm_mm.o
  CC [M]  drivers/platform/x86/intel/pmt/telemetry.o
  CC [M]  drivers/net/ethernet/intel/ixgbe/ixgbe_debugfs.o
  CC      drivers/mailbox/pcc.o
  CC      drivers/firmware/efi/libstub/pci.o
  CC [M]  drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.o
  CC      drivers/firmware/efi/memmap.o
  CC      drivers/acpi/debugfs.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_engine_heartbeat.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_engine_pm.o
  CC [M]  drivers/gpu/drm/xe/xe_module.o
  CC [M]  drivers/platform/x86/intel/pmt/crashlog.o
  CC      kernel/static_call_inline.o
  CC      fs/splice.o
  CC      drivers/mmc/core/regulator.o
  CC [M]  drivers/gpu/drm/xe/xe_pat.o
  CC [M]  drivers/gpu/drm/drm_mode_config.o
  CC      drivers/platform/x86/pmc_atom.o
  CC      lib/group_cpus.o
  CC [M]  drivers/platform/x86/intel/rst.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp102.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp108.o
  CC      drivers/firmware/efi/libstub/skip_spaces.o
  CC      drivers/md/dm-builtin.o
  CC [M]  drivers/md/dm-bufio.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/acr/gv100.o
  CC      fs/btrfs/uuid-tree.o
  CC      drivers/firmware/efi/esrt.o
  CC      fs/btrfs/props.o
  CC [M]  lib/asn1_decoder.o
  AR      drivers/hid/usbhid/built-in.a
  CC      kernel/user-return-notifier.o
  CC      drivers/firmware/efi/libstub/lib-cmdline.o
  CC      drivers/firmware/efi/efi-pstore.o
  CC      drivers/platform/x86/intel/pmc/spt.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.o
  CC      drivers/acpi/acpi_lpat.o
  LD [M]  drivers/platform/x86/intel/pmt/pmt_class.o
  CC      drivers/firmware/efi/libstub/lib-ctype.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp10b.o
  CC      drivers/acpi/acpi_lpit.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.o
  CC      drivers/firmware/efi/cper.o
  AR      drivers/mailbox/built-in.a
  CC [M]  drivers/platform/x86/wmi.o
  CC      drivers/firmware/efi/libstub/alignedmem.o
  CC      drivers/hid/hid-debug.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/acr/tu102.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.o
  CC      kernel/padata.o
  CC [M]  drivers/md/dm-bio-prison-v1.o
  CC      fs/sync.o
  LD [M]  drivers/platform/x86/intel/pmt/pmt_telemetry.o
  CC      drivers/firmware/efi/cper_cxl.o
  CC      drivers/devfreq/devfreq.o
  LD [M]  drivers/platform/x86/intel/pmt/pmt_crashlog.o
  LD [M]  drivers/platform/x86/intel/intel_vsec.o
  LD [M]  drivers/platform/x86/intel/intel-rst.o
  CC      drivers/powercap/powercap_sys.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_engine_user.o
  CC      kernel/jump_label.o
  CC      drivers/mmc/core/debugfs.o
  AR      drivers/perf/built-in.a
  CC      drivers/powercap/intel_rapl_common.o
  CC      fs/utimes.o
  CC [M]  drivers/devfreq/governor_simpleondemand.o
  CC [M]  drivers/gpu/drm/xe/xe_pci.o
  CC      drivers/platform/x86/intel/pmc/cnp.o
  GEN     lib/oid_registry_data.c
  CC [M]  lib/oid_registry.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/acr/ga100.o
  CC      drivers/hid/hidraw.o
  CC      drivers/acpi/prmt.o
  CC      drivers/firmware/efi/libstub/relocate.o
  CC      drivers/firmware/efi/runtime-wrappers.o
  CC [M]  drivers/gpu/drm/xe/xe_pcode.o
  CC      drivers/firmware/efi/dev-path-parser.o
  CC [M]  drivers/devfreq/governor_performance.o
  CC      drivers/platform/x86/intel/pmc/icl.o
  CC [M]  drivers/platform/x86/wmi-bmof.o
  AR      net/sunrpc/built-in.a
  AR      net/built-in.a
  CC [M]  drivers/platform/x86/mxm-wmi.o
  CC [M]  drivers/md/dm-bio-prison-v2.o
  CC      drivers/acpi/acpi_pcc.o
  CC      drivers/firmware/efi/apple-properties.o
  CC      drivers/platform/x86/intel/pmc/tgl.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_execlists_submission.o
  CC      drivers/firmware/efi/libstub/printk.o
  AR      lib/lib.a
  GEN     lib/crc32table.h
  CC      drivers/platform/x86/intel/pmc/adl.o
  CC      lib/crc32.o
  LD [M]  drivers/net/ethernet/intel/ixgbe/ixgbe.o
  CC      drivers/mmc/core/block.o
  CC      drivers/mmc/core/queue.o
  CC      drivers/acpi/ac.o
  CC      kernel/context_tracking.o
  CC      drivers/firmware/efi/libstub/vsprintf.o
  CC      drivers/platform/x86/intel/pmc/mtl.o
  CC      fs/btrfs/free-space-tree.o
  CC      drivers/hid/hid-generic.o
  CC      drivers/firmware/efi/earlycon.o
  CC      fs/d_path.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_ggtt.o
  CC [M]  drivers/md/dm-crypt.o
  CC      kernel/iomem.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/acr/ga102.o
  AR      drivers/net/ethernet/built-in.a
  CC      drivers/powercap/intel_rapl_msr.o
  CC      drivers/firmware/efi/cper-x86.o
  AR      drivers/net/built-in.a
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.o
  CC [M]  drivers/platform/x86/intel_ips.o
  CC      drivers/platform/x86/intel/pmc/pltdrv.o
  CC      fs/stack.o
  CC [M]  drivers/gpu/drm/drm_mode_object.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_umc.o
  CC      drivers/acpi/button.o
  CC      drivers/hid/hid-a4tech.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_ggtt_fencing.o
  CC      kernel/rseq.o
  CC      fs/btrfs/tree-checker.o
  CC      drivers/ras/ras.o
  CC [M]  drivers/gpu/drm/drm_modes.o
  CC      drivers/ras/debugfs.o
  AR      drivers/firmware/psci/built-in.a
  CC      fs/btrfs/space-info.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_gt.o
  AR      drivers/firmware/smccc/built-in.a
  CC [M]  drivers/gpu/drm/xe/xe_pm.o
  AR      drivers/firmware/tegra/built-in.a
  CC [M]  drivers/gpu/drm/xe/xe_preempt_fence.o
  CC      drivers/acpi/fan_core.o
  CC      fs/btrfs/block-rsv.o
  GZIP    kernel/config_data.gz
  CC      drivers/firmware/efi/libstub/x86-stub.o
  CC [M]  drivers/gpu/drm/xe/xe_pt.o
  AR      drivers/firmware/xilinx/built-in.a
  CC      kernel/configs.o
  AR      lib/built-in.a
  CC      fs/btrfs/delalloc-space.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.o
  CC [M]  drivers/gpu/drm/drm_modeset_lock.o
  AR      drivers/hwtracing/intel_th/built-in.a
  CC      drivers/acpi/fan_attr.o
  CC      drivers/android/binderfs.o
  CC [M]  drivers/gpu/drm/drm_plane.o
  STUBCPY drivers/firmware/efi/libstub/alignedmem.stub.o
  STUBCPY drivers/firmware/efi/libstub/efi-stub-helper.stub.o
  STUBCPY drivers/firmware/efi/libstub/file.stub.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.o
  AR      drivers/nvmem/layouts/built-in.a
  CC      drivers/nvmem/core.o
  AR      drivers/platform/x86/intel/pmc/built-in.a
  AR      drivers/platform/x86/intel/built-in.a
  CC [M]  drivers/gpu/drm/drm_prime.o
  CC [M]  drivers/mtd/chips/chipreg.o
  CC [M]  drivers/uio/uio.o
  AR      drivers/devfreq/built-in.a
  AR      drivers/platform/x86/built-in.a
  STUBCPY drivers/firmware/efi/libstub/gop.stub.o
  STUBCPY drivers/firmware/efi/libstub/lib-cmdline.stub.o
  STUBCPY drivers/firmware/efi/libstub/lib-ctype.stub.o
  CC      drivers/android/binder.o
  CC      drivers/acpi/processor_driver.o
  CC [M]  drivers/gpu/drm/drm_print.o
  CC      fs/fs_struct.o
  CC [M]  drivers/vfio/pci/vfio_pci_core.o
  AR      drivers/powercap/built-in.a
  STUBCPY drivers/firmware/efi/libstub/mem.stub.o
  CC      drivers/hid/hid-apple.o
  CC [M]  drivers/md/dm-thin.o
  CC      drivers/hid/hid-belkin.o
  CC [M]  drivers/pps/pps.o
  CC [M]  drivers/bluetooth/btusb.o
  CC [M]  drivers/dca/dca-core.o
  CC [M]  drivers/ssb/main.o
  CC [M]  drivers/vhost/net.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.o
  CC [M]  drivers/ssb/scan.o
  CC [M]  drivers/vhost/vhost.o
  AR      kernel/built-in.a
  AR      drivers/platform/built-in.a
  CC [M]  drivers/pps/kapi.o
  CC      drivers/hid/hid-cherry.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bar/g84.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.o
  AR      drivers/ras/built-in.a
  CC [M]  drivers/vfio/vfio_main.o
  CC [M]  drivers/dca/dca-sysfs.o
  STUBCPY drivers/firmware/efi/libstub/pci.stub.o
  CC [M]  drivers/mtd/mtdcore.o
  STUBCPY drivers/firmware/efi/libstub/printk.stub.o
  STUBCPY drivers/firmware/efi/libstub/random.stub.o
  STUBCPY drivers/firmware/efi/libstub/randomalloc.stub.o
  STUBCPY drivers/firmware/efi/libstub/relocate.stub.o
  STUBCPY drivers/firmware/efi/libstub/secureboot.stub.o
  CC      fs/btrfs/block-group.o
  CC      drivers/acpi/processor_thermal.o
  STUBCPY drivers/firmware/efi/libstub/skip_spaces.stub.o
  STUBCPY drivers/firmware/efi/libstub/tpm.stub.o
  STUBCPY drivers/firmware/efi/libstub/vsprintf.stub.o
  CC      fs/btrfs/discard.o
  STUBCPY drivers/firmware/efi/libstub/x86-stub.stub.o
  AR      drivers/firmware/efi/libstub/lib.a
  CC      fs/btrfs/reflink.o
  AR      drivers/firmware/efi/built-in.a
  CC      drivers/firmware/dmi_scan.o
  CC      drivers/android/binder_alloc.o
  CC [M]  drivers/gpu/drm/drm_property.o
  CC [M]  drivers/gpu/drm/drm_syncobj.o
  CC [M]  drivers/gpu/drm/drm_sysfs.o
  CC      drivers/acpi/processor_idle.o
  CC [M]  drivers/gpu/drm/xe/xe_pt_walk.o
  CC [M]  drivers/vfio/group.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.o
  CC [M]  drivers/ssb/sprom.o
  CC      drivers/firmware/dmi-sysfs.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_gt_clock_utils.o
  CC      drivers/firmware/dmi-id.o
  CC [M]  drivers/bluetooth/btintel.o
  CC [M]  drivers/vfio/iova_bitmap.o
  CC      drivers/acpi/processor_throttling.o
  CC [M]  drivers/pps/sysfs.o
  CC [M]  drivers/mtd/mtdsuper.o
  CC [M]  drivers/gpu/drm/drm_trace_points.o
  AR      drivers/nvmem/built-in.a
  CC [M]  drivers/vfio/pci/vfio_pci_intrs.o
  CC [M]  drivers/gpu/drm/xe/xe_query.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_rap.o
  CC [M]  drivers/gpu/drm/xe/xe_range_fence.o
  AR      drivers/mmc/core/built-in.a
  AR      drivers/mmc/built-in.a
  CC      drivers/hid/hid-chicony.o
  CC [M]  drivers/vfio/pci/vfio_pci_rdwr.o
  CC [M]  drivers/mtd/mtdconcat.o
  CC      fs/btrfs/subpage.o
  LD [M]  drivers/dca/dca.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_gt_debugfs.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bar/gk20a.o
  CC [M]  drivers/gpu/drm/drm_vblank.o
  CC [M]  drivers/vfio/container.o
  CC      fs/btrfs/tree-mod-log.o
  CC [M]  drivers/ssb/pci.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.o
  LD [M]  drivers/pps/pps_core.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.o
  CC      drivers/acpi/processor_perflib.o
  CC      fs/btrfs/extent-io-tree.o
  CC [M]  drivers/vfio/virqfd.o
  CC [M]  drivers/ssb/pcihost_wrapper.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_gt_engines_debugfs.o
  CC      drivers/firmware/memmap.o
  CC [M]  drivers/gpu/drm/xe/xe_reg_sr.o
  CC [M]  drivers/vfio/vfio_iommu_type1.o
  CC      fs/btrfs/fs.o
  CC      drivers/hid/hid-cypress.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bar/gm107.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_gt_irq.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.o
  CC [M]  drivers/mtd/mtdpart.o
  CC [M]  drivers/gpu/drm/drm_vblank_work.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_mca.o
  CC      fs/btrfs/messages.o
  CC      drivers/hid/hid-ezkey.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bar/gm20b.o
  CC      drivers/acpi/container.o
  CC [M]  drivers/vfio/pci/vfio_pci_config.o
  CC [M]  drivers/gpu/drm/xe/xe_reg_whitelist.o
  CC      drivers/hid/hid-kensington.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_gt_mcr.o
  CC [M]  drivers/vhost/iotlb.o
  CC [M]  drivers/bluetooth/btbcm.o
  CC [M]  drivers/gpu/drm/drm_vma_manager.o
  CC [M]  drivers/gpu/drm/xe/xe_rtp.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.o
  CC      drivers/acpi/thermal.o
  CC [M]  drivers/gpu/drm/xe/xe_ring_ops.o
  CC [M]  drivers/gpu/drm/drm_gpuva_mgr.o
  CC [M]  drivers/mtd/mtdchar.o
  CC      fs/statfs.o
  CC [M]  drivers/ssb/driver_chipcommon.o
  CC [M]  drivers/bluetooth/btrtl.o
  AR      drivers/firmware/built-in.a
  CC      fs/btrfs/bio.o
  CC [M]  drivers/gpu/drm/drm_writeback.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_gt_pm.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_lsdma.o
  CC [M]  drivers/ssb/driver_chipcommon_pmu.o
  CC      drivers/hid/hid-lg.o
  CC [M]  drivers/md/dm-thin-metadata.o
  CC      drivers/acpi/acpi_memhotplug.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.o
  CC [M]  drivers/gpu/drm/lib/drm_random.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_gt_pm_irq.o
  LD [M]  drivers/vhost/vhost_net.o
  CC [M]  drivers/vfio/pci/vfio_pci.o
  CC      drivers/hid/hid-lg-g15.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_gt_requests.o
  CC [M]  drivers/ssb/driver_pcicore.o
  CC      fs/btrfs/lru_cache.o
  CC      drivers/acpi/ioapic.o
  LD [M]  drivers/vhost/vhost_iotlb.o
  CC      drivers/acpi/battery.o
  CC [M]  drivers/gpu/drm/drm_ioc32.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bar/tu102.o
  CC [M]  drivers/gpu/drm/xe/xe_sa.o
  CC [M]  drivers/gpu/drm/drm_panel.o
  CC [M]  drivers/gpu/drm/drm_pci.o
  CC [M]  drivers/gpu/drm/drm_debugfs.o
  CC      fs/fs_pin.o
  LD [M]  drivers/vfio/vfio.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_gt_sysfs.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/base.o
  CC      fs/btrfs/acl.o
  CC [M]  drivers/gpu/drm/xe/xe_sched_job.o
  CC [M]  drivers/gpu/drm/xe/xe_step.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.o
  CC      drivers/hid/hid-microsoft.o
  CC [M]  drivers/gpu/drm/drm_debugfs_crc.o
  CC      drivers/acpi/hed.o
  CC      fs/nsfs.o
  LD [M]  drivers/md/dm-bio-prison.o
  AR      drivers/md/built-in.a
  CC [M]  drivers/gpu/drm/i915/gt/intel_gtt.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.o
  CC [M]  drivers/gpu/drm/xe/xe_sync.o
  CC      drivers/hid/hid-monterey.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_llc.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_lrc.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.o
  CC [M]  drivers/gpu/drm/drm_edid_load.o
  CC      drivers/acpi/bgrt.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_migrate.o
  CC [M]  drivers/gpu/drm/drm_panel_orientation_quirks.o
  LD [M]  drivers/vfio/pci/vfio-pci.o
  LD [M]  drivers/vfio/pci/vfio-pci-core.o
  CC [M]  drivers/gpu/drm/drm_exec.o
  LD [M]  drivers/mtd/mtd.o
  CC      drivers/acpi/cppc_acpi.o
  LD [M]  drivers/ssb/ssb.o
  CC [M]  drivers/gpu/drm/drm_buddy.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_mocs.o
  CC [M]  drivers/gpu/drm/xe/xe_tile.o
  CC      fs/fs_types.o
  CC [M]  drivers/gpu/drm/drm_gem_shmem_helper.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/bit.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/boost.o
  CC [M]  drivers/gpu/drm/xe/xe_tile_sysfs.o
  CC      drivers/acpi/spcr.o
  CC [M]  drivers/gpu/drm/drm_suballoc.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/cik.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_ppgtt.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_rc6.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_region_lmem.o
  CC      fs/fs_context.o
  CC [M]  drivers/gpu/drm/xe/xe_trace.o
  CC      drivers/acpi/acpi_pad.o
  CC [M]  drivers/gpu/drm/xe/xe_ttm_sys_mgr.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/conn.o
  LD [M]  drivers/md/dm-thin-pool.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/cik_ih.o
  CC [M]  drivers/acpi/acpi_video.o
  CC [M]  drivers/acpi/video_detect.o
  CC      fs/fs_parser.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/cstep.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.o
  CC [M]  drivers/gpu/drm/drm_gem_ttm_helper.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/dce_v8_0.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/gfx_v7_0.o
  AR      drivers/hid/built-in.a
  CC [M]  drivers/gpu/drm/drm_atomic_helper.o
  CC [M]  drivers/gpu/drm/xe/xe_ttm_stolen_mgr.o
  CC      fs/fsopen.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_renderstate.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/cik_sdma.o
  CC [M]  drivers/gpu/drm/xe/xe_ttm_vram_mgr.o
  AR      fs/btrfs/built-in.a
  CC      fs/init.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/uvd_v4_2.o
  CC [M]  drivers/gpu/drm/drm_atomic_state_helper.o
  CC [M]  drivers/gpu/drm/xe/xe_tuning.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/vce_v2_0.o
  CC [M]  drivers/gpu/drm/xe/xe_uc.o
  CC [M]  drivers/gpu/drm/xe/xe_uc_debugfs.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_reset.o
  CC [M]  drivers/gpu/drm/xe/xe_uc_fw.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_ring.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_ring_submission.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/disp.o
  CC [M]  drivers/gpu/drm/drm_bridge_connector.o
  CC [M]  drivers/gpu/drm/drm_crtc_helper.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_rps.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/si.o
  CC      fs/kernel_read_file.o
  CC [M]  drivers/gpu/drm/drm_damage_helper.o
  CC [M]  drivers/gpu/drm/drm_encoder_slave.o
  CC [M]  drivers/gpu/drm/xe/xe_vm.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/extdev.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_sa_media.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_sseu.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/gmc_v6_0.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/fan.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/gpio.o
  CC [M]  drivers/gpu/drm/drm_flip_work.o
  CC [M]  drivers/gpu/drm/xe/xe_vm_madvise.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/gfx_v6_0.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/si_ih.o
  CC      fs/mnt_idmapping.o
  AR      drivers/android/built-in.a
  CC [M]  drivers/gpu/drm/i915/gt/intel_sseu_debugfs.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/i2c.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_timeline.o
  CC [M]  drivers/gpu/drm/xe/xe_wait_user_fence.o
  CC [M]  drivers/gpu/drm/xe/xe_wa.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_tlb.o
  CC [M]  drivers/gpu/drm/xe/xe_wopcm.o
  CC [M]  drivers/gpu/drm/drm_format_helper.o
  CC [M]  drivers/gpu/drm/xe/xe_display.o
  CC [M]  drivers/gpu/drm/drm_gem_atomic_helper.o
  CC      fs/remap_range.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/si_dma.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/iccsense.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_wopcm.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/dce_v6_0.o
  CC [M]  drivers/gpu/drm/drm_gem_framebuffer_helper.o
  AR      drivers/acpi/built-in.a
  CC [M]  drivers/gpu/drm/drm_kms_helper_common.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_workarounds.o
  LD [M]  drivers/acpi/video.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/uvd_v3_1.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/vi.o
  CC [M]  drivers/gpu/drm/xe/display/xe_fb_pin.o
  CC [M]  drivers/gpu/drm/drm_modeset_helper.o
  CC [M]  drivers/gpu/drm/drm_plane_helper.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/image.o
  CC [M]  drivers/gpu/drm/xe/display/xe_hdcp_gsc.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/mxm.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/mxgpu_vi.o
  CC [M]  drivers/gpu/drm/i915/gt/shmem_utils.o
  CC [M]  drivers/gpu/drm/i915/gt/sysfs_engines.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/npde.o
  CC [M]  drivers/gpu/drm/drm_probe_helper.o
  CC [M]  drivers/gpu/drm/xe/display/xe_plane_initial.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/pcir.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_ggtt_gmch.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/nbio_v6_1.o
  CC [M]  drivers/gpu/drm/drm_rect.o
  CC [M]  drivers/gpu/drm/xe/display/xe_display_rps.o
  CC [M]  drivers/gpu/drm/i915/gt/gen6_renderstate.o
  CC      fs/buffer.o
  CC [M]  drivers/gpu/drm/xe/display/ext/i915_irq.o
  CC [M]  drivers/gpu/drm/xe/display/ext/i915_utils.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/soc15.o
  CC [M]  drivers/gpu/drm/drm_self_refresh_helper.o
  CC [M]  drivers/gpu/drm/drm_simple_kms_helper.o
  CC [M]  drivers/gpu/drm/i915/gt/gen7_renderstate.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/emu_soc.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.o
  CC [M]  drivers/gpu/drm/xe/i915-soc/intel_dram.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/mxgpu_ai.o
  CC [M]  drivers/gpu/drm/bridge/panel.o
  CC [M]  drivers/gpu/drm/i915/gt/gen8_renderstate.o
  CC [M]  drivers/gpu/drm/drm_fbdev_generic.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.o
  CC [M]  drivers/gpu/drm/drm_fb_helper.o
  CC [M]  drivers/gpu/drm/i915/gt/gen9_renderstate.o
  CC [M]  drivers/gpu/drm/xe/i915-soc/intel_pch.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_busy.o
  LD [M]  drivers/gpu/drm/drm.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_clflush.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/pmu.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/power_budget.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_context.o
  LD [M]  drivers/gpu/drm/drm_shmem_helper.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/ramcfg.o
  LD [M]  drivers/gpu/drm/drm_suballoc_helper.o
  LD [M]  drivers/gpu/drm/drm_ttm_helper.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_create.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_dmabuf.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/nbio_v7_0.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_domain.o
  CC [M]  drivers/gpu/drm/xe/i915-display/icl_dsi.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_execbuffer.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/vega10_reg_init.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_internal.o
  AR      drivers/gpu/drm/built-in.a
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_object.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/vega20_reg_init.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_lmem.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_atomic.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/nbio_v7_4.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_mman.o
  CC      fs/mpage.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/rammap.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_pages.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/nbio_v2_3.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_phys.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_pm.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_region.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/nv.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/arct_reg_init.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/mxgpu_nv.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/nbio_v7_2.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_atomic_plane.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/hdp_v4_0.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowacpi.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowof.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowpci.o
  CC      fs/proc_namespace.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowramin.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_shmem.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_audio.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_shrinker.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_stolen.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/hdp_v5_0.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/aldebaran_reg_init.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/aldebaran.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/soc21.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_throttle.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_tiling.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowrom.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/sienna_cichlid.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_ttm.o
  LD [M]  drivers/gpu/drm/drm_kms_helper.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_backlight.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_ttm_move.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.o
  CC      fs/direct-io.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_userptr.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.o
  CC      fs/eventpoll.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/therm.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/vmap.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_wait.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gemfs.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/nbio_v4_3.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/hdp_v6_0.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/vpstate.o
  CC [M]  drivers/gpu/drm/i915/i915_active.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/nbio_v7_7.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/xpio.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/hdp_v5_2.o
  CC [M]  drivers/gpu/drm/i915/i915_cmd_parser.o
  CC [M]  drivers/gpu/drm/i915/i915_deps.o
  CC [M]  drivers/gpu/drm/i915/i915_gem_evict.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/lsdma_v6_0.o
  CC      fs/anon_inodes.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0203.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/nbio_v7_9.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/df_v1_7.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/df_v3_6.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0205.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_bios.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_bw.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/df_v4_3.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/gmc_v7_0.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0209.o
  CC [M]  drivers/gpu/drm/i915/i915_gem_gtt.o
  CC [M]  drivers/gpu/drm/i915/i915_gem_ww.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_cdclk.o
  CC [M]  drivers/gpu/drm/i915/i915_gem.o
  CC [M]  drivers/gpu/drm/i915/i915_query.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/P0260.o
  CC      fs/signalfd.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/gmc_v8_0.o
  CC [M]  drivers/gpu/drm/i915/i915_request.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.o
  CC [M]  drivers/gpu/drm/i915/i915_scheduler.o
  CC [M]  drivers/gpu/drm/i915/i915_trace_points.o
  CC [M]  drivers/gpu/drm/i915/i915_ttm_buddy_manager.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bus/base.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.o
  CC      fs/timerfd.o
  CC [M]  drivers/gpu/drm/i915/i915_vma.o
  CC [M]  drivers/gpu/drm/i915/i915_vma_resource.o
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.o
  CC      fs/eventfd.o
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_color.o
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.o
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_debugfs.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.o
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_combo_phy.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/gmc_v10_0.o
  CC      fs/userfaultfd.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.o
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_guc.o
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_guc_ads.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bus/g94.o
  CC      fs/aio.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.o
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_guc_capture.o
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_guc_ct.o
  CC      fs/locks.o
  CC      fs/binfmt_script.o
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.o
  CC      fs/binfmt_elf.o
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_guc_fw.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bus/gf100.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.o
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.o
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_guc_log.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.o
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_connector.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.o
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_guc_rc.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.o
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.o
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_guc_submission.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/gmc_v11_0.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.o
  CC      fs/compat_binfmt_elf.o
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_huc.o
  CC      fs/mbcache.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/clk/g84.o
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_huc_debugfs.o
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_huc_fw.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_crtc.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.o
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_uc.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_crtc_state_dump.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.o
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.o
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_uc_fw.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_gsc.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.o
  CC [M]  drivers/gpu/drm/i915/i915_hwmon.o
  CC [M]  drivers/gpu/drm/i915/display/hsw_ips.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_cursor.o
  CC [M]  drivers/gpu/drm/i915/display/intel_atomic.o
  CC [M]  drivers/gpu/drm/i915/display/intel_atomic_plane.o
  CC      fs/posix_acl.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/umc_v6_0.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_cx0_phy.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/umc_v6_1.o
  CC [M]  drivers/gpu/drm/i915/display/intel_audio.o
  CC [M]  drivers/gpu/drm/i915/display/intel_bios.o
  CC      fs/coredump.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/umc_v6_7.o
  CC [M]  drivers/gpu/drm/i915/display/intel_bw.o
  CC      fs/drop_caches.o
  CC      fs/sysctls.o
  CC [M]  drivers/gpu/drm/i915/display/intel_cdclk.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/umc_v8_7.o
  CC [M]  drivers/gpu/drm/i915/display/intel_color.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/umc_v8_10.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_ddi.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_irq.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.o
  CC [M]  drivers/gpu/drm/i915/display/intel_combo_phy.o
  CC      fs/fhandle.o
  CC [M]  drivers/gpu/drm/i915/display/intel_connector.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllgt215.o
  CC [M]  drivers/gpu/drm/i915/display/intel_crtc.o
  CC [M]  drivers/gpu/drm/i915/display/intel_crtc_state_dump.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_ddi_buf_trans.o
  CC [M]  drivers/gpu/drm/i915/display/intel_cursor.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_ih.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/devinit/base.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.o
  CC [M]  drivers/gpu/drm/i915/display/intel_display.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_display.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/iceland_ih.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/tonga_ih.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv05.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_display_debugfs.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/cz_ih.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv10.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv1a.o
  CC [M]  drivers/gpu/drm/i915/display/intel_display_driver.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/vega10_ih.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/vega20_ih.o
  CC [M]  drivers/gpu/drm/i915/display/intel_display_irq.o
  CC [M]  drivers/gpu/drm/i915/display/intel_display_power.o
  CC [M]  drivers/gpu/drm/i915/display/intel_display_power_map.o
  CC [M]  drivers/gpu/drm/i915/display/intel_display_power_well.o
  CC [M]  drivers/gpu/drm/i915/display/intel_display_reset.o
  CC [M]  drivers/gpu/drm/i915/display/intel_display_rps.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/navi10_ih.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/ih_v6_0.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/ih_v6_1.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv20.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g84.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_psp.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/psp_v3_1.o
  CC [M]  drivers/gpu/drm/i915/display/intel_display_wa.o
  AR      fs/built-in.a
  CC [M]  drivers/gpu/drm/i915/display/intel_dmc.o
  CC [M]  drivers/gpu/drm/i915/display/intel_dpio_phy.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g98.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/devinit/mcp89.o
  CC [M]  drivers/gpu/drm/i915/display/intel_dpll.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/psp_v10_0.o
  CC [M]  drivers/gpu/drm/i915/display/intel_dpll_mgr.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm200.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_display_device.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/psp_v11_0.o
  CC [M]  drivers/gpu/drm/i915/display/intel_dpt.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/psp_v11_0_8.o
  CC [M]  drivers/gpu/drm/i915/display/intel_drrs.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/psp_v12_0.o
  CC [M]  drivers/gpu/drm/i915/display/intel_dsb.o
  CC [M]  drivers/gpu/drm/i915/display/intel_fb.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gv100.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/psp_v13_0.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/devinit/tu102.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ga100.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_display_driver.o
  CC [M]  drivers/gpu/drm/i915/display/intel_fb_pin.o
  CC [M]  drivers/gpu/drm/i915/display/intel_fbc.o
  CC [M]  drivers/gpu/drm/i915/display/intel_fdi.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fault/base.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fault/user.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/dce_v10_0.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/dce_v11_0.o
  CC [M]  drivers/gpu/drm/i915/display/intel_fifo_underrun.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fault/gp100.o
  CC [M]  drivers/gpu/drm/i915/display/intel_frontbuffer.o
  CC [M]  drivers/gpu/drm/i915/display/intel_global_state.o
  CC [M]  drivers/gpu/drm/i915/display/intel_hdcp.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fault/gp10b.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_display_irq.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fault/tu102.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_display_power.o
  CC [M]  drivers/gpu/drm/i915/display/intel_hdcp_gsc.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.o
  CC [M]  drivers/gpu/drm/i915/display/intel_hotplug.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.o
  CC [M]  drivers/gpu/drm/i915/display/intel_hotplug_irq.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.o
  CC [M]  drivers/gpu/drm/i915/display/intel_hti.o
  CC [M]  drivers/gpu/drm/i915/display/intel_load_detect.o
  CC [M]  drivers/gpu/drm/i915/display/intel_lpe_audio.o
  CC [M]  drivers/gpu/drm/i915/display/intel_modeset_lock.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/gfx_v9_4.o
  CC [M]  drivers/gpu/drm/i915/display/intel_modeset_verify.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.o
  CC [M]  drivers/gpu/drm/i915/display/intel_modeset_setup.o
  CC [M]  drivers/gpu/drm/i915/display/intel_overlay.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_display_power_map.o
  CC [M]  drivers/gpu/drm/i915/display/intel_pch_display.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.o
  CC [M]  drivers/gpu/drm/i915/display/intel_pch_refclk.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/gfx_v10_0.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.o
  CC [M]  drivers/gpu/drm/i915/display/intel_plane_initial.o
  CC [M]  drivers/gpu/drm/i915/display/intel_pmdemand.o
  CC [M]  drivers/gpu/drm/i915/display/intel_psr.o
  CC [M]  drivers/gpu/drm/i915/display/intel_quirks.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.o
  CC [M]  drivers/gpu/drm/i915/display/intel_sprite.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/imu_v11_0.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.o
  CC [M]  drivers/gpu/drm/i915/display/intel_sprite_uapi.o
  CC [M]  drivers/gpu/drm/i915/display/intel_tc.o
  CC [M]  drivers/gpu/drm/i915/display/intel_vblank.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/gfx_v11_0.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/g84.o
  CC [M]  drivers/gpu/drm/i915/display/intel_vga.o
  CC [M]  drivers/gpu/drm/i915/display/intel_wm.o
  CC [M]  drivers/gpu/drm/i915/display/i9xx_plane.o
  CC [M]  drivers/gpu/drm/i915/display/i9xx_wm.o
  CC [M]  drivers/gpu/drm/i915/display/skl_scaler.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_display_power_well.o
  CC [M]  drivers/gpu/drm/i915/display/skl_universal_plane.o
  CC [M]  drivers/gpu/drm/i915/display/skl_watermark.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/gt215.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_display_trace.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp77.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp89.o
  CC [M]  drivers/gpu/drm/i915/display/intel_acpi.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/gfx_v11_0_3.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/imu_v11_0_3.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_display_wa.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_dkl_phy.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf108.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk104.o
  CC [M]  drivers/gpu/drm/i915/display/intel_opregion.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk110.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_dmc.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk20a.o
  CC [M]  drivers/gpu/drm/i915/display/intel_fbdev.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm107.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/sdma_v2_4.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm200.o
  CC [M]  drivers/gpu/drm/i915/display/dvo_ch7017.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm20b.o
  CC [M]  drivers/gpu/drm/i915/display/dvo_ch7xxx.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp100.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/sdma_v3_0.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp102.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp10b.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/gv100.o
  CC [M]  drivers/gpu/drm/i915/display/dvo_ivch.o
  CC [M]  drivers/gpu/drm/i915/display/dvo_ns2501.o
  CC [M]  drivers/gpu/drm/i915/display/dvo_sil164.o
  CC [M]  drivers/gpu/drm/i915/display/dvo_tfp410.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_dp.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_dp_aux.o
  CC [M]  drivers/gpu/drm/i915/display/g4x_dp.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/tu102.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/ga100.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/ga102.o
  CC [M]  drivers/gpu/drm/i915/display/g4x_hdmi.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/sdma_v4_4.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv04.o
  CC [M]  drivers/gpu/drm/i915/display/icl_dsi.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv10.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv20.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv41.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv44.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv49.o
  CC [M]  drivers/gpu/drm/i915/display/intel_backlight.o
  CC [M]  drivers/gpu/drm/i915/display/intel_crt.o
  CC [M]  drivers/gpu/drm/i915/display/intel_cx0_phy.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_dp_aux_backlight.o
  CC [M]  drivers/gpu/drm/i915/display/intel_ddi.o
  CC [M]  drivers/gpu/drm/i915/display/intel_ddi_buf_trans.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv4e.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.o
  CC [M]  drivers/gpu/drm/i915/display/intel_display_device.o
  CC [M]  drivers/gpu/drm/i915/display/intel_display_trace.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_dp_hdcp.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf108.o
  CC [M]  drivers/gpu/drm/i915/display/intel_dkl_phy.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm107.o
  CC [M]  drivers/gpu/drm/i915/display/intel_dp.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/sdma_v5_0.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm200.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgp100.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/sdma_v5_2.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgp102.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr2.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_dp_link_training.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr3.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/sdma_v6_0.o
  CC [M]  drivers/gpu/drm/i915/display/intel_dp_aux.o
  CC [M]  drivers/gpu/drm/i915/display/intel_dp_aux_backlight.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_mes.o
  CC [M]  drivers/gpu/drm/i915/display/intel_dp_hdcp.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr5.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_dp_mst.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fuse/base.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_dpll.o
  CC [M]  drivers/gpu/drm/i915/display/intel_dp_link_training.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fuse/nv50.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gf100.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gm107.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_dpll_mgr.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/mes_v10_1.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv10.o
  CC [M]  drivers/gpu/drm/i915/display/intel_dp_mst.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.o
  CC [M]  drivers/gpu/drm/i915/display/intel_dsi.o
  CC [M]  drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.o
  CC [M]  drivers/gpu/drm/i915/display/intel_dsi_vbt.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/gpio/g94.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gf119.o
  CC [M]  drivers/gpu/drm/i915/display/intel_dvo.o
  CC [M]  drivers/gpu/drm/i915/display/intel_gmbus.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_dpt.o
  CC [M]  drivers/gpu/drm/i915/display/intel_hdmi.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/mes_v11_0.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gk104.o
  CC [M]  drivers/gpu/drm/i915/display/intel_lspcon.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/gpio/ga102.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/gsp/base.o
  CC [M]  drivers/gpu/drm/i915/display/intel_lvds.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gv100.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/gsp/ga102.o
  CC [M]  drivers/gpu/drm/i915/display/intel_panel.o
  CC [M]  drivers/gpu/drm/i915/display/intel_pps.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv04.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv4e.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv50.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/g94.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf117.o
  CC [M]  drivers/gpu/drm/i915/display/intel_qp_tables.o
  CC [M]  drivers/gpu/drm/i915/display/intel_sdvo.o
  CC [M]  drivers/gpu/drm/i915/display/intel_snps_phy.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/uvd_v5_0.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/uvd_v6_0.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_drrs.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_dsb.o
  CC [M]  drivers/gpu/drm/i915/display/intel_tv.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_dsi.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf119.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/uvd_v7_0.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_dsi_dcs_backlight.o
  CC [M]  drivers/gpu/drm/i915/display/intel_vdsc.o
  CC [M]  drivers/gpu/drm/i915/display/intel_vrr.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk104.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk110.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_dsi_vbt.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gm200.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/pad.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padnv04.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_vce.o
  CC [M]  drivers/gpu/drm/i915/display/vlv_dsi.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/vce_v3_0.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padnv4e.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padnv50.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padg94.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padgf119.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/vce_v4_0.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padgm200.o
  CC [M]  drivers/gpu/drm/i915/display/vlv_dsi_pll.o
  CC [M]  drivers/gpu/drm/i915/i915_perf.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/bus.o
  CC [M]  drivers/gpu/drm/i915/pxp/intel_pxp.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv04.o
  CC [M]  drivers/gpu/drm/i915/pxp/intel_pxp_tee.o
  CC [M]  drivers/gpu/drm/i915/pxp/intel_pxp_huc.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_fb.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_fbc.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv4e.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/vcn_sw_ring.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv50.o
  CC [M]  drivers/gpu/drm/i915/pxp/intel_pxp_cmd.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busgf119.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_fdi.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_fifo_underrun.o
  CC [M]  drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_frontbuffer.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/bit.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/aux.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_global_state.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/vcn_v1_0.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgf119.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/base.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/vcn_v2_0.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/gf100.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_gmbus.o
  CC [M]  drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_hdcp.o
  CC [M]  drivers/gpu/drm/i915/pxp/intel_pxp_irq.o
  CC [M]  drivers/gpu/drm/i915/pxp/intel_pxp_pm.o
  CC [M]  drivers/gpu/drm/i915/pxp/intel_pxp_session.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/vcn_v2_5.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/vcn_v3_0.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/vcn_v4_0.o
  CC [M]  drivers/gpu/drm/i915/i915_gpu_error.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.o
  CC [M]  drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.o
  CC [M]  drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.o
  CC [M]  drivers/gpu/drm/i915/selftests/intel_scheduler_helpers.o
  CC [M]  drivers/gpu/drm/i915/selftests/i915_random.o
  CC [M]  drivers/gpu/drm/i915/selftests/i915_selftest.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_hdmi.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.o
  CC [M]  drivers/gpu/drm/i915/selftests/igt_atomic.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/ltc/base.o
  CC [M]  drivers/gpu/drm/i915/selftests/igt_flush_test.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.o
  CC [M]  drivers/gpu/drm/i915/selftests/igt_live_test.o
  CC [M]  drivers/gpu/drm/i915/selftests/igt_mmap.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_hotplug.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gk104.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm200.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_hotplug_irq.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp100.o
  CC [M]  drivers/gpu/drm/i915/selftests/igt_reset.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_hti.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp102.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_lspcon.o
  CC [M]  drivers/gpu/drm/i915/selftests/igt_spinner.o
  CC [M]  drivers/gpu/drm/i915/selftests/librapl.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.o
  CC [M]  drivers/gpu/drm/i915/i915_vgpu.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/ltc/ga102.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.o
  HDRTEST drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h
  HDRTEST drivers/gpu/drm/i915/display/intel_crtc_state_dump.h
  HDRTEST drivers/gpu/drm/i915/display/hsw_ips.h
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_modeset_lock.o
  HDRTEST drivers/gpu/drm/i915/display/g4x_hdmi.h
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_modeset_setup.o
  HDRTEST drivers/gpu/drm/i915/display/intel_hdcp_regs.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.o
  HDRTEST drivers/gpu/drm/i915/display/intel_overlay.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv11.o
  HDRTEST drivers/gpu/drm/i915/display/intel_display.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.o
  HDRTEST drivers/gpu/drm/i915/display/skl_watermark_regs.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv17.o
  HDRTEST drivers/gpu/drm/i915/display/intel_dmc.h
  HDRTEST drivers/gpu/drm/i915/display/intel_vga.h
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_modeset_verify.o
  HDRTEST drivers/gpu/drm/i915/display/intel_audio.h
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_panel.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv44.o
  HDRTEST drivers/gpu/drm/i915/display/intel_lvds.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mc/g84.o
  HDRTEST drivers/gpu/drm/i915/display/intel_modeset_setup.h
  HDRTEST drivers/gpu/drm/i915/display/intel_cdclk.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mc/g98.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mc/gt215.o
  HDRTEST drivers/gpu/drm/i915/display/intel_display_limits.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_pipe_crc.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_pmdemand.o
  HDRTEST drivers/gpu/drm/i915/display/intel_hotplug.h
  HDRTEST drivers/gpu/drm/i915/display/intel_dkl_phy.h
  HDRTEST drivers/gpu/drm/i915/display/intel_atomic.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk104.o
  HDRTEST drivers/gpu/drm/i915/display/intel_display_driver.h
  HDRTEST drivers/gpu/drm/i915/display/intel_dpll.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.o
  HDRTEST drivers/gpu/drm/i915/display/vlv_dsi_pll_regs.h
  HDRTEST drivers/gpu/drm/i915/display/intel_dp_mst.h
  HDRTEST drivers/gpu/drm/i915/display/intel_fdi_regs.h
  HDRTEST drivers/gpu/drm/i915/display/g4x_dp.h
  HDRTEST drivers/gpu/drm/i915/display/intel_tc.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk20a.o
  HDRTEST drivers/gpu/drm/i915/display/intel_frontbuffer.h
  HDRTEST drivers/gpu/drm/i915/display/intel_dsi_vbt.h
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_pps.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp100.o
  HDRTEST drivers/gpu/drm/i915/display/intel_psr.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/athub_v1_0.o
  HDRTEST drivers/gpu/drm/i915/display/intel_crt.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/athub_v2_0.o
  HDRTEST drivers/gpu/drm/i915/display/intel_opregion.h
  HDRTEST drivers/gpu/drm/i915/display/intel_snps_phy_regs.h
  HDRTEST drivers/gpu/drm/i915/display/i9xx_wm.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp10b.o
  HDRTEST drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
  HDRTEST drivers/gpu/drm/i915/display/intel_global_state.h
  HDRTEST drivers/gpu/drm/i915/display/intel_lpe_audio.h
  HDRTEST drivers/gpu/drm/i915/display/intel_drrs.h
  HDRTEST drivers/gpu/drm/i915/display/intel_display_rps.h
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_psr.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_qp_tables.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mc/ga100.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/athub_v2_1.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_quirks.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/athub_v3_0.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_snps_phy.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/smuio_v9_0.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_tc.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/smuio_v11_0.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/smuio_v11_0_6.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_vblank.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.o
  HDRTEST drivers/gpu/drm/i915/display/intel_fbdev.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/g84.o
  HDRTEST drivers/gpu/drm/i915/display/intel_pps_regs.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/mcp77.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_vdsc.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/smuio_v13_0.o
  HDRTEST drivers/gpu/drm/i915/display/intel_hdmi.h
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_vga.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/smuio_v13_0_3.o
  HDRTEST drivers/gpu/drm/i915/display/intel_fdi.h
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_vrr.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_wm.o
  HDRTEST drivers/gpu/drm/i915/display/intel_fb.h
  HDRTEST drivers/gpu/drm/i915/display/intel_qp_tables.h
  CC [M]  drivers/gpu/drm/xe/i915-display/skl_scaler.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gk104.o
  HDRTEST drivers/gpu/drm/i915/display/intel_dsb_regs.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gk20a.o
  CC [M]  drivers/gpu/drm/xe/i915-display/skl_universal_plane.o
  HDRTEST drivers/gpu/drm/i915/display/intel_vdsc.h
  HDRTEST drivers/gpu/drm/i915/display/intel_snps_phy.h
  CC [M]  drivers/gpu/drm/xe/i915-display/skl_watermark.o
  HDRTEST drivers/gpu/drm/i915/display/intel_display_core.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gm200.o
  HDRTEST drivers/gpu/drm/i915/display/vlv_dsi_pll.h
  CC [M]  drivers/gpu/drm/xe/xe_pmu.o
  HDRTEST drivers/gpu/drm/i915/display/intel_dvo_dev.h
  HDRTEST drivers/gpu/drm/i915/display/intel_hdcp.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/smuio_v13_0_6.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_reset.o
  HDRTEST drivers/gpu/drm/i915/display/intel_sdvo_regs.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gm20b.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/mca_v3_0.o
  HDRTEST drivers/gpu/drm/i915/display/intel_pch_refclk.h
  HDRTEST drivers/gpu/drm/i915/display/intel_modeset_lock.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gp100.o
  HDRTEST drivers/gpu/drm/i915/display/intel_display_trace.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gp10b.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.o
  HDRTEST drivers/gpu/drm/i915/display/intel_display_power.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gv100.o
  HDRTEST drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_module.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/tu102.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/mem.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_acpi.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_chardev.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_topology.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_opregion.o
  HDRTEST drivers/gpu/drm/i915/display/i9xx_plane.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_pasid.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memnv04.o
  HDRTEST drivers/gpu/drm/i915/display/intel_dp_aux_backlight.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_doorbell.o
  HDRTEST drivers/gpu/drm/i915/display/intel_dpll_mgr.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_flat_memory.o
  HDRTEST drivers/gpu/drm/i915/display/vlv_dsi.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memnv50.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_fbdev.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_process.o
  HDRTEST drivers/gpu/drm/i915/display/intel_plane_initial.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memgf100.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_queue.o
  CC [M]  drivers/gpu/drm/xe/xe_guc.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv04.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv41.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager.o
  HDRTEST drivers/gpu/drm/i915/display/intel_display_device.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv44.o
  CC [M]  drivers/gpu/drm/xe/xe_migrate.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_cik.o
  HDRTEST drivers/gpu/drm/xe/abi/guc_klvs_abi.h
  HDRTEST drivers/gpu/drm/i915/display/intel_fifo_underrun.h
  HDRTEST drivers/gpu/drm/xe/abi/guc_errors_abi.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmmcp77.o
  HDRTEST drivers/gpu/drm/xe/abi/guc_actions_slpc_abi.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_vi.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.o
  HDRTEST drivers/gpu/drm/xe/abi/guc_communication_mmio_abi.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgk104.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_v9.o
  HDRTEST drivers/gpu/drm/xe/abi/guc_actions_abi.h
  HDRTEST drivers/gpu/drm/xe/abi/guc_communication_ctb_abi.h
  HDRTEST drivers/gpu/drm/xe/abi/guc_messages_abi.h
  HDRTEST drivers/gpu/drm/i915/display/intel_cursor.h
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_gem.h
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_vma_types.h
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_irq.h
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/vlv_sideband_reg.h
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_wakeref.h
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_pcode.h
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_v10.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgk20a.o
  HDRTEST drivers/gpu/drm/i915/display/vlv_dsi_regs.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm200.o
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_reg_defs.h
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_trace.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm20b.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_v11.o
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_reg.h
  HDRTEST drivers/gpu/drm/i915/display/intel_cx0_phy.h
  HDRTEST drivers/gpu/drm/i915/display/skl_scaler.h
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_active_types.h
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_utils.h
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_config.h
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_vma.h
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/vlv_sideband.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.o
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_gem_stolen.h
  HDRTEST drivers/gpu/drm/i915/display/intel_hti.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp10b.o
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_mchbar_regs.h
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_debugfs.h
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/soc/intel_pch.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_kernel_queue.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_packet_manager.o
  HDRTEST drivers/gpu/drm/i915/display/icl_dsi_regs.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_packet_manager_vi.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgv100.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_packet_manager_v9.o
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/soc/intel_dram.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmtu102.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/umem.o
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/soc/intel_gmch.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_process_queue_manager.o
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_vgpu.h
  HDRTEST drivers/gpu/drm/i915/display/intel_atomic_plane.h
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_fixed.h
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_runtime_pm.h
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_pci_config.h
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_object_frontbuffer.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.o
  HDRTEST drivers/gpu/drm/i915/display/skl_watermark.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager.o
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/gt/intel_rps.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.o
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_clock_gating.h
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_gt_types.h
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_active.h
  HDRTEST drivers/gpu/drm/xe/regs/xe_reg_defs.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager_cik.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager_vi.o
  HDRTEST drivers/gpu/drm/xe/regs/xe_guc_regs.h
  HDRTEST drivers/gpu/drm/xe/regs/xe_gt_regs.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager_v9.o
  HDRTEST drivers/gpu/drm/xe/regs/xe_regs.h
  HDRTEST drivers/gpu/drm/xe/regs/xe_gt_error_regs.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mxm/mxms.o
  HDRTEST drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
  HDRTEST drivers/gpu/drm/xe/regs/xe_gpu_commands.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mxm/nv50.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager_v10.o
  HDRTEST drivers/gpu/drm/xe/regs/xe_lrc_layout.h
  HDRTEST drivers/gpu/drm/xe/regs/xe_engine_regs.h
  HDRTEST drivers/gpu/drm/xe/tests/xe_test.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager_v11.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_interrupt.o
  HDRTEST drivers/gpu/drm/i915/display/intel_fbc.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pci/agp.o
  HDRTEST drivers/gpu/drm/i915/display/intel_display_reg_defs.h
  HDRTEST drivers/gpu/drm/xe/tests/xe_pci_test.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.o
  HDRTEST drivers/gpu/drm/i915/display/intel_acpi.h
  HDRTEST drivers/gpu/drm/i915/display/intel_connector.h
  HDRTEST drivers/gpu/drm/xe/tests/xe_migrate_test.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pci/pcie.o
  HDRTEST drivers/gpu/drm/i915/display/intel_dpt.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv04.o
  HDRTEST drivers/gpu/drm/i915/display/intel_quirks.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_events.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv40.o
  HDRTEST drivers/gpu/drm/xe/tests/xe_dma_buf_test.h
  HDRTEST drivers/gpu/drm/i915/display/intel_dp_link_training.h
  HDRTEST drivers/gpu/drm/xe/tests/xe_bo_test.h
  HDRTEST drivers/gpu/drm/xe/xe_assert.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/cik_event_interrupt.o
  HDRTEST drivers/gpu/drm/i915/display/intel_color.h
  HDRTEST drivers/gpu/drm/xe/xe_bb.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_int_process_v9.o
  HDRTEST drivers/gpu/drm/i915/display/intel_crtc.h
  HDRTEST drivers/gpu/drm/xe/xe_bb_types.h
  HDRTEST drivers/gpu/drm/xe/xe_bo.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_int_process_v10.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_int_process_v11.o
  HDRTEST drivers/gpu/drm/i915/display/intel_display_debugfs.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv46.o
  HDRTEST drivers/gpu/drm/i915/display/intel_modeset_verify.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv4c.o
  HDRTEST drivers/gpu/drm/xe/xe_bo_doc.h
  HDRTEST drivers/gpu/drm/xe/xe_bo_evict.h
  HDRTEST drivers/gpu/drm/xe/xe_bo_types.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_smi_events.o
  HDRTEST drivers/gpu/drm/xe/xe_debugfs.h
  HDRTEST drivers/gpu/drm/i915/display/intel_display_power_well.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pci/g84.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pci/g92.o
  HDRTEST drivers/gpu/drm/i915/display/intel_psr_regs.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pci/g94.o
  HDRTEST drivers/gpu/drm/i915/display/intel_wm.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_crat.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_debug.o
  HDRTEST drivers/gpu/drm/i915/display/intel_pipe_crc.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_debugfs.o
  HDRTEST drivers/gpu/drm/i915/display/intel_audio_regs.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf100.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_svm.o
  HDRTEST drivers/gpu/drm/i915/display/intel_panel.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf106.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pci/gk104.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pci/gp100.o
  HDRTEST drivers/gpu/drm/i915/display/intel_sprite.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_migrate.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.o
  HDRTEST drivers/gpu/drm/i915/display/intel_wm_types.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.o
  HDRTEST drivers/gpu/drm/i915/display/intel_tv.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.o
  HDRTEST drivers/gpu/drm/i915/display/intel_hti_regs.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf100.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.o
  HDRTEST drivers/gpu/drm/xe/xe_devcoredump.h
  HDRTEST drivers/gpu/drm/xe/xe_devcoredump_types.h
  HDRTEST drivers/gpu/drm/i915/display/intel_vrr.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf119.o
  HDRTEST drivers/gpu/drm/xe/xe_device.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.o
  HDRTEST drivers/gpu/drm/i915/display/intel_load_detect.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk110.o
  HDRTEST drivers/gpu/drm/i915/display/skl_universal_plane.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk208.o
  HDRTEST drivers/gpu/drm/xe/xe_device_sysfs.h
  HDRTEST drivers/gpu/drm/i915/display/intel_mg_phy_regs.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.o
  HDRTEST drivers/gpu/drm/xe/xe_device_types.h
  HDRTEST drivers/gpu/drm/i915/display/intel_bw.h
  HDRTEST drivers/gpu/drm/i915/display/intel_display_irq.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.o
  HDRTEST drivers/gpu/drm/i915/display/intel_de.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm107.o
  HDRTEST drivers/gpu/drm/i915/display/intel_lvds_regs.h
  HDRTEST drivers/gpu/drm/i915/display/intel_gmbus_regs.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm200.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp102.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp10b.o
  HDRTEST drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.h
  HDRTEST drivers/gpu/drm/xe/xe_display.h
  HDRTEST drivers/gpu/drm/i915/display/intel_dvo.h
  HDRTEST drivers/gpu/drm/i915/display/intel_sdvo.h
  HDRTEST drivers/gpu/drm/xe/xe_dma_buf.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.o
  HDRTEST drivers/gpu/drm/i915/display/intel_dp_aux.h
  HDRTEST drivers/gpu/drm/i915/display/intel_vdsc_regs.h
  HDRTEST drivers/gpu/drm/i915/display/intel_combo_phy.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/privring/gf100.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/privring/gf117.o
  HDRTEST drivers/gpu/drm/xe/xe_drm_client.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/privring/gk104.o
  HDRTEST drivers/gpu/drm/i915/display/intel_dvo_regs.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_job.o
  HDRTEST drivers/gpu/drm/i915/display/intel_gmbus.h
  HDRTEST drivers/gpu/drm/i915/display/intel_hdcp_gsc.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_acp.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/privring/gk20a.o
  HDRTEST drivers/gpu/drm/i915/display/intel_dsi.h
  HDRTEST drivers/gpu/drm/xe/xe_drv.h
  HDRTEST drivers/gpu/drm/i915/display/intel_dmc_regs.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/privring/gm200.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/privring/gp10b.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../acp/acp_hw.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/therm/fan.o
  HDRTEST drivers/gpu/drm/xe/xe_exec.h
  HDRTEST drivers/gpu/drm/xe/xe_exec_queue.h
  HDRTEST drivers/gpu/drm/xe/xe_exec_queue_types.h
  HDRTEST drivers/gpu/drm/i915/display/intel_ddi.h
  HDRTEST drivers/gpu/drm/i915/display/intel_hotplug_irq.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/therm/fannil.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/therm/fantog.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/therm/ic.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_ioc32.o
  HDRTEST drivers/gpu/drm/i915/display/intel_tv_regs.h
  HDRTEST drivers/gpu/drm/i915/display/intel_dsb.h
  HDRTEST drivers/gpu/drm/xe/xe_execlist.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.o
  HDRTEST drivers/gpu/drm/xe/xe_execlist_types.h
  HDRTEST drivers/gpu/drm/i915/display/intel_bios.h
  HDRTEST drivers/gpu/drm/i915/display/intel_pch_display.h
  HDRTEST drivers/gpu/drm/xe/xe_force_wake.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv50.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/therm/g84.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/therm/gt215.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/arcturus_ppt.o
  HDRTEST drivers/gpu/drm/i915/display/intel_display_types.h
  HDRTEST drivers/gpu/drm/i915/display/intel_backlight.h
  HDRTEST drivers/gpu/drm/i915/display/intel_vblank.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf100.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.o
  HDRTEST drivers/gpu/drm/xe/xe_force_wake_types.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/sienna_cichlid_ppt.o
  HDRTEST drivers/gpu/drm/i915/display/intel_dp.h
  HDRTEST drivers/gpu/drm/xe/xe_ggtt.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf119.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/vangogh_ppt.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/cyan_skillfish_ppt.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/smu_v11_0.o
  HDRTEST drivers/gpu/drm/xe/xe_ggtt_types.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu12/renoir_ppt.o
  HDRTEST drivers/gpu/drm/i915/display/intel_pmdemand.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm107.o
  HDRTEST drivers/gpu/drm/xe/xe_gt.h
  HDRTEST drivers/gpu/drm/i915/display/intel_backlight_regs.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm200.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/therm/gp100.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/timer/base.o
  HDRTEST drivers/gpu/drm/xe/xe_gt_clock.h
  HDRTEST drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu12/smu_v12_0.o
  HDRTEST drivers/gpu/drm/xe/xe_gt_debugfs.h
  HDRTEST drivers/gpu/drm/xe/xe_gt_idle_sysfs.h
  HDRTEST drivers/gpu/drm/i915/display/intel_display_reset.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0.o
  HDRTEST drivers/gpu/drm/xe/xe_gt_idle_sysfs_types.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/aldebaran_ppt.o
  HDRTEST drivers/gpu/drm/i915/display/intel_display_power_map.h
  HDRTEST drivers/gpu/drm/xe/xe_gt_mcr.h
  HDRTEST drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
  HDRTEST drivers/gpu/drm/i915/display/intel_display_wa.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/yellow_carp_ppt.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0_0_ppt.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv40.o
  HDRTEST drivers/gpu/drm/i915/display/icl_dsi.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0_4_ppt.o
  HDRTEST drivers/gpu/drm/xe/xe_gt_pagefault.h
  HDRTEST drivers/gpu/drm/i915/display/intel_lspcon.h
  HDRTEST drivers/gpu/drm/i915/display/intel_dpio_phy.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv41.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/timer/gk20a.o
  HDRTEST drivers/gpu/drm/xe/xe_gt_printk.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0_5_ppt.o
  HDRTEST drivers/gpu/drm/i915/display/intel_dp_hdcp.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0_7_ppt.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/top/base.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0_6_ppt.o
  HDRTEST drivers/gpu/drm/xe/xe_gt_sysfs.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/swsmu/amdgpu_smu.o
  HDRTEST drivers/gpu/drm/i915/display/intel_fb_pin.h
  HDRTEST drivers/gpu/drm/i915/display/intel_pps.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu_cmn.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/smumgr.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/top/gk104.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/smu8_smumgr.o
  HDRTEST drivers/gpu/drm/i915/display/intel_sprite_uapi.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/top/ga100.o
  HDRTEST drivers/gpu/drm/xe/xe_gt_sysfs_types.h
  HDRTEST drivers/gpu/drm/i915/gem/i915_gem_ttm.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/vfn/base.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/vfn/uvfn.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/vfn/gv100.o
  HDRTEST drivers/gpu/drm/i915/gem/i915_gem_region.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/tonga_smumgr.o
  HDRTEST drivers/gpu/drm/i915/gem/i915_gem_context_types.h
  HDRTEST drivers/gpu/drm/xe/xe_gt_tlb_invalidation.h
  HDRTEST drivers/gpu/drm/xe/xe_gt_tlb_invalidation_types.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/vfn/tu102.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/vfn/ga100.o
  HDRTEST drivers/gpu/drm/i915/gem/i915_gem_lmem.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.o
  HDRTEST drivers/gpu/drm/i915/gem/i915_gem_mman.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/volt/gpio.o
  HDRTEST drivers/gpu/drm/xe/xe_gt_topology.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/volt/nv40.o
  HDRTEST drivers/gpu/drm/i915/gem/i915_gem_object_types.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/fiji_smumgr.o
  HDRTEST drivers/gpu/drm/xe/xe_gt_types.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/polaris10_smumgr.o
  HDRTEST drivers/gpu/drm/xe/xe_guc.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/volt/gf100.o
  HDRTEST drivers/gpu/drm/xe/xe_guc_ads.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_ads_types.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/volt/gf117.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/iceland_smumgr.o
  HDRTEST drivers/gpu/drm/xe/xe_guc_ct.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.o
  HDRTEST drivers/gpu/drm/i915/gem/i915_gem_context.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/volt/gm20b.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/smu7_smumgr.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/falcon.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/xtensa.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/bsp/g84.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.o
  HDRTEST drivers/gpu/drm/i915/gem/i915_gem_clflush.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/vega10_smumgr.o
  HDRTEST drivers/gpu/drm/xe/xe_guc_ct_types.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_debugfs.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_exec_queue_types.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_fwif.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/smu10_smumgr.o
  HDRTEST drivers/gpu/drm/i915/gem/i915_gem_tiling.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/ci_smumgr.o
  HDRTEST drivers/gpu/drm/i915/gem/i915_gem_stolen.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_hwconfig.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_log.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_log_types.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/ce/gm107.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/vega12_smumgr.o
  HDRTEST drivers/gpu/drm/xe/xe_guc_pc.h
  HDRTEST drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/ce/gm200.o
  HDRTEST drivers/gpu/drm/i915/gem/i915_gem_create.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/vegam_smumgr.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/smu9_smumgr.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/vega20_smumgr.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/ce/gp100.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/hwmgr.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/ce/gp102.o
  HDRTEST drivers/gpu/drm/i915/gem/i915_gem_ttm_move.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/processpptables.o
  HDRTEST drivers/gpu/drm/i915/gem/i915_gem_ioctls.h
  HDRTEST drivers/gpu/drm/i915/gem/i915_gem_domain.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_pc_types.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/hardwaremanager.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu8_hwmgr.o
  HDRTEST drivers/gpu/drm/xe/xe_guc_submit.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/ce/gv100.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/ce/tu102.o
  HDRTEST drivers/gpu/drm/xe/xe_guc_submit_types.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/ce/ga100.o
  HDRTEST drivers/gpu/drm/xe/xe_guc_types.h
  HDRTEST drivers/gpu/drm/i915/gem/i915_gem_internal.h
  HDRTEST drivers/gpu/drm/xe/xe_huc.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/pppcielanes.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/ce/ga102.o
  HDRTEST drivers/gpu/drm/xe/xe_huc_debugfs.h
  HDRTEST drivers/gpu/drm/xe/xe_huc_types.h
  HDRTEST drivers/gpu/drm/i915/gem/i915_gem_dmabuf.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.o
  HDRTEST drivers/gpu/drm/xe/xe_hw_engine.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/process_pptables_v1_0.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/ppatomctrl.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/device/base.o
  HDRTEST drivers/gpu/drm/i915/gem/selftests/mock_context.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/ppatomfwctrl.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/device/pci.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.o
  HDRTEST drivers/gpu/drm/xe/xe_hw_engine_class_sysfs.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/device/user.o
  HDRTEST drivers/gpu/drm/i915/gem/selftests/huge_gem_object.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/base.o
  HDRTEST drivers/gpu/drm/xe/xe_hw_engine_types.h
  HDRTEST drivers/gpu/drm/xe/xe_hw_error.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_hwmgr.o
  HDRTEST drivers/gpu/drm/i915/gem/selftests/mock_gem_object.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/chan.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_powertune.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.o
  HDRTEST drivers/gpu/drm/xe/xe_hw_fence.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_thermal.o
  HDRTEST drivers/gpu/drm/xe/xe_hw_fence_types.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_clockpowergating.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmi.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/head.o
  HDRTEST drivers/gpu/drm/xe/xe_irq.h
  HDRTEST drivers/gpu/drm/xe/xe_lrc.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/vga.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_processpptables.o
  HDRTEST drivers/gpu/drm/xe/xe_lrc_types.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.o
  HDRTEST drivers/gpu/drm/xe/xe_macros.h
  HDRTEST drivers/gpu/drm/xe/xe_map.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.o
  HDRTEST drivers/gpu/drm/xe/xe_migrate.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_powertune.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_thermal.o
  HDRTEST drivers/gpu/drm/xe/xe_migrate_doc.h
  HDRTEST drivers/gpu/drm/xe/xe_mmio.h
  HDRTEST drivers/gpu/drm/xe/xe_mocs.h
  HDRTEST drivers/gpu/drm/xe/xe_module.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu10_hwmgr.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.o
  HDRTEST drivers/gpu/drm/i915/gem/selftests/mock_dmabuf.h
  HDRTEST drivers/gpu/drm/xe/xe_pat.h
  HDRTEST drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.h
  HDRTEST drivers/gpu/drm/xe/xe_pci.h
  HDRTEST drivers/gpu/drm/xe/xe_pci_types.h
  HDRTEST drivers/gpu/drm/i915/gem/i915_gem_userptr.h
  HDRTEST drivers/gpu/drm/xe/xe_pcode.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/gt200.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/pp_psm.o
  HDRTEST drivers/gpu/drm/i915/gem/i915_gem_pm.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp77.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega12_processpptables.o
  HDRTEST drivers/gpu/drm/i915/gem/i915_gem_shrinker.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega12_hwmgr.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.o
  HDRTEST drivers/gpu/drm/i915/gem/i915_gemfs.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp89.o
  HDRTEST drivers/gpu/drm/i915/gem/i915_gem_object.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega12_thermal.o
  HDRTEST drivers/gpu/drm/xe/xe_pcode_api.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/pp_overdriver.o
  HDRTEST drivers/gpu/drm/xe/xe_platform_types.h
  HDRTEST drivers/gpu/drm/xe/xe_pm.h
  HDRTEST drivers/gpu/drm/i915/gem/i915_gem_object_frontbuffer.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu_helper.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega20_processpptables.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega20_hwmgr.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/gm200.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega20_powertune.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega20_thermal.o
  HDRTEST drivers/gpu/drm/xe/xe_pmu.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/gp100.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/common_baco.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_baco.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega20_baco.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_timeline_types.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega12_baco.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu9_baco.o
  HDRTEST drivers/gpu/drm/xe/xe_pmu_types.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/tonga_baco.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/polaris_baco.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/ga102.o
  HDRTEST drivers/gpu/drm/i915/gt/selftest_engine.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/udisp.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_breadcrumbs.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_context_types.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/uhead.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/dma/base.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_execlists_submission.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_gt_pm.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/dma/nv04.o
  HDRTEST drivers/gpu/drm/xe/xe_preempt_fence.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/dma/nv50.o
  HDRTEST drivers/gpu/drm/xe/xe_preempt_fence_types.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/fiji_baco.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/ci_baco.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/dma/gf100.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_baco.o
  HDRTEST drivers/gpu/drm/xe/xe_pt.h
  HDRTEST drivers/gpu/drm/i915/gt/selftest_rc6.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/amd_powerplay.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/dma/gf119.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_llc_types.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/dma/gv100.o
  HDRTEST drivers/gpu/drm/xe/xe_pt_types.h
  HDRTEST drivers/gpu/drm/xe/xe_pt_walk.h
  HDRTEST drivers/gpu/drm/xe/xe_query.h
  HDRTEST drivers/gpu/drm/xe/xe_range_fence.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_gt.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/dma/user.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/legacy-dpm/legacy_dpm.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/legacy-dpm/kv_dpm.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/legacy-dpm/kv_smc.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/legacy-dpm/si_dpm.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_region_lmem.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.o
  HDRTEST drivers/gpu/drm/xe/xe_reg_sr.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/legacy-dpm/si_smc.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm.o
  HDRTEST drivers/gpu/drm/xe/xe_reg_sr_types.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_pm.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_gt_requests.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm_internal.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/cgrp.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_ggtt_gmch.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_crtc.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_gt_print.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.o
  HDRTEST drivers/gpu/drm/xe/xe_reg_whitelist.h
  HDRTEST drivers/gpu/drm/xe/xe_res_cursor.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/chid.o
  HDRTEST drivers/gpu/drm/xe/xe_ring_ops.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/runl.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_irq.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/runq.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.o
  HDRTEST drivers/gpu/drm/i915/gt/gen8_ppgtt.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.o
  HDRTEST drivers/gpu/drm/xe/xe_ring_ops_types.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_mst_types.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.o
  HDRTEST drivers/gpu/drm/xe/xe_rtp.h
  HDRTEST drivers/gpu/drm/xe/xe_rtp_types.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_gt_mcr.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_timeline.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_color.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/dc_fpu.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_services.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_helpers.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_pp_smu.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.o
  HDRTEST drivers/gpu/drm/xe/xe_sa.h
  HDRTEST drivers/gpu/drm/xe/xe_sa_types.h
  HDRTEST drivers/gpu/drm/i915/gt/gen6_engine_cs.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/g98.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk110.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_workarounds_types.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_psr.o
  HDRTEST drivers/gpu/drm/xe/xe_sched_job.h
  HDRTEST drivers/gpu/drm/i915/gt/selftest_rps.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_replay.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_sa_media.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_gt_debugfs.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.o
  HDRTEST drivers/gpu/drm/xe/xe_sched_job_types.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_hdcp.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_gt_clock_utils.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm200.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_crc.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp100.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.o
  HDRTEST drivers/gpu/drm/xe/xe_step.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/tu102.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_rps_types.h
  HDRTEST drivers/gpu/drm/xe/xe_step_types.h
  HDRTEST drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.h
  HDRTEST drivers/gpu/drm/xe/xe_sync.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.o
  HDRTEST drivers/gpu/drm/xe/xe_sync_types.h
  HDRTEST drivers/gpu/drm/i915/gt/sysfs_engines.h
  HDRTEST drivers/gpu/drm/xe/xe_tile.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga100.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/basics/conversion.o
  HDRTEST drivers/gpu/drm/i915/gt/gen7_renderclear.h
  HDRTEST drivers/gpu/drm/xe/xe_tile_sysfs.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_context.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga102.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/ucgrp.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/uchan.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_wopcm.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/base.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_mocs.h
  HDRTEST drivers/gpu/drm/xe/xe_tile_sysfs_types.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/basics/fixpt31_32.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_engine_pm.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/basics/vector.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_gt_sysfs.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_rc6.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/basics/dc_common.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/nv15.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser_interface.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_gt_defines.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser_helper.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_ring_types.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/bios/command_table.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/nv17.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/bios/command_table_helper.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_workarounds.h
  HDRTEST drivers/gpu/drm/xe/xe_trace.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser_common.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/bios/command_table2.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_engine_regs.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.o
  HDRTEST drivers/gpu/drm/xe/xe_ttm_stolen_mgr.h
  HDRTEST drivers/gpu/drm/xe/xe_ttm_sys_mgr.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/bios/command_table_helper2.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.o
  HDRTEST drivers/gpu/drm/xe/xe_ttm_vram_mgr.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_gt_pm_irq.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser2.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce60/command_table_helper_dce60.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce80/command_table_helper_dce80.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce110/command_table_helper_dce110.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce112/command_table_helper_dce112.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce112/command_table_helper2_dce112.o
  HDRTEST drivers/gpu/drm/i915/gt/shmem_utils.h
  HDRTEST drivers/gpu/drm/xe/xe_ttm_vram_mgr_types.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_engine.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/calcs/dce_calcs.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_reset_types.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_gt_regs.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/calcs/custom_float.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/calcs/bw_fixed.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_reset.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_rq_dlg_helpers.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/gt200.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dml1_display_rq_dlg_calc.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn10/dcn10_fpu.o
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/dcn20_fpu.o
  HDRTEST drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp79.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_vba.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/gt215.o
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_uc.h
  HDRTEST drivers/gpu/drm/xe/xe_tuning.h
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
  HDRTEST drivers/gpu/drm/xe/xe_uc.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_mode_vba_20.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp89.o
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_print.h
  HDRTEST drivers/gpu/drm/xe/xe_uc_debugfs.h
  HDRTEST drivers/gpu/drm/xe/xe_uc_fw.h
  HDRTEST drivers/gpu/drm/xe/xe_uc_fw_abi.h
  HDRTEST drivers/gpu/drm/xe/xe_uc_fw_types.h
  HDRTEST drivers/gpu/drm/xe/xe_uc_types.h
  HDRTEST drivers/gpu/drm/xe/xe_vm.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20v2.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.o
  HDRTEST drivers/gpu/drm/xe/xe_vm_doc.h
  HDRTEST drivers/gpu/drm/xe/xe_vm_madvise.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_mode_vba_20v2.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn21/display_rq_dlg_calc_21.o
  HDRTEST drivers/gpu/drm/xe/xe_vm_types.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn21/display_mode_vba_21.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/dcn30_fpu.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.o
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_fw.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/display_mode_vba_30.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/display_rq_dlg_calc_30.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/display_mode_vba_31.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/display_rq_dlg_calc_31.o
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/display_mode_vba_314.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.o
  HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/display_rq_dlg_calc_314.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.o
  HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h
  HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_rq_dlg_calc_32.o
  HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_util_32.o
  HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.o
  HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h
  HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h
  HDRTEST drivers/gpu/drm/xe/xe_wa.h
  HDRTEST drivers/gpu/drm/xe/xe_wait_user_fence.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/dcn31_fpu.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/dcn32_fpu.o
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_debugfs.h
  HDRTEST drivers/gpu/drm/xe/xe_wopcm.h
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
  HDRTEST drivers/gpu/drm/xe/xe_wopcm_types.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/gp104.o
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.h
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_huc.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/gp107.o
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_gsc_binary_headers.h
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc.h
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_huc_print.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/gp108.o
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_huc_fw.h
  LD [M]  drivers/gpu/drm/xe/xe.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/gp10b.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.o
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/tu102.o
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_capture.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/ga102.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.o
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn321/dcn321_fpu.o
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.o
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn301/dcn301_fpu.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf104.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf110.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn302/dcn302_fpu.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn303/dcn303_fpu.o
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/dcn314_fpu.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dsc/rc_calc_fpu.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf119.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/calcs/dcn_calcs.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/calcs/dcn_calc_math.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.o
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_log.h
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110.o
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110b.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/calcs/dcn_calc_auto.o
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.h
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_rc.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/clk_mgr.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk208.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dce60/dce60_clk_mgr.o
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_huc_debugfs.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_hwconfig.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_llc.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dce100/dce_clk_mgr.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dce110/dce110_clk_mgr.o
  HDRTEST drivers/gpu/drm/i915/gt/gen8_engine_cs.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_sseu_debugfs.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_rc6_types.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dce112/dce112_clk_mgr.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_context_param.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp100.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp102.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_gpu_commands.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dce120/dce120_clk_mgr.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_engine_user.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp104.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp107.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn10/rv1_clk_mgr.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_gt_irq.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_gsc.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_rps.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn10/rv2_clk_mgr.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxtu102.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_tlb.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxga102.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.o
  HDRTEST drivers/gpu/drm/i915/gt/selftest_llc.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.o
  HDRTEST drivers/gpu/drm/i915/gt/gen6_ppgtt.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn201/dcn201_clk_mgr.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_migrate_types.h
  HDRTEST drivers/gpu/drm/i915/gt/selftests/mock_timeline.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_lrc.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_lrc_reg.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn21/rn_clk_mgr.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/mpeg/g84.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_migrate.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/mspdec/base.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/mspdec/g98.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_breadcrumbs_types.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gt215.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gf100.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn301/vg_clk_mgr.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gk104.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/msppp/base.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn301/dcn301_smu.o
  HDRTEST drivers/gpu/drm/i915/gt/mock_engine.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/msppp/g98.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/msppp/gt215.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/msppp/gf100.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn31/dcn31_smu.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_engine_stats.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/msvld/base.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn31/dcn31_clk_mgr.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_gtt.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn314/dcn314_smu.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/msvld/g98.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/msvld/gt215.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn314/dcn314_clk_mgr.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn315/dcn315_smu.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/msvld/mcp89.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/msvld/gf100.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn315/dcn315_clk_mgr.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/msvld/gk104.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/nvenc/base.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_gt_buffer_pool_types.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/nvenc/gm107.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn316/dcn316_smu.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_ring.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_gt_types.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/nvdec/base.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/nvdec/gm107.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn316/dcn316_clk_mgr.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/nvdec/ga102.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/pm/base.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_renderstate.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/pm/nv50.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/pm/g84.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_sseu.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/pm/gt200.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/pm/gt215.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_audio.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_engine_types.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/pm/gf108.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_gt_engines_debugfs.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/pm/gf117.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_stream_encoder.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_link_encoder.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_hwseq.o
  HDRTEST drivers/gpu/drm/i915/gt/gen2_engine_cs.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/pm/gk104.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_clock_source.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.o
  HDRTEST drivers/gpu/drm/i915/gvt/gvt.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.o
  HDRTEST drivers/gpu/drm/i915/gvt/trace.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.o
  HDRTEST drivers/gpu/drm/i915/gvt/debug.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_scl_filters.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp108.o
  HDRTEST drivers/gpu/drm/i915/gvt/edid.h
  HDRTEST drivers/gpu/drm/i915/gvt/page_track.h
  HDRTEST drivers/gpu/drm/i915/gvt/mmio.h
  HDRTEST drivers/gpu/drm/i915/gvt/sched_policy.h
  HDRTEST drivers/gpu/drm/i915/gvt/fb_decoder.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_transform.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/sec2/tu102.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/sec2/ga102.o
  HDRTEST drivers/gpu/drm/i915/gvt/cmd_parser.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_opp.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/sw/base.o
  HDRTEST drivers/gpu/drm/i915/gvt/dmabuf.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.o
  HDRTEST drivers/gpu/drm/i915/gvt/mmio_context.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_dmcu.o
  HDRTEST drivers/gpu/drm/i915/gvt/display.h
  HDRTEST drivers/gpu/drm/i915/gvt/gtt.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_abm.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/sw/chan.o
  HDRTEST drivers/gpu/drm/i915/gvt/scheduler.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_ipp.o
  HDRTEST drivers/gpu/drm/i915/gvt/reg.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/sw/nvsw.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/vp/g84.o
  HDRTEST drivers/gpu/drm/i915/gvt/execlist.h
  CC [M]  drivers/gpu/drm/nouveau/nouveau_acpi.o
  CC [M]  drivers/gpu/drm/nouveau/nouveau_debugfs.o
  HDRTEST drivers/gpu/drm/i915/gvt/interrupt.h
  CC [M]  drivers/gpu/drm/nouveau/nouveau_drm.o
  HDRTEST drivers/gpu/drm/i915/i915_active.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_i2c.o
  CC [M]  drivers/gpu/drm/nouveau/nouveau_hwmon.o
  CC [M]  drivers/gpu/drm/nouveau/nouveau_ioc32.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_i2c_hw.o
  CC [M]  drivers/gpu/drm/nouveau/nouveau_led.o
  CC [M]  drivers/gpu/drm/nouveau/nouveau_nvif.o
  HDRTEST drivers/gpu/drm/i915/i915_active_types.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_i2c_sw.o
  HDRTEST drivers/gpu/drm/i915/i915_cmd_parser.h
  CC [M]  drivers/gpu/drm/nouveau/nouveau_usif.o
  HDRTEST drivers/gpu/drm/i915/i915_config.h
  HDRTEST drivers/gpu/drm/i915/i915_debugfs.h
  HDRTEST drivers/gpu/drm/i915/i915_debugfs_params.h
  HDRTEST drivers/gpu/drm/i915/i915_deps.h
  CC [M]  drivers/gpu/drm/nouveau/nouveau_vga.o
  HDRTEST drivers/gpu/drm/i915/i915_driver.h
  CC [M]  drivers/gpu/drm/nouveau/nouveau_bo.o
  HDRTEST drivers/gpu/drm/i915/i915_drm_client.h
  HDRTEST drivers/gpu/drm/i915

[Intel-xe] ✗ CI.Hooks: failure for Supporting CSC and SOC HARDWARE ERROR HANDLING on PVC

[Patchwork]

== Series Details ==

Series: Supporting CSC and SOC HARDWARE ERROR HANDLING on PVC
URL   : https://patchwork.freedesktop.org/series/124331/
State : failure

== Summary ==

run-parts: executing /workspace/ci/hooks/00-showenv
+ pwd
+ ls -la
/workspace
total 956
drwxrwxr-x 10 1003 1003   4096 Sep 27 11:51 .
drwxr-xr-x  1 root root   4096 Sep 27 11:51 ..
-rw-rw-r--  1 1003 1003 790032 Sep 27 11:51 build.log
-rw-rw-r--  1 1003 1003   5609 Sep 27 11:43 checkpatch.log
drwxrwxr-x  5 1003 1003   4096 Sep 27 11:41 ci
drwxrwxr-x  9 1003 1003   4096 Sep 27 11:41 docker
drwxrwxr-x  8 1003 1003   4096 Sep 27 11:41 .git
-rw-rw-r--  1 1003 1003    774 Sep 27 11:43 git_apply.log
drwxrwxr-x  4 1003 1003   4096 Sep 27 11:41 .github
-rw-rw-r--  1 1003 1003    233 Sep 27 11:41 .groovylintrc.json
-rw-rw-r--  1 1003 1003     78 Sep 27 11:51 hooks.log
drwxrwxr-x 31 1003 1003   4096 Sep 27 11:51 kernel
-rw-rw-r--  1 1003 1003  87672 Sep 27 11:43 kernel.mbox
-rw-rw-r--  1 1003 1003  26482 Sep 27 11:44 kunit.log
-rw-rw-r--  1 1003 1003     48 Sep 27 11:43 parent.tag
drwxrwxr-x 45 1003 1003   4096 Sep 27 11:41 pipelines
-rw-rw-r--  1 1003 1003    793 Sep 27 11:41 README.adoc
drwxrwxr-x  3 1003 1003   4096 Sep 27 11:41 scripts
drwxrwxr-x  2 1003 1003   4096 Sep 27 11:41 .vscode
+ uname -a
Linux ccf35e279c48 5.4.0-149-generic #166-Ubuntu SMP Tue Apr 18 16:51:45 UTC 2023 x86_64 x86_64 x86_64 GNU/Linux
+ export
+ grep -Ei '(^|\W)CI_'
declare -x CI_KERNEL_BUILD_DIR="/workspace/kernel/build64-default"
declare -x CI_KERNEL_SRC_DIR="/workspace/kernel"
declare -x CI_TOOLS_SRC_DIR="/workspace/ci"
declare -x CI_WORKSPACE_DIR="/workspace"
+ '[' -n /workspace ']'
+ git_args='-C /workspace/kernel'
+ git_log_args=
+ git --no-pager -C /workspace/kernel log --format=oneline --abbrev-commit
0709f8f34 drm/xe: Clear all SoC errors post warm reset.
5c92b3139 drm/xe: Clear SOC CORRECTABLE error registers.
155799e73 drm/xe: Handle MDFI error severity.
fc4c1730f drm/xe: Support SOC NONFATAL error handling for PVC.
6c0ed0898 drm/xe: Support SOC FATAL error handling for PVC.
ab84692ac drm/xe: Notify userspace about GSC HW errors.
2557d92dc drm/xe: Support GSC hardware error reporting for PVC.
2be90df70 drm/xe: Process fatal hardware errors.
7fdc8cb45 drm/xe: Support GT hardware error reporting for PVC.
5531034ec drm/xe: Log and count the GT hardware errors.
edab64e93 drm/xe: Handle errors from various components.
fc8ec3c56 drm/xe: Add Wa_18028616096
run-parts: executing /workspace/ci/hooks/10-build-W1
+ SRC_DIR=/workspace/kernel
+ RESTORE_DISPLAY_CONFIG=0
+ '[' -n /workspace/kernel/build64-default ']'
+ BUILD_DIR=/workspace/kernel/build64-default
+ cd /workspace/kernel
+ grep -q -e '^CONFIG_DRM_XE_DISPLAY=[yY]' /workspace/kernel/build64-default/.config
+ RESTORE_DISPLAY_CONFIG=1
+ trap cleanup EXIT
+ ./scripts/config --file /workspace/kernel/build64-default/.config --disable CONFIG_DRM_XE_DISPLAY
++ nproc
+ make -j48 O=/workspace/kernel/build64-default modules_prepare
make[1]: Entering directory '/workspace/kernel/build64-default'
  SYNC    include/config/auto.conf.cmd
  GEN     Makefile
  GEN     Makefile
  UPD     include/generated/compile.h
  UPD     include/config/kernel.release
  UPD     include/generated/utsrelease.h
  DESCEND objtool
  CALL    ../scripts/checksyscalls.sh
  HOSTCC  /workspace/kernel/build64-default/tools/objtool/fixdep.o
  HOSTLD  /workspace/kernel/build64-default/tools/objtool/fixdep-in.o
  LINK    /workspace/kernel/build64-default/tools/objtool/fixdep
  INSTALL libsubcmd_headers
  CC      /workspace/kernel/build64-default/tools/objtool/libsubcmd/exec-cmd.o
  CC      /workspace/kernel/build64-default/tools/objtool/libsubcmd/help.o
  CC      /workspace/kernel/build64-default/tools/objtool/libsubcmd/pager.o
  CC      /workspace/kernel/build64-default/tools/objtool/libsubcmd/parse-options.o
  CC      /workspace/kernel/build64-default/tools/objtool/libsubcmd/run-command.o
  CC      /workspace/kernel/build64-default/tools/objtool/libsubcmd/subcmd-config.o
  CC      /workspace/kernel/build64-default/tools/objtool/libsubcmd/sigchain.o
  LD      /workspace/kernel/build64-default/tools/objtool/libsubcmd/libsubcmd-in.o
  AR      /workspace/kernel/build64-default/tools/objtool/libsubcmd/libsubcmd.a
  CC      /workspace/kernel/build64-default/tools/objtool/weak.o
  CC      /workspace/kernel/build64-default/tools/objtool/check.o
  CC      /workspace/kernel/build64-default/tools/objtool/special.o
  CC      /workspace/kernel/build64-default/tools/objtool/builtin-check.o
  CC      /workspace/kernel/build64-default/tools/objtool/elf.o
  CC      /workspace/kernel/build64-default/tools/objtool/objtool.o
  CC      /workspace/kernel/build64-default/tools/objtool/orc_gen.o
  CC      /workspace/kernel/build64-default/tools/objtool/orc_dump.o
  CC      /workspace/kernel/build64-default/tools/objtool/libstring.o
  CC      /workspace/kernel/build64-default/tools/objtool/libctype.o
  CC      /workspace/kernel/build64-default/tools/objtool/str_error_r.o
  CC      /workspace/kernel/build64-default/tools/objtool/librbtree.o
  CC      /workspace/kernel/build64-default/tools/objtool/arch/x86/special.o
  CC      /workspace/kernel/build64-default/tools/objtool/arch/x86/decode.o
  LD      /workspace/kernel/build64-default/tools/objtool/arch/x86/objtool-in.o
  LD      /workspace/kernel/build64-default/tools/objtool/objtool-in.o
  LINK    /workspace/kernel/build64-default/tools/objtool/objtool
make[1]: Leaving directory '/workspace/kernel/build64-default'
++ nproc
+ make -j48 O=/workspace/kernel/build64-default M=drivers/gpu/drm/xe W=1
make[1]: Entering directory '/workspace/kernel/build64-default'
  CC [M]  drivers/gpu/drm/xe/xe_bb.o
  CC [M]  drivers/gpu/drm/xe/xe_bo.o
  CC [M]  drivers/gpu/drm/xe/xe_bo_evict.o
  CC [M]  drivers/gpu/drm/xe/xe_debugfs.o
  CC [M]  drivers/gpu/drm/xe/xe_devcoredump.o
  CC [M]  drivers/gpu/drm/xe/xe_device.o
  CC [M]  drivers/gpu/drm/xe/xe_device_sysfs.o
  CC [M]  drivers/gpu/drm/xe/xe_dma_buf.o
  CC [M]  drivers/gpu/drm/xe/xe_drm_client.o
  CC [M]  drivers/gpu/drm/xe/xe_exec.o
  CC [M]  drivers/gpu/drm/xe/xe_execlist.o
  CC [M]  drivers/gpu/drm/xe/xe_exec_queue.o
  CC [M]  drivers/gpu/drm/xe/xe_force_wake.o
  CC [M]  drivers/gpu/drm/xe/xe_ggtt.o
  CC [M]  drivers/gpu/drm/xe/xe_gt.o
  CC [M]  drivers/gpu/drm/xe/xe_gt_clock.o
  CC [M]  drivers/gpu/drm/xe/xe_gt_debugfs.o
  CC [M]  drivers/gpu/drm/xe/xe_gt_idle_sysfs.o
  CC [M]  drivers/gpu/drm/xe/xe_gt_mcr.o
  CC [M]  drivers/gpu/drm/xe/xe_gt_pagefault.o
  CC [M]  drivers/gpu/drm/xe/xe_gt_sysfs.o
  CC [M]  drivers/gpu/drm/xe/xe_gt_tlb_invalidation.o
  CC [M]  drivers/gpu/drm/xe/xe_gt_topology.o
  HOSTCC  drivers/gpu/drm/xe/xe_gen_wa_oob
  CC [M]  drivers/gpu/drm/xe/xe_guc_ads.o
  CC [M]  drivers/gpu/drm/xe/xe_guc_ct.o
  CC [M]  drivers/gpu/drm/xe/xe_guc_debugfs.o
  CC [M]  drivers/gpu/drm/xe/xe_guc_hwconfig.o
  CC [M]  drivers/gpu/drm/xe/xe_guc_log.o
  CC [M]  drivers/gpu/drm/xe/xe_guc_pc.o
  CC [M]  drivers/gpu/drm/xe/xe_guc_submit.o
  CC [M]  drivers/gpu/drm/xe/xe_hw_engine.o
  CC [M]  drivers/gpu/drm/xe/xe_hw_engine_class_sysfs.o
  CC [M]  drivers/gpu/drm/xe/xe_hw_error.o
  CC [M]  drivers/gpu/drm/xe/xe_hw_fence.o
  CC [M]  drivers/gpu/drm/xe/xe_huc.o
  CC [M]  drivers/gpu/drm/xe/xe_huc_debugfs.o
  CC [M]  drivers/gpu/drm/xe/xe_irq.o
  CC [M]  drivers/gpu/drm/xe/xe_lrc.o
  CC [M]  drivers/gpu/drm/xe/xe_mmio.o
  CC [M]  drivers/gpu/drm/xe/xe_mocs.o
  CC [M]  drivers/gpu/drm/xe/xe_module.o
  CC [M]  drivers/gpu/drm/xe/xe_pat.o
  CC [M]  drivers/gpu/drm/xe/xe_pci.o
  CC [M]  drivers/gpu/drm/xe/xe_pcode.o
  CC [M]  drivers/gpu/drm/xe/xe_pm.o
  CC [M]  drivers/gpu/drm/xe/xe_preempt_fence.o
  CC [M]  drivers/gpu/drm/xe/xe_pt.o
  CC [M]  drivers/gpu/drm/xe/xe_pt_walk.o
  CC [M]  drivers/gpu/drm/xe/xe_query.o
  CC [M]  drivers/gpu/drm/xe/xe_range_fence.o
  CC [M]  drivers/gpu/drm/xe/xe_reg_sr.o
  CC [M]  drivers/gpu/drm/xe/xe_reg_whitelist.o
  CC [M]  drivers/gpu/drm/xe/xe_rtp.o
  CC [M]  drivers/gpu/drm/xe/xe_sa.o
  CC [M]  drivers/gpu/drm/xe/xe_sched_job.o
  CC [M]  drivers/gpu/drm/xe/xe_step.o
  CC [M]  drivers/gpu/drm/xe/xe_sync.o
  CC [M]  drivers/gpu/drm/xe/xe_tile.o
  CC [M]  drivers/gpu/drm/xe/xe_tile_sysfs.o
  CC [M]  drivers/gpu/drm/xe/xe_trace.o
  CC [M]  drivers/gpu/drm/xe/xe_ttm_sys_mgr.o
  CC [M]  drivers/gpu/drm/xe/xe_ttm_stolen_mgr.o
  CC [M]  drivers/gpu/drm/xe/xe_ttm_vram_mgr.o
  CC [M]  drivers/gpu/drm/xe/xe_tuning.o
  CC [M]  drivers/gpu/drm/xe/xe_uc.o
  CC [M]  drivers/gpu/drm/xe/xe_uc_debugfs.o
  CC [M]  drivers/gpu/drm/xe/xe_uc_fw.o
  CC [M]  drivers/gpu/drm/xe/xe_vm_madvise.o
  CC [M]  drivers/gpu/drm/xe/xe_wait_user_fence.o
  CC [M]  drivers/gpu/drm/xe/xe_wopcm.o
  CC [M]  drivers/gpu/drm/xe/xe_pmu.o
  HDRTEST drivers/gpu/drm/xe/abi/guc_klvs_abi.h
  HDRTEST drivers/gpu/drm/xe/abi/guc_errors_abi.h
  HDRTEST drivers/gpu/drm/xe/abi/guc_actions_slpc_abi.h
  HDRTEST drivers/gpu/drm/xe/abi/guc_communication_mmio_abi.h
  CC [M]  drivers/gpu/drm/xe/tests/xe_bo_test.o
  CC [M]  drivers/gpu/drm/xe/tests/xe_dma_buf_test.o
  CC [M]  drivers/gpu/drm/xe/tests/xe_migrate_test.o
  CC [M]  drivers/gpu/drm/xe/tests/xe_pci_test.o
  HDRTEST drivers/gpu/drm/xe/abi/guc_actions_abi.h
  HDRTEST drivers/gpu/drm/xe/abi/guc_communication_ctb_abi.h
  HDRTEST drivers/gpu/drm/xe/abi/guc_messages_abi.h
  CC [M]  drivers/gpu/drm/xe/tests/xe_rtp_test.o
  HDRTEST drivers/gpu/drm/xe/regs/xe_reg_defs.h
  CC [M]  drivers/gpu/drm/xe/tests/xe_wa_test.o
  HDRTEST drivers/gpu/drm/xe/regs/xe_guc_regs.h
  HDRTEST drivers/gpu/drm/xe/regs/xe_gt_regs.h
  HDRTEST drivers/gpu/drm/xe/regs/xe_regs.h
  HDRTEST drivers/gpu/drm/xe/regs/xe_gt_error_regs.h
  HDRTEST drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
  HDRTEST drivers/gpu/drm/xe/regs/xe_gpu_commands.h
  HDRTEST drivers/gpu/drm/xe/regs/xe_lrc_layout.h
  HDRTEST drivers/gpu/drm/xe/regs/xe_engine_regs.h
  HDRTEST drivers/gpu/drm/xe/tests/xe_test.h
  HDRTEST drivers/gpu/drm/xe/tests/xe_pci_test.h
  HDRTEST drivers/gpu/drm/xe/tests/xe_migrate_test.h
  HDRTEST drivers/gpu/drm/xe/tests/xe_dma_buf_test.h
  HDRTEST drivers/gpu/drm/xe/tests/xe_bo_test.h
  HDRTEST drivers/gpu/drm/xe/xe_assert.h
  HDRTEST drivers/gpu/drm/xe/xe_bb.h
  HDRTEST drivers/gpu/drm/xe/xe_bb_types.h
  HDRTEST drivers/gpu/drm/xe/xe_bo.h
  HDRTEST drivers/gpu/drm/xe/xe_bo_doc.h
  HDRTEST drivers/gpu/drm/xe/xe_bo_types.h
  HDRTEST drivers/gpu/drm/xe/xe_bo_evict.h
  HDRTEST drivers/gpu/drm/xe/xe_debugfs.h
  HDRTEST drivers/gpu/drm/xe/xe_devcoredump.h
  HDRTEST drivers/gpu/drm/xe/xe_devcoredump_types.h
../drivers/gpu/drm/xe/xe_hw_error.c:865: warning: Function parameter or member 'xe' not described in 'xe_process_hw_errors'
../drivers/gpu/drm/xe/xe_hw_error.c:865: warning: expecting prototype for process_hw_errors(). Prototype was for xe_process_hw_errors() instead
  HDRTEST drivers/gpu/drm/xe/xe_device.h
  HDRTEST drivers/gpu/drm/xe/xe_device_types.h
  HDRTEST drivers/gpu/drm/xe/xe_device_sysfs.h
  HDRTEST drivers/gpu/drm/xe/xe_dma_buf.h
  HDRTEST drivers/gpu/drm/xe/xe_drm_client.h
  HDRTEST drivers/gpu/drm/xe/xe_drv.h
  HDRTEST drivers/gpu/drm/xe/xe_exec.h
  HDRTEST drivers/gpu/drm/xe/xe_exec_queue.h
  HDRTEST drivers/gpu/drm/xe/xe_exec_queue_types.h
  HDRTEST drivers/gpu/drm/xe/xe_execlist.h
  HDRTEST drivers/gpu/drm/xe/xe_execlist_types.h
  HDRTEST drivers/gpu/drm/xe/xe_force_wake.h
  HDRTEST drivers/gpu/drm/xe/xe_force_wake_types.h
  HDRTEST drivers/gpu/drm/xe/xe_ggtt.h
  HDRTEST drivers/gpu/drm/xe/xe_ggtt_types.h
  HDRTEST drivers/gpu/drm/xe/xe_gt.h
  HDRTEST drivers/gpu/drm/xe/xe_gt_clock.h
  HDRTEST drivers/gpu/drm/xe/xe_gt_debugfs.h
  HDRTEST drivers/gpu/drm/xe/xe_gt_idle_sysfs.h
  HDRTEST drivers/gpu/drm/xe/xe_gt_idle_sysfs_types.h
  HDRTEST drivers/gpu/drm/xe/xe_gt_mcr.h
  HDRTEST drivers/gpu/drm/xe/xe_gt_pagefault.h
  HDRTEST drivers/gpu/drm/xe/xe_gt_sysfs.h
  HDRTEST drivers/gpu/drm/xe/xe_gt_printk.h
  HDRTEST drivers/gpu/drm/xe/xe_gt_sysfs_types.h
  HDRTEST drivers/gpu/drm/xe/xe_gt_tlb_invalidation.h
  HDRTEST drivers/gpu/drm/xe/xe_gt_tlb_invalidation_types.h
  HDRTEST drivers/gpu/drm/xe/xe_gt_topology.h
  HDRTEST drivers/gpu/drm/xe/xe_gt_types.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_ads.h
  HDRTEST drivers/gpu/drm/xe/xe_guc.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_ads_types.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_ct.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_ct_types.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_debugfs.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_exec_queue_types.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_fwif.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_hwconfig.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_log.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_log_types.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_pc.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_pc_types.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_submit.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_submit_types.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_types.h
  HDRTEST drivers/gpu/drm/xe/xe_huc.h
  HDRTEST drivers/gpu/drm/xe/xe_huc_debugfs.h
  HDRTEST drivers/gpu/drm/xe/xe_huc_types.h
  HDRTEST drivers/gpu/drm/xe/xe_hw_engine.h
  HDRTEST drivers/gpu/drm/xe/xe_hw_engine_class_sysfs.h
  HDRTEST drivers/gpu/drm/xe/xe_hw_engine_types.h
  HDRTEST drivers/gpu/drm/xe/xe_hw_error.h
  HDRTEST drivers/gpu/drm/xe/xe_hw_fence.h
  HDRTEST drivers/gpu/drm/xe/xe_hw_fence_types.h
  HDRTEST drivers/gpu/drm/xe/xe_irq.h
  HDRTEST drivers/gpu/drm/xe/xe_lrc.h
  HDRTEST drivers/gpu/drm/xe/xe_lrc_types.h
  HDRTEST drivers/gpu/drm/xe/xe_macros.h
  HDRTEST drivers/gpu/drm/xe/xe_map.h
  HDRTEST drivers/gpu/drm/xe/xe_migrate.h
  HDRTEST drivers/gpu/drm/xe/xe_migrate_doc.h
  HDRTEST drivers/gpu/drm/xe/xe_mmio.h
  HDRTEST drivers/gpu/drm/xe/xe_mocs.h
  HDRTEST drivers/gpu/drm/xe/xe_module.h
  HDRTEST drivers/gpu/drm/xe/xe_pat.h
  HDRTEST drivers/gpu/drm/xe/xe_pci.h
  HDRTEST drivers/gpu/drm/xe/xe_pci_types.h
  HDRTEST drivers/gpu/drm/xe/xe_pcode.h
  HDRTEST drivers/gpu/drm/xe/xe_pcode_api.h
  HDRTEST drivers/gpu/drm/xe/xe_platform_types.h
  HDRTEST drivers/gpu/drm/xe/xe_pm.h
  HDRTEST drivers/gpu/drm/xe/xe_pmu.h
  HDRTEST drivers/gpu/drm/xe/xe_pmu_types.h
  HDRTEST drivers/gpu/drm/xe/xe_preempt_fence.h
  HDRTEST drivers/gpu/drm/xe/xe_preempt_fence_types.h
  HDRTEST drivers/gpu/drm/xe/xe_pt.h
  HDRTEST drivers/gpu/drm/xe/xe_pt_types.h
  HDRTEST drivers/gpu/drm/xe/xe_pt_walk.h
  HDRTEST drivers/gpu/drm/xe/xe_query.h
  HDRTEST drivers/gpu/drm/xe/xe_range_fence.h
  HDRTEST drivers/gpu/drm/xe/xe_reg_sr.h
  HDRTEST drivers/gpu/drm/xe/xe_reg_sr_types.h
  HDRTEST drivers/gpu/drm/xe/xe_reg_whitelist.h
  HDRTEST drivers/gpu/drm/xe/xe_res_cursor.h
  HDRTEST drivers/gpu/drm/xe/xe_ring_ops.h
  HDRTEST drivers/gpu/drm/xe/xe_ring_ops_types.h
  HDRTEST drivers/gpu/drm/xe/xe_rtp.h
  HDRTEST drivers/gpu/drm/xe/xe_rtp_types.h
  HDRTEST drivers/gpu/drm/xe/xe_sa.h
  HDRTEST drivers/gpu/drm/xe/xe_sa_types.h
  HDRTEST drivers/gpu/drm/xe/xe_sched_job.h
  HDRTEST drivers/gpu/drm/xe/xe_sched_job_types.h
  HDRTEST drivers/gpu/drm/xe/xe_step.h
  HDRTEST drivers/gpu/drm/xe/xe_step_types.h
  HDRTEST drivers/gpu/drm/xe/xe_sync.h
  HDRTEST drivers/gpu/drm/xe/xe_sync_types.h
  HDRTEST drivers/gpu/drm/xe/xe_tile.h
  HDRTEST drivers/gpu/drm/xe/xe_tile_sysfs.h
  HDRTEST drivers/gpu/drm/xe/xe_tile_sysfs_types.h
  HDRTEST drivers/gpu/drm/xe/xe_trace.h
  HDRTEST drivers/gpu/drm/xe/xe_ttm_stolen_mgr.h
  HDRTEST drivers/gpu/drm/xe/xe_ttm_sys_mgr.h
  HDRTEST drivers/gpu/drm/xe/xe_ttm_vram_mgr.h
  HDRTEST drivers/gpu/drm/xe/xe_ttm_vram_mgr_types.h
  HDRTEST drivers/gpu/drm/xe/xe_tuning.h
  HDRTEST drivers/gpu/drm/xe/xe_uc.h
  HDRTEST drivers/gpu/drm/xe/xe_uc_debugfs.h
  HDRTEST drivers/gpu/drm/xe/xe_uc_fw.h
  HDRTEST drivers/gpu/drm/xe/xe_uc_fw_abi.h
  HDRTEST drivers/gpu/drm/xe/xe_uc_fw_types.h
  HDRTEST drivers/gpu/drm/xe/xe_uc_types.h
  HDRTEST drivers/gpu/drm/xe/xe_vm.h
  HDRTEST drivers/gpu/drm/xe/xe_vm_doc.h
  HDRTEST drivers/gpu/drm/xe/xe_vm_madvise.h
  HDRTEST drivers/gpu/drm/xe/xe_vm_types.h
  HDRTEST drivers/gpu/drm/xe/xe_wa.h
  HDRTEST drivers/gpu/drm/xe/xe_wait_user_fence.h
  HDRTEST drivers/gpu/drm/xe/xe_wopcm.h
  HDRTEST drivers/gpu/drm/xe/xe_wopcm_types.h
  GEN     xe_wa_oob.c xe_wa_oob.h
  GEN     xe_wa_oob.c xe_wa_oob.h
  CC [M]  drivers/gpu/drm/xe/xe_guc.o
  CC [M]  drivers/gpu/drm/xe/xe_migrate.o
  CC [M]  drivers/gpu/drm/xe/xe_ring_ops.o
  CC [M]  drivers/gpu/drm/xe/xe_vm.o
  CC [M]  drivers/gpu/drm/xe/xe_wa.o
  LD [M]  drivers/gpu/drm/xe/xe.o
  MODPOST drivers/gpu/drm/xe/Module.symvers
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/gpu/drm/xe/tests/xe_bo_test.o
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/gpu/drm/xe/tests/xe_dma_buf_test.o
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/gpu/drm/xe/tests/xe_migrate_test.o
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/gpu/drm/xe/tests/xe_pci_test.o
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/gpu/drm/xe/tests/xe_rtp_test.o
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/gpu/drm/xe/tests/xe_wa_test.o
  CC [M]  drivers/gpu/drm/xe/xe.mod.o
  CC [M]  drivers/gpu/drm/xe/tests/xe_bo_test.mod.o
  CC [M]  drivers/gpu/drm/xe/tests/xe_dma_buf_test.mod.o
  CC [M]  drivers/gpu/drm/xe/tests/xe_migrate_test.mod.o
  CC [M]  drivers/gpu/drm/xe/tests/xe_pci_test.mod.o
  CC [M]  drivers/gpu/drm/xe/tests/xe_rtp_test.mod.o
  CC [M]  drivers/gpu/drm/xe/tests/xe_wa_test.mod.o
  LD [M]  drivers/gpu/drm/xe/tests/xe_migrate_test.ko
  LD [M]  drivers/gpu/drm/xe/tests/xe_rtp_test.ko
  LD [M]  drivers/gpu/drm/xe/tests/xe_bo_test.ko
  LD [M]  drivers/gpu/drm/xe/tests/xe_pci_test.ko
  LD [M]  drivers/gpu/drm/xe/xe.ko
  LD [M]  drivers/gpu/drm/xe/tests/xe_wa_test.ko
  LD [M]  drivers/gpu/drm/xe/tests/xe_dma_buf_test.ko
make[1]: Leaving directory '/workspace/kernel/build64-default'
+ cleanup
+ '[' 1 -eq 1 ']'
+ ./scripts/config --file /workspace/kernel/build64-default/.config --enable CONFIG_DRM_XE_DISPLAY
run-parts: executing /workspace/ci/hooks/20-kernel-doc
+ SRC_DIR=/workspace/kernel
+ cd /workspace/kernel
+ find drivers/gpu/drm/xe/ -name '*.[ch]' -not -path 'drivers/gpu/drm/xe/display/*'
+ xargs ./scripts/kernel-doc -Werror -none include/uapi/drm/xe_drm.h
drivers/gpu/drm/xe/xe_device_types.h:186: warning: Function parameter or member 'errors' not described in 'xe_tile'
drivers/gpu/drm/xe/xe_device_types.h:479: warning: Function parameter or member 'hw_err_regs' not described in 'xe_device'
drivers/gpu/drm/xe/xe_hw_error.c:866: warning: Function parameter or member 'xe' not described in 'xe_process_hw_errors'
drivers/gpu/drm/xe/xe_hw_error.c:866: warning: expecting prototype for process_hw_errors(). Prototype was for xe_process_hw_errors() instead
drivers/gpu/drm/xe/xe_gt_types.h:358: warning: Function parameter or member 'errors' not described in 'xe_gt'
5 warnings as Errors
run-parts: /workspace/ci/hooks/20-kernel-doc exited with return code 123

[Intel-xe] ✓ CI.checksparse: success for Supporting CSC and SOC HARDWARE ERROR HANDLING on PVC

[Patchwork]

== Series Details ==

Series: Supporting CSC and SOC HARDWARE ERROR HANDLING on PVC
URL   : https://patchwork.freedesktop.org/series/124331/
State : success

== Summary ==

+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast fc8ec3c56efa5c15b630ddc17c89100440fe03ef
Sparse version: 0.6.1 (Ubuntu: 0.6.1-2build1)
Fast mode used, each commit won't be checked separately.
Okay!

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

[Intel-xe] ✗ CI.BAT: failure for Supporting CSC and SOC HARDWARE ERROR HANDLING on PVC

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 3082 bytes --]

== Series Details ==

Series: Supporting CSC and SOC HARDWARE ERROR HANDLING on PVC
URL   : https://patchwork.freedesktop.org/series/124331/
State : failure

== Summary ==

CI Bug Log - changes from xe-396-fc8ec3c56efa5c15b630ddc17c89100440fe03ef_BAT -> xe-pw-124331v1_BAT
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-124331v1_BAT absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-124331v1_BAT, please notify your bug team (lgci.bug.filing@intel.com) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-124331v1_BAT:

### IGT changes ###

#### Possible regressions ####

  * igt@xe_module_load@load:
    - bat-dg2-oem2:       [PASS][1] -> [DMESG-WARN][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-396-fc8ec3c56efa5c15b630ddc17c89100440fe03ef/bat-dg2-oem2/igt@xe_module_load@load.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-124331v1/bat-dg2-oem2/igt@xe_module_load@load.html
    - bat-atsm-2:         [PASS][3] -> [DMESG-WARN][4]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-396-fc8ec3c56efa5c15b630ddc17c89100440fe03ef/bat-atsm-2/igt@xe_module_load@load.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-124331v1/bat-atsm-2/igt@xe_module_load@load.html

  
Known issues
------------

  Here are the changes found in xe-pw-124331v1_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_flip@basic-flip-vs-wf_vblank@c-dp3:
    - bat-dg2-oem2:       [PASS][5] -> [FAIL][6] ([Intel XE#554]) +2 other tests fail
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-396-fc8ec3c56efa5c15b630ddc17c89100440fe03ef/bat-dg2-oem2/igt@kms_flip@basic-flip-vs-wf_vblank@c-dp3.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-124331v1/bat-dg2-oem2/igt@kms_flip@basic-flip-vs-wf_vblank@c-dp3.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#524]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/524
  [Intel XE#554]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/554


Build changes
-------------

  * IGT: IGT_7502 -> IGT_7506
  * Linux: xe-396-fc8ec3c56efa5c15b630ddc17c89100440fe03ef -> xe-pw-124331v1

  IGT_7502: ac56ba97248b33668fbe771882360bd7b274cc9a @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  IGT_7506: 4fdf544bd0a38c5a100ef43c30171827e1c8c442 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-396-fc8ec3c56efa5c15b630ddc17c89100440fe03ef: fc8ec3c56efa5c15b630ddc17c89100440fe03ef
  xe-pw-124331v1: 124331v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-124331v1/index.html

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