* [PATCH v5 0/2] Rework/Correction on minimum hblank calculation
@ 2025-04-23 12:53 Arun R Murthy
2025-04-23 12:53 ` [PATCH v5 1/2] drm/display/dp: Export fn to calculate link symbol cycles Arun R Murthy
2025-04-23 12:53 ` [PATCH v5 2/2] drm/i915/display: move min_hblank from dp_mst.c to dp.c Arun R Murthy
0 siblings, 2 replies; 5+ messages in thread
From: Arun R Murthy @ 2025-04-23 12:53 UTC (permalink / raw)
To: intel-gfx, intel-xe, dri-devel
Cc: imre.deak, vinod.govindapillai, Arun R Murthy
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
Changes in v5:
- EDITME: describe what is new in this series revision.
- EDITME: use bulletpoints and terse descriptions.
- Link to v4: https://lore.kernel.org/r/20250423-hblank-v4-0-8e513cc54652@intel.com
Changes in v5:
- EDITME: describe what is new in this series revision.
- EDITME: use bulletpoints and terse descriptions.
- Link to v4: https://lore.kernel.org/r/20250422-hblank-v4-0-bdb7bd9c486c@intel.com
Changes in v3:
- EDITME: describe what is new in this series revision.
- EDITME: use bulletpoints and terse descriptions.
- Link to v2: https://lore.kernel.org/r/20250415-hblank-v2-0-1a23e9d97360@intel.com
Changes in v2:
- EDITME: describe what is new in this series revision.
- EDITME: use bulletpoints and terse descriptions.
- Link to v1: https://lore.kernel.org/r/20250408-hblank-v1-0-4ba17aebee65@intel.com
---
Arun R Murthy (2):
drm/display/dp: Export fn to calculate link symbol cycles
drm/i915/display: move min_hblank from dp_mst.c to dp.c
drivers/gpu/drm/display/drm_dp_helper.c | 51 ++++++++++++-------
drivers/gpu/drm/i915/display/intel_display.c | 18 +++++++
drivers/gpu/drm/i915/display/intel_dp.c | 76 ++++++++++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dp.h | 3 ++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 57 +++------------------
include/drm/display/drm_dp_helper.h | 2 +
6 files changed, 138 insertions(+), 69 deletions(-)
---
base-commit: ada794bd93930fd265c2df8f38196994173e1fde
change-id: 20250407-hblank-49b340aeba31
Best regards,
--
Arun R Murthy <arun.r.murthy@intel.com>
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v5 1/2] drm/display/dp: Export fn to calculate link symbol cycles
2025-04-23 12:53 [PATCH v5 0/2] Rework/Correction on minimum hblank calculation Arun R Murthy
@ 2025-04-23 12:53 ` Arun R Murthy
2025-04-23 13:42 ` Imre Deak
2025-04-23 12:53 ` [PATCH v5 2/2] drm/i915/display: move min_hblank from dp_mst.c to dp.c Arun R Murthy
1 sibling, 1 reply; 5+ messages in thread
From: Arun R Murthy @ 2025-04-23 12:53 UTC (permalink / raw)
To: intel-gfx, intel-xe, dri-devel
Cc: imre.deak, vinod.govindapillai, Arun R Murthy
Unify the function to calculate the link symbol cycles for both dsc and
non-dsc case and export the function so that it can be used in the
respective platform display drivers for other calculations.
v2: unify the fn for both dsc and non-dsc case (Imre)
v3: rename drm_dp_link_symbol_cycles to drm_dp_link_data_symbol_cycles
retain slice_eoc_cycles as is (Imre)
v4: Expose only drm_dp_link_symbol_cycles() (Imre)
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
drivers/gpu/drm/display/drm_dp_helper.c | 51 +++++++++++++++++++++------------
include/drm/display/drm_dp_helper.h | 2 ++
2 files changed, 35 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
index 57828f2b7b5a0582ca4a6f2a9be2d5909fe8ad24..d33a46016504ce52857b7c4e63d866af9c1eff34 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -4393,8 +4393,9 @@ EXPORT_SYMBOL(drm_panel_dp_aux_backlight);
#endif
/* See DP Standard v2.1 2.6.4.4.1.1, 2.8.4.4, 2.8.7 */
-static int drm_dp_link_symbol_cycles(int lane_count, int pixels, int bpp_x16,
- int symbol_size, bool is_mst)
+static int drm_dp_link_data_symbol_cycles(int lane_count, int pixels,
+ int bpp_x16, int symbol_size,
+ bool is_mst)
{
int cycles = DIV_ROUND_UP(pixels * bpp_x16, 16 * symbol_size * lane_count);
int align = is_mst ? 4 / lane_count : 1;
@@ -4402,22 +4403,41 @@ static int drm_dp_link_symbol_cycles(int lane_count, int pixels, int bpp_x16,
return ALIGN(cycles, align);
}
-static int drm_dp_link_dsc_symbol_cycles(int lane_count, int pixels, int slice_count,
- int bpp_x16, int symbol_size, bool is_mst)
+/**
+ * drm_dp_link_symbol_cycles - calculate the link symbol count with/without dsc
+ * @lane_count: DP link lane count
+ * @pixels: number of pixels in a scanline
+ * @dsc_slice_count: number of slices
+ * @bpp_x16: bits per pixel in .4 binary fixed format
+ * @symbol_size: DP symbol size
+ * @is_mst: %true for MST and %false for SST
+ *
+ * Calculate the link symbol cycles for both DSC(@dsc_slice_count !=0) and
+ * non-DSC case(@dsc_slice_count == 0)and return the count.
+ */
+int drm_dp_link_symbol_cycles(int lane_count, int pixels, int dsc_slice_count,
+ int bpp_x16, int symbol_size, bool is_mst)
{
- int slice_pixels = DIV_ROUND_UP(pixels, slice_count);
- int slice_data_cycles = drm_dp_link_symbol_cycles(lane_count, slice_pixels,
- bpp_x16, symbol_size, is_mst);
- int slice_eoc_cycles = is_mst ? 4 / lane_count : 1;
+ int slice_count = dsc_slice_count ? : 1;
+ int slice_data_cycles = drm_dp_link_data_symbol_cycles(lane_count,
+ pixels,
+ bpp_x16,
+ symbol_size,
+ is_mst);
+ int slice_eoc_cycles = 0;
+
+ if (dsc_slice_count)
+ slice_eoc_cycles = is_mst ? 4 / lane_count : 1;
return slice_count * (slice_data_cycles + slice_eoc_cycles);
}
+EXPORT_SYMBOL(drm_dp_link_symbol_cycles);
/**
* drm_dp_bw_overhead - Calculate the BW overhead of a DP link stream
* @lane_count: DP link lane count
* @hactive: pixel count of the active period in one scanline of the stream
- * @dsc_slice_count: DSC slice count if @flags/DRM_DP_LINK_BW_OVERHEAD_DSC is set
+ * @dsc_slice_count: number of slices
* @bpp_x16: bits per pixel in .4 binary fixed point
* @flags: DRM_DP_OVERHEAD_x flags
*
@@ -4486,15 +4506,10 @@ int drm_dp_bw_overhead(int lane_count, int hactive,
WARN_ON((flags & DRM_DP_BW_OVERHEAD_UHBR) &&
(flags & DRM_DP_BW_OVERHEAD_FEC));
- if (flags & DRM_DP_BW_OVERHEAD_DSC)
- symbol_cycles = drm_dp_link_dsc_symbol_cycles(lane_count, hactive,
- dsc_slice_count,
- bpp_x16, symbol_size,
- is_mst);
- else
- symbol_cycles = drm_dp_link_symbol_cycles(lane_count, hactive,
- bpp_x16, symbol_size,
- is_mst);
+ symbol_cycles = drm_dp_link_symbol_cycles(lane_count, hactive,
+ dsc_slice_count,
+ bpp_x16, symbol_size,
+ is_mst);
return DIV_ROUND_UP_ULL(mul_u32_u32(symbol_cycles * symbol_size * lane_count,
overhead * 16),
diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
index d9614e2c89397536f44bb7258e894628ae1dccc9..7b19192c70313d66dce1b7ba40dd59c14f80a182 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -971,5 +971,7 @@ int drm_dp_bw_channel_coding_efficiency(bool is_uhbr);
int drm_dp_max_dprx_data_rate(int max_link_rate, int max_lanes);
ssize_t drm_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, struct dp_sdp *sdp);
+int drm_dp_link_symbol_cycles(int lane_count, int pixels, int dsc_slice_count,
+ int bpp_x16, int symbol_size, bool is_mst);
#endif /* _DRM_DP_HELPER_H_ */
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v5 2/2] drm/i915/display: move min_hblank from dp_mst.c to dp.c
2025-04-23 12:53 [PATCH v5 0/2] Rework/Correction on minimum hblank calculation Arun R Murthy
2025-04-23 12:53 ` [PATCH v5 1/2] drm/display/dp: Export fn to calculate link symbol cycles Arun R Murthy
@ 2025-04-23 12:53 ` Arun R Murthy
2025-04-23 14:39 ` Imre Deak
1 sibling, 1 reply; 5+ messages in thread
From: Arun R Murthy @ 2025-04-23 12:53 UTC (permalink / raw)
To: intel-gfx, intel-xe, dri-devel
Cc: imre.deak, vinod.govindapillai, Arun R Murthy
Minimum HBlank is programmed to address jitter for high resolutions with
high refresh rates that have small Hblank, specifically where Hblank is
smaller than one MTP.
TODO: Add the min_hblank calculation for hdmi as well.
v2: move from intel_audio.c to intel_dp.c
some correction in link_bpp_x16 (Imre)
v3: min_hblank for 8b/10b MST and 128b/132b SST/MST
handle error for intel_dp_mst_dsc_get_slice_count
reset min_hblank before disabling transcoder (Imre)
v4: compute link_bpp_x16 within compute_min_hblank,
return error in case of compute failure
call compute_min_hblank() before vrr_compute_config (Imre)
v5: readout MIN_HBLAN reg for Xe3+
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 18 +++++++
drivers/gpu/drm/i915/display/intel_dp.c | 76 ++++++++++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dp.h | 3 ++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 57 +++------------------
4 files changed, 103 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 33c09999c42e046c7a8b6e6143be0b81650ee7f7..5e28f63e4d719bd605f20fd72d281c753bfbba5f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2723,6 +2723,19 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
intel_de_write(display, TRANS_VTOTAL(display, pipe),
VACTIVE(crtc_vdisplay - 1) |
VTOTAL(crtc_vtotal - 1));
+
+ if (DISPLAY_VER(display) >= 30) {
+ /*
+ * Address issues for resolutions with high refresh rate that
+ * have small Hblank, specifically where Hblank is smaller than
+ * one MTP. Simulations indicate this will address the
+ * jitter issues that currently causes BS to be immediately
+ * followed by BE which DPRX devices are unable to handle.
+ * https://groups.vesa.org/wg/DP/document/20494
+ */
+ intel_de_write(display, DP_MIN_HBLANK_CTL(cpu_transcoder),
+ crtc_state->min_hblank);
+ }
}
static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state)
@@ -2866,6 +2879,9 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
adjusted_mode->crtc_vdisplay +
intel_de_read(display,
TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder));
+ if (DISPLAY_VER(display) >= 30)
+ pipe_config->min_hblank = intel_de_read(display,
+ DP_MIN_HBLANK_CTL(cpu_transcoder));
}
static void intel_joiner_adjust_pipe_src(struct intel_crtc_state *crtc_state)
@@ -5216,6 +5232,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_I(lane_count);
PIPE_CONF_CHECK_X(lane_lat_optim_mask);
+ PIPE_CONF_CHECK_I(min_hblank);
+
if (HAS_DOUBLE_BUFFERED_M_N(display)) {
if (!fastset || !pipe_config->update_m_n)
PIPE_CONF_CHECK_M_N(dp_m_n);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index d7a30d0992b7a65250a3abfecde876321326fa84..c18889cecaf40cd6599adbb3ae0f0feb0c95990f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3104,6 +3104,77 @@ intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state,
}
}
+int intel_dp_compute_min_hblank(struct intel_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state,
+ bool is_dsc)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->hw.adjusted_mode;
+ struct intel_connector *connector = to_intel_connector(conn_state->connector);
+ int symbol_size = intel_dp_is_uhbr(crtc_state) ? 32 : 8;
+ /*
+ * min symbol cycles is 3(BS,VBID, BE) for 128b/132b and
+ * 5(BS, VBID, MVID, MAUD, BE) for 8b/10b
+ */
+ int min_sym_cycles = intel_dp_is_uhbr(crtc_state) ? 3 : 5;
+ bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
+ int num_joined_pipes = intel_crtc_num_joined_pipes(crtc_state);
+ int min_hblank;
+ int max_lane_count = 4;
+ int hactive_sym_cycles, htotal_sym_cycles;
+ int dsc_slices = 0;
+ int link_bpp_x16;
+
+ if (DISPLAY_VER(display) < 30)
+ return 0;
+
+ /* MIN_HBLANK should be set only for 8b/10b MST or for 128b/132b SST/MST */
+ if (!is_mst && !intel_dp_is_uhbr(crtc_state))
+ return 0;
+
+ if (is_dsc) {
+ dsc_slices = intel_dp_dsc_get_slice_count(connector,
+ adjusted_mode->crtc_clock,
+ adjusted_mode->crtc_hdisplay,
+ num_joined_pipes);
+ if (!dsc_slices) {
+ drm_dbg(display->drm, "failed to calculate dsc slice count\n");
+ return -EINVAL;
+ }
+ }
+
+ if (crtc_state->dsc.compression_enable)
+ link_bpp_x16 = crtc_state->dsc.compressed_bpp_x16;
+ else
+ link_bpp_x16 = fxp_q4_from_int(intel_dp_output_bpp(crtc_state->output_format,
+ crtc_state->pipe_bpp));
+
+ /* Calculate min Hblank Link Layer Symbol Cycle Count for 8b/10b MST & 128b/132b */
+ hactive_sym_cycles = drm_dp_link_symbol_cycles(max_lane_count,
+ adjusted_mode->hdisplay,
+ dsc_slices,
+ link_bpp_x16,
+ symbol_size, is_mst);
+ htotal_sym_cycles = (adjusted_mode->htotal * hactive_sym_cycles) /
+ adjusted_mode->hdisplay;
+
+ min_hblank = htotal_sym_cycles - hactive_sym_cycles;
+ /* minimum Hblank calculation: https://groups.vesa.org/wg/DP/document/20494 */
+ min_hblank = max(min_hblank, min_sym_cycles);
+
+ /*
+ * adjust the BlankingStart/BlankingEnd framing control from
+ * the calculated value
+ */
+ min_hblank = min_hblank - 2;
+
+ min_hblank = min(10, min_hblank);
+ crtc_state->min_hblank = min_hblank;
+
+ return 0;
+}
+
int
intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
@@ -3203,6 +3274,11 @@ intel_dp_compute_config(struct intel_encoder *encoder,
&pipe_config->dp_m_n);
}
+ ret = intel_dp_compute_min_hblank(pipe_config, conn_state,
+ pipe_config->dsc.compression_enable);
+ if (ret)
+ return ret;
+
/* FIXME: abstract this better */
if (pipe_config->splitter.enable)
pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 9189db4c25946a0f082223ce059c242e80cc32dc..6f2f048295ecaa6cc1f967dc7b3b4cc75f3344c0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -208,5 +208,8 @@ bool intel_dp_has_connector(struct intel_dp *intel_dp,
const struct drm_connector_state *conn_state);
int intel_dp_dsc_max_src_input_bpc(struct intel_display *display);
int intel_dp_dsc_min_src_input_bpc(void);
+int intel_dp_compute_min_hblank(struct intel_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state,
+ bool is_dsc);
#endif /* __INTEL_DP_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 4c15dcb103aa2ed5650cbbef8c12be53132e6a80..1108c3749d812a45d1675297220dad23969750fe 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -239,26 +239,6 @@ static int intel_dp_mst_dsc_get_slice_count(const struct intel_connector *connec
num_joined_pipes);
}
-static void intel_dp_mst_compute_min_hblank(struct intel_crtc_state *crtc_state,
- int bpp_x16)
-{
- struct intel_display *display = to_intel_display(crtc_state);
- const struct drm_display_mode *adjusted_mode =
- &crtc_state->hw.adjusted_mode;
- int symbol_size = intel_dp_is_uhbr(crtc_state) ? 32 : 8;
- int hblank;
-
- if (DISPLAY_VER(display) < 20)
- return;
-
- /* Calculate min Hblank Link Layer Symbol Cycle Count for 8b/10b MST & 128b/132b */
- hblank = DIV_ROUND_UP((DIV_ROUND_UP
- (adjusted_mode->htotal - adjusted_mode->hdisplay, 4) * bpp_x16),
- symbol_size);
-
- crtc_state->min_hblank = hblank;
-}
-
int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state,
@@ -329,8 +309,6 @@ int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp,
local_bw_overhead = intel_dp_mst_bw_overhead(crtc_state,
false, dsc_slice_count, link_bpp_x16);
- intel_dp_mst_compute_min_hblank(crtc_state, link_bpp_x16);
-
intel_dp_mst_compute_m_n(crtc_state,
local_bw_overhead,
link_bpp_x16,
@@ -739,6 +717,11 @@ static int mst_stream_compute_config(struct intel_encoder *encoder,
pipe_config->lane_lat_optim_mask =
bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
+ ret = intel_dp_compute_min_hblank(pipe_config, conn_state,
+ pipe_config->dsc.compression_enable);
+ if (ret)
+ return ret;
+
intel_vrr_compute_config(pipe_config, conn_state);
intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
@@ -1021,12 +1004,10 @@ static void mst_stream_disable(struct intel_atomic_state *state,
const struct intel_crtc_state *old_crtc_state,
const struct drm_connector_state *old_conn_state)
{
- struct intel_display *display = to_intel_display(state);
struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
struct intel_dp *intel_dp = to_primary_dp(encoder);
struct intel_connector *connector =
to_intel_connector(old_conn_state->connector);
- enum transcoder trans = old_crtc_state->cpu_transcoder;
if (intel_dp_mst_active_streams(intel_dp) == 1)
intel_dp->link.active = false;
@@ -1034,9 +1015,6 @@ static void mst_stream_disable(struct intel_atomic_state *state,
intel_hdcp_disable(intel_mst->connector);
intel_dp_sink_disable_decompression(state, connector, old_crtc_state);
-
- if (DISPLAY_VER(display) >= 20)
- intel_de_write(display, DP_MIN_HBLANK_CTL(trans), 0);
}
static void mst_stream_post_disable(struct intel_atomic_state *state,
@@ -1305,7 +1283,7 @@ static void mst_stream_enable(struct intel_atomic_state *state,
enum transcoder trans = pipe_config->cpu_transcoder;
bool first_mst_stream = intel_dp_mst_active_streams(intel_dp) == 1;
struct intel_crtc *pipe_crtc;
- int ret, i, min_hblank;
+ int ret, i;
drm_WARN_ON(display->drm, pipe_config->has_pch_encoder);
@@ -1320,29 +1298,6 @@ static void mst_stream_enable(struct intel_atomic_state *state,
TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff));
}
- if (DISPLAY_VER(display) >= 20) {
- /*
- * adjust the BlankingStart/BlankingEnd framing control from
- * the calculated value
- */
- min_hblank = pipe_config->min_hblank - 2;
-
- /* Maximum value to be programmed is limited to 0x10 */
- min_hblank = min(0x10, min_hblank);
-
- /*
- * Minimum hblank accepted for 128b/132b would be 5 and for
- * 8b/10b would be 3 symbol count
- */
- if (intel_dp_is_uhbr(pipe_config))
- min_hblank = max(min_hblank, 5);
- else
- min_hblank = max(min_hblank, 3);
-
- intel_de_write(display, DP_MIN_HBLANK_CTL(trans),
- min_hblank);
- }
-
enable_bs_jitter_was(pipe_config);
intel_ddi_enable_transcoder_func(encoder, pipe_config);
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v5 1/2] drm/display/dp: Export fn to calculate link symbol cycles
2025-04-23 12:53 ` [PATCH v5 1/2] drm/display/dp: Export fn to calculate link symbol cycles Arun R Murthy
@ 2025-04-23 13:42 ` Imre Deak
0 siblings, 0 replies; 5+ messages in thread
From: Imre Deak @ 2025-04-23 13:42 UTC (permalink / raw)
To: Arun R Murthy; +Cc: intel-gfx, intel-xe, dri-devel, vinod.govindapillai
On Wed, Apr 23, 2025 at 06:23:33PM +0530, Arun R Murthy wrote:
> Unify the function to calculate the link symbol cycles for both dsc and
> non-dsc case and export the function so that it can be used in the
> respective platform display drivers for other calculations.
>
> v2: unify the fn for both dsc and non-dsc case (Imre)
> v3: rename drm_dp_link_symbol_cycles to drm_dp_link_data_symbol_cycles
> retain slice_eoc_cycles as is (Imre)
> v4: Expose only drm_dp_link_symbol_cycles() (Imre)
>
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> ---
> drivers/gpu/drm/display/drm_dp_helper.c | 51 +++++++++++++++++++++------------
> include/drm/display/drm_dp_helper.h | 2 ++
> 2 files changed, 35 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
> index 57828f2b7b5a0582ca4a6f2a9be2d5909fe8ad24..d33a46016504ce52857b7c4e63d866af9c1eff34 100644
> --- a/drivers/gpu/drm/display/drm_dp_helper.c
> +++ b/drivers/gpu/drm/display/drm_dp_helper.c
> @@ -4393,8 +4393,9 @@ EXPORT_SYMBOL(drm_panel_dp_aux_backlight);
> #endif
>
> /* See DP Standard v2.1 2.6.4.4.1.1, 2.8.4.4, 2.8.7 */
> -static int drm_dp_link_symbol_cycles(int lane_count, int pixels, int bpp_x16,
> - int symbol_size, bool is_mst)
> +static int drm_dp_link_data_symbol_cycles(int lane_count, int pixels,
> + int bpp_x16, int symbol_size,
> + bool is_mst)
> {
> int cycles = DIV_ROUND_UP(pixels * bpp_x16, 16 * symbol_size * lane_count);
> int align = is_mst ? 4 / lane_count : 1;
> @@ -4402,22 +4403,41 @@ static int drm_dp_link_symbol_cycles(int lane_count, int pixels, int bpp_x16,
> return ALIGN(cycles, align);
> }
>
> -static int drm_dp_link_dsc_symbol_cycles(int lane_count, int pixels, int slice_count,
> - int bpp_x16, int symbol_size, bool is_mst)
> +/**
> + * drm_dp_link_symbol_cycles - calculate the link symbol count with/without dsc
> + * @lane_count: DP link lane count
> + * @pixels: number of pixels in a scanline
> + * @dsc_slice_count: number of slices
Nit: missed in my previous review, but could be clearer by:
@dsc_slice_count: number of slices for DSC or 0 for non-DSC
> + * @bpp_x16: bits per pixel in .4 binary fixed format
> + * @symbol_size: DP symbol size
> + * @is_mst: %true for MST and %false for SST
> + *
> + * Calculate the link symbol cycles for both DSC(@dsc_slice_count !=0) and
> + * non-DSC case(@dsc_slice_count == 0)and return the count.
Nit: keep one space before '(' and after ')'.
> + */
> +int drm_dp_link_symbol_cycles(int lane_count, int pixels, int dsc_slice_count,
> + int bpp_x16, int symbol_size, bool is_mst)
> {
> - int slice_pixels = DIV_ROUND_UP(pixels, slice_count);
> - int slice_data_cycles = drm_dp_link_symbol_cycles(lane_count, slice_pixels,
> - bpp_x16, symbol_size, is_mst);
> - int slice_eoc_cycles = is_mst ? 4 / lane_count : 1;
> + int slice_count = dsc_slice_count ? : 1;
> + int slice_data_cycles = drm_dp_link_data_symbol_cycles(lane_count,
> + pixels,
> + bpp_x16,
> + symbol_size,
> + is_mst);
> + int slice_eoc_cycles = 0;
> +
> + if (dsc_slice_count)
> + slice_eoc_cycles = is_mst ? 4 / lane_count : 1;
>
> return slice_count * (slice_data_cycles + slice_eoc_cycles);
> }
> +EXPORT_SYMBOL(drm_dp_link_symbol_cycles);
>
> /**
> * drm_dp_bw_overhead - Calculate the BW overhead of a DP link stream
> * @lane_count: DP link lane count
> * @hactive: pixel count of the active period in one scanline of the stream
> - * @dsc_slice_count: DSC slice count if @flags/DRM_DP_LINK_BW_OVERHEAD_DSC is set
> + * @dsc_slice_count: number of slices
Same nit as the above @dsc_slice_count one.
> * @bpp_x16: bits per pixel in .4 binary fixed point
> * @flags: DRM_DP_OVERHEAD_x flags
There is one more place referring to %DRM_DP_OVERHEAD_DSC in this
comment, could be changed to:
* - compression mode (@dsc_slice_count != 0)
Regardless of the nits, patch looks ok, thanks:
Reviewed-by: Imre Deak <imre.deak@intel.com>
After this patch DRM_DP_BW_OVERHEAD_DSC will be only set by the i915
driver, but it won't be used anywhere, so in a follow patch the flag
could be removed.
> *
> @@ -4486,15 +4506,10 @@ int drm_dp_bw_overhead(int lane_count, int hactive,
> WARN_ON((flags & DRM_DP_BW_OVERHEAD_UHBR) &&
> (flags & DRM_DP_BW_OVERHEAD_FEC));
>
> - if (flags & DRM_DP_BW_OVERHEAD_DSC)
> - symbol_cycles = drm_dp_link_dsc_symbol_cycles(lane_count, hactive,
> - dsc_slice_count,
> - bpp_x16, symbol_size,
> - is_mst);
> - else
> - symbol_cycles = drm_dp_link_symbol_cycles(lane_count, hactive,
> - bpp_x16, symbol_size,
> - is_mst);
> + symbol_cycles = drm_dp_link_symbol_cycles(lane_count, hactive,
> + dsc_slice_count,
> + bpp_x16, symbol_size,
> + is_mst);
>
> return DIV_ROUND_UP_ULL(mul_u32_u32(symbol_cycles * symbol_size * lane_count,
> overhead * 16),
> diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
> index d9614e2c89397536f44bb7258e894628ae1dccc9..7b19192c70313d66dce1b7ba40dd59c14f80a182 100644
> --- a/include/drm/display/drm_dp_helper.h
> +++ b/include/drm/display/drm_dp_helper.h
> @@ -971,5 +971,7 @@ int drm_dp_bw_channel_coding_efficiency(bool is_uhbr);
> int drm_dp_max_dprx_data_rate(int max_link_rate, int max_lanes);
>
> ssize_t drm_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, struct dp_sdp *sdp);
> +int drm_dp_link_symbol_cycles(int lane_count, int pixels, int dsc_slice_count,
> + int bpp_x16, int symbol_size, bool is_mst);
>
> #endif /* _DRM_DP_HELPER_H_ */
>
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v5 2/2] drm/i915/display: move min_hblank from dp_mst.c to dp.c
2025-04-23 12:53 ` [PATCH v5 2/2] drm/i915/display: move min_hblank from dp_mst.c to dp.c Arun R Murthy
@ 2025-04-23 14:39 ` Imre Deak
0 siblings, 0 replies; 5+ messages in thread
From: Imre Deak @ 2025-04-23 14:39 UTC (permalink / raw)
To: Arun R Murthy; +Cc: intel-gfx, intel-xe, dri-devel, vinod.govindapillai
On Wed, Apr 23, 2025 at 06:23:34PM +0530, Arun R Murthy wrote:
> Minimum HBlank is programmed to address jitter for high resolutions with
> high refresh rates that have small Hblank, specifically where Hblank is
> smaller than one MTP.
The log could've mentioned what the patch actually does (at least: add
programming for UHBR SST, use the correct link_bpp_x16 factor, fix the
min_hblank formula wrt. dsc, fix the platform check, add HW state
verification).
>
> TODO: Add the min_hblank calculation for hdmi as well.
>
> v2: move from intel_audio.c to intel_dp.c
> some correction in link_bpp_x16 (Imre)
> v3: min_hblank for 8b/10b MST and 128b/132b SST/MST
> handle error for intel_dp_mst_dsc_get_slice_count
> reset min_hblank before disabling transcoder (Imre)
> v4: compute link_bpp_x16 within compute_min_hblank,
> return error in case of compute failure
> call compute_min_hblank() before vrr_compute_config (Imre)
> v5: readout MIN_HBLAN reg for Xe3+
>
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 18 +++++++
> drivers/gpu/drm/i915/display/intel_dp.c | 76 ++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_dp.h | 3 ++
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 57 +++------------------
> 4 files changed, 103 insertions(+), 51 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 33c09999c42e046c7a8b6e6143be0b81650ee7f7..5e28f63e4d719bd605f20fd72d281c753bfbba5f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2723,6 +2723,19 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
> intel_de_write(display, TRANS_VTOTAL(display, pipe),
> VACTIVE(crtc_vdisplay - 1) |
> VTOTAL(crtc_vtotal - 1));
> +
> + if (DISPLAY_VER(display) >= 30) {
> + /*
> + * Address issues for resolutions with high refresh rate that
> + * have small Hblank, specifically where Hblank is smaller than
> + * one MTP. Simulations indicate this will address the
> + * jitter issues that currently causes BS to be immediately
> + * followed by BE which DPRX devices are unable to handle.
> + * https://groups.vesa.org/wg/DP/document/20494
> + */
> + intel_de_write(display, DP_MIN_HBLANK_CTL(cpu_transcoder),
> + crtc_state->min_hblank);
> + }
> }
>
> static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state)
> @@ -2866,6 +2879,9 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
> adjusted_mode->crtc_vdisplay +
> intel_de_read(display,
> TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder));
Nit: could've added an empty new line here.
> + if (DISPLAY_VER(display) >= 30)
> + pipe_config->min_hblank = intel_de_read(display,
> + DP_MIN_HBLANK_CTL(cpu_transcoder));
> }
>
> static void intel_joiner_adjust_pipe_src(struct intel_crtc_state *crtc_state)
> @@ -5216,6 +5232,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> PIPE_CONF_CHECK_I(lane_count);
> PIPE_CONF_CHECK_X(lane_lat_optim_mask);
>
> + PIPE_CONF_CHECK_I(min_hblank);
> +
> if (HAS_DOUBLE_BUFFERED_M_N(display)) {
> if (!fastset || !pipe_config->update_m_n)
> PIPE_CONF_CHECK_M_N(dp_m_n);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index d7a30d0992b7a65250a3abfecde876321326fa84..c18889cecaf40cd6599adbb3ae0f0feb0c95990f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3104,6 +3104,77 @@ intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state,
> }
> }
>
> +int intel_dp_compute_min_hblank(struct intel_crtc_state *crtc_state,
> + struct drm_connector_state *conn_state,
The above has an indent problem and the pointer could be const.
> + bool is_dsc)
No need for a separate is_dsc param, since it's just
crtc_state->dsc.compression_enable, and crtc_state is also passed.
> +{
> + struct intel_display *display = to_intel_display(crtc_state);
> + const struct drm_display_mode *adjusted_mode =
> + &crtc_state->hw.adjusted_mode;
> + struct intel_connector *connector = to_intel_connector(conn_state->connector);
> + int symbol_size = intel_dp_is_uhbr(crtc_state) ? 32 : 8;
> + /*
> + * min symbol cycles is 3(BS,VBID, BE) for 128b/132b and
> + * 5(BS, VBID, MVID, MAUD, BE) for 8b/10b
> + */
> + int min_sym_cycles = intel_dp_is_uhbr(crtc_state) ? 3 : 5;
> + bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
> + int num_joined_pipes = intel_crtc_num_joined_pipes(crtc_state);
> + int min_hblank;
> + int max_lane_count = 4;
> + int hactive_sym_cycles, htotal_sym_cycles;
> + int dsc_slices = 0;
> + int link_bpp_x16;
> +
> + if (DISPLAY_VER(display) < 30)
> + return 0;
> +
> + /* MIN_HBLANK should be set only for 8b/10b MST or for 128b/132b SST/MST */
> + if (!is_mst && !intel_dp_is_uhbr(crtc_state))
> + return 0;
> +
> + if (is_dsc) {
> + dsc_slices = intel_dp_dsc_get_slice_count(connector,
> + adjusted_mode->crtc_clock,
> + adjusted_mode->crtc_hdisplay,
> + num_joined_pipes);
The above params have an indent problem.
> + if (!dsc_slices) {
> + drm_dbg(display->drm, "failed to calculate dsc slice count\n");
> + return -EINVAL;
> + }
> + }
> +
> + if (crtc_state->dsc.compression_enable)
> + link_bpp_x16 = crtc_state->dsc.compressed_bpp_x16;
> + else
> + link_bpp_x16 = fxp_q4_from_int(intel_dp_output_bpp(crtc_state->output_format,
> + crtc_state->pipe_bpp));
> +
> + /* Calculate min Hblank Link Layer Symbol Cycle Count for 8b/10b MST & 128b/132b */
> + hactive_sym_cycles = drm_dp_link_symbol_cycles(max_lane_count,
> + adjusted_mode->hdisplay,
> + dsc_slices,
> + link_bpp_x16,
> + symbol_size, is_mst);
> + htotal_sym_cycles = (adjusted_mode->htotal * hactive_sym_cycles) /
> + adjusted_mode->hdisplay;
Nit: no need for the parentheses.
With the above things addresses patch looks ok to me:
Reviewed-by: Imre Deak <imre.deak@intel.com>
> +
> + min_hblank = htotal_sym_cycles - hactive_sym_cycles;
> + /* minimum Hblank calculation: https://groups.vesa.org/wg/DP/document/20494 */
> + min_hblank = max(min_hblank, min_sym_cycles);
> +
> + /*
> + * adjust the BlankingStart/BlankingEnd framing control from
> + * the calculated value
> + */
> + min_hblank = min_hblank - 2;
> +
> + min_hblank = min(10, min_hblank);
> + crtc_state->min_hblank = min_hblank;
> +
> + return 0;
> +}
> +
> int
> intel_dp_compute_config(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config,
> @@ -3203,6 +3274,11 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> &pipe_config->dp_m_n);
> }
>
> + ret = intel_dp_compute_min_hblank(pipe_config, conn_state,
> + pipe_config->dsc.compression_enable);
> + if (ret)
> + return ret;
> +
> /* FIXME: abstract this better */
> if (pipe_config->splitter.enable)
> pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index 9189db4c25946a0f082223ce059c242e80cc32dc..6f2f048295ecaa6cc1f967dc7b3b4cc75f3344c0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -208,5 +208,8 @@ bool intel_dp_has_connector(struct intel_dp *intel_dp,
> const struct drm_connector_state *conn_state);
> int intel_dp_dsc_max_src_input_bpc(struct intel_display *display);
> int intel_dp_dsc_min_src_input_bpc(void);
> +int intel_dp_compute_min_hblank(struct intel_crtc_state *crtc_state,
> + struct drm_connector_state *conn_state,
> + bool is_dsc);
>
> #endif /* __INTEL_DP_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 4c15dcb103aa2ed5650cbbef8c12be53132e6a80..1108c3749d812a45d1675297220dad23969750fe 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -239,26 +239,6 @@ static int intel_dp_mst_dsc_get_slice_count(const struct intel_connector *connec
> num_joined_pipes);
> }
>
> -static void intel_dp_mst_compute_min_hblank(struct intel_crtc_state *crtc_state,
> - int bpp_x16)
> -{
> - struct intel_display *display = to_intel_display(crtc_state);
> - const struct drm_display_mode *adjusted_mode =
> - &crtc_state->hw.adjusted_mode;
> - int symbol_size = intel_dp_is_uhbr(crtc_state) ? 32 : 8;
> - int hblank;
> -
> - if (DISPLAY_VER(display) < 20)
> - return;
> -
> - /* Calculate min Hblank Link Layer Symbol Cycle Count for 8b/10b MST & 128b/132b */
> - hblank = DIV_ROUND_UP((DIV_ROUND_UP
> - (adjusted_mode->htotal - adjusted_mode->hdisplay, 4) * bpp_x16),
> - symbol_size);
> -
> - crtc_state->min_hblank = hblank;
> -}
> -
> int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp,
> struct intel_crtc_state *crtc_state,
> struct drm_connector_state *conn_state,
> @@ -329,8 +309,6 @@ int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp,
> local_bw_overhead = intel_dp_mst_bw_overhead(crtc_state,
> false, dsc_slice_count, link_bpp_x16);
>
> - intel_dp_mst_compute_min_hblank(crtc_state, link_bpp_x16);
> -
> intel_dp_mst_compute_m_n(crtc_state,
> local_bw_overhead,
> link_bpp_x16,
> @@ -739,6 +717,11 @@ static int mst_stream_compute_config(struct intel_encoder *encoder,
> pipe_config->lane_lat_optim_mask =
> bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
>
> + ret = intel_dp_compute_min_hblank(pipe_config, conn_state,
> + pipe_config->dsc.compression_enable);
> + if (ret)
> + return ret;
> +
> intel_vrr_compute_config(pipe_config, conn_state);
>
> intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
> @@ -1021,12 +1004,10 @@ static void mst_stream_disable(struct intel_atomic_state *state,
> const struct intel_crtc_state *old_crtc_state,
> const struct drm_connector_state *old_conn_state)
> {
> - struct intel_display *display = to_intel_display(state);
> struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
> struct intel_dp *intel_dp = to_primary_dp(encoder);
> struct intel_connector *connector =
> to_intel_connector(old_conn_state->connector);
> - enum transcoder trans = old_crtc_state->cpu_transcoder;
>
> if (intel_dp_mst_active_streams(intel_dp) == 1)
> intel_dp->link.active = false;
> @@ -1034,9 +1015,6 @@ static void mst_stream_disable(struct intel_atomic_state *state,
> intel_hdcp_disable(intel_mst->connector);
>
> intel_dp_sink_disable_decompression(state, connector, old_crtc_state);
> -
> - if (DISPLAY_VER(display) >= 20)
> - intel_de_write(display, DP_MIN_HBLANK_CTL(trans), 0);
> }
>
> static void mst_stream_post_disable(struct intel_atomic_state *state,
> @@ -1305,7 +1283,7 @@ static void mst_stream_enable(struct intel_atomic_state *state,
> enum transcoder trans = pipe_config->cpu_transcoder;
> bool first_mst_stream = intel_dp_mst_active_streams(intel_dp) == 1;
> struct intel_crtc *pipe_crtc;
> - int ret, i, min_hblank;
> + int ret, i;
>
> drm_WARN_ON(display->drm, pipe_config->has_pch_encoder);
>
> @@ -1320,29 +1298,6 @@ static void mst_stream_enable(struct intel_atomic_state *state,
> TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff));
> }
>
> - if (DISPLAY_VER(display) >= 20) {
> - /*
> - * adjust the BlankingStart/BlankingEnd framing control from
> - * the calculated value
> - */
> - min_hblank = pipe_config->min_hblank - 2;
> -
> - /* Maximum value to be programmed is limited to 0x10 */
> - min_hblank = min(0x10, min_hblank);
> -
> - /*
> - * Minimum hblank accepted for 128b/132b would be 5 and for
> - * 8b/10b would be 3 symbol count
> - */
> - if (intel_dp_is_uhbr(pipe_config))
> - min_hblank = max(min_hblank, 5);
> - else
> - min_hblank = max(min_hblank, 3);
> -
> - intel_de_write(display, DP_MIN_HBLANK_CTL(trans),
> - min_hblank);
> - }
> -
> enable_bs_jitter_was(pipe_config);
>
> intel_ddi_enable_transcoder_func(encoder, pipe_config);
>
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2025-04-23 14:39 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-04-23 12:53 [PATCH v5 0/2] Rework/Correction on minimum hblank calculation Arun R Murthy
2025-04-23 12:53 ` [PATCH v5 1/2] drm/display/dp: Export fn to calculate link symbol cycles Arun R Murthy
2025-04-23 13:42 ` Imre Deak
2025-04-23 12:53 ` [PATCH v5 2/2] drm/i915/display: move min_hblank from dp_mst.c to dp.c Arun R Murthy
2025-04-23 14:39 ` Imre Deak
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