Intel-XE Archive on lore.kernel.org
 help / color / mirror / Atom feed
* [PATCH] drm/i915/display: Implement wa_16011342517
@ 2025-05-30  9:12 Nemesa Garg
  2025-05-30  9:40 ` ✓ CI.Patch_applied: success for drm/i915/display: Implement wa_16011342517 (rev2) Patchwork
                   ` (8 more replies)
  0 siblings, 9 replies; 17+ messages in thread
From: Nemesa Garg @ 2025-05-30  9:12 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: Nemesa Garg

While doing voltage swing for type-c phy
for DP 1.62 and HDMI write the
LOADGEN_SHARING_PMD_DISABLE bit to 1.

-v2: Update commit message.
     Add bspec[Suraj]

Bspec: 55359
Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c         | 16 ++++++++++++++++
 .../gpu/drm/i915/display/intel_dkl_phy_regs.h    |  4 ++++
 2 files changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 4c845dd410a2..2cdd51cdfe17 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -77,6 +77,7 @@
 #include "intel_psr.h"
 #include "intel_quirks.h"
 #include "intel_snps_phy.h"
+#include "intel_step.h"
 #include "intel_tc.h"
 #include "intel_vdsc.h"
 #include "intel_vdsc_regs.h"
@@ -1439,6 +1440,21 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
 					  DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK,
 					  val);
 		}
+
+		/* Wa_16011342517:adl-p */
+		if (display->platform.alderlake_p &&
+		    IS_DISPLAY_STEP(display, STEP_A0, STEP_D0)) {
+			if ((intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
+			     crtc_state->port_clock == 594000) ||
+			     (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) &&
+			     crtc_state->port_clock == 162000)) {
+				intel_dkl_phy_rmw(display, DKLP_PCS_GLUE_TX_DPCNTL2(tc_port),
+						  LOADGEN_SHARING_PMD_DISABLE, 1);
+			} else {
+				intel_dkl_phy_rmw(display, DKLP_PCS_GLUE_TX_DPCNTL2(tc_port),
+						  LOADGEN_SHARING_PMD_DISABLE, 0);
+			}
+		}
 	}
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h b/drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h
index 56085b32956d..70ad3f1b1289 100644
--- a/drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h
@@ -188,6 +188,10 @@ struct intel_dkl_phy_reg {
 								 _DKL_CMN_UC_DW27)
 #define  DKL_CMN_UC_DW27_UC_HEALTH			(0x1 << 15)
 
+#define _DKLP_PCS_GLUE_TX_DPCNTL2                       0xB68
+#define DKLP_PCS_GLUE_TX_DPCNTL2(tc_port)		_DKL_REG(tc_port, \
+								 _DKLP_PCS_GLUE_TX_DPCNTL2)
+#define LOADGEN_SHARING_PMD_DISABLE                     REG_BIT(12)
 /*
  * Each Dekel PHY is addressed through a 4KB aperture. Each PHY has more than
  * 4KB of register space, so a separate index is programmed in HIP_INDEX_REG0
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 17+ messages in thread
* [PATCH] drm/i915/display: Implement wa_16011342517
@ 2025-06-25  7:49 Nemesa Garg
  0 siblings, 0 replies; 17+ messages in thread
From: Nemesa Garg @ 2025-06-25  7:49 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: Nemesa Garg, Suraj Kandpal

While doing voltage swing for type-c phy
for DP 1.62 and HDMI write the
LOADGEN_SHARING_PMD_DISABLE bit to 1.

-v2: Update commit.
     Add bspec[Suraj]
-v3: Move w/a before DKL_TX_PMD_LANE_SUS.
     Use DKL_TX_DPCNTL2[Ville]
-v4: Use intel_encoder_is_dp and
     intel_encoder_is_hdmi. [Suraj]

Bspec: 55359
Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c         | 16 ++++++++++++++++
 .../gpu/drm/i915/display/intel_dkl_phy_regs.h    |  1 +
 2 files changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index cbd1060e9664..5d672fb82c2c 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -78,6 +78,7 @@
 #include "intel_psr.h"
 #include "intel_quirks.h"
 #include "intel_snps_phy.h"
+#include "intel_step.h"
 #include "intel_tc.h"
 #include "intel_vdsc.h"
 #include "intel_vdsc_regs.h"
@@ -1394,6 +1395,21 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
 	for (ln = 0; ln < 2; ln++) {
 		int level;
 
+		/* Wa_16011342517:adl-p */
+		if (display->platform.alderlake_p &&
+		    IS_DISPLAY_STEP(display, STEP_A0, STEP_D0)) {
+			if ((intel_encoder_is_hdmi(encoder) &&
+			     crtc_state->port_clock == 594000) ||
+			     (intel_encoder_is_dp(encoder) &&
+			      crtc_state->port_clock == 162000)) {
+				intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln),
+						  LOADGEN_SHARING_PMD_DISABLE, 1);
+			} else {
+				intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln),
+						  LOADGEN_SHARING_PMD_DISABLE, 0);
+			}
+		}
+
 		intel_dkl_phy_write(display, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0);
 
 		level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
diff --git a/drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h b/drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h
index 3d8fa667cc73..f8ffeec29e93 100644
--- a/drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h
@@ -153,6 +153,7 @@ struct intel_dkl_phy_reg {
 #define  DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(val)	REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK, (val))
 #define  DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK	REG_GENMASK(6, 5)
 #define  DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(val)	REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, (val))
+#define  LOADGEN_SHARING_PMD_DISABLE			REG_BIT(12)
 
 #define _DKL_TX_FW_CALIB_LN0				0x02F8
 #define _DKL_TX_FW_CALIB_LN1				0x12F8
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 17+ messages in thread
* [PATCH] drm/i915/display: Implement wa_16011342517
@ 2025-05-16 14:31 Nemesa Garg
  2025-05-29  7:12 ` Kandpal, Suraj
  0 siblings, 1 reply; 17+ messages in thread
From: Nemesa Garg @ 2025-05-16 14:31 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: Nemesa Garg

Workaround to prevent skew violation on type-c
phy for DP 1.62 and HDMI.

Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c         | 16 ++++++++++++++++
 .../gpu/drm/i915/display/intel_dkl_phy_regs.h    |  4 ++++
 2 files changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 74132c1d6385..34b372b18aab 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -77,6 +77,7 @@
 #include "intel_psr.h"
 #include "intel_quirks.h"
 #include "intel_snps_phy.h"
+#include "intel_step.h"
 #include "intel_tc.h"
 #include "intel_vdsc.h"
 #include "intel_vdsc_regs.h"
@@ -1439,6 +1440,21 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
 					  DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK,
 					  val);
 		}
+
+		/* Wa_16011342517:adl-p */
+		if (display->platform.alderlake_p &&
+		    IS_DISPLAY_STEP(display, STEP_A0, STEP_D0)) {
+			if ((intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
+			     crtc_state->port_clock == 594000) ||
+			     (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) &&
+			     crtc_state->port_clock == 162000)) {
+				intel_dkl_phy_rmw(display, DKLP_TX_DPCNTL2(tc_port),
+						  LOADGEN_SHARING_PMD_DISABLE, 1);
+			} else {
+				intel_dkl_phy_rmw(display, DKLP_TX_DPCNTL2(tc_port),
+						  LOADGEN_SHARING_PMD_DISABLE, 0);
+			}
+		}
 	}
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h b/drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h
index 56085b32956d..fa3bad5efca9 100644
--- a/drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h
@@ -188,6 +188,10 @@ struct intel_dkl_phy_reg {
 								 _DKL_CMN_UC_DW27)
 #define  DKL_CMN_UC_DW27_UC_HEALTH			(0x1 << 15)
 
+#define _DKLP_PCS_GLUE_TX_DPCNTL2                       0xB68
+#define DKLP_TX_DPCNTL2(tc_port)			_DKL_REG(tc_port, \
+								 _DKLP_PCS_GLUE_TX_DPCNTL2)
+#define LOADGEN_SHARING_PMD_DISABLE                     REG_BIT(12)
 /*
  * Each Dekel PHY is addressed through a 4KB aperture. Each PHY has more than
  * 4KB of register space, so a separate index is programmed in HIP_INDEX_REG0
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 17+ messages in thread
end of thread, other threads:[~2025-06-25  7:54 UTC | newest]

Thread overview: 17+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-05-30  9:12 [PATCH] drm/i915/display: Implement wa_16011342517 Nemesa Garg
2025-05-30  9:40 ` ✓ CI.Patch_applied: success for drm/i915/display: Implement wa_16011342517 (rev2) Patchwork
2025-05-30  9:40 ` ✓ CI.checkpatch: " Patchwork
2025-05-30  9:41 ` ✓ CI.KUnit: " Patchwork
2025-05-30  9:52 ` ✓ CI.Build: " Patchwork
2025-05-30  9:54 ` ✓ CI.Hooks: " Patchwork
2025-05-30  9:56 ` ✓ CI.checksparse: " Patchwork
2025-05-30 10:17 ` ✓ Xe.CI.BAT: " Patchwork
2025-05-30 11:35 ` [PATCH] drm/i915/display: Implement wa_16011342517 Ville Syrjälä
2025-06-04  8:54   ` Garg, Nemesa
2025-06-04 10:44     ` Garg, Nemesa
2025-05-31 15:25 ` ✗ Xe.CI.Full: failure for drm/i915/display: Implement wa_16011342517 (rev2) Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2025-06-25  7:49 [PATCH] drm/i915/display: Implement wa_16011342517 Nemesa Garg
2025-05-16 14:31 Nemesa Garg
2025-05-29  7:12 ` Kandpal, Suraj
2025-05-29  7:47   ` Garg, Nemesa
2025-05-30  4:16     ` Kandpal, Suraj

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox