[PATCH v4 0/3] drm/xe: Update Wa_22019338487

[PATCH v4 0/3] drm/xe: Update Wa_22019338487

[Lucas De Marchi]

Extracted from https://lore.kernel.org/r/20250602234415.2015921-4-vinay.belgaumkar@intel.com.
Now that the other workarounds were already update, also update this
one that had more changes.

I'm following the version from that patch series, so this can be
considered v4.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
Lucas De Marchi (2):
      drm/xe/guc_pc: Add _locked variant for min/max freq
      drm/xe/xe_guc_pc: Lock once to update stashed frequencies

Vinay Belgaumkar (1):
      drm/xe/bmg: Update Wa_22019338487

 drivers/gpu/drm/xe/xe_device.c       |  13 +-
 drivers/gpu/drm/xe/xe_guc_pc.c       | 280 ++++++++++++++++++++++++++---------
 drivers/gpu/drm/xe/xe_guc_pc.h       |   2 +
 drivers/gpu/drm/xe/xe_guc_pc_types.h |   2 +
 4 files changed, 225 insertions(+), 72 deletions(-)

base-commit: 6e474d767e318b98cc45d4b90095290879085741
change-id: 20250613-wa-22019338487-d18a019d79a8

Lucas De Marchi

[PATCH v4 1/3] drm/xe/guc_pc: Add _locked variant for min/max freq

[Lucas De Marchi]

There are places in which the getters/setters are called one after the
other causing a multiple lock()/unlock(). These are not currently a
problem since they are all happening from the same thread, but there's a
race possibility as calls are added outside of the early init when the
max/min and stashed values need to be correlated.

Add the _locked() variants to prepare for that.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_guc_pc.c | 124 +++++++++++++++++++++++------------------
 1 file changed, 70 insertions(+), 54 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
index 39d2acb2f30f6..53aaf937d4bec 100644
--- a/drivers/gpu/drm/xe/xe_guc_pc.c
+++ b/drivers/gpu/drm/xe/xe_guc_pc.c
@@ -5,6 +5,7 @@
 
 #include "xe_guc_pc.h"
 
+#include <linux/cleanup.h>
 #include <linux/delay.h>
 #include <linux/ktime.h>
 
@@ -554,6 +555,25 @@ u32 xe_guc_pc_get_rpn_freq(struct xe_guc_pc *pc)
 	return pc->rpn_freq;
 }
 
+static int xe_guc_pc_get_min_freq_locked(struct xe_guc_pc *pc, u32 *freq)
+{
+	int ret;
+
+	lockdep_assert_held(&pc->freq_lock);
+
+	/* Might be in the middle of a gt reset */
+	if (!pc->freq_ready)
+		return -EAGAIN;
+
+	ret = pc_action_query_task_state(pc);
+	if (ret)
+		return ret;
+
+	*freq = pc_get_min_freq(pc);
+
+	return 0;
+}
+
 /**
  * xe_guc_pc_get_min_freq - Get the min operational frequency
  * @pc: The GuC PC
@@ -563,27 +583,29 @@ u32 xe_guc_pc_get_rpn_freq(struct xe_guc_pc *pc)
  *         -EAGAIN if GuC PC not ready (likely in middle of a reset).
  */
 int xe_guc_pc_get_min_freq(struct xe_guc_pc *pc, u32 *freq)
+{
+	guard(mutex)(&pc->freq_lock);
+
+	return xe_guc_pc_get_min_freq_locked(pc, freq);
+}
+
+static int xe_guc_pc_set_min_freq_locked(struct xe_guc_pc *pc, u32 freq)
 {
 	int ret;
 
-	xe_device_assert_mem_access(pc_to_xe(pc));
+	lockdep_assert_held(&pc->freq_lock);
 
-	mutex_lock(&pc->freq_lock);
-	if (!pc->freq_ready) {
-		/* Might be in the middle of a gt reset */
-		ret = -EAGAIN;
-		goto out;
-	}
+	/* Might be in the middle of a gt reset */
+	if (!pc->freq_ready)
+		return -EAGAIN;
 
-	ret = pc_action_query_task_state(pc);
+	ret = pc_set_min_freq(pc, freq);
 	if (ret)
-		goto out;
+		return ret;
 
-	*freq = pc_get_min_freq(pc);
+	pc->user_requested_min = freq;
 
-out:
-	mutex_unlock(&pc->freq_lock);
-	return ret;
+	return 0;
 }
 
 /**
@@ -596,25 +618,30 @@ int xe_guc_pc_get_min_freq(struct xe_guc_pc *pc, u32 *freq)
  *         -EINVAL if value out of bounds.
  */
 int xe_guc_pc_set_min_freq(struct xe_guc_pc *pc, u32 freq)
+{
+	guard(mutex)(&pc->freq_lock);
+
+	return xe_guc_pc_set_min_freq_locked(pc, freq);
+}
+
+
+static int xe_guc_pc_get_max_freq_locked(struct xe_guc_pc *pc, u32 *freq)
 {
 	int ret;
 
-	mutex_lock(&pc->freq_lock);
-	if (!pc->freq_ready) {
-		/* Might be in the middle of a gt reset */
-		ret = -EAGAIN;
-		goto out;
-	}
+	lockdep_assert_held(&pc->freq_lock);
 
-	ret = pc_set_min_freq(pc, freq);
+	/* Might be in the middle of a gt reset */
+	if (!pc->freq_ready)
+		return -EAGAIN;
+
+	ret = pc_action_query_task_state(pc);
 	if (ret)
-		goto out;
+		return ret;
 
-	pc->user_requested_min = freq;
+	*freq = pc_get_max_freq(pc);
 
-out:
-	mutex_unlock(&pc->freq_lock);
-	return ret;
+	return 0;
 }
 
 /**
@@ -626,25 +653,29 @@ int xe_guc_pc_set_min_freq(struct xe_guc_pc *pc, u32 freq)
  *         -EAGAIN if GuC PC not ready (likely in middle of a reset).
  */
 int xe_guc_pc_get_max_freq(struct xe_guc_pc *pc, u32 *freq)
+{
+	guard(mutex)(&pc->freq_lock);
+
+	return xe_guc_pc_get_max_freq_locked(pc, freq);
+}
+
+static int xe_guc_pc_set_max_freq_locked(struct xe_guc_pc *pc, u32 freq)
 {
 	int ret;
 
-	mutex_lock(&pc->freq_lock);
-	if (!pc->freq_ready) {
-		/* Might be in the middle of a gt reset */
-		ret = -EAGAIN;
-		goto out;
-	}
+	lockdep_assert_held(&pc->freq_lock);
 
-	ret = pc_action_query_task_state(pc);
+	/* Might be in the middle of a gt reset */
+	if (!pc->freq_ready)
+		return -EAGAIN;
+
+	ret = pc_set_max_freq(pc, freq);
 	if (ret)
-		goto out;
+		return ret;
 
-	*freq = pc_get_max_freq(pc);
+	pc->user_requested_max = freq;
 
-out:
-	mutex_unlock(&pc->freq_lock);
-	return ret;
+	return 0;
 }
 
 /**
@@ -658,24 +689,9 @@ int xe_guc_pc_get_max_freq(struct xe_guc_pc *pc, u32 *freq)
  */
 int xe_guc_pc_set_max_freq(struct xe_guc_pc *pc, u32 freq)
 {
-	int ret;
-
-	mutex_lock(&pc->freq_lock);
-	if (!pc->freq_ready) {
-		/* Might be in the middle of a gt reset */
-		ret = -EAGAIN;
-		goto out;
-	}
-
-	ret = pc_set_max_freq(pc, freq);
-	if (ret)
-		goto out;
+	guard(mutex)(&pc->freq_lock);
 
-	pc->user_requested_max = freq;
-
-out:
-	mutex_unlock(&pc->freq_lock);
-	return ret;
+	return xe_guc_pc_set_max_freq_locked(pc, freq);
 }
 
 /**

-- 
2.49.0

Re: [PATCH v4 1/3] drm/xe/guc_pc: Add _locked variant for min/max freq

[Rodrigo Vivi]

On Sun, Jun 15, 2025 at 11:17:34PM -0700, Lucas De Marchi wrote:
> There are places in which the getters/setters are called one after the
> other causing a multiple lock()/unlock(). These are not currently a
> problem since they are all happening from the same thread, but there's a
> race possibility as calls are added outside of the early init when the
> max/min and stashed values need to be correlated.
> 
> Add the _locked() variants to prepare for that.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/xe/xe_guc_pc.c | 124 +++++++++++++++++++++++------------------
>  1 file changed, 70 insertions(+), 54 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
> index 39d2acb2f30f6..53aaf937d4bec 100644
> --- a/drivers/gpu/drm/xe/xe_guc_pc.c
> +++ b/drivers/gpu/drm/xe/xe_guc_pc.c
> @@ -5,6 +5,7 @@
>  
>  #include "xe_guc_pc.h"
>  
> +#include <linux/cleanup.h>
>  #include <linux/delay.h>
>  #include <linux/ktime.h>
>  
> @@ -554,6 +555,25 @@ u32 xe_guc_pc_get_rpn_freq(struct xe_guc_pc *pc)
>  	return pc->rpn_freq;
>  }
>  
> +static int xe_guc_pc_get_min_freq_locked(struct xe_guc_pc *pc, u32 *freq)
> +{
> +	int ret;
> +
> +	lockdep_assert_held(&pc->freq_lock);
> +
> +	/* Might be in the middle of a gt reset */
> +	if (!pc->freq_ready)
> +		return -EAGAIN;
> +
> +	ret = pc_action_query_task_state(pc);
> +	if (ret)
> +		return ret;
> +
> +	*freq = pc_get_min_freq(pc);
> +
> +	return 0;
> +}
> +
>  /**
>   * xe_guc_pc_get_min_freq - Get the min operational frequency
>   * @pc: The GuC PC
> @@ -563,27 +583,29 @@ u32 xe_guc_pc_get_rpn_freq(struct xe_guc_pc *pc)
>   *         -EAGAIN if GuC PC not ready (likely in middle of a reset).
>   */
>  int xe_guc_pc_get_min_freq(struct xe_guc_pc *pc, u32 *freq)
> +{
> +	guard(mutex)(&pc->freq_lock);
> +
> +	return xe_guc_pc_get_min_freq_locked(pc, freq);
> +}
> +
> +static int xe_guc_pc_set_min_freq_locked(struct xe_guc_pc *pc, u32 freq)
>  {
>  	int ret;
>  
> -	xe_device_assert_mem_access(pc_to_xe(pc));
> +	lockdep_assert_held(&pc->freq_lock);
>  
> -	mutex_lock(&pc->freq_lock);
> -	if (!pc->freq_ready) {
> -		/* Might be in the middle of a gt reset */
> -		ret = -EAGAIN;
> -		goto out;
> -	}
> +	/* Might be in the middle of a gt reset */
> +	if (!pc->freq_ready)
> +		return -EAGAIN;
>  
> -	ret = pc_action_query_task_state(pc);
> +	ret = pc_set_min_freq(pc, freq);
>  	if (ret)
> -		goto out;
> +		return ret;
>  
> -	*freq = pc_get_min_freq(pc);
> +	pc->user_requested_min = freq;
>  
> -out:
> -	mutex_unlock(&pc->freq_lock);
> -	return ret;
> +	return 0;
>  }
>  
>  /**
> @@ -596,25 +618,30 @@ int xe_guc_pc_get_min_freq(struct xe_guc_pc *pc, u32 *freq)
>   *         -EINVAL if value out of bounds.
>   */
>  int xe_guc_pc_set_min_freq(struct xe_guc_pc *pc, u32 freq)
> +{
> +	guard(mutex)(&pc->freq_lock);
> +
> +	return xe_guc_pc_set_min_freq_locked(pc, freq);
> +}
> +
> +
> +static int xe_guc_pc_get_max_freq_locked(struct xe_guc_pc *pc, u32 *freq)
>  {
>  	int ret;
>  
> -	mutex_lock(&pc->freq_lock);
> -	if (!pc->freq_ready) {
> -		/* Might be in the middle of a gt reset */
> -		ret = -EAGAIN;
> -		goto out;
> -	}
> +	lockdep_assert_held(&pc->freq_lock);
>  
> -	ret = pc_set_min_freq(pc, freq);
> +	/* Might be in the middle of a gt reset */
> +	if (!pc->freq_ready)
> +		return -EAGAIN;
> +
> +	ret = pc_action_query_task_state(pc);
>  	if (ret)
> -		goto out;
> +		return ret;
>  
> -	pc->user_requested_min = freq;
> +	*freq = pc_get_max_freq(pc);
>  
> -out:
> -	mutex_unlock(&pc->freq_lock);
> -	return ret;
> +	return 0;
>  }
>  
>  /**
> @@ -626,25 +653,29 @@ int xe_guc_pc_set_min_freq(struct xe_guc_pc *pc, u32 freq)
>   *         -EAGAIN if GuC PC not ready (likely in middle of a reset).
>   */
>  int xe_guc_pc_get_max_freq(struct xe_guc_pc *pc, u32 *freq)
> +{
> +	guard(mutex)(&pc->freq_lock);
> +
> +	return xe_guc_pc_get_max_freq_locked(pc, freq);
> +}
> +
> +static int xe_guc_pc_set_max_freq_locked(struct xe_guc_pc *pc, u32 freq)
>  {
>  	int ret;
>  
> -	mutex_lock(&pc->freq_lock);
> -	if (!pc->freq_ready) {
> -		/* Might be in the middle of a gt reset */
> -		ret = -EAGAIN;
> -		goto out;
> -	}
> +	lockdep_assert_held(&pc->freq_lock);
>  
> -	ret = pc_action_query_task_state(pc);
> +	/* Might be in the middle of a gt reset */
> +	if (!pc->freq_ready)
> +		return -EAGAIN;
> +
> +	ret = pc_set_max_freq(pc, freq);
>  	if (ret)
> -		goto out;
> +		return ret;
>  
> -	*freq = pc_get_max_freq(pc);
> +	pc->user_requested_max = freq;
>  
> -out:
> -	mutex_unlock(&pc->freq_lock);
> -	return ret;
> +	return 0;
>  }
>  
>  /**
> @@ -658,24 +689,9 @@ int xe_guc_pc_get_max_freq(struct xe_guc_pc *pc, u32 *freq)
>   */
>  int xe_guc_pc_set_max_freq(struct xe_guc_pc *pc, u32 freq)
>  {
> -	int ret;
> -
> -	mutex_lock(&pc->freq_lock);
> -	if (!pc->freq_ready) {
> -		/* Might be in the middle of a gt reset */
> -		ret = -EAGAIN;
> -		goto out;
> -	}
> -
> -	ret = pc_set_max_freq(pc, freq);
> -	if (ret)
> -		goto out;
> +	guard(mutex)(&pc->freq_lock);
>  
> -	pc->user_requested_max = freq;
> -
> -out:
> -	mutex_unlock(&pc->freq_lock);
> -	return ret;
> +	return xe_guc_pc_set_max_freq_locked(pc, freq);
>  }
>  
>  /**
> 
> -- 
> 2.49.0
> 

[PATCH v4 2/3] drm/xe/xe_guc_pc: Lock once to update stashed frequencies

[Lucas De Marchi]

pc_set_mert_freq_cap() currently lock()/unlock() the mutex multiple times
to stash the current frequencies. It's not a problem since
xe_guc_pc_restore_stashed_freq() is guaranteed to be called only later
in the init sequence. However, now that we have _locked() variants for
this functions, use them and avoid potential issues when called from
other places or using the same pattern.

While at it, prefer and early return for the WA check to reduce
indentation.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_guc_pc.c | 39 ++++++++++++++++++++-------------------
 1 file changed, 20 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
index 53aaf937d4bec..d449eb0e3e8af 100644
--- a/drivers/gpu/drm/xe/xe_guc_pc.c
+++ b/drivers/gpu/drm/xe/xe_guc_pc.c
@@ -891,27 +891,28 @@ static int pc_adjust_requested_freq(struct xe_guc_pc *pc)
 
 static int pc_set_mert_freq_cap(struct xe_guc_pc *pc)
 {
-	int ret = 0;
+	int ret;
 
-	if (XE_WA(pc_to_gt(pc), 22019338487)) {
-		/*
-		 * Get updated min/max and stash them.
-		 */
-		ret = xe_guc_pc_get_min_freq(pc, &pc->stashed_min_freq);
-		if (!ret)
-			ret = xe_guc_pc_get_max_freq(pc, &pc->stashed_max_freq);
-		if (ret)
-			return ret;
+	if (!XE_WA(pc_to_gt(pc), 22019338487))
+		return 0;
 
-		/*
-		 * Ensure min and max are bound by MERT_FREQ_CAP until driver loads.
-		 */
-		mutex_lock(&pc->freq_lock);
-		ret = pc_set_min_freq(pc, min(pc->rpe_freq, pc_max_freq_cap(pc)));
-		if (!ret)
-			ret = pc_set_max_freq(pc, min(pc->rp0_freq, pc_max_freq_cap(pc)));
-		mutex_unlock(&pc->freq_lock);
-	}
+	guard(mutex)(&pc->freq_lock);
+
+	/*
+	 * Get updated min/max and stash them.
+	 */
+	ret = xe_guc_pc_get_min_freq_locked(pc, &pc->stashed_min_freq);
+	if (!ret)
+		ret = xe_guc_pc_get_max_freq_locked(pc, &pc->stashed_max_freq);
+	if (ret)
+		return ret;
+
+	/*
+	 * Ensure min and max are bound by MERT_FREQ_CAP until driver loads.
+	 */
+	ret = pc_set_min_freq(pc, min(pc->rpe_freq, pc_max_freq_cap(pc)));
+	if (!ret)
+		ret = pc_set_max_freq(pc, min(pc->rp0_freq, pc_max_freq_cap(pc)));
 
 	return ret;
 }

-- 
2.49.0

Re: [PATCH v4 2/3] drm/xe/xe_guc_pc: Lock once to update stashed frequencies

[Rodrigo Vivi]

On Sun, Jun 15, 2025 at 11:17:35PM -0700, Lucas De Marchi wrote:
> pc_set_mert_freq_cap() currently lock()/unlock() the mutex multiple times
> to stash the current frequencies. It's not a problem since
> xe_guc_pc_restore_stashed_freq() is guaranteed to be called only later
> in the init sequence. However, now that we have _locked() variants for
> this functions, use them and avoid potential issues when called from
> other places or using the same pattern.
> 
> While at it, prefer and early return for the WA check to reduce
> indentation.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/xe/xe_guc_pc.c | 39 ++++++++++++++++++++-------------------
>  1 file changed, 20 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
> index 53aaf937d4bec..d449eb0e3e8af 100644
> --- a/drivers/gpu/drm/xe/xe_guc_pc.c
> +++ b/drivers/gpu/drm/xe/xe_guc_pc.c
> @@ -891,27 +891,28 @@ static int pc_adjust_requested_freq(struct xe_guc_pc *pc)
>  
>  static int pc_set_mert_freq_cap(struct xe_guc_pc *pc)
>  {
> -	int ret = 0;
> +	int ret;
>  
> -	if (XE_WA(pc_to_gt(pc), 22019338487)) {
> -		/*
> -		 * Get updated min/max and stash them.
> -		 */
> -		ret = xe_guc_pc_get_min_freq(pc, &pc->stashed_min_freq);
> -		if (!ret)
> -			ret = xe_guc_pc_get_max_freq(pc, &pc->stashed_max_freq);
> -		if (ret)
> -			return ret;
> +	if (!XE_WA(pc_to_gt(pc), 22019338487))
> +		return 0;
>  
> -		/*
> -		 * Ensure min and max are bound by MERT_FREQ_CAP until driver loads.
> -		 */
> -		mutex_lock(&pc->freq_lock);
> -		ret = pc_set_min_freq(pc, min(pc->rpe_freq, pc_max_freq_cap(pc)));
> -		if (!ret)
> -			ret = pc_set_max_freq(pc, min(pc->rp0_freq, pc_max_freq_cap(pc)));
> -		mutex_unlock(&pc->freq_lock);
> -	}
> +	guard(mutex)(&pc->freq_lock);
> +
> +	/*
> +	 * Get updated min/max and stash them.
> +	 */
> +	ret = xe_guc_pc_get_min_freq_locked(pc, &pc->stashed_min_freq);
> +	if (!ret)
> +		ret = xe_guc_pc_get_max_freq_locked(pc, &pc->stashed_max_freq);
> +	if (ret)
> +		return ret;
> +
> +	/*
> +	 * Ensure min and max are bound by MERT_FREQ_CAP until driver loads.
> +	 */
> +	ret = pc_set_min_freq(pc, min(pc->rpe_freq, pc_max_freq_cap(pc)));
> +	if (!ret)
> +		ret = pc_set_max_freq(pc, min(pc->rp0_freq, pc_max_freq_cap(pc)));
>  
>  	return ret;
>  }
> 
> -- 
> 2.49.0
> 

[PATCH v4 3/3] drm/xe/bmg: Update Wa_22019338487

[Lucas De Marchi]

From: Vinay Belgaumkar <vinay.belgaumkar@intel.com>

Limit GT max frequency to 2600Mhz during the L2 flush. Also, ensure
GT actual frequency is limited to that value before performing the
cache flush.

v2: Use generic names, ensure user set max frequency requests wait
for flush to complete (Rodrigo)
v3:
 - User requests wait via wait_var_event_timeout (Lucas)
 - Close races on flush + user requests (Lucas)
 - Fix xe_guc_pc_remove_flush_freq_limit() being called on last gt
   rather than root gt (Lucas)

Fixes: aaa08078e725 ("drm/xe/bmg: Apply Wa_22019338487")
Fixes: 01570b446939 ("drm/xe/bmg: implement Wa_16023588340")
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_device.c       |  13 +++-
 drivers/gpu/drm/xe/xe_guc_pc.c       | 125 +++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_guc_pc.h       |   2 +
 drivers/gpu/drm/xe/xe_guc_pc_types.h |   2 +
 4 files changed, 139 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index 7e87344943cdf..6ff373ad0a965 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -40,6 +40,7 @@
 #include "xe_gt_printk.h"
 #include "xe_gt_sriov_vf.h"
 #include "xe_guc.h"
+#include "xe_guc_pc.h"
 #include "xe_hw_engine_group.h"
 #include "xe_hwmon.h"
 #include "xe_irq.h"
@@ -1001,16 +1002,19 @@ void xe_device_wmb(struct xe_device *xe)
  */
 void xe_device_td_flush(struct xe_device *xe)
 {
-	struct xe_gt *gt;
+	struct xe_gt *gt, *root_gt;
 	unsigned int fw_ref;
 	u8 id;
 
 	if (!IS_DGFX(xe) || GRAPHICS_VER(xe) < 20)
 		return;
 
-	if (XE_WA(xe_root_mmio_gt(xe), 16023588340)) {
+	root_gt = xe_root_mmio_gt(xe);
+	xe_guc_pc_apply_flush_freq_limit(&root_gt->uc.guc.pc);
+
+	if (XE_WA(root_gt, 16023588340)) {
 		xe_device_l2_flush(xe);
-		return;
+		goto done;
 	}
 
 	for_each_gt(gt, xe, id) {
@@ -1035,6 +1039,9 @@ void xe_device_td_flush(struct xe_device *xe)
 
 		xe_force_wake_put(gt_to_fw(gt), fw_ref);
 	}
+
+done:
+	xe_guc_pc_remove_flush_freq_limit(&root_gt->uc.guc.pc);
 }
 
 void xe_device_l2_flush(struct xe_device *xe)
diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
index d449eb0e3e8af..eab932655b2fb 100644
--- a/drivers/gpu/drm/xe/xe_guc_pc.c
+++ b/drivers/gpu/drm/xe/xe_guc_pc.c
@@ -7,7 +7,9 @@
 
 #include <linux/cleanup.h>
 #include <linux/delay.h>
+#include <linux/jiffies.h>
 #include <linux/ktime.h>
+#include <linux/wait_bit.h>
 
 #include <drm/drm_managed.h>
 #include <drm/drm_print.h>
@@ -53,9 +55,11 @@
 #define LNL_MERT_FREQ_CAP	800
 #define BMG_MERT_FREQ_CAP	2133
 #define BMG_MIN_FREQ		1200
+#define BMG_MERT_FLUSH_FREQ_CAP	2600
 
 #define SLPC_RESET_TIMEOUT_MS 5 /* roughly 5ms, but no need for precision */
 #define SLPC_RESET_EXTENDED_TIMEOUT_MS 1000 /* To be used only at pc_start */
+#define SLPC_ACT_FREQ_TIMEOUT_MS 100
 
 /**
  * DOC: GuC Power Conservation (PC)
@@ -143,6 +147,36 @@ static int wait_for_pc_state(struct xe_guc_pc *pc,
 	return -ETIMEDOUT;
 }
 
+static int wait_for_flush_complete(struct xe_guc_pc *pc)
+{
+	const unsigned long timeout = msecs_to_jiffies(30);
+
+	if (!wait_var_event_timeout(&pc->flush_freq_limit,
+				    !atomic_read(&pc->flush_freq_limit),
+				    timeout))
+		return -ETIMEDOUT;
+
+	return 0;
+}
+
+static int wait_for_act_freq_limit(struct xe_guc_pc *pc, u32 freq)
+{
+	int timeout_us = SLPC_ACT_FREQ_TIMEOUT_MS * USEC_PER_MSEC;
+	int slept, wait = 10;
+
+	for (slept = 0; slept < timeout_us;) {
+		if (xe_guc_pc_get_act_freq(pc) <= freq)
+			return 0;
+
+		usleep_range(wait, wait << 1);
+		slept += wait;
+		wait <<= 1;
+		if (slept + wait > timeout_us)
+			wait = timeout_us - slept;
+	}
+
+	return -ETIMEDOUT;
+}
 static int pc_action_reset(struct xe_guc_pc *pc)
 {
 	struct xe_guc_ct *ct = pc_to_ct(pc);
@@ -689,6 +723,11 @@ static int xe_guc_pc_set_max_freq_locked(struct xe_guc_pc *pc, u32 freq)
  */
 int xe_guc_pc_set_max_freq(struct xe_guc_pc *pc, u32 freq)
 {
+	if (XE_WA(pc_to_gt(pc), 22019338487)) {
+		if (wait_for_flush_complete(pc) != 0)
+			return -EAGAIN;
+	}
+
 	guard(mutex)(&pc->freq_lock);
 
 	return xe_guc_pc_set_max_freq_locked(pc, freq);
@@ -889,6 +928,92 @@ static int pc_adjust_requested_freq(struct xe_guc_pc *pc)
 	return ret;
 }
 
+static bool needs_flush_freq_limit(struct xe_guc_pc *pc)
+{
+	struct xe_gt *gt = pc_to_gt(pc);
+
+	return  XE_WA(gt, 22019338487) &&
+		pc->rp0_freq > BMG_MERT_FLUSH_FREQ_CAP;
+}
+
+/**
+ * xe_guc_pc_apply_flush_freq_limit() - Limit max GT freq during L2 flush
+ * @pc: the xe_guc_pc object
+ *
+ * As per the WA, reduce max GT frequency during L2 cache flush
+ */
+void xe_guc_pc_apply_flush_freq_limit(struct xe_guc_pc *pc)
+{
+	struct xe_gt *gt = pc_to_gt(pc);
+	u32 max_freq;
+	int ret;
+
+	if (!needs_flush_freq_limit(pc))
+		return;
+
+	guard(mutex)(&pc->freq_lock);
+
+	ret = xe_guc_pc_get_max_freq_locked(pc, &max_freq);
+	if (!ret && max_freq > BMG_MERT_FLUSH_FREQ_CAP) {
+		ret = pc_set_max_freq(pc, BMG_MERT_FLUSH_FREQ_CAP);
+		if (ret) {
+			xe_gt_err_once(gt, "Failed to cap max freq on flush to %u, %pe\n",
+				       BMG_MERT_FLUSH_FREQ_CAP, ERR_PTR(ret));
+			return;
+		}
+
+		atomic_set(&pc->flush_freq_limit, 1);
+
+		/*
+		 * If user has previously changed max freq, stash that value to
+		 * restore later, otherwise use the current max. New user
+		 * requests wait on flush.
+		 */
+		if (pc->user_requested_max != 0)
+			pc->stashed_max_freq = pc->user_requested_max;
+		else
+			pc->stashed_max_freq = max_freq;
+	}
+
+	/*
+	 * Wait for actual freq to go below the flush cap: even if the previous
+	 * max was below cap, the current one might still be above it
+	 */
+	ret = wait_for_act_freq_limit(pc, BMG_MERT_FLUSH_FREQ_CAP);
+	if (ret)
+		xe_gt_err_once(gt, "Actual freq did not reduce to %u, %pe\n",
+			       BMG_MERT_FLUSH_FREQ_CAP, ERR_PTR(ret));
+}
+
+/**
+ * xe_guc_pc_remove_flush_freq_limit() - Remove max GT freq limit after L2 flush completes.
+ * @pc: the xe_guc_pc object
+ *
+ * Retrieve the previous GT max frequency value.
+ */
+void xe_guc_pc_remove_flush_freq_limit(struct xe_guc_pc *pc)
+{
+	struct xe_gt *gt = pc_to_gt(pc);
+	int ret = 0;
+
+	if (!needs_flush_freq_limit(pc))
+		return;
+
+	if (!atomic_read(&pc->flush_freq_limit))
+		return;
+
+	mutex_lock(&pc->freq_lock);
+
+	ret = pc_set_max_freq(&gt->uc.guc.pc, pc->stashed_max_freq);
+	if (ret)
+		xe_gt_err_once(gt, "Failed to restore max freq %u:%d",
+			       pc->stashed_max_freq, ret);
+
+	atomic_set(&pc->flush_freq_limit, 0);
+	mutex_unlock(&pc->freq_lock);
+	wake_up_var(&pc->flush_freq_limit);
+}
+
 static int pc_set_mert_freq_cap(struct xe_guc_pc *pc)
 {
 	int ret;
diff --git a/drivers/gpu/drm/xe/xe_guc_pc.h b/drivers/gpu/drm/xe/xe_guc_pc.h
index 0a2664d5c8114..52ecdd5ddbff2 100644
--- a/drivers/gpu/drm/xe/xe_guc_pc.h
+++ b/drivers/gpu/drm/xe/xe_guc_pc.h
@@ -38,5 +38,7 @@ u64 xe_guc_pc_mc6_residency(struct xe_guc_pc *pc);
 void xe_guc_pc_init_early(struct xe_guc_pc *pc);
 int xe_guc_pc_restore_stashed_freq(struct xe_guc_pc *pc);
 void xe_guc_pc_raise_unslice(struct xe_guc_pc *pc);
+void xe_guc_pc_apply_flush_freq_limit(struct xe_guc_pc *pc);
+void xe_guc_pc_remove_flush_freq_limit(struct xe_guc_pc *pc);
 
 #endif /* _XE_GUC_PC_H_ */
diff --git a/drivers/gpu/drm/xe/xe_guc_pc_types.h b/drivers/gpu/drm/xe/xe_guc_pc_types.h
index 2978ac9a249b5..c02053948a579 100644
--- a/drivers/gpu/drm/xe/xe_guc_pc_types.h
+++ b/drivers/gpu/drm/xe/xe_guc_pc_types.h
@@ -15,6 +15,8 @@
 struct xe_guc_pc {
 	/** @bo: GGTT buffer object that is shared with GuC PC */
 	struct xe_bo *bo;
+	/** @flush_freq_limit: 1 when max freq changes are limited by driver */
+	atomic_t flush_freq_limit;
 	/** @rp0_freq: HW RP0 frequency - The Maximum one */
 	u32 rp0_freq;
 	/** @rpa_freq: HW RPa frequency - The Achievable one */

-- 
2.49.0

Re: [PATCH v4 3/3] drm/xe/bmg: Update Wa_22019338487

[Rodrigo Vivi]

On Sun, Jun 15, 2025 at 11:17:36PM -0700, Lucas De Marchi wrote:
> From: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> 
> Limit GT max frequency to 2600Mhz during the L2 flush. Also, ensure
> GT actual frequency is limited to that value before performing the
> cache flush.
> 
> v2: Use generic names, ensure user set max frequency requests wait
> for flush to complete (Rodrigo)
> v3:
>  - User requests wait via wait_var_event_timeout (Lucas)
>  - Close races on flush + user requests (Lucas)
>  - Fix xe_guc_pc_remove_flush_freq_limit() being called on last gt
>    rather than root gt (Lucas)
> 
> Fixes: aaa08078e725 ("drm/xe/bmg: Apply Wa_22019338487")
> Fixes: 01570b446939 ("drm/xe/bmg: implement Wa_16023588340")
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_device.c       |  13 +++-
>  drivers/gpu/drm/xe/xe_guc_pc.c       | 125 +++++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/xe/xe_guc_pc.h       |   2 +
>  drivers/gpu/drm/xe/xe_guc_pc_types.h |   2 +
>  4 files changed, 139 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
> index 7e87344943cdf..6ff373ad0a965 100644
> --- a/drivers/gpu/drm/xe/xe_device.c
> +++ b/drivers/gpu/drm/xe/xe_device.c
> @@ -40,6 +40,7 @@
>  #include "xe_gt_printk.h"
>  #include "xe_gt_sriov_vf.h"
>  #include "xe_guc.h"
> +#include "xe_guc_pc.h"
>  #include "xe_hw_engine_group.h"
>  #include "xe_hwmon.h"
>  #include "xe_irq.h"
> @@ -1001,16 +1002,19 @@ void xe_device_wmb(struct xe_device *xe)
>   */
>  void xe_device_td_flush(struct xe_device *xe)
>  {
> -	struct xe_gt *gt;
> +	struct xe_gt *gt, *root_gt;
>  	unsigned int fw_ref;
>  	u8 id;
>  
>  	if (!IS_DGFX(xe) || GRAPHICS_VER(xe) < 20)
>  		return;
>  
> -	if (XE_WA(xe_root_mmio_gt(xe), 16023588340)) {
> +	root_gt = xe_root_mmio_gt(xe);
> +	xe_guc_pc_apply_flush_freq_limit(&root_gt->uc.guc.pc);
> +
> +	if (XE_WA(root_gt, 16023588340)) {
>  		xe_device_l2_flush(xe);
> -		return;
> +		goto done;
>  	}
>  
>  	for_each_gt(gt, xe, id) {
> @@ -1035,6 +1039,9 @@ void xe_device_td_flush(struct xe_device *xe)
>  
>  		xe_force_wake_put(gt_to_fw(gt), fw_ref);
>  	}
> +
> +done:
> +	xe_guc_pc_remove_flush_freq_limit(&root_gt->uc.guc.pc);
>  }
>  
>  void xe_device_l2_flush(struct xe_device *xe)
> diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
> index d449eb0e3e8af..eab932655b2fb 100644
> --- a/drivers/gpu/drm/xe/xe_guc_pc.c
> +++ b/drivers/gpu/drm/xe/xe_guc_pc.c
> @@ -7,7 +7,9 @@
>  
>  #include <linux/cleanup.h>
>  #include <linux/delay.h>
> +#include <linux/jiffies.h>
>  #include <linux/ktime.h>
> +#include <linux/wait_bit.h>
>  
>  #include <drm/drm_managed.h>
>  #include <drm/drm_print.h>
> @@ -53,9 +55,11 @@
>  #define LNL_MERT_FREQ_CAP	800
>  #define BMG_MERT_FREQ_CAP	2133
>  #define BMG_MIN_FREQ		1200
> +#define BMG_MERT_FLUSH_FREQ_CAP	2600
>  
>  #define SLPC_RESET_TIMEOUT_MS 5 /* roughly 5ms, but no need for precision */
>  #define SLPC_RESET_EXTENDED_TIMEOUT_MS 1000 /* To be used only at pc_start */
> +#define SLPC_ACT_FREQ_TIMEOUT_MS 100
>  
>  /**
>   * DOC: GuC Power Conservation (PC)
> @@ -143,6 +147,36 @@ static int wait_for_pc_state(struct xe_guc_pc *pc,
>  	return -ETIMEDOUT;
>  }
>  
> +static int wait_for_flush_complete(struct xe_guc_pc *pc)
> +{
> +	const unsigned long timeout = msecs_to_jiffies(30);
> +
> +	if (!wait_var_event_timeout(&pc->flush_freq_limit,
> +				    !atomic_read(&pc->flush_freq_limit),
> +				    timeout))
> +		return -ETIMEDOUT;
> +
> +	return 0;
> +}
> +
> +static int wait_for_act_freq_limit(struct xe_guc_pc *pc, u32 freq)

for a moment, the name of this function got me confused. I thought
it was going to wait for the *exact* act freq, and then it would be
risky because we can never know what PCODE will decide on extra
throttles.

But I don't have a suggestion for a better naming and reading the
rest of the code showed it is doing things correctly.

There's a risk though... if for some reason PCODE decides to keep
freq high for a longer time... but likely unreal for this platform.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> +{
> +	int timeout_us = SLPC_ACT_FREQ_TIMEOUT_MS * USEC_PER_MSEC;
> +	int slept, wait = 10;
> +
> +	for (slept = 0; slept < timeout_us;) {
> +		if (xe_guc_pc_get_act_freq(pc) <= freq)
> +			return 0;
> +
> +		usleep_range(wait, wait << 1);
> +		slept += wait;
> +		wait <<= 1;
> +		if (slept + wait > timeout_us)
> +			wait = timeout_us - slept;
> +	}
> +
> +	return -ETIMEDOUT;
> +}
>  static int pc_action_reset(struct xe_guc_pc *pc)
>  {
>  	struct xe_guc_ct *ct = pc_to_ct(pc);
> @@ -689,6 +723,11 @@ static int xe_guc_pc_set_max_freq_locked(struct xe_guc_pc *pc, u32 freq)
>   */
>  int xe_guc_pc_set_max_freq(struct xe_guc_pc *pc, u32 freq)
>  {
> +	if (XE_WA(pc_to_gt(pc), 22019338487)) {
> +		if (wait_for_flush_complete(pc) != 0)
> +			return -EAGAIN;
> +	}
> +
>  	guard(mutex)(&pc->freq_lock);
>  
>  	return xe_guc_pc_set_max_freq_locked(pc, freq);
> @@ -889,6 +928,92 @@ static int pc_adjust_requested_freq(struct xe_guc_pc *pc)
>  	return ret;
>  }
>  
> +static bool needs_flush_freq_limit(struct xe_guc_pc *pc)
> +{
> +	struct xe_gt *gt = pc_to_gt(pc);
> +
> +	return  XE_WA(gt, 22019338487) &&
> +		pc->rp0_freq > BMG_MERT_FLUSH_FREQ_CAP;
> +}
> +
> +/**
> + * xe_guc_pc_apply_flush_freq_limit() - Limit max GT freq during L2 flush
> + * @pc: the xe_guc_pc object
> + *
> + * As per the WA, reduce max GT frequency during L2 cache flush
> + */
> +void xe_guc_pc_apply_flush_freq_limit(struct xe_guc_pc *pc)
> +{
> +	struct xe_gt *gt = pc_to_gt(pc);
> +	u32 max_freq;
> +	int ret;
> +
> +	if (!needs_flush_freq_limit(pc))
> +		return;
> +
> +	guard(mutex)(&pc->freq_lock);
> +
> +	ret = xe_guc_pc_get_max_freq_locked(pc, &max_freq);
> +	if (!ret && max_freq > BMG_MERT_FLUSH_FREQ_CAP) {
> +		ret = pc_set_max_freq(pc, BMG_MERT_FLUSH_FREQ_CAP);
> +		if (ret) {
> +			xe_gt_err_once(gt, "Failed to cap max freq on flush to %u, %pe\n",
> +				       BMG_MERT_FLUSH_FREQ_CAP, ERR_PTR(ret));
> +			return;
> +		}
> +
> +		atomic_set(&pc->flush_freq_limit, 1);
> +
> +		/*
> +		 * If user has previously changed max freq, stash that value to
> +		 * restore later, otherwise use the current max. New user
> +		 * requests wait on flush.
> +		 */
> +		if (pc->user_requested_max != 0)
> +			pc->stashed_max_freq = pc->user_requested_max;
> +		else
> +			pc->stashed_max_freq = max_freq;
> +	}
> +
> +	/*
> +	 * Wait for actual freq to go below the flush cap: even if the previous
> +	 * max was below cap, the current one might still be above it
> +	 */
> +	ret = wait_for_act_freq_limit(pc, BMG_MERT_FLUSH_FREQ_CAP);
> +	if (ret)
> +		xe_gt_err_once(gt, "Actual freq did not reduce to %u, %pe\n",
> +			       BMG_MERT_FLUSH_FREQ_CAP, ERR_PTR(ret));
> +}
> +
> +/**
> + * xe_guc_pc_remove_flush_freq_limit() - Remove max GT freq limit after L2 flush completes.
> + * @pc: the xe_guc_pc object
> + *
> + * Retrieve the previous GT max frequency value.
> + */
> +void xe_guc_pc_remove_flush_freq_limit(struct xe_guc_pc *pc)
> +{
> +	struct xe_gt *gt = pc_to_gt(pc);
> +	int ret = 0;
> +
> +	if (!needs_flush_freq_limit(pc))
> +		return;
> +
> +	if (!atomic_read(&pc->flush_freq_limit))
> +		return;
> +
> +	mutex_lock(&pc->freq_lock);
> +
> +	ret = pc_set_max_freq(&gt->uc.guc.pc, pc->stashed_max_freq);
> +	if (ret)
> +		xe_gt_err_once(gt, "Failed to restore max freq %u:%d",
> +			       pc->stashed_max_freq, ret);
> +
> +	atomic_set(&pc->flush_freq_limit, 0);
> +	mutex_unlock(&pc->freq_lock);
> +	wake_up_var(&pc->flush_freq_limit);
> +}
> +
>  static int pc_set_mert_freq_cap(struct xe_guc_pc *pc)
>  {
>  	int ret;
> diff --git a/drivers/gpu/drm/xe/xe_guc_pc.h b/drivers/gpu/drm/xe/xe_guc_pc.h
> index 0a2664d5c8114..52ecdd5ddbff2 100644
> --- a/drivers/gpu/drm/xe/xe_guc_pc.h
> +++ b/drivers/gpu/drm/xe/xe_guc_pc.h
> @@ -38,5 +38,7 @@ u64 xe_guc_pc_mc6_residency(struct xe_guc_pc *pc);
>  void xe_guc_pc_init_early(struct xe_guc_pc *pc);
>  int xe_guc_pc_restore_stashed_freq(struct xe_guc_pc *pc);
>  void xe_guc_pc_raise_unslice(struct xe_guc_pc *pc);
> +void xe_guc_pc_apply_flush_freq_limit(struct xe_guc_pc *pc);
> +void xe_guc_pc_remove_flush_freq_limit(struct xe_guc_pc *pc);
>  
>  #endif /* _XE_GUC_PC_H_ */
> diff --git a/drivers/gpu/drm/xe/xe_guc_pc_types.h b/drivers/gpu/drm/xe/xe_guc_pc_types.h
> index 2978ac9a249b5..c02053948a579 100644
> --- a/drivers/gpu/drm/xe/xe_guc_pc_types.h
> +++ b/drivers/gpu/drm/xe/xe_guc_pc_types.h
> @@ -15,6 +15,8 @@
>  struct xe_guc_pc {
>  	/** @bo: GGTT buffer object that is shared with GuC PC */
>  	struct xe_bo *bo;
> +	/** @flush_freq_limit: 1 when max freq changes are limited by driver */
> +	atomic_t flush_freq_limit;
>  	/** @rp0_freq: HW RP0 frequency - The Maximum one */
>  	u32 rp0_freq;
>  	/** @rpa_freq: HW RPa frequency - The Achievable one */
> 
> -- 
> 2.49.0
> 

Re: [PATCH v4 3/3] drm/xe/bmg: Update Wa_22019338487

[Lucas De Marchi]

On Mon, Jun 16, 2025 at 10:37:49AM -0400, Rodrigo Vivi wrote:
>On Sun, Jun 15, 2025 at 11:17:36PM -0700, Lucas De Marchi wrote:
>> From: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
>>
>> Limit GT max frequency to 2600Mhz during the L2 flush. Also, ensure
>> GT actual frequency is limited to that value before performing the
>> cache flush.
>>
>> v2: Use generic names, ensure user set max frequency requests wait
>> for flush to complete (Rodrigo)
>> v3:
>>  - User requests wait via wait_var_event_timeout (Lucas)
>>  - Close races on flush + user requests (Lucas)
>>  - Fix xe_guc_pc_remove_flush_freq_limit() being called on last gt
>>    rather than root gt (Lucas)
>>
>> Fixes: aaa08078e725 ("drm/xe/bmg: Apply Wa_22019338487")
>> Fixes: 01570b446939 ("drm/xe/bmg: implement Wa_16023588340")
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  drivers/gpu/drm/xe/xe_device.c       |  13 +++-
>>  drivers/gpu/drm/xe/xe_guc_pc.c       | 125 +++++++++++++++++++++++++++++++++++
>>  drivers/gpu/drm/xe/xe_guc_pc.h       |   2 +
>>  drivers/gpu/drm/xe/xe_guc_pc_types.h |   2 +
>>  4 files changed, 139 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
>> index 7e87344943cdf..6ff373ad0a965 100644
>> --- a/drivers/gpu/drm/xe/xe_device.c
>> +++ b/drivers/gpu/drm/xe/xe_device.c
>> @@ -40,6 +40,7 @@
>>  #include "xe_gt_printk.h"
>>  #include "xe_gt_sriov_vf.h"
>>  #include "xe_guc.h"
>> +#include "xe_guc_pc.h"
>>  #include "xe_hw_engine_group.h"
>>  #include "xe_hwmon.h"
>>  #include "xe_irq.h"
>> @@ -1001,16 +1002,19 @@ void xe_device_wmb(struct xe_device *xe)
>>   */
>>  void xe_device_td_flush(struct xe_device *xe)
>>  {
>> -	struct xe_gt *gt;
>> +	struct xe_gt *gt, *root_gt;
>>  	unsigned int fw_ref;
>>  	u8 id;
>>
>>  	if (!IS_DGFX(xe) || GRAPHICS_VER(xe) < 20)
>>  		return;
>>
>> -	if (XE_WA(xe_root_mmio_gt(xe), 16023588340)) {
>> +	root_gt = xe_root_mmio_gt(xe);
>> +	xe_guc_pc_apply_flush_freq_limit(&root_gt->uc.guc.pc);
>> +
>> +	if (XE_WA(root_gt, 16023588340)) {
>>  		xe_device_l2_flush(xe);
>> -		return;
>> +		goto done;
>>  	}
>>
>>  	for_each_gt(gt, xe, id) {
>> @@ -1035,6 +1039,9 @@ void xe_device_td_flush(struct xe_device *xe)
>>
>>  		xe_force_wake_put(gt_to_fw(gt), fw_ref);
>>  	}
>> +
>> +done:
>> +	xe_guc_pc_remove_flush_freq_limit(&root_gt->uc.guc.pc);
>>  }
>>
>>  void xe_device_l2_flush(struct xe_device *xe)
>> diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
>> index d449eb0e3e8af..eab932655b2fb 100644
>> --- a/drivers/gpu/drm/xe/xe_guc_pc.c
>> +++ b/drivers/gpu/drm/xe/xe_guc_pc.c
>> @@ -7,7 +7,9 @@
>>
>>  #include <linux/cleanup.h>
>>  #include <linux/delay.h>
>> +#include <linux/jiffies.h>
>>  #include <linux/ktime.h>
>> +#include <linux/wait_bit.h>
>>
>>  #include <drm/drm_managed.h>
>>  #include <drm/drm_print.h>
>> @@ -53,9 +55,11 @@
>>  #define LNL_MERT_FREQ_CAP	800
>>  #define BMG_MERT_FREQ_CAP	2133
>>  #define BMG_MIN_FREQ		1200
>> +#define BMG_MERT_FLUSH_FREQ_CAP	2600
>>
>>  #define SLPC_RESET_TIMEOUT_MS 5 /* roughly 5ms, but no need for precision */
>>  #define SLPC_RESET_EXTENDED_TIMEOUT_MS 1000 /* To be used only at pc_start */
>> +#define SLPC_ACT_FREQ_TIMEOUT_MS 100
>>
>>  /**
>>   * DOC: GuC Power Conservation (PC)
>> @@ -143,6 +147,36 @@ static int wait_for_pc_state(struct xe_guc_pc *pc,
>>  	return -ETIMEDOUT;
>>  }
>>
>> +static int wait_for_flush_complete(struct xe_guc_pc *pc)
>> +{
>> +	const unsigned long timeout = msecs_to_jiffies(30);
>> +
>> +	if (!wait_var_event_timeout(&pc->flush_freq_limit,
>> +				    !atomic_read(&pc->flush_freq_limit),
>> +				    timeout))
>> +		return -ETIMEDOUT;
>> +
>> +	return 0;
>> +}
>> +
>> +static int wait_for_act_freq_limit(struct xe_guc_pc *pc, u32 freq)
>
>for a moment, the name of this function got me confused. I thought
>it was going to wait for the *exact* act freq, and then it would be
>risky because we can never know what PCODE will decide on extra
>throttles.
>
>But I don't have a suggestion for a better naming and reading the
>rest of the code showed it is doing things correctly.
>
>There's a risk though... if for some reason PCODE decides to keep
>freq high for a longer time... but likely unreal for this platform.
>
>Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

thanks... I will take a look in CI later today and think if we have
another better name or error handling.

While we are here, a couple improvements I noticed while doing the
changes; see below.

>
>> +{
>> +	int timeout_us = SLPC_ACT_FREQ_TIMEOUT_MS * USEC_PER_MSEC;
>> +	int slept, wait = 10;
>> +
>> +	for (slept = 0; slept < timeout_us;) {
>> +		if (xe_guc_pc_get_act_freq(pc) <= freq)
>> +			return 0;
>> +
>> +		usleep_range(wait, wait << 1);
>> +		slept += wait;
>> +		wait <<= 1;
>> +		if (slept + wait > timeout_us)
>> +			wait = timeout_us - slept;
>> +	}

1) wait functions

except from the call xe_guc_pc_get_act_freq(), this is a copy and paste
from the other wait function in this same file.
wait_for_flush_complete() was also a copy and paste and I moved it to
wait_var_event_timeout(), which is a better synchronization than what
this is doing.

All these functions to wait until a timeout are wrong: usleep_range()
will sleep for anything between the 2 values and we are simply using the
wait variable to decide on next sleep value. Worst case scenario, even
if unlikely, we will wait for log2(timeout_us) * timeout_us.

The xe_mmio_wait* get the wait checks right. I think we need another
function for the proper abstraction for that. Previously we decided
against because:

	a) this is the poorest synchronization method and it tends to be
	abused (see the preivous version of wait_for_flush_complete())
	b) adding such a thing in xe_helpers.h/xe_utils.h opens the
	door for things for doing other things there that should rather
	be using proper kernel infra
	c) previous attempts added that in xe_mmio or a new xe_utils.h
	and neither of them are good locations.

Proposal: xe_wait_for_cond() in xe_device.c. We should document when
it could be valid to use it: it's not a synchronization between 2
CPU threads but rather between GPU-FW-CPU; it doesn't fit the
xe_mmio_wait* because it needs to do things other than read and check
mmio value; and there's no other core kernel synchronization that can be
used. Then we migrate wait_for_act_freq_limit() and wait_for_pc_state()
to use it.

2) interaction with user requests

I kept the logic implemented on earlier versions, just changing how we
are waiting on it to complete. However, should userspace really wait?
Why not just update the stashed value that will be later flushed?
This way, if there are multitple requests they don't all keep waiting
and applying a random value depending on what thread was woken up first.
For example, with thread number also meaning the execution order:

freq_limit == xe_guc_pc_apply_flush_freq_limit()
set_max == xe_guc_pc_set_max_freq()

T0				t1	t2	t3	t4

xe_device_td_flush() {

	freq_limit
				set_max
					set_max
						set_max
							set_max
	freq_flush

Here all of t1, t2, t3, t4 are waiting on freq_flush from t0. The end
value will be whatever ordee threads are woken up later. I think that if
we change the implementation to simply set the stashed value, it will be
simpler (no need for wait) and better: the value is ultimately set in
freq_flush() and is always the last value.


thoughts?
Lucas De Marchi

>> +
>> +	return -ETIMEDOUT;
>> +}
>>  static int pc_action_reset(struct xe_guc_pc *pc)
>>  {
>>  	struct xe_guc_ct *ct = pc_to_ct(pc);
>> @@ -689,6 +723,11 @@ static int xe_guc_pc_set_max_freq_locked(struct xe_guc_pc *pc, u32 freq)
>>   */
>>  int xe_guc_pc_set_max_freq(struct xe_guc_pc *pc, u32 freq)
>>  {
>> +	if (XE_WA(pc_to_gt(pc), 22019338487)) {
>> +		if (wait_for_flush_complete(pc) != 0)
>> +			return -EAGAIN;
>> +	}
>> +
>>  	guard(mutex)(&pc->freq_lock);
>>
>>  	return xe_guc_pc_set_max_freq_locked(pc, freq);
>> @@ -889,6 +928,92 @@ static int pc_adjust_requested_freq(struct xe_guc_pc *pc)
>>  	return ret;
>>  }
>>
>> +static bool needs_flush_freq_limit(struct xe_guc_pc *pc)
>> +{
>> +	struct xe_gt *gt = pc_to_gt(pc);
>> +
>> +	return  XE_WA(gt, 22019338487) &&
>> +		pc->rp0_freq > BMG_MERT_FLUSH_FREQ_CAP;
>> +}
>> +
>> +/**
>> + * xe_guc_pc_apply_flush_freq_limit() - Limit max GT freq during L2 flush
>> + * @pc: the xe_guc_pc object
>> + *
>> + * As per the WA, reduce max GT frequency during L2 cache flush
>> + */
>> +void xe_guc_pc_apply_flush_freq_limit(struct xe_guc_pc *pc)
>> +{
>> +	struct xe_gt *gt = pc_to_gt(pc);
>> +	u32 max_freq;
>> +	int ret;
>> +
>> +	if (!needs_flush_freq_limit(pc))
>> +		return;
>> +
>> +	guard(mutex)(&pc->freq_lock);
>> +
>> +	ret = xe_guc_pc_get_max_freq_locked(pc, &max_freq);
>> +	if (!ret && max_freq > BMG_MERT_FLUSH_FREQ_CAP) {
>> +		ret = pc_set_max_freq(pc, BMG_MERT_FLUSH_FREQ_CAP);
>> +		if (ret) {
>> +			xe_gt_err_once(gt, "Failed to cap max freq on flush to %u, %pe\n",
>> +				       BMG_MERT_FLUSH_FREQ_CAP, ERR_PTR(ret));
>> +			return;
>> +		}
>> +
>> +		atomic_set(&pc->flush_freq_limit, 1);
>> +
>> +		/*
>> +		 * If user has previously changed max freq, stash that value to
>> +		 * restore later, otherwise use the current max. New user
>> +		 * requests wait on flush.
>> +		 */
>> +		if (pc->user_requested_max != 0)
>> +			pc->stashed_max_freq = pc->user_requested_max;
>> +		else
>> +			pc->stashed_max_freq = max_freq;
>> +	}
>> +
>> +	/*
>> +	 * Wait for actual freq to go below the flush cap: even if the previous
>> +	 * max was below cap, the current one might still be above it
>> +	 */
>> +	ret = wait_for_act_freq_limit(pc, BMG_MERT_FLUSH_FREQ_CAP);
>> +	if (ret)
>> +		xe_gt_err_once(gt, "Actual freq did not reduce to %u, %pe\n",
>> +			       BMG_MERT_FLUSH_FREQ_CAP, ERR_PTR(ret));
>> +}
>> +
>> +/**
>> + * xe_guc_pc_remove_flush_freq_limit() - Remove max GT freq limit after L2 flush completes.
>> + * @pc: the xe_guc_pc object
>> + *
>> + * Retrieve the previous GT max frequency value.
>> + */
>> +void xe_guc_pc_remove_flush_freq_limit(struct xe_guc_pc *pc)
>> +{
>> +	struct xe_gt *gt = pc_to_gt(pc);
>> +	int ret = 0;
>> +
>> +	if (!needs_flush_freq_limit(pc))
>> +		return;
>> +
>> +	if (!atomic_read(&pc->flush_freq_limit))
>> +		return;
>> +
>> +	mutex_lock(&pc->freq_lock);
>> +
>> +	ret = pc_set_max_freq(&gt->uc.guc.pc, pc->stashed_max_freq);
>> +	if (ret)
>> +		xe_gt_err_once(gt, "Failed to restore max freq %u:%d",
>> +			       pc->stashed_max_freq, ret);
>> +
>> +	atomic_set(&pc->flush_freq_limit, 0);
>> +	mutex_unlock(&pc->freq_lock);
>> +	wake_up_var(&pc->flush_freq_limit);
>> +}
>> +
>>  static int pc_set_mert_freq_cap(struct xe_guc_pc *pc)
>>  {
>>  	int ret;
>> diff --git a/drivers/gpu/drm/xe/xe_guc_pc.h b/drivers/gpu/drm/xe/xe_guc_pc.h
>> index 0a2664d5c8114..52ecdd5ddbff2 100644
>> --- a/drivers/gpu/drm/xe/xe_guc_pc.h
>> +++ b/drivers/gpu/drm/xe/xe_guc_pc.h
>> @@ -38,5 +38,7 @@ u64 xe_guc_pc_mc6_residency(struct xe_guc_pc *pc);
>>  void xe_guc_pc_init_early(struct xe_guc_pc *pc);
>>  int xe_guc_pc_restore_stashed_freq(struct xe_guc_pc *pc);
>>  void xe_guc_pc_raise_unslice(struct xe_guc_pc *pc);
>> +void xe_guc_pc_apply_flush_freq_limit(struct xe_guc_pc *pc);
>> +void xe_guc_pc_remove_flush_freq_limit(struct xe_guc_pc *pc);
>>
>>  #endif /* _XE_GUC_PC_H_ */
>> diff --git a/drivers/gpu/drm/xe/xe_guc_pc_types.h b/drivers/gpu/drm/xe/xe_guc_pc_types.h
>> index 2978ac9a249b5..c02053948a579 100644
>> --- a/drivers/gpu/drm/xe/xe_guc_pc_types.h
>> +++ b/drivers/gpu/drm/xe/xe_guc_pc_types.h
>> @@ -15,6 +15,8 @@
>>  struct xe_guc_pc {
>>  	/** @bo: GGTT buffer object that is shared with GuC PC */
>>  	struct xe_bo *bo;
>> +	/** @flush_freq_limit: 1 when max freq changes are limited by driver */
>> +	atomic_t flush_freq_limit;
>>  	/** @rp0_freq: HW RP0 frequency - The Maximum one */
>>  	u32 rp0_freq;
>>  	/** @rpa_freq: HW RPa frequency - The Achievable one */
>>
>> --
>> 2.49.0
>>

Re: [PATCH v4 3/3] drm/xe/bmg: Update Wa_22019338487

[Rodrigo Vivi]

On Mon, Jun 16, 2025 at 10:38:34AM -0500, Lucas De Marchi wrote:
> On Mon, Jun 16, 2025 at 10:37:49AM -0400, Rodrigo Vivi wrote:
> > On Sun, Jun 15, 2025 at 11:17:36PM -0700, Lucas De Marchi wrote:
> > > From: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> > > 
> > > Limit GT max frequency to 2600Mhz during the L2 flush. Also, ensure
> > > GT actual frequency is limited to that value before performing the
> > > cache flush.
> > > 
> > > v2: Use generic names, ensure user set max frequency requests wait
> > > for flush to complete (Rodrigo)
> > > v3:
> > >  - User requests wait via wait_var_event_timeout (Lucas)
> > >  - Close races on flush + user requests (Lucas)
> > >  - Fix xe_guc_pc_remove_flush_freq_limit() being called on last gt
> > >    rather than root gt (Lucas)
> > > 
> > > Fixes: aaa08078e725 ("drm/xe/bmg: Apply Wa_22019338487")
> > > Fixes: 01570b446939 ("drm/xe/bmg: implement Wa_16023588340")
> > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > ---
> > >  drivers/gpu/drm/xe/xe_device.c       |  13 +++-
> > >  drivers/gpu/drm/xe/xe_guc_pc.c       | 125 +++++++++++++++++++++++++++++++++++
> > >  drivers/gpu/drm/xe/xe_guc_pc.h       |   2 +
> > >  drivers/gpu/drm/xe/xe_guc_pc_types.h |   2 +
> > >  4 files changed, 139 insertions(+), 3 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
> > > index 7e87344943cdf..6ff373ad0a965 100644
> > > --- a/drivers/gpu/drm/xe/xe_device.c
> > > +++ b/drivers/gpu/drm/xe/xe_device.c
> > > @@ -40,6 +40,7 @@
> > >  #include "xe_gt_printk.h"
> > >  #include "xe_gt_sriov_vf.h"
> > >  #include "xe_guc.h"
> > > +#include "xe_guc_pc.h"
> > >  #include "xe_hw_engine_group.h"
> > >  #include "xe_hwmon.h"
> > >  #include "xe_irq.h"
> > > @@ -1001,16 +1002,19 @@ void xe_device_wmb(struct xe_device *xe)
> > >   */
> > >  void xe_device_td_flush(struct xe_device *xe)
> > >  {
> > > -	struct xe_gt *gt;
> > > +	struct xe_gt *gt, *root_gt;
> > >  	unsigned int fw_ref;
> > >  	u8 id;
> > > 
> > >  	if (!IS_DGFX(xe) || GRAPHICS_VER(xe) < 20)
> > >  		return;
> > > 
> > > -	if (XE_WA(xe_root_mmio_gt(xe), 16023588340)) {
> > > +	root_gt = xe_root_mmio_gt(xe);
> > > +	xe_guc_pc_apply_flush_freq_limit(&root_gt->uc.guc.pc);
> > > +
> > > +	if (XE_WA(root_gt, 16023588340)) {
> > >  		xe_device_l2_flush(xe);
> > > -		return;
> > > +		goto done;
> > >  	}
> > > 
> > >  	for_each_gt(gt, xe, id) {
> > > @@ -1035,6 +1039,9 @@ void xe_device_td_flush(struct xe_device *xe)
> > > 
> > >  		xe_force_wake_put(gt_to_fw(gt), fw_ref);
> > >  	}
> > > +
> > > +done:
> > > +	xe_guc_pc_remove_flush_freq_limit(&root_gt->uc.guc.pc);
> > >  }
> > > 
> > >  void xe_device_l2_flush(struct xe_device *xe)
> > > diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
> > > index d449eb0e3e8af..eab932655b2fb 100644
> > > --- a/drivers/gpu/drm/xe/xe_guc_pc.c
> > > +++ b/drivers/gpu/drm/xe/xe_guc_pc.c
> > > @@ -7,7 +7,9 @@
> > > 
> > >  #include <linux/cleanup.h>
> > >  #include <linux/delay.h>
> > > +#include <linux/jiffies.h>
> > >  #include <linux/ktime.h>
> > > +#include <linux/wait_bit.h>
> > > 
> > >  #include <drm/drm_managed.h>
> > >  #include <drm/drm_print.h>
> > > @@ -53,9 +55,11 @@
> > >  #define LNL_MERT_FREQ_CAP	800
> > >  #define BMG_MERT_FREQ_CAP	2133
> > >  #define BMG_MIN_FREQ		1200
> > > +#define BMG_MERT_FLUSH_FREQ_CAP	2600
> > > 
> > >  #define SLPC_RESET_TIMEOUT_MS 5 /* roughly 5ms, but no need for precision */
> > >  #define SLPC_RESET_EXTENDED_TIMEOUT_MS 1000 /* To be used only at pc_start */
> > > +#define SLPC_ACT_FREQ_TIMEOUT_MS 100
> > > 
> > >  /**
> > >   * DOC: GuC Power Conservation (PC)
> > > @@ -143,6 +147,36 @@ static int wait_for_pc_state(struct xe_guc_pc *pc,
> > >  	return -ETIMEDOUT;
> > >  }
> > > 
> > > +static int wait_for_flush_complete(struct xe_guc_pc *pc)
> > > +{
> > > +	const unsigned long timeout = msecs_to_jiffies(30);
> > > +
> > > +	if (!wait_var_event_timeout(&pc->flush_freq_limit,
> > > +				    !atomic_read(&pc->flush_freq_limit),
> > > +				    timeout))
> > > +		return -ETIMEDOUT;
> > > +
> > > +	return 0;
> > > +}
> > > +
> > > +static int wait_for_act_freq_limit(struct xe_guc_pc *pc, u32 freq)
> > 
> > for a moment, the name of this function got me confused. I thought
> > it was going to wait for the *exact* act freq, and then it would be
> > risky because we can never know what PCODE will decide on extra
> > throttles.
> > 
> > But I don't have a suggestion for a better naming and reading the
> > rest of the code showed it is doing things correctly.
> > 
> > There's a risk though... if for some reason PCODE decides to keep
> > freq high for a longer time... but likely unreal for this platform.
> > 
> > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> 
> thanks... I will take a look in CI later today and think if we have
> another better name or error handling.
> 
> While we are here, a couple improvements I noticed while doing the
> changes; see below.
> 
> > 
> > > +{
> > > +	int timeout_us = SLPC_ACT_FREQ_TIMEOUT_MS * USEC_PER_MSEC;
> > > +	int slept, wait = 10;
> > > +
> > > +	for (slept = 0; slept < timeout_us;) {
> > > +		if (xe_guc_pc_get_act_freq(pc) <= freq)
> > > +			return 0;
> > > +
> > > +		usleep_range(wait, wait << 1);
> > > +		slept += wait;
> > > +		wait <<= 1;
> > > +		if (slept + wait > timeout_us)
> > > +			wait = timeout_us - slept;
> > > +	}
> 
> 1) wait functions
> 
> except from the call xe_guc_pc_get_act_freq(), this is a copy and paste
> from the other wait function in this same file.
> wait_for_flush_complete() was also a copy and paste and I moved it to
> wait_var_event_timeout(), which is a better synchronization than what
> this is doing.
> 
> All these functions to wait until a timeout are wrong: usleep_range()
> will sleep for anything between the 2 values and we are simply using the
> wait variable to decide on next sleep value. Worst case scenario, even
> if unlikely, we will wait for log2(timeout_us) * timeout_us.
> 
> The xe_mmio_wait* get the wait checks right. I think we need another
> function for the proper abstraction for that. Previously we decided
> against because:
> 
> 	a) this is the poorest synchronization method and it tends to be
> 	abused (see the preivous version of wait_for_flush_complete())
> 	b) adding such a thing in xe_helpers.h/xe_utils.h opens the
> 	door for things for doing other things there that should rather
> 	be using proper kernel infra
> 	c) previous attempts added that in xe_mmio or a new xe_utils.h
> 	and neither of them are good locations.
> 
> Proposal: xe_wait_for_cond() in xe_device.c. We should document when
> it could be valid to use it: it's not a synchronization between 2
> CPU threads but rather between GPU-FW-CPU; it doesn't fit the
> xe_mmio_wait* because it needs to do things other than read and check
> mmio value; and there's no other core kernel synchronization that can be
> used. Then we migrate wait_for_act_freq_limit() and wait_for_pc_state()
> to use it.

ack on this. But it could be a follow up right?!

> 
> 2) interaction with user requests
> 
> I kept the logic implemented on earlier versions, just changing how we
> are waiting on it to complete. However, should userspace really wait?
> Why not just update the stashed value that will be later flushed?
> This way, if there are multitple requests they don't all keep waiting
> and applying a random value depending on what thread was woken up first.
> For example, with thread number also meaning the execution order:
> 
> freq_limit == xe_guc_pc_apply_flush_freq_limit()
> set_max == xe_guc_pc_set_max_freq()
> 
> T0				t1	t2	t3	t4
> 
> xe_device_td_flush() {
> 
> 	freq_limit
> 				set_max
> 					set_max
> 						set_max
> 							set_max
> 	freq_flush
> 
> Here all of t1, t2, t3, t4 are waiting on freq_flush from t0. The end
> value will be whatever ordee threads are woken up later. I think that if
> we change the implementation to simply set the stashed value, it will be
> simpler (no need for wait) and better: the value is ultimately set in
> freq_flush() and is always the last value.

We could try, but I'm afraid that this will break our IGT test cases
badly. Because when we read back what we just requested, we want to
see the value applied.

Or we will open the can of warms of the soft_freq design that i915
has and all the confusions it brings...

> 
> 
> thoughts?
> Lucas De Marchi
> 
> > > +
> > > +	return -ETIMEDOUT;
> > > +}
> > >  static int pc_action_reset(struct xe_guc_pc *pc)
> > >  {
> > >  	struct xe_guc_ct *ct = pc_to_ct(pc);
> > > @@ -689,6 +723,11 @@ static int xe_guc_pc_set_max_freq_locked(struct xe_guc_pc *pc, u32 freq)
> > >   */
> > >  int xe_guc_pc_set_max_freq(struct xe_guc_pc *pc, u32 freq)
> > >  {
> > > +	if (XE_WA(pc_to_gt(pc), 22019338487)) {
> > > +		if (wait_for_flush_complete(pc) != 0)
> > > +			return -EAGAIN;
> > > +	}
> > > +
> > >  	guard(mutex)(&pc->freq_lock);
> > > 
> > >  	return xe_guc_pc_set_max_freq_locked(pc, freq);
> > > @@ -889,6 +928,92 @@ static int pc_adjust_requested_freq(struct xe_guc_pc *pc)
> > >  	return ret;
> > >  }
> > > 
> > > +static bool needs_flush_freq_limit(struct xe_guc_pc *pc)
> > > +{
> > > +	struct xe_gt *gt = pc_to_gt(pc);
> > > +
> > > +	return  XE_WA(gt, 22019338487) &&
> > > +		pc->rp0_freq > BMG_MERT_FLUSH_FREQ_CAP;
> > > +}
> > > +
> > > +/**
> > > + * xe_guc_pc_apply_flush_freq_limit() - Limit max GT freq during L2 flush
> > > + * @pc: the xe_guc_pc object
> > > + *
> > > + * As per the WA, reduce max GT frequency during L2 cache flush
> > > + */
> > > +void xe_guc_pc_apply_flush_freq_limit(struct xe_guc_pc *pc)
> > > +{
> > > +	struct xe_gt *gt = pc_to_gt(pc);
> > > +	u32 max_freq;
> > > +	int ret;
> > > +
> > > +	if (!needs_flush_freq_limit(pc))
> > > +		return;
> > > +
> > > +	guard(mutex)(&pc->freq_lock);
> > > +
> > > +	ret = xe_guc_pc_get_max_freq_locked(pc, &max_freq);
> > > +	if (!ret && max_freq > BMG_MERT_FLUSH_FREQ_CAP) {
> > > +		ret = pc_set_max_freq(pc, BMG_MERT_FLUSH_FREQ_CAP);
> > > +		if (ret) {
> > > +			xe_gt_err_once(gt, "Failed to cap max freq on flush to %u, %pe\n",
> > > +				       BMG_MERT_FLUSH_FREQ_CAP, ERR_PTR(ret));
> > > +			return;
> > > +		}
> > > +
> > > +		atomic_set(&pc->flush_freq_limit, 1);
> > > +
> > > +		/*
> > > +		 * If user has previously changed max freq, stash that value to
> > > +		 * restore later, otherwise use the current max. New user
> > > +		 * requests wait on flush.
> > > +		 */
> > > +		if (pc->user_requested_max != 0)
> > > +			pc->stashed_max_freq = pc->user_requested_max;
> > > +		else
> > > +			pc->stashed_max_freq = max_freq;
> > > +	}
> > > +
> > > +	/*
> > > +	 * Wait for actual freq to go below the flush cap: even if the previous
> > > +	 * max was below cap, the current one might still be above it
> > > +	 */
> > > +	ret = wait_for_act_freq_limit(pc, BMG_MERT_FLUSH_FREQ_CAP);
> > > +	if (ret)
> > > +		xe_gt_err_once(gt, "Actual freq did not reduce to %u, %pe\n",
> > > +			       BMG_MERT_FLUSH_FREQ_CAP, ERR_PTR(ret));
> > > +}
> > > +
> > > +/**
> > > + * xe_guc_pc_remove_flush_freq_limit() - Remove max GT freq limit after L2 flush completes.
> > > + * @pc: the xe_guc_pc object
> > > + *
> > > + * Retrieve the previous GT max frequency value.
> > > + */
> > > +void xe_guc_pc_remove_flush_freq_limit(struct xe_guc_pc *pc)
> > > +{
> > > +	struct xe_gt *gt = pc_to_gt(pc);
> > > +	int ret = 0;
> > > +
> > > +	if (!needs_flush_freq_limit(pc))
> > > +		return;
> > > +
> > > +	if (!atomic_read(&pc->flush_freq_limit))
> > > +		return;
> > > +
> > > +	mutex_lock(&pc->freq_lock);
> > > +
> > > +	ret = pc_set_max_freq(&gt->uc.guc.pc, pc->stashed_max_freq);
> > > +	if (ret)
> > > +		xe_gt_err_once(gt, "Failed to restore max freq %u:%d",
> > > +			       pc->stashed_max_freq, ret);
> > > +
> > > +	atomic_set(&pc->flush_freq_limit, 0);
> > > +	mutex_unlock(&pc->freq_lock);
> > > +	wake_up_var(&pc->flush_freq_limit);
> > > +}
> > > +
> > >  static int pc_set_mert_freq_cap(struct xe_guc_pc *pc)
> > >  {
> > >  	int ret;
> > > diff --git a/drivers/gpu/drm/xe/xe_guc_pc.h b/drivers/gpu/drm/xe/xe_guc_pc.h
> > > index 0a2664d5c8114..52ecdd5ddbff2 100644
> > > --- a/drivers/gpu/drm/xe/xe_guc_pc.h
> > > +++ b/drivers/gpu/drm/xe/xe_guc_pc.h
> > > @@ -38,5 +38,7 @@ u64 xe_guc_pc_mc6_residency(struct xe_guc_pc *pc);
> > >  void xe_guc_pc_init_early(struct xe_guc_pc *pc);
> > >  int xe_guc_pc_restore_stashed_freq(struct xe_guc_pc *pc);
> > >  void xe_guc_pc_raise_unslice(struct xe_guc_pc *pc);
> > > +void xe_guc_pc_apply_flush_freq_limit(struct xe_guc_pc *pc);
> > > +void xe_guc_pc_remove_flush_freq_limit(struct xe_guc_pc *pc);
> > > 
> > >  #endif /* _XE_GUC_PC_H_ */
> > > diff --git a/drivers/gpu/drm/xe/xe_guc_pc_types.h b/drivers/gpu/drm/xe/xe_guc_pc_types.h
> > > index 2978ac9a249b5..c02053948a579 100644
> > > --- a/drivers/gpu/drm/xe/xe_guc_pc_types.h
> > > +++ b/drivers/gpu/drm/xe/xe_guc_pc_types.h
> > > @@ -15,6 +15,8 @@
> > >  struct xe_guc_pc {
> > >  	/** @bo: GGTT buffer object that is shared with GuC PC */
> > >  	struct xe_bo *bo;
> > > +	/** @flush_freq_limit: 1 when max freq changes are limited by driver */
> > > +	atomic_t flush_freq_limit;
> > >  	/** @rp0_freq: HW RP0 frequency - The Maximum one */
> > >  	u32 rp0_freq;
> > >  	/** @rpa_freq: HW RPa frequency - The Achievable one */
> > > 
> > > --
> > > 2.49.0
> > > 

Re: [PATCH v4 3/3] drm/xe/bmg: Update Wa_22019338487

[Lucas De Marchi]

On Mon, Jun 16, 2025 at 04:35:48PM -0400, Rodrigo Vivi wrote:
>On Mon, Jun 16, 2025 at 10:38:34AM -0500, Lucas De Marchi wrote:
>> On Mon, Jun 16, 2025 at 10:37:49AM -0400, Rodrigo Vivi wrote:
>> > On Sun, Jun 15, 2025 at 11:17:36PM -0700, Lucas De Marchi wrote:
>> > > From: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
>> > >
>> > > Limit GT max frequency to 2600Mhz during the L2 flush. Also, ensure
>> > > GT actual frequency is limited to that value before performing the
>> > > cache flush.
>> > >
>> > > v2: Use generic names, ensure user set max frequency requests wait
>> > > for flush to complete (Rodrigo)
>> > > v3:
>> > >  - User requests wait via wait_var_event_timeout (Lucas)
>> > >  - Close races on flush + user requests (Lucas)
>> > >  - Fix xe_guc_pc_remove_flush_freq_limit() being called on last gt
>> > >    rather than root gt (Lucas)
>> > >
>> > > Fixes: aaa08078e725 ("drm/xe/bmg: Apply Wa_22019338487")
>> > > Fixes: 01570b446939 ("drm/xe/bmg: implement Wa_16023588340")
>> > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> > > Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
>> > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> > > ---
>> > >  drivers/gpu/drm/xe/xe_device.c       |  13 +++-
>> > >  drivers/gpu/drm/xe/xe_guc_pc.c       | 125 +++++++++++++++++++++++++++++++++++
>> > >  drivers/gpu/drm/xe/xe_guc_pc.h       |   2 +
>> > >  drivers/gpu/drm/xe/xe_guc_pc_types.h |   2 +
>> > >  4 files changed, 139 insertions(+), 3 deletions(-)
>> > >
>> > > diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
>> > > index 7e87344943cdf..6ff373ad0a965 100644
>> > > --- a/drivers/gpu/drm/xe/xe_device.c
>> > > +++ b/drivers/gpu/drm/xe/xe_device.c
>> > > @@ -40,6 +40,7 @@
>> > >  #include "xe_gt_printk.h"
>> > >  #include "xe_gt_sriov_vf.h"
>> > >  #include "xe_guc.h"
>> > > +#include "xe_guc_pc.h"
>> > >  #include "xe_hw_engine_group.h"
>> > >  #include "xe_hwmon.h"
>> > >  #include "xe_irq.h"
>> > > @@ -1001,16 +1002,19 @@ void xe_device_wmb(struct xe_device *xe)
>> > >   */
>> > >  void xe_device_td_flush(struct xe_device *xe)
>> > >  {
>> > > -	struct xe_gt *gt;
>> > > +	struct xe_gt *gt, *root_gt;
>> > >  	unsigned int fw_ref;
>> > >  	u8 id;
>> > >
>> > >  	if (!IS_DGFX(xe) || GRAPHICS_VER(xe) < 20)
>> > >  		return;
>> > >
>> > > -	if (XE_WA(xe_root_mmio_gt(xe), 16023588340)) {
>> > > +	root_gt = xe_root_mmio_gt(xe);
>> > > +	xe_guc_pc_apply_flush_freq_limit(&root_gt->uc.guc.pc);
>> > > +
>> > > +	if (XE_WA(root_gt, 16023588340)) {
>> > >  		xe_device_l2_flush(xe);
>> > > -		return;
>> > > +		goto done;
>> > >  	}
>> > >
>> > >  	for_each_gt(gt, xe, id) {
>> > > @@ -1035,6 +1039,9 @@ void xe_device_td_flush(struct xe_device *xe)
>> > >
>> > >  		xe_force_wake_put(gt_to_fw(gt), fw_ref);
>> > >  	}
>> > > +
>> > > +done:
>> > > +	xe_guc_pc_remove_flush_freq_limit(&root_gt->uc.guc.pc);
>> > >  }
>> > >
>> > >  void xe_device_l2_flush(struct xe_device *xe)
>> > > diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
>> > > index d449eb0e3e8af..eab932655b2fb 100644
>> > > --- a/drivers/gpu/drm/xe/xe_guc_pc.c
>> > > +++ b/drivers/gpu/drm/xe/xe_guc_pc.c
>> > > @@ -7,7 +7,9 @@
>> > >
>> > >  #include <linux/cleanup.h>
>> > >  #include <linux/delay.h>
>> > > +#include <linux/jiffies.h>
>> > >  #include <linux/ktime.h>
>> > > +#include <linux/wait_bit.h>
>> > >
>> > >  #include <drm/drm_managed.h>
>> > >  #include <drm/drm_print.h>
>> > > @@ -53,9 +55,11 @@
>> > >  #define LNL_MERT_FREQ_CAP	800
>> > >  #define BMG_MERT_FREQ_CAP	2133
>> > >  #define BMG_MIN_FREQ		1200
>> > > +#define BMG_MERT_FLUSH_FREQ_CAP	2600
>> > >
>> > >  #define SLPC_RESET_TIMEOUT_MS 5 /* roughly 5ms, but no need for precision */
>> > >  #define SLPC_RESET_EXTENDED_TIMEOUT_MS 1000 /* To be used only at pc_start */
>> > > +#define SLPC_ACT_FREQ_TIMEOUT_MS 100
>> > >
>> > >  /**
>> > >   * DOC: GuC Power Conservation (PC)
>> > > @@ -143,6 +147,36 @@ static int wait_for_pc_state(struct xe_guc_pc *pc,
>> > >  	return -ETIMEDOUT;
>> > >  }
>> > >
>> > > +static int wait_for_flush_complete(struct xe_guc_pc *pc)
>> > > +{
>> > > +	const unsigned long timeout = msecs_to_jiffies(30);
>> > > +
>> > > +	if (!wait_var_event_timeout(&pc->flush_freq_limit,
>> > > +				    !atomic_read(&pc->flush_freq_limit),
>> > > +				    timeout))
>> > > +		return -ETIMEDOUT;
>> > > +
>> > > +	return 0;
>> > > +}
>> > > +
>> > > +static int wait_for_act_freq_limit(struct xe_guc_pc *pc, u32 freq)
>> >
>> > for a moment, the name of this function got me confused. I thought
>> > it was going to wait for the *exact* act freq, and then it would be
>> > risky because we can never know what PCODE will decide on extra
>> > throttles.
>> >
>> > But I don't have a suggestion for a better naming and reading the
>> > rest of the code showed it is doing things correctly.
>> >
>> > There's a risk though... if for some reason PCODE decides to keep
>> > freq high for a longer time... but likely unreal for this platform.
>> >
>> > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>
>> thanks... I will take a look in CI later today and think if we have
>> another better name or error handling.
>>
>> While we are here, a couple improvements I noticed while doing the
>> changes; see below.
>>
>> >
>> > > +{
>> > > +	int timeout_us = SLPC_ACT_FREQ_TIMEOUT_MS * USEC_PER_MSEC;
>> > > +	int slept, wait = 10;
>> > > +
>> > > +	for (slept = 0; slept < timeout_us;) {
>> > > +		if (xe_guc_pc_get_act_freq(pc) <= freq)
>> > > +			return 0;
>> > > +
>> > > +		usleep_range(wait, wait << 1);
>> > > +		slept += wait;
>> > > +		wait <<= 1;
>> > > +		if (slept + wait > timeout_us)
>> > > +			wait = timeout_us - slept;
>> > > +	}
>>
>> 1) wait functions
>>
>> except from the call xe_guc_pc_get_act_freq(), this is a copy and paste
>> from the other wait function in this same file.
>> wait_for_flush_complete() was also a copy and paste and I moved it to
>> wait_var_event_timeout(), which is a better synchronization than what
>> this is doing.
>>
>> All these functions to wait until a timeout are wrong: usleep_range()
>> will sleep for anything between the 2 values and we are simply using the
>> wait variable to decide on next sleep value. Worst case scenario, even
>> if unlikely, we will wait for log2(timeout_us) * timeout_us.
>>
>> The xe_mmio_wait* get the wait checks right. I think we need another
>> function for the proper abstraction for that. Previously we decided
>> against because:
>>
>> 	a) this is the poorest synchronization method and it tends to be
>> 	abused (see the preivous version of wait_for_flush_complete())
>> 	b) adding such a thing in xe_helpers.h/xe_utils.h opens the
>> 	door for things for doing other things there that should rather
>> 	be using proper kernel infra
>> 	c) previous attempts added that in xe_mmio or a new xe_utils.h
>> 	and neither of them are good locations.
>>
>> Proposal: xe_wait_for_cond() in xe_device.c. We should document when
>> it could be valid to use it: it's not a synchronization between 2
>> CPU threads but rather between GPU-FW-CPU; it doesn't fit the
>> xe_mmio_wait* because it needs to do things other than read and check
>> mmio value; and there's no other core kernel synchronization that can be
>> used. Then we migrate wait_for_act_freq_limit() and wait_for_pc_state()
>> to use it.
>
>ack on this. But it could be a follow up right?!

yes, follow up. I don't want to make this depend on refactors like that.

>
>>
>> 2) interaction with user requests
>>
>> I kept the logic implemented on earlier versions, just changing how we
>> are waiting on it to complete. However, should userspace really wait?
>> Why not just update the stashed value that will be later flushed?
>> This way, if there are multitple requests they don't all keep waiting
>> and applying a random value depending on what thread was woken up first.
>> For example, with thread number also meaning the execution order:
>>
>> freq_limit == xe_guc_pc_apply_flush_freq_limit()
>> set_max == xe_guc_pc_set_max_freq()
>>
>> T0				t1	t2	t3	t4
>>
>> xe_device_td_flush() {
>>
>> 	freq_limit
>> 				set_max
>> 					set_max
>> 						set_max
>> 							set_max
>> 	freq_flush
>>
>> Here all of t1, t2, t3, t4 are waiting on freq_flush from t0. The end
>> value will be whatever ordee threads are woken up later. I think that if
>> we change the implementation to simply set the stashed value, it will be
>> simpler (no need for wait) and better: the value is ultimately set in
>> freq_flush() and is always the last value.
>
>We could try, but I'm afraid that this will break our IGT test cases
>badly. Because when we read back what we just requested, we want to
>see the value applied.
>
>Or we will open the can of warms of the soft_freq design that i915
>has and all the confusions it brings...

ack. I will take a look later.

Thanks
Lucas De Marchi

✗ CI.checkpatch: warning for drm/xe: Update Wa_22019338487

[Patchwork]

== Series Details ==

Series: drm/xe: Update Wa_22019338487
URL   : https://patchwork.freedesktop.org/series/150300/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
f8ff75ae1d2127635239b134695774ed4045d05b
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit ccc12ce506e8d31c302ab2fe7ca9f8acea1f18ba
Author: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Date:   Sun Jun 15 23:17:36 2025 -0700

    drm/xe/bmg: Update Wa_22019338487
    
    Limit GT max frequency to 2600Mhz during the L2 flush. Also, ensure
    GT actual frequency is limited to that value before performing the
    cache flush.
    
    v2: Use generic names, ensure user set max frequency requests wait
    for flush to complete (Rodrigo)
    v3:
     - User requests wait via wait_var_event_timeout (Lucas)
     - Close races on flush + user requests (Lucas)
     - Fix xe_guc_pc_remove_flush_freq_limit() being called on last gt
       rather than root gt (Lucas)
    
    Fixes: aaa08078e725 ("drm/xe/bmg: Apply Wa_22019338487")
    Fixes: 01570b446939 ("drm/xe/bmg: implement Wa_16023588340")
    Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
    Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
    Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
+ /mt/dim checkpatch 4368f15da5e7f44130af5d76997265e5d48f3f45 drm-intel
7a0f47279c44 drm/xe/guc_pc: Add _locked variant for min/max freq
-:107: CHECK:LINE_SPACING: Please don't use multiple blank lines
#107: FILE: drivers/gpu/drm/xe/xe_guc_pc.c:627:
+
+

total: 0 errors, 0 warnings, 1 checks, 183 lines checked
94c8134ac756 drm/xe/xe_guc_pc: Lock once to update stashed frequencies
ccc12ce506e8 drm/xe/bmg: Update Wa_22019338487

✓ CI.KUnit: success for drm/xe: Update Wa_22019338487

[Patchwork]

== Series Details ==

Series: drm/xe: Update Wa_22019338487
URL   : https://patchwork.freedesktop.org/series/150300/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[06:24:05] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[06:24:10] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[06:24:36] Starting KUnit Kernel (1/1)...
[06:24:36] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[06:24:37] ================== guc_buf (11 subtests) ===================
[06:24:37] [PASSED] test_smallest
[06:24:37] [PASSED] test_largest
[06:24:37] [PASSED] test_granular
[06:24:37] [PASSED] test_unique
[06:24:37] [PASSED] test_overlap
[06:24:37] [PASSED] test_reusable
[06:24:37] [PASSED] test_too_big
[06:24:37] [PASSED] test_flush
[06:24:37] [PASSED] test_lookup
[06:24:37] [PASSED] test_data
[06:24:37] [PASSED] test_class
[06:24:37] ===================== [PASSED] guc_buf =====================
[06:24:37] =================== guc_dbm (7 subtests) ===================
[06:24:37] [PASSED] test_empty
[06:24:37] [PASSED] test_default
[06:24:37] ======================== test_size  ========================
[06:24:37] [PASSED] 4
[06:24:37] [PASSED] 8
[06:24:37] [PASSED] 32
[06:24:37] [PASSED] 256
[06:24:37] ==================== [PASSED] test_size ====================
[06:24:37] ======================= test_reuse  ========================
[06:24:37] [PASSED] 4
[06:24:37] [PASSED] 8
[06:24:37] [PASSED] 32
[06:24:37] [PASSED] 256
[06:24:37] =================== [PASSED] test_reuse ====================
[06:24:37] =================== test_range_overlap  ====================
[06:24:37] [PASSED] 4
[06:24:37] [PASSED] 8
[06:24:37] [PASSED] 32
[06:24:37] [PASSED] 256
[06:24:37] =============== [PASSED] test_range_overlap ================
[06:24:37] =================== test_range_compact  ====================
[06:24:37] [PASSED] 4
[06:24:37] [PASSED] 8
[06:24:37] [PASSED] 32
[06:24:37] [PASSED] 256
[06:24:37] =============== [PASSED] test_range_compact ================
[06:24:37] ==================== test_range_spare  =====================
[06:24:37] [PASSED] 4
[06:24:37] [PASSED] 8
[06:24:37] [PASSED] 32
[06:24:37] [PASSED] 256
[06:24:37] ================ [PASSED] test_range_spare =================
[06:24:37] ===================== [PASSED] guc_dbm =====================
[06:24:37] =================== guc_idm (6 subtests) ===================
[06:24:37] [PASSED] bad_init
[06:24:37] [PASSED] no_init
[06:24:37] [PASSED] init_fini
[06:24:37] [PASSED] check_used
[06:24:37] [PASSED] check_quota
[06:24:37] [PASSED] check_all
[06:24:37] ===================== [PASSED] guc_idm =====================
[06:24:37] ================== no_relay (3 subtests) ===================
[06:24:37] [PASSED] xe_drops_guc2pf_if_not_ready
[06:24:37] [PASSED] xe_drops_guc2vf_if_not_ready
[06:24:37] [PASSED] xe_rejects_send_if_not_ready
[06:24:37] ==================== [PASSED] no_relay =====================
[06:24:37] ================== pf_relay (14 subtests) ==================
[06:24:37] [PASSED] pf_rejects_guc2pf_too_short
[06:24:37] [PASSED] pf_rejects_guc2pf_too_long
[06:24:37] [PASSED] pf_rejects_guc2pf_no_payload
[06:24:37] [PASSED] pf_fails_no_payload
[06:24:37] [PASSED] pf_fails_bad_origin
[06:24:37] [PASSED] pf_fails_bad_type
[06:24:37] [PASSED] pf_txn_reports_error
[06:24:37] [PASSED] pf_txn_sends_pf2guc
[06:24:37] [PASSED] pf_sends_pf2guc
[06:24:37] [SKIPPED] pf_loopback_nop
[06:24:37] [SKIPPED] pf_loopback_echo
[06:24:37] [SKIPPED] pf_loopback_fail
[06:24:37] [SKIPPED] pf_loopback_busy
[06:24:37] [SKIPPED] pf_loopback_retry
[06:24:37] ==================== [PASSED] pf_relay =====================
[06:24:37] ================== vf_relay (3 subtests) ===================
[06:24:37] [PASSED] vf_rejects_guc2vf_too_short
[06:24:37] [PASSED] vf_rejects_guc2vf_too_long
[06:24:37] [PASSED] vf_rejects_guc2vf_no_payload
[06:24:37] ==================== [PASSED] vf_relay =====================
[06:24:37] ================= pf_service (11 subtests) =================
[06:24:37] [PASSED] pf_negotiate_any
[06:24:37] [PASSED] pf_negotiate_base_match
[06:24:37] [PASSED] pf_negotiate_base_newer
[06:24:37] [PASSED] pf_negotiate_base_next
[06:24:37] [SKIPPED] pf_negotiate_base_older
[06:24:37] [PASSED] pf_negotiate_base_prev
[06:24:37] [PASSED] pf_negotiate_latest_match
[06:24:37] [PASSED] pf_negotiate_latest_newer
[06:24:37] [PASSED] pf_negotiate_latest_next
[06:24:37] [SKIPPED] pf_negotiate_latest_older
[06:24:37] [SKIPPED] pf_negotiate_latest_prev
[06:24:37] =================== [PASSED] pf_service ====================
[06:24:37] ===================== lmtt (1 subtest) =====================
[06:24:37] ======================== test_ops  =========================
[06:24:37] [PASSED] 2-level
[06:24:37] [PASSED] multi-level
[06:24:37] ==================== [PASSED] test_ops =====================
[06:24:37] ====================== [PASSED] lmtt =======================
[06:24:37] =================== xe_mocs (2 subtests) ===================
[06:24:37] ================ xe_live_mocs_kernel_kunit  ================
[06:24:37] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[06:24:37] ================ xe_live_mocs_reset_kunit  =================
[06:24:37] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[06:24:37] ==================== [SKIPPED] xe_mocs =====================
[06:24:37] ================= xe_migrate (2 subtests) ==================
[06:24:37] ================= xe_migrate_sanity_kunit  =================
[06:24:37] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[06:24:37] ================== xe_validate_ccs_kunit  ==================
[06:24:37] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[06:24:37] =================== [SKIPPED] xe_migrate ===================
[06:24:37] ================== xe_dma_buf (1 subtest) ==================
[06:24:37] ==================== xe_dma_buf_kunit  =====================
[06:24:37] ================ [SKIPPED] xe_dma_buf_kunit ================
[06:24:37] =================== [SKIPPED] xe_dma_buf ===================
[06:24:37] ================= xe_bo_shrink (1 subtest) =================
[06:24:37] =================== xe_bo_shrink_kunit  ====================
[06:24:37] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[06:24:37] ================== [SKIPPED] xe_bo_shrink ==================
[06:24:37] ==================== xe_bo (2 subtests) ====================
[06:24:37] ================== xe_ccs_migrate_kunit  ===================
[06:24:37] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[06:24:37] ==================== xe_bo_evict_kunit  ====================
[06:24:37] =============== [SKIPPED] xe_bo_evict_kunit ================
[06:24:37] ===================== [SKIPPED] xe_bo ======================
[06:24:37] ==================== args (11 subtests) ====================
[06:24:37] [PASSED] count_args_test
[06:24:37] [PASSED] call_args_example
[06:24:37] [PASSED] call_args_test
[06:24:37] [PASSED] drop_first_arg_example
[06:24:37] [PASSED] drop_first_arg_test
[06:24:37] [PASSED] first_arg_example
[06:24:37] [PASSED] first_arg_test
[06:24:37] [PASSED] last_arg_example
[06:24:37] [PASSED] last_arg_test
[06:24:37] [PASSED] pick_arg_example
[06:24:37] [PASSED] sep_comma_example
[06:24:37] ====================== [PASSED] args =======================
[06:24:37] =================== xe_pci (2 subtests) ====================
[06:24:37] [PASSED] xe_gmdid_graphics_ip
[06:24:37] [PASSED] xe_gmdid_media_ip
[06:24:37] ===================== [PASSED] xe_pci ======================
[06:24:37] =================== xe_rtp (2 subtests) ====================
[06:24:37] =============== xe_rtp_process_to_sr_tests  ================
[06:24:37] [PASSED] coalesce-same-reg
[06:24:37] [PASSED] no-match-no-add
[06:24:37] [PASSED] match-or
[06:24:37] [PASSED] match-or-xfail
[06:24:37] [PASSED] no-match-no-add-multiple-rules
[06:24:37] [PASSED] two-regs-two-entries
[06:24:37] [PASSED] clr-one-set-other
[06:24:37] [PASSED] set-field
[06:24:37] [PASSED] conflict-duplicate
[06:24:37] [PASSED] conflict-not-disjoint
stty: 'standard input': Inappropriate ioctl for device
[06:24:37] [PASSED] conflict-reg-type
[06:24:37] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[06:24:37] ================== xe_rtp_process_tests  ===================
[06:24:37] [PASSED] active1
[06:24:37] [PASSED] active2
[06:24:37] [PASSED] active-inactive
[06:24:37] [PASSED] inactive-active
[06:24:37] [PASSED] inactive-1st_or_active-inactive
[06:24:37] [PASSED] inactive-2nd_or_active-inactive
[06:24:37] [PASSED] inactive-last_or_active-inactive
[06:24:37] [PASSED] inactive-no_or_active-inactive
[06:24:37] ============== [PASSED] xe_rtp_process_tests ===============
[06:24:37] ===================== [PASSED] xe_rtp ======================
[06:24:37] ==================== xe_wa (1 subtest) =====================
[06:24:37] ======================== xe_wa_gt  =========================
[06:24:37] [PASSED] TIGERLAKE (B0)
[06:24:37] [PASSED] DG1 (A0)
[06:24:37] [PASSED] DG1 (B0)
[06:24:37] [PASSED] ALDERLAKE_S (A0)
[06:24:37] [PASSED] ALDERLAKE_S (B0)
[06:24:37] [PASSED] ALDERLAKE_S (C0)
[06:24:37] [PASSED] ALDERLAKE_S (D0)
[06:24:37] [PASSED] ALDERLAKE_P (A0)
[06:24:37] [PASSED] ALDERLAKE_P (B0)
[06:24:37] [PASSED] ALDERLAKE_P (C0)
[06:24:37] [PASSED] ALDERLAKE_S_RPLS (D0)
[06:24:37] [PASSED] ALDERLAKE_P_RPLU (E0)
[06:24:37] [PASSED] DG2_G10 (C0)
[06:24:37] [PASSED] DG2_G11 (B1)
[06:24:37] [PASSED] DG2_G12 (A1)
[06:24:37] [PASSED] METEORLAKE (g:A0, m:A0)
[06:24:37] [PASSED] METEORLAKE (g:A0, m:A0)
[06:24:37] [PASSED] METEORLAKE (g:A0, m:A0)
[06:24:37] [PASSED] LUNARLAKE (g:A0, m:A0)
[06:24:37] [PASSED] LUNARLAKE (g:B0, m:A0)
[06:24:37] [PASSED] BATTLEMAGE (g:A0, m:A1)
[06:24:37] ==================== [PASSED] xe_wa_gt =====================
[06:24:37] ====================== [PASSED] xe_wa ======================
[06:24:37] ============================================================
[06:24:37] Testing complete. Ran 133 tests: passed: 117, skipped: 16
[06:24:37] Elapsed time: 31.279s total, 4.153s configuring, 26.810s building, 0.302s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[06:24:37] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[06:24:38] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[06:25:00] Starting KUnit Kernel (1/1)...
[06:25:00] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[06:25:00] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[06:25:00] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[06:25:00] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[06:25:00] =========== drm_validate_clone_mode (2 subtests) ===========
[06:25:00] ============== drm_test_check_in_clone_mode  ===============
[06:25:00] [PASSED] in_clone_mode
[06:25:00] [PASSED] not_in_clone_mode
[06:25:00] ========== [PASSED] drm_test_check_in_clone_mode ===========
[06:25:00] =============== drm_test_check_valid_clones  ===============
[06:25:00] [PASSED] not_in_clone_mode
[06:25:00] [PASSED] valid_clone
[06:25:00] [PASSED] invalid_clone
[06:25:00] =========== [PASSED] drm_test_check_valid_clones ===========
[06:25:00] ============= [PASSED] drm_validate_clone_mode =============
[06:25:00] ============= drm_validate_modeset (1 subtest) =============
[06:25:00] [PASSED] drm_test_check_connector_changed_modeset
[06:25:00] ============== [PASSED] drm_validate_modeset ===============
[06:25:00] ====== drm_test_bridge_get_current_state (2 subtests) ======
[06:25:00] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[06:25:00] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[06:25:00] ======== [PASSED] drm_test_bridge_get_current_state ========
[06:25:00] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[06:25:00] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[06:25:00] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[06:25:00] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[06:25:00] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[06:25:00] ============== drm_bridge_alloc (2 subtests) ===============
[06:25:00] [PASSED] drm_test_drm_bridge_alloc_basic
[06:25:00] [PASSED] drm_test_drm_bridge_alloc_get_put
[06:25:00] ================ [PASSED] drm_bridge_alloc =================
[06:25:00] ================== drm_buddy (7 subtests) ==================
[06:25:00] [PASSED] drm_test_buddy_alloc_limit
[06:25:00] [PASSED] drm_test_buddy_alloc_optimistic
[06:25:00] [PASSED] drm_test_buddy_alloc_pessimistic
[06:25:00] [PASSED] drm_test_buddy_alloc_pathological
[06:25:00] [PASSED] drm_test_buddy_alloc_contiguous
[06:25:00] [PASSED] drm_test_buddy_alloc_clear
[06:25:00] [PASSED] drm_test_buddy_alloc_range_bias
[06:25:00] ==================== [PASSED] drm_buddy ====================
[06:25:00] ============= drm_cmdline_parser (40 subtests) =============
[06:25:00] [PASSED] drm_test_cmdline_force_d_only
[06:25:00] [PASSED] drm_test_cmdline_force_D_only_dvi
[06:25:00] [PASSED] drm_test_cmdline_force_D_only_hdmi
[06:25:00] [PASSED] drm_test_cmdline_force_D_only_not_digital
[06:25:00] [PASSED] drm_test_cmdline_force_e_only
[06:25:00] [PASSED] drm_test_cmdline_res
[06:25:00] [PASSED] drm_test_cmdline_res_vesa
[06:25:00] [PASSED] drm_test_cmdline_res_vesa_rblank
[06:25:00] [PASSED] drm_test_cmdline_res_rblank
[06:25:00] [PASSED] drm_test_cmdline_res_bpp
[06:25:00] [PASSED] drm_test_cmdline_res_refresh
[06:25:00] [PASSED] drm_test_cmdline_res_bpp_refresh
[06:25:00] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[06:25:00] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[06:25:00] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[06:25:00] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[06:25:00] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[06:25:00] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[06:25:00] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[06:25:00] [PASSED] drm_test_cmdline_res_margins_force_on
[06:25:00] [PASSED] drm_test_cmdline_res_vesa_margins
[06:25:00] [PASSED] drm_test_cmdline_name
[06:25:00] [PASSED] drm_test_cmdline_name_bpp
[06:25:00] [PASSED] drm_test_cmdline_name_option
[06:25:00] [PASSED] drm_test_cmdline_name_bpp_option
[06:25:00] [PASSED] drm_test_cmdline_rotate_0
[06:25:00] [PASSED] drm_test_cmdline_rotate_90
[06:25:00] [PASSED] drm_test_cmdline_rotate_180
[06:25:00] [PASSED] drm_test_cmdline_rotate_270
[06:25:00] [PASSED] drm_test_cmdline_hmirror
[06:25:00] [PASSED] drm_test_cmdline_vmirror
[06:25:00] [PASSED] drm_test_cmdline_margin_options
[06:25:00] [PASSED] drm_test_cmdline_multiple_options
[06:25:00] [PASSED] drm_test_cmdline_bpp_extra_and_option
[06:25:00] [PASSED] drm_test_cmdline_extra_and_option
[06:25:00] [PASSED] drm_test_cmdline_freestanding_options
[06:25:00] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[06:25:00] [PASSED] drm_test_cmdline_panel_orientation
[06:25:00] ================ drm_test_cmdline_invalid  =================
[06:25:00] [PASSED] margin_only
[06:25:00] [PASSED] interlace_only
[06:25:00] [PASSED] res_missing_x
[06:25:00] [PASSED] res_missing_y
[06:25:00] [PASSED] res_bad_y
[06:25:00] [PASSED] res_missing_y_bpp
[06:25:00] [PASSED] res_bad_bpp
[06:25:00] [PASSED] res_bad_refresh
[06:25:00] [PASSED] res_bpp_refresh_force_on_off
[06:25:00] [PASSED] res_invalid_mode
[06:25:00] [PASSED] res_bpp_wrong_place_mode
[06:25:00] [PASSED] name_bpp_refresh
[06:25:00] [PASSED] name_refresh
[06:25:00] [PASSED] name_refresh_wrong_mode
[06:25:00] [PASSED] name_refresh_invalid_mode
[06:25:00] [PASSED] rotate_multiple
[06:25:00] [PASSED] rotate_invalid_val
[06:25:00] [PASSED] rotate_truncated
[06:25:00] [PASSED] invalid_option
[06:25:00] [PASSED] invalid_tv_option
[06:25:00] [PASSED] truncated_tv_option
[06:25:00] ============ [PASSED] drm_test_cmdline_invalid =============
[06:25:00] =============== drm_test_cmdline_tv_options  ===============
[06:25:00] [PASSED] NTSC
[06:25:00] [PASSED] NTSC_443
[06:25:00] [PASSED] NTSC_J
[06:25:00] [PASSED] PAL
[06:25:00] [PASSED] PAL_M
[06:25:00] [PASSED] PAL_N
[06:25:00] [PASSED] SECAM
[06:25:00] [PASSED] MONO_525
[06:25:00] [PASSED] MONO_625
[06:25:00] =========== [PASSED] drm_test_cmdline_tv_options ===========
[06:25:00] =============== [PASSED] drm_cmdline_parser ================
[06:25:00] ========== drmm_connector_hdmi_init (20 subtests) ==========
[06:25:00] [PASSED] drm_test_connector_hdmi_init_valid
[06:25:00] [PASSED] drm_test_connector_hdmi_init_bpc_8
[06:25:00] [PASSED] drm_test_connector_hdmi_init_bpc_10
[06:25:00] [PASSED] drm_test_connector_hdmi_init_bpc_12
[06:25:00] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[06:25:00] [PASSED] drm_test_connector_hdmi_init_bpc_null
[06:25:00] [PASSED] drm_test_connector_hdmi_init_formats_empty
[06:25:00] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[06:25:00] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[06:25:00] [PASSED] supported_formats=0x9 yuv420_allowed=1
[06:25:00] [PASSED] supported_formats=0x9 yuv420_allowed=0
[06:25:00] [PASSED] supported_formats=0x3 yuv420_allowed=1
[06:25:00] [PASSED] supported_formats=0x3 yuv420_allowed=0
[06:25:00] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[06:25:00] [PASSED] drm_test_connector_hdmi_init_null_ddc
[06:25:00] [PASSED] drm_test_connector_hdmi_init_null_product
[06:25:00] [PASSED] drm_test_connector_hdmi_init_null_vendor
[06:25:00] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[06:25:00] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[06:25:00] [PASSED] drm_test_connector_hdmi_init_product_valid
[06:25:00] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[06:25:00] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[06:25:00] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[06:25:00] ========= drm_test_connector_hdmi_init_type_valid  =========
[06:25:00] [PASSED] HDMI-A
[06:25:00] [PASSED] HDMI-B
[06:25:00] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[06:25:00] ======== drm_test_connector_hdmi_init_type_invalid  ========
[06:25:00] [PASSED] Unknown
[06:25:00] [PASSED] VGA
[06:25:00] [PASSED] DVI-I
[06:25:00] [PASSED] DVI-D
[06:25:00] [PASSED] DVI-A
[06:25:00] [PASSED] Composite
[06:25:00] [PASSED] SVIDEO
[06:25:00] [PASSED] LVDS
[06:25:00] [PASSED] Component
[06:25:00] [PASSED] DIN
[06:25:00] [PASSED] DP
[06:25:00] [PASSED] TV
[06:25:00] [PASSED] eDP
[06:25:00] [PASSED] Virtual
[06:25:00] [PASSED] DSI
[06:25:00] [PASSED] DPI
[06:25:00] [PASSED] Writeback
[06:25:00] [PASSED] SPI
[06:25:00] [PASSED] USB
[06:25:00] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[06:25:00] ============ [PASSED] drmm_connector_hdmi_init =============
[06:25:00] ============= drmm_connector_init (3 subtests) =============
[06:25:00] [PASSED] drm_test_drmm_connector_init
[06:25:00] [PASSED] drm_test_drmm_connector_init_null_ddc
[06:25:00] ========= drm_test_drmm_connector_init_type_valid  =========
[06:25:00] [PASSED] Unknown
[06:25:00] [PASSED] VGA
[06:25:00] [PASSED] DVI-I
[06:25:00] [PASSED] DVI-D
[06:25:00] [PASSED] DVI-A
[06:25:00] [PASSED] Composite
[06:25:00] [PASSED] SVIDEO
[06:25:00] [PASSED] LVDS
[06:25:00] [PASSED] Component
[06:25:00] [PASSED] DIN
[06:25:00] [PASSED] DP
[06:25:00] [PASSED] HDMI-A
[06:25:00] [PASSED] HDMI-B
[06:25:00] [PASSED] TV
[06:25:00] [PASSED] eDP
[06:25:00] [PASSED] Virtual
[06:25:00] [PASSED] DSI
[06:25:00] [PASSED] DPI
[06:25:00] [PASSED] Writeback
[06:25:00] [PASSED] SPI
[06:25:00] [PASSED] USB
[06:25:00] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[06:25:00] =============== [PASSED] drmm_connector_init ===============
[06:25:00] ========= drm_connector_dynamic_init (6 subtests) ==========
[06:25:00] [PASSED] drm_test_drm_connector_dynamic_init
[06:25:00] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[06:25:00] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[06:25:00] [PASSED] drm_test_drm_connector_dynamic_init_properties
[06:25:00] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[06:25:00] [PASSED] Unknown
[06:25:00] [PASSED] VGA
[06:25:00] [PASSED] DVI-I
[06:25:00] [PASSED] DVI-D
[06:25:00] [PASSED] DVI-A
[06:25:00] [PASSED] Composite
[06:25:00] [PASSED] SVIDEO
[06:25:00] [PASSED] LVDS
[06:25:00] [PASSED] Component
[06:25:00] [PASSED] DIN
[06:25:00] [PASSED] DP
[06:25:00] [PASSED] HDMI-A
[06:25:00] [PASSED] HDMI-B
[06:25:00] [PASSED] TV
[06:25:00] [PASSED] eDP
[06:25:00] [PASSED] Virtual
[06:25:00] [PASSED] DSI
[06:25:00] [PASSED] DPI
[06:25:00] [PASSED] Writeback
[06:25:00] [PASSED] SPI
[06:25:00] [PASSED] USB
[06:25:00] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[06:25:00] ======== drm_test_drm_connector_dynamic_init_name  =========
[06:25:00] [PASSED] Unknown
[06:25:00] [PASSED] VGA
[06:25:00] [PASSED] DVI-I
[06:25:00] [PASSED] DVI-D
[06:25:00] [PASSED] DVI-A
[06:25:00] [PASSED] Composite
[06:25:00] [PASSED] SVIDEO
[06:25:00] [PASSED] LVDS
[06:25:00] [PASSED] Component
[06:25:00] [PASSED] DIN
[06:25:00] [PASSED] DP
[06:25:00] [PASSED] HDMI-A
[06:25:00] [PASSED] HDMI-B
[06:25:00] [PASSED] TV
[06:25:00] [PASSED] eDP
[06:25:00] [PASSED] Virtual
[06:25:00] [PASSED] DSI
[06:25:00] [PASSED] DPI
[06:25:00] [PASSED] Writeback
[06:25:00] [PASSED] SPI
[06:25:00] [PASSED] USB
[06:25:00] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[06:25:00] =========== [PASSED] drm_connector_dynamic_init ============
[06:25:00] ==== drm_connector_dynamic_register_early (4 subtests) =====
[06:25:00] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[06:25:00] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[06:25:00] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[06:25:00] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[06:25:00] ====== [PASSED] drm_connector_dynamic_register_early =======
[06:25:00] ======= drm_connector_dynamic_register (7 subtests) ========
[06:25:00] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[06:25:00] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[06:25:00] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[06:25:00] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[06:25:00] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[06:25:00] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[06:25:00] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[06:25:00] ========= [PASSED] drm_connector_dynamic_register ==========
[06:25:00] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[06:25:00] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[06:25:00] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[06:25:00] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[06:25:00] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[06:25:00] ========== drm_test_get_tv_mode_from_name_valid  ===========
[06:25:00] [PASSED] NTSC
[06:25:00] [PASSED] NTSC-443
[06:25:00] [PASSED] NTSC-J
[06:25:00] [PASSED] PAL
[06:25:00] [PASSED] PAL-M
[06:25:00] [PASSED] PAL-N
[06:25:00] [PASSED] SECAM
[06:25:00] [PASSED] Mono
[06:25:00] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[06:25:00] [PASSED] drm_test_get_tv_mode_from_name_truncated
[06:25:00] ============ [PASSED] drm_get_tv_mode_from_name ============
[06:25:00] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[06:25:00] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[06:25:00] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[06:25:00] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[06:25:00] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[06:25:00] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[06:25:00] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[06:25:00] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[06:25:00] [PASSED] VIC 96
[06:25:00] [PASSED] VIC 97
[06:25:00] [PASSED] VIC 101
[06:25:00] [PASSED] VIC 102
[06:25:00] [PASSED] VIC 106
[06:25:00] [PASSED] VIC 107
[06:25:00] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[06:25:00] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[06:25:00] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[06:25:00] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[06:25:00] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[06:25:00] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[06:25:00] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[06:25:00] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[06:25:00] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[06:25:00] [PASSED] Automatic
[06:25:00] [PASSED] Full
[06:25:00] [PASSED] Limited 16:235
[06:25:00] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[06:25:00] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[06:25:00] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[06:25:00] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[06:25:00] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[06:25:00] [PASSED] RGB
[06:25:00] [PASSED] YUV 4:2:0
[06:25:00] [PASSED] YUV 4:2:2
[06:25:00] [PASSED] YUV 4:4:4
[06:25:00] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[06:25:00] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[06:25:00] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[06:25:00] ============= drm_damage_helper (21 subtests) ==============
[06:25:00] [PASSED] drm_test_damage_iter_no_damage
[06:25:00] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[06:25:00] [PASSED] drm_test_damage_iter_no_damage_src_moved
[06:25:00] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[06:25:00] [PASSED] drm_test_damage_iter_no_damage_not_visible
[06:25:00] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[06:25:00] [PASSED] drm_test_damage_iter_no_damage_no_fb
[06:25:00] [PASSED] drm_test_damage_iter_simple_damage
[06:25:00] [PASSED] drm_test_damage_iter_single_damage
[06:25:00] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[06:25:00] [PASSED] drm_test_damage_iter_single_damage_outside_src
[06:25:00] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[06:25:00] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[06:25:00] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[06:25:00] [PASSED] drm_test_damage_iter_single_damage_src_moved
[06:25:00] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[06:25:00] [PASSED] drm_test_damage_iter_damage
[06:25:00] [PASSED] drm_test_damage_iter_damage_one_intersect
[06:25:00] [PASSED] drm_test_damage_iter_damage_one_outside
[06:25:00] [PASSED] drm_test_damage_iter_damage_src_moved
[06:25:00] [PASSED] drm_test_damage_iter_damage_not_visible
[06:25:00] ================ [PASSED] drm_damage_helper ================
[06:25:00] ============== drm_dp_mst_helper (3 subtests) ==============
[06:25:00] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[06:25:00] [PASSED] Clock 154000 BPP 30 DSC disabled
[06:25:00] [PASSED] Clock 234000 BPP 30 DSC disabled
[06:25:00] [PASSED] Clock 297000 BPP 24 DSC disabled
[06:25:00] [PASSED] Clock 332880 BPP 24 DSC enabled
[06:25:00] [PASSED] Clock 324540 BPP 24 DSC enabled
[06:25:00] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[06:25:00] ============== drm_test_dp_mst_calc_pbn_div  ===============
[06:25:00] [PASSED] Link rate 2000000 lane count 4
[06:25:00] [PASSED] Link rate 2000000 lane count 2
[06:25:00] [PASSED] Link rate 2000000 lane count 1
[06:25:00] [PASSED] Link rate 1350000 lane count 4
[06:25:00] [PASSED] Link rate 1350000 lane count 2
[06:25:00] [PASSED] Link rate 1350000 lane count 1
[06:25:00] [PASSED] Link rate 1000000 lane count 4
[06:25:00] [PASSED] Link rate 1000000 lane count 2
[06:25:00] [PASSED] Link rate 1000000 lane count 1
[06:25:00] [PASSED] Link rate 810000 lane count 4
[06:25:00] [PASSED] Link rate 810000 lane count 2
[06:25:00] [PASSED] Link rate 810000 lane count 1
[06:25:00] [PASSED] Link rate 540000 lane count 4
[06:25:00] [PASSED] Link rate 540000 lane count 2
[06:25:00] [PASSED] Link rate 540000 lane count 1
[06:25:00] [PASSED] Link rate 270000 lane count 4
[06:25:00] [PASSED] Link rate 270000 lane count 2
[06:25:00] [PASSED] Link rate 270000 lane count 1
[06:25:00] [PASSED] Link rate 162000 lane count 4
[06:25:00] [PASSED] Link rate 162000 lane count 2
[06:25:00] [PASSED] Link rate 162000 lane count 1
[06:25:00] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[06:25:00] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[06:25:00] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[06:25:00] [PASSED] DP_POWER_UP_PHY with port number
[06:25:00] [PASSED] DP_POWER_DOWN_PHY with port number
[06:25:00] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[06:25:00] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[06:25:00] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[06:25:00] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[06:25:00] [PASSED] DP_QUERY_PAYLOAD with port number
[06:25:00] [PASSED] DP_QUERY_PAYLOAD with VCPI
[06:25:00] [PASSED] DP_REMOTE_DPCD_READ with port number
[06:25:00] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[06:25:00] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[06:25:00] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[06:25:00] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[06:25:00] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[06:25:00] [PASSED] DP_REMOTE_I2C_READ with port number
[06:25:00] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[06:25:00] [PASSED] DP_REMOTE_I2C_READ with transactions array
[06:25:00] [PASSED] DP_REMOTE_I2C_WRITE with port number
[06:25:00] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[06:25:00] [PASSED] DP_REMOTE_I2C_WRITE with data array
[06:25:00] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[06:25:00] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[06:25:00] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[06:25:00] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[06:25:00] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[06:25:00] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[06:25:00] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[06:25:00] ================ [PASSED] drm_dp_mst_helper ================
[06:25:00] ================== drm_exec (7 subtests) ===================
[06:25:00] [PASSED] sanitycheck
[06:25:00] [PASSED] test_lock
[06:25:00] [PASSED] test_lock_unlock
[06:25:00] [PASSED] test_duplicates
[06:25:00] [PASSED] test_prepare
[06:25:00] [PASSED] test_prepare_array
[06:25:00] [PASSED] test_multiple_loops
[06:25:00] ==================== [PASSED] drm_exec =====================
[06:25:00] =========== drm_format_helper_test (18 subtests) ===========
[06:25:00] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[06:25:00] [PASSED] single_pixel_source_buffer
[06:25:00] [PASSED] single_pixel_clip_rectangle
[06:25:00] [PASSED] well_known_colors
[06:25:00] [PASSED] destination_pitch
[06:25:00] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[06:25:00] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[06:25:00] [PASSED] single_pixel_source_buffer
[06:25:00] [PASSED] single_pixel_clip_rectangle
[06:25:00] [PASSED] well_known_colors
[06:25:00] [PASSED] destination_pitch
[06:25:00] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[06:25:00] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[06:25:00] [PASSED] single_pixel_source_buffer
[06:25:00] [PASSED] single_pixel_clip_rectangle
[06:25:00] [PASSED] well_known_colors
[06:25:00] [PASSED] destination_pitch
[06:25:00] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[06:25:00] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[06:25:00] [PASSED] single_pixel_source_buffer
[06:25:00] [PASSED] single_pixel_clip_rectangle
[06:25:00] [PASSED] well_known_colors
[06:25:00] [PASSED] destination_pitch
[06:25:00] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[06:25:00] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[06:25:00] [PASSED] single_pixel_source_buffer
[06:25:00] [PASSED] single_pixel_clip_rectangle
[06:25:00] [PASSED] well_known_colors
[06:25:00] [PASSED] destination_pitch
[06:25:00] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[06:25:00] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[06:25:00] [PASSED] single_pixel_source_buffer
[06:25:00] [PASSED] single_pixel_clip_rectangle
[06:25:00] [PASSED] well_known_colors
[06:25:00] [PASSED] destination_pitch
[06:25:00] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[06:25:00] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[06:25:00] [PASSED] single_pixel_source_buffer
[06:25:00] [PASSED] single_pixel_clip_rectangle
[06:25:00] [PASSED] well_known_colors
[06:25:00] [PASSED] destination_pitch
[06:25:00] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[06:25:00] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[06:25:00] [PASSED] single_pixel_source_buffer
[06:25:00] [PASSED] single_pixel_clip_rectangle
[06:25:00] [PASSED] well_known_colors
[06:25:00] [PASSED] destination_pitch
[06:25:00] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[06:25:00] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[06:25:00] [PASSED] single_pixel_source_buffer
[06:25:00] [PASSED] single_pixel_clip_rectangle
[06:25:00] [PASSED] well_known_colors
[06:25:00] [PASSED] destination_pitch
[06:25:00] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[06:25:00] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[06:25:00] [PASSED] single_pixel_source_buffer
[06:25:00] [PASSED] single_pixel_clip_rectangle
[06:25:00] [PASSED] well_known_colors
[06:25:00] [PASSED] destination_pitch
[06:25:00] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[06:25:00] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[06:25:00] [PASSED] single_pixel_source_buffer
[06:25:00] [PASSED] single_pixel_clip_rectangle
[06:25:00] [PASSED] well_known_colors
[06:25:00] [PASSED] destination_pitch
[06:25:00] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[06:25:00] ============== drm_test_fb_xrgb8888_to_mono  ===============
[06:25:00] [PASSED] single_pixel_source_buffer
[06:25:00] [PASSED] single_pixel_clip_rectangle
[06:25:00] [PASSED] well_known_colors
[06:25:00] [PASSED] destination_pitch
[06:25:00] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[06:25:00] ==================== drm_test_fb_swab  =====================
[06:25:00] [PASSED] single_pixel_source_buffer
[06:25:00] [PASSED] single_pixel_clip_rectangle
[06:25:00] [PASSED] well_known_colors
[06:25:00] [PASSED] destination_pitch
[06:25:00] ================ [PASSED] drm_test_fb_swab =================
[06:25:00] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[06:25:00] [PASSED] single_pixel_source_buffer
[06:25:00] [PASSED] single_pixel_clip_rectangle
[06:25:00] [PASSED] well_known_colors
[06:25:00] [PASSED] destination_pitch
[06:25:00] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[06:25:00] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[06:25:00] [PASSED] single_pixel_source_buffer
[06:25:00] [PASSED] single_pixel_clip_rectangle
[06:25:00] [PASSED] well_known_colors
[06:25:00] [PASSED] destination_pitch
[06:25:00] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[06:25:00] ================= drm_test_fb_clip_offset  =================
[06:25:00] [PASSED] pass through
[06:25:00] [PASSED] horizontal offset
[06:25:00] [PASSED] vertical offset
[06:25:00] [PASSED] horizontal and vertical offset
[06:25:00] [PASSED] horizontal offset (custom pitch)
[06:25:00] [PASSED] vertical offset (custom pitch)
[06:25:00] [PASSED] horizontal and vertical offset (custom pitch)
[06:25:00] ============= [PASSED] drm_test_fb_clip_offset =============
[06:25:00] ============== drm_test_fb_build_fourcc_list  ==============
[06:25:00] [PASSED] no native formats
[06:25:00] [PASSED] XRGB8888 as native format
[06:25:00] [PASSED] remove duplicates
[06:25:00] [PASSED] convert alpha formats
[06:25:00] [PASSED] random formats
[06:25:00] ========== [PASSED] drm_test_fb_build_fourcc_list ==========
[06:25:00] =================== drm_test_fb_memcpy  ====================
[06:25:00] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[06:25:00] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[06:25:00] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[06:25:00] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[06:25:00] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[06:25:00] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[06:25:00] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[06:25:00] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[06:25:00] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[06:25:00] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[06:25:00] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[06:25:00] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[06:25:00] =============== [PASSED] drm_test_fb_memcpy ================
[06:25:00] ============= [PASSED] drm_format_helper_test ==============
[06:25:00] ================= drm_format (18 subtests) =================
[06:25:00] [PASSED] drm_test_format_block_width_invalid
[06:25:00] [PASSED] drm_test_format_block_width_one_plane
[06:25:00] [PASSED] drm_test_format_block_width_two_plane
[06:25:00] [PASSED] drm_test_format_block_width_three_plane
[06:25:00] [PASSED] drm_test_format_block_width_tiled
[06:25:00] [PASSED] drm_test_format_block_height_invalid
[06:25:00] [PASSED] drm_test_format_block_height_one_plane
[06:25:00] [PASSED] drm_test_format_block_height_two_plane
[06:25:00] [PASSED] drm_test_format_block_height_three_plane
[06:25:00] [PASSED] drm_test_format_block_height_tiled
[06:25:00] [PASSED] drm_test_format_min_pitch_invalid
[06:25:00] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[06:25:00] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[06:25:00] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[06:25:00] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[06:25:00] [PASSED] drm_test_format_min_pitch_two_plane
[06:25:00] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[06:25:00] [PASSED] drm_test_format_min_pitch_tiled
[06:25:00] =================== [PASSED] drm_format ====================
[06:25:00] ============== drm_framebuffer (10 subtests) ===============
[06:25:00] ========== drm_test_framebuffer_check_src_coords  ==========
[06:25:00] [PASSED] Success: source fits into fb
[06:25:00] [PASSED] Fail: overflowing fb with x-axis coordinate
[06:25:00] [PASSED] Fail: overflowing fb with y-axis coordinate
[06:25:00] [PASSED] Fail: overflowing fb with source width
[06:25:00] [PASSED] Fail: overflowing fb with source height
[06:25:00] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[06:25:00] [PASSED] drm_test_framebuffer_cleanup
[06:25:00] =============== drm_test_framebuffer_create  ===============
[06:25:00] [PASSED] ABGR8888 normal sizes
[06:25:00] [PASSED] ABGR8888 max sizes
[06:25:00] [PASSED] ABGR8888 pitch greater than min required
[06:25:00] [PASSED] ABGR8888 pitch less than min required
[06:25:00] [PASSED] ABGR8888 Invalid width
[06:25:00] [PASSED] ABGR8888 Invalid buffer handle
[06:25:00] [PASSED] No pixel format
[06:25:00] [PASSED] ABGR8888 Width 0
[06:25:00] [PASSED] ABGR8888 Height 0
[06:25:00] [PASSED] ABGR8888 Out of bound height * pitch combination
[06:25:00] [PASSED] ABGR8888 Large buffer offset
[06:25:00] [PASSED] ABGR8888 Buffer offset for inexistent plane
[06:25:00] [PASSED] ABGR8888 Invalid flag
[06:25:00] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[06:25:00] [PASSED] ABGR8888 Valid buffer modifier
[06:25:00] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[06:25:00] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[06:25:00] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[06:25:00] [PASSED] NV12 Normal sizes
[06:25:00] [PASSED] NV12 Max sizes
[06:25:00] [PASSED] NV12 Invalid pitch
[06:25:00] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[06:25:00] [PASSED] NV12 different  modifier per-plane
[06:25:00] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[06:25:00] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[06:25:00] [PASSED] NV12 Modifier for inexistent plane
[06:25:00] [PASSED] NV12 Handle for inexistent plane
[06:25:00] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[06:25:00] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[06:25:00] [PASSED] YVU420 Normal sizes
[06:25:00] [PASSED] YVU420 Max sizes
[06:25:00] [PASSED] YVU420 Invalid pitch
[06:25:00] [PASSED] YVU420 Different pitches
[06:25:00] [PASSED] YVU420 Different buffer offsets/pitches
[06:25:00] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[06:25:00] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[06:25:00] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[06:25:00] [PASSED] YVU420 Valid modifier
[06:25:00] [PASSED] YVU420 Different modifiers per plane
[06:25:00] [PASSED] YVU420 Modifier for inexistent plane
[06:25:00] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[06:25:00] [PASSED] X0L2 Normal sizes
[06:25:00] [PASSED] X0L2 Max sizes
[06:25:00] [PASSED] X0L2 Invalid pitch
[06:25:00] [PASSED] X0L2 Pitch greater than minimum required
[06:25:00] [PASSED] X0L2 Handle for inexistent plane
[06:25:00] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[06:25:00] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[06:25:00] [PASSED] X0L2 Valid modifier
[06:25:00] [PASSED] X0L2 Modifier for inexistent plane
[06:25:00] =========== [PASSED] drm_test_framebuffer_create ===========
[06:25:00] [PASSED] drm_test_framebuffer_free
[06:25:00] [PASSED] drm_test_framebuffer_init
[06:25:00] [PASSED] drm_test_framebuffer_init_bad_format
[06:25:00] [PASSED] drm_test_framebuffer_init_dev_mismatch
[06:25:00] [PASSED] drm_test_framebuffer_lookup
[06:25:00] [PASSED] drm_test_framebuffer_lookup_inexistent
[06:25:00] [PASSED] drm_test_framebuffer_modifiers_not_supported
[06:25:00] ================= [PASSED] drm_framebuffer =================
[06:25:00] ================ drm_gem_shmem (8 subtests) ================
[06:25:00] [PASSED] drm_gem_shmem_test_obj_create
[06:25:00] [PASSED] drm_gem_shmem_test_obj_create_private
[06:25:00] [PASSED] drm_gem_shmem_test_pin_pages
[06:25:00] [PASSED] drm_gem_shmem_test_vmap
[06:25:00] [PASSED] drm_gem_shmem_test_get_pages_sgt
[06:25:00] [PASSED] drm_gem_shmem_test_get_sg_table
[06:25:00] [PASSED] drm_gem_shmem_test_madvise
[06:25:00] [PASSED] drm_gem_shmem_test_purge
[06:25:00] ================== [PASSED] drm_gem_shmem ==================
[06:25:00] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[06:25:00] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[06:25:00] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[06:25:00] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[06:25:00] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[06:25:00] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[06:25:00] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[06:25:00] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[06:25:00] [PASSED] Automatic
[06:25:00] [PASSED] Full
[06:25:00] [PASSED] Limited 16:235
[06:25:00] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[06:25:00] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[06:25:00] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[06:25:00] [PASSED] drm_test_check_disable_connector
[06:25:00] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[06:25:00] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[06:25:00] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[06:25:00] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[06:25:00] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[06:25:00] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[06:25:00] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[06:25:00] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[06:25:00] [PASSED] drm_test_check_output_bpc_dvi
[06:25:00] [PASSED] drm_test_check_output_bpc_format_vic_1
[06:25:00] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[06:25:00] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[06:25:00] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[06:25:00] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[06:25:00] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[06:25:00] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[06:25:00] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[06:25:00] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[06:25:00] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[06:25:00] [PASSED] drm_test_check_broadcast_rgb_value
[06:25:00] [PASSED] drm_test_check_bpc_8_value
[06:25:00] [PASSED] drm_test_check_bpc_10_value
[06:25:00] [PASSED] drm_test_check_bpc_12_value
[06:25:00] [PASSED] drm_test_check_format_value
[06:25:00] [PASSED] drm_test_check_tmds_char_value
[06:25:00] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[06:25:00] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[06:25:00] [PASSED] drm_test_check_mode_valid
[06:25:00] [PASSED] drm_test_check_mode_valid_reject
[06:25:00] [PASSED] drm_test_check_mode_valid_reject_rate
[06:25:00] [PASSED] drm_test_check_mode_valid_reject_max_clock
[06:25:00] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[06:25:00] ================= drm_managed (2 subtests) =================
[06:25:00] [PASSED] drm_test_managed_release_action
[06:25:00] [PASSED] drm_test_managed_run_action
[06:25:00] =================== [PASSED] drm_managed ===================
[06:25:00] =================== drm_mm (6 subtests) ====================
[06:25:00] [PASSED] drm_test_mm_init
[06:25:00] [PASSED] drm_test_mm_debug
[06:25:00] [PASSED] drm_test_mm_align32
[06:25:00] [PASSED] drm_test_mm_align64
[06:25:00] [PASSED] drm_test_mm_lowest
[06:25:00] [PASSED] drm_test_mm_highest
[06:25:00] ===================== [PASSED] drm_mm ======================
[06:25:00] ============= drm_modes_analog_tv (5 subtests) =============
[06:25:00] [PASSED] drm_test_modes_analog_tv_mono_576i
[06:25:00] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[06:25:00] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[06:25:00] [PASSED] drm_test_modes_analog_tv_pal_576i
[06:25:00] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[06:25:00] =============== [PASSED] drm_modes_analog_tv ===============
[06:25:00] ============== drm_plane_helper (2 subtests) ===============
[06:25:00] =============== drm_test_check_plane_state  ================
[06:25:00] [PASSED] clipping_simple
[06:25:00] [PASSED] clipping_rotate_reflect
[06:25:00] [PASSED] positioning_simple
[06:25:00] [PASSED] upscaling
[06:25:00] [PASSED] downscaling
[06:25:00] [PASSED] rounding1
[06:25:00] [PASSED] rounding2
[06:25:00] [PASSED] rounding3
[06:25:00] [PASSED] rounding4
[06:25:00] =========== [PASSED] drm_test_check_plane_state ============
[06:25:00] =========== drm_test_check_invalid_plane_state  ============
[06:25:00] [PASSED] positioning_invalid
[06:25:00] [PASSED] upscaling_invalid
[06:25:00] [PASSED] downscaling_invalid
[06:25:00] ======= [PASSED] drm_test_check_invalid_plane_state ========
[06:25:00] ================ [PASSED] drm_plane_helper =================
[06:25:00] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[06:25:00] ====== drm_test_connector_helper_tv_get_modes_check  =======
[06:25:00] [PASSED] None
[06:25:00] [PASSED] PAL
[06:25:00] [PASSED] NTSC
[06:25:00] [PASSED] Both, NTSC Default
[06:25:00] [PASSED] Both, PAL Default
[06:25:00] [PASSED] Both, NTSC Default, with PAL on command-line
[06:25:00] [PASSED] Both, PAL Default, with NTSC on command-line
[06:25:00] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[06:25:00] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[06:25:00] ================== drm_rect (9 subtests) ===================
[06:25:00] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[06:25:00] [PASSED] drm_test_rect_clip_scaled_not_clipped
[06:25:00] [PASSED] drm_test_rect_clip_scaled_clipped
[06:25:00] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[06:25:00] ================= drm_test_rect_intersect  =================
[06:25:00] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[06:25:00] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[06:25:00] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[06:25:00] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[06:25:00] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[06:25:00] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[06:25:00] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[06:25:00] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[06:25:00] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[06:25:00] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[06:25:00] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[06:25:00] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[06:25:00] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[06:25:00] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[06:25:00] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[06:25:00] ============= [PASSED] drm_test_rect_intersect =============
[06:25:00] ================ drm_test_rect_calc_hscale  ================
[06:25:00] [PASSED] normal use
[06:25:00] [PASSED] out of max range
[06:25:00] [PASSED] out of min range
[06:25:00] [PASSED] zero dst
[06:25:00] [PASSED] negative src
[06:25:00] [PASSED] negative dst
[06:25:00] ============ [PASSED] drm_test_rect_calc_hscale ============
[06:25:00] ================ drm_test_rect_calc_vscale  ================
[06:25:00] [PASSED] normal use
[06:25:00] [PASSED] out of max range
[06:25:00] [PASSED] out of min range
[06:25:00] [PASSED] zero dst
[06:25:00] [PASSED] negative src
[06:25:00] [PASSED] negative dst
stty: 'standard input': Inappropriate ioctl for device
[06:25:00] ============ [PASSED] drm_test_rect_calc_vscale ============
[06:25:00] ================== drm_test_rect_rotate  ===================
[06:25:00] [PASSED] reflect-x
[06:25:00] [PASSED] reflect-y
[06:25:00] [PASSED] rotate-0
[06:25:00] [PASSED] rotate-90
[06:25:00] [PASSED] rotate-180
[06:25:00] [PASSED] rotate-270
[06:25:00] ============== [PASSED] drm_test_rect_rotate ===============
[06:25:00] ================ drm_test_rect_rotate_inv  =================
[06:25:00] [PASSED] reflect-x
[06:25:00] [PASSED] reflect-y
[06:25:00] [PASSED] rotate-0
[06:25:00] [PASSED] rotate-90
[06:25:00] [PASSED] rotate-180
[06:25:00] [PASSED] rotate-270
[06:25:00] ============ [PASSED] drm_test_rect_rotate_inv =============
[06:25:00] ==================== [PASSED] drm_rect =====================
[06:25:00] ============================================================
[06:25:00] Testing complete. Ran 616 tests: passed: 616
[06:25:00] Elapsed time: 23.405s total, 1.689s configuring, 21.549s building, 0.144s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[06:25:00] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[06:25:02] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[06:25:10] Starting KUnit Kernel (1/1)...
[06:25:10] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[06:25:10] ================= ttm_device (5 subtests) ==================
[06:25:10] [PASSED] ttm_device_init_basic
[06:25:10] [PASSED] ttm_device_init_multiple
[06:25:10] [PASSED] ttm_device_fini_basic
[06:25:10] [PASSED] ttm_device_init_no_vma_man
[06:25:10] ================== ttm_device_init_pools  ==================
[06:25:10] [PASSED] No DMA allocations, no DMA32 required
[06:25:10] [PASSED] DMA allocations, DMA32 required
[06:25:10] [PASSED] No DMA allocations, DMA32 required
[06:25:10] [PASSED] DMA allocations, no DMA32 required
[06:25:10] ============== [PASSED] ttm_device_init_pools ==============
[06:25:10] =================== [PASSED] ttm_device ====================
[06:25:10] ================== ttm_pool (8 subtests) ===================
[06:25:10] ================== ttm_pool_alloc_basic  ===================
[06:25:10] [PASSED] One page
[06:25:10] [PASSED] More than one page
[06:25:10] [PASSED] Above the allocation limit
[06:25:10] [PASSED] One page, with coherent DMA mappings enabled
[06:25:10] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[06:25:10] ============== [PASSED] ttm_pool_alloc_basic ===============
[06:25:10] ============== ttm_pool_alloc_basic_dma_addr  ==============
[06:25:10] [PASSED] One page
[06:25:10] [PASSED] More than one page
[06:25:10] [PASSED] Above the allocation limit
[06:25:10] [PASSED] One page, with coherent DMA mappings enabled
[06:25:10] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[06:25:10] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[06:25:10] [PASSED] ttm_pool_alloc_order_caching_match
[06:25:10] [PASSED] ttm_pool_alloc_caching_mismatch
[06:25:10] [PASSED] ttm_pool_alloc_order_mismatch
[06:25:10] [PASSED] ttm_pool_free_dma_alloc
[06:25:10] [PASSED] ttm_pool_free_no_dma_alloc
[06:25:10] [PASSED] ttm_pool_fini_basic
[06:25:10] ==================== [PASSED] ttm_pool =====================
[06:25:10] ================ ttm_resource (8 subtests) =================
[06:25:10] ================= ttm_resource_init_basic  =================
[06:25:10] [PASSED] Init resource in TTM_PL_SYSTEM
[06:25:10] [PASSED] Init resource in TTM_PL_VRAM
[06:25:10] [PASSED] Init resource in a private placement
[06:25:10] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[06:25:10] ============= [PASSED] ttm_resource_init_basic =============
[06:25:10] [PASSED] ttm_resource_init_pinned
[06:25:10] [PASSED] ttm_resource_fini_basic
[06:25:10] [PASSED] ttm_resource_manager_init_basic
[06:25:10] [PASSED] ttm_resource_manager_usage_basic
[06:25:10] [PASSED] ttm_resource_manager_set_used_basic
[06:25:10] [PASSED] ttm_sys_man_alloc_basic
[06:25:10] [PASSED] ttm_sys_man_free_basic
[06:25:10] ================== [PASSED] ttm_resource ===================
[06:25:10] =================== ttm_tt (15 subtests) ===================
[06:25:10] ==================== ttm_tt_init_basic  ====================
[06:25:10] [PASSED] Page-aligned size
[06:25:10] [PASSED] Extra pages requested
[06:25:10] ================ [PASSED] ttm_tt_init_basic ================
[06:25:10] [PASSED] ttm_tt_init_misaligned
[06:25:10] [PASSED] ttm_tt_fini_basic
[06:25:10] [PASSED] ttm_tt_fini_sg
[06:25:10] [PASSED] ttm_tt_fini_shmem
[06:25:10] [PASSED] ttm_tt_create_basic
[06:25:10] [PASSED] ttm_tt_create_invalid_bo_type
[06:25:10] [PASSED] ttm_tt_create_ttm_exists
[06:25:10] [PASSED] ttm_tt_create_failed
[06:25:10] [PASSED] ttm_tt_destroy_basic
[06:25:10] [PASSED] ttm_tt_populate_null_ttm
[06:25:10] [PASSED] ttm_tt_populate_populated_ttm
[06:25:10] [PASSED] ttm_tt_unpopulate_basic
[06:25:10] [PASSED] ttm_tt_unpopulate_empty_ttm
[06:25:10] [PASSED] ttm_tt_swapin_basic
[06:25:10] ===================== [PASSED] ttm_tt ======================
[06:25:10] =================== ttm_bo (14 subtests) ===================
[06:25:10] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[06:25:10] [PASSED] Cannot be interrupted and sleeps
[06:25:10] [PASSED] Cannot be interrupted, locks straight away
[06:25:10] [PASSED] Can be interrupted, sleeps
[06:25:10] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[06:25:10] [PASSED] ttm_bo_reserve_locked_no_sleep
[06:25:10] [PASSED] ttm_bo_reserve_no_wait_ticket
[06:25:10] [PASSED] ttm_bo_reserve_double_resv
[06:25:10] [PASSED] ttm_bo_reserve_interrupted
[06:25:10] [PASSED] ttm_bo_reserve_deadlock
[06:25:10] [PASSED] ttm_bo_unreserve_basic
[06:25:10] [PASSED] ttm_bo_unreserve_pinned
[06:25:10] [PASSED] ttm_bo_unreserve_bulk
[06:25:10] [PASSED] ttm_bo_put_basic
[06:25:10] [PASSED] ttm_bo_put_shared_resv
[06:25:10] [PASSED] ttm_bo_pin_basic
[06:25:10] [PASSED] ttm_bo_pin_unpin_resource
[06:25:10] [PASSED] ttm_bo_multiple_pin_one_unpin
[06:25:10] ===================== [PASSED] ttm_bo ======================
[06:25:10] ============== ttm_bo_validate (22 subtests) ===============
[06:25:10] ============== ttm_bo_init_reserved_sys_man  ===============
[06:25:10] [PASSED] Buffer object for userspace
[06:25:10] [PASSED] Kernel buffer object
[06:25:10] [PASSED] Shared buffer object
[06:25:10] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[06:25:10] ============== ttm_bo_init_reserved_mock_man  ==============
[06:25:10] [PASSED] Buffer object for userspace
[06:25:10] [PASSED] Kernel buffer object
[06:25:10] [PASSED] Shared buffer object
[06:25:10] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[06:25:10] [PASSED] ttm_bo_init_reserved_resv
[06:25:10] ================== ttm_bo_validate_basic  ==================
[06:25:10] [PASSED] Buffer object for userspace
[06:25:10] [PASSED] Kernel buffer object
[06:25:10] [PASSED] Shared buffer object
[06:25:10] ============== [PASSED] ttm_bo_validate_basic ==============
[06:25:10] [PASSED] ttm_bo_validate_invalid_placement
[06:25:10] ============= ttm_bo_validate_same_placement  ==============
[06:25:10] [PASSED] System manager
[06:25:10] [PASSED] VRAM manager
[06:25:10] ========= [PASSED] ttm_bo_validate_same_placement ==========
[06:25:10] [PASSED] ttm_bo_validate_failed_alloc
[06:25:10] [PASSED] ttm_bo_validate_pinned
[06:25:10] [PASSED] ttm_bo_validate_busy_placement
[06:25:10] ================ ttm_bo_validate_multihop  =================
[06:25:10] [PASSED] Buffer object for userspace
[06:25:10] [PASSED] Kernel buffer object
[06:25:10] [PASSED] Shared buffer object
[06:25:10] ============ [PASSED] ttm_bo_validate_multihop =============
[06:25:10] ========== ttm_bo_validate_no_placement_signaled  ==========
[06:25:10] [PASSED] Buffer object in system domain, no page vector
[06:25:10] [PASSED] Buffer object in system domain with an existing page vector
[06:25:10] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[06:25:10] ======== ttm_bo_validate_no_placement_not_signaled  ========
[06:25:10] [PASSED] Buffer object for userspace
[06:25:10] [PASSED] Kernel buffer object
[06:25:10] [PASSED] Shared buffer object
[06:25:10] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[06:25:10] [PASSED] ttm_bo_validate_move_fence_signaled
[06:25:10] ========= ttm_bo_validate_move_fence_not_signaled  =========
[06:25:10] [PASSED] Waits for GPU
[06:25:10] [PASSED] Tries to lock straight away
[06:25:10] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[06:25:10] [PASSED] ttm_bo_validate_swapout
[06:25:10] [PASSED] ttm_bo_validate_happy_evict
[06:25:10] [PASSED] ttm_bo_validate_all_pinned_evict
[06:25:10] [PASSED] ttm_bo_validate_allowed_only_evict
[06:25:10] [PASSED] ttm_bo_validate_deleted_evict
[06:25:10] [PASSED] ttm_bo_validate_busy_domain_evict
[06:25:10] [PASSED] ttm_bo_validate_evict_gutting
[06:25:10] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[06:25:10] ================= [PASSED] ttm_bo_validate =================
[06:25:10] ============================================================
[06:25:10] Testing complete. Ran 102 tests: passed: 102
[06:25:10] Elapsed time: 10.130s total, 1.662s configuring, 7.800s building, 0.566s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for drm/xe: Update Wa_22019338487

[Patchwork]

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== Series Details ==

Series: drm/xe: Update Wa_22019338487
URL   : https://patchwork.freedesktop.org/series/150300/
State : success

== Summary ==

CI Bug Log - changes from xe-3254-6e474d767e318b98cc45d4b90095290879085741_BAT -> xe-pw-150300v1_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (8 -> 8)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * Linux: xe-3254-6e474d767e318b98cc45d4b90095290879085741 -> xe-pw-150300v1

  IGT_8411: d5b5d2bb4f8795a98ea58376a128b74f654b7ec1 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-3254-6e474d767e318b98cc45d4b90095290879085741: 6e474d767e318b98cc45d4b90095290879085741
  xe-pw-150300v1: 150300v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/index.html

[-- Attachment #2: Type: text/html, Size: 1489 bytes --]

✗ Xe.CI.Full: failure for drm/xe: Update Wa_22019338487

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 58389 bytes --]

== Series Details ==

Series: drm/xe: Update Wa_22019338487
URL   : https://patchwork.freedesktop.org/series/150300/
State : failure

== Summary ==

CI Bug Log - changes from xe-3254-6e474d767e318b98cc45d4b90095290879085741_FULL -> xe-pw-150300v1_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-150300v1_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-150300v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-150300v1_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_flip@flip-vs-absolute-wf_vblank@d-hdmi-a1:
    - shard-adlp:         [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-adlp-2/igt@kms_flip@flip-vs-absolute-wf_vblank@d-hdmi-a1.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-3/igt@kms_flip@flip-vs-absolute-wf_vblank@d-hdmi-a1.html

  * igt@xe_pm@s3-d3hot-basic-exec:
    - shard-adlp:         NOTRUN -> [WARN][3]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-1/igt@xe_pm@s3-d3hot-basic-exec.html

  * igt@xe_wedged@wedged-at-any-timeout:
    - shard-bmg:          [PASS][4] -> [DMESG-WARN][5]
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-bmg-7/igt@xe_wedged@wedged-at-any-timeout.html
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-3/igt@xe_wedged@wedged-at-any-timeout.html

  
Known issues
------------

  Here are the changes found in xe-pw-150300v1_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_async_flips@invalid-async-flip-atomic@pipe-b-hdmi-a-1:
    - shard-adlp:         [PASS][6] -> [DMESG-WARN][7] ([Intel XE#4543]) +1 other test dmesg-warn
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-adlp-9/igt@kms_async_flips@invalid-async-flip-atomic@pipe-b-hdmi-a-1.html
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-1/igt@kms_async_flips@invalid-async-flip-atomic@pipe-b-hdmi-a-1.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-180:
    - shard-adlp:         NOTRUN -> [SKIP][8] ([Intel XE#1124])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-1/igt@kms_big_fb@4-tiled-32bpp-rotate-180.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-270:
    - shard-bmg:          NOTRUN -> [SKIP][9] ([Intel XE#2327])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-8/igt@kms_big_fb@4-tiled-64bpp-rotate-270.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][10] ([Intel XE#316])
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-dg2-434/igt@kms_big_fb@4-tiled-64bpp-rotate-270.html

  * igt@kms_big_fb@linear-32bpp-rotate-90:
    - shard-adlp:         NOTRUN -> [SKIP][11] ([Intel XE#316]) +1 other test skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-1/igt@kms_big_fb@linear-32bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
    - shard-adlp:         [PASS][12] -> [DMESG-FAIL][13] ([Intel XE#4543])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-adlp-2/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-3/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html

  * igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
    - shard-bmg:          NOTRUN -> [SKIP][14] ([Intel XE#607])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-4/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
    - shard-dg2-set2:     NOTRUN -> [SKIP][15] ([Intel XE#1124]) +1 other test skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-dg2-434/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
    - shard-bmg:          NOTRUN -> [SKIP][16] ([Intel XE#1124]) +2 other tests skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-4/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html

  * igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p:
    - shard-bmg:          [PASS][17] -> [SKIP][18] ([Intel XE#2314] / [Intel XE#2894])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-bmg-2/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-5/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html

  * igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p:
    - shard-bmg:          NOTRUN -> [SKIP][19] ([Intel XE#2314] / [Intel XE#2894])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-8/igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][20] ([Intel XE#2191])
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-dg2-434/igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p.html

  * igt@kms_bw@linear-tiling-3-displays-2160x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][21] ([Intel XE#367])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-4/igt@kms_bw@linear-tiling-3-displays-2160x1440p.html

  * igt@kms_bw@linear-tiling-4-displays-1920x1080p:
    - shard-adlp:         NOTRUN -> [SKIP][22] ([Intel XE#367])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-1/igt@kms_bw@linear-tiling-4-displays-1920x1080p.html

  * igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc:
    - shard-adlp:         NOTRUN -> [SKIP][23] ([Intel XE#455] / [Intel XE#787]) +3 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-1/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc.html

  * igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc@pipe-a-hdmi-a-1:
    - shard-adlp:         NOTRUN -> [SKIP][24] ([Intel XE#787]) +5 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-1/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc@pipe-a-hdmi-a-1.html

  * igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc@pipe-c-dp-2:
    - shard-dg2-set2:     NOTRUN -> [SKIP][25] ([Intel XE#787]) +41 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-dg2-432/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc@pipe-c-dp-2.html

  * igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc@pipe-d-dp-2:
    - shard-dg2-set2:     NOTRUN -> [SKIP][26] ([Intel XE#455] / [Intel XE#787]) +8 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-dg2-432/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc@pipe-d-dp-2.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][27] ([Intel XE#2907])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-dg2-434/igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][28] ([Intel XE#3432])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-4/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs:
    - shard-adlp:         NOTRUN -> [SKIP][29] ([Intel XE#2907])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-1/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs@pipe-b-dp-2:
    - shard-bmg:          NOTRUN -> [SKIP][30] ([Intel XE#2652] / [Intel XE#787]) +3 other tests skip
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-7/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs@pipe-b-dp-2.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][31] ([Intel XE#2887]) +2 other tests skip
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-4/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     [PASS][32] -> [INCOMPLETE][33] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#3124])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-6.html
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-6.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc:
    - shard-dg2-set2:     [PASS][34] -> [INCOMPLETE][35] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4522]) +1 other test incomplete
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_cdclk@mode-transition@pipe-d-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][36] ([Intel XE#4417]) +3 other tests skip
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-dg2-464/igt@kms_cdclk@mode-transition@pipe-d-dp-4.html

  * igt@kms_chamelium_color@ctm-0-50:
    - shard-bmg:          NOTRUN -> [SKIP][37] ([Intel XE#2325])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-4/igt@kms_chamelium_color@ctm-0-50.html

  * igt@kms_chamelium_color@ctm-blue-to-red:
    - shard-dg2-set2:     NOTRUN -> [SKIP][38] ([Intel XE#306])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-dg2-434/igt@kms_chamelium_color@ctm-blue-to-red.html

  * igt@kms_chamelium_frames@dp-crc-single:
    - shard-bmg:          NOTRUN -> [SKIP][39] ([Intel XE#2252]) +3 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-4/igt@kms_chamelium_frames@dp-crc-single.html

  * igt@kms_chamelium_hpd@hdmi-hpd-after-suspend:
    - shard-dg2-set2:     NOTRUN -> [SKIP][40] ([Intel XE#373])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-dg2-434/igt@kms_chamelium_hpd@hdmi-hpd-after-suspend.html

  * igt@kms_content_protection@atomic@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][41] ([Intel XE#1178])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-8/igt@kms_content_protection@atomic@pipe-a-dp-2.html

  * igt@kms_content_protection@uevent:
    - shard-dg2-set2:     NOTRUN -> [FAIL][42] ([Intel XE#1188]) +1 other test fail
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-dg2-432/igt@kms_content_protection@uevent.html

  * igt@kms_cursor_crc@cursor-onscreen-32x32:
    - shard-bmg:          NOTRUN -> [SKIP][43] ([Intel XE#2320]) +2 other tests skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-8/igt@kms_cursor_crc@cursor-onscreen-32x32.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size:
    - shard-bmg:          [PASS][44] -> [SKIP][45] ([Intel XE#2291]) +2 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-bmg-7/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-5/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
    - shard-dg2-set2:     NOTRUN -> [SKIP][46] ([Intel XE#323])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-dg2-434/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@torture-move@pipe-d:
    - shard-dg2-set2:     [PASS][47] -> [INCOMPLETE][48] ([Intel XE#3226]) +1 other test incomplete
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-dg2-432/igt@kms_cursor_legacy@torture-move@pipe-d.html
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-dg2-464/igt@kms_cursor_legacy@torture-move@pipe-d.html

  * igt@kms_dsc@dsc-basic:
    - shard-bmg:          NOTRUN -> [SKIP][49] ([Intel XE#2244])
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-4/igt@kms_dsc@dsc-basic.html

  * igt@kms_dsc@dsc-with-output-formats:
    - shard-adlp:         NOTRUN -> [SKIP][50] ([Intel XE#455])
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-1/igt@kms_dsc@dsc-with-output-formats.html

  * igt@kms_fbcon_fbt@psr:
    - shard-adlp:         NOTRUN -> [SKIP][51] ([Intel XE#776])
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-1/igt@kms_fbcon_fbt@psr.html

  * igt@kms_feature_discovery@chamelium:
    - shard-bmg:          NOTRUN -> [SKIP][52] ([Intel XE#2372])
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-4/igt@kms_feature_discovery@chamelium.html

  * igt@kms_flip@2x-flip-vs-modeset-vs-hang:
    - shard-bmg:          [PASS][53] -> [SKIP][54] ([Intel XE#2316]) +3 other tests skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-bmg-2/igt@kms_flip@2x-flip-vs-modeset-vs-hang.html
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-5/igt@kms_flip@2x-flip-vs-modeset-vs-hang.html

  * igt@kms_flip@2x-plain-flip-interruptible:
    - shard-adlp:         NOTRUN -> [SKIP][55] ([Intel XE#310]) +1 other test skip
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-1/igt@kms_flip@2x-plain-flip-interruptible.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank@c-hdmi-a1:
    - shard-adlp:         [PASS][56] -> [FAIL][57] ([Intel XE#2882]) +1 other test fail
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-adlp-2/igt@kms_flip@flip-vs-absolute-wf_vblank@c-hdmi-a1.html
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-3/igt@kms_flip@flip-vs-absolute-wf_vblank@c-hdmi-a1.html

  * igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a6:
    - shard-dg2-set2:     [PASS][58] -> [FAIL][59] ([Intel XE#301])
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-dg2-433/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a6.html
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-dg2-435/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a6.html

  * igt@kms_flip@plain-flip-ts-check:
    - shard-bmg:          [PASS][60] -> [FAIL][61] ([Intel XE#2882]) +1 other test fail
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-bmg-2/igt@kms_flip@plain-flip-ts-check.html
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-5/igt@kms_flip@plain-flip-ts-check.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
    - shard-dg2-set2:     NOTRUN -> [SKIP][62] ([Intel XE#455]) +4 other tests skip
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-dg2-434/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling:
    - shard-bmg:          NOTRUN -> [SKIP][63] ([Intel XE#2293] / [Intel XE#2380])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-8/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode:
    - shard-bmg:          NOTRUN -> [SKIP][64] ([Intel XE#2293])
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-8/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-adlp:         NOTRUN -> [SKIP][65] ([Intel XE#651]) +1 other test skip
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-1/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@drrs-2p-pri-indfb-multidraw:
    - shard-bmg:          NOTRUN -> [SKIP][66] ([Intel XE#2311]) +7 other tests skip
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-2p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@fbc-1p-rte:
    - shard-adlp:         [PASS][67] -> [DMESG-WARN][68] ([Intel XE#2953] / [Intel XE#4173]) +9 other tests dmesg-warn
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-adlp-9/igt@kms_frontbuffer_tracking@fbc-1p-rte.html
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-1/igt@kms_frontbuffer_tracking@fbc-1p-rte.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-render:
    - shard-adlp:         NOTRUN -> [SKIP][69] ([Intel XE#656]) +5 other tests skip
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-linear:
    - shard-bmg:          NOTRUN -> [SKIP][70] ([Intel XE#4141]) +5 other tests skip
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-tiling-linear.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-dg2-set2:     NOTRUN -> [SKIP][71] ([Intel XE#651]) +7 other tests skip
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-dg2-434/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-stridechange:
    - shard-dg2-set2:     NOTRUN -> [SKIP][72] ([Intel XE#653]) +5 other tests skip
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-dg2-434/igt@kms_frontbuffer_tracking@fbcpsr-stridechange.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][73] ([Intel XE#2313]) +7 other tests skip
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt:
    - shard-adlp:         NOTRUN -> [SKIP][74] ([Intel XE#653])
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt.html

  * igt@kms_hdr@static-toggle-suspend:
    - shard-bmg:          [PASS][75] -> [SKIP][76] ([Intel XE#1503])
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-bmg-5/igt@kms_hdr@static-toggle-suspend.html
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-6/igt@kms_hdr@static-toggle-suspend.html

  * igt@kms_joiner@basic-force-ultra-joiner:
    - shard-dg2-set2:     NOTRUN -> [SKIP][77] ([Intel XE#2925]) +1 other test skip
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-dg2-432/igt@kms_joiner@basic-force-ultra-joiner.html

  * igt@kms_joiner@invalid-modeset-force-big-joiner:
    - shard-bmg:          [PASS][78] -> [SKIP][79] ([Intel XE#3012])
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-bmg-1/igt@kms_joiner@invalid-modeset-force-big-joiner.html
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-6/igt@kms_joiner@invalid-modeset-force-big-joiner.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-75@pipe-c:
    - shard-adlp:         NOTRUN -> [DMESG-WARN][80] ([Intel XE#2953] / [Intel XE#4173]) +4 other tests dmesg-warn
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-1/igt@kms_plane_scaling@planes-downscale-factor-0-75@pipe-c.html

  * igt@kms_pm_backlight@fade-with-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][81] ([Intel XE#870])
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-4/igt@kms_pm_backlight@fade-with-suspend.html

  * igt@kms_pm_dc@dc5-retention-flops:
    - shard-dg2-set2:     NOTRUN -> [SKIP][82] ([Intel XE#3309])
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-dg2-434/igt@kms_pm_dc@dc5-retention-flops.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf:
    - shard-bmg:          NOTRUN -> [SKIP][83] ([Intel XE#1489]) +1 other test skip
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-4/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area:
    - shard-adlp:         NOTRUN -> [SKIP][84] ([Intel XE#1489])
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-1/igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@pr-overlay-plane-move-continuous-sf:
    - shard-dg2-set2:     NOTRUN -> [SKIP][85] ([Intel XE#1489])
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-dg2-434/igt@kms_psr2_sf@pr-overlay-plane-move-continuous-sf.html

  * igt@kms_psr@fbc-pr-primary-page-flip:
    - shard-adlp:         NOTRUN -> [SKIP][86] ([Intel XE#2850] / [Intel XE#929]) +1 other test skip
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-1/igt@kms_psr@fbc-pr-primary-page-flip.html

  * igt@kms_psr@fbc-psr2-sprite-plane-move:
    - shard-dg2-set2:     NOTRUN -> [SKIP][87] ([Intel XE#2850] / [Intel XE#929]) +3 other tests skip
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-dg2-434/igt@kms_psr@fbc-psr2-sprite-plane-move.html

  * igt@kms_psr@psr-sprite-plane-move:
    - shard-bmg:          NOTRUN -> [SKIP][88] ([Intel XE#2234] / [Intel XE#2850]) +3 other tests skip
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-4/igt@kms_psr@psr-sprite-plane-move.html

  * igt@kms_setmode@invalid-clone-single-crtc-stealing:
    - shard-bmg:          [PASS][89] -> [SKIP][90] ([Intel XE#1435])
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-bmg-2/igt@kms_setmode@invalid-clone-single-crtc-stealing.html
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-5/igt@kms_setmode@invalid-clone-single-crtc-stealing.html

  * igt@kms_vrr@cmrr@pipe-a-edp-1:
    - shard-lnl:          [PASS][91] -> [FAIL][92] ([Intel XE#4459]) +1 other test fail
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-lnl-7/igt@kms_vrr@cmrr@pipe-a-edp-1.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-lnl-2/igt@kms_vrr@cmrr@pipe-a-edp-1.html

  * igt@xe_eudebug@basic-vm-bind-extended-discovery:
    - shard-dg2-set2:     NOTRUN -> [SKIP][93] ([Intel XE#4837]) +2 other tests skip
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-dg2-432/igt@xe_eudebug@basic-vm-bind-extended-discovery.html

  * igt@xe_eudebug@read-metadata:
    - shard-adlp:         NOTRUN -> [SKIP][94] ([Intel XE#4837]) +1 other test skip
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-1/igt@xe_eudebug@read-metadata.html

  * igt@xe_eudebug_online@breakpoint-many-sessions-single-tile:
    - shard-bmg:          NOTRUN -> [SKIP][95] ([Intel XE#4837]) +2 other tests skip
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-4/igt@xe_eudebug_online@breakpoint-many-sessions-single-tile.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate-race:
    - shard-dg2-set2:     NOTRUN -> [SKIP][96] ([Intel XE#1392])
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-dg2-432/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate-race.html

  * igt@xe_exec_basic@multigpu-no-exec-basic:
    - shard-bmg:          NOTRUN -> [SKIP][97] ([Intel XE#2322]) +3 other tests skip
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-4/igt@xe_exec_basic@multigpu-no-exec-basic.html

  * igt@xe_exec_basic@multigpu-no-exec-null-defer-mmap:
    - shard-dg2-set2:     [PASS][98] -> [SKIP][99] ([Intel XE#1392]) +2 other tests skip
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-dg2-463/igt@xe_exec_basic@multigpu-no-exec-null-defer-mmap.html
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-dg2-432/igt@xe_exec_basic@multigpu-no-exec-null-defer-mmap.html

  * igt@xe_exec_fault_mode@twice-bindexecqueue-rebind-prefetch:
    - shard-adlp:         NOTRUN -> [SKIP][100] ([Intel XE#288]) +1 other test skip
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-1/igt@xe_exec_fault_mode@twice-bindexecqueue-rebind-prefetch.html

  * igt@xe_exec_fault_mode@twice-invalid-fault:
    - shard-dg2-set2:     NOTRUN -> [SKIP][101] ([Intel XE#288]) +6 other tests skip
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-dg2-432/igt@xe_exec_fault_mode@twice-invalid-fault.html

  * igt@xe_exec_system_allocator@processes-evict-malloc:
    - shard-adlp:         NOTRUN -> [SKIP][102] ([Intel XE#4915]) +29 other tests skip
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-1/igt@xe_exec_system_allocator@processes-evict-malloc.html

  * igt@xe_exec_system_allocator@threads-many-execqueues-mmap-free-huge-nomemset:
    - shard-bmg:          NOTRUN -> [SKIP][103] ([Intel XE#4943]) +7 other tests skip
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-4/igt@xe_exec_system_allocator@threads-many-execqueues-mmap-free-huge-nomemset.html

  * igt@xe_exec_system_allocator@threads-many-large-execqueues-mmap-remap-ro-eocheck:
    - shard-dg2-set2:     NOTRUN -> [SKIP][104] ([Intel XE#4915]) +69 other tests skip
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-dg2-434/igt@xe_exec_system_allocator@threads-many-large-execqueues-mmap-remap-ro-eocheck.html

  * igt@xe_module_load@load:
    - shard-adlp:         ([PASS][105], [PASS][106], [PASS][107], [PASS][108], [PASS][109], [PASS][110], [PASS][111], [PASS][112], [PASS][113], [PASS][114], [PASS][115], [PASS][116], [PASS][117], [PASS][118], [PASS][119], [PASS][120], [PASS][121], [PASS][122], [PASS][123], [PASS][124], [PASS][125], [PASS][126], [PASS][127], [PASS][128], [PASS][129]) -> ([PASS][130], [PASS][131], [PASS][132], [PASS][133], [PASS][134], [PASS][135], [PASS][136], [PASS][137], [PASS][138], [PASS][139], [PASS][140], [PASS][141], [PASS][142], [PASS][143], [PASS][144], [PASS][145], [SKIP][146], [PASS][147], [PASS][148], [PASS][149], [PASS][150], [PASS][151], [PASS][152], [PASS][153], [PASS][154], [PASS][155]) ([Intel XE#378])
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-adlp-1/igt@xe_module_load@load.html
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-adlp-8/igt@xe_module_load@load.html
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-adlp-8/igt@xe_module_load@load.html
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-adlp-1/igt@xe_module_load@load.html
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-adlp-4/igt@xe_module_load@load.html
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-adlp-8/igt@xe_module_load@load.html
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-adlp-6/igt@xe_module_load@load.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-adlp-1/igt@xe_module_load@load.html
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-adlp-9/igt@xe_module_load@load.html
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-adlp-9/igt@xe_module_load@load.html
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-adlp-1/igt@xe_module_load@load.html
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-adlp-9/igt@xe_module_load@load.html
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-adlp-6/igt@xe_module_load@load.html
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-adlp-6/igt@xe_module_load@load.html
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-adlp-2/igt@xe_module_load@load.html
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-adlp-2/igt@xe_module_load@load.html
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-adlp-2/igt@xe_module_load@load.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-adlp-6/igt@xe_module_load@load.html
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-adlp-4/igt@xe_module_load@load.html
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-adlp-4/igt@xe_module_load@load.html
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-adlp-6/igt@xe_module_load@load.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-adlp-3/igt@xe_module_load@load.html
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-adlp-3/igt@xe_module_load@load.html
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-adlp-3/igt@xe_module_load@load.html
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-adlp-2/igt@xe_module_load@load.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-8/igt@xe_module_load@load.html
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-8/igt@xe_module_load@load.html
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-9/igt@xe_module_load@load.html
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-9/igt@xe_module_load@load.html
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-3/igt@xe_module_load@load.html
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-3/igt@xe_module_load@load.html
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-4/igt@xe_module_load@load.html
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-4/igt@xe_module_load@load.html
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-8/igt@xe_module_load@load.html
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-8/igt@xe_module_load@load.html
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-3/igt@xe_module_load@load.html
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-1/igt@xe_module_load@load.html
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-1/igt@xe_module_load@load.html
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-1/igt@xe_module_load@load.html
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-2/igt@xe_module_load@load.html
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-2/igt@xe_module_load@load.html
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-1/igt@xe_module_load@load.html
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-4/igt@xe_module_load@load.html
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-4/igt@xe_module_load@load.html
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-6/igt@xe_module_load@load.html
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-6/igt@xe_module_load@load.html
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-6/igt@xe_module_load@load.html
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-2/igt@xe_module_load@load.html
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-2/igt@xe_module_load@load.html
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-2/igt@xe_module_load@load.html
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-9/igt@xe_module_load@load.html

  * igt@xe_oa@missing-sample-flags:
    - shard-dg2-set2:     NOTRUN -> [SKIP][156] ([Intel XE#2541] / [Intel XE#3573])
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-dg2-434/igt@xe_oa@missing-sample-flags.html

  * igt@xe_oa@non-privileged-map-oa-buffer:
    - shard-adlp:         NOTRUN -> [SKIP][157] ([Intel XE#2541] / [Intel XE#3573])
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-1/igt@xe_oa@non-privileged-map-oa-buffer.html

  * igt@xe_pm@d3cold-mocs:
    - shard-bmg:          NOTRUN -> [SKIP][158] ([Intel XE#2284])
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-4/igt@xe_pm@d3cold-mocs.html

  * igt@xe_pmu@all-fn-engine-activity-load:
    - shard-adlp:         NOTRUN -> [ABORT][159] ([Intel XE#5214]) +1 other test abort
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-6/igt@xe_pmu@all-fn-engine-activity-load.html

  * igt@xe_pmu@fn-engine-activity-load:
    - shard-bmg:          NOTRUN -> [SKIP][160] ([Intel XE#4650])
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-4/igt@xe_pmu@fn-engine-activity-load.html

  * igt@xe_pxp@display-pxp-fb:
    - shard-adlp:         NOTRUN -> [SKIP][161] ([Intel XE#4733])
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-1/igt@xe_pxp@display-pxp-fb.html

  * igt@xe_pxp@pxp-termination-key-update-post-suspend:
    - shard-dg2-set2:     NOTRUN -> [SKIP][162] ([Intel XE#4733]) +1 other test skip
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-dg2-434/igt@xe_pxp@pxp-termination-key-update-post-suspend.html

  * igt@xe_query@multigpu-query-engines:
    - shard-bmg:          NOTRUN -> [SKIP][163] ([Intel XE#944])
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-4/igt@xe_query@multigpu-query-engines.html

  * igt@xe_spin_batch@spin-mem-copy:
    - shard-adlp:         NOTRUN -> [SKIP][164] ([Intel XE#4821])
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-1/igt@xe_spin_batch@spin-mem-copy.html

  
#### Possible fixes ####

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
    - shard-adlp:         [DMESG-FAIL][165] ([Intel XE#4543]) -> [PASS][166]
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-adlp-9/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-1/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html

  * igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p:
    - shard-bmg:          [SKIP][167] ([Intel XE#2314] / [Intel XE#2894]) -> [PASS][168]
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-bmg-6/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-2/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-dp-4:
    - shard-dg2-set2:     [INCOMPLETE][169] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4522]) -> [PASS][170] +1 other test pass
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-dp-4.html
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-dp-4.html

  * igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
    - shard-bmg:          [SKIP][171] ([Intel XE#2291]) -> [PASS][172] +4 other tests pass
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-bmg-6/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-2/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc:
    - shard-bmg:          [SKIP][173] ([Intel XE#1340]) -> [PASS][174]
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-bmg-5/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-4/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html

  * igt@kms_dp_aux_dev:
    - shard-bmg:          [SKIP][175] ([Intel XE#3009]) -> [PASS][176]
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-bmg-6/igt@kms_dp_aux_dev.html
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-8/igt@kms_dp_aux_dev.html

  * igt@kms_feature_discovery@display-2x:
    - shard-bmg:          [SKIP][177] ([Intel XE#2373]) -> [PASS][178]
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-bmg-6/igt@kms_feature_discovery@display-2x.html
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-7/igt@kms_feature_discovery@display-2x.html

  * igt@kms_flip@2x-plain-flip:
    - shard-bmg:          [SKIP][179] ([Intel XE#2316]) -> [PASS][180] +5 other tests pass
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-bmg-6/igt@kms_flip@2x-plain-flip.html
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-2/igt@kms_flip@2x-plain-flip.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-dp4:
    - shard-dg2-set2:     [FAIL][181] ([Intel XE#301]) -> [PASS][182] +8 other tests pass
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-dg2-433/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-dp4.html
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-dg2-436/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-dp4.html

  * igt@kms_flip@flip-vs-expired-vblank@b-dp4:
    - shard-dg2-set2:     [FAIL][183] ([Intel XE#301] / [Intel XE#3321]) -> [PASS][184]
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-dg2-433/igt@kms_flip@flip-vs-expired-vblank@b-dp4.html
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-dg2-435/igt@kms_flip@flip-vs-expired-vblank@b-dp4.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@a-dp2:
    - shard-bmg:          [FAIL][185] ([Intel XE#2882]) -> [PASS][186]
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-bmg-4/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-dp2.html
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-4/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-dp2.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@b-hdmi-a6:
    - shard-dg2-set2:     [INCOMPLETE][187] ([Intel XE#2049]) -> [PASS][188]
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-dg2-466/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-hdmi-a6.html
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-dg2-463/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-hdmi-a6.html

  * igt@kms_flip@wf_vblank-ts-check@a-edp1:
    - shard-lnl:          [FAIL][189] ([Intel XE#886]) -> [PASS][190] +1 other test pass
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-lnl-2/igt@kms_flip@wf_vblank-ts-check@a-edp1.html
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-lnl-7/igt@kms_flip@wf_vblank-ts-check@a-edp1.html

  * igt@kms_hdr@static-swap:
    - shard-bmg:          [SKIP][191] ([Intel XE#1503]) -> [PASS][192]
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-bmg-6/igt@kms_hdr@static-swap.html
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-2/igt@kms_hdr@static-swap.html

  * igt@kms_plane_multiple@2x-tiling-x:
    - shard-bmg:          [SKIP][193] ([Intel XE#4596]) -> [PASS][194]
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-bmg-6/igt@kms_plane_multiple@2x-tiling-x.html
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-7/igt@kms_plane_multiple@2x-tiling-x.html

  * igt@kms_vblank@query-idle@pipe-a-hdmi-a-1:
    - shard-adlp:         [DMESG-WARN][195] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][196] +1 other test pass
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-adlp-6/igt@kms_vblank@query-idle@pipe-a-hdmi-a-1.html
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-2/igt@kms_vblank@query-idle@pipe-a-hdmi-a-1.html

  * igt@xe_exec_basic@multigpu-no-exec-userptr-invalidate-race:
    - shard-dg2-set2:     [SKIP][197] ([Intel XE#1392]) -> [PASS][198] +1 other test pass
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-dg2-432/igt@xe_exec_basic@multigpu-no-exec-userptr-invalidate-race.html
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-dg2-464/igt@xe_exec_basic@multigpu-no-exec-userptr-invalidate-race.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-execqueues-new-bo-map:
    - shard-lnl:          [FAIL][199] -> [PASS][200]
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-lnl-1/igt@xe_exec_system_allocator@threads-shared-vm-many-execqueues-new-bo-map.html
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-lnl-8/igt@xe_exec_system_allocator@threads-shared-vm-many-execqueues-new-bo-map.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-large-new-bo-map-nomemset:
    - shard-lnl:          [FAIL][201] ([Intel XE#5018]) -> [PASS][202]
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-lnl-7/igt@xe_exec_system_allocator@threads-shared-vm-many-large-new-bo-map-nomemset.html
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-lnl-2/igt@xe_exec_system_allocator@threads-shared-vm-many-large-new-bo-map-nomemset.html

  * igt@xe_pm@s4-vm-bind-unbind-all:
    - shard-adlp:         [ABORT][203] ([Intel XE#1794]) -> [PASS][204]
   [203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-adlp-9/igt@xe_pm@s4-vm-bind-unbind-all.html
   [204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-1/igt@xe_pm@s4-vm-bind-unbind-all.html

  * igt@xe_pm@s4-vm-bind-userptr:
    - shard-bmg:          [ABORT][205] ([Intel XE#5255]) -> [PASS][206]
   [205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-bmg-6/igt@xe_pm@s4-vm-bind-userptr.html
   [206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-8/igt@xe_pm@s4-vm-bind-userptr.html

  
#### Warnings ####

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs:
    - shard-dg2-set2:     [INCOMPLETE][207] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4345] / [Intel XE#4522]) -> [INCOMPLETE][208] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#3124] / [Intel XE#4345])
   [207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
   [208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html

  * igt@kms_content_protection@atomic:
    - shard-bmg:          [SKIP][209] ([Intel XE#2341]) -> [FAIL][210] ([Intel XE#1178])
   [209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-bmg-5/igt@kms_content_protection@atomic.html
   [210]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-8/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@srm:
    - shard-bmg:          [FAIL][211] ([Intel XE#1178]) -> [SKIP][212] ([Intel XE#2341])
   [211]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-bmg-2/igt@kms_content_protection@srm.html
   [212]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-5/igt@kms_content_protection@srm.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt:
    - shard-bmg:          [SKIP][213] ([Intel XE#2312]) -> [SKIP][214] ([Intel XE#2311]) +16 other tests skip
   [213]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt.html
   [214]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-7/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][215] ([Intel XE#4141]) -> [SKIP][216] ([Intel XE#2312]) +4 other tests skip
   [215]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc.html
   [216]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render:
    - shard-bmg:          [SKIP][217] ([Intel XE#2312]) -> [SKIP][218] ([Intel XE#4141]) +8 other tests skip
   [217]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html
   [218]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-blt:
    - shard-bmg:          [SKIP][219] ([Intel XE#2311]) -> [SKIP][220] ([Intel XE#2312]) +9 other tests skip
   [219]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-blt.html
   [220]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render:
    - shard-bmg:          [SKIP][221] ([Intel XE#2313]) -> [SKIP][222] ([Intel XE#2312]) +5 other tests skip
   [221]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render.html
   [222]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt:
    - shard-bmg:          [SKIP][223] ([Intel XE#2312]) -> [SKIP][224] ([Intel XE#2313]) +19 other tests skip
   [223]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-bmg-5/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
   [224]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-bmg-4/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html

  * igt@xe_pmu@engine-activity-most-load-idle:
    - shard-adlp:         [ABORT][225] ([Intel XE#5214]) -> [DMESG-WARN][226] ([Intel XE#5214]) +3 other tests dmesg-warn
   [225]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-adlp-6/igt@xe_pmu@engine-activity-most-load-idle.html
   [226]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-2/igt@xe_pmu@engine-activity-most-load-idle.html

  * igt@xe_pmu@fn-engine-activity-load:
    - shard-adlp:         [ABORT][227] ([Intel XE#5214]) -> [FAIL][228] ([Intel XE#5219])
   [227]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3254-6e474d767e318b98cc45d4b90095290879085741/shard-adlp-6/igt@xe_pmu@fn-engine-activity-load.html
   [228]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/shard-adlp-1/igt@xe_pmu@fn-engine-activity-load.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1188]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1188
  [Intel XE#1340]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1340
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#1794]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1794
  [Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
  [Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
  [Intel XE#2372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2372
  [Intel XE#2373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2373
  [Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
  [Intel XE#2541]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2541
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2705
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#2882]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2882
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
  [Intel XE#2907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2907
  [Intel XE#2925]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2925
  [Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
  [Intel XE#3009]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3009
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#3012]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3012
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#310]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/310
  [Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
  [Intel XE#3124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3124
  [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
  [Intel XE#3226]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3226
  [Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
  [Intel XE#3309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3309
  [Intel XE#3321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3321
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
  [Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
  [Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
  [Intel XE#4417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4417
  [Intel XE#4459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4459
  [Intel XE#4522]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4522
  [Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
  [Intel XE#4650]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4650
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4821]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4821
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
  [Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
  [Intel XE#5018]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5018
  [Intel XE#5214]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5214
  [Intel XE#5219]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5219
  [Intel XE#5255]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5255
  [Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/886
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-3254-6e474d767e318b98cc45d4b90095290879085741 -> xe-pw-150300v1

  IGT_8411: d5b5d2bb4f8795a98ea58376a128b74f654b7ec1 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-3254-6e474d767e318b98cc45d4b90095290879085741: 6e474d767e318b98cc45d4b90095290879085741
  xe-pw-150300v1: 150300v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150300v1/index.html

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