* [PATCH v9 0/3] CCS save restore for IGPU
@ 2025-06-24 10:00 Satyanarayana K V P
2025-06-24 10:00 ` [PATCH v9 1/3] drm/xe/vf: Create contexts for CCS read write Satyanarayana K V P
` (6 more replies)
0 siblings, 7 replies; 13+ messages in thread
From: Satyanarayana K V P @ 2025-06-24 10:00 UTC (permalink / raw)
To: intel-xe; +Cc: Satyanarayana K V P
Prior IGPU design had compression supported in GPU VA domain. For
Virtualization, this makes compression Meta data save/restore for VF as
not necessary (i.e. Compression Meta data space is automatically
save/restore with normal guest/VM memory).
With latest Xe2 architecture, compression is supported by Flat, physical
domain. Meta data/compression control surface (Aka CCS) and association
is in physical domain and data is located in BIOS/firmware-reserved CCS
pool. In virtualization/SRIOV when VF save/restore now have to account for
save/restore VF associated CCS. Without this feature any restore of
compressed resource in IGPU VF domain will have corruption as Meta data
will not be restore correctly as a part of VF save/restore flow. Making it
must have/functional feature if we are supporting compression and
Save/restore of VF on IGPU platform.
This is the first in series which adds support for CCS save/restore for
IGPU.
V8 -> V9:
- Fixed review comments (atthew Brost).
- Removed MI_INVALIDATE_TLB after emitting PTEs (Matthew Brost).
- Initialized CCS read write contexts for only root tile (Matthew Brost).
V7 -> V8:
- Fixed review comments (atthew Brost).
- Removed xe_bb_ccs_realloc() and allocated a single BB by calculating BB
size first and then commands are emitted to BB.
V6 -> V7:
- Fixed review comments (Michal Wajdeczko & Matthew Brost).
- Created xe_bb_ccs_realloc() to create a single BB instead of maintaining
a list. (Matthew Brost)
- Replaced xe_tile_migrate_exec_queue() with xe_migrate_exec_queue() as per
review comments (Matthew Brost).
V5 -> V6:
- Removed dead code from xe_migrate_ccs_rw_copy() function (Matthew Brost)
- Added id field in the xe_tile_vf_ccs structure for self identification.
V4 -> V5:
- Modified read/write contexts to enums from #defines (Matthew Brost).
- The CCS BB pool size is calculated based on the system memory size
(Michal Wajdeczko & Matthew Brost).
- Fixed review comments (Matthew Brost & Matthew Auld)
- Create a list of BBs for the given BO and fixed memory leak while
detaching BOs. (Matthew Brost).
- Yet to cleanup xe_migrate_ccs_rw_copy() function.
V3 -> V4:
- Fixed issues reported by patchworks.
V2 -> V3:
- Added new variable which denotes the initialization of contexts.
- Attach and detach functions check for IS_VF_CCS_READY().
- Made xe_migrate structure private as per review comments.
- Created new xe_migrate functions to get lrc and exec_queue.
V1 -> V2:
- Fixed review comments.
Satyanarayana K V P (3):
drm/xe/vf: Create contexts for CCS read write
drm/xe/vf: Attach and detach CCS copy commands with BO
drm/xe/vf: Register CCS read/write contexts with Guc
drivers/gpu/drm/xe/Makefile | 1 +
drivers/gpu/drm/xe/xe_bb.c | 35 ++
drivers/gpu/drm/xe/xe_bb.h | 3 +
drivers/gpu/drm/xe/xe_bo.c | 23 ++
drivers/gpu/drm/xe/xe_bo_types.h | 3 +
drivers/gpu/drm/xe/xe_device.c | 4 +
drivers/gpu/drm/xe/xe_device_types.h | 4 +
drivers/gpu/drm/xe/xe_gt_debugfs.c | 36 ++
drivers/gpu/drm/xe/xe_guc_fwif.h | 5 +
drivers/gpu/drm/xe/xe_guc_submit.c | 34 +-
drivers/gpu/drm/xe/xe_guc_submit.h | 1 +
drivers/gpu/drm/xe/xe_migrate.c | 164 ++++++++-
drivers/gpu/drm/xe/xe_migrate.h | 10 +-
drivers/gpu/drm/xe/xe_pm.c | 4 +
drivers/gpu/drm/xe/xe_sriov.c | 19 ++
drivers/gpu/drm/xe/xe_sriov.h | 1 +
drivers/gpu/drm/xe/xe_sriov_types.h | 5 +
drivers/gpu/drm/xe/xe_sriov_vf_ccs.c | 366 +++++++++++++++++++++
drivers/gpu/drm/xe/xe_sriov_vf_ccs.h | 17 +
drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h | 53 +++
drivers/gpu/drm/xe/xe_vm.c | 6 +-
21 files changed, 774 insertions(+), 20 deletions(-)
create mode 100644 drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
create mode 100644 drivers/gpu/drm/xe/xe_sriov_vf_ccs.h
create mode 100644 drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h
--
2.43.0
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v9 1/3] drm/xe/vf: Create contexts for CCS read write
2025-06-24 10:00 [PATCH v9 0/3] CCS save restore for IGPU Satyanarayana K V P
@ 2025-06-24 10:00 ` Satyanarayana K V P
2025-06-24 15:40 ` Matthew Brost
2025-06-24 17:01 ` Matthew Brost
2025-06-24 10:00 ` [PATCH v9 2/3] drm/xe/vf: Attach and detach CCS copy commands with BO Satyanarayana K V P
` (5 subsequent siblings)
6 siblings, 2 replies; 13+ messages in thread
From: Satyanarayana K V P @ 2025-06-24 10:00 UTC (permalink / raw)
To: intel-xe
Cc: Satyanarayana K V P, Michal Wajdeczko, Matthew Brost,
Michał Winiarski, Tomasz Lis, Matthew Auld
Create two LRCs to handle CCS meta data read / write from CCS pool in the
VM. Read context is used to hold GPU instructions to be executed at save
time and write context is used to hold GPU instructions to be executed at
the restore time.
Allocate batch buffer pool using suballocator for both read and write
contexts.
Migration framework is reused to create LRCAs for read and write.
Signed-off-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Michał Winiarski <michal.winiarski@intel.com>
Acked-by: Matthew Brost <matthew.brost@intel.com>
---
Cc: Tomasz Lis <tomasz.lis@intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
V8 -> V9:
- Initialized CCS read write contexts for only root tile (Matthew Brost).
V7 -> V8:
- None.
V6 -> V7:
- Fixed review comments (Michal Wajdeczko & Matthew Brost).
V5 -> V6:
- Added id field in the xe_tile_vf_ccs structure for self identification.
V4 -> V5:
- Modified read/write contexts to enums from #defines (Matthew Brost).
- The CCS BB pool size is calculated based on the system memory size (Michal
Wajdeczko & Matthew Brost).
V3 -> V4:
- Fixed issues reported by patchworks.
V2 -> V3:
- Added new variable which denotes the initialization of contexts.
V1 -> V2:
- Fixed review comments.
---
drivers/gpu/drm/xe/Makefile | 1 +
drivers/gpu/drm/xe/xe_device.c | 4 +
drivers/gpu/drm/xe/xe_device_types.h | 4 +
drivers/gpu/drm/xe/xe_gt_debugfs.c | 36 ++++
drivers/gpu/drm/xe/xe_sriov.c | 19 ++
drivers/gpu/drm/xe/xe_sriov.h | 1 +
drivers/gpu/drm/xe/xe_sriov_types.h | 5 +
drivers/gpu/drm/xe/xe_sriov_vf_ccs.c | 208 +++++++++++++++++++++
drivers/gpu/drm/xe/xe_sriov_vf_ccs.h | 13 ++
drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h | 45 +++++
10 files changed, 336 insertions(+)
create mode 100644 drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
create mode 100644 drivers/gpu/drm/xe/xe_sriov_vf_ccs.h
create mode 100644 drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index eee6bac01a00..853970ab1314 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -141,6 +141,7 @@ xe-y += \
xe_memirq.o \
xe_sriov.o \
xe_sriov_vf.o \
+ xe_sriov_vf_ccs.o \
xe_tile_sriov_vf.o
xe-$(CONFIG_PCI_IOV) += \
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index e160e7be84f0..b7922668741c 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -929,6 +929,10 @@ int xe_device_probe(struct xe_device *xe)
xe_vsec_init(xe);
+ err = xe_sriov_late_init(xe);
+ if (err)
+ goto err_unregister_display;
+
return devm_add_action_or_reset(xe->drm.dev, xe_device_sanitize, xe);
err_unregister_display:
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 6aca4b1a2824..1b52db967ace 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -22,6 +22,7 @@
#include "xe_pmu_types.h"
#include "xe_pt_types.h"
#include "xe_sriov_types.h"
+#include "xe_sriov_vf_ccs_types.h"
#include "xe_step_types.h"
#include "xe_survivability_mode_types.h"
#include "xe_ttm_vram_mgr_types.h"
@@ -235,6 +236,9 @@ struct xe_tile {
struct {
/** @sriov.vf.ggtt_balloon: GGTT regions excluded from use. */
struct xe_ggtt_node *ggtt_balloon[2];
+
+ /** @sriov.vf.ccs: CCS read and write contexts for VF. */
+ struct xe_tile_vf_ccs ccs[XE_SRIOV_VF_CCS_CTX_COUNT];
} vf;
} sriov;
diff --git a/drivers/gpu/drm/xe/xe_gt_debugfs.c b/drivers/gpu/drm/xe/xe_gt_debugfs.c
index 848618acdca8..404844515523 100644
--- a/drivers/gpu/drm/xe/xe_gt_debugfs.c
+++ b/drivers/gpu/drm/xe/xe_gt_debugfs.c
@@ -134,6 +134,30 @@ static int sa_info(struct xe_gt *gt, struct drm_printer *p)
return 0;
}
+static int sa_info_vf_ccs(struct xe_gt *gt, struct drm_printer *p)
+{
+ struct xe_tile *tile = gt_to_tile(gt);
+ struct xe_sa_manager *bb_pool;
+ enum xe_sriov_vf_ccs_rw_ctxs ctx_id;
+
+ if (!IS_VF_CCS_READY(gt_to_xe(gt)))
+ return 0;
+
+ xe_pm_runtime_get(gt_to_xe(gt));
+
+ for_each_ccs_rw_ctx(ctx_id) {
+ drm_printf(p, "ccs %s bb suballoc info\n", ctx_id ? "write" : "read");
+ drm_printf(p, "-------------------------\n");
+ bb_pool = tile->sriov.vf.ccs[ctx_id].mem.ccs_bb_pool;
+ drm_suballoc_dump_debug_info(&bb_pool->base, p, bb_pool->gpu_addr);
+ drm_puts(p, "\n");
+ }
+
+ xe_pm_runtime_put(gt_to_xe(gt));
+
+ return 0;
+}
+
static int topology(struct xe_gt *gt, struct drm_printer *p)
{
xe_pm_runtime_get(gt_to_xe(gt));
@@ -303,6 +327,13 @@ static const struct drm_info_list vf_safe_debugfs_list[] = {
{"hwconfig", .show = xe_gt_debugfs_simple_show, .data = hwconfig},
};
+/*
+ * only for GT debugfs files which are valid on VF. Not valid on PF.
+ */
+static const struct drm_info_list vf_only_debugfs_list[] = {
+ {"sa_info_vf_ccs", .show = xe_gt_debugfs_simple_show, .data = sa_info_vf_ccs},
+};
+
/* everything else should be added here */
static const struct drm_info_list pf_only_debugfs_list[] = {
{"hw_engines", .show = xe_gt_debugfs_simple_show, .data = hw_engines},
@@ -419,6 +450,11 @@ void xe_gt_debugfs_register(struct xe_gt *gt)
drm_debugfs_create_files(pf_only_debugfs_list,
ARRAY_SIZE(pf_only_debugfs_list),
root, minor);
+ else
+ drm_debugfs_create_files(vf_only_debugfs_list,
+ ARRAY_SIZE(vf_only_debugfs_list),
+ root, minor);
+
xe_uc_debugfs_register(>->uc, root);
diff --git a/drivers/gpu/drm/xe/xe_sriov.c b/drivers/gpu/drm/xe/xe_sriov.c
index a0eab44c0e76..87911fb4eea7 100644
--- a/drivers/gpu/drm/xe/xe_sriov.c
+++ b/drivers/gpu/drm/xe/xe_sriov.c
@@ -15,6 +15,7 @@
#include "xe_sriov.h"
#include "xe_sriov_pf.h"
#include "xe_sriov_vf.h"
+#include "xe_sriov_vf_ccs.h"
/**
* xe_sriov_mode_to_string - Convert enum value to string.
@@ -157,3 +158,21 @@ const char *xe_sriov_function_name(unsigned int n, char *buf, size_t size)
strscpy(buf, "PF", size);
return buf;
}
+
+/**
+ * xe_sriov_late_init() - SR-IOV late initialization functions.
+ * @xe: the &xe_device to initialize
+ *
+ * On VF this function will initialize code for CCS migration.
+ *
+ * Return: 0 on success or a negative error code on failure.
+ */
+int xe_sriov_late_init(struct xe_device *xe)
+{
+ int err = 0;
+
+ if (IS_VF_CCS_INIT_NEEDED(xe))
+ err = xe_sriov_vf_ccs_init(xe);
+
+ return err;
+}
diff --git a/drivers/gpu/drm/xe/xe_sriov.h b/drivers/gpu/drm/xe/xe_sriov.h
index 688fbabf08f1..0e0c1abf2d14 100644
--- a/drivers/gpu/drm/xe/xe_sriov.h
+++ b/drivers/gpu/drm/xe/xe_sriov.h
@@ -18,6 +18,7 @@ const char *xe_sriov_function_name(unsigned int n, char *buf, size_t len);
void xe_sriov_probe_early(struct xe_device *xe);
void xe_sriov_print_info(struct xe_device *xe, struct drm_printer *p);
int xe_sriov_init(struct xe_device *xe);
+int xe_sriov_late_init(struct xe_device *xe);
static inline enum xe_sriov_mode xe_device_sriov_mode(const struct xe_device *xe)
{
diff --git a/drivers/gpu/drm/xe/xe_sriov_types.h b/drivers/gpu/drm/xe/xe_sriov_types.h
index ca94382a721e..8abfdb2c5ead 100644
--- a/drivers/gpu/drm/xe/xe_sriov_types.h
+++ b/drivers/gpu/drm/xe/xe_sriov_types.h
@@ -71,6 +71,11 @@ struct xe_device_vf {
/** @migration.gt_flags: Per-GT request flags for VF migration recovery */
unsigned long gt_flags;
} migration;
+
+ struct {
+ /** @initialized: Initilalization of vf ccs is completed or not */
+ bool initialized;
+ } ccs;
};
#endif
diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
new file mode 100644
index 000000000000..9000d618978d
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
@@ -0,0 +1,208 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#include "instructions/xe_mi_commands.h"
+#include "instructions/xe_gpu_commands.h"
+#include "xe_bo.h"
+#include "xe_device.h"
+#include "xe_migrate.h"
+#include "xe_sa.h"
+#include "xe_sriov_printk.h"
+#include "xe_sriov_vf_ccs.h"
+#include "xe_sriov_vf_ccs_types.h"
+
+/**
+ * DOC: VF save/restore of compression Meta Data
+ *
+ * VF KMD registers two special contexts/LRCAs.
+ *
+ * Save Context/LRCA: contain necessary cmds+page table to trigger Meta data /
+ * compression control surface (Aka CCS) save in regular System memory in VM.
+ *
+ * Restore Context/LRCA: contain necessary cmds+page table to trigger Meta data /
+ * compression control surface (Aka CCS) Restore from regular System memory in
+ * VM to corresponding CCS pool.
+ *
+ * Below diagram explain steps needed for VF save/Restore of compression Meta Data::
+ *
+ * CCS Save CCS Restore VF KMD Guc BCS
+ * LRCA LRCA
+ * | | | | |
+ * | | | | |
+ * | Create Save LRCA | | |
+ * [ ]<----------------------------- [ ] | |
+ * | | | | |
+ * | | | | |
+ * | | | Register save LRCA | |
+ * | | | with Guc | |
+ * | | [ ]--------------------------->[ ] |
+ * | | | | |
+ * | | Create restore LRCA | | |
+ * | [ ]<------------------[ ] | |
+ * | | | | |
+ * | | | Register restore LRCA | |
+ * | | | with Guc | |
+ * | | [ ]--------------------------->[ ] |
+ * | | | | |
+ * | | | | |
+ * | | [ ]------------------------- | |
+ * | | [ ] Allocate main memory. | | |
+ * | | [ ] Allocate CCS memory. | | |
+ * | | [ ] Update Main memory & | | |
+ * [ ]<------------------------------[ ] CCS pages PPGTT + BB | | |
+ * | [ ]<------------------[ ] cmds to save & restore.| | |
+ * | | [ ]<------------------------ | |
+ * | | | | |
+ * | | | | |
+ * | | | | |
+ * : : : : :
+ * ---------------------------- VF Paused -------------------------------------
+ * | | | | |
+ * | | | | |
+ * | | | |Schedule |
+ * | | | |CCS Save |
+ * | | | | LRCA |
+ * | | | [ ]------>[ ]
+ * | | | | |
+ * | | | | |
+ * | | | |CCS save |
+ * | | | |completed|
+ * | | | [ ]<------[ ]
+ * | | | | |
+ * : : : : :
+ * ---------------------------- VM Migrated -----------------------------------
+ * | | | | |
+ * | | | | |
+ * : : : : :
+ * ---------------------------- VF Resumed ------------------------------------
+ * | | | | |
+ * | | | | |
+ * | | [ ]-------------- | |
+ * | | [ ] Fix up GGTT | | |
+ * | | [ ]<------------- | |
+ * | | | | |
+ * | | | | |
+ * | | | Notify VF_RESFIX_DONE | |
+ * | | [ ]--------------------------->[ ] |
+ * | | | | |
+ * | | | |Schedule |
+ * | | | |CCS |
+ * | | | |Restore |
+ * | | | |LRCA |
+ * | | | [ ]------>[ ]
+ * | | | | |
+ * | | | | |
+ * | | | |CCS |
+ * | | | |restore |
+ * | | | |completed|
+ * | | | [ ]<------[ ]
+ * | | | | |
+ * | | | | |
+ * | | | VF_RESFIX_DONE complete | |
+ * | | | notification | |
+ * | | [ ]<---------------------------[ ] |
+ * | | | | |
+ * | | | | |
+ * : : : : :
+ * ------------------------- Continue VM restore ------------------------------
+ */
+
+static u64 get_ccs_bb_pool_size(struct xe_device *xe)
+{
+ u64 sys_mem_size, ccs_mem_size, ptes, bb_pool_size;
+ struct sysinfo si;
+
+ si_meminfo(&si);
+ sys_mem_size = si.totalram * si.mem_unit;
+ ccs_mem_size = sys_mem_size / NUM_BYTES_PER_CCS_BYTE(xe);
+ ptes = DIV_ROUND_UP(sys_mem_size + ccs_mem_size, XE_PAGE_SIZE);
+
+ /**
+ * We need below BB size to hold PTE mappings and some DWs for copy
+ * command. In reality, we need space for many copy commands. So, let
+ * us allocate double the calculated size which is enough to holds GPU
+ * instructions for the whole region.
+ */
+ bb_pool_size = ptes * sizeof(u32);
+
+ return round_up(bb_pool_size * 2, SZ_1M);
+}
+
+static int alloc_bb_pool(struct xe_tile *tile, struct xe_tile_vf_ccs *ctx)
+{
+ struct xe_device *xe = tile_to_xe(tile);
+ struct xe_sa_manager *sa_manager;
+ u64 bb_pool_size;
+ int offset, err;
+
+ bb_pool_size = get_ccs_bb_pool_size(xe);
+ xe_sriov_info(xe, "Allocating %s CCS BB pool size = %lldMB\n",
+ ctx->ctx_id ? "Restore" : "Save", bb_pool_size / SZ_1M);
+
+ sa_manager = xe_sa_bo_manager_init(tile, bb_pool_size, SZ_16);
+
+ if (IS_ERR(sa_manager)) {
+ xe_sriov_err(xe, "Suballocator init failed with error: %pe\n",
+ sa_manager);
+ err = PTR_ERR(sa_manager);
+ return err;
+ }
+
+ offset = 0;
+ xe_map_memset(xe, &sa_manager->bo->vmap, offset, MI_NOOP,
+ bb_pool_size);
+
+ offset = bb_pool_size - sizeof(u32);
+ xe_map_wr(xe, &sa_manager->bo->vmap, offset, u32, MI_BATCH_BUFFER_END);
+
+ ctx->mem.ccs_bb_pool = sa_manager;
+
+ return 0;
+}
+
+/**
+ * xe_sriov_vf_ccs_init - Setup LRCA for save & restore.
+ * @xe: the &xe_device to start recovery on
+ *
+ * This function shall be called only by VF. It initializes
+ * LRCA and suballocator needed for CCS save & restore.
+ *
+ * Return: 0 on success. Negative error code on failure.
+ */
+int xe_sriov_vf_ccs_init(struct xe_device *xe)
+{
+ struct xe_tile *tile = xe_device_get_root_tile(xe);
+ enum xe_sriov_vf_ccs_rw_ctxs ctx_id;
+ struct xe_migrate *migrate;
+ struct xe_tile_vf_ccs *ctx;
+ int err;
+
+ xe_assert(xe, IS_SRIOV_VF(xe));
+ xe_assert(xe, !IS_DGFX(xe));
+ xe_assert(xe, xe_device_has_flat_ccs(xe));
+
+ for_each_ccs_rw_ctx(ctx_id) {
+ ctx = &tile->sriov.vf.ccs[ctx_id];
+ ctx->ctx_id = ctx_id;
+
+ migrate = xe_migrate_init(tile);
+ if (IS_ERR(migrate)) {
+ err = PTR_ERR(migrate);
+ goto err_ret;
+ }
+ ctx->migrate = migrate;
+
+ err = alloc_bb_pool(tile, ctx);
+ if (err)
+ goto err_ret;
+ }
+
+ xe->sriov.vf.ccs.initialized = 1;
+
+ return 0;
+
+err_ret:
+ return err;
+}
diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.h b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.h
new file mode 100644
index 000000000000..5df9ba028d14
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef _XE_SRIOV_VF_CCS_H_
+#define _XE_SRIOV_VF_CCS_H_
+
+struct xe_device;
+
+int xe_sriov_vf_ccs_init(struct xe_device *xe);
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h b/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h
new file mode 100644
index 000000000000..6dc279d206ec
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef _XE_SRIOV_VF_CCS_TYPES_H_
+#define _XE_SRIOV_VF_CCS_TYPES_H_
+
+#define for_each_ccs_rw_ctx(id__) \
+ for ((id__) = 0; (id__) < XE_SRIOV_VF_CCS_CTX_COUNT; (id__)++)
+
+#define IS_VF_CCS_READY(xe) ({ \
+ struct xe_device *___xe = (xe); \
+ xe_assert(___xe, IS_SRIOV_VF(___xe)); \
+ ___xe->sriov.vf.ccs.initialized; \
+ })
+
+#define IS_VF_CCS_INIT_NEEDED(xe) ({\
+ struct xe_device *___xe = (xe); \
+ IS_SRIOV_VF(___xe) && !IS_DGFX(___xe) && \
+ xe_device_has_flat_ccs(___xe) && GRAPHICS_VER(___xe) >= 20; \
+ })
+
+enum xe_sriov_vf_ccs_rw_ctxs {
+ XE_SRIOV_VF_CCS_READ_CTX,
+ XE_SRIOV_VF_CCS_WRITE_CTX,
+ XE_SRIOV_VF_CCS_CTX_COUNT
+};
+
+struct xe_migrate;
+struct xe_sa_manager;
+
+struct xe_tile_vf_ccs {
+ /** @id: Id to which context it belongs to */
+ enum xe_sriov_vf_ccs_rw_ctxs ctx_id;
+ /** @migrate: Migration helper for save/restore of CCS data */
+ struct xe_migrate *migrate;
+
+ struct {
+ /** @ccs_rw_bb_pool: Pool from which batch buffers are allocated. */
+ struct xe_sa_manager *ccs_bb_pool;
+ } mem;
+};
+
+#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v9 2/3] drm/xe/vf: Attach and detach CCS copy commands with BO
2025-06-24 10:00 [PATCH v9 0/3] CCS save restore for IGPU Satyanarayana K V P
2025-06-24 10:00 ` [PATCH v9 1/3] drm/xe/vf: Create contexts for CCS read write Satyanarayana K V P
@ 2025-06-24 10:00 ` Satyanarayana K V P
2025-06-24 16:02 ` Matthew Brost
2025-06-24 10:00 ` [PATCH v9 3/3] drm/xe/vf: Register CCS read/write contexts with Guc Satyanarayana K V P
` (4 subsequent siblings)
6 siblings, 1 reply; 13+ messages in thread
From: Satyanarayana K V P @ 2025-06-24 10:00 UTC (permalink / raw)
To: intel-xe
Cc: Satyanarayana K V P, Michal Wajdeczko, Matthew Brost,
Matthew Auld, Michał Winiarski, Tomasz Lis
Attach CCS read/write copy commands to BO for old and new mem types as
NULL -> tt or system -> tt.
Detach the CCS read/write copy commands from BO while deleting ttm bo
from xe_ttm_bo_delete_mem_notify().
Signed-off-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: Michał Winiarski <michal.winiarski@intel.com>
---
Cc: Tomasz Lis <tomasz.lis@intel.com>
V8 -> V9:
- Removed MI_INVALIDATE_TLB after emitting PTEs (Matthew Brost).
- Fixed review comments (Matthew Brost)
V7 -> V8:
- Removed xe_bb_ccs_realloc() and created a single BB by calculating the
BB size first and then emitting the commands. (Matthew Brost)
- Added xe_assert() if BB is not NULL in xe_sriov_vf_ccs_attach_bo().
V6 -> V7:
- Created xe_bb_ccs_realloc() to create a single BB instead of maintaining
a list. (Matthew Brost)
V5 -> V6:
- Removed dead code from xe_migrate_ccs_rw_copy() function. (Matthew Brost)
V4 -> V5:
- Create a list of BBs for the given BO and fixed memory leak while
detaching BOs. (Matthew Brost).
- Fixed review comments (Matthew Brost & Matthew Auld).
- Yet to cleanup xe_migrate_ccs_rw_copy() function.
V3 -> V4:
- Fixed issues reported by patchworks.
V2 -> V3:
- Attach and detach functions check for IS_VF_CCS_READY().
V1 -> V2:
- Fixed review comments.
---
drivers/gpu/drm/xe/xe_bb.c | 35 ++++++
drivers/gpu/drm/xe/xe_bb.h | 3 +
drivers/gpu/drm/xe/xe_bo.c | 23 ++++
drivers/gpu/drm/xe/xe_bo_types.h | 3 +
drivers/gpu/drm/xe/xe_migrate.c | 129 +++++++++++++++++++++
drivers/gpu/drm/xe/xe_migrate.h | 6 +
drivers/gpu/drm/xe/xe_sriov_vf_ccs.c | 67 +++++++++++
drivers/gpu/drm/xe/xe_sriov_vf_ccs.h | 3 +
drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h | 8 ++
9 files changed, 277 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_bb.c b/drivers/gpu/drm/xe/xe_bb.c
index 9570672fce33..533352dc892f 100644
--- a/drivers/gpu/drm/xe/xe_bb.c
+++ b/drivers/gpu/drm/xe/xe_bb.c
@@ -60,6 +60,41 @@ struct xe_bb *xe_bb_new(struct xe_gt *gt, u32 dwords, bool usm)
return ERR_PTR(err);
}
+struct xe_bb *xe_bb_ccs_new(struct xe_gt *gt, u32 dwords,
+ enum xe_sriov_vf_ccs_rw_ctxs ctx_id)
+{
+ struct xe_bb *bb = kmalloc(sizeof(*bb), GFP_KERNEL);
+ struct xe_tile *tile = gt_to_tile(gt);
+ struct xe_sa_manager *bb_pool;
+ int err;
+
+ if (!bb)
+ return ERR_PTR(-ENOMEM);
+ /*
+ * We need to allocate space for the requested number of dwords &
+ * one additional MI_BATCH_BUFFER_END dword. Since the whole SA
+ * is submitted to HW, we need to make sure that the last instruction
+ * is not over written when the last chunk of SA is allocated for BB.
+ * So, this extra DW acts as a guard here.
+ */
+
+ bb_pool = tile->sriov.vf.ccs[ctx_id].mem.ccs_bb_pool;
+ bb->bo = xe_sa_bo_new(bb_pool, 4 * (dwords + 1));
+
+ if (IS_ERR(bb->bo)) {
+ err = PTR_ERR(bb->bo);
+ goto err;
+ }
+
+ bb->cs = xe_sa_bo_cpu_addr(bb->bo);
+ bb->len = 0;
+
+ return bb;
+err:
+ kfree(bb);
+ return ERR_PTR(err);
+}
+
static struct xe_sched_job *
__xe_bb_create_job(struct xe_exec_queue *q, struct xe_bb *bb, u64 *addr)
{
diff --git a/drivers/gpu/drm/xe/xe_bb.h b/drivers/gpu/drm/xe/xe_bb.h
index fafacd73dcc3..32c9c4c5d2be 100644
--- a/drivers/gpu/drm/xe/xe_bb.h
+++ b/drivers/gpu/drm/xe/xe_bb.h
@@ -13,8 +13,11 @@ struct dma_fence;
struct xe_gt;
struct xe_exec_queue;
struct xe_sched_job;
+enum xe_sriov_vf_ccs_rw_ctxs;
struct xe_bb *xe_bb_new(struct xe_gt *gt, u32 size, bool usm);
+struct xe_bb *xe_bb_ccs_new(struct xe_gt *gt, u32 dwords,
+ enum xe_sriov_vf_ccs_rw_ctxs ctx_id);
struct xe_sched_job *xe_bb_create_job(struct xe_exec_queue *q,
struct xe_bb *bb);
struct xe_sched_job *xe_bb_create_migration_job(struct xe_exec_queue *q,
diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
index 4e39188a021a..beaf8544bf08 100644
--- a/drivers/gpu/drm/xe/xe_bo.c
+++ b/drivers/gpu/drm/xe/xe_bo.c
@@ -31,6 +31,7 @@
#include "xe_pxp.h"
#include "xe_res_cursor.h"
#include "xe_shrinker.h"
+#include "xe_sriov_vf_ccs.h"
#include "xe_trace_bo.h"
#include "xe_ttm_stolen_mgr.h"
#include "xe_vm.h"
@@ -947,6 +948,20 @@ static int xe_bo_move(struct ttm_buffer_object *ttm_bo, bool evict,
dma_fence_put(fence);
xe_pm_runtime_put(xe);
+ /*
+ * CCS meta data is migrated from TT -> SMEM. So, let us detach the
+ * BBs from BO as it is no longer needed.
+ */
+ if (IS_VF_CCS_BB_VALID(xe, bo) && old_mem_type == XE_PL_TT &&
+ new_mem->mem_type == XE_PL_SYSTEM)
+ xe_sriov_vf_ccs_detach_bo(bo);
+
+ if (IS_SRIOV_VF(xe) &&
+ ((move_lacks_source && new_mem->mem_type == XE_PL_TT) ||
+ (old_mem_type == XE_PL_SYSTEM && new_mem->mem_type == XE_PL_TT)) &&
+ handle_system_ccs)
+ ret = xe_sriov_vf_ccs_attach_bo(bo);
+
out:
if ((!ttm_bo->resource || ttm_bo->resource->mem_type == XE_PL_SYSTEM) &&
ttm_bo->ttm) {
@@ -957,6 +972,9 @@ static int xe_bo_move(struct ttm_buffer_object *ttm_bo, bool evict,
if (timeout < 0)
ret = timeout;
+ if (IS_VF_CCS_BB_VALID(xe, bo))
+ xe_sriov_vf_ccs_detach_bo(bo);
+
xe_tt_unmap_sg(xe, ttm_bo->ttm);
}
@@ -1483,9 +1501,14 @@ static void xe_ttm_bo_release_notify(struct ttm_buffer_object *ttm_bo)
static void xe_ttm_bo_delete_mem_notify(struct ttm_buffer_object *ttm_bo)
{
+ struct xe_bo *bo = ttm_to_xe_bo(ttm_bo);
+
if (!xe_bo_is_xe_bo(ttm_bo))
return;
+ if (IS_VF_CCS_BB_VALID(ttm_to_xe_device(ttm_bo->bdev), bo))
+ xe_sriov_vf_ccs_detach_bo(bo);
+
/*
* Object is idle and about to be destroyed. Release the
* dma-buf attachment.
diff --git a/drivers/gpu/drm/xe/xe_bo_types.h b/drivers/gpu/drm/xe/xe_bo_types.h
index eb5e83c5f233..642e519fcfd1 100644
--- a/drivers/gpu/drm/xe/xe_bo_types.h
+++ b/drivers/gpu/drm/xe/xe_bo_types.h
@@ -78,6 +78,9 @@ struct xe_bo {
/** @ccs_cleared */
bool ccs_cleared;
+ /** @bb_ccs_rw: BB instructions of CCS read/write. Valid only for VF */
+ struct xe_bb *bb_ccs[XE_SRIOV_VF_CCS_CTX_COUNT];
+
/**
* @cpu_caching: CPU caching mode. Currently only used for userspace
* objects. Exceptions are system memory on DGFX, which is always
diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
index 8f8e9fdfb2a8..72f342924ad2 100644
--- a/drivers/gpu/drm/xe/xe_migrate.c
+++ b/drivers/gpu/drm/xe/xe_migrate.c
@@ -940,6 +940,135 @@ struct dma_fence *xe_migrate_copy(struct xe_migrate *m,
return fence;
}
+/**
+ * xe_migrate_ccs_rw_copy() - Copy content of TTM resources.
+ * @m: The migration context.
+ * @src_bo: The buffer object @src is currently bound to.
+ * @read_write : Creates BB commands for CCS read/write.
+ *
+ * Creates batch buffer instructions to copy CCS metadata from CCS pool to
+ * memory and vice versa.
+ *
+ * This function should only be called for IGPU.
+ *
+ * Return: 0 if successful, negative error code on failure.
+ */
+int xe_migrate_ccs_rw_copy(struct xe_migrate *m,
+ struct xe_bo *src_bo,
+ enum xe_sriov_vf_ccs_rw_ctxs read_write)
+
+{
+ bool src_is_pltt = read_write == XE_SRIOV_VF_CCS_WRITE_CTX;
+ bool dst_is_pltt = read_write == XE_SRIOV_VF_CCS_READ_CTX;
+ struct ttm_resource *src = src_bo->ttm.resource;
+ struct xe_gt *gt = m->tile->primary_gt;
+ u32 batch_size, batch_size_allocated;
+ struct xe_device *xe = gt_to_xe(gt);
+ struct xe_res_cursor src_it, ccs_it;
+ u64 size = src_bo->size;
+ struct xe_bb *bb = NULL;
+ u64 src_L0, src_L0_ofs;
+ u32 src_L0_pt;
+ int err;
+
+ xe_res_first_sg(xe_bo_sg(src_bo), 0, size, &src_it);
+
+ xe_res_first_sg(xe_bo_sg(src_bo), xe_bo_ccs_pages_start(src_bo),
+ PAGE_ALIGN(xe_device_ccs_bytes(xe, size)),
+ &ccs_it);
+
+ /* Calculate Batch buffer size */
+ batch_size = 0;
+ while (size) {
+ batch_size += 6; /* Flush + 2 NOP */
+ u64 ccs_ofs, ccs_size;
+ u32 ccs_pt;
+
+ u32 avail_pts = max_mem_transfer_per_pass(xe) / LEVEL0_PAGE_TABLE_ENCODE_SIZE;
+
+ src_L0 = min_t(u64, max_mem_transfer_per_pass(xe), size);
+
+ batch_size += pte_update_size(m, false, src, &src_it, &src_L0,
+ &src_L0_ofs, &src_L0_pt, 0, 0,
+ avail_pts);
+
+ ccs_size = xe_device_ccs_bytes(xe, src_L0);
+ batch_size += pte_update_size(m, 0, NULL, &ccs_it, &ccs_size, &ccs_ofs,
+ &ccs_pt, 0, avail_pts, avail_pts);
+ xe_assert(xe, IS_ALIGNED(ccs_it.start, PAGE_SIZE));
+
+ /* Add copy commands size here */
+ batch_size += EMIT_COPY_CCS_DW;
+
+ size -= src_L0;
+ }
+
+ bb = xe_bb_ccs_new(gt, batch_size, read_write);
+ if (IS_ERR(bb)) {
+ drm_err(&xe->drm, "BB allocation failed.\n");
+ err = PTR_ERR(bb);
+ goto err_ret;
+ }
+
+ batch_size_allocated = batch_size;
+ size = src_bo->size;
+ batch_size = 0;
+
+ /*
+ * Emit PTE and copy commands here.
+ * The CCS copy command can only support limited size. If the size to be
+ * copied is more than the limit, divide copy into chunks. So, calculate
+ * sizes here again before copy command is emitted.
+ */
+ while (size) {
+ batch_size += 6; /* Flush + 2 NOP */
+ u32 flush_flags = 0;
+ u64 ccs_ofs, ccs_size;
+ u32 ccs_pt;
+
+ u32 avail_pts = max_mem_transfer_per_pass(xe) / LEVEL0_PAGE_TABLE_ENCODE_SIZE;
+
+ src_L0 = xe_migrate_res_sizes(m, &src_it);
+
+ batch_size += pte_update_size(m, false, src, &src_it, &src_L0,
+ &src_L0_ofs, &src_L0_pt, 0, 0,
+ avail_pts);
+
+ ccs_size = xe_device_ccs_bytes(xe, src_L0);
+ batch_size += pte_update_size(m, 0, NULL, &ccs_it, &ccs_size, &ccs_ofs,
+ &ccs_pt, 0, avail_pts, avail_pts);
+ xe_assert(xe, IS_ALIGNED(ccs_it.start, PAGE_SIZE));
+ batch_size += EMIT_COPY_CCS_DW;
+
+ emit_pte(m, bb, src_L0_pt, false, true, &src_it, src_L0, src);
+
+ emit_pte(m, bb, ccs_pt, false, false, &ccs_it, ccs_size, src);
+
+ bb->cs[bb->len++] = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_IMM_DW;
+ bb->cs[bb->len++] = MI_NOOP;
+ bb->cs[bb->len++] = MI_NOOP;
+
+ flush_flags = xe_migrate_ccs_copy(m, bb, src_L0_ofs, src_is_pltt,
+ src_L0_ofs, dst_is_pltt,
+ src_L0, ccs_ofs, true);
+
+ bb->cs[bb->len++] = MI_FLUSH_DW | MI_INVALIDATE_TLB | MI_FLUSH_DW_OP_STOREDW |
+ MI_FLUSH_IMM_DW | flush_flags;
+ bb->cs[bb->len++] = MI_NOOP;
+ bb->cs[bb->len++] = MI_NOOP;
+
+ size -= src_L0;
+ }
+
+ xe_assert(xe, (batch_size_allocated == bb->len));
+ src_bo->bb_ccs[read_write] = bb;
+
+ return 0;
+
+err_ret:
+ return err;
+}
+
static void emit_clear_link_copy(struct xe_gt *gt, struct xe_bb *bb, u64 src_ofs,
u32 size, u32 pitch)
{
diff --git a/drivers/gpu/drm/xe/xe_migrate.h b/drivers/gpu/drm/xe/xe_migrate.h
index fb9839c1bae0..96b0449e7edb 100644
--- a/drivers/gpu/drm/xe/xe_migrate.h
+++ b/drivers/gpu/drm/xe/xe_migrate.h
@@ -24,6 +24,8 @@ struct xe_vm;
struct xe_vm_pgtable_update;
struct xe_vma;
+enum xe_sriov_vf_ccs_rw_ctxs;
+
/**
* struct xe_migrate_pt_update_ops - Callbacks for the
* xe_migrate_update_pgtables() function.
@@ -112,6 +114,10 @@ struct dma_fence *xe_migrate_copy(struct xe_migrate *m,
struct ttm_resource *dst,
bool copy_only_ccs);
+int xe_migrate_ccs_rw_copy(struct xe_migrate *m,
+ struct xe_bo *src_bo,
+ enum xe_sriov_vf_ccs_rw_ctxs read_write);
+
int xe_migrate_access_memory(struct xe_migrate *m, struct xe_bo *bo,
unsigned long offset, void *buf, int len,
int write);
diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
index 9000d618978d..7fde8aab3e20 100644
--- a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
+++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
@@ -5,6 +5,7 @@
#include "instructions/xe_mi_commands.h"
#include "instructions/xe_gpu_commands.h"
+#include "xe_bb.h"
#include "xe_bo.h"
#include "xe_device.h"
#include "xe_migrate.h"
@@ -206,3 +207,69 @@ int xe_sriov_vf_ccs_init(struct xe_device *xe)
err_ret:
return err;
}
+
+/**
+ * xe_sriov_vf_ccs_attach_bo - Insert CCS read write commands in the BO.
+ * @bo: the &buffer object to which batch buffer commands will be added.
+ *
+ * This function shall be called only by VF. It inserts the PTEs and copy
+ * command instructions in the BO by calling xe_migrate_ccs_rw_copy()
+ * function.
+ *
+ * Returns: 0 if successful, negative error code on failure.
+ */
+int xe_sriov_vf_ccs_attach_bo(struct xe_bo *bo)
+{
+ struct xe_device *xe = xe_bo_device(bo);
+ enum xe_sriov_vf_ccs_rw_ctxs ctx_id;
+ struct xe_migrate *migrate;
+ struct xe_tile *tile;
+ struct xe_bb *bb;
+ int err = 0;
+
+ if (!IS_VF_CCS_READY(xe))
+ return 0;
+
+ tile = xe_device_get_root_tile(xe);
+
+ for_each_ccs_rw_ctx(ctx_id) {
+ bb = bo->bb_ccs[ctx_id];
+ /* bb should be NULL here. Assert if not NULL */
+ xe_assert(xe, !bb);
+
+ migrate = tile->sriov.vf.ccs[ctx_id].migrate;
+ err = xe_migrate_ccs_rw_copy(migrate, bo, ctx_id);
+ }
+ return err;
+}
+
+/**
+ * xe_sriov_vf_ccs_detach_bo - Remove CCS read write commands from the BO.
+ * @bo: the &buffer object from which batch buffer commands will be removed.
+ *
+ * This function shall be called only by VF. It removes the PTEs and copy
+ * command instructions from the BO. Make sure to update the BB with MI_NOOP
+ * before freeing.
+ *
+ * Returns: 0 if successful.
+ */
+int xe_sriov_vf_ccs_detach_bo(struct xe_bo *bo)
+{
+ struct xe_device *xe = xe_bo_device(bo);
+ enum xe_sriov_vf_ccs_rw_ctxs ctx_id;
+ struct xe_bb *bb;
+
+ if (!IS_VF_CCS_READY(xe))
+ return 0;
+
+ for_each_ccs_rw_ctx(ctx_id) {
+ bb = bo->bb_ccs[ctx_id];
+ if (!bb)
+ continue;
+
+ memset(bb->cs, MI_NOOP, bb->len * sizeof(u32));
+ xe_bb_free(bb, NULL);
+ bo->bb_ccs[ctx_id] = NULL;
+ }
+ return 0;
+}
diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.h b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.h
index 5df9ba028d14..5d5e4bd25904 100644
--- a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.h
+++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.h
@@ -7,7 +7,10 @@
#define _XE_SRIOV_VF_CCS_H_
struct xe_device;
+struct xe_bo;
int xe_sriov_vf_ccs_init(struct xe_device *xe);
+int xe_sriov_vf_ccs_attach_bo(struct xe_bo *bo);
+int xe_sriov_vf_ccs_detach_bo(struct xe_bo *bo);
#endif
diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h b/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h
index 6dc279d206ec..e240f3fd18af 100644
--- a/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h
+++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h
@@ -27,6 +27,14 @@ enum xe_sriov_vf_ccs_rw_ctxs {
XE_SRIOV_VF_CCS_CTX_COUNT
};
+#define IS_VF_CCS_BB_VALID(xe, bo) ({ \
+ struct xe_device *___xe = (xe); \
+ struct xe_bo *___bo = (bo); \
+ IS_SRIOV_VF(___xe) && \
+ ___bo->bb_ccs[XE_SRIOV_VF_CCS_READ_CTX] && \
+ ___bo->bb_ccs[XE_SRIOV_VF_CCS_WRITE_CTX]; \
+ })
+
struct xe_migrate;
struct xe_sa_manager;
--
2.43.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v9 3/3] drm/xe/vf: Register CCS read/write contexts with Guc
2025-06-24 10:00 [PATCH v9 0/3] CCS save restore for IGPU Satyanarayana K V P
2025-06-24 10:00 ` [PATCH v9 1/3] drm/xe/vf: Create contexts for CCS read write Satyanarayana K V P
2025-06-24 10:00 ` [PATCH v9 2/3] drm/xe/vf: Attach and detach CCS copy commands with BO Satyanarayana K V P
@ 2025-06-24 10:00 ` Satyanarayana K V P
2025-06-24 16:07 ` Matthew Brost
2025-06-24 15:08 ` ✗ CI.checkpatch: warning for CCS save restore for IGPU (rev9) Patchwork
` (3 subsequent siblings)
6 siblings, 1 reply; 13+ messages in thread
From: Satyanarayana K V P @ 2025-06-24 10:00 UTC (permalink / raw)
To: intel-xe
Cc: Satyanarayana K V P, Michal Wajdeczko, Matthew Brost,
Maarten Lankhorst, Michał Winiarski, Tomasz Lis,
Matthew Auld
Register read write contexts with newly added flags with GUC and
enable the context immediately after registration.
Re-register the context with Guc when resuming from runtime suspend as
soft reset is applied to Guc during xe_pm_runtime_resume().
Make Ring head=tail while unbinding device to avoid issues with VF pause
after device is unbinded.
Signed-off-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
Cc: Michał Winiarski <michal.winiarski@intel.com>
Cc: Tomasz Lis <tomasz.lis@intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
V8 -> V9:
- Fixed review comments (Matthew Brost).
V7 -> V8:
-None.
V6 -> V7:
- Fixed review comments (Matthew Brost).
- Replaced xe_tile_migrate_exec_queue() with xe_migrate_exec_queue() as per
review comments (Matthew Brost).
V5 -> V6:
- None
V4 -> V5:
- Fixed review comments (Matthew Brost).
V3 -> V4:
- Fixed issues reported by patchworks.
V2 -> V3:
- Made xe_migrate structure private as per review comments.
- Created new xe_migrate functions to get lrc and exec_queue.
V1 -> V2:
- Fixed review comments.
---
drivers/gpu/drm/xe/xe_guc_fwif.h | 5 ++
drivers/gpu/drm/xe/xe_guc_submit.c | 34 ++++++++++-
drivers/gpu/drm/xe/xe_guc_submit.h | 1 +
drivers/gpu/drm/xe/xe_migrate.c | 35 +++++++----
drivers/gpu/drm/xe/xe_migrate.h | 4 +-
drivers/gpu/drm/xe/xe_pm.c | 4 ++
drivers/gpu/drm/xe/xe_sriov_vf_ccs.c | 91 ++++++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_sriov_vf_ccs.h | 1 +
drivers/gpu/drm/xe/xe_vm.c | 6 +-
9 files changed, 161 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h
index 6f57578b07cb..ca9f999d38d1 100644
--- a/drivers/gpu/drm/xe/xe_guc_fwif.h
+++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
@@ -45,6 +45,11 @@
#define GUC_MAX_ENGINE_CLASSES 16
#define GUC_MAX_INSTANCES_PER_CLASS 32
+#define GUC_CONTEXT_NORMAL 0
+#define GUC_CONTEXT_COMPRESSION_SAVE 1
+#define GUC_CONTEXT_COMPRESSION_RESTORE 2
+#define GUC_CONTEXT_COUNT (GUC_CONTEXT_COMPRESSION_RESTORE + 1)
+
/* Helper for context registration H2G */
struct guc_ctxt_registration_info {
u32 flags;
diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
index df7a5a4eec74..f17a63ea06e9 100644
--- a/drivers/gpu/drm/xe/xe_guc_submit.c
+++ b/drivers/gpu/drm/xe/xe_guc_submit.c
@@ -542,7 +542,7 @@ static void __register_exec_queue(struct xe_guc *guc,
xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action), 0, 0);
}
-static void register_exec_queue(struct xe_exec_queue *q)
+static void register_exec_queue(struct xe_exec_queue *q, int ctx_type)
{
struct xe_guc *guc = exec_queue_to_guc(q);
struct xe_device *xe = guc_to_xe(guc);
@@ -550,6 +550,7 @@ static void register_exec_queue(struct xe_exec_queue *q)
struct guc_ctxt_registration_info info;
xe_gt_assert(guc_to_gt(guc), !exec_queue_registered(q));
+ xe_gt_assert(guc_to_gt(guc), ctx_type < GUC_CONTEXT_COUNT);
memset(&info, 0, sizeof(info));
info.context_idx = q->guc->id;
@@ -559,6 +560,9 @@ static void register_exec_queue(struct xe_exec_queue *q)
info.hwlrca_hi = upper_32_bits(xe_lrc_descriptor(lrc));
info.flags = CONTEXT_REGISTRATION_FLAG_KMD;
+ if (ctx_type != GUC_CONTEXT_NORMAL)
+ info.flags |= BIT(ctx_type);
+
if (xe_exec_queue_is_parallel(q)) {
u64 ggtt_addr = xe_lrc_parallel_ggtt_addr(lrc);
struct iosys_map map = xe_lrc_parallel_map(lrc);
@@ -761,7 +765,7 @@ guc_exec_queue_run_job(struct drm_sched_job *drm_job)
if (!exec_queue_killed_or_banned_or_wedged(q) && !xe_sched_job_is_error(job)) {
if (!exec_queue_registered(q))
- register_exec_queue(q);
+ register_exec_queue(q, GUC_CONTEXT_NORMAL);
if (!lr) /* LR jobs are emitted in the exec IOCTL */
q->ring_ops->emit_job(job);
submit_exec_queue(q);
@@ -2366,6 +2370,32 @@ static void guc_exec_queue_print(struct xe_exec_queue *q, struct drm_printer *p)
xe_guc_exec_queue_snapshot_free(snapshot);
}
+/**
+ * xe_guc_register_exec_queue - Register exec queue for a given context type.
+ * @q - Execution queue
+ * @ctx_type - Type of the context
+ *
+ * This function registers the execution queue with the guc. Special context
+ * types like GUC_CONTEXT_COMPRESSION_SAVE and GUC_CONTEXT_COMPRESSION_RESTORE
+ * are only applicable for IGPU and in the VF.
+ * Submits the execution queue to GUC after registering it.
+ *
+ * Returns - None.
+ */
+void xe_guc_register_exec_queue(struct xe_exec_queue *q, int ctx_type)
+{
+ struct xe_guc *guc = exec_queue_to_guc(q);
+ struct xe_device *xe = guc_to_xe(guc);
+
+ xe_assert(xe, IS_SRIOV_VF(xe));
+ xe_assert(xe, !IS_DGFX(xe));
+ xe_assert(xe, (ctx_type > GUC_CONTEXT_NORMAL &&
+ ctx_type < GUC_CONTEXT_COUNT));
+
+ register_exec_queue(q, ctx_type);
+ enable_scheduling(q);
+}
+
/**
* xe_guc_submit_print - GuC Submit Print.
* @guc: GuC.
diff --git a/drivers/gpu/drm/xe/xe_guc_submit.h b/drivers/gpu/drm/xe/xe_guc_submit.h
index 9b71a986c6ca..8f64e799283b 100644
--- a/drivers/gpu/drm/xe/xe_guc_submit.h
+++ b/drivers/gpu/drm/xe/xe_guc_submit.h
@@ -39,5 +39,6 @@ xe_guc_exec_queue_snapshot_print(struct xe_guc_submit_exec_queue_snapshot *snaps
void
xe_guc_exec_queue_snapshot_free(struct xe_guc_submit_exec_queue_snapshot *snapshot);
void xe_guc_submit_print(struct xe_guc *guc, struct drm_printer *p);
+void xe_guc_register_exec_queue(struct xe_exec_queue *q, int ctx_type);
#endif
diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
index 72f342924ad2..277221f005f7 100644
--- a/drivers/gpu/drm/xe/xe_migrate.c
+++ b/drivers/gpu/drm/xe/xe_migrate.c
@@ -84,19 +84,6 @@ struct xe_migrate {
*/
#define MAX_PTE_PER_SDI 0x1FE
-/**
- * xe_tile_migrate_exec_queue() - Get this tile's migrate exec queue.
- * @tile: The tile.
- *
- * Returns the default migrate exec queue of this tile.
- *
- * Return: The default migrate exec queue
- */
-struct xe_exec_queue *xe_tile_migrate_exec_queue(struct xe_tile *tile)
-{
- return tile->migrate->q;
-}
-
static void xe_migrate_fini(void *arg)
{
struct xe_migrate *m = arg;
@@ -1069,6 +1056,28 @@ int xe_migrate_ccs_rw_copy(struct xe_migrate *m,
return err;
}
+/**
+ * xe_get_migrate_lrc() - Get the LRC from migrate context.
+ * @migrate: Migrate context.
+ *
+ * Return: Pointer to LRC on success, error on failure
+ */
+struct xe_lrc *xe_migrate_lrc(struct xe_migrate *migrate)
+{
+ return migrate->q->lrc[0];
+}
+
+/**
+ * xe_get_migrate_exec_queue() - Get the execution queue from migrate context.
+ * @migrate: Migrate context.
+ *
+ * Return: Pointer to execution queue on success, error on failure
+ */
+struct xe_exec_queue *xe_migrate_exec_queue(struct xe_migrate *migrate)
+{
+ return migrate->q;
+}
+
static void emit_clear_link_copy(struct xe_gt *gt, struct xe_bb *bb, u64 src_ofs,
u32 size, u32 pitch)
{
diff --git a/drivers/gpu/drm/xe/xe_migrate.h b/drivers/gpu/drm/xe/xe_migrate.h
index 96b0449e7edb..3754d9e6150f 100644
--- a/drivers/gpu/drm/xe/xe_migrate.h
+++ b/drivers/gpu/drm/xe/xe_migrate.h
@@ -118,6 +118,8 @@ int xe_migrate_ccs_rw_copy(struct xe_migrate *m,
struct xe_bo *src_bo,
enum xe_sriov_vf_ccs_rw_ctxs read_write);
+struct xe_lrc *xe_migrate_lrc(struct xe_migrate *migrate);
+struct xe_exec_queue *xe_migrate_exec_queue(struct xe_migrate *migrate);
int xe_migrate_access_memory(struct xe_migrate *m, struct xe_bo *bo,
unsigned long offset, void *buf, int len,
int write);
@@ -138,6 +140,4 @@ xe_migrate_update_pgtables(struct xe_migrate *m,
struct xe_migrate_pt_update *pt_update);
void xe_migrate_wait(struct xe_migrate *m);
-
-struct xe_exec_queue *xe_tile_migrate_exec_queue(struct xe_tile *tile);
#endif
diff --git a/drivers/gpu/drm/xe/xe_pm.c b/drivers/gpu/drm/xe/xe_pm.c
index 26e95460af87..6c32412126d7 100644
--- a/drivers/gpu/drm/xe/xe_pm.c
+++ b/drivers/gpu/drm/xe/xe_pm.c
@@ -22,6 +22,7 @@
#include "xe_irq.h"
#include "xe_pcode.h"
#include "xe_pxp.h"
+#include "xe_sriov_vf_ccs.h"
#include "xe_trace.h"
#include "xe_wa.h"
@@ -546,6 +547,9 @@ int xe_pm_runtime_resume(struct xe_device *xe)
xe_pxp_pm_resume(xe->pxp);
+ if (IS_SRIOV_VF(xe))
+ xe_sriov_vf_ccs_register_context(xe);
+
out:
xe_rpm_lockmap_release(xe);
xe_pm_write_callback_task(xe, NULL);
diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
index 7fde8aab3e20..d2f4a2674f4d 100644
--- a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
+++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
@@ -8,6 +8,9 @@
#include "xe_bb.h"
#include "xe_bo.h"
#include "xe_device.h"
+#include "xe_exec_queue_types.h"
+#include "xe_guc_submit.h"
+#include "xe_lrc.h"
#include "xe_migrate.h"
#include "xe_sa.h"
#include "xe_sriov_printk.h"
@@ -163,6 +166,84 @@ static int alloc_bb_pool(struct xe_tile *tile, struct xe_tile_vf_ccs *ctx)
return 0;
}
+static void ccs_rw_update_ring(struct xe_tile_vf_ccs *ctx)
+{
+ struct xe_lrc *lrc = xe_migrate_lrc(ctx->migrate);
+ u32 addr = ctx->mem.ccs_bb_pool->gpu_addr;
+ u32 dw[10], i = 0;
+
+ dw[i++] = MI_ARB_ON_OFF | MI_ARB_DISABLE;
+ dw[i++] = MI_BATCH_BUFFER_START | XE_INSTR_NUM_DW(3);
+ dw[i++] = addr;
+ dw[i++] = 0;
+ dw[i++] = MI_NOOP;
+ dw[i++] = MI_NOOP;
+
+ xe_lrc_write_ring(lrc, dw, i * sizeof(u32));
+}
+
+static int register_save_restore_context(struct xe_migrate *m,
+ enum xe_sriov_vf_ccs_rw_ctxs ctx_id)
+{
+ int err = -EINVAL;
+ int ctx_type;
+
+ switch (ctx_id) {
+ case XE_SRIOV_VF_CCS_READ_CTX:
+ ctx_type = GUC_CONTEXT_COMPRESSION_SAVE;
+ break;
+ case XE_SRIOV_VF_CCS_WRITE_CTX:
+ ctx_type = GUC_CONTEXT_COMPRESSION_RESTORE;
+ break;
+ default:
+ return err;
+ }
+
+ xe_guc_register_exec_queue(xe_migrate_exec_queue(m), ctx_type);
+ return 0;
+}
+
+/**
+ * xe_sriov_vf_ccs_register_context - Register read/write contexts with guc.
+ * @xe: the &xe_device to register contexts on.
+ *
+ * This function registers read and write contexts with Guc. Re-registration
+ * is needed whenever resuming from pm runtime suspend.
+ *
+ * Return: 0 on success. Negative error code on failure.
+ */
+int xe_sriov_vf_ccs_register_context(struct xe_device *xe)
+{
+ struct xe_tile *tile = xe_device_get_root_tile(xe);
+ enum xe_sriov_vf_ccs_rw_ctxs ctx_id;
+ struct xe_tile_vf_ccs *ctx;
+ int err;
+
+ if (!IS_VF_CCS_READY(xe))
+ return 0;
+
+ for_each_ccs_rw_ctx(ctx_id) {
+ ctx = &tile->sriov.vf.ccs[ctx_id];
+ err = register_save_restore_context(ctx->migrate, ctx_id);
+ if (err)
+ return err;
+ }
+
+ return err;
+}
+
+static void xe_sriov_vf_ccs_fini(void *arg)
+{
+ struct xe_tile_vf_ccs *ctx = arg;
+ struct xe_lrc *lrc = xe_migrate_lrc(ctx->migrate);
+
+ /*
+ * Make TAIL = HEAD in the ring so that no issues are seen if Guc
+ * submits this context to HW on VF pause after unbinding device.
+ */
+ xe_lrc_set_ring_tail(lrc, xe_lrc_ring_head(lrc));
+}
+
/**
* xe_sriov_vf_ccs_init - Setup LRCA for save & restore.
* @xe: the &xe_device to start recovery on
@@ -198,6 +279,16 @@ int xe_sriov_vf_ccs_init(struct xe_device *xe)
err = alloc_bb_pool(tile, ctx);
if (err)
goto err_ret;
+
+ ccs_rw_update_ring(ctx);
+
+ err = register_save_restore_context(ctx->migrate, ctx_id);
+ if (err)
+ goto err_ret;
+
+ err = devm_add_action_or_reset(xe->drm.dev,
+ xe_sriov_vf_ccs_fini,
+ ctx);
}
xe->sriov.vf.ccs.initialized = 1;
diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.h b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.h
index 5d5e4bd25904..1f1baf685fec 100644
--- a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.h
+++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.h
@@ -12,5 +12,6 @@ struct xe_bo;
int xe_sriov_vf_ccs_init(struct xe_device *xe);
int xe_sriov_vf_ccs_attach_bo(struct xe_bo *bo);
int xe_sriov_vf_ccs_detach_bo(struct xe_bo *bo);
+int xe_sriov_vf_ccs_register_context(struct xe_device *xe);
#endif
diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
index 04d1a43b81e3..8f1a258912ea 100644
--- a/drivers/gpu/drm/xe/xe_vm.c
+++ b/drivers/gpu/drm/xe/xe_vm.c
@@ -953,7 +953,7 @@ struct dma_fence *xe_vma_rebind(struct xe_vm *vm, struct xe_vma *vma, u8 tile_ma
for_each_tile(tile, vm->xe, id) {
vops.pt_update_ops[id].wait_vm_bookkeep = true;
vops.pt_update_ops[tile->id].q =
- xe_tile_migrate_exec_queue(tile);
+ xe_migrate_exec_queue(tile->migrate);
}
err = xe_vm_ops_add_rebind(&vops, vma, tile_mask);
@@ -1043,7 +1043,7 @@ struct dma_fence *xe_vm_range_rebind(struct xe_vm *vm,
for_each_tile(tile, vm->xe, id) {
vops.pt_update_ops[id].wait_vm_bookkeep = true;
vops.pt_update_ops[tile->id].q =
- xe_tile_migrate_exec_queue(tile);
+ xe_migrate_exec_queue(tile->migrate);
}
err = xe_vm_ops_add_range_rebind(&vops, vma, range, tile_mask);
@@ -1126,7 +1126,7 @@ struct dma_fence *xe_vm_range_unbind(struct xe_vm *vm,
for_each_tile(tile, vm->xe, id) {
vops.pt_update_ops[id].wait_vm_bookkeep = true;
vops.pt_update_ops[tile->id].q =
- xe_tile_migrate_exec_queue(tile);
+ xe_migrate_exec_queue(tile->migrate);
}
err = xe_vm_ops_add_range_unbind(&vops, range);
--
2.43.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* ✗ CI.checkpatch: warning for CCS save restore for IGPU (rev9)
2025-06-24 10:00 [PATCH v9 0/3] CCS save restore for IGPU Satyanarayana K V P
` (2 preceding siblings ...)
2025-06-24 10:00 ` [PATCH v9 3/3] drm/xe/vf: Register CCS read/write contexts with Guc Satyanarayana K V P
@ 2025-06-24 15:08 ` Patchwork
2025-06-24 15:10 ` ✓ CI.KUnit: success " Patchwork
` (2 subsequent siblings)
6 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2025-06-24 15:08 UTC (permalink / raw)
To: Satyanarayana K V P; +Cc: intel-xe
== Series Details ==
Series: CCS save restore for IGPU (rev9)
URL : https://patchwork.freedesktop.org/series/149108/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
f8ff75ae1d2127635239b134695774ed4045d05b
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit acefa578b8c1c905f3a9d5368d27ea207056901d
Author: Satyanarayana K V P <satyanarayana.k.v.p@intel.com>
Date: Tue Jun 24 15:30:10 2025 +0530
drm/xe/vf: Register CCS read/write contexts with Guc
Register read write contexts with newly added flags with GUC and
enable the context immediately after registration.
Re-register the context with Guc when resuming from runtime suspend as
soft reset is applied to Guc during xe_pm_runtime_resume().
Make Ring head=tail while unbinding device to avoid issues with VF pause
after device is unbinded.
Signed-off-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
+ /mt/dim checkpatch fb5dada21e3cfa26179ca58e1d7c26cdad217201 drm-intel
6a030fb29dcc drm/xe/vf: Create contexts for CCS read write
-:198: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#198:
new file mode 100644
-:444: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'id__' - possible side-effects?
#444: FILE: drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h:9:
+#define for_each_ccs_rw_ctx(id__) \
+ for ((id__) = 0; (id__) < XE_SRIOV_VF_CCS_CTX_COUNT; (id__)++)
total: 0 errors, 1 warnings, 1 checks, 399 lines checked
c4112e013596 drm/xe/vf: Attach and detach CCS copy commands with BO
acefa578b8c1 drm/xe/vf: Register CCS read/write contexts with Guc
^ permalink raw reply [flat|nested] 13+ messages in thread
* ✓ CI.KUnit: success for CCS save restore for IGPU (rev9)
2025-06-24 10:00 [PATCH v9 0/3] CCS save restore for IGPU Satyanarayana K V P
` (3 preceding siblings ...)
2025-06-24 15:08 ` ✗ CI.checkpatch: warning for CCS save restore for IGPU (rev9) Patchwork
@ 2025-06-24 15:10 ` Patchwork
2025-06-24 15:46 ` ✓ Xe.CI.BAT: " Patchwork
2025-06-25 10:02 ` ✗ Xe.CI.Full: failure " Patchwork
6 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2025-06-24 15:10 UTC (permalink / raw)
To: Satyanarayana K V P; +Cc: intel-xe
== Series Details ==
Series: CCS save restore for IGPU (rev9)
URL : https://patchwork.freedesktop.org/series/149108/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[15:08:48] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[15:08:53] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[15:09:19] Starting KUnit Kernel (1/1)...
[15:09:19] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[15:09:20] ================== guc_buf (11 subtests) ===================
[15:09:20] [PASSED] test_smallest
[15:09:20] [PASSED] test_largest
[15:09:20] [PASSED] test_granular
[15:09:20] [PASSED] test_unique
[15:09:20] [PASSED] test_overlap
[15:09:20] [PASSED] test_reusable
[15:09:20] [PASSED] test_too_big
[15:09:20] [PASSED] test_flush
[15:09:20] [PASSED] test_lookup
[15:09:20] [PASSED] test_data
[15:09:20] [PASSED] test_class
[15:09:20] ===================== [PASSED] guc_buf =====================
[15:09:20] =================== guc_dbm (7 subtests) ===================
[15:09:20] [PASSED] test_empty
[15:09:20] [PASSED] test_default
[15:09:20] ======================== test_size ========================
[15:09:20] [PASSED] 4
[15:09:20] [PASSED] 8
[15:09:20] [PASSED] 32
[15:09:20] [PASSED] 256
[15:09:20] ==================== [PASSED] test_size ====================
[15:09:20] ======================= test_reuse ========================
[15:09:20] [PASSED] 4
[15:09:20] [PASSED] 8
[15:09:20] [PASSED] 32
[15:09:20] [PASSED] 256
[15:09:20] =================== [PASSED] test_reuse ====================
[15:09:20] =================== test_range_overlap ====================
[15:09:20] [PASSED] 4
[15:09:20] [PASSED] 8
[15:09:20] [PASSED] 32
[15:09:20] [PASSED] 256
[15:09:20] =============== [PASSED] test_range_overlap ================
[15:09:20] =================== test_range_compact ====================
[15:09:20] [PASSED] 4
[15:09:20] [PASSED] 8
[15:09:20] [PASSED] 32
[15:09:20] [PASSED] 256
[15:09:20] =============== [PASSED] test_range_compact ================
[15:09:20] ==================== test_range_spare =====================
[15:09:20] [PASSED] 4
[15:09:20] [PASSED] 8
[15:09:20] [PASSED] 32
[15:09:20] [PASSED] 256
[15:09:20] ================ [PASSED] test_range_spare =================
[15:09:20] ===================== [PASSED] guc_dbm =====================
[15:09:20] =================== guc_idm (6 subtests) ===================
[15:09:20] [PASSED] bad_init
[15:09:20] [PASSED] no_init
[15:09:20] [PASSED] init_fini
[15:09:20] [PASSED] check_used
[15:09:20] [PASSED] check_quota
[15:09:20] [PASSED] check_all
[15:09:20] ===================== [PASSED] guc_idm =====================
[15:09:20] ================== no_relay (3 subtests) ===================
[15:09:20] [PASSED] xe_drops_guc2pf_if_not_ready
[15:09:20] [PASSED] xe_drops_guc2vf_if_not_ready
[15:09:20] [PASSED] xe_rejects_send_if_not_ready
[15:09:20] ==================== [PASSED] no_relay =====================
[15:09:20] ================== pf_relay (14 subtests) ==================
[15:09:20] [PASSED] pf_rejects_guc2pf_too_short
[15:09:20] [PASSED] pf_rejects_guc2pf_too_long
[15:09:20] [PASSED] pf_rejects_guc2pf_no_payload
[15:09:20] [PASSED] pf_fails_no_payload
[15:09:20] [PASSED] pf_fails_bad_origin
[15:09:20] [PASSED] pf_fails_bad_type
[15:09:20] [PASSED] pf_txn_reports_error
[15:09:20] [PASSED] pf_txn_sends_pf2guc
[15:09:20] [PASSED] pf_sends_pf2guc
[15:09:20] [SKIPPED] pf_loopback_nop
[15:09:20] [SKIPPED] pf_loopback_echo
[15:09:20] [SKIPPED] pf_loopback_fail
[15:09:20] [SKIPPED] pf_loopback_busy
[15:09:20] [SKIPPED] pf_loopback_retry
[15:09:20] ==================== [PASSED] pf_relay =====================
[15:09:20] ================== vf_relay (3 subtests) ===================
[15:09:20] [PASSED] vf_rejects_guc2vf_too_short
[15:09:20] [PASSED] vf_rejects_guc2vf_too_long
[15:09:20] [PASSED] vf_rejects_guc2vf_no_payload
[15:09:20] ==================== [PASSED] vf_relay =====================
[15:09:20] ================= pf_service (11 subtests) =================
[15:09:20] [PASSED] pf_negotiate_any
[15:09:20] [PASSED] pf_negotiate_base_match
[15:09:20] [PASSED] pf_negotiate_base_newer
[15:09:20] [PASSED] pf_negotiate_base_next
[15:09:20] [SKIPPED] pf_negotiate_base_older
[15:09:20] [PASSED] pf_negotiate_base_prev
[15:09:20] [PASSED] pf_negotiate_latest_match
[15:09:20] [PASSED] pf_negotiate_latest_newer
[15:09:20] [PASSED] pf_negotiate_latest_next
[15:09:20] [SKIPPED] pf_negotiate_latest_older
[15:09:20] [SKIPPED] pf_negotiate_latest_prev
[15:09:20] =================== [PASSED] pf_service ====================
[15:09:20] ===================== lmtt (1 subtest) =====================
[15:09:20] ======================== test_ops =========================
[15:09:20] [PASSED] 2-level
[15:09:20] [PASSED] multi-level
[15:09:20] ==================== [PASSED] test_ops =====================
[15:09:20] ====================== [PASSED] lmtt =======================
[15:09:20] =================== xe_mocs (2 subtests) ===================
[15:09:20] ================ xe_live_mocs_kernel_kunit ================
[15:09:20] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[15:09:20] ================ xe_live_mocs_reset_kunit =================
[15:09:20] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[15:09:20] ==================== [SKIPPED] xe_mocs =====================
[15:09:20] ================= xe_migrate (2 subtests) ==================
[15:09:20] ================= xe_migrate_sanity_kunit =================
[15:09:20] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[15:09:20] ================== xe_validate_ccs_kunit ==================
[15:09:20] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[15:09:20] =================== [SKIPPED] xe_migrate ===================
[15:09:20] ================== xe_dma_buf (1 subtest) ==================
[15:09:20] ==================== xe_dma_buf_kunit =====================
[15:09:20] ================ [SKIPPED] xe_dma_buf_kunit ================
[15:09:20] =================== [SKIPPED] xe_dma_buf ===================
[15:09:20] ================= xe_bo_shrink (1 subtest) =================
[15:09:20] =================== xe_bo_shrink_kunit ====================
[15:09:20] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[15:09:20] ================== [SKIPPED] xe_bo_shrink ==================
[15:09:20] ==================== xe_bo (2 subtests) ====================
[15:09:20] ================== xe_ccs_migrate_kunit ===================
[15:09:20] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[15:09:20] ==================== xe_bo_evict_kunit ====================
[15:09:20] =============== [SKIPPED] xe_bo_evict_kunit ================
[15:09:20] ===================== [SKIPPED] xe_bo ======================
[15:09:20] ==================== args (11 subtests) ====================
[15:09:20] [PASSED] count_args_test
[15:09:20] [PASSED] call_args_example
[15:09:20] [PASSED] call_args_test
[15:09:20] [PASSED] drop_first_arg_example
[15:09:20] [PASSED] drop_first_arg_test
[15:09:20] [PASSED] first_arg_example
[15:09:20] [PASSED] first_arg_test
[15:09:20] [PASSED] last_arg_example
[15:09:20] [PASSED] last_arg_test
[15:09:20] [PASSED] pick_arg_example
[15:09:20] [PASSED] sep_comma_example
[15:09:20] ====================== [PASSED] args =======================
[15:09:20] =================== xe_pci (2 subtests) ====================
[15:09:20] ==================== check_graphics_ip ====================
[15:09:20] [PASSED] 12.70 Xe_LPG
[15:09:20] [PASSED] 12.71 Xe_LPG
[15:09:20] [PASSED] 12.74 Xe_LPG+
[15:09:20] [PASSED] 20.01 Xe2_HPG
[15:09:20] [PASSED] 20.02 Xe2_HPG
[15:09:20] [PASSED] 20.04 Xe2_LPG
[15:09:20] [PASSED] 30.00 Xe3_LPG
[15:09:20] [PASSED] 30.01 Xe3_LPG
[15:09:20] [PASSED] 30.03 Xe3_LPG
[15:09:20] ================ [PASSED] check_graphics_ip ================
[15:09:20] ===================== check_media_ip ======================
[15:09:20] [PASSED] 13.00 Xe_LPM+
[15:09:20] [PASSED] 13.01 Xe2_HPM
[15:09:20] [PASSED] 20.00 Xe2_LPM
[15:09:20] [PASSED] 30.00 Xe3_LPM
[15:09:20] [PASSED] 30.02 Xe3_LPM
stty: 'standard input': Inappropriate ioctl for device
[15:09:20] ================= [PASSED] check_media_ip ==================
[15:09:20] ===================== [PASSED] xe_pci ======================
[15:09:20] =================== xe_rtp (2 subtests) ====================
[15:09:20] =============== xe_rtp_process_to_sr_tests ================
[15:09:20] [PASSED] coalesce-same-reg
[15:09:20] [PASSED] no-match-no-add
[15:09:20] [PASSED] match-or
[15:09:20] [PASSED] match-or-xfail
[15:09:20] [PASSED] no-match-no-add-multiple-rules
[15:09:20] [PASSED] two-regs-two-entries
[15:09:20] [PASSED] clr-one-set-other
[15:09:20] [PASSED] set-field
[15:09:20] [PASSED] conflict-duplicate
[15:09:20] [PASSED] conflict-not-disjoint
[15:09:20] [PASSED] conflict-reg-type
[15:09:20] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[15:09:20] ================== xe_rtp_process_tests ===================
[15:09:20] [PASSED] active1
[15:09:20] [PASSED] active2
[15:09:20] [PASSED] active-inactive
[15:09:20] [PASSED] inactive-active
[15:09:20] [PASSED] inactive-1st_or_active-inactive
[15:09:20] [PASSED] inactive-2nd_or_active-inactive
[15:09:20] [PASSED] inactive-last_or_active-inactive
[15:09:20] [PASSED] inactive-no_or_active-inactive
[15:09:20] ============== [PASSED] xe_rtp_process_tests ===============
[15:09:20] ===================== [PASSED] xe_rtp ======================
[15:09:20] ==================== xe_wa (1 subtest) =====================
[15:09:20] ======================== xe_wa_gt =========================
[15:09:20] [PASSED] TIGERLAKE (B0)
[15:09:20] [PASSED] DG1 (A0)
[15:09:20] [PASSED] DG1 (B0)
[15:09:20] [PASSED] ALDERLAKE_S (A0)
[15:09:20] [PASSED] ALDERLAKE_S (B0)
[15:09:20] [PASSED] ALDERLAKE_S (C0)
[15:09:20] [PASSED] ALDERLAKE_S (D0)
[15:09:20] [PASSED] ALDERLAKE_P (A0)
[15:09:20] [PASSED] ALDERLAKE_P (B0)
[15:09:20] [PASSED] ALDERLAKE_P (C0)
[15:09:20] [PASSED] ALDERLAKE_S_RPLS (D0)
[15:09:20] [PASSED] ALDERLAKE_P_RPLU (E0)
[15:09:20] [PASSED] DG2_G10 (C0)
[15:09:20] [PASSED] DG2_G11 (B1)
[15:09:20] [PASSED] DG2_G12 (A1)
[15:09:20] [PASSED] METEORLAKE (g:A0, m:A0)
[15:09:20] [PASSED] METEORLAKE (g:A0, m:A0)
[15:09:20] [PASSED] METEORLAKE (g:A0, m:A0)
[15:09:20] [PASSED] LUNARLAKE (g:A0, m:A0)
[15:09:20] [PASSED] LUNARLAKE (g:B0, m:A0)
[15:09:20] [PASSED] BATTLEMAGE (g:A0, m:A1)
[15:09:20] ==================== [PASSED] xe_wa_gt =====================
[15:09:20] ====================== [PASSED] xe_wa ======================
[15:09:20] ============================================================
[15:09:20] Testing complete. Ran 145 tests: passed: 129, skipped: 16
[15:09:20] Elapsed time: 31.227s total, 4.120s configuring, 26.791s building, 0.297s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[15:09:20] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[15:09:21] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[15:09:43] Starting KUnit Kernel (1/1)...
[15:09:43] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[15:09:43] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[15:09:43] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[15:09:43] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[15:09:43] =========== drm_validate_clone_mode (2 subtests) ===========
[15:09:43] ============== drm_test_check_in_clone_mode ===============
[15:09:43] [PASSED] in_clone_mode
[15:09:43] [PASSED] not_in_clone_mode
[15:09:43] ========== [PASSED] drm_test_check_in_clone_mode ===========
[15:09:43] =============== drm_test_check_valid_clones ===============
[15:09:43] [PASSED] not_in_clone_mode
[15:09:43] [PASSED] valid_clone
[15:09:43] [PASSED] invalid_clone
[15:09:43] =========== [PASSED] drm_test_check_valid_clones ===========
[15:09:43] ============= [PASSED] drm_validate_clone_mode =============
[15:09:43] ============= drm_validate_modeset (1 subtest) =============
[15:09:43] [PASSED] drm_test_check_connector_changed_modeset
[15:09:43] ============== [PASSED] drm_validate_modeset ===============
[15:09:43] ====== drm_test_bridge_get_current_state (2 subtests) ======
[15:09:43] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[15:09:43] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[15:09:43] ======== [PASSED] drm_test_bridge_get_current_state ========
[15:09:43] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[15:09:43] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[15:09:43] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[15:09:43] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[15:09:43] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[15:09:43] ============== drm_bridge_alloc (2 subtests) ===============
[15:09:43] [PASSED] drm_test_drm_bridge_alloc_basic
[15:09:43] [PASSED] drm_test_drm_bridge_alloc_get_put
[15:09:43] ================ [PASSED] drm_bridge_alloc =================
[15:09:43] ================== drm_buddy (7 subtests) ==================
[15:09:43] [PASSED] drm_test_buddy_alloc_limit
[15:09:43] [PASSED] drm_test_buddy_alloc_optimistic
[15:09:43] [PASSED] drm_test_buddy_alloc_pessimistic
[15:09:43] [PASSED] drm_test_buddy_alloc_pathological
[15:09:43] [PASSED] drm_test_buddy_alloc_contiguous
[15:09:43] [PASSED] drm_test_buddy_alloc_clear
[15:09:43] [PASSED] drm_test_buddy_alloc_range_bias
[15:09:43] ==================== [PASSED] drm_buddy ====================
[15:09:43] ============= drm_cmdline_parser (40 subtests) =============
[15:09:43] [PASSED] drm_test_cmdline_force_d_only
[15:09:43] [PASSED] drm_test_cmdline_force_D_only_dvi
[15:09:43] [PASSED] drm_test_cmdline_force_D_only_hdmi
[15:09:43] [PASSED] drm_test_cmdline_force_D_only_not_digital
[15:09:43] [PASSED] drm_test_cmdline_force_e_only
[15:09:43] [PASSED] drm_test_cmdline_res
[15:09:43] [PASSED] drm_test_cmdline_res_vesa
[15:09:43] [PASSED] drm_test_cmdline_res_vesa_rblank
[15:09:43] [PASSED] drm_test_cmdline_res_rblank
[15:09:43] [PASSED] drm_test_cmdline_res_bpp
[15:09:43] [PASSED] drm_test_cmdline_res_refresh
[15:09:43] [PASSED] drm_test_cmdline_res_bpp_refresh
[15:09:43] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[15:09:43] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[15:09:43] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[15:09:43] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[15:09:43] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[15:09:43] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[15:09:43] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[15:09:43] [PASSED] drm_test_cmdline_res_margins_force_on
[15:09:43] [PASSED] drm_test_cmdline_res_vesa_margins
[15:09:43] [PASSED] drm_test_cmdline_name
[15:09:43] [PASSED] drm_test_cmdline_name_bpp
[15:09:43] [PASSED] drm_test_cmdline_name_option
[15:09:43] [PASSED] drm_test_cmdline_name_bpp_option
[15:09:43] [PASSED] drm_test_cmdline_rotate_0
[15:09:43] [PASSED] drm_test_cmdline_rotate_90
[15:09:43] [PASSED] drm_test_cmdline_rotate_180
[15:09:43] [PASSED] drm_test_cmdline_rotate_270
[15:09:43] [PASSED] drm_test_cmdline_hmirror
[15:09:43] [PASSED] drm_test_cmdline_vmirror
[15:09:43] [PASSED] drm_test_cmdline_margin_options
[15:09:43] [PASSED] drm_test_cmdline_multiple_options
[15:09:43] [PASSED] drm_test_cmdline_bpp_extra_and_option
[15:09:43] [PASSED] drm_test_cmdline_extra_and_option
[15:09:43] [PASSED] drm_test_cmdline_freestanding_options
[15:09:43] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[15:09:43] [PASSED] drm_test_cmdline_panel_orientation
[15:09:43] ================ drm_test_cmdline_invalid =================
[15:09:43] [PASSED] margin_only
[15:09:43] [PASSED] interlace_only
[15:09:43] [PASSED] res_missing_x
[15:09:43] [PASSED] res_missing_y
[15:09:43] [PASSED] res_bad_y
[15:09:43] [PASSED] res_missing_y_bpp
[15:09:43] [PASSED] res_bad_bpp
[15:09:43] [PASSED] res_bad_refresh
[15:09:43] [PASSED] res_bpp_refresh_force_on_off
[15:09:43] [PASSED] res_invalid_mode
[15:09:43] [PASSED] res_bpp_wrong_place_mode
[15:09:43] [PASSED] name_bpp_refresh
[15:09:43] [PASSED] name_refresh
[15:09:43] [PASSED] name_refresh_wrong_mode
[15:09:43] [PASSED] name_refresh_invalid_mode
[15:09:43] [PASSED] rotate_multiple
[15:09:43] [PASSED] rotate_invalid_val
[15:09:43] [PASSED] rotate_truncated
[15:09:43] [PASSED] invalid_option
[15:09:43] [PASSED] invalid_tv_option
[15:09:43] [PASSED] truncated_tv_option
[15:09:43] ============ [PASSED] drm_test_cmdline_invalid =============
[15:09:43] =============== drm_test_cmdline_tv_options ===============
[15:09:43] [PASSED] NTSC
[15:09:43] [PASSED] NTSC_443
[15:09:43] [PASSED] NTSC_J
[15:09:43] [PASSED] PAL
[15:09:43] [PASSED] PAL_M
[15:09:43] [PASSED] PAL_N
[15:09:43] [PASSED] SECAM
[15:09:43] [PASSED] MONO_525
[15:09:43] [PASSED] MONO_625
[15:09:43] =========== [PASSED] drm_test_cmdline_tv_options ===========
[15:09:43] =============== [PASSED] drm_cmdline_parser ================
[15:09:43] ========== drmm_connector_hdmi_init (20 subtests) ==========
[15:09:43] [PASSED] drm_test_connector_hdmi_init_valid
[15:09:43] [PASSED] drm_test_connector_hdmi_init_bpc_8
[15:09:43] [PASSED] drm_test_connector_hdmi_init_bpc_10
[15:09:43] [PASSED] drm_test_connector_hdmi_init_bpc_12
[15:09:43] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[15:09:43] [PASSED] drm_test_connector_hdmi_init_bpc_null
[15:09:43] [PASSED] drm_test_connector_hdmi_init_formats_empty
[15:09:43] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[15:09:43] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[15:09:43] [PASSED] supported_formats=0x9 yuv420_allowed=1
[15:09:43] [PASSED] supported_formats=0x9 yuv420_allowed=0
[15:09:43] [PASSED] supported_formats=0x3 yuv420_allowed=1
[15:09:43] [PASSED] supported_formats=0x3 yuv420_allowed=0
[15:09:43] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[15:09:43] [PASSED] drm_test_connector_hdmi_init_null_ddc
[15:09:43] [PASSED] drm_test_connector_hdmi_init_null_product
[15:09:43] [PASSED] drm_test_connector_hdmi_init_null_vendor
[15:09:43] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[15:09:43] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[15:09:43] [PASSED] drm_test_connector_hdmi_init_product_valid
[15:09:43] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[15:09:43] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[15:09:43] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[15:09:43] ========= drm_test_connector_hdmi_init_type_valid =========
[15:09:43] [PASSED] HDMI-A
[15:09:43] [PASSED] HDMI-B
[15:09:43] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[15:09:43] ======== drm_test_connector_hdmi_init_type_invalid ========
[15:09:43] [PASSED] Unknown
[15:09:43] [PASSED] VGA
[15:09:43] [PASSED] DVI-I
[15:09:43] [PASSED] DVI-D
[15:09:43] [PASSED] DVI-A
[15:09:43] [PASSED] Composite
[15:09:43] [PASSED] SVIDEO
[15:09:43] [PASSED] LVDS
[15:09:43] [PASSED] Component
[15:09:43] [PASSED] DIN
[15:09:43] [PASSED] DP
[15:09:43] [PASSED] TV
[15:09:43] [PASSED] eDP
[15:09:43] [PASSED] Virtual
[15:09:43] [PASSED] DSI
[15:09:43] [PASSED] DPI
[15:09:43] [PASSED] Writeback
[15:09:43] [PASSED] SPI
[15:09:43] [PASSED] USB
[15:09:43] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[15:09:43] ============ [PASSED] drmm_connector_hdmi_init =============
[15:09:43] ============= drmm_connector_init (3 subtests) =============
[15:09:43] [PASSED] drm_test_drmm_connector_init
[15:09:43] [PASSED] drm_test_drmm_connector_init_null_ddc
[15:09:43] ========= drm_test_drmm_connector_init_type_valid =========
[15:09:43] [PASSED] Unknown
[15:09:43] [PASSED] VGA
[15:09:43] [PASSED] DVI-I
[15:09:43] [PASSED] DVI-D
[15:09:43] [PASSED] DVI-A
[15:09:43] [PASSED] Composite
[15:09:43] [PASSED] SVIDEO
[15:09:43] [PASSED] LVDS
[15:09:43] [PASSED] Component
[15:09:43] [PASSED] DIN
[15:09:43] [PASSED] DP
[15:09:43] [PASSED] HDMI-A
[15:09:43] [PASSED] HDMI-B
[15:09:43] [PASSED] TV
[15:09:43] [PASSED] eDP
[15:09:43] [PASSED] Virtual
[15:09:43] [PASSED] DSI
[15:09:43] [PASSED] DPI
[15:09:43] [PASSED] Writeback
[15:09:43] [PASSED] SPI
[15:09:43] [PASSED] USB
[15:09:43] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[15:09:43] =============== [PASSED] drmm_connector_init ===============
[15:09:43] ========= drm_connector_dynamic_init (6 subtests) ==========
[15:09:43] [PASSED] drm_test_drm_connector_dynamic_init
[15:09:43] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[15:09:43] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[15:09:43] [PASSED] drm_test_drm_connector_dynamic_init_properties
[15:09:43] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[15:09:43] [PASSED] Unknown
[15:09:43] [PASSED] VGA
[15:09:43] [PASSED] DVI-I
[15:09:43] [PASSED] DVI-D
[15:09:43] [PASSED] DVI-A
[15:09:43] [PASSED] Composite
[15:09:43] [PASSED] SVIDEO
[15:09:43] [PASSED] LVDS
[15:09:43] [PASSED] Component
[15:09:43] [PASSED] DIN
[15:09:43] [PASSED] DP
[15:09:43] [PASSED] HDMI-A
[15:09:43] [PASSED] HDMI-B
[15:09:43] [PASSED] TV
[15:09:43] [PASSED] eDP
[15:09:43] [PASSED] Virtual
[15:09:43] [PASSED] DSI
[15:09:43] [PASSED] DPI
[15:09:43] [PASSED] Writeback
[15:09:43] [PASSED] SPI
[15:09:43] [PASSED] USB
[15:09:43] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[15:09:43] ======== drm_test_drm_connector_dynamic_init_name =========
[15:09:43] [PASSED] Unknown
[15:09:43] [PASSED] VGA
[15:09:43] [PASSED] DVI-I
[15:09:43] [PASSED] DVI-D
[15:09:43] [PASSED] DVI-A
[15:09:43] [PASSED] Composite
[15:09:43] [PASSED] SVIDEO
[15:09:43] [PASSED] LVDS
[15:09:43] [PASSED] Component
[15:09:43] [PASSED] DIN
[15:09:43] [PASSED] DP
[15:09:43] [PASSED] HDMI-A
[15:09:43] [PASSED] HDMI-B
[15:09:43] [PASSED] TV
[15:09:43] [PASSED] eDP
[15:09:43] [PASSED] Virtual
[15:09:43] [PASSED] DSI
[15:09:43] [PASSED] DPI
[15:09:43] [PASSED] Writeback
[15:09:43] [PASSED] SPI
[15:09:43] [PASSED] USB
[15:09:43] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[15:09:43] =========== [PASSED] drm_connector_dynamic_init ============
[15:09:43] ==== drm_connector_dynamic_register_early (4 subtests) =====
[15:09:43] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[15:09:43] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[15:09:43] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[15:09:43] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[15:09:43] ====== [PASSED] drm_connector_dynamic_register_early =======
[15:09:43] ======= drm_connector_dynamic_register (7 subtests) ========
[15:09:43] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[15:09:43] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[15:09:43] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[15:09:43] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[15:09:43] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[15:09:43] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[15:09:43] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[15:09:43] ========= [PASSED] drm_connector_dynamic_register ==========
[15:09:43] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[15:09:43] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[15:09:43] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[15:09:43] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[15:09:43] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[15:09:43] ========== drm_test_get_tv_mode_from_name_valid ===========
[15:09:43] [PASSED] NTSC
[15:09:43] [PASSED] NTSC-443
[15:09:43] [PASSED] NTSC-J
[15:09:43] [PASSED] PAL
[15:09:43] [PASSED] PAL-M
[15:09:43] [PASSED] PAL-N
[15:09:43] [PASSED] SECAM
[15:09:43] [PASSED] Mono
[15:09:43] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[15:09:43] [PASSED] drm_test_get_tv_mode_from_name_truncated
[15:09:43] ============ [PASSED] drm_get_tv_mode_from_name ============
[15:09:43] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[15:09:43] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[15:09:43] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[15:09:43] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[15:09:43] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[15:09:43] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[15:09:43] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[15:09:43] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[15:09:43] [PASSED] VIC 96
[15:09:43] [PASSED] VIC 97
[15:09:43] [PASSED] VIC 101
[15:09:43] [PASSED] VIC 102
[15:09:43] [PASSED] VIC 106
[15:09:43] [PASSED] VIC 107
[15:09:43] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[15:09:43] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[15:09:43] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[15:09:43] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[15:09:43] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[15:09:43] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[15:09:43] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[15:09:43] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[15:09:43] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[15:09:43] [PASSED] Automatic
[15:09:43] [PASSED] Full
[15:09:43] [PASSED] Limited 16:235
[15:09:43] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[15:09:43] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[15:09:43] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[15:09:43] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[15:09:43] === drm_test_drm_hdmi_connector_get_output_format_name ====
[15:09:43] [PASSED] RGB
[15:09:43] [PASSED] YUV 4:2:0
[15:09:43] [PASSED] YUV 4:2:2
[15:09:43] [PASSED] YUV 4:4:4
[15:09:43] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[15:09:43] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[15:09:43] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[15:09:43] ============= drm_damage_helper (21 subtests) ==============
[15:09:43] [PASSED] drm_test_damage_iter_no_damage
[15:09:43] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[15:09:43] [PASSED] drm_test_damage_iter_no_damage_src_moved
[15:09:43] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[15:09:43] [PASSED] drm_test_damage_iter_no_damage_not_visible
[15:09:43] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[15:09:43] [PASSED] drm_test_damage_iter_no_damage_no_fb
[15:09:43] [PASSED] drm_test_damage_iter_simple_damage
[15:09:43] [PASSED] drm_test_damage_iter_single_damage
[15:09:43] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[15:09:43] [PASSED] drm_test_damage_iter_single_damage_outside_src
[15:09:43] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[15:09:43] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[15:09:43] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[15:09:43] [PASSED] drm_test_damage_iter_single_damage_src_moved
[15:09:43] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[15:09:43] [PASSED] drm_test_damage_iter_damage
[15:09:43] [PASSED] drm_test_damage_iter_damage_one_intersect
[15:09:43] [PASSED] drm_test_damage_iter_damage_one_outside
[15:09:43] [PASSED] drm_test_damage_iter_damage_src_moved
[15:09:43] [PASSED] drm_test_damage_iter_damage_not_visible
[15:09:43] ================ [PASSED] drm_damage_helper ================
[15:09:43] ============== drm_dp_mst_helper (3 subtests) ==============
[15:09:43] ============== drm_test_dp_mst_calc_pbn_mode ==============
[15:09:43] [PASSED] Clock 154000 BPP 30 DSC disabled
[15:09:43] [PASSED] Clock 234000 BPP 30 DSC disabled
[15:09:43] [PASSED] Clock 297000 BPP 24 DSC disabled
[15:09:43] [PASSED] Clock 332880 BPP 24 DSC enabled
[15:09:43] [PASSED] Clock 324540 BPP 24 DSC enabled
[15:09:43] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[15:09:43] ============== drm_test_dp_mst_calc_pbn_div ===============
[15:09:43] [PASSED] Link rate 2000000 lane count 4
[15:09:43] [PASSED] Link rate 2000000 lane count 2
[15:09:43] [PASSED] Link rate 2000000 lane count 1
[15:09:43] [PASSED] Link rate 1350000 lane count 4
[15:09:43] [PASSED] Link rate 1350000 lane count 2
[15:09:43] [PASSED] Link rate 1350000 lane count 1
[15:09:43] [PASSED] Link rate 1000000 lane count 4
[15:09:43] [PASSED] Link rate 1000000 lane count 2
[15:09:43] [PASSED] Link rate 1000000 lane count 1
[15:09:43] [PASSED] Link rate 810000 lane count 4
[15:09:43] [PASSED] Link rate 810000 lane count 2
[15:09:43] [PASSED] Link rate 810000 lane count 1
[15:09:43] [PASSED] Link rate 540000 lane count 4
[15:09:43] [PASSED] Link rate 540000 lane count 2
[15:09:43] [PASSED] Link rate 540000 lane count 1
[15:09:43] [PASSED] Link rate 270000 lane count 4
[15:09:43] [PASSED] Link rate 270000 lane count 2
[15:09:43] [PASSED] Link rate 270000 lane count 1
[15:09:43] [PASSED] Link rate 162000 lane count 4
[15:09:43] [PASSED] Link rate 162000 lane count 2
[15:09:43] [PASSED] Link rate 162000 lane count 1
[15:09:43] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[15:09:43] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[15:09:43] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[15:09:43] [PASSED] DP_POWER_UP_PHY with port number
[15:09:43] [PASSED] DP_POWER_DOWN_PHY with port number
[15:09:43] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[15:09:43] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[15:09:43] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[15:09:43] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[15:09:43] [PASSED] DP_QUERY_PAYLOAD with port number
[15:09:43] [PASSED] DP_QUERY_PAYLOAD with VCPI
[15:09:43] [PASSED] DP_REMOTE_DPCD_READ with port number
[15:09:43] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[15:09:43] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[15:09:43] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[15:09:43] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[15:09:43] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[15:09:43] [PASSED] DP_REMOTE_I2C_READ with port number
[15:09:43] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[15:09:43] [PASSED] DP_REMOTE_I2C_READ with transactions array
[15:09:43] [PASSED] DP_REMOTE_I2C_WRITE with port number
[15:09:43] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[15:09:43] [PASSED] DP_REMOTE_I2C_WRITE with data array
[15:09:43] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[15:09:43] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[15:09:43] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[15:09:43] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[15:09:43] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[15:09:43] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[15:09:43] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[15:09:43] ================ [PASSED] drm_dp_mst_helper ================
[15:09:43] ================== drm_exec (7 subtests) ===================
[15:09:43] [PASSED] sanitycheck
[15:09:43] [PASSED] test_lock
[15:09:43] [PASSED] test_lock_unlock
[15:09:43] [PASSED] test_duplicates
[15:09:43] [PASSED] test_prepare
[15:09:43] [PASSED] test_prepare_array
[15:09:43] [PASSED] test_multiple_loops
[15:09:43] ==================== [PASSED] drm_exec =====================
[15:09:43] =========== drm_format_helper_test (17 subtests) ===========
[15:09:43] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[15:09:43] [PASSED] single_pixel_source_buffer
[15:09:43] [PASSED] single_pixel_clip_rectangle
[15:09:43] [PASSED] well_known_colors
[15:09:43] [PASSED] destination_pitch
[15:09:43] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[15:09:43] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[15:09:43] [PASSED] single_pixel_source_buffer
[15:09:43] [PASSED] single_pixel_clip_rectangle
[15:09:43] [PASSED] well_known_colors
[15:09:43] [PASSED] destination_pitch
[15:09:43] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[15:09:43] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[15:09:43] [PASSED] single_pixel_source_buffer
[15:09:43] [PASSED] single_pixel_clip_rectangle
[15:09:43] [PASSED] well_known_colors
[15:09:43] [PASSED] destination_pitch
[15:09:43] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[15:09:43] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[15:09:43] [PASSED] single_pixel_source_buffer
[15:09:43] [PASSED] single_pixel_clip_rectangle
[15:09:43] [PASSED] well_known_colors
[15:09:43] [PASSED] destination_pitch
[15:09:43] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[15:09:43] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[15:09:43] [PASSED] single_pixel_source_buffer
[15:09:43] [PASSED] single_pixel_clip_rectangle
[15:09:43] [PASSED] well_known_colors
[15:09:43] [PASSED] destination_pitch
[15:09:43] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[15:09:43] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[15:09:43] [PASSED] single_pixel_source_buffer
[15:09:43] [PASSED] single_pixel_clip_rectangle
[15:09:43] [PASSED] well_known_colors
[15:09:43] [PASSED] destination_pitch
[15:09:43] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[15:09:43] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[15:09:43] [PASSED] single_pixel_source_buffer
[15:09:43] [PASSED] single_pixel_clip_rectangle
[15:09:43] [PASSED] well_known_colors
[15:09:43] [PASSED] destination_pitch
[15:09:43] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[15:09:43] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[15:09:43] [PASSED] single_pixel_source_buffer
[15:09:43] [PASSED] single_pixel_clip_rectangle
[15:09:43] [PASSED] well_known_colors
[15:09:43] [PASSED] destination_pitch
[15:09:43] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[15:09:43] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[15:09:43] [PASSED] single_pixel_source_buffer
[15:09:43] [PASSED] single_pixel_clip_rectangle
[15:09:43] [PASSED] well_known_colors
[15:09:43] [PASSED] destination_pitch
[15:09:43] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[15:09:43] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[15:09:43] [PASSED] single_pixel_source_buffer
[15:09:43] [PASSED] single_pixel_clip_rectangle
[15:09:43] [PASSED] well_known_colors
[15:09:43] [PASSED] destination_pitch
[15:09:43] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[15:09:43] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[15:09:43] [PASSED] single_pixel_source_buffer
[15:09:43] [PASSED] single_pixel_clip_rectangle
[15:09:43] [PASSED] well_known_colors
[15:09:43] [PASSED] destination_pitch
[15:09:43] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[15:09:43] ============== drm_test_fb_xrgb8888_to_mono ===============
[15:09:43] [PASSED] single_pixel_source_buffer
[15:09:43] [PASSED] single_pixel_clip_rectangle
[15:09:43] [PASSED] well_known_colors
[15:09:43] [PASSED] destination_pitch
[15:09:43] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[15:09:43] ==================== drm_test_fb_swab =====================
[15:09:43] [PASSED] single_pixel_source_buffer
[15:09:43] [PASSED] single_pixel_clip_rectangle
[15:09:43] [PASSED] well_known_colors
[15:09:43] [PASSED] destination_pitch
[15:09:43] ================ [PASSED] drm_test_fb_swab =================
[15:09:43] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[15:09:43] [PASSED] single_pixel_source_buffer
[15:09:43] [PASSED] single_pixel_clip_rectangle
[15:09:43] [PASSED] well_known_colors
[15:09:43] [PASSED] destination_pitch
[15:09:43] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[15:09:43] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[15:09:43] [PASSED] single_pixel_source_buffer
[15:09:43] [PASSED] single_pixel_clip_rectangle
[15:09:43] [PASSED] well_known_colors
[15:09:43] [PASSED] destination_pitch
[15:09:43] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[15:09:43] ================= drm_test_fb_clip_offset =================
[15:09:43] [PASSED] pass through
[15:09:43] [PASSED] horizontal offset
[15:09:43] [PASSED] vertical offset
[15:09:43] [PASSED] horizontal and vertical offset
[15:09:43] [PASSED] horizontal offset (custom pitch)
[15:09:43] [PASSED] vertical offset (custom pitch)
[15:09:43] [PASSED] horizontal and vertical offset (custom pitch)
[15:09:43] ============= [PASSED] drm_test_fb_clip_offset =============
[15:09:43] =================== drm_test_fb_memcpy ====================
[15:09:43] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[15:09:43] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[15:09:43] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[15:09:43] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[15:09:43] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[15:09:43] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[15:09:43] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[15:09:43] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[15:09:43] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[15:09:43] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[15:09:43] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[15:09:43] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[15:09:43] =============== [PASSED] drm_test_fb_memcpy ================
[15:09:43] ============= [PASSED] drm_format_helper_test ==============
[15:09:43] ================= drm_format (18 subtests) =================
[15:09:43] [PASSED] drm_test_format_block_width_invalid
[15:09:43] [PASSED] drm_test_format_block_width_one_plane
[15:09:43] [PASSED] drm_test_format_block_width_two_plane
[15:09:43] [PASSED] drm_test_format_block_width_three_plane
[15:09:43] [PASSED] drm_test_format_block_width_tiled
[15:09:43] [PASSED] drm_test_format_block_height_invalid
[15:09:43] [PASSED] drm_test_format_block_height_one_plane
[15:09:43] [PASSED] drm_test_format_block_height_two_plane
[15:09:43] [PASSED] drm_test_format_block_height_three_plane
[15:09:43] [PASSED] drm_test_format_block_height_tiled
[15:09:43] [PASSED] drm_test_format_min_pitch_invalid
[15:09:43] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[15:09:43] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[15:09:43] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[15:09:43] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[15:09:43] [PASSED] drm_test_format_min_pitch_two_plane
[15:09:43] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[15:09:43] [PASSED] drm_test_format_min_pitch_tiled
[15:09:43] =================== [PASSED] drm_format ====================
[15:09:43] ============== drm_framebuffer (10 subtests) ===============
[15:09:43] ========== drm_test_framebuffer_check_src_coords ==========
[15:09:43] [PASSED] Success: source fits into fb
[15:09:43] [PASSED] Fail: overflowing fb with x-axis coordinate
[15:09:43] [PASSED] Fail: overflowing fb with y-axis coordinate
[15:09:43] [PASSED] Fail: overflowing fb with source width
[15:09:43] [PASSED] Fail: overflowing fb with source height
[15:09:43] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[15:09:43] [PASSED] drm_test_framebuffer_cleanup
[15:09:43] =============== drm_test_framebuffer_create ===============
[15:09:43] [PASSED] ABGR8888 normal sizes
[15:09:43] [PASSED] ABGR8888 max sizes
[15:09:43] [PASSED] ABGR8888 pitch greater than min required
[15:09:43] [PASSED] ABGR8888 pitch less than min required
[15:09:43] [PASSED] ABGR8888 Invalid width
[15:09:43] [PASSED] ABGR8888 Invalid buffer handle
[15:09:43] [PASSED] No pixel format
[15:09:43] [PASSED] ABGR8888 Width 0
[15:09:43] [PASSED] ABGR8888 Height 0
[15:09:43] [PASSED] ABGR8888 Out of bound height * pitch combination
[15:09:43] [PASSED] ABGR8888 Large buffer offset
[15:09:43] [PASSED] ABGR8888 Buffer offset for inexistent plane
[15:09:43] [PASSED] ABGR8888 Invalid flag
[15:09:43] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[15:09:43] [PASSED] ABGR8888 Valid buffer modifier
[15:09:43] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[15:09:43] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[15:09:43] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[15:09:43] [PASSED] NV12 Normal sizes
[15:09:43] [PASSED] NV12 Max sizes
[15:09:43] [PASSED] NV12 Invalid pitch
[15:09:43] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[15:09:43] [PASSED] NV12 different modifier per-plane
[15:09:43] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[15:09:43] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[15:09:43] [PASSED] NV12 Modifier for inexistent plane
[15:09:43] [PASSED] NV12 Handle for inexistent plane
[15:09:43] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[15:09:43] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[15:09:43] [PASSED] YVU420 Normal sizes
[15:09:43] [PASSED] YVU420 Max sizes
[15:09:43] [PASSED] YVU420 Invalid pitch
[15:09:43] [PASSED] YVU420 Different pitches
[15:09:43] [PASSED] YVU420 Different buffer offsets/pitches
[15:09:43] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[15:09:43] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[15:09:43] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[15:09:43] [PASSED] YVU420 Valid modifier
[15:09:43] [PASSED] YVU420 Different modifiers per plane
[15:09:43] [PASSED] YVU420 Modifier for inexistent plane
[15:09:43] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[15:09:43] [PASSED] X0L2 Normal sizes
[15:09:43] [PASSED] X0L2 Max sizes
[15:09:43] [PASSED] X0L2 Invalid pitch
[15:09:43] [PASSED] X0L2 Pitch greater than minimum required
[15:09:43] [PASSED] X0L2 Handle for inexistent plane
[15:09:43] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[15:09:43] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[15:09:43] [PASSED] X0L2 Valid modifier
[15:09:43] [PASSED] X0L2 Modifier for inexistent plane
[15:09:43] =========== [PASSED] drm_test_framebuffer_create ===========
[15:09:43] [PASSED] drm_test_framebuffer_free
[15:09:43] [PASSED] drm_test_framebuffer_init
[15:09:43] [PASSED] drm_test_framebuffer_init_bad_format
[15:09:43] [PASSED] drm_test_framebuffer_init_dev_mismatch
[15:09:43] [PASSED] drm_test_framebuffer_lookup
[15:09:43] [PASSED] drm_test_framebuffer_lookup_inexistent
[15:09:43] [PASSED] drm_test_framebuffer_modifiers_not_supported
[15:09:43] ================= [PASSED] drm_framebuffer =================
[15:09:43] ================ drm_gem_shmem (8 subtests) ================
[15:09:43] [PASSED] drm_gem_shmem_test_obj_create
[15:09:43] [PASSED] drm_gem_shmem_test_obj_create_private
[15:09:43] [PASSED] drm_gem_shmem_test_pin_pages
[15:09:43] [PASSED] drm_gem_shmem_test_vmap
[15:09:43] [PASSED] drm_gem_shmem_test_get_pages_sgt
[15:09:43] [PASSED] drm_gem_shmem_test_get_sg_table
[15:09:43] [PASSED] drm_gem_shmem_test_madvise
[15:09:43] [PASSED] drm_gem_shmem_test_purge
[15:09:43] ================== [PASSED] drm_gem_shmem ==================
[15:09:43] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[15:09:43] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[15:09:43] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[15:09:43] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[15:09:43] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[15:09:43] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[15:09:43] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[15:09:43] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[15:09:43] [PASSED] Automatic
[15:09:43] [PASSED] Full
[15:09:43] [PASSED] Limited 16:235
[15:09:43] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[15:09:43] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[15:09:43] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[15:09:43] [PASSED] drm_test_check_disable_connector
[15:09:43] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[15:09:43] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[15:09:43] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[15:09:43] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[15:09:43] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[15:09:43] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[15:09:43] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[15:09:43] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[15:09:43] [PASSED] drm_test_check_output_bpc_dvi
[15:09:43] [PASSED] drm_test_check_output_bpc_format_vic_1
[15:09:43] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[15:09:43] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[15:09:43] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[15:09:43] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[15:09:43] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[15:09:43] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[15:09:43] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[15:09:43] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[15:09:43] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[15:09:43] [PASSED] drm_test_check_broadcast_rgb_value
[15:09:43] [PASSED] drm_test_check_bpc_8_value
[15:09:43] [PASSED] drm_test_check_bpc_10_value
[15:09:43] [PASSED] drm_test_check_bpc_12_value
[15:09:43] [PASSED] drm_test_check_format_value
[15:09:43] [PASSED] drm_test_check_tmds_char_value
[15:09:43] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[15:09:43] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[15:09:43] [PASSED] drm_test_check_mode_valid
[15:09:43] [PASSED] drm_test_check_mode_valid_reject
[15:09:43] [PASSED] drm_test_check_mode_valid_reject_rate
[15:09:43] [PASSED] drm_test_check_mode_valid_reject_max_clock
[15:09:43] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[15:09:43] ================= drm_managed (2 subtests) =================
[15:09:43] [PASSED] drm_test_managed_release_action
[15:09:43] [PASSED] drm_test_managed_run_action
[15:09:43] =================== [PASSED] drm_managed ===================
[15:09:43] =================== drm_mm (6 subtests) ====================
[15:09:43] [PASSED] drm_test_mm_init
[15:09:43] [PASSED] drm_test_mm_debug
[15:09:43] [PASSED] drm_test_mm_align32
[15:09:43] [PASSED] drm_test_mm_align64
[15:09:43] [PASSED] drm_test_mm_lowest
[15:09:43] [PASSED] drm_test_mm_highest
[15:09:43] ===================== [PASSED] drm_mm ======================
[15:09:43] ============= drm_modes_analog_tv (5 subtests) =============
[15:09:43] [PASSED] drm_test_modes_analog_tv_mono_576i
[15:09:43] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[15:09:43] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[15:09:43] [PASSED] drm_test_modes_analog_tv_pal_576i
[15:09:43] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[15:09:43] =============== [PASSED] drm_modes_analog_tv ===============
[15:09:43] ============== drm_plane_helper (2 subtests) ===============
[15:09:43] =============== drm_test_check_plane_state ================
[15:09:43] [PASSED] clipping_simple
[15:09:43] [PASSED] clipping_rotate_reflect
[15:09:43] [PASSED] positioning_simple
[15:09:43] [PASSED] upscaling
[15:09:43] [PASSED] downscaling
[15:09:43] [PASSED] rounding1
[15:09:43] [PASSED] rounding2
[15:09:43] [PASSED] rounding3
[15:09:43] [PASSED] rounding4
[15:09:43] =========== [PASSED] drm_test_check_plane_state ============
[15:09:43] =========== drm_test_check_invalid_plane_state ============
[15:09:43] [PASSED] positioning_invalid
[15:09:43] [PASSED] upscaling_invalid
[15:09:43] [PASSED] downscaling_invalid
[15:09:43] ======= [PASSED] drm_test_check_invalid_plane_state ========
[15:09:43] ================ [PASSED] drm_plane_helper =================
[15:09:43] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[15:09:43] ====== drm_test_connector_helper_tv_get_modes_check =======
[15:09:43] [PASSED] None
[15:09:43] [PASSED] PAL
[15:09:43] [PASSED] NTSC
[15:09:43] [PASSED] Both, NTSC Default
[15:09:43] [PASSED] Both, PAL Default
[15:09:43] [PASSED] Both, NTSC Default, with PAL on command-line
[15:09:43] [PASSED] Both, PAL Default, with NTSC on command-line
[15:09:43] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[15:09:43] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[15:09:43] ================== drm_rect (9 subtests) ===================
[15:09:43] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[15:09:43] [PASSED] drm_test_rect_clip_scaled_not_clipped
[15:09:43] [PASSED] drm_test_rect_clip_scaled_clipped
[15:09:43] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[15:09:43] ================= drm_test_rect_intersect =================
[15:09:43] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[15:09:43] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[15:09:43] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[15:09:43] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[15:09:43] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[15:09:43] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[15:09:43] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[15:09:43] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[15:09:43] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[15:09:43] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[15:09:43] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[15:09:43] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[15:09:43] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[15:09:43] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[15:09:43] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[15:09:43] ============= [PASSED] drm_test_rect_intersect =============
[15:09:43] ================ drm_test_rect_calc_hscale ================
[15:09:43] [PASSED] normal use
[15:09:43] [PASSED] out of max range
[15:09:43] [PASSED] out of min range
[15:09:43] [PASSED] zero dst
[15:09:43] [PASSED] negative src
[15:09:43] [PASSED] negative dst
[15:09:43] ============ [PASSED] drm_test_rect_calc_hscale ============
[15:09:43] ================ drm_test_rect_calc_vscale ================
[15:09:43] [PASSED] normal use
[15:09:43] [PASSED] out of max range
[15:09:43] [PASSED] out of min range
[15:09:43] [PASSED] zero dst
[15:09:43] [PASSED] negative src
[15:09:43] [PASSED] negative dst
[15:09:43] ============ [PASSED] drm_test_rect_calc_vscale ============
[15:09:43] ================== drm_test_rect_rotate ===================
[15:09:43] [PASSED] reflect-x
[15:09:43] [PASSED] reflect-y
[15:09:43] [PASSED] rotate-0
[15:09:43] [PASSED] rotate-90
[15:09:43] [PASSED] rotate-180
[15:09:43] [PASSED] rotate-270
stty: 'standard input': Inappropriate ioctl for device
[15:09:43] ============== [PASSED] drm_test_rect_rotate ===============
[15:09:43] ================ drm_test_rect_rotate_inv =================
[15:09:43] [PASSED] reflect-x
[15:09:43] [PASSED] reflect-y
[15:09:43] [PASSED] rotate-0
[15:09:43] [PASSED] rotate-90
[15:09:43] [PASSED] rotate-180
[15:09:43] [PASSED] rotate-270
[15:09:43] ============ [PASSED] drm_test_rect_rotate_inv =============
[15:09:43] ==================== [PASSED] drm_rect =====================
[15:09:43] ============ drm_sysfb_modeset_test (1 subtest) ============
[15:09:43] ============ drm_test_sysfb_build_fourcc_list =============
[15:09:43] [PASSED] no native formats
[15:09:43] [PASSED] XRGB8888 as native format
[15:09:43] [PASSED] remove duplicates
[15:09:43] [PASSED] convert alpha formats
[15:09:43] [PASSED] random formats
[15:09:43] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[15:09:43] ============= [PASSED] drm_sysfb_modeset_test ==============
[15:09:43] ============================================================
[15:09:43] Testing complete. Ran 616 tests: passed: 616
[15:09:43] Elapsed time: 23.304s total, 1.669s configuring, 21.468s building, 0.145s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[15:09:43] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[15:09:45] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[15:09:53] Starting KUnit Kernel (1/1)...
[15:09:53] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[15:09:53] ================= ttm_device (5 subtests) ==================
[15:09:53] [PASSED] ttm_device_init_basic
[15:09:53] [PASSED] ttm_device_init_multiple
[15:09:53] [PASSED] ttm_device_fini_basic
[15:09:53] [PASSED] ttm_device_init_no_vma_man
[15:09:53] ================== ttm_device_init_pools ==================
[15:09:53] [PASSED] No DMA allocations, no DMA32 required
[15:09:53] [PASSED] DMA allocations, DMA32 required
[15:09:53] [PASSED] No DMA allocations, DMA32 required
[15:09:53] [PASSED] DMA allocations, no DMA32 required
[15:09:53] ============== [PASSED] ttm_device_init_pools ==============
[15:09:53] =================== [PASSED] ttm_device ====================
[15:09:53] ================== ttm_pool (8 subtests) ===================
[15:09:53] ================== ttm_pool_alloc_basic ===================
[15:09:53] [PASSED] One page
[15:09:53] [PASSED] More than one page
[15:09:53] [PASSED] Above the allocation limit
[15:09:53] [PASSED] One page, with coherent DMA mappings enabled
[15:09:53] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[15:09:53] ============== [PASSED] ttm_pool_alloc_basic ===============
[15:09:53] ============== ttm_pool_alloc_basic_dma_addr ==============
[15:09:53] [PASSED] One page
[15:09:53] [PASSED] More than one page
[15:09:53] [PASSED] Above the allocation limit
[15:09:53] [PASSED] One page, with coherent DMA mappings enabled
[15:09:53] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[15:09:53] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[15:09:53] [PASSED] ttm_pool_alloc_order_caching_match
[15:09:53] [PASSED] ttm_pool_alloc_caching_mismatch
[15:09:53] [PASSED] ttm_pool_alloc_order_mismatch
[15:09:53] [PASSED] ttm_pool_free_dma_alloc
[15:09:53] [PASSED] ttm_pool_free_no_dma_alloc
[15:09:53] [PASSED] ttm_pool_fini_basic
[15:09:53] ==================== [PASSED] ttm_pool =====================
[15:09:53] ================ ttm_resource (8 subtests) =================
[15:09:53] ================= ttm_resource_init_basic =================
[15:09:53] [PASSED] Init resource in TTM_PL_SYSTEM
[15:09:53] [PASSED] Init resource in TTM_PL_VRAM
[15:09:53] [PASSED] Init resource in a private placement
[15:09:53] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[15:09:53] ============= [PASSED] ttm_resource_init_basic =============
[15:09:53] [PASSED] ttm_resource_init_pinned
[15:09:53] [PASSED] ttm_resource_fini_basic
[15:09:53] [PASSED] ttm_resource_manager_init_basic
[15:09:53] [PASSED] ttm_resource_manager_usage_basic
[15:09:53] [PASSED] ttm_resource_manager_set_used_basic
[15:09:53] [PASSED] ttm_sys_man_alloc_basic
[15:09:53] [PASSED] ttm_sys_man_free_basic
[15:09:53] ================== [PASSED] ttm_resource ===================
[15:09:53] =================== ttm_tt (15 subtests) ===================
[15:09:53] ==================== ttm_tt_init_basic ====================
[15:09:53] [PASSED] Page-aligned size
[15:09:53] [PASSED] Extra pages requested
[15:09:53] ================ [PASSED] ttm_tt_init_basic ================
[15:09:53] [PASSED] ttm_tt_init_misaligned
[15:09:53] [PASSED] ttm_tt_fini_basic
[15:09:53] [PASSED] ttm_tt_fini_sg
[15:09:53] [PASSED] ttm_tt_fini_shmem
[15:09:53] [PASSED] ttm_tt_create_basic
[15:09:53] [PASSED] ttm_tt_create_invalid_bo_type
[15:09:53] [PASSED] ttm_tt_create_ttm_exists
[15:09:53] [PASSED] ttm_tt_create_failed
[15:09:53] [PASSED] ttm_tt_destroy_basic
[15:09:53] [PASSED] ttm_tt_populate_null_ttm
[15:09:53] [PASSED] ttm_tt_populate_populated_ttm
[15:09:53] [PASSED] ttm_tt_unpopulate_basic
[15:09:53] [PASSED] ttm_tt_unpopulate_empty_ttm
[15:09:53] [PASSED] ttm_tt_swapin_basic
[15:09:53] ===================== [PASSED] ttm_tt ======================
[15:09:53] =================== ttm_bo (14 subtests) ===================
[15:09:53] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[15:09:53] [PASSED] Cannot be interrupted and sleeps
[15:09:53] [PASSED] Cannot be interrupted, locks straight away
[15:09:53] [PASSED] Can be interrupted, sleeps
[15:09:53] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[15:09:53] [PASSED] ttm_bo_reserve_locked_no_sleep
[15:09:53] [PASSED] ttm_bo_reserve_no_wait_ticket
[15:09:53] [PASSED] ttm_bo_reserve_double_resv
[15:09:53] [PASSED] ttm_bo_reserve_interrupted
[15:09:53] [PASSED] ttm_bo_reserve_deadlock
[15:09:53] [PASSED] ttm_bo_unreserve_basic
[15:09:53] [PASSED] ttm_bo_unreserve_pinned
[15:09:53] [PASSED] ttm_bo_unreserve_bulk
[15:09:53] [PASSED] ttm_bo_put_basic
[15:09:53] [PASSED] ttm_bo_put_shared_resv
[15:09:53] [PASSED] ttm_bo_pin_basic
[15:09:53] [PASSED] ttm_bo_pin_unpin_resource
[15:09:53] [PASSED] ttm_bo_multiple_pin_one_unpin
[15:09:53] ===================== [PASSED] ttm_bo ======================
[15:09:53] ============== ttm_bo_validate (22 subtests) ===============
[15:09:53] ============== ttm_bo_init_reserved_sys_man ===============
[15:09:53] [PASSED] Buffer object for userspace
[15:09:53] [PASSED] Kernel buffer object
[15:09:53] [PASSED] Shared buffer object
[15:09:53] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[15:09:53] ============== ttm_bo_init_reserved_mock_man ==============
[15:09:53] [PASSED] Buffer object for userspace
[15:09:53] [PASSED] Kernel buffer object
[15:09:53] [PASSED] Shared buffer object
[15:09:53] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[15:09:53] [PASSED] ttm_bo_init_reserved_resv
[15:09:53] ================== ttm_bo_validate_basic ==================
[15:09:53] [PASSED] Buffer object for userspace
[15:09:53] [PASSED] Kernel buffer object
[15:09:53] [PASSED] Shared buffer object
[15:09:53] ============== [PASSED] ttm_bo_validate_basic ==============
[15:09:53] [PASSED] ttm_bo_validate_invalid_placement
[15:09:53] ============= ttm_bo_validate_same_placement ==============
[15:09:53] [PASSED] System manager
[15:09:53] [PASSED] VRAM manager
[15:09:53] ========= [PASSED] ttm_bo_validate_same_placement ==========
[15:09:53] [PASSED] ttm_bo_validate_failed_alloc
[15:09:53] [PASSED] ttm_bo_validate_pinned
[15:09:53] [PASSED] ttm_bo_validate_busy_placement
[15:09:53] ================ ttm_bo_validate_multihop =================
[15:09:53] [PASSED] Buffer object for userspace
[15:09:53] [PASSED] Kernel buffer object
[15:09:53] [PASSED] Shared buffer object
[15:09:53] ============ [PASSED] ttm_bo_validate_multihop =============
[15:09:53] ========== ttm_bo_validate_no_placement_signaled ==========
[15:09:53] [PASSED] Buffer object in system domain, no page vector
[15:09:53] [PASSED] Buffer object in system domain with an existing page vector
[15:09:53] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[15:09:53] ======== ttm_bo_validate_no_placement_not_signaled ========
[15:09:53] [PASSED] Buffer object for userspace
[15:09:53] [PASSED] Kernel buffer object
[15:09:53] [PASSED] Shared buffer object
[15:09:53] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[15:09:53] [PASSED] ttm_bo_validate_move_fence_signaled
[15:09:53] ========= ttm_bo_validate_move_fence_not_signaled =========
[15:09:53] [PASSED] Waits for GPU
[15:09:53] [PASSED] Tries to lock straight away
[15:09:53] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[15:09:53] [PASSED] ttm_bo_validate_swapout
[15:09:53] [PASSED] ttm_bo_validate_happy_evict
[15:09:53] [PASSED] ttm_bo_validate_all_pinned_evict
[15:09:53] [PASSED] ttm_bo_validate_allowed_only_evict
[15:09:53] [PASSED] ttm_bo_validate_deleted_evict
[15:09:53] [PASSED] ttm_bo_validate_busy_domain_evict
[15:09:53] [PASSED] ttm_bo_validate_evict_gutting
[15:09:53] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[15:09:53] ================= [PASSED] ttm_bo_validate =================
[15:09:53] ============================================================
[15:09:53] Testing complete. Ran 102 tests: passed: 102
[15:09:53] Elapsed time: 10.067s total, 1.668s configuring, 7.782s building, 0.528s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v9 1/3] drm/xe/vf: Create contexts for CCS read write
2025-06-24 10:00 ` [PATCH v9 1/3] drm/xe/vf: Create contexts for CCS read write Satyanarayana K V P
@ 2025-06-24 15:40 ` Matthew Brost
2025-06-24 17:01 ` Matthew Brost
1 sibling, 0 replies; 13+ messages in thread
From: Matthew Brost @ 2025-06-24 15:40 UTC (permalink / raw)
To: Satyanarayana K V P
Cc: intel-xe, Michal Wajdeczko, Michał Winiarski, Tomasz Lis,
Matthew Auld
On Tue, Jun 24, 2025 at 03:30:08PM +0530, Satyanarayana K V P wrote:
> Create two LRCs to handle CCS meta data read / write from CCS pool in the
> VM. Read context is used to hold GPU instructions to be executed at save
> time and write context is used to hold GPU instructions to be executed at
> the restore time.
>
> Allocate batch buffer pool using suballocator for both read and write
> contexts.
>
> Migration framework is reused to create LRCAs for read and write.
>
> Signed-off-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>
> Cc: Michał Winiarski <michal.winiarski@intel.com>
> Acked-by: Matthew Brost <matthew.brost@intel.com>
> ---
> Cc: Tomasz Lis <tomasz.lis@intel.com>
> Cc: Matthew Auld <matthew.auld@intel.com>
>
> V8 -> V9:
> - Initialized CCS read write contexts for only root tile (Matthew Brost).
>
> V7 -> V8:
> - None.
>
> V6 -> V7:
> - Fixed review comments (Michal Wajdeczko & Matthew Brost).
>
> V5 -> V6:
> - Added id field in the xe_tile_vf_ccs structure for self identification.
>
> V4 -> V5:
> - Modified read/write contexts to enums from #defines (Matthew Brost).
> - The CCS BB pool size is calculated based on the system memory size (Michal
> Wajdeczko & Matthew Brost).
>
> V3 -> V4:
> - Fixed issues reported by patchworks.
>
> V2 -> V3:
> - Added new variable which denotes the initialization of contexts.
>
> V1 -> V2:
> - Fixed review comments.
> ---
> drivers/gpu/drm/xe/Makefile | 1 +
> drivers/gpu/drm/xe/xe_device.c | 4 +
> drivers/gpu/drm/xe/xe_device_types.h | 4 +
> drivers/gpu/drm/xe/xe_gt_debugfs.c | 36 ++++
> drivers/gpu/drm/xe/xe_sriov.c | 19 ++
> drivers/gpu/drm/xe/xe_sriov.h | 1 +
> drivers/gpu/drm/xe/xe_sriov_types.h | 5 +
> drivers/gpu/drm/xe/xe_sriov_vf_ccs.c | 208 +++++++++++++++++++++
> drivers/gpu/drm/xe/xe_sriov_vf_ccs.h | 13 ++
> drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h | 45 +++++
> 10 files changed, 336 insertions(+)
> create mode 100644 drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
> create mode 100644 drivers/gpu/drm/xe/xe_sriov_vf_ccs.h
> create mode 100644 drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h
>
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index eee6bac01a00..853970ab1314 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -141,6 +141,7 @@ xe-y += \
> xe_memirq.o \
> xe_sriov.o \
> xe_sriov_vf.o \
> + xe_sriov_vf_ccs.o \
> xe_tile_sriov_vf.o
>
> xe-$(CONFIG_PCI_IOV) += \
> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
> index e160e7be84f0..b7922668741c 100644
> --- a/drivers/gpu/drm/xe/xe_device.c
> +++ b/drivers/gpu/drm/xe/xe_device.c
> @@ -929,6 +929,10 @@ int xe_device_probe(struct xe_device *xe)
>
> xe_vsec_init(xe);
>
> + err = xe_sriov_late_init(xe);
> + if (err)
> + goto err_unregister_display;
> +
> return devm_add_action_or_reset(xe->drm.dev, xe_device_sanitize, xe);
>
> err_unregister_display:
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index 6aca4b1a2824..1b52db967ace 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -22,6 +22,7 @@
> #include "xe_pmu_types.h"
> #include "xe_pt_types.h"
> #include "xe_sriov_types.h"
> +#include "xe_sriov_vf_ccs_types.h"
> #include "xe_step_types.h"
> #include "xe_survivability_mode_types.h"
> #include "xe_ttm_vram_mgr_types.h"
> @@ -235,6 +236,9 @@ struct xe_tile {
> struct {
> /** @sriov.vf.ggtt_balloon: GGTT regions excluded from use. */
> struct xe_ggtt_node *ggtt_balloon[2];
> +
> + /** @sriov.vf.ccs: CCS read and write contexts for VF. */
> + struct xe_tile_vf_ccs ccs[XE_SRIOV_VF_CCS_CTX_COUNT];
> } vf;
> } sriov;
>
> diff --git a/drivers/gpu/drm/xe/xe_gt_debugfs.c b/drivers/gpu/drm/xe/xe_gt_debugfs.c
> index 848618acdca8..404844515523 100644
> --- a/drivers/gpu/drm/xe/xe_gt_debugfs.c
> +++ b/drivers/gpu/drm/xe/xe_gt_debugfs.c
> @@ -134,6 +134,30 @@ static int sa_info(struct xe_gt *gt, struct drm_printer *p)
> return 0;
> }
>
> +static int sa_info_vf_ccs(struct xe_gt *gt, struct drm_printer *p)
> +{
> + struct xe_tile *tile = gt_to_tile(gt);
> + struct xe_sa_manager *bb_pool;
> + enum xe_sriov_vf_ccs_rw_ctxs ctx_id;
> +
This function will blow up on the non-root til as bb_pool will be unitialized.
> + if (!IS_VF_CCS_READY(gt_to_xe(gt)))
> + return 0;
> +
> + xe_pm_runtime_get(gt_to_xe(gt));
> +
> + for_each_ccs_rw_ctx(ctx_id) {
> + drm_printf(p, "ccs %s bb suballoc info\n", ctx_id ? "write" : "read");
> + drm_printf(p, "-------------------------\n");
> + bb_pool = tile->sriov.vf.ccs[ctx_id].mem.ccs_bb_pool;
An easy fix, if bb_pool is NULL skip the printing.
Other than that patch LGTM.
Matt
> + drm_suballoc_dump_debug_info(&bb_pool->base, p, bb_pool->gpu_addr);
> + drm_puts(p, "\n");
> + }
> +
> + xe_pm_runtime_put(gt_to_xe(gt));
> +
> + return 0;
> +}
> +
> static int topology(struct xe_gt *gt, struct drm_printer *p)
> {
> xe_pm_runtime_get(gt_to_xe(gt));
> @@ -303,6 +327,13 @@ static const struct drm_info_list vf_safe_debugfs_list[] = {
> {"hwconfig", .show = xe_gt_debugfs_simple_show, .data = hwconfig},
> };
>
> +/*
> + * only for GT debugfs files which are valid on VF. Not valid on PF.
> + */
> +static const struct drm_info_list vf_only_debugfs_list[] = {
> + {"sa_info_vf_ccs", .show = xe_gt_debugfs_simple_show, .data = sa_info_vf_ccs},
> +};
> +
> /* everything else should be added here */
> static const struct drm_info_list pf_only_debugfs_list[] = {
> {"hw_engines", .show = xe_gt_debugfs_simple_show, .data = hw_engines},
> @@ -419,6 +450,11 @@ void xe_gt_debugfs_register(struct xe_gt *gt)
> drm_debugfs_create_files(pf_only_debugfs_list,
> ARRAY_SIZE(pf_only_debugfs_list),
> root, minor);
> + else
> + drm_debugfs_create_files(vf_only_debugfs_list,
> + ARRAY_SIZE(vf_only_debugfs_list),
> + root, minor);
> +
>
> xe_uc_debugfs_register(>->uc, root);
>
> diff --git a/drivers/gpu/drm/xe/xe_sriov.c b/drivers/gpu/drm/xe/xe_sriov.c
> index a0eab44c0e76..87911fb4eea7 100644
> --- a/drivers/gpu/drm/xe/xe_sriov.c
> +++ b/drivers/gpu/drm/xe/xe_sriov.c
> @@ -15,6 +15,7 @@
> #include "xe_sriov.h"
> #include "xe_sriov_pf.h"
> #include "xe_sriov_vf.h"
> +#include "xe_sriov_vf_ccs.h"
>
> /**
> * xe_sriov_mode_to_string - Convert enum value to string.
> @@ -157,3 +158,21 @@ const char *xe_sriov_function_name(unsigned int n, char *buf, size_t size)
> strscpy(buf, "PF", size);
> return buf;
> }
> +
> +/**
> + * xe_sriov_late_init() - SR-IOV late initialization functions.
> + * @xe: the &xe_device to initialize
> + *
> + * On VF this function will initialize code for CCS migration.
> + *
> + * Return: 0 on success or a negative error code on failure.
> + */
> +int xe_sriov_late_init(struct xe_device *xe)
> +{
> + int err = 0;
> +
> + if (IS_VF_CCS_INIT_NEEDED(xe))
> + err = xe_sriov_vf_ccs_init(xe);
> +
> + return err;
> +}
> diff --git a/drivers/gpu/drm/xe/xe_sriov.h b/drivers/gpu/drm/xe/xe_sriov.h
> index 688fbabf08f1..0e0c1abf2d14 100644
> --- a/drivers/gpu/drm/xe/xe_sriov.h
> +++ b/drivers/gpu/drm/xe/xe_sriov.h
> @@ -18,6 +18,7 @@ const char *xe_sriov_function_name(unsigned int n, char *buf, size_t len);
> void xe_sriov_probe_early(struct xe_device *xe);
> void xe_sriov_print_info(struct xe_device *xe, struct drm_printer *p);
> int xe_sriov_init(struct xe_device *xe);
> +int xe_sriov_late_init(struct xe_device *xe);
>
> static inline enum xe_sriov_mode xe_device_sriov_mode(const struct xe_device *xe)
> {
> diff --git a/drivers/gpu/drm/xe/xe_sriov_types.h b/drivers/gpu/drm/xe/xe_sriov_types.h
> index ca94382a721e..8abfdb2c5ead 100644
> --- a/drivers/gpu/drm/xe/xe_sriov_types.h
> +++ b/drivers/gpu/drm/xe/xe_sriov_types.h
> @@ -71,6 +71,11 @@ struct xe_device_vf {
> /** @migration.gt_flags: Per-GT request flags for VF migration recovery */
> unsigned long gt_flags;
> } migration;
> +
> + struct {
> + /** @initialized: Initilalization of vf ccs is completed or not */
> + bool initialized;
> + } ccs;
> };
>
> #endif
> diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
> new file mode 100644
> index 000000000000..9000d618978d
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
> @@ -0,0 +1,208 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#include "instructions/xe_mi_commands.h"
> +#include "instructions/xe_gpu_commands.h"
> +#include "xe_bo.h"
> +#include "xe_device.h"
> +#include "xe_migrate.h"
> +#include "xe_sa.h"
> +#include "xe_sriov_printk.h"
> +#include "xe_sriov_vf_ccs.h"
> +#include "xe_sriov_vf_ccs_types.h"
> +
> +/**
> + * DOC: VF save/restore of compression Meta Data
> + *
> + * VF KMD registers two special contexts/LRCAs.
> + *
> + * Save Context/LRCA: contain necessary cmds+page table to trigger Meta data /
> + * compression control surface (Aka CCS) save in regular System memory in VM.
> + *
> + * Restore Context/LRCA: contain necessary cmds+page table to trigger Meta data /
> + * compression control surface (Aka CCS) Restore from regular System memory in
> + * VM to corresponding CCS pool.
> + *
> + * Below diagram explain steps needed for VF save/Restore of compression Meta Data::
> + *
> + * CCS Save CCS Restore VF KMD Guc BCS
> + * LRCA LRCA
> + * | | | | |
> + * | | | | |
> + * | Create Save LRCA | | |
> + * [ ]<----------------------------- [ ] | |
> + * | | | | |
> + * | | | | |
> + * | | | Register save LRCA | |
> + * | | | with Guc | |
> + * | | [ ]--------------------------->[ ] |
> + * | | | | |
> + * | | Create restore LRCA | | |
> + * | [ ]<------------------[ ] | |
> + * | | | | |
> + * | | | Register restore LRCA | |
> + * | | | with Guc | |
> + * | | [ ]--------------------------->[ ] |
> + * | | | | |
> + * | | | | |
> + * | | [ ]------------------------- | |
> + * | | [ ] Allocate main memory. | | |
> + * | | [ ] Allocate CCS memory. | | |
> + * | | [ ] Update Main memory & | | |
> + * [ ]<------------------------------[ ] CCS pages PPGTT + BB | | |
> + * | [ ]<------------------[ ] cmds to save & restore.| | |
> + * | | [ ]<------------------------ | |
> + * | | | | |
> + * | | | | |
> + * | | | | |
> + * : : : : :
> + * ---------------------------- VF Paused -------------------------------------
> + * | | | | |
> + * | | | | |
> + * | | | |Schedule |
> + * | | | |CCS Save |
> + * | | | | LRCA |
> + * | | | [ ]------>[ ]
> + * | | | | |
> + * | | | | |
> + * | | | |CCS save |
> + * | | | |completed|
> + * | | | [ ]<------[ ]
> + * | | | | |
> + * : : : : :
> + * ---------------------------- VM Migrated -----------------------------------
> + * | | | | |
> + * | | | | |
> + * : : : : :
> + * ---------------------------- VF Resumed ------------------------------------
> + * | | | | |
> + * | | | | |
> + * | | [ ]-------------- | |
> + * | | [ ] Fix up GGTT | | |
> + * | | [ ]<------------- | |
> + * | | | | |
> + * | | | | |
> + * | | | Notify VF_RESFIX_DONE | |
> + * | | [ ]--------------------------->[ ] |
> + * | | | | |
> + * | | | |Schedule |
> + * | | | |CCS |
> + * | | | |Restore |
> + * | | | |LRCA |
> + * | | | [ ]------>[ ]
> + * | | | | |
> + * | | | | |
> + * | | | |CCS |
> + * | | | |restore |
> + * | | | |completed|
> + * | | | [ ]<------[ ]
> + * | | | | |
> + * | | | | |
> + * | | | VF_RESFIX_DONE complete | |
> + * | | | notification | |
> + * | | [ ]<---------------------------[ ] |
> + * | | | | |
> + * | | | | |
> + * : : : : :
> + * ------------------------- Continue VM restore ------------------------------
> + */
> +
> +static u64 get_ccs_bb_pool_size(struct xe_device *xe)
> +{
> + u64 sys_mem_size, ccs_mem_size, ptes, bb_pool_size;
> + struct sysinfo si;
> +
> + si_meminfo(&si);
> + sys_mem_size = si.totalram * si.mem_unit;
> + ccs_mem_size = sys_mem_size / NUM_BYTES_PER_CCS_BYTE(xe);
> + ptes = DIV_ROUND_UP(sys_mem_size + ccs_mem_size, XE_PAGE_SIZE);
> +
> + /**
> + * We need below BB size to hold PTE mappings and some DWs for copy
> + * command. In reality, we need space for many copy commands. So, let
> + * us allocate double the calculated size which is enough to holds GPU
> + * instructions for the whole region.
> + */
> + bb_pool_size = ptes * sizeof(u32);
> +
> + return round_up(bb_pool_size * 2, SZ_1M);
> +}
> +
> +static int alloc_bb_pool(struct xe_tile *tile, struct xe_tile_vf_ccs *ctx)
> +{
> + struct xe_device *xe = tile_to_xe(tile);
> + struct xe_sa_manager *sa_manager;
> + u64 bb_pool_size;
> + int offset, err;
> +
> + bb_pool_size = get_ccs_bb_pool_size(xe);
> + xe_sriov_info(xe, "Allocating %s CCS BB pool size = %lldMB\n",
> + ctx->ctx_id ? "Restore" : "Save", bb_pool_size / SZ_1M);
> +
> + sa_manager = xe_sa_bo_manager_init(tile, bb_pool_size, SZ_16);
> +
> + if (IS_ERR(sa_manager)) {
> + xe_sriov_err(xe, "Suballocator init failed with error: %pe\n",
> + sa_manager);
> + err = PTR_ERR(sa_manager);
> + return err;
> + }
> +
> + offset = 0;
> + xe_map_memset(xe, &sa_manager->bo->vmap, offset, MI_NOOP,
> + bb_pool_size);
> +
> + offset = bb_pool_size - sizeof(u32);
> + xe_map_wr(xe, &sa_manager->bo->vmap, offset, u32, MI_BATCH_BUFFER_END);
> +
> + ctx->mem.ccs_bb_pool = sa_manager;
> +
> + return 0;
> +}
> +
> +/**
> + * xe_sriov_vf_ccs_init - Setup LRCA for save & restore.
> + * @xe: the &xe_device to start recovery on
> + *
> + * This function shall be called only by VF. It initializes
> + * LRCA and suballocator needed for CCS save & restore.
> + *
> + * Return: 0 on success. Negative error code on failure.
> + */
> +int xe_sriov_vf_ccs_init(struct xe_device *xe)
> +{
> + struct xe_tile *tile = xe_device_get_root_tile(xe);
> + enum xe_sriov_vf_ccs_rw_ctxs ctx_id;
> + struct xe_migrate *migrate;
> + struct xe_tile_vf_ccs *ctx;
> + int err;
> +
> + xe_assert(xe, IS_SRIOV_VF(xe));
> + xe_assert(xe, !IS_DGFX(xe));
> + xe_assert(xe, xe_device_has_flat_ccs(xe));
> +
> + for_each_ccs_rw_ctx(ctx_id) {
> + ctx = &tile->sriov.vf.ccs[ctx_id];
> + ctx->ctx_id = ctx_id;
> +
> + migrate = xe_migrate_init(tile);
> + if (IS_ERR(migrate)) {
> + err = PTR_ERR(migrate);
> + goto err_ret;
> + }
> + ctx->migrate = migrate;
> +
> + err = alloc_bb_pool(tile, ctx);
> + if (err)
> + goto err_ret;
> + }
> +
> + xe->sriov.vf.ccs.initialized = 1;
> +
> + return 0;
> +
> +err_ret:
> + return err;
> +}
> diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.h b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.h
> new file mode 100644
> index 000000000000..5df9ba028d14
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.h
> @@ -0,0 +1,13 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#ifndef _XE_SRIOV_VF_CCS_H_
> +#define _XE_SRIOV_VF_CCS_H_
> +
> +struct xe_device;
> +
> +int xe_sriov_vf_ccs_init(struct xe_device *xe);
> +
> +#endif
> diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h b/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h
> new file mode 100644
> index 000000000000..6dc279d206ec
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h
> @@ -0,0 +1,45 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#ifndef _XE_SRIOV_VF_CCS_TYPES_H_
> +#define _XE_SRIOV_VF_CCS_TYPES_H_
> +
> +#define for_each_ccs_rw_ctx(id__) \
> + for ((id__) = 0; (id__) < XE_SRIOV_VF_CCS_CTX_COUNT; (id__)++)
> +
> +#define IS_VF_CCS_READY(xe) ({ \
> + struct xe_device *___xe = (xe); \
> + xe_assert(___xe, IS_SRIOV_VF(___xe)); \
> + ___xe->sriov.vf.ccs.initialized; \
> + })
> +
> +#define IS_VF_CCS_INIT_NEEDED(xe) ({\
> + struct xe_device *___xe = (xe); \
> + IS_SRIOV_VF(___xe) && !IS_DGFX(___xe) && \
> + xe_device_has_flat_ccs(___xe) && GRAPHICS_VER(___xe) >= 20; \
> + })
> +
> +enum xe_sriov_vf_ccs_rw_ctxs {
> + XE_SRIOV_VF_CCS_READ_CTX,
> + XE_SRIOV_VF_CCS_WRITE_CTX,
> + XE_SRIOV_VF_CCS_CTX_COUNT
> +};
> +
> +struct xe_migrate;
> +struct xe_sa_manager;
> +
> +struct xe_tile_vf_ccs {
> + /** @id: Id to which context it belongs to */
> + enum xe_sriov_vf_ccs_rw_ctxs ctx_id;
> + /** @migrate: Migration helper for save/restore of CCS data */
> + struct xe_migrate *migrate;
> +
> + struct {
> + /** @ccs_rw_bb_pool: Pool from which batch buffers are allocated. */
> + struct xe_sa_manager *ccs_bb_pool;
> + } mem;
> +};
> +
> +#endif
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* ✓ Xe.CI.BAT: success for CCS save restore for IGPU (rev9)
2025-06-24 10:00 [PATCH v9 0/3] CCS save restore for IGPU Satyanarayana K V P
` (4 preceding siblings ...)
2025-06-24 15:10 ` ✓ CI.KUnit: success " Patchwork
@ 2025-06-24 15:46 ` Patchwork
2025-06-25 10:02 ` ✗ Xe.CI.Full: failure " Patchwork
6 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2025-06-24 15:46 UTC (permalink / raw)
To: Satyanarayana K V P; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 986 bytes --]
== Series Details ==
Series: CCS save restore for IGPU (rev9)
URL : https://patchwork.freedesktop.org/series/149108/
State : success
== Summary ==
CI Bug Log - changes from xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201_BAT -> xe-pw-149108v9_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (9 -> 8)
------------------------------
Missing (1): bat-adlp-vm
Changes
-------
No changes found
Build changes
-------------
* IGT: IGT_8423 -> IGT_8424
* Linux: xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201 -> xe-pw-149108v9
IGT_8423: 8423
IGT_8424: 68588b3c89a1bbe08c54d21c4d3d2e509957c795 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201: fb5dada21e3cfa26179ca58e1d7c26cdad217201
xe-pw-149108v9: 149108v9
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/index.html
[-- Attachment #2: Type: text/html, Size: 1548 bytes --]
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v9 2/3] drm/xe/vf: Attach and detach CCS copy commands with BO
2025-06-24 10:00 ` [PATCH v9 2/3] drm/xe/vf: Attach and detach CCS copy commands with BO Satyanarayana K V P
@ 2025-06-24 16:02 ` Matthew Brost
0 siblings, 0 replies; 13+ messages in thread
From: Matthew Brost @ 2025-06-24 16:02 UTC (permalink / raw)
To: Satyanarayana K V P
Cc: intel-xe, Michal Wajdeczko, Matthew Auld, Michał Winiarski,
Tomasz Lis
On Tue, Jun 24, 2025 at 03:30:09PM +0530, Satyanarayana K V P wrote:
> Attach CCS read/write copy commands to BO for old and new mem types as
> NULL -> tt or system -> tt.
> Detach the CCS read/write copy commands from BO while deleting ttm bo
> from xe_ttm_bo_delete_mem_notify().
>
> Signed-off-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Cc: Michał Winiarski <michal.winiarski@intel.com>
> ---
> Cc: Tomasz Lis <tomasz.lis@intel.com>
>
> V8 -> V9:
> - Removed MI_INVALIDATE_TLB after emitting PTEs (Matthew Brost).
> - Fixed review comments (Matthew Brost)
>
> V7 -> V8:
> - Removed xe_bb_ccs_realloc() and created a single BB by calculating the
> BB size first and then emitting the commands. (Matthew Brost)
> - Added xe_assert() if BB is not NULL in xe_sriov_vf_ccs_attach_bo().
>
> V6 -> V7:
> - Created xe_bb_ccs_realloc() to create a single BB instead of maintaining
> a list. (Matthew Brost)
>
> V5 -> V6:
> - Removed dead code from xe_migrate_ccs_rw_copy() function. (Matthew Brost)
>
> V4 -> V5:
> - Create a list of BBs for the given BO and fixed memory leak while
> detaching BOs. (Matthew Brost).
> - Fixed review comments (Matthew Brost & Matthew Auld).
> - Yet to cleanup xe_migrate_ccs_rw_copy() function.
>
> V3 -> V4:
> - Fixed issues reported by patchworks.
>
> V2 -> V3:
> - Attach and detach functions check for IS_VF_CCS_READY().
>
> V1 -> V2:
> - Fixed review comments.
> ---
> drivers/gpu/drm/xe/xe_bb.c | 35 ++++++
> drivers/gpu/drm/xe/xe_bb.h | 3 +
> drivers/gpu/drm/xe/xe_bo.c | 23 ++++
> drivers/gpu/drm/xe/xe_bo_types.h | 3 +
> drivers/gpu/drm/xe/xe_migrate.c | 129 +++++++++++++++++++++
> drivers/gpu/drm/xe/xe_migrate.h | 6 +
> drivers/gpu/drm/xe/xe_sriov_vf_ccs.c | 67 +++++++++++
> drivers/gpu/drm/xe/xe_sriov_vf_ccs.h | 3 +
> drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h | 8 ++
> 9 files changed, 277 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/xe_bb.c b/drivers/gpu/drm/xe/xe_bb.c
> index 9570672fce33..533352dc892f 100644
> --- a/drivers/gpu/drm/xe/xe_bb.c
> +++ b/drivers/gpu/drm/xe/xe_bb.c
> @@ -60,6 +60,41 @@ struct xe_bb *xe_bb_new(struct xe_gt *gt, u32 dwords, bool usm)
> return ERR_PTR(err);
> }
>
> +struct xe_bb *xe_bb_ccs_new(struct xe_gt *gt, u32 dwords,
> + enum xe_sriov_vf_ccs_rw_ctxs ctx_id)
> +{
> + struct xe_bb *bb = kmalloc(sizeof(*bb), GFP_KERNEL);
> + struct xe_tile *tile = gt_to_tile(gt);
> + struct xe_sa_manager *bb_pool;
> + int err;
> +
> + if (!bb)
> + return ERR_PTR(-ENOMEM);
> + /*
> + * We need to allocate space for the requested number of dwords &
> + * one additional MI_BATCH_BUFFER_END dword. Since the whole SA
> + * is submitted to HW, we need to make sure that the last instruction
> + * is not over written when the last chunk of SA is allocated for BB.
> + * So, this extra DW acts as a guard here.
> + */
> +
> + bb_pool = tile->sriov.vf.ccs[ctx_id].mem.ccs_bb_pool;
> + bb->bo = xe_sa_bo_new(bb_pool, 4 * (dwords + 1));
> +
> + if (IS_ERR(bb->bo)) {
> + err = PTR_ERR(bb->bo);
> + goto err;
> + }
> +
> + bb->cs = xe_sa_bo_cpu_addr(bb->bo);
> + bb->len = 0;
> +
> + return bb;
> +err:
> + kfree(bb);
> + return ERR_PTR(err);
> +}
> +
> static struct xe_sched_job *
> __xe_bb_create_job(struct xe_exec_queue *q, struct xe_bb *bb, u64 *addr)
> {
> diff --git a/drivers/gpu/drm/xe/xe_bb.h b/drivers/gpu/drm/xe/xe_bb.h
> index fafacd73dcc3..32c9c4c5d2be 100644
> --- a/drivers/gpu/drm/xe/xe_bb.h
> +++ b/drivers/gpu/drm/xe/xe_bb.h
> @@ -13,8 +13,11 @@ struct dma_fence;
> struct xe_gt;
> struct xe_exec_queue;
> struct xe_sched_job;
> +enum xe_sriov_vf_ccs_rw_ctxs;
>
> struct xe_bb *xe_bb_new(struct xe_gt *gt, u32 size, bool usm);
> +struct xe_bb *xe_bb_ccs_new(struct xe_gt *gt, u32 dwords,
> + enum xe_sriov_vf_ccs_rw_ctxs ctx_id);
> struct xe_sched_job *xe_bb_create_job(struct xe_exec_queue *q,
> struct xe_bb *bb);
> struct xe_sched_job *xe_bb_create_migration_job(struct xe_exec_queue *q,
> diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
> index 4e39188a021a..beaf8544bf08 100644
> --- a/drivers/gpu/drm/xe/xe_bo.c
> +++ b/drivers/gpu/drm/xe/xe_bo.c
> @@ -31,6 +31,7 @@
> #include "xe_pxp.h"
> #include "xe_res_cursor.h"
> #include "xe_shrinker.h"
> +#include "xe_sriov_vf_ccs.h"
> #include "xe_trace_bo.h"
> #include "xe_ttm_stolen_mgr.h"
> #include "xe_vm.h"
> @@ -947,6 +948,20 @@ static int xe_bo_move(struct ttm_buffer_object *ttm_bo, bool evict,
> dma_fence_put(fence);
> xe_pm_runtime_put(xe);
>
> + /*
> + * CCS meta data is migrated from TT -> SMEM. So, let us detach the
> + * BBs from BO as it is no longer needed.
> + */
> + if (IS_VF_CCS_BB_VALID(xe, bo) && old_mem_type == XE_PL_TT &&
> + new_mem->mem_type == XE_PL_SYSTEM)
> + xe_sriov_vf_ccs_detach_bo(bo);
> +
> + if (IS_SRIOV_VF(xe) &&
> + ((move_lacks_source && new_mem->mem_type == XE_PL_TT) ||
> + (old_mem_type == XE_PL_SYSTEM && new_mem->mem_type == XE_PL_TT)) &&
> + handle_system_ccs)
> + ret = xe_sriov_vf_ccs_attach_bo(bo);
> +
> out:
> if ((!ttm_bo->resource || ttm_bo->resource->mem_type == XE_PL_SYSTEM) &&
> ttm_bo->ttm) {
> @@ -957,6 +972,9 @@ static int xe_bo_move(struct ttm_buffer_object *ttm_bo, bool evict,
> if (timeout < 0)
> ret = timeout;
>
> + if (IS_VF_CCS_BB_VALID(xe, bo))
> + xe_sriov_vf_ccs_detach_bo(bo);
> +
> xe_tt_unmap_sg(xe, ttm_bo->ttm);
> }
>
> @@ -1483,9 +1501,14 @@ static void xe_ttm_bo_release_notify(struct ttm_buffer_object *ttm_bo)
>
> static void xe_ttm_bo_delete_mem_notify(struct ttm_buffer_object *ttm_bo)
> {
> + struct xe_bo *bo = ttm_to_xe_bo(ttm_bo);
> +
> if (!xe_bo_is_xe_bo(ttm_bo))
> return;
>
> + if (IS_VF_CCS_BB_VALID(ttm_to_xe_device(ttm_bo->bdev), bo))
> + xe_sriov_vf_ccs_detach_bo(bo);
> +
> /*
> * Object is idle and about to be destroyed. Release the
> * dma-buf attachment.
> diff --git a/drivers/gpu/drm/xe/xe_bo_types.h b/drivers/gpu/drm/xe/xe_bo_types.h
> index eb5e83c5f233..642e519fcfd1 100644
> --- a/drivers/gpu/drm/xe/xe_bo_types.h
> +++ b/drivers/gpu/drm/xe/xe_bo_types.h
> @@ -78,6 +78,9 @@ struct xe_bo {
> /** @ccs_cleared */
> bool ccs_cleared;
>
> + /** @bb_ccs_rw: BB instructions of CCS read/write. Valid only for VF */
> + struct xe_bb *bb_ccs[XE_SRIOV_VF_CCS_CTX_COUNT];
> +
> /**
> * @cpu_caching: CPU caching mode. Currently only used for userspace
> * objects. Exceptions are system memory on DGFX, which is always
> diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
> index 8f8e9fdfb2a8..72f342924ad2 100644
> --- a/drivers/gpu/drm/xe/xe_migrate.c
> +++ b/drivers/gpu/drm/xe/xe_migrate.c
> @@ -940,6 +940,135 @@ struct dma_fence *xe_migrate_copy(struct xe_migrate *m,
> return fence;
> }
>
> +/**
> + * xe_migrate_ccs_rw_copy() - Copy content of TTM resources.
> + * @m: The migration context.
> + * @src_bo: The buffer object @src is currently bound to.
> + * @read_write : Creates BB commands for CCS read/write.
> + *
> + * Creates batch buffer instructions to copy CCS metadata from CCS pool to
> + * memory and vice versa.
> + *
> + * This function should only be called for IGPU.
> + *
> + * Return: 0 if successful, negative error code on failure.
> + */
> +int xe_migrate_ccs_rw_copy(struct xe_migrate *m,
> + struct xe_bo *src_bo,
> + enum xe_sriov_vf_ccs_rw_ctxs read_write)
> +
> +{
> + bool src_is_pltt = read_write == XE_SRIOV_VF_CCS_WRITE_CTX;
> + bool dst_is_pltt = read_write == XE_SRIOV_VF_CCS_READ_CTX;
> + struct ttm_resource *src = src_bo->ttm.resource;
> + struct xe_gt *gt = m->tile->primary_gt;
> + u32 batch_size, batch_size_allocated;
> + struct xe_device *xe = gt_to_xe(gt);
> + struct xe_res_cursor src_it, ccs_it;
> + u64 size = src_bo->size;
> + struct xe_bb *bb = NULL;
> + u64 src_L0, src_L0_ofs;
> + u32 src_L0_pt;
> + int err;
> +
> + xe_res_first_sg(xe_bo_sg(src_bo), 0, size, &src_it);
> +
> + xe_res_first_sg(xe_bo_sg(src_bo), xe_bo_ccs_pages_start(src_bo),
> + PAGE_ALIGN(xe_device_ccs_bytes(xe, size)),
> + &ccs_it);
> +
> + /* Calculate Batch buffer size */
> + batch_size = 0;
> + while (size) {
> + batch_size += 6; /* Flush + 2 NOP */
> + u64 ccs_ofs, ccs_size;
> + u32 ccs_pt;
> +
> + u32 avail_pts = max_mem_transfer_per_pass(xe) / LEVEL0_PAGE_TABLE_ENCODE_SIZE;
> +
> + src_L0 = min_t(u64, max_mem_transfer_per_pass(xe), size);
> +
> + batch_size += pte_update_size(m, false, src, &src_it, &src_L0,
> + &src_L0_ofs, &src_L0_pt, 0, 0,
> + avail_pts);
> +
> + ccs_size = xe_device_ccs_bytes(xe, src_L0);
> + batch_size += pte_update_size(m, 0, NULL, &ccs_it, &ccs_size, &ccs_ofs,
> + &ccs_pt, 0, avail_pts, avail_pts);
> + xe_assert(xe, IS_ALIGNED(ccs_it.start, PAGE_SIZE));
> +
> + /* Add copy commands size here */
> + batch_size += EMIT_COPY_CCS_DW;
> +
> + size -= src_L0;
> + }
> +
> + bb = xe_bb_ccs_new(gt, batch_size, read_write);
> + if (IS_ERR(bb)) {
> + drm_err(&xe->drm, "BB allocation failed.\n");
> + err = PTR_ERR(bb);
> + goto err_ret;
> + }
> +
> + batch_size_allocated = batch_size;
> + size = src_bo->size;
> + batch_size = 0;
> +
> + /*
> + * Emit PTE and copy commands here.
> + * The CCS copy command can only support limited size. If the size to be
> + * copied is more than the limit, divide copy into chunks. So, calculate
> + * sizes here again before copy command is emitted.
> + */
> + while (size) {
> + batch_size += 6; /* Flush + 2 NOP */
> + u32 flush_flags = 0;
> + u64 ccs_ofs, ccs_size;
> + u32 ccs_pt;
> +
> + u32 avail_pts = max_mem_transfer_per_pass(xe) / LEVEL0_PAGE_TABLE_ENCODE_SIZE;
> +
> + src_L0 = xe_migrate_res_sizes(m, &src_it);
> +
> + batch_size += pte_update_size(m, false, src, &src_it, &src_L0,
> + &src_L0_ofs, &src_L0_pt, 0, 0,
> + avail_pts);
> +
> + ccs_size = xe_device_ccs_bytes(xe, src_L0);
> + batch_size += pte_update_size(m, 0, NULL, &ccs_it, &ccs_size, &ccs_ofs,
> + &ccs_pt, 0, avail_pts, avail_pts);
> + xe_assert(xe, IS_ALIGNED(ccs_it.start, PAGE_SIZE));
> + batch_size += EMIT_COPY_CCS_DW;
> +
> + emit_pte(m, bb, src_L0_pt, false, true, &src_it, src_L0, src);
> +
> + emit_pte(m, bb, ccs_pt, false, false, &ccs_it, ccs_size, src);
> +
> + bb->cs[bb->len++] = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_IMM_DW;
> + bb->cs[bb->len++] = MI_NOOP;
> + bb->cs[bb->len++] = MI_NOOP;
> +
> + flush_flags = xe_migrate_ccs_copy(m, bb, src_L0_ofs, src_is_pltt,
> + src_L0_ofs, dst_is_pltt,
> + src_L0, ccs_ofs, true);
> +
> + bb->cs[bb->len++] = MI_FLUSH_DW | MI_INVALIDATE_TLB | MI_FLUSH_DW_OP_STOREDW |
> + MI_FLUSH_IMM_DW | flush_flags;
> + bb->cs[bb->len++] = MI_NOOP;
> + bb->cs[bb->len++] = MI_NOOP;
> +
> + size -= src_L0;
> + }
> +
> + xe_assert(xe, (batch_size_allocated == bb->len));
> + src_bo->bb_ccs[read_write] = bb;
> +
> + return 0;
> +
> +err_ret:
> + return err;
> +}
> +
> static void emit_clear_link_copy(struct xe_gt *gt, struct xe_bb *bb, u64 src_ofs,
> u32 size, u32 pitch)
> {
> diff --git a/drivers/gpu/drm/xe/xe_migrate.h b/drivers/gpu/drm/xe/xe_migrate.h
> index fb9839c1bae0..96b0449e7edb 100644
> --- a/drivers/gpu/drm/xe/xe_migrate.h
> +++ b/drivers/gpu/drm/xe/xe_migrate.h
> @@ -24,6 +24,8 @@ struct xe_vm;
> struct xe_vm_pgtable_update;
> struct xe_vma;
>
> +enum xe_sriov_vf_ccs_rw_ctxs;
> +
> /**
> * struct xe_migrate_pt_update_ops - Callbacks for the
> * xe_migrate_update_pgtables() function.
> @@ -112,6 +114,10 @@ struct dma_fence *xe_migrate_copy(struct xe_migrate *m,
> struct ttm_resource *dst,
> bool copy_only_ccs);
>
> +int xe_migrate_ccs_rw_copy(struct xe_migrate *m,
> + struct xe_bo *src_bo,
> + enum xe_sriov_vf_ccs_rw_ctxs read_write);
> +
> int xe_migrate_access_memory(struct xe_migrate *m, struct xe_bo *bo,
> unsigned long offset, void *buf, int len,
> int write);
> diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
> index 9000d618978d..7fde8aab3e20 100644
> --- a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
> +++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
> @@ -5,6 +5,7 @@
>
> #include "instructions/xe_mi_commands.h"
> #include "instructions/xe_gpu_commands.h"
> +#include "xe_bb.h"
> #include "xe_bo.h"
> #include "xe_device.h"
> #include "xe_migrate.h"
> @@ -206,3 +207,69 @@ int xe_sriov_vf_ccs_init(struct xe_device *xe)
> err_ret:
> return err;
> }
> +
> +/**
> + * xe_sriov_vf_ccs_attach_bo - Insert CCS read write commands in the BO.
> + * @bo: the &buffer object to which batch buffer commands will be added.
> + *
> + * This function shall be called only by VF. It inserts the PTEs and copy
> + * command instructions in the BO by calling xe_migrate_ccs_rw_copy()
> + * function.
> + *
> + * Returns: 0 if successful, negative error code on failure.
> + */
> +int xe_sriov_vf_ccs_attach_bo(struct xe_bo *bo)
> +{
> + struct xe_device *xe = xe_bo_device(bo);
> + enum xe_sriov_vf_ccs_rw_ctxs ctx_id;
> + struct xe_migrate *migrate;
> + struct xe_tile *tile;
> + struct xe_bb *bb;
> + int err = 0;
> +
> + if (!IS_VF_CCS_READY(xe))
> + return 0;
> +
> + tile = xe_device_get_root_tile(xe);
> +
> + for_each_ccs_rw_ctx(ctx_id) {
> + bb = bo->bb_ccs[ctx_id];
> + /* bb should be NULL here. Assert if not NULL */
> + xe_assert(xe, !bb);
> +
> + migrate = tile->sriov.vf.ccs[ctx_id].migrate;
> + err = xe_migrate_ccs_rw_copy(migrate, bo, ctx_id);
> + }
> + return err;
> +}
> +
> +/**
> + * xe_sriov_vf_ccs_detach_bo - Remove CCS read write commands from the BO.
> + * @bo: the &buffer object from which batch buffer commands will be removed.
> + *
> + * This function shall be called only by VF. It removes the PTEs and copy
> + * command instructions from the BO. Make sure to update the BB with MI_NOOP
> + * before freeing.
> + *
> + * Returns: 0 if successful.
> + */
> +int xe_sriov_vf_ccs_detach_bo(struct xe_bo *bo)
> +{
> + struct xe_device *xe = xe_bo_device(bo);
> + enum xe_sriov_vf_ccs_rw_ctxs ctx_id;
> + struct xe_bb *bb;
> +
> + if (!IS_VF_CCS_READY(xe))
> + return 0;
> +
> + for_each_ccs_rw_ctx(ctx_id) {
> + bb = bo->bb_ccs[ctx_id];
> + if (!bb)
> + continue;
> +
> + memset(bb->cs, MI_NOOP, bb->len * sizeof(u32));
> + xe_bb_free(bb, NULL);
> + bo->bb_ccs[ctx_id] = NULL;
> + }
> + return 0;
> +}
> diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.h b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.h
> index 5df9ba028d14..5d5e4bd25904 100644
> --- a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.h
> +++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.h
> @@ -7,7 +7,10 @@
> #define _XE_SRIOV_VF_CCS_H_
>
> struct xe_device;
> +struct xe_bo;
>
> int xe_sriov_vf_ccs_init(struct xe_device *xe);
> +int xe_sriov_vf_ccs_attach_bo(struct xe_bo *bo);
> +int xe_sriov_vf_ccs_detach_bo(struct xe_bo *bo);
>
> #endif
> diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h b/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h
> index 6dc279d206ec..e240f3fd18af 100644
> --- a/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h
> +++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h
> @@ -27,6 +27,14 @@ enum xe_sriov_vf_ccs_rw_ctxs {
> XE_SRIOV_VF_CCS_CTX_COUNT
> };
>
> +#define IS_VF_CCS_BB_VALID(xe, bo) ({ \
> + struct xe_device *___xe = (xe); \
> + struct xe_bo *___bo = (bo); \
> + IS_SRIOV_VF(___xe) && \
> + ___bo->bb_ccs[XE_SRIOV_VF_CCS_READ_CTX] && \
> + ___bo->bb_ccs[XE_SRIOV_VF_CCS_WRITE_CTX]; \
> + })
> +
> struct xe_migrate;
> struct xe_sa_manager;
>
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v9 3/3] drm/xe/vf: Register CCS read/write contexts with Guc
2025-06-24 10:00 ` [PATCH v9 3/3] drm/xe/vf: Register CCS read/write contexts with Guc Satyanarayana K V P
@ 2025-06-24 16:07 ` Matthew Brost
0 siblings, 0 replies; 13+ messages in thread
From: Matthew Brost @ 2025-06-24 16:07 UTC (permalink / raw)
To: Satyanarayana K V P
Cc: intel-xe, Michal Wajdeczko, Maarten Lankhorst,
Michał Winiarski, Tomasz Lis, Matthew Auld
On Tue, Jun 24, 2025 at 03:30:10PM +0530, Satyanarayana K V P wrote:
> Register read write contexts with newly added flags with GUC and
> enable the context immediately after registration.
> Re-register the context with Guc when resuming from runtime suspend as
> soft reset is applied to Guc during xe_pm_runtime_resume().
> Make Ring head=tail while unbinding device to avoid issues with VF pause
> after device is unbinded.
>
> Signed-off-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> ---
> Cc: Michał Winiarski <michal.winiarski@intel.com>
> Cc: Tomasz Lis <tomasz.lis@intel.com>
> Cc: Matthew Auld <matthew.auld@intel.com>
>
> V8 -> V9:
> - Fixed review comments (Matthew Brost).
>
> V7 -> V8:
> -None.
>
> V6 -> V7:
> - Fixed review comments (Matthew Brost).
> - Replaced xe_tile_migrate_exec_queue() with xe_migrate_exec_queue() as per
> review comments (Matthew Brost).
>
> V5 -> V6:
> - None
>
> V4 -> V5:
> - Fixed review comments (Matthew Brost).
>
> V3 -> V4:
> - Fixed issues reported by patchworks.
>
> V2 -> V3:
> - Made xe_migrate structure private as per review comments.
> - Created new xe_migrate functions to get lrc and exec_queue.
>
> V1 -> V2:
> - Fixed review comments.
> ---
> drivers/gpu/drm/xe/xe_guc_fwif.h | 5 ++
> drivers/gpu/drm/xe/xe_guc_submit.c | 34 ++++++++++-
> drivers/gpu/drm/xe/xe_guc_submit.h | 1 +
> drivers/gpu/drm/xe/xe_migrate.c | 35 +++++++----
> drivers/gpu/drm/xe/xe_migrate.h | 4 +-
> drivers/gpu/drm/xe/xe_pm.c | 4 ++
> drivers/gpu/drm/xe/xe_sriov_vf_ccs.c | 91 ++++++++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_sriov_vf_ccs.h | 1 +
> drivers/gpu/drm/xe/xe_vm.c | 6 +-
> 9 files changed, 161 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h
> index 6f57578b07cb..ca9f999d38d1 100644
> --- a/drivers/gpu/drm/xe/xe_guc_fwif.h
> +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
> @@ -45,6 +45,11 @@
> #define GUC_MAX_ENGINE_CLASSES 16
> #define GUC_MAX_INSTANCES_PER_CLASS 32
>
> +#define GUC_CONTEXT_NORMAL 0
> +#define GUC_CONTEXT_COMPRESSION_SAVE 1
> +#define GUC_CONTEXT_COMPRESSION_RESTORE 2
> +#define GUC_CONTEXT_COUNT (GUC_CONTEXT_COMPRESSION_RESTORE + 1)
> +
> /* Helper for context registration H2G */
> struct guc_ctxt_registration_info {
> u32 flags;
> diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
> index df7a5a4eec74..f17a63ea06e9 100644
> --- a/drivers/gpu/drm/xe/xe_guc_submit.c
> +++ b/drivers/gpu/drm/xe/xe_guc_submit.c
> @@ -542,7 +542,7 @@ static void __register_exec_queue(struct xe_guc *guc,
> xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action), 0, 0);
> }
>
> -static void register_exec_queue(struct xe_exec_queue *q)
> +static void register_exec_queue(struct xe_exec_queue *q, int ctx_type)
> {
> struct xe_guc *guc = exec_queue_to_guc(q);
> struct xe_device *xe = guc_to_xe(guc);
> @@ -550,6 +550,7 @@ static void register_exec_queue(struct xe_exec_queue *q)
> struct guc_ctxt_registration_info info;
>
> xe_gt_assert(guc_to_gt(guc), !exec_queue_registered(q));
> + xe_gt_assert(guc_to_gt(guc), ctx_type < GUC_CONTEXT_COUNT);
>
> memset(&info, 0, sizeof(info));
> info.context_idx = q->guc->id;
> @@ -559,6 +560,9 @@ static void register_exec_queue(struct xe_exec_queue *q)
> info.hwlrca_hi = upper_32_bits(xe_lrc_descriptor(lrc));
> info.flags = CONTEXT_REGISTRATION_FLAG_KMD;
>
> + if (ctx_type != GUC_CONTEXT_NORMAL)
> + info.flags |= BIT(ctx_type);
> +
> if (xe_exec_queue_is_parallel(q)) {
> u64 ggtt_addr = xe_lrc_parallel_ggtt_addr(lrc);
> struct iosys_map map = xe_lrc_parallel_map(lrc);
> @@ -761,7 +765,7 @@ guc_exec_queue_run_job(struct drm_sched_job *drm_job)
>
> if (!exec_queue_killed_or_banned_or_wedged(q) && !xe_sched_job_is_error(job)) {
> if (!exec_queue_registered(q))
> - register_exec_queue(q);
> + register_exec_queue(q, GUC_CONTEXT_NORMAL);
> if (!lr) /* LR jobs are emitted in the exec IOCTL */
> q->ring_ops->emit_job(job);
> submit_exec_queue(q);
> @@ -2366,6 +2370,32 @@ static void guc_exec_queue_print(struct xe_exec_queue *q, struct drm_printer *p)
> xe_guc_exec_queue_snapshot_free(snapshot);
> }
>
> +/**
> + * xe_guc_register_exec_queue - Register exec queue for a given context type.
> + * @q - Execution queue
> + * @ctx_type - Type of the context
> + *
> + * This function registers the execution queue with the guc. Special context
> + * types like GUC_CONTEXT_COMPRESSION_SAVE and GUC_CONTEXT_COMPRESSION_RESTORE
> + * are only applicable for IGPU and in the VF.
> + * Submits the execution queue to GUC after registering it.
> + *
> + * Returns - None.
> + */
> +void xe_guc_register_exec_queue(struct xe_exec_queue *q, int ctx_type)
> +{
> + struct xe_guc *guc = exec_queue_to_guc(q);
> + struct xe_device *xe = guc_to_xe(guc);
> +
> + xe_assert(xe, IS_SRIOV_VF(xe));
> + xe_assert(xe, !IS_DGFX(xe));
> + xe_assert(xe, (ctx_type > GUC_CONTEXT_NORMAL &&
> + ctx_type < GUC_CONTEXT_COUNT));
> +
> + register_exec_queue(q, ctx_type);
> + enable_scheduling(q);
> +}
> +
> /**
> * xe_guc_submit_print - GuC Submit Print.
> * @guc: GuC.
> diff --git a/drivers/gpu/drm/xe/xe_guc_submit.h b/drivers/gpu/drm/xe/xe_guc_submit.h
> index 9b71a986c6ca..8f64e799283b 100644
> --- a/drivers/gpu/drm/xe/xe_guc_submit.h
> +++ b/drivers/gpu/drm/xe/xe_guc_submit.h
> @@ -39,5 +39,6 @@ xe_guc_exec_queue_snapshot_print(struct xe_guc_submit_exec_queue_snapshot *snaps
> void
> xe_guc_exec_queue_snapshot_free(struct xe_guc_submit_exec_queue_snapshot *snapshot);
> void xe_guc_submit_print(struct xe_guc *guc, struct drm_printer *p);
> +void xe_guc_register_exec_queue(struct xe_exec_queue *q, int ctx_type);
>
> #endif
> diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
> index 72f342924ad2..277221f005f7 100644
> --- a/drivers/gpu/drm/xe/xe_migrate.c
> +++ b/drivers/gpu/drm/xe/xe_migrate.c
> @@ -84,19 +84,6 @@ struct xe_migrate {
> */
> #define MAX_PTE_PER_SDI 0x1FE
>
> -/**
> - * xe_tile_migrate_exec_queue() - Get this tile's migrate exec queue.
> - * @tile: The tile.
> - *
> - * Returns the default migrate exec queue of this tile.
> - *
> - * Return: The default migrate exec queue
> - */
> -struct xe_exec_queue *xe_tile_migrate_exec_queue(struct xe_tile *tile)
> -{
> - return tile->migrate->q;
> -}
> -
> static void xe_migrate_fini(void *arg)
> {
> struct xe_migrate *m = arg;
> @@ -1069,6 +1056,28 @@ int xe_migrate_ccs_rw_copy(struct xe_migrate *m,
> return err;
> }
>
> +/**
> + * xe_get_migrate_lrc() - Get the LRC from migrate context.
> + * @migrate: Migrate context.
> + *
> + * Return: Pointer to LRC on success, error on failure
> + */
> +struct xe_lrc *xe_migrate_lrc(struct xe_migrate *migrate)
> +{
> + return migrate->q->lrc[0];
> +}
> +
> +/**
> + * xe_get_migrate_exec_queue() - Get the execution queue from migrate context.
> + * @migrate: Migrate context.
> + *
> + * Return: Pointer to execution queue on success, error on failure
> + */
> +struct xe_exec_queue *xe_migrate_exec_queue(struct xe_migrate *migrate)
> +{
> + return migrate->q;
> +}
> +
> static void emit_clear_link_copy(struct xe_gt *gt, struct xe_bb *bb, u64 src_ofs,
> u32 size, u32 pitch)
> {
> diff --git a/drivers/gpu/drm/xe/xe_migrate.h b/drivers/gpu/drm/xe/xe_migrate.h
> index 96b0449e7edb..3754d9e6150f 100644
> --- a/drivers/gpu/drm/xe/xe_migrate.h
> +++ b/drivers/gpu/drm/xe/xe_migrate.h
> @@ -118,6 +118,8 @@ int xe_migrate_ccs_rw_copy(struct xe_migrate *m,
> struct xe_bo *src_bo,
> enum xe_sriov_vf_ccs_rw_ctxs read_write);
>
> +struct xe_lrc *xe_migrate_lrc(struct xe_migrate *migrate);
> +struct xe_exec_queue *xe_migrate_exec_queue(struct xe_migrate *migrate);
> int xe_migrate_access_memory(struct xe_migrate *m, struct xe_bo *bo,
> unsigned long offset, void *buf, int len,
> int write);
> @@ -138,6 +140,4 @@ xe_migrate_update_pgtables(struct xe_migrate *m,
> struct xe_migrate_pt_update *pt_update);
>
> void xe_migrate_wait(struct xe_migrate *m);
> -
> -struct xe_exec_queue *xe_tile_migrate_exec_queue(struct xe_tile *tile);
> #endif
> diff --git a/drivers/gpu/drm/xe/xe_pm.c b/drivers/gpu/drm/xe/xe_pm.c
> index 26e95460af87..6c32412126d7 100644
> --- a/drivers/gpu/drm/xe/xe_pm.c
> +++ b/drivers/gpu/drm/xe/xe_pm.c
> @@ -22,6 +22,7 @@
> #include "xe_irq.h"
> #include "xe_pcode.h"
> #include "xe_pxp.h"
> +#include "xe_sriov_vf_ccs.h"
> #include "xe_trace.h"
> #include "xe_wa.h"
>
> @@ -546,6 +547,9 @@ int xe_pm_runtime_resume(struct xe_device *xe)
>
> xe_pxp_pm_resume(xe->pxp);
>
> + if (IS_SRIOV_VF(xe))
> + xe_sriov_vf_ccs_register_context(xe);
> +
> out:
> xe_rpm_lockmap_release(xe);
> xe_pm_write_callback_task(xe, NULL);
> diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
> index 7fde8aab3e20..d2f4a2674f4d 100644
> --- a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
> +++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
> @@ -8,6 +8,9 @@
> #include "xe_bb.h"
> #include "xe_bo.h"
> #include "xe_device.h"
> +#include "xe_exec_queue_types.h"
> +#include "xe_guc_submit.h"
> +#include "xe_lrc.h"
> #include "xe_migrate.h"
> #include "xe_sa.h"
> #include "xe_sriov_printk.h"
> @@ -163,6 +166,84 @@ static int alloc_bb_pool(struct xe_tile *tile, struct xe_tile_vf_ccs *ctx)
> return 0;
> }
>
> +static void ccs_rw_update_ring(struct xe_tile_vf_ccs *ctx)
> +{
> + struct xe_lrc *lrc = xe_migrate_lrc(ctx->migrate);
> + u32 addr = ctx->mem.ccs_bb_pool->gpu_addr;
> + u32 dw[10], i = 0;
> +
> + dw[i++] = MI_ARB_ON_OFF | MI_ARB_DISABLE;
> + dw[i++] = MI_BATCH_BUFFER_START | XE_INSTR_NUM_DW(3);
> + dw[i++] = addr;
> + dw[i++] = 0;
> + dw[i++] = MI_NOOP;
> + dw[i++] = MI_NOOP;
> +
> + xe_lrc_write_ring(lrc, dw, i * sizeof(u32));
> +}
> +
> +static int register_save_restore_context(struct xe_migrate *m,
> + enum xe_sriov_vf_ccs_rw_ctxs ctx_id)
> +{
> + int err = -EINVAL;
> + int ctx_type;
> +
> + switch (ctx_id) {
> + case XE_SRIOV_VF_CCS_READ_CTX:
> + ctx_type = GUC_CONTEXT_COMPRESSION_SAVE;
> + break;
> + case XE_SRIOV_VF_CCS_WRITE_CTX:
> + ctx_type = GUC_CONTEXT_COMPRESSION_RESTORE;
> + break;
> + default:
> + return err;
> + }
> +
> + xe_guc_register_exec_queue(xe_migrate_exec_queue(m), ctx_type);
> + return 0;
> +}
> +
> +/**
> + * xe_sriov_vf_ccs_register_context - Register read/write contexts with guc.
> + * @xe: the &xe_device to register contexts on.
> + *
> + * This function registers read and write contexts with Guc. Re-registration
> + * is needed whenever resuming from pm runtime suspend.
> + *
> + * Return: 0 on success. Negative error code on failure.
> + */
> +int xe_sriov_vf_ccs_register_context(struct xe_device *xe)
> +{
> + struct xe_tile *tile = xe_device_get_root_tile(xe);
> + enum xe_sriov_vf_ccs_rw_ctxs ctx_id;
> + struct xe_tile_vf_ccs *ctx;
> + int err;
> +
> + if (!IS_VF_CCS_READY(xe))
> + return 0;
> +
> + for_each_ccs_rw_ctx(ctx_id) {
> + ctx = &tile->sriov.vf.ccs[ctx_id];
> + err = register_save_restore_context(ctx->migrate, ctx_id);
> + if (err)
> + return err;
> + }
> +
> + return err;
> +}
> +
> +static void xe_sriov_vf_ccs_fini(void *arg)
> +{
> + struct xe_tile_vf_ccs *ctx = arg;
> + struct xe_lrc *lrc = xe_migrate_lrc(ctx->migrate);
> +
> + /*
> + * Make TAIL = HEAD in the ring so that no issues are seen if Guc
> + * submits this context to HW on VF pause after unbinding device.
> + */
> + xe_lrc_set_ring_tail(lrc, xe_lrc_ring_head(lrc));
> +}
> +
> /**
> * xe_sriov_vf_ccs_init - Setup LRCA for save & restore.
> * @xe: the &xe_device to start recovery on
> @@ -198,6 +279,16 @@ int xe_sriov_vf_ccs_init(struct xe_device *xe)
> err = alloc_bb_pool(tile, ctx);
> if (err)
> goto err_ret;
> +
> + ccs_rw_update_ring(ctx);
> +
> + err = register_save_restore_context(ctx->migrate, ctx_id);
> + if (err)
> + goto err_ret;
> +
> + err = devm_add_action_or_reset(xe->drm.dev,
> + xe_sriov_vf_ccs_fini,
> + ctx);
> }
>
> xe->sriov.vf.ccs.initialized = 1;
> diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.h b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.h
> index 5d5e4bd25904..1f1baf685fec 100644
> --- a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.h
> +++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.h
> @@ -12,5 +12,6 @@ struct xe_bo;
> int xe_sriov_vf_ccs_init(struct xe_device *xe);
> int xe_sriov_vf_ccs_attach_bo(struct xe_bo *bo);
> int xe_sriov_vf_ccs_detach_bo(struct xe_bo *bo);
> +int xe_sriov_vf_ccs_register_context(struct xe_device *xe);
>
> #endif
> diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
> index 04d1a43b81e3..8f1a258912ea 100644
> --- a/drivers/gpu/drm/xe/xe_vm.c
> +++ b/drivers/gpu/drm/xe/xe_vm.c
> @@ -953,7 +953,7 @@ struct dma_fence *xe_vma_rebind(struct xe_vm *vm, struct xe_vma *vma, u8 tile_ma
> for_each_tile(tile, vm->xe, id) {
> vops.pt_update_ops[id].wait_vm_bookkeep = true;
> vops.pt_update_ops[tile->id].q =
> - xe_tile_migrate_exec_queue(tile);
> + xe_migrate_exec_queue(tile->migrate);
> }
>
> err = xe_vm_ops_add_rebind(&vops, vma, tile_mask);
> @@ -1043,7 +1043,7 @@ struct dma_fence *xe_vm_range_rebind(struct xe_vm *vm,
> for_each_tile(tile, vm->xe, id) {
> vops.pt_update_ops[id].wait_vm_bookkeep = true;
> vops.pt_update_ops[tile->id].q =
> - xe_tile_migrate_exec_queue(tile);
> + xe_migrate_exec_queue(tile->migrate);
> }
>
> err = xe_vm_ops_add_range_rebind(&vops, vma, range, tile_mask);
> @@ -1126,7 +1126,7 @@ struct dma_fence *xe_vm_range_unbind(struct xe_vm *vm,
> for_each_tile(tile, vm->xe, id) {
> vops.pt_update_ops[id].wait_vm_bookkeep = true;
> vops.pt_update_ops[tile->id].q =
> - xe_tile_migrate_exec_queue(tile);
> + xe_migrate_exec_queue(tile->migrate);
> }
>
> err = xe_vm_ops_add_range_unbind(&vops, range);
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v9 1/3] drm/xe/vf: Create contexts for CCS read write
2025-06-24 10:00 ` [PATCH v9 1/3] drm/xe/vf: Create contexts for CCS read write Satyanarayana K V P
2025-06-24 15:40 ` Matthew Brost
@ 2025-06-24 17:01 ` Matthew Brost
2025-06-25 12:46 ` K V P, Satyanarayana
1 sibling, 1 reply; 13+ messages in thread
From: Matthew Brost @ 2025-06-24 17:01 UTC (permalink / raw)
To: Satyanarayana K V P
Cc: intel-xe, Michal Wajdeczko, Michał Winiarski, Tomasz Lis,
Matthew Auld
On Tue, Jun 24, 2025 at 03:30:08PM +0530, Satyanarayana K V P wrote:
> Create two LRCs to handle CCS meta data read / write from CCS pool in the
> VM. Read context is used to hold GPU instructions to be executed at save
> time and write context is used to hold GPU instructions to be executed at
> the restore time.
>
> Allocate batch buffer pool using suballocator for both read and write
> contexts.
>
> Migration framework is reused to create LRCAs for read and write.
>
One more thing.
> Signed-off-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>
> Cc: Michał Winiarski <michal.winiarski@intel.com>
> Acked-by: Matthew Brost <matthew.brost@intel.com>
> ---
> Cc: Tomasz Lis <tomasz.lis@intel.com>
> Cc: Matthew Auld <matthew.auld@intel.com>
>
> V8 -> V9:
> - Initialized CCS read write contexts for only root tile (Matthew Brost).
>
> V7 -> V8:
> - None.
>
> V6 -> V7:
> - Fixed review comments (Michal Wajdeczko & Matthew Brost).
>
> V5 -> V6:
> - Added id field in the xe_tile_vf_ccs structure for self identification.
>
> V4 -> V5:
> - Modified read/write contexts to enums from #defines (Matthew Brost).
> - The CCS BB pool size is calculated based on the system memory size (Michal
> Wajdeczko & Matthew Brost).
>
> V3 -> V4:
> - Fixed issues reported by patchworks.
>
> V2 -> V3:
> - Added new variable which denotes the initialization of contexts.
>
> V1 -> V2:
> - Fixed review comments.
> ---
> drivers/gpu/drm/xe/Makefile | 1 +
> drivers/gpu/drm/xe/xe_device.c | 4 +
> drivers/gpu/drm/xe/xe_device_types.h | 4 +
> drivers/gpu/drm/xe/xe_gt_debugfs.c | 36 ++++
> drivers/gpu/drm/xe/xe_sriov.c | 19 ++
> drivers/gpu/drm/xe/xe_sriov.h | 1 +
> drivers/gpu/drm/xe/xe_sriov_types.h | 5 +
> drivers/gpu/drm/xe/xe_sriov_vf_ccs.c | 208 +++++++++++++++++++++
> drivers/gpu/drm/xe/xe_sriov_vf_ccs.h | 13 ++
> drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h | 45 +++++
> 10 files changed, 336 insertions(+)
> create mode 100644 drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
> create mode 100644 drivers/gpu/drm/xe/xe_sriov_vf_ccs.h
> create mode 100644 drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h
>
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index eee6bac01a00..853970ab1314 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -141,6 +141,7 @@ xe-y += \
> xe_memirq.o \
> xe_sriov.o \
> xe_sriov_vf.o \
> + xe_sriov_vf_ccs.o \
> xe_tile_sriov_vf.o
>
> xe-$(CONFIG_PCI_IOV) += \
> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
> index e160e7be84f0..b7922668741c 100644
> --- a/drivers/gpu/drm/xe/xe_device.c
> +++ b/drivers/gpu/drm/xe/xe_device.c
> @@ -929,6 +929,10 @@ int xe_device_probe(struct xe_device *xe)
>
> xe_vsec_init(xe);
>
> + err = xe_sriov_late_init(xe);
> + if (err)
> + goto err_unregister_display;
> +
> return devm_add_action_or_reset(xe->drm.dev, xe_device_sanitize, xe);
>
> err_unregister_display:
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index 6aca4b1a2824..1b52db967ace 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -22,6 +22,7 @@
> #include "xe_pmu_types.h"
> #include "xe_pt_types.h"
> #include "xe_sriov_types.h"
> +#include "xe_sriov_vf_ccs_types.h"
> #include "xe_step_types.h"
> #include "xe_survivability_mode_types.h"
> #include "xe_ttm_vram_mgr_types.h"
> @@ -235,6 +236,9 @@ struct xe_tile {
> struct {
> /** @sriov.vf.ggtt_balloon: GGTT regions excluded from use. */
> struct xe_ggtt_node *ggtt_balloon[2];
> +
> + /** @sriov.vf.ccs: CCS read and write contexts for VF. */
> + struct xe_tile_vf_ccs ccs[XE_SRIOV_VF_CCS_CTX_COUNT];
> } vf;
> } sriov;
>
> diff --git a/drivers/gpu/drm/xe/xe_gt_debugfs.c b/drivers/gpu/drm/xe/xe_gt_debugfs.c
> index 848618acdca8..404844515523 100644
> --- a/drivers/gpu/drm/xe/xe_gt_debugfs.c
> +++ b/drivers/gpu/drm/xe/xe_gt_debugfs.c
> @@ -134,6 +134,30 @@ static int sa_info(struct xe_gt *gt, struct drm_printer *p)
> return 0;
> }
>
> +static int sa_info_vf_ccs(struct xe_gt *gt, struct drm_printer *p)
> +{
> + struct xe_tile *tile = gt_to_tile(gt);
> + struct xe_sa_manager *bb_pool;
> + enum xe_sriov_vf_ccs_rw_ctxs ctx_id;
> +
> + if (!IS_VF_CCS_READY(gt_to_xe(gt)))
> + return 0;
> +
> + xe_pm_runtime_get(gt_to_xe(gt));
> +
> + for_each_ccs_rw_ctx(ctx_id) {
> + drm_printf(p, "ccs %s bb suballoc info\n", ctx_id ? "write" : "read");
> + drm_printf(p, "-------------------------\n");
> + bb_pool = tile->sriov.vf.ccs[ctx_id].mem.ccs_bb_pool;
> + drm_suballoc_dump_debug_info(&bb_pool->base, p, bb_pool->gpu_addr);
> + drm_puts(p, "\n");
> + }
> +
> + xe_pm_runtime_put(gt_to_xe(gt));
> +
> + return 0;
> +}
> +
> static int topology(struct xe_gt *gt, struct drm_printer *p)
> {
> xe_pm_runtime_get(gt_to_xe(gt));
> @@ -303,6 +327,13 @@ static const struct drm_info_list vf_safe_debugfs_list[] = {
> {"hwconfig", .show = xe_gt_debugfs_simple_show, .data = hwconfig},
> };
>
> +/*
> + * only for GT debugfs files which are valid on VF. Not valid on PF.
> + */
> +static const struct drm_info_list vf_only_debugfs_list[] = {
> + {"sa_info_vf_ccs", .show = xe_gt_debugfs_simple_show, .data = sa_info_vf_ccs},
> +};
> +
> /* everything else should be added here */
> static const struct drm_info_list pf_only_debugfs_list[] = {
> {"hw_engines", .show = xe_gt_debugfs_simple_show, .data = hw_engines},
> @@ -419,6 +450,11 @@ void xe_gt_debugfs_register(struct xe_gt *gt)
> drm_debugfs_create_files(pf_only_debugfs_list,
> ARRAY_SIZE(pf_only_debugfs_list),
> root, minor);
> + else
> + drm_debugfs_create_files(vf_only_debugfs_list,
> + ARRAY_SIZE(vf_only_debugfs_list),
> + root, minor);
> +
>
> xe_uc_debugfs_register(>->uc, root);
>
> diff --git a/drivers/gpu/drm/xe/xe_sriov.c b/drivers/gpu/drm/xe/xe_sriov.c
> index a0eab44c0e76..87911fb4eea7 100644
> --- a/drivers/gpu/drm/xe/xe_sriov.c
> +++ b/drivers/gpu/drm/xe/xe_sriov.c
> @@ -15,6 +15,7 @@
> #include "xe_sriov.h"
> #include "xe_sriov_pf.h"
> #include "xe_sriov_vf.h"
> +#include "xe_sriov_vf_ccs.h"
>
> /**
> * xe_sriov_mode_to_string - Convert enum value to string.
> @@ -157,3 +158,21 @@ const char *xe_sriov_function_name(unsigned int n, char *buf, size_t size)
> strscpy(buf, "PF", size);
> return buf;
> }
> +
> +/**
> + * xe_sriov_late_init() - SR-IOV late initialization functions.
> + * @xe: the &xe_device to initialize
> + *
> + * On VF this function will initialize code for CCS migration.
> + *
> + * Return: 0 on success or a negative error code on failure.
> + */
> +int xe_sriov_late_init(struct xe_device *xe)
> +{
> + int err = 0;
> +
> + if (IS_VF_CCS_INIT_NEEDED(xe))
> + err = xe_sriov_vf_ccs_init(xe);
> +
> + return err;
> +}
> diff --git a/drivers/gpu/drm/xe/xe_sriov.h b/drivers/gpu/drm/xe/xe_sriov.h
> index 688fbabf08f1..0e0c1abf2d14 100644
> --- a/drivers/gpu/drm/xe/xe_sriov.h
> +++ b/drivers/gpu/drm/xe/xe_sriov.h
> @@ -18,6 +18,7 @@ const char *xe_sriov_function_name(unsigned int n, char *buf, size_t len);
> void xe_sriov_probe_early(struct xe_device *xe);
> void xe_sriov_print_info(struct xe_device *xe, struct drm_printer *p);
> int xe_sriov_init(struct xe_device *xe);
> +int xe_sriov_late_init(struct xe_device *xe);
>
> static inline enum xe_sriov_mode xe_device_sriov_mode(const struct xe_device *xe)
> {
> diff --git a/drivers/gpu/drm/xe/xe_sriov_types.h b/drivers/gpu/drm/xe/xe_sriov_types.h
> index ca94382a721e..8abfdb2c5ead 100644
> --- a/drivers/gpu/drm/xe/xe_sriov_types.h
> +++ b/drivers/gpu/drm/xe/xe_sriov_types.h
> @@ -71,6 +71,11 @@ struct xe_device_vf {
> /** @migration.gt_flags: Per-GT request flags for VF migration recovery */
> unsigned long gt_flags;
> } migration;
> +
> + struct {
> + /** @initialized: Initilalization of vf ccs is completed or not */
> + bool initialized;
> + } ccs;
> };
>
> #endif
> diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
> new file mode 100644
> index 000000000000..9000d618978d
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
> @@ -0,0 +1,208 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#include "instructions/xe_mi_commands.h"
> +#include "instructions/xe_gpu_commands.h"
> +#include "xe_bo.h"
> +#include "xe_device.h"
> +#include "xe_migrate.h"
> +#include "xe_sa.h"
> +#include "xe_sriov_printk.h"
> +#include "xe_sriov_vf_ccs.h"
> +#include "xe_sriov_vf_ccs_types.h"
> +
> +/**
> + * DOC: VF save/restore of compression Meta Data
> + *
> + * VF KMD registers two special contexts/LRCAs.
> + *
> + * Save Context/LRCA: contain necessary cmds+page table to trigger Meta data /
> + * compression control surface (Aka CCS) save in regular System memory in VM.
> + *
> + * Restore Context/LRCA: contain necessary cmds+page table to trigger Meta data /
> + * compression control surface (Aka CCS) Restore from regular System memory in
> + * VM to corresponding CCS pool.
> + *
> + * Below diagram explain steps needed for VF save/Restore of compression Meta Data::
> + *
> + * CCS Save CCS Restore VF KMD Guc BCS
> + * LRCA LRCA
> + * | | | | |
> + * | | | | |
> + * | Create Save LRCA | | |
> + * [ ]<----------------------------- [ ] | |
> + * | | | | |
> + * | | | | |
> + * | | | Register save LRCA | |
> + * | | | with Guc | |
> + * | | [ ]--------------------------->[ ] |
> + * | | | | |
> + * | | Create restore LRCA | | |
> + * | [ ]<------------------[ ] | |
> + * | | | | |
> + * | | | Register restore LRCA | |
> + * | | | with Guc | |
> + * | | [ ]--------------------------->[ ] |
> + * | | | | |
> + * | | | | |
> + * | | [ ]------------------------- | |
> + * | | [ ] Allocate main memory. | | |
> + * | | [ ] Allocate CCS memory. | | |
> + * | | [ ] Update Main memory & | | |
> + * [ ]<------------------------------[ ] CCS pages PPGTT + BB | | |
> + * | [ ]<------------------[ ] cmds to save & restore.| | |
> + * | | [ ]<------------------------ | |
> + * | | | | |
> + * | | | | |
> + * | | | | |
> + * : : : : :
> + * ---------------------------- VF Paused -------------------------------------
> + * | | | | |
> + * | | | | |
> + * | | | |Schedule |
> + * | | | |CCS Save |
> + * | | | | LRCA |
> + * | | | [ ]------>[ ]
> + * | | | | |
> + * | | | | |
> + * | | | |CCS save |
> + * | | | |completed|
> + * | | | [ ]<------[ ]
> + * | | | | |
> + * : : : : :
> + * ---------------------------- VM Migrated -----------------------------------
> + * | | | | |
> + * | | | | |
> + * : : : : :
> + * ---------------------------- VF Resumed ------------------------------------
> + * | | | | |
> + * | | | | |
> + * | | [ ]-------------- | |
> + * | | [ ] Fix up GGTT | | |
> + * | | [ ]<------------- | |
> + * | | | | |
> + * | | | | |
> + * | | | Notify VF_RESFIX_DONE | |
> + * | | [ ]--------------------------->[ ] |
> + * | | | | |
> + * | | | |Schedule |
> + * | | | |CCS |
> + * | | | |Restore |
> + * | | | |LRCA |
> + * | | | [ ]------>[ ]
> + * | | | | |
> + * | | | | |
> + * | | | |CCS |
> + * | | | |restore |
> + * | | | |completed|
> + * | | | [ ]<------[ ]
> + * | | | | |
> + * | | | | |
> + * | | | VF_RESFIX_DONE complete | |
> + * | | | notification | |
> + * | | [ ]<---------------------------[ ] |
> + * | | | | |
> + * | | | | |
> + * : : : : :
> + * ------------------------- Continue VM restore ------------------------------
> + */
> +
> +static u64 get_ccs_bb_pool_size(struct xe_device *xe)
> +{
> + u64 sys_mem_size, ccs_mem_size, ptes, bb_pool_size;
> + struct sysinfo si;
> +
> + si_meminfo(&si);
> + sys_mem_size = si.totalram * si.mem_unit;
> + ccs_mem_size = sys_mem_size / NUM_BYTES_PER_CCS_BYTE(xe);
> + ptes = DIV_ROUND_UP(sys_mem_size + ccs_mem_size, XE_PAGE_SIZE);
s/DIV_ROUND_UP/DIV_ROUND_UP_ULL
I'm pretty sure this is the CI hooks failure.
Matt
> +
> + /**
> + * We need below BB size to hold PTE mappings and some DWs for copy
> + * command. In reality, we need space for many copy commands. So, let
> + * us allocate double the calculated size which is enough to holds GPU
> + * instructions for the whole region.
> + */
> + bb_pool_size = ptes * sizeof(u32);
> +
> + return round_up(bb_pool_size * 2, SZ_1M);
> +}
> +
> +static int alloc_bb_pool(struct xe_tile *tile, struct xe_tile_vf_ccs *ctx)
> +{
> + struct xe_device *xe = tile_to_xe(tile);
> + struct xe_sa_manager *sa_manager;
> + u64 bb_pool_size;
> + int offset, err;
> +
> + bb_pool_size = get_ccs_bb_pool_size(xe);
> + xe_sriov_info(xe, "Allocating %s CCS BB pool size = %lldMB\n",
> + ctx->ctx_id ? "Restore" : "Save", bb_pool_size / SZ_1M);
> +
> + sa_manager = xe_sa_bo_manager_init(tile, bb_pool_size, SZ_16);
> +
> + if (IS_ERR(sa_manager)) {
> + xe_sriov_err(xe, "Suballocator init failed with error: %pe\n",
> + sa_manager);
> + err = PTR_ERR(sa_manager);
> + return err;
> + }
> +
> + offset = 0;
> + xe_map_memset(xe, &sa_manager->bo->vmap, offset, MI_NOOP,
> + bb_pool_size);
> +
> + offset = bb_pool_size - sizeof(u32);
> + xe_map_wr(xe, &sa_manager->bo->vmap, offset, u32, MI_BATCH_BUFFER_END);
> +
> + ctx->mem.ccs_bb_pool = sa_manager;
> +
> + return 0;
> +}
> +
> +/**
> + * xe_sriov_vf_ccs_init - Setup LRCA for save & restore.
> + * @xe: the &xe_device to start recovery on
> + *
> + * This function shall be called only by VF. It initializes
> + * LRCA and suballocator needed for CCS save & restore.
> + *
> + * Return: 0 on success. Negative error code on failure.
> + */
> +int xe_sriov_vf_ccs_init(struct xe_device *xe)
> +{
> + struct xe_tile *tile = xe_device_get_root_tile(xe);
> + enum xe_sriov_vf_ccs_rw_ctxs ctx_id;
> + struct xe_migrate *migrate;
> + struct xe_tile_vf_ccs *ctx;
> + int err;
> +
> + xe_assert(xe, IS_SRIOV_VF(xe));
> + xe_assert(xe, !IS_DGFX(xe));
> + xe_assert(xe, xe_device_has_flat_ccs(xe));
> +
> + for_each_ccs_rw_ctx(ctx_id) {
> + ctx = &tile->sriov.vf.ccs[ctx_id];
> + ctx->ctx_id = ctx_id;
> +
> + migrate = xe_migrate_init(tile);
> + if (IS_ERR(migrate)) {
> + err = PTR_ERR(migrate);
> + goto err_ret;
> + }
> + ctx->migrate = migrate;
> +
> + err = alloc_bb_pool(tile, ctx);
> + if (err)
> + goto err_ret;
> + }
> +
> + xe->sriov.vf.ccs.initialized = 1;
> +
> + return 0;
> +
> +err_ret:
> + return err;
> +}
> diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.h b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.h
> new file mode 100644
> index 000000000000..5df9ba028d14
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.h
> @@ -0,0 +1,13 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#ifndef _XE_SRIOV_VF_CCS_H_
> +#define _XE_SRIOV_VF_CCS_H_
> +
> +struct xe_device;
> +
> +int xe_sriov_vf_ccs_init(struct xe_device *xe);
> +
> +#endif
> diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h b/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h
> new file mode 100644
> index 000000000000..6dc279d206ec
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h
> @@ -0,0 +1,45 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#ifndef _XE_SRIOV_VF_CCS_TYPES_H_
> +#define _XE_SRIOV_VF_CCS_TYPES_H_
> +
> +#define for_each_ccs_rw_ctx(id__) \
> + for ((id__) = 0; (id__) < XE_SRIOV_VF_CCS_CTX_COUNT; (id__)++)
> +
> +#define IS_VF_CCS_READY(xe) ({ \
> + struct xe_device *___xe = (xe); \
> + xe_assert(___xe, IS_SRIOV_VF(___xe)); \
> + ___xe->sriov.vf.ccs.initialized; \
> + })
> +
> +#define IS_VF_CCS_INIT_NEEDED(xe) ({\
> + struct xe_device *___xe = (xe); \
> + IS_SRIOV_VF(___xe) && !IS_DGFX(___xe) && \
> + xe_device_has_flat_ccs(___xe) && GRAPHICS_VER(___xe) >= 20; \
> + })
> +
> +enum xe_sriov_vf_ccs_rw_ctxs {
> + XE_SRIOV_VF_CCS_READ_CTX,
> + XE_SRIOV_VF_CCS_WRITE_CTX,
> + XE_SRIOV_VF_CCS_CTX_COUNT
> +};
> +
> +struct xe_migrate;
> +struct xe_sa_manager;
> +
> +struct xe_tile_vf_ccs {
> + /** @id: Id to which context it belongs to */
> + enum xe_sriov_vf_ccs_rw_ctxs ctx_id;
> + /** @migrate: Migration helper for save/restore of CCS data */
> + struct xe_migrate *migrate;
> +
> + struct {
> + /** @ccs_rw_bb_pool: Pool from which batch buffers are allocated. */
> + struct xe_sa_manager *ccs_bb_pool;
> + } mem;
> +};
> +
> +#endif
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* ✗ Xe.CI.Full: failure for CCS save restore for IGPU (rev9)
2025-06-24 10:00 [PATCH v9 0/3] CCS save restore for IGPU Satyanarayana K V P
` (5 preceding siblings ...)
2025-06-24 15:46 ` ✓ Xe.CI.BAT: " Patchwork
@ 2025-06-25 10:02 ` Patchwork
6 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2025-06-25 10:02 UTC (permalink / raw)
To: Satyanarayana K V P; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 94523 bytes --]
== Series Details ==
Series: CCS save restore for IGPU (rev9)
URL : https://patchwork.freedesktop.org/series/149108/
State : failure
== Summary ==
CI Bug Log - changes from xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201_FULL -> xe-pw-149108v9_FULL
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-149108v9_FULL absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-149108v9_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (4 -> 4)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-149108v9_FULL:
### IGT changes ###
#### Possible regressions ####
* igt@kms_flip@blocking-absolute-wf_vblank-interruptible@a-dp4:
- shard-dg2-set2: [PASS][1] -> [FAIL][2] +3 other tests fail
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-dg2-463/igt@kms_flip@blocking-absolute-wf_vblank-interruptible@a-dp4.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-433/igt@kms_flip@blocking-absolute-wf_vblank-interruptible@a-dp4.html
* igt@xe_exec_compute_mode@many-userptr-rebind:
- shard-bmg: [PASS][3] -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-bmg-6/igt@xe_exec_compute_mode@many-userptr-rebind.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-3/igt@xe_exec_compute_mode@many-userptr-rebind.html
* igt@xe_gt_freq@freq_suspend:
- shard-bmg: [PASS][5] -> [INCOMPLETE][6]
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-bmg-3/igt@xe_gt_freq@freq_suspend.html
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-6/igt@xe_gt_freq@freq_suspend.html
New tests
---------
New tests have been introduced between xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201_FULL and xe-pw-149108v9_FULL:
### New IGT tests (1) ###
* igt@kms_pipe_crc_basic@disable-crc-after-crtc@pipe-b-dp-2:
- Statuses : 1 pass(s)
- Exec time: [0.52] s
Known issues
------------
Here are the changes found in xe-pw-149108v9_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_async_flips@async-flip-with-page-flip-events-linear@pipe-c-edp-1:
- shard-lnl: [PASS][7] -> [FAIL][8] ([Intel XE#911]) +3 other tests fail
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-lnl-1/igt@kms_async_flips@async-flip-with-page-flip-events-linear@pipe-c-edp-1.html
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-lnl-2/igt@kms_async_flips@async-flip-with-page-flip-events-linear@pipe-c-edp-1.html
* igt@kms_async_flips@async-flip-with-page-flip-events-tiled-atomic@pipe-a-hdmi-a-6-4-rc-ccs-cc:
- shard-dg2-set2: NOTRUN -> [SKIP][9] ([Intel XE#3767]) +31 other tests skip
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-435/igt@kms_async_flips@async-flip-with-page-flip-events-tiled-atomic@pipe-a-hdmi-a-6-4-rc-ccs-cc.html
* igt@kms_async_flips@crc-atomic@pipe-d-hdmi-a-1:
- shard-adlp: [PASS][10] -> [FAIL][11] ([Intel XE#3884]) +1 other test fail
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-6/igt@kms_async_flips@crc-atomic@pipe-d-hdmi-a-1.html
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-2/igt@kms_async_flips@crc-atomic@pipe-d-hdmi-a-1.html
* igt@kms_async_flips@invalid-async-flip-atomic:
- shard-adlp: [PASS][12] -> [DMESG-WARN][13] ([Intel XE#4543]) +1 other test dmesg-warn
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@kms_async_flips@invalid-async-flip-atomic.html
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-3/igt@kms_async_flips@invalid-async-flip-atomic.html
* igt@kms_big_fb@4-tiled-8bpp-rotate-90:
- shard-bmg: NOTRUN -> [SKIP][14] ([Intel XE#2327]) +5 other tests skip
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-1/igt@kms_big_fb@4-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0:
- shard-adlp: NOTRUN -> [SKIP][15] ([Intel XE#1124])
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-8/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-lnl: NOTRUN -> [SKIP][16] ([Intel XE#1407]) +4 other tests skip
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-lnl-7/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_big_fb@linear-8bpp-rotate-270:
- shard-adlp: NOTRUN -> [SKIP][17] ([Intel XE#316])
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-3/igt@kms_big_fb@linear-8bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-16bpp-rotate-270:
- shard-dg2-set2: NOTRUN -> [SKIP][18] ([Intel XE#316]) +4 other tests skip
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-463/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-addfb:
- shard-bmg: NOTRUN -> [SKIP][19] ([Intel XE#2328])
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-5/igt@kms_big_fb@y-tiled-addfb.html
- shard-dg2-set2: NOTRUN -> [SKIP][20] ([Intel XE#619])
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-433/igt@kms_big_fb@y-tiled-addfb.html
- shard-lnl: NOTRUN -> [SKIP][21] ([Intel XE#1467])
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-lnl-3/igt@kms_big_fb@y-tiled-addfb.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- shard-adlp: [PASS][22] -> [DMESG-FAIL][23] ([Intel XE#4543]) +8 other tests dmesg-fail
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-6/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-2/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-bmg: NOTRUN -> [SKIP][24] ([Intel XE#1124]) +6 other tests skip
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-8/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
- shard-lnl: NOTRUN -> [SKIP][25] ([Intel XE#1124]) +4 other tests skip
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-lnl-3/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
- shard-dg2-set2: NOTRUN -> [SKIP][26] ([Intel XE#1124]) +12 other tests skip
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-463/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
* igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p:
- shard-bmg: [PASS][27] -> [SKIP][28] ([Intel XE#2314] / [Intel XE#2894]) +1 other test skip
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-bmg-1/igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p.html
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-6/igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p.html
* igt@kms_bw@linear-tiling-1-displays-2560x1440p:
- shard-dg2-set2: NOTRUN -> [SKIP][29] ([Intel XE#367])
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-434/igt@kms_bw@linear-tiling-1-displays-2560x1440p.html
* igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-1:
- shard-adlp: NOTRUN -> [SKIP][30] ([Intel XE#787]) +8 other tests skip
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-1/igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-1.html
* igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs-cc@pipe-d-hdmi-a-1:
- shard-adlp: NOTRUN -> [SKIP][31] ([Intel XE#455] / [Intel XE#787]) +4 other tests skip
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-1/igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs-cc@pipe-d-hdmi-a-1.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs:
- shard-lnl: NOTRUN -> [SKIP][32] ([Intel XE#2887]) +4 other tests skip
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-lnl-3/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc:
- shard-bmg: NOTRUN -> [SKIP][33] ([Intel XE#2887]) +9 other tests skip
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-1/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs@pipe-b-dp-2:
- shard-bmg: NOTRUN -> [SKIP][34] ([Intel XE#2652] / [Intel XE#787]) +7 other tests skip
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-3/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs@pipe-b-dp-2.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-2:
- shard-dg2-set2: NOTRUN -> [SKIP][35] ([Intel XE#787]) +202 other tests skip
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-432/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-2.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc:
- shard-dg2-set2: [PASS][36] -> [INCOMPLETE][37] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#3124])
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-c-dp-4:
- shard-dg2-set2: [PASS][38] -> [INCOMPLETE][39] ([Intel XE#3124])
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-c-dp-4.html
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-c-dp-4.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-6:
- shard-dg2-set2: [PASS][40] -> [DMESG-WARN][41] ([Intel XE#1727] / [Intel XE#3113])
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-6.html
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-6.html
* igt@kms_ccs@random-ccs-data-y-tiled-ccs@pipe-d-dp-2:
- shard-dg2-set2: NOTRUN -> [SKIP][42] ([Intel XE#455] / [Intel XE#787]) +40 other tests skip
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-432/igt@kms_ccs@random-ccs-data-y-tiled-ccs@pipe-d-dp-2.html
* igt@kms_cdclk@mode-transition:
- shard-bmg: NOTRUN -> [SKIP][43] ([Intel XE#2724])
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-1/igt@kms_cdclk@mode-transition.html
* igt@kms_cdclk@mode-transition@pipe-b-edp-1:
- shard-lnl: NOTRUN -> [SKIP][44] ([Intel XE#4417]) +3 other tests skip
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-lnl-5/igt@kms_cdclk@mode-transition@pipe-b-edp-1.html
* igt@kms_cdclk@mode-transition@pipe-d-dp-4:
- shard-dg2-set2: NOTRUN -> [SKIP][45] ([Intel XE#4417]) +3 other tests skip
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-436/igt@kms_cdclk@mode-transition@pipe-d-dp-4.html
* igt@kms_chamelium_color@ctm-0-25:
- shard-bmg: NOTRUN -> [SKIP][46] ([Intel XE#2325])
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-5/igt@kms_chamelium_color@ctm-0-25.html
* igt@kms_chamelium_color@gamma:
- shard-dg2-set2: NOTRUN -> [SKIP][47] ([Intel XE#306]) +2 other tests skip
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-433/igt@kms_chamelium_color@gamma.html
- shard-lnl: NOTRUN -> [SKIP][48] ([Intel XE#306]) +1 other test skip
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-lnl-7/igt@kms_chamelium_color@gamma.html
- shard-adlp: NOTRUN -> [SKIP][49] ([Intel XE#306])
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-6/igt@kms_chamelium_color@gamma.html
* igt@kms_chamelium_hpd@hdmi-hpd-storm-disable:
- shard-bmg: NOTRUN -> [SKIP][50] ([Intel XE#2252]) +3 other tests skip
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-1/igt@kms_chamelium_hpd@hdmi-hpd-storm-disable.html
* igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode:
- shard-dg2-set2: NOTRUN -> [SKIP][51] ([Intel XE#373]) +7 other tests skip
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-433/igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode.html
- shard-lnl: NOTRUN -> [SKIP][52] ([Intel XE#373]) +1 other test skip
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-lnl-3/igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode.html
- shard-adlp: NOTRUN -> [SKIP][53] ([Intel XE#373])
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-3/igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode.html
* igt@kms_content_protection@atomic:
- shard-bmg: NOTRUN -> [FAIL][54] ([Intel XE#1178]) +1 other test fail
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-3/igt@kms_content_protection@atomic.html
- shard-dg2-set2: NOTRUN -> [FAIL][55] ([Intel XE#1178]) +2 other tests fail
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-435/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@dp-mst-lic-type-0:
- shard-dg2-set2: NOTRUN -> [SKIP][56] ([Intel XE#307]) +1 other test skip
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-433/igt@kms_content_protection@dp-mst-lic-type-0.html
- shard-lnl: NOTRUN -> [SKIP][57] ([Intel XE#307]) +1 other test skip
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-lnl-3/igt@kms_content_protection@dp-mst-lic-type-0.html
- shard-adlp: NOTRUN -> [SKIP][58] ([Intel XE#307])
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-3/igt@kms_content_protection@dp-mst-lic-type-0.html
* igt@kms_content_protection@dp-mst-lic-type-1:
- shard-bmg: NOTRUN -> [SKIP][59] ([Intel XE#2390]) +1 other test skip
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-3/igt@kms_content_protection@dp-mst-lic-type-1.html
* igt@kms_content_protection@uevent:
- shard-dg2-set2: NOTRUN -> [FAIL][60] ([Intel XE#1188]) +1 other test fail
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-432/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@cursor-offscreen-512x170:
- shard-dg2-set2: NOTRUN -> [SKIP][61] ([Intel XE#308])
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-432/igt@kms_cursor_crc@cursor-offscreen-512x170.html
- shard-bmg: NOTRUN -> [SKIP][62] ([Intel XE#2321])
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-6/igt@kms_cursor_crc@cursor-offscreen-512x170.html
* igt@kms_cursor_crc@cursor-sliding-128x42:
- shard-lnl: NOTRUN -> [SKIP][63] ([Intel XE#1424]) +1 other test skip
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-lnl-6/igt@kms_cursor_crc@cursor-sliding-128x42.html
- shard-bmg: NOTRUN -> [SKIP][64] ([Intel XE#2320]) +1 other test skip
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-8/igt@kms_cursor_crc@cursor-sliding-128x42.html
* igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
- shard-bmg: [PASS][65] -> [SKIP][66] ([Intel XE#2291]) +4 other tests skip
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-bmg-3/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-5/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-bmg: NOTRUN -> [SKIP][67] ([Intel XE#2291]) +2 other tests skip
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-5/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size:
- shard-lnl: NOTRUN -> [SKIP][68] ([Intel XE#309]) +2 other tests skip
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-lnl-4/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
- shard-dg2-set2: NOTRUN -> [SKIP][69] ([Intel XE#323])
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-433/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
* igt@kms_display_modes@extended-mode-basic:
- shard-bmg: NOTRUN -> [SKIP][70] ([Intel XE#4302])
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-5/igt@kms_display_modes@extended-mode-basic.html
* igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area:
- shard-adlp: NOTRUN -> [SKIP][71] ([Intel XE#4422])
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-3/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area.html
- shard-bmg: NOTRUN -> [SKIP][72] ([Intel XE#4422])
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-6/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area.html
- shard-dg2-set2: NOTRUN -> [SKIP][73] ([Intel XE#4422])
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-436/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area.html
- shard-lnl: NOTRUN -> [SKIP][74] ([Intel XE#4422])
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-lnl-8/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area.html
* igt@kms_fbcon_fbt@psr:
- shard-bmg: NOTRUN -> [SKIP][75] ([Intel XE#776])
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-3/igt@kms_fbcon_fbt@psr.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-dg2-set2: NOTRUN -> [SKIP][76] ([Intel XE#776])
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-436/igt@kms_fbcon_fbt@psr-suspend.html
- shard-lnl: [PASS][77] -> [FAIL][78] ([Intel XE#4164])
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-lnl-3/igt@kms_fbcon_fbt@psr-suspend.html
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-lnl-8/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible@ab-dp2-hdmi-a3:
- shard-bmg: [PASS][79] -> [FAIL][80] ([Intel XE#3098]) +1 other test fail
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-bmg-1/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible@ab-dp2-hdmi-a3.html
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-1/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible@ab-dp2-hdmi-a3.html
* igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
- shard-bmg: NOTRUN -> [SKIP][81] ([Intel XE#2316]) +2 other tests skip
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-5/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html
* igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a6-dp4:
- shard-dg2-set2: [PASS][82] -> [FAIL][83] ([Intel XE#301])
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-dg2-435/igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a6-dp4.html
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-433/igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a6-dp4.html
* igt@kms_flip@2x-flip-vs-suspend-interruptible@bd-hdmi-a2-dp2:
- shard-dg2-set2: NOTRUN -> [INCOMPLETE][84] ([Intel XE#2049] / [Intel XE#2597])
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-432/igt@kms_flip@2x-flip-vs-suspend-interruptible@bd-hdmi-a2-dp2.html
* igt@kms_flip@2x-modeset-vs-vblank-race-interruptible:
- shard-adlp: NOTRUN -> [SKIP][85] ([Intel XE#310])
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-2/igt@kms_flip@2x-modeset-vs-vblank-race-interruptible.html
* igt@kms_flip@2x-plain-flip:
- shard-lnl: NOTRUN -> [SKIP][86] ([Intel XE#1421]) +3 other tests skip
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-lnl-3/igt@kms_flip@2x-plain-flip.html
* igt@kms_flip@2x-plain-flip-fb-recreate:
- shard-bmg: [PASS][87] -> [SKIP][88] ([Intel XE#2316]) +12 other tests skip
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-bmg-8/igt@kms_flip@2x-plain-flip-fb-recreate.html
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-5/igt@kms_flip@2x-plain-flip-fb-recreate.html
* igt@kms_flip@dpms-vs-vblank-race-interruptible@a-hdmi-a6:
- shard-dg2-set2: [PASS][89] -> [FAIL][90] ([Intel XE#3098]) +1 other test fail
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-dg2-434/igt@kms_flip@dpms-vs-vblank-race-interruptible@a-hdmi-a6.html
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-435/igt@kms_flip@dpms-vs-vblank-race-interruptible@a-hdmi-a6.html
* igt@kms_flip@flip-vs-absolute-wf_vblank:
- shard-lnl: [PASS][91] -> [FAIL][92] ([Intel XE#886]) +4 other tests fail
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-lnl-6/igt@kms_flip@flip-vs-absolute-wf_vblank.html
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-lnl-8/igt@kms_flip@flip-vs-absolute-wf_vblank.html
* igt@kms_flip@flip-vs-absolute-wf_vblank@a-hdmi-a3:
- shard-bmg: [PASS][93] -> [FAIL][94] ([Intel XE#2882]) +2 other tests fail
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-bmg-3/igt@kms_flip@flip-vs-absolute-wf_vblank@a-hdmi-a3.html
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-6/igt@kms_flip@flip-vs-absolute-wf_vblank@a-hdmi-a3.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-lnl: NOTRUN -> [FAIL][95] ([Intel XE#301]) +3 other tests fail
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@d-dp4:
- shard-dg2-set2: NOTRUN -> [FAIL][96] ([Intel XE#301]) +7 other tests fail
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-435/igt@kms_flip@flip-vs-expired-vblank-interruptible@d-dp4.html
* igt@kms_flip@flip-vs-expired-vblank@c-dp4:
- shard-dg2-set2: [PASS][97] -> [FAIL][98] ([Intel XE#301] / [Intel XE#3321])
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-dg2-436/igt@kms_flip@flip-vs-expired-vblank@c-dp4.html
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-434/igt@kms_flip@flip-vs-expired-vblank@c-dp4.html
* igt@kms_flip@flip-vs-suspend@d-dp4:
- shard-dg2-set2: [PASS][99] -> [INCOMPLETE][100] ([Intel XE#2049] / [Intel XE#2597]) +2 other tests incomplete
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-dg2-433/igt@kms_flip@flip-vs-suspend@d-dp4.html
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-463/igt@kms_flip@flip-vs-suspend@d-dp4.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-dg2-set2: NOTRUN -> [SKIP][101] ([Intel XE#455]) +11 other tests skip
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-463/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling:
- shard-bmg: NOTRUN -> [SKIP][102] ([Intel XE#2293] / [Intel XE#2380])
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-1/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html
- shard-lnl: NOTRUN -> [SKIP][103] ([Intel XE#1401] / [Intel XE#1745]) +1 other test skip
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-lnl-5/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-bmg: NOTRUN -> [SKIP][104] ([Intel XE#2293])
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-1/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling@pipe-a-valid-mode:
- shard-adlp: [PASS][105] -> [DMESG-FAIL][106] ([Intel XE#4543] / [Intel XE#4921]) +1 other test dmesg-fail
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling@pipe-a-valid-mode.html
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling@pipe-a-default-mode:
- shard-lnl: NOTRUN -> [SKIP][107] ([Intel XE#1401]) +1 other test skip
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-lnl-7/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling@pipe-a-default-mode.html
* igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-render:
- shard-bmg: NOTRUN -> [SKIP][108] ([Intel XE#2311]) +13 other tests skip
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-3/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-shrfb-plflip-blt:
- shard-lnl: NOTRUN -> [SKIP][109] ([Intel XE#656]) +15 other tests skip
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-lnl-8/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-blt:
- shard-bmg: NOTRUN -> [SKIP][110] ([Intel XE#4141]) +6 other tests skip
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt:
- shard-bmg: NOTRUN -> [SKIP][111] ([Intel XE#2312]) +10 other tests skip
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-mmap-wc:
- shard-dg2-set2: NOTRUN -> [SKIP][112] ([Intel XE#651]) +26 other tests skip
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-435/igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-mmap-wc.html
- shard-lnl: NOTRUN -> [SKIP][113] ([Intel XE#651]) +1 other test skip
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-lnl-3/igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt:
- shard-bmg: NOTRUN -> [SKIP][114] ([Intel XE#2313]) +12 other tests skip
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-blt:
- shard-adlp: NOTRUN -> [SKIP][115] ([Intel XE#656]) +3 other tests skip
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-blt:
- shard-dg2-set2: NOTRUN -> [SKIP][116] ([Intel XE#653]) +20 other tests skip
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-434/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt:
- shard-adlp: NOTRUN -> [SKIP][117] ([Intel XE#653])
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-4/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html
* igt@kms_hdr@brightness-with-hdr:
- shard-lnl: NOTRUN -> [SKIP][118] ([Intel XE#3374] / [Intel XE#3544])
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-lnl-3/igt@kms_hdr@brightness-with-hdr.html
- shard-bmg: NOTRUN -> [SKIP][119] ([Intel XE#3374] / [Intel XE#3544])
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-3/igt@kms_hdr@brightness-with-hdr.html
* igt@kms_hdr@invalid-hdr:
- shard-dg2-set2: [PASS][120] -> [SKIP][121] ([Intel XE#455])
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-dg2-463/igt@kms_hdr@invalid-hdr.html
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-432/igt@kms_hdr@invalid-hdr.html
* igt@kms_hdr@static-toggle-suspend:
- shard-bmg: [PASS][122] -> [SKIP][123] ([Intel XE#1503]) +1 other test skip
[122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-bmg-3/igt@kms_hdr@static-toggle-suspend.html
[123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-6/igt@kms_hdr@static-toggle-suspend.html
* igt@kms_joiner@basic-big-joiner:
- shard-dg2-set2: NOTRUN -> [SKIP][124] ([Intel XE#346])
[124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-433/igt@kms_joiner@basic-big-joiner.html
* igt@kms_lease@lease-invalid-plane:
- shard-adlp: [PASS][125] -> [DMESG-WARN][126] ([Intel XE#2953] / [Intel XE#4173])
[125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-3/igt@kms_lease@lease-invalid-plane.html
[126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-3/igt@kms_lease@lease-invalid-plane.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-bmg: NOTRUN -> [SKIP][127] ([Intel XE#2501])
[127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-1/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
- shard-dg2-set2: NOTRUN -> [SKIP][128] ([Intel XE#356])
[128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-433/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_pipe_stress@stress-xrgb8888-ytiled:
- shard-bmg: NOTRUN -> [SKIP][129] ([Intel XE#4329])
[129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-1/igt@kms_pipe_stress@stress-xrgb8888-ytiled.html
- shard-dg2-set2: NOTRUN -> [SKIP][130] ([Intel XE#4359])
[130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-433/igt@kms_pipe_stress@stress-xrgb8888-ytiled.html
* igt@kms_plane_multiple@2x-tiling-4:
- shard-bmg: [PASS][131] -> [SKIP][132] ([Intel XE#4596])
[131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-bmg-1/igt@kms_plane_multiple@2x-tiling-4.html
[132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-5/igt@kms_plane_multiple@2x-tiling-4.html
* igt@kms_plane_multiple@tiling-y:
- shard-bmg: NOTRUN -> [SKIP][133] ([Intel XE#5020])
[133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-8/igt@kms_plane_multiple@tiling-y.html
* igt@kms_pm_backlight@fade-with-suspend:
- shard-dg2-set2: NOTRUN -> [SKIP][134] ([Intel XE#870])
[134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-433/igt@kms_pm_backlight@fade-with-suspend.html
* igt@kms_pm_dc@dc6-dpms:
- shard-dg2-set2: NOTRUN -> [SKIP][135] ([Intel XE#908]) +1 other test skip
[135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-435/igt@kms_pm_dc@dc6-dpms.html
* igt@kms_pm_dc@dc6-psr:
- shard-lnl: [PASS][136] -> [FAIL][137] ([Intel XE#718]) +1 other test fail
[136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-lnl-4/igt@kms_pm_dc@dc6-psr.html
[137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-lnl-8/igt@kms_pm_dc@dc6-psr.html
* igt@kms_pm_rpm@modeset-non-lpsp:
- shard-lnl: NOTRUN -> [SKIP][138] ([Intel XE#1439] / [Intel XE#3141])
[138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-lnl-4/igt@kms_pm_rpm@modeset-non-lpsp.html
- shard-adlp: NOTRUN -> [SKIP][139] ([Intel XE#836])
[139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-3/igt@kms_pm_rpm@modeset-non-lpsp.html
* igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area:
- shard-lnl: NOTRUN -> [SKIP][140] ([Intel XE#2893] / [Intel XE#4608])
[140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-lnl-4/igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area.html
* igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area@pipe-b-edp-1:
- shard-lnl: NOTRUN -> [SKIP][141] ([Intel XE#4608]) +1 other test skip
[141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-lnl-4/igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area@pipe-b-edp-1.html
* igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf:
- shard-lnl: NOTRUN -> [SKIP][142] ([Intel XE#2893])
[142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-lnl-7/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf.html
* igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf:
- shard-bmg: NOTRUN -> [SKIP][143] ([Intel XE#1489]) +5 other tests skip
[143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-5/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-sf:
- shard-adlp: NOTRUN -> [SKIP][144] ([Intel XE#1489])
[144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-2/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area:
- shard-dg2-set2: NOTRUN -> [SKIP][145] ([Intel XE#1489]) +9 other tests skip
[145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-435/igt@kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area.html
* igt@kms_psr@fbc-psr2-primary-render:
- shard-lnl: NOTRUN -> [SKIP][146] ([Intel XE#1406])
[146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-lnl-1/igt@kms_psr@fbc-psr2-primary-render.html
- shard-bmg: NOTRUN -> [SKIP][147] ([Intel XE#2234] / [Intel XE#2850]) +1 other test skip
[147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-3/igt@kms_psr@fbc-psr2-primary-render.html
* igt@kms_psr@fbc-psr2-primary-render@edp-1:
- shard-lnl: NOTRUN -> [SKIP][148] ([Intel XE#4609])
[148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-lnl-1/igt@kms_psr@fbc-psr2-primary-render@edp-1.html
* igt@kms_psr@fbc-psr2-sprite-plane-move:
- shard-dg2-set2: NOTRUN -> [SKIP][149] ([Intel XE#2850] / [Intel XE#929]) +5 other tests skip
[149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-432/igt@kms_psr@fbc-psr2-sprite-plane-move.html
* igt@kms_rotation_crc@primary-x-tiled-reflect-x-0:
- shard-lnl: NOTRUN -> [FAIL][150] ([Intel XE#4689])
[150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-lnl-1/igt@kms_rotation_crc@primary-x-tiled-reflect-x-0.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
- shard-lnl: NOTRUN -> [SKIP][151] ([Intel XE#1127])
[151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-lnl-8/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
- shard-bmg: NOTRUN -> [SKIP][152] ([Intel XE#2330])
[152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
- shard-dg2-set2: NOTRUN -> [SKIP][153] ([Intel XE#1127])
[153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-436/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
* igt@kms_setmode@basic:
- shard-adlp: [PASS][154] -> [FAIL][155] ([Intel XE#2883]) +2 other tests fail
[154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@kms_setmode@basic.html
[155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-3/igt@kms_setmode@basic.html
* igt@kms_setmode@basic@pipe-b-edp-1:
- shard-lnl: [PASS][156] -> [FAIL][157] ([Intel XE#2883]) +2 other tests fail
[156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-lnl-7/igt@kms_setmode@basic@pipe-b-edp-1.html
[157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-lnl-3/igt@kms_setmode@basic@pipe-b-edp-1.html
* igt@kms_tiled_display@basic-test-pattern:
- shard-bmg: NOTRUN -> [SKIP][158] ([Intel XE#2426])
[158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-3/igt@kms_tiled_display@basic-test-pattern.html
- shard-dg2-set2: NOTRUN -> [SKIP][159] ([Intel XE#362])
[159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-463/igt@kms_tiled_display@basic-test-pattern.html
- shard-lnl: NOTRUN -> [SKIP][160] ([Intel XE#362])
[160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-lnl-4/igt@kms_tiled_display@basic-test-pattern.html
* igt@kms_vrr@flip-basic:
- shard-bmg: NOTRUN -> [SKIP][161] ([Intel XE#1499])
[161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-8/igt@kms_vrr@flip-basic.html
* igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all:
- shard-dg2-set2: NOTRUN -> [SKIP][162] ([Intel XE#1091] / [Intel XE#2849])
[162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-435/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html
- shard-lnl: NOTRUN -> [SKIP][163] ([Intel XE#1091] / [Intel XE#2849])
[163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-lnl-1/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html
- shard-bmg: NOTRUN -> [SKIP][164] ([Intel XE#1091] / [Intel XE#2849])
[164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-1/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html
* igt@xe_copy_basic@mem-copy-linear-0xfd:
- shard-adlp: NOTRUN -> [SKIP][165] ([Intel XE#1123])
[165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-6/igt@xe_copy_basic@mem-copy-linear-0xfd.html
- shard-dg2-set2: NOTRUN -> [SKIP][166] ([Intel XE#1123])
[166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-433/igt@xe_copy_basic@mem-copy-linear-0xfd.html
* igt@xe_eu_stall@blocking-read:
- shard-adlp: NOTRUN -> [SKIP][167] ([Intel XE#5308])
[167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-1/igt@xe_eu_stall@blocking-read.html
- shard-dg2-set2: NOTRUN -> [SKIP][168] ([Intel XE#5308])
[168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-463/igt@xe_eu_stall@blocking-read.html
* igt@xe_eudebug@discovery-race-vmbind:
- shard-adlp: NOTRUN -> [SKIP][169] ([Intel XE#4837]) +1 other test skip
[169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-4/igt@xe_eudebug@discovery-race-vmbind.html
* igt@xe_eudebug_online@reset-with-attention:
- shard-lnl: NOTRUN -> [SKIP][170] ([Intel XE#4837]) +3 other tests skip
[170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-lnl-5/igt@xe_eudebug_online@reset-with-attention.html
* igt@xe_eudebug_online@stopped-thread:
- shard-bmg: NOTRUN -> [SKIP][171] ([Intel XE#4837]) +7 other tests skip
[171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-6/igt@xe_eudebug_online@stopped-thread.html
* igt@xe_evict@evict-small-multi-vm:
- shard-lnl: NOTRUN -> [SKIP][172] ([Intel XE#688])
[172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-lnl-5/igt@xe_evict@evict-small-multi-vm.html
* igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr:
- shard-dg2-set2: NOTRUN -> [SKIP][173] ([Intel XE#1392])
[173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-432/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr.html
* igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-rebind:
- shard-lnl: NOTRUN -> [SKIP][174] ([Intel XE#1392]) +1 other test skip
[174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-lnl-5/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-rebind.html
* igt@xe_exec_basic@multigpu-no-exec-null-defer-mmap:
- shard-dg2-set2: [PASS][175] -> [SKIP][176] ([Intel XE#1392]) +6 other tests skip
[175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-dg2-436/igt@xe_exec_basic@multigpu-no-exec-null-defer-mmap.html
[176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-432/igt@xe_exec_basic@multigpu-no-exec-null-defer-mmap.html
* igt@xe_exec_basic@multigpu-no-exec-null-rebind:
- shard-adlp: NOTRUN -> [SKIP][177] ([Intel XE#1392])
[177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-4/igt@xe_exec_basic@multigpu-no-exec-null-rebind.html
* igt@xe_exec_basic@multigpu-once-bindexecqueue-rebind:
- shard-bmg: NOTRUN -> [SKIP][178] ([Intel XE#2322]) +4 other tests skip
[178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-3/igt@xe_exec_basic@multigpu-once-bindexecqueue-rebind.html
* igt@xe_exec_fault_mode@many-userptr:
- shard-dg2-set2: NOTRUN -> [SKIP][179] ([Intel XE#288]) +25 other tests skip
[179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-433/igt@xe_exec_fault_mode@many-userptr.html
* igt@xe_exec_fault_mode@once-invalid-fault:
- shard-adlp: NOTRUN -> [SKIP][180] ([Intel XE#288]) +1 other test skip
[180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-1/igt@xe_exec_fault_mode@once-invalid-fault.html
* igt@xe_exec_mix_modes@exec-simple-batch-store-lr:
- shard-dg2-set2: NOTRUN -> [SKIP][181] ([Intel XE#2360])
[181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-463/igt@xe_exec_mix_modes@exec-simple-batch-store-lr.html
* igt@xe_exec_sip_eudebug@wait-writesip-nodebug:
- shard-dg2-set2: NOTRUN -> [SKIP][182] ([Intel XE#4837]) +12 other tests skip
[182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-435/igt@xe_exec_sip_eudebug@wait-writesip-nodebug.html
* igt@xe_exec_system_allocator@threads-many-large-execqueues-mmap-huge:
- shard-lnl: NOTRUN -> [SKIP][183] ([Intel XE#4943]) +10 other tests skip
[183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-lnl-7/igt@xe_exec_system_allocator@threads-many-large-execqueues-mmap-huge.html
* igt@xe_exec_system_allocator@threads-many-large-mmap-mlock:
- shard-dg2-set2: NOTRUN -> [SKIP][184] ([Intel XE#4915]) +225 other tests skip
[184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-432/igt@xe_exec_system_allocator@threads-many-large-mmap-mlock.html
* igt@xe_exec_system_allocator@threads-shared-vm-many-execqueues-mmap-new-huge-nomemset:
- shard-adlp: NOTRUN -> [SKIP][185] ([Intel XE#4915]) +23 other tests skip
[185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-8/igt@xe_exec_system_allocator@threads-shared-vm-many-execqueues-mmap-new-huge-nomemset.html
* igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-free-huge:
- shard-bmg: NOTRUN -> [SKIP][186] ([Intel XE#4943]) +17 other tests skip
[186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-5/igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-free-huge.html
* igt@xe_mmap@pci-membarrier-bad-pagesize:
- shard-lnl: NOTRUN -> [SKIP][187] ([Intel XE#5100])
[187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-lnl-2/igt@xe_mmap@pci-membarrier-bad-pagesize.html
* igt@xe_mmap@small-bar:
- shard-dg2-set2: NOTRUN -> [SKIP][188] ([Intel XE#512])
[188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-436/igt@xe_mmap@small-bar.html
* igt@xe_oa@whitelisted-registers-userspace-config:
- shard-dg2-set2: NOTRUN -> [SKIP][189] ([Intel XE#2541] / [Intel XE#3573]) +5 other tests skip
[189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-433/igt@xe_oa@whitelisted-registers-userspace-config.html
- shard-adlp: NOTRUN -> [SKIP][190] ([Intel XE#2541] / [Intel XE#3573])
[190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-6/igt@xe_oa@whitelisted-registers-userspace-config.html
* igt@xe_pat@pat-index-xehpc:
- shard-dg2-set2: NOTRUN -> [SKIP][191] ([Intel XE#2838] / [Intel XE#979])
[191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-433/igt@xe_pat@pat-index-xehpc.html
* igt@xe_pm@d3cold-basic:
- shard-dg2-set2: NOTRUN -> [SKIP][192] ([Intel XE#2284] / [Intel XE#366])
[192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-432/igt@xe_pm@d3cold-basic.html
* igt@xe_pm@s3-vm-bind-unbind-all:
- shard-lnl: NOTRUN -> [SKIP][193] ([Intel XE#584]) +2 other tests skip
[193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-lnl-4/igt@xe_pm@s3-vm-bind-unbind-all.html
* igt@xe_pxp@pxp-stale-bo-bind-post-rpm:
- shard-dg2-set2: NOTRUN -> [SKIP][194] ([Intel XE#4733]) +3 other tests skip
[194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-463/igt@xe_pxp@pxp-stale-bo-bind-post-rpm.html
- shard-adlp: NOTRUN -> [SKIP][195] ([Intel XE#4733])
[195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-8/igt@xe_pxp@pxp-stale-bo-bind-post-rpm.html
* igt@xe_pxp@pxp-termination-key-update-post-termination-irq:
- shard-bmg: NOTRUN -> [SKIP][196] ([Intel XE#4733]) +1 other test skip
[196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-6/igt@xe_pxp@pxp-termination-key-update-post-termination-irq.html
* igt@xe_query@multigpu-query-invalid-uc-fw-version-mbz:
- shard-dg2-set2: NOTRUN -> [SKIP][197] ([Intel XE#944])
[197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-435/igt@xe_query@multigpu-query-invalid-uc-fw-version-mbz.html
* igt@xe_query@multigpu-query-mem-usage:
- shard-lnl: NOTRUN -> [SKIP][198] ([Intel XE#944])
[198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-lnl-7/igt@xe_query@multigpu-query-mem-usage.html
* igt@xe_render_copy@render-stress-2-copies:
- shard-dg2-set2: NOTRUN -> [SKIP][199] ([Intel XE#4814])
[199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-435/igt@xe_render_copy@render-stress-2-copies.html
* igt@xe_sriov_auto_provisioning@resources-released-on-vfs-disabling:
- shard-bmg: NOTRUN -> [SKIP][200] ([Intel XE#4130])
[200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-6/igt@xe_sriov_auto_provisioning@resources-released-on-vfs-disabling.html
- shard-dg2-set2: NOTRUN -> [SKIP][201] ([Intel XE#4130])
[201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-432/igt@xe_sriov_auto_provisioning@resources-released-on-vfs-disabling.html
* igt@xe_sriov_scheduling@nonpreempt-engine-resets:
- shard-dg2-set2: NOTRUN -> [SKIP][202] ([Intel XE#4351])
[202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-433/igt@xe_sriov_scheduling@nonpreempt-engine-resets.html
#### Possible fixes ####
* igt@intel_hwmon@hwmon-write:
- shard-bmg: [FAIL][203] ([Intel XE#4665]) -> [PASS][204]
[203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-bmg-1/igt@intel_hwmon@hwmon-write.html
[204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-5/igt@intel_hwmon@hwmon-write.html
* igt@kms_big_fb@x-tiled-8bpp-rotate-0:
- shard-adlp: [SKIP][205] ([Intel XE#4947]) -> [PASS][206] +2 other tests pass
[205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html
[206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-3/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html
* igt@kms_big_fb@x-tiled-addfb-size-offset-overflow:
- shard-dg2-set2: [SKIP][207] ([Intel XE#2351] / [Intel XE#4208]) -> [PASS][208]
[207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-dg2-436/igt@kms_big_fb@x-tiled-addfb-size-offset-overflow.html
[208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-463/igt@kms_big_fb@x-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-adlp: [DMESG-FAIL][209] ([Intel XE#4543]) -> [PASS][210] +4 other tests pass
[209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-1/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
[210]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-4/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-d-dp-4:
- shard-dg2-set2: [INCOMPLETE][211] ([Intel XE#3862]) -> [PASS][212] +1 other test pass
[211]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-dg2-435/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-d-dp-4.html
[212]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-433/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-d-dp-4.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size:
- shard-bmg: [SKIP][213] ([Intel XE#2291]) -> [PASS][214] +7 other tests pass
[213]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-bmg-5/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
[214]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-1/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc:
- shard-bmg: [SKIP][215] ([Intel XE#1340]) -> [PASS][216]
[215]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-bmg-6/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
[216]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-1/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
* igt@kms_dp_linktrain_fallback@dp-fallback:
- shard-bmg: [SKIP][217] ([Intel XE#4294]) -> [PASS][218]
[217]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-bmg-5/igt@kms_dp_linktrain_fallback@dp-fallback.html
[218]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-3/igt@kms_dp_linktrain_fallback@dp-fallback.html
* igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible:
- shard-bmg: [SKIP][219] ([Intel XE#2316]) -> [PASS][220] +5 other tests pass
[219]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-bmg-5/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible.html
[220]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-8/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a6-dp4:
- shard-dg2-set2: [FAIL][221] ([Intel XE#301] / [Intel XE#3321]) -> [PASS][222] +4 other tests pass
[221]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-dg2-464/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a6-dp4.html
[222]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-436/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a6-dp4.html
* igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a6:
- shard-dg2-set2: [FAIL][223] ([Intel XE#301]) -> [PASS][224] +3 other tests pass
[223]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-dg2-436/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a6.html
[224]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-434/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a6.html
* igt@kms_flip@flip-vs-suspend:
- shard-bmg: [INCOMPLETE][225] ([Intel XE#2049] / [Intel XE#2597]) -> [PASS][226] +1 other test pass
[225]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-bmg-1/igt@kms_flip@flip-vs-suspend.html
[226]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-3/igt@kms_flip@flip-vs-suspend.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-adlp: [DMESG-WARN][227] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][228] +5 other tests pass
[227]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-1/igt@kms_flip@flip-vs-suspend-interruptible.html
[228]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-9/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-valid-mode:
- shard-adlp: [DMESG-FAIL][229] ([Intel XE#4543] / [Intel XE#4921]) -> [PASS][230] +3 other tests pass
[229]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-8/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-valid-mode.html
[230]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-3/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-valid-mode.html
* igt@kms_hdr@static-swap:
- shard-bmg: [SKIP][231] ([Intel XE#1503]) -> [PASS][232] +1 other test pass
[231]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-bmg-6/igt@kms_hdr@static-swap.html
[232]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-5/igt@kms_hdr@static-swap.html
* igt@kms_joiner@basic-force-big-joiner:
- shard-bmg: [SKIP][233] ([Intel XE#3012]) -> [PASS][234]
[233]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-bmg-6/igt@kms_joiner@basic-force-big-joiner.html
[234]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-1/igt@kms_joiner@basic-force-big-joiner.html
* igt@kms_plane_cursor@overlay@pipe-a-hdmi-a-6-size-64:
- shard-dg2-set2: [FAIL][235] ([Intel XE#616]) -> [PASS][236] +1 other test pass
[235]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-dg2-463/igt@kms_plane_cursor@overlay@pipe-a-hdmi-a-6-size-64.html
[236]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-435/igt@kms_plane_cursor@overlay@pipe-a-hdmi-a-6-size-64.html
* igt@kms_plane_multiple@tiling-none:
- shard-dg2-set2: [INCOMPLETE][237] -> [PASS][238] +2 other tests pass
[237]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-dg2-432/igt@kms_plane_multiple@tiling-none.html
[238]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-435/igt@kms_plane_multiple@tiling-none.html
* igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation:
- shard-adlp: [SKIP][239] ([Intel XE#4950]) -> [PASS][240] +9 other tests pass
[239]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation.html
[240]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-1/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation.html
* igt@kms_pm_dc@dc5-psr:
- shard-lnl: [FAIL][241] ([Intel XE#718]) -> [PASS][242]
[241]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-lnl-8/igt@kms_pm_dc@dc5-psr.html
[242]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-lnl-2/igt@kms_pm_dc@dc5-psr.html
* igt@kms_pm_rpm@drm-resources-equal:
- shard-adlp: [SKIP][243] ([Intel XE#4962]) -> [PASS][244]
[243]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@kms_pm_rpm@drm-resources-equal.html
[244]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-8/igt@kms_pm_rpm@drm-resources-equal.html
* igt@kms_prop_blob@invalid-set-prop-any:
- shard-dg2-set2: [SKIP][245] ([Intel XE#4208] / [i915#2575]) -> [PASS][246] +6 other tests pass
[245]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-dg2-436/igt@kms_prop_blob@invalid-set-prop-any.html
[246]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-432/igt@kms_prop_blob@invalid-set-prop-any.html
* igt@kms_vrr@cmrr@pipe-a-edp-1:
- shard-lnl: [FAIL][247] ([Intel XE#4459]) -> [PASS][248] +1 other test pass
[247]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-lnl-2/igt@kms_vrr@cmrr@pipe-a-edp-1.html
[248]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-lnl-2/igt@kms_vrr@cmrr@pipe-a-edp-1.html
* igt@kms_vrr@max-min:
- shard-lnl: [FAIL][249] ([Intel XE#4227]) -> [PASS][250] +1 other test pass
[249]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-lnl-2/igt@kms_vrr@max-min.html
[250]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-lnl-2/igt@kms_vrr@max-min.html
* igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr:
- shard-dg2-set2: [SKIP][251] ([Intel XE#1392]) -> [PASS][252] +5 other tests pass
[251]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-dg2-432/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr.html
[252]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-434/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr.html
* igt@xe_exec_compute_mode@once-basic:
- shard-dg2-set2: [SKIP][253] ([Intel XE#4208]) -> [PASS][254] +4 other tests pass
[253]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-dg2-436/igt@xe_exec_compute_mode@once-basic.html
[254]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-433/igt@xe_exec_compute_mode@once-basic.html
* igt@xe_exec_system_allocator@threads-shared-vm-many-large-new-bo-map-nomemset:
- shard-lnl: [FAIL][255] ([Intel XE#5018]) -> [PASS][256]
[255]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-lnl-6/igt@xe_exec_system_allocator@threads-shared-vm-many-large-new-bo-map-nomemset.html
[256]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-lnl-1/igt@xe_exec_system_allocator@threads-shared-vm-many-large-new-bo-map-nomemset.html
* igt@xe_exec_threads@threads-bal-rebind:
- shard-adlp: [SKIP][257] ([Intel XE#4945]) -> [PASS][258] +10 other tests pass
[257]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@xe_exec_threads@threads-bal-rebind.html
[258]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-3/igt@xe_exec_threads@threads-bal-rebind.html
* igt@xe_live_ktest@xe_dma_buf:
- shard-adlp: [FAIL][259] ([Intel XE#3099]) -> [PASS][260] +1 other test pass
[259]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@xe_live_ktest@xe_dma_buf.html
[260]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-3/igt@xe_live_ktest@xe_dma_buf.html
#### Warnings ####
* igt@kms_big_fb@4-tiled-8bpp-rotate-90:
- shard-adlp: [SKIP][261] ([Intel XE#4947]) -> [SKIP][262] ([Intel XE#1124]) +1 other test skip
[261]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@kms_big_fb@4-tiled-8bpp-rotate-90.html
[262]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-3/igt@kms_big_fb@4-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@linear-16bpp-rotate-270:
- shard-dg2-set2: [SKIP][263] ([Intel XE#4208]) -> [SKIP][264] ([Intel XE#316])
[263]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-dg2-436/igt@kms_big_fb@linear-16bpp-rotate-270.html
[264]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-432/igt@kms_big_fb@linear-16bpp-rotate-270.html
- shard-adlp: [SKIP][265] ([Intel XE#4947]) -> [SKIP][266] ([Intel XE#316])
[265]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@kms_big_fb@linear-16bpp-rotate-270.html
[266]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-2/igt@kms_big_fb@linear-16bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-180:
- shard-adlp: [SKIP][267] ([Intel XE#4947]) -> [DMESG-FAIL][268] ([Intel XE#4543])
[267]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@kms_big_fb@y-tiled-8bpp-rotate-180.html
[268]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-8/igt@kms_big_fb@y-tiled-8bpp-rotate-180.html
- shard-dg2-set2: [SKIP][269] ([Intel XE#4208]) -> [SKIP][270] ([Intel XE#1124])
[269]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-dg2-436/igt@kms_big_fb@y-tiled-8bpp-rotate-180.html
[270]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-463/igt@kms_big_fb@y-tiled-8bpp-rotate-180.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
- shard-adlp: [DMESG-WARN][271] ([Intel XE#2953] / [Intel XE#4173]) -> [DMESG-FAIL][272] ([Intel XE#4543])
[271]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-6/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
[272]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-6/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
* igt@kms_bw@connected-linear-tiling-1-displays-3840x2160p:
- shard-adlp: [SKIP][273] ([Intel XE#4950]) -> [SKIP][274] ([Intel XE#367])
[273]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@kms_bw@connected-linear-tiling-1-displays-3840x2160p.html
[274]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-6/igt@kms_bw@connected-linear-tiling-1-displays-3840x2160p.html
* igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc:
- shard-adlp: [SKIP][275] ([Intel XE#4947]) -> [SKIP][276] ([Intel XE#455] / [Intel XE#787])
[275]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc.html
[276]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-3/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc.html
* igt@kms_chamelium_color@ctm-0-25:
- shard-adlp: [SKIP][277] ([Intel XE#4950]) -> [SKIP][278] ([Intel XE#306])
[277]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@kms_chamelium_color@ctm-0-25.html
[278]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-3/igt@kms_chamelium_color@ctm-0-25.html
* igt@kms_content_protection@uevent:
- shard-bmg: [FAIL][279] ([Intel XE#1188]) -> [SKIP][280] ([Intel XE#2341])
[279]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-bmg-1/igt@kms_content_protection@uevent.html
[280]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-6/igt@kms_content_protection@uevent.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-adlp: [SKIP][281] ([Intel XE#4950]) -> [SKIP][282] ([Intel XE#309]) +1 other test skip
[281]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
[282]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-2/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
* igt@kms_fbcon_fbt@psr:
- shard-adlp: [SKIP][283] ([Intel XE#4947]) -> [SKIP][284] ([Intel XE#776])
[283]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@kms_fbcon_fbt@psr.html
[284]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-4/igt@kms_fbcon_fbt@psr.html
- shard-dg2-set2: [SKIP][285] ([Intel XE#4208]) -> [SKIP][286] ([Intel XE#776])
[285]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-dg2-436/igt@kms_fbcon_fbt@psr.html
[286]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-435/igt@kms_fbcon_fbt@psr.html
* igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
- shard-adlp: [SKIP][287] ([Intel XE#4950]) -> [SKIP][288] ([Intel XE#310])
[287]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html
[288]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-3/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html
* igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-fullscreen:
- shard-adlp: [SKIP][289] ([Intel XE#4947]) -> [SKIP][290] ([Intel XE#651]) +1 other test skip
[289]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-fullscreen.html
[290]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-1/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-fullscreen.html
- shard-dg2-set2: [SKIP][291] ([Intel XE#4208]) -> [SKIP][292] ([Intel XE#651]) +1 other test skip
[291]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-dg2-436/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-fullscreen.html
[292]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-433/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-fullscreen.html
* igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-mmap-wc:
- shard-adlp: [SKIP][293] ([Intel XE#2351] / [Intel XE#4947]) -> [SKIP][294] ([Intel XE#656])
[293]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-mmap-wc.html
[294]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-3/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-mmap-wc.html
- shard-dg2-set2: [SKIP][295] ([Intel XE#2351] / [Intel XE#4208]) -> [SKIP][296] ([Intel XE#651])
[295]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-dg2-436/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-mmap-wc.html
[296]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-433/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][297] ([Intel XE#2312]) -> [SKIP][298] ([Intel XE#2311]) +19 other tests skip
[297]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html
[298]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-8/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render:
- shard-bmg: [SKIP][299] ([Intel XE#2312]) -> [SKIP][300] ([Intel XE#4141]) +10 other tests skip
[299]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html
[300]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt:
- shard-adlp: [SKIP][301] ([Intel XE#4947]) -> [SKIP][302] ([Intel XE#656]) +3 other tests skip
[301]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt.html
[302]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render:
- shard-bmg: [SKIP][303] ([Intel XE#4141]) -> [SKIP][304] ([Intel XE#2312]) +10 other tests skip
[303]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html
[304]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][305] ([Intel XE#2311]) -> [SKIP][306] ([Intel XE#2312]) +21 other tests skip
[305]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html
[306]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-mmap-wc:
- shard-adlp: [SKIP][307] ([Intel XE#2351] / [Intel XE#4947]) -> [SKIP][308] ([Intel XE#651])
[307]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-mmap-wc.html
[308]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-9/igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw:
- shard-bmg: [SKIP][309] ([Intel XE#2312]) -> [SKIP][310] ([Intel XE#2313]) +19 other tests skip
[309]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw.html
[310]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-msflip-blt:
- shard-dg2-set2: [SKIP][311] ([Intel XE#4208]) -> [SKIP][312] ([Intel XE#653])
[311]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-dg2-436/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-msflip-blt.html
[312]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-463/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary:
- shard-adlp: [SKIP][313] ([Intel XE#4947]) -> [SKIP][314] ([Intel XE#653]) +1 other test skip
[313]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary.html
[314]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-8/igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary.html
- shard-dg2-set2: [SKIP][315] ([Intel XE#2351] / [Intel XE#4208]) -> [SKIP][316] ([Intel XE#653])
[315]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-dg2-436/igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary.html
[316]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-463/igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt:
- shard-bmg: [SKIP][317] ([Intel XE#2313]) -> [SKIP][318] ([Intel XE#2312]) +23 other tests skip
[317]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-bmg-3/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
[318]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
* igt@kms_hdr@brightness-with-hdr:
- shard-dg2-set2: [SKIP][319] ([Intel XE#4208] / [i915#2575]) -> [SKIP][320] ([Intel XE#455])
[319]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-dg2-436/igt@kms_hdr@brightness-with-hdr.html
[320]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-434/igt@kms_hdr@brightness-with-hdr.html
* igt@kms_plane_multiple@2x-tiling-y:
- shard-bmg: [SKIP][321] ([Intel XE#4596]) -> [SKIP][322] ([Intel XE#5021])
[321]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-bmg-5/igt@kms_plane_multiple@2x-tiling-y.html
[322]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-bmg-1/igt@kms_plane_multiple@2x-tiling-y.html
* igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf:
- shard-adlp: [SKIP][323] ([Intel XE#4947]) -> [SKIP][324] ([Intel XE#1489])
[323]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf.html
[324]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-8/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf.html
* igt@kms_vrr@flip-basic:
- shard-adlp: [SKIP][325] ([Intel XE#4950]) -> [SKIP][326] ([Intel XE#455]) +1 other test skip
[325]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@kms_vrr@flip-basic.html
[326]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-9/igt@kms_vrr@flip-basic.html
* igt@xe_copy_basic@mem-set-linear-0xfffe:
- shard-adlp: [SKIP][327] ([Intel XE#4945]) -> [SKIP][328] ([Intel XE#1126])
[327]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@xe_copy_basic@mem-set-linear-0xfffe.html
[328]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-9/igt@xe_copy_basic@mem-set-linear-0xfffe.html
* igt@xe_eudebug_online@interrupt-reconnect:
- shard-adlp: [SKIP][329] ([Intel XE#4945]) -> [SKIP][330] ([Intel XE#4837])
[329]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@xe_eudebug_online@interrupt-reconnect.html
[330]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-8/igt@xe_eudebug_online@interrupt-reconnect.html
- shard-dg2-set2: [SKIP][331] ([Intel XE#4208]) -> [SKIP][332] ([Intel XE#4837])
[331]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-dg2-436/igt@xe_eudebug_online@interrupt-reconnect.html
[332]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-463/igt@xe_eudebug_online@interrupt-reconnect.html
* igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-rebind:
- shard-adlp: [SKIP][333] ([Intel XE#4945]) -> [SKIP][334] ([Intel XE#1392])
[333]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-rebind.html
[334]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-8/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-rebind.html
* igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate-imm:
- shard-adlp: [SKIP][335] ([Intel XE#4945]) -> [SKIP][336] ([Intel XE#288]) +1 other test skip
[335]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate-imm.html
[336]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-4/igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate-imm.html
- shard-dg2-set2: [SKIP][337] ([Intel XE#4208]) -> [SKIP][338] ([Intel XE#288])
[337]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-dg2-436/igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate-imm.html
[338]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-436/igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate-imm.html
* igt@xe_exec_reset@cm-cat-error:
- shard-adlp: [SKIP][339] ([Intel XE#4945]) -> [DMESG-FAIL][340] ([Intel XE#3868])
[339]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@xe_exec_reset@cm-cat-error.html
[340]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-6/igt@xe_exec_reset@cm-cat-error.html
* igt@xe_exec_system_allocator@many-large-mmap-remap-dontunmap-eocheck:
- shard-adlp: [SKIP][341] ([Intel XE#4945]) -> [SKIP][342] ([Intel XE#4915]) +33 other tests skip
[341]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@xe_exec_system_allocator@many-large-mmap-remap-dontunmap-eocheck.html
[342]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-2/igt@xe_exec_system_allocator@many-large-mmap-remap-dontunmap-eocheck.html
* igt@xe_exec_system_allocator@threads-many-new-race-nomemset:
- shard-dg2-set2: [SKIP][343] ([Intel XE#4208]) -> [SKIP][344] ([Intel XE#4915]) +16 other tests skip
[343]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-dg2-436/igt@xe_exec_system_allocator@threads-many-new-race-nomemset.html
[344]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-dg2-433/igt@xe_exec_system_allocator@threads-many-new-race-nomemset.html
* igt@xe_oa@invalid-create-userspace-config:
- shard-adlp: [SKIP][345] ([Intel XE#4945]) -> [SKIP][346] ([Intel XE#2541] / [Intel XE#3573])
[345]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@xe_oa@invalid-create-userspace-config.html
[346]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/shard-adlp-6/igt@xe_oa@invalid-create-userspace-config.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[Intel XE#1091]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1091
[Intel XE#1123]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1123
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1126
[Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
[Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
[Intel XE#1188]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1188
[Intel XE#1340]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1340
[Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
[Intel XE#1401]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1401
[Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
[Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
[Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
[Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
[Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
[Intel XE#1467]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1467
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
[Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
[Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
[Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
[Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
[Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
[Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
[Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
[Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
[Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
[Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
[Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
[Intel XE#2328]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2328
[Intel XE#2330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2330
[Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
[Intel XE#2351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2351
[Intel XE#2360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2360
[Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
[Intel XE#2390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2390
[Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
[Intel XE#2501]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2501
[Intel XE#2541]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2541
[Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
[Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
[Intel XE#2724]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2724
[Intel XE#2838]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2838
[Intel XE#2849]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2849
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
[Intel XE#2882]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2882
[Intel XE#2883]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2883
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
[Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
[Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#3012]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3012
[Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
[Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
[Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
[Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
[Intel XE#3098]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3098
[Intel XE#3099]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3099
[Intel XE#310]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/310
[Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
[Intel XE#3124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3124
[Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
[Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
[Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
[Intel XE#3321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3321
[Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
[Intel XE#346]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/346
[Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
[Intel XE#356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/356
[Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
[Intel XE#362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/362
[Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
[Intel XE#3767]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3767
[Intel XE#3862]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3862
[Intel XE#3868]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3868
[Intel XE#3884]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3884
[Intel XE#4130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4130
[Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
[Intel XE#4164]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4164
[Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
[Intel XE#4208]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4208
[Intel XE#4227]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4227
[Intel XE#4294]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4294
[Intel XE#4302]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4302
[Intel XE#4329]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4329
[Intel XE#4351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4351
[Intel XE#4359]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4359
[Intel XE#4417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4417
[Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
[Intel XE#4459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4459
[Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
[Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
[Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
[Intel XE#4608]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4608
[Intel XE#4609]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4609
[Intel XE#4665]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4665
[Intel XE#4689]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4689
[Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
[Intel XE#4814]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4814
[Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
[Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
[Intel XE#4921]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4921
[Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
[Intel XE#4945]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4945
[Intel XE#4947]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4947
[Intel XE#4950]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4950
[Intel XE#4962]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4962
[Intel XE#5018]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5018
[Intel XE#5020]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5020
[Intel XE#5021]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5021
[Intel XE#5100]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5100
[Intel XE#512]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/512
[Intel XE#5191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5191
[Intel XE#5300]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5300
[Intel XE#5308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5308
[Intel XE#584]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/584
[Intel XE#616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/616
[Intel XE#619]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/619
[Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
[Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
[Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
[Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
[Intel XE#718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/718
[Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776
[Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
[Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
[Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
[Intel XE#886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/886
[Intel XE#908]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/908
[Intel XE#911]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/911
[Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
[Intel XE#979]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/979
[i915#2575]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2575
Build changes
-------------
* IGT: IGT_8423 -> IGT_8424
* Linux: xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201 -> xe-pw-149108v9
IGT_8423: 8423
IGT_8424: 68588b3c89a1bbe08c54d21c4d3d2e509957c795 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201: fb5dada21e3cfa26179ca58e1d7c26cdad217201
xe-pw-149108v9: 149108v9
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149108v9/index.html
[-- Attachment #2: Type: text/html, Size: 111899 bytes --]
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v9 1/3] drm/xe/vf: Create contexts for CCS read write
2025-06-24 17:01 ` Matthew Brost
@ 2025-06-25 12:46 ` K V P, Satyanarayana
0 siblings, 0 replies; 13+ messages in thread
From: K V P, Satyanarayana @ 2025-06-25 12:46 UTC (permalink / raw)
To: Matthew Brost
Cc: intel-xe, Michal Wajdeczko, Michał Winiarski, Tomasz Lis,
Matthew Auld
[-- Attachment #1: Type: text/plain, Size: 21985 bytes --]
On 24-06-2025 22:31, Matthew Brost wrote:
> On Tue, Jun 24, 2025 at 03:30:08PM +0530, Satyanarayana K V P wrote:
>> Create two LRCs to handle CCS meta data read / write from CCS pool in the
>> VM. Read context is used to hold GPU instructions to be executed at save
>> time and write context is used to hold GPU instructions to be executed at
>> the restore time.
>>
>> Allocate batch buffer pool using suballocator for both read and write
>> contexts.
>>
>> Migration framework is reused to create LRCAs for read and write.
>>
> One more thing.
>
>
>> Signed-off-by: Satyanarayana K V P<satyanarayana.k.v.p@intel.com>
>> Cc: Michal Wajdeczko<michal.wajdeczko@intel.com>
>> Cc: Matthew Brost<matthew.brost@intel.com>
>> Cc: Michał Winiarski<michal.winiarski@intel.com>
>> Acked-by: Matthew Brost<matthew.brost@intel.com>
>> ---
>> Cc: Tomasz Lis<tomasz.lis@intel.com>
>> Cc: Matthew Auld<matthew.auld@intel.com>
>>
>> V8 -> V9:
>> - Initialized CCS read write contexts for only root tile (Matthew Brost).
>>
>> V7 -> V8:
>> - None.
>>
>> V6 -> V7:
>> - Fixed review comments (Michal Wajdeczko & Matthew Brost).
>>
>> V5 -> V6:
>> - Added id field in the xe_tile_vf_ccs structure for self identification.
>>
>> V4 -> V5:
>> - Modified read/write contexts to enums from #defines (Matthew Brost).
>> - The CCS BB pool size is calculated based on the system memory size (Michal
>> Wajdeczko & Matthew Brost).
>>
>> V3 -> V4:
>> - Fixed issues reported by patchworks.
>>
>> V2 -> V3:
>> - Added new variable which denotes the initialization of contexts.
>>
>> V1 -> V2:
>> - Fixed review comments.
>> ---
>> drivers/gpu/drm/xe/Makefile | 1 +
>> drivers/gpu/drm/xe/xe_device.c | 4 +
>> drivers/gpu/drm/xe/xe_device_types.h | 4 +
>> drivers/gpu/drm/xe/xe_gt_debugfs.c | 36 ++++
>> drivers/gpu/drm/xe/xe_sriov.c | 19 ++
>> drivers/gpu/drm/xe/xe_sriov.h | 1 +
>> drivers/gpu/drm/xe/xe_sriov_types.h | 5 +
>> drivers/gpu/drm/xe/xe_sriov_vf_ccs.c | 208 +++++++++++++++++++++
>> drivers/gpu/drm/xe/xe_sriov_vf_ccs.h | 13 ++
>> drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h | 45 +++++
>> 10 files changed, 336 insertions(+)
>> create mode 100644 drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
>> create mode 100644 drivers/gpu/drm/xe/xe_sriov_vf_ccs.h
>> create mode 100644 drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h
>>
>> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
>> index eee6bac01a00..853970ab1314 100644
>> --- a/drivers/gpu/drm/xe/Makefile
>> +++ b/drivers/gpu/drm/xe/Makefile
>> @@ -141,6 +141,7 @@ xe-y += \
>> xe_memirq.o \
>> xe_sriov.o \
>> xe_sriov_vf.o \
>> + xe_sriov_vf_ccs.o \
>> xe_tile_sriov_vf.o
>>
>> xe-$(CONFIG_PCI_IOV) += \
>> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
>> index e160e7be84f0..b7922668741c 100644
>> --- a/drivers/gpu/drm/xe/xe_device.c
>> +++ b/drivers/gpu/drm/xe/xe_device.c
>> @@ -929,6 +929,10 @@ int xe_device_probe(struct xe_device *xe)
>>
>> xe_vsec_init(xe);
>>
>> + err = xe_sriov_late_init(xe);
>> + if (err)
>> + goto err_unregister_display;
>> +
>> return devm_add_action_or_reset(xe->drm.dev, xe_device_sanitize, xe);
>>
>> err_unregister_display:
>> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
>> index 6aca4b1a2824..1b52db967ace 100644
>> --- a/drivers/gpu/drm/xe/xe_device_types.h
>> +++ b/drivers/gpu/drm/xe/xe_device_types.h
>> @@ -22,6 +22,7 @@
>> #include "xe_pmu_types.h"
>> #include "xe_pt_types.h"
>> #include "xe_sriov_types.h"
>> +#include "xe_sriov_vf_ccs_types.h"
>> #include "xe_step_types.h"
>> #include "xe_survivability_mode_types.h"
>> #include "xe_ttm_vram_mgr_types.h"
>> @@ -235,6 +236,9 @@ struct xe_tile {
>> struct {
>> /** @sriov.vf.ggtt_balloon: GGTT regions excluded from use. */
>> struct xe_ggtt_node *ggtt_balloon[2];
>> +
>> + /** @sriov.vf.ccs: CCS read and write contexts for VF. */
>> + struct xe_tile_vf_ccs ccs[XE_SRIOV_VF_CCS_CTX_COUNT];
>> } vf;
>> } sriov;
>>
>> diff --git a/drivers/gpu/drm/xe/xe_gt_debugfs.c b/drivers/gpu/drm/xe/xe_gt_debugfs.c
>> index 848618acdca8..404844515523 100644
>> --- a/drivers/gpu/drm/xe/xe_gt_debugfs.c
>> +++ b/drivers/gpu/drm/xe/xe_gt_debugfs.c
>> @@ -134,6 +134,30 @@ static int sa_info(struct xe_gt *gt, struct drm_printer *p)
>> return 0;
>> }
>>
>> +static int sa_info_vf_ccs(struct xe_gt *gt, struct drm_printer *p)
>> +{
>> + struct xe_tile *tile = gt_to_tile(gt);
>> + struct xe_sa_manager *bb_pool;
>> + enum xe_sriov_vf_ccs_rw_ctxs ctx_id;
>> +
>> + if (!IS_VF_CCS_READY(gt_to_xe(gt)))
>> + return 0;
>> +
>> + xe_pm_runtime_get(gt_to_xe(gt));
>> +
>> + for_each_ccs_rw_ctx(ctx_id) {
>> + drm_printf(p, "ccs %s bb suballoc info\n", ctx_id ? "write" : "read");
>> + drm_printf(p, "-------------------------\n");
>> + bb_pool = tile->sriov.vf.ccs[ctx_id].mem.ccs_bb_pool;
Skipped loop if bb_pool is NULL.
>> + drm_suballoc_dump_debug_info(&bb_pool->base, p, bb_pool->gpu_addr);
>> + drm_puts(p, "\n");
>> + }
>> +
>> + xe_pm_runtime_put(gt_to_xe(gt));
>> +
>> + return 0;
>> +}
>> +
>> static int topology(struct xe_gt *gt, struct drm_printer *p)
>> {
>> xe_pm_runtime_get(gt_to_xe(gt));
>> @@ -303,6 +327,13 @@ static const struct drm_info_list vf_safe_debugfs_list[] = {
>> {"hwconfig", .show = xe_gt_debugfs_simple_show, .data = hwconfig},
>> };
>>
>> +/*
>> + * only for GT debugfs files which are valid on VF. Not valid on PF.
>> + */
>> +static const struct drm_info_list vf_only_debugfs_list[] = {
>> + {"sa_info_vf_ccs", .show = xe_gt_debugfs_simple_show, .data = sa_info_vf_ccs},
>> +};
>> +
>> /* everything else should be added here */
>> static const struct drm_info_list pf_only_debugfs_list[] = {
>> {"hw_engines", .show = xe_gt_debugfs_simple_show, .data = hw_engines},
>> @@ -419,6 +450,11 @@ void xe_gt_debugfs_register(struct xe_gt *gt)
>> drm_debugfs_create_files(pf_only_debugfs_list,
>> ARRAY_SIZE(pf_only_debugfs_list),
>> root, minor);
>> + else
>> + drm_debugfs_create_files(vf_only_debugfs_list,
>> + ARRAY_SIZE(vf_only_debugfs_list),
>> + root, minor);
>> +
>>
>> xe_uc_debugfs_register(>->uc, root);
>>
>> diff --git a/drivers/gpu/drm/xe/xe_sriov.c b/drivers/gpu/drm/xe/xe_sriov.c
>> index a0eab44c0e76..87911fb4eea7 100644
>> --- a/drivers/gpu/drm/xe/xe_sriov.c
>> +++ b/drivers/gpu/drm/xe/xe_sriov.c
>> @@ -15,6 +15,7 @@
>> #include "xe_sriov.h"
>> #include "xe_sriov_pf.h"
>> #include "xe_sriov_vf.h"
>> +#include "xe_sriov_vf_ccs.h"
>>
>> /**
>> * xe_sriov_mode_to_string - Convert enum value to string.
>> @@ -157,3 +158,21 @@ const char *xe_sriov_function_name(unsigned int n, char *buf, size_t size)
>> strscpy(buf, "PF", size);
>> return buf;
>> }
>> +
>> +/**
>> + * xe_sriov_late_init() - SR-IOV late initialization functions.
>> + * @xe: the &xe_device to initialize
>> + *
>> + * On VF this function will initialize code for CCS migration.
>> + *
>> + * Return: 0 on success or a negative error code on failure.
>> + */
>> +int xe_sriov_late_init(struct xe_device *xe)
>> +{
>> + int err = 0;
>> +
>> + if (IS_VF_CCS_INIT_NEEDED(xe))
>> + err = xe_sriov_vf_ccs_init(xe);
>> +
>> + return err;
>> +}
>> diff --git a/drivers/gpu/drm/xe/xe_sriov.h b/drivers/gpu/drm/xe/xe_sriov.h
>> index 688fbabf08f1..0e0c1abf2d14 100644
>> --- a/drivers/gpu/drm/xe/xe_sriov.h
>> +++ b/drivers/gpu/drm/xe/xe_sriov.h
>> @@ -18,6 +18,7 @@ const char *xe_sriov_function_name(unsigned int n, char *buf, size_t len);
>> void xe_sriov_probe_early(struct xe_device *xe);
>> void xe_sriov_print_info(struct xe_device *xe, struct drm_printer *p);
>> int xe_sriov_init(struct xe_device *xe);
>> +int xe_sriov_late_init(struct xe_device *xe);
>>
>> static inline enum xe_sriov_mode xe_device_sriov_mode(const struct xe_device *xe)
>> {
>> diff --git a/drivers/gpu/drm/xe/xe_sriov_types.h b/drivers/gpu/drm/xe/xe_sriov_types.h
>> index ca94382a721e..8abfdb2c5ead 100644
>> --- a/drivers/gpu/drm/xe/xe_sriov_types.h
>> +++ b/drivers/gpu/drm/xe/xe_sriov_types.h
>> @@ -71,6 +71,11 @@ struct xe_device_vf {
>> /** @migration.gt_flags: Per-GT request flags for VF migration recovery */
>> unsigned long gt_flags;
>> } migration;
>> +
>> + struct {
>> + /** @initialized: Initilalization of vf ccs is completed or not */
>> + bool initialized;
>> + } ccs;
>> };
>>
>> #endif
>> diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
>> new file mode 100644
>> index 000000000000..9000d618978d
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
>> @@ -0,0 +1,208 @@
>> +// SPDX-License-Identifier: MIT
>> +/*
>> + * Copyright © 2025 Intel Corporation
>> + */
>> +
>> +#include "instructions/xe_mi_commands.h"
>> +#include "instructions/xe_gpu_commands.h"
>> +#include "xe_bo.h"
>> +#include "xe_device.h"
>> +#include "xe_migrate.h"
>> +#include "xe_sa.h"
>> +#include "xe_sriov_printk.h"
>> +#include "xe_sriov_vf_ccs.h"
>> +#include "xe_sriov_vf_ccs_types.h"
>> +
>> +/**
>> + * DOC: VF save/restore of compression Meta Data
>> + *
>> + * VF KMD registers two special contexts/LRCAs.
>> + *
>> + * Save Context/LRCA: contain necessary cmds+page table to trigger Meta data /
>> + * compression control surface (Aka CCS) save in regular System memory in VM.
>> + *
>> + * Restore Context/LRCA: contain necessary cmds+page table to trigger Meta data /
>> + * compression control surface (Aka CCS) Restore from regular System memory in
>> + * VM to corresponding CCS pool.
>> + *
>> + * Below diagram explain steps needed for VF save/Restore of compression Meta Data::
>> + *
>> + * CCS Save CCS Restore VF KMD Guc BCS
>> + * LRCA LRCA
>> + * | | | | |
>> + * | | | | |
>> + * | Create Save LRCA | | |
>> + * [ ]<----------------------------- [ ] | |
>> + * | | | | |
>> + * | | | | |
>> + * | | | Register save LRCA | |
>> + * | | | with Guc | |
>> + * | | [ ]--------------------------->[ ] |
>> + * | | | | |
>> + * | | Create restore LRCA | | |
>> + * | [ ]<------------------[ ] | |
>> + * | | | | |
>> + * | | | Register restore LRCA | |
>> + * | | | with Guc | |
>> + * | | [ ]--------------------------->[ ] |
>> + * | | | | |
>> + * | | | | |
>> + * | | [ ]------------------------- | |
>> + * | | [ ] Allocate main memory. | | |
>> + * | | [ ] Allocate CCS memory. | | |
>> + * | | [ ] Update Main memory & | | |
>> + * [ ]<------------------------------[ ] CCS pages PPGTT + BB | | |
>> + * | [ ]<------------------[ ] cmds to save & restore.| | |
>> + * | | [ ]<------------------------ | |
>> + * | | | | |
>> + * | | | | |
>> + * | | | | |
>> + * : : : : :
>> + * ---------------------------- VF Paused -------------------------------------
>> + * | | | | |
>> + * | | | | |
>> + * | | | |Schedule |
>> + * | | | |CCS Save |
>> + * | | | | LRCA |
>> + * | | | [ ]------>[ ]
>> + * | | | | |
>> + * | | | | |
>> + * | | | |CCS save |
>> + * | | | |completed|
>> + * | | | [ ]<------[ ]
>> + * | | | | |
>> + * : : : : :
>> + * ---------------------------- VM Migrated -----------------------------------
>> + * | | | | |
>> + * | | | | |
>> + * : : : : :
>> + * ---------------------------- VF Resumed ------------------------------------
>> + * | | | | |
>> + * | | | | |
>> + * | | [ ]-------------- | |
>> + * | | [ ] Fix up GGTT | | |
>> + * | | [ ]<------------- | |
>> + * | | | | |
>> + * | | | | |
>> + * | | | Notify VF_RESFIX_DONE | |
>> + * | | [ ]--------------------------->[ ] |
>> + * | | | | |
>> + * | | | |Schedule |
>> + * | | | |CCS |
>> + * | | | |Restore |
>> + * | | | |LRCA |
>> + * | | | [ ]------>[ ]
>> + * | | | | |
>> + * | | | | |
>> + * | | | |CCS |
>> + * | | | |restore |
>> + * | | | |completed|
>> + * | | | [ ]<------[ ]
>> + * | | | | |
>> + * | | | | |
>> + * | | | VF_RESFIX_DONE complete | |
>> + * | | | notification | |
>> + * | | [ ]<---------------------------[ ] |
>> + * | | | | |
>> + * | | | | |
>> + * : : : : :
>> + * ------------------------- Continue VM restore ------------------------------
>> + */
>> +
>> +static u64 get_ccs_bb_pool_size(struct xe_device *xe)
>> +{
>> + u64 sys_mem_size, ccs_mem_size, ptes, bb_pool_size;
>> + struct sysinfo si;
>> +
>> + si_meminfo(&si);
>> + sys_mem_size = si.totalram * si.mem_unit;
>> + ccs_mem_size = sys_mem_size / NUM_BYTES_PER_CCS_BYTE(xe);
>> + ptes = DIV_ROUND_UP(sys_mem_size + ccs_mem_size, XE_PAGE_SIZE);
> s/DIV_ROUND_UP/DIV_ROUND_UP_ULL
>
> I'm pretty sure this is the CI hooks failure.
>
> Matt
The issue is due to ccs_mem_size = sys_mem_size / NUM_BYTES_PER_CCS_BYTE(xe);
Fixed both in the new version.
-Satya.
>
>> +
>> + /**
>> + * We need below BB size to hold PTE mappings and some DWs for copy
>> + * command. In reality, we need space for many copy commands. So, let
>> + * us allocate double the calculated size which is enough to holds GPU
>> + * instructions for the whole region.
>> + */
>> + bb_pool_size = ptes * sizeof(u32);
>> +
>> + return round_up(bb_pool_size * 2, SZ_1M);
>> +}
>> +
>> +static int alloc_bb_pool(struct xe_tile *tile, struct xe_tile_vf_ccs *ctx)
>> +{
>> + struct xe_device *xe = tile_to_xe(tile);
>> + struct xe_sa_manager *sa_manager;
>> + u64 bb_pool_size;
>> + int offset, err;
>> +
>> + bb_pool_size = get_ccs_bb_pool_size(xe);
>> + xe_sriov_info(xe, "Allocating %s CCS BB pool size = %lldMB\n",
>> + ctx->ctx_id ? "Restore" : "Save", bb_pool_size / SZ_1M);
>> +
>> + sa_manager = xe_sa_bo_manager_init(tile, bb_pool_size, SZ_16);
>> +
>> + if (IS_ERR(sa_manager)) {
>> + xe_sriov_err(xe, "Suballocator init failed with error: %pe\n",
>> + sa_manager);
>> + err = PTR_ERR(sa_manager);
>> + return err;
>> + }
>> +
>> + offset = 0;
>> + xe_map_memset(xe, &sa_manager->bo->vmap, offset, MI_NOOP,
>> + bb_pool_size);
>> +
>> + offset = bb_pool_size - sizeof(u32);
>> + xe_map_wr(xe, &sa_manager->bo->vmap, offset, u32, MI_BATCH_BUFFER_END);
>> +
>> + ctx->mem.ccs_bb_pool = sa_manager;
>> +
>> + return 0;
>> +}
>> +
>> +/**
>> + * xe_sriov_vf_ccs_init - Setup LRCA for save & restore.
>> + * @xe: the &xe_device to start recovery on
>> + *
>> + * This function shall be called only by VF. It initializes
>> + * LRCA and suballocator needed for CCS save & restore.
>> + *
>> + * Return: 0 on success. Negative error code on failure.
>> + */
>> +int xe_sriov_vf_ccs_init(struct xe_device *xe)
>> +{
>> + struct xe_tile *tile = xe_device_get_root_tile(xe);
>> + enum xe_sriov_vf_ccs_rw_ctxs ctx_id;
>> + struct xe_migrate *migrate;
>> + struct xe_tile_vf_ccs *ctx;
>> + int err;
>> +
>> + xe_assert(xe, IS_SRIOV_VF(xe));
>> + xe_assert(xe, !IS_DGFX(xe));
>> + xe_assert(xe, xe_device_has_flat_ccs(xe));
>> +
>> + for_each_ccs_rw_ctx(ctx_id) {
>> + ctx = &tile->sriov.vf.ccs[ctx_id];
>> + ctx->ctx_id = ctx_id;
>> +
>> + migrate = xe_migrate_init(tile);
>> + if (IS_ERR(migrate)) {
>> + err = PTR_ERR(migrate);
>> + goto err_ret;
>> + }
>> + ctx->migrate = migrate;
>> +
>> + err = alloc_bb_pool(tile, ctx);
>> + if (err)
>> + goto err_ret;
>> + }
>> +
>> + xe->sriov.vf.ccs.initialized = 1;
>> +
>> + return 0;
>> +
>> +err_ret:
>> + return err;
>> +}
>> diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.h b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.h
>> new file mode 100644
>> index 000000000000..5df9ba028d14
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.h
>> @@ -0,0 +1,13 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2025 Intel Corporation
>> + */
>> +
>> +#ifndef _XE_SRIOV_VF_CCS_H_
>> +#define _XE_SRIOV_VF_CCS_H_
>> +
>> +struct xe_device;
>> +
>> +int xe_sriov_vf_ccs_init(struct xe_device *xe);
>> +
>> +#endif
>> diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h b/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h
>> new file mode 100644
>> index 000000000000..6dc279d206ec
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h
>> @@ -0,0 +1,45 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2025 Intel Corporation
>> + */
>> +
>> +#ifndef _XE_SRIOV_VF_CCS_TYPES_H_
>> +#define _XE_SRIOV_VF_CCS_TYPES_H_
>> +
>> +#define for_each_ccs_rw_ctx(id__) \
>> + for ((id__) = 0; (id__) < XE_SRIOV_VF_CCS_CTX_COUNT; (id__)++)
>> +
>> +#define IS_VF_CCS_READY(xe) ({ \
>> + struct xe_device *___xe = (xe); \
>> + xe_assert(___xe, IS_SRIOV_VF(___xe)); \
>> + ___xe->sriov.vf.ccs.initialized; \
>> + })
>> +
>> +#define IS_VF_CCS_INIT_NEEDED(xe) ({\
>> + struct xe_device *___xe = (xe); \
>> + IS_SRIOV_VF(___xe) && !IS_DGFX(___xe) && \
>> + xe_device_has_flat_ccs(___xe) && GRAPHICS_VER(___xe) >= 20; \
>> + })
>> +
>> +enum xe_sriov_vf_ccs_rw_ctxs {
>> + XE_SRIOV_VF_CCS_READ_CTX,
>> + XE_SRIOV_VF_CCS_WRITE_CTX,
>> + XE_SRIOV_VF_CCS_CTX_COUNT
>> +};
>> +
>> +struct xe_migrate;
>> +struct xe_sa_manager;
>> +
>> +struct xe_tile_vf_ccs {
>> + /** @id: Id to which context it belongs to */
>> + enum xe_sriov_vf_ccs_rw_ctxs ctx_id;
>> + /** @migrate: Migration helper for save/restore of CCS data */
>> + struct xe_migrate *migrate;
>> +
>> + struct {
>> + /** @ccs_rw_bb_pool: Pool from which batch buffers are allocated. */
>> + struct xe_sa_manager *ccs_bb_pool;
>> + } mem;
>> +};
>> +
>> +#endif
>> --
>> 2.43.0
>>
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^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2025-06-25 12:46 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-06-24 10:00 [PATCH v9 0/3] CCS save restore for IGPU Satyanarayana K V P
2025-06-24 10:00 ` [PATCH v9 1/3] drm/xe/vf: Create contexts for CCS read write Satyanarayana K V P
2025-06-24 15:40 ` Matthew Brost
2025-06-24 17:01 ` Matthew Brost
2025-06-25 12:46 ` K V P, Satyanarayana
2025-06-24 10:00 ` [PATCH v9 2/3] drm/xe/vf: Attach and detach CCS copy commands with BO Satyanarayana K V P
2025-06-24 16:02 ` Matthew Brost
2025-06-24 10:00 ` [PATCH v9 3/3] drm/xe/vf: Register CCS read/write contexts with Guc Satyanarayana K V P
2025-06-24 16:07 ` Matthew Brost
2025-06-24 15:08 ` ✗ CI.checkpatch: warning for CCS save restore for IGPU (rev9) Patchwork
2025-06-24 15:10 ` ✓ CI.KUnit: success " Patchwork
2025-06-24 15:46 ` ✓ Xe.CI.BAT: " Patchwork
2025-06-25 10:02 ` ✗ Xe.CI.Full: failure " Patchwork
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