* [PATCH] drm/xe/uapi: Add DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY
@ 2025-06-23 6:40 Nitin Gote
2025-06-23 6:51 ` Upadhyay, Tejas
2025-06-24 0:17 ` Matthew Brost
0 siblings, 2 replies; 18+ messages in thread
From: Nitin Gote @ 2025-06-23 6:40 UTC (permalink / raw)
To: intel-xe
Cc: joonas.lahtinen, rodrigo.vivi, himal.prasad.ghimiray,
tejas.upadhyay, nitin.r.gote
Add the DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY device query flag
which indicates whether a device supports DIS_NULL_QUERY (Disable null
anyhit shader query mechanism). The intent is for UMDs
to use this query and opt-in DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY flag
to disable null query mechanism for anyhit shader by setting
DIS_NULL_QUERY bit of RT_CTRL register for Xe2 IP.
Signed-off-by: Nitin Gote <nitin.r.gote@intel.com>
---
drivers/gpu/drm/xe/xe_exec_queue.c | 9 +++++++++
drivers/gpu/drm/xe/xe_query.c | 3 ++-
include/uapi/drm/xe_drm.h | 8 ++++++++
3 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
index fee22358cc09..519f36db7cd0 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue.c
+++ b/drivers/gpu/drm/xe/xe_exec_queue.c
@@ -26,6 +26,8 @@
#include "xe_trace.h"
#include "xe_vm.h"
#include "xe_pxp.h"
+#include "xe_gt_mcr.h"
+#include "regs/xe_gt_regs.h"
enum xe_exec_queue_sched_prop {
XE_EXEC_QUEUE_JOB_TIMEOUT = 0,
@@ -693,6 +695,13 @@ int xe_exec_queue_create_ioctl(struct drm_device *dev, void *data,
}
}
+ if (((GRAPHICS_VER(xe) >= 20) && (GRAPHICS_VER(xe) < 30)) &&
+ (args->flags & DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY) &&
+ (eci[0].engine_class == DRM_XE_ENGINE_CLASS_RENDER ||
+ eci[0].engine_class == DRM_XE_ENGINE_CLASS_COMPUTE)) {
+ xe_gt_mcr_multicast_write(q->gt, RT_CTRL, DIS_NULL_QUERY);
+ }
+
q->xef = xe_file_get(xef);
/* user id alloc must always be last in ioctl to prevent UAF */
diff --git a/drivers/gpu/drm/xe/xe_query.c b/drivers/gpu/drm/xe/xe_query.c
index e8e1743dcb1e..c5002b8c9ac0 100644
--- a/drivers/gpu/drm/xe/xe_query.c
+++ b/drivers/gpu/drm/xe/xe_query.c
@@ -344,7 +344,8 @@ static int query_config(struct xe_device *xe, struct drm_xe_device_query *query)
config->info[DRM_XE_QUERY_CONFIG_FLAGS] |=
DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR;
config->info[DRM_XE_QUERY_CONFIG_FLAGS] |=
- DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY;
+ (DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY |
+ DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY);
config->info[DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT] =
xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K ? SZ_64K : SZ_4K;
config->info[DRM_XE_QUERY_CONFIG_VA_BITS] = xe->info.va_bits;
diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
index 8e8bbdec8c5c..a5bfba121360 100644
--- a/include/uapi/drm/xe_drm.h
+++ b/include/uapi/drm/xe_drm.h
@@ -397,6 +397,8 @@ struct drm_xe_query_mem_regions {
* has low latency hint support
* - %DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR - Flag is set if the
* device has CPU address mirroring support
+ * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY - Flag is set if the
+ * device has null query support for anyhit shader.
* - %DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT - Minimal memory alignment
* required by this device, typically SZ_4K or SZ_64K
* - %DRM_XE_QUERY_CONFIG_VA_BITS - Maximum bits of a virtual address
@@ -415,6 +417,7 @@ struct drm_xe_query_config {
#define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM (1 << 0)
#define DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY (1 << 1)
#define DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR (1 << 2)
+ #define DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY (1 << 3)
#define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT 2
#define DRM_XE_QUERY_CONFIG_VA_BITS 3
#define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY 4
@@ -1271,6 +1274,11 @@ struct drm_xe_exec_queue_create {
__u32 vm_id;
#define DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT (1 << 0)
+ /*
+ * DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY flag is
+ * use to disable null query check for Anyhit shader
+ */
+#define DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY (1 << 1)
/** @flags: flags to use for this exec queue */
__u32 flags;
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* RE: [PATCH] drm/xe/uapi: Add DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY
2025-06-23 6:40 [PATCH] drm/xe/uapi: Add DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY Nitin Gote
@ 2025-06-23 6:51 ` Upadhyay, Tejas
2025-06-24 0:17 ` Matthew Brost
1 sibling, 0 replies; 18+ messages in thread
From: Upadhyay, Tejas @ 2025-06-23 6:51 UTC (permalink / raw)
To: Gote, Nitin R, intel-xe@lists.freedesktop.org
Cc: joonas.lahtinen@linux.intel.com, Vivi, Rodrigo,
Ghimiray, Himal Prasad
> -----Original Message-----
> From: Gote, Nitin R <nitin.r.gote@intel.com>
> Sent: 23 June 2025 12:11
> To: intel-xe@lists.freedesktop.org
> Cc: joonas.lahtinen@linux.intel.com; Vivi, Rodrigo <rodrigo.vivi@intel.com>;
> Ghimiray, Himal Prasad <himal.prasad.ghimiray@intel.com>; Upadhyay, Tejas
> <tejas.upadhyay@intel.com>; Gote, Nitin R <nitin.r.gote@intel.com>
> Subject: [PATCH] drm/xe/uapi: Add
> DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY
>
> Add the DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY device
> query flag which indicates whether a device supports DIS_NULL_QUERY
> (Disable null anyhit shader query mechanism). The intent is for UMDs to use
> this query and opt-in DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY flag to disable
> null query mechanism for anyhit shader by setting DIS_NULL_QUERY bit of
> RT_CTRL register for Xe2 IP.
>
> Signed-off-by: Nitin Gote <nitin.r.gote@intel.com>
> ---
> drivers/gpu/drm/xe/xe_exec_queue.c | 9 +++++++++
> drivers/gpu/drm/xe/xe_query.c | 3 ++-
> include/uapi/drm/xe_drm.h | 8 ++++++++
> 3 files changed, 19 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c
> b/drivers/gpu/drm/xe/xe_exec_queue.c
> index fee22358cc09..519f36db7cd0 100644
> --- a/drivers/gpu/drm/xe/xe_exec_queue.c
> +++ b/drivers/gpu/drm/xe/xe_exec_queue.c
> @@ -26,6 +26,8 @@
> #include "xe_trace.h"
> #include "xe_vm.h"
> #include "xe_pxp.h"
> +#include "xe_gt_mcr.h"
> +#include "regs/xe_gt_regs.h"
>
> enum xe_exec_queue_sched_prop {
> XE_EXEC_QUEUE_JOB_TIMEOUT = 0,
> @@ -693,6 +695,13 @@ int xe_exec_queue_create_ioctl(struct drm_device
> *dev, void *data,
> }
> }
>
> + if (((GRAPHICS_VER(xe) >= 20) && (GRAPHICS_VER(xe) < 30)) &&
> + (args->flags & DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY) &&
Some other bits can sneak in, I think you need to something like args->flags & ~(DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT | DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY). Also this should be checked first up as other flags are validated.
> + (eci[0].engine_class == DRM_XE_ENGINE_CLASS_RENDER ||
> + eci[0].engine_class == DRM_XE_ENGINE_CLASS_COMPUTE)) {
I think there is API to check render_or_compute()
> + xe_gt_mcr_multicast_write(q->gt, RT_CTRL,
> DIS_NULL_QUERY);
If this setting is effective post xe_exec call, that is post queue execution then its fine. Otherwise need to find alternative placement. To me it looks like placement is ok.
Tejas
> + }
> +
> q->xef = xe_file_get(xef);
>
> /* user id alloc must always be last in ioctl to prevent UAF */ diff --git
> a/drivers/gpu/drm/xe/xe_query.c b/drivers/gpu/drm/xe/xe_query.c index
> e8e1743dcb1e..c5002b8c9ac0 100644
> --- a/drivers/gpu/drm/xe/xe_query.c
> +++ b/drivers/gpu/drm/xe/xe_query.c
> @@ -344,7 +344,8 @@ static int query_config(struct xe_device *xe, struct
> drm_xe_device_query *query)
> config->info[DRM_XE_QUERY_CONFIG_FLAGS] |=
>
> DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR;
> config->info[DRM_XE_QUERY_CONFIG_FLAGS] |=
> - DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY;
> +
> (DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY |
> +
> DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY);
> config->info[DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT] =
> xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K ? SZ_64K :
> SZ_4K;
> config->info[DRM_XE_QUERY_CONFIG_VA_BITS] = xe->info.va_bits;
> diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h index
> 8e8bbdec8c5c..a5bfba121360 100644
> --- a/include/uapi/drm/xe_drm.h
> +++ b/include/uapi/drm/xe_drm.h
> @@ -397,6 +397,8 @@ struct drm_xe_query_mem_regions {
> * has low latency hint support
> * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR - Flag is
> set if the
> * device has CPU address mirroring support
> + * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY - Flag is set if
> the
> + * device has null query support for anyhit shader.
> * - %DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT - Minimal memory
> alignment
> * required by this device, typically SZ_4K or SZ_64K
> * - %DRM_XE_QUERY_CONFIG_VA_BITS - Maximum bits of a virtual address
> @@ -415,6 +417,7 @@ struct drm_xe_query_config {
> #define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM (1 << 0)
> #define DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY (1 <<
> 1)
> #define DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR
> (1 << 2)
> + #define DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY
> (1 << 3)
> #define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT 2
> #define DRM_XE_QUERY_CONFIG_VA_BITS 3
> #define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY 4
> @@ -1271,6 +1274,11 @@ struct drm_xe_exec_queue_create {
> __u32 vm_id;
>
> #define DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT (1 << 0)
> + /*
> + * DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY flag is
> + * use to disable null query check for Anyhit shader
> + */
> +#define DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY (1 << 1)
> /** @flags: flags to use for this exec queue */
> __u32 flags;
>
> --
> 2.25.1
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH] drm/xe/uapi: Add DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY
2025-06-23 6:40 [PATCH] drm/xe/uapi: Add DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY Nitin Gote
2025-06-23 6:51 ` Upadhyay, Tejas
@ 2025-06-24 0:17 ` Matthew Brost
2025-06-25 9:23 ` Gote, Nitin R
1 sibling, 1 reply; 18+ messages in thread
From: Matthew Brost @ 2025-06-24 0:17 UTC (permalink / raw)
To: Nitin Gote
Cc: intel-xe, joonas.lahtinen, rodrigo.vivi, himal.prasad.ghimiray,
tejas.upadhyay
On Mon, Jun 23, 2025 at 12:10:36PM +0530, Nitin Gote wrote:
> Add the DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY device query flag
> which indicates whether a device supports DIS_NULL_QUERY (Disable null
s/DIS_NULL_QUERY/DISABLE_NULL_QUERY
> anyhit shader query mechanism). The intent is for UMDs
> to use this query and opt-in DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY flag
> to disable null query mechanism for anyhit shader by setting
> DIS_NULL_QUERY bit of RT_CTRL register for Xe2 IP.
>
> Signed-off-by: Nitin Gote <nitin.r.gote@intel.com>
> ---
> drivers/gpu/drm/xe/xe_exec_queue.c | 9 +++++++++
> drivers/gpu/drm/xe/xe_query.c | 3 ++-
> include/uapi/drm/xe_drm.h | 8 ++++++++
> 3 files changed, 19 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
> index fee22358cc09..519f36db7cd0 100644
> --- a/drivers/gpu/drm/xe/xe_exec_queue.c
> +++ b/drivers/gpu/drm/xe/xe_exec_queue.c
> @@ -26,6 +26,8 @@
> #include "xe_trace.h"
> #include "xe_vm.h"
> #include "xe_pxp.h"
> +#include "xe_gt_mcr.h"
> +#include "regs/xe_gt_regs.h"
>
> enum xe_exec_queue_sched_prop {
> XE_EXEC_QUEUE_JOB_TIMEOUT = 0,
> @@ -693,6 +695,13 @@ int xe_exec_queue_create_ioctl(struct drm_device *dev, void *data,
> }
> }
>
> + if (((GRAPHICS_VER(xe) >= 20) && (GRAPHICS_VER(xe) < 30)) &&
> + (args->flags & DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY) &&
> + (eci[0].engine_class == DRM_XE_ENGINE_CLASS_RENDER ||
> + eci[0].engine_class == DRM_XE_ENGINE_CLASS_COMPUTE)) {
> + xe_gt_mcr_multicast_write(q->gt, RT_CTRL, DIS_NULL_QUERY);
> + }
You will hit an error before you get here because of the if statement
above (not shown in the diff) that sanitizes args->flags.
You don’t need {} here.
Also, a register write implies this would affect the entire GT, not just
the exec queue flagged with “disable NULL query.” Is that really the
intent? It doesn’t seem correct to me, but honestly, I’m not entirely
sure what this patch is trying to do. If the intent is for this to be
per-exec queue, then I think this needs to be implemented as some ring
instructions in the LRC WA BB.
> +
> q->xef = xe_file_get(xef);
>
> /* user id alloc must always be last in ioctl to prevent UAF */
> diff --git a/drivers/gpu/drm/xe/xe_query.c b/drivers/gpu/drm/xe/xe_query.c
> index e8e1743dcb1e..c5002b8c9ac0 100644
> --- a/drivers/gpu/drm/xe/xe_query.c
> +++ b/drivers/gpu/drm/xe/xe_query.c
> @@ -344,7 +344,8 @@ static int query_config(struct xe_device *xe, struct drm_xe_device_query *query)
> config->info[DRM_XE_QUERY_CONFIG_FLAGS] |=
> DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR;
> config->info[DRM_XE_QUERY_CONFIG_FLAGS] |=
> - DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY;
> + (DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY |
> + DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY);
> config->info[DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT] =
> xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K ? SZ_64K : SZ_4K;
> config->info[DRM_XE_QUERY_CONFIG_VA_BITS] = xe->info.va_bits;
> diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
> index 8e8bbdec8c5c..a5bfba121360 100644
> --- a/include/uapi/drm/xe_drm.h
> +++ b/include/uapi/drm/xe_drm.h
> @@ -397,6 +397,8 @@ struct drm_xe_query_mem_regions {
> * has low latency hint support
> * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR - Flag is set if the
> * device has CPU address mirroring support
> + * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY - Flag is set if the
> + * device has null query support for anyhit shader.
> * - %DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT - Minimal memory alignment
> * required by this device, typically SZ_4K or SZ_64K
> * - %DRM_XE_QUERY_CONFIG_VA_BITS - Maximum bits of a virtual address
> @@ -415,6 +417,7 @@ struct drm_xe_query_config {
> #define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM (1 << 0)
> #define DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY (1 << 1)
> #define DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR (1 << 2)
> + #define DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY (1 << 3)
> #define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT 2
> #define DRM_XE_QUERY_CONFIG_VA_BITS 3
> #define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY 4
> @@ -1271,6 +1274,11 @@ struct drm_xe_exec_queue_create {
> __u32 vm_id;
>
> #define DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT (1 << 0)
> + /*
> + * DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY flag is
> + * use to disable null query check for Anyhit shader
> + */
> +#define DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY (1 << 1)
We should add proper kernel-doc for this flag.
It looks like we’re also missing proper kernel-doc for
DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT. While you’re at it, could you add
that as well?
Matt
> /** @flags: flags to use for this exec queue */
> __u32 flags;
>
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* RE: [PATCH] drm/xe/uapi: Add DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY
2025-06-24 0:17 ` Matthew Brost
@ 2025-06-25 9:23 ` Gote, Nitin R
2025-06-25 13:35 ` Matthew Brost
0 siblings, 1 reply; 18+ messages in thread
From: Gote, Nitin R @ 2025-06-25 9:23 UTC (permalink / raw)
To: Brost, Matthew, Upadhyay, Tejas
Cc: intel-xe@lists.freedesktop.org, joonas.lahtinen@linux.intel.com,
Vivi, Rodrigo, Ghimiray, Himal Prasad
Hi Matthew,
>
> On Mon, Jun 23, 2025 at 12:10:36PM +0530, Nitin Gote wrote:
> > Add the DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY device query
> flag
> > which indicates whether a device supports DIS_NULL_QUERY (Disable null
>
> s/DIS_NULL_QUERY/DISABLE_NULL_QUERY
The DIS_NULL_QUERY naming convention is followed as per Bspec 57496.
>
> > anyhit shader query mechanism). The intent is for UMDs to use this
> > query and opt-in DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY flag to disable null
> > query mechanism for anyhit shader by setting DIS_NULL_QUERY bit of
> > RT_CTRL register for Xe2 IP.
> >
> > Signed-off-by: Nitin Gote <nitin.r.gote@intel.com>
> > ---
> > drivers/gpu/drm/xe/xe_exec_queue.c | 9 +++++++++
> > drivers/gpu/drm/xe/xe_query.c | 3 ++-
> > include/uapi/drm/xe_drm.h | 8 ++++++++
> > 3 files changed, 19 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c
> > b/drivers/gpu/drm/xe/xe_exec_queue.c
> > index fee22358cc09..519f36db7cd0 100644
> > --- a/drivers/gpu/drm/xe/xe_exec_queue.c
> > +++ b/drivers/gpu/drm/xe/xe_exec_queue.c
> > @@ -26,6 +26,8 @@
> > #include "xe_trace.h"
> > #include "xe_vm.h"
> > #include "xe_pxp.h"
> > +#include "xe_gt_mcr.h"
> > +#include "regs/xe_gt_regs.h"
> >
> > enum xe_exec_queue_sched_prop {
> > XE_EXEC_QUEUE_JOB_TIMEOUT = 0,
> > @@ -693,6 +695,13 @@ int xe_exec_queue_create_ioctl(struct drm_device
> *dev, void *data,
> > }
> > }
> >
> > + if (((GRAPHICS_VER(xe) >= 20) && (GRAPHICS_VER(xe) < 30)) &&
> > + (args->flags & DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY) &&
> > + (eci[0].engine_class == DRM_XE_ENGINE_CLASS_RENDER ||
> > + eci[0].engine_class == DRM_XE_ENGINE_CLASS_COMPUTE)) {
> > + xe_gt_mcr_multicast_write(q->gt, RT_CTRL, DIS_NULL_QUERY);
> > + }
>
> You will hit an error before you get here because of the if statement above (not
> shown in the diff) that sanitizes args->flags.
>
Yes. Agree with you. I will add it.
> You don’t need {} here.
>
Thanks, I will remove it.
> Also, a register write implies this would affect the entire GT, not just the exec
> queue flagged with “disable NULL query.” Is that really the intent? It doesn’t
> seem correct to me, but honestly, I’m not entirely sure what this patch is trying to
> do. If the intent is for this to be per-exec queue, then I think this needs to be
> implemented as some ring instructions in the LRC WA BB.
>
Here, the intention is that for the already released platforms Xe2,
we need to add an opt-in flag via uapi to disable null query for anyhit shader.
So that userspace can use this flag to disable anyhit shader query mechanism, and I think
that it is not possible in the LRC WA BB. And to me, this placement looks ok as this setting is
effective post xe_exec call.
> > +
> > q->xef = xe_file_get(xef);
> >
> > /* user id alloc must always be last in ioctl to prevent UAF */ diff
> > --git a/drivers/gpu/drm/xe/xe_query.c b/drivers/gpu/drm/xe/xe_query.c
> > index e8e1743dcb1e..c5002b8c9ac0 100644
> > --- a/drivers/gpu/drm/xe/xe_query.c
> > +++ b/drivers/gpu/drm/xe/xe_query.c
> > @@ -344,7 +344,8 @@ static int query_config(struct xe_device *xe, struct
> drm_xe_device_query *query)
> > config->info[DRM_XE_QUERY_CONFIG_FLAGS] |=
> >
> DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR;
> > config->info[DRM_XE_QUERY_CONFIG_FLAGS] |=
> > - DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY;
> > + (DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY
> |
> > +
> DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY);
> > config->info[DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT] =
> > xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K ? SZ_64K :
> SZ_4K;
> > config->info[DRM_XE_QUERY_CONFIG_VA_BITS] = xe->info.va_bits; diff
> > --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h index
> > 8e8bbdec8c5c..a5bfba121360 100644
> > --- a/include/uapi/drm/xe_drm.h
> > +++ b/include/uapi/drm/xe_drm.h
> > @@ -397,6 +397,8 @@ struct drm_xe_query_mem_regions {
> > * has low latency hint support
> > * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR - Flag is
> set if the
> > * device has CPU address mirroring support
> > + * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY - Flag is set if
> the
> > + * device has null query support for anyhit shader.
> > * - %DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT - Minimal memory
> alignment
> > * required by this device, typically SZ_4K or SZ_64K
> > * - %DRM_XE_QUERY_CONFIG_VA_BITS - Maximum bits of a virtual
> > address @@ -415,6 +417,7 @@ struct drm_xe_query_config {
> > #define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM (1 << 0)
> > #define DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY (1 <<
> 1)
> > #define DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR
> (1 << 2)
> > + #define DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY (1 <<
> 3)
> > #define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT 2
> > #define DRM_XE_QUERY_CONFIG_VA_BITS 3
> > #define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY 4
> > @@ -1271,6 +1274,11 @@ struct drm_xe_exec_queue_create {
> > __u32 vm_id;
> >
> > #define DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT (1 << 0)
> > + /*
> > + * DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY flag is
> > + * use to disable null query check for Anyhit shader
> > + */
> > +#define DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY (1 << 1)
>
> We should add proper kernel-doc for this flag.
>
> It looks like we’re also missing proper kernel-doc for
> DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT. While you’re at it, could you add
> that as well?
>
Sure. I will add kernel-doc for both macros.
> Matt
>
> > /** @flags: flags to use for this exec queue */
> > __u32 flags;
> >
> > --
> > 2.25.1
> >
^ permalink raw reply [flat|nested] 18+ messages in thread
* ✓ CI.KUnit: success for drm/xe/uapi: Add DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY (rev2)
2025-06-25 9:58 [PATCH] drm/xe/uapi: Add DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY Nitin Gote
@ 2025-06-25 9:41 ` Patchwork
2025-06-25 10:17 ` ✓ Xe.CI.BAT: " Patchwork
` (2 subsequent siblings)
3 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2025-06-25 9:41 UTC (permalink / raw)
To: Nitin Gote; +Cc: intel-xe
== Series Details ==
Series: drm/xe/uapi: Add DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY (rev2)
URL : https://patchwork.freedesktop.org/series/150601/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[09:40:10] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[09:40:14] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[09:40:41] Starting KUnit Kernel (1/1)...
[09:40:41] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[09:40:41] ================== guc_buf (11 subtests) ===================
[09:40:41] [PASSED] test_smallest
[09:40:41] [PASSED] test_largest
[09:40:41] [PASSED] test_granular
[09:40:41] [PASSED] test_unique
[09:40:41] [PASSED] test_overlap
[09:40:41] [PASSED] test_reusable
[09:40:41] [PASSED] test_too_big
[09:40:41] [PASSED] test_flush
[09:40:41] [PASSED] test_lookup
[09:40:41] [PASSED] test_data
[09:40:41] [PASSED] test_class
[09:40:41] ===================== [PASSED] guc_buf =====================
[09:40:41] =================== guc_dbm (7 subtests) ===================
[09:40:41] [PASSED] test_empty
[09:40:41] [PASSED] test_default
[09:40:41] ======================== test_size ========================
[09:40:41] [PASSED] 4
[09:40:41] [PASSED] 8
[09:40:41] [PASSED] 32
[09:40:41] [PASSED] 256
[09:40:41] ==================== [PASSED] test_size ====================
[09:40:41] ======================= test_reuse ========================
[09:40:41] [PASSED] 4
[09:40:41] [PASSED] 8
[09:40:41] [PASSED] 32
[09:40:41] [PASSED] 256
[09:40:41] =================== [PASSED] test_reuse ====================
[09:40:41] =================== test_range_overlap ====================
[09:40:41] [PASSED] 4
[09:40:41] [PASSED] 8
[09:40:41] [PASSED] 32
[09:40:41] [PASSED] 256
[09:40:41] =============== [PASSED] test_range_overlap ================
[09:40:41] =================== test_range_compact ====================
[09:40:41] [PASSED] 4
[09:40:41] [PASSED] 8
[09:40:41] [PASSED] 32
[09:40:41] [PASSED] 256
[09:40:41] =============== [PASSED] test_range_compact ================
[09:40:41] ==================== test_range_spare =====================
[09:40:41] [PASSED] 4
[09:40:41] [PASSED] 8
[09:40:41] [PASSED] 32
[09:40:41] [PASSED] 256
[09:40:41] ================ [PASSED] test_range_spare =================
[09:40:41] ===================== [PASSED] guc_dbm =====================
[09:40:41] =================== guc_idm (6 subtests) ===================
[09:40:41] [PASSED] bad_init
[09:40:41] [PASSED] no_init
[09:40:41] [PASSED] init_fini
[09:40:41] [PASSED] check_used
[09:40:41] [PASSED] check_quota
[09:40:41] [PASSED] check_all
[09:40:41] ===================== [PASSED] guc_idm =====================
[09:40:41] ================== no_relay (3 subtests) ===================
[09:40:41] [PASSED] xe_drops_guc2pf_if_not_ready
[09:40:41] [PASSED] xe_drops_guc2vf_if_not_ready
[09:40:41] [PASSED] xe_rejects_send_if_not_ready
[09:40:41] ==================== [PASSED] no_relay =====================
[09:40:41] ================== pf_relay (14 subtests) ==================
[09:40:41] [PASSED] pf_rejects_guc2pf_too_short
[09:40:41] [PASSED] pf_rejects_guc2pf_too_long
[09:40:41] [PASSED] pf_rejects_guc2pf_no_payload
[09:40:41] [PASSED] pf_fails_no_payload
[09:40:41] [PASSED] pf_fails_bad_origin
[09:40:41] [PASSED] pf_fails_bad_type
[09:40:41] [PASSED] pf_txn_reports_error
[09:40:41] [PASSED] pf_txn_sends_pf2guc
[09:40:41] [PASSED] pf_sends_pf2guc
[09:40:41] [SKIPPED] pf_loopback_nop
[09:40:41] [SKIPPED] pf_loopback_echo
[09:40:41] [SKIPPED] pf_loopback_fail
[09:40:41] [SKIPPED] pf_loopback_busy
[09:40:41] [SKIPPED] pf_loopback_retry
[09:40:41] ==================== [PASSED] pf_relay =====================
[09:40:41] ================== vf_relay (3 subtests) ===================
[09:40:41] [PASSED] vf_rejects_guc2vf_too_short
[09:40:41] [PASSED] vf_rejects_guc2vf_too_long
[09:40:41] [PASSED] vf_rejects_guc2vf_no_payload
[09:40:41] ==================== [PASSED] vf_relay =====================
[09:40:41] ================= pf_service (11 subtests) =================
[09:40:41] [PASSED] pf_negotiate_any
[09:40:41] [PASSED] pf_negotiate_base_match
[09:40:41] [PASSED] pf_negotiate_base_newer
[09:40:41] [PASSED] pf_negotiate_base_next
[09:40:41] [SKIPPED] pf_negotiate_base_older
[09:40:41] [PASSED] pf_negotiate_base_prev
[09:40:41] [PASSED] pf_negotiate_latest_match
[09:40:41] [PASSED] pf_negotiate_latest_newer
[09:40:41] [PASSED] pf_negotiate_latest_next
[09:40:41] [SKIPPED] pf_negotiate_latest_older
[09:40:41] [SKIPPED] pf_negotiate_latest_prev
[09:40:41] =================== [PASSED] pf_service ====================
[09:40:41] ===================== lmtt (1 subtest) =====================
[09:40:41] ======================== test_ops =========================
[09:40:41] [PASSED] 2-level
[09:40:41] [PASSED] multi-level
[09:40:41] ==================== [PASSED] test_ops =====================
[09:40:41] ====================== [PASSED] lmtt =======================
[09:40:41] =================== xe_mocs (2 subtests) ===================
[09:40:41] ================ xe_live_mocs_kernel_kunit ================
[09:40:41] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[09:40:41] ================ xe_live_mocs_reset_kunit =================
[09:40:41] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[09:40:41] ==================== [SKIPPED] xe_mocs =====================
[09:40:41] ================= xe_migrate (2 subtests) ==================
[09:40:41] ================= xe_migrate_sanity_kunit =================
[09:40:41] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[09:40:41] ================== xe_validate_ccs_kunit ==================
[09:40:41] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[09:40:41] =================== [SKIPPED] xe_migrate ===================
[09:40:41] ================== xe_dma_buf (1 subtest) ==================
[09:40:41] ==================== xe_dma_buf_kunit =====================
[09:40:41] ================ [SKIPPED] xe_dma_buf_kunit ================
[09:40:41] =================== [SKIPPED] xe_dma_buf ===================
[09:40:41] ================= xe_bo_shrink (1 subtest) =================
[09:40:41] =================== xe_bo_shrink_kunit ====================
[09:40:41] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[09:40:41] ================== [SKIPPED] xe_bo_shrink ==================
[09:40:41] ==================== xe_bo (2 subtests) ====================
[09:40:41] ================== xe_ccs_migrate_kunit ===================
[09:40:41] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[09:40:41] ==================== xe_bo_evict_kunit ====================
[09:40:41] =============== [SKIPPED] xe_bo_evict_kunit ================
[09:40:41] ===================== [SKIPPED] xe_bo ======================
[09:40:41] ==================== args (11 subtests) ====================
[09:40:41] [PASSED] count_args_test
[09:40:41] [PASSED] call_args_example
[09:40:41] [PASSED] call_args_test
[09:40:41] [PASSED] drop_first_arg_example
[09:40:41] [PASSED] drop_first_arg_test
[09:40:41] [PASSED] first_arg_example
[09:40:41] [PASSED] first_arg_test
[09:40:41] [PASSED] last_arg_example
[09:40:41] [PASSED] last_arg_test
[09:40:41] [PASSED] pick_arg_example
[09:40:41] [PASSED] sep_comma_example
[09:40:41] ====================== [PASSED] args =======================
[09:40:41] =================== xe_pci (2 subtests) ====================
[09:40:41] ==================== check_graphics_ip ====================
[09:40:41] [PASSED] 12.70 Xe_LPG
[09:40:41] [PASSED] 12.71 Xe_LPG
[09:40:41] [PASSED] 12.74 Xe_LPG+
[09:40:41] [PASSED] 20.01 Xe2_HPG
[09:40:41] [PASSED] 20.02 Xe2_HPG
[09:40:41] [PASSED] 20.04 Xe2_LPG
[09:40:41] [PASSED] 30.00 Xe3_LPG
[09:40:41] [PASSED] 30.01 Xe3_LPG
[09:40:41] [PASSED] 30.03 Xe3_LPG
[09:40:41] ================ [PASSED] check_graphics_ip ================
[09:40:41] ===================== check_media_ip ======================
[09:40:41] [PASSED] 13.00 Xe_LPM+
[09:40:41] [PASSED] 13.01 Xe2_HPM
[09:40:41] [PASSED] 20.00 Xe2_LPM
[09:40:41] [PASSED] 30.00 Xe3_LPM
[09:40:41] [PASSED] 30.02 Xe3_LPM
stty: 'standard input': Inappropriate ioctl for device
[09:40:41] ================= [PASSED] check_media_ip ==================
[09:40:41] ===================== [PASSED] xe_pci ======================
[09:40:41] =================== xe_rtp (2 subtests) ====================
[09:40:41] =============== xe_rtp_process_to_sr_tests ================
[09:40:41] [PASSED] coalesce-same-reg
[09:40:41] [PASSED] no-match-no-add
[09:40:41] [PASSED] match-or
[09:40:41] [PASSED] match-or-xfail
[09:40:41] [PASSED] no-match-no-add-multiple-rules
[09:40:41] [PASSED] two-regs-two-entries
[09:40:41] [PASSED] clr-one-set-other
[09:40:41] [PASSED] set-field
[09:40:41] [PASSED] conflict-duplicate
[09:40:41] [PASSED] conflict-not-disjoint
[09:40:41] [PASSED] conflict-reg-type
[09:40:41] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[09:40:41] ================== xe_rtp_process_tests ===================
[09:40:41] [PASSED] active1
[09:40:41] [PASSED] active2
[09:40:41] [PASSED] active-inactive
[09:40:41] [PASSED] inactive-active
[09:40:41] [PASSED] inactive-1st_or_active-inactive
[09:40:41] [PASSED] inactive-2nd_or_active-inactive
[09:40:41] [PASSED] inactive-last_or_active-inactive
[09:40:41] [PASSED] inactive-no_or_active-inactive
[09:40:41] ============== [PASSED] xe_rtp_process_tests ===============
[09:40:41] ===================== [PASSED] xe_rtp ======================
[09:40:41] ==================== xe_wa (1 subtest) =====================
[09:40:41] ======================== xe_wa_gt =========================
[09:40:41] [PASSED] TIGERLAKE (B0)
[09:40:41] [PASSED] DG1 (A0)
[09:40:41] [PASSED] DG1 (B0)
[09:40:41] [PASSED] ALDERLAKE_S (A0)
[09:40:41] [PASSED] ALDERLAKE_S (B0)
[09:40:41] [PASSED] ALDERLAKE_S (C0)
[09:40:41] [PASSED] ALDERLAKE_S (D0)
[09:40:41] [PASSED] ALDERLAKE_P (A0)
[09:40:41] [PASSED] ALDERLAKE_P (B0)
[09:40:41] [PASSED] ALDERLAKE_P (C0)
[09:40:41] [PASSED] ALDERLAKE_S_RPLS (D0)
[09:40:41] [PASSED] ALDERLAKE_P_RPLU (E0)
[09:40:41] [PASSED] DG2_G10 (C0)
[09:40:41] [PASSED] DG2_G11 (B1)
[09:40:41] [PASSED] DG2_G12 (A1)
[09:40:41] [PASSED] METEORLAKE (g:A0, m:A0)
[09:40:41] [PASSED] METEORLAKE (g:A0, m:A0)
[09:40:41] [PASSED] METEORLAKE (g:A0, m:A0)
[09:40:41] [PASSED] LUNARLAKE (g:A0, m:A0)
[09:40:41] [PASSED] LUNARLAKE (g:B0, m:A0)
[09:40:41] [PASSED] BATTLEMAGE (g:A0, m:A1)
[09:40:41] ==================== [PASSED] xe_wa_gt =====================
[09:40:41] ====================== [PASSED] xe_wa ======================
[09:40:41] ============================================================
[09:40:41] Testing complete. Ran 145 tests: passed: 129, skipped: 16
[09:40:41] Elapsed time: 31.316s total, 4.179s configuring, 26.821s building, 0.301s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[09:40:42] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[09:40:43] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[09:41:05] Starting KUnit Kernel (1/1)...
[09:41:05] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[09:41:05] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[09:41:05] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[09:41:05] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[09:41:05] =========== drm_validate_clone_mode (2 subtests) ===========
[09:41:05] ============== drm_test_check_in_clone_mode ===============
[09:41:05] [PASSED] in_clone_mode
[09:41:05] [PASSED] not_in_clone_mode
[09:41:05] ========== [PASSED] drm_test_check_in_clone_mode ===========
[09:41:05] =============== drm_test_check_valid_clones ===============
[09:41:05] [PASSED] not_in_clone_mode
[09:41:05] [PASSED] valid_clone
[09:41:05] [PASSED] invalid_clone
[09:41:05] =========== [PASSED] drm_test_check_valid_clones ===========
[09:41:05] ============= [PASSED] drm_validate_clone_mode =============
[09:41:05] ============= drm_validate_modeset (1 subtest) =============
[09:41:05] [PASSED] drm_test_check_connector_changed_modeset
[09:41:05] ============== [PASSED] drm_validate_modeset ===============
[09:41:05] ====== drm_test_bridge_get_current_state (2 subtests) ======
[09:41:05] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[09:41:05] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[09:41:05] ======== [PASSED] drm_test_bridge_get_current_state ========
[09:41:05] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[09:41:05] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[09:41:05] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[09:41:05] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[09:41:05] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[09:41:05] ============== drm_bridge_alloc (2 subtests) ===============
[09:41:05] [PASSED] drm_test_drm_bridge_alloc_basic
[09:41:05] [PASSED] drm_test_drm_bridge_alloc_get_put
[09:41:05] ================ [PASSED] drm_bridge_alloc =================
[09:41:05] ================== drm_buddy (7 subtests) ==================
[09:41:05] [PASSED] drm_test_buddy_alloc_limit
[09:41:05] [PASSED] drm_test_buddy_alloc_optimistic
[09:41:05] [PASSED] drm_test_buddy_alloc_pessimistic
[09:41:05] [PASSED] drm_test_buddy_alloc_pathological
[09:41:05] [PASSED] drm_test_buddy_alloc_contiguous
[09:41:05] [PASSED] drm_test_buddy_alloc_clear
[09:41:05] [PASSED] drm_test_buddy_alloc_range_bias
[09:41:05] ==================== [PASSED] drm_buddy ====================
[09:41:05] ============= drm_cmdline_parser (40 subtests) =============
[09:41:05] [PASSED] drm_test_cmdline_force_d_only
[09:41:05] [PASSED] drm_test_cmdline_force_D_only_dvi
[09:41:05] [PASSED] drm_test_cmdline_force_D_only_hdmi
[09:41:05] [PASSED] drm_test_cmdline_force_D_only_not_digital
[09:41:05] [PASSED] drm_test_cmdline_force_e_only
[09:41:05] [PASSED] drm_test_cmdline_res
[09:41:05] [PASSED] drm_test_cmdline_res_vesa
[09:41:05] [PASSED] drm_test_cmdline_res_vesa_rblank
[09:41:05] [PASSED] drm_test_cmdline_res_rblank
[09:41:05] [PASSED] drm_test_cmdline_res_bpp
[09:41:05] [PASSED] drm_test_cmdline_res_refresh
[09:41:05] [PASSED] drm_test_cmdline_res_bpp_refresh
[09:41:05] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[09:41:05] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[09:41:05] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[09:41:05] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[09:41:05] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[09:41:05] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[09:41:05] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[09:41:05] [PASSED] drm_test_cmdline_res_margins_force_on
[09:41:05] [PASSED] drm_test_cmdline_res_vesa_margins
[09:41:05] [PASSED] drm_test_cmdline_name
[09:41:05] [PASSED] drm_test_cmdline_name_bpp
[09:41:05] [PASSED] drm_test_cmdline_name_option
[09:41:05] [PASSED] drm_test_cmdline_name_bpp_option
[09:41:05] [PASSED] drm_test_cmdline_rotate_0
[09:41:05] [PASSED] drm_test_cmdline_rotate_90
[09:41:05] [PASSED] drm_test_cmdline_rotate_180
[09:41:05] [PASSED] drm_test_cmdline_rotate_270
[09:41:05] [PASSED] drm_test_cmdline_hmirror
[09:41:05] [PASSED] drm_test_cmdline_vmirror
[09:41:05] [PASSED] drm_test_cmdline_margin_options
[09:41:05] [PASSED] drm_test_cmdline_multiple_options
[09:41:05] [PASSED] drm_test_cmdline_bpp_extra_and_option
[09:41:05] [PASSED] drm_test_cmdline_extra_and_option
[09:41:05] [PASSED] drm_test_cmdline_freestanding_options
[09:41:05] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[09:41:05] [PASSED] drm_test_cmdline_panel_orientation
[09:41:05] ================ drm_test_cmdline_invalid =================
[09:41:05] [PASSED] margin_only
[09:41:05] [PASSED] interlace_only
[09:41:05] [PASSED] res_missing_x
[09:41:05] [PASSED] res_missing_y
[09:41:05] [PASSED] res_bad_y
[09:41:05] [PASSED] res_missing_y_bpp
[09:41:05] [PASSED] res_bad_bpp
[09:41:05] [PASSED] res_bad_refresh
[09:41:05] [PASSED] res_bpp_refresh_force_on_off
[09:41:05] [PASSED] res_invalid_mode
[09:41:05] [PASSED] res_bpp_wrong_place_mode
[09:41:05] [PASSED] name_bpp_refresh
[09:41:05] [PASSED] name_refresh
[09:41:05] [PASSED] name_refresh_wrong_mode
[09:41:05] [PASSED] name_refresh_invalid_mode
[09:41:05] [PASSED] rotate_multiple
[09:41:05] [PASSED] rotate_invalid_val
[09:41:05] [PASSED] rotate_truncated
[09:41:05] [PASSED] invalid_option
[09:41:05] [PASSED] invalid_tv_option
[09:41:05] [PASSED] truncated_tv_option
[09:41:05] ============ [PASSED] drm_test_cmdline_invalid =============
[09:41:05] =============== drm_test_cmdline_tv_options ===============
[09:41:05] [PASSED] NTSC
[09:41:05] [PASSED] NTSC_443
[09:41:05] [PASSED] NTSC_J
[09:41:05] [PASSED] PAL
[09:41:05] [PASSED] PAL_M
[09:41:05] [PASSED] PAL_N
[09:41:05] [PASSED] SECAM
[09:41:05] [PASSED] MONO_525
[09:41:05] [PASSED] MONO_625
[09:41:05] =========== [PASSED] drm_test_cmdline_tv_options ===========
[09:41:05] =============== [PASSED] drm_cmdline_parser ================
[09:41:05] ========== drmm_connector_hdmi_init (20 subtests) ==========
[09:41:05] [PASSED] drm_test_connector_hdmi_init_valid
[09:41:05] [PASSED] drm_test_connector_hdmi_init_bpc_8
[09:41:05] [PASSED] drm_test_connector_hdmi_init_bpc_10
[09:41:05] [PASSED] drm_test_connector_hdmi_init_bpc_12
[09:41:05] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[09:41:05] [PASSED] drm_test_connector_hdmi_init_bpc_null
[09:41:05] [PASSED] drm_test_connector_hdmi_init_formats_empty
[09:41:05] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[09:41:05] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[09:41:05] [PASSED] supported_formats=0x9 yuv420_allowed=1
[09:41:05] [PASSED] supported_formats=0x9 yuv420_allowed=0
[09:41:05] [PASSED] supported_formats=0x3 yuv420_allowed=1
[09:41:05] [PASSED] supported_formats=0x3 yuv420_allowed=0
[09:41:05] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[09:41:05] [PASSED] drm_test_connector_hdmi_init_null_ddc
[09:41:05] [PASSED] drm_test_connector_hdmi_init_null_product
[09:41:05] [PASSED] drm_test_connector_hdmi_init_null_vendor
[09:41:05] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[09:41:05] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[09:41:05] [PASSED] drm_test_connector_hdmi_init_product_valid
[09:41:05] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[09:41:05] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[09:41:05] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[09:41:05] ========= drm_test_connector_hdmi_init_type_valid =========
[09:41:05] [PASSED] HDMI-A
[09:41:05] [PASSED] HDMI-B
[09:41:05] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[09:41:05] ======== drm_test_connector_hdmi_init_type_invalid ========
[09:41:05] [PASSED] Unknown
[09:41:05] [PASSED] VGA
[09:41:05] [PASSED] DVI-I
[09:41:05] [PASSED] DVI-D
[09:41:05] [PASSED] DVI-A
[09:41:05] [PASSED] Composite
[09:41:05] [PASSED] SVIDEO
[09:41:05] [PASSED] LVDS
[09:41:05] [PASSED] Component
[09:41:05] [PASSED] DIN
[09:41:05] [PASSED] DP
[09:41:05] [PASSED] TV
[09:41:05] [PASSED] eDP
[09:41:05] [PASSED] Virtual
[09:41:05] [PASSED] DSI
[09:41:05] [PASSED] DPI
[09:41:05] [PASSED] Writeback
[09:41:05] [PASSED] SPI
[09:41:05] [PASSED] USB
[09:41:05] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[09:41:05] ============ [PASSED] drmm_connector_hdmi_init =============
[09:41:05] ============= drmm_connector_init (3 subtests) =============
[09:41:05] [PASSED] drm_test_drmm_connector_init
[09:41:05] [PASSED] drm_test_drmm_connector_init_null_ddc
[09:41:05] ========= drm_test_drmm_connector_init_type_valid =========
[09:41:05] [PASSED] Unknown
[09:41:05] [PASSED] VGA
[09:41:05] [PASSED] DVI-I
[09:41:05] [PASSED] DVI-D
[09:41:05] [PASSED] DVI-A
[09:41:05] [PASSED] Composite
[09:41:05] [PASSED] SVIDEO
[09:41:05] [PASSED] LVDS
[09:41:05] [PASSED] Component
[09:41:05] [PASSED] DIN
[09:41:05] [PASSED] DP
[09:41:05] [PASSED] HDMI-A
[09:41:05] [PASSED] HDMI-B
[09:41:05] [PASSED] TV
[09:41:05] [PASSED] eDP
[09:41:05] [PASSED] Virtual
[09:41:05] [PASSED] DSI
[09:41:05] [PASSED] DPI
[09:41:05] [PASSED] Writeback
[09:41:05] [PASSED] SPI
[09:41:05] [PASSED] USB
[09:41:05] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[09:41:05] =============== [PASSED] drmm_connector_init ===============
[09:41:05] ========= drm_connector_dynamic_init (6 subtests) ==========
[09:41:05] [PASSED] drm_test_drm_connector_dynamic_init
[09:41:05] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[09:41:05] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[09:41:05] [PASSED] drm_test_drm_connector_dynamic_init_properties
[09:41:05] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[09:41:05] [PASSED] Unknown
[09:41:05] [PASSED] VGA
[09:41:05] [PASSED] DVI-I
[09:41:05] [PASSED] DVI-D
[09:41:05] [PASSED] DVI-A
[09:41:05] [PASSED] Composite
[09:41:05] [PASSED] SVIDEO
[09:41:05] [PASSED] LVDS
[09:41:05] [PASSED] Component
[09:41:05] [PASSED] DIN
[09:41:05] [PASSED] DP
[09:41:05] [PASSED] HDMI-A
[09:41:05] [PASSED] HDMI-B
[09:41:05] [PASSED] TV
[09:41:05] [PASSED] eDP
[09:41:05] [PASSED] Virtual
[09:41:05] [PASSED] DSI
[09:41:05] [PASSED] DPI
[09:41:05] [PASSED] Writeback
[09:41:05] [PASSED] SPI
[09:41:05] [PASSED] USB
[09:41:05] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[09:41:05] ======== drm_test_drm_connector_dynamic_init_name =========
[09:41:05] [PASSED] Unknown
[09:41:05] [PASSED] VGA
[09:41:05] [PASSED] DVI-I
[09:41:05] [PASSED] DVI-D
[09:41:05] [PASSED] DVI-A
[09:41:05] [PASSED] Composite
[09:41:05] [PASSED] SVIDEO
[09:41:05] [PASSED] LVDS
[09:41:05] [PASSED] Component
[09:41:05] [PASSED] DIN
[09:41:05] [PASSED] DP
[09:41:05] [PASSED] HDMI-A
[09:41:05] [PASSED] HDMI-B
[09:41:05] [PASSED] TV
[09:41:05] [PASSED] eDP
[09:41:05] [PASSED] Virtual
[09:41:05] [PASSED] DSI
[09:41:05] [PASSED] DPI
[09:41:05] [PASSED] Writeback
[09:41:05] [PASSED] SPI
[09:41:05] [PASSED] USB
[09:41:05] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[09:41:05] =========== [PASSED] drm_connector_dynamic_init ============
[09:41:05] ==== drm_connector_dynamic_register_early (4 subtests) =====
[09:41:05] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[09:41:05] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[09:41:05] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[09:41:05] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[09:41:05] ====== [PASSED] drm_connector_dynamic_register_early =======
[09:41:05] ======= drm_connector_dynamic_register (7 subtests) ========
[09:41:05] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[09:41:05] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[09:41:05] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[09:41:05] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[09:41:05] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[09:41:05] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[09:41:05] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[09:41:05] ========= [PASSED] drm_connector_dynamic_register ==========
[09:41:05] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[09:41:05] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[09:41:05] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[09:41:05] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[09:41:05] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[09:41:05] ========== drm_test_get_tv_mode_from_name_valid ===========
[09:41:05] [PASSED] NTSC
[09:41:05] [PASSED] NTSC-443
[09:41:05] [PASSED] NTSC-J
[09:41:05] [PASSED] PAL
[09:41:05] [PASSED] PAL-M
[09:41:05] [PASSED] PAL-N
[09:41:05] [PASSED] SECAM
[09:41:05] [PASSED] Mono
[09:41:05] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[09:41:05] [PASSED] drm_test_get_tv_mode_from_name_truncated
[09:41:05] ============ [PASSED] drm_get_tv_mode_from_name ============
[09:41:05] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[09:41:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[09:41:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[09:41:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[09:41:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[09:41:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[09:41:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[09:41:05] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[09:41:05] [PASSED] VIC 96
[09:41:05] [PASSED] VIC 97
[09:41:05] [PASSED] VIC 101
[09:41:05] [PASSED] VIC 102
[09:41:05] [PASSED] VIC 106
[09:41:05] [PASSED] VIC 107
[09:41:05] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[09:41:05] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[09:41:05] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[09:41:05] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[09:41:05] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[09:41:05] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[09:41:05] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[09:41:05] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[09:41:05] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[09:41:05] [PASSED] Automatic
[09:41:05] [PASSED] Full
[09:41:05] [PASSED] Limited 16:235
[09:41:05] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[09:41:05] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[09:41:05] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[09:41:05] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[09:41:05] === drm_test_drm_hdmi_connector_get_output_format_name ====
[09:41:05] [PASSED] RGB
[09:41:05] [PASSED] YUV 4:2:0
[09:41:05] [PASSED] YUV 4:2:2
[09:41:05] [PASSED] YUV 4:4:4
[09:41:05] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[09:41:05] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[09:41:05] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[09:41:05] ============= drm_damage_helper (21 subtests) ==============
[09:41:05] [PASSED] drm_test_damage_iter_no_damage
[09:41:05] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[09:41:05] [PASSED] drm_test_damage_iter_no_damage_src_moved
[09:41:05] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[09:41:05] [PASSED] drm_test_damage_iter_no_damage_not_visible
[09:41:05] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[09:41:05] [PASSED] drm_test_damage_iter_no_damage_no_fb
[09:41:05] [PASSED] drm_test_damage_iter_simple_damage
[09:41:05] [PASSED] drm_test_damage_iter_single_damage
[09:41:05] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[09:41:05] [PASSED] drm_test_damage_iter_single_damage_outside_src
[09:41:05] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[09:41:05] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[09:41:05] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[09:41:05] [PASSED] drm_test_damage_iter_single_damage_src_moved
[09:41:05] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[09:41:05] [PASSED] drm_test_damage_iter_damage
[09:41:05] [PASSED] drm_test_damage_iter_damage_one_intersect
[09:41:05] [PASSED] drm_test_damage_iter_damage_one_outside
[09:41:05] [PASSED] drm_test_damage_iter_damage_src_moved
[09:41:05] [PASSED] drm_test_damage_iter_damage_not_visible
[09:41:05] ================ [PASSED] drm_damage_helper ================
[09:41:05] ============== drm_dp_mst_helper (3 subtests) ==============
[09:41:05] ============== drm_test_dp_mst_calc_pbn_mode ==============
[09:41:05] [PASSED] Clock 154000 BPP 30 DSC disabled
[09:41:05] [PASSED] Clock 234000 BPP 30 DSC disabled
[09:41:05] [PASSED] Clock 297000 BPP 24 DSC disabled
[09:41:05] [PASSED] Clock 332880 BPP 24 DSC enabled
[09:41:05] [PASSED] Clock 324540 BPP 24 DSC enabled
[09:41:05] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[09:41:05] ============== drm_test_dp_mst_calc_pbn_div ===============
[09:41:05] [PASSED] Link rate 2000000 lane count 4
[09:41:05] [PASSED] Link rate 2000000 lane count 2
[09:41:05] [PASSED] Link rate 2000000 lane count 1
[09:41:05] [PASSED] Link rate 1350000 lane count 4
[09:41:05] [PASSED] Link rate 1350000 lane count 2
[09:41:05] [PASSED] Link rate 1350000 lane count 1
[09:41:05] [PASSED] Link rate 1000000 lane count 4
[09:41:05] [PASSED] Link rate 1000000 lane count 2
[09:41:05] [PASSED] Link rate 1000000 lane count 1
[09:41:05] [PASSED] Link rate 810000 lane count 4
[09:41:05] [PASSED] Link rate 810000 lane count 2
[09:41:05] [PASSED] Link rate 810000 lane count 1
[09:41:05] [PASSED] Link rate 540000 lane count 4
[09:41:05] [PASSED] Link rate 540000 lane count 2
[09:41:05] [PASSED] Link rate 540000 lane count 1
[09:41:05] [PASSED] Link rate 270000 lane count 4
[09:41:05] [PASSED] Link rate 270000 lane count 2
[09:41:05] [PASSED] Link rate 270000 lane count 1
[09:41:05] [PASSED] Link rate 162000 lane count 4
[09:41:05] [PASSED] Link rate 162000 lane count 2
[09:41:05] [PASSED] Link rate 162000 lane count 1
[09:41:05] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[09:41:05] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[09:41:05] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[09:41:05] [PASSED] DP_POWER_UP_PHY with port number
[09:41:05] [PASSED] DP_POWER_DOWN_PHY with port number
[09:41:05] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[09:41:05] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[09:41:05] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[09:41:05] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[09:41:05] [PASSED] DP_QUERY_PAYLOAD with port number
[09:41:05] [PASSED] DP_QUERY_PAYLOAD with VCPI
[09:41:05] [PASSED] DP_REMOTE_DPCD_READ with port number
[09:41:05] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[09:41:05] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[09:41:05] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[09:41:05] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[09:41:05] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[09:41:05] [PASSED] DP_REMOTE_I2C_READ with port number
[09:41:05] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[09:41:05] [PASSED] DP_REMOTE_I2C_READ with transactions array
[09:41:05] [PASSED] DP_REMOTE_I2C_WRITE with port number
[09:41:05] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[09:41:05] [PASSED] DP_REMOTE_I2C_WRITE with data array
[09:41:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[09:41:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[09:41:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[09:41:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[09:41:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[09:41:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[09:41:05] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[09:41:05] ================ [PASSED] drm_dp_mst_helper ================
[09:41:05] ================== drm_exec (7 subtests) ===================
[09:41:05] [PASSED] sanitycheck
[09:41:05] [PASSED] test_lock
[09:41:05] [PASSED] test_lock_unlock
[09:41:05] [PASSED] test_duplicates
[09:41:05] [PASSED] test_prepare
[09:41:05] [PASSED] test_prepare_array
[09:41:05] [PASSED] test_multiple_loops
[09:41:05] ==================== [PASSED] drm_exec =====================
[09:41:05] =========== drm_format_helper_test (17 subtests) ===========
[09:41:05] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[09:41:05] [PASSED] single_pixel_source_buffer
[09:41:05] [PASSED] single_pixel_clip_rectangle
[09:41:05] [PASSED] well_known_colors
[09:41:05] [PASSED] destination_pitch
[09:41:05] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[09:41:05] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[09:41:05] [PASSED] single_pixel_source_buffer
[09:41:05] [PASSED] single_pixel_clip_rectangle
[09:41:05] [PASSED] well_known_colors
[09:41:05] [PASSED] destination_pitch
[09:41:05] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[09:41:05] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[09:41:05] [PASSED] single_pixel_source_buffer
[09:41:05] [PASSED] single_pixel_clip_rectangle
[09:41:05] [PASSED] well_known_colors
[09:41:05] [PASSED] destination_pitch
[09:41:05] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[09:41:05] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[09:41:05] [PASSED] single_pixel_source_buffer
[09:41:05] [PASSED] single_pixel_clip_rectangle
[09:41:05] [PASSED] well_known_colors
[09:41:05] [PASSED] destination_pitch
[09:41:05] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[09:41:05] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[09:41:05] [PASSED] single_pixel_source_buffer
[09:41:05] [PASSED] single_pixel_clip_rectangle
[09:41:05] [PASSED] well_known_colors
[09:41:05] [PASSED] destination_pitch
[09:41:05] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[09:41:05] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[09:41:05] [PASSED] single_pixel_source_buffer
[09:41:05] [PASSED] single_pixel_clip_rectangle
[09:41:05] [PASSED] well_known_colors
[09:41:05] [PASSED] destination_pitch
[09:41:05] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[09:41:05] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[09:41:05] [PASSED] single_pixel_source_buffer
[09:41:05] [PASSED] single_pixel_clip_rectangle
[09:41:05] [PASSED] well_known_colors
[09:41:05] [PASSED] destination_pitch
[09:41:05] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[09:41:05] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[09:41:05] [PASSED] single_pixel_source_buffer
[09:41:05] [PASSED] single_pixel_clip_rectangle
[09:41:05] [PASSED] well_known_colors
[09:41:05] [PASSED] destination_pitch
[09:41:05] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[09:41:05] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[09:41:05] [PASSED] single_pixel_source_buffer
[09:41:05] [PASSED] single_pixel_clip_rectangle
[09:41:05] [PASSED] well_known_colors
[09:41:05] [PASSED] destination_pitch
[09:41:05] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[09:41:05] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[09:41:05] [PASSED] single_pixel_source_buffer
[09:41:05] [PASSED] single_pixel_clip_rectangle
[09:41:05] [PASSED] well_known_colors
[09:41:05] [PASSED] destination_pitch
[09:41:05] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[09:41:05] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[09:41:05] [PASSED] single_pixel_source_buffer
[09:41:05] [PASSED] single_pixel_clip_rectangle
[09:41:05] [PASSED] well_known_colors
[09:41:05] [PASSED] destination_pitch
[09:41:05] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[09:41:05] ============== drm_test_fb_xrgb8888_to_mono ===============
[09:41:05] [PASSED] single_pixel_source_buffer
[09:41:05] [PASSED] single_pixel_clip_rectangle
[09:41:05] [PASSED] well_known_colors
[09:41:05] [PASSED] destination_pitch
[09:41:05] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[09:41:05] ==================== drm_test_fb_swab =====================
[09:41:05] [PASSED] single_pixel_source_buffer
[09:41:05] [PASSED] single_pixel_clip_rectangle
[09:41:05] [PASSED] well_known_colors
[09:41:05] [PASSED] destination_pitch
[09:41:05] ================ [PASSED] drm_test_fb_swab =================
[09:41:05] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[09:41:05] [PASSED] single_pixel_source_buffer
[09:41:05] [PASSED] single_pixel_clip_rectangle
[09:41:05] [PASSED] well_known_colors
[09:41:05] [PASSED] destination_pitch
[09:41:05] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[09:41:05] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[09:41:05] [PASSED] single_pixel_source_buffer
[09:41:05] [PASSED] single_pixel_clip_rectangle
[09:41:05] [PASSED] well_known_colors
[09:41:05] [PASSED] destination_pitch
[09:41:05] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[09:41:05] ================= drm_test_fb_clip_offset =================
[09:41:05] [PASSED] pass through
[09:41:05] [PASSED] horizontal offset
[09:41:05] [PASSED] vertical offset
[09:41:05] [PASSED] horizontal and vertical offset
[09:41:05] [PASSED] horizontal offset (custom pitch)
[09:41:05] [PASSED] vertical offset (custom pitch)
[09:41:05] [PASSED] horizontal and vertical offset (custom pitch)
[09:41:05] ============= [PASSED] drm_test_fb_clip_offset =============
[09:41:05] =================== drm_test_fb_memcpy ====================
[09:41:05] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[09:41:05] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[09:41:05] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[09:41:05] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[09:41:05] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[09:41:05] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[09:41:05] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[09:41:05] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[09:41:05] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[09:41:05] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[09:41:05] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[09:41:05] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[09:41:05] =============== [PASSED] drm_test_fb_memcpy ================
[09:41:05] ============= [PASSED] drm_format_helper_test ==============
[09:41:05] ================= drm_format (18 subtests) =================
[09:41:05] [PASSED] drm_test_format_block_width_invalid
[09:41:05] [PASSED] drm_test_format_block_width_one_plane
[09:41:05] [PASSED] drm_test_format_block_width_two_plane
[09:41:05] [PASSED] drm_test_format_block_width_three_plane
[09:41:05] [PASSED] drm_test_format_block_width_tiled
[09:41:05] [PASSED] drm_test_format_block_height_invalid
[09:41:05] [PASSED] drm_test_format_block_height_one_plane
[09:41:05] [PASSED] drm_test_format_block_height_two_plane
[09:41:05] [PASSED] drm_test_format_block_height_three_plane
[09:41:05] [PASSED] drm_test_format_block_height_tiled
[09:41:05] [PASSED] drm_test_format_min_pitch_invalid
[09:41:05] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[09:41:05] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[09:41:05] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[09:41:05] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[09:41:05] [PASSED] drm_test_format_min_pitch_two_plane
[09:41:05] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[09:41:05] [PASSED] drm_test_format_min_pitch_tiled
[09:41:05] =================== [PASSED] drm_format ====================
[09:41:05] ============== drm_framebuffer (10 subtests) ===============
[09:41:05] ========== drm_test_framebuffer_check_src_coords ==========
[09:41:05] [PASSED] Success: source fits into fb
[09:41:05] [PASSED] Fail: overflowing fb with x-axis coordinate
[09:41:05] [PASSED] Fail: overflowing fb with y-axis coordinate
[09:41:05] [PASSED] Fail: overflowing fb with source width
[09:41:05] [PASSED] Fail: overflowing fb with source height
[09:41:05] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[09:41:05] [PASSED] drm_test_framebuffer_cleanup
[09:41:05] =============== drm_test_framebuffer_create ===============
[09:41:05] [PASSED] ABGR8888 normal sizes
[09:41:05] [PASSED] ABGR8888 max sizes
[09:41:05] [PASSED] ABGR8888 pitch greater than min required
[09:41:05] [PASSED] ABGR8888 pitch less than min required
[09:41:05] [PASSED] ABGR8888 Invalid width
[09:41:05] [PASSED] ABGR8888 Invalid buffer handle
[09:41:05] [PASSED] No pixel format
[09:41:05] [PASSED] ABGR8888 Width 0
[09:41:05] [PASSED] ABGR8888 Height 0
[09:41:05] [PASSED] ABGR8888 Out of bound height * pitch combination
[09:41:05] [PASSED] ABGR8888 Large buffer offset
[09:41:05] [PASSED] ABGR8888 Buffer offset for inexistent plane
[09:41:05] [PASSED] ABGR8888 Invalid flag
[09:41:05] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[09:41:05] [PASSED] ABGR8888 Valid buffer modifier
[09:41:05] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[09:41:05] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[09:41:05] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[09:41:05] [PASSED] NV12 Normal sizes
[09:41:05] [PASSED] NV12 Max sizes
[09:41:05] [PASSED] NV12 Invalid pitch
[09:41:05] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[09:41:05] [PASSED] NV12 different modifier per-plane
[09:41:05] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[09:41:05] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[09:41:05] [PASSED] NV12 Modifier for inexistent plane
[09:41:05] [PASSED] NV12 Handle for inexistent plane
[09:41:05] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[09:41:05] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[09:41:05] [PASSED] YVU420 Normal sizes
[09:41:05] [PASSED] YVU420 Max sizes
[09:41:05] [PASSED] YVU420 Invalid pitch
[09:41:05] [PASSED] YVU420 Different pitches
[09:41:05] [PASSED] YVU420 Different buffer offsets/pitches
[09:41:05] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[09:41:05] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[09:41:05] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[09:41:05] [PASSED] YVU420 Valid modifier
[09:41:05] [PASSED] YVU420 Different modifiers per plane
[09:41:05] [PASSED] YVU420 Modifier for inexistent plane
[09:41:05] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[09:41:05] [PASSED] X0L2 Normal sizes
[09:41:05] [PASSED] X0L2 Max sizes
[09:41:05] [PASSED] X0L2 Invalid pitch
[09:41:05] [PASSED] X0L2 Pitch greater than minimum required
[09:41:05] [PASSED] X0L2 Handle for inexistent plane
[09:41:05] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[09:41:05] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[09:41:05] [PASSED] X0L2 Valid modifier
[09:41:05] [PASSED] X0L2 Modifier for inexistent plane
[09:41:05] =========== [PASSED] drm_test_framebuffer_create ===========
[09:41:05] [PASSED] drm_test_framebuffer_free
[09:41:05] [PASSED] drm_test_framebuffer_init
[09:41:05] [PASSED] drm_test_framebuffer_init_bad_format
[09:41:05] [PASSED] drm_test_framebuffer_init_dev_mismatch
[09:41:05] [PASSED] drm_test_framebuffer_lookup
[09:41:05] [PASSED] drm_test_framebuffer_lookup_inexistent
[09:41:05] [PASSED] drm_test_framebuffer_modifiers_not_supported
[09:41:05] ================= [PASSED] drm_framebuffer =================
[09:41:05] ================ drm_gem_shmem (8 subtests) ================
[09:41:05] [PASSED] drm_gem_shmem_test_obj_create
[09:41:05] [PASSED] drm_gem_shmem_test_obj_create_private
[09:41:05] [PASSED] drm_gem_shmem_test_pin_pages
[09:41:05] [PASSED] drm_gem_shmem_test_vmap
[09:41:05] [PASSED] drm_gem_shmem_test_get_pages_sgt
[09:41:05] [PASSED] drm_gem_shmem_test_get_sg_table
[09:41:05] [PASSED] drm_gem_shmem_test_madvise
[09:41:05] [PASSED] drm_gem_shmem_test_purge
[09:41:05] ================== [PASSED] drm_gem_shmem ==================
[09:41:05] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[09:41:05] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[09:41:05] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[09:41:05] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[09:41:05] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[09:41:05] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[09:41:05] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[09:41:05] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[09:41:05] [PASSED] Automatic
[09:41:05] [PASSED] Full
[09:41:05] [PASSED] Limited 16:235
[09:41:05] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[09:41:05] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[09:41:05] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[09:41:05] [PASSED] drm_test_check_disable_connector
[09:41:05] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[09:41:05] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[09:41:05] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[09:41:05] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[09:41:05] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[09:41:05] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[09:41:05] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[09:41:05] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[09:41:05] [PASSED] drm_test_check_output_bpc_dvi
[09:41:05] [PASSED] drm_test_check_output_bpc_format_vic_1
[09:41:05] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[09:41:05] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[09:41:05] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[09:41:05] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[09:41:05] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[09:41:05] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[09:41:05] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[09:41:05] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[09:41:05] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[09:41:05] [PASSED] drm_test_check_broadcast_rgb_value
[09:41:05] [PASSED] drm_test_check_bpc_8_value
[09:41:05] [PASSED] drm_test_check_bpc_10_value
[09:41:05] [PASSED] drm_test_check_bpc_12_value
[09:41:05] [PASSED] drm_test_check_format_value
[09:41:05] [PASSED] drm_test_check_tmds_char_value
[09:41:05] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[09:41:05] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[09:41:05] [PASSED] drm_test_check_mode_valid
[09:41:05] [PASSED] drm_test_check_mode_valid_reject
[09:41:05] [PASSED] drm_test_check_mode_valid_reject_rate
[09:41:05] [PASSED] drm_test_check_mode_valid_reject_max_clock
[09:41:05] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[09:41:05] ================= drm_managed (2 subtests) =================
[09:41:05] [PASSED] drm_test_managed_release_action
[09:41:05] [PASSED] drm_test_managed_run_action
[09:41:05] =================== [PASSED] drm_managed ===================
[09:41:05] =================== drm_mm (6 subtests) ====================
[09:41:05] [PASSED] drm_test_mm_init
[09:41:05] [PASSED] drm_test_mm_debug
[09:41:05] [PASSED] drm_test_mm_align32
[09:41:05] [PASSED] drm_test_mm_align64
[09:41:05] [PASSED] drm_test_mm_lowest
[09:41:05] [PASSED] drm_test_mm_highest
[09:41:05] ===================== [PASSED] drm_mm ======================
[09:41:05] ============= drm_modes_analog_tv (5 subtests) =============
[09:41:05] [PASSED] drm_test_modes_analog_tv_mono_576i
[09:41:05] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[09:41:05] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[09:41:05] [PASSED] drm_test_modes_analog_tv_pal_576i
[09:41:05] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[09:41:05] =============== [PASSED] drm_modes_analog_tv ===============
[09:41:05] ============== drm_plane_helper (2 subtests) ===============
[09:41:05] =============== drm_test_check_plane_state ================
[09:41:05] [PASSED] clipping_simple
[09:41:05] [PASSED] clipping_rotate_reflect
[09:41:05] [PASSED] positioning_simple
[09:41:05] [PASSED] upscaling
[09:41:05] [PASSED] downscaling
[09:41:05] [PASSED] rounding1
[09:41:05] [PASSED] rounding2
[09:41:05] [PASSED] rounding3
[09:41:05] [PASSED] rounding4
[09:41:05] =========== [PASSED] drm_test_check_plane_state ============
[09:41:05] =========== drm_test_check_invalid_plane_state ============
[09:41:05] [PASSED] positioning_invalid
[09:41:05] [PASSED] upscaling_invalid
[09:41:05] [PASSED] downscaling_invalid
[09:41:05] ======= [PASSED] drm_test_check_invalid_plane_state ========
[09:41:05] ================ [PASSED] drm_plane_helper =================
[09:41:05] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[09:41:05] ====== drm_test_connector_helper_tv_get_modes_check =======
[09:41:05] [PASSED] None
[09:41:05] [PASSED] PAL
[09:41:05] [PASSED] NTSC
[09:41:05] [PASSED] Both, NTSC Default
[09:41:05] [PASSED] Both, PAL Default
[09:41:05] [PASSED] Both, NTSC Default, with PAL on command-line
[09:41:05] [PASSED] Both, PAL Default, with NTSC on command-line
[09:41:05] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[09:41:05] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[09:41:05] ================== drm_rect (9 subtests) ===================
[09:41:05] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[09:41:05] [PASSED] drm_test_rect_clip_scaled_not_clipped
[09:41:05] [PASSED] drm_test_rect_clip_scaled_clipped
[09:41:05] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[09:41:05] ================= drm_test_rect_intersect =================
[09:41:05] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[09:41:05] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[09:41:05] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[09:41:05] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[09:41:05] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[09:41:05] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[09:41:05] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[09:41:05] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[09:41:05] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[09:41:05] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[09:41:05] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[09:41:05] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[09:41:05] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[09:41:05] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[09:41:05] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[09:41:05] ============= [PASSED] drm_test_rect_intersect =============
[09:41:05] ================ drm_test_rect_calc_hscale ================
[09:41:05] [PASSED] normal use
[09:41:05] [PASSED] out of max range
[09:41:05] [PASSED] out of min range
[09:41:05] [PASSED] zero dst
[09:41:05] [PASSED] negative src
[09:41:05] [PASSED] negative dst
[09:41:05] ============ [PASSED] drm_test_rect_calc_hscale ============
[09:41:05] ================ drm_test_rect_calc_vscale ================
[09:41:05] [PASSED] normal use
[09:41:05] [PASSED] out of max range
[09:41:05] [PASSED] out of min range
[09:41:05] [PASSED] zero dst
[09:41:05] [PASSED] negative src
[09:41:05] [PASSED] negative dst
[09:41:05] ============ [PASSED] drm_test_rect_calc_vscale ============
[09:41:05] ================== drm_test_rect_rotate ===================
[09:41:05] [PASSED] reflect-x
[09:41:05] [PASSED] reflect-y
[09:41:05] [PASSED] rotate-0
[09:41:05] [PASSED] rotate-90
[09:41:05] [PASSED] rotate-180
[09:41:05] [PASSED] rotate-270
stty: 'standard input': Inappropriate ioctl for device
[09:41:05] ============== [PASSED] drm_test_rect_rotate ===============
[09:41:05] ================ drm_test_rect_rotate_inv =================
[09:41:05] [PASSED] reflect-x
[09:41:05] [PASSED] reflect-y
[09:41:05] [PASSED] rotate-0
[09:41:05] [PASSED] rotate-90
[09:41:05] [PASSED] rotate-180
[09:41:05] [PASSED] rotate-270
[09:41:05] ============ [PASSED] drm_test_rect_rotate_inv =============
[09:41:05] ==================== [PASSED] drm_rect =====================
[09:41:05] ============ drm_sysfb_modeset_test (1 subtest) ============
[09:41:05] ============ drm_test_sysfb_build_fourcc_list =============
[09:41:05] [PASSED] no native formats
[09:41:05] [PASSED] XRGB8888 as native format
[09:41:05] [PASSED] remove duplicates
[09:41:05] [PASSED] convert alpha formats
[09:41:05] [PASSED] random formats
[09:41:05] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[09:41:05] ============= [PASSED] drm_sysfb_modeset_test ==============
[09:41:05] ============================================================
[09:41:05] Testing complete. Ran 616 tests: passed: 616
[09:41:05] Elapsed time: 23.538s total, 1.673s configuring, 21.697s building, 0.147s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[09:41:05] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[09:41:07] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[09:41:14] Starting KUnit Kernel (1/1)...
[09:41:14] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[09:41:15] ================= ttm_device (5 subtests) ==================
[09:41:15] [PASSED] ttm_device_init_basic
[09:41:15] [PASSED] ttm_device_init_multiple
[09:41:15] [PASSED] ttm_device_fini_basic
[09:41:15] [PASSED] ttm_device_init_no_vma_man
[09:41:15] ================== ttm_device_init_pools ==================
[09:41:15] [PASSED] No DMA allocations, no DMA32 required
[09:41:15] [PASSED] DMA allocations, DMA32 required
[09:41:15] [PASSED] No DMA allocations, DMA32 required
[09:41:15] [PASSED] DMA allocations, no DMA32 required
[09:41:15] ============== [PASSED] ttm_device_init_pools ==============
[09:41:15] =================== [PASSED] ttm_device ====================
[09:41:15] ================== ttm_pool (8 subtests) ===================
[09:41:15] ================== ttm_pool_alloc_basic ===================
[09:41:15] [PASSED] One page
[09:41:15] [PASSED] More than one page
[09:41:15] [PASSED] Above the allocation limit
[09:41:15] [PASSED] One page, with coherent DMA mappings enabled
[09:41:15] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[09:41:15] ============== [PASSED] ttm_pool_alloc_basic ===============
[09:41:15] ============== ttm_pool_alloc_basic_dma_addr ==============
[09:41:15] [PASSED] One page
[09:41:15] [PASSED] More than one page
[09:41:15] [PASSED] Above the allocation limit
[09:41:15] [PASSED] One page, with coherent DMA mappings enabled
[09:41:15] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[09:41:15] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[09:41:15] [PASSED] ttm_pool_alloc_order_caching_match
[09:41:15] [PASSED] ttm_pool_alloc_caching_mismatch
[09:41:15] [PASSED] ttm_pool_alloc_order_mismatch
[09:41:15] [PASSED] ttm_pool_free_dma_alloc
[09:41:15] [PASSED] ttm_pool_free_no_dma_alloc
[09:41:15] [PASSED] ttm_pool_fini_basic
[09:41:15] ==================== [PASSED] ttm_pool =====================
[09:41:15] ================ ttm_resource (8 subtests) =================
[09:41:15] ================= ttm_resource_init_basic =================
[09:41:15] [PASSED] Init resource in TTM_PL_SYSTEM
[09:41:15] [PASSED] Init resource in TTM_PL_VRAM
[09:41:15] [PASSED] Init resource in a private placement
[09:41:15] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[09:41:15] ============= [PASSED] ttm_resource_init_basic =============
[09:41:15] [PASSED] ttm_resource_init_pinned
[09:41:15] [PASSED] ttm_resource_fini_basic
[09:41:15] [PASSED] ttm_resource_manager_init_basic
[09:41:15] [PASSED] ttm_resource_manager_usage_basic
[09:41:15] [PASSED] ttm_resource_manager_set_used_basic
[09:41:15] [PASSED] ttm_sys_man_alloc_basic
[09:41:15] [PASSED] ttm_sys_man_free_basic
[09:41:15] ================== [PASSED] ttm_resource ===================
[09:41:15] =================== ttm_tt (15 subtests) ===================
[09:41:15] ==================== ttm_tt_init_basic ====================
[09:41:15] [PASSED] Page-aligned size
[09:41:15] [PASSED] Extra pages requested
[09:41:15] ================ [PASSED] ttm_tt_init_basic ================
[09:41:15] [PASSED] ttm_tt_init_misaligned
[09:41:15] [PASSED] ttm_tt_fini_basic
[09:41:15] [PASSED] ttm_tt_fini_sg
[09:41:15] [PASSED] ttm_tt_fini_shmem
[09:41:15] [PASSED] ttm_tt_create_basic
[09:41:15] [PASSED] ttm_tt_create_invalid_bo_type
[09:41:15] [PASSED] ttm_tt_create_ttm_exists
[09:41:15] [PASSED] ttm_tt_create_failed
[09:41:15] [PASSED] ttm_tt_destroy_basic
[09:41:15] [PASSED] ttm_tt_populate_null_ttm
[09:41:15] [PASSED] ttm_tt_populate_populated_ttm
[09:41:15] [PASSED] ttm_tt_unpopulate_basic
[09:41:15] [PASSED] ttm_tt_unpopulate_empty_ttm
[09:41:15] [PASSED] ttm_tt_swapin_basic
[09:41:15] ===================== [PASSED] ttm_tt ======================
[09:41:15] =================== ttm_bo (14 subtests) ===================
[09:41:15] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[09:41:15] [PASSED] Cannot be interrupted and sleeps
[09:41:15] [PASSED] Cannot be interrupted, locks straight away
[09:41:15] [PASSED] Can be interrupted, sleeps
[09:41:15] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[09:41:15] [PASSED] ttm_bo_reserve_locked_no_sleep
[09:41:15] [PASSED] ttm_bo_reserve_no_wait_ticket
[09:41:15] [PASSED] ttm_bo_reserve_double_resv
[09:41:15] [PASSED] ttm_bo_reserve_interrupted
[09:41:15] [PASSED] ttm_bo_reserve_deadlock
[09:41:15] [PASSED] ttm_bo_unreserve_basic
[09:41:15] [PASSED] ttm_bo_unreserve_pinned
[09:41:15] [PASSED] ttm_bo_unreserve_bulk
[09:41:15] [PASSED] ttm_bo_put_basic
[09:41:15] [PASSED] ttm_bo_put_shared_resv
[09:41:15] [PASSED] ttm_bo_pin_basic
[09:41:15] [PASSED] ttm_bo_pin_unpin_resource
[09:41:15] [PASSED] ttm_bo_multiple_pin_one_unpin
[09:41:15] ===================== [PASSED] ttm_bo ======================
[09:41:15] ============== ttm_bo_validate (22 subtests) ===============
[09:41:15] ============== ttm_bo_init_reserved_sys_man ===============
[09:41:15] [PASSED] Buffer object for userspace
[09:41:15] [PASSED] Kernel buffer object
[09:41:15] [PASSED] Shared buffer object
[09:41:15] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[09:41:15] ============== ttm_bo_init_reserved_mock_man ==============
[09:41:15] [PASSED] Buffer object for userspace
[09:41:15] [PASSED] Kernel buffer object
[09:41:15] [PASSED] Shared buffer object
[09:41:15] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[09:41:15] [PASSED] ttm_bo_init_reserved_resv
[09:41:15] ================== ttm_bo_validate_basic ==================
[09:41:15] [PASSED] Buffer object for userspace
[09:41:15] [PASSED] Kernel buffer object
[09:41:15] [PASSED] Shared buffer object
[09:41:15] ============== [PASSED] ttm_bo_validate_basic ==============
[09:41:15] [PASSED] ttm_bo_validate_invalid_placement
[09:41:15] ============= ttm_bo_validate_same_placement ==============
[09:41:15] [PASSED] System manager
[09:41:15] [PASSED] VRAM manager
[09:41:15] ========= [PASSED] ttm_bo_validate_same_placement ==========
[09:41:15] [PASSED] ttm_bo_validate_failed_alloc
[09:41:15] [PASSED] ttm_bo_validate_pinned
[09:41:15] [PASSED] ttm_bo_validate_busy_placement
[09:41:15] ================ ttm_bo_validate_multihop =================
[09:41:15] [PASSED] Buffer object for userspace
[09:41:15] [PASSED] Kernel buffer object
[09:41:15] [PASSED] Shared buffer object
[09:41:15] ============ [PASSED] ttm_bo_validate_multihop =============
[09:41:15] ========== ttm_bo_validate_no_placement_signaled ==========
[09:41:15] [PASSED] Buffer object in system domain, no page vector
[09:41:15] [PASSED] Buffer object in system domain with an existing page vector
[09:41:15] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[09:41:15] ======== ttm_bo_validate_no_placement_not_signaled ========
[09:41:15] [PASSED] Buffer object for userspace
[09:41:15] [PASSED] Kernel buffer object
[09:41:15] [PASSED] Shared buffer object
[09:41:15] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[09:41:15] [PASSED] ttm_bo_validate_move_fence_signaled
[09:41:15] ========= ttm_bo_validate_move_fence_not_signaled =========
[09:41:15] [PASSED] Waits for GPU
[09:41:15] [PASSED] Tries to lock straight away
[09:41:15] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[09:41:15] [PASSED] ttm_bo_validate_swapout
[09:41:15] [PASSED] ttm_bo_validate_happy_evict
[09:41:15] [PASSED] ttm_bo_validate_all_pinned_evict
[09:41:15] [PASSED] ttm_bo_validate_allowed_only_evict
[09:41:15] [PASSED] ttm_bo_validate_deleted_evict
[09:41:15] [PASSED] ttm_bo_validate_busy_domain_evict
[09:41:15] [PASSED] ttm_bo_validate_evict_gutting
[09:41:15] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[09:41:15] ================= [PASSED] ttm_bo_validate =================
[09:41:15] ============================================================
[09:41:15] Testing complete. Ran 102 tests: passed: 102
[09:41:15] Elapsed time: 9.931s total, 1.601s configuring, 7.713s building, 0.532s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH] drm/xe/uapi: Add DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY
@ 2025-06-25 9:58 Nitin Gote
2025-06-25 9:41 ` ✓ CI.KUnit: success for drm/xe/uapi: Add DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY (rev2) Patchwork
` (3 more replies)
0 siblings, 4 replies; 18+ messages in thread
From: Nitin Gote @ 2025-06-25 9:58 UTC (permalink / raw)
To: matthew.brost, tejas.upadhyay
Cc: intel-xe, joonas.lahtinen, rodrigo.vivi, himal.prasad.ghimiray,
nitin.r.gote
Add the DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY device query flag
which indicates whether a device supports DIS_NULL_QUERY (Disable null
anyhit shader query mechanism). The intent is for UMDs
to use this query and opt-in DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY flag
to disable null query mechanism for anyhit shader by setting
DIS_NULL_QUERY bit of RT_CTRL register for Xe2.
v2:
- Use xe_rtp_match_first_render_or_compute() api to check
render_or_compute. (Tejas)
- Validate args->flags (Tejas/Matthew)
- Add proper kernel-doc for both DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY
and DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT. (Matthew)
Signed-off-by: Nitin Gote <nitin.r.gote@intel.com>
---
drivers/gpu/drm/xe/xe_exec_queue.c | 11 ++++++++++-
drivers/gpu/drm/xe/xe_query.c | 3 ++-
include/uapi/drm/xe_drm.h | 12 ++++++++++++
3 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
index fee22358cc09..ef8b49d2242a 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue.c
+++ b/drivers/gpu/drm/xe/xe_exec_queue.c
@@ -26,6 +26,9 @@
#include "xe_trace.h"
#include "xe_vm.h"
#include "xe_pxp.h"
+#include "xe_gt_mcr.h"
+#include "regs/xe_gt_regs.h"
+#include "xe_rtp.h"
enum xe_exec_queue_sched_prop {
XE_EXEC_QUEUE_JOB_TIMEOUT = 0,
@@ -597,7 +600,8 @@ int xe_exec_queue_create_ioctl(struct drm_device *dev, void *data,
u32 len;
int err;
- if (XE_IOCTL_DBG(xe, args->flags & ~DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT) ||
+ if (XE_IOCTL_DBG(xe, args->flags &
+ ~(DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT | DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY)) ||
XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1]))
return -EINVAL;
@@ -693,6 +697,11 @@ int xe_exec_queue_create_ioctl(struct drm_device *dev, void *data,
}
}
+ if (((GRAPHICS_VER(xe) >= 20) && (GRAPHICS_VER(xe) < 30)) &&
+ (args->flags & DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY) &&
+ xe_rtp_match_first_render_or_compute(q->gt, q->hwe))
+ xe_gt_mcr_multicast_write(q->gt, RT_CTRL, DIS_NULL_QUERY);
+
q->xef = xe_file_get(xef);
/* user id alloc must always be last in ioctl to prevent UAF */
diff --git a/drivers/gpu/drm/xe/xe_query.c b/drivers/gpu/drm/xe/xe_query.c
index e8e1743dcb1e..c5002b8c9ac0 100644
--- a/drivers/gpu/drm/xe/xe_query.c
+++ b/drivers/gpu/drm/xe/xe_query.c
@@ -344,7 +344,8 @@ static int query_config(struct xe_device *xe, struct drm_xe_device_query *query)
config->info[DRM_XE_QUERY_CONFIG_FLAGS] |=
DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR;
config->info[DRM_XE_QUERY_CONFIG_FLAGS] |=
- DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY;
+ (DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY |
+ DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY);
config->info[DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT] =
xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K ? SZ_64K : SZ_4K;
config->info[DRM_XE_QUERY_CONFIG_VA_BITS] = xe->info.va_bits;
diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
index 8e8bbdec8c5c..7c30e707346c 100644
--- a/include/uapi/drm/xe_drm.h
+++ b/include/uapi/drm/xe_drm.h
@@ -397,6 +397,8 @@ struct drm_xe_query_mem_regions {
* has low latency hint support
* - %DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR - Flag is set if the
* device has CPU address mirroring support
+ * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY - Flag is set if the
+ * device has null query support for anyhit shader.
* - %DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT - Minimal memory alignment
* required by this device, typically SZ_4K or SZ_64K
* - %DRM_XE_QUERY_CONFIG_VA_BITS - Maximum bits of a virtual address
@@ -415,6 +417,7 @@ struct drm_xe_query_config {
#define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM (1 << 0)
#define DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY (1 << 1)
#define DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR (1 << 2)
+ #define DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY (1 << 3)
#define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT 2
#define DRM_XE_QUERY_CONFIG_VA_BITS 3
#define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY 4
@@ -1270,7 +1273,16 @@ struct drm_xe_exec_queue_create {
/** @vm_id: VM to use for this exec queue */
__u32 vm_id;
+ /** DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY - \
+ * Flag is set if the device has low latency hint support
+ */
#define DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT (1 << 0)
+
+ /** DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY - \
+ * flag is use to disable null query check for Anyhit shader
+ */
+#define DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY (1 << 1)
+
/** @flags: flags to use for this exec queue */
__u32 flags;
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* ✓ Xe.CI.BAT: success for drm/xe/uapi: Add DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY (rev2)
2025-06-25 9:58 [PATCH] drm/xe/uapi: Add DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY Nitin Gote
2025-06-25 9:41 ` ✓ CI.KUnit: success for drm/xe/uapi: Add DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY (rev2) Patchwork
@ 2025-06-25 10:17 ` Patchwork
2025-06-25 14:21 ` [PATCH] drm/xe/uapi: Add DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY Rodrigo Vivi
2025-06-26 6:22 ` ✓ Xe.CI.Full: success for drm/xe/uapi: Add DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY (rev2) Patchwork
3 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2025-06-25 10:17 UTC (permalink / raw)
To: Nitin Gote; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 974 bytes --]
== Series Details ==
Series: drm/xe/uapi: Add DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY (rev2)
URL : https://patchwork.freedesktop.org/series/150601/
State : success
== Summary ==
CI Bug Log - changes from xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19_BAT -> xe-pw-150601v2_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (9 -> 8)
------------------------------
Missing (1): bat-adlp-vm
Changes
-------
No changes found
Build changes
-------------
* Linux: xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19 -> xe-pw-150601v2
IGT_8424: 68588b3c89a1bbe08c54d21c4d3d2e509957c795 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19: bd57aee20daefb7b0dfe9017663668c92115ff19
xe-pw-150601v2: 150601v2
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/index.html
[-- Attachment #2: Type: text/html, Size: 1522 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH] drm/xe/uapi: Add DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY
2025-06-25 9:23 ` Gote, Nitin R
@ 2025-06-25 13:35 ` Matthew Brost
0 siblings, 0 replies; 18+ messages in thread
From: Matthew Brost @ 2025-06-25 13:35 UTC (permalink / raw)
To: Gote, Nitin R
Cc: Upadhyay, Tejas, intel-xe@lists.freedesktop.org,
joonas.lahtinen@linux.intel.com, Vivi, Rodrigo,
Ghimiray, Himal Prasad
On Wed, Jun 25, 2025 at 03:23:29AM -0600, Gote, Nitin R wrote:
> Hi Matthew,
> >
> > On Mon, Jun 23, 2025 at 12:10:36PM +0530, Nitin Gote wrote:
> > > Add the DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY device query
> > flag
> > > which indicates whether a device supports DIS_NULL_QUERY (Disable null
> >
> > s/DIS_NULL_QUERY/DISABLE_NULL_QUERY
>
> The DIS_NULL_QUERY naming convention is followed as per Bspec 57496.
>
The bspec has nothing to do with uAPI naming. uAPI should be as clear as
possible. Leave the register as DIS_NULL_QUERY but change the uAPI.
> >
> > > anyhit shader query mechanism). The intent is for UMDs to use this
> > > query and opt-in DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY flag to disable null
> > > query mechanism for anyhit shader by setting DIS_NULL_QUERY bit of
> > > RT_CTRL register for Xe2 IP.
> > >
> > > Signed-off-by: Nitin Gote <nitin.r.gote@intel.com>
> > > ---
> > > drivers/gpu/drm/xe/xe_exec_queue.c | 9 +++++++++
> > > drivers/gpu/drm/xe/xe_query.c | 3 ++-
> > > include/uapi/drm/xe_drm.h | 8 ++++++++
> > > 3 files changed, 19 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c
> > > b/drivers/gpu/drm/xe/xe_exec_queue.c
> > > index fee22358cc09..519f36db7cd0 100644
> > > --- a/drivers/gpu/drm/xe/xe_exec_queue.c
> > > +++ b/drivers/gpu/drm/xe/xe_exec_queue.c
> > > @@ -26,6 +26,8 @@
> > > #include "xe_trace.h"
> > > #include "xe_vm.h"
> > > #include "xe_pxp.h"
> > > +#include "xe_gt_mcr.h"
> > > +#include "regs/xe_gt_regs.h"
> > >
> > > enum xe_exec_queue_sched_prop {
> > > XE_EXEC_QUEUE_JOB_TIMEOUT = 0,
> > > @@ -693,6 +695,13 @@ int xe_exec_queue_create_ioctl(struct drm_device
> > *dev, void *data,
> > > }
> > > }
> > >
> > > + if (((GRAPHICS_VER(xe) >= 20) && (GRAPHICS_VER(xe) < 30)) &&
> > > + (args->flags & DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY) &&
> > > + (eci[0].engine_class == DRM_XE_ENGINE_CLASS_RENDER ||
> > > + eci[0].engine_class == DRM_XE_ENGINE_CLASS_COMPUTE)) {
> > > + xe_gt_mcr_multicast_write(q->gt, RT_CTRL, DIS_NULL_QUERY);
> > > + }
> >
> > You will hit an error before you get here because of the if statement above (not
> > shown in the diff) that sanitizes args->flags.
> >
>
> Yes. Agree with you. I will add it.
>
> > You don’t need {} here.
> >
> Thanks, I will remove it.
>
> > Also, a register write implies this would affect the entire GT, not just the exec
> > queue flagged with “disable NULL query.” Is that really the intent? It doesn’t
> > seem correct to me, but honestly, I’m not entirely sure what this patch is trying to
> > do. If the intent is for this to be per-exec queue, then I think this needs to be
> > implemented as some ring instructions in the LRC WA BB.
> >
>
> Here, the intention is that for the already released platforms Xe2,
> we need to add an opt-in flag via uapi to disable null query for anyhit shader.
> So that userspace can use this flag to disable anyhit shader query mechanism, and I think
> that it is not possible in the LRC WA BB. And to me, this placement looks ok as this setting is
> effective post xe_exec call.
>
Way can't you write a WA BB program that sets this?
xe_gt_mcr_multicast_write function seemly could be implemented in a WA
BB - the mcr_lock function indicates these registers are shared with
firmware, no different than WA BB.
The way you have it written it is a global (e.g., all user processes)
change which once is set is never cleared. You might as well just this
write at driver load and be done with it the way you it written.
Field a 2nd opinion here if you like, but this looks very incorrect to
me unless I'm completely missing something.
Matt
> > > +
> > > q->xef = xe_file_get(xef);
> > >
> > > /* user id alloc must always be last in ioctl to prevent UAF */ diff
> > > --git a/drivers/gpu/drm/xe/xe_query.c b/drivers/gpu/drm/xe/xe_query.c
> > > index e8e1743dcb1e..c5002b8c9ac0 100644
> > > --- a/drivers/gpu/drm/xe/xe_query.c
> > > +++ b/drivers/gpu/drm/xe/xe_query.c
> > > @@ -344,7 +344,8 @@ static int query_config(struct xe_device *xe, struct
> > drm_xe_device_query *query)
> > > config->info[DRM_XE_QUERY_CONFIG_FLAGS] |=
> > >
> > DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR;
> > > config->info[DRM_XE_QUERY_CONFIG_FLAGS] |=
> > > - DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY;
> > > + (DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY
> > |
> > > +
> > DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY);
> > > config->info[DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT] =
> > > xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K ? SZ_64K :
> > SZ_4K;
> > > config->info[DRM_XE_QUERY_CONFIG_VA_BITS] = xe->info.va_bits; diff
> > > --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h index
> > > 8e8bbdec8c5c..a5bfba121360 100644
> > > --- a/include/uapi/drm/xe_drm.h
> > > +++ b/include/uapi/drm/xe_drm.h
> > > @@ -397,6 +397,8 @@ struct drm_xe_query_mem_regions {
> > > * has low latency hint support
> > > * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR - Flag is
> > set if the
> > > * device has CPU address mirroring support
> > > + * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY - Flag is set if
> > the
> > > + * device has null query support for anyhit shader.
> > > * - %DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT - Minimal memory
> > alignment
> > > * required by this device, typically SZ_4K or SZ_64K
> > > * - %DRM_XE_QUERY_CONFIG_VA_BITS - Maximum bits of a virtual
> > > address @@ -415,6 +417,7 @@ struct drm_xe_query_config {
> > > #define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM (1 << 0)
> > > #define DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY (1 <<
> > 1)
> > > #define DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR
> > (1 << 2)
> > > + #define DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY (1 <<
> > 3)
> > > #define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT 2
> > > #define DRM_XE_QUERY_CONFIG_VA_BITS 3
> > > #define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY 4
> > > @@ -1271,6 +1274,11 @@ struct drm_xe_exec_queue_create {
> > > __u32 vm_id;
> > >
> > > #define DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT (1 << 0)
> > > + /*
> > > + * DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY flag is
> > > + * use to disable null query check for Anyhit shader
> > > + */
> > > +#define DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY (1 << 1)
> >
> > We should add proper kernel-doc for this flag.
> >
> > It looks like we’re also missing proper kernel-doc for
> > DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT. While you’re at it, could you add
> > that as well?
> >
> Sure. I will add kernel-doc for both macros.
>
> > Matt
> >
> > > /** @flags: flags to use for this exec queue */
> > > __u32 flags;
> > >
> > > --
> > > 2.25.1
> > >
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH] drm/xe/uapi: Add DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY
2025-06-25 9:58 [PATCH] drm/xe/uapi: Add DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY Nitin Gote
2025-06-25 9:41 ` ✓ CI.KUnit: success for drm/xe/uapi: Add DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY (rev2) Patchwork
2025-06-25 10:17 ` ✓ Xe.CI.BAT: " Patchwork
@ 2025-06-25 14:21 ` Rodrigo Vivi
2025-06-26 11:50 ` Gote, Nitin R
2025-06-26 6:22 ` ✓ Xe.CI.Full: success for drm/xe/uapi: Add DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY (rev2) Patchwork
3 siblings, 1 reply; 18+ messages in thread
From: Rodrigo Vivi @ 2025-06-25 14:21 UTC (permalink / raw)
To: Nitin Gote
Cc: matthew.brost, tejas.upadhyay, intel-xe, joonas.lahtinen,
himal.prasad.ghimiray
On Wed, Jun 25, 2025 at 03:28:05PM +0530, Nitin Gote wrote:
> Add the DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY device query flag
> which indicates whether a device supports DIS_NULL_QUERY (Disable null
> anyhit shader query mechanism). The intent is for UMDs
> to use this query and opt-in DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY flag
> to disable null query mechanism for anyhit shader by setting
> DIS_NULL_QUERY bit of RT_CTRL register for Xe2.
>
> v2:
> - Use xe_rtp_match_first_render_or_compute() api to check
> render_or_compute. (Tejas)
> - Validate args->flags (Tejas/Matthew)
> - Add proper kernel-doc for both DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY
> and DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT. (Matthew)
Matt asked for full spelling of DISABLE, no?!
Also, where are the UMD patches/merge-requests for this? And their ack?
Thanks,
Rodrigo.
>
> Signed-off-by: Nitin Gote <nitin.r.gote@intel.com>
> ---
> drivers/gpu/drm/xe/xe_exec_queue.c | 11 ++++++++++-
> drivers/gpu/drm/xe/xe_query.c | 3 ++-
> include/uapi/drm/xe_drm.h | 12 ++++++++++++
> 3 files changed, 24 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
> index fee22358cc09..ef8b49d2242a 100644
> --- a/drivers/gpu/drm/xe/xe_exec_queue.c
> +++ b/drivers/gpu/drm/xe/xe_exec_queue.c
> @@ -26,6 +26,9 @@
> #include "xe_trace.h"
> #include "xe_vm.h"
> #include "xe_pxp.h"
> +#include "xe_gt_mcr.h"
> +#include "regs/xe_gt_regs.h"
> +#include "xe_rtp.h"
>
> enum xe_exec_queue_sched_prop {
> XE_EXEC_QUEUE_JOB_TIMEOUT = 0,
> @@ -597,7 +600,8 @@ int xe_exec_queue_create_ioctl(struct drm_device *dev, void *data,
> u32 len;
> int err;
>
> - if (XE_IOCTL_DBG(xe, args->flags & ~DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT) ||
> + if (XE_IOCTL_DBG(xe, args->flags &
> + ~(DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT | DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY)) ||
> XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1]))
> return -EINVAL;
>
> @@ -693,6 +697,11 @@ int xe_exec_queue_create_ioctl(struct drm_device *dev, void *data,
> }
> }
>
> + if (((GRAPHICS_VER(xe) >= 20) && (GRAPHICS_VER(xe) < 30)) &&
> + (args->flags & DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY) &&
> + xe_rtp_match_first_render_or_compute(q->gt, q->hwe))
> + xe_gt_mcr_multicast_write(q->gt, RT_CTRL, DIS_NULL_QUERY);
> +
> q->xef = xe_file_get(xef);
>
> /* user id alloc must always be last in ioctl to prevent UAF */
> diff --git a/drivers/gpu/drm/xe/xe_query.c b/drivers/gpu/drm/xe/xe_query.c
> index e8e1743dcb1e..c5002b8c9ac0 100644
> --- a/drivers/gpu/drm/xe/xe_query.c
> +++ b/drivers/gpu/drm/xe/xe_query.c
> @@ -344,7 +344,8 @@ static int query_config(struct xe_device *xe, struct drm_xe_device_query *query)
> config->info[DRM_XE_QUERY_CONFIG_FLAGS] |=
> DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR;
> config->info[DRM_XE_QUERY_CONFIG_FLAGS] |=
> - DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY;
> + (DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY |
> + DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY);
> config->info[DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT] =
> xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K ? SZ_64K : SZ_4K;
> config->info[DRM_XE_QUERY_CONFIG_VA_BITS] = xe->info.va_bits;
> diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
> index 8e8bbdec8c5c..7c30e707346c 100644
> --- a/include/uapi/drm/xe_drm.h
> +++ b/include/uapi/drm/xe_drm.h
> @@ -397,6 +397,8 @@ struct drm_xe_query_mem_regions {
> * has low latency hint support
> * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR - Flag is set if the
> * device has CPU address mirroring support
> + * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY - Flag is set if the
> + * device has null query support for anyhit shader.
> * - %DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT - Minimal memory alignment
> * required by this device, typically SZ_4K or SZ_64K
> * - %DRM_XE_QUERY_CONFIG_VA_BITS - Maximum bits of a virtual address
> @@ -415,6 +417,7 @@ struct drm_xe_query_config {
> #define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM (1 << 0)
> #define DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY (1 << 1)
> #define DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR (1 << 2)
> + #define DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY (1 << 3)
> #define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT 2
> #define DRM_XE_QUERY_CONFIG_VA_BITS 3
> #define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY 4
> @@ -1270,7 +1273,16 @@ struct drm_xe_exec_queue_create {
> /** @vm_id: VM to use for this exec queue */
> __u32 vm_id;
>
> + /** DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY - \
> + * Flag is set if the device has low latency hint support
> + */
> #define DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT (1 << 0)
> +
> + /** DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY - \
> + * flag is use to disable null query check for Anyhit shader
> + */
> +#define DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY (1 << 1)
> +
> /** @flags: flags to use for this exec queue */
> __u32 flags;
>
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* ✓ Xe.CI.Full: success for drm/xe/uapi: Add DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY (rev2)
2025-06-25 9:58 [PATCH] drm/xe/uapi: Add DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY Nitin Gote
` (2 preceding siblings ...)
2025-06-25 14:21 ` [PATCH] drm/xe/uapi: Add DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY Rodrigo Vivi
@ 2025-06-26 6:22 ` Patchwork
3 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2025-06-26 6:22 UTC (permalink / raw)
To: Nitin Gote; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 49922 bytes --]
== Series Details ==
Series: drm/xe/uapi: Add DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY (rev2)
URL : https://patchwork.freedesktop.org/series/150601/
State : success
== Summary ==
CI Bug Log - changes from xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19_FULL -> xe-pw-150601v2_FULL
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (4 -> 4)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in xe-pw-150601v2_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_big_fb@4-tiled-64bpp-rotate-270:
- shard-bmg: NOTRUN -> [SKIP][1] ([Intel XE#2327]) +1 other test skip
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-7/igt@kms_big_fb@4-tiled-64bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-16bpp-rotate-0:
- shard-bmg: NOTRUN -> [SKIP][2] ([Intel XE#1124]) +5 other tests skip
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-7/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html
* igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
- shard-dg2-set2: NOTRUN -> [SKIP][3] ([Intel XE#607])
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-dg2-436/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0:
- shard-dg2-set2: NOTRUN -> [SKIP][4] ([Intel XE#1124]) +1 other test skip
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-dg2-464/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p:
- shard-bmg: NOTRUN -> [SKIP][5] ([Intel XE#2314] / [Intel XE#2894])
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-2/igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p.html
* igt@kms_bw@linear-tiling-1-displays-2160x1440p:
- shard-bmg: NOTRUN -> [SKIP][6] ([Intel XE#367])
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-3/igt@kms_bw@linear-tiling-1-displays-2160x1440p.html
* igt@kms_bw@linear-tiling-4-displays-2160x1440p:
- shard-dg2-set2: NOTRUN -> [SKIP][7] ([Intel XE#367])
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-dg2-436/igt@kms_bw@linear-tiling-4-displays-2160x1440p.html
* igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc:
- shard-bmg: NOTRUN -> [SKIP][8] ([Intel XE#2887]) +7 other tests skip
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-3/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc.html
* igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs:
- shard-dg2-set2: NOTRUN -> [SKIP][9] ([Intel XE#2907])
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-dg2-464/igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs.html
* igt@kms_ccs@crc-primary-basic-yf-tiled-ccs@pipe-d-dp-2:
- shard-dg2-set2: NOTRUN -> [SKIP][10] ([Intel XE#455] / [Intel XE#787]) +24 other tests skip
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-dg2-432/igt@kms_ccs@crc-primary-basic-yf-tiled-ccs@pipe-d-dp-2.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs@pipe-b-dp-2:
- shard-bmg: NOTRUN -> [SKIP][11] ([Intel XE#2652] / [Intel XE#787]) +7 other tests skip
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-4/igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs@pipe-b-dp-2.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc:
- shard-bmg: NOTRUN -> [SKIP][12] ([Intel XE#3432]) +1 other test skip
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-2/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-6:
- shard-dg2-set2: NOTRUN -> [SKIP][13] ([Intel XE#787]) +160 other tests skip
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-dg2-433/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-6.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-c-hdmi-a-2:
- shard-dg2-set2: NOTRUN -> [INCOMPLETE][14] ([Intel XE#1727] / [Intel XE#3113])
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-c-hdmi-a-2.html
* igt@kms_chamelium_color@ctm-0-75:
- shard-dg2-set2: NOTRUN -> [SKIP][15] ([Intel XE#306])
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-dg2-464/igt@kms_chamelium_color@ctm-0-75.html
* igt@kms_chamelium_color@ctm-max:
- shard-bmg: NOTRUN -> [SKIP][16] ([Intel XE#2325])
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-2/igt@kms_chamelium_color@ctm-max.html
* igt@kms_chamelium_edid@vga-edid-read:
- shard-dg2-set2: NOTRUN -> [SKIP][17] ([Intel XE#373])
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-dg2-436/igt@kms_chamelium_edid@vga-edid-read.html
* igt@kms_chamelium_frames@hdmi-aspect-ratio:
- shard-bmg: NOTRUN -> [SKIP][18] ([Intel XE#2252]) +5 other tests skip
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-3/igt@kms_chamelium_frames@hdmi-aspect-ratio.html
* igt@kms_content_protection@lic-type-0@pipe-a-dp-2:
- shard-bmg: NOTRUN -> [FAIL][19] ([Intel XE#1178])
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-4/igt@kms_content_protection@lic-type-0@pipe-a-dp-2.html
* igt@kms_cursor_crc@cursor-offscreen-256x85:
- shard-bmg: NOTRUN -> [SKIP][20] ([Intel XE#2320]) +3 other tests skip
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-3/igt@kms_cursor_crc@cursor-offscreen-256x85.html
* igt@kms_cursor_crc@cursor-offscreen-512x512:
- shard-dg2-set2: NOTRUN -> [SKIP][21] ([Intel XE#308])
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-dg2-433/igt@kms_cursor_crc@cursor-offscreen-512x512.html
* igt@kms_cursor_crc@cursor-sliding-512x170:
- shard-bmg: NOTRUN -> [SKIP][22] ([Intel XE#2321])
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-2/igt@kms_cursor_crc@cursor-sliding-512x170.html
* igt@kms_cursor_legacy@cursora-vs-flipb-atomic:
- shard-bmg: [PASS][23] -> [SKIP][24] ([Intel XE#2291])
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-bmg-1/igt@kms_cursor_legacy@cursora-vs-flipb-atomic.html
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-5/igt@kms_cursor_legacy@cursora-vs-flipb-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic:
- shard-bmg: [PASS][25] -> [FAIL][26] ([Intel XE#4633])
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-bmg-2/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-2/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
* igt@kms_dp_link_training@uhbr-mst:
- shard-bmg: NOTRUN -> [SKIP][27] ([Intel XE#4354])
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-7/igt@kms_dp_link_training@uhbr-mst.html
* igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-dirtyfb-tests:
- shard-bmg: NOTRUN -> [SKIP][28] ([Intel XE#4422])
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-2/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-dirtyfb-tests.html
* igt@kms_fbcon_fbt@fbc:
- shard-bmg: NOTRUN -> [SKIP][29] ([Intel XE#4156])
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-7/igt@kms_fbcon_fbt@fbc.html
* igt@kms_feature_discovery@psr2:
- shard-bmg: NOTRUN -> [SKIP][30] ([Intel XE#2374])
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-3/igt@kms_feature_discovery@psr2.html
* igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible:
- shard-bmg: [PASS][31] -> [SKIP][32] ([Intel XE#2316])
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-bmg-1/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible.html
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-5/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a6-dp4:
- shard-dg2-set2: [PASS][33] -> [FAIL][34] ([Intel XE#301] / [Intel XE#3321])
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-464/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a6-dp4.html
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-dg2-464/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a6-dp4.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a6:
- shard-dg2-set2: [PASS][35] -> [FAIL][36] ([Intel XE#301]) +3 other tests fail
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-433/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a6.html
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-dg2-433/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a6.html
* igt@kms_flip@plain-flip-fb-recreate@a-edp1:
- shard-lnl: [PASS][37] -> [FAIL][38] ([Intel XE#5337] / [Intel XE#886]) +1 other test fail
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-lnl-2/igt@kms_flip@plain-flip-fb-recreate@a-edp1.html
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-lnl-8/igt@kms_flip@plain-flip-fb-recreate@a-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling:
- shard-bmg: NOTRUN -> [SKIP][39] ([Intel XE#2293] / [Intel XE#2380])
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-2/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-valid-mode:
- shard-bmg: NOTRUN -> [SKIP][40] ([Intel XE#2293])
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-2/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling:
- shard-dg2-set2: NOTRUN -> [SKIP][41] ([Intel XE#455]) +2 other tests skip
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-dg2-436/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html
* igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-x-to-x:
- shard-adlp: [PASS][42] -> [DMESG-FAIL][43] ([Intel XE#4543]) +1 other test dmesg-fail
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-adlp-6/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-x-to-x.html
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-adlp-1/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-x-to-x.html
* igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-y-to-x:
- shard-adlp: [PASS][44] -> [FAIL][45] ([Intel XE#1874])
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-adlp-6/igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-y-to-x.html
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-adlp-1/igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-y-to-x.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt:
- shard-bmg: NOTRUN -> [SKIP][46] ([Intel XE#4141]) +8 other tests skip
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-indfb-draw-blt:
- shard-dg2-set2: NOTRUN -> [SKIP][47] ([Intel XE#651]) +2 other tests skip
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-dg2-433/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc:
- shard-bmg: NOTRUN -> [SKIP][48] ([Intel XE#2311]) +17 other tests skip
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary:
- shard-bmg: NOTRUN -> [SKIP][49] ([Intel XE#2313]) +18 other tests skip
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff:
- shard-dg2-set2: NOTRUN -> [SKIP][50] ([Intel XE#653]) +1 other test skip
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-dg2-433/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff.html
* igt@kms_hdr@brightness-with-hdr:
- shard-bmg: NOTRUN -> [SKIP][51] ([Intel XE#3374] / [Intel XE#3544])
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-2/igt@kms_hdr@brightness-with-hdr.html
* igt@kms_hdr@static-toggle-dpms:
- shard-bmg: [PASS][52] -> [SKIP][53] ([Intel XE#1503])
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-bmg-5/igt@kms_hdr@static-toggle-dpms.html
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-6/igt@kms_hdr@static-toggle-dpms.html
* igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner:
- shard-bmg: NOTRUN -> [SKIP][54] ([Intel XE#4090])
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-3/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html
* igt@kms_plane_alpha_blend@coverage-vs-premult-vs-constant@pipe-a-hdmi-a-1:
- shard-adlp: [PASS][55] -> [DMESG-WARN][56] ([Intel XE#2953] / [Intel XE#4173]) +3 other tests dmesg-warn
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-adlp-6/igt@kms_plane_alpha_blend@coverage-vs-premult-vs-constant@pipe-a-hdmi-a-1.html
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-adlp-1/igt@kms_plane_alpha_blend@coverage-vs-premult-vs-constant@pipe-a-hdmi-a-1.html
* igt@kms_pm_backlight@bad-brightness:
- shard-dg2-set2: NOTRUN -> [SKIP][57] ([Intel XE#870])
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-dg2-433/igt@kms_pm_backlight@bad-brightness.html
* igt@kms_pm_backlight@brightness-with-dpms:
- shard-bmg: NOTRUN -> [SKIP][58] ([Intel XE#2938])
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-2/igt@kms_pm_backlight@brightness-with-dpms.html
* igt@kms_pm_dc@dc3co-vpb-simulation:
- shard-bmg: NOTRUN -> [SKIP][59] ([Intel XE#2391])
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-3/igt@kms_pm_dc@dc3co-vpb-simulation.html
* igt@kms_pm_dc@dc6-psr:
- shard-bmg: NOTRUN -> [SKIP][60] ([Intel XE#2392])
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-7/igt@kms_pm_dc@dc6-psr.html
* igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-sf:
- shard-bmg: NOTRUN -> [SKIP][61] ([Intel XE#1489]) +3 other tests skip
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-2/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-sf.html
* igt@kms_psr@fbc-psr-sprite-blt:
- shard-dg2-set2: NOTRUN -> [SKIP][62] ([Intel XE#2850] / [Intel XE#929])
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-dg2-464/igt@kms_psr@fbc-psr-sprite-blt.html
* igt@kms_psr@psr2-sprite-blt:
- shard-bmg: NOTRUN -> [SKIP][63] ([Intel XE#2234] / [Intel XE#2850]) +10 other tests skip
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-7/igt@kms_psr@psr2-sprite-blt.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- shard-bmg: NOTRUN -> [SKIP][64] ([Intel XE#2414])
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-3/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
* igt@kms_setmode@basic:
- shard-adlp: [PASS][65] -> [FAIL][66] ([Intel XE#2883]) +1 other test fail
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-adlp-9/igt@kms_setmode@basic.html
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-adlp-9/igt@kms_setmode@basic.html
- shard-dg2-set2: [PASS][67] -> [FAIL][68] ([Intel XE#2883])
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-435/igt@kms_setmode@basic.html
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-dg2-432/igt@kms_setmode@basic.html
* igt@kms_setmode@basic@pipe-b-hdmi-a-2-pipe-a-dp-2:
- shard-dg2-set2: NOTRUN -> [FAIL][69] ([Intel XE#2883]) +5 other tests fail
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-dg2-432/igt@kms_setmode@basic@pipe-b-hdmi-a-2-pipe-a-dp-2.html
* igt@kms_tv_load_detect@load-detect:
- shard-bmg: NOTRUN -> [SKIP][70] ([Intel XE#2450])
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-7/igt@kms_tv_load_detect@load-detect.html
* igt@kms_vrr@negative-basic:
- shard-bmg: [PASS][71] -> [SKIP][72] ([Intel XE#1499])
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-bmg-1/igt@kms_vrr@negative-basic.html
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-5/igt@kms_vrr@negative-basic.html
* igt@kms_vrr@seamless-rr-switch-drrs:
- shard-bmg: NOTRUN -> [SKIP][73] ([Intel XE#1499])
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-3/igt@kms_vrr@seamless-rr-switch-drrs.html
* igt@xe_copy_basic@mem-set-linear-0xfd:
- shard-dg2-set2: NOTRUN -> [SKIP][74] ([Intel XE#1126])
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-dg2-464/igt@xe_copy_basic@mem-set-linear-0xfd.html
* igt@xe_eu_stall@unprivileged-access:
- shard-dg2-set2: NOTRUN -> [SKIP][75] ([Intel XE#5308])
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-dg2-433/igt@xe_eu_stall@unprivileged-access.html
* igt@xe_eudebug@basic-exec-queues:
- shard-bmg: NOTRUN -> [SKIP][76] ([Intel XE#4837]) +6 other tests skip
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-7/igt@xe_eudebug@basic-exec-queues.html
* igt@xe_eudebug_online@writes-caching-sram-bb-vram-target-sram:
- shard-dg2-set2: NOTRUN -> [SKIP][77] ([Intel XE#4837]) +2 other tests skip
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-dg2-464/igt@xe_eudebug_online@writes-caching-sram-bb-vram-target-sram.html
* igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-invalidate-race:
- shard-bmg: NOTRUN -> [SKIP][78] ([Intel XE#2322]) +3 other tests skip
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-2/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-invalidate-race.html
* igt@xe_exec_basic@multigpu-no-exec-basic-defer-mmap:
- shard-dg2-set2: [PASS][79] -> [SKIP][80] ([Intel XE#1392]) +7 other tests skip
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-434/igt@xe_exec_basic@multigpu-no-exec-basic-defer-mmap.html
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-dg2-432/igt@xe_exec_basic@multigpu-no-exec-basic-defer-mmap.html
* igt@xe_exec_fault_mode@many-execqueues-userptr-invalidate-prefetch:
- shard-dg2-set2: NOTRUN -> [SKIP][81] ([Intel XE#288]) +3 other tests skip
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-dg2-436/igt@xe_exec_fault_mode@many-execqueues-userptr-invalidate-prefetch.html
* igt@xe_exec_reset@parallel-gt-reset:
- shard-dg2-set2: [PASS][82] -> [DMESG-WARN][83] ([Intel XE#3876])
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-436/igt@xe_exec_reset@parallel-gt-reset.html
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-dg2-435/igt@xe_exec_reset@parallel-gt-reset.html
* igt@xe_exec_system_allocator@threads-many-mmap-new-huge-nomemset:
- shard-bmg: NOTRUN -> [SKIP][84] ([Intel XE#4943]) +17 other tests skip
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-3/igt@xe_exec_system_allocator@threads-many-mmap-new-huge-nomemset.html
* igt@xe_exec_system_allocator@threads-many-mmap-remap-ro:
- shard-dg2-set2: NOTRUN -> [SKIP][85] ([Intel XE#4915]) +40 other tests skip
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-dg2-464/igt@xe_exec_system_allocator@threads-many-mmap-remap-ro.html
* igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv:
- shard-dg2-set2: NOTRUN -> [ABORT][86] ([Intel XE#4917])
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-dg2-464/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
* igt@xe_live_ktest@xe_bo@xe_ccs_migrate_kunit:
- shard-bmg: NOTRUN -> [SKIP][87] ([Intel XE#2229])
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-3/igt@xe_live_ktest@xe_bo@xe_ccs_migrate_kunit.html
* igt@xe_oa@oa-unit-exclusive-stream-sample-oa:
- shard-dg2-set2: NOTRUN -> [SKIP][88] ([Intel XE#2541] / [Intel XE#3573])
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-dg2-464/igt@xe_oa@oa-unit-exclusive-stream-sample-oa.html
* igt@xe_pat@pat-index-xelpg:
- shard-bmg: NOTRUN -> [SKIP][89] ([Intel XE#2236])
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-2/igt@xe_pat@pat-index-xelpg.html
* igt@xe_peer2peer@read@read-gpua-vram01-gpub-system-p2p:
- shard-dg2-set2: NOTRUN -> [FAIL][90] ([Intel XE#1173])
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-dg2-436/igt@xe_peer2peer@read@read-gpua-vram01-gpub-system-p2p.html
* igt@xe_pm@d3cold-mmap-vram:
- shard-bmg: NOTRUN -> [SKIP][91] ([Intel XE#2284])
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-3/igt@xe_pm@d3cold-mmap-vram.html
* igt@xe_pm@d3cold-mocs:
- shard-dg2-set2: NOTRUN -> [SKIP][92] ([Intel XE#2284])
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-dg2-436/igt@xe_pm@d3cold-mocs.html
* igt@xe_pmu@gt-frequency:
- shard-dg2-set2: [PASS][93] -> [FAIL][94] ([Intel XE#4819]) +1 other test fail
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-433/igt@xe_pmu@gt-frequency.html
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-dg2-434/igt@xe_pmu@gt-frequency.html
* igt@xe_pxp@pxp-stale-bo-exec-post-rpm:
- shard-bmg: NOTRUN -> [SKIP][95] ([Intel XE#4733])
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-2/igt@xe_pxp@pxp-stale-bo-exec-post-rpm.html
* igt@xe_query@multigpu-query-invalid-cs-cycles:
- shard-dg2-set2: NOTRUN -> [SKIP][96] ([Intel XE#944])
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-dg2-464/igt@xe_query@multigpu-query-invalid-cs-cycles.html
* igt@xe_query@multigpu-query-invalid-size:
- shard-bmg: NOTRUN -> [SKIP][97] ([Intel XE#944]) +1 other test skip
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-2/igt@xe_query@multigpu-query-invalid-size.html
* igt@xe_sriov_auto_provisioning@resources-released-on-vfs-disabling:
- shard-bmg: NOTRUN -> [SKIP][98] ([Intel XE#4130]) +1 other test skip
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-7/igt@xe_sriov_auto_provisioning@resources-released-on-vfs-disabling.html
* igt@xe_sriov_auto_provisioning@selfconfig-reprovision-reduce-numvfs:
- shard-dg2-set2: NOTRUN -> [SKIP][99] ([Intel XE#4130])
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-dg2-464/igt@xe_sriov_auto_provisioning@selfconfig-reprovision-reduce-numvfs.html
#### Possible fixes ####
* igt@kms_async_flips@async-flip-suspend-resume@pipe-d-dp-4:
- shard-dg2-set2: [FAIL][100] ([Intel XE#4427]) -> [PASS][101] +1 other test pass
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-435/igt@kms_async_flips@async-flip-suspend-resume@pipe-d-dp-4.html
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-dg2-436/igt@kms_async_flips@async-flip-suspend-resume@pipe-d-dp-4.html
* igt@kms_async_flips@async-flip-with-page-flip-events-linear@pipe-c-edp-1:
- shard-lnl: [FAIL][102] ([Intel XE#911]) -> [PASS][103] +3 other tests pass
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-lnl-7/igt@kms_async_flips@async-flip-with-page-flip-events-linear@pipe-c-edp-1.html
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-lnl-6/igt@kms_async_flips@async-flip-with-page-flip-events-linear@pipe-c-edp-1.html
* igt@kms_async_flips@crc-atomic@pipe-c-hdmi-a-1:
- shard-adlp: [FAIL][104] ([Intel XE#3884]) -> [PASS][105]
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-adlp-6/igt@kms_async_flips@crc-atomic@pipe-c-hdmi-a-1.html
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-adlp-1/igt@kms_async_flips@crc-atomic@pipe-c-hdmi-a-1.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
- shard-adlp: [FAIL][106] ([Intel XE#3908]) -> [PASS][107] +1 other test pass
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-adlp-2/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-adlp-2/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-adlp: [DMESG-FAIL][108] ([Intel XE#4543]) -> [PASS][109] +2 other tests pass
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-adlp-4/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-adlp-6/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p:
- shard-bmg: [SKIP][110] ([Intel XE#2314] / [Intel XE#2894]) -> [PASS][111]
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-bmg-5/igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p.html
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-4/igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
- shard-bmg: [INCOMPLETE][112] ([Intel XE#3862]) -> [PASS][113] +1 other test pass
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-bmg-2/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-3/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc:
- shard-dg2-set2: [INCOMPLETE][114] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#3124]) -> [PASS][115]
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-dp-4:
- shard-dg2-set2: [INCOMPLETE][116] ([Intel XE#3124]) -> [PASS][117]
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-dp-4.html
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-dp-4.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-6:
- shard-dg2-set2: [DMESG-WARN][118] ([Intel XE#1727] / [Intel XE#3113]) -> [PASS][119]
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-6.html
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-6.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-bmg: [SKIP][120] ([Intel XE#2291]) -> [PASS][121] +1 other test pass
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-bmg-5/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-4/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
* igt@kms_feature_discovery@display-2x:
- shard-bmg: [SKIP][122] ([Intel XE#2373]) -> [PASS][123]
[122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-bmg-5/igt@kms_feature_discovery@display-2x.html
[123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-4/igt@kms_feature_discovery@display-2x.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a6-dp4:
- shard-dg2-set2: [FAIL][124] ([Intel XE#301]) -> [PASS][125] +3 other tests pass
[124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-464/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a6-dp4.html
[125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-dg2-464/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a6-dp4.html
* igt@kms_flip@2x-plain-flip-ts-check-interruptible:
- shard-bmg: [SKIP][126] ([Intel XE#2316]) -> [PASS][127] +7 other tests pass
[126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-bmg-5/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html
[127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-4/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html
* igt@kms_flip@blocking-absolute-wf_vblank-interruptible@a-dp4:
- shard-dg2-set2: [FAIL][128] -> [PASS][129] +3 other tests pass
[128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-435/igt@kms_flip@blocking-absolute-wf_vblank-interruptible@a-dp4.html
[129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-dg2-436/igt@kms_flip@blocking-absolute-wf_vblank-interruptible@a-dp4.html
* igt@kms_flip@flip-vs-dpms-on-nop-interruptible:
- shard-adlp: [DMESG-WARN][130] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][131] +1 other test pass
[130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-adlp-4/igt@kms_flip@flip-vs-dpms-on-nop-interruptible.html
[131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-adlp-6/igt@kms_flip@flip-vs-dpms-on-nop-interruptible.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1:
- shard-lnl: [FAIL][132] ([Intel XE#886]) -> [PASS][133] +3 other tests pass
[132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-lnl-4/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
[133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-lnl-7/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
* igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-to-y:
- shard-adlp: [FAIL][134] ([Intel XE#1874]) -> [PASS][135] +1 other test pass
[134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-adlp-6/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-to-y.html
[135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-adlp-1/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-to-y.html
* igt@kms_setmode@invalid-clone-single-crtc-stealing:
- shard-bmg: [SKIP][136] ([Intel XE#1435]) -> [PASS][137]
[136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-bmg-5/igt@kms_setmode@invalid-clone-single-crtc-stealing.html
[137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-4/igt@kms_setmode@invalid-clone-single-crtc-stealing.html
* igt@xe_exec_basic@multigpu-once-basic-defer-mmap:
- shard-dg2-set2: [SKIP][138] ([Intel XE#1392]) -> [PASS][139] +5 other tests pass
[138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-432/igt@xe_exec_basic@multigpu-once-basic-defer-mmap.html
[139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-dg2-433/igt@xe_exec_basic@multigpu-once-basic-defer-mmap.html
* igt@xe_exec_reset@gt-reset-stress:
- shard-adlp: [DMESG-WARN][140] ([Intel XE#4812]) -> [PASS][141]
[140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-adlp-4/igt@xe_exec_reset@gt-reset-stress.html
[141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-adlp-6/igt@xe_exec_reset@gt-reset-stress.html
* igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-new-bo-map-nomemset:
- shard-lnl: [FAIL][142] ([Intel XE#5018]) -> [PASS][143]
[142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-lnl-1/igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-new-bo-map-nomemset.html
[143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-lnl-4/igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-new-bo-map-nomemset.html
#### Warnings ####
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs:
- shard-dg2-set2: [INCOMPLETE][144] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#3124] / [Intel XE#4345]) -> [INCOMPLETE][145] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4345])
[144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
[145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
- shard-dg2-set2: [INCOMPLETE][146] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4345] / [Intel XE#4522]) -> [INCOMPLETE][147] ([Intel XE#2705] / [Intel XE#4212] / [Intel XE#4345])
[146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
[147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-dp-4:
- shard-dg2-set2: [INCOMPLETE][148] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4522]) -> [INCOMPLETE][149] ([Intel XE#2705] / [Intel XE#4212])
[148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-dp-4.html
[149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-dp-4.html
* igt@kms_content_protection@lic-type-0:
- shard-bmg: [SKIP][150] ([Intel XE#2341]) -> [FAIL][151] ([Intel XE#1178])
[150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-bmg-5/igt@kms_content_protection@lic-type-0.html
[151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-4/igt@kms_content_protection@lic-type-0.html
* igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible:
- shard-bmg: [FAIL][152] ([Intel XE#2882] / [Intel XE#5338]) -> [SKIP][153] ([Intel XE#2316])
[152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-bmg-7/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html
[153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-6/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html
* igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-move:
- shard-bmg: [SKIP][154] ([Intel XE#2311]) -> [SKIP][155] ([Intel XE#2312]) +3 other tests skip
[154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-bmg-1/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-move.html
[155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-move.html
* igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][156] ([Intel XE#2312]) -> [SKIP][157] ([Intel XE#2311]) +9 other tests skip
[156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-mmap-wc.html
[157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-pri-indfb-multidraw:
- shard-bmg: [SKIP][158] ([Intel XE#4141]) -> [SKIP][159] ([Intel XE#2312]) +1 other test skip
[158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-2p-pri-indfb-multidraw.html
[159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt:
- shard-bmg: [SKIP][160] ([Intel XE#2312]) -> [SKIP][161] ([Intel XE#4141]) +2 other tests skip
[160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html
[161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff:
- shard-bmg: [SKIP][162] ([Intel XE#2313]) -> [SKIP][163] ([Intel XE#2312]) +4 other tests skip
[162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff.html
[163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-blt:
- shard-bmg: [SKIP][164] ([Intel XE#2312]) -> [SKIP][165] ([Intel XE#2313]) +9 other tests skip
[164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-blt.html
[165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-blt.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-bmg: [SKIP][166] ([Intel XE#2509]) -> [SKIP][167] ([Intel XE#2426])
[166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-bmg-1/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
[167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-bmg-5/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@xe_peer2peer@read:
- shard-dg2-set2: [SKIP][168] ([Intel XE#1061]) -> [FAIL][169] ([Intel XE#1173])
[168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-432/igt@xe_peer2peer@read.html
[169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/shard-dg2-436/igt@xe_peer2peer@read.html
[Intel XE#1061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1061
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1126
[Intel XE#1173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1173
[Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
[Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
[Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
[Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
[Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
[Intel XE#1874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1874
[Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2236]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2236
[Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
[Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
[Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
[Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
[Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
[Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
[Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
[Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
[Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
[Intel XE#2373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2373
[Intel XE#2374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2374
[Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
[Intel XE#2391]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2391
[Intel XE#2392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2392
[Intel XE#2414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2414
[Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
[Intel XE#2450]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2450
[Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
[Intel XE#2541]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2541
[Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
[Intel XE#2705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2705
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
[Intel XE#2882]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2882
[Intel XE#2883]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2883
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
[Intel XE#2907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2907
[Intel XE#2938]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2938
[Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
[Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
[Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
[Intel XE#3124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3124
[Intel XE#3321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3321
[Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
[Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
[Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
[Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
[Intel XE#3862]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3862
[Intel XE#3876]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3876
[Intel XE#3884]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3884
[Intel XE#3908]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3908
[Intel XE#4090]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4090
[Intel XE#4130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4130
[Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
[Intel XE#4156]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4156
[Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
[Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
[Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
[Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
[Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
[Intel XE#4427]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4427
[Intel XE#4522]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4522
[Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
[Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
[Intel XE#4633]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4633
[Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
[Intel XE#4812]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4812
[Intel XE#4819]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4819
[Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
[Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
[Intel XE#4917]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4917
[Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
[Intel XE#5018]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5018
[Intel XE#5308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5308
[Intel XE#5337]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5337
[Intel XE#5338]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5338
[Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
[Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
[Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
[Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
[Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
[Intel XE#886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/886
[Intel XE#911]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/911
[Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
Build changes
-------------
* Linux: xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19 -> xe-pw-150601v2
IGT_8424: 68588b3c89a1bbe08c54d21c4d3d2e509957c795 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19: bd57aee20daefb7b0dfe9017663668c92115ff19
xe-pw-150601v2: 150601v2
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150601v2/index.html
[-- Attachment #2: Type: text/html, Size: 58180 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread
* RE: [PATCH] drm/xe/uapi: Add DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY
2025-06-25 14:21 ` [PATCH] drm/xe/uapi: Add DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY Rodrigo Vivi
@ 2025-06-26 11:50 ` Gote, Nitin R
2025-06-27 8:14 ` Gote, Nitin R
0 siblings, 1 reply; 18+ messages in thread
From: Gote, Nitin R @ 2025-06-26 11:50 UTC (permalink / raw)
To: Vivi, Rodrigo, Brost, Matthew
Cc: Upadhyay, Tejas, intel-xe@lists.freedesktop.org,
joonas.lahtinen@linux.intel.com, Ghimiray, Himal Prasad
Hi Matt and Rodrigo,
> On Wed, Jun 25, 2025 at 03:28:05PM +0530, Nitin Gote wrote:
> > Add the DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY device query
> flag
> > which indicates whether a device supports DIS_NULL_QUERY (Disable null
> > anyhit shader query mechanism). The intent is for UMDs to use this
> > query and opt-in DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY flag to disable null
> > query mechanism for anyhit shader by setting DIS_NULL_QUERY bit of
> > RT_CTRL register for Xe2.
> >
> > v2:
> > - Use xe_rtp_match_first_render_or_compute() api to check
> > render_or_compute. (Tejas)
> > - Validate args->flags (Tejas/Matthew)
> > - Add proper kernel-doc for both DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY
> > and DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT. (Matthew)
>
> Matt asked for full spelling of DISABLE, no?!
Thank you for clarifying the uAPI naming convention.
I will update it.
>
> Also, where are the UMD patches/merge-requests for this? And their ack?
>
From the Mesa team (Palli, Tapani) is going to send the corresponding Mesa patch.
Meanwhile, I floated this patch.
> Thanks,
> Rodrigo.
>
> >
> > Signed-off-by: Nitin Gote <nitin.r.gote@intel.com>
> > ---
> > drivers/gpu/drm/xe/xe_exec_queue.c | 11 ++++++++++-
> > drivers/gpu/drm/xe/xe_query.c | 3 ++-
> > include/uapi/drm/xe_drm.h | 12 ++++++++++++
> > 3 files changed, 24 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c
> > b/drivers/gpu/drm/xe/xe_exec_queue.c
> > index fee22358cc09..ef8b49d2242a 100644
> > --- a/drivers/gpu/drm/xe/xe_exec_queue.c
> > +++ b/drivers/gpu/drm/xe/xe_exec_queue.c
> > @@ -26,6 +26,9 @@
> > #include "xe_trace.h"
> > #include "xe_vm.h"
> > #include "xe_pxp.h"
> > +#include "xe_gt_mcr.h"
> > +#include "regs/xe_gt_regs.h"
> > +#include "xe_rtp.h"
> >
> > enum xe_exec_queue_sched_prop {
> > XE_EXEC_QUEUE_JOB_TIMEOUT = 0,
> > @@ -597,7 +600,8 @@ int xe_exec_queue_create_ioctl(struct drm_device
> *dev, void *data,
> > u32 len;
> > int err;
> >
> > - if (XE_IOCTL_DBG(xe, args->flags &
> ~DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT) ||
> > + if (XE_IOCTL_DBG(xe, args->flags &
> > + ~(DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT |
> > +DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY)) ||
> > XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1]))
> > return -EINVAL;
> >
> > @@ -693,6 +697,11 @@ int xe_exec_queue_create_ioctl(struct drm_device
> *dev, void *data,
> > }
> > }
> >
> > + if (((GRAPHICS_VER(xe) >= 20) && (GRAPHICS_VER(xe) < 30)) &&
> > + (args->flags & DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY) &&
> > + xe_rtp_match_first_render_or_compute(q->gt, q->hwe))
> > + xe_gt_mcr_multicast_write(q->gt, RT_CTRL, DIS_NULL_QUERY);
> > +
Also, as per Matt's suggestion in rev1, I'm exploring the WA BB program to set this.
Thanks,
Nitin
> > q->xef = xe_file_get(xef);
> >
> > /* user id alloc must always be last in ioctl to prevent UAF */ diff
> > --git a/drivers/gpu/drm/xe/xe_query.c b/drivers/gpu/drm/xe/xe_query.c
> > index e8e1743dcb1e..c5002b8c9ac0 100644
> > --- a/drivers/gpu/drm/xe/xe_query.c
> > +++ b/drivers/gpu/drm/xe/xe_query.c
> > @@ -344,7 +344,8 @@ static int query_config(struct xe_device *xe, struct
> drm_xe_device_query *query)
> > config->info[DRM_XE_QUERY_CONFIG_FLAGS] |=
> >
> DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR;
> > config->info[DRM_XE_QUERY_CONFIG_FLAGS] |=
> > - DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY;
> > + (DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY
> |
> > +
> DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY);
> > config->info[DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT] =
> > xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K ? SZ_64K :
> SZ_4K;
> > config->info[DRM_XE_QUERY_CONFIG_VA_BITS] = xe->info.va_bits; diff
> > --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h index
> > 8e8bbdec8c5c..7c30e707346c 100644
> > --- a/include/uapi/drm/xe_drm.h
> > +++ b/include/uapi/drm/xe_drm.h
> > @@ -397,6 +397,8 @@ struct drm_xe_query_mem_regions {
> > * has low latency hint support
> > * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR - Flag is
> set if the
> > * device has CPU address mirroring support
> > + * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY - Flag is set if
> the
> > + * device has null query support for anyhit shader.
> > * - %DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT - Minimal memory
> alignment
> > * required by this device, typically SZ_4K or SZ_64K
> > * - %DRM_XE_QUERY_CONFIG_VA_BITS - Maximum bits of a virtual
> > address @@ -415,6 +417,7 @@ struct drm_xe_query_config {
> > #define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM (1 << 0)
> > #define DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY (1 <<
> 1)
> > #define DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR
> (1 << 2)
> > + #define DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY (1 <<
> 3)
> > #define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT 2
> > #define DRM_XE_QUERY_CONFIG_VA_BITS 3
> > #define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY 4
> > @@ -1270,7 +1273,16 @@ struct drm_xe_exec_queue_create {
> > /** @vm_id: VM to use for this exec queue */
> > __u32 vm_id;
> >
> > + /** DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY - \
> > + * Flag is set if the device has low latency hint support
> > + */
> > #define DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT (1 << 0)
> > +
> > + /** DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY - \
> > + * flag is use to disable null query check for Anyhit shader
> > + */
> > +#define DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY (1 << 1)
> > +
> > /** @flags: flags to use for this exec queue */
> > __u32 flags;
> >
> > --
> > 2.25.1
> >
^ permalink raw reply [flat|nested] 18+ messages in thread
* RE: [PATCH] drm/xe/uapi: Add DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY
2025-06-26 11:50 ` Gote, Nitin R
@ 2025-06-27 8:14 ` Gote, Nitin R
2025-06-27 9:37 ` Upadhyay, Tejas
0 siblings, 1 reply; 18+ messages in thread
From: Gote, Nitin R @ 2025-06-27 8:14 UTC (permalink / raw)
To: Brost, Matthew
Cc: Vivi, Rodrigo, Upadhyay, Tejas, intel-xe@lists.freedesktop.org,
joonas.lahtinen@linux.intel.com, Ghimiray, Himal Prasad
Hi Matt,
>
> Hi Matt and Rodrigo,
>
> > On Wed, Jun 25, 2025 at 03:28:05PM +0530, Nitin Gote wrote:
> > > Add the DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY device
> query
> > flag
> > > which indicates whether a device supports DIS_NULL_QUERY (Disable
> > > null anyhit shader query mechanism). The intent is for UMDs to use
> > > this query and opt-in DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY flag to
> > > disable null query mechanism for anyhit shader by setting
> > > DIS_NULL_QUERY bit of RT_CTRL register for Xe2.
> > >
> > > v2:
> > > - Use xe_rtp_match_first_render_or_compute() api to check
> > > render_or_compute. (Tejas)
> > > - Validate args->flags (Tejas/Matthew)
> > > - Add proper kernel-doc for both
> DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY
> > > and DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT. (Matthew)
> >
> > Matt asked for full spelling of DISABLE, no?!
>
> Thank you for clarifying the uAPI naming convention.
> I will update it.
>
> >
> > Also, where are the UMD patches/merge-requests for this? And their ack?
> >
> From the Mesa team (Palli, Tapani) is going to send the corresponding Mesa
> patch.
> Meanwhile, I floated this patch.
>
> > Thanks,
> > Rodrigo.
> >
> > >
> > > Signed-off-by: Nitin Gote <nitin.r.gote@intel.com>
> > > ---
> > > drivers/gpu/drm/xe/xe_exec_queue.c | 11 ++++++++++-
> > > drivers/gpu/drm/xe/xe_query.c | 3 ++-
> > > include/uapi/drm/xe_drm.h | 12 ++++++++++++
> > > 3 files changed, 24 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c
> > > b/drivers/gpu/drm/xe/xe_exec_queue.c
> > > index fee22358cc09..ef8b49d2242a 100644
> > > --- a/drivers/gpu/drm/xe/xe_exec_queue.c
> > > +++ b/drivers/gpu/drm/xe/xe_exec_queue.c
> > > @@ -26,6 +26,9 @@
> > > #include "xe_trace.h"
> > > #include "xe_vm.h"
> > > #include "xe_pxp.h"
> > > +#include "xe_gt_mcr.h"
> > > +#include "regs/xe_gt_regs.h"
> > > +#include "xe_rtp.h"
> > >
> > > enum xe_exec_queue_sched_prop {
> > > XE_EXEC_QUEUE_JOB_TIMEOUT = 0,
> > > @@ -597,7 +600,8 @@ int xe_exec_queue_create_ioctl(struct drm_device
> > *dev, void *data,
> > > u32 len;
> > > int err;
> > >
> > > - if (XE_IOCTL_DBG(xe, args->flags &
> > ~DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT) ||
> > > + if (XE_IOCTL_DBG(xe, args->flags &
> > > + ~(DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT |
> > > +DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY)) ||
> > > XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1]))
> > > return -EINVAL;
> > >
> > > @@ -693,6 +697,11 @@ int xe_exec_queue_create_ioctl(struct
> > > drm_device
> > *dev, void *data,
> > > }
> > > }
> > >
> > > + if (((GRAPHICS_VER(xe) >= 20) && (GRAPHICS_VER(xe) < 30)) &&
> > > + (args->flags & DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY) &&
> > > + xe_rtp_match_first_render_or_compute(q->gt, q->hwe))
> > > + xe_gt_mcr_multicast_write(q->gt, RT_CTRL, DIS_NULL_QUERY);
> > > +
>
> Also, as per Matt's suggestion in rev1, I'm exploring the WA BB program to set
> this.
>
If we move this implementation from the exec queue creation time to the submission time and write
a WW BB program, then this register will be set for every exec queue submission.
Let's say if submission happens 3 times, then register gets written 3 times, which seems unnecessary.
So, having implementation in the exec queue create time, the register will be updated only once,
and we can disable it in the exec queue destroy.
What do you think? Could you please suggest?
Thanks,
Nitin
> > > q->xef = xe_file_get(xef);
> > >
> > > /* user id alloc must always be last in ioctl to prevent UAF */
> > > diff --git a/drivers/gpu/drm/xe/xe_query.c
> > > b/drivers/gpu/drm/xe/xe_query.c index e8e1743dcb1e..c5002b8c9ac0
> > > 100644
> > > --- a/drivers/gpu/drm/xe/xe_query.c
> > > +++ b/drivers/gpu/drm/xe/xe_query.c
> > > @@ -344,7 +344,8 @@ static int query_config(struct xe_device *xe,
> > > struct
> > drm_xe_device_query *query)
> > > config->info[DRM_XE_QUERY_CONFIG_FLAGS] |=
> > >
> > DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR;
> > > config->info[DRM_XE_QUERY_CONFIG_FLAGS] |=
> > > - DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY;
> > > + (DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY
> > |
> > > +
> > DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY);
> > > config->info[DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT] =
> > > xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K ? SZ_64K :
> > SZ_4K;
> > > config->info[DRM_XE_QUERY_CONFIG_VA_BITS] = xe->info.va_bits; diff
> > > --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h index
> > > 8e8bbdec8c5c..7c30e707346c 100644
> > > --- a/include/uapi/drm/xe_drm.h
> > > +++ b/include/uapi/drm/xe_drm.h
> > > @@ -397,6 +397,8 @@ struct drm_xe_query_mem_regions {
> > > * has low latency hint support
> > > * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR - Flag is
> > set if the
> > > * device has CPU address mirroring support
> > > + * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY - Flag is set
> if
> > the
> > > + * device has null query support for anyhit shader.
> > > * - %DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT - Minimal memory
> > alignment
> > > * required by this device, typically SZ_4K or SZ_64K
> > > * - %DRM_XE_QUERY_CONFIG_VA_BITS - Maximum bits of a virtual
> > > address @@ -415,6 +417,7 @@ struct drm_xe_query_config {
> > > #define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM (1 << 0)
> > > #define DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY (1 <<
> > 1)
> > > #define DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR
> > (1 << 2)
> > > + #define DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY (1 <<
> > 3)
> > > #define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT 2
> > > #define DRM_XE_QUERY_CONFIG_VA_BITS 3
> > > #define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY 4
> > > @@ -1270,7 +1273,16 @@ struct drm_xe_exec_queue_create {
> > > /** @vm_id: VM to use for this exec queue */
> > > __u32 vm_id;
> > >
> > > + /** DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY - \
> > > + * Flag is set if the device has low latency hint support
> > > + */
> > > #define DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT (1 << 0)
> > > +
> > > + /** DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY - \
> > > + * flag is use to disable null query check for Anyhit shader
> > > + */
> > > +#define DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY (1 << 1)
> > > +
> > > /** @flags: flags to use for this exec queue */
> > > __u32 flags;
> > >
> > > --
> > > 2.25.1
> > >
^ permalink raw reply [flat|nested] 18+ messages in thread
* RE: [PATCH] drm/xe/uapi: Add DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY
2025-06-27 8:14 ` Gote, Nitin R
@ 2025-06-27 9:37 ` Upadhyay, Tejas
2025-06-27 17:57 ` Matthew Brost
0 siblings, 1 reply; 18+ messages in thread
From: Upadhyay, Tejas @ 2025-06-27 9:37 UTC (permalink / raw)
To: Gote, Nitin R, Brost, Matthew
Cc: Vivi, Rodrigo, intel-xe@lists.freedesktop.org,
joonas.lahtinen@linux.intel.com, Ghimiray, Himal Prasad
> -----Original Message-----
> From: Gote, Nitin R <nitin.r.gote@intel.com>
> Sent: 27 June 2025 13:44
> To: Brost, Matthew <matthew.brost@intel.com>
> Cc: Vivi, Rodrigo <rodrigo.vivi@intel.com>; Upadhyay, Tejas
> <tejas.upadhyay@intel.com>; intel-xe@lists.freedesktop.org;
> joonas.lahtinen@linux.intel.com; Ghimiray, Himal Prasad
> <himal.prasad.ghimiray@intel.com>
> Subject: RE: [PATCH] drm/xe/uapi: Add
> DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY
>
> Hi Matt,
> >
> > Hi Matt and Rodrigo,
> >
> > > On Wed, Jun 25, 2025 at 03:28:05PM +0530, Nitin Gote wrote:
> > > > Add the DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY device
> > query
> > > flag
> > > > which indicates whether a device supports DIS_NULL_QUERY (Disable
> > > > null anyhit shader query mechanism). The intent is for UMDs to use
> > > > this query and opt-in DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY flag to
> > > > disable null query mechanism for anyhit shader by setting
> > > > DIS_NULL_QUERY bit of RT_CTRL register for Xe2.
> > > >
> > > > v2:
> > > > - Use xe_rtp_match_first_render_or_compute() api to check
> > > > render_or_compute. (Tejas)
> > > > - Validate args->flags (Tejas/Matthew)
> > > > - Add proper kernel-doc for both
> > DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY
> > > > and DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT. (Matthew)
> > >
> > > Matt asked for full spelling of DISABLE, no?!
> >
> > Thank you for clarifying the uAPI naming convention.
> > I will update it.
> >
> > >
> > > Also, where are the UMD patches/merge-requests for this? And their ack?
> > >
> > From the Mesa team (Palli, Tapani) is going to send the corresponding
> > Mesa patch.
> > Meanwhile, I floated this patch.
> >
> > > Thanks,
> > > Rodrigo.
> > >
> > > >
> > > > Signed-off-by: Nitin Gote <nitin.r.gote@intel.com>
> > > > ---
> > > > drivers/gpu/drm/xe/xe_exec_queue.c | 11 ++++++++++-
> > > > drivers/gpu/drm/xe/xe_query.c | 3 ++-
> > > > include/uapi/drm/xe_drm.h | 12 ++++++++++++
> > > > 3 files changed, 24 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c
> > > > b/drivers/gpu/drm/xe/xe_exec_queue.c
> > > > index fee22358cc09..ef8b49d2242a 100644
> > > > --- a/drivers/gpu/drm/xe/xe_exec_queue.c
> > > > +++ b/drivers/gpu/drm/xe/xe_exec_queue.c
> > > > @@ -26,6 +26,9 @@
> > > > #include "xe_trace.h"
> > > > #include "xe_vm.h"
> > > > #include "xe_pxp.h"
> > > > +#include "xe_gt_mcr.h"
> > > > +#include "regs/xe_gt_regs.h"
> > > > +#include "xe_rtp.h"
> > > >
> > > > enum xe_exec_queue_sched_prop {
> > > > XE_EXEC_QUEUE_JOB_TIMEOUT = 0,
> > > > @@ -597,7 +600,8 @@ int xe_exec_queue_create_ioctl(struct
> > > > drm_device
> > > *dev, void *data,
> > > > u32 len;
> > > > int err;
> > > >
> > > > - if (XE_IOCTL_DBG(xe, args->flags &
> > > ~DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT) ||
> > > > + if (XE_IOCTL_DBG(xe, args->flags &
> > > > + ~(DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT |
> > > > +DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY)) ||
> > > > XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1]))
> > > > return -EINVAL;
> > > >
> > > > @@ -693,6 +697,11 @@ int xe_exec_queue_create_ioctl(struct
> > > > drm_device
> > > *dev, void *data,
> > > > }
> > > > }
> > > >
> > > > + if (((GRAPHICS_VER(xe) >= 20) && (GRAPHICS_VER(xe) < 30)) &&
> > > > + (args->flags & DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY) &&
> > > > + xe_rtp_match_first_render_or_compute(q->gt, q->hwe))
> > > > + xe_gt_mcr_multicast_write(q->gt, RT_CTRL,
> DIS_NULL_QUERY);
> > > > +
> >
> > Also, as per Matt's suggestion in rev1, I'm exploring the WA BB
> > program to set this.
> >
>
> If we move this implementation from the exec queue creation time to
> the submission time and write a WW BB program, then this register will be set
> for every exec queue submission.
> Let's say if submission happens 3 times, then register gets written 3 times,
> which seems unnecessary.
>
> So, having implementation in the exec queue create time, the register will be
> updated only once, and we can disable it in the exec queue destroy.
>
> What do you think? Could you please suggest?
Hi Nitin/Matt,
Are we talking below cases,
(if kept in WA_BB) :
User1 --> submits on rcs0 -> register will be updated for rcs0 (User2 will not be affected)
User2--> submits at the same time on rcs1 -> register will be updated for only rcs1 (User1 will not be affected)
(if kept in exec_queue_create/destroy) :
User1 --> creates exec_queue (register is written(not sure on which instance of rcs?) --> submits on rcs0 (User2 will be impacted if used same instance as User1, which isn't possible)
User2--> creates exec_queue (register is written(not sure on which instance of rcs, but for sure not the instance User1 is using?) -> submits at the same time on rcs1 (User1 will be impacted if used same instance as User2, which isn't possible)
If above cases are true then both look same, isn't it? Unless I am missing something.
Tejas
>
> Thanks,
> Nitin
>
> > > > q->xef = xe_file_get(xef);
> > > >
> > > > /* user id alloc must always be last in ioctl to prevent UAF */
> > > > diff --git a/drivers/gpu/drm/xe/xe_query.c
> > > > b/drivers/gpu/drm/xe/xe_query.c index e8e1743dcb1e..c5002b8c9ac0
> > > > 100644
> > > > --- a/drivers/gpu/drm/xe/xe_query.c
> > > > +++ b/drivers/gpu/drm/xe/xe_query.c
> > > > @@ -344,7 +344,8 @@ static int query_config(struct xe_device *xe,
> > > > struct
> > > drm_xe_device_query *query)
> > > > config->info[DRM_XE_QUERY_CONFIG_FLAGS] |=
> > > >
> > > DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR;
> > > > config->info[DRM_XE_QUERY_CONFIG_FLAGS] |=
> > > > - DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY;
> > > > +
> (DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY
> > > |
> > > > +
> > > DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY);
> > > > config->info[DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT] =
> > > > xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K ? SZ_64K :
> > > SZ_4K;
> > > > config->info[DRM_XE_QUERY_CONFIG_VA_BITS] = xe->info.va_bits;
> > > > diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
> > > > index 8e8bbdec8c5c..7c30e707346c 100644
> > > > --- a/include/uapi/drm/xe_drm.h
> > > > +++ b/include/uapi/drm/xe_drm.h
> > > > @@ -397,6 +397,8 @@ struct drm_xe_query_mem_regions {
> > > > * has low latency hint support
> > > > * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR - Flag
> is
> > > set if the
> > > > * device has CPU address mirroring support
> > > > + * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY - Flag is
> set
> > if
> > > the
> > > > + * device has null query support for anyhit shader.
> > > > * - %DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT - Minimal memory
> > > alignment
> > > > * required by this device, typically SZ_4K or SZ_64K
> > > > * - %DRM_XE_QUERY_CONFIG_VA_BITS - Maximum bits of a virtual
> > > > address @@ -415,6 +417,7 @@ struct drm_xe_query_config {
> > > > #define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM (1 << 0)
> > > > #define DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY (1 <<
> > > 1)
> > > > #define DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR
> > > (1 << 2)
> > > > + #define DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY
> (1 <<
> > > 3)
> > > > #define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT 2
> > > > #define DRM_XE_QUERY_CONFIG_VA_BITS 3
> > > > #define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY 4
> > > > @@ -1270,7 +1273,16 @@ struct drm_xe_exec_queue_create {
> > > > /** @vm_id: VM to use for this exec queue */
> > > > __u32 vm_id;
> > > >
> > > > + /** DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY - \
> > > > + * Flag is set if the device has low latency hint support
> > > > + */
> > > > #define DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT (1 << 0)
> > > > +
> > > > + /** DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY - \
> > > > + * flag is use to disable null query check for Anyhit shader
> > > > + */
> > > > +#define DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY (1 << 1)
> > > > +
> > > > /** @flags: flags to use for this exec queue */
> > > > __u32 flags;
> > > >
> > > > --
> > > > 2.25.1
> > > >
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH] drm/xe/uapi: Add DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY
2025-06-27 9:37 ` Upadhyay, Tejas
@ 2025-06-27 17:57 ` Matthew Brost
2025-06-27 18:15 ` Matthew Brost
0 siblings, 1 reply; 18+ messages in thread
From: Matthew Brost @ 2025-06-27 17:57 UTC (permalink / raw)
To: Upadhyay, Tejas
Cc: Gote, Nitin R, Vivi, Rodrigo, intel-xe@lists.freedesktop.org,
joonas.lahtinen@linux.intel.com, Ghimiray, Himal Prasad
On Fri, Jun 27, 2025 at 03:37:34AM -0600, Upadhyay, Tejas wrote:
>
>
> > -----Original Message-----
> > From: Gote, Nitin R <nitin.r.gote@intel.com>
> > Sent: 27 June 2025 13:44
> > To: Brost, Matthew <matthew.brost@intel.com>
> > Cc: Vivi, Rodrigo <rodrigo.vivi@intel.com>; Upadhyay, Tejas
> > <tejas.upadhyay@intel.com>; intel-xe@lists.freedesktop.org;
> > joonas.lahtinen@linux.intel.com; Ghimiray, Himal Prasad
> > <himal.prasad.ghimiray@intel.com>
> > Subject: RE: [PATCH] drm/xe/uapi: Add
> > DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY
> >
> > Hi Matt,
> > >
> > > Hi Matt and Rodrigo,
> > >
> > > > On Wed, Jun 25, 2025 at 03:28:05PM +0530, Nitin Gote wrote:
> > > > > Add the DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY device
> > > query
> > > > flag
> > > > > which indicates whether a device supports DIS_NULL_QUERY (Disable
> > > > > null anyhit shader query mechanism). The intent is for UMDs to use
> > > > > this query and opt-in DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY flag to
> > > > > disable null query mechanism for anyhit shader by setting
> > > > > DIS_NULL_QUERY bit of RT_CTRL register for Xe2.
> > > > >
> > > > > v2:
> > > > > - Use xe_rtp_match_first_render_or_compute() api to check
> > > > > render_or_compute. (Tejas)
> > > > > - Validate args->flags (Tejas/Matthew)
> > > > > - Add proper kernel-doc for both
> > > DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY
> > > > > and DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT. (Matthew)
> > > >
> > > > Matt asked for full spelling of DISABLE, no?!
> > >
> > > Thank you for clarifying the uAPI naming convention.
> > > I will update it.
> > >
> > > >
> > > > Also, where are the UMD patches/merge-requests for this? And their ack?
> > > >
> > > From the Mesa team (Palli, Tapani) is going to send the corresponding
> > > Mesa patch.
> > > Meanwhile, I floated this patch.
> > >
> > > > Thanks,
> > > > Rodrigo.
> > > >
> > > > >
> > > > > Signed-off-by: Nitin Gote <nitin.r.gote@intel.com>
> > > > > ---
> > > > > drivers/gpu/drm/xe/xe_exec_queue.c | 11 ++++++++++-
> > > > > drivers/gpu/drm/xe/xe_query.c | 3 ++-
> > > > > include/uapi/drm/xe_drm.h | 12 ++++++++++++
> > > > > 3 files changed, 24 insertions(+), 2 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c
> > > > > b/drivers/gpu/drm/xe/xe_exec_queue.c
> > > > > index fee22358cc09..ef8b49d2242a 100644
> > > > > --- a/drivers/gpu/drm/xe/xe_exec_queue.c
> > > > > +++ b/drivers/gpu/drm/xe/xe_exec_queue.c
> > > > > @@ -26,6 +26,9 @@
> > > > > #include "xe_trace.h"
> > > > > #include "xe_vm.h"
> > > > > #include "xe_pxp.h"
> > > > > +#include "xe_gt_mcr.h"
> > > > > +#include "regs/xe_gt_regs.h"
> > > > > +#include "xe_rtp.h"
> > > > >
> > > > > enum xe_exec_queue_sched_prop {
> > > > > XE_EXEC_QUEUE_JOB_TIMEOUT = 0,
> > > > > @@ -597,7 +600,8 @@ int xe_exec_queue_create_ioctl(struct
> > > > > drm_device
> > > > *dev, void *data,
> > > > > u32 len;
> > > > > int err;
> > > > >
> > > > > - if (XE_IOCTL_DBG(xe, args->flags &
> > > > ~DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT) ||
> > > > > + if (XE_IOCTL_DBG(xe, args->flags &
> > > > > + ~(DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT |
> > > > > +DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY)) ||
> > > > > XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1]))
> > > > > return -EINVAL;
> > > > >
> > > > > @@ -693,6 +697,11 @@ int xe_exec_queue_create_ioctl(struct
> > > > > drm_device
> > > > *dev, void *data,
> > > > > }
> > > > > }
> > > > >
> > > > > + if (((GRAPHICS_VER(xe) >= 20) && (GRAPHICS_VER(xe) < 30)) &&
> > > > > + (args->flags & DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY) &&
> > > > > + xe_rtp_match_first_render_or_compute(q->gt, q->hwe))
> > > > > + xe_gt_mcr_multicast_write(q->gt, RT_CTRL,
> > DIS_NULL_QUERY);
> > > > > +
> > >
> > > Also, as per Matt's suggestion in rev1, I'm exploring the WA BB
> > > program to set this.
> > >
> >
> > If we move this implementation from the exec queue creation time to
> > the submission time and write a WW BB program, then this register will be set
> > for every exec queue submission.
> > Let's say if submission happens 3 times, then register gets written 3 times,
> > which seems unnecessary.
> >
No, completetly unnecessary, we have been over this. See below.
> > So, having implementation in the exec queue create time, the register will be
> > updated only once, and we can disable it in the exec queue destroy.
> >
> > What do you think? Could you please suggest?
>
> Hi Nitin/Matt,
>
> Are we talking below cases,
>
> (if kept in WA_BB) :
> User1 --> submits on rcs0 -> register will be updated for rcs0 (User2 will not be affected)
> User2--> submits at the same time on rcs1 -> register will be updated for only rcs1 (User1 will not be affected)
>
> (if kept in exec_queue_create/destroy) :
> User1 --> creates exec_queue (register is written(not sure on which instance of rcs?) --> submits on rcs0 (User2 will be impacted if used same instance as User1, which isn't possible)
> User2--> creates exec_queue (register is written(not sure on which instance of rcs, but for sure not the instance User1 is using?) -> submits at the same time on rcs1 (User1 will be impacted if used same instance as User2, which isn't possible)
>
> If above cases are true then both look same, isn't it? Unless I am missing something.
>
Tejas — I'm not really following your examples, but no, writing at exec
queue creation time is not the same as writing a WA BB.
This is a very basic process isolation concept that I would expect all
KMD developers to understand. If not, then please take the time to learn
it — this isn't something I should have to explain repeatedly. A quick
Google search or a query to ChatGPT will explain process isolation quite
well. With just four queries, I got an explanation for this exact
problem, including why this must be part of the context state (i.e., the
WA BB), since work gets switched on the hardware.
Here were my chatgpt queries:
"what is process isolation"
"in a computer chip why can't you set a global register wrt to process
isolation"
"more in the context the register changes behavior of computer chip
rather than data sharing"
"say in the context of kernel submitting work on behalf of a UMD which
changes global register before each submit, why is that a bad idea"
Anyway, let me give an example of why the current implementation will
not work:
Example:
User1 wants DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY set.
User2 wants DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY cleared.
If a global register is modified at exec queue creation time (i.e., it
affects the entire GPU’s settings), then both users cannot have
different behaviors — and we’re now broken.
The only way for User1 and User2 to have different settings is to make
this part of the context state (WA BB), which dynamically modifies the
registers as work from each user is scheduled on the hardware.
Matt
> Tejas
> >
> > Thanks,
> > Nitin
> >
> > > > > q->xef = xe_file_get(xef);
> > > > >
> > > > > /* user id alloc must always be last in ioctl to prevent UAF */
> > > > > diff --git a/drivers/gpu/drm/xe/xe_query.c
> > > > > b/drivers/gpu/drm/xe/xe_query.c index e8e1743dcb1e..c5002b8c9ac0
> > > > > 100644
> > > > > --- a/drivers/gpu/drm/xe/xe_query.c
> > > > > +++ b/drivers/gpu/drm/xe/xe_query.c
> > > > > @@ -344,7 +344,8 @@ static int query_config(struct xe_device *xe,
> > > > > struct
> > > > drm_xe_device_query *query)
> > > > > config->info[DRM_XE_QUERY_CONFIG_FLAGS] |=
> > > > >
> > > > DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR;
> > > > > config->info[DRM_XE_QUERY_CONFIG_FLAGS] |=
> > > > > - DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY;
> > > > > +
> > (DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY
> > > > |
> > > > > +
> > > > DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY);
> > > > > config->info[DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT] =
> > > > > xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K ? SZ_64K :
> > > > SZ_4K;
> > > > > config->info[DRM_XE_QUERY_CONFIG_VA_BITS] = xe->info.va_bits;
> > > > > diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
> > > > > index 8e8bbdec8c5c..7c30e707346c 100644
> > > > > --- a/include/uapi/drm/xe_drm.h
> > > > > +++ b/include/uapi/drm/xe_drm.h
> > > > > @@ -397,6 +397,8 @@ struct drm_xe_query_mem_regions {
> > > > > * has low latency hint support
> > > > > * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR - Flag
> > is
> > > > set if the
> > > > > * device has CPU address mirroring support
> > > > > + * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY - Flag is
> > set
> > > if
> > > > the
> > > > > + * device has null query support for anyhit shader.
> > > > > * - %DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT - Minimal memory
> > > > alignment
> > > > > * required by this device, typically SZ_4K or SZ_64K
> > > > > * - %DRM_XE_QUERY_CONFIG_VA_BITS - Maximum bits of a virtual
> > > > > address @@ -415,6 +417,7 @@ struct drm_xe_query_config {
> > > > > #define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM (1 << 0)
> > > > > #define DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY (1 <<
> > > > 1)
> > > > > #define DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR
> > > > (1 << 2)
> > > > > + #define DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY
> > (1 <<
> > > > 3)
> > > > > #define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT 2
> > > > > #define DRM_XE_QUERY_CONFIG_VA_BITS 3
> > > > > #define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY 4
> > > > > @@ -1270,7 +1273,16 @@ struct drm_xe_exec_queue_create {
> > > > > /** @vm_id: VM to use for this exec queue */
> > > > > __u32 vm_id;
> > > > >
> > > > > + /** DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY - \
> > > > > + * Flag is set if the device has low latency hint support
> > > > > + */
> > > > > #define DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT (1 << 0)
> > > > > +
> > > > > + /** DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY - \
> > > > > + * flag is use to disable null query check for Anyhit shader
> > > > > + */
> > > > > +#define DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY (1 << 1)
> > > > > +
> > > > > /** @flags: flags to use for this exec queue */
> > > > > __u32 flags;
> > > > >
> > > > > --
> > > > > 2.25.1
> > > > >
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH] drm/xe/uapi: Add DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY
2025-06-27 17:57 ` Matthew Brost
@ 2025-06-27 18:15 ` Matthew Brost
2025-07-01 12:07 ` Upadhyay, Tejas
0 siblings, 1 reply; 18+ messages in thread
From: Matthew Brost @ 2025-06-27 18:15 UTC (permalink / raw)
To: Upadhyay, Tejas
Cc: Gote, Nitin R, Vivi, Rodrigo, intel-xe@lists.freedesktop.org,
joonas.lahtinen@linux.intel.com, Ghimiray, Himal Prasad
On Fri, Jun 27, 2025 at 10:57:54AM -0700, Matthew Brost wrote:
Opps, typo.
> On Fri, Jun 27, 2025 at 03:37:34AM -0600, Upadhyay, Tejas wrote:
> >
> >
> > > -----Original Message-----
> > > From: Gote, Nitin R <nitin.r.gote@intel.com>
> > > Sent: 27 June 2025 13:44
> > > To: Brost, Matthew <matthew.brost@intel.com>
> > > Cc: Vivi, Rodrigo <rodrigo.vivi@intel.com>; Upadhyay, Tejas
> > > <tejas.upadhyay@intel.com>; intel-xe@lists.freedesktop.org;
> > > joonas.lahtinen@linux.intel.com; Ghimiray, Himal Prasad
> > > <himal.prasad.ghimiray@intel.com>
> > > Subject: RE: [PATCH] drm/xe/uapi: Add
> > > DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY
> > >
> > > Hi Matt,
> > > >
> > > > Hi Matt and Rodrigo,
> > > >
> > > > > On Wed, Jun 25, 2025 at 03:28:05PM +0530, Nitin Gote wrote:
> > > > > > Add the DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY device
> > > > query
> > > > > flag
> > > > > > which indicates whether a device supports DIS_NULL_QUERY (Disable
> > > > > > null anyhit shader query mechanism). The intent is for UMDs to use
> > > > > > this query and opt-in DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY flag to
> > > > > > disable null query mechanism for anyhit shader by setting
> > > > > > DIS_NULL_QUERY bit of RT_CTRL register for Xe2.
> > > > > >
> > > > > > v2:
> > > > > > - Use xe_rtp_match_first_render_or_compute() api to check
> > > > > > render_or_compute. (Tejas)
> > > > > > - Validate args->flags (Tejas/Matthew)
> > > > > > - Add proper kernel-doc for both
> > > > DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY
> > > > > > and DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT. (Matthew)
> > > > >
> > > > > Matt asked for full spelling of DISABLE, no?!
> > > >
> > > > Thank you for clarifying the uAPI naming convention.
> > > > I will update it.
> > > >
> > > > >
> > > > > Also, where are the UMD patches/merge-requests for this? And their ack?
> > > > >
> > > > From the Mesa team (Palli, Tapani) is going to send the corresponding
> > > > Mesa patch.
> > > > Meanwhile, I floated this patch.
> > > >
> > > > > Thanks,
> > > > > Rodrigo.
> > > > >
> > > > > >
> > > > > > Signed-off-by: Nitin Gote <nitin.r.gote@intel.com>
> > > > > > ---
> > > > > > drivers/gpu/drm/xe/xe_exec_queue.c | 11 ++++++++++-
> > > > > > drivers/gpu/drm/xe/xe_query.c | 3 ++-
> > > > > > include/uapi/drm/xe_drm.h | 12 ++++++++++++
> > > > > > 3 files changed, 24 insertions(+), 2 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c
> > > > > > b/drivers/gpu/drm/xe/xe_exec_queue.c
> > > > > > index fee22358cc09..ef8b49d2242a 100644
> > > > > > --- a/drivers/gpu/drm/xe/xe_exec_queue.c
> > > > > > +++ b/drivers/gpu/drm/xe/xe_exec_queue.c
> > > > > > @@ -26,6 +26,9 @@
> > > > > > #include "xe_trace.h"
> > > > > > #include "xe_vm.h"
> > > > > > #include "xe_pxp.h"
> > > > > > +#include "xe_gt_mcr.h"
> > > > > > +#include "regs/xe_gt_regs.h"
> > > > > > +#include "xe_rtp.h"
> > > > > >
> > > > > > enum xe_exec_queue_sched_prop {
> > > > > > XE_EXEC_QUEUE_JOB_TIMEOUT = 0,
> > > > > > @@ -597,7 +600,8 @@ int xe_exec_queue_create_ioctl(struct
> > > > > > drm_device
> > > > > *dev, void *data,
> > > > > > u32 len;
> > > > > > int err;
> > > > > >
> > > > > > - if (XE_IOCTL_DBG(xe, args->flags &
> > > > > ~DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT) ||
> > > > > > + if (XE_IOCTL_DBG(xe, args->flags &
> > > > > > + ~(DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT |
> > > > > > +DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY)) ||
> > > > > > XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1]))
> > > > > > return -EINVAL;
> > > > > >
> > > > > > @@ -693,6 +697,11 @@ int xe_exec_queue_create_ioctl(struct
> > > > > > drm_device
> > > > > *dev, void *data,
> > > > > > }
> > > > > > }
> > > > > >
> > > > > > + if (((GRAPHICS_VER(xe) >= 20) && (GRAPHICS_VER(xe) < 30)) &&
> > > > > > + (args->flags & DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY) &&
> > > > > > + xe_rtp_match_first_render_or_compute(q->gt, q->hwe))
> > > > > > + xe_gt_mcr_multicast_write(q->gt, RT_CTRL,
> > > DIS_NULL_QUERY);
> > > > > > +
> > > >
> > > > Also, as per Matt's suggestion in rev1, I'm exploring the WA BB
> > > > program to set this.
> > > >
> > >
> > > If we move this implementation from the exec queue creation time to
> > > the submission time and write a WW BB program, then this register will be set
> > > for every exec queue submission.
> > > Let's say if submission happens 3 times, then register gets written 3 times,
> > > which seems unnecessary.
> > >
>
> No, completetly unnecessary, we have been over this. See below.
>
s/unnecessary/necessary
Matt
> > > So, having implementation in the exec queue create time, the register will be
> > > updated only once, and we can disable it in the exec queue destroy.
> > >
> > > What do you think? Could you please suggest?
> >
> > Hi Nitin/Matt,
> >
> > Are we talking below cases,
> >
> > (if kept in WA_BB) :
> > User1 --> submits on rcs0 -> register will be updated for rcs0 (User2 will not be affected)
> > User2--> submits at the same time on rcs1 -> register will be updated for only rcs1 (User1 will not be affected)
> >
> > (if kept in exec_queue_create/destroy) :
> > User1 --> creates exec_queue (register is written(not sure on which instance of rcs?) --> submits on rcs0 (User2 will be impacted if used same instance as User1, which isn't possible)
> > User2--> creates exec_queue (register is written(not sure on which instance of rcs, but for sure not the instance User1 is using?) -> submits at the same time on rcs1 (User1 will be impacted if used same instance as User2, which isn't possible)
> >
> > If above cases are true then both look same, isn't it? Unless I am missing something.
> >
>
> Tejas — I'm not really following your examples, but no, writing at exec
> queue creation time is not the same as writing a WA BB.
>
> This is a very basic process isolation concept that I would expect all
> KMD developers to understand. If not, then please take the time to learn
> it — this isn't something I should have to explain repeatedly. A quick
> Google search or a query to ChatGPT will explain process isolation quite
> well. With just four queries, I got an explanation for this exact
> problem, including why this must be part of the context state (i.e., the
> WA BB), since work gets switched on the hardware.
>
> Here were my chatgpt queries:
>
> "what is process isolation"
>
> "in a computer chip why can't you set a global register wrt to process
> isolation"
>
> "more in the context the register changes behavior of computer chip
> rather than data sharing"
>
> "say in the context of kernel submitting work on behalf of a UMD which
> changes global register before each submit, why is that a bad idea"
>
> Anyway, let me give an example of why the current implementation will
> not work:
>
> Example:
> User1 wants DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY set.
> User2 wants DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY cleared.
>
> If a global register is modified at exec queue creation time (i.e., it
> affects the entire GPU’s settings), then both users cannot have
> different behaviors — and we’re now broken.
>
> The only way for User1 and User2 to have different settings is to make
> this part of the context state (WA BB), which dynamically modifies the
> registers as work from each user is scheduled on the hardware.
>
> Matt
>
> > Tejas
> > >
> > > Thanks,
> > > Nitin
> > >
> > > > > > q->xef = xe_file_get(xef);
> > > > > >
> > > > > > /* user id alloc must always be last in ioctl to prevent UAF */
> > > > > > diff --git a/drivers/gpu/drm/xe/xe_query.c
> > > > > > b/drivers/gpu/drm/xe/xe_query.c index e8e1743dcb1e..c5002b8c9ac0
> > > > > > 100644
> > > > > > --- a/drivers/gpu/drm/xe/xe_query.c
> > > > > > +++ b/drivers/gpu/drm/xe/xe_query.c
> > > > > > @@ -344,7 +344,8 @@ static int query_config(struct xe_device *xe,
> > > > > > struct
> > > > > drm_xe_device_query *query)
> > > > > > config->info[DRM_XE_QUERY_CONFIG_FLAGS] |=
> > > > > >
> > > > > DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR;
> > > > > > config->info[DRM_XE_QUERY_CONFIG_FLAGS] |=
> > > > > > - DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY;
> > > > > > +
> > > (DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY
> > > > > |
> > > > > > +
> > > > > DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY);
> > > > > > config->info[DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT] =
> > > > > > xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K ? SZ_64K :
> > > > > SZ_4K;
> > > > > > config->info[DRM_XE_QUERY_CONFIG_VA_BITS] = xe->info.va_bits;
> > > > > > diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
> > > > > > index 8e8bbdec8c5c..7c30e707346c 100644
> > > > > > --- a/include/uapi/drm/xe_drm.h
> > > > > > +++ b/include/uapi/drm/xe_drm.h
> > > > > > @@ -397,6 +397,8 @@ struct drm_xe_query_mem_regions {
> > > > > > * has low latency hint support
> > > > > > * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR - Flag
> > > is
> > > > > set if the
> > > > > > * device has CPU address mirroring support
> > > > > > + * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY - Flag is
> > > set
> > > > if
> > > > > the
> > > > > > + * device has null query support for anyhit shader.
> > > > > > * - %DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT - Minimal memory
> > > > > alignment
> > > > > > * required by this device, typically SZ_4K or SZ_64K
> > > > > > * - %DRM_XE_QUERY_CONFIG_VA_BITS - Maximum bits of a virtual
> > > > > > address @@ -415,6 +417,7 @@ struct drm_xe_query_config {
> > > > > > #define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM (1 << 0)
> > > > > > #define DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY (1 <<
> > > > > 1)
> > > > > > #define DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR
> > > > > (1 << 2)
> > > > > > + #define DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY
> > > (1 <<
> > > > > 3)
> > > > > > #define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT 2
> > > > > > #define DRM_XE_QUERY_CONFIG_VA_BITS 3
> > > > > > #define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY 4
> > > > > > @@ -1270,7 +1273,16 @@ struct drm_xe_exec_queue_create {
> > > > > > /** @vm_id: VM to use for this exec queue */
> > > > > > __u32 vm_id;
> > > > > >
> > > > > > + /** DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY - \
> > > > > > + * Flag is set if the device has low latency hint support
> > > > > > + */
> > > > > > #define DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT (1 << 0)
> > > > > > +
> > > > > > + /** DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY - \
> > > > > > + * flag is use to disable null query check for Anyhit shader
> > > > > > + */
> > > > > > +#define DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY (1 << 1)
> > > > > > +
> > > > > > /** @flags: flags to use for this exec queue */
> > > > > > __u32 flags;
> > > > > >
> > > > > > --
> > > > > > 2.25.1
> > > > > >
^ permalink raw reply [flat|nested] 18+ messages in thread
* RE: [PATCH] drm/xe/uapi: Add DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY
2025-06-27 18:15 ` Matthew Brost
@ 2025-07-01 12:07 ` Upadhyay, Tejas
2025-07-01 14:06 ` Gote, Nitin R
0 siblings, 1 reply; 18+ messages in thread
From: Upadhyay, Tejas @ 2025-07-01 12:07 UTC (permalink / raw)
To: Brost, Matthew
Cc: Gote, Nitin R, Vivi, Rodrigo, intel-xe@lists.freedesktop.org,
joonas.lahtinen@linux.intel.com, Ghimiray, Himal Prasad
> -----Original Message-----
> From: Brost, Matthew <matthew.brost@intel.com>
> Sent: 27 June 2025 23:45
> To: Upadhyay, Tejas <tejas.upadhyay@intel.com>
> Cc: Gote, Nitin R <nitin.r.gote@intel.com>; Vivi, Rodrigo
> <rodrigo.vivi@intel.com>; intel-xe@lists.freedesktop.org;
> joonas.lahtinen@linux.intel.com; Ghimiray, Himal Prasad
> <himal.prasad.ghimiray@intel.com>
> Subject: Re: [PATCH] drm/xe/uapi: Add
> DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY
>
> On Fri, Jun 27, 2025 at 10:57:54AM -0700, Matthew Brost wrote:
>
> Opps, typo.
>
> > On Fri, Jun 27, 2025 at 03:37:34AM -0600, Upadhyay, Tejas wrote:
> > >
> > >
> > > > -----Original Message-----
> > > > From: Gote, Nitin R <nitin.r.gote@intel.com>
> > > > Sent: 27 June 2025 13:44
> > > > To: Brost, Matthew <matthew.brost@intel.com>
> > > > Cc: Vivi, Rodrigo <rodrigo.vivi@intel.com>; Upadhyay, Tejas
> > > > <tejas.upadhyay@intel.com>; intel-xe@lists.freedesktop.org;
> > > > joonas.lahtinen@linux.intel.com; Ghimiray, Himal Prasad
> > > > <himal.prasad.ghimiray@intel.com>
> > > > Subject: RE: [PATCH] drm/xe/uapi: Add
> > > > DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY
> > > >
> > > > Hi Matt,
> > > > >
> > > > > Hi Matt and Rodrigo,
> > > > >
> > > > > > On Wed, Jun 25, 2025 at 03:28:05PM +0530, Nitin Gote wrote:
> > > > > > > Add the DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY
> device
> > > > > query
> > > > > > flag
> > > > > > > which indicates whether a device supports DIS_NULL_QUERY
> > > > > > > (Disable null anyhit shader query mechanism). The intent is
> > > > > > > for UMDs to use this query and opt-in
> > > > > > > DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY flag to disable null query
> > > > > > > mechanism for anyhit shader by setting DIS_NULL_QUERY bit of
> RT_CTRL register for Xe2.
> > > > > > >
> > > > > > > v2:
> > > > > > > - Use xe_rtp_match_first_render_or_compute() api to check
> > > > > > > render_or_compute. (Tejas)
> > > > > > > - Validate args->flags (Tejas/Matthew)
> > > > > > > - Add proper kernel-doc for both
> > > > > DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY
> > > > > > > and DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT. (Matthew)
> > > > > >
> > > > > > Matt asked for full spelling of DISABLE, no?!
> > > > >
> > > > > Thank you for clarifying the uAPI naming convention.
> > > > > I will update it.
> > > > >
> > > > > >
> > > > > > Also, where are the UMD patches/merge-requests for this? And their
> ack?
> > > > > >
> > > > > From the Mesa team (Palli, Tapani) is going to send the
> > > > > corresponding Mesa patch.
> > > > > Meanwhile, I floated this patch.
> > > > >
> > > > > > Thanks,
> > > > > > Rodrigo.
> > > > > >
> > > > > > >
> > > > > > > Signed-off-by: Nitin Gote <nitin.r.gote@intel.com>
> > > > > > > ---
> > > > > > > drivers/gpu/drm/xe/xe_exec_queue.c | 11 ++++++++++-
> > > > > > > drivers/gpu/drm/xe/xe_query.c | 3 ++-
> > > > > > > include/uapi/drm/xe_drm.h | 12 ++++++++++++
> > > > > > > 3 files changed, 24 insertions(+), 2 deletions(-)
> > > > > > >
> > > > > > > diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c
> > > > > > > b/drivers/gpu/drm/xe/xe_exec_queue.c
> > > > > > > index fee22358cc09..ef8b49d2242a 100644
> > > > > > > --- a/drivers/gpu/drm/xe/xe_exec_queue.c
> > > > > > > +++ b/drivers/gpu/drm/xe/xe_exec_queue.c
> > > > > > > @@ -26,6 +26,9 @@
> > > > > > > #include "xe_trace.h"
> > > > > > > #include "xe_vm.h"
> > > > > > > #include "xe_pxp.h"
> > > > > > > +#include "xe_gt_mcr.h"
> > > > > > > +#include "regs/xe_gt_regs.h"
> > > > > > > +#include "xe_rtp.h"
> > > > > > >
> > > > > > > enum xe_exec_queue_sched_prop {
> > > > > > > XE_EXEC_QUEUE_JOB_TIMEOUT = 0, @@ -597,7 +600,8 @@
> int
> > > > > > > xe_exec_queue_create_ioctl(struct drm_device
> > > > > > *dev, void *data,
> > > > > > > u32 len;
> > > > > > > int err;
> > > > > > >
> > > > > > > - if (XE_IOCTL_DBG(xe, args->flags &
> > > > > > ~DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT) ||
> > > > > > > + if (XE_IOCTL_DBG(xe, args->flags &
> > > > > > > + ~(DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT |
> > > > > > > +DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY)) ||
> > > > > > > XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1]))
> > > > > > > return -EINVAL;
> > > > > > >
> > > > > > > @@ -693,6 +697,11 @@ int xe_exec_queue_create_ioctl(struct
> > > > > > > drm_device
> > > > > > *dev, void *data,
> > > > > > > }
> > > > > > > }
> > > > > > >
> > > > > > > + if (((GRAPHICS_VER(xe) >= 20) && (GRAPHICS_VER(xe) < 30))
> &&
> > > > > > > + (args->flags & DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY)
> &&
> > > > > > > + xe_rtp_match_first_render_or_compute(q->gt, q->hwe))
> > > > > > > + xe_gt_mcr_multicast_write(q->gt, RT_CTRL,
> > > > DIS_NULL_QUERY);
> > > > > > > +
> > > > >
> > > > > Also, as per Matt's suggestion in rev1, I'm exploring the WA BB
> > > > > program to set this.
> > > > >
> > > >
> > > > If we move this implementation from the exec queue creation time
> > > > to the submission time and write a WW BB program, then this
> > > > register will be set for every exec queue submission.
> > > > Let's say if submission happens 3 times, then register gets
> > > > written 3 times, which seems unnecessary.
> > > >
> >
> > No, completetly unnecessary, we have been over this. See below.
> >
>
> s/unnecessary/necessary
>
> Matt
>
> > > > So, having implementation in the exec queue create time, the
> > > > register will be updated only once, and we can disable it in the exec queue
> destroy.
> > > >
> > > > What do you think? Could you please suggest?
> > >
> > > Hi Nitin/Matt,
> > >
> > > Are we talking below cases,
> > >
> > > (if kept in WA_BB) :
> > > User1 --> submits on rcs0 -> register will be updated for rcs0
> > > (User2 will not be affected)
> > > User2--> submits at the same time on rcs1 -> register will be
> > > User2--> updated for only rcs1 (User1 will not be affected)
> > >
> > > (if kept in exec_queue_create/destroy) :
> > > User1 --> creates exec_queue (register is written(not sure on which
> > > instance of rcs?) --> submits on rcs0 (User2 will be impacted if
> > > used same instance as User1, which isn't possible)
> > > User2--> creates exec_queue (register is written(not sure on which
> > > User2--> instance of rcs, but for sure not the instance User1 is
> > > User2--> using?) -> submits at the same time on rcs1 (User1 will be
> > > User2--> impacted if used same instance as User2, which isn't
> > > User2--> possible)
> > >
> > > If above cases are true then both look same, isn't it? Unless I am missing
> something.
> > >
> >
> > Tejas — I'm not really following your examples, but no, writing at
> > exec queue creation time is not the same as writing a WA BB.
> >
> > This is a very basic process isolation concept that I would expect all
> > KMD developers to understand. If not, then please take the time to
> > learn it — this isn't something I should have to explain repeatedly. A
> > quick Google search or a query to ChatGPT will explain process
> > isolation quite well. With just four queries, I got an explanation for
> > this exact problem, including why this must be part of the context
> > state (i.e., the WA BB), since work gets switched on the hardware.
> >
> > Here were my chatgpt queries:
> >
> > "what is process isolation"
> >
> > "in a computer chip why can't you set a global register wrt to process
> > isolation"
> >
> > "more in the context the register changes behavior of computer chip
> > rather than data sharing"
> >
> > "say in the context of kernel submitting work on behalf of a UMD which
> > changes global register before each submit, why is that a bad idea"
> >
> > Anyway, let me give an example of why the current implementation will
> > not work:
> >
> > Example:
> > User1 wants DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY set.
> > User2 wants DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY
> cleared.
> >
> > If a global register is modified at exec queue creation time (i.e., it
> > affects the entire GPU’s settings), then both users cannot have
> > different behaviors — and we’re now broken.
> >
> > The only way for User1 and User2 to have different settings is to make
> > this part of the context state (WA BB), which dynamically modifies the
> > registers as work from each user is scheduled on the hardware.
Ok, I think I missed point here, as it is engine register, When UMD submits work any engine instance will be selected for submission at the very same time we will change the reg value on that instance, so for that period that instance will be exclusively configured for specific user.
I get it.
Tejas
> >
> > Matt
> >
> > > Tejas
> > > >
> > > > Thanks,
> > > > Nitin
> > > >
> > > > > > > q->xef = xe_file_get(xef);
> > > > > > >
> > > > > > > /* user id alloc must always be last in ioctl to prevent
> > > > > > > UAF */ diff --git a/drivers/gpu/drm/xe/xe_query.c
> > > > > > > b/drivers/gpu/drm/xe/xe_query.c index
> > > > > > > e8e1743dcb1e..c5002b8c9ac0
> > > > > > > 100644
> > > > > > > --- a/drivers/gpu/drm/xe/xe_query.c
> > > > > > > +++ b/drivers/gpu/drm/xe/xe_query.c
> > > > > > > @@ -344,7 +344,8 @@ static int query_config(struct xe_device
> > > > > > > *xe, struct
> > > > > > drm_xe_device_query *query)
> > > > > > > config->info[DRM_XE_QUERY_CONFIG_FLAGS] |=
> > > > > > >
> > > > > > DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR;
> > > > > > > config->info[DRM_XE_QUERY_CONFIG_FLAGS] |=
> > > > > > > -
> DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY;
> > > > > > > +
> > > > (DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY
> > > > > > |
> > > > > > > +
> > > > > > DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY);
> > > > > > > config->info[DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT] =
> > > > > > > xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K ?
> SZ_64K :
> > > > > > SZ_4K;
> > > > > > > config->info[DRM_XE_QUERY_CONFIG_VA_BITS] =
> > > > > > > xe->info.va_bits; diff --git a/include/uapi/drm/xe_drm.h
> > > > > > > b/include/uapi/drm/xe_drm.h index 8e8bbdec8c5c..7c30e707346c
> > > > > > > 100644
> > > > > > > --- a/include/uapi/drm/xe_drm.h
> > > > > > > +++ b/include/uapi/drm/xe_drm.h
> > > > > > > @@ -397,6 +397,8 @@ struct drm_xe_query_mem_regions {
> > > > > > > * has low latency hint support
> > > > > > > * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR
> - Flag
> > > > is
> > > > > > set if the
> > > > > > > * device has CPU address mirroring support
> > > > > > > + * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY -
> Flag is
> > > > set
> > > > > if
> > > > > > the
> > > > > > > + * device has null query support for anyhit shader.
> > > > > > > * - %DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT - Minimal
> memory
> > > > > > alignment
> > > > > > > * required by this device, typically SZ_4K or SZ_64K
> > > > > > > * - %DRM_XE_QUERY_CONFIG_VA_BITS - Maximum bits of a
> > > > > > > virtual address @@ -415,6 +417,7 @@ struct drm_xe_query_config
> {
> > > > > > > #define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM (1 <<
> 0)
> > > > > > > #define DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY
> (1 <<
> > > > > > 1)
> > > > > > > #define
> DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR
> > > > > > (1 << 2)
> > > > > > > + #define
> DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY
> > > > (1 <<
> > > > > > 3)
> > > > > > > #define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT
> 2
> > > > > > > #define DRM_XE_QUERY_CONFIG_VA_BITS 3
> > > > > > > #define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY
> 4
> > > > > > > @@ -1270,7 +1273,16 @@ struct drm_xe_exec_queue_create {
> > > > > > > /** @vm_id: VM to use for this exec queue */
> > > > > > > __u32 vm_id;
> > > > > > >
> > > > > > > + /** DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY - \
> > > > > > > + * Flag is set if the device has low latency hint support
> > > > > > > + */
> > > > > > > #define DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT (1 <<
> 0)
> > > > > > > +
> > > > > > > + /** DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY - \
> > > > > > > + * flag is use to disable null query check for Anyhit shader
> > > > > > > + */
> > > > > > > +#define DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY (1 << 1)
> > > > > > > +
> > > > > > > /** @flags: flags to use for this exec queue */
> > > > > > > __u32 flags;
> > > > > > >
> > > > > > > --
> > > > > > > 2.25.1
> > > > > > >
^ permalink raw reply [flat|nested] 18+ messages in thread
* RE: [PATCH] drm/xe/uapi: Add DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY
2025-07-01 12:07 ` Upadhyay, Tejas
@ 2025-07-01 14:06 ` Gote, Nitin R
2025-07-01 16:26 ` Matthew Brost
0 siblings, 1 reply; 18+ messages in thread
From: Gote, Nitin R @ 2025-07-01 14:06 UTC (permalink / raw)
To: Upadhyay, Tejas, Brost, Matthew
Cc: Vivi, Rodrigo, intel-xe@lists.freedesktop.org,
joonas.lahtinen@linux.intel.com, Ghimiray, Himal Prasad
> -----Original Message-----
> From: Upadhyay, Tejas <tejas.upadhyay@intel.com>
> Sent: Tuesday, July 1, 2025 5:38 PM
> To: Brost, Matthew <matthew.brost@intel.com>
> Cc: Gote, Nitin R <nitin.r.gote@intel.com>; Vivi, Rodrigo <rodrigo.vivi@intel.com>;
> intel-xe@lists.freedesktop.org; joonas.lahtinen@linux.intel.com; Ghimiray, Himal
> Prasad <himal.prasad.ghimiray@intel.com>
> Subject: RE: [PATCH] drm/xe/uapi: Add
> DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY
>
>
>
> > -----Original Message-----
> > From: Brost, Matthew <matthew.brost@intel.com>
> > Sent: 27 June 2025 23:45
> > To: Upadhyay, Tejas <tejas.upadhyay@intel.com>
> > Cc: Gote, Nitin R <nitin.r.gote@intel.com>; Vivi, Rodrigo
> > <rodrigo.vivi@intel.com>; intel-xe@lists.freedesktop.org;
> > joonas.lahtinen@linux.intel.com; Ghimiray, Himal Prasad
> > <himal.prasad.ghimiray@intel.com>
> > Subject: Re: [PATCH] drm/xe/uapi: Add
> > DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY
> >
> > On Fri, Jun 27, 2025 at 10:57:54AM -0700, Matthew Brost wrote:
> >
> > Opps, typo.
> >
> > > On Fri, Jun 27, 2025 at 03:37:34AM -0600, Upadhyay, Tejas wrote:
> > > >
> > > >
> > > > > -----Original Message-----
> > > > > From: Gote, Nitin R <nitin.r.gote@intel.com>
> > > > > Sent: 27 June 2025 13:44
> > > > > To: Brost, Matthew <matthew.brost@intel.com>
> > > > > Cc: Vivi, Rodrigo <rodrigo.vivi@intel.com>; Upadhyay, Tejas
> > > > > <tejas.upadhyay@intel.com>; intel-xe@lists.freedesktop.org;
> > > > > joonas.lahtinen@linux.intel.com; Ghimiray, Himal Prasad
> > > > > <himal.prasad.ghimiray@intel.com>
> > > > > Subject: RE: [PATCH] drm/xe/uapi: Add
> > > > > DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY
> > > > >
> > > > > Hi Matt,
> > > > > >
> > > > > > Hi Matt and Rodrigo,
> > > > > >
> > > > > > > On Wed, Jun 25, 2025 at 03:28:05PM +0530, Nitin Gote wrote:
> > > > > > > > Add the DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY
> > device
> > > > > > query
> > > > > > > flag
> > > > > > > > which indicates whether a device supports DIS_NULL_QUERY
> > > > > > > > (Disable null anyhit shader query mechanism). The intent
> > > > > > > > is for UMDs to use this query and opt-in
> > > > > > > > DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY flag to disable null
> > > > > > > > query mechanism for anyhit shader by setting
> > > > > > > > DIS_NULL_QUERY bit of
> > RT_CTRL register for Xe2.
> > > > > > > >
> > > > > > > > v2:
> > > > > > > > - Use xe_rtp_match_first_render_or_compute() api to check
> > > > > > > > render_or_compute. (Tejas)
> > > > > > > > - Validate args->flags (Tejas/Matthew)
> > > > > > > > - Add proper kernel-doc for both
> > > > > > DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY
> > > > > > > > and DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT. (Matthew)
> > > > > > >
> > > > > > > Matt asked for full spelling of DISABLE, no?!
> > > > > >
> > > > > > Thank you for clarifying the uAPI naming convention.
> > > > > > I will update it.
> > > > > >
> > > > > > >
> > > > > > > Also, where are the UMD patches/merge-requests for this? And
> > > > > > > their
> > ack?
> > > > > > >
> > > > > > From the Mesa team (Palli, Tapani) is going to send the
> > > > > > corresponding Mesa patch.
> > > > > > Meanwhile, I floated this patch.
> > > > > >
> > > > > > > Thanks,
> > > > > > > Rodrigo.
> > > > > > >
> > > > > > > >
> > > > > > > > Signed-off-by: Nitin Gote <nitin.r.gote@intel.com>
> > > > > > > > ---
> > > > > > > > drivers/gpu/drm/xe/xe_exec_queue.c | 11 ++++++++++-
> > > > > > > > drivers/gpu/drm/xe/xe_query.c | 3 ++-
> > > > > > > > include/uapi/drm/xe_drm.h | 12 ++++++++++++
> > > > > > > > 3 files changed, 24 insertions(+), 2 deletions(-)
> > > > > > > >
> > > > > > > > diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c
> > > > > > > > b/drivers/gpu/drm/xe/xe_exec_queue.c
> > > > > > > > index fee22358cc09..ef8b49d2242a 100644
> > > > > > > > --- a/drivers/gpu/drm/xe/xe_exec_queue.c
> > > > > > > > +++ b/drivers/gpu/drm/xe/xe_exec_queue.c
> > > > > > > > @@ -26,6 +26,9 @@
> > > > > > > > #include "xe_trace.h"
> > > > > > > > #include "xe_vm.h"
> > > > > > > > #include "xe_pxp.h"
> > > > > > > > +#include "xe_gt_mcr.h"
> > > > > > > > +#include "regs/xe_gt_regs.h"
> > > > > > > > +#include "xe_rtp.h"
> > > > > > > >
> > > > > > > > enum xe_exec_queue_sched_prop {
> > > > > > > > XE_EXEC_QUEUE_JOB_TIMEOUT = 0, @@ -597,7 +600,8 @@
> > int
> > > > > > > > xe_exec_queue_create_ioctl(struct drm_device
> > > > > > > *dev, void *data,
> > > > > > > > u32 len;
> > > > > > > > int err;
> > > > > > > >
> > > > > > > > - if (XE_IOCTL_DBG(xe, args->flags &
> > > > > > > ~DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT) ||
> > > > > > > > + if (XE_IOCTL_DBG(xe, args->flags &
> > > > > > > > + ~(DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT |
> > > > > > > > +DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY)) ||
> > > > > > > > XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1]))
> > > > > > > > return -EINVAL;
> > > > > > > >
> > > > > > > > @@ -693,6 +697,11 @@ int xe_exec_queue_create_ioctl(struct
> > > > > > > > drm_device
> > > > > > > *dev, void *data,
> > > > > > > > }
> > > > > > > > }
> > > > > > > >
> > > > > > > > + if (((GRAPHICS_VER(xe) >= 20) && (GRAPHICS_VER(xe) <
> > > > > > > > +30))
> > &&
> > > > > > > > + (args->flags & DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY)
> > &&
> > > > > > > > + xe_rtp_match_first_render_or_compute(q->gt, q->hwe))
> > > > > > > > + xe_gt_mcr_multicast_write(q->gt, RT_CTRL,
> > > > > DIS_NULL_QUERY);
> > > > > > > > +
> > > > > >
> > > > > > Also, as per Matt's suggestion in rev1, I'm exploring the WA
> > > > > > BB program to set this.
> > > > > >
> > > > >
> > > > > If we move this implementation from the exec queue creation time
> > > > > to the submission time and write a WW BB program, then this
> > > > > register will be set for every exec queue submission.
> > > > > Let's say if submission happens 3 times, then register gets
> > > > > written 3 times, which seems unnecessary.
> > > > >
> > >
> > > No, completetly unnecessary, we have been over this. See below.
> > >
> >
> > s/unnecessary/necessary
> >
> > Matt
> >
> > > > > So, having implementation in the exec queue create time, the
> > > > > register will be updated only once, and we can disable it in the
> > > > > exec queue
> > destroy.
> > > > >
> > > > > What do you think? Could you please suggest?
> > > >
> > > > Hi Nitin/Matt,
> > > >
> > > > Are we talking below cases,
> > > >
> > > > (if kept in WA_BB) :
> > > > User1 --> submits on rcs0 -> register will be updated for rcs0
> > > > (User2 will not be affected)
> > > > User2--> submits at the same time on rcs1 -> register will be
> > > > User2--> updated for only rcs1 (User1 will not be affected)
> > > >
> > > > (if kept in exec_queue_create/destroy) :
> > > > User1 --> creates exec_queue (register is written(not sure on
> > > > which instance of rcs?) --> submits on rcs0 (User2 will be
> > > > impacted if used same instance as User1, which isn't possible)
> > > > User2--> creates exec_queue (register is written(not sure on which
> > > > User2--> instance of rcs, but for sure not the instance User1 is
> > > > User2--> using?) -> submits at the same time on rcs1 (User1 will
> > > > User2--> be impacted if used same instance as User2, which isn't
> > > > User2--> possible)
> > > >
> > > > If above cases are true then both look same, isn't it? Unless I am
> > > > missing
> > something.
> > > >
> > >
> > > Tejas — I'm not really following your examples, but no, writing at
> > > exec queue creation time is not the same as writing a WA BB.
> > >
> > > This is a very basic process isolation concept that I would expect
> > > all KMD developers to understand. If not, then please take the time
> > > to learn it — this isn't something I should have to explain
> > > repeatedly. A quick Google search or a query to ChatGPT will explain
> > > process isolation quite well. With just four queries, I got an
> > > explanation for this exact problem, including why this must be part
> > > of the context state (i.e., the WA BB), since work gets switched on the
> hardware.
> > >
> > > Here were my chatgpt queries:
> > >
> > > "what is process isolation"
> > >
> > > "in a computer chip why can't you set a global register wrt to
> > > process isolation"
> > >
> > > "more in the context the register changes behavior of computer chip
> > > rather than data sharing"
> > >
> > > "say in the context of kernel submitting work on behalf of a UMD
> > > which changes global register before each submit, why is that a bad idea"
> > >
> > > Anyway, let me give an example of why the current implementation
> > > will not work:
> > >
> > > Example:
> > > User1 wants DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY set.
> > > User2 wants DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY
> > cleared.
> > >
> > > If a global register is modified at exec queue creation time (i.e.,
> > > it affects the entire GPU’s settings), then both users cannot have
> > > different behaviors — and we’re now broken.
> > >
> > > The only way for User1 and User2 to have different settings is to
> > > make this part of the context state (WA BB), which dynamically
> > > modifies the registers as work from each user is scheduled on the hardware.
>
> Ok, I think I missed point here, as it is engine register, When UMD submits work
> any engine instance will be selected for submission at the very same time we will
> change the reg value on that instance, so for that period that instance will be
> exclusively configured for specific user.
>
> I get it.
>
> Tejas
Thank you, Tejas and Matt.
I'm moving this to WA BB.
- Nitin
> > >
> > > Matt
> > >
> > > > Tejas
> > > > >
> > > > > Thanks,
> > > > > Nitin
> > > > >
> > > > > > > > q->xef = xe_file_get(xef);
> > > > > > > >
> > > > > > > > /* user id alloc must always be last in ioctl to prevent
> > > > > > > > UAF */ diff --git a/drivers/gpu/drm/xe/xe_query.c
> > > > > > > > b/drivers/gpu/drm/xe/xe_query.c index
> > > > > > > > e8e1743dcb1e..c5002b8c9ac0
> > > > > > > > 100644
> > > > > > > > --- a/drivers/gpu/drm/xe/xe_query.c
> > > > > > > > +++ b/drivers/gpu/drm/xe/xe_query.c
> > > > > > > > @@ -344,7 +344,8 @@ static int query_config(struct
> > > > > > > > xe_device *xe, struct
> > > > > > > drm_xe_device_query *query)
> > > > > > > > config->info[DRM_XE_QUERY_CONFIG_FLAGS] |=
> > > > > > > >
> > > > > > > DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR;
> > > > > > > > config->info[DRM_XE_QUERY_CONFIG_FLAGS] |=
> > > > > > > > -
> > DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY;
> > > > > > > > +
> > > > > (DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY
> > > > > > > |
> > > > > > > > +
> > > > > > > DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY);
> > > > > > > > config->info[DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT] =
> > > > > > > > xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K ?
> > SZ_64K :
> > > > > > > SZ_4K;
> > > > > > > > config->info[DRM_XE_QUERY_CONFIG_VA_BITS] =
> > > > > > > > xe->info.va_bits; diff --git a/include/uapi/drm/xe_drm.h
> > > > > > > > b/include/uapi/drm/xe_drm.h index
> > > > > > > > 8e8bbdec8c5c..7c30e707346c
> > > > > > > > 100644
> > > > > > > > --- a/include/uapi/drm/xe_drm.h
> > > > > > > > +++ b/include/uapi/drm/xe_drm.h
> > > > > > > > @@ -397,6 +397,8 @@ struct drm_xe_query_mem_regions {
> > > > > > > > * has low latency hint support
> > > > > > > > * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR
> > - Flag
> > > > > is
> > > > > > > set if the
> > > > > > > > * device has CPU address mirroring support
> > > > > > > > + * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY -
> > Flag is
> > > > > set
> > > > > > if
> > > > > > > the
> > > > > > > > + * device has null query support for anyhit shader.
> > > > > > > > * - %DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT - Minimal
> > memory
> > > > > > > alignment
> > > > > > > > * required by this device, typically SZ_4K or SZ_64K
> > > > > > > > * - %DRM_XE_QUERY_CONFIG_VA_BITS - Maximum bits of a
> > > > > > > > virtual address @@ -415,6 +417,7 @@ struct
> > > > > > > > drm_xe_query_config
> > {
> > > > > > > > #define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM (1 <<
> > 0)
> > > > > > > > #define DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY
> > (1 <<
> > > > > > > 1)
> > > > > > > > #define
> > DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR
> > > > > > > (1 << 2)
> > > > > > > > + #define
> > DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY
> > > > > (1 <<
> > > > > > > 3)
> > > > > > > > #define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT
> > 2
> > > > > > > > #define DRM_XE_QUERY_CONFIG_VA_BITS 3
> > > > > > > > #define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY
> > 4
> > > > > > > > @@ -1270,7 +1273,16 @@ struct drm_xe_exec_queue_create {
> > > > > > > > /** @vm_id: VM to use for this exec queue */
> > > > > > > > __u32 vm_id;
> > > > > > > >
> > > > > > > > + /** DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY - \
> > > > > > > > + * Flag is set if the device has low latency hint support
> > > > > > > > + */
> > > > > > > > #define DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT (1 <<
> > 0)
> > > > > > > > +
> > > > > > > > + /** DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY - \
> > > > > > > > + * flag is use to disable null query check for Anyhit shader
> > > > > > > > + */
> > > > > > > > +#define DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY (1 << 1)
> > > > > > > > +
> > > > > > > > /** @flags: flags to use for this exec queue */
> > > > > > > > __u32 flags;
> > > > > > > >
> > > > > > > > --
> > > > > > > > 2.25.1
> > > > > > > >
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH] drm/xe/uapi: Add DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY
2025-07-01 14:06 ` Gote, Nitin R
@ 2025-07-01 16:26 ` Matthew Brost
0 siblings, 0 replies; 18+ messages in thread
From: Matthew Brost @ 2025-07-01 16:26 UTC (permalink / raw)
To: Gote, Nitin R
Cc: Upadhyay, Tejas, Vivi, Rodrigo, intel-xe@lists.freedesktop.org,
joonas.lahtinen@linux.intel.com, Ghimiray, Himal Prasad
On Tue, Jul 01, 2025 at 08:06:16AM -0600, Gote, Nitin R wrote:
>
> > -----Original Message-----
> > From: Upadhyay, Tejas <tejas.upadhyay@intel.com>
> > Sent: Tuesday, July 1, 2025 5:38 PM
> > To: Brost, Matthew <matthew.brost@intel.com>
> > Cc: Gote, Nitin R <nitin.r.gote@intel.com>; Vivi, Rodrigo <rodrigo.vivi@intel.com>;
> > intel-xe@lists.freedesktop.org; joonas.lahtinen@linux.intel.com; Ghimiray, Himal
> > Prasad <himal.prasad.ghimiray@intel.com>
> > Subject: RE: [PATCH] drm/xe/uapi: Add
> > DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY
> >
> >
> >
> > > -----Original Message-----
> > > From: Brost, Matthew <matthew.brost@intel.com>
> > > Sent: 27 June 2025 23:45
> > > To: Upadhyay, Tejas <tejas.upadhyay@intel.com>
> > > Cc: Gote, Nitin R <nitin.r.gote@intel.com>; Vivi, Rodrigo
> > > <rodrigo.vivi@intel.com>; intel-xe@lists.freedesktop.org;
> > > joonas.lahtinen@linux.intel.com; Ghimiray, Himal Prasad
> > > <himal.prasad.ghimiray@intel.com>
> > > Subject: Re: [PATCH] drm/xe/uapi: Add
> > > DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY
> > >
> > > On Fri, Jun 27, 2025 at 10:57:54AM -0700, Matthew Brost wrote:
> > >
> > > Opps, typo.
> > >
> > > > On Fri, Jun 27, 2025 at 03:37:34AM -0600, Upadhyay, Tejas wrote:
> > > > >
> > > > >
> > > > > > -----Original Message-----
> > > > > > From: Gote, Nitin R <nitin.r.gote@intel.com>
> > > > > > Sent: 27 June 2025 13:44
> > > > > > To: Brost, Matthew <matthew.brost@intel.com>
> > > > > > Cc: Vivi, Rodrigo <rodrigo.vivi@intel.com>; Upadhyay, Tejas
> > > > > > <tejas.upadhyay@intel.com>; intel-xe@lists.freedesktop.org;
> > > > > > joonas.lahtinen@linux.intel.com; Ghimiray, Himal Prasad
> > > > > > <himal.prasad.ghimiray@intel.com>
> > > > > > Subject: RE: [PATCH] drm/xe/uapi: Add
> > > > > > DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY
> > > > > >
> > > > > > Hi Matt,
> > > > > > >
> > > > > > > Hi Matt and Rodrigo,
> > > > > > >
> > > > > > > > On Wed, Jun 25, 2025 at 03:28:05PM +0530, Nitin Gote wrote:
> > > > > > > > > Add the DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY
> > > device
> > > > > > > query
> > > > > > > > flag
> > > > > > > > > which indicates whether a device supports DIS_NULL_QUERY
> > > > > > > > > (Disable null anyhit shader query mechanism). The intent
> > > > > > > > > is for UMDs to use this query and opt-in
> > > > > > > > > DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY flag to disable null
> > > > > > > > > query mechanism for anyhit shader by setting
> > > > > > > > > DIS_NULL_QUERY bit of
> > > RT_CTRL register for Xe2.
> > > > > > > > >
> > > > > > > > > v2:
> > > > > > > > > - Use xe_rtp_match_first_render_or_compute() api to check
> > > > > > > > > render_or_compute. (Tejas)
> > > > > > > > > - Validate args->flags (Tejas/Matthew)
> > > > > > > > > - Add proper kernel-doc for both
> > > > > > > DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY
> > > > > > > > > and DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT. (Matthew)
> > > > > > > >
> > > > > > > > Matt asked for full spelling of DISABLE, no?!
> > > > > > >
> > > > > > > Thank you for clarifying the uAPI naming convention.
> > > > > > > I will update it.
> > > > > > >
> > > > > > > >
> > > > > > > > Also, where are the UMD patches/merge-requests for this? And
> > > > > > > > their
> > > ack?
> > > > > > > >
> > > > > > > From the Mesa team (Palli, Tapani) is going to send the
> > > > > > > corresponding Mesa patch.
> > > > > > > Meanwhile, I floated this patch.
> > > > > > >
> > > > > > > > Thanks,
> > > > > > > > Rodrigo.
> > > > > > > >
> > > > > > > > >
> > > > > > > > > Signed-off-by: Nitin Gote <nitin.r.gote@intel.com>
> > > > > > > > > ---
> > > > > > > > > drivers/gpu/drm/xe/xe_exec_queue.c | 11 ++++++++++-
> > > > > > > > > drivers/gpu/drm/xe/xe_query.c | 3 ++-
> > > > > > > > > include/uapi/drm/xe_drm.h | 12 ++++++++++++
> > > > > > > > > 3 files changed, 24 insertions(+), 2 deletions(-)
> > > > > > > > >
> > > > > > > > > diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c
> > > > > > > > > b/drivers/gpu/drm/xe/xe_exec_queue.c
> > > > > > > > > index fee22358cc09..ef8b49d2242a 100644
> > > > > > > > > --- a/drivers/gpu/drm/xe/xe_exec_queue.c
> > > > > > > > > +++ b/drivers/gpu/drm/xe/xe_exec_queue.c
> > > > > > > > > @@ -26,6 +26,9 @@
> > > > > > > > > #include "xe_trace.h"
> > > > > > > > > #include "xe_vm.h"
> > > > > > > > > #include "xe_pxp.h"
> > > > > > > > > +#include "xe_gt_mcr.h"
> > > > > > > > > +#include "regs/xe_gt_regs.h"
> > > > > > > > > +#include "xe_rtp.h"
> > > > > > > > >
> > > > > > > > > enum xe_exec_queue_sched_prop {
> > > > > > > > > XE_EXEC_QUEUE_JOB_TIMEOUT = 0, @@ -597,7 +600,8 @@
> > > int
> > > > > > > > > xe_exec_queue_create_ioctl(struct drm_device
> > > > > > > > *dev, void *data,
> > > > > > > > > u32 len;
> > > > > > > > > int err;
> > > > > > > > >
> > > > > > > > > - if (XE_IOCTL_DBG(xe, args->flags &
> > > > > > > > ~DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT) ||
> > > > > > > > > + if (XE_IOCTL_DBG(xe, args->flags &
> > > > > > > > > + ~(DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT |
> > > > > > > > > +DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY)) ||
> > > > > > > > > XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1]))
> > > > > > > > > return -EINVAL;
> > > > > > > > >
> > > > > > > > > @@ -693,6 +697,11 @@ int xe_exec_queue_create_ioctl(struct
> > > > > > > > > drm_device
> > > > > > > > *dev, void *data,
> > > > > > > > > }
> > > > > > > > > }
> > > > > > > > >
> > > > > > > > > + if (((GRAPHICS_VER(xe) >= 20) && (GRAPHICS_VER(xe) <
> > > > > > > > > +30))
> > > &&
> > > > > > > > > + (args->flags & DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY)
> > > &&
> > > > > > > > > + xe_rtp_match_first_render_or_compute(q->gt, q->hwe))
> > > > > > > > > + xe_gt_mcr_multicast_write(q->gt, RT_CTRL,
> > > > > > DIS_NULL_QUERY);
> > > > > > > > > +
> > > > > > >
> > > > > > > Also, as per Matt's suggestion in rev1, I'm exploring the WA
> > > > > > > BB program to set this.
> > > > > > >
> > > > > >
> > > > > > If we move this implementation from the exec queue creation time
> > > > > > to the submission time and write a WW BB program, then this
> > > > > > register will be set for every exec queue submission.
> > > > > > Let's say if submission happens 3 times, then register gets
> > > > > > written 3 times, which seems unnecessary.
> > > > > >
> > > >
> > > > No, completetly unnecessary, we have been over this. See below.
> > > >
> > >
> > > s/unnecessary/necessary
> > >
> > > Matt
> > >
> > > > > > So, having implementation in the exec queue create time, the
> > > > > > register will be updated only once, and we can disable it in the
> > > > > > exec queue
> > > destroy.
> > > > > >
> > > > > > What do you think? Could you please suggest?
> > > > >
> > > > > Hi Nitin/Matt,
> > > > >
> > > > > Are we talking below cases,
> > > > >
> > > > > (if kept in WA_BB) :
> > > > > User1 --> submits on rcs0 -> register will be updated for rcs0
> > > > > (User2 will not be affected)
> > > > > User2--> submits at the same time on rcs1 -> register will be
> > > > > User2--> updated for only rcs1 (User1 will not be affected)
> > > > >
> > > > > (if kept in exec_queue_create/destroy) :
> > > > > User1 --> creates exec_queue (register is written(not sure on
> > > > > which instance of rcs?) --> submits on rcs0 (User2 will be
> > > > > impacted if used same instance as User1, which isn't possible)
> > > > > User2--> creates exec_queue (register is written(not sure on which
> > > > > User2--> instance of rcs, but for sure not the instance User1 is
> > > > > User2--> using?) -> submits at the same time on rcs1 (User1 will
> > > > > User2--> be impacted if used same instance as User2, which isn't
> > > > > User2--> possible)
> > > > >
> > > > > If above cases are true then both look same, isn't it? Unless I am
> > > > > missing
> > > something.
> > > > >
> > > >
> > > > Tejas — I'm not really following your examples, but no, writing at
> > > > exec queue creation time is not the same as writing a WA BB.
> > > >
> > > > This is a very basic process isolation concept that I would expect
> > > > all KMD developers to understand. If not, then please take the time
> > > > to learn it — this isn't something I should have to explain
> > > > repeatedly. A quick Google search or a query to ChatGPT will explain
> > > > process isolation quite well. With just four queries, I got an
> > > > explanation for this exact problem, including why this must be part
> > > > of the context state (i.e., the WA BB), since work gets switched on the
> > hardware.
> > > >
> > > > Here were my chatgpt queries:
> > > >
> > > > "what is process isolation"
> > > >
> > > > "in a computer chip why can't you set a global register wrt to
> > > > process isolation"
> > > >
> > > > "more in the context the register changes behavior of computer chip
> > > > rather than data sharing"
> > > >
> > > > "say in the context of kernel submitting work on behalf of a UMD
> > > > which changes global register before each submit, why is that a bad idea"
> > > >
> > > > Anyway, let me give an example of why the current implementation
> > > > will not work:
> > > >
> > > > Example:
> > > > User1 wants DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY set.
> > > > User2 wants DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY
> > > cleared.
> > > >
> > > > If a global register is modified at exec queue creation time (i.e.,
> > > > it affects the entire GPU’s settings), then both users cannot have
> > > > different behaviors — and we’re now broken.
> > > >
> > > > The only way for User1 and User2 to have different settings is to
> > > > make this part of the context state (WA BB), which dynamically
> > > > modifies the registers as work from each user is scheduled on the hardware.
> >
> > Ok, I think I missed point here, as it is engine register, When UMD submits work
It is actually a GT register but same idea.
> > any engine instance will be selected for submission at the very same time we will
> > change the reg value on that instance, so for that period that instance will be
> > exclusively configured for specific user.
> >
> > I get it.
> >
> > Tejas
>
> Thank you, Tejas and Matt.
> I'm moving this to WA BB.
>
+1
Matt
> - Nitin
>
> > > >
> > > > Matt
> > > >
> > > > > Tejas
> > > > > >
> > > > > > Thanks,
> > > > > > Nitin
> > > > > >
> > > > > > > > > q->xef = xe_file_get(xef);
> > > > > > > > >
> > > > > > > > > /* user id alloc must always be last in ioctl to prevent
> > > > > > > > > UAF */ diff --git a/drivers/gpu/drm/xe/xe_query.c
> > > > > > > > > b/drivers/gpu/drm/xe/xe_query.c index
> > > > > > > > > e8e1743dcb1e..c5002b8c9ac0
> > > > > > > > > 100644
> > > > > > > > > --- a/drivers/gpu/drm/xe/xe_query.c
> > > > > > > > > +++ b/drivers/gpu/drm/xe/xe_query.c
> > > > > > > > > @@ -344,7 +344,8 @@ static int query_config(struct
> > > > > > > > > xe_device *xe, struct
> > > > > > > > drm_xe_device_query *query)
> > > > > > > > > config->info[DRM_XE_QUERY_CONFIG_FLAGS] |=
> > > > > > > > >
> > > > > > > > DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR;
> > > > > > > > > config->info[DRM_XE_QUERY_CONFIG_FLAGS] |=
> > > > > > > > > -
> > > DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY;
> > > > > > > > > +
> > > > > > (DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY
> > > > > > > > |
> > > > > > > > > +
> > > > > > > > DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY);
> > > > > > > > > config->info[DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT] =
> > > > > > > > > xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K ?
> > > SZ_64K :
> > > > > > > > SZ_4K;
> > > > > > > > > config->info[DRM_XE_QUERY_CONFIG_VA_BITS] =
> > > > > > > > > xe->info.va_bits; diff --git a/include/uapi/drm/xe_drm.h
> > > > > > > > > b/include/uapi/drm/xe_drm.h index
> > > > > > > > > 8e8bbdec8c5c..7c30e707346c
> > > > > > > > > 100644
> > > > > > > > > --- a/include/uapi/drm/xe_drm.h
> > > > > > > > > +++ b/include/uapi/drm/xe_drm.h
> > > > > > > > > @@ -397,6 +397,8 @@ struct drm_xe_query_mem_regions {
> > > > > > > > > * has low latency hint support
> > > > > > > > > * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR
> > > - Flag
> > > > > > is
> > > > > > > > set if the
> > > > > > > > > * device has CPU address mirroring support
> > > > > > > > > + * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY -
> > > Flag is
> > > > > > set
> > > > > > > if
> > > > > > > > the
> > > > > > > > > + * device has null query support for anyhit shader.
> > > > > > > > > * - %DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT - Minimal
> > > memory
> > > > > > > > alignment
> > > > > > > > > * required by this device, typically SZ_4K or SZ_64K
> > > > > > > > > * - %DRM_XE_QUERY_CONFIG_VA_BITS - Maximum bits of a
> > > > > > > > > virtual address @@ -415,6 +417,7 @@ struct
> > > > > > > > > drm_xe_query_config
> > > {
> > > > > > > > > #define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM (1 <<
> > > 0)
> > > > > > > > > #define DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY
> > > (1 <<
> > > > > > > > 1)
> > > > > > > > > #define
> > > DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR
> > > > > > > > (1 << 2)
> > > > > > > > > + #define
> > > DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY
> > > > > > (1 <<
> > > > > > > > 3)
> > > > > > > > > #define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT
> > > 2
> > > > > > > > > #define DRM_XE_QUERY_CONFIG_VA_BITS 3
> > > > > > > > > #define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY
> > > 4
> > > > > > > > > @@ -1270,7 +1273,16 @@ struct drm_xe_exec_queue_create {
> > > > > > > > > /** @vm_id: VM to use for this exec queue */
> > > > > > > > > __u32 vm_id;
> > > > > > > > >
> > > > > > > > > + /** DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY - \
> > > > > > > > > + * Flag is set if the device has low latency hint support
> > > > > > > > > + */
> > > > > > > > > #define DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT (1 <<
> > > 0)
> > > > > > > > > +
> > > > > > > > > + /** DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY - \
> > > > > > > > > + * flag is use to disable null query check for Anyhit shader
> > > > > > > > > + */
> > > > > > > > > +#define DRM_XE_EXEC_QUEUE_DIS_NULL_QUERY (1 << 1)
> > > > > > > > > +
> > > > > > > > > /** @flags: flags to use for this exec queue */
> > > > > > > > > __u32 flags;
> > > > > > > > >
> > > > > > > > > --
> > > > > > > > > 2.25.1
> > > > > > > > >
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2025-07-01 16:25 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-06-25 9:58 [PATCH] drm/xe/uapi: Add DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY Nitin Gote
2025-06-25 9:41 ` ✓ CI.KUnit: success for drm/xe/uapi: Add DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY (rev2) Patchwork
2025-06-25 10:17 ` ✓ Xe.CI.BAT: " Patchwork
2025-06-25 14:21 ` [PATCH] drm/xe/uapi: Add DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY Rodrigo Vivi
2025-06-26 11:50 ` Gote, Nitin R
2025-06-27 8:14 ` Gote, Nitin R
2025-06-27 9:37 ` Upadhyay, Tejas
2025-06-27 17:57 ` Matthew Brost
2025-06-27 18:15 ` Matthew Brost
2025-07-01 12:07 ` Upadhyay, Tejas
2025-07-01 14:06 ` Gote, Nitin R
2025-07-01 16:26 ` Matthew Brost
2025-06-26 6:22 ` ✓ Xe.CI.Full: success for drm/xe/uapi: Add DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY (rev2) Patchwork
-- strict thread matches above, loose matches on Subject: below --
2025-06-23 6:40 [PATCH] drm/xe/uapi: Add DRM_XE_QUERY_CONFIG_FLAG_HAS_DIS_NULL_QUERY Nitin Gote
2025-06-23 6:51 ` Upadhyay, Tejas
2025-06-24 0:17 ` Matthew Brost
2025-06-25 9:23 ` Gote, Nitin R
2025-06-25 13:35 ` Matthew Brost
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