[PATCH 0/5] drm/i915/dp: Work around a DSC pixel throughput issue

[PATCH 0/5] drm/i915/dp: Work around a DSC pixel throughput issue

[Imre Deak]

This patchset works around an issue observed in docking stations
decompressing a DSC stream with a high pixel-clock and high compressed
link-bpp, resulting either in blank or unstable display output.

The affected devices all contain an older version of the Synaptics MST
branch device. The issue is observed both in MST and SST mode.

Add a workaround for the above, limiting the link-bpp as required for
high pixel-clock modes.

Reported-by: Vidya Srinivas <vidya.srinivas@intel.com>
Reported-by: Swati Sharma <swati2.sharma@intel.com>

Imre Deak (5):
  drm/dp: Add quirk for Synaptics DSC throughput link-bpp limit
  drm/i915/dp: Calculate DSC slice count based on per-slice peak
    throughput
  drm/i915/dp: Pass DPCD device descriptor to
    intel_dp_get_dsc_sink_cap()
  drm/i915/dp: Verify branch devices' overall pixel throughput/line
    width
  drm/i915/dp: Handle Synaptics DSC throughput link-bpp quirk

 drivers/gpu/drm/display/drm_dp_helper.c       |   4 +
 .../drm/i915/display/intel_display_types.h    |   9 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 171 +++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_dp.h       |   5 +-
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |   9 +-
 include/drm/display/drm_dp_helper.h           |   4 +
 6 files changed, 193 insertions(+), 9 deletions(-)

-- 
2.49.1

[PATCH 1/5] drm/dp: Add quirk for Synaptics DSC throughput link-bpp limit

[Imre Deak]

Some Synaptics MST branch devices have a problem decompressing a stream
with a compressed link-bpp higher than 12, if the pixel clock is higher
than ~50 % of the maximum throughput capability reported by the branch
device. The screen remains blank, or for some - mostly black content -
gets enabled, but may stil have jitter artifacts.

At least the following docking stations are affected, based on testing
both with any Intel devices or the UCD-500 reference device as a source:

- DELL WD19DCS, DELL WD19TB3, DELL WD22TB4
- ThinkPad 40AN
- HP G2

At least the following docking stations are free from this problem,
based on tests with a source/sink/mode etc. configuration matching the
test cases used above:

- DELL Dual Charge HD22Q, DELL WD25TB5
- ThinkPad 40B0
- Anker 565

All the affected devices have an older version of the Synaptics MST
branch device (Panarema), whereas all the non-affected docking stations
have a newer branch device (at least Synaptics Panarema with a higher HW
revision number and Synaptics Cayenne models). Add the required quirk
entries accordingly. The quirk will be handled by the i915/xe drivers in
a follow-up change.

The latest firmware version of the Synaptics branch device for all the
affected devices tested above is 5.7 (as reported at DPCD address
0x50a/0x50b). For the DELL devices this corresponds to the latest
01.00.14.01.A03 firmware package version of the docking station.

Cc: dri-devel@lists.freedesktop.org
Reported-by: Vidya Srinivas <vidya.srinivas@intel.com>
Reported-by: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/display/drm_dp_helper.c | 4 ++++
 include/drm/display/drm_dp_helper.h     | 4 ++++
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
index 4aaeae4fa03c3..80dfa32e88992 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -2543,6 +2543,10 @@ static const struct dpcd_quirk dpcd_quirk_list[] = {
 	{ OUI(0x00, 0x0C, 0xE7), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC) },
 	/* Apple MacBookPro 2017 15 inch eDP Retina panel reports too low DP_MAX_LINK_RATE */
 	{ OUI(0x00, 0x10, 0xfa), DEVICE_ID(101, 68, 21, 101, 98, 97), false, BIT(DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS) },
+	/* Synaptics PANAMERA branch devices having a pixel clock dependent DSC compressed bpp limit. */
+	{ OUI(0x90, 0xCC, 0x24), DEVICE_ID('S', 'Y', 'N', 'A', 0x53, 0x22), true, BIT(DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT) },
+	{ OUI(0x90, 0xCC, 0x24), DEVICE_ID('S', 'Y', 'N', 'A', 0x53, 0x31), true, BIT(DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT) },
+	{ OUI(0x90, 0xCC, 0x24), DEVICE_ID('S', 'Y', 'N', 'A', 0x53, 0x33), true, BIT(DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT) },
 };
 
 #undef OUI
diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
index 87caa4f1fdb86..30297aadd5ff9 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -820,6 +820,10 @@ enum drm_dp_quirk {
 	 * requires enabling DSC.
 	 */
 	DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC,
+	/**
+	 * @DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT
+	 */
+	DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT,
 };
 
 /**
-- 
2.49.1

Re: [PATCH 1/5] drm/dp: Add quirk for Synaptics DSC throughput link-bpp limit

[kernel test robot]

Hi Imre,

kernel test robot noticed the following build warnings:

[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on linus/master v6.17-rc6 next-20250919]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Imre-Deak/drm-dp-Add-quirk-for-Synaptics-DSC-throughput-link-bpp-limit/20250919-052049
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
patch link:    https://lore.kernel.org/r/20250918211223.209674-2-imre.deak%40intel.com
patch subject: [PATCH 1/5] drm/dp: Add quirk for Synaptics DSC throughput link-bpp limit
reproduce: (https://download.01.org/0day-ci/archive/20250920/202509201934.m60n3RyN-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202509201934.m60n3RyN-lkp@intel.com/

All warnings (new ones prefixed by >>):

   Declaration is '.. c:function:: const struct drm_format_info * drm_format_info (u32 format)'. [duplicate_declaration.c]
   Documentation/gpu/drm-kms:476: ./drivers/gpu/drm/drm_modeset_lock.c:377: WARNING: Duplicate C declaration, also defined at gpu/drm-kms:48.
   Declaration is '.. c:function:: int drm_modeset_lock (struct drm_modeset_lock *lock, struct drm_modeset_acquire_ctx *ctx)'. [duplicate_declaration.c]
   WARNING: ./include/drm/display/drm_dp_helper.h:823 Incorrect use of kernel-doc format:          * @DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT
   WARNING: ./include/drm/display/drm_dp_helper.h:826 Enum value ' */ DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT' not described in enum 'drm_dp_quirk'
>> Documentation/gpu/drm-kms-helpers:266: ./include/drm/display/drm_dp_helper.h:804: WARNING: Inline emphasis start-string without end-string. [docutils]
   ERROR: Cannot find file ./include/linux/hdmi.h
   ERROR: Cannot find file ./include/linux/hdmi.h
   WARNING: No kernel-doc for file ./include/linux/hdmi.h
   WARNING: ./include/drm/drm_gpuvm.h:1059 struct member 'map' not described in 'drm_gpuvm_map_req'
   Documentation/gpu/drm-mm:506: ./drivers/gpu/drm/drm_gpuvm.c:2547: ERROR: Unexpected indentation. [docutils]

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

[PATCH v2 1/5] drm/dp: Add quirk for Synaptics DSC throughput link-bpp limit

[Imre Deak]

Some Synaptics MST branch devices have a problem decompressing a stream
with a compressed link-bpp higher than 12, if the pixel clock is higher
than ~50 % of the maximum throughput capability reported by the branch
device. The screen remains blank, or for some - mostly black content -
gets enabled, but may stil have jitter artifacts.

At least the following docking stations are affected, based on testing
both with any Intel devices or the UCD-500 reference device as a source:

- DELL WD19DCS, DELL WD19TB3, DELL WD22TB4
- ThinkPad 40AN
- HP G2

At least the following docking stations are free from this problem,
based on tests with a source/sink/mode etc. configuration matching the
test cases used above:

- DELL Dual Charge HD22Q, DELL WD25TB5
- ThinkPad 40B0
- Anker 565

All the affected devices have an older version of the Synaptics MST
branch device (Panarema), whereas all the non-affected docking stations
have a newer branch device (at least Synaptics Panarema with a higher HW
revision number and Synaptics Cayenne models). Add the required quirk
entries accordingly. The quirk will be handled by the i915/xe drivers in
a follow-up change.

The latest firmware version of the Synaptics branch device for all the
affected devices tested above is 5.7 (as reported at DPCD address
0x50a/0x50b). For the DELL devices this corresponds to the latest
01.00.14.01.A03 firmware package version of the docking station.

v2:
- Document the DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT enum.
- Describe the quirk in more detail in the dpcd_quirk_list.

Cc: dri-devel@lists.freedesktop.org
Reported-by: Vidya Srinivas <vidya.srinivas@intel.com>
Reported-by: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/display/drm_dp_helper.c | 4 ++++
 include/drm/display/drm_dp_helper.h     | 9 +++++++++
 2 files changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
index 5426db21e53f..1c74fe9459ad 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -2551,6 +2551,10 @@ static const struct dpcd_quirk dpcd_quirk_list[] = {
 	{ OUI(0x00, 0x0C, 0xE7), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC) },
 	/* Apple MacBookPro 2017 15 inch eDP Retina panel reports too low DP_MAX_LINK_RATE */
 	{ OUI(0x00, 0x10, 0xfa), DEVICE_ID(101, 68, 21, 101, 98, 97), false, BIT(DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS) },
+	/* Synaptics Panamera supports only a compressed bpp of 12 above 50% of its max DSC pixel throughput */
+	{ OUI(0x90, 0xCC, 0x24), DEVICE_ID('S', 'Y', 'N', 'A', 0x53, 0x22), true, BIT(DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT) },
+	{ OUI(0x90, 0xCC, 0x24), DEVICE_ID('S', 'Y', 'N', 'A', 0x53, 0x31), true, BIT(DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT) },
+	{ OUI(0x90, 0xCC, 0x24), DEVICE_ID('S', 'Y', 'N', 'A', 0x53, 0x33), true, BIT(DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT) },
 };
 
 #undef OUI
diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
index 52ce28097015..e438c4440995 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -828,6 +828,15 @@ enum drm_dp_quirk {
 	 * requires enabling DSC.
 	 */
 	DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC,
+	/**
+	 * @DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT:
+	 *
+	 * The device doesn't support DSC decompression at the maximum DSC
+	 * pixel throughput and compressed bpp it indicates via its DPCD DSC
+	 * capabilities. The compressed bpp must be limited above a device
+	 * specific DSC pixel throughput.
+	 */
+	DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT,
 };
 
 /**
-- 
2.49.1

[PATCH 2/5] drm/i915/dp: Calculate DSC slice count based on per-slice peak throughput

[Imre Deak]

Use the branch device's actual per-slice peak throughput to calculate
the minimum number of required DSC slices, falling back to the
hard-coded throughput values (as suggested by the DP Standard) if the
device's reported throughput value is 0.

For now use the minimum of the two throughput values, which is ok,
potentially resulting in a higher than required minimum slice count.
This doesn't change the current way of using the same minimum throughput
value regardless of the RGB/YUV output format used.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 47 +++++++++++++++++++++----
 1 file changed, 41 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 2eab591a8ef56..a963a58c87372 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1011,6 +1011,26 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct intel_display *display,
 	return bits_per_pixel;
 }
 
+static int dsc_per_slice_throughput(struct intel_display *display, int mode_clock, int bw_code)
+{
+	switch (bw_code) {
+	case 0:
+		if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
+			return DP_DSC_MAX_ENC_THROUGHPUT_0;
+		else
+			return DP_DSC_MAX_ENC_THROUGHPUT_1;
+	case 1:
+		return 340000;
+	case 2 ... 14:
+		return 400000 + 50000 * (bw_code - 2);
+	case 15:
+		return 170000;
+	default:
+		drm_err(display->drm, "Invalid DSC peak throughput code\n");
+		return 340000;
+	}
+}
+
 u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
 				int mode_clock, int mode_hdisplay,
 				int num_joined_pipes)
@@ -1018,13 +1038,28 @@ u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
 	struct intel_display *display = to_intel_display(connector);
 	u8 min_slice_count, i;
 	int max_slice_width;
+	int tp_rgb_yuv444;
+	int tp_yuv422_420;
+	u8 val;
 
-	if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
-		min_slice_count = DIV_ROUND_UP(mode_clock,
-					       DP_DSC_MAX_ENC_THROUGHPUT_0);
-	else
-		min_slice_count = DIV_ROUND_UP(mode_clock,
-					       DP_DSC_MAX_ENC_THROUGHPUT_1);
+	val = connector->dp.dsc_dpcd[DP_DSC_PEAK_THROUGHPUT - DP_DSC_SUPPORT];
+	tp_rgb_yuv444 = dsc_per_slice_throughput(display, mode_clock,
+						 REG_FIELD_GET8(DP_DSC_THROUGHPUT_MODE_0_MASK,
+								val));
+	tp_yuv422_420 = dsc_per_slice_throughput(display, mode_clock,
+						 REG_FIELD_GET8(DP_DSC_THROUGHPUT_MODE_1_MASK,
+								val));
+
+	/*
+	 * TODO: Use the throughput value specific to the actual RGB/YUV
+	 * format of the output.
+	 * For now use the smaller of these, which is ok, potentially
+	 * resulting in a higher than required minimum slice count.
+	 * The RGB/YUV444 throughput value should be always either equal
+	 * or smaller than the YUV422/420 value, but let's not depend on
+	 * this assumption.
+	 */
+	min_slice_count = DIV_ROUND_UP(mode_clock, min(tp_rgb_yuv444, tp_yuv422_420));
 
 	/*
 	 * Due to some DSC engine BW limitations, we need to enable second
-- 
2.49.1

Re: [PATCH 2/5] drm/i915/dp: Calculate DSC slice count based on per-slice peak throughput

[Ville Syrjälä]

On Fri, Sep 19, 2025 at 12:12:20AM +0300, Imre Deak wrote:
> Use the branch device's actual per-slice peak throughput to calculate
> the minimum number of required DSC slices, falling back to the
> hard-coded throughput values (as suggested by the DP Standard) if the
> device's reported throughput value is 0.
> 
> For now use the minimum of the two throughput values, which is ok,
> potentially resulting in a higher than required minimum slice count.
> This doesn't change the current way of using the same minimum throughput
> value regardless of the RGB/YUV output format used.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 47 +++++++++++++++++++++----
>  1 file changed, 41 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 2eab591a8ef56..a963a58c87372 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1011,6 +1011,26 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct intel_display *display,
>  	return bits_per_pixel;
>  }
>  
> +static int dsc_per_slice_throughput(struct intel_display *display, int mode_clock, int bw_code)

s/bw_code/throughput_mode/ or something maybe to make it match the spec
a bit better? "bw_code" is I think what we've been calling the
LINK_BW_SET value.

> +{
> +	switch (bw_code) {
> +	case 0:
> +		if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
> +			return DP_DSC_MAX_ENC_THROUGHPUT_0;
> +		else
> +			return DP_DSC_MAX_ENC_THROUGHPUT_1;

These look like some unhelpful single use defines. I'd get
rid of them and just stick the actual numbers here.

> +	case 1:
> +		return 340000;
> +	case 2 ... 14:
> +		return 400000 + 50000 * (bw_code - 2);
> +	case 15:
> +		return 170000;
> +	default:
> +		drm_err(display->drm, "Invalid DSC peak throughput code\n");

This whole thing looks like it belongs in some drm helper.
Probably best to pass in struct drm_device from the start
so that moving it over will later be easier.

> +		return 340000;
> +	}
> +}
> +
>  u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
>  				int mode_clock, int mode_hdisplay,
>  				int num_joined_pipes)
> @@ -1018,13 +1038,28 @@ u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
>  	struct intel_display *display = to_intel_display(connector);
>  	u8 min_slice_count, i;
>  	int max_slice_width;
> +	int tp_rgb_yuv444;
> +	int tp_yuv422_420;
> +	u8 val;
>  
> -	if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
> -		min_slice_count = DIV_ROUND_UP(mode_clock,
> -					       DP_DSC_MAX_ENC_THROUGHPUT_0);
> -	else
> -		min_slice_count = DIV_ROUND_UP(mode_clock,
> -					       DP_DSC_MAX_ENC_THROUGHPUT_1);
> +	val = connector->dp.dsc_dpcd[DP_DSC_PEAK_THROUGHPUT - DP_DSC_SUPPORT];
> +	tp_rgb_yuv444 = dsc_per_slice_throughput(display, mode_clock,
> +						 REG_FIELD_GET8(DP_DSC_THROUGHPUT_MODE_0_MASK,
> +								val));
> +	tp_yuv422_420 = dsc_per_slice_throughput(display, mode_clock,
> +						 REG_FIELD_GET8(DP_DSC_THROUGHPUT_MODE_1_MASK,
> +								val));
> +
> +	/*
> +	 * TODO: Use the throughput value specific to the actual RGB/YUV
> +	 * format of the output.
> +	 * For now use the smaller of these, which is ok, potentially
> +	 * resulting in a higher than required minimum slice count.
> +	 * The RGB/YUV444 throughput value should be always either equal
> +	 * or smaller than the YUV422/420 value, but let's not depend on
> +	 * this assumption.
> +	 */
> +	min_slice_count = DIV_ROUND_UP(mode_clock, min(tp_rgb_yuv444, tp_yuv422_420));
>  
>  	/*
>  	 * Due to some DSC engine BW limitations, we need to enable second
> -- 
> 2.49.1

-- 
Ville Syrjälä
Intel

Re: [PATCH 2/5] drm/i915/dp: Calculate DSC slice count based on per-slice peak throughput

[Imre Deak]

On Mon, Sep 22, 2025 at 10:34:40PM +0300, Ville Syrjälä wrote:
> On Fri, Sep 19, 2025 at 12:12:20AM +0300, Imre Deak wrote:
> > Use the branch device's actual per-slice peak throughput to calculate
> > the minimum number of required DSC slices, falling back to the
> > hard-coded throughput values (as suggested by the DP Standard) if the
> > device's reported throughput value is 0.
> > 
> > For now use the minimum of the two throughput values, which is ok,
> > potentially resulting in a higher than required minimum slice count.
> > This doesn't change the current way of using the same minimum throughput
> > value regardless of the RGB/YUV output format used.
> > 
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp.c | 47 +++++++++++++++++++++----
> >  1 file changed, 41 insertions(+), 6 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 2eab591a8ef56..a963a58c87372 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -1011,6 +1011,26 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct intel_display *display,
> >  	return bits_per_pixel;
> >  }
> >  
> > +static int dsc_per_slice_throughput(struct intel_display *display, int mode_clock, int bw_code)
> 
> s/bw_code/throughput_mode/ or something maybe to make it match the spec
> a bit better? "bw_code" is I think what we've been calling the
> LINK_BW_SET value.

Ok, will use throughput.

> 
> > +{
> > +	switch (bw_code) {
> > +	case 0:
> > +		if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
> > +			return DP_DSC_MAX_ENC_THROUGHPUT_0;
> > +		else
> > +			return DP_DSC_MAX_ENC_THROUGHPUT_1;
> 
> These look like some unhelpful single use defines. I'd get
> rid of them and just stick the actual numbers here.

Ok, agreed, will remove/inline the defines. The Standard actually
describes a 3rd range as well above 4800 MPixel/s, will add that too.

> > +	case 1:
> > +		return 340000;
> > +	case 2 ... 14:
> > +		return 400000 + 50000 * (bw_code - 2);
> > +	case 15:
> > +		return 170000;
> > +	default:
> > +		drm_err(display->drm, "Invalid DSC peak throughput code\n");
> 
> This whole thing looks like it belongs in some drm helper.
> Probably best to pass in struct drm_device from the start
> so that moving it over will later be easier.

Ok, agreed. Moved this now and the other DSC branch query functions in
this patchset to drm_dp_helper.c as in patch [1] in branch [2].

[1] https://github.com/ideak/linux/commit/7f7cab2746f4
[2] https://github.com/ideak/linux/commits/dsc-bpp-quirk

> 
> > +		return 340000;
> > +	}
> > +}
> > +
> >  u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
> >  				int mode_clock, int mode_hdisplay,
> >  				int num_joined_pipes)
> > @@ -1018,13 +1038,28 @@ u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
> >  	struct intel_display *display = to_intel_display(connector);
> >  	u8 min_slice_count, i;
> >  	int max_slice_width;
> > +	int tp_rgb_yuv444;
> > +	int tp_yuv422_420;
> > +	u8 val;
> >  
> > -	if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
> > -		min_slice_count = DIV_ROUND_UP(mode_clock,
> > -					       DP_DSC_MAX_ENC_THROUGHPUT_0);
> > -	else
> > -		min_slice_count = DIV_ROUND_UP(mode_clock,
> > -					       DP_DSC_MAX_ENC_THROUGHPUT_1);
> > +	val = connector->dp.dsc_dpcd[DP_DSC_PEAK_THROUGHPUT - DP_DSC_SUPPORT];
> > +	tp_rgb_yuv444 = dsc_per_slice_throughput(display, mode_clock,
> > +						 REG_FIELD_GET8(DP_DSC_THROUGHPUT_MODE_0_MASK,
> > +								val));
> > +	tp_yuv422_420 = dsc_per_slice_throughput(display, mode_clock,
> > +						 REG_FIELD_GET8(DP_DSC_THROUGHPUT_MODE_1_MASK,
> > +								val));
> > +
> > +	/*
> > +	 * TODO: Use the throughput value specific to the actual RGB/YUV
> > +	 * format of the output.
> > +	 * For now use the smaller of these, which is ok, potentially
> > +	 * resulting in a higher than required minimum slice count.
> > +	 * The RGB/YUV444 throughput value should be always either equal
> > +	 * or smaller than the YUV422/420 value, but let's not depend on
> > +	 * this assumption.
> > +	 */
> > +	min_slice_count = DIV_ROUND_UP(mode_clock, min(tp_rgb_yuv444, tp_yuv422_420));
> >  
> >  	/*
> >  	 * Due to some DSC engine BW limitations, we need to enable second
> > -- 
> > 2.49.1
> 
> -- 
> Ville Syrjälä
> Intel

[PATCH 3/5] drm/i915/dp: Pass DPCD device descriptor to intel_dp_get_dsc_sink_cap()

[Imre Deak]

Pass the DPCD sink/branch device descriptor along with the
is_branch/sink flag to intel_dp_get_dsc_sink_cap(). These will be used
by a follow up change to read out the branch device's DSC overall
throughput/line width capabilities and to detect a throughput/link-bpp
quirk.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c     | 5 ++++-
 drivers/gpu/drm/i915/display/intel_dp.h     | 5 ++++-
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 9 ++++++++-
 3 files changed, 16 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index a963a58c87372..8cc123b0fd752 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4204,7 +4204,9 @@ static void intel_dp_read_dsc_dpcd(struct drm_dp_aux *aux,
 		    dsc_dpcd);
 }
 
-void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector)
+void intel_dp_get_dsc_sink_cap(u8 dpcd_rev,
+			       const struct drm_dp_desc *desc, bool is_branch,
+			       struct intel_connector *connector)
 {
 	struct intel_display *display = to_intel_display(connector);
 
@@ -4255,6 +4257,7 @@ intel_dp_detect_dsc_caps(struct intel_dp *intel_dp, struct intel_connector *conn
 					   connector);
 	else
 		intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV],
+					  &intel_dp->desc, drm_dp_is_branch(intel_dp->dpcd),
 					  connector);
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index f90cfd1dbbd05..b379443e0211e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -12,6 +12,7 @@ enum intel_output_format;
 enum pipe;
 enum port;
 struct drm_connector_state;
+struct drm_dp_desc;
 struct drm_dp_vsc_sdp;
 struct drm_encoder;
 struct drm_modeset_acquire_ctx;
@@ -199,7 +200,9 @@ bool intel_dp_compute_config_limits(struct intel_dp *intel_dp,
 				    bool dsc,
 				    struct link_config_limits *limits);
 
-void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector);
+void intel_dp_get_dsc_sink_cap(u8 dpcd_rev,
+			       const struct drm_dp_desc *desc, bool is_branch,
+			       struct intel_connector *connector);
 bool intel_dp_has_gamut_metadata_dip(struct intel_encoder *encoder);
 
 bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 352f7ef29c281..f2266b2653046 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -1658,6 +1658,7 @@ intel_dp_mst_read_decompression_port_dsc_caps(struct intel_dp *intel_dp,
 					      struct intel_connector *connector)
 {
 	u8 dpcd_caps[DP_RECEIVER_CAP_SIZE];
+	struct drm_dp_desc desc;
 
 	if (!connector->dp.dsc_decompression_aux)
 		return;
@@ -1665,7 +1666,13 @@ intel_dp_mst_read_decompression_port_dsc_caps(struct intel_dp *intel_dp,
 	if (drm_dp_read_dpcd_caps(connector->dp.dsc_decompression_aux, dpcd_caps) < 0)
 		return;
 
-	intel_dp_get_dsc_sink_cap(dpcd_caps[DP_DPCD_REV], connector);
+	if (drm_dp_read_desc(connector->dp.dsc_decompression_aux, &desc,
+			     drm_dp_is_branch(dpcd_caps)) < 0)
+		return;
+
+	intel_dp_get_dsc_sink_cap(dpcd_caps[DP_DPCD_REV],
+				  &desc, drm_dp_is_branch(dpcd_caps),
+				  connector);
 }
 
 static bool detect_dsc_hblank_expansion_quirk(const struct intel_connector *connector)
-- 
2.49.1

[PATCH 4/5] drm/i915/dp: Verify branch devices' overall pixel throughput/line width

[Imre Deak]

Read out the branch devices' maximum overall DSC pixel throughput and
line width and verify the mode's corresponding pixel clock and hactive
period against these.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  8 +++
 drivers/gpu/drm/i915/display/intel_dp.c       | 62 +++++++++++++++++++
 2 files changed, 70 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 358ab922d7a76..73bdafae604f8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -552,6 +552,14 @@ struct intel_connector {
 
 		u8 dsc_hblank_expansion_quirk:1;
 		u8 dsc_decompression_enabled:1;
+
+		struct {
+			struct {
+				int rgb_yuv444;
+				int yuv422_420;
+			} overall_throughput;
+			int max_line_width;
+		} dsc_branch_caps;
 	} dp;
 
 	struct {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 8cc123b0fd752..dd082d2fcc968 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1042,6 +1042,20 @@ u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
 	int tp_yuv422_420;
 	u8 val;
 
+	/*
+	 * TODO: Use the throughput value specific to the actual RGB/YUV
+	 * format of the output.
+	 * The RGB/YUV444 throughput value should be always either equal
+	 * or smaller than the YUV422/420 value, but let's not depend on
+	 * this assumption.
+	 */
+	if (mode_clock > max(connector->dp.dsc_branch_caps.overall_throughput.rgb_yuv444,
+			     connector->dp.dsc_branch_caps.overall_throughput.yuv422_420))
+		return 0;
+
+	if (mode_hdisplay > connector->dp.dsc_branch_caps.max_line_width)
+		return 0;
+
 	val = connector->dp.dsc_dpcd[DP_DSC_PEAK_THROUGHPUT - DP_DSC_SUPPORT];
 	tp_rgb_yuv444 = dsc_per_slice_throughput(display, mode_clock,
 						 REG_FIELD_GET8(DP_DSC_THROUGHPUT_MODE_0_MASK,
@@ -4204,6 +4218,44 @@ static void intel_dp_read_dsc_dpcd(struct drm_dp_aux *aux,
 		    dsc_dpcd);
 }
 
+static int dsc_branch_overall_throughput(u8 bw_code)
+{
+	switch (bw_code) {
+	case 0:
+		return INT_MAX;
+	case 1:
+		return 680000;
+	default:
+		return 600000 + 50000 * bw_code;
+	}
+}
+
+static void init_dsc_overall_throughput_limits(struct intel_connector *connector, bool is_branch)
+{
+	u8 branch_caps[3];
+
+	connector->dp.dsc_branch_caps.overall_throughput.rgb_yuv444 = INT_MAX;
+	connector->dp.dsc_branch_caps.overall_throughput.yuv422_420 = INT_MAX;
+	connector->dp.dsc_branch_caps.max_line_width = INT_MAX;
+
+	if (!is_branch)
+		return;
+
+	if (drm_dp_dpcd_read_data(connector->dp.dsc_decompression_aux,
+				  DP_DSC_BRANCH_OVERALL_THROUGHPUT_0, branch_caps,
+				  sizeof(branch_caps)) != 0)
+		return;
+
+	connector->dp.dsc_branch_caps.overall_throughput.rgb_yuv444 =
+		dsc_branch_overall_throughput(branch_caps[0]);
+
+	connector->dp.dsc_branch_caps.overall_throughput.yuv422_420 =
+		dsc_branch_overall_throughput(branch_caps[1]);
+
+	if (branch_caps[2] != 0)
+		connector->dp.dsc_branch_caps.max_line_width = branch_caps[2] * 320;
+}
+
 void intel_dp_get_dsc_sink_cap(u8 dpcd_rev,
 			       const struct drm_dp_desc *desc, bool is_branch,
 			       struct intel_connector *connector)
@@ -4219,6 +4271,8 @@ void intel_dp_get_dsc_sink_cap(u8 dpcd_rev,
 	/* Clear fec_capable to avoid using stale values */
 	connector->dp.fec_capability = 0;
 
+	memset(&connector->dp.dsc_branch_caps, 0, sizeof(connector->dp.dsc_branch_caps));
+
 	if (dpcd_rev < DP_DPCD_REV_14)
 		return;
 
@@ -4233,6 +4287,11 @@ void intel_dp_get_dsc_sink_cap(u8 dpcd_rev,
 
 	drm_dbg_kms(display->drm, "FEC CAPABILITY: %x\n",
 		    connector->dp.fec_capability);
+
+	if (!(connector->dp.dsc_dpcd[0] & DP_DSC_DECOMPRESSION_IS_SUPPORTED))
+		return;
+
+	init_dsc_overall_throughput_limits(connector, is_branch);
 }
 
 static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *connector)
@@ -4241,6 +4300,9 @@ static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *
 		return;
 
 	intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, connector->dp.dsc_dpcd);
+
+	if (connector->dp.dsc_dpcd[0] & DP_DSC_DECOMPRESSION_IS_SUPPORTED)
+		init_dsc_overall_throughput_limits(connector, false);
 }
 
 static void
-- 
2.49.1

Re: [PATCH 4/5] drm/i915/dp: Verify branch devices' overall pixel throughput/line width

[Ville Syrjälä]

On Fri, Sep 19, 2025 at 12:12:22AM +0300, Imre Deak wrote:
> Read out the branch devices' maximum overall DSC pixel throughput and
> line width and verify the mode's corresponding pixel clock and hactive
> period against these.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  .../drm/i915/display/intel_display_types.h    |  8 +++
>  drivers/gpu/drm/i915/display/intel_dp.c       | 62 +++++++++++++++++++
>  2 files changed, 70 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 358ab922d7a76..73bdafae604f8 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -552,6 +552,14 @@ struct intel_connector {
>  
>  		u8 dsc_hblank_expansion_quirk:1;
>  		u8 dsc_decompression_enabled:1;
> +
> +		struct {
> +			struct {
> +				int rgb_yuv444;
> +				int yuv422_420;
> +			} overall_throughput;
> +			int max_line_width;
> +		} dsc_branch_caps;
>  	} dp;
>  
>  	struct {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 8cc123b0fd752..dd082d2fcc968 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1042,6 +1042,20 @@ u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
>  	int tp_yuv422_420;
>  	u8 val;
>  
> +	/*
> +	 * TODO: Use the throughput value specific to the actual RGB/YUV
> +	 * format of the output.
> +	 * The RGB/YUV444 throughput value should be always either equal
> +	 * or smaller than the YUV422/420 value, but let's not depend on
> +	 * this assumption.
> +	 */
> +	if (mode_clock > max(connector->dp.dsc_branch_caps.overall_throughput.rgb_yuv444,
> +			     connector->dp.dsc_branch_caps.overall_throughput.yuv422_420))
> +		return 0;
> +
> +	if (mode_hdisplay > connector->dp.dsc_branch_caps.max_line_width)
> +		return 0;

Looks like you only initialize these when the branch device supports
decompression. What about a branch device that can do pass-through but
no decompression? Should we even be checking these when doing
pass-through?

> +
>  	val = connector->dp.dsc_dpcd[DP_DSC_PEAK_THROUGHPUT - DP_DSC_SUPPORT];
>  	tp_rgb_yuv444 = dsc_per_slice_throughput(display, mode_clock,
>  						 REG_FIELD_GET8(DP_DSC_THROUGHPUT_MODE_0_MASK,
> @@ -4204,6 +4218,44 @@ static void intel_dp_read_dsc_dpcd(struct drm_dp_aux *aux,
>  		    dsc_dpcd);
>  }
>  
> +static int dsc_branch_overall_throughput(u8 bw_code)
> +{
> +	switch (bw_code) {
> +	case 0:
> +		return INT_MAX;
> +	case 1:
> +		return 680000;
> +	default:
> +		return 600000 + 50000 * bw_code;
> +	}
> +}
> +
> +static void init_dsc_overall_throughput_limits(struct intel_connector *connector, bool is_branch)
> +{
> +	u8 branch_caps[3];
> +
> +	connector->dp.dsc_branch_caps.overall_throughput.rgb_yuv444 = INT_MAX;
> +	connector->dp.dsc_branch_caps.overall_throughput.yuv422_420 = INT_MAX;
> +	connector->dp.dsc_branch_caps.max_line_width = INT_MAX;
> +
> +	if (!is_branch)
> +		return;
> +
> +	if (drm_dp_dpcd_read_data(connector->dp.dsc_decompression_aux,
> +				  DP_DSC_BRANCH_OVERALL_THROUGHPUT_0, branch_caps,
> +				  sizeof(branch_caps)) != 0)
> +		return;
> +
> +	connector->dp.dsc_branch_caps.overall_throughput.rgb_yuv444 =
> +		dsc_branch_overall_throughput(branch_caps[0]);
> +
> +	connector->dp.dsc_branch_caps.overall_throughput.yuv422_420 =
> +		dsc_branch_overall_throughput(branch_caps[1]);
> +
> +	if (branch_caps[2] != 0)
> +		connector->dp.dsc_branch_caps.max_line_width = branch_caps[2] * 320;

That max line width calculation should probably be a function as well
so that it can later be moved into some drm helper file along with the
other functions.

> +}
> +
>  void intel_dp_get_dsc_sink_cap(u8 dpcd_rev,
>  			       const struct drm_dp_desc *desc, bool is_branch,
>  			       struct intel_connector *connector)
> @@ -4219,6 +4271,8 @@ void intel_dp_get_dsc_sink_cap(u8 dpcd_rev,
>  	/* Clear fec_capable to avoid using stale values */
>  	connector->dp.fec_capability = 0;
>  
> +	memset(&connector->dp.dsc_branch_caps, 0, sizeof(connector->dp.dsc_branch_caps));
> +
>  	if (dpcd_rev < DP_DPCD_REV_14)
>  		return;
>  
> @@ -4233,6 +4287,11 @@ void intel_dp_get_dsc_sink_cap(u8 dpcd_rev,
>  
>  	drm_dbg_kms(display->drm, "FEC CAPABILITY: %x\n",
>  		    connector->dp.fec_capability);
> +
> +	if (!(connector->dp.dsc_dpcd[0] & DP_DSC_DECOMPRESSION_IS_SUPPORTED))
> +		return;
> +
> +	init_dsc_overall_throughput_limits(connector, is_branch);
>  }
>  
>  static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *connector)
> @@ -4241,6 +4300,9 @@ static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *
>  		return;
>  
>  	intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, connector->dp.dsc_dpcd);
> +
> +	if (connector->dp.dsc_dpcd[0] & DP_DSC_DECOMPRESSION_IS_SUPPORTED)
> +		init_dsc_overall_throughput_limits(connector, false);
>  }
>  
>  static void
> -- 
> 2.49.1

-- 
Ville Syrjälä
Intel

Re: [PATCH 4/5] drm/i915/dp: Verify branch devices' overall pixel throughput/line width

[Ville Syrjälä]

On Mon, Sep 22, 2025 at 10:35:42PM +0300, Ville Syrjälä wrote:
> On Fri, Sep 19, 2025 at 12:12:22AM +0300, Imre Deak wrote:
> > Read out the branch devices' maximum overall DSC pixel throughput and
> > line width and verify the mode's corresponding pixel clock and hactive
> > period against these.
> > 
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  .../drm/i915/display/intel_display_types.h    |  8 +++
> >  drivers/gpu/drm/i915/display/intel_dp.c       | 62 +++++++++++++++++++
> >  2 files changed, 70 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 358ab922d7a76..73bdafae604f8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -552,6 +552,14 @@ struct intel_connector {
> >  
> >  		u8 dsc_hblank_expansion_quirk:1;
> >  		u8 dsc_decompression_enabled:1;
> > +
> > +		struct {
> > +			struct {
> > +				int rgb_yuv444;
> > +				int yuv422_420;
> > +			} overall_throughput;
> > +			int max_line_width;
> > +		} dsc_branch_caps;
> >  	} dp;
> >  
> >  	struct {
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 8cc123b0fd752..dd082d2fcc968 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -1042,6 +1042,20 @@ u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
> >  	int tp_yuv422_420;
> >  	u8 val;
> >  
> > +	/*
> > +	 * TODO: Use the throughput value specific to the actual RGB/YUV
> > +	 * format of the output.
> > +	 * The RGB/YUV444 throughput value should be always either equal
> > +	 * or smaller than the YUV422/420 value, but let's not depend on
> > +	 * this assumption.
> > +	 */
> > +	if (mode_clock > max(connector->dp.dsc_branch_caps.overall_throughput.rgb_yuv444,
> > +			     connector->dp.dsc_branch_caps.overall_throughput.yuv422_420))
> > +		return 0;
> > +
> > +	if (mode_hdisplay > connector->dp.dsc_branch_caps.max_line_width)
> > +		return 0;
> 
> Looks like you only initialize these when the branch device supports
> decompression. What about a branch device that can do pass-through but
> no decompression? Should we even be checking these when doing
> pass-through?

Ah, we read them from the decompression_aux, which I presume is always
the thing that we want to do the decompression.

So in the passthrough case it will be the sink, and then we take the
early !is_branch exit from init_dsc_overall_throughput_limits().
Same for eDP.

> 
> > +
> >  	val = connector->dp.dsc_dpcd[DP_DSC_PEAK_THROUGHPUT - DP_DSC_SUPPORT];
> >  	tp_rgb_yuv444 = dsc_per_slice_throughput(display, mode_clock,
> >  						 REG_FIELD_GET8(DP_DSC_THROUGHPUT_MODE_0_MASK,
> > @@ -4204,6 +4218,44 @@ static void intel_dp_read_dsc_dpcd(struct drm_dp_aux *aux,
> >  		    dsc_dpcd);
> >  }
> >  
> > +static int dsc_branch_overall_throughput(u8 bw_code)
> > +{
> > +	switch (bw_code) {
> > +	case 0:
> > +		return INT_MAX;
> > +	case 1:
> > +		return 680000;
> > +	default:
> > +		return 600000 + 50000 * bw_code;
> > +	}
> > +}
> > +
> > +static void init_dsc_overall_throughput_limits(struct intel_connector *connector, bool is_branch)
> > +{
> > +	u8 branch_caps[3];
> > +
> > +	connector->dp.dsc_branch_caps.overall_throughput.rgb_yuv444 = INT_MAX;
> > +	connector->dp.dsc_branch_caps.overall_throughput.yuv422_420 = INT_MAX;
> > +	connector->dp.dsc_branch_caps.max_line_width = INT_MAX;
> > +
> > +	if (!is_branch)
> > +		return;
> > +
> > +	if (drm_dp_dpcd_read_data(connector->dp.dsc_decompression_aux,
> > +				  DP_DSC_BRANCH_OVERALL_THROUGHPUT_0, branch_caps,
> > +				  sizeof(branch_caps)) != 0)
> > +		return;
> > +
> > +	connector->dp.dsc_branch_caps.overall_throughput.rgb_yuv444 =
> > +		dsc_branch_overall_throughput(branch_caps[0]);
> > +
> > +	connector->dp.dsc_branch_caps.overall_throughput.yuv422_420 =
> > +		dsc_branch_overall_throughput(branch_caps[1]);
> > +
> > +	if (branch_caps[2] != 0)
> > +		connector->dp.dsc_branch_caps.max_line_width = branch_caps[2] * 320;
> 
> That max line width calculation should probably be a function as well
> so that it can later be moved into some drm helper file along with the
> other functions.
> 
> > +}
> > +
> >  void intel_dp_get_dsc_sink_cap(u8 dpcd_rev,
> >  			       const struct drm_dp_desc *desc, bool is_branch,
> >  			       struct intel_connector *connector)
> > @@ -4219,6 +4271,8 @@ void intel_dp_get_dsc_sink_cap(u8 dpcd_rev,
> >  	/* Clear fec_capable to avoid using stale values */
> >  	connector->dp.fec_capability = 0;
> >  
> > +	memset(&connector->dp.dsc_branch_caps, 0, sizeof(connector->dp.dsc_branch_caps));
> > +
> >  	if (dpcd_rev < DP_DPCD_REV_14)
> >  		return;
> >  
> > @@ -4233,6 +4287,11 @@ void intel_dp_get_dsc_sink_cap(u8 dpcd_rev,
> >  
> >  	drm_dbg_kms(display->drm, "FEC CAPABILITY: %x\n",
> >  		    connector->dp.fec_capability);
> > +
> > +	if (!(connector->dp.dsc_dpcd[0] & DP_DSC_DECOMPRESSION_IS_SUPPORTED))
> > +		return;
> > +
> > +	init_dsc_overall_throughput_limits(connector, is_branch);
> >  }
> >  
> >  static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *connector)
> > @@ -4241,6 +4300,9 @@ static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *
> >  		return;
> >  
> >  	intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, connector->dp.dsc_dpcd);
> > +
> > +	if (connector->dp.dsc_dpcd[0] & DP_DSC_DECOMPRESSION_IS_SUPPORTED)
> > +		init_dsc_overall_throughput_limits(connector, false);
> >  }
> >  
> >  static void
> > -- 
> > 2.49.1
> 
> -- 
> Ville Syrjälä
> Intel

-- 
Ville Syrjälä
Intel

Re: [PATCH 4/5] drm/i915/dp: Verify branch devices' overall pixel throughput/line width

[Imre Deak]

On Mon, Sep 22, 2025 at 11:06:02PM +0300, Ville Syrjälä wrote:
> On Mon, Sep 22, 2025 at 10:35:42PM +0300, Ville Syrjälä wrote:
> > On Fri, Sep 19, 2025 at 12:12:22AM +0300, Imre Deak wrote:
> > > Read out the branch devices' maximum overall DSC pixel throughput and
> > > line width and verify the mode's corresponding pixel clock and hactive
> > > period against these.
> > > 
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > ---
> > >  .../drm/i915/display/intel_display_types.h    |  8 +++
> > >  drivers/gpu/drm/i915/display/intel_dp.c       | 62 +++++++++++++++++++
> > >  2 files changed, 70 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index 358ab922d7a76..73bdafae604f8 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -552,6 +552,14 @@ struct intel_connector {
> > >  
> > >  		u8 dsc_hblank_expansion_quirk:1;
> > >  		u8 dsc_decompression_enabled:1;
> > > +
> > > +		struct {
> > > +			struct {
> > > +				int rgb_yuv444;
> > > +				int yuv422_420;
> > > +			} overall_throughput;
> > > +			int max_line_width;
> > > +		} dsc_branch_caps;
> > >  	} dp;
> > >  
> > >  	struct {
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > > index 8cc123b0fd752..dd082d2fcc968 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > @@ -1042,6 +1042,20 @@ u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
> > >  	int tp_yuv422_420;
> > >  	u8 val;
> > >  
> > > +	/*
> > > +	 * TODO: Use the throughput value specific to the actual RGB/YUV
> > > +	 * format of the output.
> > > +	 * The RGB/YUV444 throughput value should be always either equal
> > > +	 * or smaller than the YUV422/420 value, but let's not depend on
> > > +	 * this assumption.
> > > +	 */
> > > +	if (mode_clock > max(connector->dp.dsc_branch_caps.overall_throughput.rgb_yuv444,
> > > +			     connector->dp.dsc_branch_caps.overall_throughput.yuv422_420))
> > > +		return 0;
> > > +
> > > +	if (mode_hdisplay > connector->dp.dsc_branch_caps.max_line_width)
> > > +		return 0;
> > 
> > Looks like you only initialize these when the branch device supports
> > decompression. What about a branch device that can do pass-through but
> > no decompression? Should we even be checking these when doing
> > pass-through?
> 
> Ah, we read them from the decompression_aux, which I presume is always
> the thing that we want to do the decompression.
> 
> So in the passthrough case it will be the sink, and then we take the
> early !is_branch exit from init_dsc_overall_throughput_limits().

Yes, for both the decompress and pass-through case decompression_aux
points to the device decompressing the stream, and the caps will be read
out for that device.

In theory even in the pass-through case the decompressing device could
be an (SST-only) branch device, in which case the caps will be parsed
for that device as well. Granted I haven't seen such a device yet.

If DSC is not supported then the caps will be left zeroed.

If DSC is supported (either via pass-through or just decompression) by a
branch device then the caps will be either the device advertised ones,
or INT_MAX for caps which the device doesn't set a cap for (i.e. leaves
the DPCD reg at 0).

If DSC is supported by a non-branch device, then the caps will not be
read out and they will be set to INT_MAX.

> Same for eDP.

Yes, for eDP if DSC is not supported, the caps are set to 0, if DSC is
supported, the caps will be set to INT_MAX.

> > > +
> > >  	val = connector->dp.dsc_dpcd[DP_DSC_PEAK_THROUGHPUT - DP_DSC_SUPPORT];
> > >  	tp_rgb_yuv444 = dsc_per_slice_throughput(display, mode_clock,
> > >  						 REG_FIELD_GET8(DP_DSC_THROUGHPUT_MODE_0_MASK,
> > > @@ -4204,6 +4218,44 @@ static void intel_dp_read_dsc_dpcd(struct drm_dp_aux *aux,
> > >  		    dsc_dpcd);
> > >  }
> > >  
> > > +static int dsc_branch_overall_throughput(u8 bw_code)
> > > +{
> > > +	switch (bw_code) {
> > > +	case 0:
> > > +		return INT_MAX;
> > > +	case 1:
> > > +		return 680000;
> > > +	default:
> > > +		return 600000 + 50000 * bw_code;
> > > +	}
> > > +}
> > > +
> > > +static void init_dsc_overall_throughput_limits(struct intel_connector *connector, bool is_branch)
> > > +{
> > > +	u8 branch_caps[3];
> > > +
> > > +	connector->dp.dsc_branch_caps.overall_throughput.rgb_yuv444 = INT_MAX;
> > > +	connector->dp.dsc_branch_caps.overall_throughput.yuv422_420 = INT_MAX;
> > > +	connector->dp.dsc_branch_caps.max_line_width = INT_MAX;
> > > +
> > > +	if (!is_branch)
> > > +		return;
> > > +
> > > +	if (drm_dp_dpcd_read_data(connector->dp.dsc_decompression_aux,
> > > +				  DP_DSC_BRANCH_OVERALL_THROUGHPUT_0, branch_caps,
> > > +				  sizeof(branch_caps)) != 0)
> > > +		return;
> > > +
> > > +	connector->dp.dsc_branch_caps.overall_throughput.rgb_yuv444 =
> > > +		dsc_branch_overall_throughput(branch_caps[0]);
> > > +
> > > +	connector->dp.dsc_branch_caps.overall_throughput.yuv422_420 =
> > > +		dsc_branch_overall_throughput(branch_caps[1]);
> > > +
> > > +	if (branch_caps[2] != 0)
> > > +		connector->dp.dsc_branch_caps.max_line_width = branch_caps[2] * 320;
> > 
> > That max line width calculation should probably be a function as well
> > so that it can later be moved into some drm helper file along with the
> > other functions.

Ok, I added a DRM helper instead as in:
https://github.com/ideak/linux/commit/7f7cab2746f4

> > 
> > > +}
> > > +
> > >  void intel_dp_get_dsc_sink_cap(u8 dpcd_rev,
> > >  			       const struct drm_dp_desc *desc, bool is_branch,
> > >  			       struct intel_connector *connector)
> > > @@ -4219,6 +4271,8 @@ void intel_dp_get_dsc_sink_cap(u8 dpcd_rev,
> > >  	/* Clear fec_capable to avoid using stale values */
> > >  	connector->dp.fec_capability = 0;
> > >  
> > > +	memset(&connector->dp.dsc_branch_caps, 0, sizeof(connector->dp.dsc_branch_caps));
> > > +
> > >  	if (dpcd_rev < DP_DPCD_REV_14)
> > >  		return;
> > >  
> > > @@ -4233,6 +4287,11 @@ void intel_dp_get_dsc_sink_cap(u8 dpcd_rev,
> > >  
> > >  	drm_dbg_kms(display->drm, "FEC CAPABILITY: %x\n",
> > >  		    connector->dp.fec_capability);
> > > +
> > > +	if (!(connector->dp.dsc_dpcd[0] & DP_DSC_DECOMPRESSION_IS_SUPPORTED))
> > > +		return;
> > > +
> > > +	init_dsc_overall_throughput_limits(connector, is_branch);
> > >  }
> > >  
> > >  static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *connector)
> > > @@ -4241,6 +4300,9 @@ static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *
> > >  		return;
> > >  
> > >  	intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, connector->dp.dsc_dpcd);
> > > +
> > > +	if (connector->dp.dsc_dpcd[0] & DP_DSC_DECOMPRESSION_IS_SUPPORTED)
> > > +		init_dsc_overall_throughput_limits(connector, false);
> > >  }
> > >  
> > >  static void
> > > -- 
> > > 2.49.1
> > 
> > -- 
> > Ville Syrjälä
> > Intel
> 
> -- 
> Ville Syrjälä
> Intel

[PATCH 5/5] drm/i915/dp: Handle Synaptics DSC throughput link-bpp quirk

[Imre Deak]

Handle the DSC pixel throughput quirk, limiting the compressed link-bpp
value for Synaptics Panamera branch devices, working around a
blank/unstable output issue observed on docking stations containing
these branch devices, when using a mode with a high pixel clock and a
high compressed link-bpp value.

For now use the same mode clock limit for RGB/YUV444 and YUV422/420
output modes. This may result in limiting the link-bpp value for a
YUV422/420 output mode already at a lower than required mode clock.

Reported-by: Vidya Srinivas <vidya.srinivas@intel.com>
Reported-by: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 57 +++++++++++++++++++
 2 files changed, 58 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 73bdafae604f8..aff63bf0f2294 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -551,6 +551,7 @@ struct intel_connector {
 		u8 fec_capability;
 
 		u8 dsc_hblank_expansion_quirk:1;
+		u8 dsc_throughput_quirk:1;
 		u8 dsc_decompression_enabled:1;
 
 		struct {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index dd082d2fcc968..7cc9364f9af88 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2509,6 +2509,56 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 	return 0;
 }
 
+static void
+adjust_limits_for_dsc_throughput_quirk(const struct intel_connector *connector,
+				       const struct intel_crtc_state *crtc_state,
+				       struct link_config_limits *limits)
+{
+	struct intel_display *display = to_intel_display(connector);
+	const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	const struct drm_display_mode *adjusted_mode =
+		&crtc_state->hw.adjusted_mode;
+	int max_bpp_x16;
+
+	if (!connector->dp.dsc_throughput_quirk)
+		return;
+
+	/*
+	 * Synaptics Panamera branch devices have a problem decompressing a
+	 * stream with a compressed link-bpp higher than 12, if the pixel
+	 * clock is higher than ~50 % of the maximum overall throughput
+	 * reported by the branch device. Work around this by limiting the
+	 * maximum link bpp for such pixel clocks.
+	 *
+	 * TODO: Use the throughput value specific to the actual RGB/YUV
+	 * format of the output, after determining the pixel clock limit for
+	 * YUV modes. For now use the smaller of the throughput values, which
+	 * may result in limiting the link-bpp value already at a lower than
+	 * required mode clock in case of native YUV422/420 output formats.
+	 * The RGB/YUV444 throughput value should be always either equal or
+	 * smaller than the YUV422/420 value, but let's not depend on this
+	 * assumption.
+	 */
+	if (adjusted_mode->crtc_clock <
+	    min(connector->dp.dsc_branch_caps.overall_throughput.rgb_yuv444,
+		connector->dp.dsc_branch_caps.overall_throughput.yuv422_420) / 2)
+		return;
+
+	max_bpp_x16 = clamp(fxp_q4_from_int(12),
+			    limits->link.min_bpp_x16, limits->link.max_bpp_x16);
+
+	if (max_bpp_x16 >= limits->link.max_bpp_x16)
+		return;
+
+	drm_dbg_kms(display->drm,
+		    "[CRTC:%d:%s][CONNECTOR:%d:%s] Decreasing link max bpp to " FXP_Q4_FMT " due to DSC throughput quirk\n",
+		    crtc->base.base.id, crtc->base.name,
+		    connector->base.base.id, connector->base.name,
+		    FXP_Q4_ARGS(max_bpp_x16));
+
+	limits->link.max_bpp_x16 = max_bpp_x16;
+}
+
 /*
  * Calculate the output link min, max bpp values in limits based on the pipe bpp
  * range, crtc_state and dsc mode. Return true on success.
@@ -2558,6 +2608,8 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
 
 	limits->link.max_bpp_x16 = max_link_bpp_x16;
 
+	adjust_limits_for_dsc_throughput_quirk(connector, crtc_state, limits);
+
 	drm_dbg_kms(display->drm,
 		    "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " FXP_Q4_FMT "\n",
 		    encoder->base.base.id, encoder->base.name,
@@ -4272,6 +4324,7 @@ void intel_dp_get_dsc_sink_cap(u8 dpcd_rev,
 	connector->dp.fec_capability = 0;
 
 	memset(&connector->dp.dsc_branch_caps, 0, sizeof(connector->dp.dsc_branch_caps));
+	connector->dp.dsc_throughput_quirk = false;
 
 	if (dpcd_rev < DP_DPCD_REV_14)
 		return;
@@ -4292,6 +4345,10 @@ void intel_dp_get_dsc_sink_cap(u8 dpcd_rev,
 		return;
 
 	init_dsc_overall_throughput_limits(connector, is_branch);
+
+	if (drm_dp_has_quirk(desc, DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT) &&
+	    desc->ident.hw_rev == 0x10)
+		connector->dp.dsc_throughput_quirk = true;
 }
 
 static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *connector)
-- 
2.49.1

[PATCH v2 5/5] drm/i915/dp: Handle Synaptics DSC throughput link-bpp quirk

[Imre Deak]

Handle the DSC pixel throughput quirk, limiting the compressed link-bpp
value for Synaptics Panamera branch devices, working around a
blank/unstable output issue observed on docking stations containing
these branch devices, when using a mode with a high pixel clock and a
high compressed link-bpp value.

For now use the same mode clock limit for RGB/YUV444 and YUV422/420
output modes. This may result in limiting the link-bpp value for a
YUV422/420 output mode already at a lower than required mode clock.

v2: Apply the quirk only when DSC is enabled.

Reported-by: Vidya Srinivas <vidya.srinivas@intel.com>
Reported-by: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 58 +++++++++++++++++++
 2 files changed, 59 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 73bdafae604f..aff63bf0f229 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -551,6 +551,7 @@ struct intel_connector {
 		u8 fec_capability;
 
 		u8 dsc_hblank_expansion_quirk:1;
+		u8 dsc_throughput_quirk:1;
 		u8 dsc_decompression_enabled:1;
 
 		struct {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index dd082d2fcc96..5e7aea560910 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2509,6 +2509,56 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 	return 0;
 }
 
+static void
+adjust_limits_for_dsc_throughput_quirk(const struct intel_connector *connector,
+				       const struct intel_crtc_state *crtc_state,
+				       struct link_config_limits *limits)
+{
+	struct intel_display *display = to_intel_display(connector);
+	const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	const struct drm_display_mode *adjusted_mode =
+		&crtc_state->hw.adjusted_mode;
+	int max_bpp_x16;
+
+	if (!connector->dp.dsc_throughput_quirk)
+		return;
+
+	/*
+	 * Synaptics Panamera branch devices have a problem decompressing a
+	 * stream with a compressed link-bpp higher than 12, if the pixel
+	 * clock is higher than ~50 % of the maximum overall throughput
+	 * reported by the branch device. Work around this by limiting the
+	 * maximum link bpp for such pixel clocks.
+	 *
+	 * TODO: Use the throughput value specific to the actual RGB/YUV
+	 * format of the output, after determining the pixel clock limit for
+	 * YUV modes. For now use the smaller of the throughput values, which
+	 * may result in limiting the link-bpp value already at a lower than
+	 * required mode clock in case of native YUV422/420 output formats.
+	 * The RGB/YUV444 throughput value should be always either equal or
+	 * smaller than the YUV422/420 value, but let's not depend on this
+	 * assumption.
+	 */
+	if (adjusted_mode->crtc_clock <
+	    min(connector->dp.dsc_branch_caps.overall_throughput.rgb_yuv444,
+		connector->dp.dsc_branch_caps.overall_throughput.yuv422_420) / 2)
+		return;
+
+	max_bpp_x16 = clamp(fxp_q4_from_int(12),
+			    limits->link.min_bpp_x16, limits->link.max_bpp_x16);
+
+	if (max_bpp_x16 >= limits->link.max_bpp_x16)
+		return;
+
+	drm_dbg_kms(display->drm,
+		    "[CRTC:%d:%s][CONNECTOR:%d:%s] Decreasing link max bpp to " FXP_Q4_FMT " due to DSC throughput quirk\n",
+		    crtc->base.base.id, crtc->base.name,
+		    connector->base.base.id, connector->base.name,
+		    FXP_Q4_ARGS(max_bpp_x16));
+
+	limits->link.max_bpp_x16 = max_bpp_x16;
+}
+
 /*
  * Calculate the output link min, max bpp values in limits based on the pipe bpp
  * range, crtc_state and dsc mode. Return true on success.
@@ -2558,6 +2608,9 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
 
 	limits->link.max_bpp_x16 = max_link_bpp_x16;
 
+	if (dsc)
+		adjust_limits_for_dsc_throughput_quirk(connector, crtc_state, limits);
+
 	drm_dbg_kms(display->drm,
 		    "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " FXP_Q4_FMT "\n",
 		    encoder->base.base.id, encoder->base.name,
@@ -4272,6 +4325,7 @@ void intel_dp_get_dsc_sink_cap(u8 dpcd_rev,
 	connector->dp.fec_capability = 0;
 
 	memset(&connector->dp.dsc_branch_caps, 0, sizeof(connector->dp.dsc_branch_caps));
+	connector->dp.dsc_throughput_quirk = false;
 
 	if (dpcd_rev < DP_DPCD_REV_14)
 		return;
@@ -4292,6 +4346,10 @@ void intel_dp_get_dsc_sink_cap(u8 dpcd_rev,
 		return;
 
 	init_dsc_overall_throughput_limits(connector, is_branch);
+
+	if (drm_dp_has_quirk(desc, DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT) &&
+	    desc->ident.hw_rev == 0x10)
+		connector->dp.dsc_throughput_quirk = true;
 }
 
 static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *connector)
-- 
2.49.1

Re: [PATCH v2 5/5] drm/i915/dp: Handle Synaptics DSC throughput link-bpp quirk

[Ville Syrjälä]

On Mon, Sep 22, 2025 at 04:46:37PM +0300, Imre Deak wrote:
> Handle the DSC pixel throughput quirk, limiting the compressed link-bpp
> value for Synaptics Panamera branch devices, working around a
> blank/unstable output issue observed on docking stations containing
> these branch devices, when using a mode with a high pixel clock and a
> high compressed link-bpp value.
> 
> For now use the same mode clock limit for RGB/YUV444 and YUV422/420
> output modes. This may result in limiting the link-bpp value for a
> YUV422/420 output mode already at a lower than required mode clock.
> 
> v2: Apply the quirk only when DSC is enabled.
> 
> Reported-by: Vidya Srinivas <vidya.srinivas@intel.com>
> Reported-by: Swati Sharma <swati2.sharma@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  .../drm/i915/display/intel_display_types.h    |  1 +
>  drivers/gpu/drm/i915/display/intel_dp.c       | 58 +++++++++++++++++++
>  2 files changed, 59 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 73bdafae604f..aff63bf0f229 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -551,6 +551,7 @@ struct intel_connector {
>  		u8 fec_capability;
>  
>  		u8 dsc_hblank_expansion_quirk:1;
> +		u8 dsc_throughput_quirk:1;
>  		u8 dsc_decompression_enabled:1;
>  
>  		struct {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index dd082d2fcc96..5e7aea560910 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2509,6 +2509,56 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
>  	return 0;
>  }
>  
> +static void
> +adjust_limits_for_dsc_throughput_quirk(const struct intel_connector *connector,
> +				       const struct intel_crtc_state *crtc_state,
> +				       struct link_config_limits *limits)
> +{
> +	struct intel_display *display = to_intel_display(connector);
> +	const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	const struct drm_display_mode *adjusted_mode =
> +		&crtc_state->hw.adjusted_mode;
> +	int max_bpp_x16;
> +
> +	if (!connector->dp.dsc_throughput_quirk)
> +		return;
> +
> +	/*
> +	 * Synaptics Panamera branch devices have a problem decompressing a
> +	 * stream with a compressed link-bpp higher than 12, if the pixel
> +	 * clock is higher than ~50 % of the maximum overall throughput
> +	 * reported by the branch device. Work around this by limiting the
> +	 * maximum link bpp for such pixel clocks.
> +	 *
> +	 * TODO: Use the throughput value specific to the actual RGB/YUV
> +	 * format of the output, after determining the pixel clock limit for
> +	 * YUV modes. For now use the smaller of the throughput values, which
> +	 * may result in limiting the link-bpp value already at a lower than
> +	 * required mode clock in case of native YUV422/420 output formats.
> +	 * The RGB/YUV444 throughput value should be always either equal or
> +	 * smaller than the YUV422/420 value, but let's not depend on this
> +	 * assumption.
> +	 */
> +	if (adjusted_mode->crtc_clock <
> +	    min(connector->dp.dsc_branch_caps.overall_throughput.rgb_yuv444,
> +		connector->dp.dsc_branch_caps.overall_throughput.yuv422_420) / 2)
> +		return;
> +
> +	max_bpp_x16 = clamp(fxp_q4_from_int(12),
> +			    limits->link.min_bpp_x16, limits->link.max_bpp_x16);
> +
> +	if (max_bpp_x16 >= limits->link.max_bpp_x16)
> +		return;
> +
> +	drm_dbg_kms(display->drm,
> +		    "[CRTC:%d:%s][CONNECTOR:%d:%s] Decreasing link max bpp to " FXP_Q4_FMT " due to DSC throughput quirk\n",
> +		    crtc->base.base.id, crtc->base.name,
> +		    connector->base.base.id, connector->base.name,
> +		    FXP_Q4_ARGS(max_bpp_x16));
> +
> +	limits->link.max_bpp_x16 = max_bpp_x16;
> +}
> +
>  /*
>   * Calculate the output link min, max bpp values in limits based on the pipe bpp
>   * range, crtc_state and dsc mode. Return true on success.
> @@ -2558,6 +2608,9 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
>  
>  	limits->link.max_bpp_x16 = max_link_bpp_x16;
>  
> +	if (dsc)
> +		adjust_limits_for_dsc_throughput_quirk(connector, crtc_state, limits);

Would feel cleaner if we did this in the actual dsc==true branch above.
Maybe the actual thing that determines that max bpp should be some kind
of pure function that returns the max acceptable bpp, and then the
caller can deal with it.

Or at least move the 'limits->link.max_bpp_x16 = max_link_bpp_x16' into both
!dsc and dsc branches. That way we don't have this strange looking drop out
from the if statement just to do the single assignment, and then going back in.

> +
>  	drm_dbg_kms(display->drm,
>  		    "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " FXP_Q4_FMT "\n",
>  		    encoder->base.base.id, encoder->base.name,
> @@ -4272,6 +4325,7 @@ void intel_dp_get_dsc_sink_cap(u8 dpcd_rev,
>  	connector->dp.fec_capability = 0;
>  
>  	memset(&connector->dp.dsc_branch_caps, 0, sizeof(connector->dp.dsc_branch_caps));
> +	connector->dp.dsc_throughput_quirk = false;
>  
>  	if (dpcd_rev < DP_DPCD_REV_14)
>  		return;
> @@ -4292,6 +4346,10 @@ void intel_dp_get_dsc_sink_cap(u8 dpcd_rev,
>  		return;
>  
>  	init_dsc_overall_throughput_limits(connector, is_branch);
> +
> +	if (drm_dp_has_quirk(desc, DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT) &&
> +	    desc->ident.hw_rev == 0x10)

Rather annoying to have part of the detection here and part in the
quirk list. Can we extend the quirk framework to support hw revisions
as well?

Could be a followup.

> +		connector->dp.dsc_throughput_quirk = true;
>  }
>  
>  static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *connector)
> -- 
> 2.49.1

-- 
Ville Syrjälä
Intel

Re: [PATCH v2 5/5] drm/i915/dp: Handle Synaptics DSC throughput link-bpp quirk

[Imre Deak]

On Mon, Sep 22, 2025 at 11:17:47PM +0300, Ville Syrjälä wrote:
> On Mon, Sep 22, 2025 at 04:46:37PM +0300, Imre Deak wrote:
> > Handle the DSC pixel throughput quirk, limiting the compressed link-bpp
> > value for Synaptics Panamera branch devices, working around a
> > blank/unstable output issue observed on docking stations containing
> > these branch devices, when using a mode with a high pixel clock and a
> > high compressed link-bpp value.
> > 
> > For now use the same mode clock limit for RGB/YUV444 and YUV422/420
> > output modes. This may result in limiting the link-bpp value for a
> > YUV422/420 output mode already at a lower than required mode clock.
> > 
> > v2: Apply the quirk only when DSC is enabled.
> > 
> > Reported-by: Vidya Srinivas <vidya.srinivas@intel.com>
> > Reported-by: Swati Sharma <swati2.sharma@intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  .../drm/i915/display/intel_display_types.h    |  1 +
> >  drivers/gpu/drm/i915/display/intel_dp.c       | 58 +++++++++++++++++++
> >  2 files changed, 59 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 73bdafae604f..aff63bf0f229 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -551,6 +551,7 @@ struct intel_connector {
> >  		u8 fec_capability;
> >  
> >  		u8 dsc_hblank_expansion_quirk:1;
> > +		u8 dsc_throughput_quirk:1;
> >  		u8 dsc_decompression_enabled:1;
> >  
> >  		struct {
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > index dd082d2fcc96..5e7aea560910 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -2509,6 +2509,56 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> >  	return 0;
> >  }
> >  
> > +static void
> > +adjust_limits_for_dsc_throughput_quirk(const struct intel_connector *connector,
> > +				       const struct intel_crtc_state *crtc_state,
> > +				       struct link_config_limits *limits)
> > +{
> > +	struct intel_display *display = to_intel_display(connector);
> > +	const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > +	const struct drm_display_mode *adjusted_mode =
> > +		&crtc_state->hw.adjusted_mode;
> > +	int max_bpp_x16;
> > +
> > +	if (!connector->dp.dsc_throughput_quirk)
> > +		return;
> > +
> > +	/*
> > +	 * Synaptics Panamera branch devices have a problem decompressing a
> > +	 * stream with a compressed link-bpp higher than 12, if the pixel
> > +	 * clock is higher than ~50 % of the maximum overall throughput
> > +	 * reported by the branch device. Work around this by limiting the
> > +	 * maximum link bpp for such pixel clocks.
> > +	 *
> > +	 * TODO: Use the throughput value specific to the actual RGB/YUV
> > +	 * format of the output, after determining the pixel clock limit for
> > +	 * YUV modes. For now use the smaller of the throughput values, which
> > +	 * may result in limiting the link-bpp value already at a lower than
> > +	 * required mode clock in case of native YUV422/420 output formats.
> > +	 * The RGB/YUV444 throughput value should be always either equal or
> > +	 * smaller than the YUV422/420 value, but let's not depend on this
> > +	 * assumption.
> > +	 */
> > +	if (adjusted_mode->crtc_clock <
> > +	    min(connector->dp.dsc_branch_caps.overall_throughput.rgb_yuv444,
> > +		connector->dp.dsc_branch_caps.overall_throughput.yuv422_420) / 2)
> > +		return;
> > +
> > +	max_bpp_x16 = clamp(fxp_q4_from_int(12),
> > +			    limits->link.min_bpp_x16, limits->link.max_bpp_x16);
> > +
> > +	if (max_bpp_x16 >= limits->link.max_bpp_x16)
> > +		return;
> > +
> > +	drm_dbg_kms(display->drm,
> > +		    "[CRTC:%d:%s][CONNECTOR:%d:%s] Decreasing link max bpp to " FXP_Q4_FMT " due to DSC throughput quirk\n",
> > +		    crtc->base.base.id, crtc->base.name,
> > +		    connector->base.base.id, connector->base.name,
> > +		    FXP_Q4_ARGS(max_bpp_x16));
> > +
> > +	limits->link.max_bpp_x16 = max_bpp_x16;
> > +}
> > +
> >  /*
> >   * Calculate the output link min, max bpp values in limits based on the pipe bpp
> >   * range, crtc_state and dsc mode. Return true on success.
> > @@ -2558,6 +2608,9 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
> >  
> >  	limits->link.max_bpp_x16 = max_link_bpp_x16;
> >  
> > +	if (dsc)
> > +		adjust_limits_for_dsc_throughput_quirk(connector, crtc_state, limits);
> 
> Would feel cleaner if we did this in the actual dsc==true branch above.
> Maybe the actual thing that determines that max bpp should be some kind
> of pure function that returns the max acceptable bpp, and then the
> caller can deal with it.

Ok, did this now as in
https://github.com/ideak/linux/commit/25edc09658439

> Or at least move the 'limits->link.max_bpp_x16 = max_link_bpp_x16' into both
> !dsc and dsc branches. That way we don't have this strange looking drop out
> from the if statement just to do the single assignment, and then going back in.
> 
> > +
> >  	drm_dbg_kms(display->drm,
> >  		    "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " FXP_Q4_FMT "\n",
> >  		    encoder->base.base.id, encoder->base.name,
> > @@ -4272,6 +4325,7 @@ void intel_dp_get_dsc_sink_cap(u8 dpcd_rev,
> >  	connector->dp.fec_capability = 0;
> >  
> >  	memset(&connector->dp.dsc_branch_caps, 0, sizeof(connector->dp.dsc_branch_caps));
> > +	connector->dp.dsc_throughput_quirk = false;
> >  
> >  	if (dpcd_rev < DP_DPCD_REV_14)
> >  		return;
> > @@ -4292,6 +4346,10 @@ void intel_dp_get_dsc_sink_cap(u8 dpcd_rev,
> >  		return;
> >  
> >  	init_dsc_overall_throughput_limits(connector, is_branch);
> > +
> > +	if (drm_dp_has_quirk(desc, DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT) &&
> > +	    desc->ident.hw_rev == 0x10)
> 
> Rather annoying to have part of the detection here and part in the
> quirk list. Can we extend the quirk framework to support hw revisions
> as well?
> 
> Could be a followup.

Yes, agreed that this should be part of the DRM quirk table. I'd like to
get a clarification about the list of affected devices. Based on that
clarification this rev check may not be required. So for now I'd leave
this here with a TODO comment.

> 
> > +		connector->dp.dsc_throughput_quirk = true;
> >  }
> >  
> >  static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *connector)
> > -- 
> > 2.49.1
> 
> -- 
> Ville Syrjälä
> Intel

[PATCH v4 5/5] drm/i915/dp: Handle Synaptics DSC throughput link-bpp quirk

[Imre Deak]

Handle the DSC pixel throughput quirk, limiting the compressed link-bpp
value for Synaptics Panamera branch devices, working around a
blank/unstable output issue observed on docking stations containing
these branch devices, when using a mode with a high pixel clock and a
high compressed link-bpp value.

For now use the same mode clock limit for RGB/YUV444 and YUV422/420
output modes. This may result in limiting the link-bpp value for a
YUV422/420 output mode already at a lower than required mode clock.

v2: Apply the quirk only when DSC is enabled.
v3 (Ville):
- Move adjustment of link-bpp within the already existing is_dsc
  if branch.
- Add TODO comment to move the HW revision check as well to the
  DRM core quirk table.
v4:
- Fix incorrect fxp_q4_from_int(INT_MAX) vs. INT_MAX return value
  from dsc_throughput_quirk_max_bpp_x16().

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reported-by: Vidya Srinivas <vidya.srinivas@intel.com>
Reported-by: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 57 +++++++++++++++++++
 2 files changed, 58 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 99d2c31236928..ca5a87772e93a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -551,6 +551,7 @@ struct intel_connector {
 		u8 fec_capability;
 
 		u8 dsc_hblank_expansion_quirk:1;
+		u8 dsc_throughput_quirk:1;
 		u8 dsc_decompression_enabled:1;
 
 		struct {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index d7ee17d3f75a6..14df3792554e5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2480,6 +2480,40 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 	return 0;
 }
 
+static int
+dsc_throughput_quirk_max_bpp_x16(const struct intel_connector *connector,
+				 const struct intel_crtc_state *crtc_state)
+{
+	const struct drm_display_mode *adjusted_mode =
+		&crtc_state->hw.adjusted_mode;
+
+	if (!connector->dp.dsc_throughput_quirk)
+		return INT_MAX;
+
+	/*
+	 * Synaptics Panamera branch devices have a problem decompressing a
+	 * stream with a compressed link-bpp higher than 12, if the pixel
+	 * clock is higher than ~50 % of the maximum overall throughput
+	 * reported by the branch device. Work around this by limiting the
+	 * maximum link bpp for such pixel clocks.
+	 *
+	 * TODO: Use the throughput value specific to the actual RGB/YUV
+	 * format of the output, after determining the pixel clock limit for
+	 * YUV modes. For now use the smaller of the throughput values, which
+	 * may result in limiting the link-bpp value already at a lower than
+	 * required mode clock in case of native YUV422/420 output formats.
+	 * The RGB/YUV444 throughput value should be always either equal or
+	 * smaller than the YUV422/420 value, but let's not depend on this
+	 * assumption.
+	 */
+	if (adjusted_mode->crtc_clock <
+	    min(connector->dp.dsc_branch_caps.overall_throughput.rgb_yuv444,
+		connector->dp.dsc_branch_caps.overall_throughput.yuv422_420) / 2)
+		return INT_MAX;
+
+	return fxp_q4_from_int(12);
+}
+
 /*
  * Calculate the output link min, max bpp values in limits based on the pipe bpp
  * range, crtc_state and dsc mode. Return true on success.
@@ -2511,6 +2545,7 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
 	} else {
 		int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
 		int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
+		int throughput_max_bpp_x16;
 
 		dsc_src_min_bpp = intel_dp_dsc_min_src_compressed_bpp();
 		dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(crtc_state);
@@ -2525,6 +2560,19 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
 			      min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
 
 		max_link_bpp_x16 = min(max_link_bpp_x16, fxp_q4_from_int(dsc_max_bpp));
+
+		throughput_max_bpp_x16 = dsc_throughput_quirk_max_bpp_x16(connector, crtc_state);
+		throughput_max_bpp_x16 = clamp(throughput_max_bpp_x16,
+					       limits->link.min_bpp_x16, max_link_bpp_x16);
+		if (throughput_max_bpp_x16 < max_link_bpp_x16) {
+			max_link_bpp_x16 = throughput_max_bpp_x16;
+
+			drm_dbg_kms(display->drm,
+				    "[CRTC:%d:%s][CONNECTOR:%d:%s] Decreasing link max bpp to " FXP_Q4_FMT " due to DSC throughput quirk\n",
+				    crtc->base.base.id, crtc->base.name,
+				    connector->base.base.id, connector->base.name,
+				    FXP_Q4_ARGS(max_link_bpp_x16));
+		}
 	}
 
 	limits->link.max_bpp_x16 = max_link_bpp_x16;
@@ -4232,6 +4280,7 @@ void intel_dp_get_dsc_sink_cap(u8 dpcd_rev,
 	connector->dp.fec_capability = 0;
 
 	memset(&connector->dp.dsc_branch_caps, 0, sizeof(connector->dp.dsc_branch_caps));
+	connector->dp.dsc_throughput_quirk = false;
 
 	if (dpcd_rev < DP_DPCD_REV_14)
 		return;
@@ -4252,6 +4301,14 @@ void intel_dp_get_dsc_sink_cap(u8 dpcd_rev,
 		return;
 
 	init_dsc_overall_throughput_limits(connector, is_branch);
+
+	/*
+	 * TODO: Move the HW rev check as well to the DRM core quirk table if
+	 * that's required after clarifying the list of affected devices.
+	 */
+	if (drm_dp_has_quirk(desc, DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT) &&
+	    desc->ident.hw_rev == 0x10)
+		connector->dp.dsc_throughput_quirk = true;
 }
 
 static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *connector)
-- 
2.49.1

✗ CI.checkpatch: warning for drm/i915/dp: Work around a DSC pixel throughput issue

[Patchwork]

== Series Details ==

Series: drm/i915/dp: Work around a DSC pixel throughput issue
URL   : https://patchwork.freedesktop.org/series/154737/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
fbd08a78c3a3bb17964db2a326514c69c1dca660
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 8fa8e5f5711e1e6681f59a6cb3f2a42c43bec987
Author: Imre Deak <imre.deak@intel.com>
Date:   Fri Sep 19 00:12:23 2025 +0300

    drm/i915/dp: Handle Synaptics DSC throughput link-bpp quirk
    
    Handle the DSC pixel throughput quirk, limiting the compressed link-bpp
    value for Synaptics Panamera branch devices, working around a
    blank/unstable output issue observed on docking stations containing
    these branch devices, when using a mode with a high pixel clock and a
    high compressed link-bpp value.
    
    For now use the same mode clock limit for RGB/YUV444 and YUV422/420
    output modes. This may result in limiting the link-bpp value for a
    YUV422/420 output mode already at a lower than required mode clock.
    
    Reported-by: Vidya Srinivas <vidya.srinivas@intel.com>
    Reported-by: Swati Sharma <swati2.sharma@intel.com>
    Signed-off-by: Imre Deak <imre.deak@intel.com>
+ /mt/dim checkpatch 3e79699fa1b216e9246e406a8649235e894772d2 drm-intel
3c182ded4953 drm/dp: Add quirk for Synaptics DSC throughput link-bpp limit
-:40: WARNING:BAD_REPORTED_BY_LINK: Reported-by: should be immediately followed by Closes: with a URL to the report
#40: 
Reported-by: Vidya Srinivas <vidya.srinivas@intel.com>
Reported-by: Swati Sharma <swati2.sharma@intel.com>

-:41: WARNING:BAD_REPORTED_BY_LINK: Reported-by: should be immediately followed by Closes: with a URL to the report
#41: 
Reported-by: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>

-:52: WARNING:LONG_LINE_COMMENT: line length of 104 exceeds 100 columns
#52: FILE: drivers/gpu/drm/display/drm_dp_helper.c:2546:
+	/* Synaptics PANAMERA branch devices having a pixel clock dependent DSC compressed bpp limit. */

-:53: WARNING:LONG_LINE: line length of 128 exceeds 100 columns
#53: FILE: drivers/gpu/drm/display/drm_dp_helper.c:2547:
+	{ OUI(0x90, 0xCC, 0x24), DEVICE_ID('S', 'Y', 'N', 'A', 0x53, 0x22), true, BIT(DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT) },

-:54: WARNING:LONG_LINE: line length of 128 exceeds 100 columns
#54: FILE: drivers/gpu/drm/display/drm_dp_helper.c:2548:
+	{ OUI(0x90, 0xCC, 0x24), DEVICE_ID('S', 'Y', 'N', 'A', 0x53, 0x31), true, BIT(DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT) },

-:55: WARNING:LONG_LINE: line length of 128 exceeds 100 columns
#55: FILE: drivers/gpu/drm/display/drm_dp_helper.c:2549:
+	{ OUI(0x90, 0xCC, 0x24), DEVICE_ID('S', 'Y', 'N', 'A', 0x53, 0x33), true, BIT(DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT) },

total: 0 errors, 6 warnings, 0 checks, 20 lines checked
845a8e72f9d5 drm/i915/dp: Calculate DSC slice count based on per-slice peak throughput
ff44afce21a6 drm/i915/dp: Pass DPCD device descriptor to intel_dp_get_dsc_sink_cap()
3f2501ed47a6 drm/i915/dp: Verify branch devices' overall pixel throughput/line width
8fa8e5f5711e drm/i915/dp: Handle Synaptics DSC throughput link-bpp quirk
-:16: WARNING:BAD_REPORTED_BY_LINK: Reported-by: should be immediately followed by Closes: with a URL to the report
#16: 
Reported-by: Vidya Srinivas <vidya.srinivas@intel.com>
Reported-by: Swati Sharma <swati2.sharma@intel.com>

-:17: WARNING:BAD_REPORTED_BY_LINK: Reported-by: should be immediately followed by Closes: with a URL to the report
#17: 
Reported-by: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>

total: 0 errors, 2 warnings, 0 checks, 88 lines checked

✓ CI.KUnit: success for drm/i915/dp: Work around a DSC pixel throughput issue

[Patchwork]

== Series Details ==

Series: drm/i915/dp: Work around a DSC pixel throughput issue
URL   : https://patchwork.freedesktop.org/series/154737/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[21:57:11] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:57:15] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[21:57:45] Starting KUnit Kernel (1/1)...
[21:57:45] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:57:45] ================== guc_buf (11 subtests) ===================
[21:57:45] [PASSED] test_smallest
[21:57:45] [PASSED] test_largest
[21:57:45] [PASSED] test_granular
[21:57:45] [PASSED] test_unique
[21:57:45] [PASSED] test_overlap
[21:57:45] [PASSED] test_reusable
[21:57:45] [PASSED] test_too_big
[21:57:45] [PASSED] test_flush
[21:57:45] [PASSED] test_lookup
[21:57:45] [PASSED] test_data
[21:57:45] [PASSED] test_class
[21:57:45] ===================== [PASSED] guc_buf =====================
[21:57:45] =================== guc_dbm (7 subtests) ===================
[21:57:45] [PASSED] test_empty
[21:57:45] [PASSED] test_default
[21:57:45] ======================== test_size  ========================
[21:57:45] [PASSED] 4
[21:57:45] [PASSED] 8
[21:57:45] [PASSED] 32
[21:57:45] [PASSED] 256
[21:57:45] ==================== [PASSED] test_size ====================
[21:57:45] ======================= test_reuse  ========================
[21:57:45] [PASSED] 4
[21:57:45] [PASSED] 8
[21:57:45] [PASSED] 32
[21:57:45] [PASSED] 256
[21:57:45] =================== [PASSED] test_reuse ====================
[21:57:45] =================== test_range_overlap  ====================
[21:57:45] [PASSED] 4
[21:57:45] [PASSED] 8
[21:57:45] [PASSED] 32
[21:57:45] [PASSED] 256
[21:57:45] =============== [PASSED] test_range_overlap ================
[21:57:45] =================== test_range_compact  ====================
[21:57:45] [PASSED] 4
[21:57:45] [PASSED] 8
[21:57:45] [PASSED] 32
[21:57:45] [PASSED] 256
[21:57:45] =============== [PASSED] test_range_compact ================
[21:57:45] ==================== test_range_spare  =====================
[21:57:45] [PASSED] 4
[21:57:45] [PASSED] 8
[21:57:45] [PASSED] 32
[21:57:45] [PASSED] 256
[21:57:45] ================ [PASSED] test_range_spare =================
[21:57:45] ===================== [PASSED] guc_dbm =====================
[21:57:45] =================== guc_idm (6 subtests) ===================
[21:57:45] [PASSED] bad_init
[21:57:45] [PASSED] no_init
[21:57:45] [PASSED] init_fini
[21:57:45] [PASSED] check_used
[21:57:45] [PASSED] check_quota
[21:57:45] [PASSED] check_all
[21:57:45] ===================== [PASSED] guc_idm =====================
[21:57:45] ================== no_relay (3 subtests) ===================
[21:57:45] [PASSED] xe_drops_guc2pf_if_not_ready
[21:57:45] [PASSED] xe_drops_guc2vf_if_not_ready
[21:57:45] [PASSED] xe_rejects_send_if_not_ready
[21:57:45] ==================== [PASSED] no_relay =====================
[21:57:45] ================== pf_relay (14 subtests) ==================
[21:57:45] [PASSED] pf_rejects_guc2pf_too_short
[21:57:45] [PASSED] pf_rejects_guc2pf_too_long
[21:57:45] [PASSED] pf_rejects_guc2pf_no_payload
[21:57:45] [PASSED] pf_fails_no_payload
[21:57:45] [PASSED] pf_fails_bad_origin
[21:57:45] [PASSED] pf_fails_bad_type
[21:57:45] [PASSED] pf_txn_reports_error
[21:57:45] [PASSED] pf_txn_sends_pf2guc
[21:57:45] [PASSED] pf_sends_pf2guc
[21:57:45] [SKIPPED] pf_loopback_nop
[21:57:45] [SKIPPED] pf_loopback_echo
[21:57:45] [SKIPPED] pf_loopback_fail
[21:57:45] [SKIPPED] pf_loopback_busy
[21:57:45] [SKIPPED] pf_loopback_retry
[21:57:45] ==================== [PASSED] pf_relay =====================
[21:57:45] ================== vf_relay (3 subtests) ===================
[21:57:45] [PASSED] vf_rejects_guc2vf_too_short
[21:57:45] [PASSED] vf_rejects_guc2vf_too_long
[21:57:45] [PASSED] vf_rejects_guc2vf_no_payload
[21:57:45] ==================== [PASSED] vf_relay =====================
[21:57:45] ===================== lmtt (1 subtest) =====================
[21:57:45] ======================== test_ops  =========================
[21:57:45] [PASSED] 2-level
[21:57:45] [PASSED] multi-level
[21:57:45] ==================== [PASSED] test_ops =====================
[21:57:45] ====================== [PASSED] lmtt =======================
[21:57:45] ================= pf_service (11 subtests) =================
[21:57:45] [PASSED] pf_negotiate_any
[21:57:45] [PASSED] pf_negotiate_base_match
[21:57:45] [PASSED] pf_negotiate_base_newer
[21:57:45] [PASSED] pf_negotiate_base_next
[21:57:45] [SKIPPED] pf_negotiate_base_older
[21:57:45] [PASSED] pf_negotiate_base_prev
[21:57:45] [PASSED] pf_negotiate_latest_match
[21:57:45] [PASSED] pf_negotiate_latest_newer
[21:57:45] [PASSED] pf_negotiate_latest_next
[21:57:45] [SKIPPED] pf_negotiate_latest_older
[21:57:45] [SKIPPED] pf_negotiate_latest_prev
[21:57:45] =================== [PASSED] pf_service ====================
[21:57:45] ================= xe_guc_g2g (2 subtests) ==================
[21:57:45] ============== xe_live_guc_g2g_kunit_default  ==============
[21:57:45] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[21:57:45] ============== xe_live_guc_g2g_kunit_allmem  ===============
[21:57:45] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[21:57:45] =================== [SKIPPED] xe_guc_g2g ===================
[21:57:45] =================== xe_mocs (2 subtests) ===================
[21:57:45] ================ xe_live_mocs_kernel_kunit  ================
[21:57:45] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[21:57:45] ================ xe_live_mocs_reset_kunit  =================
[21:57:45] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[21:57:45] ==================== [SKIPPED] xe_mocs =====================
[21:57:45] ================= xe_migrate (2 subtests) ==================
[21:57:45] ================= xe_migrate_sanity_kunit  =================
[21:57:45] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[21:57:45] ================== xe_validate_ccs_kunit  ==================
[21:57:45] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[21:57:45] =================== [SKIPPED] xe_migrate ===================
[21:57:45] ================== xe_dma_buf (1 subtest) ==================
[21:57:45] ==================== xe_dma_buf_kunit  =====================
[21:57:45] ================ [SKIPPED] xe_dma_buf_kunit ================
[21:57:45] =================== [SKIPPED] xe_dma_buf ===================
[21:57:45] ================= xe_bo_shrink (1 subtest) =================
[21:57:45] =================== xe_bo_shrink_kunit  ====================
[21:57:45] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[21:57:45] ================== [SKIPPED] xe_bo_shrink ==================
[21:57:45] ==================== xe_bo (2 subtests) ====================
[21:57:45] ================== xe_ccs_migrate_kunit  ===================
[21:57:45] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[21:57:45] ==================== xe_bo_evict_kunit  ====================
[21:57:45] =============== [SKIPPED] xe_bo_evict_kunit ================
[21:57:45] ===================== [SKIPPED] xe_bo ======================
[21:57:45] ==================== args (11 subtests) ====================
[21:57:45] [PASSED] count_args_test
[21:57:45] [PASSED] call_args_example
[21:57:45] [PASSED] call_args_test
[21:57:45] [PASSED] drop_first_arg_example
[21:57:45] [PASSED] drop_first_arg_test
[21:57:45] [PASSED] first_arg_example
[21:57:45] [PASSED] first_arg_test
[21:57:45] [PASSED] last_arg_example
[21:57:45] [PASSED] last_arg_test
[21:57:45] [PASSED] pick_arg_example
[21:57:45] [PASSED] sep_comma_example
[21:57:45] ====================== [PASSED] args =======================
[21:57:45] =================== xe_pci (3 subtests) ====================
[21:57:45] ==================== check_graphics_ip  ====================
[21:57:45] [PASSED] 12.00 Xe_LP
[21:57:45] [PASSED] 12.10 Xe_LP+
[21:57:45] [PASSED] 12.55 Xe_HPG
[21:57:45] [PASSED] 12.60 Xe_HPC
[21:57:45] [PASSED] 12.70 Xe_LPG
[21:57:45] [PASSED] 12.71 Xe_LPG
[21:57:45] [PASSED] 12.74 Xe_LPG+
[21:57:45] [PASSED] 20.01 Xe2_HPG
[21:57:45] [PASSED] 20.02 Xe2_HPG
[21:57:45] [PASSED] 20.04 Xe2_LPG
[21:57:45] [PASSED] 30.00 Xe3_LPG
[21:57:45] [PASSED] 30.01 Xe3_LPG
[21:57:45] [PASSED] 30.03 Xe3_LPG
[21:57:45] ================ [PASSED] check_graphics_ip ================
[21:57:45] ===================== check_media_ip  ======================
[21:57:45] [PASSED] 12.00 Xe_M
[21:57:45] [PASSED] 12.55 Xe_HPM
[21:57:45] [PASSED] 13.00 Xe_LPM+
[21:57:45] [PASSED] 13.01 Xe2_HPM
[21:57:45] [PASSED] 20.00 Xe2_LPM
[21:57:45] [PASSED] 30.00 Xe3_LPM
[21:57:45] [PASSED] 30.02 Xe3_LPM
[21:57:45] ================= [PASSED] check_media_ip ==================
[21:57:45] ================= check_platform_gt_count  =================
[21:57:45] [PASSED] 0x9A60 (TIGERLAKE)
[21:57:45] [PASSED] 0x9A68 (TIGERLAKE)
[21:57:45] [PASSED] 0x9A70 (TIGERLAKE)
[21:57:45] [PASSED] 0x9A40 (TIGERLAKE)
[21:57:45] [PASSED] 0x9A49 (TIGERLAKE)
[21:57:45] [PASSED] 0x9A59 (TIGERLAKE)
[21:57:45] [PASSED] 0x9A78 (TIGERLAKE)
[21:57:45] [PASSED] 0x9AC0 (TIGERLAKE)
[21:57:45] [PASSED] 0x9AC9 (TIGERLAKE)
[21:57:45] [PASSED] 0x9AD9 (TIGERLAKE)
[21:57:45] [PASSED] 0x9AF8 (TIGERLAKE)
[21:57:45] [PASSED] 0x4C80 (ROCKETLAKE)
[21:57:45] [PASSED] 0x4C8A (ROCKETLAKE)
[21:57:45] [PASSED] 0x4C8B (ROCKETLAKE)
[21:57:45] [PASSED] 0x4C8C (ROCKETLAKE)
[21:57:45] [PASSED] 0x4C90 (ROCKETLAKE)
[21:57:45] [PASSED] 0x4C9A (ROCKETLAKE)
[21:57:45] [PASSED] 0x4680 (ALDERLAKE_S)
[21:57:45] [PASSED] 0x4682 (ALDERLAKE_S)
[21:57:45] [PASSED] 0x4688 (ALDERLAKE_S)
[21:57:45] [PASSED] 0x468A (ALDERLAKE_S)
[21:57:45] [PASSED] 0x468B (ALDERLAKE_S)
[21:57:45] [PASSED] 0x4690 (ALDERLAKE_S)
[21:57:45] [PASSED] 0x4692 (ALDERLAKE_S)
[21:57:45] [PASSED] 0x4693 (ALDERLAKE_S)
[21:57:45] [PASSED] 0x46A0 (ALDERLAKE_P)
[21:57:45] [PASSED] 0x46A1 (ALDERLAKE_P)
[21:57:45] [PASSED] 0x46A2 (ALDERLAKE_P)
[21:57:45] [PASSED] 0x46A3 (ALDERLAKE_P)
[21:57:45] [PASSED] 0x46A6 (ALDERLAKE_P)
[21:57:45] [PASSED] 0x46A8 (ALDERLAKE_P)
[21:57:45] [PASSED] 0x46AA (ALDERLAKE_P)
[21:57:45] [PASSED] 0x462A (ALDERLAKE_P)
[21:57:45] [PASSED] 0x4626 (ALDERLAKE_P)
[21:57:45] [PASSED] 0x4628 (ALDERLAKE_P)
[21:57:45] [PASSED] 0x46B0 (ALDERLAKE_P)
[21:57:45] [PASSED] 0x46B1 (ALDERLAKE_P)
[21:57:45] [PASSED] 0x46B2 (ALDERLAKE_P)
[21:57:45] [PASSED] 0x46B3 (ALDERLAKE_P)
[21:57:45] [PASSED] 0x46C0 (ALDERLAKE_P)
[21:57:45] [PASSED] 0x46C1 (ALDERLAKE_P)
[21:57:45] [PASSED] 0x46C2 (ALDERLAKE_P)
[21:57:45] [PASSED] 0x46C3 (ALDERLAKE_P)
[21:57:45] [PASSED] 0x46D0 (ALDERLAKE_N)
[21:57:45] [PASSED] 0x46D1 (ALDERLAKE_N)
[21:57:45] [PASSED] 0x46D2 (ALDERLAKE_N)
[21:57:45] [PASSED] 0x46D3 (ALDERLAKE_N)
[21:57:45] [PASSED] 0x46D4 (ALDERLAKE_N)
[21:57:45] [PASSED] 0xA721 (ALDERLAKE_P)
[21:57:45] [PASSED] 0xA7A1 (ALDERLAKE_P)
[21:57:45] [PASSED] 0xA7A9 (ALDERLAKE_P)
[21:57:45] [PASSED] 0xA7AC (ALDERLAKE_P)
[21:57:45] [PASSED] 0xA7AD (ALDERLAKE_P)
[21:57:45] [PASSED] 0xA720 (ALDERLAKE_P)
[21:57:45] [PASSED] 0xA7A0 (ALDERLAKE_P)
[21:57:45] [PASSED] 0xA7A8 (ALDERLAKE_P)
[21:57:45] [PASSED] 0xA7AA (ALDERLAKE_P)
[21:57:45] [PASSED] 0xA7AB (ALDERLAKE_P)
[21:57:45] [PASSED] 0xA780 (ALDERLAKE_S)
[21:57:45] [PASSED] 0xA781 (ALDERLAKE_S)
[21:57:45] [PASSED] 0xA782 (ALDERLAKE_S)
[21:57:45] [PASSED] 0xA783 (ALDERLAKE_S)
[21:57:45] [PASSED] 0xA788 (ALDERLAKE_S)
[21:57:45] [PASSED] 0xA789 (ALDERLAKE_S)
[21:57:45] [PASSED] 0xA78A (ALDERLAKE_S)
[21:57:45] [PASSED] 0xA78B (ALDERLAKE_S)
[21:57:45] [PASSED] 0x4905 (DG1)
[21:57:45] [PASSED] 0x4906 (DG1)
[21:57:45] [PASSED] 0x4907 (DG1)
[21:57:45] [PASSED] 0x4908 (DG1)
[21:57:45] [PASSED] 0x4909 (DG1)
[21:57:45] [PASSED] 0x56C0 (DG2)
[21:57:45] [PASSED] 0x56C2 (DG2)
[21:57:45] [PASSED] 0x56C1 (DG2)
[21:57:45] [PASSED] 0x7D51 (METEORLAKE)
[21:57:45] [PASSED] 0x7DD1 (METEORLAKE)
[21:57:45] [PASSED] 0x7D41 (METEORLAKE)
[21:57:45] [PASSED] 0x7D67 (METEORLAKE)
[21:57:45] [PASSED] 0xB640 (METEORLAKE)
[21:57:45] [PASSED] 0x56A0 (DG2)
[21:57:45] [PASSED] 0x56A1 (DG2)
[21:57:45] [PASSED] 0x56A2 (DG2)
[21:57:45] [PASSED] 0x56BE (DG2)
[21:57:45] [PASSED] 0x56BF (DG2)
[21:57:45] [PASSED] 0x5690 (DG2)
[21:57:45] [PASSED] 0x5691 (DG2)
[21:57:45] [PASSED] 0x5692 (DG2)
[21:57:45] [PASSED] 0x56A5 (DG2)
[21:57:45] [PASSED] 0x56A6 (DG2)
[21:57:45] [PASSED] 0x56B0 (DG2)
[21:57:45] [PASSED] 0x56B1 (DG2)
[21:57:45] [PASSED] 0x56BA (DG2)
[21:57:45] [PASSED] 0x56BB (DG2)
[21:57:45] [PASSED] 0x56BC (DG2)
[21:57:45] [PASSED] 0x56BD (DG2)
[21:57:45] [PASSED] 0x5693 (DG2)
[21:57:45] [PASSED] 0x5694 (DG2)
[21:57:45] [PASSED] 0x5695 (DG2)
[21:57:45] [PASSED] 0x56A3 (DG2)
[21:57:45] [PASSED] 0x56A4 (DG2)
[21:57:45] [PASSED] 0x56B2 (DG2)
[21:57:45] [PASSED] 0x56B3 (DG2)
[21:57:45] [PASSED] 0x5696 (DG2)
[21:57:45] [PASSED] 0x5697 (DG2)
[21:57:45] [PASSED] 0xB69 (PVC)
[21:57:45] [PASSED] 0xB6E (PVC)
[21:57:45] [PASSED] 0xBD4 (PVC)
[21:57:45] [PASSED] 0xBD5 (PVC)
[21:57:45] [PASSED] 0xBD6 (PVC)
[21:57:45] [PASSED] 0xBD7 (PVC)
[21:57:45] [PASSED] 0xBD8 (PVC)
[21:57:45] [PASSED] 0xBD9 (PVC)
[21:57:45] [PASSED] 0xBDA (PVC)
[21:57:45] [PASSED] 0xBDB (PVC)
[21:57:45] [PASSED] 0xBE0 (PVC)
[21:57:45] [PASSED] 0xBE1 (PVC)
[21:57:45] [PASSED] 0xBE5 (PVC)
[21:57:45] [PASSED] 0x7D40 (METEORLAKE)
[21:57:45] [PASSED] 0x7D45 (METEORLAKE)
[21:57:45] [PASSED] 0x7D55 (METEORLAKE)
[21:57:45] [PASSED] 0x7D60 (METEORLAKE)
[21:57:45] [PASSED] 0x7DD5 (METEORLAKE)
[21:57:45] [PASSED] 0x6420 (LUNARLAKE)
[21:57:45] [PASSED] 0x64A0 (LUNARLAKE)
[21:57:45] [PASSED] 0x64B0 (LUNARLAKE)
[21:57:45] [PASSED] 0xE202 (BATTLEMAGE)
[21:57:45] [PASSED] 0xE209 (BATTLEMAGE)
[21:57:45] [PASSED] 0xE20B (BATTLEMAGE)
[21:57:45] [PASSED] 0xE20C (BATTLEMAGE)
[21:57:45] [PASSED] 0xE20D (BATTLEMAGE)
[21:57:45] [PASSED] 0xE210 (BATTLEMAGE)
[21:57:45] [PASSED] 0xE211 (BATTLEMAGE)
[21:57:45] [PASSED] 0xE212 (BATTLEMAGE)
[21:57:45] [PASSED] 0xE216 (BATTLEMAGE)
[21:57:45] [PASSED] 0xE220 (BATTLEMAGE)
[21:57:45] [PASSED] 0xE221 (BATTLEMAGE)
[21:57:45] [PASSED] 0xE222 (BATTLEMAGE)
[21:57:45] [PASSED] 0xE223 (BATTLEMAGE)
[21:57:45] [PASSED] 0xB080 (PANTHERLAKE)
[21:57:45] [PASSED] 0xB081 (PANTHERLAKE)
[21:57:45] [PASSED] 0xB082 (PANTHERLAKE)
[21:57:45] [PASSED] 0xB083 (PANTHERLAKE)
[21:57:45] [PASSED] 0xB084 (PANTHERLAKE)
[21:57:45] [PASSED] 0xB085 (PANTHERLAKE)
[21:57:45] [PASSED] 0xB086 (PANTHERLAKE)
[21:57:45] [PASSED] 0xB087 (PANTHERLAKE)
[21:57:45] [PASSED] 0xB08F (PANTHERLAKE)
[21:57:45] [PASSED] 0xB090 (PANTHERLAKE)
[21:57:45] [PASSED] 0xB0A0 (PANTHERLAKE)
[21:57:45] [PASSED] 0xB0B0 (PANTHERLAKE)
[21:57:45] [PASSED] 0xFD80 (PANTHERLAKE)
[21:57:45] [PASSED] 0xFD81 (PANTHERLAKE)
[21:57:45] ============= [PASSED] check_platform_gt_count =============
[21:57:45] ===================== [PASSED] xe_pci ======================
[21:57:45] =================== xe_rtp (2 subtests) ====================
[21:57:45] =============== xe_rtp_process_to_sr_tests  ================
[21:57:45] [PASSED] coalesce-same-reg
[21:57:45] [PASSED] no-match-no-add
[21:57:45] [PASSED] match-or
[21:57:45] [PASSED] match-or-xfail
[21:57:45] [PASSED] no-match-no-add-multiple-rules
[21:57:45] [PASSED] two-regs-two-entries
[21:57:45] [PASSED] clr-one-set-other
[21:57:45] [PASSED] set-field
[21:57:45] [PASSED] conflict-duplicate
[21:57:45] [PASSED] conflict-not-disjoint
[21:57:45] [PASSED] conflict-reg-type
[21:57:45] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[21:57:45] ================== xe_rtp_process_tests  ===================
[21:57:45] [PASSED] active1
[21:57:45] [PASSED] active2
[21:57:45] [PASSED] active-inactive
[21:57:45] [PASSED] inactive-active
[21:57:45] [PASSED] inactive-1st_or_active-inactive
[21:57:45] [PASSED] inactive-2nd_or_active-inactive
[21:57:45] [PASSED] inactive-last_or_active-inactive
[21:57:45] [PASSED] inactive-no_or_active-inactive
[21:57:45] ============== [PASSED] xe_rtp_process_tests ===============
[21:57:45] ===================== [PASSED] xe_rtp ======================
[21:57:45] ==================== xe_wa (1 subtest) =====================
[21:57:45] ======================== xe_wa_gt  =========================
[21:57:45] [PASSED] TIGERLAKE B0
[21:57:45] [PASSED] DG1 A0
[21:57:45] [PASSED] DG1 B0
[21:57:45] [PASSED] ALDERLAKE_S A0
[21:57:45] [PASSED] ALDERLAKE_S B0
stty: 'standard input': Inappropriate ioctl for device
[21:57:45] [PASSED] ALDERLAKE_S C0
[21:57:45] [PASSED] ALDERLAKE_S D0
[21:57:45] [PASSED] ALDERLAKE_P A0
[21:57:45] [PASSED] ALDERLAKE_P B0
[21:57:45] [PASSED] ALDERLAKE_P C0
[21:57:45] [PASSED] ALDERLAKE_S RPLS D0
[21:57:45] [PASSED] ALDERLAKE_P RPLU E0
[21:57:45] [PASSED] DG2 G10 C0
[21:57:45] [PASSED] DG2 G11 B1
[21:57:45] [PASSED] DG2 G12 A1
[21:57:45] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[21:57:46] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[21:57:46] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[21:57:46] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[21:57:46] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[21:57:46] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[21:57:46] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[21:57:46] ==================== [PASSED] xe_wa_gt =====================
[21:57:46] ====================== [PASSED] xe_wa ======================
[21:57:46] ============================================================
[21:57:46] Testing complete. Ran 306 tests: passed: 288, skipped: 18
[21:57:46] Elapsed time: 34.421s total, 4.227s configuring, 29.827s building, 0.322s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[21:57:46] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:57:47] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[21:58:12] Starting KUnit Kernel (1/1)...
[21:58:12] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:58:12] ============ drm_test_pick_cmdline (2 subtests) ============
[21:58:12] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[21:58:12] =============== drm_test_pick_cmdline_named  ===============
[21:58:12] [PASSED] NTSC
[21:58:12] [PASSED] NTSC-J
[21:58:12] [PASSED] PAL
[21:58:12] [PASSED] PAL-M
[21:58:12] =========== [PASSED] drm_test_pick_cmdline_named ===========
[21:58:12] ============== [PASSED] drm_test_pick_cmdline ==============
[21:58:12] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[21:58:12] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[21:58:12] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[21:58:12] =========== drm_validate_clone_mode (2 subtests) ===========
[21:58:12] ============== drm_test_check_in_clone_mode  ===============
[21:58:12] [PASSED] in_clone_mode
[21:58:12] [PASSED] not_in_clone_mode
[21:58:12] ========== [PASSED] drm_test_check_in_clone_mode ===========
[21:58:12] =============== drm_test_check_valid_clones  ===============
[21:58:12] [PASSED] not_in_clone_mode
[21:58:12] [PASSED] valid_clone
[21:58:12] [PASSED] invalid_clone
[21:58:12] =========== [PASSED] drm_test_check_valid_clones ===========
[21:58:12] ============= [PASSED] drm_validate_clone_mode =============
[21:58:12] ============= drm_validate_modeset (1 subtest) =============
[21:58:12] [PASSED] drm_test_check_connector_changed_modeset
[21:58:12] ============== [PASSED] drm_validate_modeset ===============
[21:58:12] ====== drm_test_bridge_get_current_state (2 subtests) ======
[21:58:12] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[21:58:12] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[21:58:12] ======== [PASSED] drm_test_bridge_get_current_state ========
[21:58:12] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[21:58:12] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[21:58:12] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[21:58:12] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[21:58:12] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[21:58:12] ============== drm_bridge_alloc (2 subtests) ===============
[21:58:12] [PASSED] drm_test_drm_bridge_alloc_basic
[21:58:12] [PASSED] drm_test_drm_bridge_alloc_get_put
[21:58:12] ================ [PASSED] drm_bridge_alloc =================
[21:58:12] ================== drm_buddy (7 subtests) ==================
[21:58:12] [PASSED] drm_test_buddy_alloc_limit
[21:58:12] [PASSED] drm_test_buddy_alloc_optimistic
[21:58:12] [PASSED] drm_test_buddy_alloc_pessimistic
[21:58:12] [PASSED] drm_test_buddy_alloc_pathological
[21:58:12] [PASSED] drm_test_buddy_alloc_contiguous
[21:58:12] [PASSED] drm_test_buddy_alloc_clear
[21:58:12] [PASSED] drm_test_buddy_alloc_range_bias
[21:58:12] ==================== [PASSED] drm_buddy ====================
[21:58:12] ============= drm_cmdline_parser (40 subtests) =============
[21:58:12] [PASSED] drm_test_cmdline_force_d_only
[21:58:12] [PASSED] drm_test_cmdline_force_D_only_dvi
[21:58:12] [PASSED] drm_test_cmdline_force_D_only_hdmi
[21:58:12] [PASSED] drm_test_cmdline_force_D_only_not_digital
[21:58:12] [PASSED] drm_test_cmdline_force_e_only
[21:58:12] [PASSED] drm_test_cmdline_res
[21:58:12] [PASSED] drm_test_cmdline_res_vesa
[21:58:12] [PASSED] drm_test_cmdline_res_vesa_rblank
[21:58:12] [PASSED] drm_test_cmdline_res_rblank
[21:58:12] [PASSED] drm_test_cmdline_res_bpp
[21:58:12] [PASSED] drm_test_cmdline_res_refresh
[21:58:12] [PASSED] drm_test_cmdline_res_bpp_refresh
[21:58:12] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[21:58:12] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[21:58:12] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[21:58:12] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[21:58:12] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[21:58:12] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[21:58:12] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[21:58:12] [PASSED] drm_test_cmdline_res_margins_force_on
[21:58:12] [PASSED] drm_test_cmdline_res_vesa_margins
[21:58:12] [PASSED] drm_test_cmdline_name
[21:58:12] [PASSED] drm_test_cmdline_name_bpp
[21:58:12] [PASSED] drm_test_cmdline_name_option
[21:58:12] [PASSED] drm_test_cmdline_name_bpp_option
[21:58:12] [PASSED] drm_test_cmdline_rotate_0
[21:58:12] [PASSED] drm_test_cmdline_rotate_90
[21:58:12] [PASSED] drm_test_cmdline_rotate_180
[21:58:12] [PASSED] drm_test_cmdline_rotate_270
[21:58:12] [PASSED] drm_test_cmdline_hmirror
[21:58:12] [PASSED] drm_test_cmdline_vmirror
[21:58:12] [PASSED] drm_test_cmdline_margin_options
[21:58:12] [PASSED] drm_test_cmdline_multiple_options
[21:58:12] [PASSED] drm_test_cmdline_bpp_extra_and_option
[21:58:12] [PASSED] drm_test_cmdline_extra_and_option
[21:58:12] [PASSED] drm_test_cmdline_freestanding_options
[21:58:12] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[21:58:12] [PASSED] drm_test_cmdline_panel_orientation
[21:58:12] ================ drm_test_cmdline_invalid  =================
[21:58:12] [PASSED] margin_only
[21:58:12] [PASSED] interlace_only
[21:58:12] [PASSED] res_missing_x
[21:58:12] [PASSED] res_missing_y
[21:58:12] [PASSED] res_bad_y
[21:58:12] [PASSED] res_missing_y_bpp
[21:58:12] [PASSED] res_bad_bpp
[21:58:12] [PASSED] res_bad_refresh
[21:58:12] [PASSED] res_bpp_refresh_force_on_off
[21:58:12] [PASSED] res_invalid_mode
[21:58:12] [PASSED] res_bpp_wrong_place_mode
[21:58:12] [PASSED] name_bpp_refresh
[21:58:12] [PASSED] name_refresh
[21:58:12] [PASSED] name_refresh_wrong_mode
[21:58:12] [PASSED] name_refresh_invalid_mode
[21:58:12] [PASSED] rotate_multiple
[21:58:12] [PASSED] rotate_invalid_val
[21:58:12] [PASSED] rotate_truncated
[21:58:12] [PASSED] invalid_option
[21:58:12] [PASSED] invalid_tv_option
[21:58:12] [PASSED] truncated_tv_option
[21:58:12] ============ [PASSED] drm_test_cmdline_invalid =============
[21:58:12] =============== drm_test_cmdline_tv_options  ===============
[21:58:12] [PASSED] NTSC
[21:58:12] [PASSED] NTSC_443
[21:58:12] [PASSED] NTSC_J
[21:58:12] [PASSED] PAL
[21:58:12] [PASSED] PAL_M
[21:58:12] [PASSED] PAL_N
[21:58:12] [PASSED] SECAM
[21:58:12] [PASSED] MONO_525
[21:58:12] [PASSED] MONO_625
[21:58:12] =========== [PASSED] drm_test_cmdline_tv_options ===========
[21:58:12] =============== [PASSED] drm_cmdline_parser ================
[21:58:12] ========== drmm_connector_hdmi_init (20 subtests) ==========
[21:58:12] [PASSED] drm_test_connector_hdmi_init_valid
[21:58:12] [PASSED] drm_test_connector_hdmi_init_bpc_8
[21:58:12] [PASSED] drm_test_connector_hdmi_init_bpc_10
[21:58:12] [PASSED] drm_test_connector_hdmi_init_bpc_12
[21:58:12] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[21:58:12] [PASSED] drm_test_connector_hdmi_init_bpc_null
[21:58:12] [PASSED] drm_test_connector_hdmi_init_formats_empty
[21:58:12] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[21:58:12] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[21:58:12] [PASSED] supported_formats=0x9 yuv420_allowed=1
[21:58:12] [PASSED] supported_formats=0x9 yuv420_allowed=0
[21:58:12] [PASSED] supported_formats=0x3 yuv420_allowed=1
[21:58:12] [PASSED] supported_formats=0x3 yuv420_allowed=0
[21:58:12] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[21:58:12] [PASSED] drm_test_connector_hdmi_init_null_ddc
[21:58:12] [PASSED] drm_test_connector_hdmi_init_null_product
[21:58:12] [PASSED] drm_test_connector_hdmi_init_null_vendor
[21:58:12] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[21:58:12] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[21:58:12] [PASSED] drm_test_connector_hdmi_init_product_valid
[21:58:12] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[21:58:12] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[21:58:12] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[21:58:12] ========= drm_test_connector_hdmi_init_type_valid  =========
[21:58:12] [PASSED] HDMI-A
[21:58:12] [PASSED] HDMI-B
[21:58:12] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[21:58:12] ======== drm_test_connector_hdmi_init_type_invalid  ========
[21:58:12] [PASSED] Unknown
[21:58:12] [PASSED] VGA
[21:58:12] [PASSED] DVI-I
[21:58:12] [PASSED] DVI-D
[21:58:12] [PASSED] DVI-A
[21:58:12] [PASSED] Composite
[21:58:12] [PASSED] SVIDEO
[21:58:12] [PASSED] LVDS
[21:58:12] [PASSED] Component
[21:58:12] [PASSED] DIN
[21:58:12] [PASSED] DP
[21:58:12] [PASSED] TV
[21:58:12] [PASSED] eDP
[21:58:12] [PASSED] Virtual
[21:58:12] [PASSED] DSI
[21:58:12] [PASSED] DPI
[21:58:12] [PASSED] Writeback
[21:58:12] [PASSED] SPI
[21:58:12] [PASSED] USB
[21:58:12] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[21:58:12] ============ [PASSED] drmm_connector_hdmi_init =============
[21:58:12] ============= drmm_connector_init (3 subtests) =============
[21:58:12] [PASSED] drm_test_drmm_connector_init
[21:58:12] [PASSED] drm_test_drmm_connector_init_null_ddc
[21:58:12] ========= drm_test_drmm_connector_init_type_valid  =========
[21:58:12] [PASSED] Unknown
[21:58:12] [PASSED] VGA
[21:58:12] [PASSED] DVI-I
[21:58:12] [PASSED] DVI-D
[21:58:12] [PASSED] DVI-A
[21:58:12] [PASSED] Composite
[21:58:12] [PASSED] SVIDEO
[21:58:12] [PASSED] LVDS
[21:58:12] [PASSED] Component
[21:58:12] [PASSED] DIN
[21:58:12] [PASSED] DP
[21:58:12] [PASSED] HDMI-A
[21:58:12] [PASSED] HDMI-B
[21:58:12] [PASSED] TV
[21:58:12] [PASSED] eDP
[21:58:12] [PASSED] Virtual
[21:58:12] [PASSED] DSI
[21:58:12] [PASSED] DPI
[21:58:12] [PASSED] Writeback
[21:58:12] [PASSED] SPI
[21:58:12] [PASSED] USB
[21:58:12] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[21:58:12] =============== [PASSED] drmm_connector_init ===============
[21:58:12] ========= drm_connector_dynamic_init (6 subtests) ==========
[21:58:12] [PASSED] drm_test_drm_connector_dynamic_init
[21:58:12] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[21:58:12] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[21:58:12] [PASSED] drm_test_drm_connector_dynamic_init_properties
[21:58:12] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[21:58:12] [PASSED] Unknown
[21:58:12] [PASSED] VGA
[21:58:12] [PASSED] DVI-I
[21:58:12] [PASSED] DVI-D
[21:58:12] [PASSED] DVI-A
[21:58:12] [PASSED] Composite
[21:58:12] [PASSED] SVIDEO
[21:58:12] [PASSED] LVDS
[21:58:12] [PASSED] Component
[21:58:12] [PASSED] DIN
[21:58:12] [PASSED] DP
[21:58:12] [PASSED] HDMI-A
[21:58:12] [PASSED] HDMI-B
[21:58:12] [PASSED] TV
[21:58:12] [PASSED] eDP
[21:58:12] [PASSED] Virtual
[21:58:12] [PASSED] DSI
[21:58:12] [PASSED] DPI
[21:58:12] [PASSED] Writeback
[21:58:12] [PASSED] SPI
[21:58:12] [PASSED] USB
[21:58:12] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[21:58:12] ======== drm_test_drm_connector_dynamic_init_name  =========
[21:58:12] [PASSED] Unknown
[21:58:12] [PASSED] VGA
[21:58:12] [PASSED] DVI-I
[21:58:12] [PASSED] DVI-D
[21:58:12] [PASSED] DVI-A
[21:58:12] [PASSED] Composite
[21:58:12] [PASSED] SVIDEO
[21:58:12] [PASSED] LVDS
[21:58:12] [PASSED] Component
[21:58:12] [PASSED] DIN
[21:58:12] [PASSED] DP
[21:58:12] [PASSED] HDMI-A
[21:58:12] [PASSED] HDMI-B
[21:58:12] [PASSED] TV
[21:58:12] [PASSED] eDP
[21:58:12] [PASSED] Virtual
[21:58:12] [PASSED] DSI
[21:58:12] [PASSED] DPI
[21:58:12] [PASSED] Writeback
[21:58:12] [PASSED] SPI
[21:58:12] [PASSED] USB
[21:58:12] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[21:58:12] =========== [PASSED] drm_connector_dynamic_init ============
[21:58:12] ==== drm_connector_dynamic_register_early (4 subtests) =====
[21:58:12] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[21:58:12] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[21:58:12] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[21:58:12] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[21:58:12] ====== [PASSED] drm_connector_dynamic_register_early =======
[21:58:12] ======= drm_connector_dynamic_register (7 subtests) ========
[21:58:12] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[21:58:12] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[21:58:12] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[21:58:12] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[21:58:12] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[21:58:12] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[21:58:12] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[21:58:12] ========= [PASSED] drm_connector_dynamic_register ==========
[21:58:12] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[21:58:12] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[21:58:12] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[21:58:12] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[21:58:12] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[21:58:12] ========== drm_test_get_tv_mode_from_name_valid  ===========
[21:58:12] [PASSED] NTSC
[21:58:12] [PASSED] NTSC-443
[21:58:12] [PASSED] NTSC-J
[21:58:12] [PASSED] PAL
[21:58:12] [PASSED] PAL-M
[21:58:12] [PASSED] PAL-N
[21:58:12] [PASSED] SECAM
[21:58:12] [PASSED] Mono
[21:58:12] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[21:58:12] [PASSED] drm_test_get_tv_mode_from_name_truncated
[21:58:12] ============ [PASSED] drm_get_tv_mode_from_name ============
[21:58:12] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[21:58:12] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[21:58:12] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[21:58:12] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[21:58:12] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[21:58:12] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[21:58:12] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[21:58:12] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[21:58:12] [PASSED] VIC 96
[21:58:12] [PASSED] VIC 97
[21:58:12] [PASSED] VIC 101
[21:58:12] [PASSED] VIC 102
[21:58:12] [PASSED] VIC 106
[21:58:12] [PASSED] VIC 107
[21:58:12] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[21:58:12] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[21:58:12] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[21:58:12] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[21:58:12] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[21:58:12] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[21:58:12] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[21:58:12] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[21:58:12] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[21:58:12] [PASSED] Automatic
[21:58:12] [PASSED] Full
[21:58:12] [PASSED] Limited 16:235
[21:58:12] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[21:58:12] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[21:58:12] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[21:58:12] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[21:58:12] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[21:58:12] [PASSED] RGB
[21:58:12] [PASSED] YUV 4:2:0
[21:58:12] [PASSED] YUV 4:2:2
[21:58:12] [PASSED] YUV 4:4:4
[21:58:12] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[21:58:12] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[21:58:12] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[21:58:12] ============= drm_damage_helper (21 subtests) ==============
[21:58:12] [PASSED] drm_test_damage_iter_no_damage
[21:58:12] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[21:58:12] [PASSED] drm_test_damage_iter_no_damage_src_moved
[21:58:12] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[21:58:12] [PASSED] drm_test_damage_iter_no_damage_not_visible
[21:58:12] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[21:58:12] [PASSED] drm_test_damage_iter_no_damage_no_fb
[21:58:12] [PASSED] drm_test_damage_iter_simple_damage
[21:58:12] [PASSED] drm_test_damage_iter_single_damage
[21:58:12] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[21:58:12] [PASSED] drm_test_damage_iter_single_damage_outside_src
[21:58:12] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[21:58:12] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[21:58:12] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[21:58:12] [PASSED] drm_test_damage_iter_single_damage_src_moved
[21:58:12] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[21:58:12] [PASSED] drm_test_damage_iter_damage
[21:58:12] [PASSED] drm_test_damage_iter_damage_one_intersect
[21:58:12] [PASSED] drm_test_damage_iter_damage_one_outside
[21:58:12] [PASSED] drm_test_damage_iter_damage_src_moved
[21:58:12] [PASSED] drm_test_damage_iter_damage_not_visible
[21:58:12] ================ [PASSED] drm_damage_helper ================
[21:58:12] ============== drm_dp_mst_helper (3 subtests) ==============
[21:58:12] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[21:58:12] [PASSED] Clock 154000 BPP 30 DSC disabled
[21:58:12] [PASSED] Clock 234000 BPP 30 DSC disabled
[21:58:12] [PASSED] Clock 297000 BPP 24 DSC disabled
[21:58:12] [PASSED] Clock 332880 BPP 24 DSC enabled
[21:58:12] [PASSED] Clock 324540 BPP 24 DSC enabled
[21:58:12] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[21:58:12] ============== drm_test_dp_mst_calc_pbn_div  ===============
[21:58:12] [PASSED] Link rate 2000000 lane count 4
[21:58:12] [PASSED] Link rate 2000000 lane count 2
[21:58:12] [PASSED] Link rate 2000000 lane count 1
[21:58:12] [PASSED] Link rate 1350000 lane count 4
[21:58:12] [PASSED] Link rate 1350000 lane count 2
[21:58:12] [PASSED] Link rate 1350000 lane count 1
[21:58:12] [PASSED] Link rate 1000000 lane count 4
[21:58:12] [PASSED] Link rate 1000000 lane count 2
[21:58:12] [PASSED] Link rate 1000000 lane count 1
[21:58:12] [PASSED] Link rate 810000 lane count 4
[21:58:12] [PASSED] Link rate 810000 lane count 2
[21:58:12] [PASSED] Link rate 810000 lane count 1
[21:58:12] [PASSED] Link rate 540000 lane count 4
[21:58:12] [PASSED] Link rate 540000 lane count 2
[21:58:12] [PASSED] Link rate 540000 lane count 1
[21:58:12] [PASSED] Link rate 270000 lane count 4
[21:58:12] [PASSED] Link rate 270000 lane count 2
[21:58:12] [PASSED] Link rate 270000 lane count 1
[21:58:12] [PASSED] Link rate 162000 lane count 4
[21:58:12] [PASSED] Link rate 162000 lane count 2
[21:58:12] [PASSED] Link rate 162000 lane count 1
[21:58:12] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[21:58:12] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[21:58:12] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[21:58:12] [PASSED] DP_POWER_UP_PHY with port number
[21:58:12] [PASSED] DP_POWER_DOWN_PHY with port number
[21:58:12] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[21:58:12] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[21:58:12] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[21:58:12] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[21:58:12] [PASSED] DP_QUERY_PAYLOAD with port number
[21:58:12] [PASSED] DP_QUERY_PAYLOAD with VCPI
[21:58:12] [PASSED] DP_REMOTE_DPCD_READ with port number
[21:58:12] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[21:58:12] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[21:58:12] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[21:58:12] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[21:58:12] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[21:58:12] [PASSED] DP_REMOTE_I2C_READ with port number
[21:58:12] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[21:58:12] [PASSED] DP_REMOTE_I2C_READ with transactions array
[21:58:12] [PASSED] DP_REMOTE_I2C_WRITE with port number
[21:58:12] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[21:58:12] [PASSED] DP_REMOTE_I2C_WRITE with data array
[21:58:12] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[21:58:12] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[21:58:12] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[21:58:12] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[21:58:12] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[21:58:12] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[21:58:12] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[21:58:12] ================ [PASSED] drm_dp_mst_helper ================
[21:58:12] ================== drm_exec (7 subtests) ===================
[21:58:12] [PASSED] sanitycheck
[21:58:12] [PASSED] test_lock
[21:58:12] [PASSED] test_lock_unlock
[21:58:12] [PASSED] test_duplicates
[21:58:12] [PASSED] test_prepare
[21:58:12] [PASSED] test_prepare_array
[21:58:12] [PASSED] test_multiple_loops
[21:58:12] ==================== [PASSED] drm_exec =====================
[21:58:12] =========== drm_format_helper_test (17 subtests) ===========
[21:58:12] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[21:58:12] [PASSED] single_pixel_source_buffer
[21:58:12] [PASSED] single_pixel_clip_rectangle
[21:58:12] [PASSED] well_known_colors
[21:58:12] [PASSED] destination_pitch
[21:58:12] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[21:58:12] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[21:58:12] [PASSED] single_pixel_source_buffer
[21:58:12] [PASSED] single_pixel_clip_rectangle
[21:58:12] [PASSED] well_known_colors
[21:58:12] [PASSED] destination_pitch
[21:58:12] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[21:58:12] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[21:58:12] [PASSED] single_pixel_source_buffer
[21:58:12] [PASSED] single_pixel_clip_rectangle
[21:58:12] [PASSED] well_known_colors
[21:58:12] [PASSED] destination_pitch
[21:58:12] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[21:58:12] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[21:58:12] [PASSED] single_pixel_source_buffer
[21:58:12] [PASSED] single_pixel_clip_rectangle
[21:58:12] [PASSED] well_known_colors
[21:58:12] [PASSED] destination_pitch
[21:58:12] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[21:58:12] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[21:58:12] [PASSED] single_pixel_source_buffer
[21:58:12] [PASSED] single_pixel_clip_rectangle
[21:58:12] [PASSED] well_known_colors
[21:58:12] [PASSED] destination_pitch
[21:58:12] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[21:58:12] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[21:58:12] [PASSED] single_pixel_source_buffer
[21:58:12] [PASSED] single_pixel_clip_rectangle
[21:58:12] [PASSED] well_known_colors
[21:58:12] [PASSED] destination_pitch
[21:58:12] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[21:58:12] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[21:58:12] [PASSED] single_pixel_source_buffer
[21:58:12] [PASSED] single_pixel_clip_rectangle
[21:58:12] [PASSED] well_known_colors
[21:58:12] [PASSED] destination_pitch
[21:58:12] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[21:58:12] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[21:58:12] [PASSED] single_pixel_source_buffer
[21:58:12] [PASSED] single_pixel_clip_rectangle
[21:58:12] [PASSED] well_known_colors
[21:58:12] [PASSED] destination_pitch
[21:58:12] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[21:58:12] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[21:58:12] [PASSED] single_pixel_source_buffer
[21:58:12] [PASSED] single_pixel_clip_rectangle
[21:58:12] [PASSED] well_known_colors
[21:58:12] [PASSED] destination_pitch
[21:58:12] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[21:58:12] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[21:58:12] [PASSED] single_pixel_source_buffer
[21:58:12] [PASSED] single_pixel_clip_rectangle
[21:58:12] [PASSED] well_known_colors
[21:58:12] [PASSED] destination_pitch
[21:58:12] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[21:58:12] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[21:58:12] [PASSED] single_pixel_source_buffer
[21:58:12] [PASSED] single_pixel_clip_rectangle
[21:58:12] [PASSED] well_known_colors
[21:58:12] [PASSED] destination_pitch
[21:58:12] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[21:58:12] ============== drm_test_fb_xrgb8888_to_mono  ===============
[21:58:12] [PASSED] single_pixel_source_buffer
[21:58:12] [PASSED] single_pixel_clip_rectangle
[21:58:12] [PASSED] well_known_colors
[21:58:12] [PASSED] destination_pitch
[21:58:12] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[21:58:12] ==================== drm_test_fb_swab  =====================
[21:58:12] [PASSED] single_pixel_source_buffer
[21:58:12] [PASSED] single_pixel_clip_rectangle
[21:58:12] [PASSED] well_known_colors
[21:58:12] [PASSED] destination_pitch
[21:58:12] ================ [PASSED] drm_test_fb_swab =================
[21:58:12] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[21:58:12] [PASSED] single_pixel_source_buffer
[21:58:12] [PASSED] single_pixel_clip_rectangle
[21:58:12] [PASSED] well_known_colors
[21:58:12] [PASSED] destination_pitch
[21:58:12] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[21:58:12] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[21:58:12] [PASSED] single_pixel_source_buffer
[21:58:12] [PASSED] single_pixel_clip_rectangle
[21:58:12] [PASSED] well_known_colors
[21:58:12] [PASSED] destination_pitch
[21:58:12] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[21:58:12] ================= drm_test_fb_clip_offset  =================
[21:58:12] [PASSED] pass through
[21:58:12] [PASSED] horizontal offset
[21:58:12] [PASSED] vertical offset
[21:58:12] [PASSED] horizontal and vertical offset
[21:58:12] [PASSED] horizontal offset (custom pitch)
[21:58:12] [PASSED] vertical offset (custom pitch)
[21:58:12] [PASSED] horizontal and vertical offset (custom pitch)
[21:58:12] ============= [PASSED] drm_test_fb_clip_offset =============
[21:58:12] =================== drm_test_fb_memcpy  ====================
[21:58:12] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[21:58:12] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[21:58:12] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[21:58:12] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[21:58:12] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[21:58:12] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[21:58:12] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[21:58:12] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[21:58:12] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[21:58:12] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[21:58:12] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[21:58:12] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[21:58:12] =============== [PASSED] drm_test_fb_memcpy ================
[21:58:12] ============= [PASSED] drm_format_helper_test ==============
[21:58:12] ================= drm_format (18 subtests) =================
[21:58:12] [PASSED] drm_test_format_block_width_invalid
[21:58:12] [PASSED] drm_test_format_block_width_one_plane
[21:58:12] [PASSED] drm_test_format_block_width_two_plane
[21:58:12] [PASSED] drm_test_format_block_width_three_plane
[21:58:12] [PASSED] drm_test_format_block_width_tiled
[21:58:12] [PASSED] drm_test_format_block_height_invalid
[21:58:12] [PASSED] drm_test_format_block_height_one_plane
[21:58:12] [PASSED] drm_test_format_block_height_two_plane
[21:58:12] [PASSED] drm_test_format_block_height_three_plane
[21:58:12] [PASSED] drm_test_format_block_height_tiled
[21:58:12] [PASSED] drm_test_format_min_pitch_invalid
[21:58:12] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[21:58:12] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[21:58:12] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[21:58:12] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[21:58:12] [PASSED] drm_test_format_min_pitch_two_plane
[21:58:12] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[21:58:12] [PASSED] drm_test_format_min_pitch_tiled
[21:58:12] =================== [PASSED] drm_format ====================
[21:58:12] ============== drm_framebuffer (10 subtests) ===============
[21:58:12] ========== drm_test_framebuffer_check_src_coords  ==========
[21:58:12] [PASSED] Success: source fits into fb
[21:58:12] [PASSED] Fail: overflowing fb with x-axis coordinate
[21:58:12] [PASSED] Fail: overflowing fb with y-axis coordinate
[21:58:12] [PASSED] Fail: overflowing fb with source width
[21:58:12] [PASSED] Fail: overflowing fb with source height
[21:58:12] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[21:58:12] [PASSED] drm_test_framebuffer_cleanup
[21:58:12] =============== drm_test_framebuffer_create  ===============
[21:58:12] [PASSED] ABGR8888 normal sizes
[21:58:12] [PASSED] ABGR8888 max sizes
[21:58:12] [PASSED] ABGR8888 pitch greater than min required
[21:58:12] [PASSED] ABGR8888 pitch less than min required
[21:58:12] [PASSED] ABGR8888 Invalid width
[21:58:12] [PASSED] ABGR8888 Invalid buffer handle
[21:58:12] [PASSED] No pixel format
[21:58:12] [PASSED] ABGR8888 Width 0
[21:58:12] [PASSED] ABGR8888 Height 0
[21:58:12] [PASSED] ABGR8888 Out of bound height * pitch combination
[21:58:12] [PASSED] ABGR8888 Large buffer offset
[21:58:12] [PASSED] ABGR8888 Buffer offset for inexistent plane
[21:58:12] [PASSED] ABGR8888 Invalid flag
[21:58:12] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[21:58:12] [PASSED] ABGR8888 Valid buffer modifier
[21:58:12] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[21:58:12] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[21:58:12] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[21:58:12] [PASSED] NV12 Normal sizes
[21:58:12] [PASSED] NV12 Max sizes
[21:58:12] [PASSED] NV12 Invalid pitch
[21:58:12] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[21:58:12] [PASSED] NV12 different  modifier per-plane
[21:58:12] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[21:58:12] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[21:58:12] [PASSED] NV12 Modifier for inexistent plane
[21:58:12] [PASSED] NV12 Handle for inexistent plane
[21:58:12] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[21:58:12] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[21:58:12] [PASSED] YVU420 Normal sizes
[21:58:12] [PASSED] YVU420 Max sizes
[21:58:12] [PASSED] YVU420 Invalid pitch
[21:58:12] [PASSED] YVU420 Different pitches
[21:58:12] [PASSED] YVU420 Different buffer offsets/pitches
[21:58:12] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[21:58:12] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[21:58:12] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[21:58:12] [PASSED] YVU420 Valid modifier
[21:58:12] [PASSED] YVU420 Different modifiers per plane
[21:58:12] [PASSED] YVU420 Modifier for inexistent plane
[21:58:12] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[21:58:12] [PASSED] X0L2 Normal sizes
[21:58:12] [PASSED] X0L2 Max sizes
[21:58:12] [PASSED] X0L2 Invalid pitch
[21:58:12] [PASSED] X0L2 Pitch greater than minimum required
[21:58:12] [PASSED] X0L2 Handle for inexistent plane
[21:58:12] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[21:58:12] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[21:58:12] [PASSED] X0L2 Valid modifier
[21:58:12] [PASSED] X0L2 Modifier for inexistent plane
[21:58:12] =========== [PASSED] drm_test_framebuffer_create ===========
[21:58:12] [PASSED] drm_test_framebuffer_free
[21:58:12] [PASSED] drm_test_framebuffer_init
[21:58:12] [PASSED] drm_test_framebuffer_init_bad_format
[21:58:12] [PASSED] drm_test_framebuffer_init_dev_mismatch
[21:58:12] [PASSED] drm_test_framebuffer_lookup
[21:58:12] [PASSED] drm_test_framebuffer_lookup_inexistent
[21:58:12] [PASSED] drm_test_framebuffer_modifiers_not_supported
[21:58:12] ================= [PASSED] drm_framebuffer =================
[21:58:12] ================ drm_gem_shmem (8 subtests) ================
[21:58:12] [PASSED] drm_gem_shmem_test_obj_create
[21:58:12] [PASSED] drm_gem_shmem_test_obj_create_private
[21:58:12] [PASSED] drm_gem_shmem_test_pin_pages
[21:58:12] [PASSED] drm_gem_shmem_test_vmap
[21:58:12] [PASSED] drm_gem_shmem_test_get_pages_sgt
[21:58:12] [PASSED] drm_gem_shmem_test_get_sg_table
[21:58:12] [PASSED] drm_gem_shmem_test_madvise
[21:58:12] [PASSED] drm_gem_shmem_test_purge
[21:58:12] ================== [PASSED] drm_gem_shmem ==================
[21:58:12] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[21:58:12] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[21:58:12] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[21:58:12] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[21:58:12] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[21:58:12] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[21:58:12] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[21:58:12] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[21:58:12] [PASSED] Automatic
[21:58:12] [PASSED] Full
[21:58:12] [PASSED] Limited 16:235
[21:58:12] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[21:58:12] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[21:58:12] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[21:58:12] [PASSED] drm_test_check_disable_connector
[21:58:12] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[21:58:12] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[21:58:12] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[21:58:12] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[21:58:12] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[21:58:12] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[21:58:12] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[21:58:12] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[21:58:12] [PASSED] drm_test_check_output_bpc_dvi
[21:58:12] [PASSED] drm_test_check_output_bpc_format_vic_1
[21:58:12] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[21:58:12] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[21:58:12] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[21:58:12] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[21:58:12] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[21:58:12] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[21:58:12] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[21:58:12] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[21:58:12] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[21:58:12] [PASSED] drm_test_check_broadcast_rgb_value
[21:58:12] [PASSED] drm_test_check_bpc_8_value
[21:58:12] [PASSED] drm_test_check_bpc_10_value
[21:58:12] [PASSED] drm_test_check_bpc_12_value
[21:58:12] [PASSED] drm_test_check_format_value
[21:58:12] [PASSED] drm_test_check_tmds_char_value
[21:58:12] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[21:58:12] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[21:58:12] [PASSED] drm_test_check_mode_valid
[21:58:12] [PASSED] drm_test_check_mode_valid_reject
[21:58:12] [PASSED] drm_test_check_mode_valid_reject_rate
[21:58:12] [PASSED] drm_test_check_mode_valid_reject_max_clock
[21:58:12] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[21:58:12] ================= drm_managed (2 subtests) =================
[21:58:12] [PASSED] drm_test_managed_release_action
[21:58:12] [PASSED] drm_test_managed_run_action
[21:58:12] =================== [PASSED] drm_managed ===================
[21:58:12] =================== drm_mm (6 subtests) ====================
[21:58:12] [PASSED] drm_test_mm_init
[21:58:12] [PASSED] drm_test_mm_debug
[21:58:12] [PASSED] drm_test_mm_align32
[21:58:12] [PASSED] drm_test_mm_align64
[21:58:12] [PASSED] drm_test_mm_lowest
[21:58:12] [PASSED] drm_test_mm_highest
[21:58:12] ===================== [PASSED] drm_mm ======================
[21:58:12] ============= drm_modes_analog_tv (5 subtests) =============
[21:58:12] [PASSED] drm_test_modes_analog_tv_mono_576i
[21:58:12] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[21:58:12] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[21:58:12] [PASSED] drm_test_modes_analog_tv_pal_576i
[21:58:12] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[21:58:12] =============== [PASSED] drm_modes_analog_tv ===============
[21:58:12] ============== drm_plane_helper (2 subtests) ===============
[21:58:12] =============== drm_test_check_plane_state  ================
[21:58:12] [PASSED] clipping_simple
[21:58:12] [PASSED] clipping_rotate_reflect
[21:58:12] [PASSED] positioning_simple
[21:58:12] [PASSED] upscaling
[21:58:12] [PASSED] downscaling
[21:58:12] [PASSED] rounding1
[21:58:12] [PASSED] rounding2
[21:58:12] [PASSED] rounding3
[21:58:12] [PASSED] rounding4
[21:58:12] =========== [PASSED] drm_test_check_plane_state ============
[21:58:12] =========== drm_test_check_invalid_plane_state  ============
[21:58:12] [PASSED] positioning_invalid
[21:58:12] [PASSED] upscaling_invalid
[21:58:12] [PASSED] downscaling_invalid
[21:58:12] ======= [PASSED] drm_test_check_invalid_plane_state ========
[21:58:12] ================ [PASSED] drm_plane_helper =================
[21:58:12] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[21:58:12] ====== drm_test_connector_helper_tv_get_modes_check  =======
[21:58:12] [PASSED] None
[21:58:12] [PASSED] PAL
[21:58:12] [PASSED] NTSC
[21:58:12] [PASSED] Both, NTSC Default
[21:58:12] [PASSED] Both, PAL Default
[21:58:12] [PASSED] Both, NTSC Default, with PAL on command-line
[21:58:12] [PASSED] Both, PAL Default, with NTSC on command-line
[21:58:12] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[21:58:12] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[21:58:12] ================== drm_rect (9 subtests) ===================
[21:58:12] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[21:58:12] [PASSED] drm_test_rect_clip_scaled_not_clipped
[21:58:12] [PASSED] drm_test_rect_clip_scaled_clipped
[21:58:12] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[21:58:12] ================= drm_test_rect_intersect  =================
[21:58:12] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[21:58:12] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[21:58:12] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[21:58:12] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[21:58:12] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[21:58:12] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[21:58:12] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[21:58:12] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[21:58:12] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[21:58:12] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[21:58:12] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[21:58:12] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[21:58:12] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[21:58:12] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[21:58:12] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[21:58:12] ============= [PASSED] drm_test_rect_intersect =============
[21:58:12] ================ drm_test_rect_calc_hscale  ================
[21:58:12] [PASSED] normal use
[21:58:12] [PASSED] out of max range
[21:58:12] [PASSED] out of min range
[21:58:12] [PASSED] zero dst
[21:58:12] [PASSED] negative src
[21:58:12] [PASSED] negative dst
[21:58:12] ============ [PASSED] drm_test_rect_calc_hscale ============
[21:58:12] ================ drm_test_rect_calc_vscale  ================
[21:58:12] [PASSED] normal use
[21:58:12] [PASSED] out of max range
[21:58:12] [PASSED] out of min range
[21:58:12] [PASSED] zero dst
[21:58:12] [PASSED] negative src
stty: 'standard input': Inappropriate ioctl for device
[21:58:12] [PASSED] negative dst
[21:58:12] ============ [PASSED] drm_test_rect_calc_vscale ============
[21:58:12] ================== drm_test_rect_rotate  ===================
[21:58:12] [PASSED] reflect-x
[21:58:12] [PASSED] reflect-y
[21:58:12] [PASSED] rotate-0
[21:58:12] [PASSED] rotate-90
[21:58:12] [PASSED] rotate-180
[21:58:12] [PASSED] rotate-270
[21:58:12] ============== [PASSED] drm_test_rect_rotate ===============
[21:58:12] ================ drm_test_rect_rotate_inv  =================
[21:58:12] [PASSED] reflect-x
[21:58:12] [PASSED] reflect-y
[21:58:12] [PASSED] rotate-0
[21:58:12] [PASSED] rotate-90
[21:58:12] [PASSED] rotate-180
[21:58:12] [PASSED] rotate-270
[21:58:12] ============ [PASSED] drm_test_rect_rotate_inv =============
[21:58:12] ==================== [PASSED] drm_rect =====================
[21:58:12] ============ drm_sysfb_modeset_test (1 subtest) ============
[21:58:12] ============ drm_test_sysfb_build_fourcc_list  =============
[21:58:12] [PASSED] no native formats
[21:58:12] [PASSED] XRGB8888 as native format
[21:58:12] [PASSED] remove duplicates
[21:58:12] [PASSED] convert alpha formats
[21:58:12] [PASSED] random formats
[21:58:12] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[21:58:12] ============= [PASSED] drm_sysfb_modeset_test ==============
[21:58:12] ============================================================
[21:58:12] Testing complete. Ran 621 tests: passed: 621
[21:58:12] Elapsed time: 26.154s total, 1.752s configuring, 24.235s building, 0.145s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[21:58:12] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:58:14] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[21:58:23] Starting KUnit Kernel (1/1)...
[21:58:23] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:58:23] ================= ttm_device (5 subtests) ==================
[21:58:23] [PASSED] ttm_device_init_basic
[21:58:23] [PASSED] ttm_device_init_multiple
[21:58:23] [PASSED] ttm_device_fini_basic
[21:58:23] [PASSED] ttm_device_init_no_vma_man
[21:58:23] ================== ttm_device_init_pools  ==================
[21:58:23] [PASSED] No DMA allocations, no DMA32 required
[21:58:23] [PASSED] DMA allocations, DMA32 required
[21:58:23] [PASSED] No DMA allocations, DMA32 required
[21:58:23] [PASSED] DMA allocations, no DMA32 required
[21:58:23] ============== [PASSED] ttm_device_init_pools ==============
[21:58:23] =================== [PASSED] ttm_device ====================
[21:58:23] ================== ttm_pool (8 subtests) ===================
[21:58:23] ================== ttm_pool_alloc_basic  ===================
[21:58:23] [PASSED] One page
[21:58:23] [PASSED] More than one page
[21:58:23] [PASSED] Above the allocation limit
[21:58:23] [PASSED] One page, with coherent DMA mappings enabled
[21:58:23] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[21:58:23] ============== [PASSED] ttm_pool_alloc_basic ===============
[21:58:23] ============== ttm_pool_alloc_basic_dma_addr  ==============
[21:58:23] [PASSED] One page
[21:58:23] [PASSED] More than one page
[21:58:23] [PASSED] Above the allocation limit
[21:58:23] [PASSED] One page, with coherent DMA mappings enabled
[21:58:23] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[21:58:23] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[21:58:23] [PASSED] ttm_pool_alloc_order_caching_match
[21:58:23] [PASSED] ttm_pool_alloc_caching_mismatch
[21:58:23] [PASSED] ttm_pool_alloc_order_mismatch
[21:58:23] [PASSED] ttm_pool_free_dma_alloc
[21:58:23] [PASSED] ttm_pool_free_no_dma_alloc
[21:58:23] [PASSED] ttm_pool_fini_basic
[21:58:23] ==================== [PASSED] ttm_pool =====================
[21:58:23] ================ ttm_resource (8 subtests) =================
[21:58:23] ================= ttm_resource_init_basic  =================
[21:58:23] [PASSED] Init resource in TTM_PL_SYSTEM
[21:58:23] [PASSED] Init resource in TTM_PL_VRAM
[21:58:23] [PASSED] Init resource in a private placement
[21:58:23] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[21:58:23] ============= [PASSED] ttm_resource_init_basic =============
[21:58:23] [PASSED] ttm_resource_init_pinned
[21:58:23] [PASSED] ttm_resource_fini_basic
[21:58:23] [PASSED] ttm_resource_manager_init_basic
[21:58:23] [PASSED] ttm_resource_manager_usage_basic
[21:58:23] [PASSED] ttm_resource_manager_set_used_basic
[21:58:23] [PASSED] ttm_sys_man_alloc_basic
[21:58:23] [PASSED] ttm_sys_man_free_basic
[21:58:23] ================== [PASSED] ttm_resource ===================
[21:58:23] =================== ttm_tt (15 subtests) ===================
[21:58:23] ==================== ttm_tt_init_basic  ====================
[21:58:23] [PASSED] Page-aligned size
[21:58:23] [PASSED] Extra pages requested
[21:58:23] ================ [PASSED] ttm_tt_init_basic ================
[21:58:23] [PASSED] ttm_tt_init_misaligned
[21:58:23] [PASSED] ttm_tt_fini_basic
[21:58:23] [PASSED] ttm_tt_fini_sg
[21:58:23] [PASSED] ttm_tt_fini_shmem
[21:58:23] [PASSED] ttm_tt_create_basic
[21:58:23] [PASSED] ttm_tt_create_invalid_bo_type
[21:58:23] [PASSED] ttm_tt_create_ttm_exists
[21:58:23] [PASSED] ttm_tt_create_failed
[21:58:23] [PASSED] ttm_tt_destroy_basic
[21:58:23] [PASSED] ttm_tt_populate_null_ttm
[21:58:23] [PASSED] ttm_tt_populate_populated_ttm
[21:58:23] [PASSED] ttm_tt_unpopulate_basic
[21:58:23] [PASSED] ttm_tt_unpopulate_empty_ttm
[21:58:23] [PASSED] ttm_tt_swapin_basic
[21:58:23] ===================== [PASSED] ttm_tt ======================
[21:58:23] =================== ttm_bo (14 subtests) ===================
[21:58:23] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[21:58:23] [PASSED] Cannot be interrupted and sleeps
[21:58:23] [PASSED] Cannot be interrupted, locks straight away
[21:58:23] [PASSED] Can be interrupted, sleeps
[21:58:23] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[21:58:23] [PASSED] ttm_bo_reserve_locked_no_sleep
[21:58:23] [PASSED] ttm_bo_reserve_no_wait_ticket
[21:58:23] [PASSED] ttm_bo_reserve_double_resv
[21:58:23] [PASSED] ttm_bo_reserve_interrupted
[21:58:23] [PASSED] ttm_bo_reserve_deadlock
[21:58:23] [PASSED] ttm_bo_unreserve_basic
[21:58:23] [PASSED] ttm_bo_unreserve_pinned
[21:58:23] [PASSED] ttm_bo_unreserve_bulk
[21:58:23] [PASSED] ttm_bo_fini_basic
[21:58:23] [PASSED] ttm_bo_fini_shared_resv
[21:58:23] [PASSED] ttm_bo_pin_basic
[21:58:23] [PASSED] ttm_bo_pin_unpin_resource
[21:58:23] [PASSED] ttm_bo_multiple_pin_one_unpin
[21:58:23] ===================== [PASSED] ttm_bo ======================
[21:58:23] ============== ttm_bo_validate (21 subtests) ===============
[21:58:23] ============== ttm_bo_init_reserved_sys_man  ===============
[21:58:23] [PASSED] Buffer object for userspace
[21:58:23] [PASSED] Kernel buffer object
[21:58:23] [PASSED] Shared buffer object
[21:58:23] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[21:58:23] ============== ttm_bo_init_reserved_mock_man  ==============
[21:58:23] [PASSED] Buffer object for userspace
[21:58:23] [PASSED] Kernel buffer object
[21:58:23] [PASSED] Shared buffer object
[21:58:23] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[21:58:23] [PASSED] ttm_bo_init_reserved_resv
[21:58:23] ================== ttm_bo_validate_basic  ==================
[21:58:23] [PASSED] Buffer object for userspace
[21:58:23] [PASSED] Kernel buffer object
[21:58:23] [PASSED] Shared buffer object
[21:58:23] ============== [PASSED] ttm_bo_validate_basic ==============
[21:58:23] [PASSED] ttm_bo_validate_invalid_placement
[21:58:23] ============= ttm_bo_validate_same_placement  ==============
[21:58:23] [PASSED] System manager
[21:58:23] [PASSED] VRAM manager
[21:58:23] ========= [PASSED] ttm_bo_validate_same_placement ==========
[21:58:23] [PASSED] ttm_bo_validate_failed_alloc
[21:58:23] [PASSED] ttm_bo_validate_pinned
[21:58:23] [PASSED] ttm_bo_validate_busy_placement
[21:58:23] ================ ttm_bo_validate_multihop  =================
[21:58:23] [PASSED] Buffer object for userspace
[21:58:23] [PASSED] Kernel buffer object
[21:58:23] [PASSED] Shared buffer object
[21:58:23] ============ [PASSED] ttm_bo_validate_multihop =============
[21:58:23] ========== ttm_bo_validate_no_placement_signaled  ==========
[21:58:23] [PASSED] Buffer object in system domain, no page vector
[21:58:23] [PASSED] Buffer object in system domain with an existing page vector
[21:58:23] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[21:58:23] ======== ttm_bo_validate_no_placement_not_signaled  ========
[21:58:23] [PASSED] Buffer object for userspace
[21:58:23] [PASSED] Kernel buffer object
[21:58:23] [PASSED] Shared buffer object
[21:58:23] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[21:58:23] [PASSED] ttm_bo_validate_move_fence_signaled
[21:58:23] ========= ttm_bo_validate_move_fence_not_signaled  =========
[21:58:23] [PASSED] Waits for GPU
[21:58:23] [PASSED] Tries to lock straight away
[21:58:23] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[21:58:23] [PASSED] ttm_bo_validate_happy_evict
[21:58:23] [PASSED] ttm_bo_validate_all_pinned_evict
[21:58:23] [PASSED] ttm_bo_validate_allowed_only_evict
[21:58:23] [PASSED] ttm_bo_validate_deleted_evict
[21:58:23] [PASSED] ttm_bo_validate_busy_domain_evict
[21:58:23] [PASSED] ttm_bo_validate_evict_gutting
[21:58:23] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[21:58:23] ================= [PASSED] ttm_bo_validate =================
[21:58:23] ============================================================
[21:58:23] Testing complete. Ran 101 tests: passed: 101
[21:58:23] Elapsed time: 11.078s total, 1.749s configuring, 9.114s building, 0.186s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for drm/i915/dp: Work around a DSC pixel throughput issue

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1478 bytes --]

== Series Details ==

Series: drm/i915/dp: Work around a DSC pixel throughput issue
URL   : https://patchwork.freedesktop.org/series/154737/
State : success

== Summary ==

CI Bug Log - changes from xe-3793-8031d70dbb4201841897de480cec1f9750d4a5dc_BAT -> xe-pw-154737v1_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-154737v1_BAT that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@kms_flip@basic-plain-flip@c-edp1:
    - bat-adlp-7:         [DMESG-WARN][1] ([Intel XE#4543]) -> [PASS][2] +1 other test pass
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3793-8031d70dbb4201841897de480cec1f9750d4a5dc/bat-adlp-7/igt@kms_flip@basic-plain-flip@c-edp1.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v1/bat-adlp-7/igt@kms_flip@basic-plain-flip@c-edp1.html

  
  [Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543


Build changes
-------------

  * Linux: xe-3793-8031d70dbb4201841897de480cec1f9750d4a5dc -> xe-pw-154737v1

  IGT_8543: 8543
  xe-3793-8031d70dbb4201841897de480cec1f9750d4a5dc: 8031d70dbb4201841897de480cec1f9750d4a5dc
  xe-pw-154737v1: 154737v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v1/index.html

[-- Attachment #2: Type: text/html, Size: 2043 bytes --]

✗ CI.checkpatch: warning for drm/i915/dp: Work around a DSC pixel throughput issue (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/dp: Work around a DSC pixel throughput issue (rev3)
URL   : https://patchwork.freedesktop.org/series/154737/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
fbd08a78c3a3bb17964db2a326514c69c1dca660
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 631951d594d23ca7da58e8510b349b93fac5238d
Author: Imre Deak <imre.deak@intel.com>
Date:   Mon Sep 22 16:46:37 2025 +0300

    drm/i915/dp: Handle Synaptics DSC throughput link-bpp quirk
    
    Handle the DSC pixel throughput quirk, limiting the compressed link-bpp
    value for Synaptics Panamera branch devices, working around a
    blank/unstable output issue observed on docking stations containing
    these branch devices, when using a mode with a high pixel clock and a
    high compressed link-bpp value.
    
    For now use the same mode clock limit for RGB/YUV444 and YUV422/420
    output modes. This may result in limiting the link-bpp value for a
    YUV422/420 output mode already at a lower than required mode clock.
    
    v2: Apply the quirk only when DSC is enabled.
    
    Reported-by: Vidya Srinivas <vidya.srinivas@intel.com>
    Reported-by: Swati Sharma <swati2.sharma@intel.com>
    Signed-off-by: Imre Deak <imre.deak@intel.com>
+ /mt/dim checkpatch c4d19320a0e2f7d8dec97d4a59309349a3a63ec0 drm-intel
5ace16ed8794 drm/dp: Add quirk for Synaptics DSC throughput link-bpp limit
-:44: WARNING:BAD_REPORTED_BY_LINK: Reported-by: should be immediately followed by Closes: with a URL to the report
#44: 
Reported-by: Vidya Srinivas <vidya.srinivas@intel.com>
Reported-by: Swati Sharma <swati2.sharma@intel.com>

-:45: WARNING:BAD_REPORTED_BY_LINK: Reported-by: should be immediately followed by Closes: with a URL to the report
#45: 
Reported-by: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>

-:56: WARNING:LONG_LINE_COMMENT: line length of 111 exceeds 100 columns
#56: FILE: drivers/gpu/drm/display/drm_dp_helper.c:2554:
+	/* Synaptics Panamera supports only a compressed bpp of 12 above 50% of its max DSC pixel throughput */

-:57: WARNING:LONG_LINE: line length of 128 exceeds 100 columns
#57: FILE: drivers/gpu/drm/display/drm_dp_helper.c:2555:
+	{ OUI(0x90, 0xCC, 0x24), DEVICE_ID('S', 'Y', 'N', 'A', 0x53, 0x22), true, BIT(DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT) },

-:58: WARNING:LONG_LINE: line length of 128 exceeds 100 columns
#58: FILE: drivers/gpu/drm/display/drm_dp_helper.c:2556:
+	{ OUI(0x90, 0xCC, 0x24), DEVICE_ID('S', 'Y', 'N', 'A', 0x53, 0x31), true, BIT(DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT) },

-:59: WARNING:LONG_LINE: line length of 128 exceeds 100 columns
#59: FILE: drivers/gpu/drm/display/drm_dp_helper.c:2557:
+	{ OUI(0x90, 0xCC, 0x24), DEVICE_ID('S', 'Y', 'N', 'A', 0x53, 0x33), true, BIT(DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT) },

total: 0 errors, 6 warnings, 0 checks, 25 lines checked
6ee68b8bf2cf drm/i915/dp: Calculate DSC slice count based on per-slice peak throughput
ffb57dc4befd drm/i915/dp: Pass DPCD device descriptor to intel_dp_get_dsc_sink_cap()
157d36ccdcc8 drm/i915/dp: Verify branch devices' overall pixel throughput/line width
631951d594d2 drm/i915/dp: Handle Synaptics DSC throughput link-bpp quirk
-:18: WARNING:BAD_REPORTED_BY_LINK: Reported-by: should be immediately followed by Closes: with a URL to the report
#18: 
Reported-by: Vidya Srinivas <vidya.srinivas@intel.com>
Reported-by: Swati Sharma <swati2.sharma@intel.com>

-:19: WARNING:BAD_REPORTED_BY_LINK: Reported-by: should be immediately followed by Closes: with a URL to the report
#19: 
Reported-by: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>

total: 0 errors, 2 warnings, 0 checks, 89 lines checked

✓ CI.KUnit: success for drm/i915/dp: Work around a DSC pixel throughput issue (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/dp: Work around a DSC pixel throughput issue (rev3)
URL   : https://patchwork.freedesktop.org/series/154737/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[14:35:14] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[14:35:19] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[14:35:48] Starting KUnit Kernel (1/1)...
[14:35:48] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[14:35:49] ================== guc_buf (11 subtests) ===================
[14:35:49] [PASSED] test_smallest
[14:35:49] [PASSED] test_largest
[14:35:49] [PASSED] test_granular
[14:35:49] [PASSED] test_unique
[14:35:49] [PASSED] test_overlap
[14:35:49] [PASSED] test_reusable
[14:35:49] [PASSED] test_too_big
[14:35:49] [PASSED] test_flush
[14:35:49] [PASSED] test_lookup
[14:35:49] [PASSED] test_data
[14:35:49] [PASSED] test_class
[14:35:49] ===================== [PASSED] guc_buf =====================
[14:35:49] =================== guc_dbm (7 subtests) ===================
[14:35:49] [PASSED] test_empty
[14:35:49] [PASSED] test_default
[14:35:49] ======================== test_size  ========================
[14:35:49] [PASSED] 4
[14:35:49] [PASSED] 8
[14:35:49] [PASSED] 32
[14:35:49] [PASSED] 256
[14:35:49] ==================== [PASSED] test_size ====================
[14:35:49] ======================= test_reuse  ========================
[14:35:49] [PASSED] 4
[14:35:49] [PASSED] 8
[14:35:49] [PASSED] 32
[14:35:49] [PASSED] 256
[14:35:49] =================== [PASSED] test_reuse ====================
[14:35:49] =================== test_range_overlap  ====================
[14:35:49] [PASSED] 4
[14:35:49] [PASSED] 8
[14:35:49] [PASSED] 32
[14:35:49] [PASSED] 256
[14:35:49] =============== [PASSED] test_range_overlap ================
[14:35:49] =================== test_range_compact  ====================
[14:35:49] [PASSED] 4
[14:35:49] [PASSED] 8
[14:35:49] [PASSED] 32
[14:35:49] [PASSED] 256
[14:35:49] =============== [PASSED] test_range_compact ================
[14:35:49] ==================== test_range_spare  =====================
[14:35:49] [PASSED] 4
[14:35:49] [PASSED] 8
[14:35:49] [PASSED] 32
[14:35:49] [PASSED] 256
[14:35:49] ================ [PASSED] test_range_spare =================
[14:35:49] ===================== [PASSED] guc_dbm =====================
[14:35:49] =================== guc_idm (6 subtests) ===================
[14:35:49] [PASSED] bad_init
[14:35:49] [PASSED] no_init
[14:35:49] [PASSED] init_fini
[14:35:49] [PASSED] check_used
[14:35:49] [PASSED] check_quota
[14:35:49] [PASSED] check_all
[14:35:49] ===================== [PASSED] guc_idm =====================
[14:35:49] ================== no_relay (3 subtests) ===================
[14:35:49] [PASSED] xe_drops_guc2pf_if_not_ready
[14:35:49] [PASSED] xe_drops_guc2vf_if_not_ready
[14:35:49] [PASSED] xe_rejects_send_if_not_ready
[14:35:49] ==================== [PASSED] no_relay =====================
[14:35:49] ================== pf_relay (14 subtests) ==================
[14:35:49] [PASSED] pf_rejects_guc2pf_too_short
[14:35:49] [PASSED] pf_rejects_guc2pf_too_long
[14:35:49] [PASSED] pf_rejects_guc2pf_no_payload
[14:35:49] [PASSED] pf_fails_no_payload
[14:35:49] [PASSED] pf_fails_bad_origin
[14:35:49] [PASSED] pf_fails_bad_type
[14:35:49] [PASSED] pf_txn_reports_error
[14:35:49] [PASSED] pf_txn_sends_pf2guc
[14:35:49] [PASSED] pf_sends_pf2guc
[14:35:49] [SKIPPED] pf_loopback_nop
[14:35:49] [SKIPPED] pf_loopback_echo
[14:35:49] [SKIPPED] pf_loopback_fail
[14:35:49] [SKIPPED] pf_loopback_busy
[14:35:49] [SKIPPED] pf_loopback_retry
[14:35:49] ==================== [PASSED] pf_relay =====================
[14:35:49] ================== vf_relay (3 subtests) ===================
[14:35:49] [PASSED] vf_rejects_guc2vf_too_short
[14:35:49] [PASSED] vf_rejects_guc2vf_too_long
[14:35:49] [PASSED] vf_rejects_guc2vf_no_payload
[14:35:49] ==================== [PASSED] vf_relay =====================
[14:35:49] ===================== lmtt (1 subtest) =====================
[14:35:49] ======================== test_ops  =========================
[14:35:49] [PASSED] 2-level
[14:35:49] [PASSED] multi-level
[14:35:49] ==================== [PASSED] test_ops =====================
[14:35:49] ====================== [PASSED] lmtt =======================
[14:35:49] ================= pf_service (11 subtests) =================
[14:35:49] [PASSED] pf_negotiate_any
[14:35:49] [PASSED] pf_negotiate_base_match
[14:35:49] [PASSED] pf_negotiate_base_newer
[14:35:49] [PASSED] pf_negotiate_base_next
[14:35:49] [SKIPPED] pf_negotiate_base_older
[14:35:49] [PASSED] pf_negotiate_base_prev
[14:35:49] [PASSED] pf_negotiate_latest_match
[14:35:49] [PASSED] pf_negotiate_latest_newer
[14:35:49] [PASSED] pf_negotiate_latest_next
[14:35:49] [SKIPPED] pf_negotiate_latest_older
[14:35:49] [SKIPPED] pf_negotiate_latest_prev
[14:35:49] =================== [PASSED] pf_service ====================
[14:35:49] ================= xe_guc_g2g (2 subtests) ==================
[14:35:49] ============== xe_live_guc_g2g_kunit_default  ==============
[14:35:49] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[14:35:49] ============== xe_live_guc_g2g_kunit_allmem  ===============
[14:35:49] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[14:35:49] =================== [SKIPPED] xe_guc_g2g ===================
[14:35:49] =================== xe_mocs (2 subtests) ===================
[14:35:49] ================ xe_live_mocs_kernel_kunit  ================
[14:35:49] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[14:35:49] ================ xe_live_mocs_reset_kunit  =================
[14:35:49] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[14:35:49] ==================== [SKIPPED] xe_mocs =====================
[14:35:49] ================= xe_migrate (2 subtests) ==================
[14:35:49] ================= xe_migrate_sanity_kunit  =================
[14:35:49] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[14:35:49] ================== xe_validate_ccs_kunit  ==================
[14:35:49] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[14:35:49] =================== [SKIPPED] xe_migrate ===================
[14:35:49] ================== xe_dma_buf (1 subtest) ==================
[14:35:49] ==================== xe_dma_buf_kunit  =====================
[14:35:49] ================ [SKIPPED] xe_dma_buf_kunit ================
[14:35:49] =================== [SKIPPED] xe_dma_buf ===================
[14:35:49] ================= xe_bo_shrink (1 subtest) =================
[14:35:49] =================== xe_bo_shrink_kunit  ====================
[14:35:49] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[14:35:49] ================== [SKIPPED] xe_bo_shrink ==================
[14:35:49] ==================== xe_bo (2 subtests) ====================
[14:35:49] ================== xe_ccs_migrate_kunit  ===================
[14:35:49] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[14:35:49] ==================== xe_bo_evict_kunit  ====================
[14:35:49] =============== [SKIPPED] xe_bo_evict_kunit ================
[14:35:49] ===================== [SKIPPED] xe_bo ======================
[14:35:49] ==================== args (11 subtests) ====================
[14:35:49] [PASSED] count_args_test
[14:35:49] [PASSED] call_args_example
[14:35:49] [PASSED] call_args_test
[14:35:49] [PASSED] drop_first_arg_example
[14:35:49] [PASSED] drop_first_arg_test
[14:35:49] [PASSED] first_arg_example
[14:35:49] [PASSED] first_arg_test
[14:35:49] [PASSED] last_arg_example
[14:35:49] [PASSED] last_arg_test
[14:35:49] [PASSED] pick_arg_example
[14:35:49] [PASSED] sep_comma_example
[14:35:49] ====================== [PASSED] args =======================
[14:35:49] =================== xe_pci (3 subtests) ====================
[14:35:49] ==================== check_graphics_ip  ====================
[14:35:49] [PASSED] 12.00 Xe_LP
[14:35:49] [PASSED] 12.10 Xe_LP+
[14:35:49] [PASSED] 12.55 Xe_HPG
[14:35:49] [PASSED] 12.60 Xe_HPC
[14:35:49] [PASSED] 12.70 Xe_LPG
[14:35:49] [PASSED] 12.71 Xe_LPG
[14:35:49] [PASSED] 12.74 Xe_LPG+
[14:35:49] [PASSED] 20.01 Xe2_HPG
[14:35:49] [PASSED] 20.02 Xe2_HPG
[14:35:49] [PASSED] 20.04 Xe2_LPG
[14:35:49] [PASSED] 30.00 Xe3_LPG
[14:35:49] [PASSED] 30.01 Xe3_LPG
[14:35:49] [PASSED] 30.03 Xe3_LPG
[14:35:49] ================ [PASSED] check_graphics_ip ================
[14:35:49] ===================== check_media_ip  ======================
[14:35:49] [PASSED] 12.00 Xe_M
[14:35:49] [PASSED] 12.55 Xe_HPM
[14:35:49] [PASSED] 13.00 Xe_LPM+
[14:35:49] [PASSED] 13.01 Xe2_HPM
[14:35:49] [PASSED] 20.00 Xe2_LPM
[14:35:49] [PASSED] 30.00 Xe3_LPM
[14:35:49] [PASSED] 30.02 Xe3_LPM
[14:35:49] ================= [PASSED] check_media_ip ==================
[14:35:49] ================= check_platform_gt_count  =================
[14:35:49] [PASSED] 0x9A60 (TIGERLAKE)
[14:35:49] [PASSED] 0x9A68 (TIGERLAKE)
[14:35:49] [PASSED] 0x9A70 (TIGERLAKE)
[14:35:49] [PASSED] 0x9A40 (TIGERLAKE)
[14:35:49] [PASSED] 0x9A49 (TIGERLAKE)
[14:35:49] [PASSED] 0x9A59 (TIGERLAKE)
[14:35:49] [PASSED] 0x9A78 (TIGERLAKE)
[14:35:49] [PASSED] 0x9AC0 (TIGERLAKE)
[14:35:49] [PASSED] 0x9AC9 (TIGERLAKE)
[14:35:49] [PASSED] 0x9AD9 (TIGERLAKE)
[14:35:49] [PASSED] 0x9AF8 (TIGERLAKE)
[14:35:49] [PASSED] 0x4C80 (ROCKETLAKE)
[14:35:49] [PASSED] 0x4C8A (ROCKETLAKE)
[14:35:49] [PASSED] 0x4C8B (ROCKETLAKE)
[14:35:49] [PASSED] 0x4C8C (ROCKETLAKE)
[14:35:49] [PASSED] 0x4C90 (ROCKETLAKE)
[14:35:49] [PASSED] 0x4C9A (ROCKETLAKE)
[14:35:49] [PASSED] 0x4680 (ALDERLAKE_S)
[14:35:49] [PASSED] 0x4682 (ALDERLAKE_S)
[14:35:49] [PASSED] 0x4688 (ALDERLAKE_S)
[14:35:49] [PASSED] 0x468A (ALDERLAKE_S)
[14:35:49] [PASSED] 0x468B (ALDERLAKE_S)
[14:35:49] [PASSED] 0x4690 (ALDERLAKE_S)
[14:35:49] [PASSED] 0x4692 (ALDERLAKE_S)
[14:35:49] [PASSED] 0x4693 (ALDERLAKE_S)
[14:35:49] [PASSED] 0x46A0 (ALDERLAKE_P)
[14:35:49] [PASSED] 0x46A1 (ALDERLAKE_P)
[14:35:49] [PASSED] 0x46A2 (ALDERLAKE_P)
[14:35:49] [PASSED] 0x46A3 (ALDERLAKE_P)
[14:35:49] [PASSED] 0x46A6 (ALDERLAKE_P)
[14:35:49] [PASSED] 0x46A8 (ALDERLAKE_P)
[14:35:49] [PASSED] 0x46AA (ALDERLAKE_P)
[14:35:49] [PASSED] 0x462A (ALDERLAKE_P)
[14:35:49] [PASSED] 0x4626 (ALDERLAKE_P)
[14:35:49] [PASSED] 0x4628 (ALDERLAKE_P)
[14:35:49] [PASSED] 0x46B0 (ALDERLAKE_P)
[14:35:49] [PASSED] 0x46B1 (ALDERLAKE_P)
[14:35:49] [PASSED] 0x46B2 (ALDERLAKE_P)
[14:35:49] [PASSED] 0x46B3 (ALDERLAKE_P)
[14:35:49] [PASSED] 0x46C0 (ALDERLAKE_P)
[14:35:49] [PASSED] 0x46C1 (ALDERLAKE_P)
[14:35:49] [PASSED] 0x46C2 (ALDERLAKE_P)
[14:35:49] [PASSED] 0x46C3 (ALDERLAKE_P)
[14:35:49] [PASSED] 0x46D0 (ALDERLAKE_N)
[14:35:49] [PASSED] 0x46D1 (ALDERLAKE_N)
[14:35:49] [PASSED] 0x46D2 (ALDERLAKE_N)
[14:35:49] [PASSED] 0x46D3 (ALDERLAKE_N)
[14:35:49] [PASSED] 0x46D4 (ALDERLAKE_N)
[14:35:49] [PASSED] 0xA721 (ALDERLAKE_P)
[14:35:49] [PASSED] 0xA7A1 (ALDERLAKE_P)
[14:35:49] [PASSED] 0xA7A9 (ALDERLAKE_P)
[14:35:49] [PASSED] 0xA7AC (ALDERLAKE_P)
[14:35:49] [PASSED] 0xA7AD (ALDERLAKE_P)
[14:35:49] [PASSED] 0xA720 (ALDERLAKE_P)
[14:35:49] [PASSED] 0xA7A0 (ALDERLAKE_P)
[14:35:49] [PASSED] 0xA7A8 (ALDERLAKE_P)
[14:35:49] [PASSED] 0xA7AA (ALDERLAKE_P)
[14:35:49] [PASSED] 0xA7AB (ALDERLAKE_P)
[14:35:49] [PASSED] 0xA780 (ALDERLAKE_S)
[14:35:49] [PASSED] 0xA781 (ALDERLAKE_S)
[14:35:49] [PASSED] 0xA782 (ALDERLAKE_S)
[14:35:49] [PASSED] 0xA783 (ALDERLAKE_S)
[14:35:49] [PASSED] 0xA788 (ALDERLAKE_S)
[14:35:49] [PASSED] 0xA789 (ALDERLAKE_S)
[14:35:49] [PASSED] 0xA78A (ALDERLAKE_S)
[14:35:49] [PASSED] 0xA78B (ALDERLAKE_S)
[14:35:49] [PASSED] 0x4905 (DG1)
[14:35:49] [PASSED] 0x4906 (DG1)
[14:35:49] [PASSED] 0x4907 (DG1)
[14:35:49] [PASSED] 0x4908 (DG1)
[14:35:49] [PASSED] 0x4909 (DG1)
[14:35:49] [PASSED] 0x56C0 (DG2)
[14:35:49] [PASSED] 0x56C2 (DG2)
[14:35:49] [PASSED] 0x56C1 (DG2)
[14:35:49] [PASSED] 0x7D51 (METEORLAKE)
[14:35:49] [PASSED] 0x7DD1 (METEORLAKE)
[14:35:49] [PASSED] 0x7D41 (METEORLAKE)
[14:35:49] [PASSED] 0x7D67 (METEORLAKE)
[14:35:49] [PASSED] 0xB640 (METEORLAKE)
[14:35:49] [PASSED] 0x56A0 (DG2)
[14:35:49] [PASSED] 0x56A1 (DG2)
[14:35:49] [PASSED] 0x56A2 (DG2)
[14:35:49] [PASSED] 0x56BE (DG2)
[14:35:49] [PASSED] 0x56BF (DG2)
[14:35:49] [PASSED] 0x5690 (DG2)
[14:35:49] [PASSED] 0x5691 (DG2)
[14:35:49] [PASSED] 0x5692 (DG2)
[14:35:49] [PASSED] 0x56A5 (DG2)
[14:35:49] [PASSED] 0x56A6 (DG2)
[14:35:49] [PASSED] 0x56B0 (DG2)
[14:35:49] [PASSED] 0x56B1 (DG2)
[14:35:49] [PASSED] 0x56BA (DG2)
[14:35:49] [PASSED] 0x56BB (DG2)
[14:35:49] [PASSED] 0x56BC (DG2)
[14:35:49] [PASSED] 0x56BD (DG2)
[14:35:49] [PASSED] 0x5693 (DG2)
[14:35:49] [PASSED] 0x5694 (DG2)
[14:35:49] [PASSED] 0x5695 (DG2)
[14:35:49] [PASSED] 0x56A3 (DG2)
[14:35:49] [PASSED] 0x56A4 (DG2)
[14:35:49] [PASSED] 0x56B2 (DG2)
[14:35:49] [PASSED] 0x56B3 (DG2)
[14:35:49] [PASSED] 0x5696 (DG2)
[14:35:49] [PASSED] 0x5697 (DG2)
[14:35:49] [PASSED] 0xB69 (PVC)
[14:35:49] [PASSED] 0xB6E (PVC)
[14:35:49] [PASSED] 0xBD4 (PVC)
[14:35:49] [PASSED] 0xBD5 (PVC)
[14:35:49] [PASSED] 0xBD6 (PVC)
[14:35:49] [PASSED] 0xBD7 (PVC)
[14:35:49] [PASSED] 0xBD8 (PVC)
[14:35:49] [PASSED] 0xBD9 (PVC)
[14:35:49] [PASSED] 0xBDA (PVC)
[14:35:49] [PASSED] 0xBDB (PVC)
[14:35:49] [PASSED] 0xBE0 (PVC)
[14:35:49] [PASSED] 0xBE1 (PVC)
[14:35:49] [PASSED] 0xBE5 (PVC)
[14:35:49] [PASSED] 0x7D40 (METEORLAKE)
[14:35:49] [PASSED] 0x7D45 (METEORLAKE)
[14:35:49] [PASSED] 0x7D55 (METEORLAKE)
[14:35:49] [PASSED] 0x7D60 (METEORLAKE)
[14:35:49] [PASSED] 0x7DD5 (METEORLAKE)
[14:35:49] [PASSED] 0x6420 (LUNARLAKE)
[14:35:49] [PASSED] 0x64A0 (LUNARLAKE)
[14:35:49] [PASSED] 0x64B0 (LUNARLAKE)
[14:35:49] [PASSED] 0xE202 (BATTLEMAGE)
[14:35:49] [PASSED] 0xE209 (BATTLEMAGE)
[14:35:49] [PASSED] 0xE20B (BATTLEMAGE)
[14:35:49] [PASSED] 0xE20C (BATTLEMAGE)
[14:35:49] [PASSED] 0xE20D (BATTLEMAGE)
[14:35:49] [PASSED] 0xE210 (BATTLEMAGE)
[14:35:49] [PASSED] 0xE211 (BATTLEMAGE)
[14:35:49] [PASSED] 0xE212 (BATTLEMAGE)
[14:35:49] [PASSED] 0xE216 (BATTLEMAGE)
[14:35:49] [PASSED] 0xE220 (BATTLEMAGE)
[14:35:49] [PASSED] 0xE221 (BATTLEMAGE)
[14:35:49] [PASSED] 0xE222 (BATTLEMAGE)
[14:35:49] [PASSED] 0xE223 (BATTLEMAGE)
[14:35:49] [PASSED] 0xB080 (PANTHERLAKE)
[14:35:49] [PASSED] 0xB081 (PANTHERLAKE)
[14:35:49] [PASSED] 0xB082 (PANTHERLAKE)
[14:35:49] [PASSED] 0xB083 (PANTHERLAKE)
[14:35:49] [PASSED] 0xB084 (PANTHERLAKE)
[14:35:49] [PASSED] 0xB085 (PANTHERLAKE)
[14:35:49] [PASSED] 0xB086 (PANTHERLAKE)
[14:35:49] [PASSED] 0xB087 (PANTHERLAKE)
[14:35:49] [PASSED] 0xB08F (PANTHERLAKE)
[14:35:49] [PASSED] 0xB090 (PANTHERLAKE)
[14:35:49] [PASSED] 0xB0A0 (PANTHERLAKE)
[14:35:49] [PASSED] 0xB0B0 (PANTHERLAKE)
[14:35:49] [PASSED] 0xFD80 (PANTHERLAKE)
[14:35:49] [PASSED] 0xFD81 (PANTHERLAKE)
[14:35:49] ============= [PASSED] check_platform_gt_count =============
[14:35:49] ===================== [PASSED] xe_pci ======================
[14:35:49] =================== xe_rtp (2 subtests) ====================
[14:35:49] =============== xe_rtp_process_to_sr_tests  ================
[14:35:49] [PASSED] coalesce-same-reg
[14:35:49] [PASSED] no-match-no-add
[14:35:49] [PASSED] match-or
[14:35:49] [PASSED] match-or-xfail
[14:35:49] [PASSED] no-match-no-add-multiple-rules
[14:35:49] [PASSED] two-regs-two-entries
[14:35:49] [PASSED] clr-one-set-other
[14:35:49] [PASSED] set-field
[14:35:49] [PASSED] conflict-duplicate
[14:35:49] [PASSED] conflict-not-disjoint
[14:35:49] [PASSED] conflict-reg-type
[14:35:49] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[14:35:49] ================== xe_rtp_process_tests  ===================
[14:35:49] [PASSED] active1
[14:35:49] [PASSED] active2
[14:35:49] [PASSED] active-inactive
[14:35:49] [PASSED] inactive-active
[14:35:49] [PASSED] inactive-1st_or_active-inactive
[14:35:49] [PASSED] inactive-2nd_or_active-inactive
[14:35:49] [PASSED] inactive-last_or_active-inactive
[14:35:49] [PASSED] inactive-no_or_active-inactive
[14:35:49] ============== [PASSED] xe_rtp_process_tests ===============
[14:35:49] ===================== [PASSED] xe_rtp ======================
[14:35:49] ==================== xe_wa (1 subtest) =====================
[14:35:49] ======================== xe_wa_gt  =========================
[14:35:49] [PASSED] TIGERLAKE B0
[14:35:49] [PASSED] DG1 A0
[14:35:49] [PASSED] DG1 B0
[14:35:49] [PASSED] ALDERLAKE_S A0
[14:35:49] [PASSED] ALDERLAKE_S B0
stty: 'standard input': Inappropriate ioctl for device
[14:35:49] [PASSED] ALDERLAKE_S C0
[14:35:49] [PASSED] ALDERLAKE_S D0
[14:35:49] [PASSED] ALDERLAKE_P A0
[14:35:49] [PASSED] ALDERLAKE_P B0
[14:35:49] [PASSED] ALDERLAKE_P C0
[14:35:49] [PASSED] ALDERLAKE_S RPLS D0
[14:35:49] [PASSED] ALDERLAKE_P RPLU E0
[14:35:49] [PASSED] DG2 G10 C0
[14:35:49] [PASSED] DG2 G11 B1
[14:35:49] [PASSED] DG2 G12 A1
[14:35:49] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[14:35:49] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[14:35:49] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[14:35:49] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[14:35:49] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[14:35:49] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[14:35:49] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[14:35:49] ==================== [PASSED] xe_wa_gt =====================
[14:35:49] ====================== [PASSED] xe_wa ======================
[14:35:49] ============================================================
[14:35:49] Testing complete. Ran 306 tests: passed: 288, skipped: 18
[14:35:49] Elapsed time: 34.264s total, 4.313s configuring, 29.584s building, 0.320s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[14:35:49] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[14:35:51] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[14:36:14] Starting KUnit Kernel (1/1)...
[14:36:14] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[14:36:15] ============ drm_test_pick_cmdline (2 subtests) ============
[14:36:15] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[14:36:15] =============== drm_test_pick_cmdline_named  ===============
[14:36:15] [PASSED] NTSC
[14:36:15] [PASSED] NTSC-J
[14:36:15] [PASSED] PAL
[14:36:15] [PASSED] PAL-M
[14:36:15] =========== [PASSED] drm_test_pick_cmdline_named ===========
[14:36:15] ============== [PASSED] drm_test_pick_cmdline ==============
[14:36:15] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[14:36:15] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[14:36:15] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[14:36:15] =========== drm_validate_clone_mode (2 subtests) ===========
[14:36:15] ============== drm_test_check_in_clone_mode  ===============
[14:36:15] [PASSED] in_clone_mode
[14:36:15] [PASSED] not_in_clone_mode
[14:36:15] ========== [PASSED] drm_test_check_in_clone_mode ===========
[14:36:15] =============== drm_test_check_valid_clones  ===============
[14:36:15] [PASSED] not_in_clone_mode
[14:36:15] [PASSED] valid_clone
[14:36:15] [PASSED] invalid_clone
[14:36:15] =========== [PASSED] drm_test_check_valid_clones ===========
[14:36:15] ============= [PASSED] drm_validate_clone_mode =============
[14:36:15] ============= drm_validate_modeset (1 subtest) =============
[14:36:15] [PASSED] drm_test_check_connector_changed_modeset
[14:36:15] ============== [PASSED] drm_validate_modeset ===============
[14:36:15] ====== drm_test_bridge_get_current_state (2 subtests) ======
[14:36:15] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[14:36:15] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[14:36:15] ======== [PASSED] drm_test_bridge_get_current_state ========
[14:36:15] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[14:36:15] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[14:36:15] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[14:36:15] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[14:36:15] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[14:36:15] ============== drm_bridge_alloc (2 subtests) ===============
[14:36:15] [PASSED] drm_test_drm_bridge_alloc_basic
[14:36:15] [PASSED] drm_test_drm_bridge_alloc_get_put
[14:36:15] ================ [PASSED] drm_bridge_alloc =================
[14:36:15] ================== drm_buddy (7 subtests) ==================
[14:36:15] [PASSED] drm_test_buddy_alloc_limit
[14:36:15] [PASSED] drm_test_buddy_alloc_optimistic
[14:36:15] [PASSED] drm_test_buddy_alloc_pessimistic
[14:36:15] [PASSED] drm_test_buddy_alloc_pathological
[14:36:15] [PASSED] drm_test_buddy_alloc_contiguous
[14:36:15] [PASSED] drm_test_buddy_alloc_clear
[14:36:15] [PASSED] drm_test_buddy_alloc_range_bias
[14:36:15] ==================== [PASSED] drm_buddy ====================
[14:36:15] ============= drm_cmdline_parser (40 subtests) =============
[14:36:15] [PASSED] drm_test_cmdline_force_d_only
[14:36:15] [PASSED] drm_test_cmdline_force_D_only_dvi
[14:36:15] [PASSED] drm_test_cmdline_force_D_only_hdmi
[14:36:15] [PASSED] drm_test_cmdline_force_D_only_not_digital
[14:36:15] [PASSED] drm_test_cmdline_force_e_only
[14:36:15] [PASSED] drm_test_cmdline_res
[14:36:15] [PASSED] drm_test_cmdline_res_vesa
[14:36:15] [PASSED] drm_test_cmdline_res_vesa_rblank
[14:36:15] [PASSED] drm_test_cmdline_res_rblank
[14:36:15] [PASSED] drm_test_cmdline_res_bpp
[14:36:15] [PASSED] drm_test_cmdline_res_refresh
[14:36:15] [PASSED] drm_test_cmdline_res_bpp_refresh
[14:36:15] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[14:36:15] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[14:36:15] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[14:36:15] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[14:36:15] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[14:36:15] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[14:36:15] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[14:36:15] [PASSED] drm_test_cmdline_res_margins_force_on
[14:36:15] [PASSED] drm_test_cmdline_res_vesa_margins
[14:36:15] [PASSED] drm_test_cmdline_name
[14:36:15] [PASSED] drm_test_cmdline_name_bpp
[14:36:15] [PASSED] drm_test_cmdline_name_option
[14:36:15] [PASSED] drm_test_cmdline_name_bpp_option
[14:36:15] [PASSED] drm_test_cmdline_rotate_0
[14:36:15] [PASSED] drm_test_cmdline_rotate_90
[14:36:15] [PASSED] drm_test_cmdline_rotate_180
[14:36:15] [PASSED] drm_test_cmdline_rotate_270
[14:36:15] [PASSED] drm_test_cmdline_hmirror
[14:36:15] [PASSED] drm_test_cmdline_vmirror
[14:36:15] [PASSED] drm_test_cmdline_margin_options
[14:36:15] [PASSED] drm_test_cmdline_multiple_options
[14:36:15] [PASSED] drm_test_cmdline_bpp_extra_and_option
[14:36:15] [PASSED] drm_test_cmdline_extra_and_option
[14:36:15] [PASSED] drm_test_cmdline_freestanding_options
[14:36:15] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[14:36:15] [PASSED] drm_test_cmdline_panel_orientation
[14:36:15] ================ drm_test_cmdline_invalid  =================
[14:36:15] [PASSED] margin_only
[14:36:15] [PASSED] interlace_only
[14:36:15] [PASSED] res_missing_x
[14:36:15] [PASSED] res_missing_y
[14:36:15] [PASSED] res_bad_y
[14:36:15] [PASSED] res_missing_y_bpp
[14:36:15] [PASSED] res_bad_bpp
[14:36:15] [PASSED] res_bad_refresh
[14:36:15] [PASSED] res_bpp_refresh_force_on_off
[14:36:15] [PASSED] res_invalid_mode
[14:36:15] [PASSED] res_bpp_wrong_place_mode
[14:36:15] [PASSED] name_bpp_refresh
[14:36:15] [PASSED] name_refresh
[14:36:15] [PASSED] name_refresh_wrong_mode
[14:36:15] [PASSED] name_refresh_invalid_mode
[14:36:15] [PASSED] rotate_multiple
[14:36:15] [PASSED] rotate_invalid_val
[14:36:15] [PASSED] rotate_truncated
[14:36:15] [PASSED] invalid_option
[14:36:15] [PASSED] invalid_tv_option
[14:36:15] [PASSED] truncated_tv_option
[14:36:15] ============ [PASSED] drm_test_cmdline_invalid =============
[14:36:15] =============== drm_test_cmdline_tv_options  ===============
[14:36:15] [PASSED] NTSC
[14:36:15] [PASSED] NTSC_443
[14:36:15] [PASSED] NTSC_J
[14:36:15] [PASSED] PAL
[14:36:15] [PASSED] PAL_M
[14:36:15] [PASSED] PAL_N
[14:36:15] [PASSED] SECAM
[14:36:15] [PASSED] MONO_525
[14:36:15] [PASSED] MONO_625
[14:36:15] =========== [PASSED] drm_test_cmdline_tv_options ===========
[14:36:15] =============== [PASSED] drm_cmdline_parser ================
[14:36:15] ========== drmm_connector_hdmi_init (20 subtests) ==========
[14:36:15] [PASSED] drm_test_connector_hdmi_init_valid
[14:36:15] [PASSED] drm_test_connector_hdmi_init_bpc_8
[14:36:15] [PASSED] drm_test_connector_hdmi_init_bpc_10
[14:36:15] [PASSED] drm_test_connector_hdmi_init_bpc_12
[14:36:15] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[14:36:15] [PASSED] drm_test_connector_hdmi_init_bpc_null
[14:36:15] [PASSED] drm_test_connector_hdmi_init_formats_empty
[14:36:15] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[14:36:15] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[14:36:15] [PASSED] supported_formats=0x9 yuv420_allowed=1
[14:36:15] [PASSED] supported_formats=0x9 yuv420_allowed=0
[14:36:15] [PASSED] supported_formats=0x3 yuv420_allowed=1
[14:36:15] [PASSED] supported_formats=0x3 yuv420_allowed=0
[14:36:15] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[14:36:15] [PASSED] drm_test_connector_hdmi_init_null_ddc
[14:36:15] [PASSED] drm_test_connector_hdmi_init_null_product
[14:36:15] [PASSED] drm_test_connector_hdmi_init_null_vendor
[14:36:15] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[14:36:15] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[14:36:15] [PASSED] drm_test_connector_hdmi_init_product_valid
[14:36:15] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[14:36:15] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[14:36:15] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[14:36:15] ========= drm_test_connector_hdmi_init_type_valid  =========
[14:36:15] [PASSED] HDMI-A
[14:36:15] [PASSED] HDMI-B
[14:36:15] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[14:36:15] ======== drm_test_connector_hdmi_init_type_invalid  ========
[14:36:15] [PASSED] Unknown
[14:36:15] [PASSED] VGA
[14:36:15] [PASSED] DVI-I
[14:36:15] [PASSED] DVI-D
[14:36:15] [PASSED] DVI-A
[14:36:15] [PASSED] Composite
[14:36:15] [PASSED] SVIDEO
[14:36:15] [PASSED] LVDS
[14:36:15] [PASSED] Component
[14:36:15] [PASSED] DIN
[14:36:15] [PASSED] DP
[14:36:15] [PASSED] TV
[14:36:15] [PASSED] eDP
[14:36:15] [PASSED] Virtual
[14:36:15] [PASSED] DSI
[14:36:15] [PASSED] DPI
[14:36:15] [PASSED] Writeback
[14:36:15] [PASSED] SPI
[14:36:15] [PASSED] USB
[14:36:15] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[14:36:15] ============ [PASSED] drmm_connector_hdmi_init =============
[14:36:15] ============= drmm_connector_init (3 subtests) =============
[14:36:15] [PASSED] drm_test_drmm_connector_init
[14:36:15] [PASSED] drm_test_drmm_connector_init_null_ddc
[14:36:15] ========= drm_test_drmm_connector_init_type_valid  =========
[14:36:15] [PASSED] Unknown
[14:36:15] [PASSED] VGA
[14:36:15] [PASSED] DVI-I
[14:36:15] [PASSED] DVI-D
[14:36:15] [PASSED] DVI-A
[14:36:15] [PASSED] Composite
[14:36:15] [PASSED] SVIDEO
[14:36:15] [PASSED] LVDS
[14:36:15] [PASSED] Component
[14:36:15] [PASSED] DIN
[14:36:15] [PASSED] DP
[14:36:15] [PASSED] HDMI-A
[14:36:15] [PASSED] HDMI-B
[14:36:15] [PASSED] TV
[14:36:15] [PASSED] eDP
[14:36:15] [PASSED] Virtual
[14:36:15] [PASSED] DSI
[14:36:15] [PASSED] DPI
[14:36:15] [PASSED] Writeback
[14:36:15] [PASSED] SPI
[14:36:15] [PASSED] USB
[14:36:15] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[14:36:15] =============== [PASSED] drmm_connector_init ===============
[14:36:15] ========= drm_connector_dynamic_init (6 subtests) ==========
[14:36:15] [PASSED] drm_test_drm_connector_dynamic_init
[14:36:15] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[14:36:15] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[14:36:15] [PASSED] drm_test_drm_connector_dynamic_init_properties
[14:36:15] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[14:36:15] [PASSED] Unknown
[14:36:15] [PASSED] VGA
[14:36:15] [PASSED] DVI-I
[14:36:15] [PASSED] DVI-D
[14:36:15] [PASSED] DVI-A
[14:36:15] [PASSED] Composite
[14:36:15] [PASSED] SVIDEO
[14:36:15] [PASSED] LVDS
[14:36:15] [PASSED] Component
[14:36:15] [PASSED] DIN
[14:36:15] [PASSED] DP
[14:36:15] [PASSED] HDMI-A
[14:36:15] [PASSED] HDMI-B
[14:36:15] [PASSED] TV
[14:36:15] [PASSED] eDP
[14:36:15] [PASSED] Virtual
[14:36:15] [PASSED] DSI
[14:36:15] [PASSED] DPI
[14:36:15] [PASSED] Writeback
[14:36:15] [PASSED] SPI
[14:36:15] [PASSED] USB
[14:36:15] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[14:36:15] ======== drm_test_drm_connector_dynamic_init_name  =========
[14:36:15] [PASSED] Unknown
[14:36:15] [PASSED] VGA
[14:36:15] [PASSED] DVI-I
[14:36:15] [PASSED] DVI-D
[14:36:15] [PASSED] DVI-A
[14:36:15] [PASSED] Composite
[14:36:15] [PASSED] SVIDEO
[14:36:15] [PASSED] LVDS
[14:36:15] [PASSED] Component
[14:36:15] [PASSED] DIN
[14:36:15] [PASSED] DP
[14:36:15] [PASSED] HDMI-A
[14:36:15] [PASSED] HDMI-B
[14:36:15] [PASSED] TV
[14:36:15] [PASSED] eDP
[14:36:15] [PASSED] Virtual
[14:36:15] [PASSED] DSI
[14:36:15] [PASSED] DPI
[14:36:15] [PASSED] Writeback
[14:36:15] [PASSED] SPI
[14:36:15] [PASSED] USB
[14:36:15] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[14:36:15] =========== [PASSED] drm_connector_dynamic_init ============
[14:36:15] ==== drm_connector_dynamic_register_early (4 subtests) =====
[14:36:15] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[14:36:15] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[14:36:15] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[14:36:15] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[14:36:15] ====== [PASSED] drm_connector_dynamic_register_early =======
[14:36:15] ======= drm_connector_dynamic_register (7 subtests) ========
[14:36:15] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[14:36:15] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[14:36:15] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[14:36:15] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[14:36:15] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[14:36:15] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[14:36:15] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[14:36:15] ========= [PASSED] drm_connector_dynamic_register ==========
[14:36:15] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[14:36:15] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[14:36:15] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[14:36:15] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[14:36:15] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[14:36:15] ========== drm_test_get_tv_mode_from_name_valid  ===========
[14:36:15] [PASSED] NTSC
[14:36:15] [PASSED] NTSC-443
[14:36:15] [PASSED] NTSC-J
[14:36:15] [PASSED] PAL
[14:36:15] [PASSED] PAL-M
[14:36:15] [PASSED] PAL-N
[14:36:15] [PASSED] SECAM
[14:36:15] [PASSED] Mono
[14:36:15] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[14:36:15] [PASSED] drm_test_get_tv_mode_from_name_truncated
[14:36:15] ============ [PASSED] drm_get_tv_mode_from_name ============
[14:36:15] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[14:36:15] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[14:36:15] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[14:36:15] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[14:36:15] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[14:36:15] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[14:36:15] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[14:36:15] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[14:36:15] [PASSED] VIC 96
[14:36:15] [PASSED] VIC 97
[14:36:15] [PASSED] VIC 101
[14:36:15] [PASSED] VIC 102
[14:36:15] [PASSED] VIC 106
[14:36:15] [PASSED] VIC 107
[14:36:15] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[14:36:15] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[14:36:15] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[14:36:15] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[14:36:15] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[14:36:15] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[14:36:15] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[14:36:15] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[14:36:15] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[14:36:15] [PASSED] Automatic
[14:36:15] [PASSED] Full
[14:36:15] [PASSED] Limited 16:235
[14:36:15] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[14:36:15] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[14:36:15] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[14:36:15] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[14:36:15] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[14:36:15] [PASSED] RGB
[14:36:15] [PASSED] YUV 4:2:0
[14:36:15] [PASSED] YUV 4:2:2
[14:36:15] [PASSED] YUV 4:4:4
[14:36:15] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[14:36:15] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[14:36:15] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[14:36:15] ============= drm_damage_helper (21 subtests) ==============
[14:36:15] [PASSED] drm_test_damage_iter_no_damage
[14:36:15] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[14:36:15] [PASSED] drm_test_damage_iter_no_damage_src_moved
[14:36:15] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[14:36:15] [PASSED] drm_test_damage_iter_no_damage_not_visible
[14:36:15] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[14:36:15] [PASSED] drm_test_damage_iter_no_damage_no_fb
[14:36:15] [PASSED] drm_test_damage_iter_simple_damage
[14:36:15] [PASSED] drm_test_damage_iter_single_damage
[14:36:15] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[14:36:15] [PASSED] drm_test_damage_iter_single_damage_outside_src
[14:36:15] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[14:36:15] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[14:36:15] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[14:36:15] [PASSED] drm_test_damage_iter_single_damage_src_moved
[14:36:15] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[14:36:15] [PASSED] drm_test_damage_iter_damage
[14:36:15] [PASSED] drm_test_damage_iter_damage_one_intersect
[14:36:15] [PASSED] drm_test_damage_iter_damage_one_outside
[14:36:15] [PASSED] drm_test_damage_iter_damage_src_moved
[14:36:15] [PASSED] drm_test_damage_iter_damage_not_visible
[14:36:15] ================ [PASSED] drm_damage_helper ================
[14:36:15] ============== drm_dp_mst_helper (3 subtests) ==============
[14:36:15] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[14:36:15] [PASSED] Clock 154000 BPP 30 DSC disabled
[14:36:15] [PASSED] Clock 234000 BPP 30 DSC disabled
[14:36:15] [PASSED] Clock 297000 BPP 24 DSC disabled
[14:36:15] [PASSED] Clock 332880 BPP 24 DSC enabled
[14:36:15] [PASSED] Clock 324540 BPP 24 DSC enabled
[14:36:15] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[14:36:15] ============== drm_test_dp_mst_calc_pbn_div  ===============
[14:36:15] [PASSED] Link rate 2000000 lane count 4
[14:36:15] [PASSED] Link rate 2000000 lane count 2
[14:36:15] [PASSED] Link rate 2000000 lane count 1
[14:36:15] [PASSED] Link rate 1350000 lane count 4
[14:36:15] [PASSED] Link rate 1350000 lane count 2
[14:36:15] [PASSED] Link rate 1350000 lane count 1
[14:36:15] [PASSED] Link rate 1000000 lane count 4
[14:36:15] [PASSED] Link rate 1000000 lane count 2
[14:36:15] [PASSED] Link rate 1000000 lane count 1
[14:36:15] [PASSED] Link rate 810000 lane count 4
[14:36:15] [PASSED] Link rate 810000 lane count 2
[14:36:15] [PASSED] Link rate 810000 lane count 1
[14:36:15] [PASSED] Link rate 540000 lane count 4
[14:36:15] [PASSED] Link rate 540000 lane count 2
[14:36:15] [PASSED] Link rate 540000 lane count 1
[14:36:15] [PASSED] Link rate 270000 lane count 4
[14:36:15] [PASSED] Link rate 270000 lane count 2
[14:36:15] [PASSED] Link rate 270000 lane count 1
[14:36:15] [PASSED] Link rate 162000 lane count 4
[14:36:15] [PASSED] Link rate 162000 lane count 2
[14:36:15] [PASSED] Link rate 162000 lane count 1
[14:36:15] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[14:36:15] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[14:36:15] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[14:36:15] [PASSED] DP_POWER_UP_PHY with port number
[14:36:15] [PASSED] DP_POWER_DOWN_PHY with port number
[14:36:15] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[14:36:15] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[14:36:15] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[14:36:15] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[14:36:15] [PASSED] DP_QUERY_PAYLOAD with port number
[14:36:15] [PASSED] DP_QUERY_PAYLOAD with VCPI
[14:36:15] [PASSED] DP_REMOTE_DPCD_READ with port number
[14:36:15] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[14:36:15] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[14:36:15] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[14:36:15] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[14:36:15] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[14:36:15] [PASSED] DP_REMOTE_I2C_READ with port number
[14:36:15] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[14:36:15] [PASSED] DP_REMOTE_I2C_READ with transactions array
[14:36:15] [PASSED] DP_REMOTE_I2C_WRITE with port number
[14:36:15] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[14:36:15] [PASSED] DP_REMOTE_I2C_WRITE with data array
[14:36:15] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[14:36:15] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[14:36:15] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[14:36:15] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[14:36:15] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[14:36:15] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[14:36:15] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[14:36:15] ================ [PASSED] drm_dp_mst_helper ================
[14:36:15] ================== drm_exec (7 subtests) ===================
[14:36:15] [PASSED] sanitycheck
[14:36:15] [PASSED] test_lock
[14:36:15] [PASSED] test_lock_unlock
[14:36:15] [PASSED] test_duplicates
[14:36:15] [PASSED] test_prepare
[14:36:15] [PASSED] test_prepare_array
[14:36:15] [PASSED] test_multiple_loops
[14:36:15] ==================== [PASSED] drm_exec =====================
[14:36:15] =========== drm_format_helper_test (17 subtests) ===========
[14:36:15] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[14:36:15] [PASSED] single_pixel_source_buffer
[14:36:15] [PASSED] single_pixel_clip_rectangle
[14:36:15] [PASSED] well_known_colors
[14:36:15] [PASSED] destination_pitch
[14:36:15] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[14:36:15] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[14:36:15] [PASSED] single_pixel_source_buffer
[14:36:15] [PASSED] single_pixel_clip_rectangle
[14:36:15] [PASSED] well_known_colors
[14:36:15] [PASSED] destination_pitch
[14:36:15] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[14:36:15] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[14:36:15] [PASSED] single_pixel_source_buffer
[14:36:15] [PASSED] single_pixel_clip_rectangle
[14:36:15] [PASSED] well_known_colors
[14:36:15] [PASSED] destination_pitch
[14:36:15] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[14:36:15] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[14:36:15] [PASSED] single_pixel_source_buffer
[14:36:15] [PASSED] single_pixel_clip_rectangle
[14:36:15] [PASSED] well_known_colors
[14:36:15] [PASSED] destination_pitch
[14:36:15] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[14:36:15] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[14:36:15] [PASSED] single_pixel_source_buffer
[14:36:15] [PASSED] single_pixel_clip_rectangle
[14:36:15] [PASSED] well_known_colors
[14:36:15] [PASSED] destination_pitch
[14:36:15] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[14:36:15] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[14:36:15] [PASSED] single_pixel_source_buffer
[14:36:15] [PASSED] single_pixel_clip_rectangle
[14:36:15] [PASSED] well_known_colors
[14:36:15] [PASSED] destination_pitch
[14:36:15] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[14:36:15] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[14:36:15] [PASSED] single_pixel_source_buffer
[14:36:15] [PASSED] single_pixel_clip_rectangle
[14:36:15] [PASSED] well_known_colors
[14:36:15] [PASSED] destination_pitch
[14:36:15] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[14:36:15] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[14:36:15] [PASSED] single_pixel_source_buffer
[14:36:15] [PASSED] single_pixel_clip_rectangle
[14:36:15] [PASSED] well_known_colors
[14:36:15] [PASSED] destination_pitch
[14:36:15] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[14:36:15] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[14:36:15] [PASSED] single_pixel_source_buffer
[14:36:15] [PASSED] single_pixel_clip_rectangle
[14:36:15] [PASSED] well_known_colors
[14:36:15] [PASSED] destination_pitch
[14:36:15] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[14:36:15] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[14:36:15] [PASSED] single_pixel_source_buffer
[14:36:15] [PASSED] single_pixel_clip_rectangle
[14:36:15] [PASSED] well_known_colors
[14:36:15] [PASSED] destination_pitch
[14:36:15] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[14:36:15] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[14:36:15] [PASSED] single_pixel_source_buffer
[14:36:15] [PASSED] single_pixel_clip_rectangle
[14:36:15] [PASSED] well_known_colors
[14:36:15] [PASSED] destination_pitch
[14:36:15] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[14:36:15] ============== drm_test_fb_xrgb8888_to_mono  ===============
[14:36:15] [PASSED] single_pixel_source_buffer
[14:36:15] [PASSED] single_pixel_clip_rectangle
[14:36:15] [PASSED] well_known_colors
[14:36:15] [PASSED] destination_pitch
[14:36:15] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[14:36:15] ==================== drm_test_fb_swab  =====================
[14:36:15] [PASSED] single_pixel_source_buffer
[14:36:15] [PASSED] single_pixel_clip_rectangle
[14:36:15] [PASSED] well_known_colors
[14:36:15] [PASSED] destination_pitch
[14:36:15] ================ [PASSED] drm_test_fb_swab =================
[14:36:15] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[14:36:15] [PASSED] single_pixel_source_buffer
[14:36:15] [PASSED] single_pixel_clip_rectangle
[14:36:15] [PASSED] well_known_colors
[14:36:15] [PASSED] destination_pitch
[14:36:15] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[14:36:15] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[14:36:15] [PASSED] single_pixel_source_buffer
[14:36:15] [PASSED] single_pixel_clip_rectangle
[14:36:15] [PASSED] well_known_colors
[14:36:15] [PASSED] destination_pitch
[14:36:15] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[14:36:15] ================= drm_test_fb_clip_offset  =================
[14:36:15] [PASSED] pass through
[14:36:15] [PASSED] horizontal offset
[14:36:15] [PASSED] vertical offset
[14:36:15] [PASSED] horizontal and vertical offset
[14:36:15] [PASSED] horizontal offset (custom pitch)
[14:36:15] [PASSED] vertical offset (custom pitch)
[14:36:15] [PASSED] horizontal and vertical offset (custom pitch)
[14:36:15] ============= [PASSED] drm_test_fb_clip_offset =============
[14:36:15] =================== drm_test_fb_memcpy  ====================
[14:36:15] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[14:36:15] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[14:36:15] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[14:36:15] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[14:36:15] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[14:36:15] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[14:36:15] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[14:36:15] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[14:36:15] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[14:36:15] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[14:36:15] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[14:36:15] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[14:36:15] =============== [PASSED] drm_test_fb_memcpy ================
[14:36:15] ============= [PASSED] drm_format_helper_test ==============
[14:36:15] ================= drm_format (18 subtests) =================
[14:36:15] [PASSED] drm_test_format_block_width_invalid
[14:36:15] [PASSED] drm_test_format_block_width_one_plane
[14:36:15] [PASSED] drm_test_format_block_width_two_plane
[14:36:15] [PASSED] drm_test_format_block_width_three_plane
[14:36:15] [PASSED] drm_test_format_block_width_tiled
[14:36:15] [PASSED] drm_test_format_block_height_invalid
[14:36:15] [PASSED] drm_test_format_block_height_one_plane
[14:36:15] [PASSED] drm_test_format_block_height_two_plane
[14:36:15] [PASSED] drm_test_format_block_height_three_plane
[14:36:15] [PASSED] drm_test_format_block_height_tiled
[14:36:15] [PASSED] drm_test_format_min_pitch_invalid
[14:36:15] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[14:36:15] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[14:36:15] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[14:36:15] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[14:36:15] [PASSED] drm_test_format_min_pitch_two_plane
[14:36:15] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[14:36:15] [PASSED] drm_test_format_min_pitch_tiled
[14:36:15] =================== [PASSED] drm_format ====================
[14:36:15] ============== drm_framebuffer (10 subtests) ===============
[14:36:15] ========== drm_test_framebuffer_check_src_coords  ==========
[14:36:15] [PASSED] Success: source fits into fb
[14:36:15] [PASSED] Fail: overflowing fb with x-axis coordinate
[14:36:15] [PASSED] Fail: overflowing fb with y-axis coordinate
[14:36:15] [PASSED] Fail: overflowing fb with source width
[14:36:15] [PASSED] Fail: overflowing fb with source height
[14:36:15] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[14:36:15] [PASSED] drm_test_framebuffer_cleanup
[14:36:15] =============== drm_test_framebuffer_create  ===============
[14:36:15] [PASSED] ABGR8888 normal sizes
[14:36:15] [PASSED] ABGR8888 max sizes
[14:36:15] [PASSED] ABGR8888 pitch greater than min required
[14:36:15] [PASSED] ABGR8888 pitch less than min required
[14:36:15] [PASSED] ABGR8888 Invalid width
[14:36:15] [PASSED] ABGR8888 Invalid buffer handle
[14:36:15] [PASSED] No pixel format
[14:36:15] [PASSED] ABGR8888 Width 0
[14:36:15] [PASSED] ABGR8888 Height 0
[14:36:15] [PASSED] ABGR8888 Out of bound height * pitch combination
[14:36:15] [PASSED] ABGR8888 Large buffer offset
[14:36:15] [PASSED] ABGR8888 Buffer offset for inexistent plane
[14:36:15] [PASSED] ABGR8888 Invalid flag
[14:36:15] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[14:36:15] [PASSED] ABGR8888 Valid buffer modifier
[14:36:15] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[14:36:15] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[14:36:15] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[14:36:15] [PASSED] NV12 Normal sizes
[14:36:15] [PASSED] NV12 Max sizes
[14:36:15] [PASSED] NV12 Invalid pitch
[14:36:15] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[14:36:15] [PASSED] NV12 different  modifier per-plane
[14:36:15] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[14:36:15] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[14:36:15] [PASSED] NV12 Modifier for inexistent plane
[14:36:15] [PASSED] NV12 Handle for inexistent plane
[14:36:15] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[14:36:15] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[14:36:15] [PASSED] YVU420 Normal sizes
[14:36:15] [PASSED] YVU420 Max sizes
[14:36:15] [PASSED] YVU420 Invalid pitch
[14:36:15] [PASSED] YVU420 Different pitches
[14:36:15] [PASSED] YVU420 Different buffer offsets/pitches
[14:36:15] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[14:36:15] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[14:36:15] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[14:36:15] [PASSED] YVU420 Valid modifier
[14:36:15] [PASSED] YVU420 Different modifiers per plane
[14:36:15] [PASSED] YVU420 Modifier for inexistent plane
[14:36:15] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[14:36:15] [PASSED] X0L2 Normal sizes
[14:36:15] [PASSED] X0L2 Max sizes
[14:36:15] [PASSED] X0L2 Invalid pitch
[14:36:15] [PASSED] X0L2 Pitch greater than minimum required
[14:36:15] [PASSED] X0L2 Handle for inexistent plane
[14:36:15] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[14:36:15] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[14:36:15] [PASSED] X0L2 Valid modifier
[14:36:15] [PASSED] X0L2 Modifier for inexistent plane
[14:36:15] =========== [PASSED] drm_test_framebuffer_create ===========
[14:36:15] [PASSED] drm_test_framebuffer_free
[14:36:15] [PASSED] drm_test_framebuffer_init
[14:36:15] [PASSED] drm_test_framebuffer_init_bad_format
[14:36:15] [PASSED] drm_test_framebuffer_init_dev_mismatch
[14:36:15] [PASSED] drm_test_framebuffer_lookup
[14:36:15] [PASSED] drm_test_framebuffer_lookup_inexistent
[14:36:15] [PASSED] drm_test_framebuffer_modifiers_not_supported
[14:36:15] ================= [PASSED] drm_framebuffer =================
[14:36:15] ================ drm_gem_shmem (8 subtests) ================
[14:36:15] [PASSED] drm_gem_shmem_test_obj_create
[14:36:15] [PASSED] drm_gem_shmem_test_obj_create_private
[14:36:15] [PASSED] drm_gem_shmem_test_pin_pages
[14:36:15] [PASSED] drm_gem_shmem_test_vmap
[14:36:15] [PASSED] drm_gem_shmem_test_get_pages_sgt
[14:36:15] [PASSED] drm_gem_shmem_test_get_sg_table
[14:36:15] [PASSED] drm_gem_shmem_test_madvise
[14:36:15] [PASSED] drm_gem_shmem_test_purge
[14:36:15] ================== [PASSED] drm_gem_shmem ==================
[14:36:15] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[14:36:15] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[14:36:15] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[14:36:15] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[14:36:15] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[14:36:15] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[14:36:15] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[14:36:15] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[14:36:15] [PASSED] Automatic
[14:36:15] [PASSED] Full
[14:36:15] [PASSED] Limited 16:235
[14:36:15] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[14:36:15] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[14:36:15] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[14:36:15] [PASSED] drm_test_check_disable_connector
[14:36:15] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[14:36:15] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[14:36:15] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[14:36:15] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[14:36:15] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[14:36:15] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[14:36:15] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[14:36:15] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[14:36:15] [PASSED] drm_test_check_output_bpc_dvi
[14:36:15] [PASSED] drm_test_check_output_bpc_format_vic_1
[14:36:15] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[14:36:15] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[14:36:15] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[14:36:15] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[14:36:15] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[14:36:15] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[14:36:15] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[14:36:15] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[14:36:15] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[14:36:15] [PASSED] drm_test_check_broadcast_rgb_value
[14:36:15] [PASSED] drm_test_check_bpc_8_value
[14:36:15] [PASSED] drm_test_check_bpc_10_value
[14:36:15] [PASSED] drm_test_check_bpc_12_value
[14:36:15] [PASSED] drm_test_check_format_value
[14:36:15] [PASSED] drm_test_check_tmds_char_value
[14:36:15] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[14:36:15] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[14:36:15] [PASSED] drm_test_check_mode_valid
[14:36:15] [PASSED] drm_test_check_mode_valid_reject
[14:36:15] [PASSED] drm_test_check_mode_valid_reject_rate
[14:36:15] [PASSED] drm_test_check_mode_valid_reject_max_clock
[14:36:15] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[14:36:15] ================= drm_managed (2 subtests) =================
[14:36:15] [PASSED] drm_test_managed_release_action
[14:36:15] [PASSED] drm_test_managed_run_action
[14:36:15] =================== [PASSED] drm_managed ===================
[14:36:15] =================== drm_mm (6 subtests) ====================
[14:36:15] [PASSED] drm_test_mm_init
[14:36:15] [PASSED] drm_test_mm_debug
[14:36:15] [PASSED] drm_test_mm_align32
[14:36:15] [PASSED] drm_test_mm_align64
[14:36:15] [PASSED] drm_test_mm_lowest
[14:36:15] [PASSED] drm_test_mm_highest
[14:36:15] ===================== [PASSED] drm_mm ======================
[14:36:15] ============= drm_modes_analog_tv (5 subtests) =============
[14:36:15] [PASSED] drm_test_modes_analog_tv_mono_576i
[14:36:15] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[14:36:15] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[14:36:15] [PASSED] drm_test_modes_analog_tv_pal_576i
[14:36:15] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[14:36:15] =============== [PASSED] drm_modes_analog_tv ===============
[14:36:15] ============== drm_plane_helper (2 subtests) ===============
[14:36:15] =============== drm_test_check_plane_state  ================
[14:36:15] [PASSED] clipping_simple
[14:36:15] [PASSED] clipping_rotate_reflect
[14:36:15] [PASSED] positioning_simple
[14:36:15] [PASSED] upscaling
[14:36:15] [PASSED] downscaling
[14:36:15] [PASSED] rounding1
[14:36:15] [PASSED] rounding2
[14:36:15] [PASSED] rounding3
[14:36:15] [PASSED] rounding4
[14:36:15] =========== [PASSED] drm_test_check_plane_state ============
[14:36:15] =========== drm_test_check_invalid_plane_state  ============
[14:36:15] [PASSED] positioning_invalid
[14:36:15] [PASSED] upscaling_invalid
[14:36:15] [PASSED] downscaling_invalid
[14:36:15] ======= [PASSED] drm_test_check_invalid_plane_state ========
[14:36:15] ================ [PASSED] drm_plane_helper =================
[14:36:15] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[14:36:15] ====== drm_test_connector_helper_tv_get_modes_check  =======
[14:36:15] [PASSED] None
[14:36:15] [PASSED] PAL
[14:36:15] [PASSED] NTSC
[14:36:15] [PASSED] Both, NTSC Default
[14:36:15] [PASSED] Both, PAL Default
[14:36:15] [PASSED] Both, NTSC Default, with PAL on command-line
[14:36:15] [PASSED] Both, PAL Default, with NTSC on command-line
[14:36:15] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[14:36:15] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[14:36:15] ================== drm_rect (9 subtests) ===================
[14:36:15] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[14:36:15] [PASSED] drm_test_rect_clip_scaled_not_clipped
[14:36:15] [PASSED] drm_test_rect_clip_scaled_clipped
[14:36:15] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[14:36:15] ================= drm_test_rect_intersect  =================
[14:36:15] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[14:36:15] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[14:36:15] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[14:36:15] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[14:36:15] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[14:36:15] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[14:36:15] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[14:36:15] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[14:36:15] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[14:36:15] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[14:36:15] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[14:36:15] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[14:36:15] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[14:36:15] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[14:36:15] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[14:36:15] ============= [PASSED] drm_test_rect_intersect =============
[14:36:15] ================ drm_test_rect_calc_hscale  ================
[14:36:15] [PASSED] normal use
[14:36:15] [PASSED] out of max range
[14:36:15] [PASSED] out of min range
[14:36:15] [PASSED] zero dst
[14:36:15] [PASSED] negative src
[14:36:15] [PASSED] negative dst
[14:36:15] ============ [PASSED] drm_test_rect_calc_hscale ============
[14:36:15] ================ drm_test_rect_calc_vscale  ================
[14:36:15] [PASSED] normal use
[14:36:15] [PASSED] out of max range
[14:36:15] [PASSED] out of min range
[14:36:15] [PASSED] zero dst
[14:36:15] [PASSED] negative src
stty: 'standard input': Inappropriate ioctl for device
[14:36:15] [PASSED] negative dst
[14:36:15] ============ [PASSED] drm_test_rect_calc_vscale ============
[14:36:15] ================== drm_test_rect_rotate  ===================
[14:36:15] [PASSED] reflect-x
[14:36:15] [PASSED] reflect-y
[14:36:15] [PASSED] rotate-0
[14:36:15] [PASSED] rotate-90
[14:36:15] [PASSED] rotate-180
[14:36:15] [PASSED] rotate-270
[14:36:15] ============== [PASSED] drm_test_rect_rotate ===============
[14:36:15] ================ drm_test_rect_rotate_inv  =================
[14:36:15] [PASSED] reflect-x
[14:36:15] [PASSED] reflect-y
[14:36:15] [PASSED] rotate-0
[14:36:15] [PASSED] rotate-90
[14:36:15] [PASSED] rotate-180
[14:36:15] [PASSED] rotate-270
[14:36:15] ============ [PASSED] drm_test_rect_rotate_inv =============
[14:36:15] ==================== [PASSED] drm_rect =====================
[14:36:15] ============ drm_sysfb_modeset_test (1 subtest) ============
[14:36:15] ============ drm_test_sysfb_build_fourcc_list  =============
[14:36:15] [PASSED] no native formats
[14:36:15] [PASSED] XRGB8888 as native format
[14:36:15] [PASSED] remove duplicates
[14:36:15] [PASSED] convert alpha formats
[14:36:15] [PASSED] random formats
[14:36:15] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[14:36:15] ============= [PASSED] drm_sysfb_modeset_test ==============
[14:36:15] ============================================================
[14:36:15] Testing complete. Ran 621 tests: passed: 621
[14:36:15] Elapsed time: 25.752s total, 1.718s configuring, 23.868s building, 0.144s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[14:36:15] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[14:36:16] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[14:36:26] Starting KUnit Kernel (1/1)...
[14:36:26] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[14:36:26] ================= ttm_device (5 subtests) ==================
[14:36:26] [PASSED] ttm_device_init_basic
[14:36:26] [PASSED] ttm_device_init_multiple
[14:36:26] [PASSED] ttm_device_fini_basic
[14:36:26] [PASSED] ttm_device_init_no_vma_man
[14:36:26] ================== ttm_device_init_pools  ==================
[14:36:26] [PASSED] No DMA allocations, no DMA32 required
[14:36:26] [PASSED] DMA allocations, DMA32 required
[14:36:26] [PASSED] No DMA allocations, DMA32 required
[14:36:26] [PASSED] DMA allocations, no DMA32 required
[14:36:26] ============== [PASSED] ttm_device_init_pools ==============
[14:36:26] =================== [PASSED] ttm_device ====================
[14:36:26] ================== ttm_pool (8 subtests) ===================
[14:36:26] ================== ttm_pool_alloc_basic  ===================
[14:36:26] [PASSED] One page
[14:36:26] [PASSED] More than one page
[14:36:26] [PASSED] Above the allocation limit
[14:36:26] [PASSED] One page, with coherent DMA mappings enabled
[14:36:26] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[14:36:26] ============== [PASSED] ttm_pool_alloc_basic ===============
[14:36:26] ============== ttm_pool_alloc_basic_dma_addr  ==============
[14:36:26] [PASSED] One page
[14:36:26] [PASSED] More than one page
[14:36:26] [PASSED] Above the allocation limit
[14:36:26] [PASSED] One page, with coherent DMA mappings enabled
[14:36:26] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[14:36:26] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[14:36:26] [PASSED] ttm_pool_alloc_order_caching_match
[14:36:26] [PASSED] ttm_pool_alloc_caching_mismatch
[14:36:26] [PASSED] ttm_pool_alloc_order_mismatch
[14:36:26] [PASSED] ttm_pool_free_dma_alloc
[14:36:26] [PASSED] ttm_pool_free_no_dma_alloc
[14:36:26] [PASSED] ttm_pool_fini_basic
[14:36:26] ==================== [PASSED] ttm_pool =====================
[14:36:26] ================ ttm_resource (8 subtests) =================
[14:36:26] ================= ttm_resource_init_basic  =================
[14:36:26] [PASSED] Init resource in TTM_PL_SYSTEM
[14:36:26] [PASSED] Init resource in TTM_PL_VRAM
[14:36:26] [PASSED] Init resource in a private placement
[14:36:26] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[14:36:26] ============= [PASSED] ttm_resource_init_basic =============
[14:36:26] [PASSED] ttm_resource_init_pinned
[14:36:26] [PASSED] ttm_resource_fini_basic
[14:36:26] [PASSED] ttm_resource_manager_init_basic
[14:36:26] [PASSED] ttm_resource_manager_usage_basic
[14:36:26] [PASSED] ttm_resource_manager_set_used_basic
[14:36:26] [PASSED] ttm_sys_man_alloc_basic
[14:36:26] [PASSED] ttm_sys_man_free_basic
[14:36:26] ================== [PASSED] ttm_resource ===================
[14:36:26] =================== ttm_tt (15 subtests) ===================
[14:36:26] ==================== ttm_tt_init_basic  ====================
[14:36:26] [PASSED] Page-aligned size
[14:36:26] [PASSED] Extra pages requested
[14:36:26] ================ [PASSED] ttm_tt_init_basic ================
[14:36:26] [PASSED] ttm_tt_init_misaligned
[14:36:26] [PASSED] ttm_tt_fini_basic
[14:36:26] [PASSED] ttm_tt_fini_sg
[14:36:26] [PASSED] ttm_tt_fini_shmem
[14:36:26] [PASSED] ttm_tt_create_basic
[14:36:26] [PASSED] ttm_tt_create_invalid_bo_type
[14:36:26] [PASSED] ttm_tt_create_ttm_exists
[14:36:26] [PASSED] ttm_tt_create_failed
[14:36:26] [PASSED] ttm_tt_destroy_basic
[14:36:26] [PASSED] ttm_tt_populate_null_ttm
[14:36:26] [PASSED] ttm_tt_populate_populated_ttm
[14:36:26] [PASSED] ttm_tt_unpopulate_basic
[14:36:26] [PASSED] ttm_tt_unpopulate_empty_ttm
[14:36:26] [PASSED] ttm_tt_swapin_basic
[14:36:26] ===================== [PASSED] ttm_tt ======================
[14:36:26] =================== ttm_bo (14 subtests) ===================
[14:36:26] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[14:36:26] [PASSED] Cannot be interrupted and sleeps
[14:36:26] [PASSED] Cannot be interrupted, locks straight away
[14:36:26] [PASSED] Can be interrupted, sleeps
[14:36:26] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[14:36:26] [PASSED] ttm_bo_reserve_locked_no_sleep
[14:36:26] [PASSED] ttm_bo_reserve_no_wait_ticket
[14:36:26] [PASSED] ttm_bo_reserve_double_resv
[14:36:26] [PASSED] ttm_bo_reserve_interrupted
[14:36:26] [PASSED] ttm_bo_reserve_deadlock
[14:36:26] [PASSED] ttm_bo_unreserve_basic
[14:36:26] [PASSED] ttm_bo_unreserve_pinned
[14:36:26] [PASSED] ttm_bo_unreserve_bulk
[14:36:26] [PASSED] ttm_bo_fini_basic
[14:36:26] [PASSED] ttm_bo_fini_shared_resv
[14:36:26] [PASSED] ttm_bo_pin_basic
[14:36:26] [PASSED] ttm_bo_pin_unpin_resource
[14:36:26] [PASSED] ttm_bo_multiple_pin_one_unpin
[14:36:26] ===================== [PASSED] ttm_bo ======================
[14:36:26] ============== ttm_bo_validate (21 subtests) ===============
[14:36:26] ============== ttm_bo_init_reserved_sys_man  ===============
[14:36:26] [PASSED] Buffer object for userspace
[14:36:26] [PASSED] Kernel buffer object
[14:36:26] [PASSED] Shared buffer object
[14:36:26] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[14:36:26] ============== ttm_bo_init_reserved_mock_man  ==============
[14:36:26] [PASSED] Buffer object for userspace
[14:36:26] [PASSED] Kernel buffer object
[14:36:26] [PASSED] Shared buffer object
[14:36:26] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[14:36:26] [PASSED] ttm_bo_init_reserved_resv
[14:36:26] ================== ttm_bo_validate_basic  ==================
[14:36:26] [PASSED] Buffer object for userspace
[14:36:26] [PASSED] Kernel buffer object
[14:36:26] [PASSED] Shared buffer object
[14:36:26] ============== [PASSED] ttm_bo_validate_basic ==============
[14:36:26] [PASSED] ttm_bo_validate_invalid_placement
[14:36:26] ============= ttm_bo_validate_same_placement  ==============
[14:36:26] [PASSED] System manager
[14:36:26] [PASSED] VRAM manager
[14:36:26] ========= [PASSED] ttm_bo_validate_same_placement ==========
[14:36:26] [PASSED] ttm_bo_validate_failed_alloc
[14:36:26] [PASSED] ttm_bo_validate_pinned
[14:36:26] [PASSED] ttm_bo_validate_busy_placement
[14:36:26] ================ ttm_bo_validate_multihop  =================
[14:36:26] [PASSED] Buffer object for userspace
[14:36:26] [PASSED] Kernel buffer object
[14:36:26] [PASSED] Shared buffer object
[14:36:26] ============ [PASSED] ttm_bo_validate_multihop =============
[14:36:26] ========== ttm_bo_validate_no_placement_signaled  ==========
[14:36:26] [PASSED] Buffer object in system domain, no page vector
[14:36:26] [PASSED] Buffer object in system domain with an existing page vector
[14:36:26] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[14:36:26] ======== ttm_bo_validate_no_placement_not_signaled  ========
[14:36:26] [PASSED] Buffer object for userspace
[14:36:26] [PASSED] Kernel buffer object
[14:36:26] [PASSED] Shared buffer object
[14:36:26] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[14:36:26] [PASSED] ttm_bo_validate_move_fence_signaled
[14:36:26] ========= ttm_bo_validate_move_fence_not_signaled  =========
[14:36:26] [PASSED] Waits for GPU
[14:36:26] [PASSED] Tries to lock straight away
[14:36:26] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[14:36:26] [PASSED] ttm_bo_validate_happy_evict
[14:36:26] [PASSED] ttm_bo_validate_all_pinned_evict
[14:36:26] [PASSED] ttm_bo_validate_allowed_only_evict
[14:36:26] [PASSED] ttm_bo_validate_deleted_evict
[14:36:26] [PASSED] ttm_bo_validate_busy_domain_evict
[14:36:26] [PASSED] ttm_bo_validate_evict_gutting
[14:36:26] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[14:36:26] ================= [PASSED] ttm_bo_validate =================
[14:36:26] ============================================================
[14:36:26] Testing complete. Ran 101 tests: passed: 101
[14:36:26] Elapsed time: 11.045s total, 1.636s configuring, 9.192s building, 0.188s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✗ Xe.CI.BAT: failure for drm/i915/dp: Work around a DSC pixel throughput issue (rev3)

[Patchwork]

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== Series Details ==

Series: drm/i915/dp: Work around a DSC pixel throughput issue (rev3)
URL   : https://patchwork.freedesktop.org/series/154737/
State : failure

== Summary ==

CI Bug Log - changes from xe-3812-c4d19320a0e2f7d8dec97d4a59309349a3a63ec0_BAT -> xe-pw-154737v3_BAT
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-154737v3_BAT absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-154737v3_BAT, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (11 -> 9)
------------------------------

  Missing    (2): bat-adlp-vm bat-ptl-vm 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-154737v3_BAT:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_force_connector_basic@force-edid:
    - bat-bmg-2:          NOTRUN -> [ABORT][1]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v3/bat-bmg-2/igt@kms_force_connector_basic@force-edid.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_force_connector_basic@force-connector-state:
    - {bat-ptl-1}:        [ABORT][2] ([Intel XE#6201]) -> [ABORT][3]
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3812-c4d19320a0e2f7d8dec97d4a59309349a3a63ec0/bat-ptl-1/igt@kms_force_connector_basic@force-connector-state.html
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v3/bat-ptl-1/igt@kms_force_connector_basic@force-connector-state.html

  
Known issues
------------

  Here are the changes found in xe-pw-154737v3_BAT that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@kms_force_connector_basic@force-connector-state:
    - bat-bmg-2:          [ABORT][4] ([Intel XE#6201]) -> [PASS][5]
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3812-c4d19320a0e2f7d8dec97d4a59309349a3a63ec0/bat-bmg-2/igt@kms_force_connector_basic@force-connector-state.html
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v3/bat-bmg-2/igt@kms_force_connector_basic@force-connector-state.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#6201]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6201


Build changes
-------------

  * IGT: IGT_8546 -> IGT_8547
  * Linux: xe-3812-c4d19320a0e2f7d8dec97d4a59309349a3a63ec0 -> xe-pw-154737v3

  IGT_8546: 8546
  IGT_8547: 8547
  xe-3812-c4d19320a0e2f7d8dec97d4a59309349a3a63ec0: c4d19320a0e2f7d8dec97d4a59309349a3a63ec0
  xe-pw-154737v3: 154737v3

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v3/index.html

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Re: ✗ Xe.CI.BAT: failure for drm/i915/dp: Work around a DSC pixel throughput issue (rev3)

[Imre Deak]

On Mon, Sep 22, 2025 at 03:49:05PM +0000, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915/dp: Work around a DSC pixel throughput issue (rev3)
> URL   : https://patchwork.freedesktop.org/series/154737/
> State : failure

Hi CI team,

could you please re-report this result?

The issue is unrelated, it's present in base-line IGT/xe testruns as
well and has now an open ticket too:

https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/6201

I suppose the cibug filter could be simply set to all platforms for this
issue.

Thanks,
Imre

> 
> == Summary ==
> 
> CI Bug Log - changes from xe-3812-c4d19320a0e2f7d8dec97d4a59309349a3a63ec0_BAT -> xe-pw-154737v3_BAT
> ====================================================
> 
> Summary
> -------
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with xe-pw-154737v3_BAT absolutely need to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in xe-pw-154737v3_BAT, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   
> 
> Participating hosts (11 -> 9)
> ------------------------------
> 
>   Missing    (2): bat-adlp-vm bat-ptl-vm 
> 
> Possible new issues
> -------------------
> 
>   Here are the unknown changes that may have been introduced in xe-pw-154737v3_BAT:
> 
> ### IGT changes ###
> 
> #### Possible regressions ####
> 
>   * igt@kms_force_connector_basic@force-edid:
>     - bat-bmg-2:          NOTRUN -> [ABORT][1]
>    [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v3/bat-bmg-2/igt@kms_force_connector_basic@force-edid.html
> 
>   
> #### Suppressed ####
> 
>   The following results come from untrusted machines, tests, or statuses.
>   They do not affect the overall result.
> 
>   * igt@kms_force_connector_basic@force-connector-state:
>     - {bat-ptl-1}:        [ABORT][2] ([Intel XE#6201]) -> [ABORT][3]
>    [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3812-c4d19320a0e2f7d8dec97d4a59309349a3a63ec0/bat-ptl-1/igt@kms_force_connector_basic@force-connector-state.html
>    [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v3/bat-ptl-1/igt@kms_force_connector_basic@force-connector-state.html
> 
>   
> Known issues
> ------------
> 
>   Here are the changes found in xe-pw-154737v3_BAT that come from known issues:
> 
> ### IGT changes ###
> 
> #### Possible fixes ####
> 
>   * igt@kms_force_connector_basic@force-connector-state:
>     - bat-bmg-2:          [ABORT][4] ([Intel XE#6201]) -> [PASS][5]
>    [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3812-c4d19320a0e2f7d8dec97d4a59309349a3a63ec0/bat-bmg-2/igt@kms_force_connector_basic@force-connector-state.html
>    [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v3/bat-bmg-2/igt@kms_force_connector_basic@force-connector-state.html
> 
>   
>   {name}: This element is suppressed. This means it is ignored when computing
>           the status of the difference (SUCCESS, WARNING, or FAILURE).
> 
>   [Intel XE#6201]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6201
> 
> 
> Build changes
> -------------
> 
>   * IGT: IGT_8546 -> IGT_8547
>   * Linux: xe-3812-c4d19320a0e2f7d8dec97d4a59309349a3a63ec0 -> xe-pw-154737v3
> 
>   IGT_8546: 8546
>   IGT_8547: 8547
>   xe-3812-c4d19320a0e2f7d8dec97d4a59309349a3a63ec0: c4d19320a0e2f7d8dec97d4a59309349a3a63ec0
>   xe-pw-154737v3: 154737v3
> 
> == Logs ==
> 
> For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v3/index.html

RE: ✗ Xe.CI.BAT: failure for drm/i915/dp: Work around a DSC pixel throughput issue (rev3)

[Ravali, JupallyX]

Hi,

 https://patchwork.freedesktop.org/series/154737/
Xe.CI.BAT - Addressed failures, Xe cannot be re-reported.

Thanks,
Ravali.

-----Original Message-----
From: I915-ci-infra <i915-ci-infra-bounces@lists.freedesktop.org> On Behalf Of Imre Deak
Sent: 22 September 2025 21:35
To: I915-ci-infra@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org
Subject: Re: ✗ Xe.CI.BAT: failure for drm/i915/dp: Work around a DSC pixel throughput issue (rev3)

On Mon, Sep 22, 2025 at 03:49:05PM +0000, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915/dp: Work around a DSC pixel throughput issue (rev3)
> URL   : https://patchwork.freedesktop.org/series/154737/
> State : failure

Hi CI team,

could you please re-report this result?

The issue is unrelated, it's present in base-line IGT/xe testruns as well and has now an open ticket too:

https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/6201

I suppose the cibug filter could be simply set to all platforms for this issue.

Thanks,
Imre

> 
> == Summary ==
> 
> CI Bug Log - changes from 
> xe-3812-c4d19320a0e2f7d8dec97d4a59309349a3a63ec0_BAT -> 
> xe-pw-154737v3_BAT 
> ====================================================
> 
> Summary
> -------
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with xe-pw-154737v3_BAT absolutely need to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in xe-pw-154737v3_BAT, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   
> 
> Participating hosts (11 -> 9)
> ------------------------------
> 
>   Missing    (2): bat-adlp-vm bat-ptl-vm 
> 
> Possible new issues
> -------------------
> 
>   Here are the unknown changes that may have been introduced in xe-pw-154737v3_BAT:
> 
> ### IGT changes ###
> 
> #### Possible regressions ####
> 
>   * igt@kms_force_connector_basic@force-edid:
>     - bat-bmg-2:          NOTRUN -> [ABORT][1]
>    [1]: 
> https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v3/bat-bmg-2/igt
> @kms_force_connector_basic@force-edid.html
> 
>   
> #### Suppressed ####
> 
>   The following results come from untrusted machines, tests, or statuses.
>   They do not affect the overall result.
> 
>   * igt@kms_force_connector_basic@force-connector-state:
>     - {bat-ptl-1}:        [ABORT][2] ([Intel XE#6201]) -> [ABORT][3]
>    [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3812-c4d19320a0e2f7d8dec97d4a59309349a3a63ec0/bat-ptl-1/igt@kms_force_connector_basic@force-connector-state.html
>    [3]: 
> https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v3/bat-ptl-1/igt
> @kms_force_connector_basic@force-connector-state.html
> 
>   
> Known issues
> ------------
> 
>   Here are the changes found in xe-pw-154737v3_BAT that come from known issues:
> 
> ### IGT changes ###
> 
> #### Possible fixes ####
> 
>   * igt@kms_force_connector_basic@force-connector-state:
>     - bat-bmg-2:          [ABORT][4] ([Intel XE#6201]) -> [PASS][5]
>    [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3812-c4d19320a0e2f7d8dec97d4a59309349a3a63ec0/bat-bmg-2/igt@kms_force_connector_basic@force-connector-state.html
>    [5]: 
> https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v3/bat-bmg-2/igt
> @kms_force_connector_basic@force-connector-state.html
> 
>   
>   {name}: This element is suppressed. This means it is ignored when computing
>           the status of the difference (SUCCESS, WARNING, or FAILURE).
> 
>   [Intel XE#6201]: 
> https://gitlab.freedesktop.org/drm/xe/kernel/issues/6201
> 
> 
> Build changes
> -------------
> 
>   * IGT: IGT_8546 -> IGT_8547
>   * Linux: xe-3812-c4d19320a0e2f7d8dec97d4a59309349a3a63ec0 -> 
> xe-pw-154737v3
> 
>   IGT_8546: 8546
>   IGT_8547: 8547
>   xe-3812-c4d19320a0e2f7d8dec97d4a59309349a3a63ec0: c4d19320a0e2f7d8dec97d4a59309349a3a63ec0
>   xe-pw-154737v3: 154737v3
> 
> == Logs ==
> 
> For more details see: 
> https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v3/index.html

✓ Xe.CI.Full: success for drm/i915/dp: Work around a DSC pixel throughput issue (rev3)

[Patchwork]

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== Series Details ==

Series: drm/i915/dp: Work around a DSC pixel throughput issue (rev3)
URL   : https://patchwork.freedesktop.org/series/154737/
State : success

== Summary ==

CI Bug Log - changes from xe-3812-c4d19320a0e2f7d8dec97d4a59309349a3a63ec0_FULL -> xe-pw-154737v3_FULL
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * IGT: IGT_8546 -> IGT_8547
  * Linux: xe-3812-c4d19320a0e2f7d8dec97d4a59309349a3a63ec0 -> xe-pw-154737v3

  IGT_8546: 8546
  IGT_8547: 8547
  xe-3812-c4d19320a0e2f7d8dec97d4a59309349a3a63ec0: c4d19320a0e2f7d8dec97d4a59309349a3a63ec0
  xe-pw-154737v3: 154737v3

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v3/index.html

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