* [PATCH v4 0/6] drm/i915/dp: Work around a DSC pixel throughput issue
@ 2025-09-26 21:12 Imre Deak
2025-09-26 21:12 ` [PATCH v4 1/6] drm/dp: Add quirk for Synaptics DSC throughput link-bpp limit Imre Deak
` (14 more replies)
0 siblings, 15 replies; 25+ messages in thread
From: Imre Deak @ 2025-09-26 21:12 UTC (permalink / raw)
To: intel-gfx, intel-xe
Cc: Vidya Srinivas, Swati Sharma, Ville Syrjälä, dri-devel
This is v4 of [1], with the following changes:
- Fix drm_dp_dsc_sink_max_slice_throughput()'s name.
- Use the clearer peak_pixel_rate vs. pixel_clock as the above
function's parameter.
- Clarify the meaning of peak_pixel_rate for MST tiled displays.
- Fix return value from dsc_throughput_quirk_max_bpp_x16(), in case it's
not required to limit the BPP.
[1] https://lore.kernel.org/all/20250924152332.359768-1-imre.deak@intel.com
Reported-by: Vidya Srinivas <vidya.srinivas@intel.com>
Reported-by: Swati Sharma <swati2.sharma@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: dri-devel@lists.freedesktop.org
Imre Deak (6):
drm/dp: Add quirk for Synaptics DSC throughput link-bpp limit
drm/dp: Add helpers to query the branch DSC max throughput/line-width
drm/i915/dp: Calculate DSC slice count based on per-slice peak
throughput
drm/i915/dp: Pass DPCD device descriptor to
intel_dp_get_dsc_sink_cap()
drm/i915/dp: Verify branch devices' overall pixel throughput/line
width
drm/i915/dp: Handle Synaptics DSC throughput link-bpp quirk
drivers/gpu/drm/display/drm_dp_helper.c | 146 ++++++++++++++++++
.../drm/i915/display/intel_display_types.h | 9 ++
drivers/gpu/drm/i915/display/intel_dp.c | 146 ++++++++++++++++--
drivers/gpu/drm/i915/display/intel_dp.h | 5 +-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 9 +-
include/drm/display/drm_dp.h | 1 +
include/drm/display/drm_dp_helper.h | 14 ++
7 files changed, 316 insertions(+), 14 deletions(-)
--
2.49.1
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v4 1/6] drm/dp: Add quirk for Synaptics DSC throughput link-bpp limit
2025-09-26 21:12 [PATCH v4 0/6] drm/i915/dp: Work around a DSC pixel throughput issue Imre Deak
@ 2025-09-26 21:12 ` Imre Deak
2025-09-26 21:12 ` [PATCH v4 2/6] drm/dp: Add helpers to query the branch DSC max throughput/line-width Imre Deak
` (13 subsequent siblings)
14 siblings, 0 replies; 25+ messages in thread
From: Imre Deak @ 2025-09-26 21:12 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: dri-devel, Vidya Srinivas, Swati Sharma
Some Synaptics MST branch devices have a problem decompressing a stream
with a compressed link-bpp higher than 12, if the pixel clock is higher
than ~50 % of the maximum throughput capability reported by the branch
device. The screen remains blank, or for some - mostly black content -
gets enabled, but may stil have jitter artifacts.
At least the following docking stations are affected, based on testing
both with any Intel devices or the UCD-500 reference device as a source:
- DELL WD19DCS, DELL WD19TB3, DELL WD22TB4
- ThinkPad 40AN
- HP G2
At least the following docking stations are free from this problem,
based on tests with a source/sink/mode etc. configuration matching the
test cases used above:
- DELL Dual Charge HD22Q, DELL WD25TB5
- ThinkPad 40B0
- Anker 565
All the affected devices have an older version of the Synaptics MST
branch device (Panamera), whereas all the non-affected docking stations
have a newer branch device (at least Synaptics Panamera with a higher HW
revision number and Synaptics Cayenne models). Add the required quirk
entries accordingly. The quirk will be handled by the i915/xe drivers in
a follow-up change.
The latest firmware version of the Synaptics branch device for all the
affected devices tested above is 5.7 (as reported at DPCD address
0x50a/0x50b). For the DELL devices this corresponds to the latest
01.00.14.01.A03 firmware package version of the docking station.
v2:
- Document the DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT enum.
- Describe the quirk in more detail in the dpcd_quirk_list.
v3:
- s/Panarema/Panamera in the commit log.
Cc: dri-devel@lists.freedesktop.org
Reported-by: Vidya Srinivas <vidya.srinivas@intel.com>
Reported-by: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/display/drm_dp_helper.c | 4 ++++
include/drm/display/drm_dp_helper.h | 9 +++++++++
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
index 5426db21e53f7..1c74fe9459ad9 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -2551,6 +2551,10 @@ static const struct dpcd_quirk dpcd_quirk_list[] = {
{ OUI(0x00, 0x0C, 0xE7), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC) },
/* Apple MacBookPro 2017 15 inch eDP Retina panel reports too low DP_MAX_LINK_RATE */
{ OUI(0x00, 0x10, 0xfa), DEVICE_ID(101, 68, 21, 101, 98, 97), false, BIT(DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS) },
+ /* Synaptics Panamera supports only a compressed bpp of 12 above 50% of its max DSC pixel throughput */
+ { OUI(0x90, 0xCC, 0x24), DEVICE_ID('S', 'Y', 'N', 'A', 0x53, 0x22), true, BIT(DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT) },
+ { OUI(0x90, 0xCC, 0x24), DEVICE_ID('S', 'Y', 'N', 'A', 0x53, 0x31), true, BIT(DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT) },
+ { OUI(0x90, 0xCC, 0x24), DEVICE_ID('S', 'Y', 'N', 'A', 0x53, 0x33), true, BIT(DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT) },
};
#undef OUI
diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
index 52ce280970151..e438c44409952 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -828,6 +828,15 @@ enum drm_dp_quirk {
* requires enabling DSC.
*/
DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC,
+ /**
+ * @DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT:
+ *
+ * The device doesn't support DSC decompression at the maximum DSC
+ * pixel throughput and compressed bpp it indicates via its DPCD DSC
+ * capabilities. The compressed bpp must be limited above a device
+ * specific DSC pixel throughput.
+ */
+ DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT,
};
/**
--
2.49.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v4 2/6] drm/dp: Add helpers to query the branch DSC max throughput/line-width
2025-09-26 21:12 [PATCH v4 0/6] drm/i915/dp: Work around a DSC pixel throughput issue Imre Deak
2025-09-26 21:12 ` [PATCH v4 1/6] drm/dp: Add quirk for Synaptics DSC throughput link-bpp limit Imre Deak
@ 2025-09-26 21:12 ` Imre Deak
2025-09-29 6:36 ` [PATCH v5 " Imre Deak
2025-09-26 21:12 ` [PATCH v4 3/6] drm/i915/dp: Calculate DSC slice count based on per-slice peak throughput Imre Deak
` (12 subsequent siblings)
14 siblings, 1 reply; 25+ messages in thread
From: Imre Deak @ 2025-09-26 21:12 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: dri-devel, Ville Syrjälä
Add helpers to query the DP DSC sink device's per-slice throughput as
well as a DSC branch device's overall throughput and line-width
capabilities.
v2 (Ville):
- Rename pixel_clock to peak_pixel_rate, document what the value means
in case of MST tiled displays.
- Fix name of drm_dp_dsc_branch_max_slice_throughput() to
drm_dp_dsc_sink_max_slice_throughput().
Cc: dri-devel@lists.freedesktop.org
Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/display/drm_dp_helper.c | 142 ++++++++++++++++++++++++
include/drm/display/drm_dp.h | 1 +
include/drm/display/drm_dp_helper.h | 5 +
3 files changed, 148 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
index 1c74fe9459ad9..e0f96b5ba4518 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -2844,6 +2844,148 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
}
EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
+/*
+ * See DP Standard v2.1a 2.8.4 Minimum Slices/Display, Table 2-159 and
+ * Appendix L.1 Derivation of Slice Count Requirements.
+ */
+static int dsc_sink_min_slice_throughput(int peak_pixel_rate)
+{
+ if (peak_pixel_rate >= 4800000)
+ return 600000;
+ else if (peak_pixel_rate >= 2700000)
+ return 400000;
+ else
+ return 340000;
+}
+
+/**
+ * drm_dp_dsc_sink_max_slice_throughput() - Get a DSC sink's maximum pixel throughput per slice
+ * @dsc_dpcd: DSC sink's capabilities from DPCD
+ * @peak_pixel_rate: Cumulative peak pixel rate in kHz
+ * @is_rgb_yuv444: The mode is either RGB or YUV444
+ *
+ * Return the DSC sink device's maximum pixel throughput per slice, based on
+ * the device's @dsc_dpcd capabilities, the @peak_pixel_rate of the transferred
+ * stream(s) and whether the output format @is_rgb_yuv444 or yuv422/yuv420.
+ *
+ * Note that @peak_pixel_rate is the total pixel rate transferred to the same
+ * DSC/display sink. For instance to calculate a tile's slice count of an MST
+ * multi-tiled display sink (not considering here the required
+ * rounding/alignment of slice count)::
+ *
+ * @peak_pixel_rate = tile_pixel_rate * tile_count
+ * total_slice_count = @peak_pixel_rate / drm_dp_dsc_sink_max_slice_throughput(@peak_pixel_rate)
+ * tile_slice_count = total_slice_count / tile_count
+ *
+ * Returns:
+ * The maximum pixel throughput per slice supported by the DSC sink device
+ * in kPixels/sec.
+ */
+int drm_dp_dsc_sink_max_slice_throughput(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
+ int peak_pixel_rate, bool is_rgb_yuv444)
+{
+ int throughput;
+
+ throughput = dsc_dpcd[DP_DSC_PEAK_THROUGHPUT - DP_DSC_SUPPORT];
+
+ if (is_rgb_yuv444)
+ throughput = (throughput & DP_DSC_THROUGHPUT_MODE_0_MASK) >>
+ DP_DSC_THROUGHPUT_MODE_0_SHIFT;
+ else
+ throughput = (throughput & DP_DSC_THROUGHPUT_MODE_1_MASK) >>
+ DP_DSC_THROUGHPUT_MODE_1_SHIFT;
+
+ switch (throughput) {
+ case 0:
+ return dsc_sink_min_slice_throughput(peak_pixel_rate);
+ case 1:
+ return 340000;
+ case 2 ... 14:
+ return 400000 + 50000 * (throughput - 2);
+ case 15:
+ return 170000;
+ default:
+ WARN(1, "Missing case %d\n", throughput);
+ return 340000;
+ }
+}
+EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_throughput);
+
+static u8 dsc_branch_dpcd_cap(const u8 dpcd[DP_DSC_BRANCH_CAP_SIZE], int reg)
+{
+ return dpcd[reg - DP_DSC_BRANCH_OVERALL_THROUGHPUT_0];
+}
+
+/**
+ * drm_dp_dsc_branch_max_overall_throughput() - Branch device's max overall DSC pixel throughput
+ * @dsc_branch_dpcd: DSC branch capabilities from DPCD
+ * @is_rgb_yuv444: The mode is either RGB or YUV444
+ *
+ * Return the branch device's maximum overall DSC pixel throughput, based on
+ * the device's DPCD DSC branch capabilities, and whether the output
+ * format @is_rgb_yuv444 or yuv422/yuv420.
+ *
+ * Returns:
+ * - 0: The maximum overall throughput capability is not indicated by
+ * the device separately and it must be determined from the per-slice
+ * max throughput (see @drm_dp_dsc_branch_slice_max_throughput())
+ * and the maximum slice count supported by the device.
+ * - > 0: The maximum overall DSC pixel throughput supported by the branch
+ * device in kPixels/sec.
+ */
+int drm_dp_dsc_branch_max_overall_throughput(const u8 dsc_branch_dpcd[DP_DSC_BRANCH_CAP_SIZE],
+ bool is_rgb_yuv444)
+{
+ int throughput;
+
+ if (is_rgb_yuv444)
+ throughput = dsc_branch_dpcd_cap(dsc_branch_dpcd,
+ DP_DSC_BRANCH_OVERALL_THROUGHPUT_0);
+ else
+ throughput = dsc_branch_dpcd_cap(dsc_branch_dpcd,
+ DP_DSC_BRANCH_OVERALL_THROUGHPUT_1);
+
+ switch (throughput) {
+ case 0:
+ return 0;
+ case 1:
+ return 680000;
+ default:
+ return 600000 + 50000 * throughput;
+ }
+}
+EXPORT_SYMBOL(drm_dp_dsc_branch_max_overall_throughput);
+
+/**
+ * drm_dp_dsc_branch_max_line_width() - Branch device's max DSC line width
+ * @dsc_branch_dpcd: DSC branch capabilities from DPCD
+ *
+ * Return the branch device's maximum overall DSC line width, based on
+ * the device's @dsc_branch_dpcd capabilities.
+ *
+ * Returns:
+ * - 0: The maximum line width is not indicated by the device
+ * separately and it must be determined from the maximum
+ * slice count and slice-width supported by the device.
+ * - %-EINVAL: The device indicates an invalid maximum line width
+ * (< 2560 pixels).
+ * - >= 2560: The maximum line width in pixels.
+ */
+int drm_dp_dsc_branch_max_line_width(const u8 dsc_branch_dpcd[DP_DSC_BRANCH_CAP_SIZE])
+{
+ int line_width = dsc_branch_dpcd_cap(dsc_branch_dpcd, DP_DSC_BRANCH_MAX_LINE_WIDTH);
+
+ switch (line_width) {
+ case 0:
+ return 0;
+ case 1 ... 7:
+ return -EINVAL;
+ default:
+ return line_width * 320;
+ }
+}
+EXPORT_SYMBOL(drm_dp_dsc_branch_max_line_width);
+
static int drm_dp_read_lttpr_regs(struct drm_dp_aux *aux,
const u8 dpcd[DP_RECEIVER_CAP_SIZE], int address,
u8 *buf, int buf_size)
diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index cf318e3ddb5c5..43978ddd15056 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -1686,6 +1686,7 @@ enum drm_dp_phy {
#define DP_BRANCH_OUI_HEADER_SIZE 0xc
#define DP_RECEIVER_CAP_SIZE 0xf
#define DP_DSC_RECEIVER_CAP_SIZE 0x10 /* DSC Capabilities 0x60 through 0x6F */
+#define DP_DSC_BRANCH_CAP_SIZE 3
#define EDP_PSR_RECEIVER_CAP_SIZE 2
#define EDP_DISPLAY_CTL_CAP_SIZE 5
#define DP_LTTPR_COMMON_CAP_SIZE 8
diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
index e438c44409952..ac03bfbb0fb52 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -211,6 +211,11 @@ u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE],
u8 dsc_bpc[3]);
+int drm_dp_dsc_sink_max_slice_throughput(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
+ int mode_clock, bool is_rgb_yuv444);
+int drm_dp_dsc_branch_max_overall_throughput(const u8 dsc_branch_dpcd[DP_DSC_BRANCH_CAP_SIZE],
+ bool is_rgb_yuv444);
+int drm_dp_dsc_branch_max_line_width(const u8 dsc_branch_dpcd[DP_DSC_BRANCH_CAP_SIZE]);
static inline bool
drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
--
2.49.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v4 3/6] drm/i915/dp: Calculate DSC slice count based on per-slice peak throughput
2025-09-26 21:12 [PATCH v4 0/6] drm/i915/dp: Work around a DSC pixel throughput issue Imre Deak
2025-09-26 21:12 ` [PATCH v4 1/6] drm/dp: Add quirk for Synaptics DSC throughput link-bpp limit Imre Deak
2025-09-26 21:12 ` [PATCH v4 2/6] drm/dp: Add helpers to query the branch DSC max throughput/line-width Imre Deak
@ 2025-09-26 21:12 ` Imre Deak
2025-09-26 21:12 ` [PATCH v4 4/6] drm/i915/dp: Pass DPCD device descriptor to intel_dp_get_dsc_sink_cap() Imre Deak
` (11 subsequent siblings)
14 siblings, 0 replies; 25+ messages in thread
From: Imre Deak @ 2025-09-26 21:12 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: Ville Syrjälä
Use the DSC sink device's actual per-slice peak throughput to calculate
the minimum number of required DSC slices, falling back to the
hard-coded throughput values (as suggested by the DP Standard) if the
device's reported throughput value is 0.
For now use the minimum of the two throughput values, which is ok,
potentially resulting in a higher than required minimum slice count.
This doesn't change the current way of using the same minimum throughput
value regardless of the RGB/YUV output format used.
While at it add a TODO comment for MST tiled displays to calculate the
slice count for these based on the total pixel rate of all the tiles.
v2: Use drm helpers to query the throughput caps. (Ville)
v3: Add TODO comment to account for MST tiled displays. (Ville)
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 33 ++++++++++++++++---------
1 file changed, 22 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 2eab591a8ef56..491a804c1f6a0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -96,11 +96,6 @@
#include "intel_vdsc.h"
#include "intel_vrr.h"
-/* DP DSC throughput values used for slice count calculations KPixels/s */
-#define DP_DSC_PEAK_PIXEL_RATE 2720000
-#define DP_DSC_MAX_ENC_THROUGHPUT_0 340000
-#define DP_DSC_MAX_ENC_THROUGHPUT_1 400000
-
/* Max DSC line buffer depth supported by HW. */
#define INTEL_DP_DSC_MAX_LINE_BUF_DEPTH 13
@@ -1018,13 +1013,29 @@ u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
struct intel_display *display = to_intel_display(connector);
u8 min_slice_count, i;
int max_slice_width;
+ int tp_rgb_yuv444;
+ int tp_yuv422_420;
- if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
- min_slice_count = DIV_ROUND_UP(mode_clock,
- DP_DSC_MAX_ENC_THROUGHPUT_0);
- else
- min_slice_count = DIV_ROUND_UP(mode_clock,
- DP_DSC_MAX_ENC_THROUGHPUT_1);
+ /*
+ * TODO: Pass the total pixel rate of all the streams transferred to
+ * an MST tiled display, calculate the total slice count for all tiles
+ * from this and the per-tile slice count from the total slice count.
+ */
+ tp_rgb_yuv444 = drm_dp_dsc_sink_max_slice_throughput(connector->dp.dsc_dpcd,
+ mode_clock, true);
+ tp_yuv422_420 = drm_dp_dsc_sink_max_slice_throughput(connector->dp.dsc_dpcd,
+ mode_clock, false);
+
+ /*
+ * TODO: Use the throughput value specific to the actual RGB/YUV
+ * format of the output.
+ * For now use the smaller of these, which is ok, potentially
+ * resulting in a higher than required minimum slice count.
+ * The RGB/YUV444 throughput value should be always either equal
+ * or smaller than the YUV422/420 value, but let's not depend on
+ * this assumption.
+ */
+ min_slice_count = DIV_ROUND_UP(mode_clock, min(tp_rgb_yuv444, tp_yuv422_420));
/*
* Due to some DSC engine BW limitations, we need to enable second
--
2.49.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v4 4/6] drm/i915/dp: Pass DPCD device descriptor to intel_dp_get_dsc_sink_cap()
2025-09-26 21:12 [PATCH v4 0/6] drm/i915/dp: Work around a DSC pixel throughput issue Imre Deak
` (2 preceding siblings ...)
2025-09-26 21:12 ` [PATCH v4 3/6] drm/i915/dp: Calculate DSC slice count based on per-slice peak throughput Imre Deak
@ 2025-09-26 21:12 ` Imre Deak
2025-09-26 21:12 ` [PATCH v4 5/6] drm/i915/dp: Verify branch devices' overall pixel throughput/line width Imre Deak
` (10 subsequent siblings)
14 siblings, 0 replies; 25+ messages in thread
From: Imre Deak @ 2025-09-26 21:12 UTC (permalink / raw)
To: intel-gfx, intel-xe
Pass the DPCD sink/branch device descriptor along with the
is_branch/sink flag to intel_dp_get_dsc_sink_cap(). These will be used
by a follow up change to read out the branch device's DSC overall
throughput/line width capabilities and to detect a throughput/link-bpp
quirk.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 5 ++++-
drivers/gpu/drm/i915/display/intel_dp.h | 5 ++++-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 9 ++++++++-
3 files changed, 16 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 491a804c1f6a0..2dcc20bcfa0ba 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4180,7 +4180,9 @@ static void intel_dp_read_dsc_dpcd(struct drm_dp_aux *aux,
dsc_dpcd);
}
-void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector)
+void intel_dp_get_dsc_sink_cap(u8 dpcd_rev,
+ const struct drm_dp_desc *desc, bool is_branch,
+ struct intel_connector *connector)
{
struct intel_display *display = to_intel_display(connector);
@@ -4231,6 +4233,7 @@ intel_dp_detect_dsc_caps(struct intel_dp *intel_dp, struct intel_connector *conn
connector);
else
intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV],
+ &intel_dp->desc, drm_dp_is_branch(intel_dp->dpcd),
connector);
}
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index f90cfd1dbbd05..b379443e0211e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -12,6 +12,7 @@ enum intel_output_format;
enum pipe;
enum port;
struct drm_connector_state;
+struct drm_dp_desc;
struct drm_dp_vsc_sdp;
struct drm_encoder;
struct drm_modeset_acquire_ctx;
@@ -199,7 +200,9 @@ bool intel_dp_compute_config_limits(struct intel_dp *intel_dp,
bool dsc,
struct link_config_limits *limits);
-void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector);
+void intel_dp_get_dsc_sink_cap(u8 dpcd_rev,
+ const struct drm_dp_desc *desc, bool is_branch,
+ struct intel_connector *connector);
bool intel_dp_has_gamut_metadata_dip(struct intel_encoder *encoder);
bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 352f7ef29c281..f2266b2653046 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -1658,6 +1658,7 @@ intel_dp_mst_read_decompression_port_dsc_caps(struct intel_dp *intel_dp,
struct intel_connector *connector)
{
u8 dpcd_caps[DP_RECEIVER_CAP_SIZE];
+ struct drm_dp_desc desc;
if (!connector->dp.dsc_decompression_aux)
return;
@@ -1665,7 +1666,13 @@ intel_dp_mst_read_decompression_port_dsc_caps(struct intel_dp *intel_dp,
if (drm_dp_read_dpcd_caps(connector->dp.dsc_decompression_aux, dpcd_caps) < 0)
return;
- intel_dp_get_dsc_sink_cap(dpcd_caps[DP_DPCD_REV], connector);
+ if (drm_dp_read_desc(connector->dp.dsc_decompression_aux, &desc,
+ drm_dp_is_branch(dpcd_caps)) < 0)
+ return;
+
+ intel_dp_get_dsc_sink_cap(dpcd_caps[DP_DPCD_REV],
+ &desc, drm_dp_is_branch(dpcd_caps),
+ connector);
}
static bool detect_dsc_hblank_expansion_quirk(const struct intel_connector *connector)
--
2.49.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v4 5/6] drm/i915/dp: Verify branch devices' overall pixel throughput/line width
2025-09-26 21:12 [PATCH v4 0/6] drm/i915/dp: Work around a DSC pixel throughput issue Imre Deak
` (3 preceding siblings ...)
2025-09-26 21:12 ` [PATCH v4 4/6] drm/i915/dp: Pass DPCD device descriptor to intel_dp_get_dsc_sink_cap() Imre Deak
@ 2025-09-26 21:12 ` Imre Deak
2025-09-26 21:12 ` [PATCH v4 6/6] drm/i915/dp: Handle Synaptics DSC throughput link-bpp quirk Imre Deak
` (9 subsequent siblings)
14 siblings, 0 replies; 25+ messages in thread
From: Imre Deak @ 2025-09-26 21:12 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: Ville Syrjälä
Read out the branch devices' maximum overall DSC pixel throughput and
line width and verify the mode's corresponding pixel clock and hactive
period against these.
v2: Use drm helpers to query the throughput/line-width caps. (Ville)
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
.../drm/i915/display/intel_display_types.h | 8 +++
drivers/gpu/drm/i915/display/intel_dp.c | 51 +++++++++++++++++++
2 files changed, 59 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 029c47743f8b1..99d2c31236928 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -552,6 +552,14 @@ struct intel_connector {
u8 dsc_hblank_expansion_quirk:1;
u8 dsc_decompression_enabled:1;
+
+ struct {
+ struct {
+ int rgb_yuv444;
+ int yuv422_420;
+ } overall_throughput;
+ int max_line_width;
+ } dsc_branch_caps;
} dp;
struct {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 2dcc20bcfa0ba..9de9356302f97 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1016,6 +1016,20 @@ u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
int tp_rgb_yuv444;
int tp_yuv422_420;
+ /*
+ * TODO: Use the throughput value specific to the actual RGB/YUV
+ * format of the output.
+ * The RGB/YUV444 throughput value should be always either equal
+ * or smaller than the YUV422/420 value, but let's not depend on
+ * this assumption.
+ */
+ if (mode_clock > max(connector->dp.dsc_branch_caps.overall_throughput.rgb_yuv444,
+ connector->dp.dsc_branch_caps.overall_throughput.yuv422_420))
+ return 0;
+
+ if (mode_hdisplay > connector->dp.dsc_branch_caps.max_line_width)
+ return 0;
+
/*
* TODO: Pass the total pixel rate of all the streams transferred to
* an MST tiled display, calculate the total slice count for all tiles
@@ -4180,6 +4194,33 @@ static void intel_dp_read_dsc_dpcd(struct drm_dp_aux *aux,
dsc_dpcd);
}
+static void init_dsc_overall_throughput_limits(struct intel_connector *connector, bool is_branch)
+{
+ u8 branch_caps[DP_DSC_BRANCH_CAP_SIZE];
+ int line_width;
+
+ connector->dp.dsc_branch_caps.overall_throughput.rgb_yuv444 = INT_MAX;
+ connector->dp.dsc_branch_caps.overall_throughput.yuv422_420 = INT_MAX;
+ connector->dp.dsc_branch_caps.max_line_width = INT_MAX;
+
+ if (!is_branch)
+ return;
+
+ if (drm_dp_dpcd_read_data(connector->dp.dsc_decompression_aux,
+ DP_DSC_BRANCH_OVERALL_THROUGHPUT_0, branch_caps,
+ sizeof(branch_caps)) != 0)
+ return;
+
+ connector->dp.dsc_branch_caps.overall_throughput.rgb_yuv444 =
+ drm_dp_dsc_branch_max_overall_throughput(branch_caps, true) ? : INT_MAX;
+
+ connector->dp.dsc_branch_caps.overall_throughput.yuv422_420 =
+ drm_dp_dsc_branch_max_overall_throughput(branch_caps, false) ? : INT_MAX;
+
+ line_width = drm_dp_dsc_branch_max_line_width(branch_caps);
+ connector->dp.dsc_branch_caps.max_line_width = line_width > 0 ? line_width : INT_MAX;
+}
+
void intel_dp_get_dsc_sink_cap(u8 dpcd_rev,
const struct drm_dp_desc *desc, bool is_branch,
struct intel_connector *connector)
@@ -4195,6 +4236,8 @@ void intel_dp_get_dsc_sink_cap(u8 dpcd_rev,
/* Clear fec_capable to avoid using stale values */
connector->dp.fec_capability = 0;
+ memset(&connector->dp.dsc_branch_caps, 0, sizeof(connector->dp.dsc_branch_caps));
+
if (dpcd_rev < DP_DPCD_REV_14)
return;
@@ -4209,6 +4252,11 @@ void intel_dp_get_dsc_sink_cap(u8 dpcd_rev,
drm_dbg_kms(display->drm, "FEC CAPABILITY: %x\n",
connector->dp.fec_capability);
+
+ if (!(connector->dp.dsc_dpcd[0] & DP_DSC_DECOMPRESSION_IS_SUPPORTED))
+ return;
+
+ init_dsc_overall_throughput_limits(connector, is_branch);
}
static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *connector)
@@ -4217,6 +4265,9 @@ static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *
return;
intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, connector->dp.dsc_dpcd);
+
+ if (connector->dp.dsc_dpcd[0] & DP_DSC_DECOMPRESSION_IS_SUPPORTED)
+ init_dsc_overall_throughput_limits(connector, false);
}
static void
--
2.49.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v4 6/6] drm/i915/dp: Handle Synaptics DSC throughput link-bpp quirk
2025-09-26 21:12 [PATCH v4 0/6] drm/i915/dp: Work around a DSC pixel throughput issue Imre Deak
` (4 preceding siblings ...)
2025-09-26 21:12 ` [PATCH v4 5/6] drm/i915/dp: Verify branch devices' overall pixel throughput/line width Imre Deak
@ 2025-09-26 21:12 ` Imre Deak
2025-09-26 21:56 ` ✗ CI.checkpatch: warning for drm/i915/dp: Work around a DSC pixel throughput issue (rev5) Patchwork
` (8 subsequent siblings)
14 siblings, 0 replies; 25+ messages in thread
From: Imre Deak @ 2025-09-26 21:12 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: Ville Syrjälä, Vidya Srinivas, Swati Sharma
Handle the DSC pixel throughput quirk, limiting the compressed link-bpp
value for Synaptics Panamera branch devices, working around a
blank/unstable output issue observed on docking stations containing
these branch devices, when using a mode with a high pixel clock and a
high compressed link-bpp value.
For now use the same mode clock limit for RGB/YUV444 and YUV422/420
output modes. This may result in limiting the link-bpp value for a
YUV422/420 output mode already at a lower than required mode clock.
v2: Apply the quirk only when DSC is enabled.
v3 (Ville):
- Move adjustment of link-bpp within the already existing is_dsc
if branch.
- Add TODO comment to move the HW revision check as well to the
DRM core quirk table.
v4:
- Fix incorrect fxp_q4_from_int(INT_MAX) vs. INT_MAX return value
from dsc_throughput_quirk_max_bpp_x16().
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reported-by: Vidya Srinivas <vidya.srinivas@intel.com>
Reported-by: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
.../drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 57 +++++++++++++++++++
2 files changed, 58 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 99d2c31236928..ca5a87772e93a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -551,6 +551,7 @@ struct intel_connector {
u8 fec_capability;
u8 dsc_hblank_expansion_quirk:1;
+ u8 dsc_throughput_quirk:1;
u8 dsc_decompression_enabled:1;
struct {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 9de9356302f97..8a2fc1fcb5d04 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2485,6 +2485,40 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
return 0;
}
+static int
+dsc_throughput_quirk_max_bpp_x16(const struct intel_connector *connector,
+ const struct intel_crtc_state *crtc_state)
+{
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->hw.adjusted_mode;
+
+ if (!connector->dp.dsc_throughput_quirk)
+ return INT_MAX;
+
+ /*
+ * Synaptics Panamera branch devices have a problem decompressing a
+ * stream with a compressed link-bpp higher than 12, if the pixel
+ * clock is higher than ~50 % of the maximum overall throughput
+ * reported by the branch device. Work around this by limiting the
+ * maximum link bpp for such pixel clocks.
+ *
+ * TODO: Use the throughput value specific to the actual RGB/YUV
+ * format of the output, after determining the pixel clock limit for
+ * YUV modes. For now use the smaller of the throughput values, which
+ * may result in limiting the link-bpp value already at a lower than
+ * required mode clock in case of native YUV422/420 output formats.
+ * The RGB/YUV444 throughput value should be always either equal or
+ * smaller than the YUV422/420 value, but let's not depend on this
+ * assumption.
+ */
+ if (adjusted_mode->crtc_clock <
+ min(connector->dp.dsc_branch_caps.overall_throughput.rgb_yuv444,
+ connector->dp.dsc_branch_caps.overall_throughput.yuv422_420) / 2)
+ return INT_MAX;
+
+ return fxp_q4_from_int(12);
+}
+
/*
* Calculate the output link min, max bpp values in limits based on the pipe bpp
* range, crtc_state and dsc mode. Return true on success.
@@ -2516,6 +2550,7 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
} else {
int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
+ int throughput_max_bpp_x16;
dsc_src_min_bpp = intel_dp_dsc_min_src_compressed_bpp();
dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(crtc_state);
@@ -2530,6 +2565,19 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
max_link_bpp_x16 = min(max_link_bpp_x16, fxp_q4_from_int(dsc_max_bpp));
+
+ throughput_max_bpp_x16 = dsc_throughput_quirk_max_bpp_x16(connector, crtc_state);
+ throughput_max_bpp_x16 = clamp(throughput_max_bpp_x16,
+ limits->link.min_bpp_x16, max_link_bpp_x16);
+ if (throughput_max_bpp_x16 < max_link_bpp_x16) {
+ max_link_bpp_x16 = throughput_max_bpp_x16;
+
+ drm_dbg_kms(display->drm,
+ "[CRTC:%d:%s][CONNECTOR:%d:%s] Decreasing link max bpp to " FXP_Q4_FMT " due to DSC throughput quirk\n",
+ crtc->base.base.id, crtc->base.name,
+ connector->base.base.id, connector->base.name,
+ FXP_Q4_ARGS(max_link_bpp_x16));
+ }
}
limits->link.max_bpp_x16 = max_link_bpp_x16;
@@ -4237,6 +4285,7 @@ void intel_dp_get_dsc_sink_cap(u8 dpcd_rev,
connector->dp.fec_capability = 0;
memset(&connector->dp.dsc_branch_caps, 0, sizeof(connector->dp.dsc_branch_caps));
+ connector->dp.dsc_throughput_quirk = false;
if (dpcd_rev < DP_DPCD_REV_14)
return;
@@ -4257,6 +4306,14 @@ void intel_dp_get_dsc_sink_cap(u8 dpcd_rev,
return;
init_dsc_overall_throughput_limits(connector, is_branch);
+
+ /*
+ * TODO: Move the HW rev check as well to the DRM core quirk table if
+ * that's required after clarifying the list of affected devices.
+ */
+ if (drm_dp_has_quirk(desc, DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT) &&
+ desc->ident.hw_rev == 0x10)
+ connector->dp.dsc_throughput_quirk = true;
}
static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *connector)
--
2.49.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* ✗ CI.checkpatch: warning for drm/i915/dp: Work around a DSC pixel throughput issue (rev5)
2025-09-26 21:12 [PATCH v4 0/6] drm/i915/dp: Work around a DSC pixel throughput issue Imre Deak
` (5 preceding siblings ...)
2025-09-26 21:12 ` [PATCH v4 6/6] drm/i915/dp: Handle Synaptics DSC throughput link-bpp quirk Imre Deak
@ 2025-09-26 21:56 ` Patchwork
2025-09-26 21:57 ` ✓ CI.KUnit: success " Patchwork
` (7 subsequent siblings)
14 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2025-09-26 21:56 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-xe
== Series Details ==
Series: drm/i915/dp: Work around a DSC pixel throughput issue (rev5)
URL : https://patchwork.freedesktop.org/series/154737/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
fbd08a78c3a3bb17964db2a326514c69c1dca660
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit c60fd37d3c48faa4617de9f2bd2b253afebfaf71
Author: Imre Deak <imre.deak@intel.com>
Date: Sat Sep 27 00:12:36 2025 +0300
drm/i915/dp: Handle Synaptics DSC throughput link-bpp quirk
Handle the DSC pixel throughput quirk, limiting the compressed link-bpp
value for Synaptics Panamera branch devices, working around a
blank/unstable output issue observed on docking stations containing
these branch devices, when using a mode with a high pixel clock and a
high compressed link-bpp value.
For now use the same mode clock limit for RGB/YUV444 and YUV422/420
output modes. This may result in limiting the link-bpp value for a
YUV422/420 output mode already at a lower than required mode clock.
v2: Apply the quirk only when DSC is enabled.
v3 (Ville):
- Move adjustment of link-bpp within the already existing is_dsc
if branch.
- Add TODO comment to move the HW revision check as well to the
DRM core quirk table.
v4:
- Fix incorrect fxp_q4_from_int(INT_MAX) vs. INT_MAX return value
from dsc_throughput_quirk_max_bpp_x16().
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reported-by: Vidya Srinivas <vidya.srinivas@intel.com>
Reported-by: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
+ /mt/dim checkpatch 3008c5c8e2fade05918e6d8c456572c91f30d412 drm-intel
7adc9ce5d564 drm/dp: Add quirk for Synaptics DSC throughput link-bpp limit
-:46: WARNING:BAD_REPORTED_BY_LINK: Reported-by: should be immediately followed by Closes: with a URL to the report
#46:
Reported-by: Vidya Srinivas <vidya.srinivas@intel.com>
Reported-by: Swati Sharma <swati2.sharma@intel.com>
-:47: WARNING:BAD_REPORTED_BY_LINK: Reported-by: should be immediately followed by Closes: with a URL to the report
#47:
Reported-by: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
-:58: WARNING:LONG_LINE_COMMENT: line length of 111 exceeds 100 columns
#58: FILE: drivers/gpu/drm/display/drm_dp_helper.c:2554:
+ /* Synaptics Panamera supports only a compressed bpp of 12 above 50% of its max DSC pixel throughput */
-:59: WARNING:LONG_LINE: line length of 128 exceeds 100 columns
#59: FILE: drivers/gpu/drm/display/drm_dp_helper.c:2555:
+ { OUI(0x90, 0xCC, 0x24), DEVICE_ID('S', 'Y', 'N', 'A', 0x53, 0x22), true, BIT(DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT) },
-:60: WARNING:LONG_LINE: line length of 128 exceeds 100 columns
#60: FILE: drivers/gpu/drm/display/drm_dp_helper.c:2556:
+ { OUI(0x90, 0xCC, 0x24), DEVICE_ID('S', 'Y', 'N', 'A', 0x53, 0x31), true, BIT(DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT) },
-:61: WARNING:LONG_LINE: line length of 128 exceeds 100 columns
#61: FILE: drivers/gpu/drm/display/drm_dp_helper.c:2557:
+ { OUI(0x90, 0xCC, 0x24), DEVICE_ID('S', 'Y', 'N', 'A', 0x53, 0x33), true, BIT(DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT) },
total: 0 errors, 6 warnings, 0 checks, 25 lines checked
c8191003d571 drm/dp: Add helpers to query the branch DSC max throughput/line-width
d5e07aca3798 drm/i915/dp: Calculate DSC slice count based on per-slice peak throughput
afcba3c514bc drm/i915/dp: Pass DPCD device descriptor to intel_dp_get_dsc_sink_cap()
ba52e5677703 drm/i915/dp: Verify branch devices' overall pixel throughput/line width
c60fd37d3c48 drm/i915/dp: Handle Synaptics DSC throughput link-bpp quirk
-:30: WARNING:BAD_REPORTED_BY_LINK: Reported-by: should be immediately followed by Closes: with a URL to the report
#30:
Reported-by: Vidya Srinivas <vidya.srinivas@intel.com>
Reported-by: Swati Sharma <swati2.sharma@intel.com>
-:31: WARNING:BAD_REPORTED_BY_LINK: Reported-by: should be immediately followed by Closes: with a URL to the report
#31:
Reported-by: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
-:111: WARNING:LONG_LINE: line length of 140 exceeds 100 columns
#111: FILE: drivers/gpu/drm/i915/display/intel_dp.c:2576:
+ "[CRTC:%d:%s][CONNECTOR:%d:%s] Decreasing link max bpp to " FXP_Q4_FMT " due to DSC throughput quirk\n",
total: 0 errors, 3 warnings, 0 checks, 94 lines checked
^ permalink raw reply [flat|nested] 25+ messages in thread
* ✓ CI.KUnit: success for drm/i915/dp: Work around a DSC pixel throughput issue (rev5)
2025-09-26 21:12 [PATCH v4 0/6] drm/i915/dp: Work around a DSC pixel throughput issue Imre Deak
` (6 preceding siblings ...)
2025-09-26 21:56 ` ✗ CI.checkpatch: warning for drm/i915/dp: Work around a DSC pixel throughput issue (rev5) Patchwork
@ 2025-09-26 21:57 ` Patchwork
2025-09-26 22:33 ` ✓ Xe.CI.BAT: " Patchwork
` (6 subsequent siblings)
14 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2025-09-26 21:57 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-xe
== Series Details ==
Series: drm/i915/dp: Work around a DSC pixel throughput issue (rev5)
URL : https://patchwork.freedesktop.org/series/154737/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[21:56:04] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:56:09] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[21:56:38] Starting KUnit Kernel (1/1)...
[21:56:38] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:56:38] ================== guc_buf (11 subtests) ===================
[21:56:38] [PASSED] test_smallest
[21:56:38] [PASSED] test_largest
[21:56:38] [PASSED] test_granular
[21:56:38] [PASSED] test_unique
[21:56:38] [PASSED] test_overlap
[21:56:38] [PASSED] test_reusable
[21:56:38] [PASSED] test_too_big
[21:56:38] [PASSED] test_flush
[21:56:38] [PASSED] test_lookup
[21:56:38] [PASSED] test_data
[21:56:38] [PASSED] test_class
[21:56:38] ===================== [PASSED] guc_buf =====================
[21:56:38] =================== guc_dbm (7 subtests) ===================
[21:56:38] [PASSED] test_empty
[21:56:38] [PASSED] test_default
[21:56:38] ======================== test_size ========================
[21:56:38] [PASSED] 4
[21:56:38] [PASSED] 8
[21:56:38] [PASSED] 32
[21:56:38] [PASSED] 256
[21:56:38] ==================== [PASSED] test_size ====================
[21:56:38] ======================= test_reuse ========================
[21:56:38] [PASSED] 4
[21:56:38] [PASSED] 8
[21:56:38] [PASSED] 32
[21:56:38] [PASSED] 256
[21:56:38] =================== [PASSED] test_reuse ====================
[21:56:38] =================== test_range_overlap ====================
[21:56:38] [PASSED] 4
[21:56:38] [PASSED] 8
[21:56:38] [PASSED] 32
[21:56:38] [PASSED] 256
[21:56:38] =============== [PASSED] test_range_overlap ================
[21:56:38] =================== test_range_compact ====================
[21:56:38] [PASSED] 4
[21:56:38] [PASSED] 8
[21:56:38] [PASSED] 32
[21:56:38] [PASSED] 256
[21:56:38] =============== [PASSED] test_range_compact ================
[21:56:38] ==================== test_range_spare =====================
[21:56:38] [PASSED] 4
[21:56:38] [PASSED] 8
[21:56:38] [PASSED] 32
[21:56:38] [PASSED] 256
[21:56:38] ================ [PASSED] test_range_spare =================
[21:56:38] ===================== [PASSED] guc_dbm =====================
[21:56:38] =================== guc_idm (6 subtests) ===================
[21:56:38] [PASSED] bad_init
[21:56:38] [PASSED] no_init
[21:56:38] [PASSED] init_fini
[21:56:38] [PASSED] check_used
[21:56:38] [PASSED] check_quota
[21:56:38] [PASSED] check_all
[21:56:38] ===================== [PASSED] guc_idm =====================
[21:56:38] ================== no_relay (3 subtests) ===================
[21:56:38] [PASSED] xe_drops_guc2pf_if_not_ready
[21:56:38] [PASSED] xe_drops_guc2vf_if_not_ready
[21:56:38] [PASSED] xe_rejects_send_if_not_ready
[21:56:38] ==================== [PASSED] no_relay =====================
[21:56:38] ================== pf_relay (14 subtests) ==================
[21:56:38] [PASSED] pf_rejects_guc2pf_too_short
[21:56:38] [PASSED] pf_rejects_guc2pf_too_long
[21:56:38] [PASSED] pf_rejects_guc2pf_no_payload
[21:56:38] [PASSED] pf_fails_no_payload
[21:56:38] [PASSED] pf_fails_bad_origin
[21:56:38] [PASSED] pf_fails_bad_type
[21:56:38] [PASSED] pf_txn_reports_error
[21:56:38] [PASSED] pf_txn_sends_pf2guc
[21:56:38] [PASSED] pf_sends_pf2guc
[21:56:38] [SKIPPED] pf_loopback_nop
[21:56:38] [SKIPPED] pf_loopback_echo
[21:56:38] [SKIPPED] pf_loopback_fail
[21:56:38] [SKIPPED] pf_loopback_busy
[21:56:38] [SKIPPED] pf_loopback_retry
[21:56:38] ==================== [PASSED] pf_relay =====================
[21:56:38] ================== vf_relay (3 subtests) ===================
[21:56:38] [PASSED] vf_rejects_guc2vf_too_short
[21:56:38] [PASSED] vf_rejects_guc2vf_too_long
[21:56:38] [PASSED] vf_rejects_guc2vf_no_payload
[21:56:38] ==================== [PASSED] vf_relay =====================
[21:56:38] ===================== lmtt (1 subtest) =====================
[21:56:38] ======================== test_ops =========================
[21:56:38] [PASSED] 2-level
[21:56:38] [PASSED] multi-level
[21:56:38] ==================== [PASSED] test_ops =====================
[21:56:38] ====================== [PASSED] lmtt =======================
[21:56:38] ================= pf_service (11 subtests) =================
[21:56:38] [PASSED] pf_negotiate_any
[21:56:38] [PASSED] pf_negotiate_base_match
[21:56:38] [PASSED] pf_negotiate_base_newer
[21:56:38] [PASSED] pf_negotiate_base_next
[21:56:38] [SKIPPED] pf_negotiate_base_older
[21:56:38] [PASSED] pf_negotiate_base_prev
[21:56:38] [PASSED] pf_negotiate_latest_match
[21:56:38] [PASSED] pf_negotiate_latest_newer
[21:56:38] [PASSED] pf_negotiate_latest_next
[21:56:38] [SKIPPED] pf_negotiate_latest_older
[21:56:38] [SKIPPED] pf_negotiate_latest_prev
[21:56:38] =================== [PASSED] pf_service ====================
[21:56:38] ================= xe_guc_g2g (2 subtests) ==================
[21:56:38] ============== xe_live_guc_g2g_kunit_default ==============
[21:56:38] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[21:56:38] ============== xe_live_guc_g2g_kunit_allmem ===============
[21:56:38] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[21:56:38] =================== [SKIPPED] xe_guc_g2g ===================
[21:56:38] =================== xe_mocs (2 subtests) ===================
[21:56:38] ================ xe_live_mocs_kernel_kunit ================
[21:56:38] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[21:56:38] ================ xe_live_mocs_reset_kunit =================
[21:56:38] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[21:56:38] ==================== [SKIPPED] xe_mocs =====================
[21:56:38] ================= xe_migrate (2 subtests) ==================
[21:56:38] ================= xe_migrate_sanity_kunit =================
[21:56:38] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[21:56:38] ================== xe_validate_ccs_kunit ==================
[21:56:38] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[21:56:38] =================== [SKIPPED] xe_migrate ===================
[21:56:38] ================== xe_dma_buf (1 subtest) ==================
[21:56:38] ==================== xe_dma_buf_kunit =====================
[21:56:38] ================ [SKIPPED] xe_dma_buf_kunit ================
[21:56:38] =================== [SKIPPED] xe_dma_buf ===================
[21:56:38] ================= xe_bo_shrink (1 subtest) =================
[21:56:38] =================== xe_bo_shrink_kunit ====================
[21:56:38] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[21:56:38] ================== [SKIPPED] xe_bo_shrink ==================
[21:56:38] ==================== xe_bo (2 subtests) ====================
[21:56:38] ================== xe_ccs_migrate_kunit ===================
[21:56:38] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[21:56:38] ==================== xe_bo_evict_kunit ====================
[21:56:38] =============== [SKIPPED] xe_bo_evict_kunit ================
[21:56:38] ===================== [SKIPPED] xe_bo ======================
[21:56:38] ==================== args (11 subtests) ====================
[21:56:38] [PASSED] count_args_test
[21:56:38] [PASSED] call_args_example
[21:56:38] [PASSED] call_args_test
[21:56:38] [PASSED] drop_first_arg_example
[21:56:38] [PASSED] drop_first_arg_test
[21:56:38] [PASSED] first_arg_example
[21:56:38] [PASSED] first_arg_test
[21:56:38] [PASSED] last_arg_example
[21:56:38] [PASSED] last_arg_test
[21:56:38] [PASSED] pick_arg_example
[21:56:38] [PASSED] sep_comma_example
[21:56:38] ====================== [PASSED] args =======================
[21:56:38] =================== xe_pci (3 subtests) ====================
[21:56:38] ==================== check_graphics_ip ====================
[21:56:38] [PASSED] 12.00 Xe_LP
[21:56:38] [PASSED] 12.10 Xe_LP+
[21:56:38] [PASSED] 12.55 Xe_HPG
[21:56:38] [PASSED] 12.60 Xe_HPC
[21:56:38] [PASSED] 12.70 Xe_LPG
[21:56:38] [PASSED] 12.71 Xe_LPG
[21:56:38] [PASSED] 12.74 Xe_LPG+
[21:56:38] [PASSED] 20.01 Xe2_HPG
[21:56:38] [PASSED] 20.02 Xe2_HPG
[21:56:38] [PASSED] 20.04 Xe2_LPG
[21:56:38] [PASSED] 30.00 Xe3_LPG
[21:56:38] [PASSED] 30.01 Xe3_LPG
[21:56:38] [PASSED] 30.03 Xe3_LPG
[21:56:38] ================ [PASSED] check_graphics_ip ================
[21:56:38] ===================== check_media_ip ======================
[21:56:38] [PASSED] 12.00 Xe_M
[21:56:38] [PASSED] 12.55 Xe_HPM
[21:56:38] [PASSED] 13.00 Xe_LPM+
[21:56:38] [PASSED] 13.01 Xe2_HPM
[21:56:38] [PASSED] 20.00 Xe2_LPM
[21:56:38] [PASSED] 30.00 Xe3_LPM
[21:56:38] [PASSED] 30.02 Xe3_LPM
[21:56:38] ================= [PASSED] check_media_ip ==================
[21:56:38] ================= check_platform_gt_count =================
[21:56:38] [PASSED] 0x9A60 (TIGERLAKE)
[21:56:38] [PASSED] 0x9A68 (TIGERLAKE)
[21:56:38] [PASSED] 0x9A70 (TIGERLAKE)
[21:56:38] [PASSED] 0x9A40 (TIGERLAKE)
[21:56:38] [PASSED] 0x9A49 (TIGERLAKE)
[21:56:38] [PASSED] 0x9A59 (TIGERLAKE)
[21:56:38] [PASSED] 0x9A78 (TIGERLAKE)
[21:56:38] [PASSED] 0x9AC0 (TIGERLAKE)
[21:56:38] [PASSED] 0x9AC9 (TIGERLAKE)
[21:56:38] [PASSED] 0x9AD9 (TIGERLAKE)
[21:56:38] [PASSED] 0x9AF8 (TIGERLAKE)
[21:56:38] [PASSED] 0x4C80 (ROCKETLAKE)
[21:56:38] [PASSED] 0x4C8A (ROCKETLAKE)
[21:56:38] [PASSED] 0x4C8B (ROCKETLAKE)
[21:56:38] [PASSED] 0x4C8C (ROCKETLAKE)
[21:56:38] [PASSED] 0x4C90 (ROCKETLAKE)
[21:56:38] [PASSED] 0x4C9A (ROCKETLAKE)
[21:56:38] [PASSED] 0x4680 (ALDERLAKE_S)
[21:56:38] [PASSED] 0x4682 (ALDERLAKE_S)
[21:56:38] [PASSED] 0x4688 (ALDERLAKE_S)
[21:56:38] [PASSED] 0x468A (ALDERLAKE_S)
[21:56:38] [PASSED] 0x468B (ALDERLAKE_S)
[21:56:38] [PASSED] 0x4690 (ALDERLAKE_S)
[21:56:38] [PASSED] 0x4692 (ALDERLAKE_S)
[21:56:38] [PASSED] 0x4693 (ALDERLAKE_S)
[21:56:38] [PASSED] 0x46A0 (ALDERLAKE_P)
[21:56:38] [PASSED] 0x46A1 (ALDERLAKE_P)
[21:56:38] [PASSED] 0x46A2 (ALDERLAKE_P)
[21:56:38] [PASSED] 0x46A3 (ALDERLAKE_P)
[21:56:38] [PASSED] 0x46A6 (ALDERLAKE_P)
[21:56:38] [PASSED] 0x46A8 (ALDERLAKE_P)
[21:56:38] [PASSED] 0x46AA (ALDERLAKE_P)
[21:56:38] [PASSED] 0x462A (ALDERLAKE_P)
[21:56:38] [PASSED] 0x4626 (ALDERLAKE_P)
[21:56:38] [PASSED] 0x4628 (ALDERLAKE_P)
[21:56:38] [PASSED] 0x46B0 (ALDERLAKE_P)
[21:56:38] [PASSED] 0x46B1 (ALDERLAKE_P)
[21:56:38] [PASSED] 0x46B2 (ALDERLAKE_P)
[21:56:38] [PASSED] 0x46B3 (ALDERLAKE_P)
[21:56:38] [PASSED] 0x46C0 (ALDERLAKE_P)
[21:56:38] [PASSED] 0x46C1 (ALDERLAKE_P)
[21:56:38] [PASSED] 0x46C2 (ALDERLAKE_P)
[21:56:38] [PASSED] 0x46C3 (ALDERLAKE_P)
[21:56:38] [PASSED] 0x46D0 (ALDERLAKE_N)
[21:56:38] [PASSED] 0x46D1 (ALDERLAKE_N)
[21:56:38] [PASSED] 0x46D2 (ALDERLAKE_N)
[21:56:38] [PASSED] 0x46D3 (ALDERLAKE_N)
[21:56:38] [PASSED] 0x46D4 (ALDERLAKE_N)
[21:56:38] [PASSED] 0xA721 (ALDERLAKE_P)
[21:56:38] [PASSED] 0xA7A1 (ALDERLAKE_P)
[21:56:38] [PASSED] 0xA7A9 (ALDERLAKE_P)
[21:56:38] [PASSED] 0xA7AC (ALDERLAKE_P)
[21:56:38] [PASSED] 0xA7AD (ALDERLAKE_P)
[21:56:38] [PASSED] 0xA720 (ALDERLAKE_P)
[21:56:38] [PASSED] 0xA7A0 (ALDERLAKE_P)
[21:56:38] [PASSED] 0xA7A8 (ALDERLAKE_P)
[21:56:38] [PASSED] 0xA7AA (ALDERLAKE_P)
[21:56:38] [PASSED] 0xA7AB (ALDERLAKE_P)
[21:56:38] [PASSED] 0xA780 (ALDERLAKE_S)
[21:56:38] [PASSED] 0xA781 (ALDERLAKE_S)
[21:56:38] [PASSED] 0xA782 (ALDERLAKE_S)
[21:56:38] [PASSED] 0xA783 (ALDERLAKE_S)
[21:56:38] [PASSED] 0xA788 (ALDERLAKE_S)
[21:56:38] [PASSED] 0xA789 (ALDERLAKE_S)
[21:56:38] [PASSED] 0xA78A (ALDERLAKE_S)
[21:56:38] [PASSED] 0xA78B (ALDERLAKE_S)
[21:56:38] [PASSED] 0x4905 (DG1)
[21:56:38] [PASSED] 0x4906 (DG1)
[21:56:38] [PASSED] 0x4907 (DG1)
[21:56:38] [PASSED] 0x4908 (DG1)
[21:56:38] [PASSED] 0x4909 (DG1)
[21:56:38] [PASSED] 0x56C0 (DG2)
[21:56:38] [PASSED] 0x56C2 (DG2)
[21:56:38] [PASSED] 0x56C1 (DG2)
[21:56:38] [PASSED] 0x7D51 (METEORLAKE)
[21:56:38] [PASSED] 0x7DD1 (METEORLAKE)
[21:56:38] [PASSED] 0x7D41 (METEORLAKE)
[21:56:38] [PASSED] 0x7D67 (METEORLAKE)
[21:56:38] [PASSED] 0xB640 (METEORLAKE)
[21:56:38] [PASSED] 0x56A0 (DG2)
[21:56:38] [PASSED] 0x56A1 (DG2)
[21:56:38] [PASSED] 0x56A2 (DG2)
[21:56:38] [PASSED] 0x56BE (DG2)
[21:56:38] [PASSED] 0x56BF (DG2)
[21:56:38] [PASSED] 0x5690 (DG2)
[21:56:38] [PASSED] 0x5691 (DG2)
[21:56:38] [PASSED] 0x5692 (DG2)
[21:56:38] [PASSED] 0x56A5 (DG2)
[21:56:38] [PASSED] 0x56A6 (DG2)
[21:56:38] [PASSED] 0x56B0 (DG2)
[21:56:38] [PASSED] 0x56B1 (DG2)
[21:56:38] [PASSED] 0x56BA (DG2)
[21:56:38] [PASSED] 0x56BB (DG2)
[21:56:38] [PASSED] 0x56BC (DG2)
[21:56:38] [PASSED] 0x56BD (DG2)
[21:56:38] [PASSED] 0x5693 (DG2)
[21:56:38] [PASSED] 0x5694 (DG2)
[21:56:38] [PASSED] 0x5695 (DG2)
[21:56:38] [PASSED] 0x56A3 (DG2)
[21:56:38] [PASSED] 0x56A4 (DG2)
[21:56:38] [PASSED] 0x56B2 (DG2)
[21:56:38] [PASSED] 0x56B3 (DG2)
[21:56:38] [PASSED] 0x5696 (DG2)
[21:56:38] [PASSED] 0x5697 (DG2)
[21:56:38] [PASSED] 0xB69 (PVC)
[21:56:38] [PASSED] 0xB6E (PVC)
[21:56:38] [PASSED] 0xBD4 (PVC)
[21:56:38] [PASSED] 0xBD5 (PVC)
[21:56:38] [PASSED] 0xBD6 (PVC)
[21:56:38] [PASSED] 0xBD7 (PVC)
[21:56:38] [PASSED] 0xBD8 (PVC)
[21:56:38] [PASSED] 0xBD9 (PVC)
[21:56:38] [PASSED] 0xBDA (PVC)
[21:56:38] [PASSED] 0xBDB (PVC)
[21:56:38] [PASSED] 0xBE0 (PVC)
[21:56:38] [PASSED] 0xBE1 (PVC)
[21:56:38] [PASSED] 0xBE5 (PVC)
[21:56:38] [PASSED] 0x7D40 (METEORLAKE)
[21:56:38] [PASSED] 0x7D45 (METEORLAKE)
[21:56:38] [PASSED] 0x7D55 (METEORLAKE)
[21:56:38] [PASSED] 0x7D60 (METEORLAKE)
[21:56:38] [PASSED] 0x7DD5 (METEORLAKE)
[21:56:38] [PASSED] 0x6420 (LUNARLAKE)
[21:56:38] [PASSED] 0x64A0 (LUNARLAKE)
[21:56:38] [PASSED] 0x64B0 (LUNARLAKE)
[21:56:38] [PASSED] 0xE202 (BATTLEMAGE)
[21:56:38] [PASSED] 0xE209 (BATTLEMAGE)
[21:56:38] [PASSED] 0xE20B (BATTLEMAGE)
[21:56:38] [PASSED] 0xE20C (BATTLEMAGE)
[21:56:38] [PASSED] 0xE20D (BATTLEMAGE)
[21:56:38] [PASSED] 0xE210 (BATTLEMAGE)
[21:56:38] [PASSED] 0xE211 (BATTLEMAGE)
[21:56:38] [PASSED] 0xE212 (BATTLEMAGE)
[21:56:38] [PASSED] 0xE216 (BATTLEMAGE)
[21:56:38] [PASSED] 0xE220 (BATTLEMAGE)
[21:56:38] [PASSED] 0xE221 (BATTLEMAGE)
[21:56:38] [PASSED] 0xE222 (BATTLEMAGE)
[21:56:38] [PASSED] 0xE223 (BATTLEMAGE)
[21:56:38] [PASSED] 0xB080 (PANTHERLAKE)
[21:56:38] [PASSED] 0xB081 (PANTHERLAKE)
[21:56:38] [PASSED] 0xB082 (PANTHERLAKE)
[21:56:38] [PASSED] 0xB083 (PANTHERLAKE)
[21:56:38] [PASSED] 0xB084 (PANTHERLAKE)
[21:56:38] [PASSED] 0xB085 (PANTHERLAKE)
[21:56:38] [PASSED] 0xB086 (PANTHERLAKE)
[21:56:38] [PASSED] 0xB087 (PANTHERLAKE)
[21:56:38] [PASSED] 0xB08F (PANTHERLAKE)
[21:56:38] [PASSED] 0xB090 (PANTHERLAKE)
[21:56:38] [PASSED] 0xB0A0 (PANTHERLAKE)
[21:56:38] [PASSED] 0xB0B0 (PANTHERLAKE)
[21:56:38] [PASSED] 0xFD80 (PANTHERLAKE)
[21:56:38] [PASSED] 0xFD81 (PANTHERLAKE)
[21:56:38] ============= [PASSED] check_platform_gt_count =============
[21:56:38] ===================== [PASSED] xe_pci ======================
[21:56:38] =================== xe_rtp (2 subtests) ====================
[21:56:38] =============== xe_rtp_process_to_sr_tests ================
[21:56:38] [PASSED] coalesce-same-reg
[21:56:38] [PASSED] no-match-no-add
[21:56:38] [PASSED] match-or
[21:56:38] [PASSED] match-or-xfail
[21:56:38] [PASSED] no-match-no-add-multiple-rules
[21:56:38] [PASSED] two-regs-two-entries
[21:56:38] [PASSED] clr-one-set-other
[21:56:38] [PASSED] set-field
[21:56:38] [PASSED] conflict-duplicate
[21:56:38] [PASSED] conflict-not-disjoint
[21:56:38] [PASSED] conflict-reg-type
[21:56:38] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[21:56:38] ================== xe_rtp_process_tests ===================
[21:56:38] [PASSED] active1
[21:56:38] [PASSED] active2
[21:56:38] [PASSED] active-inactive
[21:56:38] [PASSED] inactive-active
[21:56:38] [PASSED] inactive-1st_or_active-inactive
[21:56:38] [PASSED] inactive-2nd_or_active-inactive
[21:56:38] [PASSED] inactive-last_or_active-inactive
[21:56:38] [PASSED] inactive-no_or_active-inactive
[21:56:38] ============== [PASSED] xe_rtp_process_tests ===============
[21:56:38] ===================== [PASSED] xe_rtp ======================
[21:56:38] ==================== xe_wa (1 subtest) =====================
[21:56:38] ======================== xe_wa_gt =========================
[21:56:38] [PASSED] TIGERLAKE B0
[21:56:38] [PASSED] DG1 A0
[21:56:38] [PASSED] DG1 B0
[21:56:38] [PASSED] ALDERLAKE_S A0
[21:56:38] [PASSED] ALDERLAKE_S B0
stty: 'standard input': Inappropriate ioctl for device
[21:56:38] [PASSED] ALDERLAKE_S C0
[21:56:38] [PASSED] ALDERLAKE_S D0
[21:56:38] [PASSED] ALDERLAKE_P A0
[21:56:38] [PASSED] ALDERLAKE_P B0
[21:56:38] [PASSED] ALDERLAKE_P C0
[21:56:38] [PASSED] ALDERLAKE_S RPLS D0
[21:56:38] [PASSED] ALDERLAKE_P RPLU E0
[21:56:38] [PASSED] DG2 G10 C0
[21:56:38] [PASSED] DG2 G11 B1
[21:56:38] [PASSED] DG2 G12 A1
[21:56:38] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[21:56:38] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[21:56:38] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[21:56:38] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[21:56:38] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[21:56:38] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[21:56:38] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[21:56:38] ==================== [PASSED] xe_wa_gt =====================
[21:56:38] ====================== [PASSED] xe_wa ======================
[21:56:38] ============================================================
[21:56:38] Testing complete. Ran 306 tests: passed: 288, skipped: 18
[21:56:38] Elapsed time: 33.673s total, 4.279s configuring, 29.027s building, 0.322s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[21:56:38] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:56:40] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[21:57:03] Starting KUnit Kernel (1/1)...
[21:57:03] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:57:03] ============ drm_test_pick_cmdline (2 subtests) ============
[21:57:03] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[21:57:03] =============== drm_test_pick_cmdline_named ===============
[21:57:03] [PASSED] NTSC
[21:57:03] [PASSED] NTSC-J
[21:57:03] [PASSED] PAL
[21:57:03] [PASSED] PAL-M
[21:57:03] =========== [PASSED] drm_test_pick_cmdline_named ===========
[21:57:03] ============== [PASSED] drm_test_pick_cmdline ==============
[21:57:03] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[21:57:03] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[21:57:03] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[21:57:03] =========== drm_validate_clone_mode (2 subtests) ===========
[21:57:03] ============== drm_test_check_in_clone_mode ===============
[21:57:03] [PASSED] in_clone_mode
[21:57:03] [PASSED] not_in_clone_mode
[21:57:03] ========== [PASSED] drm_test_check_in_clone_mode ===========
[21:57:03] =============== drm_test_check_valid_clones ===============
[21:57:03] [PASSED] not_in_clone_mode
[21:57:03] [PASSED] valid_clone
[21:57:03] [PASSED] invalid_clone
[21:57:03] =========== [PASSED] drm_test_check_valid_clones ===========
[21:57:03] ============= [PASSED] drm_validate_clone_mode =============
[21:57:03] ============= drm_validate_modeset (1 subtest) =============
[21:57:03] [PASSED] drm_test_check_connector_changed_modeset
[21:57:03] ============== [PASSED] drm_validate_modeset ===============
[21:57:03] ====== drm_test_bridge_get_current_state (2 subtests) ======
[21:57:03] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[21:57:03] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[21:57:03] ======== [PASSED] drm_test_bridge_get_current_state ========
[21:57:03] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[21:57:03] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[21:57:03] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[21:57:03] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[21:57:03] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[21:57:03] ============== drm_bridge_alloc (2 subtests) ===============
[21:57:03] [PASSED] drm_test_drm_bridge_alloc_basic
[21:57:03] [PASSED] drm_test_drm_bridge_alloc_get_put
[21:57:03] ================ [PASSED] drm_bridge_alloc =================
[21:57:03] ================== drm_buddy (7 subtests) ==================
[21:57:03] [PASSED] drm_test_buddy_alloc_limit
[21:57:03] [PASSED] drm_test_buddy_alloc_optimistic
[21:57:03] [PASSED] drm_test_buddy_alloc_pessimistic
[21:57:03] [PASSED] drm_test_buddy_alloc_pathological
[21:57:03] [PASSED] drm_test_buddy_alloc_contiguous
[21:57:03] [PASSED] drm_test_buddy_alloc_clear
[21:57:03] [PASSED] drm_test_buddy_alloc_range_bias
[21:57:03] ==================== [PASSED] drm_buddy ====================
[21:57:03] ============= drm_cmdline_parser (40 subtests) =============
[21:57:03] [PASSED] drm_test_cmdline_force_d_only
[21:57:03] [PASSED] drm_test_cmdline_force_D_only_dvi
[21:57:03] [PASSED] drm_test_cmdline_force_D_only_hdmi
[21:57:03] [PASSED] drm_test_cmdline_force_D_only_not_digital
[21:57:03] [PASSED] drm_test_cmdline_force_e_only
[21:57:03] [PASSED] drm_test_cmdline_res
[21:57:03] [PASSED] drm_test_cmdline_res_vesa
[21:57:03] [PASSED] drm_test_cmdline_res_vesa_rblank
[21:57:03] [PASSED] drm_test_cmdline_res_rblank
[21:57:03] [PASSED] drm_test_cmdline_res_bpp
[21:57:03] [PASSED] drm_test_cmdline_res_refresh
[21:57:03] [PASSED] drm_test_cmdline_res_bpp_refresh
[21:57:03] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[21:57:03] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[21:57:03] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[21:57:03] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[21:57:03] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[21:57:03] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[21:57:03] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[21:57:03] [PASSED] drm_test_cmdline_res_margins_force_on
[21:57:03] [PASSED] drm_test_cmdline_res_vesa_margins
[21:57:03] [PASSED] drm_test_cmdline_name
[21:57:03] [PASSED] drm_test_cmdline_name_bpp
[21:57:03] [PASSED] drm_test_cmdline_name_option
[21:57:03] [PASSED] drm_test_cmdline_name_bpp_option
[21:57:03] [PASSED] drm_test_cmdline_rotate_0
[21:57:03] [PASSED] drm_test_cmdline_rotate_90
[21:57:03] [PASSED] drm_test_cmdline_rotate_180
[21:57:03] [PASSED] drm_test_cmdline_rotate_270
[21:57:03] [PASSED] drm_test_cmdline_hmirror
[21:57:03] [PASSED] drm_test_cmdline_vmirror
[21:57:03] [PASSED] drm_test_cmdline_margin_options
[21:57:03] [PASSED] drm_test_cmdline_multiple_options
[21:57:03] [PASSED] drm_test_cmdline_bpp_extra_and_option
[21:57:03] [PASSED] drm_test_cmdline_extra_and_option
[21:57:03] [PASSED] drm_test_cmdline_freestanding_options
[21:57:03] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[21:57:03] [PASSED] drm_test_cmdline_panel_orientation
[21:57:03] ================ drm_test_cmdline_invalid =================
[21:57:03] [PASSED] margin_only
[21:57:03] [PASSED] interlace_only
[21:57:03] [PASSED] res_missing_x
[21:57:03] [PASSED] res_missing_y
[21:57:03] [PASSED] res_bad_y
[21:57:03] [PASSED] res_missing_y_bpp
[21:57:03] [PASSED] res_bad_bpp
[21:57:03] [PASSED] res_bad_refresh
[21:57:03] [PASSED] res_bpp_refresh_force_on_off
[21:57:03] [PASSED] res_invalid_mode
[21:57:03] [PASSED] res_bpp_wrong_place_mode
[21:57:03] [PASSED] name_bpp_refresh
[21:57:03] [PASSED] name_refresh
[21:57:03] [PASSED] name_refresh_wrong_mode
[21:57:03] [PASSED] name_refresh_invalid_mode
[21:57:03] [PASSED] rotate_multiple
[21:57:03] [PASSED] rotate_invalid_val
[21:57:03] [PASSED] rotate_truncated
[21:57:03] [PASSED] invalid_option
[21:57:03] [PASSED] invalid_tv_option
[21:57:03] [PASSED] truncated_tv_option
[21:57:03] ============ [PASSED] drm_test_cmdline_invalid =============
[21:57:03] =============== drm_test_cmdline_tv_options ===============
[21:57:03] [PASSED] NTSC
[21:57:03] [PASSED] NTSC_443
[21:57:03] [PASSED] NTSC_J
[21:57:03] [PASSED] PAL
[21:57:03] [PASSED] PAL_M
[21:57:03] [PASSED] PAL_N
[21:57:03] [PASSED] SECAM
[21:57:03] [PASSED] MONO_525
[21:57:03] [PASSED] MONO_625
[21:57:03] =========== [PASSED] drm_test_cmdline_tv_options ===========
[21:57:03] =============== [PASSED] drm_cmdline_parser ================
[21:57:03] ========== drmm_connector_hdmi_init (20 subtests) ==========
[21:57:03] [PASSED] drm_test_connector_hdmi_init_valid
[21:57:03] [PASSED] drm_test_connector_hdmi_init_bpc_8
[21:57:03] [PASSED] drm_test_connector_hdmi_init_bpc_10
[21:57:03] [PASSED] drm_test_connector_hdmi_init_bpc_12
[21:57:03] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[21:57:03] [PASSED] drm_test_connector_hdmi_init_bpc_null
[21:57:03] [PASSED] drm_test_connector_hdmi_init_formats_empty
[21:57:03] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[21:57:03] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[21:57:03] [PASSED] supported_formats=0x9 yuv420_allowed=1
[21:57:03] [PASSED] supported_formats=0x9 yuv420_allowed=0
[21:57:03] [PASSED] supported_formats=0x3 yuv420_allowed=1
[21:57:03] [PASSED] supported_formats=0x3 yuv420_allowed=0
[21:57:03] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[21:57:03] [PASSED] drm_test_connector_hdmi_init_null_ddc
[21:57:03] [PASSED] drm_test_connector_hdmi_init_null_product
[21:57:03] [PASSED] drm_test_connector_hdmi_init_null_vendor
[21:57:03] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[21:57:03] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[21:57:03] [PASSED] drm_test_connector_hdmi_init_product_valid
[21:57:03] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[21:57:03] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[21:57:03] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[21:57:03] ========= drm_test_connector_hdmi_init_type_valid =========
[21:57:03] [PASSED] HDMI-A
[21:57:03] [PASSED] HDMI-B
[21:57:03] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[21:57:03] ======== drm_test_connector_hdmi_init_type_invalid ========
[21:57:03] [PASSED] Unknown
[21:57:03] [PASSED] VGA
[21:57:03] [PASSED] DVI-I
[21:57:03] [PASSED] DVI-D
[21:57:03] [PASSED] DVI-A
[21:57:03] [PASSED] Composite
[21:57:03] [PASSED] SVIDEO
[21:57:03] [PASSED] LVDS
[21:57:03] [PASSED] Component
[21:57:03] [PASSED] DIN
[21:57:03] [PASSED] DP
[21:57:03] [PASSED] TV
[21:57:03] [PASSED] eDP
[21:57:03] [PASSED] Virtual
[21:57:03] [PASSED] DSI
[21:57:03] [PASSED] DPI
[21:57:03] [PASSED] Writeback
[21:57:03] [PASSED] SPI
[21:57:03] [PASSED] USB
[21:57:03] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[21:57:03] ============ [PASSED] drmm_connector_hdmi_init =============
[21:57:03] ============= drmm_connector_init (3 subtests) =============
[21:57:03] [PASSED] drm_test_drmm_connector_init
[21:57:03] [PASSED] drm_test_drmm_connector_init_null_ddc
[21:57:03] ========= drm_test_drmm_connector_init_type_valid =========
[21:57:03] [PASSED] Unknown
[21:57:03] [PASSED] VGA
[21:57:03] [PASSED] DVI-I
[21:57:03] [PASSED] DVI-D
[21:57:03] [PASSED] DVI-A
[21:57:03] [PASSED] Composite
[21:57:03] [PASSED] SVIDEO
[21:57:03] [PASSED] LVDS
[21:57:03] [PASSED] Component
[21:57:03] [PASSED] DIN
[21:57:03] [PASSED] DP
[21:57:03] [PASSED] HDMI-A
[21:57:03] [PASSED] HDMI-B
[21:57:03] [PASSED] TV
[21:57:03] [PASSED] eDP
[21:57:03] [PASSED] Virtual
[21:57:03] [PASSED] DSI
[21:57:03] [PASSED] DPI
[21:57:03] [PASSED] Writeback
[21:57:03] [PASSED] SPI
[21:57:03] [PASSED] USB
[21:57:03] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[21:57:03] =============== [PASSED] drmm_connector_init ===============
[21:57:03] ========= drm_connector_dynamic_init (6 subtests) ==========
[21:57:03] [PASSED] drm_test_drm_connector_dynamic_init
[21:57:03] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[21:57:03] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[21:57:03] [PASSED] drm_test_drm_connector_dynamic_init_properties
[21:57:03] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[21:57:03] [PASSED] Unknown
[21:57:03] [PASSED] VGA
[21:57:03] [PASSED] DVI-I
[21:57:03] [PASSED] DVI-D
[21:57:03] [PASSED] DVI-A
[21:57:03] [PASSED] Composite
[21:57:03] [PASSED] SVIDEO
[21:57:03] [PASSED] LVDS
[21:57:03] [PASSED] Component
[21:57:03] [PASSED] DIN
[21:57:03] [PASSED] DP
[21:57:03] [PASSED] HDMI-A
[21:57:03] [PASSED] HDMI-B
[21:57:03] [PASSED] TV
[21:57:03] [PASSED] eDP
[21:57:03] [PASSED] Virtual
[21:57:03] [PASSED] DSI
[21:57:03] [PASSED] DPI
[21:57:03] [PASSED] Writeback
[21:57:03] [PASSED] SPI
[21:57:03] [PASSED] USB
[21:57:03] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[21:57:03] ======== drm_test_drm_connector_dynamic_init_name =========
[21:57:03] [PASSED] Unknown
[21:57:03] [PASSED] VGA
[21:57:03] [PASSED] DVI-I
[21:57:03] [PASSED] DVI-D
[21:57:03] [PASSED] DVI-A
[21:57:03] [PASSED] Composite
[21:57:03] [PASSED] SVIDEO
[21:57:03] [PASSED] LVDS
[21:57:03] [PASSED] Component
[21:57:03] [PASSED] DIN
[21:57:03] [PASSED] DP
[21:57:03] [PASSED] HDMI-A
[21:57:03] [PASSED] HDMI-B
[21:57:03] [PASSED] TV
[21:57:03] [PASSED] eDP
[21:57:03] [PASSED] Virtual
[21:57:03] [PASSED] DSI
[21:57:03] [PASSED] DPI
[21:57:03] [PASSED] Writeback
[21:57:03] [PASSED] SPI
[21:57:03] [PASSED] USB
[21:57:03] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[21:57:03] =========== [PASSED] drm_connector_dynamic_init ============
[21:57:03] ==== drm_connector_dynamic_register_early (4 subtests) =====
[21:57:03] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[21:57:03] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[21:57:03] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[21:57:03] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[21:57:03] ====== [PASSED] drm_connector_dynamic_register_early =======
[21:57:03] ======= drm_connector_dynamic_register (7 subtests) ========
[21:57:03] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[21:57:03] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[21:57:03] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[21:57:03] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[21:57:03] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[21:57:03] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[21:57:03] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[21:57:03] ========= [PASSED] drm_connector_dynamic_register ==========
[21:57:03] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[21:57:03] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[21:57:03] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[21:57:03] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[21:57:03] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[21:57:03] ========== drm_test_get_tv_mode_from_name_valid ===========
[21:57:03] [PASSED] NTSC
[21:57:03] [PASSED] NTSC-443
[21:57:03] [PASSED] NTSC-J
[21:57:03] [PASSED] PAL
[21:57:03] [PASSED] PAL-M
[21:57:03] [PASSED] PAL-N
[21:57:03] [PASSED] SECAM
[21:57:03] [PASSED] Mono
[21:57:03] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[21:57:03] [PASSED] drm_test_get_tv_mode_from_name_truncated
[21:57:03] ============ [PASSED] drm_get_tv_mode_from_name ============
[21:57:03] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[21:57:03] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[21:57:03] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[21:57:03] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[21:57:03] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[21:57:03] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[21:57:03] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[21:57:03] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[21:57:03] [PASSED] VIC 96
[21:57:03] [PASSED] VIC 97
[21:57:03] [PASSED] VIC 101
[21:57:03] [PASSED] VIC 102
[21:57:03] [PASSED] VIC 106
[21:57:03] [PASSED] VIC 107
[21:57:03] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[21:57:03] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[21:57:03] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[21:57:03] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[21:57:03] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[21:57:03] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[21:57:03] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[21:57:03] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[21:57:03] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[21:57:03] [PASSED] Automatic
[21:57:03] [PASSED] Full
[21:57:03] [PASSED] Limited 16:235
[21:57:03] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[21:57:03] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[21:57:03] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[21:57:03] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[21:57:03] === drm_test_drm_hdmi_connector_get_output_format_name ====
[21:57:03] [PASSED] RGB
[21:57:03] [PASSED] YUV 4:2:0
[21:57:03] [PASSED] YUV 4:2:2
[21:57:03] [PASSED] YUV 4:4:4
[21:57:03] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[21:57:03] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[21:57:03] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[21:57:03] ============= drm_damage_helper (21 subtests) ==============
[21:57:03] [PASSED] drm_test_damage_iter_no_damage
[21:57:03] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[21:57:03] [PASSED] drm_test_damage_iter_no_damage_src_moved
[21:57:03] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[21:57:03] [PASSED] drm_test_damage_iter_no_damage_not_visible
[21:57:03] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[21:57:03] [PASSED] drm_test_damage_iter_no_damage_no_fb
[21:57:03] [PASSED] drm_test_damage_iter_simple_damage
[21:57:03] [PASSED] drm_test_damage_iter_single_damage
[21:57:03] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[21:57:03] [PASSED] drm_test_damage_iter_single_damage_outside_src
[21:57:03] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[21:57:03] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[21:57:03] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[21:57:03] [PASSED] drm_test_damage_iter_single_damage_src_moved
[21:57:03] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[21:57:03] [PASSED] drm_test_damage_iter_damage
[21:57:03] [PASSED] drm_test_damage_iter_damage_one_intersect
[21:57:03] [PASSED] drm_test_damage_iter_damage_one_outside
[21:57:03] [PASSED] drm_test_damage_iter_damage_src_moved
[21:57:03] [PASSED] drm_test_damage_iter_damage_not_visible
[21:57:03] ================ [PASSED] drm_damage_helper ================
[21:57:03] ============== drm_dp_mst_helper (3 subtests) ==============
[21:57:03] ============== drm_test_dp_mst_calc_pbn_mode ==============
[21:57:03] [PASSED] Clock 154000 BPP 30 DSC disabled
[21:57:03] [PASSED] Clock 234000 BPP 30 DSC disabled
[21:57:03] [PASSED] Clock 297000 BPP 24 DSC disabled
[21:57:03] [PASSED] Clock 332880 BPP 24 DSC enabled
[21:57:03] [PASSED] Clock 324540 BPP 24 DSC enabled
[21:57:03] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[21:57:03] ============== drm_test_dp_mst_calc_pbn_div ===============
[21:57:03] [PASSED] Link rate 2000000 lane count 4
[21:57:03] [PASSED] Link rate 2000000 lane count 2
[21:57:03] [PASSED] Link rate 2000000 lane count 1
[21:57:03] [PASSED] Link rate 1350000 lane count 4
[21:57:03] [PASSED] Link rate 1350000 lane count 2
[21:57:03] [PASSED] Link rate 1350000 lane count 1
[21:57:03] [PASSED] Link rate 1000000 lane count 4
[21:57:03] [PASSED] Link rate 1000000 lane count 2
[21:57:03] [PASSED] Link rate 1000000 lane count 1
[21:57:03] [PASSED] Link rate 810000 lane count 4
[21:57:03] [PASSED] Link rate 810000 lane count 2
[21:57:03] [PASSED] Link rate 810000 lane count 1
[21:57:03] [PASSED] Link rate 540000 lane count 4
[21:57:03] [PASSED] Link rate 540000 lane count 2
[21:57:03] [PASSED] Link rate 540000 lane count 1
[21:57:03] [PASSED] Link rate 270000 lane count 4
[21:57:03] [PASSED] Link rate 270000 lane count 2
[21:57:03] [PASSED] Link rate 270000 lane count 1
[21:57:03] [PASSED] Link rate 162000 lane count 4
[21:57:03] [PASSED] Link rate 162000 lane count 2
[21:57:03] [PASSED] Link rate 162000 lane count 1
[21:57:03] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[21:57:03] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[21:57:03] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[21:57:03] [PASSED] DP_POWER_UP_PHY with port number
[21:57:03] [PASSED] DP_POWER_DOWN_PHY with port number
[21:57:03] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[21:57:03] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[21:57:03] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[21:57:03] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[21:57:03] [PASSED] DP_QUERY_PAYLOAD with port number
[21:57:03] [PASSED] DP_QUERY_PAYLOAD with VCPI
[21:57:03] [PASSED] DP_REMOTE_DPCD_READ with port number
[21:57:03] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[21:57:03] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[21:57:03] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[21:57:03] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[21:57:03] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[21:57:03] [PASSED] DP_REMOTE_I2C_READ with port number
[21:57:03] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[21:57:03] [PASSED] DP_REMOTE_I2C_READ with transactions array
[21:57:03] [PASSED] DP_REMOTE_I2C_WRITE with port number
[21:57:03] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[21:57:03] [PASSED] DP_REMOTE_I2C_WRITE with data array
[21:57:03] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[21:57:03] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[21:57:03] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[21:57:03] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[21:57:03] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[21:57:03] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[21:57:03] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[21:57:03] ================ [PASSED] drm_dp_mst_helper ================
[21:57:03] ================== drm_exec (7 subtests) ===================
[21:57:03] [PASSED] sanitycheck
[21:57:03] [PASSED] test_lock
[21:57:03] [PASSED] test_lock_unlock
[21:57:03] [PASSED] test_duplicates
[21:57:03] [PASSED] test_prepare
[21:57:03] [PASSED] test_prepare_array
[21:57:03] [PASSED] test_multiple_loops
[21:57:03] ==================== [PASSED] drm_exec =====================
[21:57:03] =========== drm_format_helper_test (17 subtests) ===========
[21:57:03] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[21:57:03] [PASSED] single_pixel_source_buffer
[21:57:03] [PASSED] single_pixel_clip_rectangle
[21:57:03] [PASSED] well_known_colors
[21:57:03] [PASSED] destination_pitch
[21:57:03] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[21:57:03] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[21:57:03] [PASSED] single_pixel_source_buffer
[21:57:03] [PASSED] single_pixel_clip_rectangle
[21:57:03] [PASSED] well_known_colors
[21:57:03] [PASSED] destination_pitch
[21:57:03] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[21:57:03] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[21:57:03] [PASSED] single_pixel_source_buffer
[21:57:03] [PASSED] single_pixel_clip_rectangle
[21:57:03] [PASSED] well_known_colors
[21:57:03] [PASSED] destination_pitch
[21:57:03] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[21:57:03] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[21:57:03] [PASSED] single_pixel_source_buffer
[21:57:03] [PASSED] single_pixel_clip_rectangle
[21:57:03] [PASSED] well_known_colors
[21:57:03] [PASSED] destination_pitch
[21:57:03] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[21:57:03] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[21:57:03] [PASSED] single_pixel_source_buffer
[21:57:03] [PASSED] single_pixel_clip_rectangle
[21:57:03] [PASSED] well_known_colors
[21:57:03] [PASSED] destination_pitch
[21:57:03] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[21:57:03] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[21:57:03] [PASSED] single_pixel_source_buffer
[21:57:03] [PASSED] single_pixel_clip_rectangle
[21:57:03] [PASSED] well_known_colors
[21:57:03] [PASSED] destination_pitch
[21:57:03] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[21:57:03] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[21:57:03] [PASSED] single_pixel_source_buffer
[21:57:03] [PASSED] single_pixel_clip_rectangle
[21:57:03] [PASSED] well_known_colors
[21:57:03] [PASSED] destination_pitch
[21:57:03] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[21:57:03] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[21:57:03] [PASSED] single_pixel_source_buffer
[21:57:03] [PASSED] single_pixel_clip_rectangle
[21:57:03] [PASSED] well_known_colors
[21:57:03] [PASSED] destination_pitch
[21:57:03] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[21:57:03] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[21:57:03] [PASSED] single_pixel_source_buffer
[21:57:03] [PASSED] single_pixel_clip_rectangle
[21:57:03] [PASSED] well_known_colors
[21:57:03] [PASSED] destination_pitch
[21:57:03] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[21:57:03] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[21:57:03] [PASSED] single_pixel_source_buffer
[21:57:03] [PASSED] single_pixel_clip_rectangle
[21:57:03] [PASSED] well_known_colors
[21:57:03] [PASSED] destination_pitch
[21:57:03] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[21:57:03] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[21:57:03] [PASSED] single_pixel_source_buffer
[21:57:03] [PASSED] single_pixel_clip_rectangle
[21:57:03] [PASSED] well_known_colors
[21:57:03] [PASSED] destination_pitch
[21:57:03] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[21:57:03] ============== drm_test_fb_xrgb8888_to_mono ===============
[21:57:03] [PASSED] single_pixel_source_buffer
[21:57:03] [PASSED] single_pixel_clip_rectangle
[21:57:03] [PASSED] well_known_colors
[21:57:03] [PASSED] destination_pitch
[21:57:03] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[21:57:03] ==================== drm_test_fb_swab =====================
[21:57:03] [PASSED] single_pixel_source_buffer
[21:57:03] [PASSED] single_pixel_clip_rectangle
[21:57:03] [PASSED] well_known_colors
[21:57:03] [PASSED] destination_pitch
[21:57:03] ================ [PASSED] drm_test_fb_swab =================
[21:57:03] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[21:57:03] [PASSED] single_pixel_source_buffer
[21:57:03] [PASSED] single_pixel_clip_rectangle
[21:57:03] [PASSED] well_known_colors
[21:57:03] [PASSED] destination_pitch
[21:57:03] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[21:57:03] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[21:57:03] [PASSED] single_pixel_source_buffer
[21:57:03] [PASSED] single_pixel_clip_rectangle
[21:57:03] [PASSED] well_known_colors
[21:57:03] [PASSED] destination_pitch
[21:57:03] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[21:57:03] ================= drm_test_fb_clip_offset =================
[21:57:03] [PASSED] pass through
[21:57:03] [PASSED] horizontal offset
[21:57:03] [PASSED] vertical offset
[21:57:03] [PASSED] horizontal and vertical offset
[21:57:03] [PASSED] horizontal offset (custom pitch)
[21:57:03] [PASSED] vertical offset (custom pitch)
[21:57:03] [PASSED] horizontal and vertical offset (custom pitch)
[21:57:03] ============= [PASSED] drm_test_fb_clip_offset =============
[21:57:03] =================== drm_test_fb_memcpy ====================
[21:57:03] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[21:57:03] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[21:57:03] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[21:57:03] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[21:57:03] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[21:57:03] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[21:57:03] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[21:57:03] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[21:57:03] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[21:57:03] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[21:57:03] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[21:57:03] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[21:57:03] =============== [PASSED] drm_test_fb_memcpy ================
[21:57:03] ============= [PASSED] drm_format_helper_test ==============
[21:57:03] ================= drm_format (18 subtests) =================
[21:57:03] [PASSED] drm_test_format_block_width_invalid
[21:57:03] [PASSED] drm_test_format_block_width_one_plane
[21:57:03] [PASSED] drm_test_format_block_width_two_plane
[21:57:03] [PASSED] drm_test_format_block_width_three_plane
[21:57:03] [PASSED] drm_test_format_block_width_tiled
[21:57:03] [PASSED] drm_test_format_block_height_invalid
[21:57:03] [PASSED] drm_test_format_block_height_one_plane
[21:57:03] [PASSED] drm_test_format_block_height_two_plane
[21:57:03] [PASSED] drm_test_format_block_height_three_plane
[21:57:03] [PASSED] drm_test_format_block_height_tiled
[21:57:03] [PASSED] drm_test_format_min_pitch_invalid
[21:57:03] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[21:57:03] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[21:57:03] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[21:57:03] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[21:57:03] [PASSED] drm_test_format_min_pitch_two_plane
[21:57:03] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[21:57:03] [PASSED] drm_test_format_min_pitch_tiled
[21:57:03] =================== [PASSED] drm_format ====================
[21:57:03] ============== drm_framebuffer (10 subtests) ===============
[21:57:03] ========== drm_test_framebuffer_check_src_coords ==========
[21:57:03] [PASSED] Success: source fits into fb
[21:57:03] [PASSED] Fail: overflowing fb with x-axis coordinate
[21:57:03] [PASSED] Fail: overflowing fb with y-axis coordinate
[21:57:03] [PASSED] Fail: overflowing fb with source width
[21:57:03] [PASSED] Fail: overflowing fb with source height
[21:57:03] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[21:57:03] [PASSED] drm_test_framebuffer_cleanup
[21:57:03] =============== drm_test_framebuffer_create ===============
[21:57:03] [PASSED] ABGR8888 normal sizes
[21:57:03] [PASSED] ABGR8888 max sizes
[21:57:03] [PASSED] ABGR8888 pitch greater than min required
[21:57:03] [PASSED] ABGR8888 pitch less than min required
[21:57:03] [PASSED] ABGR8888 Invalid width
[21:57:03] [PASSED] ABGR8888 Invalid buffer handle
[21:57:03] [PASSED] No pixel format
[21:57:03] [PASSED] ABGR8888 Width 0
[21:57:03] [PASSED] ABGR8888 Height 0
[21:57:03] [PASSED] ABGR8888 Out of bound height * pitch combination
[21:57:03] [PASSED] ABGR8888 Large buffer offset
[21:57:03] [PASSED] ABGR8888 Buffer offset for inexistent plane
[21:57:03] [PASSED] ABGR8888 Invalid flag
[21:57:03] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[21:57:03] [PASSED] ABGR8888 Valid buffer modifier
[21:57:03] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[21:57:03] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[21:57:03] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[21:57:03] [PASSED] NV12 Normal sizes
[21:57:03] [PASSED] NV12 Max sizes
[21:57:03] [PASSED] NV12 Invalid pitch
[21:57:03] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[21:57:03] [PASSED] NV12 different modifier per-plane
[21:57:03] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[21:57:03] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[21:57:03] [PASSED] NV12 Modifier for inexistent plane
[21:57:03] [PASSED] NV12 Handle for inexistent plane
[21:57:03] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[21:57:03] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[21:57:03] [PASSED] YVU420 Normal sizes
[21:57:03] [PASSED] YVU420 Max sizes
[21:57:03] [PASSED] YVU420 Invalid pitch
[21:57:03] [PASSED] YVU420 Different pitches
[21:57:03] [PASSED] YVU420 Different buffer offsets/pitches
[21:57:03] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[21:57:03] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[21:57:03] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[21:57:03] [PASSED] YVU420 Valid modifier
[21:57:03] [PASSED] YVU420 Different modifiers per plane
[21:57:03] [PASSED] YVU420 Modifier for inexistent plane
[21:57:03] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[21:57:03] [PASSED] X0L2 Normal sizes
[21:57:03] [PASSED] X0L2 Max sizes
[21:57:03] [PASSED] X0L2 Invalid pitch
[21:57:03] [PASSED] X0L2 Pitch greater than minimum required
[21:57:03] [PASSED] X0L2 Handle for inexistent plane
[21:57:03] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[21:57:03] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[21:57:03] [PASSED] X0L2 Valid modifier
[21:57:03] [PASSED] X0L2 Modifier for inexistent plane
[21:57:03] =========== [PASSED] drm_test_framebuffer_create ===========
[21:57:03] [PASSED] drm_test_framebuffer_free
[21:57:03] [PASSED] drm_test_framebuffer_init
[21:57:03] [PASSED] drm_test_framebuffer_init_bad_format
[21:57:03] [PASSED] drm_test_framebuffer_init_dev_mismatch
[21:57:03] [PASSED] drm_test_framebuffer_lookup
[21:57:03] [PASSED] drm_test_framebuffer_lookup_inexistent
[21:57:03] [PASSED] drm_test_framebuffer_modifiers_not_supported
[21:57:03] ================= [PASSED] drm_framebuffer =================
[21:57:03] ================ drm_gem_shmem (8 subtests) ================
[21:57:03] [PASSED] drm_gem_shmem_test_obj_create
[21:57:03] [PASSED] drm_gem_shmem_test_obj_create_private
[21:57:03] [PASSED] drm_gem_shmem_test_pin_pages
[21:57:03] [PASSED] drm_gem_shmem_test_vmap
[21:57:03] [PASSED] drm_gem_shmem_test_get_pages_sgt
[21:57:03] [PASSED] drm_gem_shmem_test_get_sg_table
[21:57:03] [PASSED] drm_gem_shmem_test_madvise
[21:57:03] [PASSED] drm_gem_shmem_test_purge
[21:57:03] ================== [PASSED] drm_gem_shmem ==================
[21:57:03] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[21:57:03] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[21:57:03] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[21:57:03] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[21:57:03] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[21:57:03] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[21:57:03] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[21:57:03] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[21:57:03] [PASSED] Automatic
[21:57:03] [PASSED] Full
[21:57:03] [PASSED] Limited 16:235
[21:57:03] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[21:57:03] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[21:57:03] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[21:57:03] [PASSED] drm_test_check_disable_connector
[21:57:03] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[21:57:03] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[21:57:03] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[21:57:03] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[21:57:03] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[21:57:03] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[21:57:03] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[21:57:03] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[21:57:03] [PASSED] drm_test_check_output_bpc_dvi
[21:57:03] [PASSED] drm_test_check_output_bpc_format_vic_1
[21:57:03] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[21:57:03] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[21:57:03] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[21:57:03] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[21:57:03] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[21:57:03] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[21:57:03] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[21:57:03] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[21:57:03] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[21:57:03] [PASSED] drm_test_check_broadcast_rgb_value
[21:57:03] [PASSED] drm_test_check_bpc_8_value
[21:57:03] [PASSED] drm_test_check_bpc_10_value
[21:57:03] [PASSED] drm_test_check_bpc_12_value
[21:57:03] [PASSED] drm_test_check_format_value
[21:57:03] [PASSED] drm_test_check_tmds_char_value
[21:57:03] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[21:57:03] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[21:57:03] [PASSED] drm_test_check_mode_valid
[21:57:03] [PASSED] drm_test_check_mode_valid_reject
[21:57:03] [PASSED] drm_test_check_mode_valid_reject_rate
[21:57:03] [PASSED] drm_test_check_mode_valid_reject_max_clock
[21:57:03] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[21:57:03] ================= drm_managed (2 subtests) =================
[21:57:03] [PASSED] drm_test_managed_release_action
[21:57:03] [PASSED] drm_test_managed_run_action
[21:57:03] =================== [PASSED] drm_managed ===================
[21:57:03] =================== drm_mm (6 subtests) ====================
[21:57:03] [PASSED] drm_test_mm_init
[21:57:03] [PASSED] drm_test_mm_debug
[21:57:03] [PASSED] drm_test_mm_align32
[21:57:03] [PASSED] drm_test_mm_align64
[21:57:03] [PASSED] drm_test_mm_lowest
[21:57:03] [PASSED] drm_test_mm_highest
[21:57:03] ===================== [PASSED] drm_mm ======================
[21:57:03] ============= drm_modes_analog_tv (5 subtests) =============
[21:57:03] [PASSED] drm_test_modes_analog_tv_mono_576i
[21:57:03] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[21:57:03] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[21:57:03] [PASSED] drm_test_modes_analog_tv_pal_576i
[21:57:03] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[21:57:03] =============== [PASSED] drm_modes_analog_tv ===============
[21:57:03] ============== drm_plane_helper (2 subtests) ===============
[21:57:03] =============== drm_test_check_plane_state ================
[21:57:03] [PASSED] clipping_simple
[21:57:03] [PASSED] clipping_rotate_reflect
[21:57:03] [PASSED] positioning_simple
[21:57:03] [PASSED] upscaling
[21:57:03] [PASSED] downscaling
[21:57:03] [PASSED] rounding1
[21:57:03] [PASSED] rounding2
[21:57:03] [PASSED] rounding3
[21:57:03] [PASSED] rounding4
[21:57:03] =========== [PASSED] drm_test_check_plane_state ============
[21:57:03] =========== drm_test_check_invalid_plane_state ============
[21:57:03] [PASSED] positioning_invalid
[21:57:03] [PASSED] upscaling_invalid
[21:57:03] [PASSED] downscaling_invalid
[21:57:03] ======= [PASSED] drm_test_check_invalid_plane_state ========
[21:57:03] ================ [PASSED] drm_plane_helper =================
[21:57:03] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[21:57:03] ====== drm_test_connector_helper_tv_get_modes_check =======
[21:57:03] [PASSED] None
[21:57:03] [PASSED] PAL
[21:57:03] [PASSED] NTSC
[21:57:03] [PASSED] Both, NTSC Default
[21:57:03] [PASSED] Both, PAL Default
[21:57:03] [PASSED] Both, NTSC Default, with PAL on command-line
[21:57:03] [PASSED] Both, PAL Default, with NTSC on command-line
[21:57:03] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[21:57:03] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[21:57:03] ================== drm_rect (9 subtests) ===================
[21:57:03] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[21:57:03] [PASSED] drm_test_rect_clip_scaled_not_clipped
[21:57:03] [PASSED] drm_test_rect_clip_scaled_clipped
[21:57:03] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[21:57:03] ================= drm_test_rect_intersect =================
[21:57:03] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[21:57:03] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[21:57:03] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[21:57:03] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[21:57:03] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[21:57:03] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[21:57:03] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[21:57:03] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[21:57:03] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[21:57:03] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[21:57:03] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[21:57:03] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[21:57:03] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[21:57:03] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[21:57:03] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[21:57:03] ============= [PASSED] drm_test_rect_intersect =============
[21:57:03] ================ drm_test_rect_calc_hscale ================
[21:57:03] [PASSED] normal use
[21:57:03] [PASSED] out of max range
[21:57:03] [PASSED] out of min range
[21:57:03] [PASSED] zero dst
[21:57:03] [PASSED] negative src
[21:57:03] [PASSED] negative dst
[21:57:03] ============ [PASSED] drm_test_rect_calc_hscale ============
[21:57:03] ================ drm_test_rect_calc_vscale ================
[21:57:03] [PASSED] normal use
[21:57:03] [PASSED] out of max range
[21:57:03] [PASSED] out of min range
[21:57:03] [PASSED] zero dst
[21:57:03] [PASSED] negative src
stty: 'standard input': Inappropriate ioctl for device
[21:57:03] [PASSED] negative dst
[21:57:03] ============ [PASSED] drm_test_rect_calc_vscale ============
[21:57:03] ================== drm_test_rect_rotate ===================
[21:57:03] [PASSED] reflect-x
[21:57:03] [PASSED] reflect-y
[21:57:03] [PASSED] rotate-0
[21:57:03] [PASSED] rotate-90
[21:57:03] [PASSED] rotate-180
[21:57:03] [PASSED] rotate-270
[21:57:03] ============== [PASSED] drm_test_rect_rotate ===============
[21:57:03] ================ drm_test_rect_rotate_inv =================
[21:57:03] [PASSED] reflect-x
[21:57:03] [PASSED] reflect-y
[21:57:03] [PASSED] rotate-0
[21:57:03] [PASSED] rotate-90
[21:57:03] [PASSED] rotate-180
[21:57:03] [PASSED] rotate-270
[21:57:03] ============ [PASSED] drm_test_rect_rotate_inv =============
[21:57:03] ==================== [PASSED] drm_rect =====================
[21:57:03] ============ drm_sysfb_modeset_test (1 subtest) ============
[21:57:03] ============ drm_test_sysfb_build_fourcc_list =============
[21:57:03] [PASSED] no native formats
[21:57:03] [PASSED] XRGB8888 as native format
[21:57:03] [PASSED] remove duplicates
[21:57:03] [PASSED] convert alpha formats
[21:57:03] [PASSED] random formats
[21:57:03] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[21:57:03] ============= [PASSED] drm_sysfb_modeset_test ==============
[21:57:03] ============================================================
[21:57:03] Testing complete. Ran 621 tests: passed: 621
[21:57:03] Elapsed time: 25.299s total, 1.712s configuring, 23.365s building, 0.207s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[21:57:04] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:57:05] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[21:57:14] Starting KUnit Kernel (1/1)...
[21:57:14] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:57:14] ================= ttm_device (5 subtests) ==================
[21:57:14] [PASSED] ttm_device_init_basic
[21:57:14] [PASSED] ttm_device_init_multiple
[21:57:14] [PASSED] ttm_device_fini_basic
[21:57:14] [PASSED] ttm_device_init_no_vma_man
[21:57:14] ================== ttm_device_init_pools ==================
[21:57:14] [PASSED] No DMA allocations, no DMA32 required
[21:57:14] [PASSED] DMA allocations, DMA32 required
[21:57:14] [PASSED] No DMA allocations, DMA32 required
[21:57:14] [PASSED] DMA allocations, no DMA32 required
[21:57:14] ============== [PASSED] ttm_device_init_pools ==============
[21:57:14] =================== [PASSED] ttm_device ====================
[21:57:14] ================== ttm_pool (8 subtests) ===================
[21:57:14] ================== ttm_pool_alloc_basic ===================
[21:57:14] [PASSED] One page
[21:57:14] [PASSED] More than one page
[21:57:14] [PASSED] Above the allocation limit
[21:57:14] [PASSED] One page, with coherent DMA mappings enabled
[21:57:14] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[21:57:14] ============== [PASSED] ttm_pool_alloc_basic ===============
[21:57:14] ============== ttm_pool_alloc_basic_dma_addr ==============
[21:57:14] [PASSED] One page
[21:57:14] [PASSED] More than one page
[21:57:14] [PASSED] Above the allocation limit
[21:57:14] [PASSED] One page, with coherent DMA mappings enabled
[21:57:14] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[21:57:14] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[21:57:14] [PASSED] ttm_pool_alloc_order_caching_match
[21:57:14] [PASSED] ttm_pool_alloc_caching_mismatch
[21:57:14] [PASSED] ttm_pool_alloc_order_mismatch
[21:57:14] [PASSED] ttm_pool_free_dma_alloc
[21:57:14] [PASSED] ttm_pool_free_no_dma_alloc
[21:57:14] [PASSED] ttm_pool_fini_basic
[21:57:14] ==================== [PASSED] ttm_pool =====================
[21:57:14] ================ ttm_resource (8 subtests) =================
[21:57:14] ================= ttm_resource_init_basic =================
[21:57:14] [PASSED] Init resource in TTM_PL_SYSTEM
[21:57:14] [PASSED] Init resource in TTM_PL_VRAM
[21:57:14] [PASSED] Init resource in a private placement
[21:57:14] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[21:57:14] ============= [PASSED] ttm_resource_init_basic =============
[21:57:14] [PASSED] ttm_resource_init_pinned
[21:57:14] [PASSED] ttm_resource_fini_basic
[21:57:14] [PASSED] ttm_resource_manager_init_basic
[21:57:14] [PASSED] ttm_resource_manager_usage_basic
[21:57:14] [PASSED] ttm_resource_manager_set_used_basic
[21:57:14] [PASSED] ttm_sys_man_alloc_basic
[21:57:14] [PASSED] ttm_sys_man_free_basic
[21:57:14] ================== [PASSED] ttm_resource ===================
[21:57:14] =================== ttm_tt (15 subtests) ===================
[21:57:14] ==================== ttm_tt_init_basic ====================
[21:57:14] [PASSED] Page-aligned size
[21:57:14] [PASSED] Extra pages requested
[21:57:14] ================ [PASSED] ttm_tt_init_basic ================
[21:57:14] [PASSED] ttm_tt_init_misaligned
[21:57:14] [PASSED] ttm_tt_fini_basic
[21:57:14] [PASSED] ttm_tt_fini_sg
[21:57:14] [PASSED] ttm_tt_fini_shmem
[21:57:14] [PASSED] ttm_tt_create_basic
[21:57:14] [PASSED] ttm_tt_create_invalid_bo_type
[21:57:14] [PASSED] ttm_tt_create_ttm_exists
[21:57:14] [PASSED] ttm_tt_create_failed
[21:57:14] [PASSED] ttm_tt_destroy_basic
[21:57:14] [PASSED] ttm_tt_populate_null_ttm
[21:57:14] [PASSED] ttm_tt_populate_populated_ttm
[21:57:14] [PASSED] ttm_tt_unpopulate_basic
[21:57:14] [PASSED] ttm_tt_unpopulate_empty_ttm
[21:57:14] [PASSED] ttm_tt_swapin_basic
[21:57:14] ===================== [PASSED] ttm_tt ======================
[21:57:14] =================== ttm_bo (14 subtests) ===================
[21:57:14] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[21:57:14] [PASSED] Cannot be interrupted and sleeps
[21:57:14] [PASSED] Cannot be interrupted, locks straight away
[21:57:14] [PASSED] Can be interrupted, sleeps
[21:57:14] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[21:57:14] [PASSED] ttm_bo_reserve_locked_no_sleep
[21:57:14] [PASSED] ttm_bo_reserve_no_wait_ticket
[21:57:14] [PASSED] ttm_bo_reserve_double_resv
[21:57:14] [PASSED] ttm_bo_reserve_interrupted
[21:57:14] [PASSED] ttm_bo_reserve_deadlock
[21:57:14] [PASSED] ttm_bo_unreserve_basic
[21:57:14] [PASSED] ttm_bo_unreserve_pinned
[21:57:14] [PASSED] ttm_bo_unreserve_bulk
[21:57:14] [PASSED] ttm_bo_fini_basic
[21:57:14] [PASSED] ttm_bo_fini_shared_resv
[21:57:14] [PASSED] ttm_bo_pin_basic
[21:57:14] [PASSED] ttm_bo_pin_unpin_resource
[21:57:14] [PASSED] ttm_bo_multiple_pin_one_unpin
[21:57:14] ===================== [PASSED] ttm_bo ======================
[21:57:14] ============== ttm_bo_validate (21 subtests) ===============
[21:57:14] ============== ttm_bo_init_reserved_sys_man ===============
[21:57:14] [PASSED] Buffer object for userspace
[21:57:14] [PASSED] Kernel buffer object
[21:57:14] [PASSED] Shared buffer object
[21:57:14] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[21:57:14] ============== ttm_bo_init_reserved_mock_man ==============
[21:57:14] [PASSED] Buffer object for userspace
[21:57:14] [PASSED] Kernel buffer object
[21:57:14] [PASSED] Shared buffer object
[21:57:14] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[21:57:14] [PASSED] ttm_bo_init_reserved_resv
[21:57:14] ================== ttm_bo_validate_basic ==================
[21:57:14] [PASSED] Buffer object for userspace
[21:57:14] [PASSED] Kernel buffer object
[21:57:14] [PASSED] Shared buffer object
[21:57:14] ============== [PASSED] ttm_bo_validate_basic ==============
[21:57:14] [PASSED] ttm_bo_validate_invalid_placement
[21:57:14] ============= ttm_bo_validate_same_placement ==============
[21:57:14] [PASSED] System manager
[21:57:14] [PASSED] VRAM manager
[21:57:14] ========= [PASSED] ttm_bo_validate_same_placement ==========
[21:57:15] [PASSED] ttm_bo_validate_failed_alloc
[21:57:15] [PASSED] ttm_bo_validate_pinned
[21:57:15] [PASSED] ttm_bo_validate_busy_placement
[21:57:15] ================ ttm_bo_validate_multihop =================
[21:57:15] [PASSED] Buffer object for userspace
[21:57:15] [PASSED] Kernel buffer object
[21:57:15] [PASSED] Shared buffer object
[21:57:15] ============ [PASSED] ttm_bo_validate_multihop =============
[21:57:15] ========== ttm_bo_validate_no_placement_signaled ==========
[21:57:15] [PASSED] Buffer object in system domain, no page vector
[21:57:15] [PASSED] Buffer object in system domain with an existing page vector
[21:57:15] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[21:57:15] ======== ttm_bo_validate_no_placement_not_signaled ========
[21:57:15] [PASSED] Buffer object for userspace
[21:57:15] [PASSED] Kernel buffer object
[21:57:15] [PASSED] Shared buffer object
[21:57:15] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[21:57:15] [PASSED] ttm_bo_validate_move_fence_signaled
[21:57:15] ========= ttm_bo_validate_move_fence_not_signaled =========
[21:57:15] [PASSED] Waits for GPU
[21:57:15] [PASSED] Tries to lock straight away
[21:57:15] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[21:57:15] [PASSED] ttm_bo_validate_happy_evict
[21:57:15] [PASSED] ttm_bo_validate_all_pinned_evict
[21:57:15] [PASSED] ttm_bo_validate_allowed_only_evict
[21:57:15] [PASSED] ttm_bo_validate_deleted_evict
[21:57:15] [PASSED] ttm_bo_validate_busy_domain_evict
[21:57:15] [PASSED] ttm_bo_validate_evict_gutting
[21:57:15] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[21:57:15] ================= [PASSED] ttm_bo_validate =================
[21:57:15] ============================================================
[21:57:15] Testing complete. Ran 101 tests: passed: 101
[21:57:15] Elapsed time: 11.076s total, 1.721s configuring, 9.138s building, 0.181s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 25+ messages in thread
* ✓ Xe.CI.BAT: success for drm/i915/dp: Work around a DSC pixel throughput issue (rev5)
2025-09-26 21:12 [PATCH v4 0/6] drm/i915/dp: Work around a DSC pixel throughput issue Imre Deak
` (7 preceding siblings ...)
2025-09-26 21:57 ` ✓ CI.KUnit: success " Patchwork
@ 2025-09-26 22:33 ` Patchwork
2025-09-27 5:36 ` ✗ Xe.CI.Full: failure " Patchwork
` (5 subsequent siblings)
14 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2025-09-26 22:33 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 883 bytes --]
== Series Details ==
Series: drm/i915/dp: Work around a DSC pixel throughput issue (rev5)
URL : https://patchwork.freedesktop.org/series/154737/
State : success
== Summary ==
CI Bug Log - changes from xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412_BAT -> xe-pw-154737v5_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Changes
-------
No changes found
Build changes
-------------
* Linux: xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412 -> xe-pw-154737v5
IGT_8555: 8555
xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412: 3008c5c8e2fade05918e6d8c456572c91f30d412
xe-pw-154737v5: 154737v5
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/index.html
[-- Attachment #2: Type: text/html, Size: 1431 bytes --]
^ permalink raw reply [flat|nested] 25+ messages in thread
* ✗ Xe.CI.Full: failure for drm/i915/dp: Work around a DSC pixel throughput issue (rev5)
2025-09-26 21:12 [PATCH v4 0/6] drm/i915/dp: Work around a DSC pixel throughput issue Imre Deak
` (8 preceding siblings ...)
2025-09-26 22:33 ` ✓ Xe.CI.BAT: " Patchwork
@ 2025-09-27 5:36 ` Patchwork
2025-09-29 7:12 ` ✗ CI.checkpatch: warning for drm/i915/dp: Work around a DSC pixel throughput issue (rev6) Patchwork
` (4 subsequent siblings)
14 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2025-09-27 5:36 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 44612 bytes --]
== Series Details ==
Series: drm/i915/dp: Work around a DSC pixel throughput issue (rev5)
URL : https://patchwork.freedesktop.org/series/154737/
State : failure
== Summary ==
CI Bug Log - changes from xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412_FULL -> xe-pw-154737v5_FULL
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-154737v5_FULL absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-154737v5_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (4 -> 4)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-154737v5_FULL:
### IGT changes ###
#### Possible regressions ####
* igt@xe_pm@s3-vm-bind-prefetch:
- shard-bmg: NOTRUN -> [INCOMPLETE][1]
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-bmg-1/igt@xe_pm@s3-vm-bind-prefetch.html
Known issues
------------
Here are the changes found in xe-pw-154737v5_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_big_fb@4-tiled-32bpp-rotate-270:
- shard-dg2-set2: NOTRUN -> [SKIP][2] ([Intel XE#316]) +1 other test skip
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-dg2-464/igt@kms_big_fb@4-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
- shard-adlp: NOTRUN -> [DMESG-FAIL][3] ([Intel XE#4543])
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-adlp-6/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@y-tiled-16bpp-rotate-0:
- shard-dg2-set2: NOTRUN -> [SKIP][4] ([Intel XE#1124]) +3 other tests skip
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-dg2-463/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html
* igt@kms_big_fb@y-tiled-addfb-size-overflow:
- shard-dg2-set2: NOTRUN -> [SKIP][5] ([Intel XE#610])
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-dg2-466/igt@kms_big_fb@y-tiled-addfb-size-overflow.html
* igt@kms_bw@connected-linear-tiling-4-displays-3840x2160p:
- shard-dg2-set2: NOTRUN -> [SKIP][6] ([Intel XE#2191])
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-dg2-464/igt@kms_bw@connected-linear-tiling-4-displays-3840x2160p.html
* igt@kms_bw@linear-tiling-1-displays-2560x1440p:
- shard-dg2-set2: NOTRUN -> [SKIP][7] ([Intel XE#367])
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-dg2-463/igt@kms_bw@linear-tiling-1-displays-2560x1440p.html
* igt@kms_bw@linear-tiling-1-displays-3840x2160p:
- shard-adlp: NOTRUN -> [SKIP][8] ([Intel XE#367])
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-adlp-6/igt@kms_bw@linear-tiling-1-displays-3840x2160p.html
* igt@kms_ccs@bad-rotation-90-yf-tiled-ccs@pipe-c-dp-2:
- shard-dg2-set2: NOTRUN -> [SKIP][9] ([Intel XE#787]) +160 other tests skip
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-dg2-432/igt@kms_ccs@bad-rotation-90-yf-tiled-ccs@pipe-c-dp-2.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-d-dp-2:
- shard-dg2-set2: NOTRUN -> [SKIP][10] ([Intel XE#455] / [Intel XE#787]) +26 other tests skip
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-dg2-432/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-d-dp-2.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc:
- shard-dg2-set2: [PASS][11] -> [INCOMPLETE][12] ([Intel XE#2705] / [Intel XE#4212] / [Intel XE#4345])
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-dp-4:
- shard-dg2-set2: [PASS][13] -> [INCOMPLETE][14] ([Intel XE#2705] / [Intel XE#4212])
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-dp-4.html
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-dp-4.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-dp-4:
- shard-dg2-set2: [PASS][15] -> [INCOMPLETE][16] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4522])
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-dp-4.html
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-dp-4.html
* igt@kms_cdclk@plane-scaling@pipe-b-dp-2:
- shard-dg2-set2: NOTRUN -> [SKIP][17] ([Intel XE#4416]) +3 other tests skip
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-dg2-432/igt@kms_cdclk@plane-scaling@pipe-b-dp-2.html
* igt@kms_chamelium_color@ctm-0-25:
- shard-dg2-set2: NOTRUN -> [SKIP][18] ([Intel XE#306])
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-dg2-464/igt@kms_chamelium_color@ctm-0-25.html
* igt@kms_chamelium_color@ctm-negative:
- shard-adlp: NOTRUN -> [SKIP][19] ([Intel XE#306])
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-adlp-6/igt@kms_chamelium_color@ctm-negative.html
* igt@kms_chamelium_frames@hdmi-aspect-ratio:
- shard-adlp: NOTRUN -> [SKIP][20] ([Intel XE#373]) +1 other test skip
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-adlp-6/igt@kms_chamelium_frames@hdmi-aspect-ratio.html
* igt@kms_chamelium_hpd@dp-hpd:
- shard-dg2-set2: NOTRUN -> [SKIP][21] ([Intel XE#373]) +4 other tests skip
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-dg2-464/igt@kms_chamelium_hpd@dp-hpd.html
* igt@kms_content_protection@dp-mst-lic-type-0:
- shard-dg2-set2: NOTRUN -> [SKIP][22] ([Intel XE#307])
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-dg2-463/igt@kms_content_protection@dp-mst-lic-type-0.html
* igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic:
- shard-adlp: NOTRUN -> [SKIP][23] ([Intel XE#309])
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-adlp-1/igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-legacy:
- shard-bmg: [PASS][24] -> [SKIP][25] ([Intel XE#2291])
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-bmg-5/igt@kms_cursor_legacy@cursorb-vs-flipb-legacy.html
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipb-legacy.html
* igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area:
- shard-dg2-set2: NOTRUN -> [SKIP][26] ([Intel XE#4422])
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-dg2-466/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area.html
* igt@kms_flip@2x-nonexisting-fb:
- shard-bmg: [PASS][27] -> [SKIP][28] ([Intel XE#2316]) +6 other tests skip
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-bmg-5/igt@kms_flip@2x-nonexisting-fb.html
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-bmg-6/igt@kms_flip@2x-nonexisting-fb.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-lnl: [PASS][29] -> [FAIL][30] ([Intel XE#301])
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
* igt@kms_flip@flip-vs-rmfb-interruptible:
- shard-adlp: [PASS][31] -> [DMESG-WARN][32] ([Intel XE#4543] / [Intel XE#5208])
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-adlp-2/igt@kms_flip@flip-vs-rmfb-interruptible.html
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-adlp-1/igt@kms_flip@flip-vs-rmfb-interruptible.html
* igt@kms_flip@flip-vs-rmfb-interruptible@b-hdmi-a1:
- shard-adlp: [PASS][33] -> [DMESG-WARN][34] ([Intel XE#4543]) +4 other tests dmesg-warn
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-adlp-2/igt@kms_flip@flip-vs-rmfb-interruptible@b-hdmi-a1.html
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-adlp-1/igt@kms_flip@flip-vs-rmfb-interruptible@b-hdmi-a1.html
* igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-x-to-x:
- shard-adlp: [PASS][35] -> [DMESG-FAIL][36] ([Intel XE#4543])
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-adlp-3/igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-x-to-x.html
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-adlp-4/igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-x-to-x.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-blt:
- shard-adlp: NOTRUN -> [SKIP][37] ([Intel XE#656]) +2 other tests skip
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-adlp-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-plflip-blt:
- shard-dg2-set2: NOTRUN -> [SKIP][38] ([Intel XE#651]) +15 other tests skip
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-dg2-463/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-render:
- shard-adlp: NOTRUN -> [SKIP][39] ([Intel XE#651]) +2 other tests skip
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-adlp-1/igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc:
- shard-adlp: NOTRUN -> [SKIP][40] ([Intel XE#653]) +4 other tests skip
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-adlp-1/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt:
- shard-dg2-set2: NOTRUN -> [SKIP][41] ([Intel XE#653]) +16 other tests skip
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-dg2-466/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt.html
* igt@kms_hdr@brightness-with-hdr:
- shard-dg2-set2: NOTRUN -> [SKIP][42] ([Intel XE#455]) +7 other tests skip
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-dg2-463/igt@kms_hdr@brightness-with-hdr.html
* igt@kms_hdr@invalid-hdr:
- shard-dg2-set2: [PASS][43] -> [SKIP][44] ([Intel XE#455])
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-dg2-463/igt@kms_hdr@invalid-hdr.html
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-dg2-435/igt@kms_hdr@invalid-hdr.html
* igt@kms_joiner@invalid-modeset-force-big-joiner:
- shard-adlp: NOTRUN -> [SKIP][45] ([Intel XE#3012])
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-adlp-1/igt@kms_joiner@invalid-modeset-force-big-joiner.html
* igt@kms_lease@setcrtc-implicit-plane:
- shard-adlp: [PASS][46] -> [DMESG-WARN][47] ([Intel XE#2953] / [Intel XE#4173]) +3 other tests dmesg-warn
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-adlp-8/igt@kms_lease@setcrtc-implicit-plane.html
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-adlp-4/igt@kms_lease@setcrtc-implicit-plane.html
* igt@kms_pm_backlight@brightness-with-dpms:
- shard-dg2-set2: NOTRUN -> [SKIP][48] ([Intel XE#2938])
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-dg2-464/igt@kms_pm_backlight@brightness-with-dpms.html
* igt@kms_pm_dc@dc6-psr:
- shard-dg2-set2: NOTRUN -> [SKIP][49] ([Intel XE#1129])
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-dg2-463/igt@kms_pm_dc@dc6-psr.html
* igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-fully-sf:
- shard-dg2-set2: NOTRUN -> [SKIP][50] ([Intel XE#1406] / [Intel XE#1489]) +4 other tests skip
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-dg2-463/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@pr-overlay-plane-move-continuous-sf:
- shard-adlp: NOTRUN -> [SKIP][51] ([Intel XE#1406] / [Intel XE#1489]) +2 other tests skip
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-adlp-1/igt@kms_psr2_sf@pr-overlay-plane-move-continuous-sf.html
* igt@kms_psr@fbc-psr-primary-blt:
- shard-adlp: NOTRUN -> [SKIP][52] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) +1 other test skip
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-adlp-6/igt@kms_psr@fbc-psr-primary-blt.html
* igt@kms_psr@fbc-psr2-sprite-plane-onoff:
- shard-dg2-set2: NOTRUN -> [SKIP][53] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) +5 other tests skip
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-dg2-464/igt@kms_psr@fbc-psr2-sprite-plane-onoff.html
* igt@kms_psr@pr-sprite-blt:
- shard-bmg: NOTRUN -> [SKIP][54] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850])
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-bmg-1/igt@kms_psr@pr-sprite-blt.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- shard-adlp: NOTRUN -> [SKIP][55] ([Intel XE#1406] / [Intel XE#2939] / [Intel XE#5585])
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-adlp-1/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
- shard-dg2-set2: NOTRUN -> [SKIP][56] ([Intel XE#1406] / [Intel XE#2939])
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-dg2-466/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
* igt@kms_setmode@basic-clone-single-crtc:
- shard-adlp: NOTRUN -> [SKIP][57] ([Intel XE#455]) +1 other test skip
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-adlp-6/igt@kms_setmode@basic-clone-single-crtc.html
* igt@kms_setmode@invalid-clone-single-crtc:
- shard-bmg: [PASS][58] -> [SKIP][59] ([Intel XE#1435])
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-bmg-4/igt@kms_setmode@invalid-clone-single-crtc.html
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-bmg-6/igt@kms_setmode@invalid-clone-single-crtc.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-adlp: NOTRUN -> [SKIP][60] ([Intel XE#362])
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-adlp-1/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
- shard-dg2-set2: NOTRUN -> [SKIP][61] ([Intel XE#1500])
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-dg2-466/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@kms_tv_load_detect@load-detect:
- shard-dg2-set2: NOTRUN -> [SKIP][62] ([Intel XE#330])
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-dg2-464/igt@kms_tv_load_detect@load-detect.html
* igt@xe_compute_preempt@compute-preempt:
- shard-adlp: NOTRUN -> [SKIP][63] ([Intel XE#455] / [Intel XE#5632])
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-adlp-6/igt@xe_compute_preempt@compute-preempt.html
* igt@xe_compute_preempt@compute-preempt-many:
- shard-dg2-set2: NOTRUN -> [FAIL][64] ([Intel XE#5890]) +1 other test fail
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-dg2-464/igt@xe_compute_preempt@compute-preempt-many.html
* igt@xe_eudebug@basic-vm-access-parameters-userptr-faultable:
- shard-dg2-set2: NOTRUN -> [SKIP][65] ([Intel XE#4837]) +2 other tests skip
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-dg2-463/igt@xe_eudebug@basic-vm-access-parameters-userptr-faultable.html
* igt@xe_evict@evict-beng-large:
- shard-adlp: NOTRUN -> [SKIP][66] ([Intel XE#261] / [Intel XE#5564])
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-adlp-1/igt@xe_evict@evict-beng-large.html
* igt@xe_exec_basic@multigpu-many-execqueues-many-vm-rebind:
- shard-adlp: NOTRUN -> [SKIP][67] ([Intel XE#1392] / [Intel XE#5575])
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-adlp-1/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-rebind.html
* igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate-race:
- shard-dg2-set2: [PASS][68] -> [SKIP][69] ([Intel XE#1392]) +6 other tests skip
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-dg2-434/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate-race.html
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-dg2-432/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate-race.html
* igt@xe_exec_fault_mode@many-execqueues-userptr-invalidate-race:
- shard-adlp: NOTRUN -> [SKIP][70] ([Intel XE#288] / [Intel XE#5561]) +2 other tests skip
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-adlp-1/igt@xe_exec_fault_mode@many-execqueues-userptr-invalidate-race.html
* igt@xe_exec_fault_mode@once-rebind-imm:
- shard-dg2-set2: NOTRUN -> [SKIP][71] ([Intel XE#288]) +13 other tests skip
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-dg2-463/igt@xe_exec_fault_mode@once-rebind-imm.html
* igt@xe_exec_system_allocator@many-new-bo-map:
- shard-adlp: NOTRUN -> [SKIP][72] ([Intel XE#4915]) +31 other tests skip
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-adlp-6/igt@xe_exec_system_allocator@many-new-bo-map.html
* igt@xe_exec_system_allocator@threads-shared-vm-many-stride-new-race-nomemset:
- shard-dg2-set2: NOTRUN -> [SKIP][73] ([Intel XE#4915]) +124 other tests skip
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-dg2-466/igt@xe_exec_system_allocator@threads-shared-vm-many-stride-new-race-nomemset.html
* igt@xe_mmap@pci-membarrier-bad-object:
- shard-adlp: NOTRUN -> [SKIP][74] ([Intel XE#5100])
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-adlp-1/igt@xe_mmap@pci-membarrier-bad-object.html
* igt@xe_mmap@small-bar:
- shard-dg2-set2: NOTRUN -> [SKIP][75] ([Intel XE#512])
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-dg2-463/igt@xe_mmap@small-bar.html
* igt@xe_oa@polling-small-buf:
- shard-dg2-set2: NOTRUN -> [SKIP][76] ([Intel XE#3573]) +3 other tests skip
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-dg2-463/igt@xe_oa@polling-small-buf.html
* igt@xe_pm@s4-d3cold-basic-exec:
- shard-dg2-set2: NOTRUN -> [SKIP][77] ([Intel XE#2284] / [Intel XE#366])
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-dg2-464/igt@xe_pm@s4-d3cold-basic-exec.html
* igt@xe_pxp@pxp-src-to-pxp-dest-rendercopy:
- shard-adlp: NOTRUN -> [SKIP][78] ([Intel XE#4733] / [Intel XE#5594])
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-adlp-1/igt@xe_pxp@pxp-src-to-pxp-dest-rendercopy.html
- shard-dg2-set2: NOTRUN -> [SKIP][79] ([Intel XE#4733]) +1 other test skip
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-dg2-466/igt@xe_pxp@pxp-src-to-pxp-dest-rendercopy.html
* igt@xe_query@multigpu-query-engines:
- shard-dg2-set2: NOTRUN -> [SKIP][80] ([Intel XE#944]) +2 other tests skip
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-dg2-464/igt@xe_query@multigpu-query-engines.html
* igt@xe_sriov_auto_provisioning@resources-released-on-vfs-disabling:
- shard-dg2-set2: NOTRUN -> [SKIP][81] ([Intel XE#4130])
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-dg2-464/igt@xe_sriov_auto_provisioning@resources-released-on-vfs-disabling.html
* igt@xe_sriov_scheduling@equal-throughput:
- shard-dg2-set2: NOTRUN -> [SKIP][82] ([Intel XE#4351])
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-dg2-463/igt@xe_sriov_scheduling@equal-throughput.html
#### Possible fixes ####
* igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
- shard-bmg: [INCOMPLETE][83] ([Intel XE#3862]) -> [PASS][84] +1 other test pass
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-bmg-5/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-bmg-1/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs:
- shard-dg2-set2: [INCOMPLETE][85] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4345]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-6:
- shard-dg2-set2: [INCOMPLETE][87] ([Intel XE#1727] / [Intel XE#3113]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-6.html
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-6.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size:
- shard-bmg: [SKIP][89] ([Intel XE#2291]) -> [PASS][90]
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-bmg-7/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-bmg: [FAIL][91] ([Intel XE#1475]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-bmg-7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-bmg-4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_dp_aux_dev:
- shard-bmg: [SKIP][93] ([Intel XE#3009]) -> [PASS][94]
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-bmg-6/igt@kms_dp_aux_dev.html
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-bmg-7/igt@kms_dp_aux_dev.html
* igt@kms_flip@2x-modeset-vs-vblank-race-interruptible:
- shard-bmg: [SKIP][95] ([Intel XE#2316]) -> [PASS][96] +2 other tests pass
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-bmg-6/igt@kms_flip@2x-modeset-vs-vblank-race-interruptible.html
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-bmg-3/igt@kms_flip@2x-modeset-vs-vblank-race-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
- shard-lnl: [FAIL][97] ([Intel XE#301]) -> [PASS][98]
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@d-hdmi-a1:
- shard-adlp: [DMESG-WARN][99] ([Intel XE#4543]) -> [PASS][100] +11 other tests pass
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-adlp-1/igt@kms_flip@flip-vs-expired-vblank-interruptible@d-hdmi-a1.html
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-adlp-3/igt@kms_flip@flip-vs-expired-vblank-interruptible@d-hdmi-a1.html
* igt@kms_flip@flip-vs-suspend@b-hdmi-a1:
- shard-adlp: [DMESG-WARN][101] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][102] +2 other tests pass
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-adlp-1/igt@kms_flip@flip-vs-suspend@b-hdmi-a1.html
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-adlp-3/igt@kms_flip@flip-vs-suspend@b-hdmi-a1.html
* igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-x-to-y:
- shard-adlp: [FAIL][103] ([Intel XE#1874]) -> [PASS][104]
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-adlp-3/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-x-to-y.html
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-adlp-4/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-x-to-y.html
* igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-to-x:
- shard-adlp: [DMESG-FAIL][105] ([Intel XE#4543]) -> [PASS][106]
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-adlp-3/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-to-x.html
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-adlp-4/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-to-x.html
* igt@kms_hdr@invalid-hdr:
- shard-bmg: [SKIP][107] ([Intel XE#1503]) -> [PASS][108]
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-bmg-5/igt@kms_hdr@invalid-hdr.html
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-bmg-6/igt@kms_hdr@invalid-hdr.html
* igt@kms_plane_alpha_blend@constant-alpha-mid@pipe-a-hdmi-a-6:
- shard-dg2-set2: [INCOMPLETE][109] -> [PASS][110] +1 other test pass
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-dg2-464/igt@kms_plane_alpha_blend@constant-alpha-mid@pipe-a-hdmi-a-6.html
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-dg2-464/igt@kms_plane_alpha_blend@constant-alpha-mid@pipe-a-hdmi-a-6.html
* igt@kms_plane_multiple@2x-tiling-x:
- shard-bmg: [SKIP][111] ([Intel XE#4596]) -> [PASS][112]
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-bmg-6/igt@kms_plane_multiple@2x-tiling-x.html
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-bmg-7/igt@kms_plane_multiple@2x-tiling-x.html
* igt@kms_setmode@basic@pipe-a-dp-4:
- shard-dg2-set2: [FAIL][113] ([Intel XE#2883]) -> [PASS][114]
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-dg2-466/igt@kms_setmode@basic@pipe-a-dp-4.html
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-dg2-434/igt@kms_setmode@basic@pipe-a-dp-4.html
* igt@kms_setmode@basic@pipe-b-dp-2-pipe-a-hdmi-a-3:
- shard-bmg: [FAIL][115] ([Intel XE#2883]) -> [PASS][116] +1 other test pass
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-bmg-3/igt@kms_setmode@basic@pipe-b-dp-2-pipe-a-hdmi-a-3.html
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-bmg-7/igt@kms_setmode@basic@pipe-b-dp-2-pipe-a-hdmi-a-3.html
* igt@kms_vrr@max-min:
- shard-lnl: [FAIL][117] ([Intel XE#4227]) -> [PASS][118] +1 other test pass
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-lnl-1/igt@kms_vrr@max-min.html
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-lnl-3/igt@kms_vrr@max-min.html
* igt@xe_exec_basic@multigpu-once-null:
- shard-dg2-set2: [SKIP][119] ([Intel XE#1392]) -> [PASS][120] +4 other tests pass
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-dg2-432/igt@xe_exec_basic@multigpu-once-null.html
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-dg2-464/igt@xe_exec_basic@multigpu-once-null.html
* igt@xe_exec_system_allocator@fault-benchmark:
- shard-bmg: [TIMEOUT][121] -> [PASS][122]
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-bmg-4/igt@xe_exec_system_allocator@fault-benchmark.html
[122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-bmg-8/igt@xe_exec_system_allocator@fault-benchmark.html
* {igt@xe_exec_system_allocator@twice-malloc-prefetch}:
- shard-lnl: [CRASH][123] ([Intel XE#6192]) -> [PASS][124] +8 other tests pass
[123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-lnl-3/igt@xe_exec_system_allocator@twice-malloc-prefetch.html
[124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-lnl-3/igt@xe_exec_system_allocator@twice-malloc-prefetch.html
* {igt@xe_exec_system_allocator@twice-new-prefetch}:
- shard-bmg: [CRASH][125] ([Intel XE#6192]) -> [PASS][126] +9 other tests pass
[125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-bmg-3/igt@xe_exec_system_allocator@twice-new-prefetch.html
[126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-bmg-7/igt@xe_exec_system_allocator@twice-new-prefetch.html
#### Warnings ####
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-lnl: [FAIL][127] ([Intel XE#301] / [Intel XE#3149]) -> [FAIL][128] ([Intel XE#301])
[127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-suspend:
- shard-adlp: [DMESG-WARN][129] ([Intel XE#2953] / [Intel XE#4173]) -> [DMESG-WARN][130] ([Intel XE#4543])
[129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-adlp-1/igt@kms_flip@flip-vs-suspend.html
[130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-adlp-3/igt@kms_flip@flip-vs-suspend.html
* igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-blt:
- shard-bmg: [SKIP][131] ([Intel XE#2311]) -> [SKIP][132] ([Intel XE#2312]) +9 other tests skip
[131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-blt.html
[132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][133] ([Intel XE#2312]) -> [SKIP][134] ([Intel XE#2311]) +6 other tests skip
[133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html
[134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-bmg-3/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][135] ([Intel XE#5390]) -> [SKIP][136] ([Intel XE#2312]) +3 other tests skip
[135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc.html
[136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt:
- shard-bmg: [SKIP][137] ([Intel XE#2312]) -> [SKIP][138] ([Intel XE#5390]) +3 other tests skip
[137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt.html
[138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-plflip-blt:
- shard-bmg: [SKIP][139] ([Intel XE#2312]) -> [SKIP][140] ([Intel XE#2313]) +6 other tests skip
[139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-plflip-blt.html
[140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt:
- shard-bmg: [SKIP][141] ([Intel XE#2313]) -> [SKIP][142] ([Intel XE#2312]) +8 other tests skip
[141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-bmg-5/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
[142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
* igt@kms_tiled_display@basic-test-pattern:
- shard-bmg: [FAIL][143] ([Intel XE#1729]) -> [SKIP][144] ([Intel XE#2426])
[143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-bmg-5/igt@kms_tiled_display@basic-test-pattern.html
[144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-bmg-6/igt@kms_tiled_display@basic-test-pattern.html
- shard-dg2-set2: [SKIP][145] ([Intel XE#362]) -> [FAIL][146] ([Intel XE#1729])
[145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-dg2-463/igt@kms_tiled_display@basic-test-pattern.html
[146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-dg2-435/igt@kms_tiled_display@basic-test-pattern.html
* igt@xe_exec_fault_mode@many-rebind:
- shard-adlp: [INCOMPLETE][147] ([Intel XE#2594]) -> [SKIP][148] ([Intel XE#288] / [Intel XE#5561])
[147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-adlp-9/igt@xe_exec_fault_mode@many-rebind.html
[148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-adlp-6/igt@xe_exec_fault_mode@many-rebind.html
* igt@xe_exec_threads@threads-mixed-userptr-rebind:
- shard-adlp: [FAIL][149] -> [DMESG-FAIL][150] ([Intel XE#3876])
[149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-adlp-4/igt@xe_exec_threads@threads-mixed-userptr-rebind.html
[150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-adlp-9/igt@xe_exec_threads@threads-mixed-userptr-rebind.html
* igt@xe_peer2peer@read:
- shard-dg2-set2: [FAIL][151] ([Intel XE#1173]) -> [SKIP][152] ([Intel XE#1061])
[151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-dg2-463/igt@xe_peer2peer@read.html
[152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-dg2-432/igt@xe_peer2peer@read.html
* igt@xe_sriov_scheduling@nonpreempt-engine-resets@numvfs-random:
- shard-adlp: [ABORT][153] ([Intel XE#4917] / [Intel XE#5545]) -> [ABORT][154] ([Intel XE#4917]) +1 other test abort
[153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412/shard-adlp-8/igt@xe_sriov_scheduling@nonpreempt-engine-resets@numvfs-random.html
[154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/shard-adlp-4/igt@xe_sriov_scheduling@nonpreempt-engine-resets@numvfs-random.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[Intel XE#1061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1061
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1129]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1129
[Intel XE#1173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1173
[Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
[Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
[Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
[Intel XE#1475]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1475
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1500]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1500
[Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
[Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
[Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
[Intel XE#1874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1874
[Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
[Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
[Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
[Intel XE#2594]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2594
[Intel XE#261]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/261
[Intel XE#2705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2705
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
[Intel XE#2883]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2883
[Intel XE#2938]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2938
[Intel XE#2939]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2939
[Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
[Intel XE#3009]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3009
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#3012]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3012
[Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
[Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
[Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
[Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
[Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
[Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
[Intel XE#330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/330
[Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
[Intel XE#362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/362
[Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
[Intel XE#3862]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3862
[Intel XE#3876]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3876
[Intel XE#4130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4130
[Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
[Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
[Intel XE#4227]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4227
[Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
[Intel XE#4351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4351
[Intel XE#4416]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4416
[Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
[Intel XE#4522]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4522
[Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
[Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
[Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
[Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
[Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
[Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
[Intel XE#4917]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4917
[Intel XE#5100]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5100
[Intel XE#512]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/512
[Intel XE#5208]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5208
[Intel XE#5390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5390
[Intel XE#5545]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5545
[Intel XE#5561]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5561
[Intel XE#5564]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5564
[Intel XE#5575]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5575
[Intel XE#5585]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5585
[Intel XE#5594]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5594
[Intel XE#5632]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5632
[Intel XE#5786]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5786
[Intel XE#5890]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5890
[Intel XE#610]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/610
[Intel XE#6192]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6192
[Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
[Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
[Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
[Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
[Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
Build changes
-------------
* Linux: xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412 -> xe-pw-154737v5
IGT_8555: 8555
xe-3835-3008c5c8e2fade05918e6d8c456572c91f30d412: 3008c5c8e2fade05918e6d8c456572c91f30d412
xe-pw-154737v5: 154737v5
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v5/index.html
[-- Attachment #2: Type: text/html, Size: 51818 bytes --]
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v5 2/6] drm/dp: Add helpers to query the branch DSC max throughput/line-width
2025-09-26 21:12 ` [PATCH v4 2/6] drm/dp: Add helpers to query the branch DSC max throughput/line-width Imre Deak
@ 2025-09-29 6:36 ` Imre Deak
2025-09-29 9:00 ` Dmitry Baryshkov
2025-09-29 10:12 ` Ville Syrjälä
0 siblings, 2 replies; 25+ messages in thread
From: Imre Deak @ 2025-09-29 6:36 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: dri-devel, Ville Syrjälä
Add helpers to query the DP DSC sink device's per-slice throughput as
well as a DSC branch device's overall throughput and line-width
capabilities.
v2 (Ville):
- Rename pixel_clock to peak_pixel_rate, document what the value means
in case of MST tiled displays.
- Fix name of drm_dp_dsc_branch_max_slice_throughput() to
drm_dp_dsc_sink_max_slice_throughput().
v3:
- Fix the DSC branch device minimum valid line width value from 2560
to 5120 pixels.
- Fix drm_dp_dsc_sink_max_slice_throughput()'s pixel_clock parameter
name to peak_pixel_rate in header file.
- Add handling for throughput mode 0 granular delta, defined by DP
Standard v2.1a.
Cc: dri-devel@lists.freedesktop.org
Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/display/drm_dp_helper.c | 156 ++++++++++++++++++++++++
include/drm/display/drm_dp.h | 3 +
include/drm/display/drm_dp_helper.h | 5 +
3 files changed, 164 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
index 1c74fe9459ad9..6084ca7fbe263 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -2844,6 +2844,162 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
}
EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
+/*
+ * See DP Standard v2.1a 2.8.4 Minimum Slices/Display, Table 2-159 and
+ * Appendix L.1 Derivation of Slice Count Requirements.
+ */
+static int dsc_sink_min_slice_throughput(int peak_pixel_rate)
+{
+ if (peak_pixel_rate >= 4800000)
+ return 600000;
+ else if (peak_pixel_rate >= 2700000)
+ return 400000;
+ else
+ return 340000;
+}
+
+/**
+ * drm_dp_dsc_sink_max_slice_throughput() - Get a DSC sink's maximum pixel throughput per slice
+ * @dsc_dpcd: DSC sink's capabilities from DPCD
+ * @peak_pixel_rate: Cumulative peak pixel rate in kHz
+ * @is_rgb_yuv444: The mode is either RGB or YUV444
+ *
+ * Return the DSC sink device's maximum pixel throughput per slice, based on
+ * the device's @dsc_dpcd capabilities, the @peak_pixel_rate of the transferred
+ * stream(s) and whether the output format @is_rgb_yuv444 or yuv422/yuv420.
+ *
+ * Note that @peak_pixel_rate is the total pixel rate transferred to the same
+ * DSC/display sink. For instance to calculate a tile's slice count of an MST
+ * multi-tiled display sink (not considering here the required
+ * rounding/alignment of slice count)::
+ *
+ * @peak_pixel_rate = tile_pixel_rate * tile_count
+ * total_slice_count = @peak_pixel_rate / drm_dp_dsc_sink_max_slice_throughput(@peak_pixel_rate)
+ * tile_slice_count = total_slice_count / tile_count
+ *
+ * Returns:
+ * The maximum pixel throughput per slice supported by the DSC sink device
+ * in kPixels/sec.
+ */
+int drm_dp_dsc_sink_max_slice_throughput(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
+ int peak_pixel_rate, bool is_rgb_yuv444)
+{
+ int throughput;
+ int delta = 0;
+ int base;
+
+ throughput = dsc_dpcd[DP_DSC_PEAK_THROUGHPUT - DP_DSC_SUPPORT];
+
+ if (is_rgb_yuv444) {
+ throughput = (throughput & DP_DSC_THROUGHPUT_MODE_0_MASK) >>
+ DP_DSC_THROUGHPUT_MODE_0_SHIFT;
+
+ delta = ((dsc_dpcd[DP_DSC_RC_BUF_BLK_SIZE - DP_DSC_SUPPORT]) &
+ DP_DSC_THROUGHPUT_MODE_0_DELTA_MASK) >>
+ DP_DSC_THROUGHPUT_MODE_0_DELTA_SHIFT; /* in units of 2 MPixels/sec */
+ delta *= 2000;
+ } else {
+ throughput = (throughput & DP_DSC_THROUGHPUT_MODE_1_MASK) >>
+ DP_DSC_THROUGHPUT_MODE_1_SHIFT;
+ }
+
+ switch (throughput) {
+ case 0:
+ return dsc_sink_min_slice_throughput(peak_pixel_rate);
+ case 1:
+ base = 340000;
+ break;
+ case 2 ... 14:
+ base = 400000 + 50000 * (throughput - 2);
+ break;
+ case 15:
+ base = 170000;
+ break;
+ default:
+ WARN(1, "Missing case %d\n", throughput);
+ base = 340000;
+ break;
+ }
+
+ return base + delta;
+}
+EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_throughput);
+
+static u8 dsc_branch_dpcd_cap(const u8 dpcd[DP_DSC_BRANCH_CAP_SIZE], int reg)
+{
+ return dpcd[reg - DP_DSC_BRANCH_OVERALL_THROUGHPUT_0];
+}
+
+/**
+ * drm_dp_dsc_branch_max_overall_throughput() - Branch device's max overall DSC pixel throughput
+ * @dsc_branch_dpcd: DSC branch capabilities from DPCD
+ * @is_rgb_yuv444: The mode is either RGB or YUV444
+ *
+ * Return the branch device's maximum overall DSC pixel throughput, based on
+ * the device's DPCD DSC branch capabilities, and whether the output
+ * format @is_rgb_yuv444 or yuv422/yuv420.
+ *
+ * Returns:
+ * - 0: The maximum overall throughput capability is not indicated by
+ * the device separately and it must be determined from the per-slice
+ * max throughput (see @drm_dp_dsc_branch_slice_max_throughput())
+ * and the maximum slice count supported by the device.
+ * - > 0: The maximum overall DSC pixel throughput supported by the branch
+ * device in kPixels/sec.
+ */
+int drm_dp_dsc_branch_max_overall_throughput(const u8 dsc_branch_dpcd[DP_DSC_BRANCH_CAP_SIZE],
+ bool is_rgb_yuv444)
+{
+ int throughput;
+
+ if (is_rgb_yuv444)
+ throughput = dsc_branch_dpcd_cap(dsc_branch_dpcd,
+ DP_DSC_BRANCH_OVERALL_THROUGHPUT_0);
+ else
+ throughput = dsc_branch_dpcd_cap(dsc_branch_dpcd,
+ DP_DSC_BRANCH_OVERALL_THROUGHPUT_1);
+
+ switch (throughput) {
+ case 0:
+ return 0;
+ case 1:
+ return 680000;
+ default:
+ return 600000 + 50000 * throughput;
+ }
+}
+EXPORT_SYMBOL(drm_dp_dsc_branch_max_overall_throughput);
+
+/**
+ * drm_dp_dsc_branch_max_line_width() - Branch device's max DSC line width
+ * @dsc_branch_dpcd: DSC branch capabilities from DPCD
+ *
+ * Return the branch device's maximum overall DSC line width, based on
+ * the device's @dsc_branch_dpcd capabilities.
+ *
+ * Returns:
+ * - 0: The maximum line width is not indicated by the device
+ * separately and it must be determined from the maximum
+ * slice count and slice-width supported by the device.
+ * - %-EINVAL: The device indicates an invalid maximum line width
+ * (< 5120 pixels).
+ * - >= 5120: The maximum line width in pixels.
+ */
+int drm_dp_dsc_branch_max_line_width(const u8 dsc_branch_dpcd[DP_DSC_BRANCH_CAP_SIZE])
+{
+ int line_width = dsc_branch_dpcd_cap(dsc_branch_dpcd, DP_DSC_BRANCH_MAX_LINE_WIDTH);
+
+ switch (line_width) {
+ case 0:
+ return 0;
+ case 1 ... 15:
+ return -EINVAL;
+ default:
+ return line_width * 320;
+ }
+}
+EXPORT_SYMBOL(drm_dp_dsc_branch_max_line_width);
+
static int drm_dp_read_lttpr_regs(struct drm_dp_aux *aux,
const u8 dpcd[DP_RECEIVER_CAP_SIZE], int address,
u8 *buf, int buf_size)
diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index cf318e3ddb5c5..e4eebabab9759 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -258,6 +258,8 @@
# define DP_DSC_RC_BUF_BLK_SIZE_4 0x1
# define DP_DSC_RC_BUF_BLK_SIZE_16 0x2
# define DP_DSC_RC_BUF_BLK_SIZE_64 0x3
+# define DP_DSC_THROUGHPUT_MODE_0_DELTA_SHIFT 3 /* DP 2.1a, in units of 2 MPixels/sec */
+# define DP_DSC_THROUGHPUT_MODE_0_DELTA_MASK (0x1f << DP_DSC_THROUGHPUT_MODE_0_DELTA_SHIFT)
#define DP_DSC_RC_BUF_SIZE 0x063
@@ -1686,6 +1688,7 @@ enum drm_dp_phy {
#define DP_BRANCH_OUI_HEADER_SIZE 0xc
#define DP_RECEIVER_CAP_SIZE 0xf
#define DP_DSC_RECEIVER_CAP_SIZE 0x10 /* DSC Capabilities 0x60 through 0x6F */
+#define DP_DSC_BRANCH_CAP_SIZE 3
#define EDP_PSR_RECEIVER_CAP_SIZE 2
#define EDP_DISPLAY_CTL_CAP_SIZE 5
#define DP_LTTPR_COMMON_CAP_SIZE 8
diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
index e438c44409952..df2f24b950e4c 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -211,6 +211,11 @@ u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE],
u8 dsc_bpc[3]);
+int drm_dp_dsc_sink_max_slice_throughput(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
+ int peak_pixel_rate, bool is_rgb_yuv444);
+int drm_dp_dsc_branch_max_overall_throughput(const u8 dsc_branch_dpcd[DP_DSC_BRANCH_CAP_SIZE],
+ bool is_rgb_yuv444);
+int drm_dp_dsc_branch_max_line_width(const u8 dsc_branch_dpcd[DP_DSC_BRANCH_CAP_SIZE]);
static inline bool
drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
--
2.49.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* ✗ CI.checkpatch: warning for drm/i915/dp: Work around a DSC pixel throughput issue (rev6)
2025-09-26 21:12 [PATCH v4 0/6] drm/i915/dp: Work around a DSC pixel throughput issue Imre Deak
` (9 preceding siblings ...)
2025-09-27 5:36 ` ✗ Xe.CI.Full: failure " Patchwork
@ 2025-09-29 7:12 ` Patchwork
2025-09-29 7:13 ` ✓ CI.KUnit: success " Patchwork
` (3 subsequent siblings)
14 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2025-09-29 7:12 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-xe
== Series Details ==
Series: drm/i915/dp: Work around a DSC pixel throughput issue (rev6)
URL : https://patchwork.freedesktop.org/series/154737/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
fbd08a78c3a3bb17964db2a326514c69c1dca660
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 3232564c43d2db568574d01aee89053ce087f63a
Author: Imre Deak <imre.deak@intel.com>
Date: Sat Sep 27 00:12:36 2025 +0300
drm/i915/dp: Handle Synaptics DSC throughput link-bpp quirk
Handle the DSC pixel throughput quirk, limiting the compressed link-bpp
value for Synaptics Panamera branch devices, working around a
blank/unstable output issue observed on docking stations containing
these branch devices, when using a mode with a high pixel clock and a
high compressed link-bpp value.
For now use the same mode clock limit for RGB/YUV444 and YUV422/420
output modes. This may result in limiting the link-bpp value for a
YUV422/420 output mode already at a lower than required mode clock.
v2: Apply the quirk only when DSC is enabled.
v3 (Ville):
- Move adjustment of link-bpp within the already existing is_dsc
if branch.
- Add TODO comment to move the HW revision check as well to the
DRM core quirk table.
v4:
- Fix incorrect fxp_q4_from_int(INT_MAX) vs. INT_MAX return value
from dsc_throughput_quirk_max_bpp_x16().
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reported-by: Vidya Srinivas <vidya.srinivas@intel.com>
Reported-by: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
+ /mt/dim checkpatch e2a896e95ea5f65aa137dcf117bfd0d61176c8ce drm-intel
ec60e7c1b44e drm/dp: Add quirk for Synaptics DSC throughput link-bpp limit
-:46: WARNING:BAD_REPORTED_BY_LINK: Reported-by: should be immediately followed by Closes: with a URL to the report
#46:
Reported-by: Vidya Srinivas <vidya.srinivas@intel.com>
Reported-by: Swati Sharma <swati2.sharma@intel.com>
-:47: WARNING:BAD_REPORTED_BY_LINK: Reported-by: should be immediately followed by Closes: with a URL to the report
#47:
Reported-by: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
-:58: WARNING:LONG_LINE_COMMENT: line length of 111 exceeds 100 columns
#58: FILE: drivers/gpu/drm/display/drm_dp_helper.c:2554:
+ /* Synaptics Panamera supports only a compressed bpp of 12 above 50% of its max DSC pixel throughput */
-:59: WARNING:LONG_LINE: line length of 128 exceeds 100 columns
#59: FILE: drivers/gpu/drm/display/drm_dp_helper.c:2555:
+ { OUI(0x90, 0xCC, 0x24), DEVICE_ID('S', 'Y', 'N', 'A', 0x53, 0x22), true, BIT(DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT) },
-:60: WARNING:LONG_LINE: line length of 128 exceeds 100 columns
#60: FILE: drivers/gpu/drm/display/drm_dp_helper.c:2556:
+ { OUI(0x90, 0xCC, 0x24), DEVICE_ID('S', 'Y', 'N', 'A', 0x53, 0x31), true, BIT(DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT) },
-:61: WARNING:LONG_LINE: line length of 128 exceeds 100 columns
#61: FILE: drivers/gpu/drm/display/drm_dp_helper.c:2557:
+ { OUI(0x90, 0xCC, 0x24), DEVICE_ID('S', 'Y', 'N', 'A', 0x53, 0x33), true, BIT(DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT) },
total: 0 errors, 6 warnings, 0 checks, 25 lines checked
54d601d5d48e drm/dp: Add helpers to query the branch DSC max throughput/line-width
b9d871789bb9 drm/i915/dp: Calculate DSC slice count based on per-slice peak throughput
9d267bb18081 drm/i915/dp: Pass DPCD device descriptor to intel_dp_get_dsc_sink_cap()
0cef6b54d2e9 drm/i915/dp: Verify branch devices' overall pixel throughput/line width
3232564c43d2 drm/i915/dp: Handle Synaptics DSC throughput link-bpp quirk
-:30: WARNING:BAD_REPORTED_BY_LINK: Reported-by: should be immediately followed by Closes: with a URL to the report
#30:
Reported-by: Vidya Srinivas <vidya.srinivas@intel.com>
Reported-by: Swati Sharma <swati2.sharma@intel.com>
-:31: WARNING:BAD_REPORTED_BY_LINK: Reported-by: should be immediately followed by Closes: with a URL to the report
#31:
Reported-by: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
-:111: WARNING:LONG_LINE: line length of 140 exceeds 100 columns
#111: FILE: drivers/gpu/drm/i915/display/intel_dp.c:2576:
+ "[CRTC:%d:%s][CONNECTOR:%d:%s] Decreasing link max bpp to " FXP_Q4_FMT " due to DSC throughput quirk\n",
total: 0 errors, 3 warnings, 0 checks, 94 lines checked
^ permalink raw reply [flat|nested] 25+ messages in thread
* ✓ CI.KUnit: success for drm/i915/dp: Work around a DSC pixel throughput issue (rev6)
2025-09-26 21:12 [PATCH v4 0/6] drm/i915/dp: Work around a DSC pixel throughput issue Imre Deak
` (10 preceding siblings ...)
2025-09-29 7:12 ` ✗ CI.checkpatch: warning for drm/i915/dp: Work around a DSC pixel throughput issue (rev6) Patchwork
@ 2025-09-29 7:13 ` Patchwork
2025-09-29 9:22 ` ✓ Xe.CI.BAT: " Patchwork
` (2 subsequent siblings)
14 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2025-09-29 7:13 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-xe
== Series Details ==
Series: drm/i915/dp: Work around a DSC pixel throughput issue (rev6)
URL : https://patchwork.freedesktop.org/series/154737/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[07:12:17] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[07:12:21] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[07:12:50] Starting KUnit Kernel (1/1)...
[07:12:50] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[07:12:50] ================== guc_buf (11 subtests) ===================
[07:12:50] [PASSED] test_smallest
[07:12:50] [PASSED] test_largest
[07:12:50] [PASSED] test_granular
[07:12:50] [PASSED] test_unique
[07:12:50] [PASSED] test_overlap
[07:12:50] [PASSED] test_reusable
[07:12:50] [PASSED] test_too_big
[07:12:50] [PASSED] test_flush
[07:12:50] [PASSED] test_lookup
[07:12:50] [PASSED] test_data
[07:12:50] [PASSED] test_class
[07:12:50] ===================== [PASSED] guc_buf =====================
[07:12:50] =================== guc_dbm (7 subtests) ===================
[07:12:50] [PASSED] test_empty
[07:12:50] [PASSED] test_default
[07:12:50] ======================== test_size ========================
[07:12:50] [PASSED] 4
[07:12:50] [PASSED] 8
[07:12:50] [PASSED] 32
[07:12:50] [PASSED] 256
[07:12:50] ==================== [PASSED] test_size ====================
[07:12:50] ======================= test_reuse ========================
[07:12:50] [PASSED] 4
[07:12:50] [PASSED] 8
[07:12:50] [PASSED] 32
[07:12:50] [PASSED] 256
[07:12:50] =================== [PASSED] test_reuse ====================
[07:12:50] =================== test_range_overlap ====================
[07:12:50] [PASSED] 4
[07:12:50] [PASSED] 8
[07:12:50] [PASSED] 32
[07:12:50] [PASSED] 256
[07:12:50] =============== [PASSED] test_range_overlap ================
[07:12:50] =================== test_range_compact ====================
[07:12:50] [PASSED] 4
[07:12:50] [PASSED] 8
[07:12:50] [PASSED] 32
[07:12:50] [PASSED] 256
[07:12:50] =============== [PASSED] test_range_compact ================
[07:12:50] ==================== test_range_spare =====================
[07:12:50] [PASSED] 4
[07:12:50] [PASSED] 8
[07:12:50] [PASSED] 32
[07:12:50] [PASSED] 256
[07:12:50] ================ [PASSED] test_range_spare =================
[07:12:50] ===================== [PASSED] guc_dbm =====================
[07:12:50] =================== guc_idm (6 subtests) ===================
[07:12:50] [PASSED] bad_init
[07:12:50] [PASSED] no_init
[07:12:50] [PASSED] init_fini
[07:12:50] [PASSED] check_used
[07:12:50] [PASSED] check_quota
[07:12:50] [PASSED] check_all
[07:12:50] ===================== [PASSED] guc_idm =====================
[07:12:50] ================== no_relay (3 subtests) ===================
[07:12:50] [PASSED] xe_drops_guc2pf_if_not_ready
[07:12:50] [PASSED] xe_drops_guc2vf_if_not_ready
[07:12:50] [PASSED] xe_rejects_send_if_not_ready
[07:12:50] ==================== [PASSED] no_relay =====================
[07:12:50] ================== pf_relay (14 subtests) ==================
[07:12:50] [PASSED] pf_rejects_guc2pf_too_short
[07:12:50] [PASSED] pf_rejects_guc2pf_too_long
[07:12:50] [PASSED] pf_rejects_guc2pf_no_payload
[07:12:50] [PASSED] pf_fails_no_payload
[07:12:50] [PASSED] pf_fails_bad_origin
[07:12:50] [PASSED] pf_fails_bad_type
[07:12:50] [PASSED] pf_txn_reports_error
[07:12:50] [PASSED] pf_txn_sends_pf2guc
[07:12:50] [PASSED] pf_sends_pf2guc
[07:12:50] [SKIPPED] pf_loopback_nop
[07:12:50] [SKIPPED] pf_loopback_echo
[07:12:50] [SKIPPED] pf_loopback_fail
[07:12:50] [SKIPPED] pf_loopback_busy
[07:12:50] [SKIPPED] pf_loopback_retry
[07:12:50] ==================== [PASSED] pf_relay =====================
[07:12:50] ================== vf_relay (3 subtests) ===================
[07:12:50] [PASSED] vf_rejects_guc2vf_too_short
[07:12:50] [PASSED] vf_rejects_guc2vf_too_long
[07:12:50] [PASSED] vf_rejects_guc2vf_no_payload
[07:12:50] ==================== [PASSED] vf_relay =====================
[07:12:50] ===================== lmtt (1 subtest) =====================
[07:12:50] ======================== test_ops =========================
[07:12:50] [PASSED] 2-level
[07:12:50] [PASSED] multi-level
[07:12:50] ==================== [PASSED] test_ops =====================
[07:12:50] ====================== [PASSED] lmtt =======================
[07:12:50] ================= pf_service (11 subtests) =================
[07:12:50] [PASSED] pf_negotiate_any
[07:12:50] [PASSED] pf_negotiate_base_match
[07:12:50] [PASSED] pf_negotiate_base_newer
[07:12:50] [PASSED] pf_negotiate_base_next
[07:12:50] [SKIPPED] pf_negotiate_base_older
[07:12:50] [PASSED] pf_negotiate_base_prev
[07:12:50] [PASSED] pf_negotiate_latest_match
[07:12:50] [PASSED] pf_negotiate_latest_newer
[07:12:50] [PASSED] pf_negotiate_latest_next
[07:12:50] [SKIPPED] pf_negotiate_latest_older
[07:12:50] [SKIPPED] pf_negotiate_latest_prev
[07:12:50] =================== [PASSED] pf_service ====================
[07:12:50] ================= xe_guc_g2g (2 subtests) ==================
[07:12:50] ============== xe_live_guc_g2g_kunit_default ==============
[07:12:50] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[07:12:50] ============== xe_live_guc_g2g_kunit_allmem ===============
[07:12:50] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[07:12:50] =================== [SKIPPED] xe_guc_g2g ===================
[07:12:50] =================== xe_mocs (2 subtests) ===================
[07:12:50] ================ xe_live_mocs_kernel_kunit ================
[07:12:50] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[07:12:50] ================ xe_live_mocs_reset_kunit =================
[07:12:50] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[07:12:50] ==================== [SKIPPED] xe_mocs =====================
[07:12:50] ================= xe_migrate (2 subtests) ==================
[07:12:50] ================= xe_migrate_sanity_kunit =================
[07:12:50] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[07:12:50] ================== xe_validate_ccs_kunit ==================
[07:12:50] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[07:12:50] =================== [SKIPPED] xe_migrate ===================
[07:12:50] ================== xe_dma_buf (1 subtest) ==================
[07:12:50] ==================== xe_dma_buf_kunit =====================
[07:12:50] ================ [SKIPPED] xe_dma_buf_kunit ================
[07:12:50] =================== [SKIPPED] xe_dma_buf ===================
[07:12:50] ================= xe_bo_shrink (1 subtest) =================
[07:12:50] =================== xe_bo_shrink_kunit ====================
[07:12:50] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[07:12:50] ================== [SKIPPED] xe_bo_shrink ==================
[07:12:50] ==================== xe_bo (2 subtests) ====================
[07:12:50] ================== xe_ccs_migrate_kunit ===================
[07:12:50] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[07:12:50] ==================== xe_bo_evict_kunit ====================
[07:12:50] =============== [SKIPPED] xe_bo_evict_kunit ================
[07:12:50] ===================== [SKIPPED] xe_bo ======================
[07:12:50] ==================== args (11 subtests) ====================
[07:12:50] [PASSED] count_args_test
[07:12:50] [PASSED] call_args_example
[07:12:50] [PASSED] call_args_test
[07:12:50] [PASSED] drop_first_arg_example
[07:12:50] [PASSED] drop_first_arg_test
[07:12:50] [PASSED] first_arg_example
[07:12:50] [PASSED] first_arg_test
[07:12:50] [PASSED] last_arg_example
[07:12:50] [PASSED] last_arg_test
[07:12:50] [PASSED] pick_arg_example
[07:12:50] [PASSED] sep_comma_example
[07:12:50] ====================== [PASSED] args =======================
[07:12:50] =================== xe_pci (3 subtests) ====================
[07:12:50] ==================== check_graphics_ip ====================
[07:12:50] [PASSED] 12.00 Xe_LP
[07:12:50] [PASSED] 12.10 Xe_LP+
[07:12:50] [PASSED] 12.55 Xe_HPG
[07:12:50] [PASSED] 12.60 Xe_HPC
[07:12:50] [PASSED] 12.70 Xe_LPG
[07:12:50] [PASSED] 12.71 Xe_LPG
[07:12:50] [PASSED] 12.74 Xe_LPG+
[07:12:50] [PASSED] 20.01 Xe2_HPG
[07:12:50] [PASSED] 20.02 Xe2_HPG
[07:12:50] [PASSED] 20.04 Xe2_LPG
[07:12:50] [PASSED] 30.00 Xe3_LPG
[07:12:50] [PASSED] 30.01 Xe3_LPG
[07:12:50] [PASSED] 30.03 Xe3_LPG
[07:12:50] ================ [PASSED] check_graphics_ip ================
[07:12:50] ===================== check_media_ip ======================
[07:12:50] [PASSED] 12.00 Xe_M
[07:12:50] [PASSED] 12.55 Xe_HPM
[07:12:50] [PASSED] 13.00 Xe_LPM+
[07:12:50] [PASSED] 13.01 Xe2_HPM
[07:12:50] [PASSED] 20.00 Xe2_LPM
[07:12:50] [PASSED] 30.00 Xe3_LPM
[07:12:50] [PASSED] 30.02 Xe3_LPM
[07:12:50] ================= [PASSED] check_media_ip ==================
[07:12:50] ================= check_platform_gt_count =================
[07:12:50] [PASSED] 0x9A60 (TIGERLAKE)
[07:12:50] [PASSED] 0x9A68 (TIGERLAKE)
[07:12:50] [PASSED] 0x9A70 (TIGERLAKE)
[07:12:50] [PASSED] 0x9A40 (TIGERLAKE)
[07:12:50] [PASSED] 0x9A49 (TIGERLAKE)
[07:12:50] [PASSED] 0x9A59 (TIGERLAKE)
[07:12:50] [PASSED] 0x9A78 (TIGERLAKE)
[07:12:50] [PASSED] 0x9AC0 (TIGERLAKE)
[07:12:50] [PASSED] 0x9AC9 (TIGERLAKE)
[07:12:50] [PASSED] 0x9AD9 (TIGERLAKE)
[07:12:50] [PASSED] 0x9AF8 (TIGERLAKE)
[07:12:50] [PASSED] 0x4C80 (ROCKETLAKE)
[07:12:50] [PASSED] 0x4C8A (ROCKETLAKE)
[07:12:50] [PASSED] 0x4C8B (ROCKETLAKE)
[07:12:50] [PASSED] 0x4C8C (ROCKETLAKE)
[07:12:50] [PASSED] 0x4C90 (ROCKETLAKE)
[07:12:50] [PASSED] 0x4C9A (ROCKETLAKE)
[07:12:50] [PASSED] 0x4680 (ALDERLAKE_S)
[07:12:50] [PASSED] 0x4682 (ALDERLAKE_S)
[07:12:50] [PASSED] 0x4688 (ALDERLAKE_S)
[07:12:50] [PASSED] 0x468A (ALDERLAKE_S)
[07:12:50] [PASSED] 0x468B (ALDERLAKE_S)
[07:12:50] [PASSED] 0x4690 (ALDERLAKE_S)
[07:12:50] [PASSED] 0x4692 (ALDERLAKE_S)
[07:12:50] [PASSED] 0x4693 (ALDERLAKE_S)
[07:12:50] [PASSED] 0x46A0 (ALDERLAKE_P)
[07:12:50] [PASSED] 0x46A1 (ALDERLAKE_P)
[07:12:50] [PASSED] 0x46A2 (ALDERLAKE_P)
[07:12:50] [PASSED] 0x46A3 (ALDERLAKE_P)
[07:12:50] [PASSED] 0x46A6 (ALDERLAKE_P)
[07:12:50] [PASSED] 0x46A8 (ALDERLAKE_P)
[07:12:50] [PASSED] 0x46AA (ALDERLAKE_P)
[07:12:50] [PASSED] 0x462A (ALDERLAKE_P)
[07:12:50] [PASSED] 0x4626 (ALDERLAKE_P)
[07:12:50] [PASSED] 0x4628 (ALDERLAKE_P)
[07:12:50] [PASSED] 0x46B0 (ALDERLAKE_P)
[07:12:50] [PASSED] 0x46B1 (ALDERLAKE_P)
[07:12:50] [PASSED] 0x46B2 (ALDERLAKE_P)
[07:12:50] [PASSED] 0x46B3 (ALDERLAKE_P)
[07:12:50] [PASSED] 0x46C0 (ALDERLAKE_P)
[07:12:50] [PASSED] 0x46C1 (ALDERLAKE_P)
[07:12:50] [PASSED] 0x46C2 (ALDERLAKE_P)
[07:12:50] [PASSED] 0x46C3 (ALDERLAKE_P)
[07:12:50] [PASSED] 0x46D0 (ALDERLAKE_N)
[07:12:50] [PASSED] 0x46D1 (ALDERLAKE_N)
[07:12:50] [PASSED] 0x46D2 (ALDERLAKE_N)
[07:12:50] [PASSED] 0x46D3 (ALDERLAKE_N)
[07:12:50] [PASSED] 0x46D4 (ALDERLAKE_N)
[07:12:50] [PASSED] 0xA721 (ALDERLAKE_P)
[07:12:50] [PASSED] 0xA7A1 (ALDERLAKE_P)
[07:12:50] [PASSED] 0xA7A9 (ALDERLAKE_P)
[07:12:50] [PASSED] 0xA7AC (ALDERLAKE_P)
[07:12:50] [PASSED] 0xA7AD (ALDERLAKE_P)
[07:12:50] [PASSED] 0xA720 (ALDERLAKE_P)
[07:12:50] [PASSED] 0xA7A0 (ALDERLAKE_P)
[07:12:50] [PASSED] 0xA7A8 (ALDERLAKE_P)
[07:12:50] [PASSED] 0xA7AA (ALDERLAKE_P)
[07:12:50] [PASSED] 0xA7AB (ALDERLAKE_P)
[07:12:50] [PASSED] 0xA780 (ALDERLAKE_S)
[07:12:50] [PASSED] 0xA781 (ALDERLAKE_S)
[07:12:50] [PASSED] 0xA782 (ALDERLAKE_S)
[07:12:50] [PASSED] 0xA783 (ALDERLAKE_S)
[07:12:50] [PASSED] 0xA788 (ALDERLAKE_S)
[07:12:50] [PASSED] 0xA789 (ALDERLAKE_S)
[07:12:50] [PASSED] 0xA78A (ALDERLAKE_S)
[07:12:50] [PASSED] 0xA78B (ALDERLAKE_S)
[07:12:50] [PASSED] 0x4905 (DG1)
[07:12:50] [PASSED] 0x4906 (DG1)
[07:12:50] [PASSED] 0x4907 (DG1)
[07:12:50] [PASSED] 0x4908 (DG1)
[07:12:50] [PASSED] 0x4909 (DG1)
[07:12:50] [PASSED] 0x56C0 (DG2)
[07:12:50] [PASSED] 0x56C2 (DG2)
[07:12:50] [PASSED] 0x56C1 (DG2)
[07:12:50] [PASSED] 0x7D51 (METEORLAKE)
[07:12:50] [PASSED] 0x7DD1 (METEORLAKE)
[07:12:50] [PASSED] 0x7D41 (METEORLAKE)
[07:12:50] [PASSED] 0x7D67 (METEORLAKE)
[07:12:50] [PASSED] 0xB640 (METEORLAKE)
[07:12:50] [PASSED] 0x56A0 (DG2)
[07:12:50] [PASSED] 0x56A1 (DG2)
[07:12:50] [PASSED] 0x56A2 (DG2)
[07:12:50] [PASSED] 0x56BE (DG2)
[07:12:50] [PASSED] 0x56BF (DG2)
[07:12:50] [PASSED] 0x5690 (DG2)
[07:12:50] [PASSED] 0x5691 (DG2)
[07:12:50] [PASSED] 0x5692 (DG2)
[07:12:50] [PASSED] 0x56A5 (DG2)
[07:12:50] [PASSED] 0x56A6 (DG2)
[07:12:50] [PASSED] 0x56B0 (DG2)
[07:12:50] [PASSED] 0x56B1 (DG2)
[07:12:50] [PASSED] 0x56BA (DG2)
[07:12:50] [PASSED] 0x56BB (DG2)
[07:12:50] [PASSED] 0x56BC (DG2)
[07:12:50] [PASSED] 0x56BD (DG2)
[07:12:50] [PASSED] 0x5693 (DG2)
[07:12:50] [PASSED] 0x5694 (DG2)
[07:12:50] [PASSED] 0x5695 (DG2)
[07:12:50] [PASSED] 0x56A3 (DG2)
[07:12:50] [PASSED] 0x56A4 (DG2)
[07:12:50] [PASSED] 0x56B2 (DG2)
[07:12:50] [PASSED] 0x56B3 (DG2)
[07:12:50] [PASSED] 0x5696 (DG2)
[07:12:50] [PASSED] 0x5697 (DG2)
[07:12:50] [PASSED] 0xB69 (PVC)
[07:12:50] [PASSED] 0xB6E (PVC)
[07:12:50] [PASSED] 0xBD4 (PVC)
[07:12:50] [PASSED] 0xBD5 (PVC)
[07:12:50] [PASSED] 0xBD6 (PVC)
[07:12:50] [PASSED] 0xBD7 (PVC)
[07:12:50] [PASSED] 0xBD8 (PVC)
[07:12:50] [PASSED] 0xBD9 (PVC)
[07:12:50] [PASSED] 0xBDA (PVC)
[07:12:50] [PASSED] 0xBDB (PVC)
[07:12:50] [PASSED] 0xBE0 (PVC)
[07:12:50] [PASSED] 0xBE1 (PVC)
[07:12:50] [PASSED] 0xBE5 (PVC)
[07:12:50] [PASSED] 0x7D40 (METEORLAKE)
[07:12:50] [PASSED] 0x7D45 (METEORLAKE)
[07:12:50] [PASSED] 0x7D55 (METEORLAKE)
[07:12:50] [PASSED] 0x7D60 (METEORLAKE)
[07:12:50] [PASSED] 0x7DD5 (METEORLAKE)
[07:12:50] [PASSED] 0x6420 (LUNARLAKE)
[07:12:50] [PASSED] 0x64A0 (LUNARLAKE)
[07:12:50] [PASSED] 0x64B0 (LUNARLAKE)
[07:12:50] [PASSED] 0xE202 (BATTLEMAGE)
[07:12:50] [PASSED] 0xE209 (BATTLEMAGE)
[07:12:50] [PASSED] 0xE20B (BATTLEMAGE)
[07:12:50] [PASSED] 0xE20C (BATTLEMAGE)
[07:12:50] [PASSED] 0xE20D (BATTLEMAGE)
[07:12:50] [PASSED] 0xE210 (BATTLEMAGE)
[07:12:50] [PASSED] 0xE211 (BATTLEMAGE)
[07:12:50] [PASSED] 0xE212 (BATTLEMAGE)
[07:12:50] [PASSED] 0xE216 (BATTLEMAGE)
[07:12:50] [PASSED] 0xE220 (BATTLEMAGE)
[07:12:50] [PASSED] 0xE221 (BATTLEMAGE)
[07:12:50] [PASSED] 0xE222 (BATTLEMAGE)
[07:12:50] [PASSED] 0xE223 (BATTLEMAGE)
[07:12:50] [PASSED] 0xB080 (PANTHERLAKE)
[07:12:50] [PASSED] 0xB081 (PANTHERLAKE)
[07:12:50] [PASSED] 0xB082 (PANTHERLAKE)
[07:12:50] [PASSED] 0xB083 (PANTHERLAKE)
[07:12:50] [PASSED] 0xB084 (PANTHERLAKE)
[07:12:50] [PASSED] 0xB085 (PANTHERLAKE)
[07:12:50] [PASSED] 0xB086 (PANTHERLAKE)
[07:12:50] [PASSED] 0xB087 (PANTHERLAKE)
[07:12:50] [PASSED] 0xB08F (PANTHERLAKE)
[07:12:50] [PASSED] 0xB090 (PANTHERLAKE)
[07:12:50] [PASSED] 0xB0A0 (PANTHERLAKE)
[07:12:50] [PASSED] 0xB0B0 (PANTHERLAKE)
[07:12:50] [PASSED] 0xFD80 (PANTHERLAKE)
[07:12:50] [PASSED] 0xFD81 (PANTHERLAKE)
[07:12:50] ============= [PASSED] check_platform_gt_count =============
[07:12:50] ===================== [PASSED] xe_pci ======================
[07:12:50] =================== xe_rtp (2 subtests) ====================
[07:12:50] =============== xe_rtp_process_to_sr_tests ================
[07:12:50] [PASSED] coalesce-same-reg
[07:12:50] [PASSED] no-match-no-add
[07:12:50] [PASSED] match-or
[07:12:50] [PASSED] match-or-xfail
[07:12:50] [PASSED] no-match-no-add-multiple-rules
[07:12:50] [PASSED] two-regs-two-entries
[07:12:50] [PASSED] clr-one-set-other
[07:12:50] [PASSED] set-field
[07:12:50] [PASSED] conflict-duplicate
[07:12:50] [PASSED] conflict-not-disjoint
[07:12:50] [PASSED] conflict-reg-type
[07:12:50] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[07:12:50] ================== xe_rtp_process_tests ===================
[07:12:50] [PASSED] active1
[07:12:50] [PASSED] active2
[07:12:50] [PASSED] active-inactive
[07:12:50] [PASSED] inactive-active
[07:12:50] [PASSED] inactive-1st_or_active-inactive
[07:12:50] [PASSED] inactive-2nd_or_active-inactive
[07:12:50] [PASSED] inactive-last_or_active-inactive
[07:12:50] [PASSED] inactive-no_or_active-inactive
[07:12:50] ============== [PASSED] xe_rtp_process_tests ===============
[07:12:50] ===================== [PASSED] xe_rtp ======================
[07:12:50] ==================== xe_wa (1 subtest) =====================
[07:12:50] ======================== xe_wa_gt =========================
[07:12:50] [PASSED] TIGERLAKE B0
[07:12:50] [PASSED] DG1 A0
[07:12:50] [PASSED] DG1 B0
[07:12:50] [PASSED] ALDERLAKE_S A0
[07:12:50] [PASSED] ALDERLAKE_S B0
stty: 'standard input': Inappropriate ioctl for device
[07:12:50] [PASSED] ALDERLAKE_S C0
[07:12:50] [PASSED] ALDERLAKE_S D0
[07:12:50] [PASSED] ALDERLAKE_P A0
[07:12:50] [PASSED] ALDERLAKE_P B0
[07:12:50] [PASSED] ALDERLAKE_P C0
[07:12:50] [PASSED] ALDERLAKE_S RPLS D0
[07:12:50] [PASSED] ALDERLAKE_P RPLU E0
[07:12:50] [PASSED] DG2 G10 C0
[07:12:50] [PASSED] DG2 G11 B1
[07:12:50] [PASSED] DG2 G12 A1
[07:12:50] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[07:12:50] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[07:12:50] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[07:12:50] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[07:12:50] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[07:12:50] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[07:12:50] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[07:12:50] ==================== [PASSED] xe_wa_gt =====================
[07:12:50] ====================== [PASSED] xe_wa ======================
[07:12:50] ============================================================
[07:12:50] Testing complete. Ran 306 tests: passed: 288, skipped: 18
[07:12:50] Elapsed time: 33.592s total, 4.306s configuring, 28.920s building, 0.328s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[07:12:50] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[07:12:52] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[07:13:16] Starting KUnit Kernel (1/1)...
[07:13:16] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[07:13:16] ============ drm_test_pick_cmdline (2 subtests) ============
[07:13:16] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[07:13:16] =============== drm_test_pick_cmdline_named ===============
[07:13:16] [PASSED] NTSC
[07:13:16] [PASSED] NTSC-J
[07:13:16] [PASSED] PAL
[07:13:16] [PASSED] PAL-M
[07:13:16] =========== [PASSED] drm_test_pick_cmdline_named ===========
[07:13:16] ============== [PASSED] drm_test_pick_cmdline ==============
[07:13:16] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[07:13:16] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[07:13:16] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[07:13:16] =========== drm_validate_clone_mode (2 subtests) ===========
[07:13:16] ============== drm_test_check_in_clone_mode ===============
[07:13:16] [PASSED] in_clone_mode
[07:13:16] [PASSED] not_in_clone_mode
[07:13:16] ========== [PASSED] drm_test_check_in_clone_mode ===========
[07:13:16] =============== drm_test_check_valid_clones ===============
[07:13:16] [PASSED] not_in_clone_mode
[07:13:16] [PASSED] valid_clone
[07:13:16] [PASSED] invalid_clone
[07:13:16] =========== [PASSED] drm_test_check_valid_clones ===========
[07:13:16] ============= [PASSED] drm_validate_clone_mode =============
[07:13:16] ============= drm_validate_modeset (1 subtest) =============
[07:13:16] [PASSED] drm_test_check_connector_changed_modeset
[07:13:16] ============== [PASSED] drm_validate_modeset ===============
[07:13:16] ====== drm_test_bridge_get_current_state (2 subtests) ======
[07:13:16] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[07:13:16] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[07:13:16] ======== [PASSED] drm_test_bridge_get_current_state ========
[07:13:16] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[07:13:16] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[07:13:16] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[07:13:16] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[07:13:16] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[07:13:16] ============== drm_bridge_alloc (2 subtests) ===============
[07:13:16] [PASSED] drm_test_drm_bridge_alloc_basic
[07:13:16] [PASSED] drm_test_drm_bridge_alloc_get_put
[07:13:16] ================ [PASSED] drm_bridge_alloc =================
[07:13:16] ================== drm_buddy (7 subtests) ==================
[07:13:16] [PASSED] drm_test_buddy_alloc_limit
[07:13:16] [PASSED] drm_test_buddy_alloc_optimistic
[07:13:16] [PASSED] drm_test_buddy_alloc_pessimistic
[07:13:16] [PASSED] drm_test_buddy_alloc_pathological
[07:13:16] [PASSED] drm_test_buddy_alloc_contiguous
[07:13:16] [PASSED] drm_test_buddy_alloc_clear
[07:13:16] [PASSED] drm_test_buddy_alloc_range_bias
[07:13:16] ==================== [PASSED] drm_buddy ====================
[07:13:16] ============= drm_cmdline_parser (40 subtests) =============
[07:13:16] [PASSED] drm_test_cmdline_force_d_only
[07:13:16] [PASSED] drm_test_cmdline_force_D_only_dvi
[07:13:16] [PASSED] drm_test_cmdline_force_D_only_hdmi
[07:13:16] [PASSED] drm_test_cmdline_force_D_only_not_digital
[07:13:16] [PASSED] drm_test_cmdline_force_e_only
[07:13:16] [PASSED] drm_test_cmdline_res
[07:13:16] [PASSED] drm_test_cmdline_res_vesa
[07:13:16] [PASSED] drm_test_cmdline_res_vesa_rblank
[07:13:16] [PASSED] drm_test_cmdline_res_rblank
[07:13:16] [PASSED] drm_test_cmdline_res_bpp
[07:13:16] [PASSED] drm_test_cmdline_res_refresh
[07:13:16] [PASSED] drm_test_cmdline_res_bpp_refresh
[07:13:16] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[07:13:16] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[07:13:16] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[07:13:16] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[07:13:16] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[07:13:16] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[07:13:16] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[07:13:16] [PASSED] drm_test_cmdline_res_margins_force_on
[07:13:16] [PASSED] drm_test_cmdline_res_vesa_margins
[07:13:16] [PASSED] drm_test_cmdline_name
[07:13:16] [PASSED] drm_test_cmdline_name_bpp
[07:13:16] [PASSED] drm_test_cmdline_name_option
[07:13:16] [PASSED] drm_test_cmdline_name_bpp_option
[07:13:16] [PASSED] drm_test_cmdline_rotate_0
[07:13:16] [PASSED] drm_test_cmdline_rotate_90
[07:13:16] [PASSED] drm_test_cmdline_rotate_180
[07:13:16] [PASSED] drm_test_cmdline_rotate_270
[07:13:16] [PASSED] drm_test_cmdline_hmirror
[07:13:16] [PASSED] drm_test_cmdline_vmirror
[07:13:16] [PASSED] drm_test_cmdline_margin_options
[07:13:16] [PASSED] drm_test_cmdline_multiple_options
[07:13:16] [PASSED] drm_test_cmdline_bpp_extra_and_option
[07:13:16] [PASSED] drm_test_cmdline_extra_and_option
[07:13:16] [PASSED] drm_test_cmdline_freestanding_options
[07:13:16] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[07:13:16] [PASSED] drm_test_cmdline_panel_orientation
[07:13:16] ================ drm_test_cmdline_invalid =================
[07:13:16] [PASSED] margin_only
[07:13:16] [PASSED] interlace_only
[07:13:16] [PASSED] res_missing_x
[07:13:16] [PASSED] res_missing_y
[07:13:16] [PASSED] res_bad_y
[07:13:16] [PASSED] res_missing_y_bpp
[07:13:16] [PASSED] res_bad_bpp
[07:13:16] [PASSED] res_bad_refresh
[07:13:16] [PASSED] res_bpp_refresh_force_on_off
[07:13:16] [PASSED] res_invalid_mode
[07:13:16] [PASSED] res_bpp_wrong_place_mode
[07:13:16] [PASSED] name_bpp_refresh
[07:13:16] [PASSED] name_refresh
[07:13:16] [PASSED] name_refresh_wrong_mode
[07:13:16] [PASSED] name_refresh_invalid_mode
[07:13:16] [PASSED] rotate_multiple
[07:13:16] [PASSED] rotate_invalid_val
[07:13:16] [PASSED] rotate_truncated
[07:13:16] [PASSED] invalid_option
[07:13:16] [PASSED] invalid_tv_option
[07:13:16] [PASSED] truncated_tv_option
[07:13:16] ============ [PASSED] drm_test_cmdline_invalid =============
[07:13:16] =============== drm_test_cmdline_tv_options ===============
[07:13:16] [PASSED] NTSC
[07:13:16] [PASSED] NTSC_443
[07:13:16] [PASSED] NTSC_J
[07:13:16] [PASSED] PAL
[07:13:16] [PASSED] PAL_M
[07:13:16] [PASSED] PAL_N
[07:13:16] [PASSED] SECAM
[07:13:16] [PASSED] MONO_525
[07:13:16] [PASSED] MONO_625
[07:13:16] =========== [PASSED] drm_test_cmdline_tv_options ===========
[07:13:16] =============== [PASSED] drm_cmdline_parser ================
[07:13:16] ========== drmm_connector_hdmi_init (20 subtests) ==========
[07:13:16] [PASSED] drm_test_connector_hdmi_init_valid
[07:13:16] [PASSED] drm_test_connector_hdmi_init_bpc_8
[07:13:16] [PASSED] drm_test_connector_hdmi_init_bpc_10
[07:13:16] [PASSED] drm_test_connector_hdmi_init_bpc_12
[07:13:16] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[07:13:16] [PASSED] drm_test_connector_hdmi_init_bpc_null
[07:13:16] [PASSED] drm_test_connector_hdmi_init_formats_empty
[07:13:16] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[07:13:16] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[07:13:16] [PASSED] supported_formats=0x9 yuv420_allowed=1
[07:13:16] [PASSED] supported_formats=0x9 yuv420_allowed=0
[07:13:16] [PASSED] supported_formats=0x3 yuv420_allowed=1
[07:13:16] [PASSED] supported_formats=0x3 yuv420_allowed=0
[07:13:16] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[07:13:16] [PASSED] drm_test_connector_hdmi_init_null_ddc
[07:13:16] [PASSED] drm_test_connector_hdmi_init_null_product
[07:13:16] [PASSED] drm_test_connector_hdmi_init_null_vendor
[07:13:16] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[07:13:16] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[07:13:16] [PASSED] drm_test_connector_hdmi_init_product_valid
[07:13:16] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[07:13:16] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[07:13:16] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[07:13:16] ========= drm_test_connector_hdmi_init_type_valid =========
[07:13:16] [PASSED] HDMI-A
[07:13:16] [PASSED] HDMI-B
[07:13:16] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[07:13:16] ======== drm_test_connector_hdmi_init_type_invalid ========
[07:13:16] [PASSED] Unknown
[07:13:16] [PASSED] VGA
[07:13:16] [PASSED] DVI-I
[07:13:16] [PASSED] DVI-D
[07:13:16] [PASSED] DVI-A
[07:13:16] [PASSED] Composite
[07:13:16] [PASSED] SVIDEO
[07:13:16] [PASSED] LVDS
[07:13:16] [PASSED] Component
[07:13:16] [PASSED] DIN
[07:13:16] [PASSED] DP
[07:13:16] [PASSED] TV
[07:13:16] [PASSED] eDP
[07:13:16] [PASSED] Virtual
[07:13:16] [PASSED] DSI
[07:13:16] [PASSED] DPI
[07:13:16] [PASSED] Writeback
[07:13:16] [PASSED] SPI
[07:13:16] [PASSED] USB
[07:13:16] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[07:13:16] ============ [PASSED] drmm_connector_hdmi_init =============
[07:13:16] ============= drmm_connector_init (3 subtests) =============
[07:13:16] [PASSED] drm_test_drmm_connector_init
[07:13:16] [PASSED] drm_test_drmm_connector_init_null_ddc
[07:13:16] ========= drm_test_drmm_connector_init_type_valid =========
[07:13:16] [PASSED] Unknown
[07:13:16] [PASSED] VGA
[07:13:16] [PASSED] DVI-I
[07:13:16] [PASSED] DVI-D
[07:13:16] [PASSED] DVI-A
[07:13:16] [PASSED] Composite
[07:13:16] [PASSED] SVIDEO
[07:13:16] [PASSED] LVDS
[07:13:16] [PASSED] Component
[07:13:16] [PASSED] DIN
[07:13:16] [PASSED] DP
[07:13:16] [PASSED] HDMI-A
[07:13:16] [PASSED] HDMI-B
[07:13:16] [PASSED] TV
[07:13:16] [PASSED] eDP
[07:13:16] [PASSED] Virtual
[07:13:16] [PASSED] DSI
[07:13:16] [PASSED] DPI
[07:13:16] [PASSED] Writeback
[07:13:16] [PASSED] SPI
[07:13:16] [PASSED] USB
[07:13:16] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[07:13:16] =============== [PASSED] drmm_connector_init ===============
[07:13:16] ========= drm_connector_dynamic_init (6 subtests) ==========
[07:13:16] [PASSED] drm_test_drm_connector_dynamic_init
[07:13:16] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[07:13:16] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[07:13:16] [PASSED] drm_test_drm_connector_dynamic_init_properties
[07:13:16] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[07:13:16] [PASSED] Unknown
[07:13:16] [PASSED] VGA
[07:13:16] [PASSED] DVI-I
[07:13:16] [PASSED] DVI-D
[07:13:16] [PASSED] DVI-A
[07:13:16] [PASSED] Composite
[07:13:16] [PASSED] SVIDEO
[07:13:16] [PASSED] LVDS
[07:13:16] [PASSED] Component
[07:13:16] [PASSED] DIN
[07:13:16] [PASSED] DP
[07:13:16] [PASSED] HDMI-A
[07:13:16] [PASSED] HDMI-B
[07:13:16] [PASSED] TV
[07:13:16] [PASSED] eDP
[07:13:16] [PASSED] Virtual
[07:13:16] [PASSED] DSI
[07:13:16] [PASSED] DPI
[07:13:16] [PASSED] Writeback
[07:13:16] [PASSED] SPI
[07:13:16] [PASSED] USB
[07:13:16] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[07:13:16] ======== drm_test_drm_connector_dynamic_init_name =========
[07:13:16] [PASSED] Unknown
[07:13:16] [PASSED] VGA
[07:13:16] [PASSED] DVI-I
[07:13:16] [PASSED] DVI-D
[07:13:16] [PASSED] DVI-A
[07:13:16] [PASSED] Composite
[07:13:16] [PASSED] SVIDEO
[07:13:16] [PASSED] LVDS
[07:13:16] [PASSED] Component
[07:13:16] [PASSED] DIN
[07:13:16] [PASSED] DP
[07:13:16] [PASSED] HDMI-A
[07:13:16] [PASSED] HDMI-B
[07:13:16] [PASSED] TV
[07:13:16] [PASSED] eDP
[07:13:16] [PASSED] Virtual
[07:13:16] [PASSED] DSI
[07:13:16] [PASSED] DPI
[07:13:16] [PASSED] Writeback
[07:13:16] [PASSED] SPI
[07:13:16] [PASSED] USB
[07:13:16] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[07:13:16] =========== [PASSED] drm_connector_dynamic_init ============
[07:13:16] ==== drm_connector_dynamic_register_early (4 subtests) =====
[07:13:16] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[07:13:16] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[07:13:16] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[07:13:16] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[07:13:16] ====== [PASSED] drm_connector_dynamic_register_early =======
[07:13:16] ======= drm_connector_dynamic_register (7 subtests) ========
[07:13:16] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[07:13:16] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[07:13:16] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[07:13:16] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[07:13:16] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[07:13:16] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[07:13:16] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[07:13:16] ========= [PASSED] drm_connector_dynamic_register ==========
[07:13:16] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[07:13:16] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[07:13:16] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[07:13:16] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[07:13:16] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[07:13:16] ========== drm_test_get_tv_mode_from_name_valid ===========
[07:13:16] [PASSED] NTSC
[07:13:16] [PASSED] NTSC-443
[07:13:16] [PASSED] NTSC-J
[07:13:16] [PASSED] PAL
[07:13:16] [PASSED] PAL-M
[07:13:16] [PASSED] PAL-N
[07:13:16] [PASSED] SECAM
[07:13:16] [PASSED] Mono
[07:13:16] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[07:13:16] [PASSED] drm_test_get_tv_mode_from_name_truncated
[07:13:16] ============ [PASSED] drm_get_tv_mode_from_name ============
[07:13:16] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[07:13:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[07:13:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[07:13:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[07:13:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[07:13:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[07:13:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[07:13:16] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[07:13:16] [PASSED] VIC 96
[07:13:16] [PASSED] VIC 97
[07:13:16] [PASSED] VIC 101
[07:13:16] [PASSED] VIC 102
[07:13:16] [PASSED] VIC 106
[07:13:16] [PASSED] VIC 107
[07:13:16] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[07:13:16] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[07:13:16] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[07:13:16] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[07:13:16] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[07:13:16] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[07:13:16] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[07:13:16] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[07:13:16] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[07:13:16] [PASSED] Automatic
[07:13:16] [PASSED] Full
[07:13:16] [PASSED] Limited 16:235
[07:13:16] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[07:13:16] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[07:13:16] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[07:13:16] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[07:13:16] === drm_test_drm_hdmi_connector_get_output_format_name ====
[07:13:16] [PASSED] RGB
[07:13:16] [PASSED] YUV 4:2:0
[07:13:16] [PASSED] YUV 4:2:2
[07:13:16] [PASSED] YUV 4:4:4
[07:13:16] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[07:13:16] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[07:13:16] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[07:13:16] ============= drm_damage_helper (21 subtests) ==============
[07:13:16] [PASSED] drm_test_damage_iter_no_damage
[07:13:16] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[07:13:16] [PASSED] drm_test_damage_iter_no_damage_src_moved
[07:13:16] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[07:13:16] [PASSED] drm_test_damage_iter_no_damage_not_visible
[07:13:16] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[07:13:16] [PASSED] drm_test_damage_iter_no_damage_no_fb
[07:13:16] [PASSED] drm_test_damage_iter_simple_damage
[07:13:16] [PASSED] drm_test_damage_iter_single_damage
[07:13:16] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[07:13:16] [PASSED] drm_test_damage_iter_single_damage_outside_src
[07:13:16] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[07:13:16] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[07:13:16] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[07:13:16] [PASSED] drm_test_damage_iter_single_damage_src_moved
[07:13:16] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[07:13:16] [PASSED] drm_test_damage_iter_damage
[07:13:16] [PASSED] drm_test_damage_iter_damage_one_intersect
[07:13:16] [PASSED] drm_test_damage_iter_damage_one_outside
[07:13:16] [PASSED] drm_test_damage_iter_damage_src_moved
[07:13:16] [PASSED] drm_test_damage_iter_damage_not_visible
[07:13:16] ================ [PASSED] drm_damage_helper ================
[07:13:16] ============== drm_dp_mst_helper (3 subtests) ==============
[07:13:16] ============== drm_test_dp_mst_calc_pbn_mode ==============
[07:13:16] [PASSED] Clock 154000 BPP 30 DSC disabled
[07:13:16] [PASSED] Clock 234000 BPP 30 DSC disabled
[07:13:16] [PASSED] Clock 297000 BPP 24 DSC disabled
[07:13:16] [PASSED] Clock 332880 BPP 24 DSC enabled
[07:13:16] [PASSED] Clock 324540 BPP 24 DSC enabled
[07:13:16] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[07:13:16] ============== drm_test_dp_mst_calc_pbn_div ===============
[07:13:16] [PASSED] Link rate 2000000 lane count 4
[07:13:16] [PASSED] Link rate 2000000 lane count 2
[07:13:16] [PASSED] Link rate 2000000 lane count 1
[07:13:16] [PASSED] Link rate 1350000 lane count 4
[07:13:16] [PASSED] Link rate 1350000 lane count 2
[07:13:16] [PASSED] Link rate 1350000 lane count 1
[07:13:16] [PASSED] Link rate 1000000 lane count 4
[07:13:16] [PASSED] Link rate 1000000 lane count 2
[07:13:16] [PASSED] Link rate 1000000 lane count 1
[07:13:16] [PASSED] Link rate 810000 lane count 4
[07:13:16] [PASSED] Link rate 810000 lane count 2
[07:13:16] [PASSED] Link rate 810000 lane count 1
[07:13:16] [PASSED] Link rate 540000 lane count 4
[07:13:16] [PASSED] Link rate 540000 lane count 2
[07:13:16] [PASSED] Link rate 540000 lane count 1
[07:13:16] [PASSED] Link rate 270000 lane count 4
[07:13:16] [PASSED] Link rate 270000 lane count 2
[07:13:16] [PASSED] Link rate 270000 lane count 1
[07:13:16] [PASSED] Link rate 162000 lane count 4
[07:13:16] [PASSED] Link rate 162000 lane count 2
[07:13:16] [PASSED] Link rate 162000 lane count 1
[07:13:16] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[07:13:16] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[07:13:16] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[07:13:16] [PASSED] DP_POWER_UP_PHY with port number
[07:13:16] [PASSED] DP_POWER_DOWN_PHY with port number
[07:13:16] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[07:13:16] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[07:13:16] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[07:13:16] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[07:13:16] [PASSED] DP_QUERY_PAYLOAD with port number
[07:13:16] [PASSED] DP_QUERY_PAYLOAD with VCPI
[07:13:16] [PASSED] DP_REMOTE_DPCD_READ with port number
[07:13:16] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[07:13:16] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[07:13:16] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[07:13:16] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[07:13:16] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[07:13:16] [PASSED] DP_REMOTE_I2C_READ with port number
[07:13:16] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[07:13:16] [PASSED] DP_REMOTE_I2C_READ with transactions array
[07:13:16] [PASSED] DP_REMOTE_I2C_WRITE with port number
[07:13:16] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[07:13:16] [PASSED] DP_REMOTE_I2C_WRITE with data array
[07:13:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[07:13:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[07:13:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[07:13:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[07:13:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[07:13:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[07:13:16] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[07:13:16] ================ [PASSED] drm_dp_mst_helper ================
[07:13:16] ================== drm_exec (7 subtests) ===================
[07:13:16] [PASSED] sanitycheck
[07:13:16] [PASSED] test_lock
[07:13:16] [PASSED] test_lock_unlock
[07:13:16] [PASSED] test_duplicates
[07:13:16] [PASSED] test_prepare
[07:13:16] [PASSED] test_prepare_array
[07:13:16] [PASSED] test_multiple_loops
[07:13:16] ==================== [PASSED] drm_exec =====================
[07:13:16] =========== drm_format_helper_test (17 subtests) ===========
[07:13:16] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[07:13:16] [PASSED] single_pixel_source_buffer
[07:13:16] [PASSED] single_pixel_clip_rectangle
[07:13:16] [PASSED] well_known_colors
[07:13:16] [PASSED] destination_pitch
[07:13:16] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[07:13:16] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[07:13:16] [PASSED] single_pixel_source_buffer
[07:13:16] [PASSED] single_pixel_clip_rectangle
[07:13:16] [PASSED] well_known_colors
[07:13:16] [PASSED] destination_pitch
[07:13:16] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[07:13:16] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[07:13:16] [PASSED] single_pixel_source_buffer
[07:13:16] [PASSED] single_pixel_clip_rectangle
[07:13:16] [PASSED] well_known_colors
[07:13:16] [PASSED] destination_pitch
[07:13:16] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[07:13:16] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[07:13:16] [PASSED] single_pixel_source_buffer
[07:13:16] [PASSED] single_pixel_clip_rectangle
[07:13:16] [PASSED] well_known_colors
[07:13:16] [PASSED] destination_pitch
[07:13:16] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[07:13:16] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[07:13:16] [PASSED] single_pixel_source_buffer
[07:13:16] [PASSED] single_pixel_clip_rectangle
[07:13:16] [PASSED] well_known_colors
[07:13:16] [PASSED] destination_pitch
[07:13:16] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[07:13:16] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[07:13:16] [PASSED] single_pixel_source_buffer
[07:13:16] [PASSED] single_pixel_clip_rectangle
[07:13:16] [PASSED] well_known_colors
[07:13:16] [PASSED] destination_pitch
[07:13:16] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[07:13:16] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[07:13:16] [PASSED] single_pixel_source_buffer
[07:13:16] [PASSED] single_pixel_clip_rectangle
[07:13:16] [PASSED] well_known_colors
[07:13:16] [PASSED] destination_pitch
[07:13:16] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[07:13:16] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[07:13:16] [PASSED] single_pixel_source_buffer
[07:13:16] [PASSED] single_pixel_clip_rectangle
[07:13:16] [PASSED] well_known_colors
[07:13:16] [PASSED] destination_pitch
[07:13:16] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[07:13:16] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[07:13:16] [PASSED] single_pixel_source_buffer
[07:13:16] [PASSED] single_pixel_clip_rectangle
[07:13:16] [PASSED] well_known_colors
[07:13:16] [PASSED] destination_pitch
[07:13:16] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[07:13:16] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[07:13:16] [PASSED] single_pixel_source_buffer
[07:13:16] [PASSED] single_pixel_clip_rectangle
[07:13:16] [PASSED] well_known_colors
[07:13:16] [PASSED] destination_pitch
[07:13:16] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[07:13:16] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[07:13:16] [PASSED] single_pixel_source_buffer
[07:13:16] [PASSED] single_pixel_clip_rectangle
[07:13:16] [PASSED] well_known_colors
[07:13:16] [PASSED] destination_pitch
[07:13:16] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[07:13:16] ============== drm_test_fb_xrgb8888_to_mono ===============
[07:13:16] [PASSED] single_pixel_source_buffer
[07:13:16] [PASSED] single_pixel_clip_rectangle
[07:13:16] [PASSED] well_known_colors
[07:13:16] [PASSED] destination_pitch
[07:13:16] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[07:13:16] ==================== drm_test_fb_swab =====================
[07:13:16] [PASSED] single_pixel_source_buffer
[07:13:16] [PASSED] single_pixel_clip_rectangle
[07:13:16] [PASSED] well_known_colors
[07:13:16] [PASSED] destination_pitch
[07:13:16] ================ [PASSED] drm_test_fb_swab =================
[07:13:16] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[07:13:16] [PASSED] single_pixel_source_buffer
[07:13:16] [PASSED] single_pixel_clip_rectangle
[07:13:16] [PASSED] well_known_colors
[07:13:16] [PASSED] destination_pitch
[07:13:16] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[07:13:16] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[07:13:16] [PASSED] single_pixel_source_buffer
[07:13:16] [PASSED] single_pixel_clip_rectangle
[07:13:16] [PASSED] well_known_colors
[07:13:16] [PASSED] destination_pitch
[07:13:16] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[07:13:16] ================= drm_test_fb_clip_offset =================
[07:13:16] [PASSED] pass through
[07:13:16] [PASSED] horizontal offset
[07:13:16] [PASSED] vertical offset
[07:13:16] [PASSED] horizontal and vertical offset
[07:13:16] [PASSED] horizontal offset (custom pitch)
[07:13:16] [PASSED] vertical offset (custom pitch)
[07:13:16] [PASSED] horizontal and vertical offset (custom pitch)
[07:13:16] ============= [PASSED] drm_test_fb_clip_offset =============
[07:13:16] =================== drm_test_fb_memcpy ====================
[07:13:16] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[07:13:16] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[07:13:16] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[07:13:16] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[07:13:16] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[07:13:16] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[07:13:16] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[07:13:16] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[07:13:16] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[07:13:16] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[07:13:16] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[07:13:16] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[07:13:16] =============== [PASSED] drm_test_fb_memcpy ================
[07:13:16] ============= [PASSED] drm_format_helper_test ==============
[07:13:16] ================= drm_format (18 subtests) =================
[07:13:16] [PASSED] drm_test_format_block_width_invalid
[07:13:16] [PASSED] drm_test_format_block_width_one_plane
[07:13:16] [PASSED] drm_test_format_block_width_two_plane
[07:13:16] [PASSED] drm_test_format_block_width_three_plane
[07:13:16] [PASSED] drm_test_format_block_width_tiled
[07:13:16] [PASSED] drm_test_format_block_height_invalid
[07:13:16] [PASSED] drm_test_format_block_height_one_plane
[07:13:16] [PASSED] drm_test_format_block_height_two_plane
[07:13:16] [PASSED] drm_test_format_block_height_three_plane
[07:13:16] [PASSED] drm_test_format_block_height_tiled
[07:13:16] [PASSED] drm_test_format_min_pitch_invalid
[07:13:16] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[07:13:16] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[07:13:16] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[07:13:16] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[07:13:16] [PASSED] drm_test_format_min_pitch_two_plane
[07:13:16] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[07:13:16] [PASSED] drm_test_format_min_pitch_tiled
[07:13:16] =================== [PASSED] drm_format ====================
[07:13:16] ============== drm_framebuffer (10 subtests) ===============
[07:13:16] ========== drm_test_framebuffer_check_src_coords ==========
[07:13:16] [PASSED] Success: source fits into fb
[07:13:16] [PASSED] Fail: overflowing fb with x-axis coordinate
[07:13:16] [PASSED] Fail: overflowing fb with y-axis coordinate
[07:13:16] [PASSED] Fail: overflowing fb with source width
[07:13:16] [PASSED] Fail: overflowing fb with source height
[07:13:16] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[07:13:16] [PASSED] drm_test_framebuffer_cleanup
[07:13:16] =============== drm_test_framebuffer_create ===============
[07:13:16] [PASSED] ABGR8888 normal sizes
[07:13:16] [PASSED] ABGR8888 max sizes
[07:13:16] [PASSED] ABGR8888 pitch greater than min required
[07:13:16] [PASSED] ABGR8888 pitch less than min required
[07:13:16] [PASSED] ABGR8888 Invalid width
[07:13:16] [PASSED] ABGR8888 Invalid buffer handle
[07:13:16] [PASSED] No pixel format
[07:13:16] [PASSED] ABGR8888 Width 0
[07:13:16] [PASSED] ABGR8888 Height 0
[07:13:16] [PASSED] ABGR8888 Out of bound height * pitch combination
[07:13:16] [PASSED] ABGR8888 Large buffer offset
[07:13:16] [PASSED] ABGR8888 Buffer offset for inexistent plane
[07:13:16] [PASSED] ABGR8888 Invalid flag
[07:13:16] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[07:13:16] [PASSED] ABGR8888 Valid buffer modifier
[07:13:16] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[07:13:16] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[07:13:16] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[07:13:16] [PASSED] NV12 Normal sizes
[07:13:16] [PASSED] NV12 Max sizes
[07:13:16] [PASSED] NV12 Invalid pitch
[07:13:16] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[07:13:16] [PASSED] NV12 different modifier per-plane
[07:13:16] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[07:13:16] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[07:13:16] [PASSED] NV12 Modifier for inexistent plane
[07:13:16] [PASSED] NV12 Handle for inexistent plane
[07:13:16] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[07:13:16] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[07:13:16] [PASSED] YVU420 Normal sizes
[07:13:16] [PASSED] YVU420 Max sizes
[07:13:16] [PASSED] YVU420 Invalid pitch
[07:13:16] [PASSED] YVU420 Different pitches
[07:13:16] [PASSED] YVU420 Different buffer offsets/pitches
[07:13:16] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[07:13:16] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[07:13:16] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[07:13:16] [PASSED] YVU420 Valid modifier
[07:13:16] [PASSED] YVU420 Different modifiers per plane
[07:13:16] [PASSED] YVU420 Modifier for inexistent plane
[07:13:16] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[07:13:16] [PASSED] X0L2 Normal sizes
[07:13:16] [PASSED] X0L2 Max sizes
[07:13:16] [PASSED] X0L2 Invalid pitch
[07:13:16] [PASSED] X0L2 Pitch greater than minimum required
[07:13:16] [PASSED] X0L2 Handle for inexistent plane
[07:13:16] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[07:13:16] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[07:13:16] [PASSED] X0L2 Valid modifier
[07:13:16] [PASSED] X0L2 Modifier for inexistent plane
[07:13:16] =========== [PASSED] drm_test_framebuffer_create ===========
[07:13:16] [PASSED] drm_test_framebuffer_free
[07:13:16] [PASSED] drm_test_framebuffer_init
[07:13:16] [PASSED] drm_test_framebuffer_init_bad_format
[07:13:16] [PASSED] drm_test_framebuffer_init_dev_mismatch
[07:13:16] [PASSED] drm_test_framebuffer_lookup
[07:13:16] [PASSED] drm_test_framebuffer_lookup_inexistent
[07:13:16] [PASSED] drm_test_framebuffer_modifiers_not_supported
[07:13:16] ================= [PASSED] drm_framebuffer =================
[07:13:16] ================ drm_gem_shmem (8 subtests) ================
[07:13:16] [PASSED] drm_gem_shmem_test_obj_create
[07:13:16] [PASSED] drm_gem_shmem_test_obj_create_private
[07:13:16] [PASSED] drm_gem_shmem_test_pin_pages
[07:13:16] [PASSED] drm_gem_shmem_test_vmap
[07:13:16] [PASSED] drm_gem_shmem_test_get_pages_sgt
[07:13:16] [PASSED] drm_gem_shmem_test_get_sg_table
[07:13:16] [PASSED] drm_gem_shmem_test_madvise
[07:13:16] [PASSED] drm_gem_shmem_test_purge
[07:13:16] ================== [PASSED] drm_gem_shmem ==================
[07:13:16] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[07:13:16] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[07:13:16] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[07:13:16] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[07:13:16] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[07:13:16] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[07:13:16] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[07:13:16] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[07:13:16] [PASSED] Automatic
[07:13:16] [PASSED] Full
[07:13:16] [PASSED] Limited 16:235
[07:13:16] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[07:13:16] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[07:13:16] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[07:13:16] [PASSED] drm_test_check_disable_connector
[07:13:16] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[07:13:16] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[07:13:16] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[07:13:16] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[07:13:16] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[07:13:16] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[07:13:16] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[07:13:16] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[07:13:16] [PASSED] drm_test_check_output_bpc_dvi
[07:13:16] [PASSED] drm_test_check_output_bpc_format_vic_1
[07:13:16] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[07:13:16] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[07:13:16] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[07:13:16] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[07:13:16] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[07:13:16] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[07:13:16] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[07:13:16] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[07:13:16] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[07:13:16] [PASSED] drm_test_check_broadcast_rgb_value
[07:13:16] [PASSED] drm_test_check_bpc_8_value
[07:13:16] [PASSED] drm_test_check_bpc_10_value
[07:13:16] [PASSED] drm_test_check_bpc_12_value
[07:13:16] [PASSED] drm_test_check_format_value
[07:13:16] [PASSED] drm_test_check_tmds_char_value
[07:13:16] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[07:13:16] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[07:13:16] [PASSED] drm_test_check_mode_valid
[07:13:16] [PASSED] drm_test_check_mode_valid_reject
[07:13:16] [PASSED] drm_test_check_mode_valid_reject_rate
[07:13:16] [PASSED] drm_test_check_mode_valid_reject_max_clock
[07:13:16] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[07:13:16] ================= drm_managed (2 subtests) =================
[07:13:16] [PASSED] drm_test_managed_release_action
[07:13:16] [PASSED] drm_test_managed_run_action
[07:13:16] =================== [PASSED] drm_managed ===================
[07:13:16] =================== drm_mm (6 subtests) ====================
[07:13:16] [PASSED] drm_test_mm_init
[07:13:16] [PASSED] drm_test_mm_debug
[07:13:16] [PASSED] drm_test_mm_align32
[07:13:16] [PASSED] drm_test_mm_align64
[07:13:16] [PASSED] drm_test_mm_lowest
[07:13:16] [PASSED] drm_test_mm_highest
[07:13:16] ===================== [PASSED] drm_mm ======================
[07:13:16] ============= drm_modes_analog_tv (5 subtests) =============
[07:13:16] [PASSED] drm_test_modes_analog_tv_mono_576i
[07:13:16] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[07:13:16] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[07:13:16] [PASSED] drm_test_modes_analog_tv_pal_576i
[07:13:16] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[07:13:16] =============== [PASSED] drm_modes_analog_tv ===============
[07:13:16] ============== drm_plane_helper (2 subtests) ===============
[07:13:16] =============== drm_test_check_plane_state ================
[07:13:16] [PASSED] clipping_simple
[07:13:16] [PASSED] clipping_rotate_reflect
[07:13:16] [PASSED] positioning_simple
[07:13:16] [PASSED] upscaling
[07:13:16] [PASSED] downscaling
[07:13:16] [PASSED] rounding1
[07:13:16] [PASSED] rounding2
[07:13:16] [PASSED] rounding3
[07:13:16] [PASSED] rounding4
[07:13:16] =========== [PASSED] drm_test_check_plane_state ============
[07:13:16] =========== drm_test_check_invalid_plane_state ============
[07:13:16] [PASSED] positioning_invalid
[07:13:16] [PASSED] upscaling_invalid
[07:13:16] [PASSED] downscaling_invalid
[07:13:16] ======= [PASSED] drm_test_check_invalid_plane_state ========
[07:13:16] ================ [PASSED] drm_plane_helper =================
[07:13:16] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[07:13:16] ====== drm_test_connector_helper_tv_get_modes_check =======
[07:13:16] [PASSED] None
[07:13:16] [PASSED] PAL
[07:13:16] [PASSED] NTSC
[07:13:16] [PASSED] Both, NTSC Default
[07:13:16] [PASSED] Both, PAL Default
[07:13:16] [PASSED] Both, NTSC Default, with PAL on command-line
[07:13:16] [PASSED] Both, PAL Default, with NTSC on command-line
[07:13:16] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[07:13:16] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[07:13:16] ================== drm_rect (9 subtests) ===================
[07:13:16] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[07:13:16] [PASSED] drm_test_rect_clip_scaled_not_clipped
[07:13:16] [PASSED] drm_test_rect_clip_scaled_clipped
[07:13:16] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[07:13:16] ================= drm_test_rect_intersect =================
[07:13:16] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[07:13:16] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[07:13:16] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[07:13:16] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[07:13:16] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[07:13:16] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[07:13:16] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[07:13:16] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[07:13:16] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[07:13:16] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[07:13:16] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[07:13:16] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[07:13:16] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[07:13:16] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[07:13:16] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[07:13:16] ============= [PASSED] drm_test_rect_intersect =============
[07:13:16] ================ drm_test_rect_calc_hscale ================
[07:13:16] [PASSED] normal use
[07:13:16] [PASSED] out of max range
[07:13:16] [PASSED] out of min range
[07:13:16] [PASSED] zero dst
[07:13:16] [PASSED] negative src
[07:13:16] [PASSED] negative dst
[07:13:16] ============ [PASSED] drm_test_rect_calc_hscale ============
[07:13:16] ================ drm_test_rect_calc_vscale ================
[07:13:16] [PASSED] normal use
[07:13:16] [PASSED] out of max range
[07:13:16] [PASSED] out of min range
[07:13:16] [PASSED] zero dst
[07:13:16] [PASSED] negative src
stty: 'standard input': Inappropriate ioctl for device
[07:13:16] [PASSED] negative dst
[07:13:16] ============ [PASSED] drm_test_rect_calc_vscale ============
[07:13:16] ================== drm_test_rect_rotate ===================
[07:13:16] [PASSED] reflect-x
[07:13:16] [PASSED] reflect-y
[07:13:16] [PASSED] rotate-0
[07:13:16] [PASSED] rotate-90
[07:13:16] [PASSED] rotate-180
[07:13:16] [PASSED] rotate-270
[07:13:16] ============== [PASSED] drm_test_rect_rotate ===============
[07:13:16] ================ drm_test_rect_rotate_inv =================
[07:13:16] [PASSED] reflect-x
[07:13:16] [PASSED] reflect-y
[07:13:16] [PASSED] rotate-0
[07:13:16] [PASSED] rotate-90
[07:13:16] [PASSED] rotate-180
[07:13:16] [PASSED] rotate-270
[07:13:16] ============ [PASSED] drm_test_rect_rotate_inv =============
[07:13:16] ==================== [PASSED] drm_rect =====================
[07:13:16] ============ drm_sysfb_modeset_test (1 subtest) ============
[07:13:16] ============ drm_test_sysfb_build_fourcc_list =============
[07:13:16] [PASSED] no native formats
[07:13:16] [PASSED] XRGB8888 as native format
[07:13:16] [PASSED] remove duplicates
[07:13:16] [PASSED] convert alpha formats
[07:13:16] [PASSED] random formats
[07:13:16] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[07:13:16] ============= [PASSED] drm_sysfb_modeset_test ==============
[07:13:16] ============================================================
[07:13:16] Testing complete. Ran 621 tests: passed: 621
[07:13:16] Elapsed time: 25.802s total, 1.716s configuring, 23.863s building, 0.185s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[07:13:16] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[07:13:18] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[07:13:27] Starting KUnit Kernel (1/1)...
[07:13:27] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[07:13:27] ================= ttm_device (5 subtests) ==================
[07:13:27] [PASSED] ttm_device_init_basic
[07:13:27] [PASSED] ttm_device_init_multiple
[07:13:27] [PASSED] ttm_device_fini_basic
[07:13:27] [PASSED] ttm_device_init_no_vma_man
[07:13:27] ================== ttm_device_init_pools ==================
[07:13:27] [PASSED] No DMA allocations, no DMA32 required
[07:13:27] [PASSED] DMA allocations, DMA32 required
[07:13:27] [PASSED] No DMA allocations, DMA32 required
[07:13:27] [PASSED] DMA allocations, no DMA32 required
[07:13:27] ============== [PASSED] ttm_device_init_pools ==============
[07:13:27] =================== [PASSED] ttm_device ====================
[07:13:27] ================== ttm_pool (8 subtests) ===================
[07:13:27] ================== ttm_pool_alloc_basic ===================
[07:13:27] [PASSED] One page
[07:13:27] [PASSED] More than one page
[07:13:27] [PASSED] Above the allocation limit
[07:13:27] [PASSED] One page, with coherent DMA mappings enabled
[07:13:27] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[07:13:27] ============== [PASSED] ttm_pool_alloc_basic ===============
[07:13:27] ============== ttm_pool_alloc_basic_dma_addr ==============
[07:13:27] [PASSED] One page
[07:13:27] [PASSED] More than one page
[07:13:27] [PASSED] Above the allocation limit
[07:13:27] [PASSED] One page, with coherent DMA mappings enabled
[07:13:27] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[07:13:27] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[07:13:27] [PASSED] ttm_pool_alloc_order_caching_match
[07:13:27] [PASSED] ttm_pool_alloc_caching_mismatch
[07:13:27] [PASSED] ttm_pool_alloc_order_mismatch
[07:13:27] [PASSED] ttm_pool_free_dma_alloc
[07:13:27] [PASSED] ttm_pool_free_no_dma_alloc
[07:13:27] [PASSED] ttm_pool_fini_basic
[07:13:27] ==================== [PASSED] ttm_pool =====================
[07:13:27] ================ ttm_resource (8 subtests) =================
[07:13:27] ================= ttm_resource_init_basic =================
[07:13:27] [PASSED] Init resource in TTM_PL_SYSTEM
[07:13:27] [PASSED] Init resource in TTM_PL_VRAM
[07:13:27] [PASSED] Init resource in a private placement
[07:13:27] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[07:13:27] ============= [PASSED] ttm_resource_init_basic =============
[07:13:27] [PASSED] ttm_resource_init_pinned
[07:13:27] [PASSED] ttm_resource_fini_basic
[07:13:27] [PASSED] ttm_resource_manager_init_basic
[07:13:27] [PASSED] ttm_resource_manager_usage_basic
[07:13:27] [PASSED] ttm_resource_manager_set_used_basic
[07:13:27] [PASSED] ttm_sys_man_alloc_basic
[07:13:27] [PASSED] ttm_sys_man_free_basic
[07:13:27] ================== [PASSED] ttm_resource ===================
[07:13:27] =================== ttm_tt (15 subtests) ===================
[07:13:27] ==================== ttm_tt_init_basic ====================
[07:13:27] [PASSED] Page-aligned size
[07:13:27] [PASSED] Extra pages requested
[07:13:27] ================ [PASSED] ttm_tt_init_basic ================
[07:13:27] [PASSED] ttm_tt_init_misaligned
[07:13:27] [PASSED] ttm_tt_fini_basic
[07:13:27] [PASSED] ttm_tt_fini_sg
[07:13:27] [PASSED] ttm_tt_fini_shmem
[07:13:27] [PASSED] ttm_tt_create_basic
[07:13:27] [PASSED] ttm_tt_create_invalid_bo_type
[07:13:27] [PASSED] ttm_tt_create_ttm_exists
[07:13:27] [PASSED] ttm_tt_create_failed
[07:13:27] [PASSED] ttm_tt_destroy_basic
[07:13:27] [PASSED] ttm_tt_populate_null_ttm
[07:13:27] [PASSED] ttm_tt_populate_populated_ttm
[07:13:27] [PASSED] ttm_tt_unpopulate_basic
[07:13:27] [PASSED] ttm_tt_unpopulate_empty_ttm
[07:13:27] [PASSED] ttm_tt_swapin_basic
[07:13:27] ===================== [PASSED] ttm_tt ======================
[07:13:27] =================== ttm_bo (14 subtests) ===================
[07:13:27] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[07:13:27] [PASSED] Cannot be interrupted and sleeps
[07:13:27] [PASSED] Cannot be interrupted, locks straight away
[07:13:27] [PASSED] Can be interrupted, sleeps
[07:13:27] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[07:13:27] [PASSED] ttm_bo_reserve_locked_no_sleep
[07:13:27] [PASSED] ttm_bo_reserve_no_wait_ticket
[07:13:27] [PASSED] ttm_bo_reserve_double_resv
[07:13:27] [PASSED] ttm_bo_reserve_interrupted
[07:13:27] [PASSED] ttm_bo_reserve_deadlock
[07:13:27] [PASSED] ttm_bo_unreserve_basic
[07:13:27] [PASSED] ttm_bo_unreserve_pinned
[07:13:27] [PASSED] ttm_bo_unreserve_bulk
[07:13:27] [PASSED] ttm_bo_fini_basic
[07:13:27] [PASSED] ttm_bo_fini_shared_resv
[07:13:27] [PASSED] ttm_bo_pin_basic
[07:13:27] [PASSED] ttm_bo_pin_unpin_resource
[07:13:27] [PASSED] ttm_bo_multiple_pin_one_unpin
[07:13:27] ===================== [PASSED] ttm_bo ======================
[07:13:27] ============== ttm_bo_validate (21 subtests) ===============
[07:13:27] ============== ttm_bo_init_reserved_sys_man ===============
[07:13:27] [PASSED] Buffer object for userspace
[07:13:27] [PASSED] Kernel buffer object
[07:13:27] [PASSED] Shared buffer object
[07:13:27] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[07:13:27] ============== ttm_bo_init_reserved_mock_man ==============
[07:13:27] [PASSED] Buffer object for userspace
[07:13:27] [PASSED] Kernel buffer object
[07:13:27] [PASSED] Shared buffer object
[07:13:27] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[07:13:27] [PASSED] ttm_bo_init_reserved_resv
[07:13:27] ================== ttm_bo_validate_basic ==================
[07:13:27] [PASSED] Buffer object for userspace
[07:13:27] [PASSED] Kernel buffer object
[07:13:27] [PASSED] Shared buffer object
[07:13:27] ============== [PASSED] ttm_bo_validate_basic ==============
[07:13:27] [PASSED] ttm_bo_validate_invalid_placement
[07:13:27] ============= ttm_bo_validate_same_placement ==============
[07:13:27] [PASSED] System manager
[07:13:27] [PASSED] VRAM manager
[07:13:27] ========= [PASSED] ttm_bo_validate_same_placement ==========
[07:13:27] [PASSED] ttm_bo_validate_failed_alloc
[07:13:27] [PASSED] ttm_bo_validate_pinned
[07:13:27] [PASSED] ttm_bo_validate_busy_placement
[07:13:27] ================ ttm_bo_validate_multihop =================
[07:13:27] [PASSED] Buffer object for userspace
[07:13:27] [PASSED] Kernel buffer object
[07:13:27] [PASSED] Shared buffer object
[07:13:27] ============ [PASSED] ttm_bo_validate_multihop =============
[07:13:27] ========== ttm_bo_validate_no_placement_signaled ==========
[07:13:27] [PASSED] Buffer object in system domain, no page vector
[07:13:27] [PASSED] Buffer object in system domain with an existing page vector
[07:13:27] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[07:13:27] ======== ttm_bo_validate_no_placement_not_signaled ========
[07:13:27] [PASSED] Buffer object for userspace
[07:13:27] [PASSED] Kernel buffer object
[07:13:27] [PASSED] Shared buffer object
[07:13:27] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[07:13:27] [PASSED] ttm_bo_validate_move_fence_signaled
[07:13:27] ========= ttm_bo_validate_move_fence_not_signaled =========
[07:13:27] [PASSED] Waits for GPU
[07:13:27] [PASSED] Tries to lock straight away
[07:13:27] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[07:13:27] [PASSED] ttm_bo_validate_happy_evict
[07:13:27] [PASSED] ttm_bo_validate_all_pinned_evict
[07:13:27] [PASSED] ttm_bo_validate_allowed_only_evict
[07:13:27] [PASSED] ttm_bo_validate_deleted_evict
[07:13:27] [PASSED] ttm_bo_validate_busy_domain_evict
[07:13:27] [PASSED] ttm_bo_validate_evict_gutting
[07:13:27] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[07:13:27] ================= [PASSED] ttm_bo_validate =================
[07:13:27] ============================================================
[07:13:27] Testing complete. Ran 101 tests: passed: 101
[07:13:27] Elapsed time: 11.147s total, 1.779s configuring, 9.151s building, 0.185s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v5 2/6] drm/dp: Add helpers to query the branch DSC max throughput/line-width
2025-09-29 6:36 ` [PATCH v5 " Imre Deak
@ 2025-09-29 9:00 ` Dmitry Baryshkov
2025-09-29 10:10 ` Imre Deak
2025-09-29 10:12 ` Ville Syrjälä
1 sibling, 1 reply; 25+ messages in thread
From: Dmitry Baryshkov @ 2025-09-29 9:00 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx, intel-xe, dri-devel, Ville Syrjälä
On Mon, Sep 29, 2025 at 09:36:44AM +0300, Imre Deak wrote:
> Add helpers to query the DP DSC sink device's per-slice throughput as
> well as a DSC branch device's overall throughput and line-width
> capabilities.
>
> v2 (Ville):
> - Rename pixel_clock to peak_pixel_rate, document what the value means
> in case of MST tiled displays.
> - Fix name of drm_dp_dsc_branch_max_slice_throughput() to
> drm_dp_dsc_sink_max_slice_throughput().
> v3:
> - Fix the DSC branch device minimum valid line width value from 2560
> to 5120 pixels.
> - Fix drm_dp_dsc_sink_max_slice_throughput()'s pixel_clock parameter
> name to peak_pixel_rate in header file.
> - Add handling for throughput mode 0 granular delta, defined by DP
> Standard v2.1a.
This one got sent as a separate V5, without a proper changelog. What has
changed?
>
> Cc: dri-devel@lists.freedesktop.org
> Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/display/drm_dp_helper.c | 156 ++++++++++++++++++++++++
> include/drm/display/drm_dp.h | 3 +
> include/drm/display/drm_dp_helper.h | 5 +
> 3 files changed, 164 insertions(+)
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 25+ messages in thread
* ✓ Xe.CI.BAT: success for drm/i915/dp: Work around a DSC pixel throughput issue (rev6)
2025-09-26 21:12 [PATCH v4 0/6] drm/i915/dp: Work around a DSC pixel throughput issue Imre Deak
` (11 preceding siblings ...)
2025-09-29 7:13 ` ✓ CI.KUnit: success " Patchwork
@ 2025-09-29 9:22 ` Patchwork
2025-09-29 9:40 ` ✓ Xe.CI.Full: " Patchwork
2025-09-29 21:47 ` [PATCH v4 0/6] drm/i915/dp: Work around a DSC pixel throughput issue Sharma, Swati2
14 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2025-09-29 9:22 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 1600 bytes --]
== Series Details ==
Series: drm/i915/dp: Work around a DSC pixel throughput issue (rev6)
URL : https://patchwork.freedesktop.org/series/154737/
State : success
== Summary ==
CI Bug Log - changes from xe-3836-e2a896e95ea5f65aa137dcf117bfd0d61176c8ce_BAT -> xe-pw-154737v6_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in xe-pw-154737v6_BAT that come from known issues:
### IGT changes ###
#### Possible fixes ####
* igt@xe_pat@pat-index-xe2@render:
- bat-bmg-1: [FAIL][1] ([Intel XE#5507]) -> [PASS][2] +1 other test pass
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3836-e2a896e95ea5f65aa137dcf117bfd0d61176c8ce/bat-bmg-1/igt@xe_pat@pat-index-xe2@render.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/bat-bmg-1/igt@xe_pat@pat-index-xe2@render.html
[Intel XE#5507]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5507
Build changes
-------------
* IGT: IGT_8555 -> IGT_8556
* Linux: xe-3836-e2a896e95ea5f65aa137dcf117bfd0d61176c8ce -> xe-pw-154737v6
IGT_8555: 8555
IGT_8556: e5eda2a187432a54f5e6fada18e4187e5175a10c @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-3836-e2a896e95ea5f65aa137dcf117bfd0d61176c8ce: e2a896e95ea5f65aa137dcf117bfd0d61176c8ce
xe-pw-154737v6: 154737v6
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/index.html
[-- Attachment #2: Type: text/html, Size: 2179 bytes --]
^ permalink raw reply [flat|nested] 25+ messages in thread
* ✓ Xe.CI.Full: success for drm/i915/dp: Work around a DSC pixel throughput issue (rev6)
2025-09-26 21:12 [PATCH v4 0/6] drm/i915/dp: Work around a DSC pixel throughput issue Imre Deak
` (12 preceding siblings ...)
2025-09-29 9:22 ` ✓ Xe.CI.BAT: " Patchwork
@ 2025-09-29 9:40 ` Patchwork
2025-09-29 21:47 ` [PATCH v4 0/6] drm/i915/dp: Work around a DSC pixel throughput issue Sharma, Swati2
14 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2025-09-29 9:40 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 44513 bytes --]
== Series Details ==
Series: drm/i915/dp: Work around a DSC pixel throughput issue (rev6)
URL : https://patchwork.freedesktop.org/series/154737/
State : success
== Summary ==
CI Bug Log - changes from xe-3836-e2a896e95ea5f65aa137dcf117bfd0d61176c8ce_FULL -> xe-pw-154737v6_FULL
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (4 -> 4)
------------------------------
No changes in participating hosts
New tests
---------
New tests have been introduced between xe-3836-e2a896e95ea5f65aa137dcf117bfd0d61176c8ce_FULL and xe-pw-154737v6_FULL:
### New IGT tests (4) ###
* igt@kms_lease@page-flip-implicit-plane@pipe-a-dp-4:
- Statuses : 1 pass(s)
- Exec time: [0.32] s
* igt@kms_lease@page-flip-implicit-plane@pipe-b-dp-4:
- Statuses : 1 pass(s)
- Exec time: [0.27] s
* igt@kms_lease@page-flip-implicit-plane@pipe-c-dp-4:
- Statuses : 1 pass(s)
- Exec time: [0.27] s
* igt@kms_lease@page-flip-implicit-plane@pipe-d-dp-4:
- Statuses : 1 pass(s)
- Exec time: [0.28] s
Known issues
------------
Here are the changes found in xe-pw-154737v6_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_async_flips@async-flip-with-page-flip-events-linear-atomic@pipe-c-edp-1:
- shard-lnl: NOTRUN -> [FAIL][1] ([Intel XE#6054]) +3 other tests fail
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-lnl-1/igt@kms_async_flips@async-flip-with-page-flip-events-linear-atomic@pipe-c-edp-1.html
* igt@kms_atomic@test-only:
- shard-adlp: [PASS][2] -> [DMESG-WARN][3] ([Intel XE#2953] / [Intel XE#4173])
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3836-e2a896e95ea5f65aa137dcf117bfd0d61176c8ce/shard-adlp-1/igt@kms_atomic@test-only.html
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-adlp-3/igt@kms_atomic@test-only.html
* igt@kms_big_fb@linear-8bpp-rotate-270:
- shard-dg2-set2: NOTRUN -> [SKIP][4] ([Intel XE#316])
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-dg2-432/igt@kms_big_fb@linear-8bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-bmg: NOTRUN -> [SKIP][5] ([Intel XE#1124]) +2 other tests skip
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-bmg-6/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-0:
- shard-lnl: NOTRUN -> [SKIP][6] ([Intel XE#1124]) +1 other test skip
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-lnl-1/igt@kms_big_fb@yf-tiled-16bpp-rotate-0.html
* igt@kms_bw@connected-linear-tiling-4-displays-1920x1080p:
- shard-lnl: NOTRUN -> [SKIP][7] ([Intel XE#1512])
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-lnl-7/igt@kms_bw@connected-linear-tiling-4-displays-1920x1080p.html
* igt@kms_bw@linear-tiling-1-displays-2560x1440p:
- shard-dg2-set2: NOTRUN -> [SKIP][8] ([Intel XE#367])
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-dg2-463/igt@kms_bw@linear-tiling-1-displays-2560x1440p.html
* igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs:
- shard-bmg: NOTRUN -> [SKIP][9] ([Intel XE#2887]) +2 other tests skip
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-bmg-7/igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs.html
* igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs@pipe-c-dp-2:
- shard-bmg: NOTRUN -> [SKIP][10] ([Intel XE#2652] / [Intel XE#787]) +7 other tests skip
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-bmg-4/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs@pipe-c-dp-2.html
* igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc@pipe-b-dp-2:
- shard-dg2-set2: NOTRUN -> [SKIP][11] ([Intel XE#787]) +97 other tests skip
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-dg2-432/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc@pipe-b-dp-2.html
* igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs:
- shard-lnl: NOTRUN -> [SKIP][12] ([Intel XE#3432])
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-lnl-1/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs.html
* igt@kms_ccs@random-ccs-data-y-tiled-ccs@pipe-d-dp-2:
- shard-dg2-set2: NOTRUN -> [SKIP][13] ([Intel XE#455] / [Intel XE#787]) +15 other tests skip
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-dg2-432/igt@kms_ccs@random-ccs-data-y-tiled-ccs@pipe-d-dp-2.html
* igt@kms_chamelium_color@ctm-red-to-blue:
- shard-lnl: NOTRUN -> [SKIP][14] ([Intel XE#306])
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-lnl-3/igt@kms_chamelium_color@ctm-red-to-blue.html
* igt@kms_chamelium_edid@dp-edid-resolution-list:
- shard-bmg: NOTRUN -> [SKIP][15] ([Intel XE#2252]) +1 other test skip
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-bmg-8/igt@kms_chamelium_edid@dp-edid-resolution-list.html
* igt@kms_chamelium_frames@hdmi-crc-single:
- shard-adlp: NOTRUN -> [SKIP][16] ([Intel XE#373])
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-adlp-3/igt@kms_chamelium_frames@hdmi-crc-single.html
- shard-dg2-set2: NOTRUN -> [SKIP][17] ([Intel XE#373])
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-dg2-433/igt@kms_chamelium_frames@hdmi-crc-single.html
- shard-lnl: NOTRUN -> [SKIP][18] ([Intel XE#373]) +1 other test skip
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-lnl-2/igt@kms_chamelium_frames@hdmi-crc-single.html
* igt@kms_content_protection@lic-type-1:
- shard-dg2-set2: NOTRUN -> [SKIP][19] ([Intel XE#455]) +4 other tests skip
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-dg2-435/igt@kms_content_protection@lic-type-1.html
- shard-lnl: NOTRUN -> [SKIP][20] ([Intel XE#3278])
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-lnl-8/igt@kms_content_protection@lic-type-1.html
- shard-bmg: NOTRUN -> [SKIP][21] ([Intel XE#2341])
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-bmg-6/igt@kms_content_protection@lic-type-1.html
- shard-adlp: NOTRUN -> [SKIP][22] ([Intel XE#455])
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-adlp-4/igt@kms_content_protection@lic-type-1.html
* igt@kms_cursor_crc@cursor-random-128x42:
- shard-bmg: NOTRUN -> [SKIP][23] ([Intel XE#2320])
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-bmg-4/igt@kms_cursor_crc@cursor-random-128x42.html
* igt@kms_cursor_crc@cursor-random-512x512:
- shard-bmg: NOTRUN -> [SKIP][24] ([Intel XE#2321])
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-bmg-2/igt@kms_cursor_crc@cursor-random-512x512.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size:
- shard-bmg: [PASS][25] -> [SKIP][26] ([Intel XE#2291])
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3836-e2a896e95ea5f65aa137dcf117bfd0d61176c8ce/shard-bmg-7/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-bmg: [PASS][27] -> [FAIL][28] ([Intel XE#1475])
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3836-e2a896e95ea5f65aa137dcf117bfd0d61176c8ce/shard-bmg-3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-bmg-8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
- shard-bmg: NOTRUN -> [SKIP][29] ([Intel XE#1508])
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-bmg-2/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html
* igt@kms_dsc@dsc-with-bpc-formats:
- shard-lnl: NOTRUN -> [SKIP][30] ([Intel XE#2244])
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-lnl-1/igt@kms_dsc@dsc-with-bpc-formats.html
* igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-dirtyfb-tests:
- shard-bmg: NOTRUN -> [SKIP][31] ([Intel XE#4422])
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-bmg-6/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-dirtyfb-tests.html
* igt@kms_flip@2x-flip-vs-panning-vs-hang:
- shard-bmg: [PASS][32] -> [SKIP][33] ([Intel XE#2316])
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3836-e2a896e95ea5f65aa137dcf117bfd0d61176c8ce/shard-bmg-8/igt@kms_flip@2x-flip-vs-panning-vs-hang.html
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-bmg-6/igt@kms_flip@2x-flip-vs-panning-vs-hang.html
* igt@kms_flip@2x-flip-vs-suspend:
- shard-lnl: NOTRUN -> [SKIP][34] ([Intel XE#1421]) +2 other tests skip
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-lnl-7/igt@kms_flip@2x-flip-vs-suspend.html
* igt@kms_flip@2x-flip-vs-wf_vblank:
- shard-adlp: NOTRUN -> [SKIP][35] ([Intel XE#310]) +1 other test skip
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-adlp-3/igt@kms_flip@2x-flip-vs-wf_vblank.html
* igt@kms_flip@basic-plain-flip:
- shard-adlp: [PASS][36] -> [DMESG-WARN][37] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#4543])
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3836-e2a896e95ea5f65aa137dcf117bfd0d61176c8ce/shard-adlp-1/igt@kms_flip@basic-plain-flip.html
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-adlp-9/igt@kms_flip@basic-plain-flip.html
* igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-hdmi-a1:
- shard-adlp: [PASS][38] -> [DMESG-WARN][39] ([Intel XE#4543]) +8 other tests dmesg-warn
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3836-e2a896e95ea5f65aa137dcf117bfd0d61176c8ce/shard-adlp-6/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-hdmi-a1.html
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-adlp-2/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-hdmi-a1.html
* igt@kms_flip@flip-vs-expired-vblank@c-edp1:
- shard-lnl: [PASS][40] -> [FAIL][41] ([Intel XE#301] / [Intel XE#3149])
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3836-e2a896e95ea5f65aa137dcf117bfd0d61176c8ce/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling:
- shard-bmg: NOTRUN -> [SKIP][42] ([Intel XE#2293] / [Intel XE#2380]) +1 other test skip
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-bmg-5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html
- shard-lnl: NOTRUN -> [SKIP][43] ([Intel XE#1401] / [Intel XE#1745])
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-lnl-2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling@pipe-a-default-mode:
- shard-lnl: NOTRUN -> [SKIP][44] ([Intel XE#1401])
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-lnl-2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling@pipe-a-valid-mode:
- shard-bmg: NOTRUN -> [SKIP][45] ([Intel XE#2293]) +1 other test skip
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-bmg-5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt:
- shard-bmg: NOTRUN -> [SKIP][46] ([Intel XE#5390]) +1 other test skip
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt:
- shard-lnl: NOTRUN -> [SKIP][47] ([Intel XE#656]) +6 other tests skip
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-lnl-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-plflip-blt:
- shard-adlp: NOTRUN -> [SKIP][48] ([Intel XE#656]) +1 other test skip
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-adlp-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-plflip-blt.html
- shard-bmg: NOTRUN -> [SKIP][49] ([Intel XE#2312]) +1 other test skip
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscren-pri-indfb-draw-mmap-wc:
- shard-adlp: NOTRUN -> [SKIP][50] ([Intel XE#651])
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-adlp-4/igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscren-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc:
- shard-bmg: NOTRUN -> [SKIP][51] ([Intel XE#2311]) +6 other tests skip
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-plflip-blt:
- shard-dg2-set2: NOTRUN -> [SKIP][52] ([Intel XE#651]) +5 other tests skip
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-dg2-463/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-mmap-wc:
- shard-lnl: NOTRUN -> [SKIP][53] ([Intel XE#651]) +1 other test skip
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-lnl-2/igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render:
- shard-bmg: NOTRUN -> [SKIP][54] ([Intel XE#2313]) +6 other tests skip
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-blt:
- shard-dg2-set2: NOTRUN -> [SKIP][55] ([Intel XE#653]) +4 other tests skip
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-dg2-433/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-blt.html
* igt@kms_pm_dc@dc3co-vpb-simulation:
- shard-bmg: NOTRUN -> [SKIP][56] ([Intel XE#2391])
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-bmg-5/igt@kms_pm_dc@dc3co-vpb-simulation.html
* igt@kms_pm_dc@dc6-psr:
- shard-dg2-set2: NOTRUN -> [SKIP][57] ([Intel XE#1129])
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-dg2-433/igt@kms_pm_dc@dc6-psr.html
* igt@kms_pm_rpm@modeset-lpsp:
- shard-bmg: NOTRUN -> [SKIP][58] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#836])
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-bmg-2/igt@kms_pm_rpm@modeset-lpsp.html
* igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-continuous-sf:
- shard-lnl: NOTRUN -> [SKIP][59] ([Intel XE#1406] / [Intel XE#2893] / [Intel XE#4608])
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-lnl-1/igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-continuous-sf.html
- shard-adlp: NOTRUN -> [SKIP][60] ([Intel XE#1406] / [Intel XE#1489])
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-adlp-3/igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-continuous-sf.html
* igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-continuous-sf@pipe-a-edp-1:
- shard-lnl: NOTRUN -> [SKIP][61] ([Intel XE#1406] / [Intel XE#4608]) +1 other test skip
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-lnl-1/igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-continuous-sf@pipe-a-edp-1.html
* igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area:
- shard-bmg: NOTRUN -> [SKIP][62] ([Intel XE#1406] / [Intel XE#1489]) +2 other tests skip
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-bmg-8/igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area.html
* igt@kms_psr2_sf@pr-plane-move-sf-dmg-area:
- shard-lnl: NOTRUN -> [SKIP][63] ([Intel XE#1406] / [Intel XE#2893])
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-lnl-8/igt@kms_psr2_sf@pr-plane-move-sf-dmg-area.html
* igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-fully-sf:
- shard-dg2-set2: NOTRUN -> [SKIP][64] ([Intel XE#1406] / [Intel XE#1489]) +4 other tests skip
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-dg2-466/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr@fbc-pr-dpms:
- shard-dg2-set2: NOTRUN -> [SKIP][65] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) +1 other test skip
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-dg2-435/igt@kms_psr@fbc-pr-dpms.html
- shard-lnl: NOTRUN -> [SKIP][66] ([Intel XE#1406]) +2 other tests skip
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-lnl-8/igt@kms_psr@fbc-pr-dpms.html
- shard-adlp: NOTRUN -> [SKIP][67] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) +1 other test skip
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-adlp-4/igt@kms_psr@fbc-pr-dpms.html
* igt@kms_psr@fbc-psr2-dpms@edp-1:
- shard-lnl: NOTRUN -> [SKIP][68] ([Intel XE#1406] / [Intel XE#4609])
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-lnl-1/igt@kms_psr@fbc-psr2-dpms@edp-1.html
* igt@kms_psr@pr-sprite-plane-onoff:
- shard-bmg: NOTRUN -> [SKIP][69] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +2 other tests skip
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-bmg-8/igt@kms_psr@pr-sprite-plane-onoff.html
* igt@kms_rotation_crc@bad-pixel-format:
- shard-adlp: NOTRUN -> [SKIP][70] ([Intel XE#3414])
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-adlp-9/igt@kms_rotation_crc@bad-pixel-format.html
- shard-bmg: NOTRUN -> [SKIP][71] ([Intel XE#3414] / [Intel XE#3904])
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-bmg-5/igt@kms_rotation_crc@bad-pixel-format.html
- shard-dg2-set2: NOTRUN -> [SKIP][72] ([Intel XE#3414])
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-dg2-436/igt@kms_rotation_crc@bad-pixel-format.html
- shard-lnl: NOTRUN -> [SKIP][73] ([Intel XE#3414] / [Intel XE#3904])
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-lnl-2/igt@kms_rotation_crc@bad-pixel-format.html
* igt@kms_vrr@lobf:
- shard-bmg: NOTRUN -> [SKIP][74] ([Intel XE#2168])
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-bmg-1/igt@kms_vrr@lobf.html
* igt@kms_vrr@negative-basic:
- shard-bmg: [PASS][75] -> [SKIP][76] ([Intel XE#1499])
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3836-e2a896e95ea5f65aa137dcf117bfd0d61176c8ce/shard-bmg-5/igt@kms_vrr@negative-basic.html
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-bmg-6/igt@kms_vrr@negative-basic.html
* igt@xe_compute_preempt@compute-preempt-many-all-ram@engine-drm_xe_engine_class_compute:
- shard-dg2-set2: NOTRUN -> [FAIL][77] ([Intel XE#5890]) +1 other test fail
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-dg2-436/igt@xe_compute_preempt@compute-preempt-many-all-ram@engine-drm_xe_engine_class_compute.html
* igt@xe_eudebug@basic-vm-access-parameters-userptr-faultable:
- shard-dg2-set2: NOTRUN -> [SKIP][78] ([Intel XE#4837]) +1 other test skip
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-dg2-464/igt@xe_eudebug@basic-vm-access-parameters-userptr-faultable.html
* igt@xe_eudebug@vm-bind-clear:
- shard-adlp: NOTRUN -> [SKIP][79] ([Intel XE#4837] / [Intel XE#5565])
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-adlp-3/igt@xe_eudebug@vm-bind-clear.html
- shard-lnl: NOTRUN -> [SKIP][80] ([Intel XE#4837])
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-lnl-1/igt@xe_eudebug@vm-bind-clear.html
* igt@xe_eudebug_online@writes-caching-vram-bb-vram-target-vram:
- shard-bmg: NOTRUN -> [SKIP][81] ([Intel XE#4837]) +2 other tests skip
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-bmg-7/igt@xe_eudebug_online@writes-caching-vram-bb-vram-target-vram.html
* igt@xe_eudebug_sriov@deny-sriov:
- shard-lnl: NOTRUN -> [SKIP][82] ([Intel XE#4518])
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-lnl-2/igt@xe_eudebug_sriov@deny-sriov.html
* igt@xe_evict@evict-small-external-cm:
- shard-lnl: NOTRUN -> [SKIP][83] ([Intel XE#688])
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-lnl-1/igt@xe_evict@evict-small-external-cm.html
* igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-invalidate:
- shard-lnl: NOTRUN -> [SKIP][84] ([Intel XE#1392])
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-lnl-4/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-invalidate.html
* igt@xe_exec_basic@multigpu-once-bindexecqueue:
- shard-dg2-set2: [PASS][85] -> [SKIP][86] ([Intel XE#1392]) +2 other tests skip
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3836-e2a896e95ea5f65aa137dcf117bfd0d61176c8ce/shard-dg2-435/igt@xe_exec_basic@multigpu-once-bindexecqueue.html
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-dg2-432/igt@xe_exec_basic@multigpu-once-bindexecqueue.html
* igt@xe_exec_basic@multigpu-once-bindexecqueue-rebind:
- shard-bmg: NOTRUN -> [SKIP][87] ([Intel XE#2322])
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-bmg-8/igt@xe_exec_basic@multigpu-once-bindexecqueue-rebind.html
* igt@xe_exec_fault_mode@many-userptr-invalidate:
- shard-adlp: NOTRUN -> [SKIP][88] ([Intel XE#288] / [Intel XE#5561])
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-adlp-3/igt@xe_exec_fault_mode@many-userptr-invalidate.html
* igt@xe_exec_fault_mode@once-rebind-imm:
- shard-dg2-set2: NOTRUN -> [SKIP][89] ([Intel XE#288]) +6 other tests skip
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-dg2-464/igt@xe_exec_fault_mode@once-rebind-imm.html
* igt@xe_exec_system_allocator@many-stride-malloc-busy:
- shard-dg2-set2: NOTRUN -> [SKIP][90] ([Intel XE#4915]) +42 other tests skip
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-dg2-434/igt@xe_exec_system_allocator@many-stride-malloc-busy.html
* igt@xe_exec_system_allocator@many-stride-mmap-free-huge-nomemset:
- shard-lnl: NOTRUN -> [SKIP][91] ([Intel XE#4943]) +1 other test skip
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-lnl-1/igt@xe_exec_system_allocator@many-stride-mmap-free-huge-nomemset.html
* igt@xe_exec_system_allocator@threads-shared-vm-many-execqueues-malloc:
- shard-adlp: NOTRUN -> [SKIP][92] ([Intel XE#4915]) +11 other tests skip
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-adlp-2/igt@xe_exec_system_allocator@threads-shared-vm-many-execqueues-malloc.html
* igt@xe_exec_system_allocator@threads-shared-vm-many-mmap-new-huge:
- shard-bmg: NOTRUN -> [SKIP][93] ([Intel XE#4943]) +5 other tests skip
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-bmg-1/igt@xe_exec_system_allocator@threads-shared-vm-many-mmap-new-huge.html
* igt@xe_mmap@small-bar:
- shard-dg2-set2: NOTRUN -> [SKIP][94] ([Intel XE#512])
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-dg2-466/igt@xe_mmap@small-bar.html
* igt@xe_pat@pat-index-xehpc:
- shard-lnl: NOTRUN -> [SKIP][95] ([Intel XE#1420] / [Intel XE#2838])
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-lnl-1/igt@xe_pat@pat-index-xehpc.html
* igt@xe_pm@s2idle-vm-bind-prefetch:
- shard-lnl: [PASS][96] -> [ABORT][97] ([Intel XE#4847])
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3836-e2a896e95ea5f65aa137dcf117bfd0d61176c8ce/shard-lnl-8/igt@xe_pm@s2idle-vm-bind-prefetch.html
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-lnl-7/igt@xe_pm@s2idle-vm-bind-prefetch.html
* igt@xe_pmu@engine-activity-all-load-idle:
- shard-bmg: NOTRUN -> [DMESG-WARN][98] ([Intel XE#6190])
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-bmg-1/igt@xe_pmu@engine-activity-all-load-idle.html
* igt@xe_pxp@pxp-stale-bo-exec-post-rpm:
- shard-dg2-set2: NOTRUN -> [SKIP][99] ([Intel XE#4733])
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-dg2-432/igt@xe_pxp@pxp-stale-bo-exec-post-rpm.html
* igt@xe_query@multigpu-query-cs-cycles:
- shard-lnl: NOTRUN -> [SKIP][100] ([Intel XE#944])
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-lnl-1/igt@xe_query@multigpu-query-cs-cycles.html
* igt@xe_query@multigpu-query-invalid-extension:
- shard-bmg: NOTRUN -> [SKIP][101] ([Intel XE#944])
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-bmg-3/igt@xe_query@multigpu-query-invalid-extension.html
* igt@xe_sriov_auto_provisioning@fair-allocation:
- shard-lnl: NOTRUN -> [SKIP][102] ([Intel XE#4130])
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-lnl-7/igt@xe_sriov_auto_provisioning@fair-allocation.html
#### Possible fixes ####
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc:
- shard-dg2-set2: [INCOMPLETE][103] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4345] / [Intel XE#4522]) -> [PASS][104]
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3836-e2a896e95ea5f65aa137dcf117bfd0d61176c8ce/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-d-dp-4:
- shard-dg2-set2: [INCOMPLETE][105] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4522]) -> [PASS][106]
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3836-e2a896e95ea5f65aa137dcf117bfd0d61176c8ce/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-d-dp-4.html
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-d-dp-4.html
* igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-1:
- shard-adlp: [DMESG-WARN][107] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][108] +3 other tests pass
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3836-e2a896e95ea5f65aa137dcf117bfd0d61176c8ce/shard-adlp-4/igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-1.html
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-adlp-8/igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-1.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-lnl: [FAIL][109] ([Intel XE#301]) -> [PASS][110]
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3836-e2a896e95ea5f65aa137dcf117bfd0d61176c8ce/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-adlp: [DMESG-WARN][111] ([Intel XE#4543]) -> [PASS][112] +4 other tests pass
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3836-e2a896e95ea5f65aa137dcf117bfd0d61176c8ce/shard-adlp-1/igt@kms_flip@flip-vs-suspend-interruptible.html
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-adlp-8/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_plane_cursor@viewport:
- shard-dg2-set2: [FAIL][113] ([Intel XE#616]) -> [PASS][114] +1 other test pass
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3836-e2a896e95ea5f65aa137dcf117bfd0d61176c8ce/shard-dg2-433/igt@kms_plane_cursor@viewport.html
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-dg2-463/igt@kms_plane_cursor@viewport.html
* igt@kms_pm_dc@dc5-psr:
- shard-lnl: [FAIL][115] ([Intel XE#718]) -> [PASS][116]
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3836-e2a896e95ea5f65aa137dcf117bfd0d61176c8ce/shard-lnl-5/igt@kms_pm_dc@dc5-psr.html
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-lnl-1/igt@kms_pm_dc@dc5-psr.html
* igt@xe_exec_basic@multigpu-no-exec-basic:
- shard-dg2-set2: [SKIP][117] ([Intel XE#1392]) -> [PASS][118] +4 other tests pass
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3836-e2a896e95ea5f65aa137dcf117bfd0d61176c8ce/shard-dg2-432/igt@xe_exec_basic@multigpu-no-exec-basic.html
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-dg2-436/igt@xe_exec_basic@multigpu-no-exec-basic.html
* igt@xe_exec_compute_mode@many-execqueues-basic:
- shard-adlp: [FAIL][119] -> [PASS][120]
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3836-e2a896e95ea5f65aa137dcf117bfd0d61176c8ce/shard-adlp-2/igt@xe_exec_compute_mode@many-execqueues-basic.html
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-adlp-9/igt@xe_exec_compute_mode@many-execqueues-basic.html
- shard-bmg: [FAIL][121] -> [PASS][122]
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3836-e2a896e95ea5f65aa137dcf117bfd0d61176c8ce/shard-bmg-1/igt@xe_exec_compute_mode@many-execqueues-basic.html
[122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-bmg-2/igt@xe_exec_compute_mode@many-execqueues-basic.html
* {igt@xe_exec_system_allocator@many-large-new-prefetch}:
- shard-bmg: [CRASH][123] ([Intel XE#6192]) -> [PASS][124] +1 other test pass
[123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3836-e2a896e95ea5f65aa137dcf117bfd0d61176c8ce/shard-bmg-3/igt@xe_exec_system_allocator@many-large-new-prefetch.html
[124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-bmg-1/igt@xe_exec_system_allocator@many-large-new-prefetch.html
* {igt@xe_exec_system_allocator@once-new-prefetch}:
- shard-lnl: [CRASH][125] ([Intel XE#6192]) -> [PASS][126] +1 other test pass
[125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3836-e2a896e95ea5f65aa137dcf117bfd0d61176c8ce/shard-lnl-1/igt@xe_exec_system_allocator@once-new-prefetch.html
[126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-lnl-1/igt@xe_exec_system_allocator@once-new-prefetch.html
* igt@xe_exec_threads@threads-mixed-userptr-rebind:
- shard-adlp: [DMESG-FAIL][127] ([Intel XE#3876]) -> [PASS][128]
[127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3836-e2a896e95ea5f65aa137dcf117bfd0d61176c8ce/shard-adlp-2/igt@xe_exec_threads@threads-mixed-userptr-rebind.html
[128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-adlp-9/igt@xe_exec_threads@threads-mixed-userptr-rebind.html
- shard-bmg: [DMESG-FAIL][129] ([Intel XE#3876]) -> [PASS][130]
[129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3836-e2a896e95ea5f65aa137dcf117bfd0d61176c8ce/shard-bmg-1/igt@xe_exec_threads@threads-mixed-userptr-rebind.html
[130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-bmg-2/igt@xe_exec_threads@threads-mixed-userptr-rebind.html
#### Warnings ####
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-adlp: [DMESG-FAIL][131] ([Intel XE#4543]) -> [DMESG-FAIL][132] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#4543])
[131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3836-e2a896e95ea5f65aa137dcf117bfd0d61176c8ce/shard-adlp-3/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
[132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-adlp-3/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-lnl: [FAIL][133] ([Intel XE#301]) -> [FAIL][134] ([Intel XE#301] / [Intel XE#3149])
[133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3836-e2a896e95ea5f65aa137dcf117bfd0d61176c8ce/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank.html
[134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-shrfb-msflip-blt:
- shard-bmg: [SKIP][135] ([Intel XE#2312]) -> [SKIP][136] ([Intel XE#2311]) +2 other tests skip
[135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3836-e2a896e95ea5f65aa137dcf117bfd0d61176c8ce/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-shrfb-msflip-blt.html
[136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][137] ([Intel XE#2312]) -> [SKIP][138] ([Intel XE#5390])
[137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3836-e2a896e95ea5f65aa137dcf117bfd0d61176c8ce/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html
[138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render:
- shard-bmg: [SKIP][139] ([Intel XE#5390]) -> [SKIP][140] ([Intel XE#2312]) +1 other test skip
[139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3836-e2a896e95ea5f65aa137dcf117bfd0d61176c8ce/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html
[140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-render:
- shard-bmg: [SKIP][141] ([Intel XE#2311]) -> [SKIP][142] ([Intel XE#2312]) +2 other tests skip
[141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3836-e2a896e95ea5f65aa137dcf117bfd0d61176c8ce/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-render.html
[142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][143] ([Intel XE#2313]) -> [SKIP][144] ([Intel XE#2312]) +1 other test skip
[143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3836-e2a896e95ea5f65aa137dcf117bfd0d61176c8ce/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-wc.html
[144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-blt:
- shard-bmg: [SKIP][145] ([Intel XE#2312]) -> [SKIP][146] ([Intel XE#2313]) +2 other tests skip
[145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3836-e2a896e95ea5f65aa137dcf117bfd0d61176c8ce/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-blt.html
[146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-bmg-1/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-blt.html
* igt@xe_peer2peer@read:
- shard-dg2-set2: [FAIL][147] ([Intel XE#1173]) -> [SKIP][148] ([Intel XE#1061])
[147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3836-e2a896e95ea5f65aa137dcf117bfd0d61176c8ce/shard-dg2-434/igt@xe_peer2peer@read.html
[148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/shard-dg2-432/igt@xe_peer2peer@read.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[Intel XE#1061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1061
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1129]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1129
[Intel XE#1173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1173
[Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
[Intel XE#1401]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1401
[Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
[Intel XE#1420]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1420
[Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
[Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
[Intel XE#1475]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1475
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
[Intel XE#1508]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1508
[Intel XE#1512]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1512
[Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
[Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
[Intel XE#2168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2168
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
[Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
[Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
[Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
[Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
[Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
[Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
[Intel XE#2391]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2391
[Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
[Intel XE#2838]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2838
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
[Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
[Intel XE#310]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/310
[Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
[Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
[Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
[Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
[Intel XE#3278]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3278
[Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
[Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
[Intel XE#3876]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3876
[Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
[Intel XE#4130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4130
[Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
[Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
[Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
[Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
[Intel XE#4518]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4518
[Intel XE#4522]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4522
[Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
[Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
[Intel XE#4608]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4608
[Intel XE#4609]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4609
[Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
[Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
[Intel XE#4847]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4847
[Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
[Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
[Intel XE#512]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/512
[Intel XE#5390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5390
[Intel XE#5561]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5561
[Intel XE#5565]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5565
[Intel XE#5624]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5624
[Intel XE#5732]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5732
[Intel XE#5786]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5786
[Intel XE#5890]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5890
[Intel XE#6054]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6054
[Intel XE#616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/616
[Intel XE#6190]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6190
[Intel XE#6192]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6192
[Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
[Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
[Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
[Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
[Intel XE#718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/718
[Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
[Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
[Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
Build changes
-------------
* IGT: IGT_8555 -> IGT_8556
* Linux: xe-3836-e2a896e95ea5f65aa137dcf117bfd0d61176c8ce -> xe-pw-154737v6
IGT_8555: 8555
IGT_8556: e5eda2a187432a54f5e6fada18e4187e5175a10c @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-3836-e2a896e95ea5f65aa137dcf117bfd0d61176c8ce: e2a896e95ea5f65aa137dcf117bfd0d61176c8ce
xe-pw-154737v6: 154737v6
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154737v6/index.html
[-- Attachment #2: Type: text/html, Size: 52331 bytes --]
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v5 2/6] drm/dp: Add helpers to query the branch DSC max throughput/line-width
2025-09-29 9:00 ` Dmitry Baryshkov
@ 2025-09-29 10:10 ` Imre Deak
2025-09-30 5:30 ` Dmitry Baryshkov
0 siblings, 1 reply; 25+ messages in thread
From: Imre Deak @ 2025-09-29 10:10 UTC (permalink / raw)
To: Dmitry Baryshkov; +Cc: intel-gfx, intel-xe, dri-devel, Ville Syrjälä
On Mon, Sep 29, 2025 at 12:00:03PM +0300, Dmitry Baryshkov wrote:
> On Mon, Sep 29, 2025 at 09:36:44AM +0300, Imre Deak wrote:
> > Add helpers to query the DP DSC sink device's per-slice throughput as
> > well as a DSC branch device's overall throughput and line-width
> > capabilities.
> >
> > v2 (Ville):
> > - Rename pixel_clock to peak_pixel_rate, document what the value means
> > in case of MST tiled displays.
> > - Fix name of drm_dp_dsc_branch_max_slice_throughput() to
> > drm_dp_dsc_sink_max_slice_throughput().
> > v3:
> > - Fix the DSC branch device minimum valid line width value from 2560
> > to 5120 pixels.
> > - Fix drm_dp_dsc_sink_max_slice_throughput()'s pixel_clock parameter
> > name to peak_pixel_rate in header file.
> > - Add handling for throughput mode 0 granular delta, defined by DP
> > Standard v2.1a.
>
> This one got sent as a separate V5, without a proper changelog. What has
> changed?
This is v3 of the patch, the changes are listed under v3. The patchset's
version is v5.
> > Cc: dri-devel@lists.freedesktop.org
> > Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/display/drm_dp_helper.c | 156 ++++++++++++++++++++++++
> > include/drm/display/drm_dp.h | 3 +
> > include/drm/display/drm_dp_helper.h | 5 +
> > 3 files changed, 164 insertions(+)
> >
>
> --
> With best wishes
> Dmitry
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v5 2/6] drm/dp: Add helpers to query the branch DSC max throughput/line-width
2025-09-29 6:36 ` [PATCH v5 " Imre Deak
2025-09-29 9:00 ` Dmitry Baryshkov
@ 2025-09-29 10:12 ` Ville Syrjälä
2025-09-29 10:47 ` Imre Deak
1 sibling, 1 reply; 25+ messages in thread
From: Ville Syrjälä @ 2025-09-29 10:12 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx, intel-xe, dri-devel
On Mon, Sep 29, 2025 at 09:36:44AM +0300, Imre Deak wrote:
> Add helpers to query the DP DSC sink device's per-slice throughput as
> well as a DSC branch device's overall throughput and line-width
> capabilities.
>
> v2 (Ville):
> - Rename pixel_clock to peak_pixel_rate, document what the value means
> in case of MST tiled displays.
> - Fix name of drm_dp_dsc_branch_max_slice_throughput() to
> drm_dp_dsc_sink_max_slice_throughput().
> v3:
> - Fix the DSC branch device minimum valid line width value from 2560
> to 5120 pixels.
> - Fix drm_dp_dsc_sink_max_slice_throughput()'s pixel_clock parameter
> name to peak_pixel_rate in header file.
> - Add handling for throughput mode 0 granular delta, defined by DP
> Standard v2.1a.
>
> Cc: dri-devel@lists.freedesktop.org
> Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/display/drm_dp_helper.c | 156 ++++++++++++++++++++++++
> include/drm/display/drm_dp.h | 3 +
> include/drm/display/drm_dp_helper.h | 5 +
> 3 files changed, 164 insertions(+)
>
> diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
> index 1c74fe9459ad9..6084ca7fbe263 100644
> --- a/drivers/gpu/drm/display/drm_dp_helper.c
> +++ b/drivers/gpu/drm/display/drm_dp_helper.c
> @@ -2844,6 +2844,162 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
> }
> EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
>
> +/*
> + * See DP Standard v2.1a 2.8.4 Minimum Slices/Display, Table 2-159 and
> + * Appendix L.1 Derivation of Slice Count Requirements.
> + */
> +static int dsc_sink_min_slice_throughput(int peak_pixel_rate)
> +{
> + if (peak_pixel_rate >= 4800000)
> + return 600000;
> + else if (peak_pixel_rate >= 2700000)
> + return 400000;
> + else
> + return 340000;
> +}
> +
> +/**
> + * drm_dp_dsc_sink_max_slice_throughput() - Get a DSC sink's maximum pixel throughput per slice
> + * @dsc_dpcd: DSC sink's capabilities from DPCD
> + * @peak_pixel_rate: Cumulative peak pixel rate in kHz
> + * @is_rgb_yuv444: The mode is either RGB or YUV444
> + *
> + * Return the DSC sink device's maximum pixel throughput per slice, based on
> + * the device's @dsc_dpcd capabilities, the @peak_pixel_rate of the transferred
> + * stream(s) and whether the output format @is_rgb_yuv444 or yuv422/yuv420.
> + *
> + * Note that @peak_pixel_rate is the total pixel rate transferred to the same
> + * DSC/display sink. For instance to calculate a tile's slice count of an MST
> + * multi-tiled display sink (not considering here the required
> + * rounding/alignment of slice count)::
> + *
> + * @peak_pixel_rate = tile_pixel_rate * tile_count
> + * total_slice_count = @peak_pixel_rate / drm_dp_dsc_sink_max_slice_throughput(@peak_pixel_rate)
> + * tile_slice_count = total_slice_count / tile_count
> + *
> + * Returns:
> + * The maximum pixel throughput per slice supported by the DSC sink device
> + * in kPixels/sec.
> + */
> +int drm_dp_dsc_sink_max_slice_throughput(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
> + int peak_pixel_rate, bool is_rgb_yuv444)
> +{
> + int throughput;
> + int delta = 0;
> + int base;
> +
> + throughput = dsc_dpcd[DP_DSC_PEAK_THROUGHPUT - DP_DSC_SUPPORT];
> +
> + if (is_rgb_yuv444) {
> + throughput = (throughput & DP_DSC_THROUGHPUT_MODE_0_MASK) >>
> + DP_DSC_THROUGHPUT_MODE_0_SHIFT;
> +
> + delta = ((dsc_dpcd[DP_DSC_RC_BUF_BLK_SIZE - DP_DSC_SUPPORT]) &
> + DP_DSC_THROUGHPUT_MODE_0_DELTA_MASK) >>
> + DP_DSC_THROUGHPUT_MODE_0_DELTA_SHIFT; /* in units of 2 MPixels/sec */
> + delta *= 2000;
That thing really is very poorly documented. The DSC spec has a
note about possibly needing extra throughput at the right edges
of slices due to some alignment reasons. Maybe this is for that?
Dunno.
And the fact that there is a delta just for the 4:4:4 throughput
is also rather weird.
> + } else {
> + throughput = (throughput & DP_DSC_THROUGHPUT_MODE_1_MASK) >>
> + DP_DSC_THROUGHPUT_MODE_1_SHIFT;
> + }
> +
> + switch (throughput) {
> + case 0:
> + return dsc_sink_min_slice_throughput(peak_pixel_rate);
> + case 1:
> + base = 340000;
> + break;
> + case 2 ... 14:
> + base = 400000 + 50000 * (throughput - 2);
> + break;
> + case 15:
> + base = 170000;
> + break;
> + default:
> + WARN(1, "Missing case %d\n", throughput);
> + base = 340000;
> + break;
nit: that looks like an impossible situation. Could either nuke
the default case, or if the compiler/static checks are dumb
then get rid of the 2...14 case instead.
Anyways, for the series
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> + }
> +
> + return base + delta;
> +}
> +EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_throughput);
> +
> +static u8 dsc_branch_dpcd_cap(const u8 dpcd[DP_DSC_BRANCH_CAP_SIZE], int reg)
> +{
> + return dpcd[reg - DP_DSC_BRANCH_OVERALL_THROUGHPUT_0];
> +}
> +
> +/**
> + * drm_dp_dsc_branch_max_overall_throughput() - Branch device's max overall DSC pixel throughput
> + * @dsc_branch_dpcd: DSC branch capabilities from DPCD
> + * @is_rgb_yuv444: The mode is either RGB or YUV444
> + *
> + * Return the branch device's maximum overall DSC pixel throughput, based on
> + * the device's DPCD DSC branch capabilities, and whether the output
> + * format @is_rgb_yuv444 or yuv422/yuv420.
> + *
> + * Returns:
> + * - 0: The maximum overall throughput capability is not indicated by
> + * the device separately and it must be determined from the per-slice
> + * max throughput (see @drm_dp_dsc_branch_slice_max_throughput())
> + * and the maximum slice count supported by the device.
> + * - > 0: The maximum overall DSC pixel throughput supported by the branch
> + * device in kPixels/sec.
> + */
> +int drm_dp_dsc_branch_max_overall_throughput(const u8 dsc_branch_dpcd[DP_DSC_BRANCH_CAP_SIZE],
> + bool is_rgb_yuv444)
> +{
> + int throughput;
> +
> + if (is_rgb_yuv444)
> + throughput = dsc_branch_dpcd_cap(dsc_branch_dpcd,
> + DP_DSC_BRANCH_OVERALL_THROUGHPUT_0);
> + else
> + throughput = dsc_branch_dpcd_cap(dsc_branch_dpcd,
> + DP_DSC_BRANCH_OVERALL_THROUGHPUT_1);
> +
> + switch (throughput) {
> + case 0:
> + return 0;
> + case 1:
> + return 680000;
> + default:
> + return 600000 + 50000 * throughput;
> + }
> +}
> +EXPORT_SYMBOL(drm_dp_dsc_branch_max_overall_throughput);
> +
> +/**
> + * drm_dp_dsc_branch_max_line_width() - Branch device's max DSC line width
> + * @dsc_branch_dpcd: DSC branch capabilities from DPCD
> + *
> + * Return the branch device's maximum overall DSC line width, based on
> + * the device's @dsc_branch_dpcd capabilities.
> + *
> + * Returns:
> + * - 0: The maximum line width is not indicated by the device
> + * separately and it must be determined from the maximum
> + * slice count and slice-width supported by the device.
> + * - %-EINVAL: The device indicates an invalid maximum line width
> + * (< 5120 pixels).
> + * - >= 5120: The maximum line width in pixels.
> + */
> +int drm_dp_dsc_branch_max_line_width(const u8 dsc_branch_dpcd[DP_DSC_BRANCH_CAP_SIZE])
> +{
> + int line_width = dsc_branch_dpcd_cap(dsc_branch_dpcd, DP_DSC_BRANCH_MAX_LINE_WIDTH);
> +
> + switch (line_width) {
> + case 0:
> + return 0;
> + case 1 ... 15:
> + return -EINVAL;
> + default:
> + return line_width * 320;
> + }
> +}
> +EXPORT_SYMBOL(drm_dp_dsc_branch_max_line_width);
> +
> static int drm_dp_read_lttpr_regs(struct drm_dp_aux *aux,
> const u8 dpcd[DP_RECEIVER_CAP_SIZE], int address,
> u8 *buf, int buf_size)
> diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
> index cf318e3ddb5c5..e4eebabab9759 100644
> --- a/include/drm/display/drm_dp.h
> +++ b/include/drm/display/drm_dp.h
> @@ -258,6 +258,8 @@
> # define DP_DSC_RC_BUF_BLK_SIZE_4 0x1
> # define DP_DSC_RC_BUF_BLK_SIZE_16 0x2
> # define DP_DSC_RC_BUF_BLK_SIZE_64 0x3
> +# define DP_DSC_THROUGHPUT_MODE_0_DELTA_SHIFT 3 /* DP 2.1a, in units of 2 MPixels/sec */
> +# define DP_DSC_THROUGHPUT_MODE_0_DELTA_MASK (0x1f << DP_DSC_THROUGHPUT_MODE_0_DELTA_SHIFT)
>
> #define DP_DSC_RC_BUF_SIZE 0x063
>
> @@ -1686,6 +1688,7 @@ enum drm_dp_phy {
> #define DP_BRANCH_OUI_HEADER_SIZE 0xc
> #define DP_RECEIVER_CAP_SIZE 0xf
> #define DP_DSC_RECEIVER_CAP_SIZE 0x10 /* DSC Capabilities 0x60 through 0x6F */
> +#define DP_DSC_BRANCH_CAP_SIZE 3
> #define EDP_PSR_RECEIVER_CAP_SIZE 2
> #define EDP_DISPLAY_CTL_CAP_SIZE 5
> #define DP_LTTPR_COMMON_CAP_SIZE 8
> diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
> index e438c44409952..df2f24b950e4c 100644
> --- a/include/drm/display/drm_dp_helper.h
> +++ b/include/drm/display/drm_dp_helper.h
> @@ -211,6 +211,11 @@ u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
> u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
> int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE],
> u8 dsc_bpc[3]);
> +int drm_dp_dsc_sink_max_slice_throughput(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
> + int peak_pixel_rate, bool is_rgb_yuv444);
> +int drm_dp_dsc_branch_max_overall_throughput(const u8 dsc_branch_dpcd[DP_DSC_BRANCH_CAP_SIZE],
> + bool is_rgb_yuv444);
> +int drm_dp_dsc_branch_max_line_width(const u8 dsc_branch_dpcd[DP_DSC_BRANCH_CAP_SIZE]);
>
> static inline bool
> drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
> --
> 2.49.1
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v5 2/6] drm/dp: Add helpers to query the branch DSC max throughput/line-width
2025-09-29 10:12 ` Ville Syrjälä
@ 2025-09-29 10:47 ` Imre Deak
0 siblings, 0 replies; 25+ messages in thread
From: Imre Deak @ 2025-09-29 10:47 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, intel-xe, dri-devel
On Mon, Sep 29, 2025 at 01:12:15PM +0300, Ville Syrjälä wrote:
> On Mon, Sep 29, 2025 at 09:36:44AM +0300, Imre Deak wrote:
> > Add helpers to query the DP DSC sink device's per-slice throughput as
> > well as a DSC branch device's overall throughput and line-width
> > capabilities.
> >
> > v2 (Ville):
> > - Rename pixel_clock to peak_pixel_rate, document what the value means
> > in case of MST tiled displays.
> > - Fix name of drm_dp_dsc_branch_max_slice_throughput() to
> > drm_dp_dsc_sink_max_slice_throughput().
> > v3:
> > - Fix the DSC branch device minimum valid line width value from 2560
> > to 5120 pixels.
> > - Fix drm_dp_dsc_sink_max_slice_throughput()'s pixel_clock parameter
> > name to peak_pixel_rate in header file.
> > - Add handling for throughput mode 0 granular delta, defined by DP
> > Standard v2.1a.
> >
> > Cc: dri-devel@lists.freedesktop.org
> > Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/display/drm_dp_helper.c | 156 ++++++++++++++++++++++++
> > include/drm/display/drm_dp.h | 3 +
> > include/drm/display/drm_dp_helper.h | 5 +
> > 3 files changed, 164 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
> > index 1c74fe9459ad9..6084ca7fbe263 100644
> > --- a/drivers/gpu/drm/display/drm_dp_helper.c
> > +++ b/drivers/gpu/drm/display/drm_dp_helper.c
> > @@ -2844,6 +2844,162 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
> > }
> > EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
> >
> > +/*
> > + * See DP Standard v2.1a 2.8.4 Minimum Slices/Display, Table 2-159 and
> > + * Appendix L.1 Derivation of Slice Count Requirements.
> > + */
> > +static int dsc_sink_min_slice_throughput(int peak_pixel_rate)
> > +{
> > + if (peak_pixel_rate >= 4800000)
> > + return 600000;
> > + else if (peak_pixel_rate >= 2700000)
> > + return 400000;
> > + else
> > + return 340000;
> > +}
> > +
> > +/**
> > + * drm_dp_dsc_sink_max_slice_throughput() - Get a DSC sink's maximum pixel throughput per slice
> > + * @dsc_dpcd: DSC sink's capabilities from DPCD
> > + * @peak_pixel_rate: Cumulative peak pixel rate in kHz
> > + * @is_rgb_yuv444: The mode is either RGB or YUV444
> > + *
> > + * Return the DSC sink device's maximum pixel throughput per slice, based on
> > + * the device's @dsc_dpcd capabilities, the @peak_pixel_rate of the transferred
> > + * stream(s) and whether the output format @is_rgb_yuv444 or yuv422/yuv420.
> > + *
> > + * Note that @peak_pixel_rate is the total pixel rate transferred to the same
> > + * DSC/display sink. For instance to calculate a tile's slice count of an MST
> > + * multi-tiled display sink (not considering here the required
> > + * rounding/alignment of slice count)::
> > + *
> > + * @peak_pixel_rate = tile_pixel_rate * tile_count
> > + * total_slice_count = @peak_pixel_rate / drm_dp_dsc_sink_max_slice_throughput(@peak_pixel_rate)
> > + * tile_slice_count = total_slice_count / tile_count
> > + *
> > + * Returns:
> > + * The maximum pixel throughput per slice supported by the DSC sink device
> > + * in kPixels/sec.
> > + */
> > +int drm_dp_dsc_sink_max_slice_throughput(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
> > + int peak_pixel_rate, bool is_rgb_yuv444)
> > +{
> > + int throughput;
> > + int delta = 0;
> > + int base;
> > +
> > + throughput = dsc_dpcd[DP_DSC_PEAK_THROUGHPUT - DP_DSC_SUPPORT];
> > +
> > + if (is_rgb_yuv444) {
> > + throughput = (throughput & DP_DSC_THROUGHPUT_MODE_0_MASK) >>
> > + DP_DSC_THROUGHPUT_MODE_0_SHIFT;
> > +
> > + delta = ((dsc_dpcd[DP_DSC_RC_BUF_BLK_SIZE - DP_DSC_SUPPORT]) &
> > + DP_DSC_THROUGHPUT_MODE_0_DELTA_MASK) >>
> > + DP_DSC_THROUGHPUT_MODE_0_DELTA_SHIFT; /* in units of 2 MPixels/sec */
> > + delta *= 2000;
>
> That thing really is very poorly documented. The DSC spec has a
> note about possibly needing extra throughput at the right edges
> of slices due to some alignment reasons. Maybe this is for that?
> Dunno.
I assumed it's for the sink to be able to specify the throughput in a
smaller granularity, so the calculated slice count is then also closer
to the actual requirement. But yes, could be for another reason too,
I'll reread the DSC spec too.
> And the fact that there is a delta just for the 4:4:4 throughput
> is also rather weird.
Yes it is, but that's what the Standard says, unless I missed something.
> > + } else {
> > + throughput = (throughput & DP_DSC_THROUGHPUT_MODE_1_MASK) >>
> > + DP_DSC_THROUGHPUT_MODE_1_SHIFT;
> > + }
> > +
> > + switch (throughput) {
> > + case 0:
> > + return dsc_sink_min_slice_throughput(peak_pixel_rate);
> > + case 1:
> > + base = 340000;
> > + break;
> > + case 2 ... 14:
> > + base = 400000 + 50000 * (throughput - 2);
> > + break;
> > + case 15:
> > + base = 170000;
> > + break;
> > + default:
> > + WARN(1, "Missing case %d\n", throughput);
> > + base = 340000;
> > + break;
>
> nit: that looks like an impossible situation. Could either nuke
> the default case, or if the compiler/static checks are dumb
> then get rid of the 2...14 case instead.
Yes, the compiler should catch an unhandled case and atm the default
case could cause an an unreachable code compiler warn. Will remove the
default case.
> Anyways, for the series
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Thanks!
> > + }
> > +
> > + return base + delta;
> > +}
> > +EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_throughput);
> > +
> > +static u8 dsc_branch_dpcd_cap(const u8 dpcd[DP_DSC_BRANCH_CAP_SIZE], int reg)
> > +{
> > + return dpcd[reg - DP_DSC_BRANCH_OVERALL_THROUGHPUT_0];
> > +}
> > +
> > +/**
> > + * drm_dp_dsc_branch_max_overall_throughput() - Branch device's max overall DSC pixel throughput
> > + * @dsc_branch_dpcd: DSC branch capabilities from DPCD
> > + * @is_rgb_yuv444: The mode is either RGB or YUV444
> > + *
> > + * Return the branch device's maximum overall DSC pixel throughput, based on
> > + * the device's DPCD DSC branch capabilities, and whether the output
> > + * format @is_rgb_yuv444 or yuv422/yuv420.
> > + *
> > + * Returns:
> > + * - 0: The maximum overall throughput capability is not indicated by
> > + * the device separately and it must be determined from the per-slice
> > + * max throughput (see @drm_dp_dsc_branch_slice_max_throughput())
> > + * and the maximum slice count supported by the device.
> > + * - > 0: The maximum overall DSC pixel throughput supported by the branch
> > + * device in kPixels/sec.
> > + */
> > +int drm_dp_dsc_branch_max_overall_throughput(const u8 dsc_branch_dpcd[DP_DSC_BRANCH_CAP_SIZE],
> > + bool is_rgb_yuv444)
> > +{
> > + int throughput;
> > +
> > + if (is_rgb_yuv444)
> > + throughput = dsc_branch_dpcd_cap(dsc_branch_dpcd,
> > + DP_DSC_BRANCH_OVERALL_THROUGHPUT_0);
> > + else
> > + throughput = dsc_branch_dpcd_cap(dsc_branch_dpcd,
> > + DP_DSC_BRANCH_OVERALL_THROUGHPUT_1);
> > +
> > + switch (throughput) {
> > + case 0:
> > + return 0;
> > + case 1:
> > + return 680000;
> > + default:
> > + return 600000 + 50000 * throughput;
> > + }
> > +}
> > +EXPORT_SYMBOL(drm_dp_dsc_branch_max_overall_throughput);
> > +
> > +/**
> > + * drm_dp_dsc_branch_max_line_width() - Branch device's max DSC line width
> > + * @dsc_branch_dpcd: DSC branch capabilities from DPCD
> > + *
> > + * Return the branch device's maximum overall DSC line width, based on
> > + * the device's @dsc_branch_dpcd capabilities.
> > + *
> > + * Returns:
> > + * - 0: The maximum line width is not indicated by the device
> > + * separately and it must be determined from the maximum
> > + * slice count and slice-width supported by the device.
> > + * - %-EINVAL: The device indicates an invalid maximum line width
> > + * (< 5120 pixels).
> > + * - >= 5120: The maximum line width in pixels.
> > + */
> > +int drm_dp_dsc_branch_max_line_width(const u8 dsc_branch_dpcd[DP_DSC_BRANCH_CAP_SIZE])
> > +{
> > + int line_width = dsc_branch_dpcd_cap(dsc_branch_dpcd, DP_DSC_BRANCH_MAX_LINE_WIDTH);
> > +
> > + switch (line_width) {
> > + case 0:
> > + return 0;
> > + case 1 ... 15:
> > + return -EINVAL;
> > + default:
> > + return line_width * 320;
> > + }
> > +}
> > +EXPORT_SYMBOL(drm_dp_dsc_branch_max_line_width);
> > +
> > static int drm_dp_read_lttpr_regs(struct drm_dp_aux *aux,
> > const u8 dpcd[DP_RECEIVER_CAP_SIZE], int address,
> > u8 *buf, int buf_size)
> > diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
> > index cf318e3ddb5c5..e4eebabab9759 100644
> > --- a/include/drm/display/drm_dp.h
> > +++ b/include/drm/display/drm_dp.h
> > @@ -258,6 +258,8 @@
> > # define DP_DSC_RC_BUF_BLK_SIZE_4 0x1
> > # define DP_DSC_RC_BUF_BLK_SIZE_16 0x2
> > # define DP_DSC_RC_BUF_BLK_SIZE_64 0x3
> > +# define DP_DSC_THROUGHPUT_MODE_0_DELTA_SHIFT 3 /* DP 2.1a, in units of 2 MPixels/sec */
> > +# define DP_DSC_THROUGHPUT_MODE_0_DELTA_MASK (0x1f << DP_DSC_THROUGHPUT_MODE_0_DELTA_SHIFT)
> >
> > #define DP_DSC_RC_BUF_SIZE 0x063
> >
> > @@ -1686,6 +1688,7 @@ enum drm_dp_phy {
> > #define DP_BRANCH_OUI_HEADER_SIZE 0xc
> > #define DP_RECEIVER_CAP_SIZE 0xf
> > #define DP_DSC_RECEIVER_CAP_SIZE 0x10 /* DSC Capabilities 0x60 through 0x6F */
> > +#define DP_DSC_BRANCH_CAP_SIZE 3
> > #define EDP_PSR_RECEIVER_CAP_SIZE 2
> > #define EDP_DISPLAY_CTL_CAP_SIZE 5
> > #define DP_LTTPR_COMMON_CAP_SIZE 8
> > diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
> > index e438c44409952..df2f24b950e4c 100644
> > --- a/include/drm/display/drm_dp_helper.h
> > +++ b/include/drm/display/drm_dp_helper.h
> > @@ -211,6 +211,11 @@ u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
> > u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
> > int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE],
> > u8 dsc_bpc[3]);
> > +int drm_dp_dsc_sink_max_slice_throughput(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
> > + int peak_pixel_rate, bool is_rgb_yuv444);
> > +int drm_dp_dsc_branch_max_overall_throughput(const u8 dsc_branch_dpcd[DP_DSC_BRANCH_CAP_SIZE],
> > + bool is_rgb_yuv444);
> > +int drm_dp_dsc_branch_max_line_width(const u8 dsc_branch_dpcd[DP_DSC_BRANCH_CAP_SIZE]);
> >
> > static inline bool
> > drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
> > --
> > 2.49.1
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v4 0/6] drm/i915/dp: Work around a DSC pixel throughput issue
2025-09-26 21:12 [PATCH v4 0/6] drm/i915/dp: Work around a DSC pixel throughput issue Imre Deak
` (13 preceding siblings ...)
2025-09-29 9:40 ` ✓ Xe.CI.Full: " Patchwork
@ 2025-09-29 21:47 ` Sharma, Swati2
14 siblings, 0 replies; 25+ messages in thread
From: Sharma, Swati2 @ 2025-09-29 21:47 UTC (permalink / raw)
To: Imre Deak, intel-gfx, intel-xe
Cc: Vidya Srinivas, Ville Syrjälä, dri-devel
Hi Imre,
Thanks for the fix.
Validated with Dell WD 19TB and LG 40WP95-C
Tested-by: Swati Sharma <swati2.sharma@intel.com>
On 27-09-2025 02:42 am, Imre Deak wrote:
> This is v4 of [1], with the following changes:
>
> - Fix drm_dp_dsc_sink_max_slice_throughput()'s name.
> - Use the clearer peak_pixel_rate vs. pixel_clock as the above
> function's parameter.
> - Clarify the meaning of peak_pixel_rate for MST tiled displays.
> - Fix return value from dsc_throughput_quirk_max_bpp_x16(), in case it's
> not required to limit the BPP.
>
> [1] https://lore.kernel.org/all/20250924152332.359768-1-imre.deak@intel.com
>
> Reported-by: Vidya Srinivas <vidya.srinivas@intel.com>
> Reported-by: Swati Sharma <swati2.sharma@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: dri-devel@lists.freedesktop.org
>
> Imre Deak (6):
> drm/dp: Add quirk for Synaptics DSC throughput link-bpp limit
> drm/dp: Add helpers to query the branch DSC max throughput/line-width
> drm/i915/dp: Calculate DSC slice count based on per-slice peak
> throughput
> drm/i915/dp: Pass DPCD device descriptor to
> intel_dp_get_dsc_sink_cap()
> drm/i915/dp: Verify branch devices' overall pixel throughput/line
> width
> drm/i915/dp: Handle Synaptics DSC throughput link-bpp quirk
>
> drivers/gpu/drm/display/drm_dp_helper.c | 146 ++++++++++++++++++
> .../drm/i915/display/intel_display_types.h | 9 ++
> drivers/gpu/drm/i915/display/intel_dp.c | 146 ++++++++++++++++--
> drivers/gpu/drm/i915/display/intel_dp.h | 5 +-
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 9 +-
> include/drm/display/drm_dp.h | 1 +
> include/drm/display/drm_dp_helper.h | 14 ++
> 7 files changed, 316 insertions(+), 14 deletions(-)
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v5 2/6] drm/dp: Add helpers to query the branch DSC max throughput/line-width
2025-09-29 10:10 ` Imre Deak
@ 2025-09-30 5:30 ` Dmitry Baryshkov
2025-09-30 11:38 ` Imre Deak
0 siblings, 1 reply; 25+ messages in thread
From: Dmitry Baryshkov @ 2025-09-30 5:30 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx, intel-xe, dri-devel, Ville Syrjälä
On Mon, Sep 29, 2025 at 01:10:17PM +0300, Imre Deak wrote:
> On Mon, Sep 29, 2025 at 12:00:03PM +0300, Dmitry Baryshkov wrote:
> > On Mon, Sep 29, 2025 at 09:36:44AM +0300, Imre Deak wrote:
> > > Add helpers to query the DP DSC sink device's per-slice throughput as
> > > well as a DSC branch device's overall throughput and line-width
> > > capabilities.
> > >
> > > v2 (Ville):
> > > - Rename pixel_clock to peak_pixel_rate, document what the value means
> > > in case of MST tiled displays.
> > > - Fix name of drm_dp_dsc_branch_max_slice_throughput() to
> > > drm_dp_dsc_sink_max_slice_throughput().
> > > v3:
> > > - Fix the DSC branch device minimum valid line width value from 2560
> > > to 5120 pixels.
> > > - Fix drm_dp_dsc_sink_max_slice_throughput()'s pixel_clock parameter
> > > name to peak_pixel_rate in header file.
> > > - Add handling for throughput mode 0 granular delta, defined by DP
> > > Standard v2.1a.
> >
> > This one got sent as a separate V5, without a proper changelog. What has
> > changed?
>
> This is v3 of the patch, the changes are listed under v3. The patchset's
> version is v5.
Ugh. How one does relate this v3 (which is not mentioned anywhere) and
v5 of the series? This is totally counterintuitive. A usual
recommendation is to send the full series and to send it as a new
thread, sending all the patches in one go.
>
> > > Cc: dri-devel@lists.freedesktop.org
> > > Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > ---
> > > drivers/gpu/drm/display/drm_dp_helper.c | 156 ++++++++++++++++++++++++
> > > include/drm/display/drm_dp.h | 3 +
> > > include/drm/display/drm_dp_helper.h | 5 +
> > > 3 files changed, 164 insertions(+)
> > >
> >
> > --
> > With best wishes
> > Dmitry
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v5 2/6] drm/dp: Add helpers to query the branch DSC max throughput/line-width
2025-09-30 5:30 ` Dmitry Baryshkov
@ 2025-09-30 11:38 ` Imre Deak
2025-09-30 20:04 ` Dmitry Baryshkov
0 siblings, 1 reply; 25+ messages in thread
From: Imre Deak @ 2025-09-30 11:38 UTC (permalink / raw)
To: Dmitry Baryshkov; +Cc: intel-gfx, intel-xe, dri-devel, Ville Syrjälä
On Tue, Sep 30, 2025 at 08:30:10AM +0300, Dmitry Baryshkov wrote:
> On Mon, Sep 29, 2025 at 01:10:17PM +0300, Imre Deak wrote:
> > On Mon, Sep 29, 2025 at 12:00:03PM +0300, Dmitry Baryshkov wrote:
> > > On Mon, Sep 29, 2025 at 09:36:44AM +0300, Imre Deak wrote:
> > > > Add helpers to query the DP DSC sink device's per-slice throughput as
> > > > well as a DSC branch device's overall throughput and line-width
> > > > capabilities.
> > > >
> > > > v2 (Ville):
> > > > - Rename pixel_clock to peak_pixel_rate, document what the value means
> > > > in case of MST tiled displays.
> > > > - Fix name of drm_dp_dsc_branch_max_slice_throughput() to
> > > > drm_dp_dsc_sink_max_slice_throughput().
> > > > v3:
> > > > - Fix the DSC branch device minimum valid line width value from 2560
> > > > to 5120 pixels.
> > > > - Fix drm_dp_dsc_sink_max_slice_throughput()'s pixel_clock parameter
> > > > name to peak_pixel_rate in header file.
> > > > - Add handling for throughput mode 0 granular delta, defined by DP
> > > > Standard v2.1a.
> > >
> > > This one got sent as a separate V5, without a proper changelog. What has
> > > changed?
> >
> > This is v3 of the patch, the changes are listed under v3. The patchset's
> > version is v5.
>
> Ugh. How one does relate this v3 (which is not mentioned anywhere) and
> v5 of the series? This is totally counterintuitive. A usual
> recommendation is to send the full series and to send it as a new
> thread, sending all the patches in one go.
It's a common practice on intel-gfx to send a new version of one patch
on top of the last patchset version in that patchset's thread. For
matching the patch version to the patchset version I can change the
patch version log above to be like:
v2 (Ville):
- Rename pixel_clock to peak_pixel_rate ...
v3-v4:
- No changes
v5:
- Fix the DSC branch device minimum valid line width value ...
> > > > Cc: dri-devel@lists.freedesktop.org
> > > > Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > > ---
> > > > drivers/gpu/drm/display/drm_dp_helper.c | 156 ++++++++++++++++++++++++
> > > > include/drm/display/drm_dp.h | 3 +
> > > > include/drm/display/drm_dp_helper.h | 5 +
> > > > 3 files changed, 164 insertions(+)
> > > >
> > >
> > > --
> > > With best wishes
> > > Dmitry
>
> --
> With best wishes
> Dmitry
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v5 2/6] drm/dp: Add helpers to query the branch DSC max throughput/line-width
2025-09-30 11:38 ` Imre Deak
@ 2025-09-30 20:04 ` Dmitry Baryshkov
2025-09-30 21:03 ` Imre Deak
0 siblings, 1 reply; 25+ messages in thread
From: Dmitry Baryshkov @ 2025-09-30 20:04 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx, intel-xe, dri-devel, Ville Syrjälä
On Tue, Sep 30, 2025 at 02:38:09PM +0300, Imre Deak wrote:
> On Tue, Sep 30, 2025 at 08:30:10AM +0300, Dmitry Baryshkov wrote:
> > On Mon, Sep 29, 2025 at 01:10:17PM +0300, Imre Deak wrote:
> > > On Mon, Sep 29, 2025 at 12:00:03PM +0300, Dmitry Baryshkov wrote:
> > > > On Mon, Sep 29, 2025 at 09:36:44AM +0300, Imre Deak wrote:
> > > > > Add helpers to query the DP DSC sink device's per-slice throughput as
> > > > > well as a DSC branch device's overall throughput and line-width
> > > > > capabilities.
> > > > >
> > > > > v2 (Ville):
> > > > > - Rename pixel_clock to peak_pixel_rate, document what the value means
> > > > > in case of MST tiled displays.
> > > > > - Fix name of drm_dp_dsc_branch_max_slice_throughput() to
> > > > > drm_dp_dsc_sink_max_slice_throughput().
> > > > > v3:
> > > > > - Fix the DSC branch device minimum valid line width value from 2560
> > > > > to 5120 pixels.
> > > > > - Fix drm_dp_dsc_sink_max_slice_throughput()'s pixel_clock parameter
> > > > > name to peak_pixel_rate in header file.
> > > > > - Add handling for throughput mode 0 granular delta, defined by DP
> > > > > Standard v2.1a.
> > > >
> > > > This one got sent as a separate V5, without a proper changelog. What has
> > > > changed?
> > >
> > > This is v3 of the patch, the changes are listed under v3. The patchset's
> > > version is v5.
> >
> > Ugh. How one does relate this v3 (which is not mentioned anywhere) and
> > v5 of the series? This is totally counterintuitive. A usual
> > recommendation is to send the full series and to send it as a new
> > thread, sending all the patches in one go.
>
> It's a common practice on intel-gfx to send a new version of one patch
> on top of the last patchset version in that patchset's thread. For
I don't want to step on intel-gfx ways of working, but how would that
work with e.g. 'b4 shazam'?
> matching the patch version to the patchset version I can change the
> patch version log above to be like:
>
> v2 (Ville):
> - Rename pixel_clock to peak_pixel_rate ...
> v3-v4:
> - No changes
> v5:
> - Fix the DSC branch device minimum valid line width value ...
Yes, I think that's more obvious, thanks!
>
> > > > > Cc: dri-devel@lists.freedesktop.org
> > > > > Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > > > ---
> > > > > drivers/gpu/drm/display/drm_dp_helper.c | 156 ++++++++++++++++++++++++
> > > > > include/drm/display/drm_dp.h | 3 +
> > > > > include/drm/display/drm_dp_helper.h | 5 +
> > > > > 3 files changed, 164 insertions(+)
> > > > >
> > > >
> > > > --
> > > > With best wishes
> > > > Dmitry
> >
> > --
> > With best wishes
> > Dmitry
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v5 2/6] drm/dp: Add helpers to query the branch DSC max throughput/line-width
2025-09-30 20:04 ` Dmitry Baryshkov
@ 2025-09-30 21:03 ` Imre Deak
0 siblings, 0 replies; 25+ messages in thread
From: Imre Deak @ 2025-09-30 21:03 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: intel-gfx, intel-xe, dri-devel, Ville Syrjälä,
Jani Nikula
On Tue, Sep 30, 2025 at 11:04:47PM +0300, Dmitry Baryshkov wrote:
> On Tue, Sep 30, 2025 at 02:38:09PM +0300, Imre Deak wrote:
> > On Tue, Sep 30, 2025 at 08:30:10AM +0300, Dmitry Baryshkov wrote:
> > > On Mon, Sep 29, 2025 at 01:10:17PM +0300, Imre Deak wrote:
> > > > On Mon, Sep 29, 2025 at 12:00:03PM +0300, Dmitry Baryshkov wrote:
> > > > > On Mon, Sep 29, 2025 at 09:36:44AM +0300, Imre Deak wrote:
> > > > > > Add helpers to query the DP DSC sink device's per-slice throughput as
> > > > > > well as a DSC branch device's overall throughput and line-width
> > > > > > capabilities.
> > > > > >
> > > > > > v2 (Ville):
> > > > > > - Rename pixel_clock to peak_pixel_rate, document what the value means
> > > > > > in case of MST tiled displays.
> > > > > > - Fix name of drm_dp_dsc_branch_max_slice_throughput() to
> > > > > > drm_dp_dsc_sink_max_slice_throughput().
> > > > > > v3:
> > > > > > - Fix the DSC branch device minimum valid line width value from 2560
> > > > > > to 5120 pixels.
> > > > > > - Fix drm_dp_dsc_sink_max_slice_throughput()'s pixel_clock parameter
> > > > > > name to peak_pixel_rate in header file.
> > > > > > - Add handling for throughput mode 0 granular delta, defined by DP
> > > > > > Standard v2.1a.
> > > > >
> > > > > This one got sent as a separate V5, without a proper changelog. What has
> > > > > changed?
> > > >
> > > > This is v3 of the patch, the changes are listed under v3. The patchset's
> > > > version is v5.
> > >
> > > Ugh. How one does relate this v3 (which is not mentioned anywhere) and
> > > v5 of the series? This is totally counterintuitive. A usual
> > > recommendation is to send the full series and to send it as a new
> > > thread, sending all the patches in one go.
> >
> > It's a common practice on intel-gfx to send a new version of one patch
> > on top of the last patchset version in that patchset's thread. For
>
> I don't want to step on intel-gfx ways of working, but how would that
> work with e.g. 'b4 shazam'?
I don't - yet - use b4, but I suppose it must work because CI/patchwork
uses it and it does manage to assemble the new patchset for its test run
based on the In-reply-to header I think.
> > matching the patch version to the patchset version I can change the
> > patch version log above to be like:
> >
> > v2 (Ville):
> > - Rename pixel_clock to peak_pixel_rate ...
> > v3-v4:
> > - No changes
> > v5:
> > - Fix the DSC branch device minimum valid line width value ...
>
> Yes, I think that's more obvious, thanks!
I've been brooding over how to send the next version and then decided to
stick with the current practice and sent it as [1]. That is, increment
the patchset version to the next version of the patchset which is 6 and
increment the version of the patch with a change to the next version of
the patch itself which is 4.
Not sure if introducing the above "No changes" revisions is a good idea
after all. When the patchset is merged, this notation would lose its
meaning: you see then only the individual patches, not patchsets, so the
only interesting thing in that case is the versions the patch itself
went through. Keeping the version of the patchset and the patches within
it in sync could be also too tedious, especially if you wanted the
version of a patch without any changes to be brought up to the patchset
version.
One view is that the version of the patchset is simply different than
that of the patches within it. If an individual patch is sent in-reply
to a previous patchset, then it should be clear that this patch has a
change on top of the previous patchset and the changes are described
under the last revision log of the patch. Otherwise, when the whole
patchset is resent, the changes in that patchset version must be anyway
described in the cover letter.
I'm open to ideas, but this is my stance atm, also based on past
discussions about it with Ville and Jani.
--Imre
[1] https://lore.kernel.org/all/20250930182450.563016-1-imre.deak@intel.com
> > > > > > Cc: dri-devel@lists.freedesktop.org
> > > > > > Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > > > > ---
> > > > > > drivers/gpu/drm/display/drm_dp_helper.c | 156 ++++++++++++++++++++++++
> > > > > > include/drm/display/drm_dp.h | 3 +
> > > > > > include/drm/display/drm_dp_helper.h | 5 +
> > > > > > 3 files changed, 164 insertions(+)
> > > > > >
> > > > >
> > > > > --
> > > > > With best wishes
> > > > > Dmitry
> > >
> > > --
> > > With best wishes
> > > Dmitry
>
> --
> With best wishes
> Dmitry
^ permalink raw reply [flat|nested] 25+ messages in thread
end of thread, other threads:[~2025-09-30 21:03 UTC | newest]
Thread overview: 25+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-09-26 21:12 [PATCH v4 0/6] drm/i915/dp: Work around a DSC pixel throughput issue Imre Deak
2025-09-26 21:12 ` [PATCH v4 1/6] drm/dp: Add quirk for Synaptics DSC throughput link-bpp limit Imre Deak
2025-09-26 21:12 ` [PATCH v4 2/6] drm/dp: Add helpers to query the branch DSC max throughput/line-width Imre Deak
2025-09-29 6:36 ` [PATCH v5 " Imre Deak
2025-09-29 9:00 ` Dmitry Baryshkov
2025-09-29 10:10 ` Imre Deak
2025-09-30 5:30 ` Dmitry Baryshkov
2025-09-30 11:38 ` Imre Deak
2025-09-30 20:04 ` Dmitry Baryshkov
2025-09-30 21:03 ` Imre Deak
2025-09-29 10:12 ` Ville Syrjälä
2025-09-29 10:47 ` Imre Deak
2025-09-26 21:12 ` [PATCH v4 3/6] drm/i915/dp: Calculate DSC slice count based on per-slice peak throughput Imre Deak
2025-09-26 21:12 ` [PATCH v4 4/6] drm/i915/dp: Pass DPCD device descriptor to intel_dp_get_dsc_sink_cap() Imre Deak
2025-09-26 21:12 ` [PATCH v4 5/6] drm/i915/dp: Verify branch devices' overall pixel throughput/line width Imre Deak
2025-09-26 21:12 ` [PATCH v4 6/6] drm/i915/dp: Handle Synaptics DSC throughput link-bpp quirk Imre Deak
2025-09-26 21:56 ` ✗ CI.checkpatch: warning for drm/i915/dp: Work around a DSC pixel throughput issue (rev5) Patchwork
2025-09-26 21:57 ` ✓ CI.KUnit: success " Patchwork
2025-09-26 22:33 ` ✓ Xe.CI.BAT: " Patchwork
2025-09-27 5:36 ` ✗ Xe.CI.Full: failure " Patchwork
2025-09-29 7:12 ` ✗ CI.checkpatch: warning for drm/i915/dp: Work around a DSC pixel throughput issue (rev6) Patchwork
2025-09-29 7:13 ` ✓ CI.KUnit: success " Patchwork
2025-09-29 9:22 ` ✓ Xe.CI.BAT: " Patchwork
2025-09-29 9:40 ` ✓ Xe.CI.Full: " Patchwork
2025-09-29 21:47 ` [PATCH v4 0/6] drm/i915/dp: Work around a DSC pixel throughput issue Sharma, Swati2
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