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From: Matthew Brost <matthew.brost@intel.com>
To: <Simon.Richter@hogyros.de>
Cc: "Summers, Stuart" <stuart.summers@intel.com>,
	<intel-xe@lists.freedesktop.org>,
	"Auld, Matthew" <matthew.auld@intel.com>
Subject: Re: [PATCH v5 2/2] drm/xe: Enable 2M pages in xe_migrate_vram
Date: Mon, 13 Oct 2025 10:32:46 -0700	[thread overview]
Message-ID: <aO03vp4Nl3gWlPx7@lstrano-desk.jf.intel.com> (raw)
In-Reply-To: <6aa691b1-1c7b-4534-8698-71cec3952d7b@hogyros.de>

On Tue, Oct 14, 2025 at 02:29:52AM +0900, Simon.Richter@hogyros.de wrote:
> 14 Oct 2025 02:14:44 Matthew Brost <matthew.brost@intel.com>:
> 
> > I'm not handling this but I believe CPU pages are at most 64k on ARM,
> > power, or longsoon. I could add an assert I suppose to make sure this
> > unhandled case never occurs.
> Hi,
> 
> POWER can also do 256kB, but that is a very uncommon configuration because
> it requires the complete userspace to be rebuilt with 256k segment
> alignment.
> 
> For that reason I'd expect even larger pages to be very unlikely.
> 

That's still considerably less than 2M so we are good here.

Matt

>    Simon

  reply	other threads:[~2025-10-13 17:32 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-13  3:45 [PATCH v5 0/2] Different page size handle in migrate layer Matthew Brost
2025-10-13  3:45 ` [PATCH v5 1/2] drm/xe: Fix build_pt_update_batch_sram for non-4K PAGE_SIZE Matthew Brost
2025-10-13 16:38   ` [v5,1/2] " Simon Richter
2025-10-13 16:53   ` [PATCH v5 1/2] " Summers, Stuart
2025-10-13  3:45 ` [PATCH v5 2/2] drm/xe: Enable 2M pages in xe_migrate_vram Matthew Brost
2025-10-13 17:08   ` Summers, Stuart
2025-10-13 17:14     ` Matthew Brost
2025-10-13 17:22       ` Summers, Stuart
2025-10-13 17:34         ` Matthew Brost
2025-10-13 18:01           ` Summers, Stuart
2025-10-14  2:17         ` Simon Richter
2025-10-14  3:08           ` Summers, Stuart
2025-10-13 17:29       ` Simon.Richter
2025-10-13 17:32         ` Matthew Brost [this message]
2025-10-13  5:38 ` ✓ CI.KUnit: success for Different page size handle in migrate layer (rev2) Patchwork
2025-10-13  6:23 ` ✓ Xe.CI.BAT: " Patchwork
2025-10-13  6:51 ` ✓ Xe.CI.Full: " Patchwork

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