From: Heikki Krogerus <heikki.krogerus@linux.intel.com>
To: Raag Jadav <raag.jadav@intel.com>
Cc: lucas.demarchi@intel.com, rodrigo.vivi@intel.com,
intel-xe@lists.freedesktop.org, riana.tauro@intel.com
Subject: Re: [PATCH v1 2/2] drm/xe/i2c: Wire up reset/postinstall for I2C IRQ
Date: Wed, 8 Oct 2025 11:09:22 +0300 [thread overview]
Message-ID: <aOYcMmasu4Ui2VWc@kuha.fi.intel.com> (raw)
In-Reply-To: <20250924200835.3143173-3-raag.jadav@intel.com>
On Thu, Sep 25, 2025 at 01:38:35AM +0530, Raag Jadav wrote:
> I2C IRQ needs to be routed to SGUnit or PUnit for the devices that support
> it. Wire up reset/postinstall handles for I2C IRQ to take care of this.
>
> Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
> ---
> drivers/gpu/drm/xe/regs/xe_i2c_regs.h | 3 +++
> drivers/gpu/drm/xe/xe_i2c.c | 20 ++++++++++++++++++++
> drivers/gpu/drm/xe/xe_i2c.h | 4 ++++
> drivers/gpu/drm/xe/xe_irq.c | 2 ++
> 4 files changed, 29 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_i2c_regs.h b/drivers/gpu/drm/xe/regs/xe_i2c_regs.h
> index af781c8e4a80..f2e455e2bfe4 100644
> --- a/drivers/gpu/drm/xe/regs/xe_i2c_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_i2c_regs.h
> @@ -14,6 +14,9 @@
> #define REG_SG_REMAP_ADDR_PREFIX XE_REG(SOC_BASE + 0x0164)
> #define REG_SG_REMAP_ADDR_POSTFIX XE_REG(SOC_BASE + 0x0168)
>
> +#define I2C_BRIDGE_PCICFGCTL XE_REG(I2C_BRIDGE_OFFSET + 0x200)
> +#define ACPI_INTR_EN REG_BIT(1)
> +
> #define I2C_CONFIG_CMD XE_REG(I2C_CONFIG_SPACE_OFFSET + PCI_COMMAND)
> #define I2C_CONFIG_PMCSR XE_REG(I2C_CONFIG_SPACE_OFFSET + 0x84)
>
> diff --git a/drivers/gpu/drm/xe/xe_i2c.c b/drivers/gpu/drm/xe/xe_i2c.c
> index 25c6b8f3c0bb..69f39df5a692 100644
> --- a/drivers/gpu/drm/xe/xe_i2c.c
> +++ b/drivers/gpu/drm/xe/xe_i2c.c
> @@ -182,6 +182,26 @@ void xe_i2c_irq_handler(struct xe_device *xe, u32 master_ctl)
> generic_handle_irq_safe(xe->i2c->adapter_irq);
> }
>
> +void xe_i2c_irq_reset(struct xe_device *xe)
> +{
> + struct xe_mmio *mmio = xe_root_tile_mmio(xe);
> +
> + if (!xe_i2c_irq_present(xe))
> + return;
> +
> + xe_mmio_rmw32(mmio, I2C_BRIDGE_PCICFGCTL, ACPI_INTR_EN, 0);
> +}
> +
> +void xe_i2c_irq_postinstall(struct xe_device *xe)
> +{
> + struct xe_mmio *mmio = xe_root_tile_mmio(xe);
> +
> + if (!xe_i2c_irq_present(xe))
> + return;
> +
> + xe_mmio_rmw32(mmio, I2C_BRIDGE_PCICFGCTL, 0, ACPI_INTR_EN);
> +}
> +
> static int xe_i2c_irq_map(struct irq_domain *h, unsigned int virq,
> irq_hw_number_t hw_irq_num)
> {
> diff --git a/drivers/gpu/drm/xe/xe_i2c.h b/drivers/gpu/drm/xe/xe_i2c.h
> index ecd5f10358e2..425d8160835f 100644
> --- a/drivers/gpu/drm/xe/xe_i2c.h
> +++ b/drivers/gpu/drm/xe/xe_i2c.h
> @@ -51,12 +51,16 @@ struct xe_i2c {
> int xe_i2c_probe(struct xe_device *xe);
> bool xe_i2c_present(struct xe_device *xe);
> void xe_i2c_irq_handler(struct xe_device *xe, u32 master_ctl);
> +void xe_i2c_irq_postinstall(struct xe_device *xe);
> +void xe_i2c_irq_reset(struct xe_device *xe);
> void xe_i2c_pm_suspend(struct xe_device *xe);
> void xe_i2c_pm_resume(struct xe_device *xe, bool d3cold);
> #else
> static inline int xe_i2c_probe(struct xe_device *xe) { return 0; }
> static inline bool xe_i2c_present(struct xe_device *xe) { return false; }
> static inline void xe_i2c_irq_handler(struct xe_device *xe, u32 master_ctl) { }
> +static inline void xe_i2c_irq_postinstall(struct xe_device *xe) { }
> +static inline void xe_i2c_irq_reset(struct xe_device *xe) { }
> static inline void xe_i2c_pm_suspend(struct xe_device *xe) { }
> static inline void xe_i2c_pm_resume(struct xe_device *xe, bool d3cold) { }
> #endif
> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> index 870edaf69388..af519414a429 100644
> --- a/drivers/gpu/drm/xe/xe_irq.c
> +++ b/drivers/gpu/drm/xe/xe_irq.c
> @@ -616,6 +616,7 @@ static void xe_irq_reset(struct xe_device *xe)
> tile = xe_device_get_root_tile(xe);
> mask_and_disable(tile, GU_MISC_IRQ_OFFSET);
> xe_display_irq_reset(xe);
> + xe_i2c_irq_reset(xe);
>
> /*
> * The tile's top-level status register should be the last one
> @@ -657,6 +658,7 @@ static void xe_irq_postinstall(struct xe_device *xe)
> }
>
> xe_display_irq_postinstall(xe, xe_root_mmio_gt(xe));
> + xe_i2c_irq_postinstall(xe);
>
> /*
> * ASLE backlight operations are reported via GUnit GSE interrupts
> --
> 2.34.1
--
heikki
next prev parent reply other threads:[~2025-10-08 8:09 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-24 20:08 [PATCH v1 0/2] Wire up reset/postinstall for I2C IRQ Raag Jadav
2025-09-24 20:08 ` [PATCH v1 1/2] drm/xe/i2c: Introduce xe_i2c_irq_present() Raag Jadav
2025-09-30 11:08 ` Andi Shyti
2025-10-08 8:08 ` Heikki Krogerus
2025-09-24 20:08 ` [PATCH v1 2/2] drm/xe/i2c: Wire up reset/postinstall for I2C IRQ Raag Jadav
2025-09-30 11:13 ` Andi Shyti
2025-09-30 11:22 ` Raag Jadav
2025-10-08 8:01 ` Heikki Krogerus
2025-10-08 8:05 ` Heikki Krogerus
2025-10-09 6:14 ` Raag Jadav
2025-10-09 6:12 ` Raag Jadav
2025-10-08 8:09 ` Heikki Krogerus [this message]
2025-09-24 20:16 ` ✓ CI.KUnit: success for " Patchwork
2025-09-24 21:13 ` ✓ Xe.CI.BAT: " Patchwork
2025-09-25 3:42 ` ✗ Xe.CI.Full: failure " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=aOYcMmasu4Ui2VWc@kuha.fi.intel.com \
--to=heikki.krogerus@linux.intel.com \
--cc=intel-xe@lists.freedesktop.org \
--cc=lucas.demarchi@intel.com \
--cc=raag.jadav@intel.com \
--cc=riana.tauro@intel.com \
--cc=rodrigo.vivi@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox