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* [PATCH v5 0/2] drm/xe/guc: Remove cached frequency values for GuC SLPC
@ 2025-10-29 11:20 Sk Anirban
  2025-10-29 11:20 ` [PATCH v5 1/2] drm/xe/guc: Eliminate RPe caching for SLPC parameter handling Sk Anirban
                   ` (3 more replies)
  0 siblings, 4 replies; 12+ messages in thread
From: Sk Anirban @ 2025-10-29 11:20 UTC (permalink / raw)
  To: intel-xe
  Cc: anshuman.gupta, badal.nilawar, riana.tauro, karthik.poosa,
	raag.jadav, soham.purkait, mallesh.koujalagi, vinay.belgaumkar,
	rodrigo.vivi, Sk Anirban

This series eliminates cached frequency values that were causing stale
data in GuC SLPC parameter handling. Both RPe and RPa frequencies are
now read live from hardware registers on each request.

Signed-off-by: Sk Anirban <sk.anirban@intel.com>

Sk Anirban (2):
  drm/xe/guc: Eliminate RPe caching for SLPC parameter handling
  drm/xe/guc: Eliminate RPa frequency caching

 drivers/gpu/drm/xe/xe_guc_pc.c       | 114 ++++++++++++++-------------
 drivers/gpu/drm/xe/xe_guc_pc_types.h |   4 -
 2 files changed, 60 insertions(+), 58 deletions(-)

-- 
2.43.0


^ permalink raw reply	[flat|nested] 12+ messages in thread
* [PATCH v5 1/2] drm/xe/guc: Eliminate RPe caching for SLPC parameter handling
  2025-10-29 11:20 [PATCH v5 0/2] drm/xe/guc: Remove cached frequency values for GuC SLPC Sk Anirban
@ 2025-10-29 11:20 ` Sk Anirban
  2025-10-29 18:04   ` Rodrigo Vivi
  2025-10-29 11:20 ` [PATCH v5 2/2] drm/xe/guc: Eliminate RPa frequency caching Sk Anirban
                   ` (2 subsequent siblings)
  3 siblings, 1 reply; 12+ messages in thread
From: Sk Anirban @ 2025-10-29 11:20 UTC (permalink / raw)
  To: intel-xe
  Cc: anshuman.gupta, badal.nilawar, riana.tauro, karthik.poosa,
	raag.jadav, soham.purkait, mallesh.koujalagi, vinay.belgaumkar,
	rodrigo.vivi, Sk Anirban

RPe is runtime-determined by PCODE and caching it caused stale values,
leading to incorrect GuC SLPC parameter settings.
Drop the cached rpe_freq field and query fresh values from hardware
on each use to ensure GuC SLPC parameters reflect current RPe.

v2: Remove cached RPe frequency field (Rodrigo)
v3: Remove extra variable (Vinay)
    Modify function name (Vinay)
v4: Maintain a separate function for PVC (Rodrigo)
v5: Update RPn while fetching RPe frequency

Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/5166
Signed-off-by: Sk Anirban <sk.anirban@intel.com>
---
 drivers/gpu/drm/xe/xe_guc_pc.c       | 75 ++++++++++++++++------------
 drivers/gpu/drm/xe/xe_guc_pc_types.h |  2 -
 2 files changed, 42 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
index 3c0feb50a1e2..08deaa64aa85 100644
--- a/drivers/gpu/drm/xe/xe_guc_pc.c
+++ b/drivers/gpu/drm/xe/xe_guc_pc.c
@@ -330,7 +330,7 @@ static int pc_set_min_freq(struct xe_guc_pc *pc, u32 freq)
 	 * Our goal is to have the admin choices respected.
 	 */
 	pc_action_set_param(pc, SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY,
-			    freq < pc->rpe_freq);
+			    freq < xe_guc_pc_get_rpe_freq(pc));
 
 	return pc_action_set_param(pc,
 				   SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
@@ -375,7 +375,7 @@ static void mtl_update_rpa_value(struct xe_guc_pc *pc)
 	pc->rpa_freq = decode_freq(REG_FIELD_GET(MTL_RPA_MASK, reg));
 }
 
-static void mtl_update_rpe_value(struct xe_guc_pc *pc)
+static u32 mtl_get_rpe_freq(struct xe_guc_pc *pc)
 {
 	struct xe_gt *gt = pc_to_gt(pc);
 	u32 reg;
@@ -385,7 +385,7 @@ static void mtl_update_rpe_value(struct xe_guc_pc *pc)
 	else
 		reg = xe_mmio_read32(&gt->mmio, MTL_GT_RPE_FREQUENCY);
 
-	pc->rpe_freq = decode_freq(REG_FIELD_GET(MTL_RPE_MASK, reg));
+	return decode_freq(REG_FIELD_GET(MTL_RPE_MASK, reg));
 }
 
 static void tgl_update_rpa_value(struct xe_guc_pc *pc)
@@ -408,24 +408,22 @@ static void tgl_update_rpa_value(struct xe_guc_pc *pc)
 	}
 }
 
-static void tgl_update_rpe_value(struct xe_guc_pc *pc)
+static u32 pvc_get_rpe_freq(struct xe_guc_pc *pc)
 {
 	struct xe_gt *gt = pc_to_gt(pc);
-	struct xe_device *xe = gt_to_xe(gt);
 	u32 reg;
 
-	/*
-	 * For PVC we still need to use fused RP1 as the approximation for RPe
-	 * For other platforms than PVC we get the resolved RPe directly from
-	 * PCODE at a different register
-	 */
-	if (xe->info.platform == XE_PVC) {
-		reg = xe_mmio_read32(&gt->mmio, PVC_RP_STATE_CAP);
-		pc->rpe_freq = REG_FIELD_GET(RP1_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
-	} else {
-		reg = xe_mmio_read32(&gt->mmio, FREQ_INFO_REC);
-		pc->rpe_freq = REG_FIELD_GET(RPE_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
-	}
+	reg = xe_mmio_read32(&gt->mmio, PVC_RP_STATE_CAP);
+	return REG_FIELD_GET(RP1_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
+}
+
+static u32 tgl_get_rpe_freq(struct xe_guc_pc *pc)
+{
+	struct xe_gt *gt = pc_to_gt(pc);
+	u32 reg;
+
+	reg = xe_mmio_read32(&gt->mmio, FREQ_INFO_REC);
+	return REG_FIELD_GET(RPE_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
 }
 
 static void pc_update_rp_values(struct xe_guc_pc *pc)
@@ -433,20 +431,10 @@ static void pc_update_rp_values(struct xe_guc_pc *pc)
 	struct xe_gt *gt = pc_to_gt(pc);
 	struct xe_device *xe = gt_to_xe(gt);
 
-	if (GRAPHICS_VERx100(xe) >= 1270) {
+	if (GRAPHICS_VERx100(xe) >= 1270)
 		mtl_update_rpa_value(pc);
-		mtl_update_rpe_value(pc);
-	} else {
+	else
 		tgl_update_rpa_value(pc);
-		tgl_update_rpe_value(pc);
-	}
-
-	/*
-	 * RPe is decided at runtime by PCODE. In the rare case where that's
-	 * smaller than the fused min, we will trust the PCODE and use that
-	 * as our minimum one.
-	 */
-	pc->rpn_freq = min(pc->rpn_freq, pc->rpe_freq);
 }
 
 /**
@@ -560,9 +548,30 @@ u32 xe_guc_pc_get_rpa_freq(struct xe_guc_pc *pc)
  */
 u32 xe_guc_pc_get_rpe_freq(struct xe_guc_pc *pc)
 {
-	pc_update_rp_values(pc);
+	struct xe_gt *gt = pc_to_gt(pc);
+	struct xe_device *xe = gt_to_xe(gt);
+	u32 freq;
 
-	return pc->rpe_freq;
+	/*
+	 * For PVC we still need to use fused RP1 as the approximation for RPe
+	 * For other platforms than PVC we get the resolved RPe directly from
+	 * PCODE at a different register
+	 */
+	if (xe->info.platform == XE_PVC)
+		freq = pvc_get_rpe_freq(pc);
+	else if (GRAPHICS_VERx100(xe) >= 1270)
+		freq = mtl_get_rpe_freq(pc);
+	else
+		freq = tgl_get_rpe_freq(pc);
+
+	/*
+	 * RPe is decided at runtime by PCODE. In the rare case where that's
+	 * smaller than the fused min, we will trust the PCODE and use that
+	 * as our minimum one.
+	 */
+	pc->rpn_freq = min(pc->rpn_freq, freq);
+
+	return freq;
 }
 
 /**
@@ -1021,7 +1030,7 @@ static int pc_set_mert_freq_cap(struct xe_guc_pc *pc)
 	/*
 	 * Ensure min and max are bound by MERT_FREQ_CAP until driver loads.
 	 */
-	ret = pc_set_min_freq(pc, min(pc->rpe_freq, pc_max_freq_cap(pc)));
+	ret = pc_set_min_freq(pc, min(xe_guc_pc_get_rpe_freq(pc), pc_max_freq_cap(pc)));
 	if (!ret)
 		ret = pc_set_max_freq(pc, min(pc->rp0_freq, pc_max_freq_cap(pc)));
 
@@ -1339,7 +1348,7 @@ static void xe_guc_pc_fini_hw(void *arg)
 	XE_WARN_ON(xe_guc_pc_stop(pc));
 
 	/* Bind requested freq to mert_freq_cap before unload */
-	pc_set_cur_freq(pc, min(pc_max_freq_cap(pc), pc->rpe_freq));
+	pc_set_cur_freq(pc, min(pc_max_freq_cap(pc), xe_guc_pc_get_rpe_freq(pc)));
 
 	xe_force_wake_put(gt_to_fw(pc_to_gt(pc)), fw_ref);
 }
diff --git a/drivers/gpu/drm/xe/xe_guc_pc_types.h b/drivers/gpu/drm/xe/xe_guc_pc_types.h
index 5e4ea53fbee6..f27c05d81706 100644
--- a/drivers/gpu/drm/xe/xe_guc_pc_types.h
+++ b/drivers/gpu/drm/xe/xe_guc_pc_types.h
@@ -21,8 +21,6 @@ struct xe_guc_pc {
 	u32 rp0_freq;
 	/** @rpa_freq: HW RPa frequency - The Achievable one */
 	u32 rpa_freq;
-	/** @rpe_freq: HW RPe frequency - The Efficient one */
-	u32 rpe_freq;
 	/** @rpn_freq: HW RPN frequency - The Minimum one */
 	u32 rpn_freq;
 	/** @user_requested_min: Stash the minimum requested freq by user */
-- 
2.43.0


^ permalink raw reply related	[flat|nested] 12+ messages in thread
* [PATCH v5 2/2] drm/xe/guc: Eliminate RPa frequency caching
  2025-10-29 11:20 [PATCH v5 0/2] drm/xe/guc: Remove cached frequency values for GuC SLPC Sk Anirban
  2025-10-29 11:20 ` [PATCH v5 1/2] drm/xe/guc: Eliminate RPe caching for SLPC parameter handling Sk Anirban
@ 2025-10-29 11:20 ` Sk Anirban
  2025-10-29 15:40 ` ✓ CI.KUnit: success for drm/xe/guc: Remove cached frequency values for GuC SLPC Patchwork
  2025-10-29 16:28 ` ✓ Xe.CI.BAT: " Patchwork
  3 siblings, 0 replies; 12+ messages in thread
From: Sk Anirban @ 2025-10-29 11:20 UTC (permalink / raw)
  To: intel-xe
  Cc: anshuman.gupta, badal.nilawar, riana.tauro, karthik.poosa,
	raag.jadav, soham.purkait, mallesh.koujalagi, vinay.belgaumkar,
	rodrigo.vivi, Sk Anirban

Remove the cached pc->rpa_freq field and refactor RPA frequency handling
to fetch values directly from hardware registers on each request.

Suggested-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Suggested-by: Badal Nilawar <badal.nilawar@intel.com>
Signed-off-by: Sk Anirban <sk.anirban@intel.com>
---
 drivers/gpu/drm/xe/xe_guc_pc.c       | 55 +++++++++++++---------------
 drivers/gpu/drm/xe/xe_guc_pc_types.h |  2 -
 2 files changed, 26 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
index 08deaa64aa85..379b9aac1b42 100644
--- a/drivers/gpu/drm/xe/xe_guc_pc.c
+++ b/drivers/gpu/drm/xe/xe_guc_pc.c
@@ -362,7 +362,7 @@ static int pc_set_max_freq(struct xe_guc_pc *pc, u32 freq)
 				   freq);
 }
 
-static void mtl_update_rpa_value(struct xe_guc_pc *pc)
+static u32 mtl_get_rpa_freq(struct xe_guc_pc *pc)
 {
 	struct xe_gt *gt = pc_to_gt(pc);
 	u32 reg;
@@ -372,7 +372,7 @@ static void mtl_update_rpa_value(struct xe_guc_pc *pc)
 	else
 		reg = xe_mmio_read32(&gt->mmio, MTL_GT_RPA_FREQUENCY);
 
-	pc->rpa_freq = decode_freq(REG_FIELD_GET(MTL_RPA_MASK, reg));
+	return decode_freq(REG_FIELD_GET(MTL_RPA_MASK, reg));
 }
 
 static u32 mtl_get_rpe_freq(struct xe_guc_pc *pc)
@@ -388,24 +388,28 @@ static u32 mtl_get_rpe_freq(struct xe_guc_pc *pc)
 	return decode_freq(REG_FIELD_GET(MTL_RPE_MASK, reg));
 }
 
-static void tgl_update_rpa_value(struct xe_guc_pc *pc)
+static u32 pvc_get_rpa_freq(struct xe_guc_pc *pc)
 {
-	struct xe_gt *gt = pc_to_gt(pc);
-	struct xe_device *xe = gt_to_xe(gt);
-	u32 reg;
-
 	/*
 	 * For PVC we still need to use fused RP0 as the approximation for RPa
 	 * For other platforms than PVC we get the resolved RPa directly from
 	 * PCODE at a different register
 	 */
-	if (xe->info.platform == XE_PVC) {
-		reg = xe_mmio_read32(&gt->mmio, PVC_RP_STATE_CAP);
-		pc->rpa_freq = REG_FIELD_GET(RP0_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
-	} else {
-		reg = xe_mmio_read32(&gt->mmio, FREQ_INFO_REC);
-		pc->rpa_freq = REG_FIELD_GET(RPA_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
-	}
+
+	struct xe_gt *gt = pc_to_gt(pc);
+	u32 reg;
+
+	reg = xe_mmio_read32(&gt->mmio, PVC_RP_STATE_CAP);
+	return REG_FIELD_GET(RP0_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
+}
+
+static u32 tgl_get_rpa_freq(struct xe_guc_pc *pc)
+{
+	struct xe_gt *gt = pc_to_gt(pc);
+	u32 reg;
+
+	reg = xe_mmio_read32(&gt->mmio, FREQ_INFO_REC);
+	return REG_FIELD_GET(RPA_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
 }
 
 static u32 pvc_get_rpe_freq(struct xe_guc_pc *pc)
@@ -426,17 +430,6 @@ static u32 tgl_get_rpe_freq(struct xe_guc_pc *pc)
 	return REG_FIELD_GET(RPE_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
 }
 
-static void pc_update_rp_values(struct xe_guc_pc *pc)
-{
-	struct xe_gt *gt = pc_to_gt(pc);
-	struct xe_device *xe = gt_to_xe(gt);
-
-	if (GRAPHICS_VERx100(xe) >= 1270)
-		mtl_update_rpa_value(pc);
-	else
-		tgl_update_rpa_value(pc);
-}
-
 /**
  * xe_guc_pc_get_act_freq - Get Actual running frequency
  * @pc: The GuC PC
@@ -535,9 +528,15 @@ u32 xe_guc_pc_get_rp0_freq(struct xe_guc_pc *pc)
  */
 u32 xe_guc_pc_get_rpa_freq(struct xe_guc_pc *pc)
 {
-	pc_update_rp_values(pc);
+	struct xe_gt *gt = pc_to_gt(pc);
+	struct xe_device *xe = gt_to_xe(gt);
 
-	return pc->rpa_freq;
+	if (xe->info.platform == XE_PVC)
+		return pvc_get_rpa_freq(pc);
+	else if (GRAPHICS_VERx100(xe) >= 1270)
+		return mtl_get_rpa_freq(pc);
+	else
+		return tgl_get_rpa_freq(pc);
 }
 
 /**
@@ -1141,8 +1140,6 @@ static int pc_init_freqs(struct xe_guc_pc *pc)
 	if (ret)
 		goto out;
 
-	pc_update_rp_values(pc);
-
 	pc_init_pcode_freq(pc);
 
 	/*
diff --git a/drivers/gpu/drm/xe/xe_guc_pc_types.h b/drivers/gpu/drm/xe/xe_guc_pc_types.h
index f27c05d81706..711bbcdcb0d3 100644
--- a/drivers/gpu/drm/xe/xe_guc_pc_types.h
+++ b/drivers/gpu/drm/xe/xe_guc_pc_types.h
@@ -19,8 +19,6 @@ struct xe_guc_pc {
 	atomic_t flush_freq_limit;
 	/** @rp0_freq: HW RP0 frequency - The Maximum one */
 	u32 rp0_freq;
-	/** @rpa_freq: HW RPa frequency - The Achievable one */
-	u32 rpa_freq;
 	/** @rpn_freq: HW RPN frequency - The Minimum one */
 	u32 rpn_freq;
 	/** @user_requested_min: Stash the minimum requested freq by user */
-- 
2.43.0


^ permalink raw reply related	[flat|nested] 12+ messages in thread
* ✓ CI.KUnit: success for drm/xe/guc: Remove cached frequency values for GuC SLPC
  2025-10-29 11:20 [PATCH v5 0/2] drm/xe/guc: Remove cached frequency values for GuC SLPC Sk Anirban
  2025-10-29 11:20 ` [PATCH v5 1/2] drm/xe/guc: Eliminate RPe caching for SLPC parameter handling Sk Anirban
  2025-10-29 11:20 ` [PATCH v5 2/2] drm/xe/guc: Eliminate RPa frequency caching Sk Anirban
@ 2025-10-29 15:40 ` Patchwork
  2025-10-29 16:28 ` ✓ Xe.CI.BAT: " Patchwork
  3 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2025-10-29 15:40 UTC (permalink / raw)
  To: Sk Anirban; +Cc: intel-xe

== Series Details ==

Series: drm/xe/guc: Remove cached frequency values for GuC SLPC
URL   : https://patchwork.freedesktop.org/series/156738/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[15:39:21] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[15:39:25] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[15:39:58] Starting KUnit Kernel (1/1)...
[15:39:58] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[15:39:59] ================== guc_buf (11 subtests) ===================
[15:39:59] [PASSED] test_smallest
[15:39:59] [PASSED] test_largest
[15:39:59] [PASSED] test_granular
[15:39:59] [PASSED] test_unique
[15:39:59] [PASSED] test_overlap
[15:39:59] [PASSED] test_reusable
[15:39:59] [PASSED] test_too_big
[15:39:59] [PASSED] test_flush
[15:39:59] [PASSED] test_lookup
[15:39:59] [PASSED] test_data
[15:39:59] [PASSED] test_class
[15:39:59] ===================== [PASSED] guc_buf =====================
[15:39:59] =================== guc_dbm (7 subtests) ===================
[15:39:59] [PASSED] test_empty
[15:39:59] [PASSED] test_default
[15:39:59] ======================== test_size  ========================
[15:39:59] [PASSED] 4
[15:39:59] [PASSED] 8
[15:39:59] [PASSED] 32
[15:39:59] [PASSED] 256
[15:39:59] ==================== [PASSED] test_size ====================
[15:39:59] ======================= test_reuse  ========================
[15:39:59] [PASSED] 4
[15:39:59] [PASSED] 8
[15:39:59] [PASSED] 32
[15:39:59] [PASSED] 256
[15:39:59] =================== [PASSED] test_reuse ====================
[15:39:59] =================== test_range_overlap  ====================
[15:39:59] [PASSED] 4
[15:39:59] [PASSED] 8
[15:39:59] [PASSED] 32
[15:39:59] [PASSED] 256
[15:39:59] =============== [PASSED] test_range_overlap ================
[15:39:59] =================== test_range_compact  ====================
[15:39:59] [PASSED] 4
[15:39:59] [PASSED] 8
[15:39:59] [PASSED] 32
[15:39:59] [PASSED] 256
[15:39:59] =============== [PASSED] test_range_compact ================
[15:39:59] ==================== test_range_spare  =====================
[15:39:59] [PASSED] 4
[15:39:59] [PASSED] 8
[15:39:59] [PASSED] 32
[15:39:59] [PASSED] 256
[15:39:59] ================ [PASSED] test_range_spare =================
[15:39:59] ===================== [PASSED] guc_dbm =====================
[15:39:59] =================== guc_idm (6 subtests) ===================
[15:39:59] [PASSED] bad_init
[15:39:59] [PASSED] no_init
[15:39:59] [PASSED] init_fini
[15:39:59] [PASSED] check_used
[15:39:59] [PASSED] check_quota
[15:39:59] [PASSED] check_all
[15:39:59] ===================== [PASSED] guc_idm =====================
[15:39:59] ================== no_relay (3 subtests) ===================
[15:39:59] [PASSED] xe_drops_guc2pf_if_not_ready
[15:39:59] [PASSED] xe_drops_guc2vf_if_not_ready
[15:39:59] [PASSED] xe_rejects_send_if_not_ready
[15:39:59] ==================== [PASSED] no_relay =====================
[15:39:59] ================== pf_relay (14 subtests) ==================
[15:39:59] [PASSED] pf_rejects_guc2pf_too_short
[15:39:59] [PASSED] pf_rejects_guc2pf_too_long
[15:39:59] [PASSED] pf_rejects_guc2pf_no_payload
[15:39:59] [PASSED] pf_fails_no_payload
[15:39:59] [PASSED] pf_fails_bad_origin
[15:39:59] [PASSED] pf_fails_bad_type
[15:39:59] [PASSED] pf_txn_reports_error
[15:39:59] [PASSED] pf_txn_sends_pf2guc
[15:39:59] [PASSED] pf_sends_pf2guc
[15:39:59] [SKIPPED] pf_loopback_nop
[15:39:59] [SKIPPED] pf_loopback_echo
[15:39:59] [SKIPPED] pf_loopback_fail
[15:39:59] [SKIPPED] pf_loopback_busy
[15:39:59] [SKIPPED] pf_loopback_retry
[15:39:59] ==================== [PASSED] pf_relay =====================
[15:39:59] ================== vf_relay (3 subtests) ===================
[15:39:59] [PASSED] vf_rejects_guc2vf_too_short
[15:39:59] [PASSED] vf_rejects_guc2vf_too_long
[15:39:59] [PASSED] vf_rejects_guc2vf_no_payload
[15:39:59] ==================== [PASSED] vf_relay =====================
[15:39:59] ===================== lmtt (1 subtest) =====================
[15:39:59] ======================== test_ops  =========================
[15:39:59] [PASSED] 2-level
[15:39:59] [PASSED] multi-level
[15:39:59] ==================== [PASSED] test_ops =====================
[15:39:59] ====================== [PASSED] lmtt =======================
[15:39:59] ================= pf_service (11 subtests) =================
[15:39:59] [PASSED] pf_negotiate_any
[15:39:59] [PASSED] pf_negotiate_base_match
[15:39:59] [PASSED] pf_negotiate_base_newer
[15:39:59] [PASSED] pf_negotiate_base_next
[15:39:59] [SKIPPED] pf_negotiate_base_older
[15:39:59] [PASSED] pf_negotiate_base_prev
[15:39:59] [PASSED] pf_negotiate_latest_match
[15:39:59] [PASSED] pf_negotiate_latest_newer
[15:39:59] [PASSED] pf_negotiate_latest_next
[15:39:59] [SKIPPED] pf_negotiate_latest_older
[15:39:59] [SKIPPED] pf_negotiate_latest_prev
[15:39:59] =================== [PASSED] pf_service ====================
[15:39:59] ================= xe_guc_g2g (2 subtests) ==================
[15:39:59] ============== xe_live_guc_g2g_kunit_default  ==============
[15:39:59] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[15:39:59] ============== xe_live_guc_g2g_kunit_allmem  ===============
[15:39:59] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[15:39:59] =================== [SKIPPED] xe_guc_g2g ===================
[15:39:59] =================== xe_mocs (2 subtests) ===================
[15:39:59] ================ xe_live_mocs_kernel_kunit  ================
[15:39:59] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[15:39:59] ================ xe_live_mocs_reset_kunit  =================
[15:39:59] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[15:39:59] ==================== [SKIPPED] xe_mocs =====================
[15:39:59] ================= xe_migrate (2 subtests) ==================
[15:39:59] ================= xe_migrate_sanity_kunit  =================
[15:39:59] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[15:39:59] ================== xe_validate_ccs_kunit  ==================
[15:39:59] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[15:39:59] =================== [SKIPPED] xe_migrate ===================
[15:39:59] ================== xe_dma_buf (1 subtest) ==================
[15:39:59] ==================== xe_dma_buf_kunit  =====================
[15:39:59] ================ [SKIPPED] xe_dma_buf_kunit ================
[15:39:59] =================== [SKIPPED] xe_dma_buf ===================
[15:39:59] ================= xe_bo_shrink (1 subtest) =================
[15:39:59] =================== xe_bo_shrink_kunit  ====================
[15:39:59] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[15:39:59] ================== [SKIPPED] xe_bo_shrink ==================
[15:39:59] ==================== xe_bo (2 subtests) ====================
[15:39:59] ================== xe_ccs_migrate_kunit  ===================
[15:39:59] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[15:39:59] ==================== xe_bo_evict_kunit  ====================
[15:39:59] =============== [SKIPPED] xe_bo_evict_kunit ================
[15:39:59] ===================== [SKIPPED] xe_bo ======================
[15:39:59] ==================== args (11 subtests) ====================
[15:39:59] [PASSED] count_args_test
[15:39:59] [PASSED] call_args_example
[15:39:59] [PASSED] call_args_test
[15:39:59] [PASSED] drop_first_arg_example
[15:39:59] [PASSED] drop_first_arg_test
[15:39:59] [PASSED] first_arg_example
[15:39:59] [PASSED] first_arg_test
[15:39:59] [PASSED] last_arg_example
[15:39:59] [PASSED] last_arg_test
[15:39:59] [PASSED] pick_arg_example
[15:39:59] [PASSED] sep_comma_example
[15:39:59] ====================== [PASSED] args =======================
[15:39:59] =================== xe_pci (3 subtests) ====================
[15:39:59] ==================== check_graphics_ip  ====================
[15:39:59] [PASSED] 12.00 Xe_LP
[15:39:59] [PASSED] 12.10 Xe_LP+
[15:39:59] [PASSED] 12.55 Xe_HPG
[15:39:59] [PASSED] 12.60 Xe_HPC
[15:39:59] [PASSED] 12.70 Xe_LPG
[15:39:59] [PASSED] 12.71 Xe_LPG
[15:39:59] [PASSED] 12.74 Xe_LPG+
[15:39:59] [PASSED] 20.01 Xe2_HPG
[15:39:59] [PASSED] 20.02 Xe2_HPG
[15:39:59] [PASSED] 20.04 Xe2_LPG
[15:39:59] [PASSED] 30.00 Xe3_LPG
[15:39:59] [PASSED] 30.01 Xe3_LPG
[15:39:59] [PASSED] 30.03 Xe3_LPG
[15:39:59] [PASSED] 30.04 Xe3_LPG
[15:39:59] [PASSED] 30.05 Xe3_LPG
[15:39:59] [PASSED] 35.11 Xe3p_XPC
[15:39:59] ================ [PASSED] check_graphics_ip ================
[15:39:59] ===================== check_media_ip  ======================
[15:39:59] [PASSED] 12.00 Xe_M
[15:39:59] [PASSED] 12.55 Xe_HPM
[15:39:59] [PASSED] 13.00 Xe_LPM+
[15:39:59] [PASSED] 13.01 Xe2_HPM
[15:39:59] [PASSED] 20.00 Xe2_LPM
[15:39:59] [PASSED] 30.00 Xe3_LPM
[15:39:59] [PASSED] 30.02 Xe3_LPM
[15:39:59] [PASSED] 35.00 Xe3p_LPM
[15:39:59] [PASSED] 35.03 Xe3p_HPM
[15:39:59] ================= [PASSED] check_media_ip ==================
[15:39:59] =================== check_platform_desc  ===================
[15:39:59] [PASSED] 0x9A60 (TIGERLAKE)
[15:39:59] [PASSED] 0x9A68 (TIGERLAKE)
[15:39:59] [PASSED] 0x9A70 (TIGERLAKE)
[15:39:59] [PASSED] 0x9A40 (TIGERLAKE)
[15:39:59] [PASSED] 0x9A49 (TIGERLAKE)
[15:39:59] [PASSED] 0x9A59 (TIGERLAKE)
[15:39:59] [PASSED] 0x9A78 (TIGERLAKE)
[15:39:59] [PASSED] 0x9AC0 (TIGERLAKE)
[15:39:59] [PASSED] 0x9AC9 (TIGERLAKE)
[15:39:59] [PASSED] 0x9AD9 (TIGERLAKE)
[15:39:59] [PASSED] 0x9AF8 (TIGERLAKE)
[15:39:59] [PASSED] 0x4C80 (ROCKETLAKE)
[15:39:59] [PASSED] 0x4C8A (ROCKETLAKE)
[15:39:59] [PASSED] 0x4C8B (ROCKETLAKE)
[15:39:59] [PASSED] 0x4C8C (ROCKETLAKE)
[15:39:59] [PASSED] 0x4C90 (ROCKETLAKE)
[15:39:59] [PASSED] 0x4C9A (ROCKETLAKE)
[15:39:59] [PASSED] 0x4680 (ALDERLAKE_S)
[15:39:59] [PASSED] 0x4682 (ALDERLAKE_S)
[15:39:59] [PASSED] 0x4688 (ALDERLAKE_S)
[15:39:59] [PASSED] 0x468A (ALDERLAKE_S)
[15:39:59] [PASSED] 0x468B (ALDERLAKE_S)
[15:39:59] [PASSED] 0x4690 (ALDERLAKE_S)
[15:39:59] [PASSED] 0x4692 (ALDERLAKE_S)
[15:39:59] [PASSED] 0x4693 (ALDERLAKE_S)
[15:39:59] [PASSED] 0x46A0 (ALDERLAKE_P)
[15:39:59] [PASSED] 0x46A1 (ALDERLAKE_P)
[15:39:59] [PASSED] 0x46A2 (ALDERLAKE_P)
[15:39:59] [PASSED] 0x46A3 (ALDERLAKE_P)
[15:39:59] [PASSED] 0x46A6 (ALDERLAKE_P)
[15:39:59] [PASSED] 0x46A8 (ALDERLAKE_P)
[15:39:59] [PASSED] 0x46AA (ALDERLAKE_P)
[15:39:59] [PASSED] 0x462A (ALDERLAKE_P)
[15:39:59] [PASSED] 0x4626 (ALDERLAKE_P)
[15:39:59] [PASSED] 0x4628 (ALDERLAKE_P)
[15:39:59] [PASSED] 0x46B0 (ALDERLAKE_P)
[15:39:59] [PASSED] 0x46B1 (ALDERLAKE_P)
[15:39:59] [PASSED] 0x46B2 (ALDERLAKE_P)
[15:39:59] [PASSED] 0x46B3 (ALDERLAKE_P)
[15:39:59] [PASSED] 0x46C0 (ALDERLAKE_P)
[15:39:59] [PASSED] 0x46C1 (ALDERLAKE_P)
[15:39:59] [PASSED] 0x46C2 (ALDERLAKE_P)
[15:39:59] [PASSED] 0x46C3 (ALDERLAKE_P)
[15:39:59] [PASSED] 0x46D0 (ALDERLAKE_N)
[15:39:59] [PASSED] 0x46D1 (ALDERLAKE_N)
[15:39:59] [PASSED] 0x46D2 (ALDERLAKE_N)
[15:39:59] [PASSED] 0x46D3 (ALDERLAKE_N)
[15:39:59] [PASSED] 0x46D4 (ALDERLAKE_N)
[15:39:59] [PASSED] 0xA721 (ALDERLAKE_P)
[15:39:59] [PASSED] 0xA7A1 (ALDERLAKE_P)
[15:39:59] [PASSED] 0xA7A9 (ALDERLAKE_P)
[15:39:59] [PASSED] 0xA7AC (ALDERLAKE_P)
[15:39:59] [PASSED] 0xA7AD (ALDERLAKE_P)
[15:39:59] [PASSED] 0xA720 (ALDERLAKE_P)
[15:39:59] [PASSED] 0xA7A0 (ALDERLAKE_P)
[15:39:59] [PASSED] 0xA7A8 (ALDERLAKE_P)
[15:39:59] [PASSED] 0xA7AA (ALDERLAKE_P)
[15:39:59] [PASSED] 0xA7AB (ALDERLAKE_P)
[15:39:59] [PASSED] 0xA780 (ALDERLAKE_S)
[15:39:59] [PASSED] 0xA781 (ALDERLAKE_S)
[15:39:59] [PASSED] 0xA782 (ALDERLAKE_S)
[15:39:59] [PASSED] 0xA783 (ALDERLAKE_S)
[15:39:59] [PASSED] 0xA788 (ALDERLAKE_S)
[15:39:59] [PASSED] 0xA789 (ALDERLAKE_S)
[15:39:59] [PASSED] 0xA78A (ALDERLAKE_S)
[15:39:59] [PASSED] 0xA78B (ALDERLAKE_S)
[15:39:59] [PASSED] 0x4905 (DG1)
[15:39:59] [PASSED] 0x4906 (DG1)
[15:39:59] [PASSED] 0x4907 (DG1)
[15:39:59] [PASSED] 0x4908 (DG1)
[15:39:59] [PASSED] 0x4909 (DG1)
[15:39:59] [PASSED] 0x56C0 (DG2)
[15:39:59] [PASSED] 0x56C2 (DG2)
[15:39:59] [PASSED] 0x56C1 (DG2)
[15:39:59] [PASSED] 0x7D51 (METEORLAKE)
[15:39:59] [PASSED] 0x7DD1 (METEORLAKE)
[15:39:59] [PASSED] 0x7D41 (METEORLAKE)
[15:39:59] [PASSED] 0x7D67 (METEORLAKE)
[15:39:59] [PASSED] 0xB640 (METEORLAKE)
[15:39:59] [PASSED] 0x56A0 (DG2)
[15:39:59] [PASSED] 0x56A1 (DG2)
[15:39:59] [PASSED] 0x56A2 (DG2)
[15:39:59] [PASSED] 0x56BE (DG2)
[15:39:59] [PASSED] 0x56BF (DG2)
[15:39:59] [PASSED] 0x5690 (DG2)
[15:39:59] [PASSED] 0x5691 (DG2)
[15:39:59] [PASSED] 0x5692 (DG2)
[15:39:59] [PASSED] 0x56A5 (DG2)
[15:39:59] [PASSED] 0x56A6 (DG2)
[15:39:59] [PASSED] 0x56B0 (DG2)
[15:39:59] [PASSED] 0x56B1 (DG2)
[15:39:59] [PASSED] 0x56BA (DG2)
[15:39:59] [PASSED] 0x56BB (DG2)
[15:39:59] [PASSED] 0x56BC (DG2)
[15:39:59] [PASSED] 0x56BD (DG2)
[15:39:59] [PASSED] 0x5693 (DG2)
[15:39:59] [PASSED] 0x5694 (DG2)
[15:39:59] [PASSED] 0x5695 (DG2)
[15:39:59] [PASSED] 0x56A3 (DG2)
[15:39:59] [PASSED] 0x56A4 (DG2)
[15:39:59] [PASSED] 0x56B2 (DG2)
[15:39:59] [PASSED] 0x56B3 (DG2)
[15:39:59] [PASSED] 0x5696 (DG2)
[15:39:59] [PASSED] 0x5697 (DG2)
[15:39:59] [PASSED] 0xB69 (PVC)
[15:39:59] [PASSED] 0xB6E (PVC)
[15:39:59] [PASSED] 0xBD4 (PVC)
[15:39:59] [PASSED] 0xBD5 (PVC)
[15:39:59] [PASSED] 0xBD6 (PVC)
[15:39:59] [PASSED] 0xBD7 (PVC)
[15:39:59] [PASSED] 0xBD8 (PVC)
[15:39:59] [PASSED] 0xBD9 (PVC)
[15:39:59] [PASSED] 0xBDA (PVC)
[15:39:59] [PASSED] 0xBDB (PVC)
[15:39:59] [PASSED] 0xBE0 (PVC)
[15:39:59] [PASSED] 0xBE1 (PVC)
[15:39:59] [PASSED] 0xBE5 (PVC)
[15:39:59] [PASSED] 0x7D40 (METEORLAKE)
[15:39:59] [PASSED] 0x7D45 (METEORLAKE)
[15:39:59] [PASSED] 0x7D55 (METEORLAKE)
[15:39:59] [PASSED] 0x7D60 (METEORLAKE)
[15:39:59] [PASSED] 0x7DD5 (METEORLAKE)
[15:39:59] [PASSED] 0x6420 (LUNARLAKE)
[15:39:59] [PASSED] 0x64A0 (LUNARLAKE)
[15:39:59] [PASSED] 0x64B0 (LUNARLAKE)
[15:39:59] [PASSED] 0xE202 (BATTLEMAGE)
[15:39:59] [PASSED] 0xE209 (BATTLEMAGE)
[15:39:59] [PASSED] 0xE20B (BATTLEMAGE)
[15:39:59] [PASSED] 0xE20C (BATTLEMAGE)
[15:39:59] [PASSED] 0xE20D (BATTLEMAGE)
[15:39:59] [PASSED] 0xE210 (BATTLEMAGE)
[15:39:59] [PASSED] 0xE211 (BATTLEMAGE)
[15:39:59] [PASSED] 0xE212 (BATTLEMAGE)
[15:39:59] [PASSED] 0xE216 (BATTLEMAGE)
[15:39:59] [PASSED] 0xE220 (BATTLEMAGE)
[15:39:59] [PASSED] 0xE221 (BATTLEMAGE)
[15:39:59] [PASSED] 0xE222 (BATTLEMAGE)
[15:39:59] [PASSED] 0xE223 (BATTLEMAGE)
[15:39:59] [PASSED] 0xB080 (PANTHERLAKE)
[15:39:59] [PASSED] 0xB081 (PANTHERLAKE)
[15:39:59] [PASSED] 0xB082 (PANTHERLAKE)
[15:39:59] [PASSED] 0xB083 (PANTHERLAKE)
[15:39:59] [PASSED] 0xB084 (PANTHERLAKE)
[15:39:59] [PASSED] 0xB085 (PANTHERLAKE)
[15:39:59] [PASSED] 0xB086 (PANTHERLAKE)
[15:39:59] [PASSED] 0xB087 (PANTHERLAKE)
[15:39:59] [PASSED] 0xB08F (PANTHERLAKE)
[15:39:59] [PASSED] 0xB090 (PANTHERLAKE)
[15:39:59] [PASSED] 0xB0A0 (PANTHERLAKE)
[15:39:59] [PASSED] 0xB0B0 (PANTHERLAKE)
[15:39:59] [PASSED] 0xFD80 (PANTHERLAKE)
[15:39:59] [PASSED] 0xFD81 (PANTHERLAKE)
[15:39:59] [PASSED] 0xD740 (NOVALAKE_S)
[15:39:59] [PASSED] 0xD741 (NOVALAKE_S)
[15:39:59] [PASSED] 0xD742 (NOVALAKE_S)
[15:39:59] [PASSED] 0xD743 (NOVALAKE_S)
[15:39:59] [PASSED] 0xD744 (NOVALAKE_S)
[15:39:59] [PASSED] 0xD745 (NOVALAKE_S)
[15:39:59] [PASSED] 0x674C (CRESCENTISLAND)
[15:39:59] =============== [PASSED] check_platform_desc ===============
[15:39:59] ===================== [PASSED] xe_pci ======================
[15:39:59] =================== xe_rtp (2 subtests) ====================
[15:39:59] =============== xe_rtp_process_to_sr_tests  ================
[15:39:59] [PASSED] coalesce-same-reg
[15:39:59] [PASSED] no-match-no-add
[15:39:59] [PASSED] match-or
[15:39:59] [PASSED] match-or-xfail
[15:39:59] [PASSED] no-match-no-add-multiple-rules
[15:39:59] [PASSED] two-regs-two-entries
[15:39:59] [PASSED] clr-one-set-other
[15:39:59] [PASSED] set-field
[15:39:59] [PASSED] conflict-duplicate
[15:39:59] [PASSED] conflict-not-disjoint
[15:39:59] [PASSED] conflict-reg-type
[15:39:59] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[15:39:59] ================== xe_rtp_process_tests  ===================
[15:39:59] [PASSED] active1
[15:39:59] [PASSED] active2
[15:39:59] [PASSED] active-inactive
[15:39:59] [PASSED] inactive-active
[15:39:59] [PASSED] inactive-1st_or_active-inactive
[15:39:59] [PASSED] inactive-2nd_or_active-inactive
[15:39:59] [PASSED] inactive-last_or_active-inactive
stty: 'standard input': Inappropriate ioctl for device
[15:39:59] [PASSED] inactive-no_or_active-inactive
[15:39:59] ============== [PASSED] xe_rtp_process_tests ===============
[15:39:59] ===================== [PASSED] xe_rtp ======================
[15:39:59] ==================== xe_wa (1 subtest) =====================
[15:39:59] ======================== xe_wa_gt  =========================
[15:39:59] [PASSED] TIGERLAKE B0
[15:39:59] [PASSED] DG1 A0
[15:39:59] [PASSED] DG1 B0
[15:39:59] [PASSED] ALDERLAKE_S A0
[15:39:59] [PASSED] ALDERLAKE_S B0
[15:39:59] [PASSED] ALDERLAKE_S C0
[15:39:59] [PASSED] ALDERLAKE_S D0
[15:39:59] [PASSED] ALDERLAKE_P A0
[15:39:59] [PASSED] ALDERLAKE_P B0
[15:39:59] [PASSED] ALDERLAKE_P C0
[15:39:59] [PASSED] ALDERLAKE_S RPLS D0
[15:39:59] [PASSED] ALDERLAKE_P RPLU E0
[15:39:59] [PASSED] DG2 G10 C0
[15:39:59] [PASSED] DG2 G11 B1
[15:39:59] [PASSED] DG2 G12 A1
[15:39:59] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[15:39:59] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[15:39:59] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[15:39:59] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[15:39:59] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[15:39:59] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[15:39:59] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[15:39:59] ==================== [PASSED] xe_wa_gt =====================
[15:39:59] ====================== [PASSED] xe_wa ======================
[15:39:59] ============================================================
[15:39:59] Testing complete. Ran 318 tests: passed: 300, skipped: 18
[15:39:59] Elapsed time: 38.073s total, 4.193s configuring, 33.514s building, 0.336s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[15:39:59] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[15:40:00] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[15:40:25] Starting KUnit Kernel (1/1)...
[15:40:25] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[15:40:25] ============ drm_test_pick_cmdline (2 subtests) ============
[15:40:25] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[15:40:25] =============== drm_test_pick_cmdline_named  ===============
[15:40:25] [PASSED] NTSC
[15:40:25] [PASSED] NTSC-J
[15:40:25] [PASSED] PAL
[15:40:25] [PASSED] PAL-M
[15:40:25] =========== [PASSED] drm_test_pick_cmdline_named ===========
[15:40:25] ============== [PASSED] drm_test_pick_cmdline ==============
[15:40:25] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[15:40:25] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[15:40:25] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[15:40:25] =========== drm_validate_clone_mode (2 subtests) ===========
[15:40:25] ============== drm_test_check_in_clone_mode  ===============
[15:40:25] [PASSED] in_clone_mode
[15:40:25] [PASSED] not_in_clone_mode
[15:40:25] ========== [PASSED] drm_test_check_in_clone_mode ===========
[15:40:25] =============== drm_test_check_valid_clones  ===============
[15:40:25] [PASSED] not_in_clone_mode
[15:40:25] [PASSED] valid_clone
[15:40:25] [PASSED] invalid_clone
[15:40:25] =========== [PASSED] drm_test_check_valid_clones ===========
[15:40:25] ============= [PASSED] drm_validate_clone_mode =============
[15:40:25] ============= drm_validate_modeset (1 subtest) =============
[15:40:25] [PASSED] drm_test_check_connector_changed_modeset
[15:40:25] ============== [PASSED] drm_validate_modeset ===============
[15:40:25] ====== drm_test_bridge_get_current_state (2 subtests) ======
[15:40:25] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[15:40:25] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[15:40:25] ======== [PASSED] drm_test_bridge_get_current_state ========
[15:40:25] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[15:40:25] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[15:40:25] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[15:40:25] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[15:40:25] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[15:40:25] ============== drm_bridge_alloc (2 subtests) ===============
[15:40:25] [PASSED] drm_test_drm_bridge_alloc_basic
[15:40:25] [PASSED] drm_test_drm_bridge_alloc_get_put
[15:40:25] ================ [PASSED] drm_bridge_alloc =================
[15:40:25] ================== drm_buddy (8 subtests) ==================
[15:40:25] [PASSED] drm_test_buddy_alloc_limit
[15:40:25] [PASSED] drm_test_buddy_alloc_optimistic
[15:40:25] [PASSED] drm_test_buddy_alloc_pessimistic
[15:40:25] [PASSED] drm_test_buddy_alloc_pathological
[15:40:25] [PASSED] drm_test_buddy_alloc_contiguous
[15:40:25] [PASSED] drm_test_buddy_alloc_clear
[15:40:26] [PASSED] drm_test_buddy_alloc_range_bias
[15:40:26] [PASSED] drm_test_buddy_fragmentation_performance
[15:40:26] ==================== [PASSED] drm_buddy ====================
[15:40:26] ============= drm_cmdline_parser (40 subtests) =============
[15:40:26] [PASSED] drm_test_cmdline_force_d_only
[15:40:26] [PASSED] drm_test_cmdline_force_D_only_dvi
[15:40:26] [PASSED] drm_test_cmdline_force_D_only_hdmi
[15:40:26] [PASSED] drm_test_cmdline_force_D_only_not_digital
[15:40:26] [PASSED] drm_test_cmdline_force_e_only
[15:40:26] [PASSED] drm_test_cmdline_res
[15:40:26] [PASSED] drm_test_cmdline_res_vesa
[15:40:26] [PASSED] drm_test_cmdline_res_vesa_rblank
[15:40:26] [PASSED] drm_test_cmdline_res_rblank
[15:40:26] [PASSED] drm_test_cmdline_res_bpp
[15:40:26] [PASSED] drm_test_cmdline_res_refresh
[15:40:26] [PASSED] drm_test_cmdline_res_bpp_refresh
[15:40:26] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[15:40:26] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[15:40:26] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[15:40:26] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[15:40:26] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[15:40:26] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[15:40:26] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[15:40:26] [PASSED] drm_test_cmdline_res_margins_force_on
[15:40:26] [PASSED] drm_test_cmdline_res_vesa_margins
[15:40:26] [PASSED] drm_test_cmdline_name
[15:40:26] [PASSED] drm_test_cmdline_name_bpp
[15:40:26] [PASSED] drm_test_cmdline_name_option
[15:40:26] [PASSED] drm_test_cmdline_name_bpp_option
[15:40:26] [PASSED] drm_test_cmdline_rotate_0
[15:40:26] [PASSED] drm_test_cmdline_rotate_90
[15:40:26] [PASSED] drm_test_cmdline_rotate_180
[15:40:26] [PASSED] drm_test_cmdline_rotate_270
[15:40:26] [PASSED] drm_test_cmdline_hmirror
[15:40:26] [PASSED] drm_test_cmdline_vmirror
[15:40:26] [PASSED] drm_test_cmdline_margin_options
[15:40:26] [PASSED] drm_test_cmdline_multiple_options
[15:40:26] [PASSED] drm_test_cmdline_bpp_extra_and_option
[15:40:26] [PASSED] drm_test_cmdline_extra_and_option
[15:40:26] [PASSED] drm_test_cmdline_freestanding_options
[15:40:26] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[15:40:26] [PASSED] drm_test_cmdline_panel_orientation
[15:40:26] ================ drm_test_cmdline_invalid  =================
[15:40:26] [PASSED] margin_only
[15:40:26] [PASSED] interlace_only
[15:40:26] [PASSED] res_missing_x
[15:40:26] [PASSED] res_missing_y
[15:40:26] [PASSED] res_bad_y
[15:40:26] [PASSED] res_missing_y_bpp
[15:40:26] [PASSED] res_bad_bpp
[15:40:26] [PASSED] res_bad_refresh
[15:40:26] [PASSED] res_bpp_refresh_force_on_off
[15:40:26] [PASSED] res_invalid_mode
[15:40:26] [PASSED] res_bpp_wrong_place_mode
[15:40:26] [PASSED] name_bpp_refresh
[15:40:26] [PASSED] name_refresh
[15:40:26] [PASSED] name_refresh_wrong_mode
[15:40:26] [PASSED] name_refresh_invalid_mode
[15:40:26] [PASSED] rotate_multiple
[15:40:26] [PASSED] rotate_invalid_val
[15:40:26] [PASSED] rotate_truncated
[15:40:26] [PASSED] invalid_option
[15:40:26] [PASSED] invalid_tv_option
[15:40:26] [PASSED] truncated_tv_option
[15:40:26] ============ [PASSED] drm_test_cmdline_invalid =============
[15:40:26] =============== drm_test_cmdline_tv_options  ===============
[15:40:26] [PASSED] NTSC
[15:40:26] [PASSED] NTSC_443
[15:40:26] [PASSED] NTSC_J
[15:40:26] [PASSED] PAL
[15:40:26] [PASSED] PAL_M
[15:40:26] [PASSED] PAL_N
[15:40:26] [PASSED] SECAM
[15:40:26] [PASSED] MONO_525
[15:40:26] [PASSED] MONO_625
[15:40:26] =========== [PASSED] drm_test_cmdline_tv_options ===========
[15:40:26] =============== [PASSED] drm_cmdline_parser ================
[15:40:26] ========== drmm_connector_hdmi_init (20 subtests) ==========
[15:40:26] [PASSED] drm_test_connector_hdmi_init_valid
[15:40:26] [PASSED] drm_test_connector_hdmi_init_bpc_8
[15:40:26] [PASSED] drm_test_connector_hdmi_init_bpc_10
[15:40:26] [PASSED] drm_test_connector_hdmi_init_bpc_12
[15:40:26] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[15:40:26] [PASSED] drm_test_connector_hdmi_init_bpc_null
[15:40:26] [PASSED] drm_test_connector_hdmi_init_formats_empty
[15:40:26] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[15:40:26] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[15:40:26] [PASSED] supported_formats=0x9 yuv420_allowed=1
[15:40:26] [PASSED] supported_formats=0x9 yuv420_allowed=0
[15:40:26] [PASSED] supported_formats=0x3 yuv420_allowed=1
[15:40:26] [PASSED] supported_formats=0x3 yuv420_allowed=0
[15:40:26] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[15:40:26] [PASSED] drm_test_connector_hdmi_init_null_ddc
[15:40:26] [PASSED] drm_test_connector_hdmi_init_null_product
[15:40:26] [PASSED] drm_test_connector_hdmi_init_null_vendor
[15:40:26] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[15:40:26] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[15:40:26] [PASSED] drm_test_connector_hdmi_init_product_valid
[15:40:26] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[15:40:26] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[15:40:26] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[15:40:26] ========= drm_test_connector_hdmi_init_type_valid  =========
[15:40:26] [PASSED] HDMI-A
[15:40:26] [PASSED] HDMI-B
[15:40:26] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[15:40:26] ======== drm_test_connector_hdmi_init_type_invalid  ========
[15:40:26] [PASSED] Unknown
[15:40:26] [PASSED] VGA
[15:40:26] [PASSED] DVI-I
[15:40:26] [PASSED] DVI-D
[15:40:26] [PASSED] DVI-A
[15:40:26] [PASSED] Composite
[15:40:26] [PASSED] SVIDEO
[15:40:26] [PASSED] LVDS
[15:40:26] [PASSED] Component
[15:40:26] [PASSED] DIN
[15:40:26] [PASSED] DP
[15:40:26] [PASSED] TV
[15:40:26] [PASSED] eDP
[15:40:26] [PASSED] Virtual
[15:40:26] [PASSED] DSI
[15:40:26] [PASSED] DPI
[15:40:26] [PASSED] Writeback
[15:40:26] [PASSED] SPI
[15:40:26] [PASSED] USB
[15:40:26] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[15:40:26] ============ [PASSED] drmm_connector_hdmi_init =============
[15:40:26] ============= drmm_connector_init (3 subtests) =============
[15:40:26] [PASSED] drm_test_drmm_connector_init
[15:40:26] [PASSED] drm_test_drmm_connector_init_null_ddc
[15:40:26] ========= drm_test_drmm_connector_init_type_valid  =========
[15:40:26] [PASSED] Unknown
[15:40:26] [PASSED] VGA
[15:40:26] [PASSED] DVI-I
[15:40:26] [PASSED] DVI-D
[15:40:26] [PASSED] DVI-A
[15:40:26] [PASSED] Composite
[15:40:26] [PASSED] SVIDEO
[15:40:26] [PASSED] LVDS
[15:40:26] [PASSED] Component
[15:40:26] [PASSED] DIN
[15:40:26] [PASSED] DP
[15:40:26] [PASSED] HDMI-A
[15:40:26] [PASSED] HDMI-B
[15:40:26] [PASSED] TV
[15:40:26] [PASSED] eDP
[15:40:26] [PASSED] Virtual
[15:40:26] [PASSED] DSI
[15:40:26] [PASSED] DPI
[15:40:26] [PASSED] Writeback
[15:40:26] [PASSED] SPI
[15:40:26] [PASSED] USB
[15:40:26] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[15:40:26] =============== [PASSED] drmm_connector_init ===============
[15:40:26] ========= drm_connector_dynamic_init (6 subtests) ==========
[15:40:26] [PASSED] drm_test_drm_connector_dynamic_init
[15:40:26] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[15:40:26] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[15:40:26] [PASSED] drm_test_drm_connector_dynamic_init_properties
[15:40:26] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[15:40:26] [PASSED] Unknown
[15:40:26] [PASSED] VGA
[15:40:26] [PASSED] DVI-I
[15:40:26] [PASSED] DVI-D
[15:40:26] [PASSED] DVI-A
[15:40:26] [PASSED] Composite
[15:40:26] [PASSED] SVIDEO
[15:40:26] [PASSED] LVDS
[15:40:26] [PASSED] Component
[15:40:26] [PASSED] DIN
[15:40:26] [PASSED] DP
[15:40:26] [PASSED] HDMI-A
[15:40:26] [PASSED] HDMI-B
[15:40:26] [PASSED] TV
[15:40:26] [PASSED] eDP
[15:40:26] [PASSED] Virtual
[15:40:26] [PASSED] DSI
[15:40:26] [PASSED] DPI
[15:40:26] [PASSED] Writeback
[15:40:26] [PASSED] SPI
[15:40:26] [PASSED] USB
[15:40:26] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[15:40:26] ======== drm_test_drm_connector_dynamic_init_name  =========
[15:40:26] [PASSED] Unknown
[15:40:26] [PASSED] VGA
[15:40:26] [PASSED] DVI-I
[15:40:26] [PASSED] DVI-D
[15:40:26] [PASSED] DVI-A
[15:40:26] [PASSED] Composite
[15:40:26] [PASSED] SVIDEO
[15:40:26] [PASSED] LVDS
[15:40:26] [PASSED] Component
[15:40:26] [PASSED] DIN
[15:40:26] [PASSED] DP
[15:40:26] [PASSED] HDMI-A
[15:40:26] [PASSED] HDMI-B
[15:40:26] [PASSED] TV
[15:40:26] [PASSED] eDP
[15:40:26] [PASSED] Virtual
[15:40:26] [PASSED] DSI
[15:40:26] [PASSED] DPI
[15:40:26] [PASSED] Writeback
[15:40:26] [PASSED] SPI
[15:40:26] [PASSED] USB
[15:40:26] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[15:40:26] =========== [PASSED] drm_connector_dynamic_init ============
[15:40:26] ==== drm_connector_dynamic_register_early (4 subtests) =====
[15:40:26] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[15:40:26] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[15:40:26] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[15:40:26] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[15:40:26] ====== [PASSED] drm_connector_dynamic_register_early =======
[15:40:26] ======= drm_connector_dynamic_register (7 subtests) ========
[15:40:26] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[15:40:26] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[15:40:26] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[15:40:26] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[15:40:26] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[15:40:26] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[15:40:26] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[15:40:26] ========= [PASSED] drm_connector_dynamic_register ==========
[15:40:26] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[15:40:26] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[15:40:26] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[15:40:26] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[15:40:26] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[15:40:26] ========== drm_test_get_tv_mode_from_name_valid  ===========
[15:40:26] [PASSED] NTSC
[15:40:26] [PASSED] NTSC-443
[15:40:26] [PASSED] NTSC-J
[15:40:26] [PASSED] PAL
[15:40:26] [PASSED] PAL-M
[15:40:26] [PASSED] PAL-N
[15:40:26] [PASSED] SECAM
[15:40:26] [PASSED] Mono
[15:40:26] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[15:40:26] [PASSED] drm_test_get_tv_mode_from_name_truncated
[15:40:26] ============ [PASSED] drm_get_tv_mode_from_name ============
[15:40:26] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[15:40:26] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[15:40:26] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[15:40:26] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[15:40:26] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[15:40:26] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[15:40:26] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[15:40:26] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[15:40:26] [PASSED] VIC 96
[15:40:26] [PASSED] VIC 97
[15:40:26] [PASSED] VIC 101
[15:40:26] [PASSED] VIC 102
[15:40:26] [PASSED] VIC 106
[15:40:26] [PASSED] VIC 107
[15:40:26] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[15:40:26] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[15:40:26] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[15:40:26] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[15:40:26] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[15:40:26] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[15:40:26] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[15:40:26] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[15:40:26] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[15:40:26] [PASSED] Automatic
[15:40:26] [PASSED] Full
[15:40:26] [PASSED] Limited 16:235
[15:40:26] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[15:40:26] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[15:40:26] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[15:40:26] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[15:40:26] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[15:40:26] [PASSED] RGB
[15:40:26] [PASSED] YUV 4:2:0
[15:40:26] [PASSED] YUV 4:2:2
[15:40:26] [PASSED] YUV 4:4:4
[15:40:26] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[15:40:26] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[15:40:26] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[15:40:26] ============= drm_damage_helper (21 subtests) ==============
[15:40:26] [PASSED] drm_test_damage_iter_no_damage
[15:40:26] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[15:40:26] [PASSED] drm_test_damage_iter_no_damage_src_moved
[15:40:26] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[15:40:26] [PASSED] drm_test_damage_iter_no_damage_not_visible
[15:40:26] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[15:40:26] [PASSED] drm_test_damage_iter_no_damage_no_fb
[15:40:26] [PASSED] drm_test_damage_iter_simple_damage
[15:40:26] [PASSED] drm_test_damage_iter_single_damage
[15:40:26] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[15:40:26] [PASSED] drm_test_damage_iter_single_damage_outside_src
[15:40:26] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[15:40:26] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[15:40:26] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[15:40:26] [PASSED] drm_test_damage_iter_single_damage_src_moved
[15:40:26] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[15:40:26] [PASSED] drm_test_damage_iter_damage
[15:40:26] [PASSED] drm_test_damage_iter_damage_one_intersect
[15:40:26] [PASSED] drm_test_damage_iter_damage_one_outside
[15:40:26] [PASSED] drm_test_damage_iter_damage_src_moved
[15:40:26] [PASSED] drm_test_damage_iter_damage_not_visible
[15:40:26] ================ [PASSED] drm_damage_helper ================
[15:40:26] ============== drm_dp_mst_helper (3 subtests) ==============
[15:40:26] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[15:40:26] [PASSED] Clock 154000 BPP 30 DSC disabled
[15:40:26] [PASSED] Clock 234000 BPP 30 DSC disabled
[15:40:26] [PASSED] Clock 297000 BPP 24 DSC disabled
[15:40:26] [PASSED] Clock 332880 BPP 24 DSC enabled
[15:40:26] [PASSED] Clock 324540 BPP 24 DSC enabled
[15:40:26] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[15:40:26] ============== drm_test_dp_mst_calc_pbn_div  ===============
[15:40:26] [PASSED] Link rate 2000000 lane count 4
[15:40:26] [PASSED] Link rate 2000000 lane count 2
[15:40:26] [PASSED] Link rate 2000000 lane count 1
[15:40:26] [PASSED] Link rate 1350000 lane count 4
[15:40:26] [PASSED] Link rate 1350000 lane count 2
[15:40:26] [PASSED] Link rate 1350000 lane count 1
[15:40:26] [PASSED] Link rate 1000000 lane count 4
[15:40:26] [PASSED] Link rate 1000000 lane count 2
[15:40:26] [PASSED] Link rate 1000000 lane count 1
[15:40:26] [PASSED] Link rate 810000 lane count 4
[15:40:26] [PASSED] Link rate 810000 lane count 2
[15:40:26] [PASSED] Link rate 810000 lane count 1
[15:40:26] [PASSED] Link rate 540000 lane count 4
[15:40:26] [PASSED] Link rate 540000 lane count 2
[15:40:26] [PASSED] Link rate 540000 lane count 1
[15:40:26] [PASSED] Link rate 270000 lane count 4
[15:40:26] [PASSED] Link rate 270000 lane count 2
[15:40:26] [PASSED] Link rate 270000 lane count 1
[15:40:26] [PASSED] Link rate 162000 lane count 4
[15:40:26] [PASSED] Link rate 162000 lane count 2
[15:40:26] [PASSED] Link rate 162000 lane count 1
[15:40:26] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[15:40:26] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[15:40:26] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[15:40:26] [PASSED] DP_POWER_UP_PHY with port number
[15:40:26] [PASSED] DP_POWER_DOWN_PHY with port number
[15:40:26] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[15:40:26] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[15:40:26] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[15:40:26] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[15:40:26] [PASSED] DP_QUERY_PAYLOAD with port number
[15:40:26] [PASSED] DP_QUERY_PAYLOAD with VCPI
[15:40:26] [PASSED] DP_REMOTE_DPCD_READ with port number
[15:40:26] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[15:40:26] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[15:40:26] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[15:40:26] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[15:40:26] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[15:40:26] [PASSED] DP_REMOTE_I2C_READ with port number
[15:40:26] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[15:40:26] [PASSED] DP_REMOTE_I2C_READ with transactions array
[15:40:26] [PASSED] DP_REMOTE_I2C_WRITE with port number
[15:40:26] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[15:40:26] [PASSED] DP_REMOTE_I2C_WRITE with data array
[15:40:26] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[15:40:26] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[15:40:26] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[15:40:26] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[15:40:26] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[15:40:26] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[15:40:26] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[15:40:26] ================ [PASSED] drm_dp_mst_helper ================
[15:40:26] ================== drm_exec (7 subtests) ===================
[15:40:26] [PASSED] sanitycheck
[15:40:26] [PASSED] test_lock
[15:40:26] [PASSED] test_lock_unlock
[15:40:26] [PASSED] test_duplicates
[15:40:26] [PASSED] test_prepare
[15:40:26] [PASSED] test_prepare_array
[15:40:26] [PASSED] test_multiple_loops
[15:40:26] ==================== [PASSED] drm_exec =====================
[15:40:26] =========== drm_format_helper_test (17 subtests) ===========
[15:40:26] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[15:40:26] [PASSED] single_pixel_source_buffer
[15:40:26] [PASSED] single_pixel_clip_rectangle
[15:40:26] [PASSED] well_known_colors
[15:40:26] [PASSED] destination_pitch
[15:40:26] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[15:40:26] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[15:40:26] [PASSED] single_pixel_source_buffer
[15:40:26] [PASSED] single_pixel_clip_rectangle
[15:40:26] [PASSED] well_known_colors
[15:40:26] [PASSED] destination_pitch
[15:40:26] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[15:40:26] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[15:40:26] [PASSED] single_pixel_source_buffer
[15:40:26] [PASSED] single_pixel_clip_rectangle
[15:40:26] [PASSED] well_known_colors
[15:40:26] [PASSED] destination_pitch
[15:40:26] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[15:40:26] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[15:40:26] [PASSED] single_pixel_source_buffer
[15:40:26] [PASSED] single_pixel_clip_rectangle
[15:40:26] [PASSED] well_known_colors
[15:40:26] [PASSED] destination_pitch
[15:40:26] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[15:40:26] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[15:40:26] [PASSED] single_pixel_source_buffer
[15:40:26] [PASSED] single_pixel_clip_rectangle
[15:40:26] [PASSED] well_known_colors
[15:40:26] [PASSED] destination_pitch
[15:40:26] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[15:40:26] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[15:40:26] [PASSED] single_pixel_source_buffer
[15:40:26] [PASSED] single_pixel_clip_rectangle
[15:40:26] [PASSED] well_known_colors
[15:40:26] [PASSED] destination_pitch
[15:40:26] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[15:40:26] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[15:40:26] [PASSED] single_pixel_source_buffer
[15:40:26] [PASSED] single_pixel_clip_rectangle
[15:40:26] [PASSED] well_known_colors
[15:40:26] [PASSED] destination_pitch
[15:40:26] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[15:40:26] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[15:40:26] [PASSED] single_pixel_source_buffer
[15:40:26] [PASSED] single_pixel_clip_rectangle
[15:40:26] [PASSED] well_known_colors
[15:40:26] [PASSED] destination_pitch
[15:40:26] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[15:40:26] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[15:40:26] [PASSED] single_pixel_source_buffer
[15:40:26] [PASSED] single_pixel_clip_rectangle
[15:40:26] [PASSED] well_known_colors
[15:40:26] [PASSED] destination_pitch
[15:40:26] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[15:40:26] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[15:40:26] [PASSED] single_pixel_source_buffer
[15:40:26] [PASSED] single_pixel_clip_rectangle
[15:40:26] [PASSED] well_known_colors
[15:40:26] [PASSED] destination_pitch
[15:40:26] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[15:40:26] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[15:40:26] [PASSED] single_pixel_source_buffer
[15:40:26] [PASSED] single_pixel_clip_rectangle
[15:40:26] [PASSED] well_known_colors
[15:40:26] [PASSED] destination_pitch
[15:40:26] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[15:40:26] ============== drm_test_fb_xrgb8888_to_mono  ===============
[15:40:26] [PASSED] single_pixel_source_buffer
[15:40:26] [PASSED] single_pixel_clip_rectangle
[15:40:26] [PASSED] well_known_colors
[15:40:26] [PASSED] destination_pitch
[15:40:26] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[15:40:26] ==================== drm_test_fb_swab  =====================
[15:40:26] [PASSED] single_pixel_source_buffer
[15:40:26] [PASSED] single_pixel_clip_rectangle
[15:40:26] [PASSED] well_known_colors
[15:40:26] [PASSED] destination_pitch
[15:40:26] ================ [PASSED] drm_test_fb_swab =================
[15:40:26] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[15:40:26] [PASSED] single_pixel_source_buffer
[15:40:26] [PASSED] single_pixel_clip_rectangle
[15:40:26] [PASSED] well_known_colors
[15:40:26] [PASSED] destination_pitch
[15:40:26] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[15:40:26] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[15:40:26] [PASSED] single_pixel_source_buffer
[15:40:26] [PASSED] single_pixel_clip_rectangle
[15:40:26] [PASSED] well_known_colors
[15:40:26] [PASSED] destination_pitch
[15:40:26] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[15:40:26] ================= drm_test_fb_clip_offset  =================
[15:40:26] [PASSED] pass through
[15:40:26] [PASSED] horizontal offset
[15:40:26] [PASSED] vertical offset
[15:40:26] [PASSED] horizontal and vertical offset
[15:40:26] [PASSED] horizontal offset (custom pitch)
[15:40:26] [PASSED] vertical offset (custom pitch)
[15:40:26] [PASSED] horizontal and vertical offset (custom pitch)
[15:40:26] ============= [PASSED] drm_test_fb_clip_offset =============
[15:40:26] =================== drm_test_fb_memcpy  ====================
[15:40:26] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[15:40:26] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[15:40:26] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[15:40:26] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[15:40:26] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[15:40:26] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[15:40:26] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[15:40:26] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[15:40:26] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[15:40:26] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[15:40:26] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[15:40:26] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[15:40:26] =============== [PASSED] drm_test_fb_memcpy ================
[15:40:26] ============= [PASSED] drm_format_helper_test ==============
[15:40:26] ================= drm_format (18 subtests) =================
[15:40:26] [PASSED] drm_test_format_block_width_invalid
[15:40:26] [PASSED] drm_test_format_block_width_one_plane
[15:40:26] [PASSED] drm_test_format_block_width_two_plane
[15:40:26] [PASSED] drm_test_format_block_width_three_plane
[15:40:26] [PASSED] drm_test_format_block_width_tiled
[15:40:26] [PASSED] drm_test_format_block_height_invalid
[15:40:26] [PASSED] drm_test_format_block_height_one_plane
[15:40:26] [PASSED] drm_test_format_block_height_two_plane
[15:40:26] [PASSED] drm_test_format_block_height_three_plane
[15:40:26] [PASSED] drm_test_format_block_height_tiled
[15:40:26] [PASSED] drm_test_format_min_pitch_invalid
[15:40:26] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[15:40:26] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[15:40:26] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[15:40:26] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[15:40:26] [PASSED] drm_test_format_min_pitch_two_plane
[15:40:26] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[15:40:26] [PASSED] drm_test_format_min_pitch_tiled
[15:40:26] =================== [PASSED] drm_format ====================
[15:40:26] ============== drm_framebuffer (10 subtests) ===============
[15:40:26] ========== drm_test_framebuffer_check_src_coords  ==========
[15:40:26] [PASSED] Success: source fits into fb
[15:40:26] [PASSED] Fail: overflowing fb with x-axis coordinate
[15:40:26] [PASSED] Fail: overflowing fb with y-axis coordinate
[15:40:26] [PASSED] Fail: overflowing fb with source width
[15:40:26] [PASSED] Fail: overflowing fb with source height
[15:40:26] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[15:40:26] [PASSED] drm_test_framebuffer_cleanup
[15:40:26] =============== drm_test_framebuffer_create  ===============
[15:40:26] [PASSED] ABGR8888 normal sizes
[15:40:26] [PASSED] ABGR8888 max sizes
[15:40:26] [PASSED] ABGR8888 pitch greater than min required
[15:40:26] [PASSED] ABGR8888 pitch less than min required
[15:40:26] [PASSED] ABGR8888 Invalid width
[15:40:26] [PASSED] ABGR8888 Invalid buffer handle
[15:40:26] [PASSED] No pixel format
[15:40:26] [PASSED] ABGR8888 Width 0
[15:40:26] [PASSED] ABGR8888 Height 0
[15:40:26] [PASSED] ABGR8888 Out of bound height * pitch combination
[15:40:26] [PASSED] ABGR8888 Large buffer offset
[15:40:26] [PASSED] ABGR8888 Buffer offset for inexistent plane
[15:40:26] [PASSED] ABGR8888 Invalid flag
[15:40:26] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[15:40:26] [PASSED] ABGR8888 Valid buffer modifier
[15:40:26] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[15:40:26] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[15:40:26] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[15:40:26] [PASSED] NV12 Normal sizes
[15:40:26] [PASSED] NV12 Max sizes
[15:40:26] [PASSED] NV12 Invalid pitch
[15:40:26] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[15:40:26] [PASSED] NV12 different  modifier per-plane
[15:40:26] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[15:40:26] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[15:40:26] [PASSED] NV12 Modifier for inexistent plane
[15:40:26] [PASSED] NV12 Handle for inexistent plane
[15:40:26] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[15:40:26] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[15:40:26] [PASSED] YVU420 Normal sizes
[15:40:26] [PASSED] YVU420 Max sizes
[15:40:26] [PASSED] YVU420 Invalid pitch
[15:40:26] [PASSED] YVU420 Different pitches
[15:40:26] [PASSED] YVU420 Different buffer offsets/pitches
[15:40:26] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[15:40:26] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[15:40:26] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[15:40:26] [PASSED] YVU420 Valid modifier
[15:40:26] [PASSED] YVU420 Different modifiers per plane
[15:40:26] [PASSED] YVU420 Modifier for inexistent plane
[15:40:26] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[15:40:26] [PASSED] X0L2 Normal sizes
[15:40:26] [PASSED] X0L2 Max sizes
[15:40:26] [PASSED] X0L2 Invalid pitch
[15:40:26] [PASSED] X0L2 Pitch greater than minimum required
[15:40:26] [PASSED] X0L2 Handle for inexistent plane
[15:40:26] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[15:40:26] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[15:40:26] [PASSED] X0L2 Valid modifier
[15:40:26] [PASSED] X0L2 Modifier for inexistent plane
[15:40:26] =========== [PASSED] drm_test_framebuffer_create ===========
[15:40:26] [PASSED] drm_test_framebuffer_free
[15:40:26] [PASSED] drm_test_framebuffer_init
[15:40:26] [PASSED] drm_test_framebuffer_init_bad_format
[15:40:26] [PASSED] drm_test_framebuffer_init_dev_mismatch
[15:40:26] [PASSED] drm_test_framebuffer_lookup
[15:40:26] [PASSED] drm_test_framebuffer_lookup_inexistent
[15:40:26] [PASSED] drm_test_framebuffer_modifiers_not_supported
[15:40:26] ================= [PASSED] drm_framebuffer =================
[15:40:26] ================ drm_gem_shmem (8 subtests) ================
[15:40:26] [PASSED] drm_gem_shmem_test_obj_create
[15:40:26] [PASSED] drm_gem_shmem_test_obj_create_private
[15:40:26] [PASSED] drm_gem_shmem_test_pin_pages
[15:40:26] [PASSED] drm_gem_shmem_test_vmap
[15:40:26] [PASSED] drm_gem_shmem_test_get_pages_sgt
[15:40:26] [PASSED] drm_gem_shmem_test_get_sg_table
[15:40:26] [PASSED] drm_gem_shmem_test_madvise
[15:40:26] [PASSED] drm_gem_shmem_test_purge
[15:40:26] ================== [PASSED] drm_gem_shmem ==================
[15:40:26] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[15:40:26] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[15:40:26] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[15:40:26] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[15:40:26] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[15:40:26] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[15:40:26] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[15:40:26] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[15:40:26] [PASSED] Automatic
[15:40:26] [PASSED] Full
[15:40:26] [PASSED] Limited 16:235
[15:40:26] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[15:40:26] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[15:40:26] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[15:40:26] [PASSED] drm_test_check_disable_connector
[15:40:26] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[15:40:26] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[15:40:26] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[15:40:26] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[15:40:26] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[15:40:26] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[15:40:26] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[15:40:26] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[15:40:26] [PASSED] drm_test_check_output_bpc_dvi
[15:40:26] [PASSED] drm_test_check_output_bpc_format_vic_1
[15:40:26] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[15:40:26] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[15:40:26] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[15:40:26] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[15:40:26] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[15:40:26] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[15:40:26] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[15:40:26] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[15:40:26] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[15:40:26] [PASSED] drm_test_check_broadcast_rgb_value
[15:40:26] [PASSED] drm_test_check_bpc_8_value
[15:40:26] [PASSED] drm_test_check_bpc_10_value
[15:40:26] [PASSED] drm_test_check_bpc_12_value
[15:40:26] [PASSED] drm_test_check_format_value
[15:40:26] [PASSED] drm_test_check_tmds_char_value
[15:40:26] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[15:40:26] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[15:40:26] [PASSED] drm_test_check_mode_valid
[15:40:26] [PASSED] drm_test_check_mode_valid_reject
[15:40:26] [PASSED] drm_test_check_mode_valid_reject_rate
[15:40:26] [PASSED] drm_test_check_mode_valid_reject_max_clock
[15:40:26] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[15:40:26] ================= drm_managed (2 subtests) =================
[15:40:26] [PASSED] drm_test_managed_release_action
[15:40:26] [PASSED] drm_test_managed_run_action
[15:40:26] =================== [PASSED] drm_managed ===================
[15:40:26] =================== drm_mm (6 subtests) ====================
[15:40:26] [PASSED] drm_test_mm_init
[15:40:26] [PASSED] drm_test_mm_debug
[15:40:26] [PASSED] drm_test_mm_align32
[15:40:26] [PASSED] drm_test_mm_align64
[15:40:26] [PASSED] drm_test_mm_lowest
[15:40:26] [PASSED] drm_test_mm_highest
[15:40:26] ===================== [PASSED] drm_mm ======================
[15:40:26] ============= drm_modes_analog_tv (5 subtests) =============
[15:40:26] [PASSED] drm_test_modes_analog_tv_mono_576i
[15:40:26] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[15:40:26] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[15:40:26] [PASSED] drm_test_modes_analog_tv_pal_576i
[15:40:26] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[15:40:26] =============== [PASSED] drm_modes_analog_tv ===============
[15:40:26] ============== drm_plane_helper (2 subtests) ===============
[15:40:26] =============== drm_test_check_plane_state  ================
[15:40:26] [PASSED] clipping_simple
[15:40:26] [PASSED] clipping_rotate_reflect
[15:40:26] [PASSED] positioning_simple
[15:40:26] [PASSED] upscaling
[15:40:26] [PASSED] downscaling
[15:40:26] [PASSED] rounding1
[15:40:26] [PASSED] rounding2
[15:40:26] [PASSED] rounding3
[15:40:26] [PASSED] rounding4
[15:40:26] =========== [PASSED] drm_test_check_plane_state ============
[15:40:26] =========== drm_test_check_invalid_plane_state  ============
[15:40:26] [PASSED] positioning_invalid
[15:40:26] [PASSED] upscaling_invalid
[15:40:26] [PASSED] downscaling_invalid
[15:40:26] ======= [PASSED] drm_test_check_invalid_plane_state ========
[15:40:26] ================ [PASSED] drm_plane_helper =================
[15:40:26] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[15:40:26] ====== drm_test_connector_helper_tv_get_modes_check  =======
[15:40:26] [PASSED] None
[15:40:26] [PASSED] PAL
[15:40:26] [PASSED] NTSC
[15:40:26] [PASSED] Both, NTSC Default
[15:40:26] [PASSED] Both, PAL Default
[15:40:26] [PASSED] Both, NTSC Default, with PAL on command-line
[15:40:26] [PASSED] Both, PAL Default, with NTSC on command-line
[15:40:26] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[15:40:26] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[15:40:26] ================== drm_rect (9 subtests) ===================
[15:40:26] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[15:40:26] [PASSED] drm_test_rect_clip_scaled_not_clipped
[15:40:26] [PASSED] drm_test_rect_clip_scaled_clipped
[15:40:26] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[15:40:26] ================= drm_test_rect_intersect  =================
[15:40:26] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[15:40:26] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[15:40:26] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[15:40:26] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[15:40:26] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[15:40:26] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[15:40:26] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[15:40:26] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[15:40:26] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[15:40:26] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[15:40:26] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[15:40:26] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[15:40:26] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[15:40:26] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[15:40:26] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[15:40:26] ============= [PASSED] drm_test_rect_intersect =============
[15:40:26] ================ drm_test_rect_calc_hscale  ================
[15:40:26] [PASSED] normal use
[15:40:26] [PASSED] out of max range
[15:40:26] [PASSED] out of min range
[15:40:26] [PASSED] zero dst
[15:40:26] [PASSED] negative src
[15:40:26] [PASSED] negative dst
[15:40:26] ============ [PASSED] drm_test_rect_calc_hscale ============
[15:40:26] ================ drm_test_rect_calc_vscale  ================
[15:40:26] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[15:40:26] [PASSED] out of max range
[15:40:26] [PASSED] out of min range
[15:40:26] [PASSED] zero dst
[15:40:26] [PASSED] negative src
[15:40:26] [PASSED] negative dst
[15:40:26] ============ [PASSED] drm_test_rect_calc_vscale ============
[15:40:26] ================== drm_test_rect_rotate  ===================
[15:40:26] [PASSED] reflect-x
[15:40:26] [PASSED] reflect-y
[15:40:26] [PASSED] rotate-0
[15:40:26] [PASSED] rotate-90
[15:40:26] [PASSED] rotate-180
[15:40:26] [PASSED] rotate-270
[15:40:26] ============== [PASSED] drm_test_rect_rotate ===============
[15:40:26] ================ drm_test_rect_rotate_inv  =================
[15:40:26] [PASSED] reflect-x
[15:40:26] [PASSED] reflect-y
[15:40:26] [PASSED] rotate-0
[15:40:26] [PASSED] rotate-90
[15:40:26] [PASSED] rotate-180
[15:40:26] [PASSED] rotate-270
[15:40:26] ============ [PASSED] drm_test_rect_rotate_inv =============
[15:40:26] ==================== [PASSED] drm_rect =====================
[15:40:26] ============ drm_sysfb_modeset_test (1 subtest) ============
[15:40:26] ============ drm_test_sysfb_build_fourcc_list  =============
[15:40:26] [PASSED] no native formats
[15:40:26] [PASSED] XRGB8888 as native format
[15:40:26] [PASSED] remove duplicates
[15:40:26] [PASSED] convert alpha formats
[15:40:26] [PASSED] random formats
[15:40:26] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[15:40:26] ============= [PASSED] drm_sysfb_modeset_test ==============
[15:40:26] ============================================================
[15:40:26] Testing complete. Ran 622 tests: passed: 622
[15:40:26] Elapsed time: 26.923s total, 1.653s configuring, 24.849s building, 0.385s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[15:40:26] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[15:40:28] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[15:40:37] Starting KUnit Kernel (1/1)...
[15:40:37] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[15:40:37] ================= ttm_device (5 subtests) ==================
[15:40:37] [PASSED] ttm_device_init_basic
[15:40:37] [PASSED] ttm_device_init_multiple
[15:40:37] [PASSED] ttm_device_fini_basic
[15:40:37] [PASSED] ttm_device_init_no_vma_man
[15:40:37] ================== ttm_device_init_pools  ==================
[15:40:37] [PASSED] No DMA allocations, no DMA32 required
[15:40:37] [PASSED] DMA allocations, DMA32 required
[15:40:37] [PASSED] No DMA allocations, DMA32 required
[15:40:37] [PASSED] DMA allocations, no DMA32 required
[15:40:37] ============== [PASSED] ttm_device_init_pools ==============
[15:40:37] =================== [PASSED] ttm_device ====================
[15:40:37] ================== ttm_pool (8 subtests) ===================
[15:40:37] ================== ttm_pool_alloc_basic  ===================
[15:40:37] [PASSED] One page
[15:40:37] [PASSED] More than one page
[15:40:37] [PASSED] Above the allocation limit
[15:40:37] [PASSED] One page, with coherent DMA mappings enabled
[15:40:37] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[15:40:37] ============== [PASSED] ttm_pool_alloc_basic ===============
[15:40:37] ============== ttm_pool_alloc_basic_dma_addr  ==============
[15:40:37] [PASSED] One page
[15:40:37] [PASSED] More than one page
[15:40:37] [PASSED] Above the allocation limit
[15:40:37] [PASSED] One page, with coherent DMA mappings enabled
[15:40:37] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[15:40:37] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[15:40:37] [PASSED] ttm_pool_alloc_order_caching_match
[15:40:37] [PASSED] ttm_pool_alloc_caching_mismatch
[15:40:37] [PASSED] ttm_pool_alloc_order_mismatch
[15:40:37] [PASSED] ttm_pool_free_dma_alloc
[15:40:37] [PASSED] ttm_pool_free_no_dma_alloc
[15:40:37] [PASSED] ttm_pool_fini_basic
[15:40:37] ==================== [PASSED] ttm_pool =====================
[15:40:37] ================ ttm_resource (8 subtests) =================
[15:40:37] ================= ttm_resource_init_basic  =================
[15:40:37] [PASSED] Init resource in TTM_PL_SYSTEM
[15:40:37] [PASSED] Init resource in TTM_PL_VRAM
[15:40:37] [PASSED] Init resource in a private placement
[15:40:37] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[15:40:37] ============= [PASSED] ttm_resource_init_basic =============
[15:40:37] [PASSED] ttm_resource_init_pinned
[15:40:37] [PASSED] ttm_resource_fini_basic
[15:40:37] [PASSED] ttm_resource_manager_init_basic
[15:40:37] [PASSED] ttm_resource_manager_usage_basic
[15:40:37] [PASSED] ttm_resource_manager_set_used_basic
[15:40:37] [PASSED] ttm_sys_man_alloc_basic
[15:40:37] [PASSED] ttm_sys_man_free_basic
[15:40:37] ================== [PASSED] ttm_resource ===================
[15:40:37] =================== ttm_tt (15 subtests) ===================
[15:40:37] ==================== ttm_tt_init_basic  ====================
[15:40:37] [PASSED] Page-aligned size
[15:40:37] [PASSED] Extra pages requested
[15:40:37] ================ [PASSED] ttm_tt_init_basic ================
[15:40:37] [PASSED] ttm_tt_init_misaligned
[15:40:37] [PASSED] ttm_tt_fini_basic
[15:40:37] [PASSED] ttm_tt_fini_sg
[15:40:37] [PASSED] ttm_tt_fini_shmem
[15:40:37] [PASSED] ttm_tt_create_basic
[15:40:37] [PASSED] ttm_tt_create_invalid_bo_type
[15:40:37] [PASSED] ttm_tt_create_ttm_exists
[15:40:37] [PASSED] ttm_tt_create_failed
[15:40:37] [PASSED] ttm_tt_destroy_basic
[15:40:37] [PASSED] ttm_tt_populate_null_ttm
[15:40:37] [PASSED] ttm_tt_populate_populated_ttm
[15:40:37] [PASSED] ttm_tt_unpopulate_basic
[15:40:37] [PASSED] ttm_tt_unpopulate_empty_ttm
[15:40:37] [PASSED] ttm_tt_swapin_basic
[15:40:37] ===================== [PASSED] ttm_tt ======================
[15:40:37] =================== ttm_bo (14 subtests) ===================
[15:40:37] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[15:40:37] [PASSED] Cannot be interrupted and sleeps
[15:40:37] [PASSED] Cannot be interrupted, locks straight away
[15:40:37] [PASSED] Can be interrupted, sleeps
[15:40:37] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[15:40:37] [PASSED] ttm_bo_reserve_locked_no_sleep
[15:40:37] [PASSED] ttm_bo_reserve_no_wait_ticket
[15:40:37] [PASSED] ttm_bo_reserve_double_resv
[15:40:37] [PASSED] ttm_bo_reserve_interrupted
[15:40:37] [PASSED] ttm_bo_reserve_deadlock
[15:40:37] [PASSED] ttm_bo_unreserve_basic
[15:40:37] [PASSED] ttm_bo_unreserve_pinned
[15:40:37] [PASSED] ttm_bo_unreserve_bulk
[15:40:37] [PASSED] ttm_bo_fini_basic
[15:40:37] [PASSED] ttm_bo_fini_shared_resv
[15:40:37] [PASSED] ttm_bo_pin_basic
[15:40:37] [PASSED] ttm_bo_pin_unpin_resource
[15:40:37] [PASSED] ttm_bo_multiple_pin_one_unpin
[15:40:37] ===================== [PASSED] ttm_bo ======================
[15:40:37] ============== ttm_bo_validate (21 subtests) ===============
[15:40:37] ============== ttm_bo_init_reserved_sys_man  ===============
[15:40:37] [PASSED] Buffer object for userspace
[15:40:37] [PASSED] Kernel buffer object
[15:40:37] [PASSED] Shared buffer object
[15:40:37] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[15:40:37] ============== ttm_bo_init_reserved_mock_man  ==============
[15:40:37] [PASSED] Buffer object for userspace
[15:40:37] [PASSED] Kernel buffer object
[15:40:37] [PASSED] Shared buffer object
[15:40:37] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[15:40:37] [PASSED] ttm_bo_init_reserved_resv
[15:40:37] ================== ttm_bo_validate_basic  ==================
[15:40:37] [PASSED] Buffer object for userspace
[15:40:37] [PASSED] Kernel buffer object
[15:40:37] [PASSED] Shared buffer object
[15:40:37] ============== [PASSED] ttm_bo_validate_basic ==============
[15:40:37] [PASSED] ttm_bo_validate_invalid_placement
[15:40:37] ============= ttm_bo_validate_same_placement  ==============
[15:40:37] [PASSED] System manager
[15:40:37] [PASSED] VRAM manager
[15:40:37] ========= [PASSED] ttm_bo_validate_same_placement ==========
[15:40:37] [PASSED] ttm_bo_validate_failed_alloc
[15:40:37] [PASSED] ttm_bo_validate_pinned
[15:40:37] [PASSED] ttm_bo_validate_busy_placement
[15:40:37] ================ ttm_bo_validate_multihop  =================
[15:40:37] [PASSED] Buffer object for userspace
[15:40:37] [PASSED] Kernel buffer object
[15:40:37] [PASSED] Shared buffer object
[15:40:37] ============ [PASSED] ttm_bo_validate_multihop =============
[15:40:37] ========== ttm_bo_validate_no_placement_signaled  ==========
[15:40:37] [PASSED] Buffer object in system domain, no page vector
[15:40:37] [PASSED] Buffer object in system domain with an existing page vector
[15:40:37] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[15:40:37] ======== ttm_bo_validate_no_placement_not_signaled  ========
[15:40:37] [PASSED] Buffer object for userspace
[15:40:37] [PASSED] Kernel buffer object
[15:40:37] [PASSED] Shared buffer object
[15:40:37] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[15:40:37] [PASSED] ttm_bo_validate_move_fence_signaled
[15:40:37] ========= ttm_bo_validate_move_fence_not_signaled  =========
[15:40:37] [PASSED] Waits for GPU
[15:40:37] [PASSED] Tries to lock straight away
[15:40:37] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[15:40:37] [PASSED] ttm_bo_validate_happy_evict
[15:40:37] [PASSED] ttm_bo_validate_all_pinned_evict
[15:40:37] [PASSED] ttm_bo_validate_allowed_only_evict
[15:40:37] [PASSED] ttm_bo_validate_deleted_evict
[15:40:37] [PASSED] ttm_bo_validate_busy_domain_evict
[15:40:37] [PASSED] ttm_bo_validate_evict_gutting
[15:40:37] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[15:40:37] ================= [PASSED] ttm_bo_validate =================
[15:40:37] ============================================================
[15:40:37] Testing complete. Ran 101 tests: passed: 101
[15:40:37] Elapsed time: 11.184s total, 1.684s configuring, 9.283s building, 0.191s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel



^ permalink raw reply	[flat|nested] 12+ messages in thread
* ✓ Xe.CI.BAT: success for drm/xe/guc: Remove cached frequency values for GuC SLPC
  2025-10-29 11:20 [PATCH v5 0/2] drm/xe/guc: Remove cached frequency values for GuC SLPC Sk Anirban
                   ` (2 preceding siblings ...)
  2025-10-29 15:40 ` ✓ CI.KUnit: success for drm/xe/guc: Remove cached frequency values for GuC SLPC Patchwork
@ 2025-10-29 16:28 ` Patchwork
  3 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2025-10-29 16:28 UTC (permalink / raw)
  To: Sk Anirban; +Cc: intel-xe

[-- Attachment #1: Type: text/plain, Size: 878 bytes --]

== Series Details ==

Series: drm/xe/guc: Remove cached frequency values for GuC SLPC
URL   : https://patchwork.freedesktop.org/series/156738/
State : success

== Summary ==

CI Bug Log - changes from xe-4003-c96b6fcb185b5fd5ebc9ea5d788a94a0f477d4ae_BAT -> xe-pw-156738v1_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 13)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * Linux: xe-4003-c96b6fcb185b5fd5ebc9ea5d788a94a0f477d4ae -> xe-pw-156738v1

  IGT_8600: 8600
  xe-4003-c96b6fcb185b5fd5ebc9ea5d788a94a0f477d4ae: c96b6fcb185b5fd5ebc9ea5d788a94a0f477d4ae
  xe-pw-156738v1: 156738v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156738v1/index.html

[-- Attachment #2: Type: text/html, Size: 1426 bytes --]

^ permalink raw reply	[flat|nested] 12+ messages in thread
* Re: [PATCH v5 1/2] drm/xe/guc: Eliminate RPe caching for SLPC parameter handling
  2025-10-29 11:20 ` [PATCH v5 1/2] drm/xe/guc: Eliminate RPe caching for SLPC parameter handling Sk Anirban
@ 2025-10-29 18:04   ` Rodrigo Vivi
  2025-10-29 18:35     ` Anirban, Sk
  0 siblings, 1 reply; 12+ messages in thread
From: Rodrigo Vivi @ 2025-10-29 18:04 UTC (permalink / raw)
  To: Sk Anirban
  Cc: intel-xe, anshuman.gupta, badal.nilawar, riana.tauro,
	karthik.poosa, raag.jadav, soham.purkait, mallesh.koujalagi,
	vinay.belgaumkar

On Wed, Oct 29, 2025 at 04:50:16PM +0530, Sk Anirban wrote:
> RPe is runtime-determined by PCODE and caching it caused stale values,
> leading to incorrect GuC SLPC parameter settings.
> Drop the cached rpe_freq field and query fresh values from hardware
> on each use to ensure GuC SLPC parameters reflect current RPe.
> 
> v2: Remove cached RPe frequency field (Rodrigo)
> v3: Remove extra variable (Vinay)
>     Modify function name (Vinay)
> v4: Maintain a separate function for PVC (Rodrigo)
> v5: Update RPn while fetching RPe frequency
> 
> Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/5166
> Signed-off-by: Sk Anirban <sk.anirban@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_guc_pc.c       | 75 ++++++++++++++++------------
>  drivers/gpu/drm/xe/xe_guc_pc_types.h |  2 -
>  2 files changed, 42 insertions(+), 35 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
> index 3c0feb50a1e2..08deaa64aa85 100644
> --- a/drivers/gpu/drm/xe/xe_guc_pc.c
> +++ b/drivers/gpu/drm/xe/xe_guc_pc.c
> @@ -330,7 +330,7 @@ static int pc_set_min_freq(struct xe_guc_pc *pc, u32 freq)
>  	 * Our goal is to have the admin choices respected.
>  	 */
>  	pc_action_set_param(pc, SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY,
> -			    freq < pc->rpe_freq);
> +			    freq < xe_guc_pc_get_rpe_freq(pc));
>  
>  	return pc_action_set_param(pc,
>  				   SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
> @@ -375,7 +375,7 @@ static void mtl_update_rpa_value(struct xe_guc_pc *pc)
>  	pc->rpa_freq = decode_freq(REG_FIELD_GET(MTL_RPA_MASK, reg));
>  }
>  
> -static void mtl_update_rpe_value(struct xe_guc_pc *pc)
> +static u32 mtl_get_rpe_freq(struct xe_guc_pc *pc)
>  {
>  	struct xe_gt *gt = pc_to_gt(pc);
>  	u32 reg;
> @@ -385,7 +385,7 @@ static void mtl_update_rpe_value(struct xe_guc_pc *pc)
>  	else
>  		reg = xe_mmio_read32(&gt->mmio, MTL_GT_RPE_FREQUENCY);
>  
> -	pc->rpe_freq = decode_freq(REG_FIELD_GET(MTL_RPE_MASK, reg));
> +	return decode_freq(REG_FIELD_GET(MTL_RPE_MASK, reg));
>  }
>  
>  static void tgl_update_rpa_value(struct xe_guc_pc *pc)
> @@ -408,24 +408,22 @@ static void tgl_update_rpa_value(struct xe_guc_pc *pc)
>  	}
>  }
>  
> -static void tgl_update_rpe_value(struct xe_guc_pc *pc)
> +static u32 pvc_get_rpe_freq(struct xe_guc_pc *pc)
>  {
>  	struct xe_gt *gt = pc_to_gt(pc);
> -	struct xe_device *xe = gt_to_xe(gt);
>  	u32 reg;
>  
> -	/*
> -	 * For PVC we still need to use fused RP1 as the approximation for RPe
> -	 * For other platforms than PVC we get the resolved RPe directly from
> -	 * PCODE at a different register
> -	 */
> -	if (xe->info.platform == XE_PVC) {
> -		reg = xe_mmio_read32(&gt->mmio, PVC_RP_STATE_CAP);
> -		pc->rpe_freq = REG_FIELD_GET(RP1_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
> -	} else {
> -		reg = xe_mmio_read32(&gt->mmio, FREQ_INFO_REC);
> -		pc->rpe_freq = REG_FIELD_GET(RPE_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
> -	}
> +	reg = xe_mmio_read32(&gt->mmio, PVC_RP_STATE_CAP);
> +	return REG_FIELD_GET(RP1_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
> +}
> +
> +static u32 tgl_get_rpe_freq(struct xe_guc_pc *pc)
> +{
> +	struct xe_gt *gt = pc_to_gt(pc);
> +	u32 reg;
> +
> +	reg = xe_mmio_read32(&gt->mmio, FREQ_INFO_REC);
> +	return REG_FIELD_GET(RPE_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
>  }
>  
>  static void pc_update_rp_values(struct xe_guc_pc *pc)
> @@ -433,20 +431,10 @@ static void pc_update_rp_values(struct xe_guc_pc *pc)
>  	struct xe_gt *gt = pc_to_gt(pc);
>  	struct xe_device *xe = gt_to_xe(gt);
>  
> -	if (GRAPHICS_VERx100(xe) >= 1270) {
> +	if (GRAPHICS_VERx100(xe) >= 1270)
>  		mtl_update_rpa_value(pc);
> -		mtl_update_rpe_value(pc);
> -	} else {
> +	else
>  		tgl_update_rpa_value(pc);
> -		tgl_update_rpe_value(pc);
> -	}
> -
> -	/*
> -	 * RPe is decided at runtime by PCODE. In the rare case where that's
> -	 * smaller than the fused min, we will trust the PCODE and use that
> -	 * as our minimum one.
> -	 */
> -	pc->rpn_freq = min(pc->rpn_freq, pc->rpe_freq);
>  }
>  
>  /**
> @@ -560,9 +548,30 @@ u32 xe_guc_pc_get_rpa_freq(struct xe_guc_pc *pc)
>   */
>  u32 xe_guc_pc_get_rpe_freq(struct xe_guc_pc *pc)
>  {
> -	pc_update_rp_values(pc);
> +	struct xe_gt *gt = pc_to_gt(pc);
> +	struct xe_device *xe = gt_to_xe(gt);
> +	u32 freq;
>  
> -	return pc->rpe_freq;
> +	/*
> +	 * For PVC we still need to use fused RP1 as the approximation for RPe
> +	 * For other platforms than PVC we get the resolved RPe directly from
> +	 * PCODE at a different register
> +	 */
> +	if (xe->info.platform == XE_PVC)

I believe it would be better to convert this to the graphics version here
instead of the platform name. But no block since it was already a platform check
above.

> +		freq = pvc_get_rpe_freq(pc);
> +	else if (GRAPHICS_VERx100(xe) >= 1270)
> +		freq = mtl_get_rpe_freq(pc);
> +	else
> +		freq = tgl_get_rpe_freq(pc);
> +
> +	/*
> +	 * RPe is decided at runtime by PCODE. In the rare case where that's
> +	 * smaller than the fused min, we will trust the PCODE and use that
> +	 * as our minimum one.
> +	 */
> +	pc->rpn_freq = min(pc->rpn_freq, freq);

setting rpn_freq inside this get_rpe function makes no sense.

I'm sorry I forgot about this when I told you to kill the other function.
It should stay there, but be called update_rpn instead...

> +
> +	return freq;
>  }
>  
>  /**
> @@ -1021,7 +1030,7 @@ static int pc_set_mert_freq_cap(struct xe_guc_pc *pc)
>  	/*
>  	 * Ensure min and max are bound by MERT_FREQ_CAP until driver loads.
>  	 */
> -	ret = pc_set_min_freq(pc, min(pc->rpe_freq, pc_max_freq_cap(pc)));
> +	ret = pc_set_min_freq(pc, min(xe_guc_pc_get_rpe_freq(pc), pc_max_freq_cap(pc)));
>  	if (!ret)
>  		ret = pc_set_max_freq(pc, min(pc->rp0_freq, pc_max_freq_cap(pc)));
>  
> @@ -1339,7 +1348,7 @@ static void xe_guc_pc_fini_hw(void *arg)
>  	XE_WARN_ON(xe_guc_pc_stop(pc));
>  
>  	/* Bind requested freq to mert_freq_cap before unload */
> -	pc_set_cur_freq(pc, min(pc_max_freq_cap(pc), pc->rpe_freq));
> +	pc_set_cur_freq(pc, min(pc_max_freq_cap(pc), xe_guc_pc_get_rpe_freq(pc)));
>  
>  	xe_force_wake_put(gt_to_fw(pc_to_gt(pc)), fw_ref);
>  }
> diff --git a/drivers/gpu/drm/xe/xe_guc_pc_types.h b/drivers/gpu/drm/xe/xe_guc_pc_types.h
> index 5e4ea53fbee6..f27c05d81706 100644
> --- a/drivers/gpu/drm/xe/xe_guc_pc_types.h
> +++ b/drivers/gpu/drm/xe/xe_guc_pc_types.h
> @@ -21,8 +21,6 @@ struct xe_guc_pc {
>  	u32 rp0_freq;
>  	/** @rpa_freq: HW RPa frequency - The Achievable one */
>  	u32 rpa_freq;
> -	/** @rpe_freq: HW RPe frequency - The Efficient one */
> -	u32 rpe_freq;
>  	/** @rpn_freq: HW RPN frequency - The Minimum one */
>  	u32 rpn_freq;
>  	/** @user_requested_min: Stash the minimum requested freq by user */
> -- 
> 2.43.0
> 

^ permalink raw reply	[flat|nested] 12+ messages in thread
* Re: [PATCH v5 1/2] drm/xe/guc: Eliminate RPe caching for SLPC parameter handling
  2025-10-29 18:04   ` Rodrigo Vivi
@ 2025-10-29 18:35     ` Anirban, Sk
  2025-10-29 19:58       ` Vivi, Rodrigo
  0 siblings, 1 reply; 12+ messages in thread
From: Anirban, Sk @ 2025-10-29 18:35 UTC (permalink / raw)
  To: Rodrigo Vivi
  Cc: intel-xe, anshuman.gupta, badal.nilawar, riana.tauro,
	karthik.poosa, raag.jadav, soham.purkait, mallesh.koujalagi,
	vinay.belgaumkar

Hi,

On 29-10-2025 23:34, Rodrigo Vivi wrote:
> On Wed, Oct 29, 2025 at 04:50:16PM +0530, Sk Anirban wrote:
>> RPe is runtime-determined by PCODE and caching it caused stale values,
>> leading to incorrect GuC SLPC parameter settings.
>> Drop the cached rpe_freq field and query fresh values from hardware
>> on each use to ensure GuC SLPC parameters reflect current RPe.
>>
>> v2: Remove cached RPe frequency field (Rodrigo)
>> v3: Remove extra variable (Vinay)
>>      Modify function name (Vinay)
>> v4: Maintain a separate function for PVC (Rodrigo)
>> v5: Update RPn while fetching RPe frequency
>>
>> Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/5166
>> Signed-off-by: Sk Anirban <sk.anirban@intel.com>
>> ---
>>   drivers/gpu/drm/xe/xe_guc_pc.c       | 75 ++++++++++++++++------------
>>   drivers/gpu/drm/xe/xe_guc_pc_types.h |  2 -
>>   2 files changed, 42 insertions(+), 35 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
>> index 3c0feb50a1e2..08deaa64aa85 100644
>> --- a/drivers/gpu/drm/xe/xe_guc_pc.c
>> +++ b/drivers/gpu/drm/xe/xe_guc_pc.c
>> @@ -330,7 +330,7 @@ static int pc_set_min_freq(struct xe_guc_pc *pc, u32 freq)
>>   	 * Our goal is to have the admin choices respected.
>>   	 */
>>   	pc_action_set_param(pc, SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY,
>> -			    freq < pc->rpe_freq);
>> +			    freq < xe_guc_pc_get_rpe_freq(pc));
>>   
>>   	return pc_action_set_param(pc,
>>   				   SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
>> @@ -375,7 +375,7 @@ static void mtl_update_rpa_value(struct xe_guc_pc *pc)
>>   	pc->rpa_freq = decode_freq(REG_FIELD_GET(MTL_RPA_MASK, reg));
>>   }
>>   
>> -static void mtl_update_rpe_value(struct xe_guc_pc *pc)
>> +static u32 mtl_get_rpe_freq(struct xe_guc_pc *pc)
>>   {
>>   	struct xe_gt *gt = pc_to_gt(pc);
>>   	u32 reg;
>> @@ -385,7 +385,7 @@ static void mtl_update_rpe_value(struct xe_guc_pc *pc)
>>   	else
>>   		reg = xe_mmio_read32(&gt->mmio, MTL_GT_RPE_FREQUENCY);
>>   
>> -	pc->rpe_freq = decode_freq(REG_FIELD_GET(MTL_RPE_MASK, reg));
>> +	return decode_freq(REG_FIELD_GET(MTL_RPE_MASK, reg));
>>   }
>>   
>>   static void tgl_update_rpa_value(struct xe_guc_pc *pc)
>> @@ -408,24 +408,22 @@ static void tgl_update_rpa_value(struct xe_guc_pc *pc)
>>   	}
>>   }
>>   
>> -static void tgl_update_rpe_value(struct xe_guc_pc *pc)
>> +static u32 pvc_get_rpe_freq(struct xe_guc_pc *pc)
>>   {
>>   	struct xe_gt *gt = pc_to_gt(pc);
>> -	struct xe_device *xe = gt_to_xe(gt);
>>   	u32 reg;
>>   
>> -	/*
>> -	 * For PVC we still need to use fused RP1 as the approximation for RPe
>> -	 * For other platforms than PVC we get the resolved RPe directly from
>> -	 * PCODE at a different register
>> -	 */
>> -	if (xe->info.platform == XE_PVC) {
>> -		reg = xe_mmio_read32(&gt->mmio, PVC_RP_STATE_CAP);
>> -		pc->rpe_freq = REG_FIELD_GET(RP1_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
>> -	} else {
>> -		reg = xe_mmio_read32(&gt->mmio, FREQ_INFO_REC);
>> -		pc->rpe_freq = REG_FIELD_GET(RPE_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
>> -	}
>> +	reg = xe_mmio_read32(&gt->mmio, PVC_RP_STATE_CAP);
>> +	return REG_FIELD_GET(RP1_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
>> +}
>> +
>> +static u32 tgl_get_rpe_freq(struct xe_guc_pc *pc)
>> +{
>> +	struct xe_gt *gt = pc_to_gt(pc);
>> +	u32 reg;
>> +
>> +	reg = xe_mmio_read32(&gt->mmio, FREQ_INFO_REC);
>> +	return REG_FIELD_GET(RPE_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
>>   }
>>   
>>   static void pc_update_rp_values(struct xe_guc_pc *pc)
>> @@ -433,20 +431,10 @@ static void pc_update_rp_values(struct xe_guc_pc *pc)
>>   	struct xe_gt *gt = pc_to_gt(pc);
>>   	struct xe_device *xe = gt_to_xe(gt);
>>   
>> -	if (GRAPHICS_VERx100(xe) >= 1270) {
>> +	if (GRAPHICS_VERx100(xe) >= 1270)
>>   		mtl_update_rpa_value(pc);
>> -		mtl_update_rpe_value(pc);
>> -	} else {
>> +	else
>>   		tgl_update_rpa_value(pc);
>> -		tgl_update_rpe_value(pc);
>> -	}
>> -
>> -	/*
>> -	 * RPe is decided at runtime by PCODE. In the rare case where that's
>> -	 * smaller than the fused min, we will trust the PCODE and use that
>> -	 * as our minimum one.
>> -	 */
>> -	pc->rpn_freq = min(pc->rpn_freq, pc->rpe_freq);
>>   }
>>   
>>   /**
>> @@ -560,9 +548,30 @@ u32 xe_guc_pc_get_rpa_freq(struct xe_guc_pc *pc)
>>    */
>>   u32 xe_guc_pc_get_rpe_freq(struct xe_guc_pc *pc)
>>   {
>> -	pc_update_rp_values(pc);
>> +	struct xe_gt *gt = pc_to_gt(pc);
>> +	struct xe_device *xe = gt_to_xe(gt);
>> +	u32 freq;
>>   
>> -	return pc->rpe_freq;
>> +	/*
>> +	 * For PVC we still need to use fused RP1 as the approximation for RPe
>> +	 * For other platforms than PVC we get the resolved RPe directly from
>> +	 * PCODE at a different register
>> +	 */
>> +	if (xe->info.platform == XE_PVC)
> I believe it would be better to convert this to the graphics version here
> instead of the platform name. But no block since it was already a platform check
> above.
sure, I will look into this.
>> +		freq = pvc_get_rpe_freq(pc);
>> +	else if (GRAPHICS_VERx100(xe) >= 1270)
>> +		freq = mtl_get_rpe_freq(pc);
>> +	else
>> +		freq = tgl_get_rpe_freq(pc);
>> +
>> +	/*
>> +	 * RPe is decided at runtime by PCODE. In the rare case where that's
>> +	 * smaller than the fused min, we will trust the PCODE and use that
>> +	 * as our minimum one.
>> +	 */
>> +	pc->rpn_freq = min(pc->rpn_freq, freq);
> setting rpn_freq inside this get_rpe function makes no sense.
>
> I'm sorry I forgot about this when I told you to kill the other function.
> It should stay there, but be called update_rpn instead...
Since RPn updates depend on RPe, my intention was to update RPn whenever 
RPe is fetched.
Alternatively, I can maintain a separate update_rpn() function, but in 
either case, it will be invoked during initialization and while 
retrieving RPe frequencies.
Another option could be to simply rename the function to 
xe_guc_pc_get_rpe_rpn_freq() to reflect its dual purpose.
What are your thoughts on this approach?

Thanks,
Anirban
>> +
>> +	return freq;
>>   }
>>   
>>   /**
>> @@ -1021,7 +1030,7 @@ static int pc_set_mert_freq_cap(struct xe_guc_pc *pc)
>>   	/*
>>   	 * Ensure min and max are bound by MERT_FREQ_CAP until driver loads.
>>   	 */
>> -	ret = pc_set_min_freq(pc, min(pc->rpe_freq, pc_max_freq_cap(pc)));
>> +	ret = pc_set_min_freq(pc, min(xe_guc_pc_get_rpe_freq(pc), pc_max_freq_cap(pc)));
>>   	if (!ret)
>>   		ret = pc_set_max_freq(pc, min(pc->rp0_freq, pc_max_freq_cap(pc)));
>>   
>> @@ -1339,7 +1348,7 @@ static void xe_guc_pc_fini_hw(void *arg)
>>   	XE_WARN_ON(xe_guc_pc_stop(pc));
>>   
>>   	/* Bind requested freq to mert_freq_cap before unload */
>> -	pc_set_cur_freq(pc, min(pc_max_freq_cap(pc), pc->rpe_freq));
>> +	pc_set_cur_freq(pc, min(pc_max_freq_cap(pc), xe_guc_pc_get_rpe_freq(pc)));
>>   
>>   	xe_force_wake_put(gt_to_fw(pc_to_gt(pc)), fw_ref);
>>   }
>> diff --git a/drivers/gpu/drm/xe/xe_guc_pc_types.h b/drivers/gpu/drm/xe/xe_guc_pc_types.h
>> index 5e4ea53fbee6..f27c05d81706 100644
>> --- a/drivers/gpu/drm/xe/xe_guc_pc_types.h
>> +++ b/drivers/gpu/drm/xe/xe_guc_pc_types.h
>> @@ -21,8 +21,6 @@ struct xe_guc_pc {
>>   	u32 rp0_freq;
>>   	/** @rpa_freq: HW RPa frequency - The Achievable one */
>>   	u32 rpa_freq;
>> -	/** @rpe_freq: HW RPe frequency - The Efficient one */
>> -	u32 rpe_freq;
>>   	/** @rpn_freq: HW RPN frequency - The Minimum one */
>>   	u32 rpn_freq;
>>   	/** @user_requested_min: Stash the minimum requested freq by user */
>> -- 
>> 2.43.0
>>


^ permalink raw reply	[flat|nested] 12+ messages in thread
* Re: [PATCH v5 1/2] drm/xe/guc: Eliminate RPe caching for SLPC parameter handling
  2025-10-29 18:35     ` Anirban, Sk
@ 2025-10-29 19:58       ` Vivi, Rodrigo
  2025-10-29 20:37         ` Belgaumkar, Vinay
  0 siblings, 1 reply; 12+ messages in thread
From: Vivi, Rodrigo @ 2025-10-29 19:58 UTC (permalink / raw)
  To: Anirban, Sk
  Cc: intel-xe@lists.freedesktop.org, Jadav,  Raag, Belgaumkar, Vinay,
	Koujalagi, Mallesh, Purkait, Soham, Tauro, Riana, Nilawar, Badal,
	Poosa, Karthik, Gupta, Anshuman

On Thu, 2025-10-30 at 00:05 +0530, Anirban, Sk wrote:
> Hi,
> 
> On 29-10-2025 23:34, Rodrigo Vivi wrote:
> > On Wed, Oct 29, 2025 at 04:50:16PM +0530, Sk Anirban wrote:
> > > RPe is runtime-determined by PCODE and caching it caused stale
> > > values,
> > > leading to incorrect GuC SLPC parameter settings.
> > > Drop the cached rpe_freq field and query fresh values from
> > > hardware
> > > on each use to ensure GuC SLPC parameters reflect current RPe.
> > > 
> > > v2: Remove cached RPe frequency field (Rodrigo)
> > > v3: Remove extra variable (Vinay)
> > >      Modify function name (Vinay)
> > > v4: Maintain a separate function for PVC (Rodrigo)
> > > v5: Update RPn while fetching RPe frequency
> > > 
> > > Closes:
> > > https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/5166
> > > Signed-off-by: Sk Anirban <sk.anirban@intel.com>
> > > ---
> > >   drivers/gpu/drm/xe/xe_guc_pc.c       | 75 ++++++++++++++++-----
> > > -------
> > >   drivers/gpu/drm/xe/xe_guc_pc_types.h |  2 -
> > >   2 files changed, 42 insertions(+), 35 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c
> > > b/drivers/gpu/drm/xe/xe_guc_pc.c
> > > index 3c0feb50a1e2..08deaa64aa85 100644
> > > --- a/drivers/gpu/drm/xe/xe_guc_pc.c
> > > +++ b/drivers/gpu/drm/xe/xe_guc_pc.c
> > > @@ -330,7 +330,7 @@ static int pc_set_min_freq(struct xe_guc_pc
> > > *pc, u32 freq)
> > >   	 * Our goal is to have the admin choices respected.
> > >   	 */
> > >   	pc_action_set_param(pc,
> > > SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY,
> > > -			    freq < pc->rpe_freq);
> > > +			    freq < xe_guc_pc_get_rpe_freq(pc));
> > >   
> > >   	return pc_action_set_param(pc,
> > >   				  
> > > SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
> > > @@ -375,7 +375,7 @@ static void mtl_update_rpa_value(struct
> > > xe_guc_pc *pc)
> > >   	pc->rpa_freq = decode_freq(REG_FIELD_GET(MTL_RPA_MASK,
> > > reg));
> > >   }
> > >   
> > > -static void mtl_update_rpe_value(struct xe_guc_pc *pc)
> > > +static u32 mtl_get_rpe_freq(struct xe_guc_pc *pc)
> > >   {
> > >   	struct xe_gt *gt = pc_to_gt(pc);
> > >   	u32 reg;
> > > @@ -385,7 +385,7 @@ static void mtl_update_rpe_value(struct
> > > xe_guc_pc *pc)
> > >   	else
> > >   		reg = xe_mmio_read32(&gt->mmio,
> > > MTL_GT_RPE_FREQUENCY);
> > >   
> > > -	pc->rpe_freq = decode_freq(REG_FIELD_GET(MTL_RPE_MASK,
> > > reg));
> > > +	return decode_freq(REG_FIELD_GET(MTL_RPE_MASK, reg));
> > >   }
> > >   
> > >   static void tgl_update_rpa_value(struct xe_guc_pc *pc)
> > > @@ -408,24 +408,22 @@ static void tgl_update_rpa_value(struct
> > > xe_guc_pc *pc)
> > >   	}
> > >   }
> > >   
> > > -static void tgl_update_rpe_value(struct xe_guc_pc *pc)
> > > +static u32 pvc_get_rpe_freq(struct xe_guc_pc *pc)
> > >   {
> > >   	struct xe_gt *gt = pc_to_gt(pc);
> > > -	struct xe_device *xe = gt_to_xe(gt);
> > >   	u32 reg;
> > >   
> > > -	/*
> > > -	 * For PVC we still need to use fused RP1 as the
> > > approximation for RPe
> > > -	 * For other platforms than PVC we get the resolved RPe
> > > directly from
> > > -	 * PCODE at a different register
> > > -	 */
> > > -	if (xe->info.platform == XE_PVC) {
> > > -		reg = xe_mmio_read32(&gt->mmio,
> > > PVC_RP_STATE_CAP);
> > > -		pc->rpe_freq = REG_FIELD_GET(RP1_MASK, reg) *
> > > GT_FREQUENCY_MULTIPLIER;
> > > -	} else {
> > > -		reg = xe_mmio_read32(&gt->mmio, FREQ_INFO_REC);
> > > -		pc->rpe_freq = REG_FIELD_GET(RPE_MASK, reg) *
> > > GT_FREQUENCY_MULTIPLIER;
> > > -	}
> > > +	reg = xe_mmio_read32(&gt->mmio, PVC_RP_STATE_CAP);
> > > +	return REG_FIELD_GET(RP1_MASK, reg) *
> > > GT_FREQUENCY_MULTIPLIER;
> > > +}
> > > +
> > > +static u32 tgl_get_rpe_freq(struct xe_guc_pc *pc)
> > > +{
> > > +	struct xe_gt *gt = pc_to_gt(pc);
> > > +	u32 reg;
> > > +
> > > +	reg = xe_mmio_read32(&gt->mmio, FREQ_INFO_REC);
> > > +	return REG_FIELD_GET(RPE_MASK, reg) *
> > > GT_FREQUENCY_MULTIPLIER;
> > >   }
> > >   
> > >   static void pc_update_rp_values(struct xe_guc_pc *pc)
> > > @@ -433,20 +431,10 @@ static void pc_update_rp_values(struct
> > > xe_guc_pc *pc)
> > >   	struct xe_gt *gt = pc_to_gt(pc);
> > >   	struct xe_device *xe = gt_to_xe(gt);
> > >   
> > > -	if (GRAPHICS_VERx100(xe) >= 1270) {
> > > +	if (GRAPHICS_VERx100(xe) >= 1270)
> > >   		mtl_update_rpa_value(pc);
> > > -		mtl_update_rpe_value(pc);
> > > -	} else {
> > > +	else
> > >   		tgl_update_rpa_value(pc);
> > > -		tgl_update_rpe_value(pc);
> > > -	}
> > > -
> > > -	/*
> > > -	 * RPe is decided at runtime by PCODE. In the rare case
> > > where that's
> > > -	 * smaller than the fused min, we will trust the PCODE
> > > and use that
> > > -	 * as our minimum one.
> > > -	 */
> > > -	pc->rpn_freq = min(pc->rpn_freq, pc->rpe_freq);
> > >   }
> > >   
> > >   /**
> > > @@ -560,9 +548,30 @@ u32 xe_guc_pc_get_rpa_freq(struct xe_guc_pc
> > > *pc)
> > >    */
> > >   u32 xe_guc_pc_get_rpe_freq(struct xe_guc_pc *pc)
> > >   {
> > > -	pc_update_rp_values(pc);
> > > +	struct xe_gt *gt = pc_to_gt(pc);
> > > +	struct xe_device *xe = gt_to_xe(gt);
> > > +	u32 freq;
> > >   
> > > -	return pc->rpe_freq;
> > > +	/*
> > > +	 * For PVC we still need to use fused RP1 as the
> > > approximation for RPe
> > > +	 * For other platforms than PVC we get the resolved RPe
> > > directly from
> > > +	 * PCODE at a different register
> > > +	 */
> > > +	if (xe->info.platform == XE_PVC)
> > I believe it would be better to convert this to the graphics
> > version here
> > instead of the platform name. But no block since it was already a
> > platform check
> > above.
> sure, I will look into this.
> > > +		freq = pvc_get_rpe_freq(pc);
> > > +	else if (GRAPHICS_VERx100(xe) >= 1270)
> > > +		freq = mtl_get_rpe_freq(pc);
> > > +	else
> > > +		freq = tgl_get_rpe_freq(pc);
> > > +
> > > +	/*
> > > +	 * RPe is decided at runtime by PCODE. In the rare case
> > > where that's
> > > +	 * smaller than the fused min, we will trust the PCODE
> > > and use that
> > > +	 * as our minimum one.
> > > +	 */
> > > +	pc->rpn_freq = min(pc->rpn_freq, freq);
> > setting rpn_freq inside this get_rpe function makes no sense.
> > 
> > I'm sorry I forgot about this when I told you to kill the other
> > function.
> > It should stay there, but be called update_rpn instead...
> Since RPn updates depend on RPe, my intention was to update RPn
> whenever 
> RPe is fetched.
> Alternatively, I can maintain a separate update_rpn() function, but
> in 
> either case, it will be invoked during initialization and while 
> retrieving RPe frequencies.
> Another option could be to simply rename the function to 
> xe_guc_pc_get_rpe_rpn_freq() to reflect its dual purpose.
> What are your thoughts on this approach?

I think you need to get to the drawing board and think on another
proposal. This is becoming to get really messier.

update_rp simply update them all before the actual get.

you don't update another thing inside a get of a specific thing
of interest.

think of what are the cases where the rpn update is really needed.
think if we should have a constant workqueue refreshing it if not
idle/suspended. Think about all the consequences of the updates
and removal that you are proposing. And always making sure that
that that igt freq test is reliably passing.

But something is strange in the current proposal.

> 
> Thanks,
> Anirban
> > > +
> > > +	return freq;
> > >   }
> > >   
> > >   /**
> > > @@ -1021,7 +1030,7 @@ static int pc_set_mert_freq_cap(struct
> > > xe_guc_pc *pc)
> > >   	/*
> > >   	 * Ensure min and max are bound by MERT_FREQ_CAP until
> > > driver loads.
> > >   	 */
> > > -	ret = pc_set_min_freq(pc, min(pc->rpe_freq,
> > > pc_max_freq_cap(pc)));
> > > +	ret = pc_set_min_freq(pc,
> > > min(xe_guc_pc_get_rpe_freq(pc), pc_max_freq_cap(pc)));
> > >   	if (!ret)
> > >   		ret = pc_set_max_freq(pc, min(pc->rp0_freq,
> > > pc_max_freq_cap(pc)));
> > >   
> > > @@ -1339,7 +1348,7 @@ static void xe_guc_pc_fini_hw(void *arg)
> > >   	XE_WARN_ON(xe_guc_pc_stop(pc));
> > >   
> > >   	/* Bind requested freq to mert_freq_cap before unload */
> > > -	pc_set_cur_freq(pc, min(pc_max_freq_cap(pc), pc-
> > > >rpe_freq));
> > > +	pc_set_cur_freq(pc, min(pc_max_freq_cap(pc),
> > > xe_guc_pc_get_rpe_freq(pc)));
> > >   
> > >   	xe_force_wake_put(gt_to_fw(pc_to_gt(pc)), fw_ref);
> > >   }
> > > diff --git a/drivers/gpu/drm/xe/xe_guc_pc_types.h
> > > b/drivers/gpu/drm/xe/xe_guc_pc_types.h
> > > index 5e4ea53fbee6..f27c05d81706 100644
> > > --- a/drivers/gpu/drm/xe/xe_guc_pc_types.h
> > > +++ b/drivers/gpu/drm/xe/xe_guc_pc_types.h
> > > @@ -21,8 +21,6 @@ struct xe_guc_pc {
> > >   	u32 rp0_freq;
> > >   	/** @rpa_freq: HW RPa frequency - The Achievable one */
> > >   	u32 rpa_freq;
> > > -	/** @rpe_freq: HW RPe frequency - The Efficient one */
> > > -	u32 rpe_freq;
> > >   	/** @rpn_freq: HW RPN frequency - The Minimum one */
> > >   	u32 rpn_freq;
> > >   	/** @user_requested_min: Stash the minimum requested
> > > freq by user */
> > > -- 
> > > 2.43.0
> > > 

^ permalink raw reply	[flat|nested] 12+ messages in thread
* Re: [PATCH v5 1/2] drm/xe/guc: Eliminate RPe caching for SLPC parameter handling
  2025-10-29 19:58       ` Vivi, Rodrigo
@ 2025-10-29 20:37         ` Belgaumkar, Vinay
  2025-10-30 15:11           ` Anirban, Sk
  2025-10-30 15:18           ` Anirban, Sk
  0 siblings, 2 replies; 12+ messages in thread
From: Belgaumkar, Vinay @ 2025-10-29 20:37 UTC (permalink / raw)
  To: Vivi, Rodrigo, Anirban, Sk
  Cc: intel-xe@lists.freedesktop.org, Jadav,  Raag, Koujalagi, Mallesh,
	Purkait, Soham, Tauro, Riana, Nilawar, Badal, Poosa, Karthik,
	Gupta, Anshuman


On 10/29/2025 12:58 PM, Vivi, Rodrigo wrote:
> On Thu, 2025-10-30 at 00:05 +0530, Anirban, Sk wrote:
>> Hi,
>>
>> On 29-10-2025 23:34, Rodrigo Vivi wrote:
>>> On Wed, Oct 29, 2025 at 04:50:16PM +0530, Sk Anirban wrote:
>>>> RPe is runtime-determined by PCODE and caching it caused stale
>>>> values,
>>>> leading to incorrect GuC SLPC parameter settings.
>>>> Drop the cached rpe_freq field and query fresh values from
>>>> hardware
>>>> on each use to ensure GuC SLPC parameters reflect current RPe.
>>>>
>>>> v2: Remove cached RPe frequency field (Rodrigo)
>>>> v3: Remove extra variable (Vinay)
>>>>       Modify function name (Vinay)
>>>> v4: Maintain a separate function for PVC (Rodrigo)
>>>> v5: Update RPn while fetching RPe frequency
>>>>
>>>> Closes:
>>>> https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/5166
>>>> Signed-off-by: Sk Anirban <sk.anirban@intel.com>
>>>> ---
>>>>    drivers/gpu/drm/xe/xe_guc_pc.c       | 75 ++++++++++++++++-----
>>>> -------
>>>>    drivers/gpu/drm/xe/xe_guc_pc_types.h |  2 -
>>>>    2 files changed, 42 insertions(+), 35 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c
>>>> b/drivers/gpu/drm/xe/xe_guc_pc.c
>>>> index 3c0feb50a1e2..08deaa64aa85 100644
>>>> --- a/drivers/gpu/drm/xe/xe_guc_pc.c
>>>> +++ b/drivers/gpu/drm/xe/xe_guc_pc.c
>>>> @@ -330,7 +330,7 @@ static int pc_set_min_freq(struct xe_guc_pc
>>>> *pc, u32 freq)
>>>>    	 * Our goal is to have the admin choices respected.
>>>>    	 */
>>>>    	pc_action_set_param(pc,
>>>> SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY,
>>>> -			    freq < pc->rpe_freq);
>>>> +			    freq < xe_guc_pc_get_rpe_freq(pc));
>>>>    
>>>>    	return pc_action_set_param(pc,
>>>>    				
>>>> SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
>>>> @@ -375,7 +375,7 @@ static void mtl_update_rpa_value(struct
>>>> xe_guc_pc *pc)
>>>>    	pc->rpa_freq = decode_freq(REG_FIELD_GET(MTL_RPA_MASK,
>>>> reg));
>>>>    }
>>>>    
>>>> -static void mtl_update_rpe_value(struct xe_guc_pc *pc)
>>>> +static u32 mtl_get_rpe_freq(struct xe_guc_pc *pc)
>>>>    {
>>>>    	struct xe_gt *gt = pc_to_gt(pc);
>>>>    	u32 reg;
>>>> @@ -385,7 +385,7 @@ static void mtl_update_rpe_value(struct
>>>> xe_guc_pc *pc)
>>>>    	else
>>>>    		reg = xe_mmio_read32(&gt->mmio,
>>>> MTL_GT_RPE_FREQUENCY);
>>>>    
>>>> -	pc->rpe_freq = decode_freq(REG_FIELD_GET(MTL_RPE_MASK,
>>>> reg));
>>>> +	return decode_freq(REG_FIELD_GET(MTL_RPE_MASK, reg));
>>>>    }
>>>>    
>>>>    static void tgl_update_rpa_value(struct xe_guc_pc *pc)
>>>> @@ -408,24 +408,22 @@ static void tgl_update_rpa_value(struct
>>>> xe_guc_pc *pc)
>>>>    	}
>>>>    }
>>>>    
>>>> -static void tgl_update_rpe_value(struct xe_guc_pc *pc)
>>>> +static u32 pvc_get_rpe_freq(struct xe_guc_pc *pc)
>>>>    {
>>>>    	struct xe_gt *gt = pc_to_gt(pc);
>>>> -	struct xe_device *xe = gt_to_xe(gt);
>>>>    	u32 reg;
>>>>    
>>>> -	/*
>>>> -	 * For PVC we still need to use fused RP1 as the
>>>> approximation for RPe
>>>> -	 * For other platforms than PVC we get the resolved RPe
>>>> directly from
>>>> -	 * PCODE at a different register
>>>> -	 */
>>>> -	if (xe->info.platform == XE_PVC) {
>>>> -		reg = xe_mmio_read32(&gt->mmio,
>>>> PVC_RP_STATE_CAP);
>>>> -		pc->rpe_freq = REG_FIELD_GET(RP1_MASK, reg) *
>>>> GT_FREQUENCY_MULTIPLIER;
>>>> -	} else {
>>>> -		reg = xe_mmio_read32(&gt->mmio, FREQ_INFO_REC);
>>>> -		pc->rpe_freq = REG_FIELD_GET(RPE_MASK, reg) *
>>>> GT_FREQUENCY_MULTIPLIER;
>>>> -	}
>>>> +	reg = xe_mmio_read32(&gt->mmio, PVC_RP_STATE_CAP);
>>>> +	return REG_FIELD_GET(RP1_MASK, reg) *
>>>> GT_FREQUENCY_MULTIPLIER;
>>>> +}
>>>> +
>>>> +static u32 tgl_get_rpe_freq(struct xe_guc_pc *pc)
>>>> +{
>>>> +	struct xe_gt *gt = pc_to_gt(pc);
>>>> +	u32 reg;
>>>> +
>>>> +	reg = xe_mmio_read32(&gt->mmio, FREQ_INFO_REC);
>>>> +	return REG_FIELD_GET(RPE_MASK, reg) *
>>>> GT_FREQUENCY_MULTIPLIER;
>>>>    }
>>>>    
>>>>    static void pc_update_rp_values(struct xe_guc_pc *pc)
>>>> @@ -433,20 +431,10 @@ static void pc_update_rp_values(struct
>>>> xe_guc_pc *pc)
>>>>    	struct xe_gt *gt = pc_to_gt(pc);
>>>>    	struct xe_device *xe = gt_to_xe(gt);
>>>>    
>>>> -	if (GRAPHICS_VERx100(xe) >= 1270) {
>>>> +	if (GRAPHICS_VERx100(xe) >= 1270)
>>>>    		mtl_update_rpa_value(pc);
>>>> -		mtl_update_rpe_value(pc);
>>>> -	} else {
>>>> +	else
>>>>    		tgl_update_rpa_value(pc);
>>>> -		tgl_update_rpe_value(pc);
>>>> -	}
>>>> -
>>>> -	/*
>>>> -	 * RPe is decided at runtime by PCODE. In the rare case
>>>> where that's
>>>> -	 * smaller than the fused min, we will trust the PCODE
>>>> and use that
>>>> -	 * as our minimum one.
>>>> -	 */
>>>> -	pc->rpn_freq = min(pc->rpn_freq, pc->rpe_freq);
>>>>    }
>>>>    
>>>>    /**
>>>> @@ -560,9 +548,30 @@ u32 xe_guc_pc_get_rpa_freq(struct xe_guc_pc
>>>> *pc)
>>>>     */
>>>>    u32 xe_guc_pc_get_rpe_freq(struct xe_guc_pc *pc)
>>>>    {
>>>> -	pc_update_rp_values(pc);
>>>> +	struct xe_gt *gt = pc_to_gt(pc);
>>>> +	struct xe_device *xe = gt_to_xe(gt);
>>>> +	u32 freq;
>>>>    
>>>> -	return pc->rpe_freq;
>>>> +	/*
>>>> +	 * For PVC we still need to use fused RP1 as the
>>>> approximation for RPe
>>>> +	 * For other platforms than PVC we get the resolved RPe
>>>> directly from
>>>> +	 * PCODE at a different register
>>>> +	 */
>>>> +	if (xe->info.platform == XE_PVC)
>>> I believe it would be better to convert this to the graphics
>>> version here
>>> instead of the platform name. But no block since it was already a
>>> platform check
>>> above.
>> sure, I will look into this.
>>>> +		freq = pvc_get_rpe_freq(pc);
>>>> +	else if (GRAPHICS_VERx100(xe) >= 1270)
>>>> +		freq = mtl_get_rpe_freq(pc);
>>>> +	else
>>>> +		freq = tgl_get_rpe_freq(pc);
>>>> +
>>>> +	/*
>>>> +	 * RPe is decided at runtime by PCODE. In the rare case
>>>> where that's
>>>> +	 * smaller than the fused min, we will trust the PCODE
>>>> and use that
>>>> +	 * as our minimum one.
>>>> +	 */
>>>> +	pc->rpn_freq = min(pc->rpn_freq, freq);
>>> setting rpn_freq inside this get_rpe function makes no sense.
>>>
>>> I'm sorry I forgot about this when I told you to kill the other
>>> function.
>>> It should stay there, but be called update_rpn instead...
>> Since RPn updates depend on RPe, my intention was to update RPn
>> whenever
>> RPe is fetched.
>> Alternatively, I can maintain a separate update_rpn() function, but
>> in
>> either case, it will be invoked during initialization and while
>> retrieving RPe frequencies.
>> Another option could be to simply rename the function to
>> xe_guc_pc_get_rpe_rpn_freq() to reflect its dual purpose.
>> What are your thoughts on this approach?
> I think you need to get to the drawing board and think on another
> proposal. This is becoming to get really messier.
>
> update_rp simply update them all before the actual get.
>
> you don't update another thing inside a get of a specific thing
> of interest.
>
> think of what are the cases where the rpn update is really needed.
> think if we should have a constant workqueue refreshing it if not
> idle/suspended. Think about all the consequences of the updates
> and removal that you are proposing. And always making sure that
> that that igt freq test is reliably passing.
>
> But something is strange in the current proposal.

Agreed. The issue was we needed to get updated RPe. Why do we need to 
update RPn? That is a fused value and never changes. SLPC min freq 
changes with RPe. So we need to ensure we read SLPC min every time (if 
we are not doing that already).

Thanks,

Vinay.

>
>> Thanks,
>> Anirban
>>>> +
>>>> +	return freq;
>>>>    }
>>>>    
>>>>    /**
>>>> @@ -1021,7 +1030,7 @@ static int pc_set_mert_freq_cap(struct
>>>> xe_guc_pc *pc)
>>>>    	/*
>>>>    	 * Ensure min and max are bound by MERT_FREQ_CAP until
>>>> driver loads.
>>>>    	 */
>>>> -	ret = pc_set_min_freq(pc, min(pc->rpe_freq,
>>>> pc_max_freq_cap(pc)));
>>>> +	ret = pc_set_min_freq(pc,
>>>> min(xe_guc_pc_get_rpe_freq(pc), pc_max_freq_cap(pc)));
>>>>    	if (!ret)
>>>>    		ret = pc_set_max_freq(pc, min(pc->rp0_freq,
>>>> pc_max_freq_cap(pc)));
>>>>    
>>>> @@ -1339,7 +1348,7 @@ static void xe_guc_pc_fini_hw(void *arg)
>>>>    	XE_WARN_ON(xe_guc_pc_stop(pc));
>>>>    
>>>>    	/* Bind requested freq to mert_freq_cap before unload */
>>>> -	pc_set_cur_freq(pc, min(pc_max_freq_cap(pc), pc-
>>>>> rpe_freq));
>>>> +	pc_set_cur_freq(pc, min(pc_max_freq_cap(pc),
>>>> xe_guc_pc_get_rpe_freq(pc)));
>>>>    
>>>>    	xe_force_wake_put(gt_to_fw(pc_to_gt(pc)), fw_ref);
>>>>    }
>>>> diff --git a/drivers/gpu/drm/xe/xe_guc_pc_types.h
>>>> b/drivers/gpu/drm/xe/xe_guc_pc_types.h
>>>> index 5e4ea53fbee6..f27c05d81706 100644
>>>> --- a/drivers/gpu/drm/xe/xe_guc_pc_types.h
>>>> +++ b/drivers/gpu/drm/xe/xe_guc_pc_types.h
>>>> @@ -21,8 +21,6 @@ struct xe_guc_pc {
>>>>    	u32 rp0_freq;
>>>>    	/** @rpa_freq: HW RPa frequency - The Achievable one */
>>>>    	u32 rpa_freq;
>>>> -	/** @rpe_freq: HW RPe frequency - The Efficient one */
>>>> -	u32 rpe_freq;
>>>>    	/** @rpn_freq: HW RPN frequency - The Minimum one */
>>>>    	u32 rpn_freq;
>>>>    	/** @user_requested_min: Stash the minimum requested
>>>> freq by user */
>>>> -- 
>>>> 2.43.0
>>>>

^ permalink raw reply	[flat|nested] 12+ messages in thread
* Re: [PATCH v5 1/2] drm/xe/guc: Eliminate RPe caching for SLPC parameter handling
  2025-10-29 20:37         ` Belgaumkar, Vinay
@ 2025-10-30 15:11           ` Anirban, Sk
  2025-10-30 15:18           ` Anirban, Sk
  1 sibling, 0 replies; 12+ messages in thread
From: Anirban, Sk @ 2025-10-30 15:11 UTC (permalink / raw)
  To: Belgaumkar, Vinay, Vivi, Rodrigo
  Cc: intel-xe@lists.freedesktop.org, Jadav,  Raag, Koujalagi, Mallesh,
	Purkait, Soham, Tauro, Riana, Nilawar, Badal, Poosa, Karthik,
	Gupta, Anshuman

Hi,

On 30-10-2025 02:07, Belgaumkar, Vinay wrote:
>
> On 10/29/2025 12:58 PM, Vivi, Rodrigo wrote:
>> On Thu, 2025-10-30 at 00:05 +0530, Anirban, Sk wrote:
>>> Hi,
>>>
>>> On 29-10-2025 23:34, Rodrigo Vivi wrote:
>>>> On Wed, Oct 29, 2025 at 04:50:16PM +0530, Sk Anirban wrote:
>>>>> RPe is runtime-determined by PCODE and caching it caused stale
>>>>> values,
>>>>> leading to incorrect GuC SLPC parameter settings.
>>>>> Drop the cached rpe_freq field and query fresh values from
>>>>> hardware
>>>>> on each use to ensure GuC SLPC parameters reflect current RPe.
>>>>>
>>>>> v2: Remove cached RPe frequency field (Rodrigo)
>>>>> v3: Remove extra variable (Vinay)
>>>>>       Modify function name (Vinay)
>>>>> v4: Maintain a separate function for PVC (Rodrigo)
>>>>> v5: Update RPn while fetching RPe frequency
>>>>>
>>>>> Closes:
>>>>> https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/5166
>>>>> Signed-off-by: Sk Anirban <sk.anirban@intel.com>
>>>>> ---
>>>>>    drivers/gpu/drm/xe/xe_guc_pc.c       | 75 ++++++++++++++++-----
>>>>> -------
>>>>>    drivers/gpu/drm/xe/xe_guc_pc_types.h |  2 -
>>>>>    2 files changed, 42 insertions(+), 35 deletions(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c
>>>>> b/drivers/gpu/drm/xe/xe_guc_pc.c
>>>>> index 3c0feb50a1e2..08deaa64aa85 100644
>>>>> --- a/drivers/gpu/drm/xe/xe_guc_pc.c
>>>>> +++ b/drivers/gpu/drm/xe/xe_guc_pc.c
>>>>> @@ -330,7 +330,7 @@ static int pc_set_min_freq(struct xe_guc_pc
>>>>> *pc, u32 freq)
>>>>>         * Our goal is to have the admin choices respected.
>>>>>         */
>>>>>        pc_action_set_param(pc,
>>>>> SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY,
>>>>> -                freq < pc->rpe_freq);
>>>>> +                freq < xe_guc_pc_get_rpe_freq(pc));
>>>>>           return pc_action_set_param(pc,
>>>>>
>>>>> SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
>>>>> @@ -375,7 +375,7 @@ static void mtl_update_rpa_value(struct
>>>>> xe_guc_pc *pc)
>>>>>        pc->rpa_freq = decode_freq(REG_FIELD_GET(MTL_RPA_MASK,
>>>>> reg));
>>>>>    }
>>>>>    -static void mtl_update_rpe_value(struct xe_guc_pc *pc)
>>>>> +static u32 mtl_get_rpe_freq(struct xe_guc_pc *pc)
>>>>>    {
>>>>>        struct xe_gt *gt = pc_to_gt(pc);
>>>>>        u32 reg;
>>>>> @@ -385,7 +385,7 @@ static void mtl_update_rpe_value(struct
>>>>> xe_guc_pc *pc)
>>>>>        else
>>>>>            reg = xe_mmio_read32(&gt->mmio,
>>>>> MTL_GT_RPE_FREQUENCY);
>>>>>    -    pc->rpe_freq = decode_freq(REG_FIELD_GET(MTL_RPE_MASK,
>>>>> reg));
>>>>> +    return decode_freq(REG_FIELD_GET(MTL_RPE_MASK, reg));
>>>>>    }
>>>>>       static void tgl_update_rpa_value(struct xe_guc_pc *pc)
>>>>> @@ -408,24 +408,22 @@ static void tgl_update_rpa_value(struct
>>>>> xe_guc_pc *pc)
>>>>>        }
>>>>>    }
>>>>>    -static void tgl_update_rpe_value(struct xe_guc_pc *pc)
>>>>> +static u32 pvc_get_rpe_freq(struct xe_guc_pc *pc)
>>>>>    {
>>>>>        struct xe_gt *gt = pc_to_gt(pc);
>>>>> -    struct xe_device *xe = gt_to_xe(gt);
>>>>>        u32 reg;
>>>>>    -    /*
>>>>> -     * For PVC we still need to use fused RP1 as the
>>>>> approximation for RPe
>>>>> -     * For other platforms than PVC we get the resolved RPe
>>>>> directly from
>>>>> -     * PCODE at a different register
>>>>> -     */
>>>>> -    if (xe->info.platform == XE_PVC) {
>>>>> -        reg = xe_mmio_read32(&gt->mmio,
>>>>> PVC_RP_STATE_CAP);
>>>>> -        pc->rpe_freq = REG_FIELD_GET(RP1_MASK, reg) *
>>>>> GT_FREQUENCY_MULTIPLIER;
>>>>> -    } else {
>>>>> -        reg = xe_mmio_read32(&gt->mmio, FREQ_INFO_REC);
>>>>> -        pc->rpe_freq = REG_FIELD_GET(RPE_MASK, reg) *
>>>>> GT_FREQUENCY_MULTIPLIER;
>>>>> -    }
>>>>> +    reg = xe_mmio_read32(&gt->mmio, PVC_RP_STATE_CAP);
>>>>> +    return REG_FIELD_GET(RP1_MASK, reg) *
>>>>> GT_FREQUENCY_MULTIPLIER;
>>>>> +}
>>>>> +
>>>>> +static u32 tgl_get_rpe_freq(struct xe_guc_pc *pc)
>>>>> +{
>>>>> +    struct xe_gt *gt = pc_to_gt(pc);
>>>>> +    u32 reg;
>>>>> +
>>>>> +    reg = xe_mmio_read32(&gt->mmio, FREQ_INFO_REC);
>>>>> +    return REG_FIELD_GET(RPE_MASK, reg) *
>>>>> GT_FREQUENCY_MULTIPLIER;
>>>>>    }
>>>>>       static void pc_update_rp_values(struct xe_guc_pc *pc)
>>>>> @@ -433,20 +431,10 @@ static void pc_update_rp_values(struct
>>>>> xe_guc_pc *pc)
>>>>>        struct xe_gt *gt = pc_to_gt(pc);
>>>>>        struct xe_device *xe = gt_to_xe(gt);
>>>>>    -    if (GRAPHICS_VERx100(xe) >= 1270) {
>>>>> +    if (GRAPHICS_VERx100(xe) >= 1270)
>>>>>            mtl_update_rpa_value(pc);
>>>>> -        mtl_update_rpe_value(pc);
>>>>> -    } else {
>>>>> +    else
>>>>>            tgl_update_rpa_value(pc);
>>>>> -        tgl_update_rpe_value(pc);
>>>>> -    }
>>>>> -
>>>>> -    /*
>>>>> -     * RPe is decided at runtime by PCODE. In the rare case
>>>>> where that's
>>>>> -     * smaller than the fused min, we will trust the PCODE
>>>>> and use that
>>>>> -     * as our minimum one.
>>>>> -     */
>>>>> -    pc->rpn_freq = min(pc->rpn_freq, pc->rpe_freq);
>>>>>    }
>>>>>       /**
>>>>> @@ -560,9 +548,30 @@ u32 xe_guc_pc_get_rpa_freq(struct xe_guc_pc
>>>>> *pc)
>>>>>     */
>>>>>    u32 xe_guc_pc_get_rpe_freq(struct xe_guc_pc *pc)
>>>>>    {
>>>>> -    pc_update_rp_values(pc);
>>>>> +    struct xe_gt *gt = pc_to_gt(pc);
>>>>> +    struct xe_device *xe = gt_to_xe(gt);
>>>>> +    u32 freq;
>>>>>    -    return pc->rpe_freq;
>>>>> +    /*
>>>>> +     * For PVC we still need to use fused RP1 as the
>>>>> approximation for RPe
>>>>> +     * For other platforms than PVC we get the resolved RPe
>>>>> directly from
>>>>> +     * PCODE at a different register
>>>>> +     */
>>>>> +    if (xe->info.platform == XE_PVC)
>>>> I believe it would be better to convert this to the graphics
>>>> version here
>>>> instead of the platform name. But no block since it was already a
>>>> platform check
>>>> above.
>>> sure, I will look into this.
>>>>> +        freq = pvc_get_rpe_freq(pc);
>>>>> +    else if (GRAPHICS_VERx100(xe) >= 1270)
>>>>> +        freq = mtl_get_rpe_freq(pc);
>>>>> +    else
>>>>> +        freq = tgl_get_rpe_freq(pc);
>>>>> +
>>>>> +    /*
>>>>> +     * RPe is decided at runtime by PCODE. In the rare case
>>>>> where that's
>>>>> +     * smaller than the fused min, we will trust the PCODE
>>>>> and use that
>>>>> +     * as our minimum one.
>>>>> +     */
>>>>> +    pc->rpn_freq = min(pc->rpn_freq, freq);
>>>> setting rpn_freq inside this get_rpe function makes no sense.
>>>>
>>>> I'm sorry I forgot about this when I told you to kill the other
>>>> function.
>>>> It should stay there, but be called update_rpn instead...
>>> Since RPn updates depend on RPe, my intention was to update RPn
>>> whenever
>>> RPe is fetched.
>>> Alternatively, I can maintain a separate update_rpn() function, but
>>> in
>>> either case, it will be invoked during initialization and while
>>> retrieving RPe frequencies.
>>> Another option could be to simply rename the function to
>>> xe_guc_pc_get_rpe_rpn_freq() to reflect its dual purpose.
>>> What are your thoughts on this approach?
>> I think you need to get to the drawing board and think on another
>> proposal. This is becoming to get really messier.
>>
>> update_rp simply update them all before the actual get.
>>
>> you don't update another thing inside a get of a specific thing
>> of interest.
>>
>> think of what are the cases where the rpn update is really needed.
>> think if we should have a constant workqueue refreshing it if not
>> idle/suspended. Think about all the consequences of the updates
>> and removal that you are proposing. And always making sure that
>> that that igt freq test is reliably passing.
>>
>> But something is strange in the current proposal.
>
> Agreed. The issue was we needed to get updated RPe. Why do we need to 
> update RPn? That is a fused value and never changes. SLPC min freq 
> changes with RPe. So we need to ensure we read SLPC min every time (if 
> we are not doing that already).
>
> Thanks,
>
> Vinay.
In that case I guess it's better to remove the RPn update from the 
current implementation. Also we are not caching the min_freq & guc will 
update both so everything else should be fine. I will send a revision 
with these fixes.
>
>>
>>> Thanks,
>>> Anirban
>>>>> +
>>>>> +    return freq;
>>>>>    }
>>>>>       /**
>>>>> @@ -1021,7 +1030,7 @@ static int pc_set_mert_freq_cap(struct
>>>>> xe_guc_pc *pc)
>>>>>        /*
>>>>>         * Ensure min and max are bound by MERT_FREQ_CAP until
>>>>> driver loads.
>>>>>         */
>>>>> -    ret = pc_set_min_freq(pc, min(pc->rpe_freq,
>>>>> pc_max_freq_cap(pc)));
>>>>> +    ret = pc_set_min_freq(pc,
>>>>> min(xe_guc_pc_get_rpe_freq(pc), pc_max_freq_cap(pc)));
>>>>>        if (!ret)
>>>>>            ret = pc_set_max_freq(pc, min(pc->rp0_freq,
>>>>> pc_max_freq_cap(pc)));
>>>>>    @@ -1339,7 +1348,7 @@ static void xe_guc_pc_fini_hw(void *arg)
>>>>>        XE_WARN_ON(xe_guc_pc_stop(pc));
>>>>>           /* Bind requested freq to mert_freq_cap before unload */
>>>>> -    pc_set_cur_freq(pc, min(pc_max_freq_cap(pc), pc-
>>>>>> rpe_freq));
>>>>> +    pc_set_cur_freq(pc, min(pc_max_freq_cap(pc),
>>>>> xe_guc_pc_get_rpe_freq(pc)));
>>>>>           xe_force_wake_put(gt_to_fw(pc_to_gt(pc)), fw_ref);
>>>>>    }
>>>>> diff --git a/drivers/gpu/drm/xe/xe_guc_pc_types.h
>>>>> b/drivers/gpu/drm/xe/xe_guc_pc_types.h
>>>>> index 5e4ea53fbee6..f27c05d81706 100644
>>>>> --- a/drivers/gpu/drm/xe/xe_guc_pc_types.h
>>>>> +++ b/drivers/gpu/drm/xe/xe_guc_pc_types.h
>>>>> @@ -21,8 +21,6 @@ struct xe_guc_pc {
>>>>>        u32 rp0_freq;
>>>>>        /** @rpa_freq: HW RPa frequency - The Achievable one */
>>>>>        u32 rpa_freq;
>>>>> -    /** @rpe_freq: HW RPe frequency - The Efficient one */
>>>>> -    u32 rpe_freq;
>>>>>        /** @rpn_freq: HW RPN frequency - The Minimum one */
>>>>>        u32 rpn_freq;
>>>>>        /** @user_requested_min: Stash the minimum requested
>>>>> freq by user */
>>>>> -- 
>>>>> 2.43.0
>>>>>


^ permalink raw reply	[flat|nested] 12+ messages in thread
* Re: [PATCH v5 1/2] drm/xe/guc: Eliminate RPe caching for SLPC parameter handling
  2025-10-29 20:37         ` Belgaumkar, Vinay
  2025-10-30 15:11           ` Anirban, Sk
@ 2025-10-30 15:18           ` Anirban, Sk
  1 sibling, 0 replies; 12+ messages in thread
From: Anirban, Sk @ 2025-10-30 15:18 UTC (permalink / raw)
  To: Belgaumkar, Vinay, Vivi, Rodrigo
  Cc: intel-xe@lists.freedesktop.org, Jadav,  Raag, Koujalagi, Mallesh,
	Purkait, Soham, Tauro, Riana, Nilawar, Badal, Poosa, Karthik,
	Gupta, Anshuman

Hi,

On 30-10-2025 02:07, Belgaumkar, Vinay wrote:
>
> On 10/29/2025 12:58 PM, Vivi, Rodrigo wrote:
>> On Thu, 2025-10-30 at 00:05 +0530, Anirban, Sk wrote:
>>> Hi,
>>>
>>> On 29-10-2025 23:34, Rodrigo Vivi wrote:
>>>> On Wed, Oct 29, 2025 at 04:50:16PM +0530, Sk Anirban wrote:
>>>>> RPe is runtime-determined by PCODE and caching it caused stale
>>>>> values,
>>>>> leading to incorrect GuC SLPC parameter settings.
>>>>> Drop the cached rpe_freq field and query fresh values from
>>>>> hardware
>>>>> on each use to ensure GuC SLPC parameters reflect current RPe.
>>>>>
>>>>> v2: Remove cached RPe frequency field (Rodrigo)
>>>>> v3: Remove extra variable (Vinay)
>>>>>       Modify function name (Vinay)
>>>>> v4: Maintain a separate function for PVC (Rodrigo)
>>>>> v5: Update RPn while fetching RPe frequency
>>>>>
>>>>> Closes:
>>>>> https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/5166
>>>>> Signed-off-by: Sk Anirban <sk.anirban@intel.com>
>>>>> ---
>>>>>    drivers/gpu/drm/xe/xe_guc_pc.c       | 75 ++++++++++++++++-----
>>>>> -------
>>>>>    drivers/gpu/drm/xe/xe_guc_pc_types.h |  2 -
>>>>>    2 files changed, 42 insertions(+), 35 deletions(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c
>>>>> b/drivers/gpu/drm/xe/xe_guc_pc.c
>>>>> index 3c0feb50a1e2..08deaa64aa85 100644
>>>>> --- a/drivers/gpu/drm/xe/xe_guc_pc.c
>>>>> +++ b/drivers/gpu/drm/xe/xe_guc_pc.c
>>>>> @@ -330,7 +330,7 @@ static int pc_set_min_freq(struct xe_guc_pc
>>>>> *pc, u32 freq)
>>>>>         * Our goal is to have the admin choices respected.
>>>>>         */
>>>>>        pc_action_set_param(pc,
>>>>> SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY,
>>>>> -                freq < pc->rpe_freq);
>>>>> +                freq < xe_guc_pc_get_rpe_freq(pc));
>>>>>           return pc_action_set_param(pc,
>>>>>
>>>>> SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
>>>>> @@ -375,7 +375,7 @@ static void mtl_update_rpa_value(struct
>>>>> xe_guc_pc *pc)
>>>>>        pc->rpa_freq = decode_freq(REG_FIELD_GET(MTL_RPA_MASK,
>>>>> reg));
>>>>>    }
>>>>>    -static void mtl_update_rpe_value(struct xe_guc_pc *pc)
>>>>> +static u32 mtl_get_rpe_freq(struct xe_guc_pc *pc)
>>>>>    {
>>>>>        struct xe_gt *gt = pc_to_gt(pc);
>>>>>        u32 reg;
>>>>> @@ -385,7 +385,7 @@ static void mtl_update_rpe_value(struct
>>>>> xe_guc_pc *pc)
>>>>>        else
>>>>>            reg = xe_mmio_read32(&gt->mmio,
>>>>> MTL_GT_RPE_FREQUENCY);
>>>>>    -    pc->rpe_freq = decode_freq(REG_FIELD_GET(MTL_RPE_MASK,
>>>>> reg));
>>>>> +    return decode_freq(REG_FIELD_GET(MTL_RPE_MASK, reg));
>>>>>    }
>>>>>       static void tgl_update_rpa_value(struct xe_guc_pc *pc)
>>>>> @@ -408,24 +408,22 @@ static void tgl_update_rpa_value(struct
>>>>> xe_guc_pc *pc)
>>>>>        }
>>>>>    }
>>>>>    -static void tgl_update_rpe_value(struct xe_guc_pc *pc)
>>>>> +static u32 pvc_get_rpe_freq(struct xe_guc_pc *pc)
>>>>>    {
>>>>>        struct xe_gt *gt = pc_to_gt(pc);
>>>>> -    struct xe_device *xe = gt_to_xe(gt);
>>>>>        u32 reg;
>>>>>    -    /*
>>>>> -     * For PVC we still need to use fused RP1 as the
>>>>> approximation for RPe
>>>>> -     * For other platforms than PVC we get the resolved RPe
>>>>> directly from
>>>>> -     * PCODE at a different register
>>>>> -     */
>>>>> -    if (xe->info.platform == XE_PVC) {
>>>>> -        reg = xe_mmio_read32(&gt->mmio,
>>>>> PVC_RP_STATE_CAP);
>>>>> -        pc->rpe_freq = REG_FIELD_GET(RP1_MASK, reg) *
>>>>> GT_FREQUENCY_MULTIPLIER;
>>>>> -    } else {
>>>>> -        reg = xe_mmio_read32(&gt->mmio, FREQ_INFO_REC);
>>>>> -        pc->rpe_freq = REG_FIELD_GET(RPE_MASK, reg) *
>>>>> GT_FREQUENCY_MULTIPLIER;
>>>>> -    }
>>>>> +    reg = xe_mmio_read32(&gt->mmio, PVC_RP_STATE_CAP);
>>>>> +    return REG_FIELD_GET(RP1_MASK, reg) *
>>>>> GT_FREQUENCY_MULTIPLIER;
>>>>> +}
>>>>> +
>>>>> +static u32 tgl_get_rpe_freq(struct xe_guc_pc *pc)
>>>>> +{
>>>>> +    struct xe_gt *gt = pc_to_gt(pc);
>>>>> +    u32 reg;
>>>>> +
>>>>> +    reg = xe_mmio_read32(&gt->mmio, FREQ_INFO_REC);
>>>>> +    return REG_FIELD_GET(RPE_MASK, reg) *
>>>>> GT_FREQUENCY_MULTIPLIER;
>>>>>    }
>>>>>       static void pc_update_rp_values(struct xe_guc_pc *pc)
>>>>> @@ -433,20 +431,10 @@ static void pc_update_rp_values(struct
>>>>> xe_guc_pc *pc)
>>>>>        struct xe_gt *gt = pc_to_gt(pc);
>>>>>        struct xe_device *xe = gt_to_xe(gt);
>>>>>    -    if (GRAPHICS_VERx100(xe) >= 1270) {
>>>>> +    if (GRAPHICS_VERx100(xe) >= 1270)
>>>>>            mtl_update_rpa_value(pc);
>>>>> -        mtl_update_rpe_value(pc);
>>>>> -    } else {
>>>>> +    else
>>>>>            tgl_update_rpa_value(pc);
>>>>> -        tgl_update_rpe_value(pc);
>>>>> -    }
>>>>> -
>>>>> -    /*
>>>>> -     * RPe is decided at runtime by PCODE. In the rare case
>>>>> where that's
>>>>> -     * smaller than the fused min, we will trust the PCODE
>>>>> and use that
>>>>> -     * as our minimum one.
>>>>> -     */
>>>>> -    pc->rpn_freq = min(pc->rpn_freq, pc->rpe_freq);
>>>>>    }
>>>>>       /**
>>>>> @@ -560,9 +548,30 @@ u32 xe_guc_pc_get_rpa_freq(struct xe_guc_pc
>>>>> *pc)
>>>>>     */
>>>>>    u32 xe_guc_pc_get_rpe_freq(struct xe_guc_pc *pc)
>>>>>    {
>>>>> -    pc_update_rp_values(pc);
>>>>> +    struct xe_gt *gt = pc_to_gt(pc);
>>>>> +    struct xe_device *xe = gt_to_xe(gt);
>>>>> +    u32 freq;
>>>>>    -    return pc->rpe_freq;
>>>>> +    /*
>>>>> +     * For PVC we still need to use fused RP1 as the
>>>>> approximation for RPe
>>>>> +     * For other platforms than PVC we get the resolved RPe
>>>>> directly from
>>>>> +     * PCODE at a different register
>>>>> +     */
>>>>> +    if (xe->info.platform == XE_PVC)
>>>> I believe it would be better to convert this to the graphics
>>>> version here
>>>> instead of the platform name. But no block since it was already a
>>>> platform check
>>>> above.
>>> sure, I will look into this.
>>>>> +        freq = pvc_get_rpe_freq(pc);
>>>>> +    else if (GRAPHICS_VERx100(xe) >= 1270)
>>>>> +        freq = mtl_get_rpe_freq(pc);
>>>>> +    else
>>>>> +        freq = tgl_get_rpe_freq(pc);
>>>>> +
>>>>> +    /*
>>>>> +     * RPe is decided at runtime by PCODE. In the rare case
>>>>> where that's
>>>>> +     * smaller than the fused min, we will trust the PCODE
>>>>> and use that
>>>>> +     * as our minimum one.
>>>>> +     */
>>>>> +    pc->rpn_freq = min(pc->rpn_freq, freq);
>>>> setting rpn_freq inside this get_rpe function makes no sense.
>>>>
>>>> I'm sorry I forgot about this when I told you to kill the other
>>>> function.
>>>> It should stay there, but be called update_rpn instead...
>>> Since RPn updates depend on RPe, my intention was to update RPn
>>> whenever
>>> RPe is fetched.
>>> Alternatively, I can maintain a separate update_rpn() function, but
>>> in
>>> either case, it will be invoked during initialization and while
>>> retrieving RPe frequencies.
>>> Another option could be to simply rename the function to
>>> xe_guc_pc_get_rpe_rpn_freq() to reflect its dual purpose.
>>> What are your thoughts on this approach?
>> I think you need to get to the drawing board and think on another
>> proposal. This is becoming to get really messier.
>>
>> update_rp simply update them all before the actual get.
>>
>> you don't update another thing inside a get of a specific thing
>> of interest.
>>
>> think of what are the cases where the rpn update is really needed.
>> think if we should have a constant workqueue refreshing it if not
>> idle/suspended. Think about all the consequences of the updates
>> and removal that you are proposing. And always making sure that
>> that that igt freq test is reliably passing.
>>
>> But something is strange in the current proposal.
>
> Agreed. The issue was we needed to get updated RPe. Why do we need to 
> update RPn? That is a fused value and never changes. SLPC min freq 
> changes with RPe. So we need to ensure we read SLPC min every time (if 
> we are not doing that already).
>
> Thanks,
>
> Vinay.
>
In that case the current implementation of updating RPn wrt Rpe is not 
required anymore, I will remove that. So we will update RPe only & while 
reading
>>
>>> Thanks,
>>> Anirban
>>>>> +
>>>>> +    return freq;
>>>>>    }
>>>>>       /**
>>>>> @@ -1021,7 +1030,7 @@ static int pc_set_mert_freq_cap(struct
>>>>> xe_guc_pc *pc)
>>>>>        /*
>>>>>         * Ensure min and max are bound by MERT_FREQ_CAP until
>>>>> driver loads.
>>>>>         */
>>>>> -    ret = pc_set_min_freq(pc, min(pc->rpe_freq,
>>>>> pc_max_freq_cap(pc)));
>>>>> +    ret = pc_set_min_freq(pc,
>>>>> min(xe_guc_pc_get_rpe_freq(pc), pc_max_freq_cap(pc)));
>>>>>        if (!ret)
>>>>>            ret = pc_set_max_freq(pc, min(pc->rp0_freq,
>>>>> pc_max_freq_cap(pc)));
>>>>>    @@ -1339,7 +1348,7 @@ static void xe_guc_pc_fini_hw(void *arg)
>>>>>        XE_WARN_ON(xe_guc_pc_stop(pc));
>>>>>           /* Bind requested freq to mert_freq_cap before unload */
>>>>> -    pc_set_cur_freq(pc, min(pc_max_freq_cap(pc), pc-
>>>>>> rpe_freq));
>>>>> +    pc_set_cur_freq(pc, min(pc_max_freq_cap(pc),
>>>>> xe_guc_pc_get_rpe_freq(pc)));
>>>>>           xe_force_wake_put(gt_to_fw(pc_to_gt(pc)), fw_ref);
>>>>>    }
>>>>> diff --git a/drivers/gpu/drm/xe/xe_guc_pc_types.h
>>>>> b/drivers/gpu/drm/xe/xe_guc_pc_types.h
>>>>> index 5e4ea53fbee6..f27c05d81706 100644
>>>>> --- a/drivers/gpu/drm/xe/xe_guc_pc_types.h
>>>>> +++ b/drivers/gpu/drm/xe/xe_guc_pc_types.h
>>>>> @@ -21,8 +21,6 @@ struct xe_guc_pc {
>>>>>        u32 rp0_freq;
>>>>>        /** @rpa_freq: HW RPa frequency - The Achievable one */
>>>>>        u32 rpa_freq;
>>>>> -    /** @rpe_freq: HW RPe frequency - The Efficient one */
>>>>> -    u32 rpe_freq;
>>>>>        /** @rpn_freq: HW RPN frequency - The Minimum one */
>>>>>        u32 rpn_freq;
>>>>>        /** @user_requested_min: Stash the minimum requested
>>>>> freq by user */
>>>>> -- 
>>>>> 2.43.0
>>>>>


^ permalink raw reply	[flat|nested] 12+ messages in thread
* [PATCH v5 1/2] drm/xe/guc: Eliminate RPe caching for SLPC parameter handling
  2025-11-04 10:42 [PATCH v5 0/2] " Sk Anirban
@ 2025-11-04 10:42 ` Sk Anirban
  0 siblings, 0 replies; 12+ messages in thread
From: Sk Anirban @ 2025-11-04 10:42 UTC (permalink / raw)
  To: intel-xe
  Cc: anshuman.gupta, badal.nilawar, riana.tauro, karthik.poosa,
	raag.jadav, soham.purkait, mallesh.koujalagi, vinay.belgaumkar,
	rodrigo.vivi, Sk Anirban

RPe is runtime-determined by PCODE and caching it caused stale values,
leading to incorrect GuC SLPC parameter settings.
Drop the cached rpe_freq field and query fresh values from hardware
on each use to ensure GuC SLPC parameters reflect current RPe.

v2: Remove cached RPe frequency field (Rodrigo)
v3: Remove extra variable (Vinay)
    Modify function name (Vinay)
v4: Maintain a separate function for PVC (Rodrigo)
v5: Avoid RPn update while fetching RPe frequency (Rodrigo)

Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/5166
Signed-off-by: Sk Anirban <sk.anirban@intel.com>
---
 drivers/gpu/drm/xe/xe_guc_pc.c       | 68 ++++++++++++++--------------
 drivers/gpu/drm/xe/xe_guc_pc_types.h |  2 -
 2 files changed, 35 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
index 3c0feb50a1e2..a9c29f123b37 100644
--- a/drivers/gpu/drm/xe/xe_guc_pc.c
+++ b/drivers/gpu/drm/xe/xe_guc_pc.c
@@ -330,7 +330,7 @@ static int pc_set_min_freq(struct xe_guc_pc *pc, u32 freq)
 	 * Our goal is to have the admin choices respected.
 	 */
 	pc_action_set_param(pc, SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY,
-			    freq < pc->rpe_freq);
+			    freq < xe_guc_pc_get_rpe_freq(pc));
 
 	return pc_action_set_param(pc,
 				   SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
@@ -375,7 +375,7 @@ static void mtl_update_rpa_value(struct xe_guc_pc *pc)
 	pc->rpa_freq = decode_freq(REG_FIELD_GET(MTL_RPA_MASK, reg));
 }
 
-static void mtl_update_rpe_value(struct xe_guc_pc *pc)
+static u32 mtl_get_rpe_freq(struct xe_guc_pc *pc)
 {
 	struct xe_gt *gt = pc_to_gt(pc);
 	u32 reg;
@@ -385,7 +385,7 @@ static void mtl_update_rpe_value(struct xe_guc_pc *pc)
 	else
 		reg = xe_mmio_read32(&gt->mmio, MTL_GT_RPE_FREQUENCY);
 
-	pc->rpe_freq = decode_freq(REG_FIELD_GET(MTL_RPE_MASK, reg));
+	return decode_freq(REG_FIELD_GET(MTL_RPE_MASK, reg));
 }
 
 static void tgl_update_rpa_value(struct xe_guc_pc *pc)
@@ -408,24 +408,22 @@ static void tgl_update_rpa_value(struct xe_guc_pc *pc)
 	}
 }
 
-static void tgl_update_rpe_value(struct xe_guc_pc *pc)
+static u32 pvc_get_rpe_freq(struct xe_guc_pc *pc)
 {
 	struct xe_gt *gt = pc_to_gt(pc);
-	struct xe_device *xe = gt_to_xe(gt);
 	u32 reg;
 
-	/*
-	 * For PVC we still need to use fused RP1 as the approximation for RPe
-	 * For other platforms than PVC we get the resolved RPe directly from
-	 * PCODE at a different register
-	 */
-	if (xe->info.platform == XE_PVC) {
-		reg = xe_mmio_read32(&gt->mmio, PVC_RP_STATE_CAP);
-		pc->rpe_freq = REG_FIELD_GET(RP1_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
-	} else {
-		reg = xe_mmio_read32(&gt->mmio, FREQ_INFO_REC);
-		pc->rpe_freq = REG_FIELD_GET(RPE_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
-	}
+	reg = xe_mmio_read32(&gt->mmio, PVC_RP_STATE_CAP);
+	return REG_FIELD_GET(RP1_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
+}
+
+static u32 tgl_get_rpe_freq(struct xe_guc_pc *pc)
+{
+	struct xe_gt *gt = pc_to_gt(pc);
+	u32 reg;
+
+	reg = xe_mmio_read32(&gt->mmio, FREQ_INFO_REC);
+	return REG_FIELD_GET(RPE_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
 }
 
 static void pc_update_rp_values(struct xe_guc_pc *pc)
@@ -433,20 +431,10 @@ static void pc_update_rp_values(struct xe_guc_pc *pc)
 	struct xe_gt *gt = pc_to_gt(pc);
 	struct xe_device *xe = gt_to_xe(gt);
 
-	if (GRAPHICS_VERx100(xe) >= 1270) {
+	if (GRAPHICS_VERx100(xe) >= 1270)
 		mtl_update_rpa_value(pc);
-		mtl_update_rpe_value(pc);
-	} else {
+	else
 		tgl_update_rpa_value(pc);
-		tgl_update_rpe_value(pc);
-	}
-
-	/*
-	 * RPe is decided at runtime by PCODE. In the rare case where that's
-	 * smaller than the fused min, we will trust the PCODE and use that
-	 * as our minimum one.
-	 */
-	pc->rpn_freq = min(pc->rpn_freq, pc->rpe_freq);
 }
 
 /**
@@ -560,9 +548,23 @@ u32 xe_guc_pc_get_rpa_freq(struct xe_guc_pc *pc)
  */
 u32 xe_guc_pc_get_rpe_freq(struct xe_guc_pc *pc)
 {
-	pc_update_rp_values(pc);
+	struct xe_gt *gt = pc_to_gt(pc);
+	struct xe_device *xe = gt_to_xe(gt);
+	u32 freq;
 
-	return pc->rpe_freq;
+	/*
+	 * For PVC we still need to use fused RP1 as the approximation for RPe
+	 * For other platforms than PVC we get the resolved RPe directly from
+	 * PCODE at a different register
+	 */
+	if (GRAPHICS_VERx100(xe) >= 1260)
+		freq = pvc_get_rpe_freq(pc);
+	else if (GRAPHICS_VERx100(xe) >= 1270)
+		freq = mtl_get_rpe_freq(pc);
+	else
+		freq = tgl_get_rpe_freq(pc);
+
+	return freq;
 }
 
 /**
@@ -1021,7 +1023,7 @@ static int pc_set_mert_freq_cap(struct xe_guc_pc *pc)
 	/*
 	 * Ensure min and max are bound by MERT_FREQ_CAP until driver loads.
 	 */
-	ret = pc_set_min_freq(pc, min(pc->rpe_freq, pc_max_freq_cap(pc)));
+	ret = pc_set_min_freq(pc, min(xe_guc_pc_get_rpe_freq(pc), pc_max_freq_cap(pc)));
 	if (!ret)
 		ret = pc_set_max_freq(pc, min(pc->rp0_freq, pc_max_freq_cap(pc)));
 
@@ -1339,7 +1341,7 @@ static void xe_guc_pc_fini_hw(void *arg)
 	XE_WARN_ON(xe_guc_pc_stop(pc));
 
 	/* Bind requested freq to mert_freq_cap before unload */
-	pc_set_cur_freq(pc, min(pc_max_freq_cap(pc), pc->rpe_freq));
+	pc_set_cur_freq(pc, min(pc_max_freq_cap(pc), xe_guc_pc_get_rpe_freq(pc)));
 
 	xe_force_wake_put(gt_to_fw(pc_to_gt(pc)), fw_ref);
 }
diff --git a/drivers/gpu/drm/xe/xe_guc_pc_types.h b/drivers/gpu/drm/xe/xe_guc_pc_types.h
index 5e4ea53fbee6..f27c05d81706 100644
--- a/drivers/gpu/drm/xe/xe_guc_pc_types.h
+++ b/drivers/gpu/drm/xe/xe_guc_pc_types.h
@@ -21,8 +21,6 @@ struct xe_guc_pc {
 	u32 rp0_freq;
 	/** @rpa_freq: HW RPa frequency - The Achievable one */
 	u32 rpa_freq;
-	/** @rpe_freq: HW RPe frequency - The Efficient one */
-	u32 rpe_freq;
 	/** @rpn_freq: HW RPN frequency - The Minimum one */
 	u32 rpn_freq;
 	/** @user_requested_min: Stash the minimum requested freq by user */
-- 
2.43.0


^ permalink raw reply related	[flat|nested] 12+ messages in thread
end of thread, other threads:[~2025-11-04 10:47 UTC | newest]

Thread overview: 12+ messages (download: mbox.gz follow: Atom feed
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2025-10-29 11:20 [PATCH v5 0/2] drm/xe/guc: Remove cached frequency values for GuC SLPC Sk Anirban
2025-10-29 11:20 ` [PATCH v5 1/2] drm/xe/guc: Eliminate RPe caching for SLPC parameter handling Sk Anirban
2025-10-29 18:04   ` Rodrigo Vivi
2025-10-29 18:35     ` Anirban, Sk
2025-10-29 19:58       ` Vivi, Rodrigo
2025-10-29 20:37         ` Belgaumkar, Vinay
2025-10-30 15:11           ` Anirban, Sk
2025-10-30 15:18           ` Anirban, Sk
2025-10-29 11:20 ` [PATCH v5 2/2] drm/xe/guc: Eliminate RPa frequency caching Sk Anirban
2025-10-29 15:40 ` ✓ CI.KUnit: success for drm/xe/guc: Remove cached frequency values for GuC SLPC Patchwork
2025-10-29 16:28 ` ✓ Xe.CI.BAT: " Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2025-11-04 10:42 [PATCH v5 0/2] " Sk Anirban
2025-11-04 10:42 ` [PATCH v5 1/2] drm/xe/guc: Eliminate RPe caching for SLPC parameter handling Sk Anirban

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