* [PATCH v2 01/16] drm/xe/multi_queue: Add multi_queue_enable_mask to gt information
2025-11-04 18:51 [PATCH v2 00/16] drm/xe: Multi Queue feature support Niranjana Vishwanathapura
@ 2025-11-04 18:51 ` Niranjana Vishwanathapura
2025-11-04 22:42 ` Matthew Brost
2025-11-04 18:51 ` [PATCH v2 02/16] drm/xe/multi_queue: Add user interface for multi queue support Niranjana Vishwanathapura
` (18 subsequent siblings)
19 siblings, 1 reply; 27+ messages in thread
From: Niranjana Vishwanathapura @ 2025-11-04 18:51 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.brost
Add multi_queue_enable_mask field to the gt information structure
which is bitmask of all engine classes with multi queue support
enabled.
v2: Rename multi_queue_enable_mask to multi_queue_engine_class_mask
(Matt Brost)
Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
---
drivers/gpu/drm/xe/xe_debugfs.c | 2 ++
drivers/gpu/drm/xe/xe_gt_types.h | 5 +++++
drivers/gpu/drm/xe/xe_pci.c | 1 +
drivers/gpu/drm/xe/xe_pci_types.h | 1 +
4 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_debugfs.c b/drivers/gpu/drm/xe/xe_debugfs.c
index e91da9589c5f..e1e3f7ddeff7 100644
--- a/drivers/gpu/drm/xe/xe_debugfs.c
+++ b/drivers/gpu/drm/xe/xe_debugfs.c
@@ -93,6 +93,8 @@ static int info(struct seq_file *m, void *data)
xe_force_wake_ref(gt_to_fw(gt), XE_FW_GT));
drm_printf(&p, "gt%d engine_mask 0x%llx\n", id,
gt->info.engine_mask);
+ drm_printf(&p, "gt%d multi_queue_engine_class_mask 0x%x\n", id,
+ gt->info.multi_queue_engine_class_mask);
}
xe_pm_runtime_put(xe);
diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
index 0a728180b6fe..5318d92fd473 100644
--- a/drivers/gpu/drm/xe/xe_gt_types.h
+++ b/drivers/gpu/drm/xe/xe_gt_types.h
@@ -140,6 +140,11 @@ struct xe_gt {
u64 engine_mask;
/** @info.gmdid: raw GMD_ID value from hardware */
u32 gmdid;
+ /**
+ * @multi_queue_engine_class_mask: Bitmask of engine classes with
+ * multi queue support enabled.
+ */
+ u16 multi_queue_engine_class_mask;
/** @info.id: Unique ID of this GT within the PCI Device */
u8 id;
/** @info.has_indirect_ring_state: GT has indirect ring state support */
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 6e59642e7820..927d3a62c02d 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -754,6 +754,7 @@ static struct xe_gt *alloc_primary_gt(struct xe_tile *tile,
gt->info.type = XE_GT_TYPE_MAIN;
gt->info.id = tile->id * xe->info.max_gt_per_tile;
gt->info.has_indirect_ring_state = graphics_desc->has_indirect_ring_state;
+ gt->info.multi_queue_engine_class_mask = graphics_desc->multi_queue_engine_class_mask;
gt->info.engine_mask = graphics_desc->hw_engine_mask;
/*
diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
index 9892c063a9c5..975e9857f70c 100644
--- a/drivers/gpu/drm/xe/xe_pci_types.h
+++ b/drivers/gpu/drm/xe/xe_pci_types.h
@@ -58,6 +58,7 @@ struct xe_device_desc {
struct xe_graphics_desc {
u64 hw_engine_mask; /* hardware engines provided by graphics IP */
+ u16 multi_queue_engine_class_mask; /* bitmask of engine classes which support multi queue */
u8 has_asid:1;
u8 has_atomic_enable_pte_bit:1;
--
2.43.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH v2 01/16] drm/xe/multi_queue: Add multi_queue_enable_mask to gt information
2025-11-04 18:51 ` [PATCH v2 01/16] drm/xe/multi_queue: Add multi_queue_enable_mask to gt information Niranjana Vishwanathapura
@ 2025-11-04 22:42 ` Matthew Brost
0 siblings, 0 replies; 27+ messages in thread
From: Matthew Brost @ 2025-11-04 22:42 UTC (permalink / raw)
To: Niranjana Vishwanathapura; +Cc: intel-xe
On Tue, Nov 04, 2025 at 10:51:35AM -0800, Niranjana Vishwanathapura wrote:
> Add multi_queue_enable_mask field to the gt information structure
> which is bitmask of all engine classes with multi queue support
> enabled.
>
> v2: Rename multi_queue_enable_mask to multi_queue_engine_class_mask
> (Matt Brost)
>
> Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
> ---
> drivers/gpu/drm/xe/xe_debugfs.c | 2 ++
> drivers/gpu/drm/xe/xe_gt_types.h | 5 +++++
> drivers/gpu/drm/xe/xe_pci.c | 1 +
> drivers/gpu/drm/xe/xe_pci_types.h | 1 +
> 4 files changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/xe_debugfs.c b/drivers/gpu/drm/xe/xe_debugfs.c
> index e91da9589c5f..e1e3f7ddeff7 100644
> --- a/drivers/gpu/drm/xe/xe_debugfs.c
> +++ b/drivers/gpu/drm/xe/xe_debugfs.c
> @@ -93,6 +93,8 @@ static int info(struct seq_file *m, void *data)
> xe_force_wake_ref(gt_to_fw(gt), XE_FW_GT));
> drm_printf(&p, "gt%d engine_mask 0x%llx\n", id,
> gt->info.engine_mask);
> + drm_printf(&p, "gt%d multi_queue_engine_class_mask 0x%x\n", id,
> + gt->info.multi_queue_engine_class_mask);
> }
>
> xe_pm_runtime_put(xe);
> diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
> index 0a728180b6fe..5318d92fd473 100644
> --- a/drivers/gpu/drm/xe/xe_gt_types.h
> +++ b/drivers/gpu/drm/xe/xe_gt_types.h
> @@ -140,6 +140,11 @@ struct xe_gt {
> u64 engine_mask;
> /** @info.gmdid: raw GMD_ID value from hardware */
> u32 gmdid;
> + /**
> + * @multi_queue_engine_class_mask: Bitmask of engine classes with
> + * multi queue support enabled.
> + */
> + u16 multi_queue_engine_class_mask;
> /** @info.id: Unique ID of this GT within the PCI Device */
> u8 id;
> /** @info.has_indirect_ring_state: GT has indirect ring state support */
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index 6e59642e7820..927d3a62c02d 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -754,6 +754,7 @@ static struct xe_gt *alloc_primary_gt(struct xe_tile *tile,
> gt->info.type = XE_GT_TYPE_MAIN;
> gt->info.id = tile->id * xe->info.max_gt_per_tile;
> gt->info.has_indirect_ring_state = graphics_desc->has_indirect_ring_state;
> + gt->info.multi_queue_engine_class_mask = graphics_desc->multi_queue_engine_class_mask;
> gt->info.engine_mask = graphics_desc->hw_engine_mask;
>
> /*
> diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
> index 9892c063a9c5..975e9857f70c 100644
> --- a/drivers/gpu/drm/xe/xe_pci_types.h
> +++ b/drivers/gpu/drm/xe/xe_pci_types.h
> @@ -58,6 +58,7 @@ struct xe_device_desc {
>
> struct xe_graphics_desc {
> u64 hw_engine_mask; /* hardware engines provided by graphics IP */
> + u16 multi_queue_engine_class_mask; /* bitmask of engine classes which support multi queue */
>
> u8 has_asid:1;
> u8 has_atomic_enable_pte_bit:1;
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v2 02/16] drm/xe/multi_queue: Add user interface for multi queue support
2025-11-04 18:51 [PATCH v2 00/16] drm/xe: Multi Queue feature support Niranjana Vishwanathapura
2025-11-04 18:51 ` [PATCH v2 01/16] drm/xe/multi_queue: Add multi_queue_enable_mask to gt information Niranjana Vishwanathapura
@ 2025-11-04 18:51 ` Niranjana Vishwanathapura
2025-11-04 18:51 ` [PATCH v2 03/16] drm/xe/multi_queue: Add GuC " Niranjana Vishwanathapura
` (17 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Niranjana Vishwanathapura @ 2025-11-04 18:51 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.brost
Multi Queue is a new mode of execution supported by the compute and
blitter copy command streamers (CCS and BCS, respectively). It is an
enhancement of the existing hardware architecture and leverages the
same submission model. It enables support for efficient, parallel
execution of multiple queues within a single context. All the queues
of a group must use the same address space (VM).
The new DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE execution queue
property supports creating a multi queue group and adding queues to
a queue group. All queues of a multi queue group share the same
context.
A exec queue create ioctl call with above property specified with value
DRM_XE_SUPER_GROUP_CREATE will create a new multi queue group with the
queue being created as the primary queue (aka q0) of the group. To add
secondary queues to the group, they need to be created with the above
property with id of the primary queue as the value. The properties of
the primary queue (like priority, timeslice) applies to the whole group.
So, these properties can't be set for secondary queues of a group.
Once destroyed, the secondary queues of a multi queue group can't be
replaced. However, they can be dynamically added to the group up to a
total of 64 queues per group. Once the primary queue is destroyed,
secondary queues can't be added to the queue group.
v2: Remove group->lock, fix xe_exec_queue_group_add()/delete()
function semantics, add additional comments, remove unused
group->list_lock, add XE_BO_FLAG_GGTT_INVALIDATE for cgp bo,
Assert LRC is valid, update uapi kernel doc.
(Matt Brost)
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
---
drivers/gpu/drm/xe/xe_exec_queue.c | 191 ++++++++++++++++++++++-
drivers/gpu/drm/xe/xe_exec_queue.h | 47 ++++++
drivers/gpu/drm/xe/xe_exec_queue_types.h | 26 +++
include/uapi/drm/xe_drm.h | 10 ++
4 files changed, 272 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
index 8724f8de67e2..3a701fa477d7 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue.c
+++ b/drivers/gpu/drm/xe/xe_exec_queue.c
@@ -13,6 +13,7 @@
#include <drm/drm_syncobj.h>
#include <uapi/drm/xe_drm.h>
+#include "xe_bo.h"
#include "xe_dep_scheduler.h"
#include "xe_device.h"
#include "xe_gt.h"
@@ -63,6 +64,33 @@ enum xe_exec_queue_sched_prop {
static int exec_queue_user_extensions(struct xe_device *xe, struct xe_exec_queue *q,
u64 extensions, int ext_number);
+static void xe_exec_queue_group_cleanup(struct xe_exec_queue *q)
+{
+ struct xe_exec_queue_group *group = q->multi_queue.group;
+ struct xe_lrc *lrc;
+ unsigned long idx;
+
+ if (xe_exec_queue_is_multi_queue_secondary(q)) {
+ /*
+ * Put pairs with get from xe_exec_queue_lookup() call
+ * in xe_exec_queue_group_validate().
+ */
+ xe_exec_queue_put(xe_exec_queue_multi_queue_primary(q));
+ return;
+ }
+
+ if (!group)
+ return;
+
+ /* Primary queue cleanup */
+ xa_for_each(&group->xa, idx, lrc)
+ xe_lrc_put(lrc);
+
+ xa_destroy(&group->xa);
+ xe_bo_unpin_map_no_vm(group->cgp_bo);
+ kfree(group);
+}
+
static void __xe_exec_queue_free(struct xe_exec_queue *q)
{
int i;
@@ -73,6 +101,10 @@ static void __xe_exec_queue_free(struct xe_exec_queue *q)
if (xe_exec_queue_uses_pxp(q))
xe_pxp_exec_queue_remove(gt_to_xe(q->gt)->pxp, q);
+
+ if (xe_exec_queue_is_multi_queue(q))
+ xe_exec_queue_group_cleanup(q);
+
if (q->vm)
xe_vm_put(q->vm);
@@ -567,6 +599,144 @@ exec_queue_set_pxp_type(struct xe_device *xe, struct xe_exec_queue *q, u64 value
return xe_pxp_exec_queue_set_type(xe->pxp, q, DRM_XE_PXP_TYPE_HWDRM);
}
+static int xe_exec_queue_group_init(struct xe_device *xe, struct xe_exec_queue *q)
+{
+ struct xe_tile *tile = gt_to_tile(q->gt);
+ struct xe_exec_queue_group *group;
+ struct xe_bo *bo;
+
+ group = kzalloc(sizeof(*group), GFP_KERNEL);
+ if (!group)
+ return -ENOMEM;
+
+ bo = xe_bo_create_pin_map_novm(xe, tile, SZ_4K, ttm_bo_type_kernel,
+ XE_BO_FLAG_VRAM_IF_DGFX(tile) | XE_BO_FLAG_GGTT |
+ XE_BO_FLAG_GGTT_INVALIDATE, false);
+ if (IS_ERR(bo)) {
+ drm_err(&xe->drm, "CGP bo allocation for queue group failed: %ld\n",
+ PTR_ERR(bo));
+ kfree(group);
+ return PTR_ERR(bo);
+ }
+
+ xe_map_memset(xe, &bo->vmap, 0, 0, SZ_4K);
+
+ group->primary = q;
+ group->cgp_bo = bo;
+ xa_init_flags(&group->xa, XA_FLAGS_ALLOC1);
+ q->multi_queue.group = group;
+
+ return 0;
+}
+
+static inline bool xe_exec_queue_supports_multi_queue(struct xe_exec_queue *q)
+{
+ return q->gt->info.multi_queue_engine_class_mask & BIT(q->class);
+}
+
+static int xe_exec_queue_group_validate(struct xe_device *xe, struct xe_exec_queue *q,
+ u32 primary_id)
+{
+ struct xe_exec_queue_group *group;
+ struct xe_exec_queue *primary;
+ int ret;
+
+ /*
+ * Get from below xe_exec_queue_lookup() pairs with put
+ * in xe_exec_queue_group_cleanup().
+ */
+ primary = xe_exec_queue_lookup(q->vm->xef, primary_id);
+ if (XE_IOCTL_DBG(xe, !primary))
+ return -ENOENT;
+
+ if (XE_IOCTL_DBG(xe, !xe_exec_queue_is_multi_queue_primary(primary)) ||
+ XE_IOCTL_DBG(xe, q->vm != primary->vm) ||
+ XE_IOCTL_DBG(xe, q->logical_mask != primary->logical_mask)) {
+ ret = -EINVAL;
+ goto put_primary;
+ }
+
+ group = primary->multi_queue.group;
+ q->multi_queue.valid = true;
+ q->multi_queue.group = group;
+
+ return 0;
+put_primary:
+ xe_exec_queue_put(primary);
+ return ret;
+}
+
+#define XE_MAX_GROUP_SIZE 64
+static int xe_exec_queue_group_add(struct xe_device *xe, struct xe_exec_queue *q)
+{
+ struct xe_exec_queue_group *group = q->multi_queue.group;
+ u32 pos;
+ int err;
+
+ xe_assert(xe, xe_exec_queue_is_multi_queue_secondary(q));
+
+ /* Primary queue holds a reference to LRCs of all secondary queues */
+ err = xa_alloc(&group->xa, &pos, xe_lrc_get(q->lrc[0]),
+ XA_LIMIT(1, XE_MAX_GROUP_SIZE - 1), GFP_KERNEL);
+ if (XE_IOCTL_DBG(xe, err)) {
+ xe_lrc_put(q->lrc[0]);
+
+ /* It is invalid if queue group limit is exceeded */
+ if (err == -EBUSY)
+ err = -EINVAL;
+
+ return err;
+ }
+
+ q->multi_queue.pos = pos;
+
+ return 0;
+}
+
+static void xe_exec_queue_group_delete(struct xe_device *xe, struct xe_exec_queue *q)
+{
+ struct xe_exec_queue_group *group = q->multi_queue.group;
+ struct xe_lrc *lrc;
+
+ xe_assert(xe, xe_exec_queue_is_multi_queue_secondary(q));
+
+ lrc = xa_erase(&group->xa, q->multi_queue.pos);
+ xe_assert(xe, lrc);
+ xe_lrc_put(lrc);
+}
+
+static int exec_queue_set_multi_group(struct xe_device *xe, struct xe_exec_queue *q,
+ u64 value)
+{
+ if (XE_IOCTL_DBG(xe, !xe_exec_queue_supports_multi_queue(q)))
+ return -ENODEV;
+
+ if (XE_IOCTL_DBG(xe, !xe_device_uc_enabled(xe)))
+ return -EOPNOTSUPP;
+
+ if (XE_IOCTL_DBG(xe, xe_exec_queue_is_parallel(q)))
+ return -EINVAL;
+
+ if (XE_IOCTL_DBG(xe, xe_exec_queue_is_multi_queue(q)))
+ return -EINVAL;
+
+ if (value & DRM_XE_MULTI_GROUP_CREATE) {
+ if (XE_IOCTL_DBG(xe, value & ~DRM_XE_MULTI_GROUP_CREATE))
+ return -EINVAL;
+
+ q->multi_queue.valid = true;
+ q->multi_queue.is_primary = true;
+ q->multi_queue.pos = 0;
+ return 0;
+ }
+
+ /* While adding secondary queues, the upper 32 bits must be 0 */
+ if (XE_IOCTL_DBG(xe, value & (~0ull << 32)))
+ return -EINVAL;
+
+ return xe_exec_queue_group_validate(xe, q, value);
+}
+
typedef int (*xe_exec_queue_set_property_fn)(struct xe_device *xe,
struct xe_exec_queue *q,
u64 value);
@@ -575,6 +745,7 @@ static const xe_exec_queue_set_property_fn exec_queue_set_property_funcs[] = {
[DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY] = exec_queue_set_priority,
[DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE] = exec_queue_set_timeslice,
[DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE] = exec_queue_set_pxp_type,
+ [DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP] = exec_queue_set_multi_group,
};
static int exec_queue_user_ext_set_property(struct xe_device *xe,
@@ -595,7 +766,8 @@ static int exec_queue_user_ext_set_property(struct xe_device *xe,
XE_IOCTL_DBG(xe, ext.pad) ||
XE_IOCTL_DBG(xe, ext.property != DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY &&
ext.property != DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE &&
- ext.property != DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE))
+ ext.property != DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE &&
+ ext.property != DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP))
return -EINVAL;
idx = array_index_nospec(ext.property, ARRAY_SIZE(exec_queue_set_property_funcs));
@@ -644,6 +816,12 @@ static int exec_queue_user_extensions(struct xe_device *xe, struct xe_exec_queue
return exec_queue_user_extensions(xe, q, ext.next_extension,
++ext_number);
+ if (xe_exec_queue_is_multi_queue_primary(q)) {
+ err = xe_exec_queue_group_init(xe, q);
+ if (XE_IOCTL_DBG(xe, err))
+ return err;
+ }
+
return 0;
}
@@ -798,12 +976,18 @@ int xe_exec_queue_create_ioctl(struct drm_device *dev, void *data,
if (IS_ERR(q))
return PTR_ERR(q);
+ if (xe_exec_queue_is_multi_queue_secondary(q)) {
+ err = xe_exec_queue_group_add(xe, q);
+ if (XE_IOCTL_DBG(xe, err))
+ goto put_exec_queue;
+ }
+
if (xe_vm_in_preempt_fence_mode(vm)) {
q->lr.context = dma_fence_context_alloc(1);
err = xe_vm_add_compute_exec_queue(vm, q);
if (XE_IOCTL_DBG(xe, err))
- goto put_exec_queue;
+ goto delete_queue_group;
}
if (q->vm && q->hwe->hw_engine_group) {
@@ -826,6 +1010,9 @@ int xe_exec_queue_create_ioctl(struct drm_device *dev, void *data,
kill_exec_queue:
xe_exec_queue_kill(q);
+delete_queue_group:
+ if (xe_exec_queue_is_multi_queue_secondary(q))
+ xe_exec_queue_group_delete(xe, q);
put_exec_queue:
xe_exec_queue_put(q);
return err;
diff --git a/drivers/gpu/drm/xe/xe_exec_queue.h b/drivers/gpu/drm/xe/xe_exec_queue.h
index fda4d4f9bda8..e6daa40003f2 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue.h
+++ b/drivers/gpu/drm/xe/xe_exec_queue.h
@@ -66,6 +66,53 @@ static inline bool xe_exec_queue_uses_pxp(struct xe_exec_queue *q)
return q->pxp.type;
}
+/**
+ * xe_exec_queue_is_multi_queue() - Whether an exec_queue is part of a queue group.
+ * @q: The exec_queue
+ *
+ * Return: True if the exec_queue is part of a queue group, false otherwise.
+ */
+static inline bool xe_exec_queue_is_multi_queue(struct xe_exec_queue *q)
+{
+ return q->multi_queue.valid;
+}
+
+/**
+ * xe_exec_queue_is_multi_queue_primary() - Whether an exec_queue is primary queue
+ * of a multi queue group.
+ * @q: The exec_queue
+ *
+ * Return: True if @q is primary queue of a queue group, false otherwise.
+ */
+static inline bool xe_exec_queue_is_multi_queue_primary(struct xe_exec_queue *q)
+{
+ return q->multi_queue.is_primary;
+}
+
+/**
+ * xe_exec_queue_is_multi_queue_secondary() - Whether an exec_queue is secondary queue
+ * of a multi queue group.
+ * @q: The exec_queue
+ *
+ * Return: True if @q is secondary queue of a queue group, false otherwise.
+ */
+static inline bool xe_exec_queue_is_multi_queue_secondary(struct xe_exec_queue *q)
+{
+ return xe_exec_queue_is_multi_queue(q) && !xe_exec_queue_is_multi_queue_primary(q);
+}
+
+/**
+ * xe_exec_queue_multi_queue_primary() - Get multi queue group's primary queue
+ * @q: The exec_queue
+ *
+ * If @q belongs to a multi queue group, then the primary queue of the group will
+ * be returned. Otherwise, @q will be returned.
+ */
+static inline struct xe_exec_queue *xe_exec_queue_multi_queue_primary(struct xe_exec_queue *q)
+{
+ return xe_exec_queue_is_multi_queue(q) ? q->multi_queue.group->primary : q;
+}
+
bool xe_exec_queue_is_lr(struct xe_exec_queue *q);
bool xe_exec_queue_is_idle(struct xe_exec_queue *q);
diff --git a/drivers/gpu/drm/xe/xe_exec_queue_types.h b/drivers/gpu/drm/xe/xe_exec_queue_types.h
index 771ffe35cd0c..f429b1952be9 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue_types.h
+++ b/drivers/gpu/drm/xe/xe_exec_queue_types.h
@@ -32,6 +32,20 @@ enum xe_exec_queue_priority {
XE_EXEC_QUEUE_PRIORITY_COUNT
};
+/**
+ * struct xe_exec_queue_group - Execution multi queue group
+ *
+ * Contains multi queue group information.
+ */
+struct xe_exec_queue_group {
+ /** @primary: Primary queue of this group */
+ struct xe_exec_queue *primary;
+ /** @cgp_bo: BO for the Context Group Page */
+ struct xe_bo *cgp_bo;
+ /** @xa: xarray to store LRCs */
+ struct xarray xa;
+};
+
/**
* struct xe_exec_queue - Execution queue
*
@@ -111,6 +125,18 @@ struct xe_exec_queue {
struct xe_guc_exec_queue *guc;
};
+ /** @multi_queue: Multi queue information */
+ struct {
+ /** @multi_queue.group: Queue group information */
+ struct xe_exec_queue_group *group;
+ /** @multi_queue.pos: Position of queue within the multi-queue group */
+ u8 pos;
+ /** @multi_queue.valid: Queue belongs to a multi queue group */
+ u8 valid:1;
+ /** @multi_queue.is_primary: Is primary queue (Q0) of the group */
+ u8 is_primary:1;
+ } multi_queue;
+
/** @sched_props: scheduling properties */
struct {
/** @sched_props.timeslice_us: timeslice period in micro-seconds */
diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
index 47853659a705..4de21e0a4fcf 100644
--- a/include/uapi/drm/xe_drm.h
+++ b/include/uapi/drm/xe_drm.h
@@ -1252,6 +1252,14 @@ struct drm_xe_vm_bind {
* Given that going into a power-saving state kills PXP HWDRM sessions,
* runtime PM will be blocked while queues of this type are alive.
* All PXP queues will be killed if a PXP invalidation event occurs.
+ * - %DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP - Create a multi-queue group
+ * or add secondary queues to a multi-queue group.
+ * If the extension's 'value' field has %DRM_XE_MULTI_GROUP_CREATE flag set,
+ * then a new multi-queue group is created with this queue as the primary queue
+ * (Q0). Otherwise, the queue gets added to the multi-queue group whose primary
+ * queue's exec_queue_id is specified in the lower 32 bits of the 'value' field.
+ * All the other non-relevant bits of extension's 'value' field while adding the
+ * primary or the secondary queues of the group must be set to 0.
*
* The example below shows how to use @drm_xe_exec_queue_create to create
* a simple exec_queue (no parallel submission) of class
@@ -1292,6 +1300,8 @@ struct drm_xe_exec_queue_create {
#define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY 0
#define DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE 1
#define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE 2
+#define DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP 3
+#define DRM_XE_MULTI_GROUP_CREATE (1ull << 63)
/** @extensions: Pointer to the first extension struct, if any */
__u64 extensions;
--
2.43.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v2 03/16] drm/xe/multi_queue: Add GuC interface for multi queue support
2025-11-04 18:51 [PATCH v2 00/16] drm/xe: Multi Queue feature support Niranjana Vishwanathapura
2025-11-04 18:51 ` [PATCH v2 01/16] drm/xe/multi_queue: Add multi_queue_enable_mask to gt information Niranjana Vishwanathapura
2025-11-04 18:51 ` [PATCH v2 02/16] drm/xe/multi_queue: Add user interface for multi queue support Niranjana Vishwanathapura
@ 2025-11-04 18:51 ` Niranjana Vishwanathapura
2025-11-04 18:51 ` [PATCH v2 04/16] drm/xe/multi_queue: Add multi queue priority property Niranjana Vishwanathapura
` (16 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Niranjana Vishwanathapura @ 2025-11-04 18:51 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.brost
Implement GuC commands and response along with the Context
Group Page (CGP) interface for multi queue support.
Ensure that only primary queue (q0) of a multi queue group
communicate with GuC. The secondary queues of the group only
need to maintain LRCA and interface with drm scheduler.
Use primary queue's submit_wq for all secondary queues of a multi
queue group. This serialization avoids any locking around CGP
synchronization with GuC.
v2: Fix G2H_LEN_DW_MULTI_QUEUE_CONTEXT value, add more comments
(Matt Brost)
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
---
drivers/gpu/drm/xe/abi/guc_actions_abi.h | 3 +
drivers/gpu/drm/xe/xe_exec_queue_types.h | 2 +
drivers/gpu/drm/xe/xe_guc_ct.c | 4 +
drivers/gpu/drm/xe/xe_guc_fwif.h | 3 +
drivers/gpu/drm/xe/xe_guc_submit.c | 309 +++++++++++++++++++----
drivers/gpu/drm/xe/xe_guc_submit.h | 1 +
6 files changed, 277 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/xe/abi/guc_actions_abi.h b/drivers/gpu/drm/xe/abi/guc_actions_abi.h
index 47756e4674a1..3e9fbed9cda6 100644
--- a/drivers/gpu/drm/xe/abi/guc_actions_abi.h
+++ b/drivers/gpu/drm/xe/abi/guc_actions_abi.h
@@ -139,6 +139,9 @@ enum xe_guc_action {
XE_GUC_ACTION_DEREGISTER_G2G = 0x4508,
XE_GUC_ACTION_DEREGISTER_CONTEXT_DONE = 0x4600,
XE_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC = 0x4601,
+ XE_GUC_ACTION_REGISTER_CONTEXT_MULTI_QUEUE = 0x4602,
+ XE_GUC_ACTION_MULTI_QUEUE_CONTEXT_CGP_SYNC = 0x4603,
+ XE_GUC_ACTION_NOTIFY_MULTI_QUEUE_CONTEXT_CGP_SYNC_DONE = 0x4604,
XE_GUC_ACTION_CLIENT_SOFT_RESET = 0x5507,
XE_GUC_ACTION_SET_ENG_UTIL_BUFF = 0x550A,
XE_GUC_ACTION_SET_DEVICE_ENGINE_ACTIVITY_BUFFER = 0x550C,
diff --git a/drivers/gpu/drm/xe/xe_exec_queue_types.h b/drivers/gpu/drm/xe/xe_exec_queue_types.h
index f429b1952be9..b9da51ab7eaf 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue_types.h
+++ b/drivers/gpu/drm/xe/xe_exec_queue_types.h
@@ -44,6 +44,8 @@ struct xe_exec_queue_group {
struct xe_bo *cgp_bo;
/** @xa: xarray to store LRCs */
struct xarray xa;
+ /** @sync_pending: CGP_SYNC_DONE g2h response pending */
+ bool sync_pending;
};
/**
diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c b/drivers/gpu/drm/xe/xe_guc_ct.c
index 2697d711adb2..43a79bcdfb18 100644
--- a/drivers/gpu/drm/xe/xe_guc_ct.c
+++ b/drivers/gpu/drm/xe/xe_guc_ct.c
@@ -1307,6 +1307,7 @@ static int parse_g2h_event(struct xe_guc_ct *ct, u32 *msg, u32 len)
lockdep_assert_held(&ct->lock);
switch (action) {
+ case XE_GUC_ACTION_NOTIFY_MULTI_QUEUE_CONTEXT_CGP_SYNC_DONE:
case XE_GUC_ACTION_SCHED_CONTEXT_MODE_DONE:
case XE_GUC_ACTION_DEREGISTER_CONTEXT_DONE:
case XE_GUC_ACTION_SCHED_ENGINE_MODE_DONE:
@@ -1569,6 +1570,9 @@ static int process_g2h_msg(struct xe_guc_ct *ct, u32 *msg, u32 len)
ret = xe_guc_g2g_test_notification(guc, payload, adj_len);
break;
#endif
+ case XE_GUC_ACTION_NOTIFY_MULTI_QUEUE_CONTEXT_CGP_SYNC_DONE:
+ ret = xe_guc_exec_queue_cgp_sync_done_handler(guc, payload, adj_len);
+ break;
default:
xe_gt_err(gt, "unexpected G2H action 0x%04x\n", action);
}
diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h
index c90dd266e9cf..9b090d9b95f1 100644
--- a/drivers/gpu/drm/xe/xe_guc_fwif.h
+++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
@@ -16,6 +16,7 @@
#define G2H_LEN_DW_DEREGISTER_CONTEXT 3
#define G2H_LEN_DW_TLB_INVALIDATE 3
#define G2H_LEN_DW_G2G_NOTIFY_MIN 3
+#define G2H_LEN_DW_MULTI_QUEUE_CONTEXT 3
#define GUC_ID_MAX 65535
#define GUC_ID_UNKNOWN 0xffffffff
@@ -62,6 +63,8 @@ struct guc_ctxt_registration_info {
u32 wq_base_lo;
u32 wq_base_hi;
u32 wq_size;
+ u32 cgp_lo;
+ u32 cgp_hi;
u32 hwlrca_lo;
u32 hwlrca_hi;
};
diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
index d4ffdb71ef3d..2e5106687a6e 100644
--- a/drivers/gpu/drm/xe/xe_guc_submit.c
+++ b/drivers/gpu/drm/xe/xe_guc_submit.c
@@ -19,6 +19,7 @@
#include "abi/guc_klvs_abi.h"
#include "regs/xe_lrc_layout.h"
#include "xe_assert.h"
+#include "xe_bo.h"
#include "xe_devcoredump.h"
#include "xe_device.h"
#include "xe_exec_queue.h"
@@ -541,7 +542,8 @@ static void init_policies(struct xe_guc *guc, struct xe_exec_queue *q)
u32 slpc_exec_queue_freq_req = 0;
u32 preempt_timeout_us = q->sched_props.preempt_timeout_us;
- xe_gt_assert(guc_to_gt(guc), exec_queue_registered(q));
+ xe_gt_assert(guc_to_gt(guc), exec_queue_registered(q) &&
+ !xe_exec_queue_is_multi_queue_secondary(q));
if (q->flags & EXEC_QUEUE_FLAG_LOW_LATENCY)
slpc_exec_queue_freq_req |= SLPC_CTX_FREQ_REQ_IS_COMPUTE;
@@ -561,6 +563,8 @@ static void set_min_preemption_timeout(struct xe_guc *guc, struct xe_exec_queue
{
struct exec_queue_policy policy;
+ xe_assert(guc_to_xe(guc), !xe_exec_queue_is_multi_queue_secondary(q));
+
__guc_exec_queue_policy_start_klv(&policy, q->guc->id);
__guc_exec_queue_policy_add_preemption_timeout(&policy, 1);
@@ -575,6 +579,136 @@ static void set_min_preemption_timeout(struct xe_guc *guc, struct xe_exec_queue
xe_map_wr_field(xe_, &map_, 0, struct guc_submit_parallel_scratch, \
field_, val_)
+#define CGP_VERSION_MAJOR_SHIFT 8
+
+static void xe_guc_exec_queue_group_cgp_update(struct xe_device *xe,
+ struct xe_exec_queue *q)
+{
+ struct xe_exec_queue_group *group = q->multi_queue.group;
+ u32 guc_id = group->primary->guc->id;
+
+ /* Currently implementing CGP version 1.0 */
+ xe_map_wr(xe, &group->cgp_bo->vmap, 0, u32,
+ 1 << CGP_VERSION_MAJOR_SHIFT);
+
+ xe_map_wr(xe, &group->cgp_bo->vmap,
+ (32 + q->multi_queue.pos * 2) * sizeof(u32),
+ u32, lower_32_bits(xe_lrc_descriptor(q->lrc[0])));
+
+ xe_map_wr(xe, &group->cgp_bo->vmap,
+ (33 + q->multi_queue.pos * 2) * sizeof(u32),
+ u32, guc_id);
+
+ if (q->multi_queue.pos / 32) {
+ xe_map_wr(xe, &group->cgp_bo->vmap, 17 * sizeof(u32),
+ u32, BIT(q->multi_queue.pos % 32));
+ xe_map_wr(xe, &group->cgp_bo->vmap, 16 * sizeof(u32), u32, 0);
+ } else {
+ xe_map_wr(xe, &group->cgp_bo->vmap, 16 * sizeof(u32),
+ u32, BIT(q->multi_queue.pos));
+ xe_map_wr(xe, &group->cgp_bo->vmap, 17 * sizeof(u32), u32, 0);
+ }
+}
+
+static void xe_guc_exec_queue_group_cgp_sync(struct xe_guc *guc,
+ struct xe_exec_queue *q,
+ const u32 *action, u32 len)
+{
+ struct xe_exec_queue_group *group = q->multi_queue.group;
+ struct xe_device *xe = guc_to_xe(guc);
+ long ret;
+
+ /*
+ * As all queues of a multi queue group use single drm scheduler
+ * submit workqueue, CGP synchronization with GuC are serialized.
+ * Hence, no locking is required here.
+ * Wait for any pending CGP_SYNC_DONE response before updating the
+ * CGP page and sending CGP_SYNC message.
+ */
+ ret = wait_event_timeout(guc->ct.wq,
+ !READ_ONCE(group->sync_pending) ||
+ xe_guc_read_stopped(guc), HZ);
+ if (!ret || xe_guc_read_stopped(guc)) {
+ drm_err(&xe->drm, "Wait for CGP_SYNC_DONE response failed!\n");
+ /* Something wrong with the CTB or GuC, no need to proceed */
+ return;
+ }
+
+ xe_guc_exec_queue_group_cgp_update(xe, q);
+
+ WRITE_ONCE(group->sync_pending, true);
+ xe_guc_ct_send(&guc->ct, action, len, G2H_LEN_DW_MULTI_QUEUE_CONTEXT, 1);
+}
+
+static void __register_exec_queue(struct xe_guc *guc,
+ struct guc_ctxt_registration_info *info)
+{
+ u32 action[] = {
+ XE_GUC_ACTION_REGISTER_CONTEXT,
+ info->flags,
+ info->context_idx,
+ info->engine_class,
+ info->engine_submit_mask,
+ info->wq_desc_lo,
+ info->wq_desc_hi,
+ info->wq_base_lo,
+ info->wq_base_hi,
+ info->wq_size,
+ info->hwlrca_lo,
+ info->hwlrca_hi,
+ };
+
+ /* explicitly checks some fields that we might fixup later */
+ xe_gt_assert(guc_to_gt(guc), info->wq_desc_lo ==
+ action[XE_GUC_REGISTER_CONTEXT_DATA_5_WQ_DESC_ADDR_LOWER]);
+ xe_gt_assert(guc_to_gt(guc), info->wq_base_lo ==
+ action[XE_GUC_REGISTER_CONTEXT_DATA_7_WQ_BUF_BASE_LOWER]);
+ xe_gt_assert(guc_to_gt(guc), info->hwlrca_lo ==
+ action[XE_GUC_REGISTER_CONTEXT_DATA_10_HW_LRC_ADDR]);
+
+ xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action), 0, 0);
+}
+
+static void __register_exec_queue_group(struct xe_guc *guc,
+ struct xe_exec_queue *q,
+ struct guc_ctxt_registration_info *info)
+{
+#define MAX_MULTI_QUEUE_REG_SIZE (8)
+ struct xe_device *xe = guc_to_xe(guc);
+ u32 action[MAX_MULTI_QUEUE_REG_SIZE];
+ int len = 0;
+
+ if (xe_exec_queue_is_multi_queue_primary(q)) {
+ action[len++] = XE_GUC_ACTION_REGISTER_CONTEXT_MULTI_QUEUE;
+ action[len++] = info->flags;
+ action[len++] = info->context_idx;
+ action[len++] = info->engine_class;
+ action[len++] = info->engine_submit_mask;
+ action[len++] = 0; /* Reserved */
+ action[len++] = info->cgp_lo;
+ action[len++] = info->cgp_hi;
+ } else {
+ /*
+ * No need to wait before CGP sync since CT descriptors
+ * should be ordered.
+ */
+
+ action[len++] = XE_GUC_ACTION_MULTI_QUEUE_CONTEXT_CGP_SYNC;
+ action[len++] = q->multi_queue.group->primary->guc->id;
+ }
+
+ xe_assert(xe, len <= MAX_MULTI_QUEUE_REG_SIZE);
+#undef MAX_MULTI_QUEUE_REG_SIZE
+
+ /*
+ * Both of the above XE_GUC_ACTION_REGISTER_CONTEXT_MULTI_QUEUE
+ * and XE_GUC_ACTION_MULTI_QUEUE_CONTEXT_CGP_SYNC do expect a
+ * XE_GUC_ACTION_NOTIFY_MULTI_QUEUE_CONTEXT_CGP_SYNC_DONE response
+ * from guc.
+ */
+ xe_guc_exec_queue_group_cgp_sync(guc, q, action, len);
+}
+
static void __register_mlrc_exec_queue(struct xe_guc *guc,
struct xe_exec_queue *q,
struct guc_ctxt_registration_info *info)
@@ -622,35 +756,6 @@ static void __register_mlrc_exec_queue(struct xe_guc *guc,
xe_guc_ct_send(&guc->ct, action, len, 0, 0);
}
-static void __register_exec_queue(struct xe_guc *guc,
- struct guc_ctxt_registration_info *info)
-{
- u32 action[] = {
- XE_GUC_ACTION_REGISTER_CONTEXT,
- info->flags,
- info->context_idx,
- info->engine_class,
- info->engine_submit_mask,
- info->wq_desc_lo,
- info->wq_desc_hi,
- info->wq_base_lo,
- info->wq_base_hi,
- info->wq_size,
- info->hwlrca_lo,
- info->hwlrca_hi,
- };
-
- /* explicitly checks some fields that we might fixup later */
- xe_gt_assert(guc_to_gt(guc), info->wq_desc_lo ==
- action[XE_GUC_REGISTER_CONTEXT_DATA_5_WQ_DESC_ADDR_LOWER]);
- xe_gt_assert(guc_to_gt(guc), info->wq_base_lo ==
- action[XE_GUC_REGISTER_CONTEXT_DATA_7_WQ_BUF_BASE_LOWER]);
- xe_gt_assert(guc_to_gt(guc), info->hwlrca_lo ==
- action[XE_GUC_REGISTER_CONTEXT_DATA_10_HW_LRC_ADDR]);
-
- xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action), 0, 0);
-}
-
static void register_exec_queue(struct xe_exec_queue *q, int ctx_type)
{
struct xe_guc *guc = exec_queue_to_guc(q);
@@ -670,6 +775,13 @@ static void register_exec_queue(struct xe_exec_queue *q, int ctx_type)
info.flags = CONTEXT_REGISTRATION_FLAG_KMD |
FIELD_PREP(CONTEXT_REGISTRATION_FLAG_TYPE, ctx_type);
+ if (xe_exec_queue_is_multi_queue(q)) {
+ struct xe_exec_queue_group *group = q->multi_queue.group;
+
+ info.cgp_lo = xe_bo_ggtt_addr(group->cgp_bo);
+ info.cgp_hi = 0;
+ }
+
if (xe_exec_queue_is_parallel(q)) {
u64 ggtt_addr = xe_lrc_parallel_ggtt_addr(lrc);
struct iosys_map map = xe_lrc_parallel_map(lrc);
@@ -700,11 +812,15 @@ static void register_exec_queue(struct xe_exec_queue *q, int ctx_type)
set_exec_queue_registered(q);
trace_xe_exec_queue_register(q);
- if (xe_exec_queue_is_parallel(q))
+ if (xe_exec_queue_is_multi_queue(q))
+ __register_exec_queue_group(guc, q, &info);
+ else if (xe_exec_queue_is_parallel(q))
__register_mlrc_exec_queue(guc, q, &info);
else
__register_exec_queue(guc, &info);
- init_policies(guc, q);
+
+ if (!xe_exec_queue_is_multi_queue_secondary(q))
+ init_policies(guc, q);
}
static u32 wq_space_until_wrap(struct xe_exec_queue *q)
@@ -833,6 +949,12 @@ static void submit_exec_queue(struct xe_exec_queue *q, struct xe_sched_job *job)
if (exec_queue_suspended(q) && !xe_exec_queue_is_parallel(q))
return;
+ /*
+ * All queues in a multi-queue group will use the primary queue
+ * of the group to interface with GuC.
+ */
+ q = xe_exec_queue_multi_queue_primary(q);
+
if (!exec_queue_enabled(q) && !exec_queue_suspended(q)) {
action[len++] = XE_GUC_ACTION_SCHED_CONTEXT_MODE_SET;
action[len++] = q->guc->id;
@@ -879,6 +1001,18 @@ guc_exec_queue_run_job(struct drm_sched_job *drm_job)
trace_xe_sched_job_run(job);
if (!killed_or_banned_or_wedged && !xe_sched_job_is_error(job)) {
+ if (xe_exec_queue_is_multi_queue_secondary(q)) {
+ struct xe_exec_queue *primary = xe_exec_queue_multi_queue_primary(q);
+
+ if (exec_queue_killed_or_banned_or_wedged(primary)) {
+ killed_or_banned_or_wedged = true;
+ goto run_job_out;
+ }
+
+ if (!exec_queue_registered(primary))
+ register_exec_queue(primary, GUC_CONTEXT_NORMAL);
+ }
+
if (!exec_queue_registered(q))
register_exec_queue(q, GUC_CONTEXT_NORMAL);
if (!job->skip_emit)
@@ -887,6 +1021,7 @@ guc_exec_queue_run_job(struct drm_sched_job *drm_job)
job->skip_emit = false;
}
+run_job_out:
/*
* We don't care about job-fence ordering in LR VMs because these fences
* are never exported; they are used solely to keep jobs on the pending
@@ -912,6 +1047,11 @@ int xe_guc_read_stopped(struct xe_guc *guc)
return atomic_read(&guc->submission_state.stopped);
}
+static void handle_multi_queue_secondary_sched_done(struct xe_guc *guc,
+ struct xe_exec_queue *q,
+ u32 runnable_state);
+static void handle_deregister_done(struct xe_guc *guc, struct xe_exec_queue *q);
+
#define MAKE_SCHED_CONTEXT_ACTION(q, enable_disable) \
u32 action[] = { \
XE_GUC_ACTION_SCHED_CONTEXT_MODE_SET, \
@@ -925,7 +1065,9 @@ static void disable_scheduling_deregister(struct xe_guc *guc,
MAKE_SCHED_CONTEXT_ACTION(q, DISABLE);
int ret;
- set_min_preemption_timeout(guc, q);
+ if (!xe_exec_queue_is_multi_queue_secondary(q))
+ set_min_preemption_timeout(guc, q);
+
smp_rmb();
ret = wait_event_timeout(guc->ct.wq,
(!exec_queue_pending_enable(q) &&
@@ -953,9 +1095,12 @@ static void disable_scheduling_deregister(struct xe_guc *guc,
* Reserve space for both G2H here as the 2nd G2H is sent from a G2H
* handler and we are not allowed to reserved G2H space in handlers.
*/
- xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action),
- G2H_LEN_DW_SCHED_CONTEXT_MODE_SET +
- G2H_LEN_DW_DEREGISTER_CONTEXT, 2);
+ if (xe_exec_queue_is_multi_queue_secondary(q))
+ handle_multi_queue_secondary_sched_done(guc, q, 0);
+ else
+ xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action),
+ G2H_LEN_DW_SCHED_CONTEXT_MODE_SET +
+ G2H_LEN_DW_DEREGISTER_CONTEXT, 2);
}
static void xe_guc_exec_queue_trigger_cleanup(struct xe_exec_queue *q)
@@ -1161,8 +1306,11 @@ static void enable_scheduling(struct xe_exec_queue *q)
set_exec_queue_enabled(q);
trace_xe_exec_queue_scheduling_enable(q);
- xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action),
- G2H_LEN_DW_SCHED_CONTEXT_MODE_SET, 1);
+ if (xe_exec_queue_is_multi_queue_secondary(q))
+ handle_multi_queue_secondary_sched_done(guc, q, 1);
+ else
+ xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action),
+ G2H_LEN_DW_SCHED_CONTEXT_MODE_SET, 1);
ret = wait_event_timeout(guc->ct.wq,
!exec_queue_pending_enable(q) ||
@@ -1186,14 +1334,17 @@ static void disable_scheduling(struct xe_exec_queue *q, bool immediate)
xe_gt_assert(guc_to_gt(guc), exec_queue_registered(q));
xe_gt_assert(guc_to_gt(guc), !exec_queue_pending_disable(q));
- if (immediate)
+ if (immediate && !xe_exec_queue_is_multi_queue_secondary(q))
set_min_preemption_timeout(guc, q);
clear_exec_queue_enabled(q);
set_exec_queue_pending_disable(q);
trace_xe_exec_queue_scheduling_disable(q);
- xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action),
- G2H_LEN_DW_SCHED_CONTEXT_MODE_SET, 1);
+ if (xe_exec_queue_is_multi_queue_secondary(q))
+ handle_multi_queue_secondary_sched_done(guc, q, 0);
+ else
+ xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action),
+ G2H_LEN_DW_SCHED_CONTEXT_MODE_SET, 1);
}
static void __deregister_exec_queue(struct xe_guc *guc, struct xe_exec_queue *q)
@@ -1211,8 +1362,11 @@ static void __deregister_exec_queue(struct xe_guc *guc, struct xe_exec_queue *q)
set_exec_queue_destroyed(q);
trace_xe_exec_queue_deregister(q);
- xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action),
- G2H_LEN_DW_DEREGISTER_CONTEXT, 1);
+ if (xe_exec_queue_is_multi_queue_secondary(q))
+ handle_deregister_done(guc, q);
+ else
+ xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action),
+ G2H_LEN_DW_DEREGISTER_CONTEXT, 1);
}
static enum drm_gpu_sched_stat
@@ -1660,6 +1814,7 @@ static int guc_exec_queue_init(struct xe_exec_queue *q)
{
struct xe_gpu_scheduler *sched;
struct xe_guc *guc = exec_queue_to_guc(q);
+ struct workqueue_struct *submit_wq = NULL;
struct xe_guc_exec_queue *ge;
long timeout;
int err, i;
@@ -1680,8 +1835,20 @@ static int guc_exec_queue_init(struct xe_exec_queue *q)
timeout = (q->vm && xe_vm_in_lr_mode(q->vm)) ? MAX_SCHEDULE_TIMEOUT :
msecs_to_jiffies(q->sched_props.job_timeout_ms);
+
+ /*
+ * Use primary queue's submit_wq for all secondary queues of a
+ * multi queue group. This serialization avoids any locking around
+ * CGP synchronization with GuC.
+ */
+ if (xe_exec_queue_is_multi_queue_secondary(q)) {
+ struct xe_exec_queue *primary = xe_exec_queue_multi_queue_primary(q);
+
+ submit_wq = primary->guc->sched.base.submit_wq;
+ }
+
err = xe_sched_init(&ge->sched, &drm_sched_ops, &xe_sched_ops,
- NULL, xe_lrc_ring_size() / MAX_JOB_SIZE_BYTES, 64,
+ submit_wq, xe_lrc_ring_size() / MAX_JOB_SIZE_BYTES, 64,
timeout, guc_to_gt(guc)->ordered_wq, NULL,
q->name, gt_to_xe(q->gt)->drm.dev);
if (err)
@@ -2418,7 +2585,11 @@ static void deregister_exec_queue(struct xe_guc *guc, struct xe_exec_queue *q)
trace_xe_exec_queue_deregister(q);
- xe_guc_ct_send_g2h_handler(&guc->ct, action, ARRAY_SIZE(action));
+ if (xe_exec_queue_is_multi_queue_secondary(q))
+ handle_deregister_done(guc, q);
+ else
+ xe_guc_ct_send_g2h_handler(&guc->ct, action,
+ ARRAY_SIZE(action));
}
static void handle_sched_done(struct xe_guc *guc, struct xe_exec_queue *q,
@@ -2468,6 +2639,16 @@ static void handle_sched_done(struct xe_guc *guc, struct xe_exec_queue *q,
}
}
+static void handle_multi_queue_secondary_sched_done(struct xe_guc *guc,
+ struct xe_exec_queue *q,
+ u32 runnable_state)
+{
+ /* Take CT lock here as handle_sched_done() do send a h2g message */
+ mutex_lock(&guc->ct.lock);
+ handle_sched_done(guc, q, runnable_state);
+ mutex_unlock(&guc->ct.lock);
+}
+
int xe_guc_sched_done_handler(struct xe_guc *guc, u32 *msg, u32 len)
{
struct xe_exec_queue *q;
@@ -2672,6 +2853,44 @@ int xe_guc_exec_queue_reset_failure_handler(struct xe_guc *guc, u32 *msg, u32 le
return 0;
}
+/**
+ * xe_guc_exec_queue_cgp_sync_done_handler - CGP synchronization done handler
+ * @guc: guc
+ * @msg: message indicating CGP sync done
+ * @len: length of message
+ *
+ * Set multi queue group's sync_pending flag to false and wakeup anyone waiting
+ * for CGP synchronization to complete.
+ *
+ * Return: 0 on success, -EPROTO for malformed messages.
+ */
+int xe_guc_exec_queue_cgp_sync_done_handler(struct xe_guc *guc, u32 *msg, u32 len)
+{
+ struct xe_device *xe = guc_to_xe(guc);
+ struct xe_exec_queue *q;
+ u32 guc_id = msg[0];
+
+ if (unlikely(len < 1)) {
+ drm_err(&xe->drm, "Invalid CGP_SYNC_DONE length %u", len);
+ return -EPROTO;
+ }
+
+ q = g2h_exec_queue_lookup(guc, guc_id);
+ if (unlikely(!q))
+ return -EPROTO;
+
+ if (!xe_exec_queue_is_multi_queue_primary(q)) {
+ drm_err(&xe->drm, "Unexpected CGP_SYNC_DONE response");
+ return -EPROTO;
+ }
+
+ /* Wakeup the serialized cgp update wait */
+ WRITE_ONCE(q->multi_queue.group->sync_pending, false);
+ wake_up_all(&guc->ct.wq);
+
+ return 0;
+}
+
static void
guc_exec_queue_wq_snapshot_capture(struct xe_exec_queue *q,
struct xe_guc_submit_exec_queue_snapshot *snapshot)
diff --git a/drivers/gpu/drm/xe/xe_guc_submit.h b/drivers/gpu/drm/xe/xe_guc_submit.h
index b49a2748ec46..abfa94bce391 100644
--- a/drivers/gpu/drm/xe/xe_guc_submit.h
+++ b/drivers/gpu/drm/xe/xe_guc_submit.h
@@ -34,6 +34,7 @@ int xe_guc_exec_queue_memory_cat_error_handler(struct xe_guc *guc, u32 *msg,
u32 len);
int xe_guc_exec_queue_reset_failure_handler(struct xe_guc *guc, u32 *msg, u32 len);
int xe_guc_error_capture_handler(struct xe_guc *guc, u32 *msg, u32 len);
+int xe_guc_exec_queue_cgp_sync_done_handler(struct xe_guc *guc, u32 *msg, u32 len);
struct xe_guc_submit_exec_queue_snapshot *
xe_guc_exec_queue_snapshot_capture(struct xe_exec_queue *q);
--
2.43.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v2 04/16] drm/xe/multi_queue: Add multi queue priority property
2025-11-04 18:51 [PATCH v2 00/16] drm/xe: Multi Queue feature support Niranjana Vishwanathapura
` (2 preceding siblings ...)
2025-11-04 18:51 ` [PATCH v2 03/16] drm/xe/multi_queue: Add GuC " Niranjana Vishwanathapura
@ 2025-11-04 18:51 ` Niranjana Vishwanathapura
2025-11-04 22:58 ` Matthew Brost
2025-11-04 18:51 ` [PATCH v2 05/16] drm/xe/multi_queue: Handle invalid exec queue property setting Niranjana Vishwanathapura
` (15 subsequent siblings)
19 siblings, 1 reply; 27+ messages in thread
From: Niranjana Vishwanathapura @ 2025-11-04 18:51 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.brost
Add support for queues of a multi queue group to set
their priority within the queue group by adding property
DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY.
This is the only other property supported by secondary
queues of a multi queue group, other than
DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE.
v2: Add kernel doc for enum xe_multi_queue_priority,
Add assert for priority values, fix includes and
declarations (Matt Brost)
Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
---
drivers/gpu/drm/xe/xe_exec_queue.c | 17 +++++++++++++-
drivers/gpu/drm/xe/xe_exec_queue_types.h | 16 +++++++++++++
drivers/gpu/drm/xe/xe_guc_submit.c | 1 +
drivers/gpu/drm/xe/xe_lrc.c | 29 ++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_lrc.h | 3 +++
include/uapi/drm/xe_drm.h | 3 +++
6 files changed, 68 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
index 3a701fa477d7..7e9960ede0be 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue.c
+++ b/drivers/gpu/drm/xe/xe_exec_queue.c
@@ -179,6 +179,7 @@ static struct xe_exec_queue *__xe_exec_queue_alloc(struct xe_device *xe,
INIT_LIST_HEAD(&q->multi_gt_link);
INIT_LIST_HEAD(&q->hw_engine_group_link);
INIT_LIST_HEAD(&q->pxp.link);
+ q->multi_queue.priority = XE_MULTI_QUEUE_PRIORITY_NORMAL;
q->sched_props.timeslice_us = hwe->eclass->sched_props.timeslice_us;
q->sched_props.preempt_timeout_us =
@@ -737,6 +738,17 @@ static int exec_queue_set_multi_group(struct xe_device *xe, struct xe_exec_queue
return xe_exec_queue_group_validate(xe, q, value);
}
+static int exec_queue_set_multi_queue_priority(struct xe_device *xe, struct xe_exec_queue *q,
+ u64 value)
+{
+ if (XE_IOCTL_DBG(xe, value > XE_MULTI_QUEUE_PRIORITY_HIGH))
+ return -EINVAL;
+
+ q->multi_queue.priority = value;
+
+ return 0;
+}
+
typedef int (*xe_exec_queue_set_property_fn)(struct xe_device *xe,
struct xe_exec_queue *q,
u64 value);
@@ -746,6 +758,8 @@ static const xe_exec_queue_set_property_fn exec_queue_set_property_funcs[] = {
[DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE] = exec_queue_set_timeslice,
[DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE] = exec_queue_set_pxp_type,
[DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP] = exec_queue_set_multi_group,
+ [DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY] =
+ exec_queue_set_multi_queue_priority,
};
static int exec_queue_user_ext_set_property(struct xe_device *xe,
@@ -767,7 +781,8 @@ static int exec_queue_user_ext_set_property(struct xe_device *xe,
XE_IOCTL_DBG(xe, ext.property != DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY &&
ext.property != DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE &&
ext.property != DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE &&
- ext.property != DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP))
+ ext.property != DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP &&
+ ext.property != DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY))
return -EINVAL;
idx = array_index_nospec(ext.property, ARRAY_SIZE(exec_queue_set_property_funcs));
diff --git a/drivers/gpu/drm/xe/xe_exec_queue_types.h b/drivers/gpu/drm/xe/xe_exec_queue_types.h
index b9da51ab7eaf..445ae4979c0c 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue_types.h
+++ b/drivers/gpu/drm/xe/xe_exec_queue_types.h
@@ -32,6 +32,20 @@ enum xe_exec_queue_priority {
XE_EXEC_QUEUE_PRIORITY_COUNT
};
+/**
+ * enum xe_multi_queue_priority - Multi Queue priority values
+ *
+ * The priority values of the queues within the multi queue group.
+ */
+enum xe_multi_queue_priority {
+ /** @XE_MULTI_QUEUE_PRIORITY_LOW: Priority low */
+ XE_MULTI_QUEUE_PRIORITY_LOW = 0,
+ /** @XE_MULTI_QUEUE_PRIORITY_NORMAL: Priority normal */
+ XE_MULTI_QUEUE_PRIORITY_NORMAL,
+ /** @XE_MULTI_QUEUE_PRIORITY_HIGH: Priority high */
+ XE_MULTI_QUEUE_PRIORITY_HIGH,
+};
+
/**
* struct xe_exec_queue_group - Execution multi queue group
*
@@ -131,6 +145,8 @@ struct xe_exec_queue {
struct {
/** @multi_queue.group: Queue group information */
struct xe_exec_queue_group *group;
+ /** @multi_queue.priority: Queue priority within the multi-queue group */
+ enum xe_multi_queue_priority priority;
/** @multi_queue.pos: Position of queue within the multi-queue group */
u8 pos;
/** @multi_queue.valid: Queue belongs to a multi queue group */
diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
index 2e5106687a6e..b01d852ae526 100644
--- a/drivers/gpu/drm/xe/xe_guc_submit.c
+++ b/drivers/gpu/drm/xe/xe_guc_submit.c
@@ -634,6 +634,7 @@ static void xe_guc_exec_queue_group_cgp_sync(struct xe_guc *guc,
return;
}
+ xe_lrc_set_multi_queue_priority(q->lrc[0], q->multi_queue.priority);
xe_guc_exec_queue_group_cgp_update(xe, q);
WRITE_ONCE(group->sync_pending, true);
diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
index b5083c99dd50..56836a5546d8 100644
--- a/drivers/gpu/drm/xe/xe_lrc.c
+++ b/drivers/gpu/drm/xe/xe_lrc.c
@@ -44,6 +44,11 @@
#define LRC_INDIRECT_CTX_BO_SIZE SZ_4K
#define LRC_INDIRECT_RING_STATE_SIZE SZ_4K
+#define LRC_PRIORITY GENMASK_ULL(10, 9)
+#define LRC_PRIORITY_LOW 0
+#define LRC_PRIORITY_NORMAL 1
+#define LRC_PRIORITY_HIGH 2
+
/*
* Layout of the LRC and associated data allocated as
* lrc->bo:
@@ -1386,6 +1391,30 @@ setup_indirect_ctx(struct xe_lrc *lrc, struct xe_hw_engine *hwe)
return 0;
}
+static u8 xe_multi_queue_prio_to_lrc(struct xe_lrc *lrc, enum xe_multi_queue_priority priority)
+{
+ struct xe_device *xe = gt_to_xe(lrc->gt);
+
+ xe_assert(xe, (priority >= XE_MULTI_QUEUE_PRIORITY_LOW &&
+ priority <= XE_MULTI_QUEUE_PRIORITY_HIGH));
+
+ /* xe_multi_queue_priority is directly mapped to LRC priority values */
+ return priority;
+}
+
+/**
+ * xe_lrc_set_multi_queue_priority() - Set multi queue priority in LRC
+ * @lrc: Logical Ring Context
+ * @priority: Multi queue priority of the exec queue
+ *
+ * Convert @priority to LRC multi queue priority and update the @lrc descriptor
+ */
+void xe_lrc_set_multi_queue_priority(struct xe_lrc *lrc, enum xe_multi_queue_priority priority)
+{
+ lrc->desc &= ~LRC_PRIORITY;
+ lrc->desc |= FIELD_PREP(LRC_PRIORITY, xe_multi_queue_prio_to_lrc(lrc, priority));
+}
+
static int xe_lrc_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe,
struct xe_vm *vm, u32 ring_size, u16 msix_vec,
u32 init_flags)
diff --git a/drivers/gpu/drm/xe/xe_lrc.h b/drivers/gpu/drm/xe/xe_lrc.h
index 2fb628da5c43..569ca380676e 100644
--- a/drivers/gpu/drm/xe/xe_lrc.h
+++ b/drivers/gpu/drm/xe/xe_lrc.h
@@ -13,6 +13,7 @@ struct drm_printer;
struct xe_bb;
struct xe_device;
struct xe_exec_queue;
+enum xe_multi_queue_priority;
enum xe_engine_class;
struct xe_gt;
struct xe_hw_engine;
@@ -133,6 +134,8 @@ void xe_lrc_dump_default(struct drm_printer *p,
u32 *xe_lrc_emit_hwe_state_instructions(struct xe_exec_queue *q, u32 *cs);
+void xe_lrc_set_multi_queue_priority(struct xe_lrc *lrc, enum xe_multi_queue_priority priority);
+
struct xe_lrc_snapshot *xe_lrc_snapshot_capture(struct xe_lrc *lrc);
void xe_lrc_snapshot_capture_delayed(struct xe_lrc_snapshot *snapshot);
void xe_lrc_snapshot_print(struct xe_lrc_snapshot *snapshot, struct drm_printer *p);
diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
index 4de21e0a4fcf..6734ef7fada1 100644
--- a/include/uapi/drm/xe_drm.h
+++ b/include/uapi/drm/xe_drm.h
@@ -1260,6 +1260,8 @@ struct drm_xe_vm_bind {
* queue's exec_queue_id is specified in the lower 32 bits of the 'value' field.
* All the other non-relevant bits of extension's 'value' field while adding the
* primary or the secondary queues of the group must be set to 0.
+ * - %DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY - Set the queue
+ * priority within the multi-queue group.
*
* The example below shows how to use @drm_xe_exec_queue_create to create
* a simple exec_queue (no parallel submission) of class
@@ -1302,6 +1304,7 @@ struct drm_xe_exec_queue_create {
#define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE 2
#define DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP 3
#define DRM_XE_MULTI_GROUP_CREATE (1ull << 63)
+#define DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY 4
/** @extensions: Pointer to the first extension struct, if any */
__u64 extensions;
--
2.43.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH v2 04/16] drm/xe/multi_queue: Add multi queue priority property
2025-11-04 18:51 ` [PATCH v2 04/16] drm/xe/multi_queue: Add multi queue priority property Niranjana Vishwanathapura
@ 2025-11-04 22:58 ` Matthew Brost
2025-11-04 23:53 ` Niranjana Vishwanathapura
0 siblings, 1 reply; 27+ messages in thread
From: Matthew Brost @ 2025-11-04 22:58 UTC (permalink / raw)
To: Niranjana Vishwanathapura; +Cc: intel-xe
On Tue, Nov 04, 2025 at 10:51:38AM -0800, Niranjana Vishwanathapura wrote:
> Add support for queues of a multi queue group to set
> their priority within the queue group by adding property
> DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY.
> This is the only other property supported by secondary
> queues of a multi queue group, other than
> DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE.
>
> v2: Add kernel doc for enum xe_multi_queue_priority,
> Add assert for priority values, fix includes and
> declarations (Matt Brost)
>
> Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
> ---
> drivers/gpu/drm/xe/xe_exec_queue.c | 17 +++++++++++++-
> drivers/gpu/drm/xe/xe_exec_queue_types.h | 16 +++++++++++++
> drivers/gpu/drm/xe/xe_guc_submit.c | 1 +
> drivers/gpu/drm/xe/xe_lrc.c | 29 ++++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_lrc.h | 3 +++
> include/uapi/drm/xe_drm.h | 3 +++
> 6 files changed, 68 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
> index 3a701fa477d7..7e9960ede0be 100644
> --- a/drivers/gpu/drm/xe/xe_exec_queue.c
> +++ b/drivers/gpu/drm/xe/xe_exec_queue.c
> @@ -179,6 +179,7 @@ static struct xe_exec_queue *__xe_exec_queue_alloc(struct xe_device *xe,
> INIT_LIST_HEAD(&q->multi_gt_link);
> INIT_LIST_HEAD(&q->hw_engine_group_link);
> INIT_LIST_HEAD(&q->pxp.link);
> + q->multi_queue.priority = XE_MULTI_QUEUE_PRIORITY_NORMAL;
>
> q->sched_props.timeslice_us = hwe->eclass->sched_props.timeslice_us;
> q->sched_props.preempt_timeout_us =
> @@ -737,6 +738,17 @@ static int exec_queue_set_multi_group(struct xe_device *xe, struct xe_exec_queue
> return xe_exec_queue_group_validate(xe, q, value);
> }
>
> +static int exec_queue_set_multi_queue_priority(struct xe_device *xe, struct xe_exec_queue *q,
> + u64 value)
> +{
> + if (XE_IOCTL_DBG(xe, value > XE_MULTI_QUEUE_PRIORITY_HIGH))
> + return -EINVAL;
> +
> + q->multi_queue.priority = value;
> +
> + return 0;
> +}
> +
> typedef int (*xe_exec_queue_set_property_fn)(struct xe_device *xe,
> struct xe_exec_queue *q,
> u64 value);
> @@ -746,6 +758,8 @@ static const xe_exec_queue_set_property_fn exec_queue_set_property_funcs[] = {
> [DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE] = exec_queue_set_timeslice,
> [DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE] = exec_queue_set_pxp_type,
> [DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP] = exec_queue_set_multi_group,
> + [DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY] =
> + exec_queue_set_multi_queue_priority,
> };
>
> static int exec_queue_user_ext_set_property(struct xe_device *xe,
> @@ -767,7 +781,8 @@ static int exec_queue_user_ext_set_property(struct xe_device *xe,
> XE_IOCTL_DBG(xe, ext.property != DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY &&
> ext.property != DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE &&
> ext.property != DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE &&
> - ext.property != DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP))
> + ext.property != DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP &&
> + ext.property != DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY))
> return -EINVAL;
>
> idx = array_index_nospec(ext.property, ARRAY_SIZE(exec_queue_set_property_funcs));
> diff --git a/drivers/gpu/drm/xe/xe_exec_queue_types.h b/drivers/gpu/drm/xe/xe_exec_queue_types.h
> index b9da51ab7eaf..445ae4979c0c 100644
> --- a/drivers/gpu/drm/xe/xe_exec_queue_types.h
> +++ b/drivers/gpu/drm/xe/xe_exec_queue_types.h
> @@ -32,6 +32,20 @@ enum xe_exec_queue_priority {
> XE_EXEC_QUEUE_PRIORITY_COUNT
> };
>
> +/**
> + * enum xe_multi_queue_priority - Multi Queue priority values
> + *
> + * The priority values of the queues within the multi queue group.
> + */
> +enum xe_multi_queue_priority {
> + /** @XE_MULTI_QUEUE_PRIORITY_LOW: Priority low */
> + XE_MULTI_QUEUE_PRIORITY_LOW = 0,
> + /** @XE_MULTI_QUEUE_PRIORITY_NORMAL: Priority normal */
> + XE_MULTI_QUEUE_PRIORITY_NORMAL,
> + /** @XE_MULTI_QUEUE_PRIORITY_HIGH: Priority high */
> + XE_MULTI_QUEUE_PRIORITY_HIGH,
> +};
> +
> /**
> * struct xe_exec_queue_group - Execution multi queue group
> *
> @@ -131,6 +145,8 @@ struct xe_exec_queue {
> struct {
> /** @multi_queue.group: Queue group information */
> struct xe_exec_queue_group *group;
> + /** @multi_queue.priority: Queue priority within the multi-queue group */
> + enum xe_multi_queue_priority priority;
> /** @multi_queue.pos: Position of queue within the multi-queue group */
> u8 pos;
> /** @multi_queue.valid: Queue belongs to a multi queue group */
> diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
> index 2e5106687a6e..b01d852ae526 100644
> --- a/drivers/gpu/drm/xe/xe_guc_submit.c
> +++ b/drivers/gpu/drm/xe/xe_guc_submit.c
> @@ -634,6 +634,7 @@ static void xe_guc_exec_queue_group_cgp_sync(struct xe_guc *guc,
> return;
> }
>
> + xe_lrc_set_multi_queue_priority(q->lrc[0], q->multi_queue.priority);
> xe_guc_exec_queue_group_cgp_update(xe, q);
>
> WRITE_ONCE(group->sync_pending, true);
> diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
> index b5083c99dd50..56836a5546d8 100644
> --- a/drivers/gpu/drm/xe/xe_lrc.c
> +++ b/drivers/gpu/drm/xe/xe_lrc.c
> @@ -44,6 +44,11 @@
> #define LRC_INDIRECT_CTX_BO_SIZE SZ_4K
> #define LRC_INDIRECT_RING_STATE_SIZE SZ_4K
>
> +#define LRC_PRIORITY GENMASK_ULL(10, 9)
> +#define LRC_PRIORITY_LOW 0
> +#define LRC_PRIORITY_NORMAL 1
> +#define LRC_PRIORITY_HIGH 2
> +
> /*
> * Layout of the LRC and associated data allocated as
> * lrc->bo:
> @@ -1386,6 +1391,30 @@ setup_indirect_ctx(struct xe_lrc *lrc, struct xe_hw_engine *hwe)
> return 0;
> }
>
> +static u8 xe_multi_queue_prio_to_lrc(struct xe_lrc *lrc, enum xe_multi_queue_priority priority)
> +{
> + struct xe_device *xe = gt_to_xe(lrc->gt);
> +
> + xe_assert(xe, (priority >= XE_MULTI_QUEUE_PRIORITY_LOW &&
> + priority <= XE_MULTI_QUEUE_PRIORITY_HIGH));
> +
> + /* xe_multi_queue_priority is directly mapped to LRC priority values */
> + return priority;
> +}
> +
> +/**
> + * xe_lrc_set_multi_queue_priority() - Set multi queue priority in LRC
> + * @lrc: Logical Ring Context
> + * @priority: Multi queue priority of the exec queue
> + *
> + * Convert @priority to LRC multi queue priority and update the @lrc descriptor
> + */
> +void xe_lrc_set_multi_queue_priority(struct xe_lrc *lrc, enum xe_multi_queue_priority priority)
> +{
> + lrc->desc &= ~LRC_PRIORITY;
> + lrc->desc |= FIELD_PREP(LRC_PRIORITY, xe_multi_queue_prio_to_lrc(lrc, priority));
> +}
> +
> static int xe_lrc_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe,
> struct xe_vm *vm, u32 ring_size, u16 msix_vec,
> u32 init_flags)
> diff --git a/drivers/gpu/drm/xe/xe_lrc.h b/drivers/gpu/drm/xe/xe_lrc.h
> index 2fb628da5c43..569ca380676e 100644
> --- a/drivers/gpu/drm/xe/xe_lrc.h
> +++ b/drivers/gpu/drm/xe/xe_lrc.h
> @@ -13,6 +13,7 @@ struct drm_printer;
> struct xe_bb;
> struct xe_device;
> struct xe_exec_queue;
> +enum xe_multi_queue_priority;
> enum xe_engine_class;
> struct xe_gt;
> struct xe_hw_engine;
> @@ -133,6 +134,8 @@ void xe_lrc_dump_default(struct drm_printer *p,
>
> u32 *xe_lrc_emit_hwe_state_instructions(struct xe_exec_queue *q, u32 *cs);
>
> +void xe_lrc_set_multi_queue_priority(struct xe_lrc *lrc, enum xe_multi_queue_priority priority);
> +
> struct xe_lrc_snapshot *xe_lrc_snapshot_capture(struct xe_lrc *lrc);
> void xe_lrc_snapshot_capture_delayed(struct xe_lrc_snapshot *snapshot);
> void xe_lrc_snapshot_print(struct xe_lrc_snapshot *snapshot, struct drm_printer *p);
> diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
> index 4de21e0a4fcf..6734ef7fada1 100644
> --- a/include/uapi/drm/xe_drm.h
> +++ b/include/uapi/drm/xe_drm.h
> @@ -1260,6 +1260,8 @@ struct drm_xe_vm_bind {
> * queue's exec_queue_id is specified in the lower 32 bits of the 'value' field.
> * All the other non-relevant bits of extension's 'value' field while adding the
> * primary or the secondary queues of the group must be set to 0.
> + * - %DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY - Set the queue
> + * priority within the multi-queue group.
'Current valid priority values are 0–2 (default is 1), with higher
values indicating higher priority.' ?
Do we have any concerns about exposing XE_MULTI_QUEUE_PRIORITY_HIGH to
non-elevated privileged users? For example, could this allow a user
process to cause a denial of service by locking out others? This is why
we restrict normal privileged users from setting
DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY to the highest level.
For DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY, we have the query
DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY, which indicates the maximum
queue priority level. Do we need a similar mechanism for multi-queue
priority?
Matt
> *
> * The example below shows how to use @drm_xe_exec_queue_create to create
> * a simple exec_queue (no parallel submission) of class
> @@ -1302,6 +1304,7 @@ struct drm_xe_exec_queue_create {
> #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE 2
> #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP 3
> #define DRM_XE_MULTI_GROUP_CREATE (1ull << 63)
> +#define DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY 4
> /** @extensions: Pointer to the first extension struct, if any */
> __u64 extensions;
>
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH v2 04/16] drm/xe/multi_queue: Add multi queue priority property
2025-11-04 22:58 ` Matthew Brost
@ 2025-11-04 23:53 ` Niranjana Vishwanathapura
0 siblings, 0 replies; 27+ messages in thread
From: Niranjana Vishwanathapura @ 2025-11-04 23:53 UTC (permalink / raw)
To: Matthew Brost; +Cc: intel-xe
On Tue, Nov 04, 2025 at 02:58:00PM -0800, Matthew Brost wrote:
>On Tue, Nov 04, 2025 at 10:51:38AM -0800, Niranjana Vishwanathapura wrote:
>> Add support for queues of a multi queue group to set
>> their priority within the queue group by adding property
>> DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY.
>> This is the only other property supported by secondary
>> queues of a multi queue group, other than
>> DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE.
>>
>> v2: Add kernel doc for enum xe_multi_queue_priority,
>> Add assert for priority values, fix includes and
>> declarations (Matt Brost)
>>
>> Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
>> ---
>> drivers/gpu/drm/xe/xe_exec_queue.c | 17 +++++++++++++-
>> drivers/gpu/drm/xe/xe_exec_queue_types.h | 16 +++++++++++++
>> drivers/gpu/drm/xe/xe_guc_submit.c | 1 +
>> drivers/gpu/drm/xe/xe_lrc.c | 29 ++++++++++++++++++++++++
>> drivers/gpu/drm/xe/xe_lrc.h | 3 +++
>> include/uapi/drm/xe_drm.h | 3 +++
>> 6 files changed, 68 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
>> index 3a701fa477d7..7e9960ede0be 100644
>> --- a/drivers/gpu/drm/xe/xe_exec_queue.c
>> +++ b/drivers/gpu/drm/xe/xe_exec_queue.c
>> @@ -179,6 +179,7 @@ static struct xe_exec_queue *__xe_exec_queue_alloc(struct xe_device *xe,
>> INIT_LIST_HEAD(&q->multi_gt_link);
>> INIT_LIST_HEAD(&q->hw_engine_group_link);
>> INIT_LIST_HEAD(&q->pxp.link);
>> + q->multi_queue.priority = XE_MULTI_QUEUE_PRIORITY_NORMAL;
>>
>> q->sched_props.timeslice_us = hwe->eclass->sched_props.timeslice_us;
>> q->sched_props.preempt_timeout_us =
>> @@ -737,6 +738,17 @@ static int exec_queue_set_multi_group(struct xe_device *xe, struct xe_exec_queue
>> return xe_exec_queue_group_validate(xe, q, value);
>> }
>>
>> +static int exec_queue_set_multi_queue_priority(struct xe_device *xe, struct xe_exec_queue *q,
>> + u64 value)
>> +{
>> + if (XE_IOCTL_DBG(xe, value > XE_MULTI_QUEUE_PRIORITY_HIGH))
>> + return -EINVAL;
>> +
>> + q->multi_queue.priority = value;
>> +
>> + return 0;
>> +}
>> +
>> typedef int (*xe_exec_queue_set_property_fn)(struct xe_device *xe,
>> struct xe_exec_queue *q,
>> u64 value);
>> @@ -746,6 +758,8 @@ static const xe_exec_queue_set_property_fn exec_queue_set_property_funcs[] = {
>> [DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE] = exec_queue_set_timeslice,
>> [DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE] = exec_queue_set_pxp_type,
>> [DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP] = exec_queue_set_multi_group,
>> + [DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY] =
>> + exec_queue_set_multi_queue_priority,
>> };
>>
>> static int exec_queue_user_ext_set_property(struct xe_device *xe,
>> @@ -767,7 +781,8 @@ static int exec_queue_user_ext_set_property(struct xe_device *xe,
>> XE_IOCTL_DBG(xe, ext.property != DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY &&
>> ext.property != DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE &&
>> ext.property != DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE &&
>> - ext.property != DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP))
>> + ext.property != DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP &&
>> + ext.property != DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY))
>> return -EINVAL;
>>
>> idx = array_index_nospec(ext.property, ARRAY_SIZE(exec_queue_set_property_funcs));
>> diff --git a/drivers/gpu/drm/xe/xe_exec_queue_types.h b/drivers/gpu/drm/xe/xe_exec_queue_types.h
>> index b9da51ab7eaf..445ae4979c0c 100644
>> --- a/drivers/gpu/drm/xe/xe_exec_queue_types.h
>> +++ b/drivers/gpu/drm/xe/xe_exec_queue_types.h
>> @@ -32,6 +32,20 @@ enum xe_exec_queue_priority {
>> XE_EXEC_QUEUE_PRIORITY_COUNT
>> };
>>
>> +/**
>> + * enum xe_multi_queue_priority - Multi Queue priority values
>> + *
>> + * The priority values of the queues within the multi queue group.
>> + */
>> +enum xe_multi_queue_priority {
>> + /** @XE_MULTI_QUEUE_PRIORITY_LOW: Priority low */
>> + XE_MULTI_QUEUE_PRIORITY_LOW = 0,
>> + /** @XE_MULTI_QUEUE_PRIORITY_NORMAL: Priority normal */
>> + XE_MULTI_QUEUE_PRIORITY_NORMAL,
>> + /** @XE_MULTI_QUEUE_PRIORITY_HIGH: Priority high */
>> + XE_MULTI_QUEUE_PRIORITY_HIGH,
>> +};
>> +
>> /**
>> * struct xe_exec_queue_group - Execution multi queue group
>> *
>> @@ -131,6 +145,8 @@ struct xe_exec_queue {
>> struct {
>> /** @multi_queue.group: Queue group information */
>> struct xe_exec_queue_group *group;
>> + /** @multi_queue.priority: Queue priority within the multi-queue group */
>> + enum xe_multi_queue_priority priority;
>> /** @multi_queue.pos: Position of queue within the multi-queue group */
>> u8 pos;
>> /** @multi_queue.valid: Queue belongs to a multi queue group */
>> diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
>> index 2e5106687a6e..b01d852ae526 100644
>> --- a/drivers/gpu/drm/xe/xe_guc_submit.c
>> +++ b/drivers/gpu/drm/xe/xe_guc_submit.c
>> @@ -634,6 +634,7 @@ static void xe_guc_exec_queue_group_cgp_sync(struct xe_guc *guc,
>> return;
>> }
>>
>> + xe_lrc_set_multi_queue_priority(q->lrc[0], q->multi_queue.priority);
>> xe_guc_exec_queue_group_cgp_update(xe, q);
>>
>> WRITE_ONCE(group->sync_pending, true);
>> diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
>> index b5083c99dd50..56836a5546d8 100644
>> --- a/drivers/gpu/drm/xe/xe_lrc.c
>> +++ b/drivers/gpu/drm/xe/xe_lrc.c
>> @@ -44,6 +44,11 @@
>> #define LRC_INDIRECT_CTX_BO_SIZE SZ_4K
>> #define LRC_INDIRECT_RING_STATE_SIZE SZ_4K
>>
>> +#define LRC_PRIORITY GENMASK_ULL(10, 9)
>> +#define LRC_PRIORITY_LOW 0
>> +#define LRC_PRIORITY_NORMAL 1
>> +#define LRC_PRIORITY_HIGH 2
>> +
>> /*
>> * Layout of the LRC and associated data allocated as
>> * lrc->bo:
>> @@ -1386,6 +1391,30 @@ setup_indirect_ctx(struct xe_lrc *lrc, struct xe_hw_engine *hwe)
>> return 0;
>> }
>>
>> +static u8 xe_multi_queue_prio_to_lrc(struct xe_lrc *lrc, enum xe_multi_queue_priority priority)
>> +{
>> + struct xe_device *xe = gt_to_xe(lrc->gt);
>> +
>> + xe_assert(xe, (priority >= XE_MULTI_QUEUE_PRIORITY_LOW &&
>> + priority <= XE_MULTI_QUEUE_PRIORITY_HIGH));
>> +
>> + /* xe_multi_queue_priority is directly mapped to LRC priority values */
>> + return priority;
>> +}
>> +
>> +/**
>> + * xe_lrc_set_multi_queue_priority() - Set multi queue priority in LRC
>> + * @lrc: Logical Ring Context
>> + * @priority: Multi queue priority of the exec queue
>> + *
>> + * Convert @priority to LRC multi queue priority and update the @lrc descriptor
>> + */
>> +void xe_lrc_set_multi_queue_priority(struct xe_lrc *lrc, enum xe_multi_queue_priority priority)
>> +{
>> + lrc->desc &= ~LRC_PRIORITY;
>> + lrc->desc |= FIELD_PREP(LRC_PRIORITY, xe_multi_queue_prio_to_lrc(lrc, priority));
>> +}
>> +
>> static int xe_lrc_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe,
>> struct xe_vm *vm, u32 ring_size, u16 msix_vec,
>> u32 init_flags)
>> diff --git a/drivers/gpu/drm/xe/xe_lrc.h b/drivers/gpu/drm/xe/xe_lrc.h
>> index 2fb628da5c43..569ca380676e 100644
>> --- a/drivers/gpu/drm/xe/xe_lrc.h
>> +++ b/drivers/gpu/drm/xe/xe_lrc.h
>> @@ -13,6 +13,7 @@ struct drm_printer;
>> struct xe_bb;
>> struct xe_device;
>> struct xe_exec_queue;
>> +enum xe_multi_queue_priority;
>> enum xe_engine_class;
>> struct xe_gt;
>> struct xe_hw_engine;
>> @@ -133,6 +134,8 @@ void xe_lrc_dump_default(struct drm_printer *p,
>>
>> u32 *xe_lrc_emit_hwe_state_instructions(struct xe_exec_queue *q, u32 *cs);
>>
>> +void xe_lrc_set_multi_queue_priority(struct xe_lrc *lrc, enum xe_multi_queue_priority priority);
>> +
>> struct xe_lrc_snapshot *xe_lrc_snapshot_capture(struct xe_lrc *lrc);
>> void xe_lrc_snapshot_capture_delayed(struct xe_lrc_snapshot *snapshot);
>> void xe_lrc_snapshot_print(struct xe_lrc_snapshot *snapshot, struct drm_printer *p);
>> diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
>> index 4de21e0a4fcf..6734ef7fada1 100644
>> --- a/include/uapi/drm/xe_drm.h
>> +++ b/include/uapi/drm/xe_drm.h
>> @@ -1260,6 +1260,8 @@ struct drm_xe_vm_bind {
>> * queue's exec_queue_id is specified in the lower 32 bits of the 'value' field.
>> * All the other non-relevant bits of extension's 'value' field while adding the
>> * primary or the secondary queues of the group must be set to 0.
>> + * - %DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY - Set the queue
>> + * priority within the multi-queue group.
>
>'Current valid priority values are 0–2 (default is 1), with higher
>values indicating higher priority.' ?
>
Ok, will add.
>Do we have any concerns about exposing XE_MULTI_QUEUE_PRIORITY_HIGH to
>non-elevated privileged users? For example, could this allow a user
>process to cause a denial of service by locking out others? This is why
>we restrict normal privileged users from setting
>DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY to the highest level.
>
No. Unlike the queue priority, in the multi-queue priority case,
the PRIORITY_HIGH is available to the user with normal privilege also.
>For DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY, we have the query
>DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY, which indicates the maximum
>queue priority level. Do we need a similar mechanism for multi-queue
>priority?
>
There was some discussion with compute team on this, but no decision
yet. If needed, we can add it later.
Niranjana
>Matt
>
>> *
>> * The example below shows how to use @drm_xe_exec_queue_create to create
>> * a simple exec_queue (no parallel submission) of class
>> @@ -1302,6 +1304,7 @@ struct drm_xe_exec_queue_create {
>> #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE 2
>> #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP 3
>> #define DRM_XE_MULTI_GROUP_CREATE (1ull << 63)
>> +#define DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY 4
>> /** @extensions: Pointer to the first extension struct, if any */
>> __u64 extensions;
>>
>> --
>> 2.43.0
>>
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v2 05/16] drm/xe/multi_queue: Handle invalid exec queue property setting
2025-11-04 18:51 [PATCH v2 00/16] drm/xe: Multi Queue feature support Niranjana Vishwanathapura
` (3 preceding siblings ...)
2025-11-04 18:51 ` [PATCH v2 04/16] drm/xe/multi_queue: Add multi queue priority property Niranjana Vishwanathapura
@ 2025-11-04 18:51 ` Niranjana Vishwanathapura
2025-11-04 18:51 ` [PATCH v2 06/16] drm/xe/multi_queue: Add exec_queue set_property ioctl support Niranjana Vishwanathapura
` (14 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Niranjana Vishwanathapura @ 2025-11-04 18:51 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.brost
Only MULTI_QUEUE_PRIORITY property is valid for secondary queues of a
multi queue group. MULTI_QUEUE_PRIORITY only applies to multi queue group
queues. Detect invalid user queue property setting and return error.
Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
---
drivers/gpu/drm/xe/xe_exec_queue.c | 66 ++++++++++++++++++++++++++----
1 file changed, 57 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
index 7e9960ede0be..d36d018d7ba0 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue.c
+++ b/drivers/gpu/drm/xe/xe_exec_queue.c
@@ -62,7 +62,7 @@ enum xe_exec_queue_sched_prop {
};
static int exec_queue_user_extensions(struct xe_device *xe, struct xe_exec_queue *q,
- u64 extensions, int ext_number);
+ u64 extensions);
static void xe_exec_queue_group_cleanup(struct xe_exec_queue *q)
{
@@ -208,7 +208,7 @@ static struct xe_exec_queue *__xe_exec_queue_alloc(struct xe_device *xe,
* may set q->usm, must come before xe_lrc_create(),
* may overwrite q->sched_props, must come before q->ops->init()
*/
- err = exec_queue_user_extensions(xe, q, extensions, 0);
+ err = exec_queue_user_extensions(xe, q, extensions);
if (err) {
__xe_exec_queue_free(q);
return ERR_PTR(err);
@@ -762,9 +762,35 @@ static const xe_exec_queue_set_property_fn exec_queue_set_property_funcs[] = {
exec_queue_set_multi_queue_priority,
};
+static int exec_queue_user_ext_check(struct xe_exec_queue *q, u64 properties)
+{
+ u64 secondary_queue_valid_props = BIT_ULL(DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP) |
+ BIT_ULL(DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY);
+
+ /*
+ * Only MULTI_QUEUE_PRIORITY property is valid for secondary queues of a
+ * multi-queue group.
+ */
+ if (xe_exec_queue_is_multi_queue_secondary(q) &&
+ properties & ~secondary_queue_valid_props)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int exec_queue_user_ext_check_final(struct xe_exec_queue *q, u64 properties)
+{
+ /* MULTI_QUEUE_PRIORITY only applies to multi-queue group queues */
+ if ((properties & BIT_ULL(DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY)) &&
+ !(properties & BIT_ULL(DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP)))
+ return -EINVAL;
+
+ return 0;
+}
+
static int exec_queue_user_ext_set_property(struct xe_device *xe,
struct xe_exec_queue *q,
- u64 extension)
+ u64 extension, u64 *properties)
{
u64 __user *address = u64_to_user_ptr(extension);
struct drm_xe_ext_set_property ext;
@@ -789,20 +815,25 @@ static int exec_queue_user_ext_set_property(struct xe_device *xe,
if (!exec_queue_set_property_funcs[idx])
return -EINVAL;
+ *properties |= BIT_ULL(idx);
+ err = exec_queue_user_ext_check(q, *properties);
+ if (XE_IOCTL_DBG(xe, err))
+ return err;
+
return exec_queue_set_property_funcs[idx](xe, q, ext.value);
}
typedef int (*xe_exec_queue_user_extension_fn)(struct xe_device *xe,
struct xe_exec_queue *q,
- u64 extension);
+ u64 extension, u64 *properties);
static const xe_exec_queue_user_extension_fn exec_queue_user_extension_funcs[] = {
[DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY] = exec_queue_user_ext_set_property,
};
#define MAX_USER_EXTENSIONS 16
-static int exec_queue_user_extensions(struct xe_device *xe, struct xe_exec_queue *q,
- u64 extensions, int ext_number)
+static int __exec_queue_user_extensions(struct xe_device *xe, struct xe_exec_queue *q,
+ u64 extensions, int ext_number, u64 *properties)
{
u64 __user *address = u64_to_user_ptr(extensions);
struct drm_xe_user_extension ext;
@@ -823,13 +854,30 @@ static int exec_queue_user_extensions(struct xe_device *xe, struct xe_exec_queue
idx = array_index_nospec(ext.name,
ARRAY_SIZE(exec_queue_user_extension_funcs));
- err = exec_queue_user_extension_funcs[idx](xe, q, extensions);
+ err = exec_queue_user_extension_funcs[idx](xe, q, extensions, properties);
if (XE_IOCTL_DBG(xe, err))
return err;
if (ext.next_extension)
- return exec_queue_user_extensions(xe, q, ext.next_extension,
- ++ext_number);
+ return __exec_queue_user_extensions(xe, q, ext.next_extension,
+ ++ext_number, properties);
+
+ return 0;
+}
+
+static int exec_queue_user_extensions(struct xe_device *xe, struct xe_exec_queue *q,
+ u64 extensions)
+{
+ u64 properties = 0;
+ int err;
+
+ err = __exec_queue_user_extensions(xe, q, extensions, 0, &properties);
+ if (XE_IOCTL_DBG(xe, err))
+ return err;
+
+ err = exec_queue_user_ext_check_final(q, properties);
+ if (XE_IOCTL_DBG(xe, err))
+ return err;
if (xe_exec_queue_is_multi_queue_primary(q)) {
err = xe_exec_queue_group_init(xe, q);
--
2.43.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v2 06/16] drm/xe/multi_queue: Add exec_queue set_property ioctl support
2025-11-04 18:51 [PATCH v2 00/16] drm/xe: Multi Queue feature support Niranjana Vishwanathapura
` (4 preceding siblings ...)
2025-11-04 18:51 ` [PATCH v2 05/16] drm/xe/multi_queue: Handle invalid exec queue property setting Niranjana Vishwanathapura
@ 2025-11-04 18:51 ` Niranjana Vishwanathapura
2025-11-04 22:48 ` Matthew Brost
2025-11-04 18:51 ` [PATCH v2 07/16] drm/xe/multi_queue: Add support for multi queue dynamic priority change Niranjana Vishwanathapura
` (13 subsequent siblings)
19 siblings, 1 reply; 27+ messages in thread
From: Niranjana Vishwanathapura @ 2025-11-04 18:51 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.brost
This patch adds support for exec_queue set_property ioctl.
It is derived from the original work which is part of
https://patchwork.freedesktop.org/series/112188/
Currently only DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY
property can be dynamically set.
v2: Check for and update kernel-doc which property this ioctl
supports (Matt Brost)
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Pallavi Mishra <pallavi.mishra@intel.com>
Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
---
drivers/gpu/drm/xe/xe_device.c | 2 ++
drivers/gpu/drm/xe/xe_exec_queue.c | 35 ++++++++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_exec_queue.h | 2 ++
include/uapi/drm/xe_drm.h | 26 ++++++++++++++++++++++
4 files changed, 65 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index 9f2f19dc1fd3..391b2f9a2846 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -209,6 +209,8 @@ static const struct drm_ioctl_desc xe_ioctls[] = {
DRM_IOCTL_DEF_DRV(XE_MADVISE, xe_vm_madvise_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(XE_VM_QUERY_MEM_RANGE_ATTRS, xe_vm_query_vmas_attrs_ioctl,
DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(XE_EXEC_QUEUE_SET_PROPERTY, xe_exec_queue_set_property_ioctl,
+ DRM_RENDER_ALLOW),
};
static long xe_drm_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
index d36d018d7ba0..c96cc085e8e8 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue.c
+++ b/drivers/gpu/drm/xe/xe_exec_queue.c
@@ -762,6 +762,41 @@ static const xe_exec_queue_set_property_fn exec_queue_set_property_funcs[] = {
exec_queue_set_multi_queue_priority,
};
+int xe_exec_queue_set_property_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file)
+{
+ struct xe_device *xe = to_xe_device(dev);
+ struct xe_file *xef = to_xe_file(file);
+ struct drm_xe_exec_queue_set_property *args = data;
+ struct xe_exec_queue *q;
+ int ret;
+ u32 idx;
+
+ if (XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1]))
+ return -EINVAL;
+
+ if (XE_IOCTL_DBG(xe, args->property !=
+ DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY))
+ return -EINVAL;
+
+ q = xe_exec_queue_lookup(xef, args->exec_queue_id);
+ if (XE_IOCTL_DBG(xe, !q))
+ return -ENOENT;
+
+ idx = array_index_nospec(args->property,
+ ARRAY_SIZE(exec_queue_set_property_funcs));
+ ret = exec_queue_set_property_funcs[idx](xe, q, args->value);
+ if (XE_IOCTL_DBG(xe, ret))
+ goto err_post_lookup;
+
+ xe_exec_queue_put(q);
+ return 0;
+
+ err_post_lookup:
+ xe_exec_queue_put(q);
+ return ret;
+}
+
static int exec_queue_user_ext_check(struct xe_exec_queue *q, u64 properties)
{
u64 secondary_queue_valid_props = BIT_ULL(DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP) |
diff --git a/drivers/gpu/drm/xe/xe_exec_queue.h b/drivers/gpu/drm/xe/xe_exec_queue.h
index e6daa40003f2..ffcc1feb879e 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue.h
+++ b/drivers/gpu/drm/xe/xe_exec_queue.h
@@ -125,6 +125,8 @@ int xe_exec_queue_destroy_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
int xe_exec_queue_get_property_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
+int xe_exec_queue_set_property_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file);
enum xe_exec_queue_priority xe_exec_queue_device_get_max_priority(struct xe_device *xe);
void xe_exec_queue_last_fence_put(struct xe_exec_queue *e, struct xe_vm *vm);
diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
index 6734ef7fada1..d5162a3a89db 100644
--- a/include/uapi/drm/xe_drm.h
+++ b/include/uapi/drm/xe_drm.h
@@ -106,6 +106,7 @@ extern "C" {
#define DRM_XE_OBSERVATION 0x0b
#define DRM_XE_MADVISE 0x0c
#define DRM_XE_VM_QUERY_MEM_RANGE_ATTRS 0x0d
+#define DRM_XE_EXEC_QUEUE_SET_PROPERTY 0x0e
/* Must be kept compact -- no holes */
@@ -123,6 +124,7 @@ extern "C" {
#define DRM_IOCTL_XE_OBSERVATION DRM_IOW(DRM_COMMAND_BASE + DRM_XE_OBSERVATION, struct drm_xe_observation_param)
#define DRM_IOCTL_XE_MADVISE DRM_IOW(DRM_COMMAND_BASE + DRM_XE_MADVISE, struct drm_xe_madvise)
#define DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_QUERY_MEM_RANGE_ATTRS, struct drm_xe_vm_query_mem_range_attr)
+#define DRM_IOCTL_XE_EXEC_QUEUE_SET_PROPERTY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_SET_PROPERTY, struct drm_xe_exec_queue_set_property)
/**
* DOC: Xe IOCTL Extensions
@@ -2286,6 +2288,30 @@ struct drm_xe_vm_query_mem_range_attr {
};
+/**
+ * struct drm_xe_exec_queue_set_property - exec queue set property
+ *
+ * Sets execution queue properties dynamically.
+ * Currently only %DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY
+ * property can be dynamically set.
+ */
+struct drm_xe_exec_queue_set_property {
+ /** @extensions: Pointer to the first extension struct, if any */
+ __u64 extensions;
+
+ /** @exec_queue_id: Exec queue ID */
+ __u32 exec_queue_id;
+
+ /** @property: property to set */
+ __u32 property;
+
+ /** @value: property value */
+ __u64 value;
+
+ /** @reserved: Reserved */
+ __u64 reserved[2];
+};
+
#if defined(__cplusplus)
}
#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH v2 06/16] drm/xe/multi_queue: Add exec_queue set_property ioctl support
2025-11-04 18:51 ` [PATCH v2 06/16] drm/xe/multi_queue: Add exec_queue set_property ioctl support Niranjana Vishwanathapura
@ 2025-11-04 22:48 ` Matthew Brost
0 siblings, 0 replies; 27+ messages in thread
From: Matthew Brost @ 2025-11-04 22:48 UTC (permalink / raw)
To: Niranjana Vishwanathapura; +Cc: intel-xe
On Tue, Nov 04, 2025 at 10:51:40AM -0800, Niranjana Vishwanathapura wrote:
> This patch adds support for exec_queue set_property ioctl.
> It is derived from the original work which is part of
> https://patchwork.freedesktop.org/series/112188/
>
> Currently only DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY
> property can be dynamically set.
>
> v2: Check for and update kernel-doc which property this ioctl
> supports (Matt Brost)
>
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
> Signed-off-by: Pallavi Mishra <pallavi.mishra@intel.com>
> Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
> ---
> drivers/gpu/drm/xe/xe_device.c | 2 ++
> drivers/gpu/drm/xe/xe_exec_queue.c | 35 ++++++++++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_exec_queue.h | 2 ++
> include/uapi/drm/xe_drm.h | 26 ++++++++++++++++++++++
> 4 files changed, 65 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
> index 9f2f19dc1fd3..391b2f9a2846 100644
> --- a/drivers/gpu/drm/xe/xe_device.c
> +++ b/drivers/gpu/drm/xe/xe_device.c
> @@ -209,6 +209,8 @@ static const struct drm_ioctl_desc xe_ioctls[] = {
> DRM_IOCTL_DEF_DRV(XE_MADVISE, xe_vm_madvise_ioctl, DRM_RENDER_ALLOW),
> DRM_IOCTL_DEF_DRV(XE_VM_QUERY_MEM_RANGE_ATTRS, xe_vm_query_vmas_attrs_ioctl,
> DRM_RENDER_ALLOW),
> + DRM_IOCTL_DEF_DRV(XE_EXEC_QUEUE_SET_PROPERTY, xe_exec_queue_set_property_ioctl,
> + DRM_RENDER_ALLOW),
> };
>
> static long xe_drm_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
> diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
> index d36d018d7ba0..c96cc085e8e8 100644
> --- a/drivers/gpu/drm/xe/xe_exec_queue.c
> +++ b/drivers/gpu/drm/xe/xe_exec_queue.c
> @@ -762,6 +762,41 @@ static const xe_exec_queue_set_property_fn exec_queue_set_property_funcs[] = {
> exec_queue_set_multi_queue_priority,
> };
>
> +int xe_exec_queue_set_property_ioctl(struct drm_device *dev, void *data,
> + struct drm_file *file)
> +{
> + struct xe_device *xe = to_xe_device(dev);
> + struct xe_file *xef = to_xe_file(file);
> + struct drm_xe_exec_queue_set_property *args = data;
> + struct xe_exec_queue *q;
> + int ret;
> + u32 idx;
> +
> + if (XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1]))
> + return -EINVAL;
> +
> + if (XE_IOCTL_DBG(xe, args->property !=
> + DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY))
> + return -EINVAL;
> +
> + q = xe_exec_queue_lookup(xef, args->exec_queue_id);
> + if (XE_IOCTL_DBG(xe, !q))
> + return -ENOENT;
> +
> + idx = array_index_nospec(args->property,
> + ARRAY_SIZE(exec_queue_set_property_funcs));
> + ret = exec_queue_set_property_funcs[idx](xe, q, args->value);
> + if (XE_IOCTL_DBG(xe, ret))
> + goto err_post_lookup;
> +
> + xe_exec_queue_put(q);
> + return 0;
> +
> + err_post_lookup:
> + xe_exec_queue_put(q);
> + return ret;
> +}
> +
> static int exec_queue_user_ext_check(struct xe_exec_queue *q, u64 properties)
> {
> u64 secondary_queue_valid_props = BIT_ULL(DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP) |
> diff --git a/drivers/gpu/drm/xe/xe_exec_queue.h b/drivers/gpu/drm/xe/xe_exec_queue.h
> index e6daa40003f2..ffcc1feb879e 100644
> --- a/drivers/gpu/drm/xe/xe_exec_queue.h
> +++ b/drivers/gpu/drm/xe/xe_exec_queue.h
> @@ -125,6 +125,8 @@ int xe_exec_queue_destroy_ioctl(struct drm_device *dev, void *data,
> struct drm_file *file);
> int xe_exec_queue_get_property_ioctl(struct drm_device *dev, void *data,
> struct drm_file *file);
> +int xe_exec_queue_set_property_ioctl(struct drm_device *dev, void *data,
> + struct drm_file *file);
> enum xe_exec_queue_priority xe_exec_queue_device_get_max_priority(struct xe_device *xe);
>
> void xe_exec_queue_last_fence_put(struct xe_exec_queue *e, struct xe_vm *vm);
> diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
> index 6734ef7fada1..d5162a3a89db 100644
> --- a/include/uapi/drm/xe_drm.h
> +++ b/include/uapi/drm/xe_drm.h
> @@ -106,6 +106,7 @@ extern "C" {
> #define DRM_XE_OBSERVATION 0x0b
> #define DRM_XE_MADVISE 0x0c
> #define DRM_XE_VM_QUERY_MEM_RANGE_ATTRS 0x0d
> +#define DRM_XE_EXEC_QUEUE_SET_PROPERTY 0x0e
>
> /* Must be kept compact -- no holes */
>
> @@ -123,6 +124,7 @@ extern "C" {
> #define DRM_IOCTL_XE_OBSERVATION DRM_IOW(DRM_COMMAND_BASE + DRM_XE_OBSERVATION, struct drm_xe_observation_param)
> #define DRM_IOCTL_XE_MADVISE DRM_IOW(DRM_COMMAND_BASE + DRM_XE_MADVISE, struct drm_xe_madvise)
> #define DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_QUERY_MEM_RANGE_ATTRS, struct drm_xe_vm_query_mem_range_attr)
> +#define DRM_IOCTL_XE_EXEC_QUEUE_SET_PROPERTY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_SET_PROPERTY, struct drm_xe_exec_queue_set_property)
>
> /**
> * DOC: Xe IOCTL Extensions
> @@ -2286,6 +2288,30 @@ struct drm_xe_vm_query_mem_range_attr {
>
> };
>
> +/**
> + * struct drm_xe_exec_queue_set_property - exec queue set property
> + *
> + * Sets execution queue properties dynamically.
> + * Currently only %DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY
> + * property can be dynamically set.
> + */
> +struct drm_xe_exec_queue_set_property {
> + /** @extensions: Pointer to the first extension struct, if any */
> + __u64 extensions;
> +
> + /** @exec_queue_id: Exec queue ID */
> + __u32 exec_queue_id;
> +
> + /** @property: property to set */
> + __u32 property;
> +
> + /** @value: property value */
> + __u64 value;
> +
> + /** @reserved: Reserved */
> + __u64 reserved[2];
> +};
> +
> #if defined(__cplusplus)
> }
> #endif
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v2 07/16] drm/xe/multi_queue: Add support for multi queue dynamic priority change
2025-11-04 18:51 [PATCH v2 00/16] drm/xe: Multi Queue feature support Niranjana Vishwanathapura
` (5 preceding siblings ...)
2025-11-04 18:51 ` [PATCH v2 06/16] drm/xe/multi_queue: Add exec_queue set_property ioctl support Niranjana Vishwanathapura
@ 2025-11-04 18:51 ` Niranjana Vishwanathapura
2025-11-04 23:02 ` Matthew Brost
2025-11-04 18:51 ` [PATCH v2 08/16] drm/xe/multi_queue: Add multi queue information to guc_info dump Niranjana Vishwanathapura
` (12 subsequent siblings)
19 siblings, 1 reply; 27+ messages in thread
From: Niranjana Vishwanathapura @ 2025-11-04 18:51 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.brost
Support dynamic priority change for multi queue group queues via
exec queue set_property ioctl. Issue CGP_SYNC command to GuC through
the drm scheduler message interface for priority to take effect.
v2: Move is_multi_queue check to exec_queue layer and assert
is_multi_queue being set in guc submission layer (Matt Brost)
Signed-off-by: Pallavi Mishra <pallavi.mishra@intel.com>
Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
---
drivers/gpu/drm/xe/xe_exec_queue.c | 11 ++++-
drivers/gpu/drm/xe/xe_exec_queue_types.h | 3 ++
drivers/gpu/drm/xe/xe_guc_submit.c | 55 ++++++++++++++++++++++--
3 files changed, 63 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
index c96cc085e8e8..fef48b82b189 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue.c
+++ b/drivers/gpu/drm/xe/xe_exec_queue.c
@@ -744,9 +744,16 @@ static int exec_queue_set_multi_queue_priority(struct xe_device *xe, struct xe_e
if (XE_IOCTL_DBG(xe, value > XE_MULTI_QUEUE_PRIORITY_HIGH))
return -EINVAL;
- q->multi_queue.priority = value;
+ /* For queue creation time (!q->xef) setting, just store the priority value */
+ if (!q->xef) {
+ q->multi_queue.priority = value;
+ return 0;
+ }
- return 0;
+ if (!xe_exec_queue_is_multi_queue(q))
+ return -EINVAL;
+
+ return q->ops->set_multi_queue_priority(q, value);
}
typedef int (*xe_exec_queue_set_property_fn)(struct xe_device *xe,
diff --git a/drivers/gpu/drm/xe/xe_exec_queue_types.h b/drivers/gpu/drm/xe/xe_exec_queue_types.h
index 445ae4979c0c..cafb3ba9a123 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue_types.h
+++ b/drivers/gpu/drm/xe/xe_exec_queue_types.h
@@ -257,6 +257,9 @@ struct xe_exec_queue_ops {
int (*set_timeslice)(struct xe_exec_queue *q, u32 timeslice_us);
/** @set_preempt_timeout: Set preemption timeout for exec queue */
int (*set_preempt_timeout)(struct xe_exec_queue *q, u32 preempt_timeout_us);
+ /** @set_multi_queue_priority: Set multi queue priority */
+ int (*set_multi_queue_priority)(struct xe_exec_queue *q,
+ enum xe_multi_queue_priority priority);
/**
* @suspend: Suspend exec queue from executing, allowed to be called
* multiple times in a row before resume with the caveat that
diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
index b01d852ae526..27ef83524a34 100644
--- a/drivers/gpu/drm/xe/xe_guc_submit.c
+++ b/drivers/gpu/drm/xe/xe_guc_submit.c
@@ -1767,10 +1767,32 @@ static void __guc_exec_queue_process_msg_resume(struct xe_sched_msg *msg)
}
}
-#define CLEANUP 1 /* Non-zero values to catch uninitialized msg */
-#define SET_SCHED_PROPS 2
-#define SUSPEND 3
-#define RESUME 4
+static void __guc_exec_queue_process_msg_set_multi_queue_priority(struct xe_sched_msg *msg)
+{
+ struct xe_exec_queue *q = msg->private_data;
+
+ if (guc_exec_queue_allowed_to_change_state(q)) {
+#define MAX_MULTI_QUEUE_REG_SIZE (2)
+ struct xe_guc *guc = exec_queue_to_guc(q);
+ struct xe_exec_queue_group *group = q->multi_queue.group;
+ u32 action[MAX_MULTI_QUEUE_REG_SIZE];
+ int len = 0;
+
+ action[len++] = XE_GUC_ACTION_MULTI_QUEUE_CONTEXT_CGP_SYNC;
+ action[len++] = group->primary->guc->id;
+#undef MAX_MULTI_QUEUE_REG_SIZE
+
+ xe_guc_exec_queue_group_cgp_sync(guc, q, action, len);
+ }
+
+ kfree(msg);
+}
+
+#define CLEANUP 1 /* Non-zero values to catch uninitialized msg */
+#define SET_SCHED_PROPS 2
+#define SUSPEND 3
+#define RESUME 4
+#define SET_MULTI_QUEUE_PRIORITY 5
#define OPCODE_MASK 0xf
#define MSG_LOCKED BIT(8)
#define MSG_HEAD BIT(9)
@@ -1794,6 +1816,9 @@ static void guc_exec_queue_process_msg(struct xe_sched_msg *msg)
case RESUME:
__guc_exec_queue_process_msg_resume(msg);
break;
+ case SET_MULTI_QUEUE_PRIORITY:
+ __guc_exec_queue_process_msg_set_multi_queue_priority(msg);
+ break;
default:
XE_WARN_ON("Unknown message type");
}
@@ -2010,6 +2035,27 @@ static int guc_exec_queue_set_preempt_timeout(struct xe_exec_queue *q,
return 0;
}
+static int guc_exec_queue_set_multi_queue_priority(struct xe_exec_queue *q,
+ enum xe_multi_queue_priority priority)
+{
+ struct xe_sched_msg *msg;
+
+ xe_gt_assert(guc_to_gt(exec_queue_to_guc(q)), xe_exec_queue_is_multi_queue(q));
+
+ if (q->multi_queue.priority == priority ||
+ exec_queue_killed_or_banned_or_wedged(q))
+ return 0;
+
+ msg = kmalloc(sizeof(*msg), GFP_KERNEL);
+ if (!msg)
+ return -ENOMEM;
+
+ q->multi_queue.priority = priority;
+ guc_exec_queue_add_msg(q, msg, SET_MULTI_QUEUE_PRIORITY);
+
+ return 0;
+}
+
static int guc_exec_queue_suspend(struct xe_exec_queue *q)
{
struct xe_gpu_scheduler *sched = &q->guc->sched;
@@ -2101,6 +2147,7 @@ static const struct xe_exec_queue_ops guc_exec_queue_ops = {
.set_priority = guc_exec_queue_set_priority,
.set_timeslice = guc_exec_queue_set_timeslice,
.set_preempt_timeout = guc_exec_queue_set_preempt_timeout,
+ .set_multi_queue_priority = guc_exec_queue_set_multi_queue_priority,
.suspend = guc_exec_queue_suspend,
.suspend_wait = guc_exec_queue_suspend_wait,
.resume = guc_exec_queue_resume,
--
2.43.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH v2 07/16] drm/xe/multi_queue: Add support for multi queue dynamic priority change
2025-11-04 18:51 ` [PATCH v2 07/16] drm/xe/multi_queue: Add support for multi queue dynamic priority change Niranjana Vishwanathapura
@ 2025-11-04 23:02 ` Matthew Brost
2025-11-04 23:49 ` Niranjana Vishwanathapura
0 siblings, 1 reply; 27+ messages in thread
From: Matthew Brost @ 2025-11-04 23:02 UTC (permalink / raw)
To: Niranjana Vishwanathapura; +Cc: intel-xe
On Tue, Nov 04, 2025 at 10:51:41AM -0800, Niranjana Vishwanathapura wrote:
> Support dynamic priority change for multi queue group queues via
> exec queue set_property ioctl. Issue CGP_SYNC command to GuC through
> the drm scheduler message interface for priority to take effect.
>
> v2: Move is_multi_queue check to exec_queue layer and assert
> is_multi_queue being set in guc submission layer (Matt Brost)
>
> Signed-off-by: Pallavi Mishra <pallavi.mishra@intel.com>
> Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
> ---
> drivers/gpu/drm/xe/xe_exec_queue.c | 11 ++++-
> drivers/gpu/drm/xe/xe_exec_queue_types.h | 3 ++
> drivers/gpu/drm/xe/xe_guc_submit.c | 55 ++++++++++++++++++++++--
> 3 files changed, 63 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
> index c96cc085e8e8..fef48b82b189 100644
> --- a/drivers/gpu/drm/xe/xe_exec_queue.c
> +++ b/drivers/gpu/drm/xe/xe_exec_queue.c
> @@ -744,9 +744,16 @@ static int exec_queue_set_multi_queue_priority(struct xe_device *xe, struct xe_e
> if (XE_IOCTL_DBG(xe, value > XE_MULTI_QUEUE_PRIORITY_HIGH))
> return -EINVAL;
>
> - q->multi_queue.priority = value;
> + /* For queue creation time (!q->xef) setting, just store the priority value */
> + if (!q->xef) {
> + q->multi_queue.priority = value;
> + return 0;
> + }
>
> - return 0;
> + if (!xe_exec_queue_is_multi_queue(q))
> + return -EINVAL;
> +
> + return q->ops->set_multi_queue_priority(q, value);
> }
>
> typedef int (*xe_exec_queue_set_property_fn)(struct xe_device *xe,
> diff --git a/drivers/gpu/drm/xe/xe_exec_queue_types.h b/drivers/gpu/drm/xe/xe_exec_queue_types.h
> index 445ae4979c0c..cafb3ba9a123 100644
> --- a/drivers/gpu/drm/xe/xe_exec_queue_types.h
> +++ b/drivers/gpu/drm/xe/xe_exec_queue_types.h
> @@ -257,6 +257,9 @@ struct xe_exec_queue_ops {
> int (*set_timeslice)(struct xe_exec_queue *q, u32 timeslice_us);
> /** @set_preempt_timeout: Set preemption timeout for exec queue */
> int (*set_preempt_timeout)(struct xe_exec_queue *q, u32 preempt_timeout_us);
> + /** @set_multi_queue_priority: Set multi queue priority */
> + int (*set_multi_queue_priority)(struct xe_exec_queue *q,
> + enum xe_multi_queue_priority priority);
> /**
> * @suspend: Suspend exec queue from executing, allowed to be called
> * multiple times in a row before resume with the caveat that
> diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
> index b01d852ae526..27ef83524a34 100644
> --- a/drivers/gpu/drm/xe/xe_guc_submit.c
> +++ b/drivers/gpu/drm/xe/xe_guc_submit.c
> @@ -1767,10 +1767,32 @@ static void __guc_exec_queue_process_msg_resume(struct xe_sched_msg *msg)
> }
> }
>
> -#define CLEANUP 1 /* Non-zero values to catch uninitialized msg */
> -#define SET_SCHED_PROPS 2
> -#define SUSPEND 3
> -#define RESUME 4
> +static void __guc_exec_queue_process_msg_set_multi_queue_priority(struct xe_sched_msg *msg)
> +{
> + struct xe_exec_queue *q = msg->private_data;
> +
> + if (guc_exec_queue_allowed_to_change_state(q)) {
> +#define MAX_MULTI_QUEUE_REG_SIZE (2)
> + struct xe_guc *guc = exec_queue_to_guc(q);
> + struct xe_exec_queue_group *group = q->multi_queue.group;
> + u32 action[MAX_MULTI_QUEUE_REG_SIZE];
> + int len = 0;
> +
> + action[len++] = XE_GUC_ACTION_MULTI_QUEUE_CONTEXT_CGP_SYNC;
> + action[len++] = group->primary->guc->id;
If we want to be really paranoid;
xe_gt_assert(..., len <= MAX_MULTI_QUEUE_REG_SIZE);
Anyways:
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
> +#undef MAX_MULTI_QUEUE_REG_SIZE
> +
> + xe_guc_exec_queue_group_cgp_sync(guc, q, action, len);
> + }
> +
> + kfree(msg);
> +}
> +
> +#define CLEANUP 1 /* Non-zero values to catch uninitialized msg */
> +#define SET_SCHED_PROPS 2
> +#define SUSPEND 3
> +#define RESUME 4
> +#define SET_MULTI_QUEUE_PRIORITY 5
> #define OPCODE_MASK 0xf
> #define MSG_LOCKED BIT(8)
> #define MSG_HEAD BIT(9)
> @@ -1794,6 +1816,9 @@ static void guc_exec_queue_process_msg(struct xe_sched_msg *msg)
> case RESUME:
> __guc_exec_queue_process_msg_resume(msg);
> break;
> + case SET_MULTI_QUEUE_PRIORITY:
> + __guc_exec_queue_process_msg_set_multi_queue_priority(msg);
> + break;
> default:
> XE_WARN_ON("Unknown message type");
> }
> @@ -2010,6 +2035,27 @@ static int guc_exec_queue_set_preempt_timeout(struct xe_exec_queue *q,
> return 0;
> }
>
> +static int guc_exec_queue_set_multi_queue_priority(struct xe_exec_queue *q,
> + enum xe_multi_queue_priority priority)
> +{
> + struct xe_sched_msg *msg;
> +
> + xe_gt_assert(guc_to_gt(exec_queue_to_guc(q)), xe_exec_queue_is_multi_queue(q));
> +
> + if (q->multi_queue.priority == priority ||
> + exec_queue_killed_or_banned_or_wedged(q))
> + return 0;
> +
> + msg = kmalloc(sizeof(*msg), GFP_KERNEL);
> + if (!msg)
> + return -ENOMEM;
> +
> + q->multi_queue.priority = priority;
> + guc_exec_queue_add_msg(q, msg, SET_MULTI_QUEUE_PRIORITY);
> +
> + return 0;
> +}
> +
> static int guc_exec_queue_suspend(struct xe_exec_queue *q)
> {
> struct xe_gpu_scheduler *sched = &q->guc->sched;
> @@ -2101,6 +2147,7 @@ static const struct xe_exec_queue_ops guc_exec_queue_ops = {
> .set_priority = guc_exec_queue_set_priority,
> .set_timeslice = guc_exec_queue_set_timeslice,
> .set_preempt_timeout = guc_exec_queue_set_preempt_timeout,
> + .set_multi_queue_priority = guc_exec_queue_set_multi_queue_priority,
> .suspend = guc_exec_queue_suspend,
> .suspend_wait = guc_exec_queue_suspend_wait,
> .resume = guc_exec_queue_resume,
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH v2 07/16] drm/xe/multi_queue: Add support for multi queue dynamic priority change
2025-11-04 23:02 ` Matthew Brost
@ 2025-11-04 23:49 ` Niranjana Vishwanathapura
0 siblings, 0 replies; 27+ messages in thread
From: Niranjana Vishwanathapura @ 2025-11-04 23:49 UTC (permalink / raw)
To: Matthew Brost; +Cc: intel-xe
On Tue, Nov 04, 2025 at 03:02:51PM -0800, Matthew Brost wrote:
>On Tue, Nov 04, 2025 at 10:51:41AM -0800, Niranjana Vishwanathapura wrote:
>> Support dynamic priority change for multi queue group queues via
>> exec queue set_property ioctl. Issue CGP_SYNC command to GuC through
>> the drm scheduler message interface for priority to take effect.
>>
>> v2: Move is_multi_queue check to exec_queue layer and assert
>> is_multi_queue being set in guc submission layer (Matt Brost)
>>
>> Signed-off-by: Pallavi Mishra <pallavi.mishra@intel.com>
>> Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
>> ---
>> drivers/gpu/drm/xe/xe_exec_queue.c | 11 ++++-
>> drivers/gpu/drm/xe/xe_exec_queue_types.h | 3 ++
>> drivers/gpu/drm/xe/xe_guc_submit.c | 55 ++++++++++++++++++++++--
>> 3 files changed, 63 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
>> index c96cc085e8e8..fef48b82b189 100644
>> --- a/drivers/gpu/drm/xe/xe_exec_queue.c
>> +++ b/drivers/gpu/drm/xe/xe_exec_queue.c
>> @@ -744,9 +744,16 @@ static int exec_queue_set_multi_queue_priority(struct xe_device *xe, struct xe_e
>> if (XE_IOCTL_DBG(xe, value > XE_MULTI_QUEUE_PRIORITY_HIGH))
>> return -EINVAL;
>>
>> - q->multi_queue.priority = value;
>> + /* For queue creation time (!q->xef) setting, just store the priority value */
>> + if (!q->xef) {
>> + q->multi_queue.priority = value;
>> + return 0;
>> + }
>>
>> - return 0;
>> + if (!xe_exec_queue_is_multi_queue(q))
>> + return -EINVAL;
>> +
>> + return q->ops->set_multi_queue_priority(q, value);
>> }
>>
>> typedef int (*xe_exec_queue_set_property_fn)(struct xe_device *xe,
>> diff --git a/drivers/gpu/drm/xe/xe_exec_queue_types.h b/drivers/gpu/drm/xe/xe_exec_queue_types.h
>> index 445ae4979c0c..cafb3ba9a123 100644
>> --- a/drivers/gpu/drm/xe/xe_exec_queue_types.h
>> +++ b/drivers/gpu/drm/xe/xe_exec_queue_types.h
>> @@ -257,6 +257,9 @@ struct xe_exec_queue_ops {
>> int (*set_timeslice)(struct xe_exec_queue *q, u32 timeslice_us);
>> /** @set_preempt_timeout: Set preemption timeout for exec queue */
>> int (*set_preempt_timeout)(struct xe_exec_queue *q, u32 preempt_timeout_us);
>> + /** @set_multi_queue_priority: Set multi queue priority */
>> + int (*set_multi_queue_priority)(struct xe_exec_queue *q,
>> + enum xe_multi_queue_priority priority);
>> /**
>> * @suspend: Suspend exec queue from executing, allowed to be called
>> * multiple times in a row before resume with the caveat that
>> diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
>> index b01d852ae526..27ef83524a34 100644
>> --- a/drivers/gpu/drm/xe/xe_guc_submit.c
>> +++ b/drivers/gpu/drm/xe/xe_guc_submit.c
>> @@ -1767,10 +1767,32 @@ static void __guc_exec_queue_process_msg_resume(struct xe_sched_msg *msg)
>> }
>> }
>>
>> -#define CLEANUP 1 /* Non-zero values to catch uninitialized msg */
>> -#define SET_SCHED_PROPS 2
>> -#define SUSPEND 3
>> -#define RESUME 4
>> +static void __guc_exec_queue_process_msg_set_multi_queue_priority(struct xe_sched_msg *msg)
>> +{
>> + struct xe_exec_queue *q = msg->private_data;
>> +
>> + if (guc_exec_queue_allowed_to_change_state(q)) {
>> +#define MAX_MULTI_QUEUE_REG_SIZE (2)
>> + struct xe_guc *guc = exec_queue_to_guc(q);
>> + struct xe_exec_queue_group *group = q->multi_queue.group;
>> + u32 action[MAX_MULTI_QUEUE_REG_SIZE];
>> + int len = 0;
>> +
>> + action[len++] = XE_GUC_ACTION_MULTI_QUEUE_CONTEXT_CGP_SYNC;
>> + action[len++] = group->primary->guc->id;
>
>If we want to be really paranoid;
>
>xe_gt_assert(..., len <= MAX_MULTI_QUEUE_REG_SIZE);
>
>Anyways:
>Reviewed-by: Matthew Brost <matthew.brost@intel.com>
>
Ok, will add the assert.
Niranjana
>> +#undef MAX_MULTI_QUEUE_REG_SIZE
>> +
>> + xe_guc_exec_queue_group_cgp_sync(guc, q, action, len);
>> + }
>> +
>> + kfree(msg);
>> +}
>> +
>> +#define CLEANUP 1 /* Non-zero values to catch uninitialized msg */
>> +#define SET_SCHED_PROPS 2
>> +#define SUSPEND 3
>> +#define RESUME 4
>> +#define SET_MULTI_QUEUE_PRIORITY 5
>> #define OPCODE_MASK 0xf
>> #define MSG_LOCKED BIT(8)
>> #define MSG_HEAD BIT(9)
>> @@ -1794,6 +1816,9 @@ static void guc_exec_queue_process_msg(struct xe_sched_msg *msg)
>> case RESUME:
>> __guc_exec_queue_process_msg_resume(msg);
>> break;
>> + case SET_MULTI_QUEUE_PRIORITY:
>> + __guc_exec_queue_process_msg_set_multi_queue_priority(msg);
>> + break;
>> default:
>> XE_WARN_ON("Unknown message type");
>> }
>> @@ -2010,6 +2035,27 @@ static int guc_exec_queue_set_preempt_timeout(struct xe_exec_queue *q,
>> return 0;
>> }
>>
>> +static int guc_exec_queue_set_multi_queue_priority(struct xe_exec_queue *q,
>> + enum xe_multi_queue_priority priority)
>> +{
>> + struct xe_sched_msg *msg;
>> +
>> + xe_gt_assert(guc_to_gt(exec_queue_to_guc(q)), xe_exec_queue_is_multi_queue(q));
>> +
>> + if (q->multi_queue.priority == priority ||
>> + exec_queue_killed_or_banned_or_wedged(q))
>> + return 0;
>> +
>> + msg = kmalloc(sizeof(*msg), GFP_KERNEL);
>> + if (!msg)
>> + return -ENOMEM;
>> +
>> + q->multi_queue.priority = priority;
>> + guc_exec_queue_add_msg(q, msg, SET_MULTI_QUEUE_PRIORITY);
>> +
>> + return 0;
>> +}
>> +
>> static int guc_exec_queue_suspend(struct xe_exec_queue *q)
>> {
>> struct xe_gpu_scheduler *sched = &q->guc->sched;
>> @@ -2101,6 +2147,7 @@ static const struct xe_exec_queue_ops guc_exec_queue_ops = {
>> .set_priority = guc_exec_queue_set_priority,
>> .set_timeslice = guc_exec_queue_set_timeslice,
>> .set_preempt_timeout = guc_exec_queue_set_preempt_timeout,
>> + .set_multi_queue_priority = guc_exec_queue_set_multi_queue_priority,
>> .suspend = guc_exec_queue_suspend,
>> .suspend_wait = guc_exec_queue_suspend_wait,
>> .resume = guc_exec_queue_resume,
>> --
>> 2.43.0
>>
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v2 08/16] drm/xe/multi_queue: Add multi queue information to guc_info dump
2025-11-04 18:51 [PATCH v2 00/16] drm/xe: Multi Queue feature support Niranjana Vishwanathapura
` (6 preceding siblings ...)
2025-11-04 18:51 ` [PATCH v2 07/16] drm/xe/multi_queue: Add support for multi queue dynamic priority change Niranjana Vishwanathapura
@ 2025-11-04 18:51 ` Niranjana Vishwanathapura
2025-11-04 18:51 ` [PATCH v2 09/16] drm/xe/multi_queue: Handle tearing down of a multi queue Niranjana Vishwanathapura
` (11 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Niranjana Vishwanathapura @ 2025-11-04 18:51 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.brost
Dump multi queue specific information in the guc exec queue
dump.
v2: Move multi queue related fields inside the multi_queue
sub-structure (Matt Brost)
Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
---
drivers/gpu/drm/xe/xe_guc_submit.c | 10 ++++++++++
drivers/gpu/drm/xe/xe_guc_submit_types.h | 13 +++++++++++++
2 files changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
index 27ef83524a34..f70c5f8003b7 100644
--- a/drivers/gpu/drm/xe/xe_guc_submit.c
+++ b/drivers/gpu/drm/xe/xe_guc_submit.c
@@ -3038,6 +3038,11 @@ xe_guc_exec_queue_snapshot_capture(struct xe_exec_queue *q)
if (snapshot->parallel_execution)
guc_exec_queue_wq_snapshot_capture(q, snapshot);
+ if (xe_exec_queue_is_multi_queue(q)) {
+ snapshot->multi_queue.valid = true;
+ snapshot->multi_queue.primary = xe_exec_queue_multi_queue_primary(q)->guc->id;
+ snapshot->multi_queue.pos = q->multi_queue.pos;
+ }
spin_lock(&sched->base.job_list_lock);
snapshot->pending_list_size = list_count_nodes(&sched->base.pending_list);
snapshot->pending_list = kmalloc_array(snapshot->pending_list_size,
@@ -3120,6 +3125,11 @@ xe_guc_exec_queue_snapshot_print(struct xe_guc_submit_exec_queue_snapshot *snaps
if (snapshot->parallel_execution)
guc_exec_queue_wq_snapshot_print(snapshot, p);
+ if (snapshot->multi_queue.valid) {
+ drm_printf(p, "\tMulti queue primary GuC ID: %d\n", snapshot->multi_queue.primary);
+ drm_printf(p, "\tMulti queue position: %d\n", snapshot->multi_queue.pos);
+ }
+
for (i = 0; snapshot->pending_list && i < snapshot->pending_list_size;
i++)
drm_printf(p, "\tJob: seqno=%d, fence=%d, finished=%d\n",
diff --git a/drivers/gpu/drm/xe/xe_guc_submit_types.h b/drivers/gpu/drm/xe/xe_guc_submit_types.h
index dc7456c34583..25e29e85502c 100644
--- a/drivers/gpu/drm/xe/xe_guc_submit_types.h
+++ b/drivers/gpu/drm/xe/xe_guc_submit_types.h
@@ -135,6 +135,19 @@ struct xe_guc_submit_exec_queue_snapshot {
u32 wq[WQ_SIZE / sizeof(u32)];
} parallel;
+ /** @multi_queue: snapshot of the multi queue information */
+ struct {
+ /**
+ * @multi_queue.primary: GuC id of the primary exec queue
+ * of the multi queue group.
+ */
+ u32 primary;
+ /** @multi_queue.pos: Position of the exec queue within the multi queue group */
+ u8 pos;
+ /** @valid: The exec queue is part of a multi queue group */
+ bool valid;
+ } multi_queue;
+
/** @pending_list_size: Size of the pending list snapshot array */
int pending_list_size;
/** @pending_list: snapshot of the pending list info */
--
2.43.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v2 09/16] drm/xe/multi_queue: Handle tearing down of a multi queue
2025-11-04 18:51 [PATCH v2 00/16] drm/xe: Multi Queue feature support Niranjana Vishwanathapura
` (7 preceding siblings ...)
2025-11-04 18:51 ` [PATCH v2 08/16] drm/xe/multi_queue: Add multi queue information to guc_info dump Niranjana Vishwanathapura
@ 2025-11-04 18:51 ` Niranjana Vishwanathapura
2025-11-04 18:51 ` [PATCH v2 10/16] drm/xe/multi_queue: Set QUEUE_DRAIN_MODE for Multi Queue batches Niranjana Vishwanathapura
` (10 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Niranjana Vishwanathapura @ 2025-11-04 18:51 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.brost
As all queues of a multi queue group use the primary queue of the group
to interface with GuC. Hence there is a dependency between the queues of
the group. So, when primary queue of a multi queue group is cleaned up,
also trigger a cleanup of the secondary queues. During cleanup, stop and
re-start submission for all queues of a multi queue group to avoid any
submission happening in parallel when a queue is being cleaned up.
v2: Initialize group->list_lock, add fs_reclaim dependency, remove
unwanted secondary queues cleanup (Matt Brost)
Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
---
drivers/gpu/drm/xe/xe_exec_queue.c | 10 ++
drivers/gpu/drm/xe/xe_exec_queue_types.h | 6 +
drivers/gpu/drm/xe/xe_guc_submit.c | 146 +++++++++++++++++++----
3 files changed, 140 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
index fef48b82b189..f86f8198aedb 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue.c
+++ b/drivers/gpu/drm/xe/xe_exec_queue.c
@@ -87,6 +87,7 @@ static void xe_exec_queue_group_cleanup(struct xe_exec_queue *q)
xe_lrc_put(lrc);
xa_destroy(&group->xa);
+ mutex_destroy(&group->list_lock);
xe_bo_unpin_map_no_vm(group->cgp_bo);
kfree(group);
}
@@ -624,9 +625,18 @@ static int xe_exec_queue_group_init(struct xe_device *xe, struct xe_exec_queue *
group->primary = q;
group->cgp_bo = bo;
+ INIT_LIST_HEAD(&group->list);
xa_init_flags(&group->xa, XA_FLAGS_ALLOC1);
+ mutex_init(&group->list_lock);
q->multi_queue.group = group;
+ /* group->list_lock is used in submission backend */
+ if (!IS_ENABLED(CONFIG_LOCKDEP)) {
+ fs_reclaim_acquire(GFP_KERNEL);
+ might_lock(&group->list_lock);
+ fs_reclaim_release(GFP_KERNEL);
+ }
+
return 0;
}
diff --git a/drivers/gpu/drm/xe/xe_exec_queue_types.h b/drivers/gpu/drm/xe/xe_exec_queue_types.h
index cafb3ba9a123..5721fb4bad1a 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue_types.h
+++ b/drivers/gpu/drm/xe/xe_exec_queue_types.h
@@ -58,6 +58,10 @@ struct xe_exec_queue_group {
struct xe_bo *cgp_bo;
/** @xa: xarray to store LRCs */
struct xarray xa;
+ /** @list: List of all secondary queues in the group */
+ struct list_head list;
+ /** @list_lock: Secondary queue list lock */
+ struct mutex list_lock;
/** @sync_pending: CGP_SYNC_DONE g2h response pending */
bool sync_pending;
};
@@ -145,6 +149,8 @@ struct xe_exec_queue {
struct {
/** @multi_queue.group: Queue group information */
struct xe_exec_queue_group *group;
+ /** @multi_queue.link: Link into group's secondary queues list */
+ struct list_head link;
/** @multi_queue.priority: Queue priority within the multi-queue group */
enum xe_multi_queue_priority priority;
/** @multi_queue.pos: Position of queue within the multi-queue group */
diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
index f70c5f8003b7..b5ea86069d49 100644
--- a/drivers/gpu/drm/xe/xe_guc_submit.c
+++ b/drivers/gpu/drm/xe/xe_guc_submit.c
@@ -926,6 +926,81 @@ static void wq_item_append(struct xe_exec_queue *q)
parallel_write(xe, map, wq_desc.tail, q->guc->wqi_tail);
}
+static void xe_guc_exec_queue_submission_start(struct xe_exec_queue *q)
+{
+ /*
+ * If the exec queue is part of a multi queue group, then start submission
+ * on all queues of the multi queue group.
+ */
+ if (xe_exec_queue_is_multi_queue(q)) {
+ struct xe_exec_queue *primary = xe_exec_queue_multi_queue_primary(q);
+ struct xe_exec_queue_group *group = q->multi_queue.group;
+ struct xe_exec_queue *eq;
+
+ xe_sched_submission_start(&primary->guc->sched);
+
+ mutex_lock(&group->list_lock);
+ list_for_each_entry(eq, &group->list, multi_queue.link)
+ xe_sched_submission_start(&eq->guc->sched);
+ mutex_unlock(&group->list_lock);
+ } else {
+ xe_sched_submission_start(&q->guc->sched);
+ }
+}
+
+static void xe_guc_exec_queue_submission_stop(struct xe_exec_queue *q)
+{
+ /*
+ * If the exec queue is part of a multi queue group, then stop submission
+ * on all queues of the multi queue group.
+ */
+ if (xe_exec_queue_is_multi_queue(q)) {
+ struct xe_exec_queue *primary = xe_exec_queue_multi_queue_primary(q);
+ struct xe_exec_queue_group *group = q->multi_queue.group;
+ struct xe_exec_queue *eq;
+
+ xe_sched_submission_stop(&primary->guc->sched);
+
+ mutex_lock(&group->list_lock);
+ list_for_each_entry(eq, &group->list, multi_queue.link)
+ xe_sched_submission_stop(&eq->guc->sched);
+ mutex_unlock(&group->list_lock);
+ } else {
+ xe_sched_submission_stop(&q->guc->sched);
+ }
+}
+
+static void xe_guc_exec_queue_trigger_cleanup(struct xe_exec_queue *q)
+{
+ struct xe_guc *guc = exec_queue_to_guc(q);
+ struct xe_device *xe = guc_to_xe(guc);
+
+ /** to wakeup xe_wait_user_fence ioctl if exec queue is reset */
+ wake_up_all(&xe->ufence_wq);
+
+ if (xe_exec_queue_is_lr(q))
+ queue_work(guc_to_gt(guc)->ordered_wq, &q->guc->lr_tdr);
+ else
+ xe_sched_tdr_queue_imm(&q->guc->sched);
+}
+
+static void xe_guc_exec_queue_trigger_secondary_cleanup(struct xe_exec_queue *q)
+{
+ struct xe_exec_queue *primary = xe_exec_queue_multi_queue_primary(q);
+ struct xe_exec_queue_group *group = q->multi_queue.group;
+ struct xe_exec_queue *eq;
+
+ mutex_lock(&group->list_lock);
+ list_for_each_entry(eq, &group->list, multi_queue.link) {
+ if (exec_queue_reset(primary))
+ set_exec_queue_reset(eq);
+
+ if (!exec_queue_banned(eq))
+ xe_guc_exec_queue_trigger_cleanup(eq);
+ }
+ mutex_unlock(&group->list_lock);
+}
+
#define RESUME_PENDING ~0x0ull
static void submit_exec_queue(struct xe_exec_queue *q, struct xe_sched_job *job)
{
@@ -1104,20 +1179,6 @@ static void disable_scheduling_deregister(struct xe_guc *guc,
G2H_LEN_DW_DEREGISTER_CONTEXT, 2);
}
-static void xe_guc_exec_queue_trigger_cleanup(struct xe_exec_queue *q)
-{
- struct xe_guc *guc = exec_queue_to_guc(q);
- struct xe_device *xe = guc_to_xe(guc);
-
- /** to wakeup xe_wait_user_fence ioctl if exec queue is reset */
- wake_up_all(&xe->ufence_wq);
-
- if (xe_exec_queue_is_lr(q))
- queue_work(guc_to_gt(guc)->ordered_wq, &q->guc->lr_tdr);
- else
- xe_sched_tdr_queue_imm(&q->guc->sched);
-}
-
/**
* xe_guc_submit_wedge() - Wedge GuC submission
* @guc: the GuC object
@@ -1191,8 +1252,12 @@ static void xe_guc_exec_queue_lr_cleanup(struct work_struct *w)
if (!exec_queue_killed(q))
wedged = guc_submit_hint_wedged(exec_queue_to_guc(q));
- /* Kill the run_job / process_msg entry points */
- xe_sched_submission_stop(sched);
+ /*
+ * Kill the run_job / process_msg entry points.
+ * As this function is serialized across exec queues, it is safe to
+ * stop and restart submission on all queues of a multi queue group.
+ */
+ xe_guc_exec_queue_submission_stop(q);
/*
* Engine state now mostly stable, disable scheduling / deregister if
@@ -1228,7 +1293,7 @@ static void xe_guc_exec_queue_lr_cleanup(struct work_struct *w)
q->guc->id);
xe_devcoredump(q, NULL, "Schedule disable failed to respond, guc_id=%d\n",
q->guc->id);
- xe_sched_submission_start(sched);
+ xe_guc_exec_queue_submission_start(q);
xe_gt_reset_async(q->gt);
return;
}
@@ -1239,7 +1304,11 @@ static void xe_guc_exec_queue_lr_cleanup(struct work_struct *w)
xe_hw_fence_irq_stop(q->fence_irq);
- xe_sched_submission_start(sched);
+ xe_guc_exec_queue_submission_start(q);
+
+ /* Trigger cleanup of secondary queues of multi queue group */
+ if (xe_exec_queue_is_multi_queue_primary(q))
+ xe_guc_exec_queue_trigger_secondary_cleanup(q);
spin_lock(&sched->base.job_list_lock);
list_for_each_entry(job, &sched->base.pending_list, drm.list)
@@ -1398,8 +1467,12 @@ guc_exec_queue_timedout_job(struct drm_sched_job *drm_job)
vf_recovery(guc))
return DRM_GPU_SCHED_STAT_NO_HANG;
- /* Kill the run_job entry point */
- xe_sched_submission_stop(sched);
+ /*
+ * Kill the run_job entry point.
+ * As this function is serialized across exec queues, it is safe to
+ * stop and restart submission on all queues of a multi queue group.
+ */
+ xe_guc_exec_queue_submission_stop(q);
/* Must check all state after stopping scheduler */
skip_timeout_check = exec_queue_reset(q) ||
@@ -1558,7 +1631,7 @@ guc_exec_queue_timedout_job(struct drm_sched_job *drm_job)
* fences that are complete
*/
xe_sched_add_pending_job(sched, job);
- xe_sched_submission_start(sched);
+ xe_guc_exec_queue_submission_start(q);
xe_guc_exec_queue_trigger_cleanup(q);
@@ -1571,6 +1644,10 @@ guc_exec_queue_timedout_job(struct drm_sched_job *drm_job)
/* Start fence signaling */
xe_hw_fence_irq_start(q->fence_irq);
+ /* Trigger cleanup of secondary queues of multi queue group */
+ if (xe_exec_queue_is_multi_queue_primary(q))
+ xe_guc_exec_queue_trigger_secondary_cleanup(q);
+
return DRM_GPU_SCHED_STAT_RESET;
sched_enable:
@@ -1582,7 +1659,7 @@ guc_exec_queue_timedout_job(struct drm_sched_job *drm_job)
* but there is not currently an easy way to do in DRM scheduler. With
* some thought, do this in a follow up.
*/
- xe_sched_submission_start(sched);
+ xe_guc_exec_queue_submission_start(q);
handle_vf_resume:
return DRM_GPU_SCHED_STAT_NO_HANG;
}
@@ -1613,6 +1690,14 @@ static void __guc_exec_queue_destroy_async(struct work_struct *w)
xe_pm_runtime_get(guc_to_xe(guc));
trace_xe_exec_queue_destroy(q);
+ if (xe_exec_queue_is_multi_queue_secondary(q)) {
+ struct xe_exec_queue_group *group = q->multi_queue.group;
+
+ mutex_lock(&group->list_lock);
+ list_del(&q->multi_queue.link);
+ mutex_unlock(&group->list_lock);
+ }
+
if (xe_exec_queue_is_lr(q))
cancel_work_sync(&ge->lr_tdr);
/* Confirm no work left behind accessing device structures */
@@ -1903,6 +1988,19 @@ static int guc_exec_queue_init(struct xe_exec_queue *q)
xe_exec_queue_assign_name(q, q->guc->id);
+ /*
+ * Maintain secondary queues of the multi queue group in a list
+ * for handling dependencies across the queues in the group.
+ */
+ if (xe_exec_queue_is_multi_queue_secondary(q)) {
+ struct xe_exec_queue_group *group = q->multi_queue.group;
+
+ INIT_LIST_HEAD(&q->multi_queue.link);
+ mutex_lock(&group->list_lock);
+ list_add_tail(&q->multi_queue.link, &group->list);
+ mutex_unlock(&group->list_lock);
+ }
+
trace_xe_exec_queue_create(q);
return 0;
@@ -2130,6 +2228,10 @@ static void guc_exec_queue_resume(struct xe_exec_queue *q)
static bool guc_exec_queue_reset_status(struct xe_exec_queue *q)
{
+ if (xe_exec_queue_is_multi_queue_secondary(q) &&
+ guc_exec_queue_reset_status(xe_exec_queue_multi_queue_primary(q)))
+ return true;
+
return exec_queue_reset(q) || exec_queue_killed_or_banned_or_wedged(q);
}
--
2.43.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v2 10/16] drm/xe/multi_queue: Set QUEUE_DRAIN_MODE for Multi Queue batches
2025-11-04 18:51 [PATCH v2 00/16] drm/xe: Multi Queue feature support Niranjana Vishwanathapura
` (8 preceding siblings ...)
2025-11-04 18:51 ` [PATCH v2 09/16] drm/xe/multi_queue: Handle tearing down of a multi queue Niranjana Vishwanathapura
@ 2025-11-04 18:51 ` Niranjana Vishwanathapura
2025-11-04 18:51 ` [PATCH v2 11/16] drm/xe/multi_queue: Handle CGP context error Niranjana Vishwanathapura
` (9 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Niranjana Vishwanathapura @ 2025-11-04 18:51 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.brost
To properly support soft light restore between batches
being arbitrated at the CFEG, PIPE_CONTROL instructions
have a new bit in the first DW, QUEUE_DRAIN_MODE. When
set, this indicates to the CFEG that it should only
drain the current queue.
Additionally we no longer want to set the CS_STALL bit
for these multi queue queues as this causes the entire
pipeline to stall waiting for completion of the prior
batch, preventing this soft light restore from occurring
between queues in a queue group.
Bspec: 56551
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
---
.../gpu/drm/xe/instructions/xe_gpu_commands.h | 1 +
drivers/gpu/drm/xe/xe_ring_ops.c | 68 ++++++++++++-------
2 files changed, 45 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/xe/instructions/xe_gpu_commands.h b/drivers/gpu/drm/xe/instructions/xe_gpu_commands.h
index 5d41ca297447..885fcf211e6d 100644
--- a/drivers/gpu/drm/xe/instructions/xe_gpu_commands.h
+++ b/drivers/gpu/drm/xe/instructions/xe_gpu_commands.h
@@ -47,6 +47,7 @@
#define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2))
+#define PIPE_CONTROL0_QUEUE_DRAIN_MODE BIT(12)
#define PIPE_CONTROL0_L3_READ_ONLY_CACHE_INVALIDATE BIT(10) /* gen12 */
#define PIPE_CONTROL0_HDC_PIPELINE_FLUSH BIT(9) /* gen12 */
diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
index ac0c6dcffe15..71f0e19fe8ba 100644
--- a/drivers/gpu/drm/xe/xe_ring_ops.c
+++ b/drivers/gpu/drm/xe/xe_ring_ops.c
@@ -12,7 +12,7 @@
#include "regs/xe_engine_regs.h"
#include "regs/xe_gt_regs.h"
#include "regs/xe_lrc_layout.h"
-#include "xe_exec_queue_types.h"
+#include "xe_exec_queue.h"
#include "xe_gt.h"
#include "xe_lrc.h"
#include "xe_macros.h"
@@ -135,12 +135,11 @@ emit_pipe_control(u32 *dw, int i, u32 bit_group_0, u32 bit_group_1, u32 offset,
return i;
}
-static int emit_pipe_invalidate(u32 mask_flags, bool invalidate_tlb, u32 *dw,
- int i)
+static int emit_pipe_invalidate(struct xe_exec_queue *q, u32 mask_flags,
+ bool invalidate_tlb, u32 *dw, int i)
{
u32 flags0 = 0;
- u32 flags1 = PIPE_CONTROL_CS_STALL |
- PIPE_CONTROL_COMMAND_CACHE_INVALIDATE |
+ u32 flags1 = PIPE_CONTROL_COMMAND_CACHE_INVALIDATE |
PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE |
PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
PIPE_CONTROL_VF_CACHE_INVALIDATE |
@@ -152,6 +151,11 @@ static int emit_pipe_invalidate(u32 mask_flags, bool invalidate_tlb, u32 *dw,
if (invalidate_tlb)
flags1 |= PIPE_CONTROL_TLB_INVALIDATE;
+ if (xe_exec_queue_is_multi_queue(q))
+ flags0 |= PIPE_CONTROL0_QUEUE_DRAIN_MODE;
+ else
+ flags1 |= PIPE_CONTROL_CS_STALL;
+
flags1 &= ~mask_flags;
if (flags1 & PIPE_CONTROL_VF_CACHE_INVALIDATE)
@@ -175,54 +179,70 @@ static int emit_store_imm_ppgtt_posted(u64 addr, u64 value,
static int emit_render_cache_flush(struct xe_sched_job *job, u32 *dw, int i)
{
- struct xe_gt *gt = job->q->gt;
+ struct xe_exec_queue *q = job->q;
+ struct xe_gt *gt = q->gt;
bool lacks_render = !(gt->info.engine_mask & XE_HW_ENGINE_RCS_MASK);
- u32 flags;
+ u32 flags0, flags1;
if (XE_GT_WA(gt, 14016712196))
i = emit_pipe_control(dw, i, 0, PIPE_CONTROL_DEPTH_CACHE_FLUSH,
LRC_PPHWSP_FLUSH_INVAL_SCRATCH_ADDR, 0);
- flags = (PIPE_CONTROL_CS_STALL |
- PIPE_CONTROL_TILE_CACHE_FLUSH |
+ flags0 = PIPE_CONTROL0_HDC_PIPELINE_FLUSH;
+ flags1 = (PIPE_CONTROL_TILE_CACHE_FLUSH |
PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
PIPE_CONTROL_DC_FLUSH_ENABLE |
PIPE_CONTROL_FLUSH_ENABLE);
if (XE_GT_WA(gt, 1409600907))
- flags |= PIPE_CONTROL_DEPTH_STALL;
+ flags1 |= PIPE_CONTROL_DEPTH_STALL;
if (lacks_render)
- flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
+ flags1 &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
else if (job->q->class == XE_ENGINE_CLASS_COMPUTE)
- flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
+ flags1 &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
+
+ if (xe_exec_queue_is_multi_queue(q))
+ flags0 |= PIPE_CONTROL0_QUEUE_DRAIN_MODE;
+ else
+ flags1 |= PIPE_CONTROL_CS_STALL;
- return emit_pipe_control(dw, i, PIPE_CONTROL0_HDC_PIPELINE_FLUSH, flags, 0, 0);
+ return emit_pipe_control(dw, i, flags0, flags1, 0, 0);
}
-static int emit_pipe_control_to_ring_end(struct xe_hw_engine *hwe, u32 *dw, int i)
+static int emit_pipe_control_to_ring_end(struct xe_exec_queue *q, u32 *dw, int i)
{
+ u32 flags0 = 0, flags1 = PIPE_CONTROL_LRI_POST_SYNC;
+ struct xe_hw_engine *hwe = q->hwe;
+
if (hwe->class != XE_ENGINE_CLASS_RENDER)
return i;
+ if (xe_exec_queue_is_multi_queue(q))
+ flags0 |= PIPE_CONTROL0_QUEUE_DRAIN_MODE;
+
if (XE_GT_WA(hwe->gt, 16020292621))
- i = emit_pipe_control(dw, i, 0, PIPE_CONTROL_LRI_POST_SYNC,
+ i = emit_pipe_control(dw, i, flags0, flags1,
RING_NOPID(hwe->mmio_base).addr, 0);
return i;
}
-static int emit_pipe_imm_ggtt(u32 addr, u32 value, bool stall_only, u32 *dw,
- int i)
+static int emit_pipe_imm_ggtt(struct xe_exec_queue *q, u32 addr, u32 value,
+ bool stall_only, u32 *dw, int i)
{
- u32 flags = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_GLOBAL_GTT_IVB |
- PIPE_CONTROL_QW_WRITE;
+ u32 flags0 = 0, flags1 = PIPE_CONTROL_GLOBAL_GTT_IVB | PIPE_CONTROL_QW_WRITE;
if (!stall_only)
- flags |= PIPE_CONTROL_FLUSH_ENABLE;
+ flags1 |= PIPE_CONTROL_FLUSH_ENABLE;
+
+ if (xe_exec_queue_is_multi_queue(q))
+ flags0 |= PIPE_CONTROL0_QUEUE_DRAIN_MODE;
+ else
+ flags1 |= PIPE_CONTROL_CS_STALL;
- return emit_pipe_control(dw, i, 0, flags, addr, value);
+ return emit_pipe_control(dw, i, flags0, flags1, addr, value);
}
static u32 get_ppgtt_flag(struct xe_sched_job *job)
@@ -371,7 +391,7 @@ static void __emit_job_gen12_render_compute(struct xe_sched_job *job,
mask_flags = PIPE_CONTROL_3D_ENGINE_FLAGS;
/* See __xe_pt_bind_vma() for a discussion on TLB invalidations. */
- i = emit_pipe_invalidate(mask_flags, job->ring_ops_flush_tlb, dw, i);
+ i = emit_pipe_invalidate(job->q, mask_flags, job->ring_ops_flush_tlb, dw, i);
/* hsdes: 1809175790 */
if (has_aux_ccs(xe))
@@ -391,11 +411,11 @@ static void __emit_job_gen12_render_compute(struct xe_sched_job *job,
job->user_fence.value,
dw, i);
- i = emit_pipe_imm_ggtt(xe_lrc_seqno_ggtt_addr(lrc), seqno, lacks_render, dw, i);
+ i = emit_pipe_imm_ggtt(job->q, xe_lrc_seqno_ggtt_addr(lrc), seqno, lacks_render, dw, i);
i = emit_user_interrupt(dw, i);
- i = emit_pipe_control_to_ring_end(job->q->hwe, dw, i);
+ i = emit_pipe_control_to_ring_end(job->q, dw, i);
xe_gt_assert(gt, i <= MAX_JOB_SIZE_DW);
--
2.43.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v2 11/16] drm/xe/multi_queue: Handle CGP context error
2025-11-04 18:51 [PATCH v2 00/16] drm/xe: Multi Queue feature support Niranjana Vishwanathapura
` (9 preceding siblings ...)
2025-11-04 18:51 ` [PATCH v2 10/16] drm/xe/multi_queue: Set QUEUE_DRAIN_MODE for Multi Queue batches Niranjana Vishwanathapura
@ 2025-11-04 18:51 ` Niranjana Vishwanathapura
2025-11-04 18:51 ` [PATCH v2 12/16] drm/xe/multi_queue: Tracepoint support Niranjana Vishwanathapura
` (8 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Niranjana Vishwanathapura @ 2025-11-04 18:51 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.brost
Trigger multi-queue context cleanup upon CGP context error
notification from GuC.
Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
---
drivers/gpu/drm/xe/abi/guc_actions_abi.h | 1 +
drivers/gpu/drm/xe/xe_guc_ct.c | 4 +++
drivers/gpu/drm/xe/xe_guc_submit.c | 33 ++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_guc_submit.h | 2 ++
drivers/gpu/drm/xe/xe_trace.h | 5 ++++
5 files changed, 45 insertions(+)
diff --git a/drivers/gpu/drm/xe/abi/guc_actions_abi.h b/drivers/gpu/drm/xe/abi/guc_actions_abi.h
index 3e9fbed9cda6..8af3691626bf 100644
--- a/drivers/gpu/drm/xe/abi/guc_actions_abi.h
+++ b/drivers/gpu/drm/xe/abi/guc_actions_abi.h
@@ -142,6 +142,7 @@ enum xe_guc_action {
XE_GUC_ACTION_REGISTER_CONTEXT_MULTI_QUEUE = 0x4602,
XE_GUC_ACTION_MULTI_QUEUE_CONTEXT_CGP_SYNC = 0x4603,
XE_GUC_ACTION_NOTIFY_MULTI_QUEUE_CONTEXT_CGP_SYNC_DONE = 0x4604,
+ XE_GUC_ACTION_NOTIFY_MULTI_QUEUE_CGP_CONTEXT_ERROR = 0x4605,
XE_GUC_ACTION_CLIENT_SOFT_RESET = 0x5507,
XE_GUC_ACTION_SET_ENG_UTIL_BUFF = 0x550A,
XE_GUC_ACTION_SET_DEVICE_ENGINE_ACTIVITY_BUFFER = 0x550C,
diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c b/drivers/gpu/drm/xe/xe_guc_ct.c
index 43a79bcdfb18..384a724421cd 100644
--- a/drivers/gpu/drm/xe/xe_guc_ct.c
+++ b/drivers/gpu/drm/xe/xe_guc_ct.c
@@ -1573,6 +1573,10 @@ static int process_g2h_msg(struct xe_guc_ct *ct, u32 *msg, u32 len)
case XE_GUC_ACTION_NOTIFY_MULTI_QUEUE_CONTEXT_CGP_SYNC_DONE:
ret = xe_guc_exec_queue_cgp_sync_done_handler(guc, payload, adj_len);
break;
+ case XE_GUC_ACTION_NOTIFY_MULTI_QUEUE_CGP_CONTEXT_ERROR:
+ ret = xe_guc_exec_queue_cgp_context_error_handler(guc, payload,
+ adj_len);
+ break;
default:
xe_gt_err(gt, "unexpected G2H action 0x%04x\n", action);
}
diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
index b5ea86069d49..c54175619342 100644
--- a/drivers/gpu/drm/xe/xe_guc_submit.c
+++ b/drivers/gpu/drm/xe/xe_guc_submit.c
@@ -48,6 +48,8 @@
#include "xe_uc_fw.h"
#include "xe_vm.h"
+#define XE_GUC_EXEC_QUEUE_CGP_CONTEXT_ERROR_LEN 6
+
static struct xe_guc *
exec_queue_to_guc(struct xe_exec_queue *q)
{
@@ -3003,6 +3005,37 @@ int xe_guc_exec_queue_reset_failure_handler(struct xe_guc *guc, u32 *msg, u32 le
return 0;
}
+int xe_guc_exec_queue_cgp_context_error_handler(struct xe_guc *guc, u32 *msg,
+ u32 len)
+{
+ struct xe_gt *gt = guc_to_gt(guc);
+ struct xe_device *xe = guc_to_xe(guc);
+ struct xe_exec_queue *q;
+ u32 guc_id = msg[2];
+
+ if (unlikely(len != XE_GUC_EXEC_QUEUE_CGP_CONTEXT_ERROR_LEN)) {
+ drm_err(&xe->drm, "Invalid length %u", len);
+ return -EPROTO;
+ }
+
+ q = g2h_exec_queue_lookup(guc, guc_id);
+ if (unlikely(!q))
+ return -EPROTO;
+
+ xe_gt_dbg(gt,
+ "CGP context error: region=%s err=0x%x, context=0x%x LRCA=0x%x:0x%x SgId=0x%x",
+ msg[0] & 1 ? "uc" : "kmd", msg[1], msg[2], msg[4], msg[3], msg[5]);
+
+ trace_xe_exec_queue_cgp_context_error(q);
+
+ /* Treat the same as engine reset */
+ set_exec_queue_reset(q);
+ if (!exec_queue_banned(q) && !exec_queue_check_timeout(q))
+ xe_guc_exec_queue_trigger_cleanup(q);
+
+ return 0;
+}
+
/**
* xe_guc_exec_queue_cgp_sync_done_handler - CGP synchronization done handler
* @guc: guc
diff --git a/drivers/gpu/drm/xe/xe_guc_submit.h b/drivers/gpu/drm/xe/xe_guc_submit.h
index abfa94bce391..01b013a90b1b 100644
--- a/drivers/gpu/drm/xe/xe_guc_submit.h
+++ b/drivers/gpu/drm/xe/xe_guc_submit.h
@@ -35,6 +35,8 @@ int xe_guc_exec_queue_memory_cat_error_handler(struct xe_guc *guc, u32 *msg,
int xe_guc_exec_queue_reset_failure_handler(struct xe_guc *guc, u32 *msg, u32 len);
int xe_guc_error_capture_handler(struct xe_guc *guc, u32 *msg, u32 len);
int xe_guc_exec_queue_cgp_sync_done_handler(struct xe_guc *guc, u32 *msg, u32 len);
+int xe_guc_exec_queue_cgp_context_error_handler(struct xe_guc *guc, u32 *msg,
+ u32 len);
struct xe_guc_submit_exec_queue_snapshot *
xe_guc_exec_queue_snapshot_capture(struct xe_exec_queue *q);
diff --git a/drivers/gpu/drm/xe/xe_trace.h b/drivers/gpu/drm/xe/xe_trace.h
index 79a97b086cb2..c9d0748dae9d 100644
--- a/drivers/gpu/drm/xe/xe_trace.h
+++ b/drivers/gpu/drm/xe/xe_trace.h
@@ -172,6 +172,11 @@ DEFINE_EVENT(xe_exec_queue, xe_exec_queue_memory_cat_error,
TP_ARGS(q)
);
+DEFINE_EVENT(xe_exec_queue, xe_exec_queue_cgp_context_error,
+ TP_PROTO(struct xe_exec_queue *q),
+ TP_ARGS(q)
+);
+
DEFINE_EVENT(xe_exec_queue, xe_exec_queue_stop,
TP_PROTO(struct xe_exec_queue *q),
TP_ARGS(q)
--
2.43.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v2 12/16] drm/xe/multi_queue: Tracepoint support
2025-11-04 18:51 [PATCH v2 00/16] drm/xe: Multi Queue feature support Niranjana Vishwanathapura
` (10 preceding siblings ...)
2025-11-04 18:51 ` [PATCH v2 11/16] drm/xe/multi_queue: Handle CGP context error Niranjana Vishwanathapura
@ 2025-11-04 18:51 ` Niranjana Vishwanathapura
2025-11-04 18:51 ` [PATCH v2 13/16] drm/xe/multi_queue: Support active group after primary is destroyed Niranjana Vishwanathapura
` (7 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Niranjana Vishwanathapura @ 2025-11-04 18:51 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.brost
Add xe_exec_queue_create_multi_queue event with
multi-queue information.
Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
---
drivers/gpu/drm/xe/xe_guc_submit.c | 5 +++-
drivers/gpu/drm/xe/xe_trace.h | 41 ++++++++++++++++++++++++++++++
2 files changed, 45 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
index c54175619342..d49775c1cf5e 100644
--- a/drivers/gpu/drm/xe/xe_guc_submit.c
+++ b/drivers/gpu/drm/xe/xe_guc_submit.c
@@ -2003,7 +2003,10 @@ static int guc_exec_queue_init(struct xe_exec_queue *q)
mutex_unlock(&group->list_lock);
}
- trace_xe_exec_queue_create(q);
+ if (xe_exec_queue_is_multi_queue(q))
+ trace_xe_exec_queue_create_multi_queue(q);
+ else
+ trace_xe_exec_queue_create(q);
return 0;
diff --git a/drivers/gpu/drm/xe/xe_trace.h b/drivers/gpu/drm/xe/xe_trace.h
index c9d0748dae9d..6d12fcc13f43 100644
--- a/drivers/gpu/drm/xe/xe_trace.h
+++ b/drivers/gpu/drm/xe/xe_trace.h
@@ -13,6 +13,7 @@
#include <linux/types.h>
#include "xe_exec_queue_types.h"
+#include "xe_exec_queue.h"
#include "xe_gpu_scheduler_types.h"
#include "xe_gt_types.h"
#include "xe_guc_exec_queue_types.h"
@@ -97,11 +98,51 @@ DECLARE_EVENT_CLASS(xe_exec_queue,
__entry->guc_state, __entry->flags)
);
+DECLARE_EVENT_CLASS(xe_exec_queue_multi_queue,
+ TP_PROTO(struct xe_exec_queue *q),
+ TP_ARGS(q),
+
+ TP_STRUCT__entry(
+ __string(dev, __dev_name_eq(q))
+ __field(enum xe_engine_class, class)
+ __field(u32, logical_mask)
+ __field(u8, gt_id)
+ __field(u16, width)
+ __field(u32, guc_id)
+ __field(u32, guc_state)
+ __field(u32, flags)
+ __field(u32, primary)
+ ),
+
+ TP_fast_assign(
+ __assign_str(dev);
+ __entry->class = q->class;
+ __entry->logical_mask = q->logical_mask;
+ __entry->gt_id = q->gt->info.id;
+ __entry->width = q->width;
+ __entry->guc_id = q->guc->id;
+ __entry->guc_state = atomic_read(&q->guc->state);
+ __entry->flags = q->flags;
+ __entry->primary = xe_exec_queue_multi_queue_primary(q)->guc->id;
+ ),
+
+ TP_printk("dev=%s, %d:0x%x, gt=%d, width=%d guc_id=%d, guc_state=0x%x, flags=0x%x, primary=%d",
+ __get_str(dev), __entry->class, __entry->logical_mask,
+ __entry->gt_id, __entry->width, __entry->guc_id,
+ __entry->guc_state, __entry->flags,
+ __entry->primary)
+);
+
DEFINE_EVENT(xe_exec_queue, xe_exec_queue_create,
TP_PROTO(struct xe_exec_queue *q),
TP_ARGS(q)
);
+DEFINE_EVENT(xe_exec_queue_multi_queue, xe_exec_queue_create_multi_queue,
+ TP_PROTO(struct xe_exec_queue *q),
+ TP_ARGS(q)
+);
+
DEFINE_EVENT(xe_exec_queue, xe_exec_queue_supress_resume,
TP_PROTO(struct xe_exec_queue *q),
TP_ARGS(q)
--
2.43.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v2 13/16] drm/xe/multi_queue: Support active group after primary is destroyed
2025-11-04 18:51 [PATCH v2 00/16] drm/xe: Multi Queue feature support Niranjana Vishwanathapura
` (11 preceding siblings ...)
2025-11-04 18:51 ` [PATCH v2 12/16] drm/xe/multi_queue: Tracepoint support Niranjana Vishwanathapura
@ 2025-11-04 18:51 ` Niranjana Vishwanathapura
2025-11-04 18:51 ` [PATCH v2 14/16] drm/xe/doc: Add documentation for Multi Queue Group Niranjana Vishwanathapura
` (6 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Niranjana Vishwanathapura @ 2025-11-04 18:51 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.brost
Add support to keep the group active after the primary queue is
destroyed. Instead of killing the primary queue during exec_queue
destroy ioctl, kill it when all the secondary queues of the group
are killed.
Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
---
drivers/gpu/drm/xe/xe_device.c | 7 ++-
drivers/gpu/drm/xe/xe_exec_queue.c | 55 +++++++++++++++++++++++-
drivers/gpu/drm/xe/xe_exec_queue.h | 2 +
drivers/gpu/drm/xe/xe_exec_queue_types.h | 4 ++
include/uapi/drm/xe_drm.h | 4 ++
5 files changed, 69 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index 391b2f9a2846..229278635551 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -177,7 +177,12 @@ static void xe_file_close(struct drm_device *dev, struct drm_file *file)
xa_for_each(&xef->exec_queue.xa, idx, q) {
if (q->vm && q->hwe->hw_engine_group)
xe_hw_engine_group_del_exec_queue(q->hwe->hw_engine_group, q);
- xe_exec_queue_kill(q);
+
+ if (xe_exec_queue_is_multi_queue_primary(q))
+ xe_exec_queue_group_kill_put(q->multi_queue.group);
+ else
+ xe_exec_queue_kill(q);
+
xe_exec_queue_put(q);
}
xa_for_each(&xef->vm.xa, idx, vm)
diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
index f86f8198aedb..52e54db1c5ad 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue.c
+++ b/drivers/gpu/drm/xe/xe_exec_queue.c
@@ -417,6 +417,26 @@ struct xe_exec_queue *xe_exec_queue_create_bind(struct xe_device *xe,
}
ALLOW_ERROR_INJECTION(xe_exec_queue_create_bind, ERRNO);
+static void xe_exec_queue_group_kill(struct kref *ref)
+{
+ struct xe_exec_queue_group *group = container_of(ref, struct xe_exec_queue_group,
+ kill_refcount);
+ xe_exec_queue_kill(group->primary);
+}
+
+static inline void xe_exec_queue_group_kill_get(struct xe_exec_queue_group *group)
+{
+ kref_get(&group->kill_refcount);
+}
+
+void xe_exec_queue_group_kill_put(struct xe_exec_queue_group *group)
+{
+ if (!group)
+ return;
+
+ kref_put(&group->kill_refcount, xe_exec_queue_group_kill);
+}
+
void xe_exec_queue_destroy(struct kref *ref)
{
struct xe_exec_queue *q = container_of(ref, struct xe_exec_queue, refcount);
@@ -626,6 +646,7 @@ static int xe_exec_queue_group_init(struct xe_device *xe, struct xe_exec_queue *
group->primary = q;
group->cgp_bo = bo;
INIT_LIST_HEAD(&group->list);
+ kref_init(&group->kill_refcount);
xa_init_flags(&group->xa, XA_FLAGS_ALLOC1);
mutex_init(&group->list_lock);
q->multi_queue.group = group;
@@ -701,6 +722,11 @@ static int xe_exec_queue_group_add(struct xe_device *xe, struct xe_exec_queue *q
q->multi_queue.pos = pos;
+ if (group->primary->multi_queue.keep_active) {
+ xe_exec_queue_group_kill_get(group);
+ q->multi_queue.keep_active = true;
+ }
+
return 0;
}
@@ -714,6 +740,11 @@ static void xe_exec_queue_group_delete(struct xe_device *xe, struct xe_exec_queu
lrc = xa_erase(&group->xa, q->multi_queue.pos);
xe_assert(xe, lrc);
xe_lrc_put(lrc);
+
+ if (q->multi_queue.keep_active) {
+ xe_exec_queue_group_kill_put(group);
+ q->multi_queue.keep_active = false;
+ }
}
static int exec_queue_set_multi_group(struct xe_device *xe, struct xe_exec_queue *q,
@@ -732,12 +763,24 @@ static int exec_queue_set_multi_group(struct xe_device *xe, struct xe_exec_queue
return -EINVAL;
if (value & DRM_XE_MULTI_GROUP_CREATE) {
- if (XE_IOCTL_DBG(xe, value & ~DRM_XE_MULTI_GROUP_CREATE))
+ if (XE_IOCTL_DBG(xe, value & ~(DRM_XE_MULTI_GROUP_CREATE |
+ DRM_XE_MULTI_GROUP_KEEP_ACTIVE)))
+ return -EINVAL;
+
+ /*
+ * KEEP_ACTIVE is not supported in preempt fence mode as in that mode,
+ * VM_DESTROY ioctl expects all exec queues of that VM are already killed.
+ */
+ if (XE_IOCTL_DBG(xe, (value & DRM_XE_MULTI_GROUP_KEEP_ACTIVE) &&
+ xe_vm_in_preempt_fence_mode(q->vm)))
return -EINVAL;
q->multi_queue.valid = true;
q->multi_queue.is_primary = true;
q->multi_queue.pos = 0;
+ if (value & DRM_XE_MULTI_GROUP_KEEP_ACTIVE)
+ q->multi_queue.keep_active = true;
+
return 0;
}
@@ -1283,6 +1326,11 @@ void xe_exec_queue_kill(struct xe_exec_queue *q)
q->ops->kill(q);
xe_vm_remove_compute_exec_queue(q->vm, q);
+
+ if (!xe_exec_queue_is_multi_queue_primary(q) && q->multi_queue.keep_active) {
+ xe_exec_queue_group_kill_put(q->multi_queue.group);
+ q->multi_queue.keep_active = false;
+ }
}
int xe_exec_queue_destroy_ioctl(struct drm_device *dev, void *data,
@@ -1309,7 +1357,10 @@ int xe_exec_queue_destroy_ioctl(struct drm_device *dev, void *data,
if (q->vm && q->hwe->hw_engine_group)
xe_hw_engine_group_del_exec_queue(q->hwe->hw_engine_group, q);
- xe_exec_queue_kill(q);
+ if (xe_exec_queue_is_multi_queue_primary(q))
+ xe_exec_queue_group_kill_put(q->multi_queue.group);
+ else
+ xe_exec_queue_kill(q);
trace_xe_exec_queue_close(q);
xe_exec_queue_put(q);
diff --git a/drivers/gpu/drm/xe/xe_exec_queue.h b/drivers/gpu/drm/xe/xe_exec_queue.h
index ffcc1feb879e..10abed98fb6b 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue.h
+++ b/drivers/gpu/drm/xe/xe_exec_queue.h
@@ -113,6 +113,8 @@ static inline struct xe_exec_queue *xe_exec_queue_multi_queue_primary(struct xe_
return xe_exec_queue_is_multi_queue(q) ? q->multi_queue.group->primary : q;
}
+void xe_exec_queue_group_kill_put(struct xe_exec_queue_group *group);
+
bool xe_exec_queue_is_lr(struct xe_exec_queue *q);
bool xe_exec_queue_is_idle(struct xe_exec_queue *q);
diff --git a/drivers/gpu/drm/xe/xe_exec_queue_types.h b/drivers/gpu/drm/xe/xe_exec_queue_types.h
index 5721fb4bad1a..c6b80977ff4f 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue_types.h
+++ b/drivers/gpu/drm/xe/xe_exec_queue_types.h
@@ -62,6 +62,8 @@ struct xe_exec_queue_group {
struct list_head list;
/** @list_lock: Secondary queue list lock */
struct mutex list_lock;
+ /** @kill_refcount: ref count to kill primary queue */
+ struct kref kill_refcount;
/** @sync_pending: CGP_SYNC_DONE g2h response pending */
bool sync_pending;
};
@@ -159,6 +161,8 @@ struct xe_exec_queue {
u8 valid:1;
/** @multi_queue.is_primary: Is primary queue (Q0) of the group */
u8 is_primary:1;
+ /** @multi_queue.keep_active: Keep the group active after primary is destroyed */
+ u8 keep_active:1;
} multi_queue;
/** @sched_props: scheduling properties */
diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
index d5162a3a89db..3df93e3c556a 100644
--- a/include/uapi/drm/xe_drm.h
+++ b/include/uapi/drm/xe_drm.h
@@ -1260,6 +1260,9 @@ struct drm_xe_vm_bind {
* then a new multi-queue group is created with this queue as the primary queue
* (Q0). Otherwise, the queue gets added to the multi-queue group whose primary
* queue's exec_queue_id is specified in the lower 32 bits of the 'value' field.
+ * If the extension's 'value' field has %DRM_XE_MULTI_GROUP_KEEP_ACTIVE flag
+ * set, then the multi-queue group is kept active after the primary queue is
+ * destroyed.
* All the other non-relevant bits of extension's 'value' field while adding the
* primary or the secondary queues of the group must be set to 0.
* - %DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY - Set the queue
@@ -1306,6 +1309,7 @@ struct drm_xe_exec_queue_create {
#define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE 2
#define DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP 3
#define DRM_XE_MULTI_GROUP_CREATE (1ull << 63)
+#define DRM_XE_MULTI_GROUP_KEEP_ACTIVE (1ull << 62)
#define DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY 4
/** @extensions: Pointer to the first extension struct, if any */
__u64 extensions;
--
2.43.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v2 14/16] drm/xe/doc: Add documentation for Multi Queue Group
2025-11-04 18:51 [PATCH v2 00/16] drm/xe: Multi Queue feature support Niranjana Vishwanathapura
` (12 preceding siblings ...)
2025-11-04 18:51 ` [PATCH v2 13/16] drm/xe/multi_queue: Support active group after primary is destroyed Niranjana Vishwanathapura
@ 2025-11-04 18:51 ` Niranjana Vishwanathapura
2025-11-04 18:51 ` [PATCH v2 15/16] drm/xe/doc: Add documentation for Multi Queue Group GuC interface Niranjana Vishwanathapura
` (5 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Niranjana Vishwanathapura @ 2025-11-04 18:51 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.brost
Add kernel documentation for Multi Queue group and update
the corresponding rst.
Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
---
Documentation/gpu/xe/xe_exec_queue.rst | 6 ++++
drivers/gpu/drm/xe/xe_exec_queue.c | 45 ++++++++++++++++++++++++++
2 files changed, 51 insertions(+)
diff --git a/Documentation/gpu/xe/xe_exec_queue.rst b/Documentation/gpu/xe/xe_exec_queue.rst
index 6076569e311c..732af4741df4 100644
--- a/Documentation/gpu/xe/xe_exec_queue.rst
+++ b/Documentation/gpu/xe/xe_exec_queue.rst
@@ -7,6 +7,12 @@ Execution Queue
.. kernel-doc:: drivers/gpu/drm/xe/xe_exec_queue.c
:doc: Execution Queue
+Multi Queue Group
+=================
+
+.. kernel-doc:: drivers/gpu/drm/xe/xe_exec_queue.c
+ :doc: Multi Queue Group
+
Internal API
============
diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
index 52e54db1c5ad..525cb3821e6c 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue.c
+++ b/drivers/gpu/drm/xe/xe_exec_queue.c
@@ -54,6 +54,51 @@
* the ring operations the different engine classes support.
*/
+/**
+ * DOC: Multi Queue Group
+ *
+ * Multi Queue Group is another mode of execution supported by the compute
+ * and blitter copy command streamers (CCS and BCS, respectively). It is
+ * an enhancement of the existing hardware architecture and leverages the
+ * same submission model. It enables support for efficient, parallel
+ * execution of multiple queues within a single shared context. The multi
+ * queue group functionality is only supported with GuC submission backend.
+ * All the queues of a group must use the same address space (VM).
+ *
+ * The DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE execution queue property
+ * supports creating a multi queue group and adding queues to a queue group.
+ *
+ * The XE_EXEC_QUEUE_CREATE ioctl call with above property with value field
+ * set to DRM_XE_MULTI_GROUP_CREATE, will create a new multi queue group with
+ * the queue being created as the primary queue (aka q0) of the group. To add
+ * secondary queues to the group, they need to be created with the above
+ * property with id of the primary queue as the value. The properties of
+ * the primary queue (like priority, time slice) applies to the whole group.
+ * So, these properties can't be set for secondary queues of a group.
+ *
+ * The hardware does not support removing a queue from a multi-queue group.
+ * However, queues can be dynamically added to the group. A group can have
+ * up to 64 queues. To support this, XeKMD holds references to LRCs of the
+ * queues even after the queues are destroyed by the user until the whole
+ * group is destroyed. The secondary queues hold a reference to the primary
+ * queue thus preventing the group from being destroyed when user destroys
+ * the primary queue. Once the primary queue is destroyed, secondary queues
+ * can't be added to the queue group, but they can continue to submit the
+ * jobs if the DRM_XE_MULTI_GROUP_KEEP_ACTIVE flag is set during the multi
+ * queue group creation.
+ *
+ * The queues of a multi queue group can set their priority within the group
+ * through the DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY property.
+ * This multi queue priority can also be set dynamically through the
+ * XE_EXEC_QUEUE_SET_PROPERTY ioctl. This is the only other property
+ * supported by the secondary queues of a multi queue group, other than
+ * DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE.
+ *
+ * When GuC reports an error on any of the queues of a multi queue group,
+ * the queue cleanup mechanism is invoked for all the queues of the group
+ * as hardware cannot make progress on the multi queue context.
+ */
+
enum xe_exec_queue_sched_prop {
XE_EXEC_QUEUE_JOB_TIMEOUT = 0,
XE_EXEC_QUEUE_TIMESLICE = 1,
--
2.43.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v2 15/16] drm/xe/doc: Add documentation for Multi Queue Group GuC interface
2025-11-04 18:51 [PATCH v2 00/16] drm/xe: Multi Queue feature support Niranjana Vishwanathapura
` (13 preceding siblings ...)
2025-11-04 18:51 ` [PATCH v2 14/16] drm/xe/doc: Add documentation for Multi Queue Group Niranjana Vishwanathapura
@ 2025-11-04 18:51 ` Niranjana Vishwanathapura
2025-11-04 18:51 ` [PATCH v2 16/16] drm/xe/multi_queue: Enable multi_queue on xe3p_xpc Niranjana Vishwanathapura
` (4 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Niranjana Vishwanathapura @ 2025-11-04 18:51 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.brost
Add kernel documentation for Multi Queue group GuC interface.
Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
---
Documentation/gpu/xe/xe_exec_queue.rst | 8 ++++
drivers/gpu/drm/xe/xe_exec_queue.c | 3 ++
drivers/gpu/drm/xe/xe_guc_submit.c | 57 ++++++++++++++++++++++++++
3 files changed, 68 insertions(+)
diff --git a/Documentation/gpu/xe/xe_exec_queue.rst b/Documentation/gpu/xe/xe_exec_queue.rst
index 732af4741df4..8707806211c9 100644
--- a/Documentation/gpu/xe/xe_exec_queue.rst
+++ b/Documentation/gpu/xe/xe_exec_queue.rst
@@ -13,6 +13,14 @@ Multi Queue Group
.. kernel-doc:: drivers/gpu/drm/xe/xe_exec_queue.c
:doc: Multi Queue Group
+.. _multi-queue-group-guc-interface:
+
+Multi Queue Group GuC interface
+===============================
+
+.. kernel-doc:: drivers/gpu/drm/xe/xe_guc_submit.c
+ :doc: Multi Queue Group GuC interface
+
Internal API
============
diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
index 525cb3821e6c..6d8c0b3006a2 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue.c
+++ b/drivers/gpu/drm/xe/xe_exec_queue.c
@@ -97,6 +97,9 @@
* When GuC reports an error on any of the queues of a multi queue group,
* the queue cleanup mechanism is invoked for all the queues of the group
* as hardware cannot make progress on the multi queue context.
+ *
+ * Refer :ref:`multi-queue-group-guc-interface` for multi queue group GuC
+ * interface.
*/
enum xe_exec_queue_sched_prop {
diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
index d49775c1cf5e..50ec721f60be 100644
--- a/drivers/gpu/drm/xe/xe_guc_submit.c
+++ b/drivers/gpu/drm/xe/xe_guc_submit.c
@@ -581,6 +581,63 @@ static void set_min_preemption_timeout(struct xe_guc *guc, struct xe_exec_queue
xe_map_wr_field(xe_, &map_, 0, struct guc_submit_parallel_scratch, \
field_, val_)
+/**
+ * DOC: Multi Queue Group GuC interface
+ *
+ * The multi queue group coordination between KMD and GuC is through a software
+ * construct called Context Group Page (CGP). The CGP is a KMD managed 4KB page
+ * allocated in the global GTT.
+ *
+ * CGP format:
+ *
+ * +-----------+---------------------------+---------------------------------------------+
+ * | DWORD | Name | Description |
+ * +-----------+---------------------------+---------------------------------------------+
+ * | 0 | Version | Bits [15:8]=Major ver, [7:0]=Minor ver |
+ * +-----------+---------------------------+---------------------------------------------+
+ * | 1..15 | RESERVED | MBZ |
+ * +-----------+---------------------------+---------------------------------------------+
+ * | 16 | KMD_QUEUE_UPDATE_MASK_DW0 | KMD queue mask for queues 31..0 |
+ * +-----------+---------------------------+---------------------------------------------+
+ * | 17 | KMD_QUEUE_UPDATE_MASK_DW1 | KMD queue mask for queues 63..32 |
+ * +-----------+---------------------------+---------------------------------------------+
+ * | 18..31 | RESERVED | MBZ |
+ * +-----------+---------------------------+---------------------------------------------+
+ * | 32 | Q0CD_DW0 | Queue 0 context LRC descriptor lower DWORD |
+ * +-----------+---------------------------+---------------------------------------------+
+ * | 33 | Q0ContextIndex | Context ID for Queue 0 |
+ * +-----------+---------------------------+---------------------------------------------+
+ * | 34 | Q1CD_DW0 | Queue 1 context LRC descriptor lower DWORD |
+ * +-----------+---------------------------+---------------------------------------------+
+ * | 35 | Q1ContextIndex | Context ID for Queue 1 |
+ * +-----------+---------------------------+---------------------------------------------+
+ * | ... |... | ... |
+ * +-----------+---------------------------+---------------------------------------------+
+ * | 158 | Q63CD_DW0 | Queue 63 context LRC descriptor lower DWORD |
+ * +-----------+---------------------------+---------------------------------------------+
+ * | 159 | Q63ContextIndex | Context ID for Queue 63 |
+ * +-----------+---------------------------+---------------------------------------------+
+ * | 160..1024 | RESERVED | MBZ |
+ * +-----------+---------------------------+---------------------------------------------+
+ *
+ * While registering Q0 with GuC, CGP is updated with Q0 entry and GuC is notified
+ * through XE_GUC_ACTION_REGISTER_CONTEXT_MULTI_QUEUE H2G message which specifies
+ * the CGP address. When the secondary queues are added to the group, the CGP is
+ * updated with entry for that queue and GuC is notified through the H2G interface
+ * XE_GUC_ACTION_MULTI_QUEUE_CONTEXT_CGP_SYNC. GuC responds to these H2G messages
+ * with a XE_GUC_ACTION_NOTIFY_MULTIQ_CONTEXT_CGP_SYNC_DONE G2H message. GuC also
+ * sends a XE_GUC_ACTION_NOTIFY_MULTI_QUEUE_CGP_CONTEXT_ERROR notification for any
+ * error in the CGP. Only one of these CGP update messages can be outstanding
+ * (waiting for GuC response) at any time. The bits in KMD_QUEUE_UPDATE_MASK_DW*
+ * fields indicate which queue entry is being updated in the CGP.
+ *
+ * The primary queue (Q0) represents the multi queue group context in GuC and
+ * submission on any queue of the group must be through Q0 GuC interface only.
+ *
+ * As it is not required to register secondary queues with GuC, the secondary queue
+ * context ids in the CGP are populated with Q0 context id.
+ */
+
#define CGP_VERSION_MAJOR_SHIFT 8
static void xe_guc_exec_queue_group_cgp_update(struct xe_device *xe,
--
2.43.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v2 16/16] drm/xe/multi_queue: Enable multi_queue on xe3p_xpc
2025-11-04 18:51 [PATCH v2 00/16] drm/xe: Multi Queue feature support Niranjana Vishwanathapura
` (14 preceding siblings ...)
2025-11-04 18:51 ` [PATCH v2 15/16] drm/xe/doc: Add documentation for Multi Queue Group GuC interface Niranjana Vishwanathapura
@ 2025-11-04 18:51 ` Niranjana Vishwanathapura
2025-11-04 23:16 ` ✗ CI.checkpatch: warning for drm/xe: Multi Queue feature support (rev2) Patchwork
` (3 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Niranjana Vishwanathapura @ 2025-11-04 18:51 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.brost
xe3p_xpc supports multi_queue, enable it.
v2: Rename multi_queue_enable_mask to multi_queue_engine_class_mask
(Matt Brost)
Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
---
drivers/gpu/drm/xe/xe_pci.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 927d3a62c02d..d375f0c0395e 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -111,6 +111,8 @@ static const struct xe_graphics_desc graphics_xe3p_xpc = {
.hw_engine_mask =
GENMASK(XE_HW_ENGINE_BCS8, XE_HW_ENGINE_BCS1) |
GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0),
+ .multi_queue_engine_class_mask = BIT(XE_ENGINE_CLASS_COPY) |
+ BIT(XE_ENGINE_CLASS_COMPUTE),
};
static const struct xe_media_desc media_xem = {
--
2.43.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* ✗ CI.checkpatch: warning for drm/xe: Multi Queue feature support (rev2)
2025-11-04 18:51 [PATCH v2 00/16] drm/xe: Multi Queue feature support Niranjana Vishwanathapura
` (15 preceding siblings ...)
2025-11-04 18:51 ` [PATCH v2 16/16] drm/xe/multi_queue: Enable multi_queue on xe3p_xpc Niranjana Vishwanathapura
@ 2025-11-04 23:16 ` Patchwork
2025-11-04 23:18 ` ✓ CI.KUnit: success " Patchwork
` (2 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2025-11-04 23:16 UTC (permalink / raw)
To: Niranjana Vishwanathapura; +Cc: intel-xe
== Series Details ==
Series: drm/xe: Multi Queue feature support (rev2)
URL : https://patchwork.freedesktop.org/series/156865/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
f867e605613af1770f90c4b0afd4a8f06424d1f0
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 231aa8a462e5d9f63ab458c1e294431031cfc5e6
Author: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Date: Tue Nov 4 10:51:50 2025 -0800
drm/xe/multi_queue: Enable multi_queue on xe3p_xpc
xe3p_xpc supports multi_queue, enable it.
v2: Rename multi_queue_enable_mask to multi_queue_engine_class_mask
(Matt Brost)
Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
+ /mt/dim checkpatch 957ab9ac657700dee50f42438ed79652dad939a0 drm-intel
94a2a1b50dee drm/xe/multi_queue: Add multi_queue_enable_mask to gt information
f57cb9b50165 drm/xe/multi_queue: Add user interface for multi queue support
f149e62b42da drm/xe/multi_queue: Add GuC interface for multi queue support
d41436ff4587 drm/xe/multi_queue: Add multi queue priority property
41c623c4ff89 drm/xe/multi_queue: Handle invalid exec queue property setting
eb08c903e190 drm/xe/multi_queue: Add exec_queue set_property ioctl support
-:109: WARNING:LONG_LINE: line length of 145 exceeds 100 columns
#109: FILE: include/uapi/drm/xe_drm.h:127:
+#define DRM_IOCTL_XE_EXEC_QUEUE_SET_PROPERTY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_SET_PROPERTY, struct drm_xe_exec_queue_set_property)
total: 0 errors, 1 warnings, 0 checks, 101 lines checked
e6d62a872d11 drm/xe/multi_queue: Add support for multi queue dynamic priority change
0faf37506924 drm/xe/multi_queue: Add multi queue information to guc_info dump
1f1b739ce223 drm/xe/multi_queue: Handle tearing down of a multi queue
994f4a47c885 drm/xe/multi_queue: Set QUEUE_DRAIN_MODE for Multi Queue batches
42996778255d drm/xe/multi_queue: Handle CGP context error
dfe62c113ffa drm/xe/multi_queue: Tracepoint support
-:48: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#48: FILE: drivers/gpu/drm/xe/xe_trace.h:105:
+ TP_STRUCT__entry(
-:60: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#60: FILE: drivers/gpu/drm/xe/xe_trace.h:117:
+ TP_fast_assign(
total: 0 errors, 0 warnings, 2 checks, 69 lines checked
241218bb949c drm/xe/multi_queue: Support active group after primary is destroyed
4cf5b9b5a6ca drm/xe/doc: Add documentation for Multi Queue Group
3f1d6705a455 drm/xe/doc: Add documentation for Multi Queue Group GuC interface
231aa8a462e5 drm/xe/multi_queue: Enable multi_queue on xe3p_xpc
^ permalink raw reply [flat|nested] 27+ messages in thread* ✓ CI.KUnit: success for drm/xe: Multi Queue feature support (rev2)
2025-11-04 18:51 [PATCH v2 00/16] drm/xe: Multi Queue feature support Niranjana Vishwanathapura
` (16 preceding siblings ...)
2025-11-04 23:16 ` ✗ CI.checkpatch: warning for drm/xe: Multi Queue feature support (rev2) Patchwork
@ 2025-11-04 23:18 ` Patchwork
2025-11-05 0:14 ` ✗ Xe.CI.BAT: failure " Patchwork
2025-11-05 7:10 ` ✗ Xe.CI.Full: " Patchwork
19 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2025-11-04 23:18 UTC (permalink / raw)
To: Niranjana Vishwanathapura; +Cc: intel-xe
== Series Details ==
Series: drm/xe: Multi Queue feature support (rev2)
URL : https://patchwork.freedesktop.org/series/156865/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[23:16:59] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[23:17:04] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[23:17:34] Starting KUnit Kernel (1/1)...
[23:17:34] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[23:17:34] ================== guc_buf (11 subtests) ===================
[23:17:34] [PASSED] test_smallest
[23:17:34] [PASSED] test_largest
[23:17:34] [PASSED] test_granular
[23:17:34] [PASSED] test_unique
[23:17:34] [PASSED] test_overlap
[23:17:34] [PASSED] test_reusable
[23:17:34] [PASSED] test_too_big
[23:17:34] [PASSED] test_flush
[23:17:34] [PASSED] test_lookup
[23:17:34] [PASSED] test_data
[23:17:34] [PASSED] test_class
[23:17:34] ===================== [PASSED] guc_buf =====================
[23:17:34] =================== guc_dbm (7 subtests) ===================
[23:17:34] [PASSED] test_empty
[23:17:34] [PASSED] test_default
[23:17:34] ======================== test_size ========================
[23:17:34] [PASSED] 4
[23:17:34] [PASSED] 8
[23:17:34] [PASSED] 32
[23:17:34] [PASSED] 256
[23:17:34] ==================== [PASSED] test_size ====================
[23:17:34] ======================= test_reuse ========================
[23:17:34] [PASSED] 4
[23:17:34] [PASSED] 8
[23:17:34] [PASSED] 32
[23:17:34] [PASSED] 256
[23:17:34] =================== [PASSED] test_reuse ====================
[23:17:34] =================== test_range_overlap ====================
[23:17:34] [PASSED] 4
[23:17:34] [PASSED] 8
[23:17:34] [PASSED] 32
[23:17:34] [PASSED] 256
[23:17:34] =============== [PASSED] test_range_overlap ================
[23:17:34] =================== test_range_compact ====================
[23:17:34] [PASSED] 4
[23:17:34] [PASSED] 8
[23:17:34] [PASSED] 32
[23:17:34] [PASSED] 256
[23:17:34] =============== [PASSED] test_range_compact ================
[23:17:34] ==================== test_range_spare =====================
[23:17:34] [PASSED] 4
[23:17:34] [PASSED] 8
[23:17:34] [PASSED] 32
[23:17:34] [PASSED] 256
[23:17:34] ================ [PASSED] test_range_spare =================
[23:17:34] ===================== [PASSED] guc_dbm =====================
[23:17:34] =================== guc_idm (6 subtests) ===================
[23:17:34] [PASSED] bad_init
[23:17:34] [PASSED] no_init
[23:17:34] [PASSED] init_fini
[23:17:34] [PASSED] check_used
[23:17:34] [PASSED] check_quota
[23:17:34] [PASSED] check_all
[23:17:34] ===================== [PASSED] guc_idm =====================
[23:17:34] ================== no_relay (3 subtests) ===================
[23:17:34] [PASSED] xe_drops_guc2pf_if_not_ready
[23:17:34] [PASSED] xe_drops_guc2vf_if_not_ready
[23:17:34] [PASSED] xe_rejects_send_if_not_ready
[23:17:34] ==================== [PASSED] no_relay =====================
[23:17:34] ================== pf_relay (14 subtests) ==================
[23:17:34] [PASSED] pf_rejects_guc2pf_too_short
[23:17:34] [PASSED] pf_rejects_guc2pf_too_long
[23:17:34] [PASSED] pf_rejects_guc2pf_no_payload
[23:17:34] [PASSED] pf_fails_no_payload
[23:17:34] [PASSED] pf_fails_bad_origin
[23:17:34] [PASSED] pf_fails_bad_type
[23:17:34] [PASSED] pf_txn_reports_error
[23:17:34] [PASSED] pf_txn_sends_pf2guc
[23:17:34] [PASSED] pf_sends_pf2guc
[23:17:34] [SKIPPED] pf_loopback_nop
[23:17:34] [SKIPPED] pf_loopback_echo
[23:17:34] [SKIPPED] pf_loopback_fail
[23:17:34] [SKIPPED] pf_loopback_busy
[23:17:34] [SKIPPED] pf_loopback_retry
[23:17:34] ==================== [PASSED] pf_relay =====================
[23:17:34] ================== vf_relay (3 subtests) ===================
[23:17:34] [PASSED] vf_rejects_guc2vf_too_short
[23:17:34] [PASSED] vf_rejects_guc2vf_too_long
[23:17:34] [PASSED] vf_rejects_guc2vf_no_payload
[23:17:34] ==================== [PASSED] vf_relay =====================
[23:17:34] ===================== lmtt (1 subtest) =====================
[23:17:34] ======================== test_ops =========================
[23:17:34] [PASSED] 2-level
[23:17:34] [PASSED] multi-level
[23:17:34] ==================== [PASSED] test_ops =====================
[23:17:34] ====================== [PASSED] lmtt =======================
[23:17:34] ================= pf_service (11 subtests) =================
[23:17:34] [PASSED] pf_negotiate_any
[23:17:34] [PASSED] pf_negotiate_base_match
[23:17:34] [PASSED] pf_negotiate_base_newer
[23:17:34] [PASSED] pf_negotiate_base_next
[23:17:34] [SKIPPED] pf_negotiate_base_older
[23:17:34] [PASSED] pf_negotiate_base_prev
[23:17:34] [PASSED] pf_negotiate_latest_match
[23:17:34] [PASSED] pf_negotiate_latest_newer
[23:17:34] [PASSED] pf_negotiate_latest_next
[23:17:34] [SKIPPED] pf_negotiate_latest_older
[23:17:34] [SKIPPED] pf_negotiate_latest_prev
[23:17:34] =================== [PASSED] pf_service ====================
[23:17:34] ================= xe_guc_g2g (2 subtests) ==================
[23:17:34] ============== xe_live_guc_g2g_kunit_default ==============
[23:17:34] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[23:17:34] ============== xe_live_guc_g2g_kunit_allmem ===============
[23:17:34] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[23:17:34] =================== [SKIPPED] xe_guc_g2g ===================
[23:17:34] =================== xe_mocs (2 subtests) ===================
[23:17:34] ================ xe_live_mocs_kernel_kunit ================
[23:17:34] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[23:17:34] ================ xe_live_mocs_reset_kunit =================
[23:17:34] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[23:17:34] ==================== [SKIPPED] xe_mocs =====================
[23:17:34] ================= xe_migrate (2 subtests) ==================
[23:17:34] ================= xe_migrate_sanity_kunit =================
[23:17:34] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[23:17:34] ================== xe_validate_ccs_kunit ==================
[23:17:34] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[23:17:34] =================== [SKIPPED] xe_migrate ===================
[23:17:34] ================== xe_dma_buf (1 subtest) ==================
[23:17:34] ==================== xe_dma_buf_kunit =====================
[23:17:34] ================ [SKIPPED] xe_dma_buf_kunit ================
[23:17:34] =================== [SKIPPED] xe_dma_buf ===================
[23:17:34] ================= xe_bo_shrink (1 subtest) =================
[23:17:34] =================== xe_bo_shrink_kunit ====================
[23:17:34] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[23:17:34] ================== [SKIPPED] xe_bo_shrink ==================
[23:17:34] ==================== xe_bo (2 subtests) ====================
[23:17:34] ================== xe_ccs_migrate_kunit ===================
[23:17:34] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[23:17:34] ==================== xe_bo_evict_kunit ====================
[23:17:34] =============== [SKIPPED] xe_bo_evict_kunit ================
[23:17:34] ===================== [SKIPPED] xe_bo ======================
[23:17:34] ==================== args (11 subtests) ====================
[23:17:34] [PASSED] count_args_test
[23:17:34] [PASSED] call_args_example
[23:17:34] [PASSED] call_args_test
[23:17:34] [PASSED] drop_first_arg_example
[23:17:34] [PASSED] drop_first_arg_test
[23:17:34] [PASSED] first_arg_example
[23:17:34] [PASSED] first_arg_test
[23:17:34] [PASSED] last_arg_example
[23:17:34] [PASSED] last_arg_test
[23:17:34] [PASSED] pick_arg_example
[23:17:34] [PASSED] sep_comma_example
[23:17:34] ====================== [PASSED] args =======================
[23:17:34] =================== xe_pci (3 subtests) ====================
[23:17:34] ==================== check_graphics_ip ====================
[23:17:34] [PASSED] 12.00 Xe_LP
[23:17:34] [PASSED] 12.10 Xe_LP+
[23:17:34] [PASSED] 12.55 Xe_HPG
[23:17:34] [PASSED] 12.60 Xe_HPC
[23:17:34] [PASSED] 12.70 Xe_LPG
[23:17:34] [PASSED] 12.71 Xe_LPG
[23:17:34] [PASSED] 12.74 Xe_LPG+
[23:17:34] [PASSED] 20.01 Xe2_HPG
[23:17:34] [PASSED] 20.02 Xe2_HPG
[23:17:34] [PASSED] 20.04 Xe2_LPG
[23:17:34] [PASSED] 30.00 Xe3_LPG
[23:17:34] [PASSED] 30.01 Xe3_LPG
[23:17:34] [PASSED] 30.03 Xe3_LPG
[23:17:34] [PASSED] 30.04 Xe3_LPG
[23:17:34] [PASSED] 30.05 Xe3_LPG
[23:17:34] [PASSED] 35.11 Xe3p_XPC
[23:17:34] ================ [PASSED] check_graphics_ip ================
[23:17:34] ===================== check_media_ip ======================
[23:17:34] [PASSED] 12.00 Xe_M
[23:17:34] [PASSED] 12.55 Xe_HPM
[23:17:34] [PASSED] 13.00 Xe_LPM+
[23:17:34] [PASSED] 13.01 Xe2_HPM
[23:17:34] [PASSED] 20.00 Xe2_LPM
[23:17:34] [PASSED] 30.00 Xe3_LPM
[23:17:34] [PASSED] 30.02 Xe3_LPM
[23:17:34] [PASSED] 35.00 Xe3p_LPM
[23:17:34] [PASSED] 35.03 Xe3p_HPM
[23:17:34] ================= [PASSED] check_media_ip ==================
[23:17:34] =================== check_platform_desc ===================
[23:17:34] [PASSED] 0x9A60 (TIGERLAKE)
[23:17:34] [PASSED] 0x9A68 (TIGERLAKE)
[23:17:34] [PASSED] 0x9A70 (TIGERLAKE)
[23:17:34] [PASSED] 0x9A40 (TIGERLAKE)
[23:17:34] [PASSED] 0x9A49 (TIGERLAKE)
[23:17:34] [PASSED] 0x9A59 (TIGERLAKE)
[23:17:34] [PASSED] 0x9A78 (TIGERLAKE)
[23:17:34] [PASSED] 0x9AC0 (TIGERLAKE)
[23:17:34] [PASSED] 0x9AC9 (TIGERLAKE)
[23:17:34] [PASSED] 0x9AD9 (TIGERLAKE)
[23:17:34] [PASSED] 0x9AF8 (TIGERLAKE)
[23:17:34] [PASSED] 0x4C80 (ROCKETLAKE)
[23:17:34] [PASSED] 0x4C8A (ROCKETLAKE)
[23:17:34] [PASSED] 0x4C8B (ROCKETLAKE)
[23:17:34] [PASSED] 0x4C8C (ROCKETLAKE)
[23:17:34] [PASSED] 0x4C90 (ROCKETLAKE)
[23:17:34] [PASSED] 0x4C9A (ROCKETLAKE)
[23:17:34] [PASSED] 0x4680 (ALDERLAKE_S)
[23:17:34] [PASSED] 0x4682 (ALDERLAKE_S)
[23:17:34] [PASSED] 0x4688 (ALDERLAKE_S)
[23:17:34] [PASSED] 0x468A (ALDERLAKE_S)
[23:17:34] [PASSED] 0x468B (ALDERLAKE_S)
[23:17:34] [PASSED] 0x4690 (ALDERLAKE_S)
[23:17:34] [PASSED] 0x4692 (ALDERLAKE_S)
[23:17:34] [PASSED] 0x4693 (ALDERLAKE_S)
[23:17:34] [PASSED] 0x46A0 (ALDERLAKE_P)
[23:17:34] [PASSED] 0x46A1 (ALDERLAKE_P)
[23:17:34] [PASSED] 0x46A2 (ALDERLAKE_P)
[23:17:34] [PASSED] 0x46A3 (ALDERLAKE_P)
[23:17:34] [PASSED] 0x46A6 (ALDERLAKE_P)
[23:17:34] [PASSED] 0x46A8 (ALDERLAKE_P)
[23:17:34] [PASSED] 0x46AA (ALDERLAKE_P)
[23:17:34] [PASSED] 0x462A (ALDERLAKE_P)
[23:17:34] [PASSED] 0x4626 (ALDERLAKE_P)
[23:17:34] [PASSED] 0x4628 (ALDERLAKE_P)
[23:17:34] [PASSED] 0x46B0 (ALDERLAKE_P)
[23:17:34] [PASSED] 0x46B1 (ALDERLAKE_P)
[23:17:34] [PASSED] 0x46B2 (ALDERLAKE_P)
[23:17:34] [PASSED] 0x46B3 (ALDERLAKE_P)
[23:17:34] [PASSED] 0x46C0 (ALDERLAKE_P)
[23:17:34] [PASSED] 0x46C1 (ALDERLAKE_P)
[23:17:34] [PASSED] 0x46C2 (ALDERLAKE_P)
[23:17:34] [PASSED] 0x46C3 (ALDERLAKE_P)
[23:17:34] [PASSED] 0x46D0 (ALDERLAKE_N)
[23:17:34] [PASSED] 0x46D1 (ALDERLAKE_N)
[23:17:34] [PASSED] 0x46D2 (ALDERLAKE_N)
[23:17:34] [PASSED] 0x46D3 (ALDERLAKE_N)
[23:17:34] [PASSED] 0x46D4 (ALDERLAKE_N)
[23:17:34] [PASSED] 0xA721 (ALDERLAKE_P)
[23:17:34] [PASSED] 0xA7A1 (ALDERLAKE_P)
[23:17:34] [PASSED] 0xA7A9 (ALDERLAKE_P)
[23:17:34] [PASSED] 0xA7AC (ALDERLAKE_P)
[23:17:34] [PASSED] 0xA7AD (ALDERLAKE_P)
[23:17:34] [PASSED] 0xA720 (ALDERLAKE_P)
[23:17:34] [PASSED] 0xA7A0 (ALDERLAKE_P)
[23:17:34] [PASSED] 0xA7A8 (ALDERLAKE_P)
[23:17:34] [PASSED] 0xA7AA (ALDERLAKE_P)
[23:17:34] [PASSED] 0xA7AB (ALDERLAKE_P)
[23:17:34] [PASSED] 0xA780 (ALDERLAKE_S)
[23:17:34] [PASSED] 0xA781 (ALDERLAKE_S)
[23:17:34] [PASSED] 0xA782 (ALDERLAKE_S)
[23:17:34] [PASSED] 0xA783 (ALDERLAKE_S)
[23:17:34] [PASSED] 0xA788 (ALDERLAKE_S)
[23:17:34] [PASSED] 0xA789 (ALDERLAKE_S)
[23:17:34] [PASSED] 0xA78A (ALDERLAKE_S)
[23:17:34] [PASSED] 0xA78B (ALDERLAKE_S)
[23:17:34] [PASSED] 0x4905 (DG1)
[23:17:34] [PASSED] 0x4906 (DG1)
[23:17:34] [PASSED] 0x4907 (DG1)
[23:17:34] [PASSED] 0x4908 (DG1)
[23:17:34] [PASSED] 0x4909 (DG1)
[23:17:34] [PASSED] 0x56C0 (DG2)
[23:17:34] [PASSED] 0x56C2 (DG2)
[23:17:34] [PASSED] 0x56C1 (DG2)
[23:17:34] [PASSED] 0x7D51 (METEORLAKE)
[23:17:34] [PASSED] 0x7DD1 (METEORLAKE)
[23:17:34] [PASSED] 0x7D41 (METEORLAKE)
[23:17:34] [PASSED] 0x7D67 (METEORLAKE)
[23:17:34] [PASSED] 0xB640 (METEORLAKE)
[23:17:34] [PASSED] 0x56A0 (DG2)
[23:17:34] [PASSED] 0x56A1 (DG2)
[23:17:34] [PASSED] 0x56A2 (DG2)
[23:17:34] [PASSED] 0x56BE (DG2)
[23:17:34] [PASSED] 0x56BF (DG2)
[23:17:34] [PASSED] 0x5690 (DG2)
[23:17:34] [PASSED] 0x5691 (DG2)
[23:17:34] [PASSED] 0x5692 (DG2)
[23:17:34] [PASSED] 0x56A5 (DG2)
[23:17:34] [PASSED] 0x56A6 (DG2)
[23:17:34] [PASSED] 0x56B0 (DG2)
[23:17:34] [PASSED] 0x56B1 (DG2)
[23:17:34] [PASSED] 0x56BA (DG2)
[23:17:34] [PASSED] 0x56BB (DG2)
[23:17:34] [PASSED] 0x56BC (DG2)
[23:17:34] [PASSED] 0x56BD (DG2)
[23:17:34] [PASSED] 0x5693 (DG2)
[23:17:34] [PASSED] 0x5694 (DG2)
[23:17:34] [PASSED] 0x5695 (DG2)
[23:17:34] [PASSED] 0x56A3 (DG2)
[23:17:34] [PASSED] 0x56A4 (DG2)
[23:17:34] [PASSED] 0x56B2 (DG2)
[23:17:34] [PASSED] 0x56B3 (DG2)
[23:17:34] [PASSED] 0x5696 (DG2)
[23:17:34] [PASSED] 0x5697 (DG2)
[23:17:34] [PASSED] 0xB69 (PVC)
[23:17:34] [PASSED] 0xB6E (PVC)
[23:17:34] [PASSED] 0xBD4 (PVC)
[23:17:34] [PASSED] 0xBD5 (PVC)
[23:17:34] [PASSED] 0xBD6 (PVC)
[23:17:34] [PASSED] 0xBD7 (PVC)
[23:17:34] [PASSED] 0xBD8 (PVC)
[23:17:34] [PASSED] 0xBD9 (PVC)
[23:17:34] [PASSED] 0xBDA (PVC)
[23:17:34] [PASSED] 0xBDB (PVC)
[23:17:34] [PASSED] 0xBE0 (PVC)
[23:17:34] [PASSED] 0xBE1 (PVC)
[23:17:34] [PASSED] 0xBE5 (PVC)
[23:17:34] [PASSED] 0x7D40 (METEORLAKE)
[23:17:34] [PASSED] 0x7D45 (METEORLAKE)
[23:17:34] [PASSED] 0x7D55 (METEORLAKE)
[23:17:34] [PASSED] 0x7D60 (METEORLAKE)
[23:17:34] [PASSED] 0x7DD5 (METEORLAKE)
[23:17:34] [PASSED] 0x6420 (LUNARLAKE)
[23:17:34] [PASSED] 0x64A0 (LUNARLAKE)
[23:17:34] [PASSED] 0x64B0 (LUNARLAKE)
[23:17:34] [PASSED] 0xE202 (BATTLEMAGE)
[23:17:34] [PASSED] 0xE209 (BATTLEMAGE)
[23:17:34] [PASSED] 0xE20B (BATTLEMAGE)
[23:17:34] [PASSED] 0xE20C (BATTLEMAGE)
[23:17:34] [PASSED] 0xE20D (BATTLEMAGE)
[23:17:34] [PASSED] 0xE210 (BATTLEMAGE)
[23:17:34] [PASSED] 0xE211 (BATTLEMAGE)
[23:17:34] [PASSED] 0xE212 (BATTLEMAGE)
[23:17:34] [PASSED] 0xE216 (BATTLEMAGE)
[23:17:34] [PASSED] 0xE220 (BATTLEMAGE)
[23:17:34] [PASSED] 0xE221 (BATTLEMAGE)
[23:17:34] [PASSED] 0xE222 (BATTLEMAGE)
[23:17:34] [PASSED] 0xE223 (BATTLEMAGE)
[23:17:34] [PASSED] 0xB080 (PANTHERLAKE)
[23:17:34] [PASSED] 0xB081 (PANTHERLAKE)
[23:17:34] [PASSED] 0xB082 (PANTHERLAKE)
[23:17:34] [PASSED] 0xB083 (PANTHERLAKE)
[23:17:34] [PASSED] 0xB084 (PANTHERLAKE)
[23:17:34] [PASSED] 0xB085 (PANTHERLAKE)
[23:17:34] [PASSED] 0xB086 (PANTHERLAKE)
[23:17:34] [PASSED] 0xB087 (PANTHERLAKE)
[23:17:34] [PASSED] 0xB08F (PANTHERLAKE)
[23:17:34] [PASSED] 0xB090 (PANTHERLAKE)
[23:17:34] [PASSED] 0xB0A0 (PANTHERLAKE)
[23:17:34] [PASSED] 0xB0B0 (PANTHERLAKE)
[23:17:34] [PASSED] 0xD740 (NOVALAKE_S)
[23:17:34] [PASSED] 0xD741 (NOVALAKE_S)
[23:17:34] [PASSED] 0xD742 (NOVALAKE_S)
[23:17:34] [PASSED] 0xD743 (NOVALAKE_S)
[23:17:34] [PASSED] 0xD744 (NOVALAKE_S)
[23:17:34] [PASSED] 0xD745 (NOVALAKE_S)
[23:17:34] [PASSED] 0x674C (CRESCENTISLAND)
[23:17:34] [PASSED] 0xFD80 (PANTHERLAKE)
[23:17:34] [PASSED] 0xFD81 (PANTHERLAKE)
[23:17:34] =============== [PASSED] check_platform_desc ===============
[23:17:34] ===================== [PASSED] xe_pci ======================
[23:17:34] =================== xe_rtp (2 subtests) ====================
[23:17:34] =============== xe_rtp_process_to_sr_tests ================
[23:17:34] [PASSED] coalesce-same-reg
[23:17:34] [PASSED] no-match-no-add
[23:17:34] [PASSED] match-or
[23:17:34] [PASSED] match-or-xfail
[23:17:34] [PASSED] no-match-no-add-multiple-rules
[23:17:34] [PASSED] two-regs-two-entries
[23:17:34] [PASSED] clr-one-set-other
[23:17:34] [PASSED] set-field
[23:17:34] [PASSED] conflict-duplicate
[23:17:34] [PASSED] conflict-not-disjoint
[23:17:34] [PASSED] conflict-reg-type
[23:17:34] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[23:17:34] ================== xe_rtp_process_tests ===================
[23:17:34] [PASSED] active1
[23:17:34] [PASSED] active2
[23:17:34] [PASSED] active-inactive
[23:17:34] [PASSED] inactive-active
[23:17:34] [PASSED] inactive-1st_or_active-inactive
[23:17:34] [PASSED] inactive-2nd_or_active-inactive
[23:17:34] [PASSED] inactive-last_or_active-inactive
stty: 'standard input': Inappropriate ioctl for device
[23:17:34] [PASSED] inactive-no_or_active-inactive
[23:17:34] ============== [PASSED] xe_rtp_process_tests ===============
[23:17:34] ===================== [PASSED] xe_rtp ======================
[23:17:34] ==================== xe_wa (1 subtest) =====================
[23:17:34] ======================== xe_wa_gt =========================
[23:17:34] [PASSED] TIGERLAKE B0
[23:17:34] [PASSED] DG1 A0
[23:17:34] [PASSED] DG1 B0
[23:17:34] [PASSED] ALDERLAKE_S A0
[23:17:34] [PASSED] ALDERLAKE_S B0
[23:17:34] [PASSED] ALDERLAKE_S C0
[23:17:34] [PASSED] ALDERLAKE_S D0
[23:17:34] [PASSED] ALDERLAKE_P A0
[23:17:34] [PASSED] ALDERLAKE_P B0
[23:17:34] [PASSED] ALDERLAKE_P C0
[23:17:34] [PASSED] ALDERLAKE_S RPLS D0
[23:17:34] [PASSED] ALDERLAKE_P RPLU E0
[23:17:34] [PASSED] DG2 G10 C0
[23:17:34] [PASSED] DG2 G11 B1
[23:17:34] [PASSED] DG2 G12 A1
[23:17:34] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[23:17:34] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[23:17:34] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[23:17:34] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[23:17:34] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[23:17:34] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[23:17:34] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[23:17:34] ==================== [PASSED] xe_wa_gt =====================
[23:17:34] ====================== [PASSED] xe_wa ======================
[23:17:34] ============================================================
[23:17:34] Testing complete. Ran 318 tests: passed: 300, skipped: 18
[23:17:34] Elapsed time: 35.209s total, 4.223s configuring, 30.620s building, 0.332s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[23:17:35] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[23:17:36] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[23:18:01] Starting KUnit Kernel (1/1)...
[23:18:01] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[23:18:01] ============ drm_test_pick_cmdline (2 subtests) ============
[23:18:01] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[23:18:01] =============== drm_test_pick_cmdline_named ===============
[23:18:01] [PASSED] NTSC
[23:18:01] [PASSED] NTSC-J
[23:18:01] [PASSED] PAL
[23:18:01] [PASSED] PAL-M
[23:18:01] =========== [PASSED] drm_test_pick_cmdline_named ===========
[23:18:01] ============== [PASSED] drm_test_pick_cmdline ==============
[23:18:01] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[23:18:01] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[23:18:01] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[23:18:01] =========== drm_validate_clone_mode (2 subtests) ===========
[23:18:01] ============== drm_test_check_in_clone_mode ===============
[23:18:01] [PASSED] in_clone_mode
[23:18:01] [PASSED] not_in_clone_mode
[23:18:01] ========== [PASSED] drm_test_check_in_clone_mode ===========
[23:18:01] =============== drm_test_check_valid_clones ===============
[23:18:01] [PASSED] not_in_clone_mode
[23:18:01] [PASSED] valid_clone
[23:18:01] [PASSED] invalid_clone
[23:18:01] =========== [PASSED] drm_test_check_valid_clones ===========
[23:18:01] ============= [PASSED] drm_validate_clone_mode =============
[23:18:01] ============= drm_validate_modeset (1 subtest) =============
[23:18:01] [PASSED] drm_test_check_connector_changed_modeset
[23:18:01] ============== [PASSED] drm_validate_modeset ===============
[23:18:01] ====== drm_test_bridge_get_current_state (2 subtests) ======
[23:18:01] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[23:18:01] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[23:18:01] ======== [PASSED] drm_test_bridge_get_current_state ========
[23:18:01] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[23:18:01] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[23:18:01] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[23:18:01] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[23:18:01] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[23:18:01] ============== drm_bridge_alloc (2 subtests) ===============
[23:18:01] [PASSED] drm_test_drm_bridge_alloc_basic
[23:18:01] [PASSED] drm_test_drm_bridge_alloc_get_put
[23:18:01] ================ [PASSED] drm_bridge_alloc =================
[23:18:01] ================== drm_buddy (8 subtests) ==================
[23:18:01] [PASSED] drm_test_buddy_alloc_limit
[23:18:01] [PASSED] drm_test_buddy_alloc_optimistic
[23:18:01] [PASSED] drm_test_buddy_alloc_pessimistic
[23:18:01] [PASSED] drm_test_buddy_alloc_pathological
[23:18:01] [PASSED] drm_test_buddy_alloc_contiguous
[23:18:01] [PASSED] drm_test_buddy_alloc_clear
[23:18:01] [PASSED] drm_test_buddy_alloc_range_bias
[23:18:01] [PASSED] drm_test_buddy_fragmentation_performance
[23:18:01] ==================== [PASSED] drm_buddy ====================
[23:18:01] ============= drm_cmdline_parser (40 subtests) =============
[23:18:01] [PASSED] drm_test_cmdline_force_d_only
[23:18:01] [PASSED] drm_test_cmdline_force_D_only_dvi
[23:18:01] [PASSED] drm_test_cmdline_force_D_only_hdmi
[23:18:01] [PASSED] drm_test_cmdline_force_D_only_not_digital
[23:18:01] [PASSED] drm_test_cmdline_force_e_only
[23:18:01] [PASSED] drm_test_cmdline_res
[23:18:01] [PASSED] drm_test_cmdline_res_vesa
[23:18:01] [PASSED] drm_test_cmdline_res_vesa_rblank
[23:18:01] [PASSED] drm_test_cmdline_res_rblank
[23:18:01] [PASSED] drm_test_cmdline_res_bpp
[23:18:01] [PASSED] drm_test_cmdline_res_refresh
[23:18:01] [PASSED] drm_test_cmdline_res_bpp_refresh
[23:18:01] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[23:18:01] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[23:18:01] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[23:18:01] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[23:18:01] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[23:18:01] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[23:18:01] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[23:18:01] [PASSED] drm_test_cmdline_res_margins_force_on
[23:18:01] [PASSED] drm_test_cmdline_res_vesa_margins
[23:18:01] [PASSED] drm_test_cmdline_name
[23:18:01] [PASSED] drm_test_cmdline_name_bpp
[23:18:01] [PASSED] drm_test_cmdline_name_option
[23:18:01] [PASSED] drm_test_cmdline_name_bpp_option
[23:18:01] [PASSED] drm_test_cmdline_rotate_0
[23:18:01] [PASSED] drm_test_cmdline_rotate_90
[23:18:01] [PASSED] drm_test_cmdline_rotate_180
[23:18:01] [PASSED] drm_test_cmdline_rotate_270
[23:18:01] [PASSED] drm_test_cmdline_hmirror
[23:18:01] [PASSED] drm_test_cmdline_vmirror
[23:18:01] [PASSED] drm_test_cmdline_margin_options
[23:18:01] [PASSED] drm_test_cmdline_multiple_options
[23:18:01] [PASSED] drm_test_cmdline_bpp_extra_and_option
[23:18:01] [PASSED] drm_test_cmdline_extra_and_option
[23:18:01] [PASSED] drm_test_cmdline_freestanding_options
[23:18:01] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[23:18:01] [PASSED] drm_test_cmdline_panel_orientation
[23:18:01] ================ drm_test_cmdline_invalid =================
[23:18:01] [PASSED] margin_only
[23:18:01] [PASSED] interlace_only
[23:18:01] [PASSED] res_missing_x
[23:18:01] [PASSED] res_missing_y
[23:18:01] [PASSED] res_bad_y
[23:18:01] [PASSED] res_missing_y_bpp
[23:18:01] [PASSED] res_bad_bpp
[23:18:01] [PASSED] res_bad_refresh
[23:18:01] [PASSED] res_bpp_refresh_force_on_off
[23:18:01] [PASSED] res_invalid_mode
[23:18:01] [PASSED] res_bpp_wrong_place_mode
[23:18:01] [PASSED] name_bpp_refresh
[23:18:01] [PASSED] name_refresh
[23:18:01] [PASSED] name_refresh_wrong_mode
[23:18:01] [PASSED] name_refresh_invalid_mode
[23:18:01] [PASSED] rotate_multiple
[23:18:01] [PASSED] rotate_invalid_val
[23:18:01] [PASSED] rotate_truncated
[23:18:01] [PASSED] invalid_option
[23:18:01] [PASSED] invalid_tv_option
[23:18:01] [PASSED] truncated_tv_option
[23:18:01] ============ [PASSED] drm_test_cmdline_invalid =============
[23:18:01] =============== drm_test_cmdline_tv_options ===============
[23:18:01] [PASSED] NTSC
[23:18:01] [PASSED] NTSC_443
[23:18:01] [PASSED] NTSC_J
[23:18:01] [PASSED] PAL
[23:18:01] [PASSED] PAL_M
[23:18:01] [PASSED] PAL_N
[23:18:01] [PASSED] SECAM
[23:18:01] [PASSED] MONO_525
[23:18:01] [PASSED] MONO_625
[23:18:01] =========== [PASSED] drm_test_cmdline_tv_options ===========
[23:18:01] =============== [PASSED] drm_cmdline_parser ================
[23:18:01] ========== drmm_connector_hdmi_init (20 subtests) ==========
[23:18:01] [PASSED] drm_test_connector_hdmi_init_valid
[23:18:01] [PASSED] drm_test_connector_hdmi_init_bpc_8
[23:18:01] [PASSED] drm_test_connector_hdmi_init_bpc_10
[23:18:01] [PASSED] drm_test_connector_hdmi_init_bpc_12
[23:18:01] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[23:18:01] [PASSED] drm_test_connector_hdmi_init_bpc_null
[23:18:01] [PASSED] drm_test_connector_hdmi_init_formats_empty
[23:18:01] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[23:18:01] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[23:18:01] [PASSED] supported_formats=0x9 yuv420_allowed=1
[23:18:01] [PASSED] supported_formats=0x9 yuv420_allowed=0
[23:18:01] [PASSED] supported_formats=0x3 yuv420_allowed=1
[23:18:01] [PASSED] supported_formats=0x3 yuv420_allowed=0
[23:18:01] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[23:18:01] [PASSED] drm_test_connector_hdmi_init_null_ddc
[23:18:01] [PASSED] drm_test_connector_hdmi_init_null_product
[23:18:01] [PASSED] drm_test_connector_hdmi_init_null_vendor
[23:18:01] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[23:18:01] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[23:18:01] [PASSED] drm_test_connector_hdmi_init_product_valid
[23:18:01] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[23:18:01] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[23:18:01] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[23:18:01] ========= drm_test_connector_hdmi_init_type_valid =========
[23:18:01] [PASSED] HDMI-A
[23:18:01] [PASSED] HDMI-B
[23:18:01] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[23:18:01] ======== drm_test_connector_hdmi_init_type_invalid ========
[23:18:01] [PASSED] Unknown
[23:18:01] [PASSED] VGA
[23:18:01] [PASSED] DVI-I
[23:18:01] [PASSED] DVI-D
[23:18:01] [PASSED] DVI-A
[23:18:01] [PASSED] Composite
[23:18:01] [PASSED] SVIDEO
[23:18:01] [PASSED] LVDS
[23:18:01] [PASSED] Component
[23:18:01] [PASSED] DIN
[23:18:01] [PASSED] DP
[23:18:01] [PASSED] TV
[23:18:01] [PASSED] eDP
[23:18:01] [PASSED] Virtual
[23:18:01] [PASSED] DSI
[23:18:01] [PASSED] DPI
[23:18:01] [PASSED] Writeback
[23:18:01] [PASSED] SPI
[23:18:01] [PASSED] USB
[23:18:01] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[23:18:01] ============ [PASSED] drmm_connector_hdmi_init =============
[23:18:01] ============= drmm_connector_init (3 subtests) =============
[23:18:01] [PASSED] drm_test_drmm_connector_init
[23:18:01] [PASSED] drm_test_drmm_connector_init_null_ddc
[23:18:01] ========= drm_test_drmm_connector_init_type_valid =========
[23:18:01] [PASSED] Unknown
[23:18:01] [PASSED] VGA
[23:18:01] [PASSED] DVI-I
[23:18:01] [PASSED] DVI-D
[23:18:01] [PASSED] DVI-A
[23:18:01] [PASSED] Composite
[23:18:01] [PASSED] SVIDEO
[23:18:01] [PASSED] LVDS
[23:18:01] [PASSED] Component
[23:18:01] [PASSED] DIN
[23:18:01] [PASSED] DP
[23:18:01] [PASSED] HDMI-A
[23:18:01] [PASSED] HDMI-B
[23:18:01] [PASSED] TV
[23:18:01] [PASSED] eDP
[23:18:01] [PASSED] Virtual
[23:18:01] [PASSED] DSI
[23:18:01] [PASSED] DPI
[23:18:01] [PASSED] Writeback
[23:18:01] [PASSED] SPI
[23:18:01] [PASSED] USB
[23:18:01] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[23:18:01] =============== [PASSED] drmm_connector_init ===============
[23:18:01] ========= drm_connector_dynamic_init (6 subtests) ==========
[23:18:01] [PASSED] drm_test_drm_connector_dynamic_init
[23:18:01] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[23:18:01] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[23:18:01] [PASSED] drm_test_drm_connector_dynamic_init_properties
[23:18:01] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[23:18:01] [PASSED] Unknown
[23:18:01] [PASSED] VGA
[23:18:01] [PASSED] DVI-I
[23:18:01] [PASSED] DVI-D
[23:18:01] [PASSED] DVI-A
[23:18:01] [PASSED] Composite
[23:18:01] [PASSED] SVIDEO
[23:18:01] [PASSED] LVDS
[23:18:01] [PASSED] Component
[23:18:01] [PASSED] DIN
[23:18:01] [PASSED] DP
[23:18:01] [PASSED] HDMI-A
[23:18:01] [PASSED] HDMI-B
[23:18:01] [PASSED] TV
[23:18:01] [PASSED] eDP
[23:18:01] [PASSED] Virtual
[23:18:01] [PASSED] DSI
[23:18:01] [PASSED] DPI
[23:18:01] [PASSED] Writeback
[23:18:01] [PASSED] SPI
[23:18:01] [PASSED] USB
[23:18:01] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[23:18:01] ======== drm_test_drm_connector_dynamic_init_name =========
[23:18:01] [PASSED] Unknown
[23:18:01] [PASSED] VGA
[23:18:01] [PASSED] DVI-I
[23:18:01] [PASSED] DVI-D
[23:18:01] [PASSED] DVI-A
[23:18:01] [PASSED] Composite
[23:18:01] [PASSED] SVIDEO
[23:18:01] [PASSED] LVDS
[23:18:01] [PASSED] Component
[23:18:01] [PASSED] DIN
[23:18:01] [PASSED] DP
[23:18:01] [PASSED] HDMI-A
[23:18:01] [PASSED] HDMI-B
[23:18:01] [PASSED] TV
[23:18:01] [PASSED] eDP
[23:18:01] [PASSED] Virtual
[23:18:01] [PASSED] DSI
[23:18:01] [PASSED] DPI
[23:18:01] [PASSED] Writeback
[23:18:01] [PASSED] SPI
[23:18:01] [PASSED] USB
[23:18:01] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[23:18:01] =========== [PASSED] drm_connector_dynamic_init ============
[23:18:01] ==== drm_connector_dynamic_register_early (4 subtests) =====
[23:18:01] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[23:18:01] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[23:18:01] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[23:18:01] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[23:18:01] ====== [PASSED] drm_connector_dynamic_register_early =======
[23:18:01] ======= drm_connector_dynamic_register (7 subtests) ========
[23:18:01] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[23:18:01] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[23:18:01] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[23:18:01] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[23:18:01] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[23:18:01] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[23:18:01] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[23:18:01] ========= [PASSED] drm_connector_dynamic_register ==========
[23:18:01] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[23:18:01] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[23:18:01] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[23:18:01] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[23:18:01] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[23:18:01] ========== drm_test_get_tv_mode_from_name_valid ===========
[23:18:01] [PASSED] NTSC
[23:18:01] [PASSED] NTSC-443
[23:18:01] [PASSED] NTSC-J
[23:18:01] [PASSED] PAL
[23:18:01] [PASSED] PAL-M
[23:18:01] [PASSED] PAL-N
[23:18:01] [PASSED] SECAM
[23:18:01] [PASSED] Mono
[23:18:01] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[23:18:01] [PASSED] drm_test_get_tv_mode_from_name_truncated
[23:18:01] ============ [PASSED] drm_get_tv_mode_from_name ============
[23:18:01] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[23:18:01] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[23:18:01] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[23:18:01] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[23:18:01] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[23:18:01] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[23:18:01] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[23:18:01] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[23:18:01] [PASSED] VIC 96
[23:18:01] [PASSED] VIC 97
[23:18:01] [PASSED] VIC 101
[23:18:01] [PASSED] VIC 102
[23:18:01] [PASSED] VIC 106
[23:18:01] [PASSED] VIC 107
[23:18:01] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[23:18:01] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[23:18:01] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[23:18:01] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[23:18:01] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[23:18:01] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[23:18:01] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[23:18:01] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[23:18:01] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[23:18:01] [PASSED] Automatic
[23:18:01] [PASSED] Full
[23:18:01] [PASSED] Limited 16:235
[23:18:01] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[23:18:01] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[23:18:01] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[23:18:01] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[23:18:01] === drm_test_drm_hdmi_connector_get_output_format_name ====
[23:18:01] [PASSED] RGB
[23:18:01] [PASSED] YUV 4:2:0
[23:18:01] [PASSED] YUV 4:2:2
[23:18:01] [PASSED] YUV 4:4:4
[23:18:01] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[23:18:01] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[23:18:01] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[23:18:01] ============= drm_damage_helper (21 subtests) ==============
[23:18:01] [PASSED] drm_test_damage_iter_no_damage
[23:18:01] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[23:18:01] [PASSED] drm_test_damage_iter_no_damage_src_moved
[23:18:01] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[23:18:01] [PASSED] drm_test_damage_iter_no_damage_not_visible
[23:18:01] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[23:18:01] [PASSED] drm_test_damage_iter_no_damage_no_fb
[23:18:01] [PASSED] drm_test_damage_iter_simple_damage
[23:18:01] [PASSED] drm_test_damage_iter_single_damage
[23:18:01] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[23:18:01] [PASSED] drm_test_damage_iter_single_damage_outside_src
[23:18:01] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[23:18:01] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[23:18:01] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[23:18:01] [PASSED] drm_test_damage_iter_single_damage_src_moved
[23:18:01] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[23:18:01] [PASSED] drm_test_damage_iter_damage
[23:18:01] [PASSED] drm_test_damage_iter_damage_one_intersect
[23:18:01] [PASSED] drm_test_damage_iter_damage_one_outside
[23:18:01] [PASSED] drm_test_damage_iter_damage_src_moved
[23:18:01] [PASSED] drm_test_damage_iter_damage_not_visible
[23:18:01] ================ [PASSED] drm_damage_helper ================
[23:18:01] ============== drm_dp_mst_helper (3 subtests) ==============
[23:18:01] ============== drm_test_dp_mst_calc_pbn_mode ==============
[23:18:01] [PASSED] Clock 154000 BPP 30 DSC disabled
[23:18:01] [PASSED] Clock 234000 BPP 30 DSC disabled
[23:18:01] [PASSED] Clock 297000 BPP 24 DSC disabled
[23:18:01] [PASSED] Clock 332880 BPP 24 DSC enabled
[23:18:01] [PASSED] Clock 324540 BPP 24 DSC enabled
[23:18:01] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[23:18:01] ============== drm_test_dp_mst_calc_pbn_div ===============
[23:18:01] [PASSED] Link rate 2000000 lane count 4
[23:18:01] [PASSED] Link rate 2000000 lane count 2
[23:18:01] [PASSED] Link rate 2000000 lane count 1
[23:18:01] [PASSED] Link rate 1350000 lane count 4
[23:18:01] [PASSED] Link rate 1350000 lane count 2
[23:18:01] [PASSED] Link rate 1350000 lane count 1
[23:18:01] [PASSED] Link rate 1000000 lane count 4
[23:18:01] [PASSED] Link rate 1000000 lane count 2
[23:18:01] [PASSED] Link rate 1000000 lane count 1
[23:18:01] [PASSED] Link rate 810000 lane count 4
[23:18:01] [PASSED] Link rate 810000 lane count 2
[23:18:01] [PASSED] Link rate 810000 lane count 1
[23:18:01] [PASSED] Link rate 540000 lane count 4
[23:18:01] [PASSED] Link rate 540000 lane count 2
[23:18:01] [PASSED] Link rate 540000 lane count 1
[23:18:01] [PASSED] Link rate 270000 lane count 4
[23:18:01] [PASSED] Link rate 270000 lane count 2
[23:18:01] [PASSED] Link rate 270000 lane count 1
[23:18:01] [PASSED] Link rate 162000 lane count 4
[23:18:01] [PASSED] Link rate 162000 lane count 2
[23:18:01] [PASSED] Link rate 162000 lane count 1
[23:18:01] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[23:18:01] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[23:18:01] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[23:18:01] [PASSED] DP_POWER_UP_PHY with port number
[23:18:01] [PASSED] DP_POWER_DOWN_PHY with port number
[23:18:01] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[23:18:01] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[23:18:01] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[23:18:01] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[23:18:01] [PASSED] DP_QUERY_PAYLOAD with port number
[23:18:01] [PASSED] DP_QUERY_PAYLOAD with VCPI
[23:18:01] [PASSED] DP_REMOTE_DPCD_READ with port number
[23:18:01] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[23:18:01] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[23:18:01] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[23:18:01] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[23:18:01] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[23:18:01] [PASSED] DP_REMOTE_I2C_READ with port number
[23:18:01] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[23:18:01] [PASSED] DP_REMOTE_I2C_READ with transactions array
[23:18:01] [PASSED] DP_REMOTE_I2C_WRITE with port number
[23:18:01] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[23:18:01] [PASSED] DP_REMOTE_I2C_WRITE with data array
[23:18:01] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[23:18:01] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[23:18:01] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[23:18:01] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[23:18:01] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[23:18:01] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[23:18:01] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[23:18:01] ================ [PASSED] drm_dp_mst_helper ================
[23:18:01] ================== drm_exec (7 subtests) ===================
[23:18:01] [PASSED] sanitycheck
[23:18:01] [PASSED] test_lock
[23:18:01] [PASSED] test_lock_unlock
[23:18:01] [PASSED] test_duplicates
[23:18:01] [PASSED] test_prepare
[23:18:01] [PASSED] test_prepare_array
[23:18:01] [PASSED] test_multiple_loops
[23:18:01] ==================== [PASSED] drm_exec =====================
[23:18:01] =========== drm_format_helper_test (17 subtests) ===========
[23:18:01] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[23:18:01] [PASSED] single_pixel_source_buffer
[23:18:01] [PASSED] single_pixel_clip_rectangle
[23:18:01] [PASSED] well_known_colors
[23:18:01] [PASSED] destination_pitch
[23:18:01] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[23:18:01] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[23:18:01] [PASSED] single_pixel_source_buffer
[23:18:01] [PASSED] single_pixel_clip_rectangle
[23:18:01] [PASSED] well_known_colors
[23:18:01] [PASSED] destination_pitch
[23:18:01] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[23:18:01] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[23:18:01] [PASSED] single_pixel_source_buffer
[23:18:01] [PASSED] single_pixel_clip_rectangle
[23:18:01] [PASSED] well_known_colors
[23:18:01] [PASSED] destination_pitch
[23:18:01] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[23:18:01] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[23:18:01] [PASSED] single_pixel_source_buffer
[23:18:01] [PASSED] single_pixel_clip_rectangle
[23:18:01] [PASSED] well_known_colors
[23:18:01] [PASSED] destination_pitch
[23:18:01] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[23:18:01] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[23:18:01] [PASSED] single_pixel_source_buffer
[23:18:01] [PASSED] single_pixel_clip_rectangle
[23:18:01] [PASSED] well_known_colors
[23:18:01] [PASSED] destination_pitch
[23:18:01] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[23:18:01] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[23:18:01] [PASSED] single_pixel_source_buffer
[23:18:01] [PASSED] single_pixel_clip_rectangle
[23:18:01] [PASSED] well_known_colors
[23:18:01] [PASSED] destination_pitch
[23:18:01] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[23:18:01] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[23:18:01] [PASSED] single_pixel_source_buffer
[23:18:01] [PASSED] single_pixel_clip_rectangle
[23:18:01] [PASSED] well_known_colors
[23:18:01] [PASSED] destination_pitch
[23:18:01] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[23:18:01] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[23:18:01] [PASSED] single_pixel_source_buffer
[23:18:01] [PASSED] single_pixel_clip_rectangle
[23:18:01] [PASSED] well_known_colors
[23:18:01] [PASSED] destination_pitch
[23:18:01] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[23:18:01] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[23:18:01] [PASSED] single_pixel_source_buffer
[23:18:01] [PASSED] single_pixel_clip_rectangle
[23:18:01] [PASSED] well_known_colors
[23:18:01] [PASSED] destination_pitch
[23:18:01] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[23:18:01] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[23:18:01] [PASSED] single_pixel_source_buffer
[23:18:01] [PASSED] single_pixel_clip_rectangle
[23:18:01] [PASSED] well_known_colors
[23:18:01] [PASSED] destination_pitch
[23:18:01] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[23:18:01] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[23:18:01] [PASSED] single_pixel_source_buffer
[23:18:01] [PASSED] single_pixel_clip_rectangle
[23:18:01] [PASSED] well_known_colors
[23:18:01] [PASSED] destination_pitch
[23:18:01] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[23:18:01] ============== drm_test_fb_xrgb8888_to_mono ===============
[23:18:01] [PASSED] single_pixel_source_buffer
[23:18:01] [PASSED] single_pixel_clip_rectangle
[23:18:01] [PASSED] well_known_colors
[23:18:01] [PASSED] destination_pitch
[23:18:01] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[23:18:01] ==================== drm_test_fb_swab =====================
[23:18:01] [PASSED] single_pixel_source_buffer
[23:18:01] [PASSED] single_pixel_clip_rectangle
[23:18:01] [PASSED] well_known_colors
[23:18:01] [PASSED] destination_pitch
[23:18:01] ================ [PASSED] drm_test_fb_swab =================
[23:18:01] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[23:18:01] [PASSED] single_pixel_source_buffer
[23:18:01] [PASSED] single_pixel_clip_rectangle
[23:18:01] [PASSED] well_known_colors
[23:18:01] [PASSED] destination_pitch
[23:18:01] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[23:18:01] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[23:18:01] [PASSED] single_pixel_source_buffer
[23:18:01] [PASSED] single_pixel_clip_rectangle
[23:18:01] [PASSED] well_known_colors
[23:18:01] [PASSED] destination_pitch
[23:18:01] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[23:18:01] ================= drm_test_fb_clip_offset =================
[23:18:01] [PASSED] pass through
[23:18:01] [PASSED] horizontal offset
[23:18:01] [PASSED] vertical offset
[23:18:01] [PASSED] horizontal and vertical offset
[23:18:01] [PASSED] horizontal offset (custom pitch)
[23:18:01] [PASSED] vertical offset (custom pitch)
[23:18:01] [PASSED] horizontal and vertical offset (custom pitch)
[23:18:01] ============= [PASSED] drm_test_fb_clip_offset =============
[23:18:01] =================== drm_test_fb_memcpy ====================
[23:18:01] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[23:18:01] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[23:18:01] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[23:18:01] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[23:18:01] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[23:18:01] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[23:18:01] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[23:18:01] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[23:18:01] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[23:18:01] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[23:18:01] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[23:18:01] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[23:18:01] =============== [PASSED] drm_test_fb_memcpy ================
[23:18:01] ============= [PASSED] drm_format_helper_test ==============
[23:18:01] ================= drm_format (18 subtests) =================
[23:18:01] [PASSED] drm_test_format_block_width_invalid
[23:18:01] [PASSED] drm_test_format_block_width_one_plane
[23:18:01] [PASSED] drm_test_format_block_width_two_plane
[23:18:01] [PASSED] drm_test_format_block_width_three_plane
[23:18:01] [PASSED] drm_test_format_block_width_tiled
[23:18:01] [PASSED] drm_test_format_block_height_invalid
[23:18:01] [PASSED] drm_test_format_block_height_one_plane
[23:18:01] [PASSED] drm_test_format_block_height_two_plane
[23:18:01] [PASSED] drm_test_format_block_height_three_plane
[23:18:01] [PASSED] drm_test_format_block_height_tiled
[23:18:01] [PASSED] drm_test_format_min_pitch_invalid
[23:18:01] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[23:18:01] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[23:18:01] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[23:18:01] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[23:18:01] [PASSED] drm_test_format_min_pitch_two_plane
[23:18:01] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[23:18:01] [PASSED] drm_test_format_min_pitch_tiled
[23:18:01] =================== [PASSED] drm_format ====================
[23:18:01] ============== drm_framebuffer (10 subtests) ===============
[23:18:01] ========== drm_test_framebuffer_check_src_coords ==========
[23:18:01] [PASSED] Success: source fits into fb
[23:18:01] [PASSED] Fail: overflowing fb with x-axis coordinate
[23:18:01] [PASSED] Fail: overflowing fb with y-axis coordinate
[23:18:01] [PASSED] Fail: overflowing fb with source width
[23:18:01] [PASSED] Fail: overflowing fb with source height
[23:18:01] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[23:18:01] [PASSED] drm_test_framebuffer_cleanup
[23:18:01] =============== drm_test_framebuffer_create ===============
[23:18:01] [PASSED] ABGR8888 normal sizes
[23:18:01] [PASSED] ABGR8888 max sizes
[23:18:01] [PASSED] ABGR8888 pitch greater than min required
[23:18:01] [PASSED] ABGR8888 pitch less than min required
[23:18:01] [PASSED] ABGR8888 Invalid width
[23:18:01] [PASSED] ABGR8888 Invalid buffer handle
[23:18:01] [PASSED] No pixel format
[23:18:01] [PASSED] ABGR8888 Width 0
[23:18:01] [PASSED] ABGR8888 Height 0
[23:18:01] [PASSED] ABGR8888 Out of bound height * pitch combination
[23:18:01] [PASSED] ABGR8888 Large buffer offset
[23:18:01] [PASSED] ABGR8888 Buffer offset for inexistent plane
[23:18:01] [PASSED] ABGR8888 Invalid flag
[23:18:01] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[23:18:01] [PASSED] ABGR8888 Valid buffer modifier
[23:18:01] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[23:18:01] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[23:18:01] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[23:18:01] [PASSED] NV12 Normal sizes
[23:18:01] [PASSED] NV12 Max sizes
[23:18:01] [PASSED] NV12 Invalid pitch
[23:18:01] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[23:18:01] [PASSED] NV12 different modifier per-plane
[23:18:01] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[23:18:01] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[23:18:01] [PASSED] NV12 Modifier for inexistent plane
[23:18:01] [PASSED] NV12 Handle for inexistent plane
[23:18:01] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[23:18:01] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[23:18:01] [PASSED] YVU420 Normal sizes
[23:18:01] [PASSED] YVU420 Max sizes
[23:18:01] [PASSED] YVU420 Invalid pitch
[23:18:01] [PASSED] YVU420 Different pitches
[23:18:01] [PASSED] YVU420 Different buffer offsets/pitches
[23:18:01] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[23:18:01] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[23:18:01] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[23:18:01] [PASSED] YVU420 Valid modifier
[23:18:01] [PASSED] YVU420 Different modifiers per plane
[23:18:01] [PASSED] YVU420 Modifier for inexistent plane
[23:18:01] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[23:18:01] [PASSED] X0L2 Normal sizes
[23:18:01] [PASSED] X0L2 Max sizes
[23:18:01] [PASSED] X0L2 Invalid pitch
[23:18:01] [PASSED] X0L2 Pitch greater than minimum required
[23:18:01] [PASSED] X0L2 Handle for inexistent plane
[23:18:01] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[23:18:01] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[23:18:01] [PASSED] X0L2 Valid modifier
[23:18:01] [PASSED] X0L2 Modifier for inexistent plane
[23:18:01] =========== [PASSED] drm_test_framebuffer_create ===========
[23:18:01] [PASSED] drm_test_framebuffer_free
[23:18:01] [PASSED] drm_test_framebuffer_init
[23:18:01] [PASSED] drm_test_framebuffer_init_bad_format
[23:18:01] [PASSED] drm_test_framebuffer_init_dev_mismatch
[23:18:01] [PASSED] drm_test_framebuffer_lookup
[23:18:01] [PASSED] drm_test_framebuffer_lookup_inexistent
[23:18:01] [PASSED] drm_test_framebuffer_modifiers_not_supported
[23:18:01] ================= [PASSED] drm_framebuffer =================
[23:18:01] ================ drm_gem_shmem (8 subtests) ================
[23:18:01] [PASSED] drm_gem_shmem_test_obj_create
[23:18:01] [PASSED] drm_gem_shmem_test_obj_create_private
[23:18:01] [PASSED] drm_gem_shmem_test_pin_pages
[23:18:01] [PASSED] drm_gem_shmem_test_vmap
[23:18:01] [PASSED] drm_gem_shmem_test_get_pages_sgt
[23:18:01] [PASSED] drm_gem_shmem_test_get_sg_table
[23:18:01] [PASSED] drm_gem_shmem_test_madvise
[23:18:01] [PASSED] drm_gem_shmem_test_purge
[23:18:01] ================== [PASSED] drm_gem_shmem ==================
[23:18:01] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[23:18:01] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[23:18:01] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[23:18:01] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[23:18:01] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[23:18:01] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[23:18:01] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[23:18:01] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[23:18:01] [PASSED] Automatic
[23:18:01] [PASSED] Full
[23:18:01] [PASSED] Limited 16:235
[23:18:01] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[23:18:01] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[23:18:01] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[23:18:01] [PASSED] drm_test_check_disable_connector
[23:18:01] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[23:18:01] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[23:18:01] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[23:18:01] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[23:18:01] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[23:18:01] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[23:18:01] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[23:18:01] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[23:18:01] [PASSED] drm_test_check_output_bpc_dvi
[23:18:01] [PASSED] drm_test_check_output_bpc_format_vic_1
[23:18:01] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[23:18:01] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[23:18:01] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[23:18:01] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[23:18:01] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[23:18:01] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[23:18:01] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[23:18:01] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[23:18:01] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[23:18:01] [PASSED] drm_test_check_broadcast_rgb_value
[23:18:01] [PASSED] drm_test_check_bpc_8_value
[23:18:01] [PASSED] drm_test_check_bpc_10_value
[23:18:01] [PASSED] drm_test_check_bpc_12_value
[23:18:01] [PASSED] drm_test_check_format_value
[23:18:01] [PASSED] drm_test_check_tmds_char_value
[23:18:01] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[23:18:01] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[23:18:01] [PASSED] drm_test_check_mode_valid
[23:18:01] [PASSED] drm_test_check_mode_valid_reject
[23:18:01] [PASSED] drm_test_check_mode_valid_reject_rate
[23:18:01] [PASSED] drm_test_check_mode_valid_reject_max_clock
[23:18:01] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[23:18:01] ================= drm_managed (2 subtests) =================
[23:18:01] [PASSED] drm_test_managed_release_action
[23:18:01] [PASSED] drm_test_managed_run_action
[23:18:01] =================== [PASSED] drm_managed ===================
[23:18:01] =================== drm_mm (6 subtests) ====================
[23:18:01] [PASSED] drm_test_mm_init
[23:18:01] [PASSED] drm_test_mm_debug
[23:18:01] [PASSED] drm_test_mm_align32
[23:18:01] [PASSED] drm_test_mm_align64
[23:18:01] [PASSED] drm_test_mm_lowest
[23:18:01] [PASSED] drm_test_mm_highest
[23:18:01] ===================== [PASSED] drm_mm ======================
[23:18:01] ============= drm_modes_analog_tv (5 subtests) =============
[23:18:01] [PASSED] drm_test_modes_analog_tv_mono_576i
[23:18:01] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[23:18:01] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[23:18:01] [PASSED] drm_test_modes_analog_tv_pal_576i
[23:18:01] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[23:18:01] =============== [PASSED] drm_modes_analog_tv ===============
[23:18:01] ============== drm_plane_helper (2 subtests) ===============
[23:18:01] =============== drm_test_check_plane_state ================
[23:18:01] [PASSED] clipping_simple
[23:18:01] [PASSED] clipping_rotate_reflect
[23:18:01] [PASSED] positioning_simple
[23:18:01] [PASSED] upscaling
[23:18:01] [PASSED] downscaling
[23:18:01] [PASSED] rounding1
[23:18:01] [PASSED] rounding2
[23:18:01] [PASSED] rounding3
[23:18:01] [PASSED] rounding4
[23:18:01] =========== [PASSED] drm_test_check_plane_state ============
[23:18:01] =========== drm_test_check_invalid_plane_state ============
[23:18:01] [PASSED] positioning_invalid
[23:18:01] [PASSED] upscaling_invalid
[23:18:01] [PASSED] downscaling_invalid
[23:18:01] ======= [PASSED] drm_test_check_invalid_plane_state ========
[23:18:01] ================ [PASSED] drm_plane_helper =================
[23:18:01] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[23:18:01] ====== drm_test_connector_helper_tv_get_modes_check =======
[23:18:01] [PASSED] None
[23:18:01] [PASSED] PAL
[23:18:01] [PASSED] NTSC
[23:18:01] [PASSED] Both, NTSC Default
[23:18:01] [PASSED] Both, PAL Default
[23:18:01] [PASSED] Both, NTSC Default, with PAL on command-line
[23:18:01] [PASSED] Both, PAL Default, with NTSC on command-line
[23:18:01] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[23:18:01] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[23:18:01] ================== drm_rect (9 subtests) ===================
[23:18:01] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[23:18:01] [PASSED] drm_test_rect_clip_scaled_not_clipped
[23:18:01] [PASSED] drm_test_rect_clip_scaled_clipped
[23:18:01] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[23:18:01] ================= drm_test_rect_intersect =================
[23:18:01] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[23:18:01] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[23:18:01] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[23:18:01] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[23:18:01] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[23:18:01] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[23:18:01] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[23:18:01] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[23:18:01] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[23:18:01] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[23:18:01] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[23:18:01] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[23:18:01] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[23:18:01] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[23:18:01] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[23:18:01] ============= [PASSED] drm_test_rect_intersect =============
[23:18:01] ================ drm_test_rect_calc_hscale ================
[23:18:01] [PASSED] normal use
[23:18:01] [PASSED] out of max range
[23:18:01] [PASSED] out of min range
[23:18:01] [PASSED] zero dst
[23:18:01] [PASSED] negative src
[23:18:01] [PASSED] negative dst
[23:18:01] ============ [PASSED] drm_test_rect_calc_hscale ============
[23:18:01] ================ drm_test_rect_calc_vscale ================
[23:18:01] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[23:18:01] [PASSED] out of max range
[23:18:01] [PASSED] out of min range
[23:18:01] [PASSED] zero dst
[23:18:01] [PASSED] negative src
[23:18:01] [PASSED] negative dst
[23:18:01] ============ [PASSED] drm_test_rect_calc_vscale ============
[23:18:01] ================== drm_test_rect_rotate ===================
[23:18:01] [PASSED] reflect-x
[23:18:01] [PASSED] reflect-y
[23:18:01] [PASSED] rotate-0
[23:18:01] [PASSED] rotate-90
[23:18:01] [PASSED] rotate-180
[23:18:01] [PASSED] rotate-270
[23:18:01] ============== [PASSED] drm_test_rect_rotate ===============
[23:18:01] ================ drm_test_rect_rotate_inv =================
[23:18:01] [PASSED] reflect-x
[23:18:01] [PASSED] reflect-y
[23:18:01] [PASSED] rotate-0
[23:18:01] [PASSED] rotate-90
[23:18:01] [PASSED] rotate-180
[23:18:01] [PASSED] rotate-270
[23:18:01] ============ [PASSED] drm_test_rect_rotate_inv =============
[23:18:01] ==================== [PASSED] drm_rect =====================
[23:18:01] ============ drm_sysfb_modeset_test (1 subtest) ============
[23:18:01] ============ drm_test_sysfb_build_fourcc_list =============
[23:18:01] [PASSED] no native formats
[23:18:01] [PASSED] XRGB8888 as native format
[23:18:01] [PASSED] remove duplicates
[23:18:01] [PASSED] convert alpha formats
[23:18:01] [PASSED] random formats
[23:18:01] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[23:18:01] ============= [PASSED] drm_sysfb_modeset_test ==============
[23:18:01] ============================================================
[23:18:01] Testing complete. Ran 622 tests: passed: 622
[23:18:01] Elapsed time: 26.753s total, 1.761s configuring, 24.572s building, 0.391s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[23:18:01] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[23:18:03] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[23:18:13] Starting KUnit Kernel (1/1)...
[23:18:13] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[23:18:13] ================= ttm_device (5 subtests) ==================
[23:18:13] [PASSED] ttm_device_init_basic
[23:18:13] [PASSED] ttm_device_init_multiple
[23:18:13] [PASSED] ttm_device_fini_basic
[23:18:13] [PASSED] ttm_device_init_no_vma_man
[23:18:13] ================== ttm_device_init_pools ==================
[23:18:13] [PASSED] No DMA allocations, no DMA32 required
[23:18:13] [PASSED] DMA allocations, DMA32 required
[23:18:13] [PASSED] No DMA allocations, DMA32 required
[23:18:13] [PASSED] DMA allocations, no DMA32 required
[23:18:13] ============== [PASSED] ttm_device_init_pools ==============
[23:18:13] =================== [PASSED] ttm_device ====================
[23:18:13] ================== ttm_pool (8 subtests) ===================
[23:18:13] ================== ttm_pool_alloc_basic ===================
[23:18:13] [PASSED] One page
[23:18:13] [PASSED] More than one page
[23:18:13] [PASSED] Above the allocation limit
[23:18:13] [PASSED] One page, with coherent DMA mappings enabled
[23:18:13] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[23:18:13] ============== [PASSED] ttm_pool_alloc_basic ===============
[23:18:13] ============== ttm_pool_alloc_basic_dma_addr ==============
[23:18:13] [PASSED] One page
[23:18:13] [PASSED] More than one page
[23:18:13] [PASSED] Above the allocation limit
[23:18:13] [PASSED] One page, with coherent DMA mappings enabled
[23:18:13] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[23:18:13] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[23:18:13] [PASSED] ttm_pool_alloc_order_caching_match
[23:18:13] [PASSED] ttm_pool_alloc_caching_mismatch
[23:18:13] [PASSED] ttm_pool_alloc_order_mismatch
[23:18:13] [PASSED] ttm_pool_free_dma_alloc
[23:18:13] [PASSED] ttm_pool_free_no_dma_alloc
[23:18:13] [PASSED] ttm_pool_fini_basic
[23:18:13] ==================== [PASSED] ttm_pool =====================
[23:18:13] ================ ttm_resource (8 subtests) =================
[23:18:13] ================= ttm_resource_init_basic =================
[23:18:13] [PASSED] Init resource in TTM_PL_SYSTEM
[23:18:13] [PASSED] Init resource in TTM_PL_VRAM
[23:18:13] [PASSED] Init resource in a private placement
[23:18:13] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[23:18:13] ============= [PASSED] ttm_resource_init_basic =============
[23:18:13] [PASSED] ttm_resource_init_pinned
[23:18:13] [PASSED] ttm_resource_fini_basic
[23:18:13] [PASSED] ttm_resource_manager_init_basic
[23:18:13] [PASSED] ttm_resource_manager_usage_basic
[23:18:13] [PASSED] ttm_resource_manager_set_used_basic
[23:18:13] [PASSED] ttm_sys_man_alloc_basic
[23:18:13] [PASSED] ttm_sys_man_free_basic
[23:18:13] ================== [PASSED] ttm_resource ===================
[23:18:13] =================== ttm_tt (15 subtests) ===================
[23:18:13] ==================== ttm_tt_init_basic ====================
[23:18:13] [PASSED] Page-aligned size
[23:18:13] [PASSED] Extra pages requested
[23:18:13] ================ [PASSED] ttm_tt_init_basic ================
[23:18:13] [PASSED] ttm_tt_init_misaligned
[23:18:13] [PASSED] ttm_tt_fini_basic
[23:18:13] [PASSED] ttm_tt_fini_sg
[23:18:13] [PASSED] ttm_tt_fini_shmem
[23:18:13] [PASSED] ttm_tt_create_basic
[23:18:13] [PASSED] ttm_tt_create_invalid_bo_type
[23:18:13] [PASSED] ttm_tt_create_ttm_exists
[23:18:13] [PASSED] ttm_tt_create_failed
[23:18:13] [PASSED] ttm_tt_destroy_basic
[23:18:13] [PASSED] ttm_tt_populate_null_ttm
[23:18:13] [PASSED] ttm_tt_populate_populated_ttm
[23:18:13] [PASSED] ttm_tt_unpopulate_basic
[23:18:13] [PASSED] ttm_tt_unpopulate_empty_ttm
[23:18:13] [PASSED] ttm_tt_swapin_basic
[23:18:13] ===================== [PASSED] ttm_tt ======================
[23:18:13] =================== ttm_bo (14 subtests) ===================
[23:18:13] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[23:18:13] [PASSED] Cannot be interrupted and sleeps
[23:18:13] [PASSED] Cannot be interrupted, locks straight away
[23:18:13] [PASSED] Can be interrupted, sleeps
[23:18:13] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[23:18:13] [PASSED] ttm_bo_reserve_locked_no_sleep
[23:18:13] [PASSED] ttm_bo_reserve_no_wait_ticket
[23:18:13] [PASSED] ttm_bo_reserve_double_resv
[23:18:13] [PASSED] ttm_bo_reserve_interrupted
[23:18:13] [PASSED] ttm_bo_reserve_deadlock
[23:18:13] [PASSED] ttm_bo_unreserve_basic
[23:18:13] [PASSED] ttm_bo_unreserve_pinned
[23:18:13] [PASSED] ttm_bo_unreserve_bulk
[23:18:13] [PASSED] ttm_bo_fini_basic
[23:18:13] [PASSED] ttm_bo_fini_shared_resv
[23:18:13] [PASSED] ttm_bo_pin_basic
[23:18:13] [PASSED] ttm_bo_pin_unpin_resource
[23:18:13] [PASSED] ttm_bo_multiple_pin_one_unpin
[23:18:13] ===================== [PASSED] ttm_bo ======================
[23:18:13] ============== ttm_bo_validate (21 subtests) ===============
[23:18:13] ============== ttm_bo_init_reserved_sys_man ===============
[23:18:13] [PASSED] Buffer object for userspace
[23:18:13] [PASSED] Kernel buffer object
[23:18:13] [PASSED] Shared buffer object
[23:18:13] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[23:18:13] ============== ttm_bo_init_reserved_mock_man ==============
[23:18:13] [PASSED] Buffer object for userspace
[23:18:13] [PASSED] Kernel buffer object
[23:18:13] [PASSED] Shared buffer object
[23:18:13] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[23:18:13] [PASSED] ttm_bo_init_reserved_resv
[23:18:13] ================== ttm_bo_validate_basic ==================
[23:18:13] [PASSED] Buffer object for userspace
[23:18:13] [PASSED] Kernel buffer object
[23:18:13] [PASSED] Shared buffer object
[23:18:13] ============== [PASSED] ttm_bo_validate_basic ==============
[23:18:13] [PASSED] ttm_bo_validate_invalid_placement
[23:18:13] ============= ttm_bo_validate_same_placement ==============
[23:18:13] [PASSED] System manager
[23:18:13] [PASSED] VRAM manager
[23:18:13] ========= [PASSED] ttm_bo_validate_same_placement ==========
[23:18:13] [PASSED] ttm_bo_validate_failed_alloc
[23:18:13] [PASSED] ttm_bo_validate_pinned
[23:18:13] [PASSED] ttm_bo_validate_busy_placement
[23:18:13] ================ ttm_bo_validate_multihop =================
[23:18:13] [PASSED] Buffer object for userspace
[23:18:13] [PASSED] Kernel buffer object
[23:18:13] [PASSED] Shared buffer object
[23:18:13] ============ [PASSED] ttm_bo_validate_multihop =============
[23:18:13] ========== ttm_bo_validate_no_placement_signaled ==========
[23:18:13] [PASSED] Buffer object in system domain, no page vector
[23:18:13] [PASSED] Buffer object in system domain with an existing page vector
[23:18:13] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[23:18:13] ======== ttm_bo_validate_no_placement_not_signaled ========
[23:18:13] [PASSED] Buffer object for userspace
[23:18:13] [PASSED] Kernel buffer object
[23:18:13] [PASSED] Shared buffer object
[23:18:13] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[23:18:13] [PASSED] ttm_bo_validate_move_fence_signaled
[23:18:13] ========= ttm_bo_validate_move_fence_not_signaled =========
[23:18:13] [PASSED] Waits for GPU
[23:18:13] [PASSED] Tries to lock straight away
[23:18:13] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[23:18:13] [PASSED] ttm_bo_validate_happy_evict
[23:18:13] [PASSED] ttm_bo_validate_all_pinned_evict
[23:18:13] [PASSED] ttm_bo_validate_allowed_only_evict
[23:18:13] [PASSED] ttm_bo_validate_deleted_evict
[23:18:13] [PASSED] ttm_bo_validate_busy_domain_evict
[23:18:13] [PASSED] ttm_bo_validate_evict_gutting
[23:18:13] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[23:18:13] ================= [PASSED] ttm_bo_validate =================
[23:18:13] ============================================================
[23:18:13] Testing complete. Ran 101 tests: passed: 101
[23:18:13] Elapsed time: 11.495s total, 1.738s configuring, 9.490s building, 0.218s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 27+ messages in thread* ✗ Xe.CI.BAT: failure for drm/xe: Multi Queue feature support (rev2)
2025-11-04 18:51 [PATCH v2 00/16] drm/xe: Multi Queue feature support Niranjana Vishwanathapura
` (17 preceding siblings ...)
2025-11-04 23:18 ` ✓ CI.KUnit: success " Patchwork
@ 2025-11-05 0:14 ` Patchwork
2025-11-05 7:10 ` ✗ Xe.CI.Full: " Patchwork
19 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2025-11-05 0:14 UTC (permalink / raw)
To: Niranjana Vishwanathapura; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 5828 bytes --]
== Series Details ==
Series: drm/xe: Multi Queue feature support (rev2)
URL : https://patchwork.freedesktop.org/series/156865/
State : failure
== Summary ==
CI Bug Log - changes from xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d_BAT -> xe-pw-156865v2_BAT
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-156865v2_BAT absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-156865v2_BAT, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-156865v2_BAT:
### IGT changes ###
#### Possible regressions ####
* igt@xe_exec_queue_property@invalid-property:
- bat-ptl-2: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/bat-ptl-2/igt@xe_exec_queue_property@invalid-property.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/bat-ptl-2/igt@xe_exec_queue_property@invalid-property.html
- bat-dg2-oem2: [PASS][3] -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/bat-dg2-oem2/igt@xe_exec_queue_property@invalid-property.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/bat-dg2-oem2/igt@xe_exec_queue_property@invalid-property.html
- bat-atsm-2: [PASS][5] -> [FAIL][6]
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/bat-atsm-2/igt@xe_exec_queue_property@invalid-property.html
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/bat-atsm-2/igt@xe_exec_queue_property@invalid-property.html
- bat-adlp-vm: [PASS][7] -> [FAIL][8]
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/bat-adlp-vm/igt@xe_exec_queue_property@invalid-property.html
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/bat-adlp-vm/igt@xe_exec_queue_property@invalid-property.html
- bat-ptl-1: [PASS][9] -> [FAIL][10]
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/bat-ptl-1/igt@xe_exec_queue_property@invalid-property.html
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/bat-ptl-1/igt@xe_exec_queue_property@invalid-property.html
- bat-lnl-1: [PASS][11] -> [FAIL][12]
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/bat-lnl-1/igt@xe_exec_queue_property@invalid-property.html
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/bat-lnl-1/igt@xe_exec_queue_property@invalid-property.html
- bat-bmg-2: [PASS][13] -> [FAIL][14]
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/bat-bmg-2/igt@xe_exec_queue_property@invalid-property.html
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/bat-bmg-2/igt@xe_exec_queue_property@invalid-property.html
- bat-adlp-7: [PASS][15] -> [FAIL][16]
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/bat-adlp-7/igt@xe_exec_queue_property@invalid-property.html
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/bat-adlp-7/igt@xe_exec_queue_property@invalid-property.html
- bat-bmg-1: [PASS][17] -> [FAIL][18]
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/bat-bmg-1/igt@xe_exec_queue_property@invalid-property.html
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/bat-bmg-1/igt@xe_exec_queue_property@invalid-property.html
- bat-lnl-2: [PASS][19] -> [FAIL][20]
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/bat-lnl-2/igt@xe_exec_queue_property@invalid-property.html
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/bat-lnl-2/igt@xe_exec_queue_property@invalid-property.html
Known issues
------------
Here are the changes found in xe-pw-156865v2_BAT that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_flip@basic-flip-vs-modeset:
- bat-adlp-7: [PASS][21] -> [DMESG-WARN][22] ([Intel XE#4543]) +1 other test dmesg-warn
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/bat-adlp-7/igt@kms_flip@basic-flip-vs-modeset.html
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/bat-adlp-7/igt@kms_flip@basic-flip-vs-modeset.html
#### Possible fixes ####
* igt@kms_flip@basic-plain-flip@a-edp1:
- bat-adlp-7: [DMESG-WARN][23] ([Intel XE#4543]) -> [PASS][24] +1 other test pass
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/bat-adlp-7/igt@kms_flip@basic-plain-flip@a-edp1.html
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/bat-adlp-7/igt@kms_flip@basic-plain-flip@a-edp1.html
[Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
Build changes
-------------
* Linux: xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d -> xe-pw-156865v2
IGT_8607: 8607
xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d: 5fc5af47c48c461ff910c39f88694b966fcebc5d
xe-pw-156865v2: 156865v2
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/index.html
[-- Attachment #2: Type: text/html, Size: 6574 bytes --]
^ permalink raw reply [flat|nested] 27+ messages in thread* ✗ Xe.CI.Full: failure for drm/xe: Multi Queue feature support (rev2)
2025-11-04 18:51 [PATCH v2 00/16] drm/xe: Multi Queue feature support Niranjana Vishwanathapura
` (18 preceding siblings ...)
2025-11-05 0:14 ` ✗ Xe.CI.BAT: failure " Patchwork
@ 2025-11-05 7:10 ` Patchwork
19 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2025-11-05 7:10 UTC (permalink / raw)
To: Niranjana Vishwanathapura; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 40975 bytes --]
== Series Details ==
Series: drm/xe: Multi Queue feature support (rev2)
URL : https://patchwork.freedesktop.org/series/156865/
State : failure
== Summary ==
CI Bug Log - changes from xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d_FULL -> xe-pw-156865v2_FULL
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-156865v2_FULL absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-156865v2_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (4 -> 4)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-156865v2_FULL:
### IGT changes ###
#### Possible regressions ####
* igt@xe_exec_queue_property@invalid-property:
- shard-dg2-set2: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-dg2-432/igt@xe_exec_queue_property@invalid-property.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-dg2-432/igt@xe_exec_queue_property@invalid-property.html
- shard-lnl: [PASS][3] -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-lnl-2/igt@xe_exec_queue_property@invalid-property.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-lnl-2/igt@xe_exec_queue_property@invalid-property.html
- shard-adlp: [PASS][5] -> [FAIL][6]
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-adlp-6/igt@xe_exec_queue_property@invalid-property.html
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-adlp-6/igt@xe_exec_queue_property@invalid-property.html
- shard-bmg: [PASS][7] -> [FAIL][8]
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-bmg-5/igt@xe_exec_queue_property@invalid-property.html
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-5/igt@xe_exec_queue_property@invalid-property.html
Known issues
------------
Here are the changes found in xe-pw-156865v2_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- shard-bmg: NOTRUN -> [SKIP][9] ([Intel XE#2233])
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-4/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
* igt@kms_big_fb@4-tiled-8bpp-rotate-90:
- shard-dg2-set2: NOTRUN -> [SKIP][10] ([Intel XE#316]) +1 other test skip
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-dg2-436/igt@kms_big_fb@4-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-adlp: [PASS][11] -> [DMESG-WARN][12] ([Intel XE#2953] / [Intel XE#4173])
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-adlp-9/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-adlp-8/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-180:
- shard-bmg: NOTRUN -> [SKIP][13] ([Intel XE#1124]) +2 other tests skip
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-4/igt@kms_big_fb@yf-tiled-8bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-dg2-set2: NOTRUN -> [SKIP][14] ([Intel XE#1124]) +2 other tests skip
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-dg2-466/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p:
- shard-bmg: [PASS][15] -> [SKIP][16] ([Intel XE#2314] / [Intel XE#2894])
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-bmg-7/igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p.html
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-6/igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p.html
* igt@kms_bw@connected-linear-tiling-3-displays-3840x2160p:
- shard-dg2-set2: NOTRUN -> [SKIP][17] ([Intel XE#2191])
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-dg2-466/igt@kms_bw@connected-linear-tiling-3-displays-3840x2160p.html
* igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc:
- shard-bmg: NOTRUN -> [SKIP][18] ([Intel XE#2887]) +4 other tests skip
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-4/igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc.html
* igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs:
- shard-dg2-set2: NOTRUN -> [SKIP][19] ([Intel XE#455] / [Intel XE#787]) +5 other tests skip
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-dg2-436/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs.html
* igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-6:
- shard-dg2-set2: NOTRUN -> [SKIP][20] ([Intel XE#787]) +20 other tests skip
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-dg2-436/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-6.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs:
- shard-dg2-set2: NOTRUN -> [SKIP][21] ([Intel XE#2907])
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-dg2-436/igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
- shard-bmg: [PASS][22] -> [INCOMPLETE][23] ([Intel XE#3862]) +1 other test incomplete
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-bmg-2/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-8/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs@pipe-c-dp-2:
- shard-bmg: NOTRUN -> [SKIP][24] ([Intel XE#2652] / [Intel XE#787]) +7 other tests skip
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-2/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs@pipe-c-dp-2.html
* igt@kms_cdclk@plane-scaling@pipe-b-dp-4:
- shard-dg2-set2: NOTRUN -> [SKIP][25] ([Intel XE#4416]) +3 other tests skip
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-dg2-466/igt@kms_cdclk@plane-scaling@pipe-b-dp-4.html
* igt@kms_chamelium_color@ctm-red-to-blue:
- shard-dg2-set2: NOTRUN -> [SKIP][26] ([Intel XE#306])
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-dg2-466/igt@kms_chamelium_color@ctm-red-to-blue.html
* igt@kms_chamelium_hpd@dp-hpd-enable-disable-mode:
- shard-bmg: NOTRUN -> [SKIP][27] ([Intel XE#2252]) +1 other test skip
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-4/igt@kms_chamelium_hpd@dp-hpd-enable-disable-mode.html
* igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode:
- shard-dg2-set2: NOTRUN -> [SKIP][28] ([Intel XE#373]) +3 other tests skip
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-dg2-466/igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode.html
* igt@kms_content_protection@legacy:
- shard-bmg: NOTRUN -> [FAIL][29] ([Intel XE#1178]) +1 other test fail
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-4/igt@kms_content_protection@legacy.html
* igt@kms_content_protection@uevent@pipe-a-dp-2:
- shard-bmg: NOTRUN -> [FAIL][30] ([Intel XE#1188])
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-7/igt@kms_content_protection@uevent@pipe-a-dp-2.html
* igt@kms_cursor_crc@cursor-sliding-512x170:
- shard-bmg: NOTRUN -> [SKIP][31] ([Intel XE#2321])
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-4/igt@kms_cursor_crc@cursor-sliding-512x170.html
* igt@kms_cursor_legacy@cursora-vs-flipb-varying-size:
- shard-bmg: [PASS][32] -> [DMESG-WARN][33] ([Intel XE#5354])
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-bmg-4/igt@kms_cursor_legacy@cursora-vs-flipb-varying-size.html
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-1/igt@kms_cursor_legacy@cursora-vs-flipb-varying-size.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
- shard-bmg: [PASS][34] -> [SKIP][35] ([Intel XE#2291]) +2 other tests skip
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-bmg-7/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html
* igt@kms_cursor_legacy@flip-vs-cursor-legacy:
- shard-bmg: [PASS][36] -> [FAIL][37] ([Intel XE#5299])
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-bmg-6/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-7/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
- shard-dg2-set2: NOTRUN -> [SKIP][38] ([Intel XE#323])
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-dg2-466/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
* igt@kms_dp_link_training@non-uhbr-sst:
- shard-bmg: [PASS][39] -> [SKIP][40] ([Intel XE#4354])
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-bmg-7/igt@kms_dp_link_training@non-uhbr-sst.html
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-6/igt@kms_dp_link_training@non-uhbr-sst.html
* igt@kms_dsc@dsc-with-bpc:
- shard-dg2-set2: NOTRUN -> [SKIP][41] ([Intel XE#455]) +4 other tests skip
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-dg2-435/igt@kms_dsc@dsc-with-bpc.html
* igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-different-formats:
- shard-dg2-set2: NOTRUN -> [SKIP][42] ([Intel XE#4422])
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-dg2-436/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-different-formats.html
* igt@kms_flip@2x-flip-vs-panning-vs-hang:
- shard-bmg: [PASS][43] -> [SKIP][44] ([Intel XE#2316]) +4 other tests skip
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-bmg-7/igt@kms_flip@2x-flip-vs-panning-vs-hang.html
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-6/igt@kms_flip@2x-flip-vs-panning-vs-hang.html
* igt@kms_flip@blocking-wf_vblank@a-hdmi-a1:
- shard-adlp: [PASS][45] -> [FAIL][46] ([Intel XE#5408]) +1 other test fail
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-adlp-3/igt@kms_flip@blocking-wf_vblank@a-hdmi-a1.html
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-adlp-9/igt@kms_flip@blocking-wf_vblank@a-hdmi-a1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-dp4:
- shard-dg2-set2: [PASS][47] -> [FAIL][48] ([Intel XE#301]) +1 other test fail
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-dg2-433/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-dp4.html
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-dg2-432/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-dp4.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
- shard-lnl: [PASS][49] -> [FAIL][50] ([Intel XE#301] / [Intel XE#3149])
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-lnl: [PASS][51] -> [FAIL][52] ([Intel XE#301]) +1 other test fail
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-lnl-7/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@flip-vs-rmfb:
- shard-adlp: [PASS][53] -> [DMESG-WARN][54] ([Intel XE#4543] / [Intel XE#5208])
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-adlp-2/igt@kms_flip@flip-vs-rmfb.html
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-adlp-8/igt@kms_flip@flip-vs-rmfb.html
* igt@kms_flip@flip-vs-wf_vblank-interruptible:
- shard-adlp: [PASS][55] -> [DMESG-WARN][56] ([Intel XE#4543]) +2 other tests dmesg-warn
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-adlp-2/igt@kms_flip@flip-vs-wf_vblank-interruptible.html
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-adlp-2/igt@kms_flip@flip-vs-wf_vblank-interruptible.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling:
- shard-bmg: NOTRUN -> [SKIP][57] ([Intel XE#2293] / [Intel XE#2380]) +1 other test skip
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-4/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode:
- shard-bmg: NOTRUN -> [SKIP][58] ([Intel XE#2293]) +1 other test skip
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-4/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-shrfb-draw-render:
- shard-bmg: NOTRUN -> [SKIP][59] ([Intel XE#2311]) +6 other tests skip
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-blt:
- shard-dg2-set2: NOTRUN -> [SKIP][60] ([Intel XE#651]) +3 other tests skip
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-dg2-466/igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-shrfb-draw-blt:
- shard-bmg: NOTRUN -> [SKIP][61] ([Intel XE#6313])
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen:
- shard-bmg: NOTRUN -> [SKIP][62] ([Intel XE#5390]) +4 other tests skip
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-render:
- shard-dg2-set2: NOTRUN -> [SKIP][63] ([Intel XE#653]) +5 other tests skip
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-dg2-436/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt:
- shard-bmg: NOTRUN -> [SKIP][64] ([Intel XE#2313]) +7 other tests skip
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html
* igt@kms_hdr@brightness-with-hdr:
- shard-bmg: NOTRUN -> [SKIP][65] ([Intel XE#3374] / [Intel XE#3544])
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-4/igt@kms_hdr@brightness-with-hdr.html
* igt@kms_hdr@invalid-metadata-sizes:
- shard-bmg: [PASS][66] -> [SKIP][67] ([Intel XE#1503])
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-bmg-7/igt@kms_hdr@invalid-metadata-sizes.html
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-6/igt@kms_hdr@invalid-metadata-sizes.html
* igt@kms_joiner@basic-max-non-joiner:
- shard-bmg: NOTRUN -> [SKIP][68] ([Intel XE#4298])
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-4/igt@kms_joiner@basic-max-non-joiner.html
* igt@kms_joiner@invalid-modeset-force-big-joiner:
- shard-bmg: [PASS][69] -> [SKIP][70] ([Intel XE#3012])
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-bmg-7/igt@kms_joiner@invalid-modeset-force-big-joiner.html
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-6/igt@kms_joiner@invalid-modeset-force-big-joiner.html
* igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-sf:
- shard-bmg: NOTRUN -> [SKIP][71] ([Intel XE#1406] / [Intel XE#1489]) +3 other tests skip
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-4/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-sf.html
* igt@kms_psr2_sf@fbc-pr-overlay-plane-update-continuous-sf:
- shard-dg2-set2: NOTRUN -> [SKIP][72] ([Intel XE#1406] / [Intel XE#1489])
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-dg2-466/igt@kms_psr2_sf@fbc-pr-overlay-plane-update-continuous-sf.html
* igt@kms_psr@pr-primary-page-flip:
- shard-dg2-set2: NOTRUN -> [SKIP][73] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) +2 other tests skip
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-dg2-436/igt@kms_psr@pr-primary-page-flip.html
* igt@kms_psr@psr-basic:
- shard-bmg: NOTRUN -> [SKIP][74] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +2 other tests skip
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-4/igt@kms_psr@psr-basic.html
* igt@kms_rotation_crc@primary-rotation-90:
- shard-bmg: NOTRUN -> [SKIP][75] ([Intel XE#3414] / [Intel XE#3904])
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-4/igt@kms_rotation_crc@primary-rotation-90.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
- shard-bmg: NOTRUN -> [SKIP][76] ([Intel XE#2330])
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-4/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
* igt@kms_setmode@invalid-clone-single-crtc:
- shard-bmg: [PASS][77] -> [SKIP][78] ([Intel XE#1435])
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-bmg-7/igt@kms_setmode@invalid-clone-single-crtc.html
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-6/igt@kms_setmode@invalid-clone-single-crtc.html
* igt@xe_eu_stall@blocking-read:
- shard-dg2-set2: NOTRUN -> [SKIP][79] ([Intel XE#5626]) +1 other test skip
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-dg2-436/igt@xe_eu_stall@blocking-read.html
* igt@xe_eudebug@basic-client-th:
- shard-dg2-set2: NOTRUN -> [SKIP][80] ([Intel XE#4837])
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-dg2-436/igt@xe_eudebug@basic-client-th.html
* igt@xe_eudebug_online@writes-caching-sram-bb-vram-target-vram:
- shard-bmg: NOTRUN -> [SKIP][81] ([Intel XE#4837]) +3 other tests skip
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-4/igt@xe_eudebug_online@writes-caching-sram-bb-vram-target-vram.html
* igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue:
- shard-bmg: NOTRUN -> [SKIP][82] ([Intel XE#2322]) +1 other test skip
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-4/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue.html
* igt@xe_exec_fault_mode@twice-userptr-prefetch:
- shard-dg2-set2: NOTRUN -> [SKIP][83] ([Intel XE#288]) +5 other tests skip
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-dg2-435/igt@xe_exec_fault_mode@twice-userptr-prefetch.html
* igt@xe_exec_mix_modes@exec-spinner-interrupted-dma-fence:
- shard-dg2-set2: NOTRUN -> [SKIP][84] ([Intel XE#2360])
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-dg2-466/igt@xe_exec_mix_modes@exec-spinner-interrupted-dma-fence.html
* igt@xe_exec_system_allocator@threads-many-large-execqueues-malloc-mlock-nomemset:
- shard-dg2-set2: NOTRUN -> [SKIP][85] ([Intel XE#4915]) +68 other tests skip
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-dg2-436/igt@xe_exec_system_allocator@threads-many-large-execqueues-malloc-mlock-nomemset.html
* igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-free-huge:
- shard-bmg: NOTRUN -> [SKIP][86] ([Intel XE#4943]) +8 other tests skip
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-4/igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-free-huge.html
* igt@xe_oa@buffer-size:
- shard-dg2-set2: NOTRUN -> [SKIP][87] ([Intel XE#6032])
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-dg2-466/igt@xe_oa@buffer-size.html
* igt@xe_oa@oa-tlb-invalidate:
- shard-dg2-set2: NOTRUN -> [SKIP][88] ([Intel XE#3573]) +1 other test skip
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-dg2-466/igt@xe_oa@oa-tlb-invalidate.html
* igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_compute0:
- shard-lnl: [PASS][89] -> [FAIL][90] ([Intel XE#6251]) +1 other test fail
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-lnl-5/igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_compute0.html
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-lnl-7/igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_compute0.html
* igt@xe_pmu@fn-engine-activity-sched-if-idle@engine-drm_xe_engine_class_video_enhance1:
- shard-bmg: [PASS][91] -> [DMESG-WARN][92] ([Intel XE#3876] / [Intel XE#3970]) +1 other test dmesg-warn
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-bmg-1/igt@xe_pmu@fn-engine-activity-sched-if-idle@engine-drm_xe_engine_class_video_enhance1.html
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-8/igt@xe_pmu@fn-engine-activity-sched-if-idle@engine-drm_xe_engine_class_video_enhance1.html
* igt@xe_query@multigpu-query-topology-l3-bank-mask:
- shard-bmg: NOTRUN -> [SKIP][93] ([Intel XE#944])
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-4/igt@xe_query@multigpu-query-topology-l3-bank-mask.html
* igt@xe_sriov_flr@flr-vfs-parallel:
- shard-dg2-set2: NOTRUN -> [SKIP][94] ([Intel XE#4273])
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-dg2-436/igt@xe_sriov_flr@flr-vfs-parallel.html
#### Possible fixes ####
* igt@kms_addfb_basic@size-max:
- shard-adlp: [DMESG-WARN][95] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][96] +7 other tests pass
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-adlp-4/igt@kms_addfb_basic@size-max.html
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-adlp-6/igt@kms_addfb_basic@size-max.html
* igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p:
- shard-bmg: [SKIP][97] ([Intel XE#2314] / [Intel XE#2894]) -> [PASS][98] +1 other test pass
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-bmg-6/igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p.html
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-1/igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p.html
* igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
- shard-bmg: [SKIP][99] ([Intel XE#2291]) -> [PASS][100] +1 other test pass
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-bmg-6/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-2/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@single-move:
- shard-dg2-set2: [DMESG-WARN][101] ([Intel XE#6363]) -> [PASS][102] +1 other test pass
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-dg2-435/igt@kms_cursor_legacy@single-move.html
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-dg2-466/igt@kms_cursor_legacy@single-move.html
* igt@kms_flip@2x-flip-vs-dpms-on-nop:
- shard-bmg: [SKIP][103] ([Intel XE#2316]) -> [PASS][104] +8 other tests pass
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-bmg-6/igt@kms_flip@2x-flip-vs-dpms-on-nop.html
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-7/igt@kms_flip@2x-flip-vs-dpms-on-nop.html
* igt@kms_hdr@invalid-hdr:
- shard-dg2-set2: [SKIP][105] ([Intel XE#455]) -> [PASS][106]
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-dg2-432/igt@kms_hdr@invalid-hdr.html
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-dg2-463/igt@kms_hdr@invalid-hdr.html
* igt@kms_vrr@negative-basic:
- shard-bmg: [SKIP][107] ([Intel XE#1499]) -> [PASS][108]
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-bmg-6/igt@kms_vrr@negative-basic.html
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-7/igt@kms_vrr@negative-basic.html
* igt@xe_evict@evict-beng-mixed-many-threads-small:
- shard-dg2-set2: [INCOMPLETE][109] -> [PASS][110] +1 other test pass
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-dg2-435/igt@xe_evict@evict-beng-mixed-many-threads-small.html
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-dg2-466/igt@xe_evict@evict-beng-mixed-many-threads-small.html
* igt@xe_evict@evict-mixed-many-threads-small:
- shard-bmg: [INCOMPLETE][111] ([Intel XE#6321]) -> [PASS][112]
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-bmg-5/igt@xe_evict@evict-mixed-many-threads-small.html
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-5/igt@xe_evict@evict-mixed-many-threads-small.html
* igt@xe_exec_threads@threads-bal-mixed-userptr-invalidate:
- shard-dg2-set2: [ABORT][113] -> [PASS][114]
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-dg2-436/igt@xe_exec_threads@threads-bal-mixed-userptr-invalidate.html
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-dg2-435/igt@xe_exec_threads@threads-bal-mixed-userptr-invalidate.html
* igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv:
- shard-dg2-set2: [DMESG-WARN][115] ([Intel XE#5893]) -> [PASS][116]
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-dg2-435/igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv.html
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-dg2-466/igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv.html
* igt@xe_pm@s2idle-basic-exec:
- shard-adlp: [DMESG-WARN][117] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#4504]) -> [PASS][118]
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-adlp-4/igt@xe_pm@s2idle-basic-exec.html
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-adlp-6/igt@xe_pm@s2idle-basic-exec.html
* igt@xe_pmu@engine-activity-accuracy-50:
- shard-lnl: [FAIL][119] ([Intel XE#6251]) -> [PASS][120] +1 other test pass
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-lnl-1/igt@xe_pmu@engine-activity-accuracy-50.html
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-lnl-1/igt@xe_pmu@engine-activity-accuracy-50.html
* igt@xe_pmu@gt-frequency:
- shard-dg2-set2: [FAIL][121] ([Intel XE#5166]) -> [PASS][122] +1 other test pass
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-dg2-435/igt@xe_pmu@gt-frequency.html
[122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-dg2-466/igt@xe_pmu@gt-frequency.html
#### Warnings ####
* igt@kms_content_protection@lic-type-0:
- shard-bmg: [FAIL][123] ([Intel XE#1178]) -> [SKIP][124] ([Intel XE#2341])
[123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-bmg-7/igt@kms_content_protection@lic-type-0.html
[124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-6/igt@kms_content_protection@lic-type-0.html
* igt@kms_content_protection@uevent:
- shard-bmg: [SKIP][125] ([Intel XE#2341]) -> [FAIL][126] ([Intel XE#1188])
[125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-bmg-6/igt@kms_content_protection@uevent.html
[126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-7/igt@kms_content_protection@uevent.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-lnl: [FAIL][127] ([Intel XE#301]) -> [FAIL][128] ([Intel XE#301] / [Intel XE#3149])
[127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-render:
- shard-bmg: [SKIP][129] ([Intel XE#2311]) -> [SKIP][130] ([Intel XE#2312]) +10 other tests skip
[129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-bmg-7/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-render.html
[130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][131] ([Intel XE#5390]) -> [SKIP][132] ([Intel XE#2312]) +5 other tests skip
[131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc.html
[132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt:
- shard-bmg: [SKIP][133] ([Intel XE#2312]) -> [SKIP][134] ([Intel XE#5390]) +7 other tests skip
[133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt.html
[134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][135] ([Intel XE#2312]) -> [SKIP][136] ([Intel XE#2311]) +16 other tests skip
[135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html
[136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt:
- shard-bmg: [SKIP][137] ([Intel XE#2312]) -> [SKIP][138] ([Intel XE#2313]) +11 other tests skip
[137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt.html
[138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt:
- shard-bmg: [SKIP][139] ([Intel XE#2313]) -> [SKIP][140] ([Intel XE#2312]) +11 other tests skip
[139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-bmg-7/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
[140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
* igt@kms_tiled_display@basic-test-pattern:
- shard-bmg: [SKIP][141] ([Intel XE#2426]) -> [FAIL][142] ([Intel XE#1729])
[141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d/shard-bmg-6/igt@kms_tiled_display@basic-test-pattern.html
[142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/shard-bmg-1/igt@kms_tiled_display@basic-test-pattern.html
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
[Intel XE#1188]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1188
[Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
[Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
[Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
[Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
[Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
[Intel XE#2233]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2233
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
[Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
[Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
[Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
[Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2330
[Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
[Intel XE#2360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2360
[Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
[Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
[Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
[Intel XE#2907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2907
[Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#3012]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3012
[Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
[Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
[Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
[Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
[Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
[Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
[Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
[Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
[Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
[Intel XE#3862]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3862
[Intel XE#3876]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3876
[Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
[Intel XE#3970]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3970
[Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
[Intel XE#4273]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4273
[Intel XE#4298]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4298
[Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
[Intel XE#4416]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4416
[Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
[Intel XE#4504]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4504
[Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
[Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
[Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
[Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
[Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
[Intel XE#5166]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5166
[Intel XE#5208]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5208
[Intel XE#5299]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5299
[Intel XE#5354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5354
[Intel XE#5390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5390
[Intel XE#5408]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5408
[Intel XE#5626]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5626
[Intel XE#5893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5893
[Intel XE#6032]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6032
[Intel XE#6251]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6251
[Intel XE#6313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6313
[Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
[Intel XE#6363]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6363
[Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
[Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
[Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
[Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
Build changes
-------------
* Linux: xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d -> xe-pw-156865v2
IGT_8607: 8607
xe-4043-5fc5af47c48c461ff910c39f88694b966fcebc5d: 5fc5af47c48c461ff910c39f88694b966fcebc5d
xe-pw-156865v2: 156865v2
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156865v2/index.html
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