* [PATCH v2 1/2] drm/xe/sa: Shadow buffer support in the sub-allocator pool
2025-11-05 12:11 [PATCH v2 0/2] Improve CCS save/restore series (cont...) Satyanarayana K V P
@ 2025-11-05 12:11 ` Satyanarayana K V P
2025-11-17 18:25 ` Matthew Brost
2025-11-05 12:11 ` [PATCH v2 2/2] drm/xe/vf: Shadow buffer management for CCS read/write operations Satyanarayana K V P
2025-11-13 12:49 ` ✓ CI.KUnit: success for Improve CCS save/restore series (cont...) (rev3) Patchwork
2 siblings, 1 reply; 6+ messages in thread
From: Satyanarayana K V P @ 2025-11-05 12:11 UTC (permalink / raw)
To: intel-xe; +Cc: Satyanarayana K V P, Matthew Brost, Michal Wajdeczko,
Matthew Auld
The existing sub-allocator is limited to managing a single buffer object.
This enhancement introduces shadow buffer functionality to support
scenarios requiring dual buffer management.
The changes include added shadow buffer object creation capability,
Management for both primary and shadow buffers, and appropriate locking
mechanisms for thread-safe operations.
This enables more flexible buffer allocation strategies in scenarios where
shadow buffering is required.
Signed-off-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com>
Suggested-by: Matthew Brost <matthew.brost@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
---
V1 -> V2:
- Added kernel doc for xe_sa_bo_swap_shadow() and xe_sa_bo_sync_shadow()
functions (Matt B).
- Removed xe_sa_bo_swap_guard_lock() and xe_sa_bo_swap_guard_unlock() and
created xe_sa_bo_swap_guard() to which return mutex. (Michal W).
---
drivers/gpu/drm/xe/xe_guc_buf.c | 2 +-
drivers/gpu/drm/xe/xe_sa.c | 67 +++++++++++++++++++++++++++-
drivers/gpu/drm/xe/xe_sa.h | 20 ++++++++-
drivers/gpu/drm/xe/xe_sa_types.h | 3 ++
drivers/gpu/drm/xe/xe_sriov_vf_ccs.c | 3 ++
5 files changed, 91 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_guc_buf.c b/drivers/gpu/drm/xe/xe_guc_buf.c
index 3ce442500130..c36fc31e0438 100644
--- a/drivers/gpu/drm/xe/xe_guc_buf.c
+++ b/drivers/gpu/drm/xe/xe_guc_buf.c
@@ -30,7 +30,7 @@ static int guc_buf_cache_init(struct xe_guc_buf_cache *cache, u32 size)
struct xe_gt *gt = cache_to_gt(cache);
struct xe_sa_manager *sam;
- sam = __xe_sa_bo_manager_init(gt_to_tile(gt), size, 0, sizeof(u32));
+ sam = __xe_sa_bo_manager_init(gt_to_tile(gt), size, 0, sizeof(u32), 0);
if (IS_ERR(sam))
return PTR_ERR(sam);
cache->sam = sam;
diff --git a/drivers/gpu/drm/xe/xe_sa.c b/drivers/gpu/drm/xe/xe_sa.c
index 63a5263dcf1b..a87c1436c7c1 100644
--- a/drivers/gpu/drm/xe/xe_sa.c
+++ b/drivers/gpu/drm/xe/xe_sa.c
@@ -29,6 +29,7 @@ static void xe_sa_bo_manager_fini(struct drm_device *drm, void *arg)
kvfree(sa_manager->cpu_ptr);
sa_manager->bo = NULL;
+ sa_manager->shadow = NULL;
}
/**
@@ -37,12 +38,14 @@ static void xe_sa_bo_manager_fini(struct drm_device *drm, void *arg)
* @size: number of bytes to allocate
* @guard: number of bytes to exclude from suballocations
* @align: alignment for each suballocated chunk
+ * @flags: flags for suballocator
*
* Prepares the suballocation manager for suballocations.
*
* Return: a pointer to the &xe_sa_manager or an ERR_PTR on failure.
*/
-struct xe_sa_manager *__xe_sa_bo_manager_init(struct xe_tile *tile, u32 size, u32 guard, u32 align)
+struct xe_sa_manager *__xe_sa_bo_manager_init(struct xe_tile *tile, u32 size,
+ u32 guard, u32 align, u32 flags)
{
struct xe_device *xe = tile_to_xe(tile);
struct xe_sa_manager *sa_manager;
@@ -79,6 +82,26 @@ struct xe_sa_manager *__xe_sa_bo_manager_init(struct xe_tile *tile, u32 size, u3
memset(sa_manager->cpu_ptr, 0, bo->ttm.base.size);
}
+ if (flags & XE_SA_BO_MANAGER_FLAG_SHADOW) {
+ struct xe_bo *shadow;
+
+ ret = drmm_mutex_init(&xe->drm, &sa_manager->swap_guard);
+ if (ret)
+ return ERR_PTR(ret);
+
+ shadow = xe_managed_bo_create_pin_map(xe, tile, size,
+ XE_BO_FLAG_VRAM_IF_DGFX(tile) |
+ XE_BO_FLAG_GGTT |
+ XE_BO_FLAG_GGTT_INVALIDATE |
+ XE_BO_FLAG_PINNED_NORESTORE);
+ if (IS_ERR(shadow)) {
+ drm_err(&xe->drm, "Failed to prepare %uKiB BO for SA manager (%pe)\n",
+ size / SZ_1K, shadow);
+ return ERR_CAST(shadow);
+ }
+ sa_manager->shadow = shadow;
+ }
+
drm_suballoc_manager_init(&sa_manager->base, managed_size, align);
ret = drmm_add_action_or_reset(&xe->drm, xe_sa_bo_manager_fini,
sa_manager);
@@ -88,6 +111,48 @@ struct xe_sa_manager *__xe_sa_bo_manager_init(struct xe_tile *tile, u32 size, u3
return sa_manager;
}
+/**
+ * xe_sa_bo_swap_shadow() - Swap the SA BO with shadow BO.
+ * @sa_manager: the XE sub allocator manager
+ *
+ * Swaps the sub-allocator primary buffer object with shadow buffer object.
+ *
+ * Return: None.
+ */
+void xe_sa_bo_swap_shadow(struct xe_sa_manager *sa_manager)
+{
+ struct xe_device *xe = tile_to_xe(sa_manager->bo->tile);
+
+ xe_assert(xe, sa_manager->shadow);
+ lockdep_assert_held(&sa_manager->swap_guard);
+
+ swap(sa_manager->bo, sa_manager->shadow);
+ if (!sa_manager->bo->vmap.is_iomem)
+ sa_manager->cpu_ptr = sa_manager->bo->vmap.vaddr;
+}
+
+/**
+ * xe_sa_bo_sync_shadow() - Sync the SA Shadow BO with primary BO.
+ * @sa_bo: the sub-allocator buffer object.
+ *
+ * Synchronize sub-allocator shadow buffer object with primary buffer object.
+ *
+ * Return: None.
+ */
+void xe_sa_bo_sync_shadow(struct drm_suballoc *sa_bo)
+{
+ struct xe_sa_manager *sa_manager = to_xe_sa_manager(sa_bo->manager);
+ struct xe_device *xe = tile_to_xe(sa_manager->bo->tile);
+
+ xe_assert(xe, sa_manager->shadow);
+ lockdep_assert_held(&sa_manager->swap_guard);
+
+ xe_map_memcpy_to(xe, &sa_manager->shadow->vmap,
+ drm_suballoc_soffset(sa_bo),
+ xe_sa_bo_cpu_addr(sa_bo),
+ drm_suballoc_size(sa_bo));
+}
+
/**
* __xe_sa_bo_new() - Make a suballocation but use custom gfp flags.
* @sa_manager: the &xe_sa_manager
diff --git a/drivers/gpu/drm/xe/xe_sa.h b/drivers/gpu/drm/xe/xe_sa.h
index 1be744350836..05e9a4e00e78 100644
--- a/drivers/gpu/drm/xe/xe_sa.h
+++ b/drivers/gpu/drm/xe/xe_sa.h
@@ -14,12 +14,14 @@
struct dma_fence;
struct xe_tile;
-struct xe_sa_manager *__xe_sa_bo_manager_init(struct xe_tile *tile, u32 size, u32 guard, u32 align);
+#define XE_SA_BO_MANAGER_FLAG_SHADOW BIT(0)
+struct xe_sa_manager *__xe_sa_bo_manager_init(struct xe_tile *tile, u32 size,
+ u32 guard, u32 align, u32 flags);
struct drm_suballoc *__xe_sa_bo_new(struct xe_sa_manager *sa_manager, u32 size, gfp_t gfp);
static inline struct xe_sa_manager *xe_sa_bo_manager_init(struct xe_tile *tile, u32 size, u32 align)
{
- return __xe_sa_bo_manager_init(tile, size, SZ_4K, align);
+ return __xe_sa_bo_manager_init(tile, size, SZ_4K, align, 0);
}
/**
@@ -69,4 +71,18 @@ static inline void *xe_sa_bo_cpu_addr(struct drm_suballoc *sa)
drm_suballoc_soffset(sa);
}
+void xe_sa_bo_swap_shadow(struct xe_sa_manager *sa_manager);
+void xe_sa_bo_sync_shadow(struct drm_suballoc *sa_bo);
+
+/**
+ * xe_sa_bo_swap_guard() - Retrieve the SA BO swap guard within sub-allocator.
+ * @sa_manager: the &xe_sa_manager
+ *
+ * Return: Sub alloctor swap guard mutex.
+ */
+static inline struct mutex *xe_sa_bo_swap_guard(struct xe_sa_manager *sa_manager)
+{
+ return &sa_manager->swap_guard;
+}
+
#endif
diff --git a/drivers/gpu/drm/xe/xe_sa_types.h b/drivers/gpu/drm/xe/xe_sa_types.h
index cb7238799dcb..1085c9c37d6b 100644
--- a/drivers/gpu/drm/xe/xe_sa_types.h
+++ b/drivers/gpu/drm/xe/xe_sa_types.h
@@ -12,6 +12,9 @@ struct xe_bo;
struct xe_sa_manager {
struct drm_suballoc_manager base;
struct xe_bo *bo;
+ struct xe_bo *shadow;
+ /** @swap_guard: Timeline guard updating @bo and @shadow */
+ struct mutex swap_guard;
void *cpu_ptr;
bool is_iomem;
};
diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
index 797a4b866226..9959d619addc 100644
--- a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
+++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
@@ -162,9 +162,12 @@ static int alloc_bb_pool(struct xe_tile *tile, struct xe_sriov_vf_ccs_ctx *ctx)
offset = 0;
xe_map_memset(xe, &sa_manager->bo->vmap, offset, MI_NOOP,
bb_pool_size);
+ xe_map_memset(xe, &sa_manager->shadow->vmap, offset, MI_NOOP,
+ bb_pool_size);
offset = bb_pool_size - sizeof(u32);
xe_map_wr(xe, &sa_manager->bo->vmap, offset, u32, MI_BATCH_BUFFER_END);
+ xe_map_wr(xe, &sa_manager->shadow->vmap, offset, u32, MI_BATCH_BUFFER_END);
ctx->mem.ccs_bb_pool = sa_manager;
--
2.43.0
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH v2 1/2] drm/xe/sa: Shadow buffer support in the sub-allocator pool
2025-11-05 12:11 ` [PATCH v2 1/2] drm/xe/sa: Shadow buffer support in the sub-allocator pool Satyanarayana K V P
@ 2025-11-17 18:25 ` Matthew Brost
0 siblings, 0 replies; 6+ messages in thread
From: Matthew Brost @ 2025-11-17 18:25 UTC (permalink / raw)
To: Satyanarayana K V P; +Cc: intel-xe, Michal Wajdeczko, Matthew Auld
On Wed, Nov 05, 2025 at 12:11:50PM +0000, Satyanarayana K V P wrote:
> The existing sub-allocator is limited to managing a single buffer object.
> This enhancement introduces shadow buffer functionality to support
> scenarios requiring dual buffer management.
>
> The changes include added shadow buffer object creation capability,
> Management for both primary and shadow buffers, and appropriate locking
> mechanisms for thread-safe operations.
>
> This enables more flexible buffer allocation strategies in scenarios where
> shadow buffering is required.
>
> Signed-off-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com>
> Suggested-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Matthew Auld <matthew.auld@intel.com>
>
> ---
> V1 -> V2:
> - Added kernel doc for xe_sa_bo_swap_shadow() and xe_sa_bo_sync_shadow()
> functions (Matt B).
> - Removed xe_sa_bo_swap_guard_lock() and xe_sa_bo_swap_guard_unlock() and
> created xe_sa_bo_swap_guard() to which return mutex. (Michal W).
> ---
> drivers/gpu/drm/xe/xe_guc_buf.c | 2 +-
> drivers/gpu/drm/xe/xe_sa.c | 67 +++++++++++++++++++++++++++-
> drivers/gpu/drm/xe/xe_sa.h | 20 ++++++++-
> drivers/gpu/drm/xe/xe_sa_types.h | 3 ++
> drivers/gpu/drm/xe/xe_sriov_vf_ccs.c | 3 ++
> 5 files changed, 91 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_guc_buf.c b/drivers/gpu/drm/xe/xe_guc_buf.c
> index 3ce442500130..c36fc31e0438 100644
> --- a/drivers/gpu/drm/xe/xe_guc_buf.c
> +++ b/drivers/gpu/drm/xe/xe_guc_buf.c
> @@ -30,7 +30,7 @@ static int guc_buf_cache_init(struct xe_guc_buf_cache *cache, u32 size)
> struct xe_gt *gt = cache_to_gt(cache);
> struct xe_sa_manager *sam;
>
> - sam = __xe_sa_bo_manager_init(gt_to_tile(gt), size, 0, sizeof(u32));
> + sam = __xe_sa_bo_manager_init(gt_to_tile(gt), size, 0, sizeof(u32), 0);
> if (IS_ERR(sam))
> return PTR_ERR(sam);
> cache->sam = sam;
> diff --git a/drivers/gpu/drm/xe/xe_sa.c b/drivers/gpu/drm/xe/xe_sa.c
> index 63a5263dcf1b..a87c1436c7c1 100644
> --- a/drivers/gpu/drm/xe/xe_sa.c
> +++ b/drivers/gpu/drm/xe/xe_sa.c
> @@ -29,6 +29,7 @@ static void xe_sa_bo_manager_fini(struct drm_device *drm, void *arg)
> kvfree(sa_manager->cpu_ptr);
>
> sa_manager->bo = NULL;
> + sa_manager->shadow = NULL;
> }
>
> /**
> @@ -37,12 +38,14 @@ static void xe_sa_bo_manager_fini(struct drm_device *drm, void *arg)
> * @size: number of bytes to allocate
> * @guard: number of bytes to exclude from suballocations
> * @align: alignment for each suballocated chunk
> + * @flags: flags for suballocator
> *
> * Prepares the suballocation manager for suballocations.
> *
> * Return: a pointer to the &xe_sa_manager or an ERR_PTR on failure.
> */
> -struct xe_sa_manager *__xe_sa_bo_manager_init(struct xe_tile *tile, u32 size, u32 guard, u32 align)
> +struct xe_sa_manager *__xe_sa_bo_manager_init(struct xe_tile *tile, u32 size,
> + u32 guard, u32 align, u32 flags)
> {
> struct xe_device *xe = tile_to_xe(tile);
> struct xe_sa_manager *sa_manager;
> @@ -79,6 +82,26 @@ struct xe_sa_manager *__xe_sa_bo_manager_init(struct xe_tile *tile, u32 size, u3
> memset(sa_manager->cpu_ptr, 0, bo->ttm.base.size);
> }
>
> + if (flags & XE_SA_BO_MANAGER_FLAG_SHADOW) {
> + struct xe_bo *shadow;
> +
> + ret = drmm_mutex_init(&xe->drm, &sa_manager->swap_guard);
> + if (ret)
> + return ERR_PTR(ret);
> +
> + shadow = xe_managed_bo_create_pin_map(xe, tile, size,
> + XE_BO_FLAG_VRAM_IF_DGFX(tile) |
> + XE_BO_FLAG_GGTT |
> + XE_BO_FLAG_GGTT_INVALIDATE |
> + XE_BO_FLAG_PINNED_NORESTORE);
> + if (IS_ERR(shadow)) {
> + drm_err(&xe->drm, "Failed to prepare %uKiB BO for SA manager (%pe)\n",
> + size / SZ_1K, shadow);
> + return ERR_CAST(shadow);
> + }
> + sa_manager->shadow = shadow;
> + }
> +
> drm_suballoc_manager_init(&sa_manager->base, managed_size, align);
> ret = drmm_add_action_or_reset(&xe->drm, xe_sa_bo_manager_fini,
> sa_manager);
> @@ -88,6 +111,48 @@ struct xe_sa_manager *__xe_sa_bo_manager_init(struct xe_tile *tile, u32 size, u3
> return sa_manager;
> }
>
> +/**
> + * xe_sa_bo_swap_shadow() - Swap the SA BO with shadow BO.
> + * @sa_manager: the XE sub allocator manager
> + *
> + * Swaps the sub-allocator primary buffer object with shadow buffer object.
> + *
> + * Return: None.
> + */
> +void xe_sa_bo_swap_shadow(struct xe_sa_manager *sa_manager)
> +{
> + struct xe_device *xe = tile_to_xe(sa_manager->bo->tile);
> +
> + xe_assert(xe, sa_manager->shadow);
> + lockdep_assert_held(&sa_manager->swap_guard);
> +
> + swap(sa_manager->bo, sa_manager->shadow);
> + if (!sa_manager->bo->vmap.is_iomem)
> + sa_manager->cpu_ptr = sa_manager->bo->vmap.vaddr;
> +}
> +
> +/**
> + * xe_sa_bo_sync_shadow() - Sync the SA Shadow BO with primary BO.
> + * @sa_bo: the sub-allocator buffer object.
> + *
> + * Synchronize sub-allocator shadow buffer object with primary buffer object.
> + *
> + * Return: None.
> + */
> +void xe_sa_bo_sync_shadow(struct drm_suballoc *sa_bo)
> +{
> + struct xe_sa_manager *sa_manager = to_xe_sa_manager(sa_bo->manager);
> + struct xe_device *xe = tile_to_xe(sa_manager->bo->tile);
> +
> + xe_assert(xe, sa_manager->shadow);
> + lockdep_assert_held(&sa_manager->swap_guard);
> +
> + xe_map_memcpy_to(xe, &sa_manager->shadow->vmap,
> + drm_suballoc_soffset(sa_bo),
> + xe_sa_bo_cpu_addr(sa_bo),
> + drm_suballoc_size(sa_bo));
> +}
> +
> /**
> * __xe_sa_bo_new() - Make a suballocation but use custom gfp flags.
> * @sa_manager: the &xe_sa_manager
> diff --git a/drivers/gpu/drm/xe/xe_sa.h b/drivers/gpu/drm/xe/xe_sa.h
> index 1be744350836..05e9a4e00e78 100644
> --- a/drivers/gpu/drm/xe/xe_sa.h
> +++ b/drivers/gpu/drm/xe/xe_sa.h
> @@ -14,12 +14,14 @@
> struct dma_fence;
> struct xe_tile;
>
> -struct xe_sa_manager *__xe_sa_bo_manager_init(struct xe_tile *tile, u32 size, u32 guard, u32 align);
> +#define XE_SA_BO_MANAGER_FLAG_SHADOW BIT(0)
> +struct xe_sa_manager *__xe_sa_bo_manager_init(struct xe_tile *tile, u32 size,
> + u32 guard, u32 align, u32 flags);
> struct drm_suballoc *__xe_sa_bo_new(struct xe_sa_manager *sa_manager, u32 size, gfp_t gfp);
>
> static inline struct xe_sa_manager *xe_sa_bo_manager_init(struct xe_tile *tile, u32 size, u32 align)
> {
> - return __xe_sa_bo_manager_init(tile, size, SZ_4K, align);
> + return __xe_sa_bo_manager_init(tile, size, SZ_4K, align, 0);
> }
>
> /**
> @@ -69,4 +71,18 @@ static inline void *xe_sa_bo_cpu_addr(struct drm_suballoc *sa)
> drm_suballoc_soffset(sa);
> }
>
> +void xe_sa_bo_swap_shadow(struct xe_sa_manager *sa_manager);
> +void xe_sa_bo_sync_shadow(struct drm_suballoc *sa_bo);
> +
> +/**
> + * xe_sa_bo_swap_guard() - Retrieve the SA BO swap guard within sub-allocator.
> + * @sa_manager: the &xe_sa_manager
> + *
> + * Return: Sub alloctor swap guard mutex.
> + */
> +static inline struct mutex *xe_sa_bo_swap_guard(struct xe_sa_manager *sa_manager)
> +{
> + return &sa_manager->swap_guard;
> +}
> +
> #endif
> diff --git a/drivers/gpu/drm/xe/xe_sa_types.h b/drivers/gpu/drm/xe/xe_sa_types.h
> index cb7238799dcb..1085c9c37d6b 100644
> --- a/drivers/gpu/drm/xe/xe_sa_types.h
> +++ b/drivers/gpu/drm/xe/xe_sa_types.h
> @@ -12,6 +12,9 @@ struct xe_bo;
> struct xe_sa_manager {
> struct drm_suballoc_manager base;
> struct xe_bo *bo;
> + struct xe_bo *shadow;
> + /** @swap_guard: Timeline guard updating @bo and @shadow */
> + struct mutex swap_guard;
> void *cpu_ptr;
> bool is_iomem;
> };
> diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
> index 797a4b866226..9959d619addc 100644
> --- a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
> +++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
> @@ -162,9 +162,12 @@ static int alloc_bb_pool(struct xe_tile *tile, struct xe_sriov_vf_ccs_ctx *ctx)
> offset = 0;
> xe_map_memset(xe, &sa_manager->bo->vmap, offset, MI_NOOP,
> bb_pool_size);
> + xe_map_memset(xe, &sa_manager->shadow->vmap, offset, MI_NOOP,
> + bb_pool_size);
>
> offset = bb_pool_size - sizeof(u32);
> xe_map_wr(xe, &sa_manager->bo->vmap, offset, u32, MI_BATCH_BUFFER_END);
> + xe_map_wr(xe, &sa_manager->shadow->vmap, offset, u32, MI_BATCH_BUFFER_END);
>
> ctx->mem.ccs_bb_pool = sa_manager;
>
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 2/2] drm/xe/vf: Shadow buffer management for CCS read/write operations
2025-11-05 12:11 [PATCH v2 0/2] Improve CCS save/restore series (cont...) Satyanarayana K V P
2025-11-05 12:11 ` [PATCH v2 1/2] drm/xe/sa: Shadow buffer support in the sub-allocator pool Satyanarayana K V P
@ 2025-11-05 12:11 ` Satyanarayana K V P
2025-11-17 18:29 ` Matthew Brost
2025-11-13 12:49 ` ✓ CI.KUnit: success for Improve CCS save/restore series (cont...) (rev3) Patchwork
2 siblings, 1 reply; 6+ messages in thread
From: Satyanarayana K V P @ 2025-11-05 12:11 UTC (permalink / raw)
To: intel-xe; +Cc: Satyanarayana K V P, Matthew Brost, Michal Wajdeczko,
Matthew Auld
CCS copy command consist of 5-dword sequence. If vCPU halts during
save/restore operations while these sequences are being programmed,
incomplete writes can cause page faults during IGPU CCS metadata saving.
Use shadow buffer management to prevent partial write issues during CCS
operations.
Signed-off-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com>
Suggested-by: Matthew Brost <matthew.brost@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
---
V1 -> V2:
- Updated xe_sa_bo_swap_guard_lock() to use guard(mutex) class (Michal W).
- Moved xe_device_wmb() into xe_sriov_vf_ccs_rw_update_bb_addr() (Matt B).
---
drivers/gpu/drm/xe/xe_migrate.c | 54 ++++++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_migrate.h | 3 ++
drivers/gpu/drm/xe/xe_sriov_vf_ccs.c | 19 +++++++---
drivers/gpu/drm/xe/xe_sriov_vf_ccs.h | 1 +
4 files changed, 73 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
index dbe9320863ab..2106593fe48e 100644
--- a/drivers/gpu/drm/xe/xe_migrate.c
+++ b/drivers/gpu/drm/xe/xe_migrate.c
@@ -34,6 +34,7 @@
#include "xe_res_cursor.h"
#include "xe_sa.h"
#include "xe_sched_job.h"
+#include "xe_sriov_vf_ccs.h"
#include "xe_sync.h"
#include "xe_trace_bo.h"
#include "xe_validation.h"
@@ -1103,12 +1104,16 @@ int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct xe_exec_queue *q,
u32 batch_size, batch_size_allocated;
struct xe_device *xe = gt_to_xe(gt);
struct xe_res_cursor src_it, ccs_it;
+ struct xe_sriov_vf_ccs_ctx *ctx;
+ struct xe_sa_manager *bb_pool;
u64 size = xe_bo_size(src_bo);
struct xe_bb *bb = NULL;
u64 src_L0, src_L0_ofs;
u32 src_L0_pt;
int err;
+ ctx = &xe->sriov.vf.ccs.contexts[read_write];
+
xe_res_first_sg(xe_bo_sg(src_bo), 0, size, &src_it);
xe_res_first_sg(xe_bo_sg(src_bo), xe_bo_ccs_pages_start(src_bo),
@@ -1141,6 +1146,10 @@ int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct xe_exec_queue *q,
size -= src_L0;
}
+ bb_pool = ctx->mem.ccs_bb_pool;
+ guard(mutex) (xe_sa_bo_swap_guard(bb_pool));
+ xe_sa_bo_swap_shadow(bb_pool);
+
bb = xe_bb_ccs_new(gt, batch_size, read_write);
if (IS_ERR(bb)) {
drm_err(&xe->drm, "BB allocation failed.\n");
@@ -1194,12 +1203,57 @@ int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct xe_exec_queue *q,
xe_assert(xe, (batch_size_allocated == bb->len));
src_bo->bb_ccs[read_write] = bb;
+ xe_sriov_vf_ccs_rw_update_bb_addr(ctx);
+ xe_sa_bo_sync_shadow(bb->bo);
return 0;
err_ret:
return err;
}
+/**
+ * xe_migrate_ccs_rw_copy_clear() - Clear the CCS read/write batch buffer
+ * content.
+ * @src_bo: The buffer object @src is currently bound to.
+ * @read_write : Creates BB commands for CCS read/write.
+ *
+ * Directly clearing the BB lacks atomicity and can lead to undefined
+ * behavior if the vCPU is halted mid-operation during the clearing
+ * process. To avoid this issue, we use a shadow buffer object approach.
+ *
+ * First swap the SA BO address with the shadow BO, perform the clearing
+ * operation on the BB, update the shadow BO in the ring buffer, then
+ * sync the shadow and the actual buffer to maintain consistency.
+ *
+ * Returns: None.
+ */
+void xe_migrate_ccs_rw_copy_clear(struct xe_bo *src_bo,
+ enum xe_sriov_vf_ccs_rw_ctxs read_write)
+{
+ struct xe_bb *bb = src_bo->bb_ccs[read_write];
+ struct xe_device *xe = xe_bo_device(src_bo);
+ struct xe_sriov_vf_ccs_ctx *ctx;
+ struct xe_sa_manager *bb_pool;
+ u32 *cs;
+
+ xe_assert(xe, IS_SRIOV_VF(xe));
+
+ ctx = &xe->sriov.vf.ccs.contexts[read_write];
+ bb_pool = ctx->mem.ccs_bb_pool;
+
+ guard(mutex) (xe_sa_bo_swap_guard(bb_pool));
+ xe_sa_bo_swap_shadow(bb_pool);
+
+ cs = xe_sa_bo_cpu_addr(bb->bo);
+ memset(cs, MI_NOOP, bb->len * sizeof(u32));
+ xe_sriov_vf_ccs_rw_update_bb_addr(ctx);
+
+ xe_sa_bo_sync_shadow(bb->bo);
+
+ xe_bb_free(bb, NULL);
+ src_bo->bb_ccs[read_write] = NULL;
+}
+
/**
* xe_get_migrate_exec_queue() - Get the execution queue from migrate context.
* @migrate: Migrate context.
diff --git a/drivers/gpu/drm/xe/xe_migrate.h b/drivers/gpu/drm/xe/xe_migrate.h
index d7bcc6ad8464..db66b2ea31a5 100644
--- a/drivers/gpu/drm/xe/xe_migrate.h
+++ b/drivers/gpu/drm/xe/xe_migrate.h
@@ -134,6 +134,9 @@ int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct xe_exec_queue *q,
struct xe_bo *src_bo,
enum xe_sriov_vf_ccs_rw_ctxs read_write);
+void xe_migrate_ccs_rw_copy_clear(struct xe_bo *src_bo,
+ enum xe_sriov_vf_ccs_rw_ctxs read_write);
+
struct xe_lrc *xe_migrate_lrc(struct xe_migrate *migrate);
struct xe_exec_queue *xe_migrate_exec_queue(struct xe_migrate *migrate);
struct dma_fence *xe_migrate_vram_copy_chunk(struct xe_bo *vram_bo, u64 vram_offset,
diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
index 9959d619addc..33f4238604e1 100644
--- a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
+++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
@@ -150,7 +150,8 @@ static int alloc_bb_pool(struct xe_tile *tile, struct xe_sriov_vf_ccs_ctx *ctx)
xe_sriov_info(xe, "Allocating %s CCS BB pool size = %lldMB\n",
ctx->ctx_id ? "Restore" : "Save", bb_pool_size / SZ_1M);
- sa_manager = xe_sa_bo_manager_init(tile, bb_pool_size, SZ_16);
+ sa_manager = __xe_sa_bo_manager_init(tile, bb_pool_size, SZ_4K, SZ_16,
+ XE_SA_BO_MANAGER_FLAG_SHADOW);
if (IS_ERR(sa_manager)) {
xe_sriov_err(xe, "Suballocator init failed with error: %pe\n",
@@ -384,6 +385,18 @@ int xe_sriov_vf_ccs_init(struct xe_device *xe)
return err;
}
+#define XE_SRIOV_VF_CCS_RW_BB_ADDR_OFFSET (2 * sizeof(u32))
+void xe_sriov_vf_ccs_rw_update_bb_addr(struct xe_sriov_vf_ccs_ctx *ctx)
+{
+ u64 addr = xe_sa_manager_gpu_addr(ctx->mem.ccs_bb_pool);
+ struct xe_lrc *lrc = xe_exec_queue_lrc(ctx->mig_q);
+ struct xe_device *xe = gt_to_xe(ctx->mig_q->gt);
+
+ xe_device_wmb(xe);
+ xe_map_wr(xe, &lrc->bo->vmap, XE_SRIOV_VF_CCS_RW_BB_ADDR_OFFSET, u32, addr);
+ xe_device_wmb(xe);
+}
+
/**
* xe_sriov_vf_ccs_attach_bo - Insert CCS read write commands in the BO.
* @bo: the &buffer object to which batch buffer commands will be added.
@@ -444,9 +457,7 @@ int xe_sriov_vf_ccs_detach_bo(struct xe_bo *bo)
if (!bb)
continue;
- memset(bb->cs, MI_NOOP, bb->len * sizeof(u32));
- xe_bb_free(bb, NULL);
- bo->bb_ccs[ctx_id] = NULL;
+ xe_migrate_ccs_rw_copy_clear(bo, ctx_id);
}
return 0;
}
diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.h b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.h
index f8ca6efce9ee..00e58b36c510 100644
--- a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.h
+++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.h
@@ -20,6 +20,7 @@ int xe_sriov_vf_ccs_detach_bo(struct xe_bo *bo);
int xe_sriov_vf_ccs_register_context(struct xe_device *xe);
void xe_sriov_vf_ccs_rebase(struct xe_device *xe);
void xe_sriov_vf_ccs_print(struct xe_device *xe, struct drm_printer *p);
+void xe_sriov_vf_ccs_rw_update_bb_addr(struct xe_sriov_vf_ccs_ctx *ctx);
static inline bool xe_sriov_vf_ccs_ready(struct xe_device *xe)
{
--
2.43.0
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH v2 2/2] drm/xe/vf: Shadow buffer management for CCS read/write operations
2025-11-05 12:11 ` [PATCH v2 2/2] drm/xe/vf: Shadow buffer management for CCS read/write operations Satyanarayana K V P
@ 2025-11-17 18:29 ` Matthew Brost
0 siblings, 0 replies; 6+ messages in thread
From: Matthew Brost @ 2025-11-17 18:29 UTC (permalink / raw)
To: Satyanarayana K V P; +Cc: intel-xe, Michal Wajdeczko, Matthew Auld
On Wed, Nov 05, 2025 at 12:11:51PM +0000, Satyanarayana K V P wrote:
> CCS copy command consist of 5-dword sequence. If vCPU halts during
> save/restore operations while these sequences are being programmed,
> incomplete writes can cause page faults during IGPU CCS metadata saving.
>
> Use shadow buffer management to prevent partial write issues during CCS
> operations.
>
> Signed-off-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com>
> Suggested-by: Matthew Brost <matthew.brost@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Matthew Auld <matthew.auld@intel.com>
>
> ---
> V1 -> V2:
> - Updated xe_sa_bo_swap_guard_lock() to use guard(mutex) class (Michal W).
> - Moved xe_device_wmb() into xe_sriov_vf_ccs_rw_update_bb_addr() (Matt B).
> ---
> drivers/gpu/drm/xe/xe_migrate.c | 54 ++++++++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_migrate.h | 3 ++
> drivers/gpu/drm/xe/xe_sriov_vf_ccs.c | 19 +++++++---
> drivers/gpu/drm/xe/xe_sriov_vf_ccs.h | 1 +
> 4 files changed, 73 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
> index dbe9320863ab..2106593fe48e 100644
> --- a/drivers/gpu/drm/xe/xe_migrate.c
> +++ b/drivers/gpu/drm/xe/xe_migrate.c
> @@ -34,6 +34,7 @@
> #include "xe_res_cursor.h"
> #include "xe_sa.h"
> #include "xe_sched_job.h"
> +#include "xe_sriov_vf_ccs.h"
> #include "xe_sync.h"
> #include "xe_trace_bo.h"
> #include "xe_validation.h"
> @@ -1103,12 +1104,16 @@ int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct xe_exec_queue *q,
> u32 batch_size, batch_size_allocated;
> struct xe_device *xe = gt_to_xe(gt);
> struct xe_res_cursor src_it, ccs_it;
> + struct xe_sriov_vf_ccs_ctx *ctx;
> + struct xe_sa_manager *bb_pool;
> u64 size = xe_bo_size(src_bo);
> struct xe_bb *bb = NULL;
> u64 src_L0, src_L0_ofs;
> u32 src_L0_pt;
> int err;
>
> + ctx = &xe->sriov.vf.ccs.contexts[read_write];
> +
> xe_res_first_sg(xe_bo_sg(src_bo), 0, size, &src_it);
>
> xe_res_first_sg(xe_bo_sg(src_bo), xe_bo_ccs_pages_start(src_bo),
> @@ -1141,6 +1146,10 @@ int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct xe_exec_queue *q,
> size -= src_L0;
> }
>
> + bb_pool = ctx->mem.ccs_bb_pool;
> + guard(mutex) (xe_sa_bo_swap_guard(bb_pool));
> + xe_sa_bo_swap_shadow(bb_pool);
> +
> bb = xe_bb_ccs_new(gt, batch_size, read_write);
> if (IS_ERR(bb)) {
> drm_err(&xe->drm, "BB allocation failed.\n");
There is a goto just below here. We should drop the goto and just return
as the suggestion [1] is if guards are used, avoid using gotos.
Other than this nit, LGTM.
Matt
[1] https://elixir.bootlin.com/linux/v6.17.8/source/include/linux/cleanup.h#L148
> @@ -1194,12 +1203,57 @@ int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct xe_exec_queue *q,
> xe_assert(xe, (batch_size_allocated == bb->len));
> src_bo->bb_ccs[read_write] = bb;
>
> + xe_sriov_vf_ccs_rw_update_bb_addr(ctx);
> + xe_sa_bo_sync_shadow(bb->bo);
> return 0;
>
> err_ret:
> return err;
> }
>
> +/**
> + * xe_migrate_ccs_rw_copy_clear() - Clear the CCS read/write batch buffer
> + * content.
> + * @src_bo: The buffer object @src is currently bound to.
> + * @read_write : Creates BB commands for CCS read/write.
> + *
> + * Directly clearing the BB lacks atomicity and can lead to undefined
> + * behavior if the vCPU is halted mid-operation during the clearing
> + * process. To avoid this issue, we use a shadow buffer object approach.
> + *
> + * First swap the SA BO address with the shadow BO, perform the clearing
> + * operation on the BB, update the shadow BO in the ring buffer, then
> + * sync the shadow and the actual buffer to maintain consistency.
> + *
> + * Returns: None.
> + */
> +void xe_migrate_ccs_rw_copy_clear(struct xe_bo *src_bo,
> + enum xe_sriov_vf_ccs_rw_ctxs read_write)
> +{
> + struct xe_bb *bb = src_bo->bb_ccs[read_write];
> + struct xe_device *xe = xe_bo_device(src_bo);
> + struct xe_sriov_vf_ccs_ctx *ctx;
> + struct xe_sa_manager *bb_pool;
> + u32 *cs;
> +
> + xe_assert(xe, IS_SRIOV_VF(xe));
> +
> + ctx = &xe->sriov.vf.ccs.contexts[read_write];
> + bb_pool = ctx->mem.ccs_bb_pool;
> +
> + guard(mutex) (xe_sa_bo_swap_guard(bb_pool));
> + xe_sa_bo_swap_shadow(bb_pool);
> +
> + cs = xe_sa_bo_cpu_addr(bb->bo);
> + memset(cs, MI_NOOP, bb->len * sizeof(u32));
> + xe_sriov_vf_ccs_rw_update_bb_addr(ctx);
> +
> + xe_sa_bo_sync_shadow(bb->bo);
> +
> + xe_bb_free(bb, NULL);
> + src_bo->bb_ccs[read_write] = NULL;
> +}
> +
> /**
> * xe_get_migrate_exec_queue() - Get the execution queue from migrate context.
> * @migrate: Migrate context.
> diff --git a/drivers/gpu/drm/xe/xe_migrate.h b/drivers/gpu/drm/xe/xe_migrate.h
> index d7bcc6ad8464..db66b2ea31a5 100644
> --- a/drivers/gpu/drm/xe/xe_migrate.h
> +++ b/drivers/gpu/drm/xe/xe_migrate.h
> @@ -134,6 +134,9 @@ int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct xe_exec_queue *q,
> struct xe_bo *src_bo,
> enum xe_sriov_vf_ccs_rw_ctxs read_write);
>
> +void xe_migrate_ccs_rw_copy_clear(struct xe_bo *src_bo,
> + enum xe_sriov_vf_ccs_rw_ctxs read_write);
> +
> struct xe_lrc *xe_migrate_lrc(struct xe_migrate *migrate);
> struct xe_exec_queue *xe_migrate_exec_queue(struct xe_migrate *migrate);
> struct dma_fence *xe_migrate_vram_copy_chunk(struct xe_bo *vram_bo, u64 vram_offset,
> diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
> index 9959d619addc..33f4238604e1 100644
> --- a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
> +++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
> @@ -150,7 +150,8 @@ static int alloc_bb_pool(struct xe_tile *tile, struct xe_sriov_vf_ccs_ctx *ctx)
> xe_sriov_info(xe, "Allocating %s CCS BB pool size = %lldMB\n",
> ctx->ctx_id ? "Restore" : "Save", bb_pool_size / SZ_1M);
>
> - sa_manager = xe_sa_bo_manager_init(tile, bb_pool_size, SZ_16);
> + sa_manager = __xe_sa_bo_manager_init(tile, bb_pool_size, SZ_4K, SZ_16,
> + XE_SA_BO_MANAGER_FLAG_SHADOW);
>
> if (IS_ERR(sa_manager)) {
> xe_sriov_err(xe, "Suballocator init failed with error: %pe\n",
> @@ -384,6 +385,18 @@ int xe_sriov_vf_ccs_init(struct xe_device *xe)
> return err;
> }
>
> +#define XE_SRIOV_VF_CCS_RW_BB_ADDR_OFFSET (2 * sizeof(u32))
> +void xe_sriov_vf_ccs_rw_update_bb_addr(struct xe_sriov_vf_ccs_ctx *ctx)
> +{
> + u64 addr = xe_sa_manager_gpu_addr(ctx->mem.ccs_bb_pool);
> + struct xe_lrc *lrc = xe_exec_queue_lrc(ctx->mig_q);
> + struct xe_device *xe = gt_to_xe(ctx->mig_q->gt);
> +
> + xe_device_wmb(xe);
> + xe_map_wr(xe, &lrc->bo->vmap, XE_SRIOV_VF_CCS_RW_BB_ADDR_OFFSET, u32, addr);
> + xe_device_wmb(xe);
> +}
> +
> /**
> * xe_sriov_vf_ccs_attach_bo - Insert CCS read write commands in the BO.
> * @bo: the &buffer object to which batch buffer commands will be added.
> @@ -444,9 +457,7 @@ int xe_sriov_vf_ccs_detach_bo(struct xe_bo *bo)
> if (!bb)
> continue;
>
> - memset(bb->cs, MI_NOOP, bb->len * sizeof(u32));
> - xe_bb_free(bb, NULL);
> - bo->bb_ccs[ctx_id] = NULL;
> + xe_migrate_ccs_rw_copy_clear(bo, ctx_id);
> }
> return 0;
> }
> diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.h b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.h
> index f8ca6efce9ee..00e58b36c510 100644
> --- a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.h
> +++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.h
> @@ -20,6 +20,7 @@ int xe_sriov_vf_ccs_detach_bo(struct xe_bo *bo);
> int xe_sriov_vf_ccs_register_context(struct xe_device *xe);
> void xe_sriov_vf_ccs_rebase(struct xe_device *xe);
> void xe_sriov_vf_ccs_print(struct xe_device *xe, struct drm_printer *p);
> +void xe_sriov_vf_ccs_rw_update_bb_addr(struct xe_sriov_vf_ccs_ctx *ctx);
>
> static inline bool xe_sriov_vf_ccs_ready(struct xe_device *xe)
> {
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* ✓ CI.KUnit: success for Improve CCS save/restore series (cont...) (rev3)
2025-11-05 12:11 [PATCH v2 0/2] Improve CCS save/restore series (cont...) Satyanarayana K V P
2025-11-05 12:11 ` [PATCH v2 1/2] drm/xe/sa: Shadow buffer support in the sub-allocator pool Satyanarayana K V P
2025-11-05 12:11 ` [PATCH v2 2/2] drm/xe/vf: Shadow buffer management for CCS read/write operations Satyanarayana K V P
@ 2025-11-13 12:49 ` Patchwork
2 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2025-11-13 12:49 UTC (permalink / raw)
To: Satyanarayana K V P; +Cc: intel-xe
== Series Details ==
Series: Improve CCS save/restore series (cont...) (rev3)
URL : https://patchwork.freedesktop.org/series/156932/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[12:48:18] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[12:48:22] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[12:48:52] Starting KUnit Kernel (1/1)...
[12:48:52] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[12:48:52] ================== guc_buf (11 subtests) ===================
[12:48:52] [PASSED] test_smallest
[12:48:52] [PASSED] test_largest
[12:48:52] [PASSED] test_granular
[12:48:52] [PASSED] test_unique
[12:48:52] [PASSED] test_overlap
[12:48:52] [PASSED] test_reusable
[12:48:52] [PASSED] test_too_big
[12:48:52] [PASSED] test_flush
[12:48:52] [PASSED] test_lookup
[12:48:52] [PASSED] test_data
[12:48:52] [PASSED] test_class
[12:48:52] ===================== [PASSED] guc_buf =====================
[12:48:52] =================== guc_dbm (7 subtests) ===================
[12:48:52] [PASSED] test_empty
[12:48:52] [PASSED] test_default
[12:48:52] ======================== test_size ========================
[12:48:52] [PASSED] 4
[12:48:52] [PASSED] 8
[12:48:52] [PASSED] 32
[12:48:52] [PASSED] 256
[12:48:52] ==================== [PASSED] test_size ====================
[12:48:52] ======================= test_reuse ========================
[12:48:52] [PASSED] 4
[12:48:52] [PASSED] 8
[12:48:52] [PASSED] 32
[12:48:52] [PASSED] 256
[12:48:52] =================== [PASSED] test_reuse ====================
[12:48:52] =================== test_range_overlap ====================
[12:48:52] [PASSED] 4
[12:48:52] [PASSED] 8
[12:48:52] [PASSED] 32
[12:48:52] [PASSED] 256
[12:48:52] =============== [PASSED] test_range_overlap ================
[12:48:52] =================== test_range_compact ====================
[12:48:52] [PASSED] 4
[12:48:52] [PASSED] 8
[12:48:52] [PASSED] 32
[12:48:52] [PASSED] 256
[12:48:52] =============== [PASSED] test_range_compact ================
[12:48:52] ==================== test_range_spare =====================
[12:48:52] [PASSED] 4
[12:48:52] [PASSED] 8
[12:48:52] [PASSED] 32
[12:48:52] [PASSED] 256
[12:48:52] ================ [PASSED] test_range_spare =================
[12:48:52] ===================== [PASSED] guc_dbm =====================
[12:48:52] =================== guc_idm (6 subtests) ===================
[12:48:52] [PASSED] bad_init
[12:48:52] [PASSED] no_init
[12:48:52] [PASSED] init_fini
[12:48:52] [PASSED] check_used
[12:48:52] [PASSED] check_quota
[12:48:52] [PASSED] check_all
[12:48:52] ===================== [PASSED] guc_idm =====================
[12:48:52] ================== no_relay (3 subtests) ===================
[12:48:52] [PASSED] xe_drops_guc2pf_if_not_ready
[12:48:52] [PASSED] xe_drops_guc2vf_if_not_ready
[12:48:52] [PASSED] xe_rejects_send_if_not_ready
[12:48:52] ==================== [PASSED] no_relay =====================
[12:48:52] ================== pf_relay (14 subtests) ==================
[12:48:52] [PASSED] pf_rejects_guc2pf_too_short
[12:48:52] [PASSED] pf_rejects_guc2pf_too_long
[12:48:52] [PASSED] pf_rejects_guc2pf_no_payload
[12:48:52] [PASSED] pf_fails_no_payload
[12:48:52] [PASSED] pf_fails_bad_origin
[12:48:52] [PASSED] pf_fails_bad_type
[12:48:52] [PASSED] pf_txn_reports_error
[12:48:52] [PASSED] pf_txn_sends_pf2guc
[12:48:52] [PASSED] pf_sends_pf2guc
[12:48:52] [SKIPPED] pf_loopback_nop
[12:48:52] [SKIPPED] pf_loopback_echo
[12:48:52] [SKIPPED] pf_loopback_fail
[12:48:52] [SKIPPED] pf_loopback_busy
[12:48:52] [SKIPPED] pf_loopback_retry
[12:48:52] ==================== [PASSED] pf_relay =====================
[12:48:52] ================== vf_relay (3 subtests) ===================
[12:48:52] [PASSED] vf_rejects_guc2vf_too_short
[12:48:52] [PASSED] vf_rejects_guc2vf_too_long
[12:48:52] [PASSED] vf_rejects_guc2vf_no_payload
[12:48:52] ==================== [PASSED] vf_relay =====================
[12:48:52] ================ pf_gt_config (4 subtests) =================
[12:48:52] [PASSED] fair_contexts_1vf
[12:48:52] [PASSED] fair_doorbells_1vf
[12:48:52] ====================== fair_contexts ======================
[12:48:52] [PASSED] 1 VF
[12:48:52] [PASSED] 2 VFs
[12:48:52] [PASSED] 3 VFs
[12:48:52] [PASSED] 4 VFs
[12:48:52] [PASSED] 5 VFs
[12:48:52] [PASSED] 6 VFs
[12:48:52] [PASSED] 7 VFs
[12:48:52] [PASSED] 8 VFs
[12:48:52] [PASSED] 9 VFs
[12:48:52] [PASSED] 10 VFs
[12:48:52] [PASSED] 11 VFs
[12:48:52] [PASSED] 12 VFs
[12:48:52] [PASSED] 13 VFs
[12:48:52] [PASSED] 14 VFs
[12:48:52] [PASSED] 15 VFs
[12:48:52] [PASSED] 16 VFs
[12:48:52] [PASSED] 17 VFs
[12:48:52] [PASSED] 18 VFs
[12:48:52] [PASSED] 19 VFs
[12:48:52] [PASSED] 20 VFs
[12:48:52] [PASSED] 21 VFs
[12:48:52] [PASSED] 22 VFs
[12:48:52] [PASSED] 23 VFs
[12:48:52] [PASSED] 24 VFs
[12:48:52] [PASSED] 25 VFs
[12:48:52] [PASSED] 26 VFs
[12:48:52] [PASSED] 27 VFs
[12:48:52] [PASSED] 28 VFs
[12:48:52] [PASSED] 29 VFs
[12:48:52] [PASSED] 30 VFs
[12:48:52] [PASSED] 31 VFs
[12:48:52] [PASSED] 32 VFs
[12:48:52] [PASSED] 33 VFs
[12:48:52] [PASSED] 34 VFs
[12:48:52] [PASSED] 35 VFs
[12:48:52] [PASSED] 36 VFs
[12:48:52] [PASSED] 37 VFs
[12:48:52] [PASSED] 38 VFs
[12:48:52] [PASSED] 39 VFs
[12:48:52] [PASSED] 40 VFs
[12:48:52] [PASSED] 41 VFs
[12:48:52] [PASSED] 42 VFs
[12:48:52] [PASSED] 43 VFs
[12:48:52] [PASSED] 44 VFs
[12:48:52] [PASSED] 45 VFs
[12:48:52] [PASSED] 46 VFs
[12:48:52] [PASSED] 47 VFs
[12:48:52] [PASSED] 48 VFs
[12:48:52] [PASSED] 49 VFs
[12:48:52] [PASSED] 50 VFs
[12:48:52] [PASSED] 51 VFs
[12:48:52] [PASSED] 52 VFs
[12:48:52] [PASSED] 53 VFs
[12:48:52] [PASSED] 54 VFs
[12:48:52] [PASSED] 55 VFs
[12:48:52] [PASSED] 56 VFs
[12:48:52] [PASSED] 57 VFs
[12:48:52] [PASSED] 58 VFs
[12:48:52] [PASSED] 59 VFs
[12:48:52] [PASSED] 60 VFs
[12:48:52] [PASSED] 61 VFs
[12:48:52] [PASSED] 62 VFs
[12:48:52] [PASSED] 63 VFs
[12:48:52] ================== [PASSED] fair_contexts ==================
[12:48:52] ===================== fair_doorbells ======================
[12:48:52] [PASSED] 1 VF
[12:48:52] [PASSED] 2 VFs
[12:48:52] [PASSED] 3 VFs
[12:48:52] [PASSED] 4 VFs
[12:48:52] [PASSED] 5 VFs
[12:48:52] [PASSED] 6 VFs
[12:48:52] [PASSED] 7 VFs
[12:48:52] [PASSED] 8 VFs
[12:48:52] [PASSED] 9 VFs
[12:48:52] [PASSED] 10 VFs
[12:48:52] [PASSED] 11 VFs
[12:48:52] [PASSED] 12 VFs
[12:48:52] [PASSED] 13 VFs
[12:48:52] [PASSED] 14 VFs
[12:48:52] [PASSED] 15 VFs
[12:48:52] [PASSED] 16 VFs
[12:48:52] [PASSED] 17 VFs
[12:48:52] [PASSED] 18 VFs
[12:48:52] [PASSED] 19 VFs
[12:48:52] [PASSED] 20 VFs
[12:48:52] [PASSED] 21 VFs
[12:48:52] [PASSED] 22 VFs
[12:48:52] [PASSED] 23 VFs
[12:48:52] [PASSED] 24 VFs
[12:48:52] [PASSED] 25 VFs
[12:48:52] [PASSED] 26 VFs
[12:48:52] [PASSED] 27 VFs
[12:48:52] [PASSED] 28 VFs
[12:48:52] [PASSED] 29 VFs
[12:48:52] [PASSED] 30 VFs
[12:48:52] [PASSED] 31 VFs
[12:48:52] [PASSED] 32 VFs
[12:48:52] [PASSED] 33 VFs
[12:48:52] [PASSED] 34 VFs
[12:48:52] [PASSED] 35 VFs
[12:48:52] [PASSED] 36 VFs
[12:48:52] [PASSED] 37 VFs
[12:48:52] [PASSED] 38 VFs
[12:48:52] [PASSED] 39 VFs
[12:48:52] [PASSED] 40 VFs
[12:48:52] [PASSED] 41 VFs
[12:48:52] [PASSED] 42 VFs
[12:48:52] [PASSED] 43 VFs
[12:48:52] [PASSED] 44 VFs
[12:48:52] [PASSED] 45 VFs
[12:48:52] [PASSED] 46 VFs
[12:48:52] [PASSED] 47 VFs
[12:48:52] [PASSED] 48 VFs
[12:48:52] [PASSED] 49 VFs
[12:48:52] [PASSED] 50 VFs
[12:48:52] [PASSED] 51 VFs
[12:48:52] [PASSED] 52 VFs
[12:48:52] [PASSED] 53 VFs
[12:48:52] [PASSED] 54 VFs
[12:48:52] [PASSED] 55 VFs
[12:48:52] [PASSED] 56 VFs
[12:48:52] [PASSED] 57 VFs
[12:48:52] [PASSED] 58 VFs
[12:48:52] [PASSED] 59 VFs
[12:48:52] [PASSED] 60 VFs
[12:48:52] [PASSED] 61 VFs
[12:48:52] [PASSED] 62 VFs
[12:48:52] [PASSED] 63 VFs
[12:48:52] ================= [PASSED] fair_doorbells ==================
[12:48:52] ================== [PASSED] pf_gt_config ===================
[12:48:52] ===================== lmtt (1 subtest) =====================
[12:48:52] ======================== test_ops =========================
[12:48:52] [PASSED] 2-level
[12:48:52] [PASSED] multi-level
[12:48:52] ==================== [PASSED] test_ops =====================
[12:48:52] ====================== [PASSED] lmtt =======================
[12:48:52] ================= pf_service (11 subtests) =================
[12:48:52] [PASSED] pf_negotiate_any
[12:48:52] [PASSED] pf_negotiate_base_match
[12:48:52] [PASSED] pf_negotiate_base_newer
[12:48:52] [PASSED] pf_negotiate_base_next
[12:48:52] [SKIPPED] pf_negotiate_base_older
[12:48:52] [PASSED] pf_negotiate_base_prev
[12:48:52] [PASSED] pf_negotiate_latest_match
[12:48:53] [PASSED] pf_negotiate_latest_newer
[12:48:53] [PASSED] pf_negotiate_latest_next
[12:48:53] [SKIPPED] pf_negotiate_latest_older
[12:48:53] [SKIPPED] pf_negotiate_latest_prev
[12:48:53] =================== [PASSED] pf_service ====================
[12:48:53] ================= xe_guc_g2g (2 subtests) ==================
[12:48:53] ============== xe_live_guc_g2g_kunit_default ==============
[12:48:53] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[12:48:53] ============== xe_live_guc_g2g_kunit_allmem ===============
[12:48:53] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[12:48:53] =================== [SKIPPED] xe_guc_g2g ===================
[12:48:53] =================== xe_mocs (2 subtests) ===================
[12:48:53] ================ xe_live_mocs_kernel_kunit ================
[12:48:53] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[12:48:53] ================ xe_live_mocs_reset_kunit =================
[12:48:53] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[12:48:53] ==================== [SKIPPED] xe_mocs =====================
[12:48:53] ================= xe_migrate (2 subtests) ==================
[12:48:53] ================= xe_migrate_sanity_kunit =================
[12:48:53] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[12:48:53] ================== xe_validate_ccs_kunit ==================
[12:48:53] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[12:48:53] =================== [SKIPPED] xe_migrate ===================
[12:48:53] ================== xe_dma_buf (1 subtest) ==================
[12:48:53] ==================== xe_dma_buf_kunit =====================
[12:48:53] ================ [SKIPPED] xe_dma_buf_kunit ================
[12:48:53] =================== [SKIPPED] xe_dma_buf ===================
[12:48:53] ================= xe_bo_shrink (1 subtest) =================
[12:48:53] =================== xe_bo_shrink_kunit ====================
[12:48:53] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[12:48:53] ================== [SKIPPED] xe_bo_shrink ==================
[12:48:53] ==================== xe_bo (2 subtests) ====================
[12:48:53] ================== xe_ccs_migrate_kunit ===================
[12:48:53] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[12:48:53] ==================== xe_bo_evict_kunit ====================
[12:48:53] =============== [SKIPPED] xe_bo_evict_kunit ================
[12:48:53] ===================== [SKIPPED] xe_bo ======================
[12:48:53] ==================== args (11 subtests) ====================
[12:48:53] [PASSED] count_args_test
[12:48:53] [PASSED] call_args_example
[12:48:53] [PASSED] call_args_test
[12:48:53] [PASSED] drop_first_arg_example
[12:48:53] [PASSED] drop_first_arg_test
[12:48:53] [PASSED] first_arg_example
[12:48:53] [PASSED] first_arg_test
[12:48:53] [PASSED] last_arg_example
[12:48:53] [PASSED] last_arg_test
[12:48:53] [PASSED] pick_arg_example
[12:48:53] [PASSED] sep_comma_example
[12:48:53] ====================== [PASSED] args =======================
[12:48:53] =================== xe_pci (3 subtests) ====================
[12:48:53] ==================== check_graphics_ip ====================
[12:48:53] [PASSED] 12.00 Xe_LP
[12:48:53] [PASSED] 12.10 Xe_LP+
[12:48:53] [PASSED] 12.55 Xe_HPG
[12:48:53] [PASSED] 12.60 Xe_HPC
[12:48:53] [PASSED] 12.70 Xe_LPG
[12:48:53] [PASSED] 12.71 Xe_LPG
[12:48:53] [PASSED] 12.74 Xe_LPG+
[12:48:53] [PASSED] 20.01 Xe2_HPG
[12:48:53] [PASSED] 20.02 Xe2_HPG
[12:48:53] [PASSED] 20.04 Xe2_LPG
[12:48:53] [PASSED] 30.00 Xe3_LPG
[12:48:53] [PASSED] 30.01 Xe3_LPG
[12:48:53] [PASSED] 30.03 Xe3_LPG
[12:48:53] [PASSED] 30.04 Xe3_LPG
[12:48:53] [PASSED] 30.05 Xe3_LPG
[12:48:53] [PASSED] 35.11 Xe3p_XPC
[12:48:53] ================ [PASSED] check_graphics_ip ================
[12:48:53] ===================== check_media_ip ======================
[12:48:53] [PASSED] 12.00 Xe_M
[12:48:53] [PASSED] 12.55 Xe_HPM
[12:48:53] [PASSED] 13.00 Xe_LPM+
[12:48:53] [PASSED] 13.01 Xe2_HPM
[12:48:53] [PASSED] 20.00 Xe2_LPM
[12:48:53] [PASSED] 30.00 Xe3_LPM
[12:48:53] [PASSED] 30.02 Xe3_LPM
[12:48:53] [PASSED] 35.00 Xe3p_LPM
[12:48:53] [PASSED] 35.03 Xe3p_HPM
[12:48:53] ================= [PASSED] check_media_ip ==================
[12:48:53] =================== check_platform_desc ===================
[12:48:53] [PASSED] 0x9A60 (TIGERLAKE)
[12:48:53] [PASSED] 0x9A68 (TIGERLAKE)
[12:48:53] [PASSED] 0x9A70 (TIGERLAKE)
[12:48:53] [PASSED] 0x9A40 (TIGERLAKE)
[12:48:53] [PASSED] 0x9A49 (TIGERLAKE)
[12:48:53] [PASSED] 0x9A59 (TIGERLAKE)
[12:48:53] [PASSED] 0x9A78 (TIGERLAKE)
[12:48:53] [PASSED] 0x9AC0 (TIGERLAKE)
[12:48:53] [PASSED] 0x9AC9 (TIGERLAKE)
[12:48:53] [PASSED] 0x9AD9 (TIGERLAKE)
[12:48:53] [PASSED] 0x9AF8 (TIGERLAKE)
[12:48:53] [PASSED] 0x4C80 (ROCKETLAKE)
[12:48:53] [PASSED] 0x4C8A (ROCKETLAKE)
[12:48:53] [PASSED] 0x4C8B (ROCKETLAKE)
[12:48:53] [PASSED] 0x4C8C (ROCKETLAKE)
[12:48:53] [PASSED] 0x4C90 (ROCKETLAKE)
[12:48:53] [PASSED] 0x4C9A (ROCKETLAKE)
[12:48:53] [PASSED] 0x4680 (ALDERLAKE_S)
[12:48:53] [PASSED] 0x4682 (ALDERLAKE_S)
[12:48:53] [PASSED] 0x4688 (ALDERLAKE_S)
[12:48:53] [PASSED] 0x468A (ALDERLAKE_S)
[12:48:53] [PASSED] 0x468B (ALDERLAKE_S)
[12:48:53] [PASSED] 0x4690 (ALDERLAKE_S)
[12:48:53] [PASSED] 0x4692 (ALDERLAKE_S)
[12:48:53] [PASSED] 0x4693 (ALDERLAKE_S)
[12:48:53] [PASSED] 0x46A0 (ALDERLAKE_P)
[12:48:53] [PASSED] 0x46A1 (ALDERLAKE_P)
[12:48:53] [PASSED] 0x46A2 (ALDERLAKE_P)
[12:48:53] [PASSED] 0x46A3 (ALDERLAKE_P)
[12:48:53] [PASSED] 0x46A6 (ALDERLAKE_P)
[12:48:53] [PASSED] 0x46A8 (ALDERLAKE_P)
[12:48:53] [PASSED] 0x46AA (ALDERLAKE_P)
[12:48:53] [PASSED] 0x462A (ALDERLAKE_P)
[12:48:53] [PASSED] 0x4626 (ALDERLAKE_P)
[12:48:53] [PASSED] 0x4628 (ALDERLAKE_P)
[12:48:53] [PASSED] 0x46B0 (ALDERLAKE_P)
[12:48:53] [PASSED] 0x46B1 (ALDERLAKE_P)
[12:48:53] [PASSED] 0x46B2 (ALDERLAKE_P)
[12:48:53] [PASSED] 0x46B3 (ALDERLAKE_P)
[12:48:53] [PASSED] 0x46C0 (ALDERLAKE_P)
[12:48:53] [PASSED] 0x46C1 (ALDERLAKE_P)
[12:48:53] [PASSED] 0x46C2 (ALDERLAKE_P)
[12:48:53] [PASSED] 0x46C3 (ALDERLAKE_P)
[12:48:53] [PASSED] 0x46D0 (ALDERLAKE_N)
[12:48:53] [PASSED] 0x46D1 (ALDERLAKE_N)
[12:48:53] [PASSED] 0x46D2 (ALDERLAKE_N)
[12:48:53] [PASSED] 0x46D3 (ALDERLAKE_N)
[12:48:53] [PASSED] 0x46D4 (ALDERLAKE_N)
[12:48:53] [PASSED] 0xA721 (ALDERLAKE_P)
[12:48:53] [PASSED] 0xA7A1 (ALDERLAKE_P)
[12:48:53] [PASSED] 0xA7A9 (ALDERLAKE_P)
[12:48:53] [PASSED] 0xA7AC (ALDERLAKE_P)
[12:48:53] [PASSED] 0xA7AD (ALDERLAKE_P)
[12:48:53] [PASSED] 0xA720 (ALDERLAKE_P)
[12:48:53] [PASSED] 0xA7A0 (ALDERLAKE_P)
[12:48:53] [PASSED] 0xA7A8 (ALDERLAKE_P)
[12:48:53] [PASSED] 0xA7AA (ALDERLAKE_P)
[12:48:53] [PASSED] 0xA7AB (ALDERLAKE_P)
[12:48:53] [PASSED] 0xA780 (ALDERLAKE_S)
[12:48:53] [PASSED] 0xA781 (ALDERLAKE_S)
[12:48:53] [PASSED] 0xA782 (ALDERLAKE_S)
[12:48:53] [PASSED] 0xA783 (ALDERLAKE_S)
[12:48:53] [PASSED] 0xA788 (ALDERLAKE_S)
[12:48:53] [PASSED] 0xA789 (ALDERLAKE_S)
[12:48:53] [PASSED] 0xA78A (ALDERLAKE_S)
[12:48:53] [PASSED] 0xA78B (ALDERLAKE_S)
[12:48:53] [PASSED] 0x4905 (DG1)
[12:48:53] [PASSED] 0x4906 (DG1)
[12:48:53] [PASSED] 0x4907 (DG1)
[12:48:53] [PASSED] 0x4908 (DG1)
[12:48:53] [PASSED] 0x4909 (DG1)
[12:48:53] [PASSED] 0x56C0 (DG2)
[12:48:53] [PASSED] 0x56C2 (DG2)
[12:48:53] [PASSED] 0x56C1 (DG2)
[12:48:53] [PASSED] 0x7D51 (METEORLAKE)
[12:48:53] [PASSED] 0x7DD1 (METEORLAKE)
[12:48:53] [PASSED] 0x7D41 (METEORLAKE)
[12:48:53] [PASSED] 0x7D67 (METEORLAKE)
[12:48:53] [PASSED] 0xB640 (METEORLAKE)
[12:48:53] [PASSED] 0x56A0 (DG2)
[12:48:53] [PASSED] 0x56A1 (DG2)
[12:48:53] [PASSED] 0x56A2 (DG2)
[12:48:53] [PASSED] 0x56BE (DG2)
[12:48:53] [PASSED] 0x56BF (DG2)
[12:48:53] [PASSED] 0x5690 (DG2)
stty: 'standard input': Inappropriate ioctl for device
[12:48:53] [PASSED] 0x5691 (DG2)
[12:48:53] [PASSED] 0x5692 (DG2)
[12:48:53] [PASSED] 0x56A5 (DG2)
[12:48:53] [PASSED] 0x56A6 (DG2)
[12:48:53] [PASSED] 0x56B0 (DG2)
[12:48:53] [PASSED] 0x56B1 (DG2)
[12:48:53] [PASSED] 0x56BA (DG2)
[12:48:53] [PASSED] 0x56BB (DG2)
[12:48:53] [PASSED] 0x56BC (DG2)
[12:48:53] [PASSED] 0x56BD (DG2)
[12:48:53] [PASSED] 0x5693 (DG2)
[12:48:53] [PASSED] 0x5694 (DG2)
[12:48:53] [PASSED] 0x5695 (DG2)
[12:48:53] [PASSED] 0x56A3 (DG2)
[12:48:53] [PASSED] 0x56A4 (DG2)
[12:48:53] [PASSED] 0x56B2 (DG2)
[12:48:53] [PASSED] 0x56B3 (DG2)
[12:48:53] [PASSED] 0x5696 (DG2)
[12:48:53] [PASSED] 0x5697 (DG2)
[12:48:53] [PASSED] 0xB69 (PVC)
[12:48:53] [PASSED] 0xB6E (PVC)
[12:48:53] [PASSED] 0xBD4 (PVC)
[12:48:53] [PASSED] 0xBD5 (PVC)
[12:48:53] [PASSED] 0xBD6 (PVC)
[12:48:53] [PASSED] 0xBD7 (PVC)
[12:48:53] [PASSED] 0xBD8 (PVC)
[12:48:53] [PASSED] 0xBD9 (PVC)
[12:48:53] [PASSED] 0xBDA (PVC)
[12:48:53] [PASSED] 0xBDB (PVC)
[12:48:53] [PASSED] 0xBE0 (PVC)
[12:48:53] [PASSED] 0xBE1 (PVC)
[12:48:53] [PASSED] 0xBE5 (PVC)
[12:48:53] [PASSED] 0x7D40 (METEORLAKE)
[12:48:53] [PASSED] 0x7D45 (METEORLAKE)
[12:48:53] [PASSED] 0x7D55 (METEORLAKE)
[12:48:53] [PASSED] 0x7D60 (METEORLAKE)
[12:48:53] [PASSED] 0x7DD5 (METEORLAKE)
[12:48:53] [PASSED] 0x6420 (LUNARLAKE)
[12:48:53] [PASSED] 0x64A0 (LUNARLAKE)
[12:48:53] [PASSED] 0x64B0 (LUNARLAKE)
[12:48:53] [PASSED] 0xE202 (BATTLEMAGE)
[12:48:53] [PASSED] 0xE209 (BATTLEMAGE)
[12:48:53] [PASSED] 0xE20B (BATTLEMAGE)
[12:48:53] [PASSED] 0xE20C (BATTLEMAGE)
[12:48:53] [PASSED] 0xE20D (BATTLEMAGE)
[12:48:53] [PASSED] 0xE210 (BATTLEMAGE)
[12:48:53] [PASSED] 0xE211 (BATTLEMAGE)
[12:48:53] [PASSED] 0xE212 (BATTLEMAGE)
[12:48:53] [PASSED] 0xE216 (BATTLEMAGE)
[12:48:53] [PASSED] 0xE220 (BATTLEMAGE)
[12:48:53] [PASSED] 0xE221 (BATTLEMAGE)
[12:48:53] [PASSED] 0xE222 (BATTLEMAGE)
[12:48:53] [PASSED] 0xE223 (BATTLEMAGE)
[12:48:53] [PASSED] 0xB080 (PANTHERLAKE)
[12:48:53] [PASSED] 0xB081 (PANTHERLAKE)
[12:48:53] [PASSED] 0xB082 (PANTHERLAKE)
[12:48:53] [PASSED] 0xB083 (PANTHERLAKE)
[12:48:53] [PASSED] 0xB084 (PANTHERLAKE)
[12:48:53] [PASSED] 0xB085 (PANTHERLAKE)
[12:48:53] [PASSED] 0xB086 (PANTHERLAKE)
[12:48:53] [PASSED] 0xB087 (PANTHERLAKE)
[12:48:53] [PASSED] 0xB08F (PANTHERLAKE)
[12:48:53] [PASSED] 0xB090 (PANTHERLAKE)
[12:48:53] [PASSED] 0xB0A0 (PANTHERLAKE)
[12:48:53] [PASSED] 0xB0B0 (PANTHERLAKE)
[12:48:53] [PASSED] 0xD740 (NOVALAKE_S)
[12:48:53] [PASSED] 0xD741 (NOVALAKE_S)
[12:48:53] [PASSED] 0xD742 (NOVALAKE_S)
[12:48:53] [PASSED] 0xD743 (NOVALAKE_S)
[12:48:53] [PASSED] 0xD744 (NOVALAKE_S)
[12:48:53] [PASSED] 0xD745 (NOVALAKE_S)
[12:48:53] [PASSED] 0x674C (CRESCENTISLAND)
[12:48:53] [PASSED] 0xFD80 (PANTHERLAKE)
[12:48:53] [PASSED] 0xFD81 (PANTHERLAKE)
[12:48:53] =============== [PASSED] check_platform_desc ===============
[12:48:53] ===================== [PASSED] xe_pci ======================
[12:48:53] =================== xe_rtp (2 subtests) ====================
[12:48:53] =============== xe_rtp_process_to_sr_tests ================
[12:48:53] [PASSED] coalesce-same-reg
[12:48:53] [PASSED] no-match-no-add
[12:48:53] [PASSED] match-or
[12:48:53] [PASSED] match-or-xfail
[12:48:53] [PASSED] no-match-no-add-multiple-rules
[12:48:53] [PASSED] two-regs-two-entries
[12:48:53] [PASSED] clr-one-set-other
[12:48:53] [PASSED] set-field
[12:48:53] [PASSED] conflict-duplicate
[12:48:53] [PASSED] conflict-not-disjoint
[12:48:53] [PASSED] conflict-reg-type
[12:48:53] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[12:48:53] ================== xe_rtp_process_tests ===================
[12:48:53] [PASSED] active1
[12:48:53] [PASSED] active2
[12:48:53] [PASSED] active-inactive
[12:48:53] [PASSED] inactive-active
[12:48:53] [PASSED] inactive-1st_or_active-inactive
[12:48:53] [PASSED] inactive-2nd_or_active-inactive
[12:48:53] [PASSED] inactive-last_or_active-inactive
[12:48:53] [PASSED] inactive-no_or_active-inactive
[12:48:53] ============== [PASSED] xe_rtp_process_tests ===============
[12:48:53] ===================== [PASSED] xe_rtp ======================
[12:48:53] ==================== xe_wa (1 subtest) =====================
[12:48:53] ======================== xe_wa_gt =========================
[12:48:53] [PASSED] TIGERLAKE B0
[12:48:53] [PASSED] DG1 A0
[12:48:53] [PASSED] DG1 B0
[12:48:53] [PASSED] ALDERLAKE_S A0
[12:48:53] [PASSED] ALDERLAKE_S B0
[12:48:53] [PASSED] ALDERLAKE_S C0
[12:48:53] [PASSED] ALDERLAKE_S D0
[12:48:53] [PASSED] ALDERLAKE_P A0
[12:48:53] [PASSED] ALDERLAKE_P B0
[12:48:53] [PASSED] ALDERLAKE_P C0
[12:48:53] [PASSED] ALDERLAKE_S RPLS D0
[12:48:53] [PASSED] ALDERLAKE_P RPLU E0
[12:48:53] [PASSED] DG2 G10 C0
[12:48:53] [PASSED] DG2 G11 B1
[12:48:53] [PASSED] DG2 G12 A1
[12:48:53] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[12:48:53] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[12:48:53] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[12:48:53] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[12:48:53] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[12:48:53] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[12:48:53] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[12:48:53] ==================== [PASSED] xe_wa_gt =====================
[12:48:53] ====================== [PASSED] xe_wa ======================
[12:48:53] ============================================================
[12:48:53] Testing complete. Ran 446 tests: passed: 428, skipped: 18
[12:48:53] Elapsed time: 35.019s total, 4.194s configuring, 30.358s building, 0.421s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[12:48:53] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[12:48:54] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[12:49:19] Starting KUnit Kernel (1/1)...
[12:49:19] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[12:49:19] ============ drm_test_pick_cmdline (2 subtests) ============
[12:49:19] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[12:49:19] =============== drm_test_pick_cmdline_named ===============
[12:49:19] [PASSED] NTSC
[12:49:19] [PASSED] NTSC-J
[12:49:19] [PASSED] PAL
[12:49:19] [PASSED] PAL-M
[12:49:19] =========== [PASSED] drm_test_pick_cmdline_named ===========
[12:49:19] ============== [PASSED] drm_test_pick_cmdline ==============
[12:49:19] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[12:49:19] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[12:49:19] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[12:49:19] =========== drm_validate_clone_mode (2 subtests) ===========
[12:49:19] ============== drm_test_check_in_clone_mode ===============
[12:49:19] [PASSED] in_clone_mode
[12:49:19] [PASSED] not_in_clone_mode
[12:49:19] ========== [PASSED] drm_test_check_in_clone_mode ===========
[12:49:19] =============== drm_test_check_valid_clones ===============
[12:49:19] [PASSED] not_in_clone_mode
[12:49:19] [PASSED] valid_clone
[12:49:19] [PASSED] invalid_clone
[12:49:19] =========== [PASSED] drm_test_check_valid_clones ===========
[12:49:19] ============= [PASSED] drm_validate_clone_mode =============
[12:49:19] ============= drm_validate_modeset (1 subtest) =============
[12:49:19] [PASSED] drm_test_check_connector_changed_modeset
[12:49:19] ============== [PASSED] drm_validate_modeset ===============
[12:49:19] ====== drm_test_bridge_get_current_state (2 subtests) ======
[12:49:19] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[12:49:19] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[12:49:19] ======== [PASSED] drm_test_bridge_get_current_state ========
[12:49:19] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[12:49:19] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[12:49:19] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[12:49:19] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[12:49:19] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[12:49:19] ============== drm_bridge_alloc (2 subtests) ===============
[12:49:19] [PASSED] drm_test_drm_bridge_alloc_basic
[12:49:19] [PASSED] drm_test_drm_bridge_alloc_get_put
[12:49:19] ================ [PASSED] drm_bridge_alloc =================
[12:49:19] ================== drm_buddy (8 subtests) ==================
[12:49:19] [PASSED] drm_test_buddy_alloc_limit
[12:49:19] [PASSED] drm_test_buddy_alloc_optimistic
[12:49:19] [PASSED] drm_test_buddy_alloc_pessimistic
[12:49:19] [PASSED] drm_test_buddy_alloc_pathological
[12:49:19] [PASSED] drm_test_buddy_alloc_contiguous
[12:49:19] [PASSED] drm_test_buddy_alloc_clear
[12:49:19] [PASSED] drm_test_buddy_alloc_range_bias
[12:49:20] [PASSED] drm_test_buddy_fragmentation_performance
[12:49:20] ==================== [PASSED] drm_buddy ====================
[12:49:20] ============= drm_cmdline_parser (40 subtests) =============
[12:49:20] [PASSED] drm_test_cmdline_force_d_only
[12:49:20] [PASSED] drm_test_cmdline_force_D_only_dvi
[12:49:20] [PASSED] drm_test_cmdline_force_D_only_hdmi
[12:49:20] [PASSED] drm_test_cmdline_force_D_only_not_digital
[12:49:20] [PASSED] drm_test_cmdline_force_e_only
[12:49:20] [PASSED] drm_test_cmdline_res
[12:49:20] [PASSED] drm_test_cmdline_res_vesa
[12:49:20] [PASSED] drm_test_cmdline_res_vesa_rblank
[12:49:20] [PASSED] drm_test_cmdline_res_rblank
[12:49:20] [PASSED] drm_test_cmdline_res_bpp
[12:49:20] [PASSED] drm_test_cmdline_res_refresh
[12:49:20] [PASSED] drm_test_cmdline_res_bpp_refresh
[12:49:20] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[12:49:20] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[12:49:20] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[12:49:20] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[12:49:20] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[12:49:20] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[12:49:20] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[12:49:20] [PASSED] drm_test_cmdline_res_margins_force_on
[12:49:20] [PASSED] drm_test_cmdline_res_vesa_margins
[12:49:20] [PASSED] drm_test_cmdline_name
[12:49:20] [PASSED] drm_test_cmdline_name_bpp
[12:49:20] [PASSED] drm_test_cmdline_name_option
[12:49:20] [PASSED] drm_test_cmdline_name_bpp_option
[12:49:20] [PASSED] drm_test_cmdline_rotate_0
[12:49:20] [PASSED] drm_test_cmdline_rotate_90
[12:49:20] [PASSED] drm_test_cmdline_rotate_180
[12:49:20] [PASSED] drm_test_cmdline_rotate_270
[12:49:20] [PASSED] drm_test_cmdline_hmirror
[12:49:20] [PASSED] drm_test_cmdline_vmirror
[12:49:20] [PASSED] drm_test_cmdline_margin_options
[12:49:20] [PASSED] drm_test_cmdline_multiple_options
[12:49:20] [PASSED] drm_test_cmdline_bpp_extra_and_option
[12:49:20] [PASSED] drm_test_cmdline_extra_and_option
[12:49:20] [PASSED] drm_test_cmdline_freestanding_options
[12:49:20] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[12:49:20] [PASSED] drm_test_cmdline_panel_orientation
[12:49:20] ================ drm_test_cmdline_invalid =================
[12:49:20] [PASSED] margin_only
[12:49:20] [PASSED] interlace_only
[12:49:20] [PASSED] res_missing_x
[12:49:20] [PASSED] res_missing_y
[12:49:20] [PASSED] res_bad_y
[12:49:20] [PASSED] res_missing_y_bpp
[12:49:20] [PASSED] res_bad_bpp
[12:49:20] [PASSED] res_bad_refresh
[12:49:20] [PASSED] res_bpp_refresh_force_on_off
[12:49:20] [PASSED] res_invalid_mode
[12:49:20] [PASSED] res_bpp_wrong_place_mode
[12:49:20] [PASSED] name_bpp_refresh
[12:49:20] [PASSED] name_refresh
[12:49:20] [PASSED] name_refresh_wrong_mode
[12:49:20] [PASSED] name_refresh_invalid_mode
[12:49:20] [PASSED] rotate_multiple
[12:49:20] [PASSED] rotate_invalid_val
[12:49:20] [PASSED] rotate_truncated
[12:49:20] [PASSED] invalid_option
[12:49:20] [PASSED] invalid_tv_option
[12:49:20] [PASSED] truncated_tv_option
[12:49:20] ============ [PASSED] drm_test_cmdline_invalid =============
[12:49:20] =============== drm_test_cmdline_tv_options ===============
[12:49:20] [PASSED] NTSC
[12:49:20] [PASSED] NTSC_443
[12:49:20] [PASSED] NTSC_J
[12:49:20] [PASSED] PAL
[12:49:20] [PASSED] PAL_M
[12:49:20] [PASSED] PAL_N
[12:49:20] [PASSED] SECAM
[12:49:20] [PASSED] MONO_525
[12:49:20] [PASSED] MONO_625
[12:49:20] =========== [PASSED] drm_test_cmdline_tv_options ===========
[12:49:20] =============== [PASSED] drm_cmdline_parser ================
[12:49:20] ========== drmm_connector_hdmi_init (20 subtests) ==========
[12:49:20] [PASSED] drm_test_connector_hdmi_init_valid
[12:49:20] [PASSED] drm_test_connector_hdmi_init_bpc_8
[12:49:20] [PASSED] drm_test_connector_hdmi_init_bpc_10
[12:49:20] [PASSED] drm_test_connector_hdmi_init_bpc_12
[12:49:20] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[12:49:20] [PASSED] drm_test_connector_hdmi_init_bpc_null
[12:49:20] [PASSED] drm_test_connector_hdmi_init_formats_empty
[12:49:20] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[12:49:20] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[12:49:20] [PASSED] supported_formats=0x9 yuv420_allowed=1
[12:49:20] [PASSED] supported_formats=0x9 yuv420_allowed=0
[12:49:20] [PASSED] supported_formats=0x3 yuv420_allowed=1
[12:49:20] [PASSED] supported_formats=0x3 yuv420_allowed=0
[12:49:20] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[12:49:20] [PASSED] drm_test_connector_hdmi_init_null_ddc
[12:49:20] [PASSED] drm_test_connector_hdmi_init_null_product
[12:49:20] [PASSED] drm_test_connector_hdmi_init_null_vendor
[12:49:20] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[12:49:20] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[12:49:20] [PASSED] drm_test_connector_hdmi_init_product_valid
[12:49:20] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[12:49:20] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[12:49:20] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[12:49:20] ========= drm_test_connector_hdmi_init_type_valid =========
[12:49:20] [PASSED] HDMI-A
[12:49:20] [PASSED] HDMI-B
[12:49:20] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[12:49:20] ======== drm_test_connector_hdmi_init_type_invalid ========
[12:49:20] [PASSED] Unknown
[12:49:20] [PASSED] VGA
[12:49:20] [PASSED] DVI-I
[12:49:20] [PASSED] DVI-D
[12:49:20] [PASSED] DVI-A
[12:49:20] [PASSED] Composite
[12:49:20] [PASSED] SVIDEO
[12:49:20] [PASSED] LVDS
[12:49:20] [PASSED] Component
[12:49:20] [PASSED] DIN
[12:49:20] [PASSED] DP
[12:49:20] [PASSED] TV
[12:49:20] [PASSED] eDP
[12:49:20] [PASSED] Virtual
[12:49:20] [PASSED] DSI
[12:49:20] [PASSED] DPI
[12:49:20] [PASSED] Writeback
[12:49:20] [PASSED] SPI
[12:49:20] [PASSED] USB
[12:49:20] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[12:49:20] ============ [PASSED] drmm_connector_hdmi_init =============
[12:49:20] ============= drmm_connector_init (3 subtests) =============
[12:49:20] [PASSED] drm_test_drmm_connector_init
[12:49:20] [PASSED] drm_test_drmm_connector_init_null_ddc
[12:49:20] ========= drm_test_drmm_connector_init_type_valid =========
[12:49:20] [PASSED] Unknown
[12:49:20] [PASSED] VGA
[12:49:20] [PASSED] DVI-I
[12:49:20] [PASSED] DVI-D
[12:49:20] [PASSED] DVI-A
[12:49:20] [PASSED] Composite
[12:49:20] [PASSED] SVIDEO
[12:49:20] [PASSED] LVDS
[12:49:20] [PASSED] Component
[12:49:20] [PASSED] DIN
[12:49:20] [PASSED] DP
[12:49:20] [PASSED] HDMI-A
[12:49:20] [PASSED] HDMI-B
[12:49:20] [PASSED] TV
[12:49:20] [PASSED] eDP
[12:49:20] [PASSED] Virtual
[12:49:20] [PASSED] DSI
[12:49:20] [PASSED] DPI
[12:49:20] [PASSED] Writeback
[12:49:20] [PASSED] SPI
[12:49:20] [PASSED] USB
[12:49:20] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[12:49:20] =============== [PASSED] drmm_connector_init ===============
[12:49:20] ========= drm_connector_dynamic_init (6 subtests) ==========
[12:49:20] [PASSED] drm_test_drm_connector_dynamic_init
[12:49:20] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[12:49:20] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[12:49:20] [PASSED] drm_test_drm_connector_dynamic_init_properties
[12:49:20] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[12:49:20] [PASSED] Unknown
[12:49:20] [PASSED] VGA
[12:49:20] [PASSED] DVI-I
[12:49:20] [PASSED] DVI-D
[12:49:20] [PASSED] DVI-A
[12:49:20] [PASSED] Composite
[12:49:20] [PASSED] SVIDEO
[12:49:20] [PASSED] LVDS
[12:49:20] [PASSED] Component
[12:49:20] [PASSED] DIN
[12:49:20] [PASSED] DP
[12:49:20] [PASSED] HDMI-A
[12:49:20] [PASSED] HDMI-B
[12:49:20] [PASSED] TV
[12:49:20] [PASSED] eDP
[12:49:20] [PASSED] Virtual
[12:49:20] [PASSED] DSI
[12:49:20] [PASSED] DPI
[12:49:20] [PASSED] Writeback
[12:49:20] [PASSED] SPI
[12:49:20] [PASSED] USB
[12:49:20] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[12:49:20] ======== drm_test_drm_connector_dynamic_init_name =========
[12:49:20] [PASSED] Unknown
[12:49:20] [PASSED] VGA
[12:49:20] [PASSED] DVI-I
[12:49:20] [PASSED] DVI-D
[12:49:20] [PASSED] DVI-A
[12:49:20] [PASSED] Composite
[12:49:20] [PASSED] SVIDEO
[12:49:20] [PASSED] LVDS
[12:49:20] [PASSED] Component
[12:49:20] [PASSED] DIN
[12:49:20] [PASSED] DP
[12:49:20] [PASSED] HDMI-A
[12:49:20] [PASSED] HDMI-B
[12:49:20] [PASSED] TV
[12:49:20] [PASSED] eDP
[12:49:20] [PASSED] Virtual
[12:49:20] [PASSED] DSI
[12:49:20] [PASSED] DPI
[12:49:20] [PASSED] Writeback
[12:49:20] [PASSED] SPI
[12:49:20] [PASSED] USB
[12:49:20] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[12:49:20] =========== [PASSED] drm_connector_dynamic_init ============
[12:49:20] ==== drm_connector_dynamic_register_early (4 subtests) =====
[12:49:20] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[12:49:20] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[12:49:20] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[12:49:20] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[12:49:20] ====== [PASSED] drm_connector_dynamic_register_early =======
[12:49:20] ======= drm_connector_dynamic_register (7 subtests) ========
[12:49:20] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[12:49:20] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[12:49:20] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[12:49:20] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[12:49:20] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[12:49:20] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[12:49:20] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[12:49:20] ========= [PASSED] drm_connector_dynamic_register ==========
[12:49:20] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[12:49:20] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[12:49:20] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[12:49:20] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[12:49:20] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[12:49:20] ========== drm_test_get_tv_mode_from_name_valid ===========
[12:49:20] [PASSED] NTSC
[12:49:20] [PASSED] NTSC-443
[12:49:20] [PASSED] NTSC-J
[12:49:20] [PASSED] PAL
[12:49:20] [PASSED] PAL-M
[12:49:20] [PASSED] PAL-N
[12:49:20] [PASSED] SECAM
[12:49:20] [PASSED] Mono
[12:49:20] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[12:49:20] [PASSED] drm_test_get_tv_mode_from_name_truncated
[12:49:20] ============ [PASSED] drm_get_tv_mode_from_name ============
[12:49:20] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[12:49:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[12:49:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[12:49:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[12:49:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[12:49:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[12:49:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[12:49:20] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[12:49:20] [PASSED] VIC 96
[12:49:20] [PASSED] VIC 97
[12:49:20] [PASSED] VIC 101
[12:49:20] [PASSED] VIC 102
[12:49:20] [PASSED] VIC 106
[12:49:20] [PASSED] VIC 107
[12:49:20] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[12:49:20] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[12:49:20] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[12:49:20] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[12:49:20] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[12:49:20] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[12:49:20] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[12:49:20] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[12:49:20] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[12:49:20] [PASSED] Automatic
[12:49:20] [PASSED] Full
[12:49:20] [PASSED] Limited 16:235
[12:49:20] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[12:49:20] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[12:49:20] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[12:49:20] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[12:49:20] === drm_test_drm_hdmi_connector_get_output_format_name ====
[12:49:20] [PASSED] RGB
[12:49:20] [PASSED] YUV 4:2:0
[12:49:20] [PASSED] YUV 4:2:2
[12:49:20] [PASSED] YUV 4:4:4
[12:49:20] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[12:49:20] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[12:49:20] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[12:49:20] ============= drm_damage_helper (21 subtests) ==============
[12:49:20] [PASSED] drm_test_damage_iter_no_damage
[12:49:20] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[12:49:20] [PASSED] drm_test_damage_iter_no_damage_src_moved
[12:49:20] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[12:49:20] [PASSED] drm_test_damage_iter_no_damage_not_visible
[12:49:20] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[12:49:20] [PASSED] drm_test_damage_iter_no_damage_no_fb
[12:49:20] [PASSED] drm_test_damage_iter_simple_damage
[12:49:20] [PASSED] drm_test_damage_iter_single_damage
[12:49:20] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[12:49:20] [PASSED] drm_test_damage_iter_single_damage_outside_src
[12:49:20] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[12:49:20] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[12:49:20] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[12:49:20] [PASSED] drm_test_damage_iter_single_damage_src_moved
[12:49:20] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[12:49:20] [PASSED] drm_test_damage_iter_damage
[12:49:20] [PASSED] drm_test_damage_iter_damage_one_intersect
[12:49:20] [PASSED] drm_test_damage_iter_damage_one_outside
[12:49:20] [PASSED] drm_test_damage_iter_damage_src_moved
[12:49:20] [PASSED] drm_test_damage_iter_damage_not_visible
[12:49:20] ================ [PASSED] drm_damage_helper ================
[12:49:20] ============== drm_dp_mst_helper (3 subtests) ==============
[12:49:20] ============== drm_test_dp_mst_calc_pbn_mode ==============
[12:49:20] [PASSED] Clock 154000 BPP 30 DSC disabled
[12:49:20] [PASSED] Clock 234000 BPP 30 DSC disabled
[12:49:20] [PASSED] Clock 297000 BPP 24 DSC disabled
[12:49:20] [PASSED] Clock 332880 BPP 24 DSC enabled
[12:49:20] [PASSED] Clock 324540 BPP 24 DSC enabled
[12:49:20] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[12:49:20] ============== drm_test_dp_mst_calc_pbn_div ===============
[12:49:20] [PASSED] Link rate 2000000 lane count 4
[12:49:20] [PASSED] Link rate 2000000 lane count 2
[12:49:20] [PASSED] Link rate 2000000 lane count 1
[12:49:20] [PASSED] Link rate 1350000 lane count 4
[12:49:20] [PASSED] Link rate 1350000 lane count 2
[12:49:20] [PASSED] Link rate 1350000 lane count 1
[12:49:20] [PASSED] Link rate 1000000 lane count 4
[12:49:20] [PASSED] Link rate 1000000 lane count 2
[12:49:20] [PASSED] Link rate 1000000 lane count 1
[12:49:20] [PASSED] Link rate 810000 lane count 4
[12:49:20] [PASSED] Link rate 810000 lane count 2
[12:49:20] [PASSED] Link rate 810000 lane count 1
[12:49:20] [PASSED] Link rate 540000 lane count 4
[12:49:20] [PASSED] Link rate 540000 lane count 2
[12:49:20] [PASSED] Link rate 540000 lane count 1
[12:49:20] [PASSED] Link rate 270000 lane count 4
[12:49:20] [PASSED] Link rate 270000 lane count 2
[12:49:20] [PASSED] Link rate 270000 lane count 1
[12:49:20] [PASSED] Link rate 162000 lane count 4
[12:49:20] [PASSED] Link rate 162000 lane count 2
[12:49:20] [PASSED] Link rate 162000 lane count 1
[12:49:20] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[12:49:20] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[12:49:20] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[12:49:20] [PASSED] DP_POWER_UP_PHY with port number
[12:49:20] [PASSED] DP_POWER_DOWN_PHY with port number
[12:49:20] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[12:49:20] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[12:49:20] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[12:49:20] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[12:49:20] [PASSED] DP_QUERY_PAYLOAD with port number
[12:49:20] [PASSED] DP_QUERY_PAYLOAD with VCPI
[12:49:20] [PASSED] DP_REMOTE_DPCD_READ with port number
[12:49:20] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[12:49:20] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[12:49:20] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[12:49:20] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[12:49:20] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[12:49:20] [PASSED] DP_REMOTE_I2C_READ with port number
[12:49:20] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[12:49:20] [PASSED] DP_REMOTE_I2C_READ with transactions array
[12:49:20] [PASSED] DP_REMOTE_I2C_WRITE with port number
[12:49:20] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[12:49:20] [PASSED] DP_REMOTE_I2C_WRITE with data array
[12:49:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[12:49:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[12:49:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[12:49:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[12:49:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[12:49:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[12:49:20] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[12:49:20] ================ [PASSED] drm_dp_mst_helper ================
[12:49:20] ================== drm_exec (7 subtests) ===================
[12:49:20] [PASSED] sanitycheck
[12:49:20] [PASSED] test_lock
[12:49:20] [PASSED] test_lock_unlock
[12:49:20] [PASSED] test_duplicates
[12:49:20] [PASSED] test_prepare
[12:49:20] [PASSED] test_prepare_array
[12:49:20] [PASSED] test_multiple_loops
[12:49:20] ==================== [PASSED] drm_exec =====================
[12:49:20] =========== drm_format_helper_test (17 subtests) ===========
[12:49:20] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[12:49:20] [PASSED] single_pixel_source_buffer
[12:49:20] [PASSED] single_pixel_clip_rectangle
[12:49:20] [PASSED] well_known_colors
[12:49:20] [PASSED] destination_pitch
[12:49:20] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[12:49:20] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[12:49:20] [PASSED] single_pixel_source_buffer
[12:49:20] [PASSED] single_pixel_clip_rectangle
[12:49:20] [PASSED] well_known_colors
[12:49:20] [PASSED] destination_pitch
[12:49:20] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[12:49:20] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[12:49:20] [PASSED] single_pixel_source_buffer
[12:49:20] [PASSED] single_pixel_clip_rectangle
[12:49:20] [PASSED] well_known_colors
[12:49:20] [PASSED] destination_pitch
[12:49:20] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[12:49:20] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[12:49:20] [PASSED] single_pixel_source_buffer
[12:49:20] [PASSED] single_pixel_clip_rectangle
[12:49:20] [PASSED] well_known_colors
[12:49:20] [PASSED] destination_pitch
[12:49:20] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[12:49:20] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[12:49:20] [PASSED] single_pixel_source_buffer
[12:49:20] [PASSED] single_pixel_clip_rectangle
[12:49:20] [PASSED] well_known_colors
[12:49:20] [PASSED] destination_pitch
[12:49:20] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[12:49:20] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[12:49:20] [PASSED] single_pixel_source_buffer
[12:49:20] [PASSED] single_pixel_clip_rectangle
[12:49:20] [PASSED] well_known_colors
[12:49:20] [PASSED] destination_pitch
[12:49:20] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[12:49:20] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[12:49:20] [PASSED] single_pixel_source_buffer
[12:49:20] [PASSED] single_pixel_clip_rectangle
[12:49:20] [PASSED] well_known_colors
[12:49:20] [PASSED] destination_pitch
[12:49:20] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[12:49:20] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[12:49:20] [PASSED] single_pixel_source_buffer
[12:49:20] [PASSED] single_pixel_clip_rectangle
[12:49:20] [PASSED] well_known_colors
[12:49:20] [PASSED] destination_pitch
[12:49:20] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[12:49:20] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[12:49:20] [PASSED] single_pixel_source_buffer
[12:49:20] [PASSED] single_pixel_clip_rectangle
[12:49:20] [PASSED] well_known_colors
[12:49:20] [PASSED] destination_pitch
[12:49:20] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[12:49:20] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[12:49:20] [PASSED] single_pixel_source_buffer
[12:49:20] [PASSED] single_pixel_clip_rectangle
[12:49:20] [PASSED] well_known_colors
[12:49:20] [PASSED] destination_pitch
[12:49:20] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[12:49:20] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[12:49:20] [PASSED] single_pixel_source_buffer
[12:49:20] [PASSED] single_pixel_clip_rectangle
[12:49:20] [PASSED] well_known_colors
[12:49:20] [PASSED] destination_pitch
[12:49:20] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[12:49:20] ============== drm_test_fb_xrgb8888_to_mono ===============
[12:49:20] [PASSED] single_pixel_source_buffer
[12:49:20] [PASSED] single_pixel_clip_rectangle
[12:49:20] [PASSED] well_known_colors
[12:49:20] [PASSED] destination_pitch
[12:49:20] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[12:49:20] ==================== drm_test_fb_swab =====================
[12:49:20] [PASSED] single_pixel_source_buffer
[12:49:20] [PASSED] single_pixel_clip_rectangle
[12:49:20] [PASSED] well_known_colors
[12:49:20] [PASSED] destination_pitch
[12:49:20] ================ [PASSED] drm_test_fb_swab =================
[12:49:20] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[12:49:20] [PASSED] single_pixel_source_buffer
[12:49:20] [PASSED] single_pixel_clip_rectangle
[12:49:20] [PASSED] well_known_colors
[12:49:20] [PASSED] destination_pitch
[12:49:20] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[12:49:20] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[12:49:20] [PASSED] single_pixel_source_buffer
[12:49:20] [PASSED] single_pixel_clip_rectangle
[12:49:20] [PASSED] well_known_colors
[12:49:20] [PASSED] destination_pitch
[12:49:20] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[12:49:20] ================= drm_test_fb_clip_offset =================
[12:49:20] [PASSED] pass through
[12:49:20] [PASSED] horizontal offset
[12:49:20] [PASSED] vertical offset
[12:49:20] [PASSED] horizontal and vertical offset
[12:49:20] [PASSED] horizontal offset (custom pitch)
[12:49:20] [PASSED] vertical offset (custom pitch)
[12:49:20] [PASSED] horizontal and vertical offset (custom pitch)
[12:49:20] ============= [PASSED] drm_test_fb_clip_offset =============
[12:49:20] =================== drm_test_fb_memcpy ====================
[12:49:20] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[12:49:20] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[12:49:20] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[12:49:20] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[12:49:20] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[12:49:20] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[12:49:20] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[12:49:20] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[12:49:20] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[12:49:20] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[12:49:20] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[12:49:20] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[12:49:20] =============== [PASSED] drm_test_fb_memcpy ================
[12:49:20] ============= [PASSED] drm_format_helper_test ==============
[12:49:20] ================= drm_format (18 subtests) =================
[12:49:20] [PASSED] drm_test_format_block_width_invalid
[12:49:20] [PASSED] drm_test_format_block_width_one_plane
[12:49:20] [PASSED] drm_test_format_block_width_two_plane
[12:49:20] [PASSED] drm_test_format_block_width_three_plane
[12:49:20] [PASSED] drm_test_format_block_width_tiled
[12:49:20] [PASSED] drm_test_format_block_height_invalid
[12:49:20] [PASSED] drm_test_format_block_height_one_plane
[12:49:20] [PASSED] drm_test_format_block_height_two_plane
[12:49:20] [PASSED] drm_test_format_block_height_three_plane
[12:49:20] [PASSED] drm_test_format_block_height_tiled
[12:49:20] [PASSED] drm_test_format_min_pitch_invalid
[12:49:20] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[12:49:20] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[12:49:20] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[12:49:20] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[12:49:20] [PASSED] drm_test_format_min_pitch_two_plane
[12:49:20] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[12:49:20] [PASSED] drm_test_format_min_pitch_tiled
[12:49:20] =================== [PASSED] drm_format ====================
[12:49:20] ============== drm_framebuffer (10 subtests) ===============
[12:49:20] ========== drm_test_framebuffer_check_src_coords ==========
[12:49:20] [PASSED] Success: source fits into fb
[12:49:20] [PASSED] Fail: overflowing fb with x-axis coordinate
[12:49:20] [PASSED] Fail: overflowing fb with y-axis coordinate
[12:49:20] [PASSED] Fail: overflowing fb with source width
[12:49:20] [PASSED] Fail: overflowing fb with source height
[12:49:20] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[12:49:20] [PASSED] drm_test_framebuffer_cleanup
[12:49:20] =============== drm_test_framebuffer_create ===============
[12:49:20] [PASSED] ABGR8888 normal sizes
[12:49:20] [PASSED] ABGR8888 max sizes
[12:49:20] [PASSED] ABGR8888 pitch greater than min required
[12:49:20] [PASSED] ABGR8888 pitch less than min required
[12:49:20] [PASSED] ABGR8888 Invalid width
[12:49:20] [PASSED] ABGR8888 Invalid buffer handle
[12:49:20] [PASSED] No pixel format
[12:49:20] [PASSED] ABGR8888 Width 0
[12:49:20] [PASSED] ABGR8888 Height 0
[12:49:20] [PASSED] ABGR8888 Out of bound height * pitch combination
[12:49:20] [PASSED] ABGR8888 Large buffer offset
[12:49:20] [PASSED] ABGR8888 Buffer offset for inexistent plane
[12:49:20] [PASSED] ABGR8888 Invalid flag
[12:49:20] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[12:49:20] [PASSED] ABGR8888 Valid buffer modifier
[12:49:20] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[12:49:20] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[12:49:20] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[12:49:20] [PASSED] NV12 Normal sizes
[12:49:20] [PASSED] NV12 Max sizes
[12:49:20] [PASSED] NV12 Invalid pitch
[12:49:20] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[12:49:20] [PASSED] NV12 different modifier per-plane
[12:49:20] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[12:49:20] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[12:49:20] [PASSED] NV12 Modifier for inexistent plane
[12:49:20] [PASSED] NV12 Handle for inexistent plane
[12:49:20] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[12:49:20] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[12:49:20] [PASSED] YVU420 Normal sizes
[12:49:20] [PASSED] YVU420 Max sizes
[12:49:20] [PASSED] YVU420 Invalid pitch
[12:49:20] [PASSED] YVU420 Different pitches
[12:49:20] [PASSED] YVU420 Different buffer offsets/pitches
[12:49:20] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[12:49:20] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[12:49:20] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[12:49:20] [PASSED] YVU420 Valid modifier
[12:49:20] [PASSED] YVU420 Different modifiers per plane
[12:49:20] [PASSED] YVU420 Modifier for inexistent plane
[12:49:20] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[12:49:20] [PASSED] X0L2 Normal sizes
[12:49:20] [PASSED] X0L2 Max sizes
[12:49:20] [PASSED] X0L2 Invalid pitch
[12:49:20] [PASSED] X0L2 Pitch greater than minimum required
[12:49:20] [PASSED] X0L2 Handle for inexistent plane
[12:49:20] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[12:49:20] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[12:49:20] [PASSED] X0L2 Valid modifier
[12:49:20] [PASSED] X0L2 Modifier for inexistent plane
[12:49:20] =========== [PASSED] drm_test_framebuffer_create ===========
[12:49:20] [PASSED] drm_test_framebuffer_free
[12:49:20] [PASSED] drm_test_framebuffer_init
[12:49:20] [PASSED] drm_test_framebuffer_init_bad_format
[12:49:20] [PASSED] drm_test_framebuffer_init_dev_mismatch
[12:49:20] [PASSED] drm_test_framebuffer_lookup
[12:49:20] [PASSED] drm_test_framebuffer_lookup_inexistent
[12:49:20] [PASSED] drm_test_framebuffer_modifiers_not_supported
[12:49:20] ================= [PASSED] drm_framebuffer =================
[12:49:20] ================ drm_gem_shmem (8 subtests) ================
[12:49:20] [PASSED] drm_gem_shmem_test_obj_create
[12:49:20] [PASSED] drm_gem_shmem_test_obj_create_private
[12:49:20] [PASSED] drm_gem_shmem_test_pin_pages
[12:49:20] [PASSED] drm_gem_shmem_test_vmap
[12:49:20] [PASSED] drm_gem_shmem_test_get_pages_sgt
[12:49:20] [PASSED] drm_gem_shmem_test_get_sg_table
[12:49:20] [PASSED] drm_gem_shmem_test_madvise
[12:49:20] [PASSED] drm_gem_shmem_test_purge
[12:49:20] ================== [PASSED] drm_gem_shmem ==================
[12:49:20] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[12:49:20] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[12:49:20] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[12:49:20] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[12:49:20] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[12:49:20] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[12:49:20] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[12:49:20] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[12:49:20] [PASSED] Automatic
[12:49:20] [PASSED] Full
[12:49:20] [PASSED] Limited 16:235
[12:49:20] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[12:49:20] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[12:49:20] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[12:49:20] [PASSED] drm_test_check_disable_connector
[12:49:20] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[12:49:20] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[12:49:20] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[12:49:20] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[12:49:20] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[12:49:20] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[12:49:20] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[12:49:20] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[12:49:20] [PASSED] drm_test_check_output_bpc_dvi
[12:49:20] [PASSED] drm_test_check_output_bpc_format_vic_1
[12:49:20] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[12:49:20] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[12:49:20] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[12:49:20] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[12:49:20] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[12:49:20] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[12:49:20] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[12:49:20] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[12:49:20] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[12:49:20] [PASSED] drm_test_check_broadcast_rgb_value
[12:49:20] [PASSED] drm_test_check_bpc_8_value
[12:49:20] [PASSED] drm_test_check_bpc_10_value
[12:49:20] [PASSED] drm_test_check_bpc_12_value
[12:49:20] [PASSED] drm_test_check_format_value
[12:49:20] [PASSED] drm_test_check_tmds_char_value
[12:49:20] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[12:49:20] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[12:49:20] [PASSED] drm_test_check_mode_valid
[12:49:20] [PASSED] drm_test_check_mode_valid_reject
[12:49:20] [PASSED] drm_test_check_mode_valid_reject_rate
[12:49:20] [PASSED] drm_test_check_mode_valid_reject_max_clock
[12:49:20] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[12:49:20] ================= drm_managed (2 subtests) =================
[12:49:20] [PASSED] drm_test_managed_release_action
[12:49:20] [PASSED] drm_test_managed_run_action
[12:49:20] =================== [PASSED] drm_managed ===================
[12:49:20] =================== drm_mm (6 subtests) ====================
[12:49:20] [PASSED] drm_test_mm_init
[12:49:20] [PASSED] drm_test_mm_debug
[12:49:20] [PASSED] drm_test_mm_align32
[12:49:20] [PASSED] drm_test_mm_align64
[12:49:20] [PASSED] drm_test_mm_lowest
[12:49:20] [PASSED] drm_test_mm_highest
[12:49:20] ===================== [PASSED] drm_mm ======================
[12:49:20] ============= drm_modes_analog_tv (5 subtests) =============
[12:49:20] [PASSED] drm_test_modes_analog_tv_mono_576i
[12:49:20] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[12:49:20] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[12:49:20] [PASSED] drm_test_modes_analog_tv_pal_576i
[12:49:20] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[12:49:20] =============== [PASSED] drm_modes_analog_tv ===============
[12:49:20] ============== drm_plane_helper (2 subtests) ===============
[12:49:20] =============== drm_test_check_plane_state ================
[12:49:20] [PASSED] clipping_simple
[12:49:20] [PASSED] clipping_rotate_reflect
[12:49:20] [PASSED] positioning_simple
[12:49:20] [PASSED] upscaling
[12:49:20] [PASSED] downscaling
[12:49:20] [PASSED] rounding1
[12:49:20] [PASSED] rounding2
[12:49:20] [PASSED] rounding3
[12:49:20] [PASSED] rounding4
[12:49:20] =========== [PASSED] drm_test_check_plane_state ============
[12:49:20] =========== drm_test_check_invalid_plane_state ============
[12:49:20] [PASSED] positioning_invalid
[12:49:20] [PASSED] upscaling_invalid
[12:49:20] [PASSED] downscaling_invalid
[12:49:20] ======= [PASSED] drm_test_check_invalid_plane_state ========
[12:49:20] ================ [PASSED] drm_plane_helper =================
[12:49:20] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[12:49:20] ====== drm_test_connector_helper_tv_get_modes_check =======
[12:49:20] [PASSED] None
[12:49:20] [PASSED] PAL
[12:49:20] [PASSED] NTSC
[12:49:20] [PASSED] Both, NTSC Default
[12:49:20] [PASSED] Both, PAL Default
[12:49:20] [PASSED] Both, NTSC Default, with PAL on command-line
[12:49:20] [PASSED] Both, PAL Default, with NTSC on command-line
[12:49:20] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[12:49:20] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[12:49:20] ================== drm_rect (9 subtests) ===================
[12:49:20] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[12:49:20] [PASSED] drm_test_rect_clip_scaled_not_clipped
[12:49:20] [PASSED] drm_test_rect_clip_scaled_clipped
[12:49:20] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[12:49:20] ================= drm_test_rect_intersect =================
[12:49:20] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[12:49:20] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[12:49:20] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[12:49:20] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[12:49:20] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[12:49:20] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[12:49:20] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[12:49:20] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[12:49:20] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[12:49:20] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[12:49:20] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[12:49:20] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[12:49:20] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[12:49:20] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[12:49:20] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[12:49:20] ============= [PASSED] drm_test_rect_intersect =============
[12:49:20] ================ drm_test_rect_calc_hscale ================
[12:49:20] [PASSED] normal use
[12:49:20] [PASSED] out of max range
[12:49:20] [PASSED] out of min range
[12:49:20] [PASSED] zero dst
[12:49:20] [PASSED] negative src
[12:49:20] [PASSED] negative dst
[12:49:20] ============ [PASSED] drm_test_rect_calc_hscale ============
[12:49:20] ================ drm_test_rect_calc_vscale ================
[12:49:20] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[12:49:20] [PASSED] out of max range
[12:49:20] [PASSED] out of min range
[12:49:20] [PASSED] zero dst
[12:49:20] [PASSED] negative src
[12:49:20] [PASSED] negative dst
[12:49:20] ============ [PASSED] drm_test_rect_calc_vscale ============
[12:49:20] ================== drm_test_rect_rotate ===================
[12:49:20] [PASSED] reflect-x
[12:49:20] [PASSED] reflect-y
[12:49:20] [PASSED] rotate-0
[12:49:20] [PASSED] rotate-90
[12:49:20] [PASSED] rotate-180
[12:49:20] [PASSED] rotate-270
[12:49:20] ============== [PASSED] drm_test_rect_rotate ===============
[12:49:20] ================ drm_test_rect_rotate_inv =================
[12:49:20] [PASSED] reflect-x
[12:49:20] [PASSED] reflect-y
[12:49:20] [PASSED] rotate-0
[12:49:20] [PASSED] rotate-90
[12:49:20] [PASSED] rotate-180
[12:49:20] [PASSED] rotate-270
[12:49:20] ============ [PASSED] drm_test_rect_rotate_inv =============
[12:49:20] ==================== [PASSED] drm_rect =====================
[12:49:20] ============ drm_sysfb_modeset_test (1 subtest) ============
[12:49:20] ============ drm_test_sysfb_build_fourcc_list =============
[12:49:20] [PASSED] no native formats
[12:49:20] [PASSED] XRGB8888 as native format
[12:49:20] [PASSED] remove duplicates
[12:49:20] [PASSED] convert alpha formats
[12:49:20] [PASSED] random formats
[12:49:20] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[12:49:20] ============= [PASSED] drm_sysfb_modeset_test ==============
[12:49:20] ============================================================
[12:49:20] Testing complete. Ran 622 tests: passed: 622
[12:49:20] Elapsed time: 26.949s total, 1.683s configuring, 24.848s building, 0.381s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[12:49:20] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[12:49:21] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[12:49:31] Starting KUnit Kernel (1/1)...
[12:49:31] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[12:49:31] ================= ttm_device (5 subtests) ==================
[12:49:31] [PASSED] ttm_device_init_basic
[12:49:31] [PASSED] ttm_device_init_multiple
[12:49:31] [PASSED] ttm_device_fini_basic
[12:49:31] [PASSED] ttm_device_init_no_vma_man
[12:49:31] ================== ttm_device_init_pools ==================
[12:49:31] [PASSED] No DMA allocations, no DMA32 required
[12:49:31] [PASSED] DMA allocations, DMA32 required
[12:49:31] [PASSED] No DMA allocations, DMA32 required
[12:49:31] [PASSED] DMA allocations, no DMA32 required
[12:49:31] ============== [PASSED] ttm_device_init_pools ==============
[12:49:31] =================== [PASSED] ttm_device ====================
[12:49:31] ================== ttm_pool (8 subtests) ===================
[12:49:31] ================== ttm_pool_alloc_basic ===================
[12:49:31] [PASSED] One page
[12:49:31] [PASSED] More than one page
[12:49:31] [PASSED] Above the allocation limit
[12:49:31] [PASSED] One page, with coherent DMA mappings enabled
[12:49:31] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[12:49:31] ============== [PASSED] ttm_pool_alloc_basic ===============
[12:49:31] ============== ttm_pool_alloc_basic_dma_addr ==============
[12:49:31] [PASSED] One page
[12:49:31] [PASSED] More than one page
[12:49:31] [PASSED] Above the allocation limit
[12:49:31] [PASSED] One page, with coherent DMA mappings enabled
[12:49:31] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[12:49:31] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[12:49:31] [PASSED] ttm_pool_alloc_order_caching_match
[12:49:31] [PASSED] ttm_pool_alloc_caching_mismatch
[12:49:31] [PASSED] ttm_pool_alloc_order_mismatch
[12:49:31] [PASSED] ttm_pool_free_dma_alloc
[12:49:31] [PASSED] ttm_pool_free_no_dma_alloc
[12:49:31] [PASSED] ttm_pool_fini_basic
[12:49:31] ==================== [PASSED] ttm_pool =====================
[12:49:31] ================ ttm_resource (8 subtests) =================
[12:49:31] ================= ttm_resource_init_basic =================
[12:49:31] [PASSED] Init resource in TTM_PL_SYSTEM
[12:49:31] [PASSED] Init resource in TTM_PL_VRAM
[12:49:31] [PASSED] Init resource in a private placement
[12:49:31] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[12:49:31] ============= [PASSED] ttm_resource_init_basic =============
[12:49:31] [PASSED] ttm_resource_init_pinned
[12:49:31] [PASSED] ttm_resource_fini_basic
[12:49:31] [PASSED] ttm_resource_manager_init_basic
[12:49:31] [PASSED] ttm_resource_manager_usage_basic
[12:49:31] [PASSED] ttm_resource_manager_set_used_basic
[12:49:31] [PASSED] ttm_sys_man_alloc_basic
[12:49:31] [PASSED] ttm_sys_man_free_basic
[12:49:31] ================== [PASSED] ttm_resource ===================
[12:49:31] =================== ttm_tt (15 subtests) ===================
[12:49:31] ==================== ttm_tt_init_basic ====================
[12:49:31] [PASSED] Page-aligned size
[12:49:31] [PASSED] Extra pages requested
[12:49:31] ================ [PASSED] ttm_tt_init_basic ================
[12:49:31] [PASSED] ttm_tt_init_misaligned
[12:49:31] [PASSED] ttm_tt_fini_basic
[12:49:31] [PASSED] ttm_tt_fini_sg
[12:49:31] [PASSED] ttm_tt_fini_shmem
[12:49:31] [PASSED] ttm_tt_create_basic
[12:49:31] [PASSED] ttm_tt_create_invalid_bo_type
[12:49:31] [PASSED] ttm_tt_create_ttm_exists
[12:49:31] [PASSED] ttm_tt_create_failed
[12:49:31] [PASSED] ttm_tt_destroy_basic
[12:49:31] [PASSED] ttm_tt_populate_null_ttm
[12:49:31] [PASSED] ttm_tt_populate_populated_ttm
[12:49:31] [PASSED] ttm_tt_unpopulate_basic
[12:49:31] [PASSED] ttm_tt_unpopulate_empty_ttm
[12:49:31] [PASSED] ttm_tt_swapin_basic
[12:49:31] ===================== [PASSED] ttm_tt ======================
[12:49:31] =================== ttm_bo (14 subtests) ===================
[12:49:31] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[12:49:31] [PASSED] Cannot be interrupted and sleeps
[12:49:31] [PASSED] Cannot be interrupted, locks straight away
[12:49:31] [PASSED] Can be interrupted, sleeps
[12:49:31] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[12:49:31] [PASSED] ttm_bo_reserve_locked_no_sleep
[12:49:31] [PASSED] ttm_bo_reserve_no_wait_ticket
[12:49:31] [PASSED] ttm_bo_reserve_double_resv
[12:49:31] [PASSED] ttm_bo_reserve_interrupted
[12:49:31] [PASSED] ttm_bo_reserve_deadlock
[12:49:31] [PASSED] ttm_bo_unreserve_basic
[12:49:31] [PASSED] ttm_bo_unreserve_pinned
[12:49:31] [PASSED] ttm_bo_unreserve_bulk
[12:49:31] [PASSED] ttm_bo_fini_basic
[12:49:31] [PASSED] ttm_bo_fini_shared_resv
[12:49:31] [PASSED] ttm_bo_pin_basic
[12:49:31] [PASSED] ttm_bo_pin_unpin_resource
[12:49:31] [PASSED] ttm_bo_multiple_pin_one_unpin
[12:49:31] ===================== [PASSED] ttm_bo ======================
[12:49:31] ============== ttm_bo_validate (21 subtests) ===============
[12:49:31] ============== ttm_bo_init_reserved_sys_man ===============
[12:49:31] [PASSED] Buffer object for userspace
[12:49:31] [PASSED] Kernel buffer object
[12:49:31] [PASSED] Shared buffer object
[12:49:31] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[12:49:31] ============== ttm_bo_init_reserved_mock_man ==============
[12:49:31] [PASSED] Buffer object for userspace
[12:49:31] [PASSED] Kernel buffer object
[12:49:31] [PASSED] Shared buffer object
[12:49:31] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[12:49:31] [PASSED] ttm_bo_init_reserved_resv
[12:49:31] ================== ttm_bo_validate_basic ==================
[12:49:31] [PASSED] Buffer object for userspace
[12:49:31] [PASSED] Kernel buffer object
[12:49:31] [PASSED] Shared buffer object
[12:49:31] ============== [PASSED] ttm_bo_validate_basic ==============
[12:49:31] [PASSED] ttm_bo_validate_invalid_placement
[12:49:31] ============= ttm_bo_validate_same_placement ==============
[12:49:31] [PASSED] System manager
[12:49:31] [PASSED] VRAM manager
[12:49:31] ========= [PASSED] ttm_bo_validate_same_placement ==========
[12:49:31] [PASSED] ttm_bo_validate_failed_alloc
[12:49:31] [PASSED] ttm_bo_validate_pinned
[12:49:31] [PASSED] ttm_bo_validate_busy_placement
[12:49:31] ================ ttm_bo_validate_multihop =================
[12:49:31] [PASSED] Buffer object for userspace
[12:49:31] [PASSED] Kernel buffer object
[12:49:31] [PASSED] Shared buffer object
[12:49:31] ============ [PASSED] ttm_bo_validate_multihop =============
[12:49:31] ========== ttm_bo_validate_no_placement_signaled ==========
[12:49:31] [PASSED] Buffer object in system domain, no page vector
[12:49:31] [PASSED] Buffer object in system domain with an existing page vector
[12:49:31] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[12:49:31] ======== ttm_bo_validate_no_placement_not_signaled ========
[12:49:31] [PASSED] Buffer object for userspace
[12:49:31] [PASSED] Kernel buffer object
[12:49:31] [PASSED] Shared buffer object
[12:49:31] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[12:49:31] [PASSED] ttm_bo_validate_move_fence_signaled
[12:49:31] ========= ttm_bo_validate_move_fence_not_signaled =========
[12:49:31] [PASSED] Waits for GPU
[12:49:31] [PASSED] Tries to lock straight away
[12:49:31] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[12:49:31] [PASSED] ttm_bo_validate_happy_evict
[12:49:31] [PASSED] ttm_bo_validate_all_pinned_evict
[12:49:31] [PASSED] ttm_bo_validate_allowed_only_evict
[12:49:31] [PASSED] ttm_bo_validate_deleted_evict
[12:49:31] [PASSED] ttm_bo_validate_busy_domain_evict
[12:49:31] [PASSED] ttm_bo_validate_evict_gutting
[12:49:31] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[12:49:31] ================= [PASSED] ttm_bo_validate =================
[12:49:31] ============================================================
[12:49:31] Testing complete. Ran 101 tests: passed: 101
[12:49:31] Elapsed time: 11.363s total, 1.740s configuring, 9.357s building, 0.224s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 6+ messages in thread