* [PATCH 0/8] Move PSR/Panel Replay sink data into intel_connector
@ 2025-11-21 11:16 Jouni Högander
2025-11-21 11:16 ` [PATCH 1/8] drm/i915/psr: Add panel granularity information " Jouni Högander
` (11 more replies)
0 siblings, 12 replies; 25+ messages in thread
From: Jouni Högander @ 2025-11-21 11:16 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: Jouni Högander
This is a preparation patch set for MST Panel Replay.
In case of MST Panel Replay we may have several CRTCs on single
pipe. There CRTCs representing virtual devices within e.g. docking
station. All these virtual devices has their own DPCD registers
containing their Panel Replay capability information. These needs to
be taken into account when computing used Panel Replay state. Due to
this we can't continue having only sink capabilities stored in struct
intel_dp.
This patch set is moving Panel Replay capabilities into struct
intel_connector to make them available for Panel Replay CRTC state
computation.
Jouni Högander (8):
drm/i915/psr: Add panel granularity information into intel_connector
drm/i915/psr: Use SU granularity information available in
intel_connector
drm/i915/psr: Compute Panel Replay/Adaptive coexistence behavior
drm/i915/psr: Move pr_dpcd and psr_dpcd to intel_connector
drm/i915/psr: Clear pr_dpcd as well on disconnect
drm/i915/psr: Move Panel Replay DSC sink support data to
intel_connector
drm/i915/psr: Move sink PSR and Panel Replay booleans to
intel_connector
drm/i915/psr: Move sink_sync_latency to intel_connector
drivers/gpu/drm/i915/display/intel_alpm.c | 6 +-
.../drm/i915/display/intel_display_types.h | 43 ++-
drivers/gpu/drm/i915/display/intel_dp.c | 11 +-
drivers/gpu/drm/i915/display/intel_psr.c | 283 ++++++++++--------
drivers/gpu/drm/i915/display/intel_psr.h | 2 +-
5 files changed, 192 insertions(+), 153 deletions(-)
--
2.43.0
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH 1/8] drm/i915/psr: Add panel granularity information into intel_connector
2025-11-21 11:16 [PATCH 0/8] Move PSR/Panel Replay sink data into intel_connector Jouni Högander
@ 2025-11-21 11:16 ` Jouni Högander
2025-12-01 9:54 ` Imre Deak
2025-11-21 11:16 ` [PATCH 2/8] drm/i915/psr: Use SU granularity information available in intel_connector Jouni Högander
` (10 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Jouni Högander @ 2025-11-21 11:16 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: Jouni Högander
As a preparation for MST Panel Replay implementation add psr_caps and
panel_replay_caps structures into intel_connector. These are supposed to
contain all sink information related to PSR and Panel Replay.
As a first step in moving Panel Replay and PSR sink data add panel
granularity information into these newly added caps structures.
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_types.h | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 38702a9e0f508..f39d62aa99246 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -561,6 +561,16 @@ struct intel_connector {
} overall_throughput;
int max_line_width;
} dsc_branch_caps;
+
+ struct {
+ u16 su_w_granularity;
+ u16 su_y_granularity;
+ } panel_replay_caps;
+
+ struct {
+ u16 su_w_granularity;
+ u16 su_y_granularity;
+ } psr_caps;
} dp;
struct {
--
2.43.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 2/8] drm/i915/psr: Use SU granularity information available in intel_connector
2025-11-21 11:16 [PATCH 0/8] Move PSR/Panel Replay sink data into intel_connector Jouni Högander
2025-11-21 11:16 ` [PATCH 1/8] drm/i915/psr: Add panel granularity information " Jouni Högander
@ 2025-11-21 11:16 ` Jouni Högander
2025-12-01 10:14 ` Imre Deak
2025-11-21 11:16 ` [PATCH 3/8] drm/i915/psr: Compute Panel Replay/Adaptive coexistence behavior Jouni Högander
` (9 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Jouni Högander @ 2025-11-21 11:16 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: Jouni Högander
Currently we are storing only one set of granularity information for panels
supporting both PSR and Panel Replay. It might be that in practice they are
always the same. As panel is informing own granularities for PSR and Panel
Replay let's use these instead of having only one set for both. This is
done by having intel_connector::psr_caps and panel_replay_caps both
containing granularity information.
This patch is also removing complexity of sharing granularity read between
PSR and Panel Replay.
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 4 +-
drivers/gpu/drm/i915/display/intel_psr.c | 139 +++++++++++------------
drivers/gpu/drm/i915/display/intel_psr.h | 2 +-
3 files changed, 69 insertions(+), 76 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 0ec82fcbcf48e..62808cd35f5f2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4562,7 +4562,7 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector
* This has to be called after intel_dp->edp_dpcd is filled, PSR checks
* for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
*/
- intel_psr_init_dpcd(intel_dp);
+ intel_psr_init_dpcd(intel_dp, connector);
intel_edp_set_sink_rates(intel_dp);
intel_dp_set_max_sink_lane_count(intel_dp);
@@ -6075,7 +6075,7 @@ intel_dp_detect(struct drm_connector *_connector,
connector->base.epoch_counter++;
if (!intel_dp_is_edp(intel_dp))
- intel_psr_init_dpcd(intel_dp);
+ intel_psr_init_dpcd(intel_dp, connector);
intel_dp_detect_dsc_caps(intel_dp, connector);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 00ac652809cca..4c5883bed612b 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -494,69 +494,26 @@ static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)
return val;
}
-static u8 intel_dp_get_su_capability(struct intel_dp *intel_dp)
-{
- u8 su_capability = 0;
-
- if (intel_dp->psr.sink_panel_replay_su_support) {
- if (drm_dp_dpcd_read_byte(&intel_dp->aux,
- DP_PANEL_REPLAY_CAP_CAPABILITY,
- &su_capability) < 0)
- return 0;
- } else {
- su_capability = intel_dp->psr_dpcd[1];
- }
-
- return su_capability;
-}
-
-static unsigned int
-intel_dp_get_su_x_granularity_offset(struct intel_dp *intel_dp)
-{
- return intel_dp->psr.sink_panel_replay_su_support ?
- DP_PANEL_REPLAY_CAP_X_GRANULARITY :
- DP_PSR2_SU_X_GRANULARITY;
-}
-
-static unsigned int
-intel_dp_get_su_y_granularity_offset(struct intel_dp *intel_dp)
-{
- return intel_dp->psr.sink_panel_replay_su_support ?
- DP_PANEL_REPLAY_CAP_Y_GRANULARITY :
- DP_PSR2_SU_Y_GRANULARITY;
-}
-
-/*
- * Note: Bits related to granularity are same in panel replay and psr
- * registers. Rely on PSR definitions on these "common" bits.
- */
-static void intel_dp_get_su_granularity(struct intel_dp *intel_dp)
+static void _psr_compute_su_granularity(struct intel_dp *intel_dp,
+ struct intel_connector *connector)
{
struct intel_display *display = to_intel_display(intel_dp);
ssize_t r;
u16 w;
u8 y;
- /*
- * TODO: Do we need to take into account panel supporting both PSR and
- * Panel replay?
- */
-
/*
* If sink don't have specific granularity requirements set legacy
* ones.
*/
- if (!(intel_dp_get_su_capability(intel_dp) &
- DP_PSR2_SU_GRANULARITY_REQUIRED)) {
+ if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) {
/* As PSR2 HW sends full lines, we do not care about x granularity */
w = 4;
y = 4;
goto exit;
}
- r = drm_dp_dpcd_read(&intel_dp->aux,
- intel_dp_get_su_x_granularity_offset(intel_dp),
- &w, 2);
+ r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &w, 2);
if (r != 2)
drm_dbg_kms(display->drm,
"Unable to read selective update x granularity\n");
@@ -567,9 +524,7 @@ static void intel_dp_get_su_granularity(struct intel_dp *intel_dp)
if (r != 2 || w == 0)
w = 4;
- r = drm_dp_dpcd_read(&intel_dp->aux,
- intel_dp_get_su_y_granularity_offset(intel_dp),
- &y, 1);
+ r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_Y_GRANULARITY, &y, 1);
if (r != 1) {
drm_dbg_kms(display->drm,
"Unable to read selective update y granularity\n");
@@ -579,8 +534,8 @@ static void intel_dp_get_su_granularity(struct intel_dp *intel_dp)
y = 1;
exit:
- intel_dp->psr.su_w_granularity = w;
- intel_dp->psr.su_y_granularity = y;
+ connector->dp.psr_caps.su_w_granularity = w;
+ connector->dp.psr_caps.su_y_granularity = y;
}
static enum intel_panel_replay_dsc_support
@@ -621,7 +576,33 @@ static const char *panel_replay_dsc_support_str(enum intel_panel_replay_dsc_supp
};
}
-static void _panel_replay_init_dpcd(struct intel_dp *intel_dp)
+static void _panel_replay_compute_su_granularity(struct intel_dp *intel_dp,
+ struct intel_connector *connector)
+{
+ u16 w;
+ u8 y;
+
+ if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
+ DP_PANEL_REPLAY_SU_GRANULARITY_REQUIRED)) {
+ w = 4;
+ y = 4;
+ goto exit;
+ }
+
+ /*
+ * Spec says that if the value read is 0 the default granularity should
+ * be used instead.
+ */
+ w = intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_X_GRANULARITY)] ? : 4;
+
+ y = intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_Y_GRANULARITY)] ? : 1;
+
+exit:
+ connector->dp.panel_replay_caps.su_w_granularity = w;
+ connector->dp.panel_replay_caps.su_y_granularity = y;
+}
+
+static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
{
struct intel_display *display = to_intel_display(intel_dp);
int ret;
@@ -657,9 +638,12 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp)
intel_dp->psr.sink_panel_replay_support = true;
if (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
- DP_PANEL_REPLAY_SU_SUPPORT)
+ DP_PANEL_REPLAY_SU_SUPPORT) {
intel_dp->psr.sink_panel_replay_su_support = true;
+ _panel_replay_compute_su_granularity(intel_dp, connector);
+ }
+
intel_dp->psr.sink_panel_replay_dsc_support = compute_pr_dsc_support(intel_dp);
drm_dbg_kms(display->drm,
@@ -669,7 +653,7 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp)
panel_replay_dsc_support_str(intel_dp->psr.sink_panel_replay_dsc_support));
}
-static void _psr_init_dpcd(struct intel_dp *intel_dp)
+static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
{
struct intel_display *display = to_intel_display(intel_dp);
int ret;
@@ -722,17 +706,16 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp)
drm_dbg_kms(display->drm, "PSR2 %ssupported\n",
intel_dp->psr.sink_psr2_support ? "" : "not ");
}
+
+ if (intel_dp->psr.sink_psr2_support)
+ _psr_compute_su_granularity(intel_dp, connector);
}
-void intel_psr_init_dpcd(struct intel_dp *intel_dp)
+void intel_psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
{
- _psr_init_dpcd(intel_dp);
+ _psr_init_dpcd(intel_dp, connector);
- _panel_replay_init_dpcd(intel_dp);
-
- if (intel_dp->psr.sink_psr2_support ||
- intel_dp->psr.sink_panel_replay_su_support)
- intel_dp_get_su_granularity(intel_dp);
+ _panel_replay_init_dpcd(intel_dp, connector);
}
static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
@@ -1311,24 +1294,32 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
}
static bool psr2_granularity_check(struct intel_dp *intel_dp,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state)
{
struct intel_display *display = to_intel_display(intel_dp);
+ struct intel_connector *connector = to_intel_connector(conn_state->connector);
const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
u16 y_granularity = 0;
+ u16 sink_y_granularity = crtc_state->has_panel_replay ?
+ connector->dp.panel_replay_caps.su_y_granularity :
+ connector->dp.psr_caps.su_y_granularity;
+ u16 sink_w_granularity = crtc_state->has_panel_replay ?
+ connector->dp.panel_replay_caps.su_w_granularity :
+ connector->dp.psr_caps.su_w_granularity;
/* PSR2 HW only send full lines so we only need to validate the width */
- if (crtc_hdisplay % intel_dp->psr.su_w_granularity)
+ if (crtc_hdisplay % sink_w_granularity)
return false;
- if (crtc_vdisplay % intel_dp->psr.su_y_granularity)
+ if (crtc_vdisplay % sink_y_granularity)
return false;
/* HW tracking is only aligned to 4 lines */
if (!crtc_state->enable_psr2_sel_fetch)
- return intel_dp->psr.su_y_granularity == 4;
+ return sink_y_granularity == 4;
/*
* adl_p and mtl platforms have 1 line granularity.
@@ -1336,11 +1327,11 @@ static bool psr2_granularity_check(struct intel_dp *intel_dp,
* to match sink requirement if multiple of 4.
*/
if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14)
- y_granularity = intel_dp->psr.su_y_granularity;
- else if (intel_dp->psr.su_y_granularity <= 2)
+ y_granularity = sink_y_granularity;
+ else if (sink_y_granularity <= 2)
y_granularity = 4;
- else if ((intel_dp->psr.su_y_granularity % 4) == 0)
- y_granularity = intel_dp->psr.su_y_granularity;
+ else if ((sink_y_granularity % 4) == 0)
+ y_granularity = sink_y_granularity;
if (y_granularity == 0 || crtc_vdisplay % y_granularity)
return false;
@@ -1628,7 +1619,8 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
}
static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state)
{
struct intel_display *display = to_intel_display(intel_dp);
@@ -1677,7 +1669,7 @@ static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
goto unsupported;
}
- if (!psr2_granularity_check(intel_dp, crtc_state)) {
+ if (!psr2_granularity_check(intel_dp, crtc_state, conn_state)) {
drm_dbg_kms(display->drm,
"Selective update not enabled, SU granularity not compatible\n");
goto unsupported;
@@ -1872,7 +1864,8 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
if (!crtc_state->has_psr)
return;
- crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp, crtc_state);
+ crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp, crtc_state,
+ conn_state);
}
void intel_psr_get_config(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 620b359288326..688ca3e73cdda 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -28,7 +28,7 @@ struct intel_plane_state;
bool intel_encoder_can_psr(struct intel_encoder *encoder);
bool intel_psr_needs_aux_io_power(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
-void intel_psr_init_dpcd(struct intel_dp *intel_dp);
+void intel_psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector);
void intel_psr_panel_replay_enable_sink(struct intel_dp *intel_dp);
void intel_psr_pre_plane_update(struct intel_atomic_state *state,
struct intel_crtc *crtc);
--
2.43.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 3/8] drm/i915/psr: Compute Panel Replay/Adaptive coexistence behavior
2025-11-21 11:16 [PATCH 0/8] Move PSR/Panel Replay sink data into intel_connector Jouni Högander
2025-11-21 11:16 ` [PATCH 1/8] drm/i915/psr: Add panel granularity information " Jouni Högander
2025-11-21 11:16 ` [PATCH 2/8] drm/i915/psr: Use SU granularity information available in intel_connector Jouni Högander
@ 2025-11-21 11:16 ` Jouni Högander
2025-11-21 11:24 ` Jani Nikula
2025-12-01 10:28 ` Imre Deak
2025-11-21 11:16 ` [PATCH 4/8] drm/i915/psr: Move pr_dpcd and psr_dpcd to intel_connector Jouni Högander
` (8 subsequent siblings)
11 siblings, 2 replies; 25+ messages in thread
From: Jouni Högander @ 2025-11-21 11:16 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: Jouni Högander
Currently we are checking Panel Replay capability DPCD register in
intel_alpm.c and writing PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU
and PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE in PR_ALPM_CTL
register base on the informaion. Instead of directly accessing
intel_dp->pr_dpcd compute the behavior during psr_compute_config and store
it in intel_crtc_state.
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
drivers/gpu/drm/i915/display/intel_alpm.c | 6 ++---
.../drm/i915/display/intel_display_types.h | 2 ++
drivers/gpu/drm/i915/display/intel_psr.c | 22 +++++++++++++++----
3 files changed, 22 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 6372f533f65b5..7ce8c674bb030 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -326,11 +326,9 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
if (intel_dp->as_sdp_supported) {
u32 pr_alpm_ctl = PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
- if (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
- DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP)
+ if (crtc_state->link_off_after_as_sdp_when_pr_active)
pr_alpm_ctl |= PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU;
- if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
- DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR))
+ if (crtc_state->disable_as_sdp_when_pr_active)
pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
intel_de_write(display, PR_ALPM_CTL(display, cpu_transcoder),
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index f39d62aa99246..d8a222689a35b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1161,6 +1161,8 @@ struct intel_crtc_state {
bool enable_psr2_su_region_et;
bool req_psr2_sdp_prior_scanline;
bool has_panel_replay;
+ bool link_off_after_as_sdp_when_pr_active;
+ bool disable_as_sdp_when_pr_active;
bool wm_level_disabled;
bool pkg_c_latency_used;
/* Only used for state verification. */
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 4c5883bed612b..9d2ba39423826 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1715,10 +1715,21 @@ static bool _psr_compute_config(struct intel_dp *intel_dp,
return true;
}
-static bool
-_panel_replay_compute_config(struct intel_dp *intel_dp,
- struct intel_crtc_state *crtc_state,
- const struct drm_connector_state *conn_state)
+static bool compute_link_off_after_as_sdp_when_pr_active(struct intel_dp *intel_dp)
+{
+ return (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
+ DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP);
+}
+
+static bool compute_disable_as_sdp_when_pr_active(struct intel_dp *intel_dp)
+{
+ return !(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
+ DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR);
+}
+
+static bool _panel_replay_compute_config(struct intel_dp *intel_dp,
+ struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state)
{
struct intel_display *display = to_intel_display(intel_dp);
struct intel_connector *connector =
@@ -1747,6 +1758,9 @@ _panel_replay_compute_config(struct intel_dp *intel_dp,
return false;
}
+ crtc_state->link_off_after_as_sdp_when_pr_active = compute_link_off_after_as_sdp_when_pr_active(intel_dp);
+ crtc_state->disable_as_sdp_when_pr_active = compute_disable_as_sdp_when_pr_active(intel_dp);
+
if (!intel_dp_is_edp(intel_dp))
return true;
--
2.43.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 4/8] drm/i915/psr: Move pr_dpcd and psr_dpcd to intel_connector
2025-11-21 11:16 [PATCH 0/8] Move PSR/Panel Replay sink data into intel_connector Jouni Högander
` (2 preceding siblings ...)
2025-11-21 11:16 ` [PATCH 3/8] drm/i915/psr: Compute Panel Replay/Adaptive coexistence behavior Jouni Högander
@ 2025-11-21 11:16 ` Jouni Högander
2025-12-01 10:45 ` Imre Deak
2025-11-21 11:16 ` [PATCH 5/8] drm/i915/psr: Clear pr_dpcd as well on disconnect Jouni Högander
` (7 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Jouni Högander @ 2025-11-21 11:16 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: Jouni Högander
As a preparation for MST Panel Replay we need to move Panel Replay sink
related data into intel_connector. Move pr_dpcd as well into
intel_connector. Generally this is more correct place for this data so move
psr_dpcd as well.
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
.../drm/i915/display/intel_display_types.h | 6 +-
drivers/gpu/drm/i915/display/intel_psr.c | 85 ++++++++++---------
2 files changed, 49 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index d8a222689a35b..8587d2c527f72 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -548,6 +548,9 @@ struct intel_connector {
struct {
struct drm_dp_aux *dsc_decompression_aux;
u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
+ u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
+ u8 pr_dpcd[DP_PANEL_REPLAY_CAP_SIZE];
+#define INTEL_PR_DPCD_INDEX(pr_dpcd_register) ((pr_dpcd_register) - DP_PANEL_REPLAY_CAP_SUPPORT)
u8 fec_capability;
u8 dsc_hblank_expansion_quirk:1;
@@ -1768,9 +1771,6 @@ struct intel_dp {
bool needs_modeset_retry;
bool use_max_params;
u8 dpcd[DP_RECEIVER_CAP_SIZE];
- u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
- u8 pr_dpcd[DP_PANEL_REPLAY_CAP_SIZE];
-#define INTEL_PR_DPCD_INDEX(pr_dpcd_register) ((pr_dpcd_register) - DP_PANEL_REPLAY_CAP_SUPPORT)
u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 9d2ba39423826..b488be8c917dc 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -506,7 +506,7 @@ static void _psr_compute_su_granularity(struct intel_dp *intel_dp,
* If sink don't have specific granularity requirements set legacy
* ones.
*/
- if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) {
+ if (!(connector->dp.psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) {
/* As PSR2 HW sends full lines, we do not care about x granularity */
w = 4;
y = 4;
@@ -539,12 +539,12 @@ static void _psr_compute_su_granularity(struct intel_dp *intel_dp,
}
static enum intel_panel_replay_dsc_support
-compute_pr_dsc_support(struct intel_dp *intel_dp)
+compute_pr_dsc_support(struct intel_connector *connector)
{
u8 pr_dsc_mode;
u8 val;
- val = intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)];
+ val = connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)];
pr_dsc_mode = REG_FIELD_GET8(DP_PANEL_REPLAY_DSC_DECODE_CAPABILITY_IN_PR_MASK, val);
switch (pr_dsc_mode) {
@@ -582,7 +582,7 @@ static void _panel_replay_compute_su_granularity(struct intel_dp *intel_dp,
u16 w;
u8 y;
- if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
+ if (!(connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
DP_PANEL_REPLAY_SU_GRANULARITY_REQUIRED)) {
w = 4;
y = 4;
@@ -593,9 +593,9 @@ static void _panel_replay_compute_su_granularity(struct intel_dp *intel_dp,
* Spec says that if the value read is 0 the default granularity should
* be used instead.
*/
- w = intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_X_GRANULARITY)] ? : 4;
+ w = connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_X_GRANULARITY)] ? : 4;
- y = intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_Y_GRANULARITY)] ? : 1;
+ y = connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_Y_GRANULARITY)] ? : 1;
exit:
connector->dp.panel_replay_caps.su_w_granularity = w;
@@ -612,11 +612,11 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_conn
return;
ret = drm_dp_dpcd_read_data(&intel_dp->aux, DP_PANEL_REPLAY_CAP_SUPPORT,
- &intel_dp->pr_dpcd, sizeof(intel_dp->pr_dpcd));
+ &connector->dp.pr_dpcd, sizeof(connector->dp.pr_dpcd));
if (ret < 0)
return;
- if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
+ if (!(connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
DP_PANEL_REPLAY_SUPPORT))
return;
@@ -627,7 +627,7 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_conn
return;
}
- if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
+ if (!(connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)) {
drm_dbg_kms(display->drm,
"Panel doesn't support early transport, eDP Panel Replay not possible\n");
@@ -637,14 +637,14 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_conn
intel_dp->psr.sink_panel_replay_support = true;
- if (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
+ if (connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
DP_PANEL_REPLAY_SU_SUPPORT) {
intel_dp->psr.sink_panel_replay_su_support = true;
_panel_replay_compute_su_granularity(intel_dp, connector);
}
- intel_dp->psr.sink_panel_replay_dsc_support = compute_pr_dsc_support(intel_dp);
+ intel_dp->psr.sink_panel_replay_dsc_support = compute_pr_dsc_support(connector);
drm_dbg_kms(display->drm,
"Panel replay %sis supported by panel (in DSC mode: %s)\n",
@@ -658,16 +658,16 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *co
struct intel_display *display = to_intel_display(intel_dp);
int ret;
- ret = drm_dp_dpcd_read_data(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
- sizeof(intel_dp->psr_dpcd));
+ ret = drm_dp_dpcd_read_data(&intel_dp->aux, DP_PSR_SUPPORT, connector->dp.psr_dpcd,
+ sizeof(connector->dp.psr_dpcd));
if (ret < 0)
return;
- if (!intel_dp->psr_dpcd[0])
+ if (!connector->dp.psr_dpcd[0])
return;
drm_dbg_kms(display->drm, "eDP panel supports PSR version %x\n",
- intel_dp->psr_dpcd[0]);
+ connector->dp.psr_dpcd[0]);
if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) {
drm_dbg_kms(display->drm,
@@ -686,8 +686,8 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *co
intel_dp_get_sink_sync_latency(intel_dp);
if (DISPLAY_VER(display) >= 9 &&
- intel_dp->psr_dpcd[0] >= DP_PSR2_WITH_Y_COORD_IS_SUPPORTED) {
- bool y_req = intel_dp->psr_dpcd[1] &
+ connector->dp.psr_dpcd[0] >= DP_PSR2_WITH_Y_COORD_IS_SUPPORTED) {
+ bool y_req = connector->dp.psr_dpcd[1] &
DP_PSR2_SU_Y_COORDINATE_REQUIRED;
/*
@@ -755,7 +755,8 @@ static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
aux_ctl);
}
-static bool psr2_su_region_et_valid(struct intel_dp *intel_dp, bool panel_replay)
+static bool psr2_su_region_et_valid(struct intel_dp *intel_dp, struct intel_connector *connector,
+ bool panel_replay)
{
struct intel_display *display = to_intel_display(intel_dp);
@@ -764,9 +765,9 @@ static bool psr2_su_region_et_valid(struct intel_dp *intel_dp, bool panel_replay
return false;
return panel_replay ?
- intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
+ connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT :
- intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED;
+ connector->dp.psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED;
}
static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
@@ -1369,16 +1370,18 @@ static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_d
}
static int intel_psr_entry_setup_frames(struct intel_dp *intel_dp,
+ struct drm_connector_state *conn_state,
const struct drm_display_mode *adjusted_mode)
{
struct intel_display *display = to_intel_display(intel_dp);
- int psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
+ struct intel_connector *connector = to_intel_connector(conn_state->connector);
+ int psr_setup_time = drm_dp_psr_setup_time(connector->dp.psr_dpcd);
int entry_setup_frames = 0;
if (psr_setup_time < 0) {
drm_dbg_kms(display->drm,
"PSR condition failed: Invalid PSR setup time (0x%02x)\n",
- intel_dp->psr_dpcd[1]);
+ connector->dp.psr_dpcd[1]);
return -ETIME;
}
@@ -1623,6 +1626,7 @@ static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
struct drm_connector_state *conn_state)
{
struct intel_display *display = to_intel_display(intel_dp);
+ struct intel_connector *connector = to_intel_connector(conn_state->connector);
if (HAS_PSR2_SEL_FETCH(display) &&
!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) &&
@@ -1676,7 +1680,7 @@ static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
}
crtc_state->enable_psr2_su_region_et =
- psr2_su_region_et_valid(intel_dp, crtc_state->has_panel_replay);
+ psr2_su_region_et_valid(intel_dp, connector, crtc_state->has_panel_replay);
return true;
@@ -1686,7 +1690,8 @@ static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
}
static bool _psr_compute_config(struct intel_dp *intel_dp,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state)
{
struct intel_display *display = to_intel_display(intel_dp);
const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
@@ -1701,7 +1706,7 @@ static bool _psr_compute_config(struct intel_dp *intel_dp,
if (crtc_state->vrr.enable)
return false;
- entry_setup_frames = intel_psr_entry_setup_frames(intel_dp, adjusted_mode);
+ entry_setup_frames = intel_psr_entry_setup_frames(intel_dp, conn_state, adjusted_mode);
if (entry_setup_frames >= 0) {
intel_dp->psr.entry_setup_frames = entry_setup_frames;
@@ -1715,15 +1720,15 @@ static bool _psr_compute_config(struct intel_dp *intel_dp,
return true;
}
-static bool compute_link_off_after_as_sdp_when_pr_active(struct intel_dp *intel_dp)
+static bool compute_link_off_after_as_sdp_when_pr_active(struct intel_connector *connector)
{
- return (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
+ return (connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP);
}
-static bool compute_disable_as_sdp_when_pr_active(struct intel_dp *intel_dp)
+static bool compute_disable_as_sdp_when_pr_active(struct intel_connector *connector)
{
- return !(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
+ return !(connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR);
}
@@ -1758,8 +1763,8 @@ static bool _panel_replay_compute_config(struct intel_dp *intel_dp,
return false;
}
- crtc_state->link_off_after_as_sdp_when_pr_active = compute_link_off_after_as_sdp_when_pr_active(intel_dp);
- crtc_state->disable_as_sdp_when_pr_active = compute_disable_as_sdp_when_pr_active(intel_dp);
+ crtc_state->link_off_after_as_sdp_when_pr_active = compute_link_off_after_as_sdp_when_pr_active(connector);
+ crtc_state->disable_as_sdp_when_pr_active = compute_disable_as_sdp_when_pr_active(connector);
if (!intel_dp_is_edp(intel_dp))
return true;
@@ -1873,7 +1878,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
conn_state);
crtc_state->has_psr = crtc_state->has_panel_replay ? true :
- _psr_compute_config(intel_dp, crtc_state);
+ _psr_compute_config(intel_dp, crtc_state, conn_state);
if (!crtc_state->has_psr)
return;
@@ -4123,6 +4128,7 @@ psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)
}
static void intel_psr_sink_capability(struct intel_dp *intel_dp,
+ struct intel_connector *connector,
struct seq_file *m)
{
struct intel_psr *psr = &intel_dp->psr;
@@ -4131,15 +4137,15 @@ static void intel_psr_sink_capability(struct intel_dp *intel_dp,
str_yes_no(psr->sink_support));
if (psr->sink_support)
- seq_printf(m, " [0x%02x]", intel_dp->psr_dpcd[0]);
- if (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED)
+ seq_printf(m, " [0x%02x]", connector->dp.psr_dpcd[0]);
+ if (connector->dp.psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED)
seq_printf(m, " (Early Transport)");
seq_printf(m, ", Panel Replay = %s", str_yes_no(psr->sink_panel_replay_support));
seq_printf(m, ", Panel Replay Selective Update = %s",
str_yes_no(psr->sink_panel_replay_su_support));
seq_printf(m, ", Panel Replay DSC support = %s",
panel_replay_dsc_support_str(psr->sink_panel_replay_dsc_support));
- if (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
+ if (connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)
seq_printf(m, " (Early Transport)");
seq_printf(m, "\n");
@@ -4177,7 +4183,8 @@ static void intel_psr_print_mode(struct intel_dp *intel_dp,
seq_printf(m, " %s\n", psr->no_psr_reason);
}
-static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
+static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp,
+ struct intel_connector *connector)
{
struct intel_display *display = to_intel_display(intel_dp);
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
@@ -4186,7 +4193,7 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
bool enabled;
u32 val, psr2_ctl;
- intel_psr_sink_capability(intel_dp, m);
+ intel_psr_sink_capability(intel_dp, connector, m);
if (!(psr->sink_support || psr->sink_panel_replay_support))
return 0;
@@ -4302,7 +4309,7 @@ static int i915_edp_psr_status_show(struct seq_file *m, void *data)
if (!intel_dp)
return -ENODEV;
- return intel_psr_status(m, intel_dp);
+ return intel_psr_status(m, intel_dp, intel_dp->attached_connector);
}
DEFINE_SHOW_ATTRIBUTE(i915_edp_psr_status);
@@ -4436,7 +4443,7 @@ static int i915_psr_status_show(struct seq_file *m, void *data)
struct intel_connector *connector = m->private;
struct intel_dp *intel_dp = intel_attached_dp(connector);
- return intel_psr_status(m, intel_dp);
+ return intel_psr_status(m, intel_dp, connector);
}
DEFINE_SHOW_ATTRIBUTE(i915_psr_status);
--
2.43.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 5/8] drm/i915/psr: Clear pr_dpcd as well on disconnect
2025-11-21 11:16 [PATCH 0/8] Move PSR/Panel Replay sink data into intel_connector Jouni Högander
` (3 preceding siblings ...)
2025-11-21 11:16 ` [PATCH 4/8] drm/i915/psr: Move pr_dpcd and psr_dpcd to intel_connector Jouni Högander
@ 2025-11-21 11:16 ` Jouni Högander
2025-12-01 10:53 ` Imre Deak
2025-11-21 11:16 ` [PATCH 6/8] drm/i915/psr: Move Panel Replay DSC sink support data to intel_connector Jouni Högander
` (6 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Jouni Högander @ 2025-11-21 11:16 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: Jouni Högander
Currently we are leaving pr_dpcd containing Panel Replay capability DPCD
registers as it is on disconnect. Clear it as well on disconnect.
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 62808cd35f5f2..7195c408d93ab 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6050,6 +6050,7 @@ intel_dp_detect(struct drm_connector *_connector,
if (status == connector_status_disconnected) {
intel_dp_test_reset(intel_dp);
memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd));
+ memset(connector->dp.pr_dpcd, 0, sizeof(connector->dp.pr_dpcd));
intel_dp->psr.sink_panel_replay_support = false;
intel_dp->psr.sink_panel_replay_su_support = false;
intel_dp->psr.sink_panel_replay_dsc_support =
--
2.43.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 6/8] drm/i915/psr: Move Panel Replay DSC sink support data to intel_connector
2025-11-21 11:16 [PATCH 0/8] Move PSR/Panel Replay sink data into intel_connector Jouni Högander
` (4 preceding siblings ...)
2025-11-21 11:16 ` [PATCH 5/8] drm/i915/psr: Clear pr_dpcd as well on disconnect Jouni Högander
@ 2025-11-21 11:16 ` Jouni Högander
2025-12-01 10:55 ` Imre Deak
2025-11-21 11:16 ` [PATCH 7/8] drm/i915/psr: Move sink PSR and Panel Replay booleans " Jouni Högander
` (5 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Jouni Högander @ 2025-11-21 11:16 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: Jouni Högander
As a preparation for MST Panel Replay we need to move Panel Replay sink
related data into intel_connector. Move Panel Replay DSC sink support data
as well into intel_connector.
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
.../gpu/drm/i915/display/intel_display_types.h | 15 ++++++++-------
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
drivers/gpu/drm/i915/display/intel_psr.c | 13 +++++++------
3 files changed, 16 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 8587d2c527f72..e1d47496ea4de 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -509,6 +509,12 @@ struct intel_hdcp {
bool force_hdcp14;
};
+enum intel_panel_replay_dsc_support {
+ INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED,
+ INTEL_DP_PANEL_REPLAY_DSC_FULL_FRAME_ONLY,
+ INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE,
+};
+
struct intel_connector {
struct drm_connector base;
/*
@@ -566,6 +572,8 @@ struct intel_connector {
} dsc_branch_caps;
struct {
+ enum intel_panel_replay_dsc_support dsc_support;
+
u16 su_w_granularity;
u16 su_y_granularity;
} panel_replay_caps;
@@ -967,12 +975,6 @@ struct intel_csc_matrix {
u16 postoff[3];
};
-enum intel_panel_replay_dsc_support {
- INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED,
- INTEL_DP_PANEL_REPLAY_DSC_FULL_FRAME_ONLY,
- INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE,
-};
-
struct scaler_filter_coeff {
u16 sign;
u16 exp;
@@ -1744,7 +1746,6 @@ struct intel_psr {
bool source_panel_replay_support;
bool sink_panel_replay_support;
bool sink_panel_replay_su_support;
- enum intel_panel_replay_dsc_support sink_panel_replay_dsc_support;
bool panel_replay_enabled;
u32 dc3co_exitline;
u32 dc3co_exit_delay;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 7195c408d93ab..d32f476c288c1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6053,7 +6053,7 @@ intel_dp_detect(struct drm_connector *_connector,
memset(connector->dp.pr_dpcd, 0, sizeof(connector->dp.pr_dpcd));
intel_dp->psr.sink_panel_replay_support = false;
intel_dp->psr.sink_panel_replay_su_support = false;
- intel_dp->psr.sink_panel_replay_dsc_support =
+ connector->dp.panel_replay_caps.dsc_support =
INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED;
intel_dp_mst_disconnect(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index b488be8c917dc..4bae39f745ea0 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -644,13 +644,13 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_conn
_panel_replay_compute_su_granularity(intel_dp, connector);
}
- intel_dp->psr.sink_panel_replay_dsc_support = compute_pr_dsc_support(connector);
+ connector->dp.panel_replay_caps.dsc_support = compute_pr_dsc_support(connector);
drm_dbg_kms(display->drm,
"Panel replay %sis supported by panel (in DSC mode: %s)\n",
intel_dp->psr.sink_panel_replay_su_support ?
"selective_update " : "",
- panel_replay_dsc_support_str(intel_dp->psr.sink_panel_replay_dsc_support));
+ panel_replay_dsc_support_str(connector->dp.panel_replay_caps.dsc_support));
}
static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
@@ -1659,7 +1659,7 @@ static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
goto unsupported;
if (intel_dsc_enabled_on_link(crtc_state) &&
- intel_dp->psr.sink_panel_replay_dsc_support !=
+ connector->dp.panel_replay_caps.dsc_support !=
INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE) {
drm_dbg_kms(display->drm,
"Selective update with Panel Replay not enabled because it's not supported with DSC\n");
@@ -1756,7 +1756,7 @@ static bool _panel_replay_compute_config(struct intel_dp *intel_dp,
}
if (intel_dsc_enabled_on_link(crtc_state) &&
- intel_dp->psr.sink_panel_replay_dsc_support ==
+ connector->dp.panel_replay_caps.dsc_support ==
INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED) {
drm_dbg_kms(display->drm,
"Panel Replay not enabled because it's not supported with DSC\n");
@@ -1841,6 +1841,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
struct drm_connector_state *conn_state)
{
struct intel_display *display = to_intel_display(intel_dp);
+ struct intel_connector *connector = to_intel_connector(conn_state->connector);
const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
if (!psr_global_enabled(intel_dp)) {
@@ -1872,7 +1873,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
}
/* Only used for state verification. */
- crtc_state->panel_replay_dsc_support = intel_dp->psr.sink_panel_replay_dsc_support;
+ crtc_state->panel_replay_dsc_support = connector->dp.panel_replay_caps.dsc_support;
crtc_state->has_panel_replay = _panel_replay_compute_config(intel_dp,
crtc_state,
conn_state);
@@ -4144,7 +4145,7 @@ static void intel_psr_sink_capability(struct intel_dp *intel_dp,
seq_printf(m, ", Panel Replay Selective Update = %s",
str_yes_no(psr->sink_panel_replay_su_support));
seq_printf(m, ", Panel Replay DSC support = %s",
- panel_replay_dsc_support_str(psr->sink_panel_replay_dsc_support));
+ panel_replay_dsc_support_str(connector->dp.panel_replay_caps.dsc_support));
if (connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)
seq_printf(m, " (Early Transport)");
--
2.43.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 7/8] drm/i915/psr: Move sink PSR and Panel Replay booleans to intel_connector
2025-11-21 11:16 [PATCH 0/8] Move PSR/Panel Replay sink data into intel_connector Jouni Högander
` (5 preceding siblings ...)
2025-11-21 11:16 ` [PATCH 6/8] drm/i915/psr: Move Panel Replay DSC sink support data to intel_connector Jouni Högander
@ 2025-11-21 11:16 ` Jouni Högander
2025-12-01 10:59 ` Imre Deak
2025-11-21 11:16 ` [PATCH 8/8] drm/i915/psr: Move sink_sync_latency " Jouni Högander
` (4 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Jouni Högander @ 2025-11-21 11:16 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: Jouni Högander
As a preparation for MST Panel Replay we need to move Panel Replay sink
related data into intel_connector. Move sink support booleans as well
into intel_connector. Generally this is more correct place for this data so
move PSR versions as well.
Still sink_support and sink_panel_replay_support are kept to keep CAN_PSR
and CAN_PANEL_REPLAY macros.
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
.../drm/i915/display/intel_display_types.h | 7 ++-
drivers/gpu/drm/i915/display/intel_dp.c | 4 +-
drivers/gpu/drm/i915/display/intel_psr.c | 44 +++++++++++--------
3 files changed, 33 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index e1d47496ea4de..04d21333130f9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -572,6 +572,8 @@ struct intel_connector {
} dsc_branch_caps;
struct {
+ bool support;
+ bool su_support;
enum intel_panel_replay_dsc_support dsc_support;
u16 su_w_granularity;
@@ -579,6 +581,9 @@ struct intel_connector {
} panel_replay_caps;
struct {
+ bool support;
+ bool su_support;
+
u16 su_w_granularity;
u16 su_y_granularity;
} psr_caps;
@@ -1729,7 +1734,6 @@ struct intel_psr {
bool active;
struct work_struct work;
unsigned int busy_frontbuffer_bits;
- bool sink_psr2_support;
bool link_standby;
bool sel_update_enabled;
bool psr2_sel_fetch_enabled;
@@ -1745,7 +1749,6 @@ struct intel_psr {
u16 su_y_granularity;
bool source_panel_replay_support;
bool sink_panel_replay_support;
- bool sink_panel_replay_su_support;
bool panel_replay_enabled;
u32 dc3co_exitline;
u32 dc3co_exit_delay;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index d32f476c288c1..2452302937c73 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6052,10 +6052,12 @@ intel_dp_detect(struct drm_connector *_connector,
memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd));
memset(connector->dp.pr_dpcd, 0, sizeof(connector->dp.pr_dpcd));
intel_dp->psr.sink_panel_replay_support = false;
- intel_dp->psr.sink_panel_replay_su_support = false;
+ connector->dp.panel_replay_caps.support = false;
+ connector->dp.panel_replay_caps.su_support = false;
connector->dp.panel_replay_caps.dsc_support =
INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED;
+
intel_dp_mst_disconnect(intel_dp);
intel_dp_tunnel_disconnect(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 4bae39f745ea0..e6268d692f89d 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -635,11 +635,12 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_conn
}
}
+ connector->dp.panel_replay_caps.support = true;
intel_dp->psr.sink_panel_replay_support = true;
if (connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
DP_PANEL_REPLAY_SU_SUPPORT) {
- intel_dp->psr.sink_panel_replay_su_support = true;
+ connector->dp.panel_replay_caps.su_support = true;
_panel_replay_compute_su_granularity(intel_dp, connector);
}
@@ -648,7 +649,7 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_conn
drm_dbg_kms(display->drm,
"Panel replay %sis supported by panel (in DSC mode: %s)\n",
- intel_dp->psr.sink_panel_replay_su_support ?
+ connector->dp.panel_replay_caps.su_support ?
"selective_update " : "",
panel_replay_dsc_support_str(connector->dp.panel_replay_caps.dsc_support));
}
@@ -681,7 +682,9 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *co
return;
}
+ connector->dp.psr_caps.support = true;
intel_dp->psr.sink_support = true;
+
intel_dp->psr.sink_sync_latency =
intel_dp_get_sink_sync_latency(intel_dp);
@@ -701,13 +704,13 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *co
* Y-coordinate requirement panels we would need to enable
* GTC first.
*/
- intel_dp->psr.sink_psr2_support = y_req &&
+ connector->dp.psr_caps.su_support = y_req &&
intel_alpm_aux_wake_supported(intel_dp);
drm_dbg_kms(display->drm, "PSR2 %ssupported\n",
- intel_dp->psr.sink_psr2_support ? "" : "not ");
+ connector->dp.psr_caps.su_support ? "" : "not ");
}
- if (intel_dp->psr.sink_psr2_support)
+ if (connector->dp.psr_caps.su_support)
_psr_compute_su_granularity(intel_dp, connector);
}
@@ -1522,14 +1525,16 @@ static bool alpm_config_valid(struct intel_dp *intel_dp,
}
static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state)
{
struct intel_display *display = to_intel_display(intel_dp);
+ struct intel_connector *connector = to_intel_connector(conn_state->connector);
int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
int psr_max_h = 0, psr_max_v = 0, max_bpp = 0;
- if (!intel_dp->psr.sink_psr2_support || display->params.enable_psr == 1)
+ if (!connector->dp.psr_caps.su_support || display->params.enable_psr == 1)
return false;
/* JSL and EHL only supports eDP 1.3 */
@@ -1642,7 +1647,8 @@ static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
goto unsupported;
}
- if (!crtc_state->has_panel_replay && !intel_psr2_config_valid(intel_dp, crtc_state))
+ if (!crtc_state->has_panel_replay && !intel_psr2_config_valid(intel_dp, crtc_state,
+ conn_state))
goto unsupported;
if (!_compute_psr2_sdp_prior_scanline_indication(intel_dp, crtc_state)) {
@@ -1655,7 +1661,7 @@ static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
if (DISPLAY_VER(display) < 14)
goto unsupported;
- if (!intel_dp->psr.sink_panel_replay_su_support)
+ if (!connector->dp.panel_replay_caps.su_support)
goto unsupported;
if (intel_dsc_enabled_on_link(crtc_state) &&
@@ -1744,6 +1750,9 @@ static bool _panel_replay_compute_config(struct intel_dp *intel_dp,
if (!CAN_PANEL_REPLAY(intel_dp))
return false;
+ if (!connector->dp.panel_replay_caps.support)
+ return false;
+
if (!panel_replay_global_enabled(intel_dp)) {
drm_dbg_kms(display->drm, "Panel Replay disabled by flag\n");
return false;
@@ -4128,22 +4137,19 @@ psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)
seq_printf(m, "Source PSR/PanelReplay status: %s [0x%08x]\n", status, val);
}
-static void intel_psr_sink_capability(struct intel_dp *intel_dp,
- struct intel_connector *connector,
+static void intel_psr_sink_capability(struct intel_connector *connector,
struct seq_file *m)
{
- struct intel_psr *psr = &intel_dp->psr;
-
seq_printf(m, "Sink support: PSR = %s",
- str_yes_no(psr->sink_support));
+ str_yes_no(connector->dp.psr_caps.support));
- if (psr->sink_support)
+ if (connector->dp.psr_caps.support)
seq_printf(m, " [0x%02x]", connector->dp.psr_dpcd[0]);
if (connector->dp.psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED)
seq_printf(m, " (Early Transport)");
- seq_printf(m, ", Panel Replay = %s", str_yes_no(psr->sink_panel_replay_support));
+ seq_printf(m, ", Panel Replay = %s", str_yes_no(connector->dp.panel_replay_caps.support));
seq_printf(m, ", Panel Replay Selective Update = %s",
- str_yes_no(psr->sink_panel_replay_su_support));
+ str_yes_no(connector->dp.panel_replay_caps.su_support));
seq_printf(m, ", Panel Replay DSC support = %s",
panel_replay_dsc_support_str(connector->dp.panel_replay_caps.dsc_support));
if (connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
@@ -4194,9 +4200,9 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp,
bool enabled;
u32 val, psr2_ctl;
- intel_psr_sink_capability(intel_dp, connector, m);
+ intel_psr_sink_capability(connector, m);
- if (!(psr->sink_support || psr->sink_panel_replay_support))
+ if (!(connector->dp.psr_caps.support || connector->dp.panel_replay_caps.support))
return 0;
wakeref = intel_display_rpm_get(display);
--
2.43.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 8/8] drm/i915/psr: Move sink_sync_latency to intel_connector
2025-11-21 11:16 [PATCH 0/8] Move PSR/Panel Replay sink data into intel_connector Jouni Högander
` (6 preceding siblings ...)
2025-11-21 11:16 ` [PATCH 7/8] drm/i915/psr: Move sink PSR and Panel Replay booleans " Jouni Högander
@ 2025-11-21 11:16 ` Jouni Högander
2025-12-01 11:03 ` Imre Deak
2025-11-24 19:59 ` ✗ CI.checkpatch: warning for Move PSR/Panel Replay sink data into intel_connector Patchwork
` (3 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Jouni Högander @ 2025-11-21 11:16 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: Jouni Högander
As everything else related to PSR and Panel Replay capabilities are moved
into intel_connector move sink_sync_latency as well.
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_types.h | 3 ++-
drivers/gpu/drm/i915/display/intel_psr.c | 8 ++++----
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 04d21333130f9..77e1948aef2ff 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -586,6 +586,8 @@ struct intel_connector {
u16 su_w_granularity;
u16 su_y_granularity;
+
+ u8 sync_latency;
} psr_caps;
} dp;
@@ -1740,7 +1742,6 @@ struct intel_psr {
bool psr2_sel_fetch_cff_enabled;
bool su_region_et_enabled;
bool req_psr2_sdp_prior_scanline;
- u8 sink_sync_latency;
ktime_t last_entry_attempt;
ktime_t last_exit;
bool sink_not_reliable;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index e6268d692f89d..bbd1b0e8beecb 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -685,8 +685,7 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *co
connector->dp.psr_caps.support = true;
intel_dp->psr.sink_support = true;
- intel_dp->psr.sink_sync_latency =
- intel_dp_get_sink_sync_latency(intel_dp);
+ connector->dp.psr_caps.sync_latency = intel_dp_get_sink_sync_latency(intel_dp);
if (DISPLAY_VER(display) >= 9 &&
connector->dp.psr_dpcd[0] >= DP_PSR2_WITH_Y_COORD_IS_SUPPORTED) {
@@ -911,7 +910,7 @@ static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
* off-by-one issue that HW has in some cases.
*/
idle_frames = max(6, connector->panel.vbt.psr.idle_frames);
- idle_frames = max(idle_frames, intel_dp->psr.sink_sync_latency + 1);
+ idle_frames = max(idle_frames, connector->dp.psr_caps.sync_latency + 1);
if (drm_WARN_ON(display->drm, idle_frames > 0xf))
idle_frames = 0xf;
@@ -1006,10 +1005,11 @@ static int psr2_block_count(struct intel_dp *intel_dp)
static u8 frames_before_su_entry(struct intel_dp *intel_dp)
{
+ struct intel_connector *connector = intel_dp->attached_connector;
u8 frames_before_su_entry;
frames_before_su_entry = max_t(u8,
- intel_dp->psr.sink_sync_latency + 1,
+ connector->dp.psr_caps.sync_latency + 1,
2);
/* Entry setup frames must be at least 1 less than frames before SU entry */
--
2.43.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH 3/8] drm/i915/psr: Compute Panel Replay/Adaptive coexistence behavior
2025-11-21 11:16 ` [PATCH 3/8] drm/i915/psr: Compute Panel Replay/Adaptive coexistence behavior Jouni Högander
@ 2025-11-21 11:24 ` Jani Nikula
2025-12-01 10:28 ` Imre Deak
1 sibling, 0 replies; 25+ messages in thread
From: Jani Nikula @ 2025-11-21 11:24 UTC (permalink / raw)
To: Jouni Högander, intel-gfx, intel-xe; +Cc: Jouni Högander
On Fri, 21 Nov 2025, Jouni Högander <jouni.hogander@intel.com> wrote:
> Currently we are checking Panel Replay capability DPCD register in
> intel_alpm.c and writing PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU
> and PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE in PR_ALPM_CTL
> register base on the informaion. Instead of directly accessing
> intel_dp->pr_dpcd compute the behavior during psr_compute_config and store
> it in intel_crtc_state.
>
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_alpm.c | 6 ++---
> .../drm/i915/display/intel_display_types.h | 2 ++
> drivers/gpu/drm/i915/display/intel_psr.c | 22 +++++++++++++++----
> 3 files changed, 22 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 6372f533f65b5..7ce8c674bb030 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -326,11 +326,9 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
> if (intel_dp->as_sdp_supported) {
> u32 pr_alpm_ctl = PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
>
> - if (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
> - DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP)
> + if (crtc_state->link_off_after_as_sdp_when_pr_active)
> pr_alpm_ctl |= PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU;
> - if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
> - DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR))
> + if (crtc_state->disable_as_sdp_when_pr_active)
> pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
>
> intel_de_write(display, PR_ALPM_CTL(display, cpu_transcoder),
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index f39d62aa99246..d8a222689a35b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1161,6 +1161,8 @@ struct intel_crtc_state {
> bool enable_psr2_su_region_et;
> bool req_psr2_sdp_prior_scanline;
> bool has_panel_replay;
> + bool link_off_after_as_sdp_when_pr_active;
> + bool disable_as_sdp_when_pr_active;
> bool wm_level_disabled;
> bool pkg_c_latency_used;
Side note, we really *really* should start adding more (anonymous)
sub-structs in intel_crtc_state to group things. This has gotten out of
hands.
> /* Only used for state verification. */
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 4c5883bed612b..9d2ba39423826 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1715,10 +1715,21 @@ static bool _psr_compute_config(struct intel_dp *intel_dp,
> return true;
> }
>
> -static bool
> -_panel_replay_compute_config(struct intel_dp *intel_dp,
> - struct intel_crtc_state *crtc_state,
> - const struct drm_connector_state *conn_state)
> +static bool compute_link_off_after_as_sdp_when_pr_active(struct intel_dp *intel_dp)
> +{
> + return (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
> + DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP);
> +}
> +
> +static bool compute_disable_as_sdp_when_pr_active(struct intel_dp *intel_dp)
> +{
> + return !(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
> + DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR);
> +}
> +
> +static bool _panel_replay_compute_config(struct intel_dp *intel_dp,
> + struct intel_crtc_state *crtc_state,
> + const struct drm_connector_state *conn_state)
> {
> struct intel_display *display = to_intel_display(intel_dp);
> struct intel_connector *connector =
> @@ -1747,6 +1758,9 @@ _panel_replay_compute_config(struct intel_dp *intel_dp,
> return false;
> }
>
> + crtc_state->link_off_after_as_sdp_when_pr_active = compute_link_off_after_as_sdp_when_pr_active(intel_dp);
> + crtc_state->disable_as_sdp_when_pr_active = compute_disable_as_sdp_when_pr_active(intel_dp);
> +
> if (!intel_dp_is_edp(intel_dp))
> return true;
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 25+ messages in thread
* ✗ CI.checkpatch: warning for Move PSR/Panel Replay sink data into intel_connector
2025-11-21 11:16 [PATCH 0/8] Move PSR/Panel Replay sink data into intel_connector Jouni Högander
` (7 preceding siblings ...)
2025-11-21 11:16 ` [PATCH 8/8] drm/i915/psr: Move sink_sync_latency " Jouni Högander
@ 2025-11-24 19:59 ` Patchwork
2025-11-24 20:00 ` ✓ CI.KUnit: success " Patchwork
` (2 subsequent siblings)
11 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2025-11-24 19:59 UTC (permalink / raw)
To: Jouni Högander; +Cc: intel-xe
== Series Details ==
Series: Move PSR/Panel Replay sink data into intel_connector
URL : https://patchwork.freedesktop.org/series/157898/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
2de9a3901bc28757c7906b454717b64e2a214021
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 9098fcd405a6a6bc63bc4da05f4f5268199a18c2
Author: Jouni Högander <jouni.hogander@intel.com>
Date: Fri Nov 21 13:16:55 2025 +0200
drm/i915/psr: Move sink_sync_latency to intel_connector
As everything else related to PSR and Panel Replay capabilities are moved
into intel_connector move sink_sync_latency as well.
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
+ /mt/dim checkpatch ed157ca0caebebe3af6d38ca0fb64a403c84ce77 drm-intel
09b49d4504d7 drm/i915/psr: Add panel granularity information into intel_connector
21cbbf29fe77 drm/i915/psr: Use SU granularity information available in intel_connector
d04d45981ba5 drm/i915/psr: Compute Panel Replay/Adaptive coexistence behavior
-:84: WARNING:LONG_LINE: line length of 114 exceeds 100 columns
#84: FILE: drivers/gpu/drm/i915/display/intel_psr.c:1755:
+ crtc_state->link_off_after_as_sdp_when_pr_active = compute_link_off_after_as_sdp_when_pr_active(intel_dp);
total: 0 errors, 1 warnings, 0 checks, 55 lines checked
c7d69b7185b6 drm/i915/psr: Move pr_dpcd and psr_dpcd to intel_connector
-:266: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#266: FILE: drivers/gpu/drm/i915/display/intel_psr.c:1760:
+ crtc_state->link_off_after_as_sdp_when_pr_active = compute_link_off_after_as_sdp_when_pr_active(connector);
-:267: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#267: FILE: drivers/gpu/drm/i915/display/intel_psr.c:1761:
+ crtc_state->disable_as_sdp_when_pr_active = compute_disable_as_sdp_when_pr_active(connector);
total: 0 errors, 2 warnings, 0 checks, 293 lines checked
8a1e72a6c657 drm/i915/psr: Clear pr_dpcd as well on disconnect
392b7c407c44 drm/i915/psr: Move Panel Replay DSC sink support data to intel_connector
6b8199822474 drm/i915/psr: Move sink PSR and Panel Replay booleans to intel_connector
-:73: CHECK:LINE_SPACING: Please don't use multiple blank lines
#73: FILE: drivers/gpu/drm/i915/display/intel_dp.c:6060:
+
total: 0 errors, 0 warnings, 1 checks, 172 lines checked
9098fcd405a6 drm/i915/psr: Move sink_sync_latency to intel_connector
^ permalink raw reply [flat|nested] 25+ messages in thread
* ✓ CI.KUnit: success for Move PSR/Panel Replay sink data into intel_connector
2025-11-21 11:16 [PATCH 0/8] Move PSR/Panel Replay sink data into intel_connector Jouni Högander
` (8 preceding siblings ...)
2025-11-24 19:59 ` ✗ CI.checkpatch: warning for Move PSR/Panel Replay sink data into intel_connector Patchwork
@ 2025-11-24 20:00 ` Patchwork
2025-11-24 20:47 ` ✓ Xe.CI.BAT: " Patchwork
2025-11-24 22:37 ` ✗ Xe.CI.Full: failure " Patchwork
11 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2025-11-24 20:00 UTC (permalink / raw)
To: Jouni Högander; +Cc: intel-xe
== Series Details ==
Series: Move PSR/Panel Replay sink data into intel_connector
URL : https://patchwork.freedesktop.org/series/157898/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[19:59:01] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[19:59:05] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[19:59:37] Starting KUnit Kernel (1/1)...
[19:59:37] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[19:59:37] ================== guc_buf (11 subtests) ===================
[19:59:37] [PASSED] test_smallest
[19:59:37] [PASSED] test_largest
[19:59:37] [PASSED] test_granular
[19:59:37] [PASSED] test_unique
[19:59:37] [PASSED] test_overlap
[19:59:37] [PASSED] test_reusable
[19:59:37] [PASSED] test_too_big
[19:59:37] [PASSED] test_flush
[19:59:37] [PASSED] test_lookup
[19:59:37] [PASSED] test_data
[19:59:37] [PASSED] test_class
[19:59:37] ===================== [PASSED] guc_buf =====================
[19:59:37] =================== guc_dbm (7 subtests) ===================
[19:59:37] [PASSED] test_empty
[19:59:37] [PASSED] test_default
[19:59:37] ======================== test_size ========================
[19:59:37] [PASSED] 4
[19:59:37] [PASSED] 8
[19:59:37] [PASSED] 32
[19:59:37] [PASSED] 256
[19:59:37] ==================== [PASSED] test_size ====================
[19:59:37] ======================= test_reuse ========================
[19:59:37] [PASSED] 4
[19:59:37] [PASSED] 8
[19:59:37] [PASSED] 32
[19:59:37] [PASSED] 256
[19:59:37] =================== [PASSED] test_reuse ====================
[19:59:37] =================== test_range_overlap ====================
[19:59:37] [PASSED] 4
[19:59:37] [PASSED] 8
[19:59:37] [PASSED] 32
[19:59:37] [PASSED] 256
[19:59:37] =============== [PASSED] test_range_overlap ================
[19:59:37] =================== test_range_compact ====================
[19:59:37] [PASSED] 4
[19:59:37] [PASSED] 8
[19:59:37] [PASSED] 32
[19:59:37] [PASSED] 256
[19:59:37] =============== [PASSED] test_range_compact ================
[19:59:37] ==================== test_range_spare =====================
[19:59:37] [PASSED] 4
[19:59:37] [PASSED] 8
[19:59:37] [PASSED] 32
[19:59:37] [PASSED] 256
[19:59:37] ================ [PASSED] test_range_spare =================
[19:59:37] ===================== [PASSED] guc_dbm =====================
[19:59:37] =================== guc_idm (6 subtests) ===================
[19:59:37] [PASSED] bad_init
[19:59:37] [PASSED] no_init
[19:59:37] [PASSED] init_fini
[19:59:37] [PASSED] check_used
[19:59:37] [PASSED] check_quota
[19:59:37] [PASSED] check_all
[19:59:37] ===================== [PASSED] guc_idm =====================
[19:59:37] ================== no_relay (3 subtests) ===================
[19:59:37] [PASSED] xe_drops_guc2pf_if_not_ready
[19:59:37] [PASSED] xe_drops_guc2vf_if_not_ready
[19:59:37] [PASSED] xe_rejects_send_if_not_ready
[19:59:37] ==================== [PASSED] no_relay =====================
[19:59:37] ================== pf_relay (14 subtests) ==================
[19:59:37] [PASSED] pf_rejects_guc2pf_too_short
[19:59:37] [PASSED] pf_rejects_guc2pf_too_long
[19:59:37] [PASSED] pf_rejects_guc2pf_no_payload
[19:59:37] [PASSED] pf_fails_no_payload
[19:59:37] [PASSED] pf_fails_bad_origin
[19:59:37] [PASSED] pf_fails_bad_type
[19:59:37] [PASSED] pf_txn_reports_error
[19:59:37] [PASSED] pf_txn_sends_pf2guc
[19:59:37] [PASSED] pf_sends_pf2guc
[19:59:37] [SKIPPED] pf_loopback_nop
[19:59:37] [SKIPPED] pf_loopback_echo
[19:59:37] [SKIPPED] pf_loopback_fail
[19:59:37] [SKIPPED] pf_loopback_busy
[19:59:37] [SKIPPED] pf_loopback_retry
[19:59:37] ==================== [PASSED] pf_relay =====================
[19:59:37] ================== vf_relay (3 subtests) ===================
[19:59:37] [PASSED] vf_rejects_guc2vf_too_short
[19:59:37] [PASSED] vf_rejects_guc2vf_too_long
[19:59:37] [PASSED] vf_rejects_guc2vf_no_payload
[19:59:37] ==================== [PASSED] vf_relay =====================
[19:59:37] ================ pf_gt_config (6 subtests) =================
[19:59:37] [PASSED] fair_contexts_1vf
[19:59:37] [PASSED] fair_doorbells_1vf
[19:59:37] [PASSED] fair_ggtt_1vf
[19:59:37] ====================== fair_contexts ======================
[19:59:37] [PASSED] 1 VF
[19:59:37] [PASSED] 2 VFs
[19:59:37] [PASSED] 3 VFs
[19:59:37] [PASSED] 4 VFs
[19:59:37] [PASSED] 5 VFs
[19:59:37] [PASSED] 6 VFs
[19:59:37] [PASSED] 7 VFs
[19:59:37] [PASSED] 8 VFs
[19:59:37] [PASSED] 9 VFs
[19:59:37] [PASSED] 10 VFs
[19:59:37] [PASSED] 11 VFs
[19:59:37] [PASSED] 12 VFs
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[19:59:37] [PASSED] 44 VFs
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[19:59:37] [PASSED] 47 VFs
[19:59:37] [PASSED] 48 VFs
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[19:59:37] [PASSED] 50 VFs
[19:59:37] [PASSED] 51 VFs
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[19:59:37] [PASSED] 54 VFs
[19:59:37] [PASSED] 55 VFs
[19:59:37] [PASSED] 56 VFs
[19:59:37] [PASSED] 57 VFs
[19:59:37] [PASSED] 58 VFs
[19:59:37] [PASSED] 59 VFs
[19:59:37] [PASSED] 60 VFs
[19:59:37] [PASSED] 61 VFs
[19:59:37] [PASSED] 62 VFs
[19:59:37] [PASSED] 63 VFs
[19:59:37] ================== [PASSED] fair_contexts ==================
[19:59:37] ===================== fair_doorbells ======================
[19:59:37] [PASSED] 1 VF
[19:59:37] [PASSED] 2 VFs
[19:59:37] [PASSED] 3 VFs
[19:59:37] [PASSED] 4 VFs
[19:59:37] [PASSED] 5 VFs
[19:59:37] [PASSED] 6 VFs
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[19:59:37] [PASSED] 8 VFs
[19:59:37] [PASSED] 9 VFs
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[19:59:37] [PASSED] 11 VFs
[19:59:37] [PASSED] 12 VFs
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[19:59:37] [PASSED] 14 VFs
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[19:59:37] [PASSED] 18 VFs
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[19:59:37] [PASSED] 22 VFs
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[19:59:37] [PASSED] 45 VFs
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[19:59:37] [PASSED] 47 VFs
[19:59:37] [PASSED] 48 VFs
[19:59:37] [PASSED] 49 VFs
[19:59:37] [PASSED] 50 VFs
[19:59:37] [PASSED] 51 VFs
[19:59:37] [PASSED] 52 VFs
[19:59:37] [PASSED] 53 VFs
[19:59:37] [PASSED] 54 VFs
[19:59:37] [PASSED] 55 VFs
[19:59:37] [PASSED] 56 VFs
[19:59:37] [PASSED] 57 VFs
[19:59:37] [PASSED] 58 VFs
[19:59:37] [PASSED] 59 VFs
[19:59:37] [PASSED] 60 VFs
[19:59:37] [PASSED] 61 VFs
[19:59:37] [PASSED] 62 VFs
[19:59:37] [PASSED] 63 VFs
[19:59:37] ================= [PASSED] fair_doorbells ==================
[19:59:37] ======================== fair_ggtt ========================
[19:59:37] [PASSED] 1 VF
[19:59:37] [PASSED] 2 VFs
[19:59:37] [PASSED] 3 VFs
[19:59:37] [PASSED] 4 VFs
[19:59:37] [PASSED] 5 VFs
[19:59:37] [PASSED] 6 VFs
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[19:59:37] [PASSED] 8 VFs
[19:59:37] [PASSED] 9 VFs
[19:59:37] [PASSED] 10 VFs
[19:59:37] [PASSED] 11 VFs
[19:59:37] [PASSED] 12 VFs
[19:59:37] [PASSED] 13 VFs
[19:59:37] [PASSED] 14 VFs
[19:59:37] [PASSED] 15 VFs
[19:59:37] [PASSED] 16 VFs
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[19:59:37] [PASSED] 19 VFs
[19:59:37] [PASSED] 20 VFs
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[19:59:37] [PASSED] 22 VFs
[19:59:37] [PASSED] 23 VFs
[19:59:37] [PASSED] 24 VFs
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[19:59:37] [PASSED] 26 VFs
[19:59:37] [PASSED] 27 VFs
[19:59:37] [PASSED] 28 VFs
[19:59:37] [PASSED] 29 VFs
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[19:59:37] [PASSED] 33 VFs
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[19:59:37] [PASSED] 36 VFs
[19:59:37] [PASSED] 37 VFs
[19:59:37] [PASSED] 38 VFs
[19:59:37] [PASSED] 39 VFs
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[19:59:37] [PASSED] 43 VFs
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[19:59:37] [PASSED] 46 VFs
[19:59:37] [PASSED] 47 VFs
[19:59:37] [PASSED] 48 VFs
[19:59:37] [PASSED] 49 VFs
[19:59:37] [PASSED] 50 VFs
[19:59:37] [PASSED] 51 VFs
[19:59:37] [PASSED] 52 VFs
[19:59:37] [PASSED] 53 VFs
[19:59:37] [PASSED] 54 VFs
[19:59:37] [PASSED] 55 VFs
[19:59:37] [PASSED] 56 VFs
[19:59:37] [PASSED] 57 VFs
[19:59:37] [PASSED] 58 VFs
[19:59:37] [PASSED] 59 VFs
[19:59:37] [PASSED] 60 VFs
[19:59:37] [PASSED] 61 VFs
[19:59:37] [PASSED] 62 VFs
[19:59:37] [PASSED] 63 VFs
[19:59:37] ==================== [PASSED] fair_ggtt ====================
[19:59:37] ================== [PASSED] pf_gt_config ===================
[19:59:37] ===================== lmtt (1 subtest) =====================
[19:59:37] ======================== test_ops =========================
[19:59:37] [PASSED] 2-level
[19:59:37] [PASSED] multi-level
[19:59:37] ==================== [PASSED] test_ops =====================
[19:59:37] ====================== [PASSED] lmtt =======================
[19:59:37] ================= pf_service (11 subtests) =================
[19:59:37] [PASSED] pf_negotiate_any
[19:59:37] [PASSED] pf_negotiate_base_match
[19:59:37] [PASSED] pf_negotiate_base_newer
[19:59:37] [PASSED] pf_negotiate_base_next
[19:59:37] [SKIPPED] pf_negotiate_base_older
[19:59:37] [PASSED] pf_negotiate_base_prev
[19:59:37] [PASSED] pf_negotiate_latest_match
[19:59:37] [PASSED] pf_negotiate_latest_newer
[19:59:37] [PASSED] pf_negotiate_latest_next
[19:59:37] [SKIPPED] pf_negotiate_latest_older
[19:59:37] [SKIPPED] pf_negotiate_latest_prev
[19:59:37] =================== [PASSED] pf_service ====================
[19:59:37] ================= xe_guc_g2g (2 subtests) ==================
[19:59:37] ============== xe_live_guc_g2g_kunit_default ==============
[19:59:37] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[19:59:37] ============== xe_live_guc_g2g_kunit_allmem ===============
[19:59:37] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[19:59:37] =================== [SKIPPED] xe_guc_g2g ===================
[19:59:37] =================== xe_mocs (2 subtests) ===================
[19:59:37] ================ xe_live_mocs_kernel_kunit ================
[19:59:37] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[19:59:37] ================ xe_live_mocs_reset_kunit =================
[19:59:37] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[19:59:37] ==================== [SKIPPED] xe_mocs =====================
[19:59:37] ================= xe_migrate (2 subtests) ==================
[19:59:37] ================= xe_migrate_sanity_kunit =================
[19:59:37] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[19:59:37] ================== xe_validate_ccs_kunit ==================
[19:59:37] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[19:59:37] =================== [SKIPPED] xe_migrate ===================
[19:59:37] ================== xe_dma_buf (1 subtest) ==================
[19:59:37] ==================== xe_dma_buf_kunit =====================
[19:59:37] ================ [SKIPPED] xe_dma_buf_kunit ================
[19:59:37] =================== [SKIPPED] xe_dma_buf ===================
[19:59:37] ================= xe_bo_shrink (1 subtest) =================
[19:59:37] =================== xe_bo_shrink_kunit ====================
[19:59:37] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[19:59:37] ================== [SKIPPED] xe_bo_shrink ==================
[19:59:37] ==================== xe_bo (2 subtests) ====================
[19:59:37] ================== xe_ccs_migrate_kunit ===================
[19:59:37] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[19:59:37] ==================== xe_bo_evict_kunit ====================
[19:59:37] =============== [SKIPPED] xe_bo_evict_kunit ================
[19:59:37] ===================== [SKIPPED] xe_bo ======================
[19:59:37] ==================== args (11 subtests) ====================
[19:59:37] [PASSED] count_args_test
[19:59:37] [PASSED] call_args_example
[19:59:37] [PASSED] call_args_test
[19:59:37] [PASSED] drop_first_arg_example
[19:59:37] [PASSED] drop_first_arg_test
[19:59:37] [PASSED] first_arg_example
[19:59:37] [PASSED] first_arg_test
[19:59:37] [PASSED] last_arg_example
[19:59:37] [PASSED] last_arg_test
[19:59:37] [PASSED] pick_arg_example
[19:59:37] [PASSED] sep_comma_example
[19:59:37] ====================== [PASSED] args =======================
[19:59:37] =================== xe_pci (3 subtests) ====================
[19:59:37] ==================== check_graphics_ip ====================
[19:59:37] [PASSED] 12.00 Xe_LP
[19:59:37] [PASSED] 12.10 Xe_LP+
[19:59:37] [PASSED] 12.55 Xe_HPG
[19:59:37] [PASSED] 12.60 Xe_HPC
[19:59:37] [PASSED] 12.70 Xe_LPG
[19:59:37] [PASSED] 12.71 Xe_LPG
[19:59:37] [PASSED] 12.74 Xe_LPG+
[19:59:37] [PASSED] 20.01 Xe2_HPG
[19:59:37] [PASSED] 20.02 Xe2_HPG
[19:59:37] [PASSED] 20.04 Xe2_LPG
[19:59:37] [PASSED] 30.00 Xe3_LPG
[19:59:37] [PASSED] 30.01 Xe3_LPG
[19:59:37] [PASSED] 30.03 Xe3_LPG
[19:59:37] [PASSED] 30.04 Xe3_LPG
[19:59:37] [PASSED] 30.05 Xe3_LPG
[19:59:37] [PASSED] 35.11 Xe3p_XPC
[19:59:37] ================ [PASSED] check_graphics_ip ================
[19:59:37] ===================== check_media_ip ======================
[19:59:37] [PASSED] 12.00 Xe_M
[19:59:37] [PASSED] 12.55 Xe_HPM
[19:59:37] [PASSED] 13.00 Xe_LPM+
[19:59:37] [PASSED] 13.01 Xe2_HPM
[19:59:37] [PASSED] 20.00 Xe2_LPM
[19:59:37] [PASSED] 30.00 Xe3_LPM
[19:59:37] [PASSED] 30.02 Xe3_LPM
[19:59:37] [PASSED] 35.00 Xe3p_LPM
[19:59:37] [PASSED] 35.03 Xe3p_HPM
[19:59:37] ================= [PASSED] check_media_ip ==================
[19:59:37] =================== check_platform_desc ===================
[19:59:37] [PASSED] 0x9A60 (TIGERLAKE)
[19:59:37] [PASSED] 0x9A68 (TIGERLAKE)
[19:59:37] [PASSED] 0x9A70 (TIGERLAKE)
[19:59:37] [PASSED] 0x9A40 (TIGERLAKE)
[19:59:37] [PASSED] 0x9A49 (TIGERLAKE)
[19:59:37] [PASSED] 0x9A59 (TIGERLAKE)
[19:59:37] [PASSED] 0x9A78 (TIGERLAKE)
[19:59:37] [PASSED] 0x9AC0 (TIGERLAKE)
[19:59:37] [PASSED] 0x9AC9 (TIGERLAKE)
[19:59:37] [PASSED] 0x9AD9 (TIGERLAKE)
[19:59:37] [PASSED] 0x9AF8 (TIGERLAKE)
[19:59:37] [PASSED] 0x4C80 (ROCKETLAKE)
[19:59:37] [PASSED] 0x4C8A (ROCKETLAKE)
[19:59:37] [PASSED] 0x4C8B (ROCKETLAKE)
[19:59:37] [PASSED] 0x4C8C (ROCKETLAKE)
[19:59:37] [PASSED] 0x4C90 (ROCKETLAKE)
[19:59:37] [PASSED] 0x4C9A (ROCKETLAKE)
[19:59:37] [PASSED] 0x4680 (ALDERLAKE_S)
[19:59:37] [PASSED] 0x4682 (ALDERLAKE_S)
[19:59:37] [PASSED] 0x4688 (ALDERLAKE_S)
[19:59:37] [PASSED] 0x468A (ALDERLAKE_S)
[19:59:37] [PASSED] 0x468B (ALDERLAKE_S)
[19:59:37] [PASSED] 0x4690 (ALDERLAKE_S)
[19:59:37] [PASSED] 0x4692 (ALDERLAKE_S)
[19:59:37] [PASSED] 0x4693 (ALDERLAKE_S)
[19:59:37] [PASSED] 0x46A0 (ALDERLAKE_P)
[19:59:37] [PASSED] 0x46A1 (ALDERLAKE_P)
[19:59:37] [PASSED] 0x46A2 (ALDERLAKE_P)
[19:59:37] [PASSED] 0x46A3 (ALDERLAKE_P)
[19:59:37] [PASSED] 0x46A6 (ALDERLAKE_P)
[19:59:37] [PASSED] 0x46A8 (ALDERLAKE_P)
[19:59:37] [PASSED] 0x46AA (ALDERLAKE_P)
[19:59:37] [PASSED] 0x462A (ALDERLAKE_P)
[19:59:37] [PASSED] 0x4626 (ALDERLAKE_P)
[19:59:37] [PASSED] 0x4628 (ALDERLAKE_P)
[19:59:37] [PASSED] 0x46B0 (ALDERLAKE_P)
stty: 'standard input': Inappropriate ioctl for device
[19:59:37] [PASSED] 0x46B1 (ALDERLAKE_P)
[19:59:37] [PASSED] 0x46B2 (ALDERLAKE_P)
[19:59:37] [PASSED] 0x46B3 (ALDERLAKE_P)
[19:59:37] [PASSED] 0x46C0 (ALDERLAKE_P)
[19:59:37] [PASSED] 0x46C1 (ALDERLAKE_P)
[19:59:37] [PASSED] 0x46C2 (ALDERLAKE_P)
[19:59:37] [PASSED] 0x46C3 (ALDERLAKE_P)
[19:59:37] [PASSED] 0x46D0 (ALDERLAKE_N)
[19:59:37] [PASSED] 0x46D1 (ALDERLAKE_N)
[19:59:37] [PASSED] 0x46D2 (ALDERLAKE_N)
[19:59:37] [PASSED] 0x46D3 (ALDERLAKE_N)
[19:59:37] [PASSED] 0x46D4 (ALDERLAKE_N)
[19:59:37] [PASSED] 0xA721 (ALDERLAKE_P)
[19:59:37] [PASSED] 0xA7A1 (ALDERLAKE_P)
[19:59:37] [PASSED] 0xA7A9 (ALDERLAKE_P)
[19:59:37] [PASSED] 0xA7AC (ALDERLAKE_P)
[19:59:37] [PASSED] 0xA7AD (ALDERLAKE_P)
[19:59:37] [PASSED] 0xA720 (ALDERLAKE_P)
[19:59:37] [PASSED] 0xA7A0 (ALDERLAKE_P)
[19:59:37] [PASSED] 0xA7A8 (ALDERLAKE_P)
[19:59:37] [PASSED] 0xA7AA (ALDERLAKE_P)
[19:59:37] [PASSED] 0xA7AB (ALDERLAKE_P)
[19:59:37] [PASSED] 0xA780 (ALDERLAKE_S)
[19:59:37] [PASSED] 0xA781 (ALDERLAKE_S)
[19:59:37] [PASSED] 0xA782 (ALDERLAKE_S)
[19:59:37] [PASSED] 0xA783 (ALDERLAKE_S)
[19:59:37] [PASSED] 0xA788 (ALDERLAKE_S)
[19:59:37] [PASSED] 0xA789 (ALDERLAKE_S)
[19:59:37] [PASSED] 0xA78A (ALDERLAKE_S)
[19:59:37] [PASSED] 0xA78B (ALDERLAKE_S)
[19:59:37] [PASSED] 0x4905 (DG1)
[19:59:37] [PASSED] 0x4906 (DG1)
[19:59:37] [PASSED] 0x4907 (DG1)
[19:59:37] [PASSED] 0x4908 (DG1)
[19:59:37] [PASSED] 0x4909 (DG1)
[19:59:37] [PASSED] 0x56C0 (DG2)
[19:59:37] [PASSED] 0x56C2 (DG2)
[19:59:37] [PASSED] 0x56C1 (DG2)
[19:59:37] [PASSED] 0x7D51 (METEORLAKE)
[19:59:37] [PASSED] 0x7DD1 (METEORLAKE)
[19:59:37] [PASSED] 0x7D41 (METEORLAKE)
[19:59:37] [PASSED] 0x7D67 (METEORLAKE)
[19:59:37] [PASSED] 0xB640 (METEORLAKE)
[19:59:37] [PASSED] 0x56A0 (DG2)
[19:59:37] [PASSED] 0x56A1 (DG2)
[19:59:37] [PASSED] 0x56A2 (DG2)
[19:59:37] [PASSED] 0x56BE (DG2)
[19:59:37] [PASSED] 0x56BF (DG2)
[19:59:37] [PASSED] 0x5690 (DG2)
[19:59:37] [PASSED] 0x5691 (DG2)
[19:59:37] [PASSED] 0x5692 (DG2)
[19:59:37] [PASSED] 0x56A5 (DG2)
[19:59:37] [PASSED] 0x56A6 (DG2)
[19:59:37] [PASSED] 0x56B0 (DG2)
[19:59:37] [PASSED] 0x56B1 (DG2)
[19:59:37] [PASSED] 0x56BA (DG2)
[19:59:37] [PASSED] 0x56BB (DG2)
[19:59:37] [PASSED] 0x56BC (DG2)
[19:59:37] [PASSED] 0x56BD (DG2)
[19:59:37] [PASSED] 0x5693 (DG2)
[19:59:37] [PASSED] 0x5694 (DG2)
[19:59:37] [PASSED] 0x5695 (DG2)
[19:59:37] [PASSED] 0x56A3 (DG2)
[19:59:37] [PASSED] 0x56A4 (DG2)
[19:59:37] [PASSED] 0x56B2 (DG2)
[19:59:37] [PASSED] 0x56B3 (DG2)
[19:59:37] [PASSED] 0x5696 (DG2)
[19:59:37] [PASSED] 0x5697 (DG2)
[19:59:37] [PASSED] 0xB69 (PVC)
[19:59:37] [PASSED] 0xB6E (PVC)
[19:59:37] [PASSED] 0xBD4 (PVC)
[19:59:37] [PASSED] 0xBD5 (PVC)
[19:59:37] [PASSED] 0xBD6 (PVC)
[19:59:37] [PASSED] 0xBD7 (PVC)
[19:59:37] [PASSED] 0xBD8 (PVC)
[19:59:37] [PASSED] 0xBD9 (PVC)
[19:59:37] [PASSED] 0xBDA (PVC)
[19:59:37] [PASSED] 0xBDB (PVC)
[19:59:37] [PASSED] 0xBE0 (PVC)
[19:59:37] [PASSED] 0xBE1 (PVC)
[19:59:37] [PASSED] 0xBE5 (PVC)
[19:59:37] [PASSED] 0x7D40 (METEORLAKE)
[19:59:37] [PASSED] 0x7D45 (METEORLAKE)
[19:59:37] [PASSED] 0x7D55 (METEORLAKE)
[19:59:37] [PASSED] 0x7D60 (METEORLAKE)
[19:59:37] [PASSED] 0x7DD5 (METEORLAKE)
[19:59:37] [PASSED] 0x6420 (LUNARLAKE)
[19:59:37] [PASSED] 0x64A0 (LUNARLAKE)
[19:59:37] [PASSED] 0x64B0 (LUNARLAKE)
[19:59:37] [PASSED] 0xE202 (BATTLEMAGE)
[19:59:37] [PASSED] 0xE209 (BATTLEMAGE)
[19:59:37] [PASSED] 0xE20B (BATTLEMAGE)
[19:59:37] [PASSED] 0xE20C (BATTLEMAGE)
[19:59:37] [PASSED] 0xE20D (BATTLEMAGE)
[19:59:37] [PASSED] 0xE210 (BATTLEMAGE)
[19:59:37] [PASSED] 0xE211 (BATTLEMAGE)
[19:59:37] [PASSED] 0xE212 (BATTLEMAGE)
[19:59:37] [PASSED] 0xE216 (BATTLEMAGE)
[19:59:37] [PASSED] 0xE220 (BATTLEMAGE)
[19:59:37] [PASSED] 0xE221 (BATTLEMAGE)
[19:59:37] [PASSED] 0xE222 (BATTLEMAGE)
[19:59:37] [PASSED] 0xE223 (BATTLEMAGE)
[19:59:37] [PASSED] 0xB080 (PANTHERLAKE)
[19:59:37] [PASSED] 0xB081 (PANTHERLAKE)
[19:59:37] [PASSED] 0xB082 (PANTHERLAKE)
[19:59:37] [PASSED] 0xB083 (PANTHERLAKE)
[19:59:37] [PASSED] 0xB084 (PANTHERLAKE)
[19:59:37] [PASSED] 0xB085 (PANTHERLAKE)
[19:59:37] [PASSED] 0xB086 (PANTHERLAKE)
[19:59:37] [PASSED] 0xB087 (PANTHERLAKE)
[19:59:37] [PASSED] 0xB08F (PANTHERLAKE)
[19:59:37] [PASSED] 0xB090 (PANTHERLAKE)
[19:59:37] [PASSED] 0xB0A0 (PANTHERLAKE)
[19:59:37] [PASSED] 0xB0B0 (PANTHERLAKE)
[19:59:37] [PASSED] 0xD740 (NOVALAKE_S)
[19:59:37] [PASSED] 0xD741 (NOVALAKE_S)
[19:59:37] [PASSED] 0xD742 (NOVALAKE_S)
[19:59:37] [PASSED] 0xD743 (NOVALAKE_S)
[19:59:37] [PASSED] 0xD744 (NOVALAKE_S)
[19:59:37] [PASSED] 0xD745 (NOVALAKE_S)
[19:59:37] [PASSED] 0x674C (CRESCENTISLAND)
[19:59:37] [PASSED] 0xFD80 (PANTHERLAKE)
[19:59:37] [PASSED] 0xFD81 (PANTHERLAKE)
[19:59:37] =============== [PASSED] check_platform_desc ===============
[19:59:37] ===================== [PASSED] xe_pci ======================
[19:59:37] =================== xe_rtp (2 subtests) ====================
[19:59:37] =============== xe_rtp_process_to_sr_tests ================
[19:59:37] [PASSED] coalesce-same-reg
[19:59:37] [PASSED] no-match-no-add
[19:59:37] [PASSED] match-or
[19:59:37] [PASSED] match-or-xfail
[19:59:37] [PASSED] no-match-no-add-multiple-rules
[19:59:37] [PASSED] two-regs-two-entries
[19:59:37] [PASSED] clr-one-set-other
[19:59:37] [PASSED] set-field
[19:59:37] [PASSED] conflict-duplicate
[19:59:37] [PASSED] conflict-not-disjoint
[19:59:37] [PASSED] conflict-reg-type
[19:59:37] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[19:59:37] ================== xe_rtp_process_tests ===================
[19:59:37] [PASSED] active1
[19:59:37] [PASSED] active2
[19:59:37] [PASSED] active-inactive
[19:59:37] [PASSED] inactive-active
[19:59:37] [PASSED] inactive-1st_or_active-inactive
[19:59:37] [PASSED] inactive-2nd_or_active-inactive
[19:59:37] [PASSED] inactive-last_or_active-inactive
[19:59:37] [PASSED] inactive-no_or_active-inactive
[19:59:37] ============== [PASSED] xe_rtp_process_tests ===============
[19:59:37] ===================== [PASSED] xe_rtp ======================
[19:59:37] ==================== xe_wa (1 subtest) =====================
[19:59:37] ======================== xe_wa_gt =========================
[19:59:37] [PASSED] TIGERLAKE B0
[19:59:37] [PASSED] DG1 A0
[19:59:37] [PASSED] DG1 B0
[19:59:37] [PASSED] ALDERLAKE_S A0
[19:59:37] [PASSED] ALDERLAKE_S B0
[19:59:37] [PASSED] ALDERLAKE_S C0
[19:59:37] [PASSED] ALDERLAKE_S D0
[19:59:37] [PASSED] ALDERLAKE_P A0
[19:59:37] [PASSED] ALDERLAKE_P B0
[19:59:37] [PASSED] ALDERLAKE_P C0
[19:59:37] [PASSED] ALDERLAKE_S RPLS D0
[19:59:37] [PASSED] ALDERLAKE_P RPLU E0
[19:59:37] [PASSED] DG2 G10 C0
[19:59:37] [PASSED] DG2 G11 B1
[19:59:37] [PASSED] DG2 G12 A1
[19:59:37] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[19:59:37] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[19:59:37] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[19:59:37] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[19:59:37] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[19:59:37] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[19:59:37] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[19:59:37] ==================== [PASSED] xe_wa_gt =====================
[19:59:37] ====================== [PASSED] xe_wa ======================
[19:59:37] ============================================================
[19:59:37] Testing complete. Ran 510 tests: passed: 492, skipped: 18
[19:59:37] Elapsed time: 35.887s total, 4.230s configuring, 31.190s building, 0.453s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[19:59:37] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[19:59:39] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[20:00:04] Starting KUnit Kernel (1/1)...
[20:00:04] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[20:00:04] ============ drm_test_pick_cmdline (2 subtests) ============
[20:00:04] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[20:00:04] =============== drm_test_pick_cmdline_named ===============
[20:00:04] [PASSED] NTSC
[20:00:04] [PASSED] NTSC-J
[20:00:04] [PASSED] PAL
[20:00:04] [PASSED] PAL-M
[20:00:04] =========== [PASSED] drm_test_pick_cmdline_named ===========
[20:00:04] ============== [PASSED] drm_test_pick_cmdline ==============
[20:00:04] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[20:00:04] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[20:00:04] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[20:00:04] =========== drm_validate_clone_mode (2 subtests) ===========
[20:00:04] ============== drm_test_check_in_clone_mode ===============
[20:00:04] [PASSED] in_clone_mode
[20:00:04] [PASSED] not_in_clone_mode
[20:00:04] ========== [PASSED] drm_test_check_in_clone_mode ===========
[20:00:04] =============== drm_test_check_valid_clones ===============
[20:00:04] [PASSED] not_in_clone_mode
[20:00:04] [PASSED] valid_clone
[20:00:04] [PASSED] invalid_clone
[20:00:04] =========== [PASSED] drm_test_check_valid_clones ===========
[20:00:04] ============= [PASSED] drm_validate_clone_mode =============
[20:00:04] ============= drm_validate_modeset (1 subtest) =============
[20:00:04] [PASSED] drm_test_check_connector_changed_modeset
[20:00:04] ============== [PASSED] drm_validate_modeset ===============
[20:00:04] ====== drm_test_bridge_get_current_state (2 subtests) ======
[20:00:04] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[20:00:04] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[20:00:04] ======== [PASSED] drm_test_bridge_get_current_state ========
[20:00:04] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[20:00:04] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[20:00:04] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[20:00:04] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[20:00:04] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[20:00:04] ============== drm_bridge_alloc (2 subtests) ===============
[20:00:04] [PASSED] drm_test_drm_bridge_alloc_basic
[20:00:04] [PASSED] drm_test_drm_bridge_alloc_get_put
[20:00:04] ================ [PASSED] drm_bridge_alloc =================
[20:00:04] ================== drm_buddy (8 subtests) ==================
[20:00:04] [PASSED] drm_test_buddy_alloc_limit
[20:00:04] [PASSED] drm_test_buddy_alloc_optimistic
[20:00:04] [PASSED] drm_test_buddy_alloc_pessimistic
[20:00:04] [PASSED] drm_test_buddy_alloc_pathological
[20:00:04] [PASSED] drm_test_buddy_alloc_contiguous
[20:00:04] [PASSED] drm_test_buddy_alloc_clear
[20:00:04] [PASSED] drm_test_buddy_alloc_range_bias
[20:00:04] [PASSED] drm_test_buddy_fragmentation_performance
[20:00:04] ==================== [PASSED] drm_buddy ====================
[20:00:04] ============= drm_cmdline_parser (40 subtests) =============
[20:00:04] [PASSED] drm_test_cmdline_force_d_only
[20:00:04] [PASSED] drm_test_cmdline_force_D_only_dvi
[20:00:04] [PASSED] drm_test_cmdline_force_D_only_hdmi
[20:00:04] [PASSED] drm_test_cmdline_force_D_only_not_digital
[20:00:04] [PASSED] drm_test_cmdline_force_e_only
[20:00:04] [PASSED] drm_test_cmdline_res
[20:00:04] [PASSED] drm_test_cmdline_res_vesa
[20:00:04] [PASSED] drm_test_cmdline_res_vesa_rblank
[20:00:04] [PASSED] drm_test_cmdline_res_rblank
[20:00:04] [PASSED] drm_test_cmdline_res_bpp
[20:00:04] [PASSED] drm_test_cmdline_res_refresh
[20:00:04] [PASSED] drm_test_cmdline_res_bpp_refresh
[20:00:04] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[20:00:04] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[20:00:04] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[20:00:04] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[20:00:04] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[20:00:04] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[20:00:04] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[20:00:04] [PASSED] drm_test_cmdline_res_margins_force_on
[20:00:04] [PASSED] drm_test_cmdline_res_vesa_margins
[20:00:04] [PASSED] drm_test_cmdline_name
[20:00:04] [PASSED] drm_test_cmdline_name_bpp
[20:00:04] [PASSED] drm_test_cmdline_name_option
[20:00:04] [PASSED] drm_test_cmdline_name_bpp_option
[20:00:04] [PASSED] drm_test_cmdline_rotate_0
[20:00:04] [PASSED] drm_test_cmdline_rotate_90
[20:00:04] [PASSED] drm_test_cmdline_rotate_180
[20:00:04] [PASSED] drm_test_cmdline_rotate_270
[20:00:04] [PASSED] drm_test_cmdline_hmirror
[20:00:04] [PASSED] drm_test_cmdline_vmirror
[20:00:04] [PASSED] drm_test_cmdline_margin_options
[20:00:04] [PASSED] drm_test_cmdline_multiple_options
[20:00:04] [PASSED] drm_test_cmdline_bpp_extra_and_option
[20:00:04] [PASSED] drm_test_cmdline_extra_and_option
[20:00:04] [PASSED] drm_test_cmdline_freestanding_options
[20:00:04] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[20:00:04] [PASSED] drm_test_cmdline_panel_orientation
[20:00:04] ================ drm_test_cmdline_invalid =================
[20:00:04] [PASSED] margin_only
[20:00:04] [PASSED] interlace_only
[20:00:04] [PASSED] res_missing_x
[20:00:04] [PASSED] res_missing_y
[20:00:04] [PASSED] res_bad_y
[20:00:04] [PASSED] res_missing_y_bpp
[20:00:04] [PASSED] res_bad_bpp
[20:00:04] [PASSED] res_bad_refresh
[20:00:04] [PASSED] res_bpp_refresh_force_on_off
[20:00:04] [PASSED] res_invalid_mode
[20:00:04] [PASSED] res_bpp_wrong_place_mode
[20:00:04] [PASSED] name_bpp_refresh
[20:00:04] [PASSED] name_refresh
[20:00:04] [PASSED] name_refresh_wrong_mode
[20:00:04] [PASSED] name_refresh_invalid_mode
[20:00:04] [PASSED] rotate_multiple
[20:00:04] [PASSED] rotate_invalid_val
[20:00:04] [PASSED] rotate_truncated
[20:00:04] [PASSED] invalid_option
[20:00:04] [PASSED] invalid_tv_option
[20:00:04] [PASSED] truncated_tv_option
[20:00:04] ============ [PASSED] drm_test_cmdline_invalid =============
[20:00:04] =============== drm_test_cmdline_tv_options ===============
[20:00:04] [PASSED] NTSC
[20:00:04] [PASSED] NTSC_443
[20:00:04] [PASSED] NTSC_J
[20:00:04] [PASSED] PAL
[20:00:04] [PASSED] PAL_M
[20:00:04] [PASSED] PAL_N
[20:00:04] [PASSED] SECAM
[20:00:04] [PASSED] MONO_525
[20:00:04] [PASSED] MONO_625
[20:00:04] =========== [PASSED] drm_test_cmdline_tv_options ===========
[20:00:04] =============== [PASSED] drm_cmdline_parser ================
[20:00:04] ========== drmm_connector_hdmi_init (20 subtests) ==========
[20:00:04] [PASSED] drm_test_connector_hdmi_init_valid
[20:00:04] [PASSED] drm_test_connector_hdmi_init_bpc_8
[20:00:04] [PASSED] drm_test_connector_hdmi_init_bpc_10
[20:00:04] [PASSED] drm_test_connector_hdmi_init_bpc_12
[20:00:04] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[20:00:04] [PASSED] drm_test_connector_hdmi_init_bpc_null
[20:00:04] [PASSED] drm_test_connector_hdmi_init_formats_empty
[20:00:04] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[20:00:04] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[20:00:04] [PASSED] supported_formats=0x9 yuv420_allowed=1
[20:00:04] [PASSED] supported_formats=0x9 yuv420_allowed=0
[20:00:04] [PASSED] supported_formats=0x3 yuv420_allowed=1
[20:00:04] [PASSED] supported_formats=0x3 yuv420_allowed=0
[20:00:04] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[20:00:04] [PASSED] drm_test_connector_hdmi_init_null_ddc
[20:00:04] [PASSED] drm_test_connector_hdmi_init_null_product
[20:00:04] [PASSED] drm_test_connector_hdmi_init_null_vendor
[20:00:04] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[20:00:04] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[20:00:04] [PASSED] drm_test_connector_hdmi_init_product_valid
[20:00:04] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[20:00:04] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[20:00:04] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[20:00:04] ========= drm_test_connector_hdmi_init_type_valid =========
[20:00:04] [PASSED] HDMI-A
[20:00:04] [PASSED] HDMI-B
[20:00:04] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[20:00:04] ======== drm_test_connector_hdmi_init_type_invalid ========
[20:00:04] [PASSED] Unknown
[20:00:04] [PASSED] VGA
[20:00:04] [PASSED] DVI-I
[20:00:04] [PASSED] DVI-D
[20:00:04] [PASSED] DVI-A
[20:00:04] [PASSED] Composite
[20:00:04] [PASSED] SVIDEO
[20:00:04] [PASSED] LVDS
[20:00:04] [PASSED] Component
[20:00:04] [PASSED] DIN
[20:00:04] [PASSED] DP
[20:00:04] [PASSED] TV
[20:00:04] [PASSED] eDP
[20:00:04] [PASSED] Virtual
[20:00:04] [PASSED] DSI
[20:00:04] [PASSED] DPI
[20:00:04] [PASSED] Writeback
[20:00:04] [PASSED] SPI
[20:00:04] [PASSED] USB
[20:00:04] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[20:00:04] ============ [PASSED] drmm_connector_hdmi_init =============
[20:00:04] ============= drmm_connector_init (3 subtests) =============
[20:00:04] [PASSED] drm_test_drmm_connector_init
[20:00:04] [PASSED] drm_test_drmm_connector_init_null_ddc
[20:00:04] ========= drm_test_drmm_connector_init_type_valid =========
[20:00:04] [PASSED] Unknown
[20:00:04] [PASSED] VGA
[20:00:04] [PASSED] DVI-I
[20:00:04] [PASSED] DVI-D
[20:00:04] [PASSED] DVI-A
[20:00:04] [PASSED] Composite
[20:00:04] [PASSED] SVIDEO
[20:00:04] [PASSED] LVDS
[20:00:04] [PASSED] Component
[20:00:04] [PASSED] DIN
[20:00:04] [PASSED] DP
[20:00:04] [PASSED] HDMI-A
[20:00:04] [PASSED] HDMI-B
[20:00:04] [PASSED] TV
[20:00:04] [PASSED] eDP
[20:00:04] [PASSED] Virtual
[20:00:04] [PASSED] DSI
[20:00:04] [PASSED] DPI
[20:00:04] [PASSED] Writeback
[20:00:04] [PASSED] SPI
[20:00:04] [PASSED] USB
[20:00:04] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[20:00:04] =============== [PASSED] drmm_connector_init ===============
[20:00:04] ========= drm_connector_dynamic_init (6 subtests) ==========
[20:00:04] [PASSED] drm_test_drm_connector_dynamic_init
[20:00:04] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[20:00:04] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[20:00:04] [PASSED] drm_test_drm_connector_dynamic_init_properties
[20:00:04] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[20:00:04] [PASSED] Unknown
[20:00:04] [PASSED] VGA
[20:00:04] [PASSED] DVI-I
[20:00:04] [PASSED] DVI-D
[20:00:04] [PASSED] DVI-A
[20:00:04] [PASSED] Composite
[20:00:04] [PASSED] SVIDEO
[20:00:04] [PASSED] LVDS
[20:00:04] [PASSED] Component
[20:00:04] [PASSED] DIN
[20:00:04] [PASSED] DP
[20:00:04] [PASSED] HDMI-A
[20:00:04] [PASSED] HDMI-B
[20:00:04] [PASSED] TV
[20:00:04] [PASSED] eDP
[20:00:04] [PASSED] Virtual
[20:00:04] [PASSED] DSI
[20:00:04] [PASSED] DPI
[20:00:04] [PASSED] Writeback
[20:00:04] [PASSED] SPI
[20:00:04] [PASSED] USB
[20:00:04] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[20:00:04] ======== drm_test_drm_connector_dynamic_init_name =========
[20:00:04] [PASSED] Unknown
[20:00:04] [PASSED] VGA
[20:00:04] [PASSED] DVI-I
[20:00:04] [PASSED] DVI-D
[20:00:04] [PASSED] DVI-A
[20:00:04] [PASSED] Composite
[20:00:04] [PASSED] SVIDEO
[20:00:04] [PASSED] LVDS
[20:00:04] [PASSED] Component
[20:00:04] [PASSED] DIN
[20:00:04] [PASSED] DP
[20:00:04] [PASSED] HDMI-A
[20:00:04] [PASSED] HDMI-B
[20:00:04] [PASSED] TV
[20:00:04] [PASSED] eDP
[20:00:04] [PASSED] Virtual
[20:00:04] [PASSED] DSI
[20:00:04] [PASSED] DPI
[20:00:04] [PASSED] Writeback
[20:00:04] [PASSED] SPI
[20:00:04] [PASSED] USB
[20:00:04] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[20:00:04] =========== [PASSED] drm_connector_dynamic_init ============
[20:00:04] ==== drm_connector_dynamic_register_early (4 subtests) =====
[20:00:04] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[20:00:04] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[20:00:04] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[20:00:04] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[20:00:04] ====== [PASSED] drm_connector_dynamic_register_early =======
[20:00:04] ======= drm_connector_dynamic_register (7 subtests) ========
[20:00:04] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[20:00:04] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[20:00:04] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[20:00:04] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[20:00:04] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[20:00:04] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[20:00:04] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[20:00:04] ========= [PASSED] drm_connector_dynamic_register ==========
[20:00:04] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[20:00:04] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[20:00:04] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[20:00:04] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[20:00:04] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[20:00:04] ========== drm_test_get_tv_mode_from_name_valid ===========
[20:00:04] [PASSED] NTSC
[20:00:04] [PASSED] NTSC-443
[20:00:04] [PASSED] NTSC-J
[20:00:04] [PASSED] PAL
[20:00:04] [PASSED] PAL-M
[20:00:04] [PASSED] PAL-N
[20:00:04] [PASSED] SECAM
[20:00:04] [PASSED] Mono
[20:00:04] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[20:00:04] [PASSED] drm_test_get_tv_mode_from_name_truncated
[20:00:04] ============ [PASSED] drm_get_tv_mode_from_name ============
[20:00:04] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[20:00:04] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[20:00:04] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[20:00:04] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[20:00:04] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[20:00:04] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[20:00:04] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[20:00:04] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[20:00:04] [PASSED] VIC 96
[20:00:04] [PASSED] VIC 97
[20:00:04] [PASSED] VIC 101
[20:00:04] [PASSED] VIC 102
[20:00:04] [PASSED] VIC 106
[20:00:04] [PASSED] VIC 107
[20:00:04] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[20:00:04] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[20:00:04] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[20:00:04] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[20:00:04] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[20:00:04] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[20:00:04] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[20:00:04] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[20:00:04] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[20:00:04] [PASSED] Automatic
[20:00:04] [PASSED] Full
[20:00:04] [PASSED] Limited 16:235
[20:00:04] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[20:00:04] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[20:00:04] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[20:00:04] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[20:00:04] === drm_test_drm_hdmi_connector_get_output_format_name ====
[20:00:04] [PASSED] RGB
[20:00:04] [PASSED] YUV 4:2:0
[20:00:04] [PASSED] YUV 4:2:2
[20:00:04] [PASSED] YUV 4:4:4
[20:00:04] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[20:00:04] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[20:00:04] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[20:00:04] ============= drm_damage_helper (21 subtests) ==============
[20:00:04] [PASSED] drm_test_damage_iter_no_damage
[20:00:04] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[20:00:04] [PASSED] drm_test_damage_iter_no_damage_src_moved
[20:00:04] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[20:00:04] [PASSED] drm_test_damage_iter_no_damage_not_visible
[20:00:04] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[20:00:04] [PASSED] drm_test_damage_iter_no_damage_no_fb
[20:00:04] [PASSED] drm_test_damage_iter_simple_damage
[20:00:04] [PASSED] drm_test_damage_iter_single_damage
[20:00:04] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[20:00:04] [PASSED] drm_test_damage_iter_single_damage_outside_src
[20:00:04] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[20:00:04] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[20:00:04] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[20:00:04] [PASSED] drm_test_damage_iter_single_damage_src_moved
[20:00:04] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[20:00:04] [PASSED] drm_test_damage_iter_damage
[20:00:04] [PASSED] drm_test_damage_iter_damage_one_intersect
[20:00:04] [PASSED] drm_test_damage_iter_damage_one_outside
[20:00:04] [PASSED] drm_test_damage_iter_damage_src_moved
[20:00:04] [PASSED] drm_test_damage_iter_damage_not_visible
[20:00:04] ================ [PASSED] drm_damage_helper ================
[20:00:04] ============== drm_dp_mst_helper (3 subtests) ==============
[20:00:04] ============== drm_test_dp_mst_calc_pbn_mode ==============
[20:00:04] [PASSED] Clock 154000 BPP 30 DSC disabled
[20:00:04] [PASSED] Clock 234000 BPP 30 DSC disabled
[20:00:04] [PASSED] Clock 297000 BPP 24 DSC disabled
[20:00:04] [PASSED] Clock 332880 BPP 24 DSC enabled
[20:00:04] [PASSED] Clock 324540 BPP 24 DSC enabled
[20:00:04] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[20:00:04] ============== drm_test_dp_mst_calc_pbn_div ===============
[20:00:04] [PASSED] Link rate 2000000 lane count 4
[20:00:04] [PASSED] Link rate 2000000 lane count 2
[20:00:04] [PASSED] Link rate 2000000 lane count 1
[20:00:04] [PASSED] Link rate 1350000 lane count 4
[20:00:04] [PASSED] Link rate 1350000 lane count 2
[20:00:04] [PASSED] Link rate 1350000 lane count 1
[20:00:04] [PASSED] Link rate 1000000 lane count 4
[20:00:04] [PASSED] Link rate 1000000 lane count 2
[20:00:04] [PASSED] Link rate 1000000 lane count 1
[20:00:04] [PASSED] Link rate 810000 lane count 4
[20:00:04] [PASSED] Link rate 810000 lane count 2
[20:00:04] [PASSED] Link rate 810000 lane count 1
[20:00:04] [PASSED] Link rate 540000 lane count 4
[20:00:04] [PASSED] Link rate 540000 lane count 2
[20:00:04] [PASSED] Link rate 540000 lane count 1
[20:00:04] [PASSED] Link rate 270000 lane count 4
[20:00:04] [PASSED] Link rate 270000 lane count 2
[20:00:04] [PASSED] Link rate 270000 lane count 1
[20:00:04] [PASSED] Link rate 162000 lane count 4
[20:00:04] [PASSED] Link rate 162000 lane count 2
[20:00:04] [PASSED] Link rate 162000 lane count 1
[20:00:04] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[20:00:04] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[20:00:04] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[20:00:04] [PASSED] DP_POWER_UP_PHY with port number
[20:00:04] [PASSED] DP_POWER_DOWN_PHY with port number
[20:00:04] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[20:00:04] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[20:00:04] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[20:00:04] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[20:00:04] [PASSED] DP_QUERY_PAYLOAD with port number
[20:00:04] [PASSED] DP_QUERY_PAYLOAD with VCPI
[20:00:04] [PASSED] DP_REMOTE_DPCD_READ with port number
[20:00:04] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[20:00:04] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[20:00:04] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[20:00:04] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[20:00:04] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[20:00:04] [PASSED] DP_REMOTE_I2C_READ with port number
[20:00:04] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[20:00:04] [PASSED] DP_REMOTE_I2C_READ with transactions array
[20:00:04] [PASSED] DP_REMOTE_I2C_WRITE with port number
[20:00:04] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[20:00:04] [PASSED] DP_REMOTE_I2C_WRITE with data array
[20:00:04] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[20:00:04] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[20:00:04] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[20:00:04] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[20:00:04] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[20:00:04] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[20:00:04] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[20:00:04] ================ [PASSED] drm_dp_mst_helper ================
[20:00:04] ================== drm_exec (7 subtests) ===================
[20:00:04] [PASSED] sanitycheck
[20:00:04] [PASSED] test_lock
[20:00:04] [PASSED] test_lock_unlock
[20:00:04] [PASSED] test_duplicates
[20:00:04] [PASSED] test_prepare
[20:00:04] [PASSED] test_prepare_array
[20:00:04] [PASSED] test_multiple_loops
[20:00:04] ==================== [PASSED] drm_exec =====================
[20:00:04] =========== drm_format_helper_test (17 subtests) ===========
[20:00:04] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[20:00:04] [PASSED] single_pixel_source_buffer
[20:00:04] [PASSED] single_pixel_clip_rectangle
[20:00:04] [PASSED] well_known_colors
[20:00:04] [PASSED] destination_pitch
[20:00:04] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[20:00:04] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[20:00:04] [PASSED] single_pixel_source_buffer
[20:00:04] [PASSED] single_pixel_clip_rectangle
[20:00:04] [PASSED] well_known_colors
[20:00:04] [PASSED] destination_pitch
[20:00:04] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[20:00:04] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[20:00:04] [PASSED] single_pixel_source_buffer
[20:00:04] [PASSED] single_pixel_clip_rectangle
[20:00:04] [PASSED] well_known_colors
[20:00:04] [PASSED] destination_pitch
[20:00:04] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[20:00:04] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[20:00:04] [PASSED] single_pixel_source_buffer
[20:00:04] [PASSED] single_pixel_clip_rectangle
[20:00:04] [PASSED] well_known_colors
[20:00:04] [PASSED] destination_pitch
[20:00:04] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[20:00:04] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[20:00:04] [PASSED] single_pixel_source_buffer
[20:00:04] [PASSED] single_pixel_clip_rectangle
[20:00:04] [PASSED] well_known_colors
[20:00:04] [PASSED] destination_pitch
[20:00:04] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[20:00:04] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[20:00:04] [PASSED] single_pixel_source_buffer
[20:00:04] [PASSED] single_pixel_clip_rectangle
[20:00:04] [PASSED] well_known_colors
[20:00:04] [PASSED] destination_pitch
[20:00:04] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[20:00:04] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[20:00:04] [PASSED] single_pixel_source_buffer
[20:00:04] [PASSED] single_pixel_clip_rectangle
[20:00:04] [PASSED] well_known_colors
[20:00:04] [PASSED] destination_pitch
[20:00:04] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[20:00:04] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[20:00:04] [PASSED] single_pixel_source_buffer
[20:00:04] [PASSED] single_pixel_clip_rectangle
[20:00:04] [PASSED] well_known_colors
[20:00:04] [PASSED] destination_pitch
[20:00:04] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[20:00:04] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[20:00:04] [PASSED] single_pixel_source_buffer
[20:00:04] [PASSED] single_pixel_clip_rectangle
[20:00:04] [PASSED] well_known_colors
[20:00:04] [PASSED] destination_pitch
[20:00:04] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[20:00:04] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[20:00:04] [PASSED] single_pixel_source_buffer
[20:00:04] [PASSED] single_pixel_clip_rectangle
[20:00:04] [PASSED] well_known_colors
[20:00:04] [PASSED] destination_pitch
[20:00:04] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[20:00:04] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[20:00:04] [PASSED] single_pixel_source_buffer
[20:00:04] [PASSED] single_pixel_clip_rectangle
[20:00:04] [PASSED] well_known_colors
[20:00:04] [PASSED] destination_pitch
[20:00:04] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[20:00:04] ============== drm_test_fb_xrgb8888_to_mono ===============
[20:00:04] [PASSED] single_pixel_source_buffer
[20:00:04] [PASSED] single_pixel_clip_rectangle
[20:00:04] [PASSED] well_known_colors
[20:00:04] [PASSED] destination_pitch
[20:00:04] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[20:00:04] ==================== drm_test_fb_swab =====================
[20:00:04] [PASSED] single_pixel_source_buffer
[20:00:04] [PASSED] single_pixel_clip_rectangle
[20:00:04] [PASSED] well_known_colors
[20:00:04] [PASSED] destination_pitch
[20:00:04] ================ [PASSED] drm_test_fb_swab =================
[20:00:04] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[20:00:04] [PASSED] single_pixel_source_buffer
[20:00:04] [PASSED] single_pixel_clip_rectangle
[20:00:04] [PASSED] well_known_colors
[20:00:04] [PASSED] destination_pitch
[20:00:04] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[20:00:04] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[20:00:04] [PASSED] single_pixel_source_buffer
[20:00:04] [PASSED] single_pixel_clip_rectangle
[20:00:04] [PASSED] well_known_colors
[20:00:04] [PASSED] destination_pitch
[20:00:04] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[20:00:04] ================= drm_test_fb_clip_offset =================
[20:00:04] [PASSED] pass through
[20:00:04] [PASSED] horizontal offset
[20:00:04] [PASSED] vertical offset
[20:00:04] [PASSED] horizontal and vertical offset
[20:00:04] [PASSED] horizontal offset (custom pitch)
[20:00:04] [PASSED] vertical offset (custom pitch)
[20:00:04] [PASSED] horizontal and vertical offset (custom pitch)
[20:00:04] ============= [PASSED] drm_test_fb_clip_offset =============
[20:00:04] =================== drm_test_fb_memcpy ====================
[20:00:04] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[20:00:04] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[20:00:04] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[20:00:04] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[20:00:04] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[20:00:04] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[20:00:04] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[20:00:04] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[20:00:04] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[20:00:04] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[20:00:04] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[20:00:04] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[20:00:04] =============== [PASSED] drm_test_fb_memcpy ================
[20:00:04] ============= [PASSED] drm_format_helper_test ==============
[20:00:04] ================= drm_format (18 subtests) =================
[20:00:04] [PASSED] drm_test_format_block_width_invalid
[20:00:04] [PASSED] drm_test_format_block_width_one_plane
[20:00:04] [PASSED] drm_test_format_block_width_two_plane
[20:00:04] [PASSED] drm_test_format_block_width_three_plane
[20:00:04] [PASSED] drm_test_format_block_width_tiled
[20:00:04] [PASSED] drm_test_format_block_height_invalid
[20:00:04] [PASSED] drm_test_format_block_height_one_plane
[20:00:04] [PASSED] drm_test_format_block_height_two_plane
[20:00:04] [PASSED] drm_test_format_block_height_three_plane
[20:00:04] [PASSED] drm_test_format_block_height_tiled
[20:00:04] [PASSED] drm_test_format_min_pitch_invalid
[20:00:04] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[20:00:04] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[20:00:04] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[20:00:04] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[20:00:04] [PASSED] drm_test_format_min_pitch_two_plane
[20:00:04] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[20:00:04] [PASSED] drm_test_format_min_pitch_tiled
[20:00:04] =================== [PASSED] drm_format ====================
[20:00:04] ============== drm_framebuffer (10 subtests) ===============
[20:00:04] ========== drm_test_framebuffer_check_src_coords ==========
[20:00:04] [PASSED] Success: source fits into fb
[20:00:04] [PASSED] Fail: overflowing fb with x-axis coordinate
[20:00:04] [PASSED] Fail: overflowing fb with y-axis coordinate
[20:00:04] [PASSED] Fail: overflowing fb with source width
[20:00:04] [PASSED] Fail: overflowing fb with source height
[20:00:04] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[20:00:04] [PASSED] drm_test_framebuffer_cleanup
[20:00:04] =============== drm_test_framebuffer_create ===============
[20:00:04] [PASSED] ABGR8888 normal sizes
[20:00:04] [PASSED] ABGR8888 max sizes
[20:00:04] [PASSED] ABGR8888 pitch greater than min required
[20:00:04] [PASSED] ABGR8888 pitch less than min required
[20:00:04] [PASSED] ABGR8888 Invalid width
[20:00:04] [PASSED] ABGR8888 Invalid buffer handle
[20:00:04] [PASSED] No pixel format
[20:00:04] [PASSED] ABGR8888 Width 0
[20:00:04] [PASSED] ABGR8888 Height 0
[20:00:04] [PASSED] ABGR8888 Out of bound height * pitch combination
[20:00:04] [PASSED] ABGR8888 Large buffer offset
[20:00:04] [PASSED] ABGR8888 Buffer offset for inexistent plane
[20:00:04] [PASSED] ABGR8888 Invalid flag
[20:00:04] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[20:00:04] [PASSED] ABGR8888 Valid buffer modifier
[20:00:04] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[20:00:04] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[20:00:04] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[20:00:04] [PASSED] NV12 Normal sizes
[20:00:04] [PASSED] NV12 Max sizes
[20:00:04] [PASSED] NV12 Invalid pitch
[20:00:04] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[20:00:04] [PASSED] NV12 different modifier per-plane
[20:00:04] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[20:00:04] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[20:00:04] [PASSED] NV12 Modifier for inexistent plane
[20:00:04] [PASSED] NV12 Handle for inexistent plane
[20:00:04] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[20:00:04] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[20:00:04] [PASSED] YVU420 Normal sizes
[20:00:04] [PASSED] YVU420 Max sizes
[20:00:04] [PASSED] YVU420 Invalid pitch
[20:00:04] [PASSED] YVU420 Different pitches
[20:00:04] [PASSED] YVU420 Different buffer offsets/pitches
[20:00:04] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[20:00:04] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[20:00:04] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[20:00:04] [PASSED] YVU420 Valid modifier
[20:00:04] [PASSED] YVU420 Different modifiers per plane
[20:00:04] [PASSED] YVU420 Modifier for inexistent plane
[20:00:04] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[20:00:04] [PASSED] X0L2 Normal sizes
[20:00:04] [PASSED] X0L2 Max sizes
[20:00:04] [PASSED] X0L2 Invalid pitch
[20:00:04] [PASSED] X0L2 Pitch greater than minimum required
[20:00:04] [PASSED] X0L2 Handle for inexistent plane
[20:00:04] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[20:00:04] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[20:00:04] [PASSED] X0L2 Valid modifier
[20:00:04] [PASSED] X0L2 Modifier for inexistent plane
[20:00:04] =========== [PASSED] drm_test_framebuffer_create ===========
[20:00:04] [PASSED] drm_test_framebuffer_free
[20:00:04] [PASSED] drm_test_framebuffer_init
[20:00:04] [PASSED] drm_test_framebuffer_init_bad_format
[20:00:04] [PASSED] drm_test_framebuffer_init_dev_mismatch
[20:00:04] [PASSED] drm_test_framebuffer_lookup
[20:00:04] [PASSED] drm_test_framebuffer_lookup_inexistent
[20:00:04] [PASSED] drm_test_framebuffer_modifiers_not_supported
[20:00:04] ================= [PASSED] drm_framebuffer =================
[20:00:04] ================ drm_gem_shmem (8 subtests) ================
[20:00:04] [PASSED] drm_gem_shmem_test_obj_create
[20:00:04] [PASSED] drm_gem_shmem_test_obj_create_private
[20:00:04] [PASSED] drm_gem_shmem_test_pin_pages
[20:00:04] [PASSED] drm_gem_shmem_test_vmap
[20:00:04] [PASSED] drm_gem_shmem_test_get_pages_sgt
[20:00:04] [PASSED] drm_gem_shmem_test_get_sg_table
[20:00:04] [PASSED] drm_gem_shmem_test_madvise
[20:00:04] [PASSED] drm_gem_shmem_test_purge
[20:00:04] ================== [PASSED] drm_gem_shmem ==================
[20:00:04] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[20:00:04] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[20:00:04] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[20:00:04] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[20:00:04] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[20:00:04] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[20:00:04] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[20:00:04] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[20:00:04] [PASSED] Automatic
[20:00:04] [PASSED] Full
[20:00:04] [PASSED] Limited 16:235
[20:00:04] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[20:00:04] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[20:00:04] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[20:00:04] [PASSED] drm_test_check_disable_connector
[20:00:04] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[20:00:04] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[20:00:04] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[20:00:04] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[20:00:04] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[20:00:04] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[20:00:04] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[20:00:04] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[20:00:04] [PASSED] drm_test_check_output_bpc_dvi
[20:00:04] [PASSED] drm_test_check_output_bpc_format_vic_1
[20:00:04] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[20:00:04] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[20:00:04] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[20:00:04] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[20:00:04] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[20:00:04] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[20:00:04] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[20:00:04] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[20:00:04] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[20:00:04] [PASSED] drm_test_check_broadcast_rgb_value
[20:00:04] [PASSED] drm_test_check_bpc_8_value
[20:00:04] [PASSED] drm_test_check_bpc_10_value
[20:00:04] [PASSED] drm_test_check_bpc_12_value
[20:00:04] [PASSED] drm_test_check_format_value
[20:00:04] [PASSED] drm_test_check_tmds_char_value
[20:00:04] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[20:00:04] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[20:00:04] [PASSED] drm_test_check_mode_valid
[20:00:04] [PASSED] drm_test_check_mode_valid_reject
[20:00:04] [PASSED] drm_test_check_mode_valid_reject_rate
[20:00:04] [PASSED] drm_test_check_mode_valid_reject_max_clock
[20:00:04] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[20:00:04] ================= drm_managed (2 subtests) =================
[20:00:04] [PASSED] drm_test_managed_release_action
[20:00:04] [PASSED] drm_test_managed_run_action
[20:00:04] =================== [PASSED] drm_managed ===================
[20:00:04] =================== drm_mm (6 subtests) ====================
[20:00:04] [PASSED] drm_test_mm_init
[20:00:04] [PASSED] drm_test_mm_debug
[20:00:04] [PASSED] drm_test_mm_align32
[20:00:04] [PASSED] drm_test_mm_align64
[20:00:04] [PASSED] drm_test_mm_lowest
[20:00:04] [PASSED] drm_test_mm_highest
[20:00:04] ===================== [PASSED] drm_mm ======================
[20:00:04] ============= drm_modes_analog_tv (5 subtests) =============
[20:00:04] [PASSED] drm_test_modes_analog_tv_mono_576i
[20:00:04] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[20:00:04] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[20:00:04] [PASSED] drm_test_modes_analog_tv_pal_576i
[20:00:04] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[20:00:04] =============== [PASSED] drm_modes_analog_tv ===============
[20:00:04] ============== drm_plane_helper (2 subtests) ===============
[20:00:04] =============== drm_test_check_plane_state ================
[20:00:04] [PASSED] clipping_simple
[20:00:04] [PASSED] clipping_rotate_reflect
[20:00:04] [PASSED] positioning_simple
[20:00:04] [PASSED] upscaling
[20:00:04] [PASSED] downscaling
[20:00:04] [PASSED] rounding1
[20:00:04] [PASSED] rounding2
[20:00:04] [PASSED] rounding3
[20:00:04] [PASSED] rounding4
[20:00:04] =========== [PASSED] drm_test_check_plane_state ============
[20:00:04] =========== drm_test_check_invalid_plane_state ============
[20:00:04] [PASSED] positioning_invalid
[20:00:04] [PASSED] upscaling_invalid
[20:00:04] [PASSED] downscaling_invalid
[20:00:04] ======= [PASSED] drm_test_check_invalid_plane_state ========
[20:00:04] ================ [PASSED] drm_plane_helper =================
[20:00:04] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[20:00:04] ====== drm_test_connector_helper_tv_get_modes_check =======
[20:00:04] [PASSED] None
[20:00:04] [PASSED] PAL
[20:00:04] [PASSED] NTSC
[20:00:04] [PASSED] Both, NTSC Default
[20:00:04] [PASSED] Both, PAL Default
[20:00:04] [PASSED] Both, NTSC Default, with PAL on command-line
[20:00:04] [PASSED] Both, PAL Default, with NTSC on command-line
[20:00:04] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[20:00:04] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[20:00:04] ================== drm_rect (9 subtests) ===================
[20:00:04] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[20:00:04] [PASSED] drm_test_rect_clip_scaled_not_clipped
[20:00:04] [PASSED] drm_test_rect_clip_scaled_clipped
[20:00:04] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[20:00:04] ================= drm_test_rect_intersect =================
[20:00:04] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[20:00:04] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[20:00:04] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[20:00:04] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[20:00:04] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[20:00:04] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[20:00:04] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[20:00:04] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[20:00:04] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[20:00:04] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[20:00:04] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[20:00:04] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[20:00:04] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[20:00:04] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[20:00:04] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[20:00:04] ============= [PASSED] drm_test_rect_intersect =============
[20:00:04] ================ drm_test_rect_calc_hscale ================
[20:00:04] [PASSED] normal use
[20:00:04] [PASSED] out of max range
[20:00:04] [PASSED] out of min range
[20:00:04] [PASSED] zero dst
[20:00:04] [PASSED] negative src
[20:00:04] [PASSED] negative dst
[20:00:04] ============ [PASSED] drm_test_rect_calc_hscale ============
[20:00:04] ================ drm_test_rect_calc_vscale ================
[20:00:04] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[20:00:04] [PASSED] out of max range
[20:00:04] [PASSED] out of min range
[20:00:04] [PASSED] zero dst
[20:00:04] [PASSED] negative src
[20:00:04] [PASSED] negative dst
[20:00:04] ============ [PASSED] drm_test_rect_calc_vscale ============
[20:00:04] ================== drm_test_rect_rotate ===================
[20:00:04] [PASSED] reflect-x
[20:00:04] [PASSED] reflect-y
[20:00:04] [PASSED] rotate-0
[20:00:04] [PASSED] rotate-90
[20:00:04] [PASSED] rotate-180
[20:00:04] [PASSED] rotate-270
[20:00:04] ============== [PASSED] drm_test_rect_rotate ===============
[20:00:04] ================ drm_test_rect_rotate_inv =================
[20:00:04] [PASSED] reflect-x
[20:00:04] [PASSED] reflect-y
[20:00:04] [PASSED] rotate-0
[20:00:04] [PASSED] rotate-90
[20:00:04] [PASSED] rotate-180
[20:00:04] [PASSED] rotate-270
[20:00:04] ============ [PASSED] drm_test_rect_rotate_inv =============
[20:00:04] ==================== [PASSED] drm_rect =====================
[20:00:04] ============ drm_sysfb_modeset_test (1 subtest) ============
[20:00:04] ============ drm_test_sysfb_build_fourcc_list =============
[20:00:04] [PASSED] no native formats
[20:00:04] [PASSED] XRGB8888 as native format
[20:00:04] [PASSED] remove duplicates
[20:00:04] [PASSED] convert alpha formats
[20:00:04] [PASSED] random formats
[20:00:04] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[20:00:04] ============= [PASSED] drm_sysfb_modeset_test ==============
[20:00:04] ============================================================
[20:00:04] Testing complete. Ran 622 tests: passed: 622
[20:00:04] Elapsed time: 27.203s total, 1.684s configuring, 25.096s building, 0.406s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[20:00:05] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[20:00:06] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[20:00:16] Starting KUnit Kernel (1/1)...
[20:00:16] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[20:00:16] ================= ttm_device (5 subtests) ==================
[20:00:16] [PASSED] ttm_device_init_basic
[20:00:16] [PASSED] ttm_device_init_multiple
[20:00:16] [PASSED] ttm_device_fini_basic
[20:00:16] [PASSED] ttm_device_init_no_vma_man
[20:00:16] ================== ttm_device_init_pools ==================
[20:00:16] [PASSED] No DMA allocations, no DMA32 required
[20:00:16] [PASSED] DMA allocations, DMA32 required
[20:00:16] [PASSED] No DMA allocations, DMA32 required
[20:00:16] [PASSED] DMA allocations, no DMA32 required
[20:00:16] ============== [PASSED] ttm_device_init_pools ==============
[20:00:16] =================== [PASSED] ttm_device ====================
[20:00:16] ================== ttm_pool (8 subtests) ===================
[20:00:16] ================== ttm_pool_alloc_basic ===================
[20:00:16] [PASSED] One page
[20:00:16] [PASSED] More than one page
[20:00:16] [PASSED] Above the allocation limit
[20:00:16] [PASSED] One page, with coherent DMA mappings enabled
[20:00:16] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[20:00:16] ============== [PASSED] ttm_pool_alloc_basic ===============
[20:00:16] ============== ttm_pool_alloc_basic_dma_addr ==============
[20:00:16] [PASSED] One page
[20:00:16] [PASSED] More than one page
[20:00:16] [PASSED] Above the allocation limit
[20:00:16] [PASSED] One page, with coherent DMA mappings enabled
[20:00:16] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[20:00:16] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[20:00:16] [PASSED] ttm_pool_alloc_order_caching_match
[20:00:16] [PASSED] ttm_pool_alloc_caching_mismatch
[20:00:16] [PASSED] ttm_pool_alloc_order_mismatch
[20:00:16] [PASSED] ttm_pool_free_dma_alloc
[20:00:16] [PASSED] ttm_pool_free_no_dma_alloc
[20:00:16] [PASSED] ttm_pool_fini_basic
[20:00:16] ==================== [PASSED] ttm_pool =====================
[20:00:16] ================ ttm_resource (8 subtests) =================
[20:00:16] ================= ttm_resource_init_basic =================
[20:00:16] [PASSED] Init resource in TTM_PL_SYSTEM
[20:00:16] [PASSED] Init resource in TTM_PL_VRAM
[20:00:16] [PASSED] Init resource in a private placement
[20:00:16] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[20:00:16] ============= [PASSED] ttm_resource_init_basic =============
[20:00:16] [PASSED] ttm_resource_init_pinned
[20:00:16] [PASSED] ttm_resource_fini_basic
[20:00:16] [PASSED] ttm_resource_manager_init_basic
[20:00:16] [PASSED] ttm_resource_manager_usage_basic
[20:00:16] [PASSED] ttm_resource_manager_set_used_basic
[20:00:16] [PASSED] ttm_sys_man_alloc_basic
[20:00:16] [PASSED] ttm_sys_man_free_basic
[20:00:16] ================== [PASSED] ttm_resource ===================
[20:00:16] =================== ttm_tt (15 subtests) ===================
[20:00:16] ==================== ttm_tt_init_basic ====================
[20:00:16] [PASSED] Page-aligned size
[20:00:16] [PASSED] Extra pages requested
[20:00:16] ================ [PASSED] ttm_tt_init_basic ================
[20:00:16] [PASSED] ttm_tt_init_misaligned
[20:00:16] [PASSED] ttm_tt_fini_basic
[20:00:16] [PASSED] ttm_tt_fini_sg
[20:00:16] [PASSED] ttm_tt_fini_shmem
[20:00:16] [PASSED] ttm_tt_create_basic
[20:00:16] [PASSED] ttm_tt_create_invalid_bo_type
[20:00:16] [PASSED] ttm_tt_create_ttm_exists
[20:00:16] [PASSED] ttm_tt_create_failed
[20:00:16] [PASSED] ttm_tt_destroy_basic
[20:00:16] [PASSED] ttm_tt_populate_null_ttm
[20:00:16] [PASSED] ttm_tt_populate_populated_ttm
[20:00:16] [PASSED] ttm_tt_unpopulate_basic
[20:00:16] [PASSED] ttm_tt_unpopulate_empty_ttm
[20:00:16] [PASSED] ttm_tt_swapin_basic
[20:00:16] ===================== [PASSED] ttm_tt ======================
[20:00:16] =================== ttm_bo (14 subtests) ===================
[20:00:16] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[20:00:16] [PASSED] Cannot be interrupted and sleeps
[20:00:16] [PASSED] Cannot be interrupted, locks straight away
[20:00:16] [PASSED] Can be interrupted, sleeps
[20:00:16] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[20:00:16] [PASSED] ttm_bo_reserve_locked_no_sleep
[20:00:16] [PASSED] ttm_bo_reserve_no_wait_ticket
[20:00:16] [PASSED] ttm_bo_reserve_double_resv
[20:00:16] [PASSED] ttm_bo_reserve_interrupted
[20:00:16] [PASSED] ttm_bo_reserve_deadlock
[20:00:16] [PASSED] ttm_bo_unreserve_basic
[20:00:16] [PASSED] ttm_bo_unreserve_pinned
[20:00:16] [PASSED] ttm_bo_unreserve_bulk
[20:00:16] [PASSED] ttm_bo_fini_basic
[20:00:16] [PASSED] ttm_bo_fini_shared_resv
[20:00:16] [PASSED] ttm_bo_pin_basic
[20:00:16] [PASSED] ttm_bo_pin_unpin_resource
[20:00:16] [PASSED] ttm_bo_multiple_pin_one_unpin
[20:00:16] ===================== [PASSED] ttm_bo ======================
[20:00:16] ============== ttm_bo_validate (21 subtests) ===============
[20:00:16] ============== ttm_bo_init_reserved_sys_man ===============
[20:00:16] [PASSED] Buffer object for userspace
[20:00:16] [PASSED] Kernel buffer object
[20:00:16] [PASSED] Shared buffer object
[20:00:16] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[20:00:16] ============== ttm_bo_init_reserved_mock_man ==============
[20:00:16] [PASSED] Buffer object for userspace
[20:00:16] [PASSED] Kernel buffer object
[20:00:16] [PASSED] Shared buffer object
[20:00:16] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[20:00:16] [PASSED] ttm_bo_init_reserved_resv
[20:00:16] ================== ttm_bo_validate_basic ==================
[20:00:16] [PASSED] Buffer object for userspace
[20:00:16] [PASSED] Kernel buffer object
[20:00:16] [PASSED] Shared buffer object
[20:00:16] ============== [PASSED] ttm_bo_validate_basic ==============
[20:00:16] [PASSED] ttm_bo_validate_invalid_placement
[20:00:16] ============= ttm_bo_validate_same_placement ==============
[20:00:16] [PASSED] System manager
[20:00:16] [PASSED] VRAM manager
[20:00:16] ========= [PASSED] ttm_bo_validate_same_placement ==========
[20:00:16] [PASSED] ttm_bo_validate_failed_alloc
[20:00:16] [PASSED] ttm_bo_validate_pinned
[20:00:16] [PASSED] ttm_bo_validate_busy_placement
[20:00:16] ================ ttm_bo_validate_multihop =================
[20:00:16] [PASSED] Buffer object for userspace
[20:00:16] [PASSED] Kernel buffer object
[20:00:16] [PASSED] Shared buffer object
[20:00:16] ============ [PASSED] ttm_bo_validate_multihop =============
[20:00:16] ========== ttm_bo_validate_no_placement_signaled ==========
[20:00:16] [PASSED] Buffer object in system domain, no page vector
[20:00:16] [PASSED] Buffer object in system domain with an existing page vector
[20:00:16] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[20:00:16] ======== ttm_bo_validate_no_placement_not_signaled ========
[20:00:16] [PASSED] Buffer object for userspace
[20:00:16] [PASSED] Kernel buffer object
[20:00:16] [PASSED] Shared buffer object
[20:00:16] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[20:00:16] [PASSED] ttm_bo_validate_move_fence_signaled
[20:00:16] ========= ttm_bo_validate_move_fence_not_signaled =========
[20:00:16] [PASSED] Waits for GPU
[20:00:16] [PASSED] Tries to lock straight away
[20:00:16] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[20:00:16] [PASSED] ttm_bo_validate_happy_evict
[20:00:16] [PASSED] ttm_bo_validate_all_pinned_evict
[20:00:16] [PASSED] ttm_bo_validate_allowed_only_evict
[20:00:16] [PASSED] ttm_bo_validate_deleted_evict
[20:00:16] [PASSED] ttm_bo_validate_busy_domain_evict
[20:00:16] [PASSED] ttm_bo_validate_evict_gutting
[20:00:16] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[20:00:16] ================= [PASSED] ttm_bo_validate =================
[20:00:16] ============================================================
[20:00:16] Testing complete. Ran 101 tests: passed: 101
[20:00:16] Elapsed time: 11.449s total, 1.745s configuring, 9.488s building, 0.187s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 25+ messages in thread
* ✓ Xe.CI.BAT: success for Move PSR/Panel Replay sink data into intel_connector
2025-11-21 11:16 [PATCH 0/8] Move PSR/Panel Replay sink data into intel_connector Jouni Högander
` (9 preceding siblings ...)
2025-11-24 20:00 ` ✓ CI.KUnit: success " Patchwork
@ 2025-11-24 20:47 ` Patchwork
2025-11-24 22:37 ` ✗ Xe.CI.Full: failure " Patchwork
11 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2025-11-24 20:47 UTC (permalink / raw)
To: Jouni Högander; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 1502 bytes --]
== Series Details ==
Series: Move PSR/Panel Replay sink data into intel_connector
URL : https://patchwork.freedesktop.org/series/157898/
State : success
== Summary ==
CI Bug Log - changes from xe-4139-1313821419324cad5cc45003ce9e2aaf1e1fed75_BAT -> xe-pw-157898v1_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (12 -> 12)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in xe-pw-157898v1_BAT that come from known issues:
### IGT changes ###
#### Possible fixes ####
* igt@xe_waitfence@engine:
- bat-pvc-2: [FAIL][1] ([Intel XE#6519]) -> [PASS][2]
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4139-1313821419324cad5cc45003ce9e2aaf1e1fed75/bat-pvc-2/igt@xe_waitfence@engine.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/bat-pvc-2/igt@xe_waitfence@engine.html
[Intel XE#6519]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6519
Build changes
-------------
* Linux: xe-4139-1313821419324cad5cc45003ce9e2aaf1e1fed75 -> xe-pw-157898v1
IGT_8636: 254cd102396ff95d61f2ebe49fc09128878bf483 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-4139-1313821419324cad5cc45003ce9e2aaf1e1fed75: 1313821419324cad5cc45003ce9e2aaf1e1fed75
xe-pw-157898v1: 157898v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/index.html
[-- Attachment #2: Type: text/html, Size: 2067 bytes --]
^ permalink raw reply [flat|nested] 25+ messages in thread
* ✗ Xe.CI.Full: failure for Move PSR/Panel Replay sink data into intel_connector
2025-11-21 11:16 [PATCH 0/8] Move PSR/Panel Replay sink data into intel_connector Jouni Högander
` (10 preceding siblings ...)
2025-11-24 20:47 ` ✓ Xe.CI.BAT: " Patchwork
@ 2025-11-24 22:37 ` Patchwork
11 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2025-11-24 22:37 UTC (permalink / raw)
To: Jouni Högander; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 33203 bytes --]
== Series Details ==
Series: Move PSR/Panel Replay sink data into intel_connector
URL : https://patchwork.freedesktop.org/series/157898/
State : failure
== Summary ==
CI Bug Log - changes from xe-4139-1313821419324cad5cc45003ce9e2aaf1e1fed75_FULL -> xe-pw-157898v1_FULL
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-157898v1_FULL absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-157898v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (4 -> 4)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-157898v1_FULL:
### IGT changes ###
#### Possible regressions ####
* igt@kms_async_flips@async-flip-suspend-resume@pipe-a-dp-4:
- shard-dg2-set2: NOTRUN -> [ABORT][1]
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-dg2-432/igt@kms_async_flips@async-flip-suspend-resume@pipe-a-dp-4.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-6:
- shard-dg2-set2: [PASS][2] -> [ABORT][3] +1 other test abort
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4139-1313821419324cad5cc45003ce9e2aaf1e1fed75/shard-dg2-432/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-6.html
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-dg2-433/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-6.html
* igt@kms_flip@2x-flip-vs-suspend@ab-dp2-hdmi-a3:
- shard-bmg: NOTRUN -> [ABORT][4] +1 other test abort
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-bmg-1/igt@kms_flip@2x-flip-vs-suspend@ab-dp2-hdmi-a3.html
* igt@xe_pm@s2idle-vm-bind-unbind-all:
- shard-adlp: [PASS][5] -> [ABORT][6] +4 other tests abort
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4139-1313821419324cad5cc45003ce9e2aaf1e1fed75/shard-adlp-6/igt@xe_pm@s2idle-vm-bind-unbind-all.html
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-adlp-4/igt@xe_pm@s2idle-vm-bind-unbind-all.html
- shard-bmg: [PASS][7] -> [ABORT][8]
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4139-1313821419324cad5cc45003ce9e2aaf1e1fed75/shard-bmg-2/igt@xe_pm@s2idle-vm-bind-unbind-all.html
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-bmg-1/igt@xe_pm@s2idle-vm-bind-unbind-all.html
* igt@xe_pm@s3-vm-bind-unbind-all:
- shard-adlp: NOTRUN -> [ABORT][9]
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-adlp-6/igt@xe_pm@s3-vm-bind-unbind-all.html
#### Warnings ####
* igt@kms_flip@2x-flip-vs-suspend:
- shard-bmg: [SKIP][10] ([Intel XE#2316]) -> [ABORT][11]
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4139-1313821419324cad5cc45003ce9e2aaf1e1fed75/shard-bmg-6/igt@kms_flip@2x-flip-vs-suspend.html
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-bmg-1/igt@kms_flip@2x-flip-vs-suspend.html
Known issues
------------
Here are the changes found in xe-pw-157898v1_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_big_fb@linear-16bpp-rotate-270:
- shard-dg2-set2: NOTRUN -> [SKIP][12] ([Intel XE#316])
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-dg2-435/igt@kms_big_fb@linear-16bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-180:
- shard-adlp: NOTRUN -> [DMESG-FAIL][13] ([Intel XE#4543])
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-adlp-1/igt@kms_big_fb@y-tiled-64bpp-rotate-180.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-90:
- shard-adlp: NOTRUN -> [SKIP][14] ([Intel XE#316])
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-adlp-6/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
- shard-dg2-set2: NOTRUN -> [SKIP][15] ([Intel XE#1124]) +3 other tests skip
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-dg2-435/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-adlp: NOTRUN -> [SKIP][16] ([Intel XE#1124]) +1 other test skip
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-adlp-1/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_bw@connected-linear-tiling-3-displays-2160x1440p:
- shard-dg2-set2: NOTRUN -> [SKIP][17] ([Intel XE#2191])
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-dg2-435/igt@kms_bw@connected-linear-tiling-3-displays-2160x1440p.html
* igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-a-hdmi-a-1:
- shard-adlp: NOTRUN -> [SKIP][18] ([Intel XE#787]) +5 other tests skip
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-adlp-6/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-a-hdmi-a-1.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs@pipe-a-dp-4:
- shard-dg2-set2: NOTRUN -> [INCOMPLETE][19] ([Intel XE#3862])
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-dg2-464/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs@pipe-a-dp-4.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc@pipe-d-dp-4:
- shard-dg2-set2: NOTRUN -> [SKIP][20] ([Intel XE#455] / [Intel XE#787]) +9 other tests skip
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-dg2-436/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc@pipe-d-dp-4.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-6:
- shard-dg2-set2: NOTRUN -> [SKIP][21] ([Intel XE#787]) +34 other tests skip
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-dg2-436/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-6.html
* igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs@pipe-c-dp-2:
- shard-bmg: NOTRUN -> [SKIP][22] ([Intel XE#2652] / [Intel XE#787]) +7 other tests skip
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-bmg-1/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs@pipe-c-dp-2.html
* igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-d-hdmi-a-1:
- shard-adlp: NOTRUN -> [SKIP][23] ([Intel XE#455] / [Intel XE#787]) +3 other tests skip
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-adlp-1/igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-d-hdmi-a-1.html
* igt@kms_chamelium_frames@dp-frame-dump:
- shard-adlp: NOTRUN -> [SKIP][24] ([Intel XE#373])
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-adlp-1/igt@kms_chamelium_frames@dp-frame-dump.html
* igt@kms_chamelium_hpd@vga-hpd-without-ddc:
- shard-dg2-set2: NOTRUN -> [SKIP][25] ([Intel XE#373]) +4 other tests skip
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-dg2-436/igt@kms_chamelium_hpd@vga-hpd-without-ddc.html
* igt@kms_content_protection@uevent@pipe-a-dp-2:
- shard-bmg: NOTRUN -> [FAIL][26] ([Intel XE#1188])
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-bmg-1/igt@kms_content_protection@uevent@pipe-a-dp-2.html
* igt@kms_cursor_crc@cursor-onscreen-512x512:
- shard-adlp: NOTRUN -> [SKIP][27] ([Intel XE#308])
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-adlp-1/igt@kms_cursor_crc@cursor-onscreen-512x512.html
* igt@kms_cursor_crc@cursor-random-512x170:
- shard-dg2-set2: NOTRUN -> [SKIP][28] ([Intel XE#308])
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-dg2-436/igt@kms_cursor_crc@cursor-random-512x170.html
* igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic:
- shard-adlp: NOTRUN -> [SKIP][29] ([Intel XE#309])
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-adlp-6/igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-atomic:
- shard-bmg: [PASS][30] -> [SKIP][31] ([Intel XE#2291]) +3 other tests skip
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4139-1313821419324cad5cc45003ce9e2aaf1e1fed75/shard-bmg-8/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic.html
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic.html
* igt@kms_dp_linktrain_fallback@dsc-fallback:
- shard-dg2-set2: NOTRUN -> [SKIP][32] ([Intel XE#4331])
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-dg2-435/igt@kms_dp_linktrain_fallback@dsc-fallback.html
* igt@kms_dsc@dsc-with-output-formats-with-bpc:
- shard-dg2-set2: NOTRUN -> [SKIP][33] ([Intel XE#455]) +7 other tests skip
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-dg2-435/igt@kms_dsc@dsc-with-output-formats-with-bpc.html
* igt@kms_flip@2x-busy-flip:
- shard-adlp: NOTRUN -> [SKIP][34] ([Intel XE#310])
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-adlp-1/igt@kms_flip@2x-busy-flip.html
* igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible:
- shard-bmg: [PASS][35] -> [SKIP][36] ([Intel XE#2316]) +4 other tests skip
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4139-1313821419324cad5cc45003ce9e2aaf1e1fed75/shard-bmg-8/igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible.html
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-bmg-6/igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-lnl: [PASS][37] -> [FAIL][38] ([Intel XE#301]) +1 other test fail
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4139-1313821419324cad5cc45003ce9e2aaf1e1fed75/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-lnl-7/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling:
- shard-adlp: NOTRUN -> [SKIP][39] ([Intel XE#455]) +5 other tests skip
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-adlp-6/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html
* igt@kms_frontbuffer_tracking@drrs-1p-primscrn-pri-indfb-draw-mmap-wc:
- shard-dg2-set2: NOTRUN -> [SKIP][40] ([Intel XE#651]) +7 other tests skip
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-dg2-436/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-pgflip-blt:
- shard-adlp: NOTRUN -> [SKIP][41] ([Intel XE#656]) +2 other tests skip
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-adlp-6/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-shrfb-draw-render:
- shard-dg2-set2: NOTRUN -> [SKIP][42] ([Intel XE#6312]) +1 other test skip
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-dg2-435/igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-shrfb-plflip-blt:
- shard-adlp: NOTRUN -> [SKIP][43] ([Intel XE#651])
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-adlp-1/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbcdrrs-tiling-y:
- shard-dg2-set2: NOTRUN -> [SKIP][44] ([Intel XE#658])
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-dg2-435/igt@kms_frontbuffer_tracking@fbcdrrs-tiling-y.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc:
- shard-adlp: NOTRUN -> [SKIP][45] ([Intel XE#653]) +3 other tests skip
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-adlp-1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-slowdraw:
- shard-dg2-set2: NOTRUN -> [SKIP][46] ([Intel XE#653]) +9 other tests skip
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-dg2-435/igt@kms_frontbuffer_tracking@psr-slowdraw.html
* igt@kms_mmap_write_crc@main:
- shard-adlp: [PASS][47] -> [DMESG-WARN][48] ([Intel XE#2953] / [Intel XE#4173]) +2 other tests dmesg-warn
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4139-1313821419324cad5cc45003ce9e2aaf1e1fed75/shard-adlp-2/igt@kms_mmap_write_crc@main.html
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-adlp-4/igt@kms_mmap_write_crc@main.html
* igt@kms_plane_multiple@tiling-yf:
- shard-adlp: NOTRUN -> [SKIP][49] ([Intel XE#5020])
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-adlp-1/igt@kms_plane_multiple@tiling-yf.html
* igt@kms_pm_backlight@brightness-with-dpms:
- shard-dg2-set2: NOTRUN -> [SKIP][50] ([Intel XE#2938])
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-dg2-435/igt@kms_pm_backlight@brightness-with-dpms.html
* igt@kms_psr2_sf@psr2-plane-move-sf-dmg-area:
- shard-dg2-set2: NOTRUN -> [SKIP][51] ([Intel XE#1406] / [Intel XE#1489]) +1 other test skip
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-dg2-436/igt@kms_psr2_sf@psr2-plane-move-sf-dmg-area.html
* igt@kms_psr@fbc-psr-no-drrs:
- shard-adlp: NOTRUN -> [SKIP][52] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929])
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-adlp-1/igt@kms_psr@fbc-psr-no-drrs.html
* igt@kms_psr@fbc-psr2-no-drrs:
- shard-dg2-set2: NOTRUN -> [SKIP][53] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) +3 other tests skip
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-dg2-435/igt@kms_psr@fbc-psr2-no-drrs.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
- shard-dg2-set2: NOTRUN -> [SKIP][54] ([Intel XE#1127])
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-dg2-435/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
* igt@xe_eu_stall@blocking-read:
- shard-dg2-set2: NOTRUN -> [SKIP][55] ([Intel XE#5626])
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-dg2-435/igt@xe_eu_stall@blocking-read.html
* igt@xe_eudebug@basic-vm-access-userptr:
- shard-adlp: NOTRUN -> [SKIP][56] ([Intel XE#4837] / [Intel XE#5565]) +2 other tests skip
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-adlp-1/igt@xe_eudebug@basic-vm-access-userptr.html
* igt@xe_eudebug_online@interrupt-other:
- shard-dg2-set2: NOTRUN -> [SKIP][57] ([Intel XE#4837]) +4 other tests skip
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-dg2-436/igt@xe_eudebug_online@interrupt-other.html
* igt@xe_evict@evict-beng-mixed-many-threads-large:
- shard-adlp: NOTRUN -> [SKIP][58] ([Intel XE#261])
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-adlp-1/igt@xe_evict@evict-beng-mixed-many-threads-large.html
* igt@xe_evict@evict-beng-mixed-many-threads-small:
- shard-bmg: [PASS][59] -> [INCOMPLETE][60] ([Intel XE#6321] / [Intel XE#6606])
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4139-1313821419324cad5cc45003ce9e2aaf1e1fed75/shard-bmg-5/igt@xe_evict@evict-beng-mixed-many-threads-small.html
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-bmg-1/igt@xe_evict@evict-beng-mixed-many-threads-small.html
* igt@xe_evict@evict-cm-threads-small:
- shard-adlp: NOTRUN -> [SKIP][61] ([Intel XE#261] / [Intel XE#688])
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-adlp-1/igt@xe_evict@evict-cm-threads-small.html
* igt@xe_exec_basic@multigpu-once-null-defer-mmap:
- shard-adlp: NOTRUN -> [SKIP][62] ([Intel XE#1392] / [Intel XE#5575])
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-adlp-1/igt@xe_exec_basic@multigpu-once-null-defer-mmap.html
* igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-invalidate-race-imm:
- shard-adlp: NOTRUN -> [SKIP][63] ([Intel XE#288] / [Intel XE#5561]) +6 other tests skip
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-adlp-6/igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-invalidate-race-imm.html
* igt@xe_exec_fault_mode@twice-rebind-prefetch:
- shard-dg2-set2: NOTRUN -> [SKIP][64] ([Intel XE#288]) +8 other tests skip
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-dg2-435/igt@xe_exec_fault_mode@twice-rebind-prefetch.html
* igt@xe_exec_system_allocator@threads-many-large-mmap-shared-remap-dontunmap-eocheck:
- shard-dg2-set2: NOTRUN -> [SKIP][65] ([Intel XE#4915]) +103 other tests skip
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-dg2-435/igt@xe_exec_system_allocator@threads-many-large-mmap-shared-remap-dontunmap-eocheck.html
* igt@xe_exec_system_allocator@threads-shared-vm-many-execqueues-malloc:
- shard-adlp: NOTRUN -> [SKIP][66] ([Intel XE#4915]) +33 other tests skip
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-adlp-1/igt@xe_exec_system_allocator@threads-shared-vm-many-execqueues-malloc.html
* igt@xe_live_ktest@xe_migrate@xe_validate_ccs_kunit:
- shard-dg2-set2: NOTRUN -> [SKIP][67] ([Intel XE#2229])
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-dg2-436/igt@xe_live_ktest@xe_migrate@xe_validate_ccs_kunit.html
* igt@xe_oa@tail-address-wrap:
- shard-adlp: NOTRUN -> [SKIP][68] ([Intel XE#6032])
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-adlp-1/igt@xe_oa@tail-address-wrap.html
* igt@xe_oa@whitelisted-registers-userspace-config:
- shard-dg2-set2: NOTRUN -> [SKIP][69] ([Intel XE#3573]) +3 other tests skip
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-dg2-436/igt@xe_oa@whitelisted-registers-userspace-config.html
* igt@xe_peer2peer@write@write-gpua-vram01-gpub-system-p2p:
- shard-dg2-set2: NOTRUN -> [SKIP][70] ([Intel XE#6566])
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-dg2-435/igt@xe_peer2peer@write@write-gpua-vram01-gpub-system-p2p.html
* igt@xe_pm@d3cold-mmap-vram:
- shard-adlp: NOTRUN -> [SKIP][71] ([Intel XE#2284] / [Intel XE#366])
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-adlp-1/igt@xe_pm@d3cold-mmap-vram.html
* igt@xe_pmu@engine-activity-accuracy-50:
- shard-lnl: [PASS][72] -> [FAIL][73] ([Intel XE#6251]) +2 other tests fail
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4139-1313821419324cad5cc45003ce9e2aaf1e1fed75/shard-lnl-8/igt@xe_pmu@engine-activity-accuracy-50.html
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-lnl-1/igt@xe_pmu@engine-activity-accuracy-50.html
* igt@xe_pxp@pxp-optout:
- shard-adlp: NOTRUN -> [SKIP][74] ([Intel XE#4733] / [Intel XE#5594])
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-adlp-1/igt@xe_pxp@pxp-optout.html
* igt@xe_pxp@pxp-termination-key-update-post-rpm:
- shard-dg2-set2: NOTRUN -> [SKIP][75] ([Intel XE#4733])
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-dg2-436/igt@xe_pxp@pxp-termination-key-update-post-rpm.html
* igt@xe_query@multigpu-query-invalid-uc-fw-version-mbz:
- shard-dg2-set2: NOTRUN -> [SKIP][76] ([Intel XE#944])
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-dg2-435/igt@xe_query@multigpu-query-invalid-uc-fw-version-mbz.html
* igt@xe_sriov_auto_provisioning@selfconfig-basic:
- shard-dg2-set2: NOTRUN -> [SKIP][77] ([Intel XE#4130])
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-dg2-435/igt@xe_sriov_auto_provisioning@selfconfig-basic.html
#### Possible fixes ####
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-adlp: [DMESG-FAIL][78] ([Intel XE#4543]) -> [PASS][79]
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4139-1313821419324cad5cc45003ce9e2aaf1e1fed75/shard-adlp-6/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-adlp-4/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_cursor_legacy@cursora-vs-flipb-varying-size:
- shard-bmg: [SKIP][80] ([Intel XE#2291]) -> [PASS][81] +2 other tests pass
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4139-1313821419324cad5cc45003ce9e2aaf1e1fed75/shard-bmg-6/igt@kms_cursor_legacy@cursora-vs-flipb-varying-size.html
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-bmg-1/igt@kms_cursor_legacy@cursora-vs-flipb-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic:
- shard-bmg: [FAIL][82] ([Intel XE#4633]) -> [PASS][83]
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4139-1313821419324cad5cc45003ce9e2aaf1e1fed75/shard-bmg-3/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-bmg-3/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-legacy:
- shard-bmg: [FAIL][84] ([Intel XE#5299]) -> [PASS][85]
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4139-1313821419324cad5cc45003ce9e2aaf1e1fed75/shard-bmg-7/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-bmg-5/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
* igt@kms_flip@2x-plain-flip:
- shard-bmg: [SKIP][86] ([Intel XE#2316]) -> [PASS][87] +3 other tests pass
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4139-1313821419324cad5cc45003ce9e2aaf1e1fed75/shard-bmg-2/igt@kms_flip@2x-plain-flip.html
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-bmg-5/igt@kms_flip@2x-plain-flip.html
* igt@kms_plane_multiple@2x-tiling-4:
- shard-bmg: [SKIP][88] ([Intel XE#4596]) -> [PASS][89]
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4139-1313821419324cad5cc45003ce9e2aaf1e1fed75/shard-bmg-6/igt@kms_plane_multiple@2x-tiling-4.html
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-bmg-1/igt@kms_plane_multiple@2x-tiling-4.html
* igt@kms_plane_scaling@2x-scaler-multi-pipe:
- shard-bmg: [SKIP][90] ([Intel XE#2571]) -> [PASS][91]
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4139-1313821419324cad5cc45003ce9e2aaf1e1fed75/shard-bmg-2/igt@kms_plane_scaling@2x-scaler-multi-pipe.html
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-bmg-1/igt@kms_plane_scaling@2x-scaler-multi-pipe.html
* igt@xe_gt_freq@freq_suspend:
- shard-adlp: [ABORT][92] -> [PASS][93]
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4139-1313821419324cad5cc45003ce9e2aaf1e1fed75/shard-adlp-3/igt@xe_gt_freq@freq_suspend.html
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-adlp-6/igt@xe_gt_freq@freq_suspend.html
* igt@xe_pm@s4-mocs:
- shard-adlp: [ABORT][94] ([Intel XE#2953]) -> [PASS][95]
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4139-1313821419324cad5cc45003ce9e2aaf1e1fed75/shard-adlp-6/igt@xe_pm@s4-mocs.html
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-adlp-1/igt@xe_pm@s4-mocs.html
* igt@xe_pm@s4-vm-bind-userptr:
- shard-dg2-set2: [ABORT][96] -> [PASS][97] +2 other tests pass
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4139-1313821419324cad5cc45003ce9e2aaf1e1fed75/shard-dg2-466/igt@xe_pm@s4-vm-bind-userptr.html
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-dg2-435/igt@xe_pm@s4-vm-bind-userptr.html
#### Warnings ####
* igt@kms_content_protection@uevent:
- shard-bmg: [SKIP][98] ([Intel XE#2341]) -> [FAIL][99] ([Intel XE#1188])
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4139-1313821419324cad5cc45003ce9e2aaf1e1fed75/shard-bmg-2/igt@kms_content_protection@uevent.html
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-bmg-1/igt@kms_content_protection@uevent.html
* igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][100] ([Intel XE#2312]) -> [SKIP][101] ([Intel XE#2311]) +14 other tests skip
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4139-1313821419324cad5cc45003ce9e2aaf1e1fed75/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][102] ([Intel XE#2312]) -> [SKIP][103] ([Intel XE#4141]) +5 other tests skip
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4139-1313821419324cad5cc45003ce9e2aaf1e1fed75/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc.html
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff:
- shard-bmg: [SKIP][104] ([Intel XE#4141]) -> [SKIP][105] ([Intel XE#2312]) +6 other tests skip
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4139-1313821419324cad5cc45003ce9e2aaf1e1fed75/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][106] ([Intel XE#2311]) -> [SKIP][107] ([Intel XE#2312]) +11 other tests skip
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4139-1313821419324cad5cc45003ce9e2aaf1e1fed75/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-plflip-blt:
- shard-bmg: [SKIP][108] ([Intel XE#2313]) -> [SKIP][109] ([Intel XE#2312]) +7 other tests skip
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4139-1313821419324cad5cc45003ce9e2aaf1e1fed75/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-plflip-blt.html
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt:
- shard-bmg: [SKIP][110] ([Intel XE#2312]) -> [SKIP][111] ([Intel XE#2313]) +15 other tests skip
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4139-1313821419324cad5cc45003ce9e2aaf1e1fed75/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt.html
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt.html
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
[Intel XE#1188]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1188
[Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
[Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
[Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229
[Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
[Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
[Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
[Intel XE#2571]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2571
[Intel XE#261]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/261
[Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
[Intel XE#2938]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2938
[Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
[Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
[Intel XE#310]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/310
[Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
[Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
[Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
[Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
[Intel XE#3862]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3862
[Intel XE#4130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4130
[Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
[Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
[Intel XE#4331]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4331
[Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
[Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
[Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
[Intel XE#4633]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4633
[Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
[Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
[Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
[Intel XE#5020]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5020
[Intel XE#5299]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5299
[Intel XE#5561]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5561
[Intel XE#5565]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5565
[Intel XE#5575]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5575
[Intel XE#5594]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5594
[Intel XE#5626]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5626
[Intel XE#6032]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6032
[Intel XE#6251]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6251
[Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
[Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
[Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
[Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
[Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
[Intel XE#6566]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6566
[Intel XE#658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/658
[Intel XE#6606]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6606
[Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
[Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
[Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
Build changes
-------------
* Linux: xe-4139-1313821419324cad5cc45003ce9e2aaf1e1fed75 -> xe-pw-157898v1
IGT_8636: 254cd102396ff95d61f2ebe49fc09128878bf483 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-4139-1313821419324cad5cc45003ce9e2aaf1e1fed75: 1313821419324cad5cc45003ce9e2aaf1e1fed75
xe-pw-157898v1: 157898v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157898v1/index.html
[-- Attachment #2: Type: text/html, Size: 38204 bytes --]
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 1/8] drm/i915/psr: Add panel granularity information into intel_connector
2025-11-21 11:16 ` [PATCH 1/8] drm/i915/psr: Add panel granularity information " Jouni Högander
@ 2025-12-01 9:54 ` Imre Deak
0 siblings, 0 replies; 25+ messages in thread
From: Imre Deak @ 2025-12-01 9:54 UTC (permalink / raw)
To: Jouni Högander; +Cc: intel-gfx, intel-xe
On Fri, Nov 21, 2025 at 01:16:48PM +0200, Jouni Högander wrote:
> As a preparation for MST Panel Replay implementation add psr_caps and
> panel_replay_caps structures into intel_connector. These are supposed to
> contain all sink information related to PSR and Panel Replay.
>
> As a first step in moving Panel Replay and PSR sink data add panel
> granularity information into these newly added caps structures.
>
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display_types.h | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 38702a9e0f508..f39d62aa99246 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -561,6 +561,16 @@ struct intel_connector {
> } overall_throughput;
> int max_line_width;
> } dsc_branch_caps;
> +
> + struct {
> + u16 su_w_granularity;
> + u16 su_y_granularity;
> + } panel_replay_caps;
> +
> + struct {
> + u16 su_w_granularity;
> + u16 su_y_granularity;
> + } psr_caps;
> } dp;
>
> struct {
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 2/8] drm/i915/psr: Use SU granularity information available in intel_connector
2025-11-21 11:16 ` [PATCH 2/8] drm/i915/psr: Use SU granularity information available in intel_connector Jouni Högander
@ 2025-12-01 10:14 ` Imre Deak
0 siblings, 0 replies; 25+ messages in thread
From: Imre Deak @ 2025-12-01 10:14 UTC (permalink / raw)
To: Jouni Högander; +Cc: intel-gfx, intel-xe
On Fri, Nov 21, 2025 at 01:16:49PM +0200, Jouni Högander wrote:
> Currently we are storing only one set of granularity information for panels
> supporting both PSR and Panel Replay. It might be that in practice they are
> always the same.
"in practice they could be different" would be what justifies the
changes. If you wanted to mention that they may be the same in practice,
it should be explained instead why tracking them separately still makes
sense.
> As panel is informing own granularities for PSR and Panel
> Replay let's use these instead of having only one set for both. This is
> done by having intel_connector::psr_caps and panel_replay_caps both
> containing granularity information.
>
> This patch is also removing complexity of sharing granularity read between
> PSR and Panel Replay.
>
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 4 +-
> drivers/gpu/drm/i915/display/intel_psr.c | 139 +++++++++++------------
> drivers/gpu/drm/i915/display/intel_psr.h | 2 +-
> 3 files changed, 69 insertions(+), 76 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 0ec82fcbcf48e..62808cd35f5f2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4562,7 +4562,7 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector
> * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
> * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
> */
> - intel_psr_init_dpcd(intel_dp);
> + intel_psr_init_dpcd(intel_dp, connector);
>
> intel_edp_set_sink_rates(intel_dp);
> intel_dp_set_max_sink_lane_count(intel_dp);
> @@ -6075,7 +6075,7 @@ intel_dp_detect(struct drm_connector *_connector,
> connector->base.epoch_counter++;
>
> if (!intel_dp_is_edp(intel_dp))
> - intel_psr_init_dpcd(intel_dp);
> + intel_psr_init_dpcd(intel_dp, connector);
>
> intel_dp_detect_dsc_caps(intel_dp, connector);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 00ac652809cca..4c5883bed612b 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -494,69 +494,26 @@ static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)
> return val;
> }
>
> -static u8 intel_dp_get_su_capability(struct intel_dp *intel_dp)
> -{
> - u8 su_capability = 0;
> -
> - if (intel_dp->psr.sink_panel_replay_su_support) {
> - if (drm_dp_dpcd_read_byte(&intel_dp->aux,
> - DP_PANEL_REPLAY_CAP_CAPABILITY,
> - &su_capability) < 0)
> - return 0;
> - } else {
> - su_capability = intel_dp->psr_dpcd[1];
> - }
> -
> - return su_capability;
> -}
> -
> -static unsigned int
> -intel_dp_get_su_x_granularity_offset(struct intel_dp *intel_dp)
> -{
> - return intel_dp->psr.sink_panel_replay_su_support ?
> - DP_PANEL_REPLAY_CAP_X_GRANULARITY :
> - DP_PSR2_SU_X_GRANULARITY;
> -}
> -
> -static unsigned int
> -intel_dp_get_su_y_granularity_offset(struct intel_dp *intel_dp)
> -{
> - return intel_dp->psr.sink_panel_replay_su_support ?
> - DP_PANEL_REPLAY_CAP_Y_GRANULARITY :
> - DP_PSR2_SU_Y_GRANULARITY;
> -}
> -
> -/*
> - * Note: Bits related to granularity are same in panel replay and psr
> - * registers. Rely on PSR definitions on these "common" bits.
> - */
> -static void intel_dp_get_su_granularity(struct intel_dp *intel_dp)
> +static void _psr_compute_su_granularity(struct intel_dp *intel_dp,
> + struct intel_connector *connector)
> {
> struct intel_display *display = to_intel_display(intel_dp);
> ssize_t r;
> u16 w;
This should be changed to __le16 (even though not added in this patch).
> u8 y;
>
> - /*
> - * TODO: Do we need to take into account panel supporting both PSR and
> - * Panel replay?
> - */
> -
> /*
> * If sink don't have specific granularity requirements set legacy
> * ones.
> */
> - if (!(intel_dp_get_su_capability(intel_dp) &
> - DP_PSR2_SU_GRANULARITY_REQUIRED)) {
> + if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) {
> /* As PSR2 HW sends full lines, we do not care about x granularity */
> w = 4;
> y = 4;
> goto exit;
> }
>
> - r = drm_dp_dpcd_read(&intel_dp->aux,
> - intel_dp_get_su_x_granularity_offset(intel_dp),
> - &w, 2);
> + r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &w, 2);
should be sizeof(w) instead of 2. (yes, not added in this patch, but
still)
> if (r != 2)
> drm_dbg_kms(display->drm,
> "Unable to read selective update x granularity\n");
> @@ -567,9 +524,7 @@ static void intel_dp_get_su_granularity(struct intel_dp *intel_dp)
> if (r != 2 || w == 0)
> w = 4;
>
> - r = drm_dp_dpcd_read(&intel_dp->aux,
> - intel_dp_get_su_y_granularity_offset(intel_dp),
> - &y, 1);
> + r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_Y_GRANULARITY, &y, 1);
> if (r != 1) {
> drm_dbg_kms(display->drm,
> "Unable to read selective update y granularity\n");
> @@ -579,8 +534,8 @@ static void intel_dp_get_su_granularity(struct intel_dp *intel_dp)
> y = 1;
>
> exit:
> - intel_dp->psr.su_w_granularity = w;
> - intel_dp->psr.su_y_granularity = y;
> + connector->dp.psr_caps.su_w_granularity = w;
Should use le16_to_cpu(w) instead of w. w was used as-is already before
this change, however there is a related issue below, so I'd fix this one
as well in this patch/patchset.
> + connector->dp.psr_caps.su_y_granularity = y;
> }
>
> static enum intel_panel_replay_dsc_support
> @@ -621,7 +576,33 @@ static const char *panel_replay_dsc_support_str(enum intel_panel_replay_dsc_supp
> };
> }
>
> -static void _panel_replay_init_dpcd(struct intel_dp *intel_dp)
> +static void _panel_replay_compute_su_granularity(struct intel_dp *intel_dp,
> + struct intel_connector *connector)
> +{
> + u16 w;
> + u8 y;
> +
> + if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
> + DP_PANEL_REPLAY_SU_GRANULARITY_REQUIRED)) {
> + w = 4;
> + y = 4;
> + goto exit;
> + }
> +
> + /*
> + * Spec says that if the value read is 0 the default granularity should
> + * be used instead.
> + */
> + w = intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_X_GRANULARITY)] ? : 4;
The DP_PANEL_REPLAY_CAP_X_GRANULARITY field is 2 bytes in size. Here the
DPCD value should be converted (explicitly) with le16_to_cpu() as above.
> +
> + y = intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_Y_GRANULARITY)] ? : 1;
> +
> +exit:
> + connector->dp.panel_replay_caps.su_w_granularity = w;
> + connector->dp.panel_replay_caps.su_y_granularity = y;
> +}
> +
> +static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
> {
> struct intel_display *display = to_intel_display(intel_dp);
> int ret;
> @@ -657,9 +638,12 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp)
> intel_dp->psr.sink_panel_replay_support = true;
>
> if (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
> - DP_PANEL_REPLAY_SU_SUPPORT)
> + DP_PANEL_REPLAY_SU_SUPPORT) {
> intel_dp->psr.sink_panel_replay_su_support = true;
>
> + _panel_replay_compute_su_granularity(intel_dp, connector);
> + }
> +
> intel_dp->psr.sink_panel_replay_dsc_support = compute_pr_dsc_support(intel_dp);
>
> drm_dbg_kms(display->drm,
> @@ -669,7 +653,7 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp)
> panel_replay_dsc_support_str(intel_dp->psr.sink_panel_replay_dsc_support));
> }
>
> -static void _psr_init_dpcd(struct intel_dp *intel_dp)
> +static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
> {
> struct intel_display *display = to_intel_display(intel_dp);
> int ret;
> @@ -722,17 +706,16 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp)
> drm_dbg_kms(display->drm, "PSR2 %ssupported\n",
> intel_dp->psr.sink_psr2_support ? "" : "not ");
> }
> +
> + if (intel_dp->psr.sink_psr2_support)
> + _psr_compute_su_granularity(intel_dp, connector);
> }
>
> -void intel_psr_init_dpcd(struct intel_dp *intel_dp)
> +void intel_psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
> {
> - _psr_init_dpcd(intel_dp);
> + _psr_init_dpcd(intel_dp, connector);
>
> - _panel_replay_init_dpcd(intel_dp);
> -
> - if (intel_dp->psr.sink_psr2_support ||
> - intel_dp->psr.sink_panel_replay_su_support)
> - intel_dp_get_su_granularity(intel_dp);
> + _panel_replay_init_dpcd(intel_dp, connector);
> }
>
> static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
> @@ -1311,24 +1294,32 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
> }
>
> static bool psr2_granularity_check(struct intel_dp *intel_dp,
> - struct intel_crtc_state *crtc_state)
> + struct intel_crtc_state *crtc_state,
> + struct drm_connector_state *conn_state)
Nit: I'd keep the parameter list as short as possible, by dropping
intel_dp and getting it from the connector with intel_attached_dp() in
this function.
> {
> struct intel_display *display = to_intel_display(intel_dp);
> + struct intel_connector *connector = to_intel_connector(conn_state->connector);
> const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
> const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
> const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
> u16 y_granularity = 0;
> + u16 sink_y_granularity = crtc_state->has_panel_replay ?
> + connector->dp.panel_replay_caps.su_y_granularity :
> + connector->dp.psr_caps.su_y_granularity;
> + u16 sink_w_granularity = crtc_state->has_panel_replay ?
> + connector->dp.panel_replay_caps.su_w_granularity :
> + connector->dp.psr_caps.su_w_granularity;
>
> /* PSR2 HW only send full lines so we only need to validate the width */
> - if (crtc_hdisplay % intel_dp->psr.su_w_granularity)
> + if (crtc_hdisplay % sink_w_granularity)
> return false;
>
> - if (crtc_vdisplay % intel_dp->psr.su_y_granularity)
> + if (crtc_vdisplay % sink_y_granularity)
> return false;
>
> /* HW tracking is only aligned to 4 lines */
> if (!crtc_state->enable_psr2_sel_fetch)
> - return intel_dp->psr.su_y_granularity == 4;
> + return sink_y_granularity == 4;
>
> /*
> * adl_p and mtl platforms have 1 line granularity.
> @@ -1336,11 +1327,11 @@ static bool psr2_granularity_check(struct intel_dp *intel_dp,
> * to match sink requirement if multiple of 4.
> */
> if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14)
> - y_granularity = intel_dp->psr.su_y_granularity;
> - else if (intel_dp->psr.su_y_granularity <= 2)
> + y_granularity = sink_y_granularity;
> + else if (sink_y_granularity <= 2)
> y_granularity = 4;
> - else if ((intel_dp->psr.su_y_granularity % 4) == 0)
> - y_granularity = intel_dp->psr.su_y_granularity;
> + else if ((sink_y_granularity % 4) == 0)
> + y_granularity = sink_y_granularity;
>
> if (y_granularity == 0 || crtc_vdisplay % y_granularity)
> return false;
> @@ -1628,7 +1619,8 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
> }
>
> static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
> - struct intel_crtc_state *crtc_state)
> + struct intel_crtc_state *crtc_state,
> + struct drm_connector_state *conn_state)
Here as well I'd drop intel_dp.
With the above fixed:
Reviewed-by: Imre Deak <imre.deak@intel.com>
> {
> struct intel_display *display = to_intel_display(intel_dp);
>
> @@ -1677,7 +1669,7 @@ static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
> goto unsupported;
> }
>
> - if (!psr2_granularity_check(intel_dp, crtc_state)) {
> + if (!psr2_granularity_check(intel_dp, crtc_state, conn_state)) {
> drm_dbg_kms(display->drm,
> "Selective update not enabled, SU granularity not compatible\n");
> goto unsupported;
> @@ -1872,7 +1864,8 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
> if (!crtc_state->has_psr)
> return;
>
> - crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp, crtc_state);
> + crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp, crtc_state,
> + conn_state);
> }
>
> void intel_psr_get_config(struct intel_encoder *encoder,
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
> index 620b359288326..688ca3e73cdda 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -28,7 +28,7 @@ struct intel_plane_state;
> bool intel_encoder_can_psr(struct intel_encoder *encoder);
> bool intel_psr_needs_aux_io_power(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state);
> -void intel_psr_init_dpcd(struct intel_dp *intel_dp);
> +void intel_psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector);
> void intel_psr_panel_replay_enable_sink(struct intel_dp *intel_dp);
> void intel_psr_pre_plane_update(struct intel_atomic_state *state,
> struct intel_crtc *crtc);
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 3/8] drm/i915/psr: Compute Panel Replay/Adaptive coexistence behavior
2025-11-21 11:16 ` [PATCH 3/8] drm/i915/psr: Compute Panel Replay/Adaptive coexistence behavior Jouni Högander
2025-11-21 11:24 ` Jani Nikula
@ 2025-12-01 10:28 ` Imre Deak
1 sibling, 0 replies; 25+ messages in thread
From: Imre Deak @ 2025-12-01 10:28 UTC (permalink / raw)
To: Jouni Högander; +Cc: intel-gfx, intel-xe
On Fri, Nov 21, 2025 at 01:16:50PM +0200, Jouni Högander wrote:
> Currently we are checking Panel Replay capability DPCD register in
> intel_alpm.c and writing PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU
> and PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE in PR_ALPM_CTL
> register base on the informaion. Instead of directly accessing
> intel_dp->pr_dpcd compute the behavior during psr_compute_config and store
> it in intel_crtc_state.
>
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_alpm.c | 6 ++---
> .../drm/i915/display/intel_display_types.h | 2 ++
> drivers/gpu/drm/i915/display/intel_psr.c | 22 +++++++++++++++----
> 3 files changed, 22 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 6372f533f65b5..7ce8c674bb030 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -326,11 +326,9 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
> if (intel_dp->as_sdp_supported) {
> u32 pr_alpm_ctl = PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
>
> - if (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
> - DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP)
> + if (crtc_state->link_off_after_as_sdp_when_pr_active)
> pr_alpm_ctl |= PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU;
> - if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
> - DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR))
> + if (crtc_state->disable_as_sdp_when_pr_active)
> pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
>
> intel_de_write(display, PR_ALPM_CTL(display, cpu_transcoder),
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index f39d62aa99246..d8a222689a35b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1161,6 +1161,8 @@ struct intel_crtc_state {
> bool enable_psr2_su_region_et;
> bool req_psr2_sdp_prior_scanline;
> bool has_panel_replay;
> + bool link_off_after_as_sdp_when_pr_active;
> + bool disable_as_sdp_when_pr_active;
I agree with Jani that moving the PSR/Panel Replay fields to a substruct
would make things clearer. That's a bigger change, so I presume it could
be also a follow-up.
> bool wm_level_disabled;
> bool pkg_c_latency_used;
> /* Only used for state verification. */
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 4c5883bed612b..9d2ba39423826 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1715,10 +1715,21 @@ static bool _psr_compute_config(struct intel_dp *intel_dp,
> return true;
> }
>
> -static bool
> -_panel_replay_compute_config(struct intel_dp *intel_dp,
> - struct intel_crtc_state *crtc_state,
> - const struct drm_connector_state *conn_state)
> +static bool compute_link_off_after_as_sdp_when_pr_active(struct intel_dp *intel_dp)
> +{
> + return (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
> + DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP);
> +}
> +
> +static bool compute_disable_as_sdp_when_pr_active(struct intel_dp *intel_dp)
> +{
> + return !(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
> + DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR);
> +}
Nit: Aren't the above functions simple enough to inline them? Or do they
get more complicated later?
> +
> +static bool _panel_replay_compute_config(struct intel_dp *intel_dp,
> + struct intel_crtc_state *crtc_state,
> + const struct drm_connector_state *conn_state)
Nit: I'd drop intel_dp as mentioned earlier.
Regardless, the patch looks ok:
Reviewed-by: Imre Deak <imre.deak@intel.com>
> {
> struct intel_display *display = to_intel_display(intel_dp);
> struct intel_connector *connector =
> @@ -1747,6 +1758,9 @@ _panel_replay_compute_config(struct intel_dp *intel_dp,
> return false;
> }
>
> + crtc_state->link_off_after_as_sdp_when_pr_active = compute_link_off_after_as_sdp_when_pr_active(intel_dp);
> + crtc_state->disable_as_sdp_when_pr_active = compute_disable_as_sdp_when_pr_active(intel_dp);
> +
> if (!intel_dp_is_edp(intel_dp))
> return true;
>
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 4/8] drm/i915/psr: Move pr_dpcd and psr_dpcd to intel_connector
2025-11-21 11:16 ` [PATCH 4/8] drm/i915/psr: Move pr_dpcd and psr_dpcd to intel_connector Jouni Högander
@ 2025-12-01 10:45 ` Imre Deak
0 siblings, 0 replies; 25+ messages in thread
From: Imre Deak @ 2025-12-01 10:45 UTC (permalink / raw)
To: Jouni Högander; +Cc: intel-gfx, intel-xe
On Fri, Nov 21, 2025 at 01:16:51PM +0200, Jouni Högander wrote:
> As a preparation for MST Panel Replay we need to move Panel Replay sink
> related data into intel_connector. Move pr_dpcd as well into
> intel_connector. Generally this is more correct place for this data so move
> psr_dpcd as well.
>
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
> .../drm/i915/display/intel_display_types.h | 6 +-
> drivers/gpu/drm/i915/display/intel_psr.c | 85 ++++++++++---------
> 2 files changed, 49 insertions(+), 42 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index d8a222689a35b..8587d2c527f72 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -548,6 +548,9 @@ struct intel_connector {
> struct {
> struct drm_dp_aux *dsc_decompression_aux;
> u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
> + u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
I'd add this to the psr_caps substruct you added earlier in the
patchset. Yes, the dsc fields could be also in their own substruct, but
all the PSR / Panel Replay could be added accordingly already now.
> + u8 pr_dpcd[DP_PANEL_REPLAY_CAP_SIZE];
> +#define INTEL_PR_DPCD_INDEX(pr_dpcd_register) ((pr_dpcd_register) - DP_PANEL_REPLAY_CAP_SUPPORT)
Similarly, I'd add this to the panel_replay_caps substruct.
> u8 fec_capability;
>
> u8 dsc_hblank_expansion_quirk:1;
> @@ -1768,9 +1771,6 @@ struct intel_dp {
> bool needs_modeset_retry;
> bool use_max_params;
> u8 dpcd[DP_RECEIVER_CAP_SIZE];
> - u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
> - u8 pr_dpcd[DP_PANEL_REPLAY_CAP_SIZE];
> -#define INTEL_PR_DPCD_INDEX(pr_dpcd_register) ((pr_dpcd_register) - DP_PANEL_REPLAY_CAP_SUPPORT)
>
> u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
> u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 9d2ba39423826..b488be8c917dc 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -506,7 +506,7 @@ static void _psr_compute_su_granularity(struct intel_dp *intel_dp,
> * If sink don't have specific granularity requirements set legacy
> * ones.
> */
> - if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) {
> + if (!(connector->dp.psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) {
> /* As PSR2 HW sends full lines, we do not care about x granularity */
> w = 4;
> y = 4;
> @@ -539,12 +539,12 @@ static void _psr_compute_su_granularity(struct intel_dp *intel_dp,
> }
>
> static enum intel_panel_replay_dsc_support
> -compute_pr_dsc_support(struct intel_dp *intel_dp)
> +compute_pr_dsc_support(struct intel_connector *connector)
> {
> u8 pr_dsc_mode;
> u8 val;
>
> - val = intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)];
> + val = connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)];
> pr_dsc_mode = REG_FIELD_GET8(DP_PANEL_REPLAY_DSC_DECODE_CAPABILITY_IN_PR_MASK, val);
>
> switch (pr_dsc_mode) {
> @@ -582,7 +582,7 @@ static void _panel_replay_compute_su_granularity(struct intel_dp *intel_dp,
> u16 w;
> u8 y;
>
> - if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
> + if (!(connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
> DP_PANEL_REPLAY_SU_GRANULARITY_REQUIRED)) {
> w = 4;
> y = 4;
> @@ -593,9 +593,9 @@ static void _panel_replay_compute_su_granularity(struct intel_dp *intel_dp,
> * Spec says that if the value read is 0 the default granularity should
> * be used instead.
> */
> - w = intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_X_GRANULARITY)] ? : 4;
> + w = connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_X_GRANULARITY)] ? : 4;
This needs the field size and le16_to_cpu() fix mentioned earlier.
>
> - y = intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_Y_GRANULARITY)] ? : 1;
> + y = connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_Y_GRANULARITY)] ? : 1;
>
> exit:
> connector->dp.panel_replay_caps.su_w_granularity = w;
> @@ -612,11 +612,11 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_conn
> return;
>
> ret = drm_dp_dpcd_read_data(&intel_dp->aux, DP_PANEL_REPLAY_CAP_SUPPORT,
> - &intel_dp->pr_dpcd, sizeof(intel_dp->pr_dpcd));
> + &connector->dp.pr_dpcd, sizeof(connector->dp.pr_dpcd));
> if (ret < 0)
> return;
>
> - if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
> + if (!(connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
> DP_PANEL_REPLAY_SUPPORT))
> return;
>
> @@ -627,7 +627,7 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_conn
> return;
> }
>
> - if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
> + if (!(connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
> DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)) {
> drm_dbg_kms(display->drm,
> "Panel doesn't support early transport, eDP Panel Replay not possible\n");
> @@ -637,14 +637,14 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_conn
>
> intel_dp->psr.sink_panel_replay_support = true;
>
> - if (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
> + if (connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
> DP_PANEL_REPLAY_SU_SUPPORT) {
> intel_dp->psr.sink_panel_replay_su_support = true;
>
> _panel_replay_compute_su_granularity(intel_dp, connector);
> }
>
> - intel_dp->psr.sink_panel_replay_dsc_support = compute_pr_dsc_support(intel_dp);
> + intel_dp->psr.sink_panel_replay_dsc_support = compute_pr_dsc_support(connector);
>
> drm_dbg_kms(display->drm,
> "Panel replay %sis supported by panel (in DSC mode: %s)\n",
> @@ -658,16 +658,16 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *co
> struct intel_display *display = to_intel_display(intel_dp);
> int ret;
>
> - ret = drm_dp_dpcd_read_data(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
> - sizeof(intel_dp->psr_dpcd));
> + ret = drm_dp_dpcd_read_data(&intel_dp->aux, DP_PSR_SUPPORT, connector->dp.psr_dpcd,
> + sizeof(connector->dp.psr_dpcd));
> if (ret < 0)
> return;
>
> - if (!intel_dp->psr_dpcd[0])
> + if (!connector->dp.psr_dpcd[0])
> return;
>
> drm_dbg_kms(display->drm, "eDP panel supports PSR version %x\n",
> - intel_dp->psr_dpcd[0]);
> + connector->dp.psr_dpcd[0]);
>
> if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) {
> drm_dbg_kms(display->drm,
> @@ -686,8 +686,8 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *co
> intel_dp_get_sink_sync_latency(intel_dp);
>
> if (DISPLAY_VER(display) >= 9 &&
> - intel_dp->psr_dpcd[0] >= DP_PSR2_WITH_Y_COORD_IS_SUPPORTED) {
> - bool y_req = intel_dp->psr_dpcd[1] &
> + connector->dp.psr_dpcd[0] >= DP_PSR2_WITH_Y_COORD_IS_SUPPORTED) {
> + bool y_req = connector->dp.psr_dpcd[1] &
> DP_PSR2_SU_Y_COORDINATE_REQUIRED;
>
> /*
> @@ -755,7 +755,8 @@ static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
> aux_ctl);
> }
>
> -static bool psr2_su_region_et_valid(struct intel_dp *intel_dp, bool panel_replay)
> +static bool psr2_su_region_et_valid(struct intel_dp *intel_dp, struct intel_connector *connector,
> + bool panel_replay)
Nit: intel_dp could be dropped here. Similarly in the functions below to
which you need to pass connector or conn_state.
Regardless of the nit, the patch looks ok:
Reviewed-by: Imre Deak <imre.deak@intel.com>
> {
> struct intel_display *display = to_intel_display(intel_dp);
>
> @@ -764,9 +765,9 @@ static bool psr2_su_region_et_valid(struct intel_dp *intel_dp, bool panel_replay
> return false;
>
> return panel_replay ?
> - intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
> + connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
> DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT :
> - intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED;
> + connector->dp.psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED;
> }
>
> static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
> @@ -1369,16 +1370,18 @@ static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_d
> }
>
> static int intel_psr_entry_setup_frames(struct intel_dp *intel_dp,
> + struct drm_connector_state *conn_state,
> const struct drm_display_mode *adjusted_mode)
> {
> struct intel_display *display = to_intel_display(intel_dp);
> - int psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
> + struct intel_connector *connector = to_intel_connector(conn_state->connector);
> + int psr_setup_time = drm_dp_psr_setup_time(connector->dp.psr_dpcd);
> int entry_setup_frames = 0;
>
> if (psr_setup_time < 0) {
> drm_dbg_kms(display->drm,
> "PSR condition failed: Invalid PSR setup time (0x%02x)\n",
> - intel_dp->psr_dpcd[1]);
> + connector->dp.psr_dpcd[1]);
> return -ETIME;
> }
>
> @@ -1623,6 +1626,7 @@ static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
> struct drm_connector_state *conn_state)
> {
> struct intel_display *display = to_intel_display(intel_dp);
> + struct intel_connector *connector = to_intel_connector(conn_state->connector);
>
> if (HAS_PSR2_SEL_FETCH(display) &&
> !intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) &&
> @@ -1676,7 +1680,7 @@ static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
> }
>
> crtc_state->enable_psr2_su_region_et =
> - psr2_su_region_et_valid(intel_dp, crtc_state->has_panel_replay);
> + psr2_su_region_et_valid(intel_dp, connector, crtc_state->has_panel_replay);
>
> return true;
>
> @@ -1686,7 +1690,8 @@ static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
> }
>
> static bool _psr_compute_config(struct intel_dp *intel_dp,
> - struct intel_crtc_state *crtc_state)
> + struct intel_crtc_state *crtc_state,
> + struct drm_connector_state *conn_state)
> {
> struct intel_display *display = to_intel_display(intel_dp);
> const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> @@ -1701,7 +1706,7 @@ static bool _psr_compute_config(struct intel_dp *intel_dp,
> if (crtc_state->vrr.enable)
> return false;
>
> - entry_setup_frames = intel_psr_entry_setup_frames(intel_dp, adjusted_mode);
> + entry_setup_frames = intel_psr_entry_setup_frames(intel_dp, conn_state, adjusted_mode);
>
> if (entry_setup_frames >= 0) {
> intel_dp->psr.entry_setup_frames = entry_setup_frames;
> @@ -1715,15 +1720,15 @@ static bool _psr_compute_config(struct intel_dp *intel_dp,
> return true;
> }
>
> -static bool compute_link_off_after_as_sdp_when_pr_active(struct intel_dp *intel_dp)
> +static bool compute_link_off_after_as_sdp_when_pr_active(struct intel_connector *connector)
> {
> - return (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
> + return (connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
> DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP);
> }
>
> -static bool compute_disable_as_sdp_when_pr_active(struct intel_dp *intel_dp)
> +static bool compute_disable_as_sdp_when_pr_active(struct intel_connector *connector)
> {
> - return !(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
> + return !(connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
> DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR);
> }
>
> @@ -1758,8 +1763,8 @@ static bool _panel_replay_compute_config(struct intel_dp *intel_dp,
> return false;
> }
>
> - crtc_state->link_off_after_as_sdp_when_pr_active = compute_link_off_after_as_sdp_when_pr_active(intel_dp);
> - crtc_state->disable_as_sdp_when_pr_active = compute_disable_as_sdp_when_pr_active(intel_dp);
> + crtc_state->link_off_after_as_sdp_when_pr_active = compute_link_off_after_as_sdp_when_pr_active(connector);
> + crtc_state->disable_as_sdp_when_pr_active = compute_disable_as_sdp_when_pr_active(connector);
>
> if (!intel_dp_is_edp(intel_dp))
> return true;
> @@ -1873,7 +1878,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
> conn_state);
>
> crtc_state->has_psr = crtc_state->has_panel_replay ? true :
> - _psr_compute_config(intel_dp, crtc_state);
> + _psr_compute_config(intel_dp, crtc_state, conn_state);
>
> if (!crtc_state->has_psr)
> return;
> @@ -4123,6 +4128,7 @@ psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)
> }
>
> static void intel_psr_sink_capability(struct intel_dp *intel_dp,
> + struct intel_connector *connector,
> struct seq_file *m)
> {
> struct intel_psr *psr = &intel_dp->psr;
> @@ -4131,15 +4137,15 @@ static void intel_psr_sink_capability(struct intel_dp *intel_dp,
> str_yes_no(psr->sink_support));
>
> if (psr->sink_support)
> - seq_printf(m, " [0x%02x]", intel_dp->psr_dpcd[0]);
> - if (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED)
> + seq_printf(m, " [0x%02x]", connector->dp.psr_dpcd[0]);
> + if (connector->dp.psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED)
> seq_printf(m, " (Early Transport)");
> seq_printf(m, ", Panel Replay = %s", str_yes_no(psr->sink_panel_replay_support));
> seq_printf(m, ", Panel Replay Selective Update = %s",
> str_yes_no(psr->sink_panel_replay_su_support));
> seq_printf(m, ", Panel Replay DSC support = %s",
> panel_replay_dsc_support_str(psr->sink_panel_replay_dsc_support));
> - if (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
> + if (connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
> DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)
> seq_printf(m, " (Early Transport)");
> seq_printf(m, "\n");
> @@ -4177,7 +4183,8 @@ static void intel_psr_print_mode(struct intel_dp *intel_dp,
> seq_printf(m, " %s\n", psr->no_psr_reason);
> }
>
> -static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
> +static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp,
> + struct intel_connector *connector)
> {
> struct intel_display *display = to_intel_display(intel_dp);
> enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
> @@ -4186,7 +4193,7 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
> bool enabled;
> u32 val, psr2_ctl;
>
> - intel_psr_sink_capability(intel_dp, m);
> + intel_psr_sink_capability(intel_dp, connector, m);
>
> if (!(psr->sink_support || psr->sink_panel_replay_support))
> return 0;
> @@ -4302,7 +4309,7 @@ static int i915_edp_psr_status_show(struct seq_file *m, void *data)
> if (!intel_dp)
> return -ENODEV;
>
> - return intel_psr_status(m, intel_dp);
> + return intel_psr_status(m, intel_dp, intel_dp->attached_connector);
> }
> DEFINE_SHOW_ATTRIBUTE(i915_edp_psr_status);
>
> @@ -4436,7 +4443,7 @@ static int i915_psr_status_show(struct seq_file *m, void *data)
> struct intel_connector *connector = m->private;
> struct intel_dp *intel_dp = intel_attached_dp(connector);
>
> - return intel_psr_status(m, intel_dp);
> + return intel_psr_status(m, intel_dp, connector);
> }
> DEFINE_SHOW_ATTRIBUTE(i915_psr_status);
>
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 5/8] drm/i915/psr: Clear pr_dpcd as well on disconnect
2025-11-21 11:16 ` [PATCH 5/8] drm/i915/psr: Clear pr_dpcd as well on disconnect Jouni Högander
@ 2025-12-01 10:53 ` Imre Deak
2025-12-01 11:23 ` Hogander, Jouni
0 siblings, 1 reply; 25+ messages in thread
From: Imre Deak @ 2025-12-01 10:53 UTC (permalink / raw)
To: Jouni Högander; +Cc: intel-gfx, intel-xe
On Fri, Nov 21, 2025 at 01:16:52PM +0200, Jouni Högander wrote:
> Currently we are leaving pr_dpcd containing Panel Replay capability DPCD
> registers as it is on disconnect. Clear it as well on disconnect.
>
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 62808cd35f5f2..7195c408d93ab 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -6050,6 +6050,7 @@ intel_dp_detect(struct drm_connector *_connector,
> if (status == connector_status_disconnected) {
> intel_dp_test_reset(intel_dp);
> memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd));
> + memset(connector->dp.pr_dpcd, 0, sizeof(connector->dp.pr_dpcd));
What about psr_dpcd?
All these resetting of the caps cause a problem if the connector needs
to be modeset after the sink is disconnected (since then the state
computation for the connector will fail seeing these caps being reset).
Instead the caps should be kept intact here, resetting/reiniting them
only when a new sink is connected. Since this is a pre-existing issue,
could you add for now a corrsponding FIXME: comment in this patch?
> intel_dp->psr.sink_panel_replay_support = false;
> intel_dp->psr.sink_panel_replay_su_support = false;
> intel_dp->psr.sink_panel_replay_dsc_support =
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 6/8] drm/i915/psr: Move Panel Replay DSC sink support data to intel_connector
2025-11-21 11:16 ` [PATCH 6/8] drm/i915/psr: Move Panel Replay DSC sink support data to intel_connector Jouni Högander
@ 2025-12-01 10:55 ` Imre Deak
0 siblings, 0 replies; 25+ messages in thread
From: Imre Deak @ 2025-12-01 10:55 UTC (permalink / raw)
To: Jouni Högander; +Cc: intel-gfx, intel-xe
On Fri, Nov 21, 2025 at 01:16:53PM +0200, Jouni Högander wrote:
> As a preparation for MST Panel Replay we need to move Panel Replay sink
> related data into intel_connector. Move Panel Replay DSC sink support data
> as well into intel_connector.
>
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> .../gpu/drm/i915/display/intel_display_types.h | 15 ++++++++-------
> drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
> drivers/gpu/drm/i915/display/intel_psr.c | 13 +++++++------
> 3 files changed, 16 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 8587d2c527f72..e1d47496ea4de 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -509,6 +509,12 @@ struct intel_hdcp {
> bool force_hdcp14;
> };
>
> +enum intel_panel_replay_dsc_support {
> + INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED,
> + INTEL_DP_PANEL_REPLAY_DSC_FULL_FRAME_ONLY,
> + INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE,
> +};
> +
> struct intel_connector {
> struct drm_connector base;
> /*
> @@ -566,6 +572,8 @@ struct intel_connector {
> } dsc_branch_caps;
>
> struct {
> + enum intel_panel_replay_dsc_support dsc_support;
> +
> u16 su_w_granularity;
> u16 su_y_granularity;
> } panel_replay_caps;
> @@ -967,12 +975,6 @@ struct intel_csc_matrix {
> u16 postoff[3];
> };
>
> -enum intel_panel_replay_dsc_support {
> - INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED,
> - INTEL_DP_PANEL_REPLAY_DSC_FULL_FRAME_ONLY,
> - INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE,
> -};
> -
> struct scaler_filter_coeff {
> u16 sign;
> u16 exp;
> @@ -1744,7 +1746,6 @@ struct intel_psr {
> bool source_panel_replay_support;
> bool sink_panel_replay_support;
> bool sink_panel_replay_su_support;
> - enum intel_panel_replay_dsc_support sink_panel_replay_dsc_support;
> bool panel_replay_enabled;
> u32 dc3co_exitline;
> u32 dc3co_exit_delay;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 7195c408d93ab..d32f476c288c1 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -6053,7 +6053,7 @@ intel_dp_detect(struct drm_connector *_connector,
> memset(connector->dp.pr_dpcd, 0, sizeof(connector->dp.pr_dpcd));
> intel_dp->psr.sink_panel_replay_support = false;
> intel_dp->psr.sink_panel_replay_su_support = false;
> - intel_dp->psr.sink_panel_replay_dsc_support =
> + connector->dp.panel_replay_caps.dsc_support =
> INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED;
>
> intel_dp_mst_disconnect(intel_dp);
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index b488be8c917dc..4bae39f745ea0 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -644,13 +644,13 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_conn
> _panel_replay_compute_su_granularity(intel_dp, connector);
> }
>
> - intel_dp->psr.sink_panel_replay_dsc_support = compute_pr_dsc_support(connector);
> + connector->dp.panel_replay_caps.dsc_support = compute_pr_dsc_support(connector);
>
> drm_dbg_kms(display->drm,
> "Panel replay %sis supported by panel (in DSC mode: %s)\n",
> intel_dp->psr.sink_panel_replay_su_support ?
> "selective_update " : "",
> - panel_replay_dsc_support_str(intel_dp->psr.sink_panel_replay_dsc_support));
> + panel_replay_dsc_support_str(connector->dp.panel_replay_caps.dsc_support));
> }
>
> static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
> @@ -1659,7 +1659,7 @@ static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
> goto unsupported;
>
> if (intel_dsc_enabled_on_link(crtc_state) &&
> - intel_dp->psr.sink_panel_replay_dsc_support !=
> + connector->dp.panel_replay_caps.dsc_support !=
> INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE) {
> drm_dbg_kms(display->drm,
> "Selective update with Panel Replay not enabled because it's not supported with DSC\n");
> @@ -1756,7 +1756,7 @@ static bool _panel_replay_compute_config(struct intel_dp *intel_dp,
> }
>
> if (intel_dsc_enabled_on_link(crtc_state) &&
> - intel_dp->psr.sink_panel_replay_dsc_support ==
> + connector->dp.panel_replay_caps.dsc_support ==
> INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED) {
> drm_dbg_kms(display->drm,
> "Panel Replay not enabled because it's not supported with DSC\n");
> @@ -1841,6 +1841,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
> struct drm_connector_state *conn_state)
> {
> struct intel_display *display = to_intel_display(intel_dp);
> + struct intel_connector *connector = to_intel_connector(conn_state->connector);
> const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
>
> if (!psr_global_enabled(intel_dp)) {
> @@ -1872,7 +1873,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
> }
>
> /* Only used for state verification. */
> - crtc_state->panel_replay_dsc_support = intel_dp->psr.sink_panel_replay_dsc_support;
> + crtc_state->panel_replay_dsc_support = connector->dp.panel_replay_caps.dsc_support;
> crtc_state->has_panel_replay = _panel_replay_compute_config(intel_dp,
> crtc_state,
> conn_state);
> @@ -4144,7 +4145,7 @@ static void intel_psr_sink_capability(struct intel_dp *intel_dp,
> seq_printf(m, ", Panel Replay Selective Update = %s",
> str_yes_no(psr->sink_panel_replay_su_support));
> seq_printf(m, ", Panel Replay DSC support = %s",
> - panel_replay_dsc_support_str(psr->sink_panel_replay_dsc_support));
> + panel_replay_dsc_support_str(connector->dp.panel_replay_caps.dsc_support));
> if (connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
> DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)
> seq_printf(m, " (Early Transport)");
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 7/8] drm/i915/psr: Move sink PSR and Panel Replay booleans to intel_connector
2025-11-21 11:16 ` [PATCH 7/8] drm/i915/psr: Move sink PSR and Panel Replay booleans " Jouni Högander
@ 2025-12-01 10:59 ` Imre Deak
0 siblings, 0 replies; 25+ messages in thread
From: Imre Deak @ 2025-12-01 10:59 UTC (permalink / raw)
To: Jouni Högander; +Cc: intel-gfx, intel-xe
On Fri, Nov 21, 2025 at 01:16:54PM +0200, Jouni Högander wrote:
> As a preparation for MST Panel Replay we need to move Panel Replay sink
> related data into intel_connector. Move sink support booleans as well
> into intel_connector. Generally this is more correct place for this data so
> move PSR versions as well.
>
> Still sink_support and sink_panel_replay_support are kept to keep CAN_PSR
> and CAN_PANEL_REPLAY macros.
Would be good to mention what's the plan with these macros (they'll take
a connector instead of an intel_dp pointer?)
>
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
> .../drm/i915/display/intel_display_types.h | 7 ++-
> drivers/gpu/drm/i915/display/intel_dp.c | 4 +-
> drivers/gpu/drm/i915/display/intel_psr.c | 44 +++++++++++--------
> 3 files changed, 33 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index e1d47496ea4de..04d21333130f9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -572,6 +572,8 @@ struct intel_connector {
> } dsc_branch_caps;
>
> struct {
> + bool support;
> + bool su_support;
> enum intel_panel_replay_dsc_support dsc_support;
>
> u16 su_w_granularity;
> @@ -579,6 +581,9 @@ struct intel_connector {
> } panel_replay_caps;
>
> struct {
> + bool support;
> + bool su_support;
> +
> u16 su_w_granularity;
> u16 su_y_granularity;
> } psr_caps;
> @@ -1729,7 +1734,6 @@ struct intel_psr {
> bool active;
> struct work_struct work;
> unsigned int busy_frontbuffer_bits;
> - bool sink_psr2_support;
> bool link_standby;
> bool sel_update_enabled;
> bool psr2_sel_fetch_enabled;
> @@ -1745,7 +1749,6 @@ struct intel_psr {
> u16 su_y_granularity;
> bool source_panel_replay_support;
> bool sink_panel_replay_support;
> - bool sink_panel_replay_su_support;
> bool panel_replay_enabled;
> u32 dc3co_exitline;
> u32 dc3co_exit_delay;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index d32f476c288c1..2452302937c73 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -6052,10 +6052,12 @@ intel_dp_detect(struct drm_connector *_connector,
> memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd));
> memset(connector->dp.pr_dpcd, 0, sizeof(connector->dp.pr_dpcd));
> intel_dp->psr.sink_panel_replay_support = false;
> - intel_dp->psr.sink_panel_replay_su_support = false;
> + connector->dp.panel_replay_caps.support = false;
> + connector->dp.panel_replay_caps.su_support = false;
What about resetting PSR counterparts?
> connector->dp.panel_replay_caps.dsc_support =
> INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED;
>
> +
Extra w/s.
> intel_dp_mst_disconnect(intel_dp);
>
> intel_dp_tunnel_disconnect(intel_dp);
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 4bae39f745ea0..e6268d692f89d 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -635,11 +635,12 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_conn
> }
> }
>
> + connector->dp.panel_replay_caps.support = true;
> intel_dp->psr.sink_panel_replay_support = true;
>
> if (connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
> DP_PANEL_REPLAY_SU_SUPPORT) {
> - intel_dp->psr.sink_panel_replay_su_support = true;
> + connector->dp.panel_replay_caps.su_support = true;
>
> _panel_replay_compute_su_granularity(intel_dp, connector);
> }
> @@ -648,7 +649,7 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_conn
>
> drm_dbg_kms(display->drm,
> "Panel replay %sis supported by panel (in DSC mode: %s)\n",
> - intel_dp->psr.sink_panel_replay_su_support ?
> + connector->dp.panel_replay_caps.su_support ?
> "selective_update " : "",
> panel_replay_dsc_support_str(connector->dp.panel_replay_caps.dsc_support));
> }
> @@ -681,7 +682,9 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *co
> return;
> }
>
> + connector->dp.psr_caps.support = true;
> intel_dp->psr.sink_support = true;
> +
> intel_dp->psr.sink_sync_latency =
> intel_dp_get_sink_sync_latency(intel_dp);
>
> @@ -701,13 +704,13 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *co
> * Y-coordinate requirement panels we would need to enable
> * GTC first.
> */
> - intel_dp->psr.sink_psr2_support = y_req &&
> + connector->dp.psr_caps.su_support = y_req &&
> intel_alpm_aux_wake_supported(intel_dp);
> drm_dbg_kms(display->drm, "PSR2 %ssupported\n",
> - intel_dp->psr.sink_psr2_support ? "" : "not ");
> + connector->dp.psr_caps.su_support ? "" : "not ");
> }
>
> - if (intel_dp->psr.sink_psr2_support)
> + if (connector->dp.psr_caps.su_support)
> _psr_compute_su_granularity(intel_dp, connector);
> }
>
> @@ -1522,14 +1525,16 @@ static bool alpm_config_valid(struct intel_dp *intel_dp,
> }
>
> static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
> - struct intel_crtc_state *crtc_state)
> + struct intel_crtc_state *crtc_state,
> + struct drm_connector_state *conn_state)
> {
> struct intel_display *display = to_intel_display(intel_dp);
> + struct intel_connector *connector = to_intel_connector(conn_state->connector);
> int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
> int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
> int psr_max_h = 0, psr_max_v = 0, max_bpp = 0;
>
> - if (!intel_dp->psr.sink_psr2_support || display->params.enable_psr == 1)
> + if (!connector->dp.psr_caps.su_support || display->params.enable_psr == 1)
> return false;
>
> /* JSL and EHL only supports eDP 1.3 */
> @@ -1642,7 +1647,8 @@ static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
> goto unsupported;
> }
>
> - if (!crtc_state->has_panel_replay && !intel_psr2_config_valid(intel_dp, crtc_state))
> + if (!crtc_state->has_panel_replay && !intel_psr2_config_valid(intel_dp, crtc_state,
> + conn_state))
> goto unsupported;
>
> if (!_compute_psr2_sdp_prior_scanline_indication(intel_dp, crtc_state)) {
> @@ -1655,7 +1661,7 @@ static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
> if (DISPLAY_VER(display) < 14)
> goto unsupported;
>
> - if (!intel_dp->psr.sink_panel_replay_su_support)
> + if (!connector->dp.panel_replay_caps.su_support)
> goto unsupported;
>
> if (intel_dsc_enabled_on_link(crtc_state) &&
> @@ -1744,6 +1750,9 @@ static bool _panel_replay_compute_config(struct intel_dp *intel_dp,
> if (!CAN_PANEL_REPLAY(intel_dp))
> return false;
>
> + if (!connector->dp.panel_replay_caps.support)
> + return false;
> +
> if (!panel_replay_global_enabled(intel_dp)) {
> drm_dbg_kms(display->drm, "Panel Replay disabled by flag\n");
> return false;
> @@ -4128,22 +4137,19 @@ psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)
> seq_printf(m, "Source PSR/PanelReplay status: %s [0x%08x]\n", status, val);
> }
>
> -static void intel_psr_sink_capability(struct intel_dp *intel_dp,
> - struct intel_connector *connector,
> +static void intel_psr_sink_capability(struct intel_connector *connector,
> struct seq_file *m)
> {
> - struct intel_psr *psr = &intel_dp->psr;
> -
> seq_printf(m, "Sink support: PSR = %s",
> - str_yes_no(psr->sink_support));
> + str_yes_no(connector->dp.psr_caps.support));
>
> - if (psr->sink_support)
> + if (connector->dp.psr_caps.support)
> seq_printf(m, " [0x%02x]", connector->dp.psr_dpcd[0]);
> if (connector->dp.psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED)
> seq_printf(m, " (Early Transport)");
> - seq_printf(m, ", Panel Replay = %s", str_yes_no(psr->sink_panel_replay_support));
> + seq_printf(m, ", Panel Replay = %s", str_yes_no(connector->dp.panel_replay_caps.support));
> seq_printf(m, ", Panel Replay Selective Update = %s",
> - str_yes_no(psr->sink_panel_replay_su_support));
> + str_yes_no(connector->dp.panel_replay_caps.su_support));
> seq_printf(m, ", Panel Replay DSC support = %s",
> panel_replay_dsc_support_str(connector->dp.panel_replay_caps.dsc_support));
> if (connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
> @@ -4194,9 +4200,9 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp,
> bool enabled;
> u32 val, psr2_ctl;
>
> - intel_psr_sink_capability(intel_dp, connector, m);
> + intel_psr_sink_capability(connector, m);
>
> - if (!(psr->sink_support || psr->sink_panel_replay_support))
> + if (!(connector->dp.psr_caps.support || connector->dp.panel_replay_caps.support))
> return 0;
>
> wakeref = intel_display_rpm_get(display);
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 8/8] drm/i915/psr: Move sink_sync_latency to intel_connector
2025-11-21 11:16 ` [PATCH 8/8] drm/i915/psr: Move sink_sync_latency " Jouni Högander
@ 2025-12-01 11:03 ` Imre Deak
0 siblings, 0 replies; 25+ messages in thread
From: Imre Deak @ 2025-12-01 11:03 UTC (permalink / raw)
To: Jouni Högander; +Cc: intel-gfx, intel-xe
On Fri, Nov 21, 2025 at 01:16:55PM +0200, Jouni Högander wrote:
> As everything else related to PSR and Panel Replay capabilities are moved
> into intel_connector move sink_sync_latency as well.
>
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display_types.h | 3 ++-
> drivers/gpu/drm/i915/display/intel_psr.c | 8 ++++----
> 2 files changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 04d21333130f9..77e1948aef2ff 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -586,6 +586,8 @@ struct intel_connector {
>
> u16 su_w_granularity;
> u16 su_y_granularity;
> +
> + u8 sync_latency;
> } psr_caps;
> } dp;
>
> @@ -1740,7 +1742,6 @@ struct intel_psr {
> bool psr2_sel_fetch_cff_enabled;
> bool su_region_et_enabled;
> bool req_psr2_sdp_prior_scanline;
> - u8 sink_sync_latency;
> ktime_t last_entry_attempt;
> ktime_t last_exit;
> bool sink_not_reliable;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index e6268d692f89d..bbd1b0e8beecb 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -685,8 +685,7 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *co
> connector->dp.psr_caps.support = true;
> intel_dp->psr.sink_support = true;
>
> - intel_dp->psr.sink_sync_latency =
> - intel_dp_get_sink_sync_latency(intel_dp);
> + connector->dp.psr_caps.sync_latency = intel_dp_get_sink_sync_latency(intel_dp);
>
> if (DISPLAY_VER(display) >= 9 &&
> connector->dp.psr_dpcd[0] >= DP_PSR2_WITH_Y_COORD_IS_SUPPORTED) {
> @@ -911,7 +910,7 @@ static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
> * off-by-one issue that HW has in some cases.
> */
> idle_frames = max(6, connector->panel.vbt.psr.idle_frames);
> - idle_frames = max(idle_frames, intel_dp->psr.sink_sync_latency + 1);
> + idle_frames = max(idle_frames, connector->dp.psr_caps.sync_latency + 1);
>
> if (drm_WARN_ON(display->drm, idle_frames > 0xf))
> idle_frames = 0xf;
> @@ -1006,10 +1005,11 @@ static int psr2_block_count(struct intel_dp *intel_dp)
>
> static u8 frames_before_su_entry(struct intel_dp *intel_dp)
> {
> + struct intel_connector *connector = intel_dp->attached_connector;
> u8 frames_before_su_entry;
>
> frames_before_su_entry = max_t(u8,
> - intel_dp->psr.sink_sync_latency + 1,
> + connector->dp.psr_caps.sync_latency + 1,
> 2);
>
> /* Entry setup frames must be at least 1 less than frames before SU entry */
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 5/8] drm/i915/psr: Clear pr_dpcd as well on disconnect
2025-12-01 10:53 ` Imre Deak
@ 2025-12-01 11:23 ` Hogander, Jouni
2025-12-03 14:37 ` Imre Deak
0 siblings, 1 reply; 25+ messages in thread
From: Hogander, Jouni @ 2025-12-01 11:23 UTC (permalink / raw)
To: Deak, Imre
Cc: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
On Mon, 2025-12-01 at 12:53 +0200, Imre Deak wrote:
> On Fri, Nov 21, 2025 at 01:16:52PM +0200, Jouni Högander wrote:
> > Currently we are leaving pr_dpcd containing Panel Replay capability
> > DPCD
> > registers as it is on disconnect. Clear it as well on disconnect.
> >
> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_dp.c | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 62808cd35f5f2..7195c408d93ab 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -6050,6 +6050,7 @@ intel_dp_detect(struct drm_connector
> > *_connector,
> > if (status == connector_status_disconnected) {
> > intel_dp_test_reset(intel_dp);
> > memset(connector->dp.dsc_dpcd, 0,
> > sizeof(connector->dp.dsc_dpcd));
> > + memset(connector->dp.pr_dpcd, 0, sizeof(connector-
> > >dp.pr_dpcd));
>
> What about psr_dpcd?
PSR is only for eDP and can't be disconnected.
>
> All these resetting of the caps cause a problem if the connector
> needs
> to be modeset after the sink is disconnected (since then the state
> computation for the connector will fail seeing these caps being
> reset).
> Instead the caps should be kept intact here, resetting/reiniting them
> only when a new sink is connected. Since this is a pre-existing
> issue,
> could you add for now a corrsponding FIXME: comment in this patch?
Thank you for pointing this out. I will add the FIXME.
BR,
Jouni Högander
>
> > intel_dp->psr.sink_panel_replay_support = false;
> > intel_dp->psr.sink_panel_replay_su_support =
> > false;
> > intel_dp->psr.sink_panel_replay_dsc_support =
> > --
> > 2.43.0
> >
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 5/8] drm/i915/psr: Clear pr_dpcd as well on disconnect
2025-12-01 11:23 ` Hogander, Jouni
@ 2025-12-03 14:37 ` Imre Deak
2025-12-03 15:10 ` Hogander, Jouni
0 siblings, 1 reply; 25+ messages in thread
From: Imre Deak @ 2025-12-03 14:37 UTC (permalink / raw)
To: Jouni Hogander
Cc: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
On Mon, Dec 01, 2025 at 01:23:41PM +0200, Jouni Hogander wrote:
> On Mon, 2025-12-01 at 12:53 +0200, Imre Deak wrote:
> > On Fri, Nov 21, 2025 at 01:16:52PM +0200, Jouni Högander wrote:
> > > Currently we are leaving pr_dpcd containing Panel Replay capability
> > > DPCD registers as it is on disconnect. Clear it as well on disconnect.
> > >
> > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_dp.c | 1 +
> > > 1 file changed, 1 insertion(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > index 62808cd35f5f2..7195c408d93ab 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > @@ -6050,6 +6050,7 @@ intel_dp_detect(struct drm_connector *_connector,
> > > if (status == connector_status_disconnected) {
> > > intel_dp_test_reset(intel_dp);
> > > memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd));
> > > + memset(connector->dp.pr_dpcd, 0, sizeof(connector->dp.pr_dpcd));
> >
> > What about psr_dpcd?
>
> PSR is only for eDP and can't be disconnected.
Ok. Panel Replay used on non-eDP has also Selective Update for instance,
but that has separate PR specific capability registers. The same is true
I presume for any other functionality that could be used both on PSR2
and PR.
It's still a bit strange that intel_dp_detect() -> intel_psr_init_dpcd()
-> _psr_init_dpcd() reads psr_dpcd (aka dp.psr_caps.dpcd after your
patch) for non-eDP as well. Even though the values should not be used
anywhere based on the above, I'd still avoid explicitly reading them out
for non-eDP (only as a follow-up imo, no need to change this now).
> > All these resetting of the caps cause a problem if the connector
> > needs to be modeset after the sink is disconnected (since then the
> > state computation for the connector will fail seeing these caps
> > being reset). Instead the caps should be kept intact here,
> > resetting/reiniting them only when a new sink is connected. Since
> > this is a pre-existing issue, could you add for now a corrsponding
> > FIXME: comment in this patch?
>
> Thank you for pointing this out. I will add the FIXME.
>
> BR,
>
> Jouni Högander
>
> >
> > > intel_dp->psr.sink_panel_replay_support = false;
> > > intel_dp->psr.sink_panel_replay_su_support = false;
> > > intel_dp->psr.sink_panel_replay_dsc_support =
> > > --
> > > 2.43.0
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 5/8] drm/i915/psr: Clear pr_dpcd as well on disconnect
2025-12-03 14:37 ` Imre Deak
@ 2025-12-03 15:10 ` Hogander, Jouni
0 siblings, 0 replies; 25+ messages in thread
From: Hogander, Jouni @ 2025-12-03 15:10 UTC (permalink / raw)
To: Deak, Imre
Cc: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
On Wed, 2025-12-03 at 16:37 +0200, Imre Deak wrote:
> On Mon, Dec 01, 2025 at 01:23:41PM +0200, Jouni Hogander wrote:
> > On Mon, 2025-12-01 at 12:53 +0200, Imre Deak wrote:
> > > On Fri, Nov 21, 2025 at 01:16:52PM +0200, Jouni Högander wrote:
> > > > Currently we are leaving pr_dpcd containing Panel Replay
> > > > capability
> > > > DPCD registers as it is on disconnect. Clear it as well on
> > > > disconnect.
> > > >
> > > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_dp.c | 1 +
> > > > 1 file changed, 1 insertion(+)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > index 62808cd35f5f2..7195c408d93ab 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > @@ -6050,6 +6050,7 @@ intel_dp_detect(struct drm_connector
> > > > *_connector,
> > > > if (status == connector_status_disconnected) {
> > > > intel_dp_test_reset(intel_dp);
> > > > memset(connector->dp.dsc_dpcd, 0,
> > > > sizeof(connector->dp.dsc_dpcd));
> > > > + memset(connector->dp.pr_dpcd, 0,
> > > > sizeof(connector->dp.pr_dpcd));
> > >
> > > What about psr_dpcd?
> >
> > PSR is only for eDP and can't be disconnected.
>
> Ok. Panel Replay used on non-eDP has also Selective Update for
> instance,
> but that has separate PR specific capability registers. The same is
> true
> I presume for any other functionality that could be used both on PSR2
> and PR.
>
> It's still a bit strange that intel_dp_detect() ->
> intel_psr_init_dpcd()
> -> _psr_init_dpcd() reads psr_dpcd (aka dp.psr_caps.dpcd after your
> patch) for non-eDP as well. Even though the values should not be used
> anywhere based on the above, I'd still avoid explicitly reading them
> out
> for non-eDP (only as a follow-up imo, no need to change this now).
Ok, I will take care of that.
Another thing I have been recently wondering is the eDP/DP version.
Generally speaking: should I check eDP/DP version before checking the
feature of some specific version. I have now seen couple of cases where
panel is stating Panel Replay support, but still saying it's eDP
version 1.4. and Panel Replay is non-functional.(Related patch in
trybot: https://patchwork.freedesktop.org/series/157760/)
BR,
Jouni Högander
>
> > > All these resetting of the caps cause a problem if the connector
> > > needs to be modeset after the sink is disconnected (since then
> > > the
> > > state computation for the connector will fail seeing these caps
> > > being reset). Instead the caps should be kept intact here,
> > > resetting/reiniting them only when a new sink is connected. Since
> > > this is a pre-existing issue, could you add for now a
> > > corrsponding
> > > FIXME: comment in this patch?
> >
> > Thank you for pointing this out. I will add the FIXME.
> >
> > BR,
> >
> > Jouni Högander
> >
> > >
> > > > intel_dp->psr.sink_panel_replay_support =
> > > > false;
> > > > intel_dp->psr.sink_panel_replay_su_support =
> > > > false;
> > > > intel_dp->psr.sink_panel_replay_dsc_support =
> > > > --
> > > > 2.43.0
^ permalink raw reply [flat|nested] 25+ messages in thread
end of thread, other threads:[~2025-12-03 15:11 UTC | newest]
Thread overview: 25+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-11-21 11:16 [PATCH 0/8] Move PSR/Panel Replay sink data into intel_connector Jouni Högander
2025-11-21 11:16 ` [PATCH 1/8] drm/i915/psr: Add panel granularity information " Jouni Högander
2025-12-01 9:54 ` Imre Deak
2025-11-21 11:16 ` [PATCH 2/8] drm/i915/psr: Use SU granularity information available in intel_connector Jouni Högander
2025-12-01 10:14 ` Imre Deak
2025-11-21 11:16 ` [PATCH 3/8] drm/i915/psr: Compute Panel Replay/Adaptive coexistence behavior Jouni Högander
2025-11-21 11:24 ` Jani Nikula
2025-12-01 10:28 ` Imre Deak
2025-11-21 11:16 ` [PATCH 4/8] drm/i915/psr: Move pr_dpcd and psr_dpcd to intel_connector Jouni Högander
2025-12-01 10:45 ` Imre Deak
2025-11-21 11:16 ` [PATCH 5/8] drm/i915/psr: Clear pr_dpcd as well on disconnect Jouni Högander
2025-12-01 10:53 ` Imre Deak
2025-12-01 11:23 ` Hogander, Jouni
2025-12-03 14:37 ` Imre Deak
2025-12-03 15:10 ` Hogander, Jouni
2025-11-21 11:16 ` [PATCH 6/8] drm/i915/psr: Move Panel Replay DSC sink support data to intel_connector Jouni Högander
2025-12-01 10:55 ` Imre Deak
2025-11-21 11:16 ` [PATCH 7/8] drm/i915/psr: Move sink PSR and Panel Replay booleans " Jouni Högander
2025-12-01 10:59 ` Imre Deak
2025-11-21 11:16 ` [PATCH 8/8] drm/i915/psr: Move sink_sync_latency " Jouni Högander
2025-12-01 11:03 ` Imre Deak
2025-11-24 19:59 ` ✗ CI.checkpatch: warning for Move PSR/Panel Replay sink data into intel_connector Patchwork
2025-11-24 20:00 ` ✓ CI.KUnit: success " Patchwork
2025-11-24 20:47 ` ✓ Xe.CI.BAT: " Patchwork
2025-11-24 22:37 ` ✗ Xe.CI.Full: failure " Patchwork
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