* ✗ CI.checkpatch: warning for Introduce DRM_RAS using generic netlink for RAS (rev2)
2025-11-26 14:36 [PATCH v2 0/4] Introduce DRM_RAS using generic netlink for RAS Riana Tauro
@ 2025-11-26 14:31 ` Patchwork
2025-11-26 14:33 ` ✓ CI.KUnit: success " Patchwork
` (4 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2025-11-26 14:31 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-xe
== Series Details ==
Series: Introduce DRM_RAS using generic netlink for RAS (rev2)
URL : https://patchwork.freedesktop.org/series/155188/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
2de9a3901bc28757c7906b454717b64e2a214021
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit a8420b34170a39ae254d2f33aa3e070924d3d551
Author: Riana Tauro <riana.tauro@intel.com>
Date: Wed Nov 26 20:06:47 2025 +0530
drm/xe/xe_hw_error: Add support for PVC SOC errors
Report the SOC nonfatal/fatal hardware error and update the counters.
Co-developed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Signed-off-by: Riana Tauro <riana.tauro@intel.com>
+ /mt/dim checkpatch 13bec21f5f4cdabdf06725e5a8dee0b9b56ff671 drm-intel
b7afc1e1111f drm/ras: Introduce the DRM RAS infrastructure over generic netlink
-:58: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#58:
new file mode 100644
-:792: WARNING:LONG_LINE: line length of 114 exceeds 100 columns
#792: FILE: drivers/gpu/drm/drm_ras_nl.c:13:
+static const struct nla_policy drm_ras_get_error_counters_nl_policy[DRM_RAS_A_ERROR_COUNTER_ATTRS_NODE_ID + 1] = {
-:797: WARNING:LONG_LINE: line length of 116 exceeds 100 columns
#797: FILE: drivers/gpu/drm/drm_ras_nl.c:18:
+static const struct nla_policy drm_ras_query_error_counter_nl_policy[DRM_RAS_A_ERROR_COUNTER_ATTRS_ERROR_ID + 1] = {
total: 0 errors, 3 warnings, 0 checks, 896 lines checked
a56d90f0215a drm/xe/xe_drm_ras: Add support for drm ras
-:49: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#49:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 388 lines checked
cd80f8058d8e drm/xe/xe_hw_error: Add support for GT hardware errors
-:73: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'hw_err' may be better as '(hw_err)' to avoid precedence issues
#73: FILE: drivers/gpu/drm/xe/regs/xe_hw_error_regs.h:60:
+#define ERR_STAT_GT_VECTOR_REG(hw_err, x) (hw_err == HARDWARE_ERROR_CORRECTABLE ? \
+ ERR_STAT_GT_COR_VECTOR_REG(x) : \
+ ERR_STAT_GT_FATAL_VECTOR_REG(x))
-:73: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'x' - possible side-effects?
#73: FILE: drivers/gpu/drm/xe/regs/xe_hw_error_regs.h:60:
+#define ERR_STAT_GT_VECTOR_REG(hw_err, x) (hw_err == HARDWARE_ERROR_CORRECTABLE ? \
+ ERR_STAT_GT_COR_VECTOR_REG(x) : \
+ ERR_STAT_GT_FATAL_VECTOR_REG(x))
-:284: CHECK:LINE_SPACING: Please don't use multiple blank lines
#284: FILE: drivers/gpu/drm/xe/xe_hw_error.c:261:
+
+
total: 0 errors, 0 warnings, 3 checks, 261 lines checked
a8420b34170a drm/xe/xe_hw_error: Add support for PVC SOC errors
-:33: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'base' - possible side-effects?
#33: FILE: drivers/gpu/drm/xe/regs/xe_hw_error_regs.h:70:
+#define SOC_GLOBAL_ERR_STAT_REG(base, x) XE_REG(_PICK_EVEN((x), \
+ (base) + SOC_GCOERRSTS, \
+ (base) + SOC_GNFERRSTS))
-:41: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'slave_base' may be better as '(slave_base)' to avoid precedence issues
#41: FILE: drivers/gpu/drm/xe/regs/xe_hw_error_regs.h:78:
+#define SOC_GSYSEVTCTL_REG(base, slave_base, x) XE_REG(_PICK_EVEN((x), \
+ (base) + SOC_GSYSEVTCTL, \
+ slave_base + SOC_GSYSEVTCTL))
-:47: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'base' - possible side-effects?
#47: FILE: drivers/gpu/drm/xe/regs/xe_hw_error_regs.h:84:
+#define SOC_LOCAL_ERR_STAT_REG(base, x) XE_REG(x == HARDWARE_ERROR_CORRECTABLE ? \
+ (base) + SOC_LERRCORSTS : \
+ (base) + SOC_LERRUNCSTS)
-:47: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#47: FILE: drivers/gpu/drm/xe/regs/xe_hw_error_regs.h:84:
+#define SOC_LOCAL_ERR_STAT_REG(base, x) XE_REG(x == HARDWARE_ERROR_CORRECTABLE ? \
+ (base) + SOC_LERRCORSTS : \
+ (base) + SOC_LERRUNCSTS)
total: 0 errors, 0 warnings, 4 checks, 280 lines checked
^ permalink raw reply [flat|nested] 10+ messages in thread* ✓ CI.KUnit: success for Introduce DRM_RAS using generic netlink for RAS (rev2)
2025-11-26 14:36 [PATCH v2 0/4] Introduce DRM_RAS using generic netlink for RAS Riana Tauro
2025-11-26 14:31 ` ✗ CI.checkpatch: warning for Introduce DRM_RAS using generic netlink for RAS (rev2) Patchwork
@ 2025-11-26 14:33 ` Patchwork
2025-11-26 14:36 ` [PATCH v2 1/4] drm/ras: Introduce the DRM RAS infrastructure over generic netlink Riana Tauro
` (3 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2025-11-26 14:33 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-xe
== Series Details ==
Series: Introduce DRM_RAS using generic netlink for RAS (rev2)
URL : https://patchwork.freedesktop.org/series/155188/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[14:31:54] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[14:31:59] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[14:32:30] Starting KUnit Kernel (1/1)...
[14:32:30] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[14:32:30] ================== guc_buf (11 subtests) ===================
[14:32:30] [PASSED] test_smallest
[14:32:30] [PASSED] test_largest
[14:32:30] [PASSED] test_granular
[14:32:30] [PASSED] test_unique
[14:32:30] [PASSED] test_overlap
[14:32:30] [PASSED] test_reusable
[14:32:30] [PASSED] test_too_big
[14:32:30] [PASSED] test_flush
[14:32:30] [PASSED] test_lookup
[14:32:30] [PASSED] test_data
[14:32:30] [PASSED] test_class
[14:32:30] ===================== [PASSED] guc_buf =====================
[14:32:30] =================== guc_dbm (7 subtests) ===================
[14:32:30] [PASSED] test_empty
[14:32:30] [PASSED] test_default
[14:32:30] ======================== test_size ========================
[14:32:30] [PASSED] 4
[14:32:30] [PASSED] 8
[14:32:30] [PASSED] 32
[14:32:30] [PASSED] 256
[14:32:30] ==================== [PASSED] test_size ====================
[14:32:30] ======================= test_reuse ========================
[14:32:30] [PASSED] 4
[14:32:30] [PASSED] 8
[14:32:30] [PASSED] 32
[14:32:30] [PASSED] 256
[14:32:30] =================== [PASSED] test_reuse ====================
[14:32:30] =================== test_range_overlap ====================
[14:32:30] [PASSED] 4
[14:32:30] [PASSED] 8
[14:32:30] [PASSED] 32
[14:32:30] [PASSED] 256
[14:32:30] =============== [PASSED] test_range_overlap ================
[14:32:30] =================== test_range_compact ====================
[14:32:30] [PASSED] 4
[14:32:30] [PASSED] 8
[14:32:30] [PASSED] 32
[14:32:30] [PASSED] 256
[14:32:30] =============== [PASSED] test_range_compact ================
[14:32:30] ==================== test_range_spare =====================
[14:32:30] [PASSED] 4
[14:32:30] [PASSED] 8
[14:32:30] [PASSED] 32
[14:32:30] [PASSED] 256
[14:32:30] ================ [PASSED] test_range_spare =================
[14:32:30] ===================== [PASSED] guc_dbm =====================
[14:32:30] =================== guc_idm (6 subtests) ===================
[14:32:30] [PASSED] bad_init
[14:32:30] [PASSED] no_init
[14:32:30] [PASSED] init_fini
[14:32:30] [PASSED] check_used
[14:32:30] [PASSED] check_quota
[14:32:30] [PASSED] check_all
[14:32:30] ===================== [PASSED] guc_idm =====================
[14:32:30] ================== no_relay (3 subtests) ===================
[14:32:30] [PASSED] xe_drops_guc2pf_if_not_ready
[14:32:30] [PASSED] xe_drops_guc2vf_if_not_ready
[14:32:30] [PASSED] xe_rejects_send_if_not_ready
[14:32:30] ==================== [PASSED] no_relay =====================
[14:32:30] ================== pf_relay (14 subtests) ==================
[14:32:30] [PASSED] pf_rejects_guc2pf_too_short
[14:32:30] [PASSED] pf_rejects_guc2pf_too_long
[14:32:30] [PASSED] pf_rejects_guc2pf_no_payload
[14:32:30] [PASSED] pf_fails_no_payload
[14:32:30] [PASSED] pf_fails_bad_origin
[14:32:30] [PASSED] pf_fails_bad_type
[14:32:30] [PASSED] pf_txn_reports_error
[14:32:30] [PASSED] pf_txn_sends_pf2guc
[14:32:30] [PASSED] pf_sends_pf2guc
[14:32:30] [SKIPPED] pf_loopback_nop
[14:32:30] [SKIPPED] pf_loopback_echo
[14:32:30] [SKIPPED] pf_loopback_fail
[14:32:30] [SKIPPED] pf_loopback_busy
[14:32:30] [SKIPPED] pf_loopback_retry
[14:32:30] ==================== [PASSED] pf_relay =====================
[14:32:30] ================== vf_relay (3 subtests) ===================
[14:32:30] [PASSED] vf_rejects_guc2vf_too_short
[14:32:30] [PASSED] vf_rejects_guc2vf_too_long
[14:32:30] [PASSED] vf_rejects_guc2vf_no_payload
[14:32:30] ==================== [PASSED] vf_relay =====================
[14:32:30] ================ pf_gt_config (6 subtests) =================
[14:32:30] [PASSED] fair_contexts_1vf
[14:32:30] [PASSED] fair_doorbells_1vf
[14:32:30] [PASSED] fair_ggtt_1vf
[14:32:30] ====================== fair_contexts ======================
[14:32:30] [PASSED] 1 VF
[14:32:30] [PASSED] 2 VFs
[14:32:30] [PASSED] 3 VFs
[14:32:30] [PASSED] 4 VFs
[14:32:30] [PASSED] 5 VFs
[14:32:30] [PASSED] 6 VFs
[14:32:30] [PASSED] 7 VFs
[14:32:30] [PASSED] 8 VFs
[14:32:30] [PASSED] 9 VFs
[14:32:30] [PASSED] 10 VFs
[14:32:30] [PASSED] 11 VFs
[14:32:30] [PASSED] 12 VFs
[14:32:30] [PASSED] 13 VFs
[14:32:30] [PASSED] 14 VFs
[14:32:30] [PASSED] 15 VFs
[14:32:30] [PASSED] 16 VFs
[14:32:30] [PASSED] 17 VFs
[14:32:30] [PASSED] 18 VFs
[14:32:30] [PASSED] 19 VFs
[14:32:30] [PASSED] 20 VFs
[14:32:30] [PASSED] 21 VFs
[14:32:30] [PASSED] 22 VFs
[14:32:30] [PASSED] 23 VFs
[14:32:30] [PASSED] 24 VFs
[14:32:30] [PASSED] 25 VFs
[14:32:30] [PASSED] 26 VFs
[14:32:30] [PASSED] 27 VFs
[14:32:30] [PASSED] 28 VFs
[14:32:30] [PASSED] 29 VFs
[14:32:30] [PASSED] 30 VFs
[14:32:30] [PASSED] 31 VFs
[14:32:30] [PASSED] 32 VFs
[14:32:30] [PASSED] 33 VFs
[14:32:30] [PASSED] 34 VFs
[14:32:30] [PASSED] 35 VFs
[14:32:30] [PASSED] 36 VFs
[14:32:30] [PASSED] 37 VFs
[14:32:30] [PASSED] 38 VFs
[14:32:30] [PASSED] 39 VFs
[14:32:30] [PASSED] 40 VFs
[14:32:30] [PASSED] 41 VFs
[14:32:30] [PASSED] 42 VFs
[14:32:30] [PASSED] 43 VFs
[14:32:30] [PASSED] 44 VFs
[14:32:30] [PASSED] 45 VFs
[14:32:30] [PASSED] 46 VFs
[14:32:30] [PASSED] 47 VFs
[14:32:30] [PASSED] 48 VFs
[14:32:30] [PASSED] 49 VFs
[14:32:30] [PASSED] 50 VFs
[14:32:30] [PASSED] 51 VFs
[14:32:30] [PASSED] 52 VFs
[14:32:30] [PASSED] 53 VFs
[14:32:30] [PASSED] 54 VFs
[14:32:30] [PASSED] 55 VFs
[14:32:30] [PASSED] 56 VFs
[14:32:30] [PASSED] 57 VFs
[14:32:30] [PASSED] 58 VFs
[14:32:30] [PASSED] 59 VFs
[14:32:30] [PASSED] 60 VFs
[14:32:30] [PASSED] 61 VFs
[14:32:30] [PASSED] 62 VFs
[14:32:30] [PASSED] 63 VFs
[14:32:30] ================== [PASSED] fair_contexts ==================
[14:32:30] ===================== fair_doorbells ======================
[14:32:30] [PASSED] 1 VF
[14:32:30] [PASSED] 2 VFs
[14:32:30] [PASSED] 3 VFs
[14:32:30] [PASSED] 4 VFs
[14:32:30] [PASSED] 5 VFs
[14:32:30] [PASSED] 6 VFs
[14:32:30] [PASSED] 7 VFs
[14:32:30] [PASSED] 8 VFs
[14:32:30] [PASSED] 9 VFs
[14:32:30] [PASSED] 10 VFs
[14:32:30] [PASSED] 11 VFs
[14:32:30] [PASSED] 12 VFs
[14:32:30] [PASSED] 13 VFs
[14:32:30] [PASSED] 14 VFs
[14:32:30] [PASSED] 15 VFs
[14:32:30] [PASSED] 16 VFs
[14:32:30] [PASSED] 17 VFs
[14:32:30] [PASSED] 18 VFs
[14:32:30] [PASSED] 19 VFs
[14:32:30] [PASSED] 20 VFs
[14:32:30] [PASSED] 21 VFs
[14:32:30] [PASSED] 22 VFs
[14:32:30] [PASSED] 23 VFs
[14:32:30] [PASSED] 24 VFs
[14:32:30] [PASSED] 25 VFs
[14:32:30] [PASSED] 26 VFs
[14:32:30] [PASSED] 27 VFs
[14:32:30] [PASSED] 28 VFs
[14:32:30] [PASSED] 29 VFs
[14:32:30] [PASSED] 30 VFs
[14:32:30] [PASSED] 31 VFs
[14:32:30] [PASSED] 32 VFs
[14:32:30] [PASSED] 33 VFs
[14:32:30] [PASSED] 34 VFs
[14:32:30] [PASSED] 35 VFs
[14:32:30] [PASSED] 36 VFs
[14:32:30] [PASSED] 37 VFs
[14:32:30] [PASSED] 38 VFs
[14:32:30] [PASSED] 39 VFs
[14:32:30] [PASSED] 40 VFs
[14:32:30] [PASSED] 41 VFs
[14:32:30] [PASSED] 42 VFs
[14:32:30] [PASSED] 43 VFs
[14:32:30] [PASSED] 44 VFs
[14:32:30] [PASSED] 45 VFs
[14:32:30] [PASSED] 46 VFs
[14:32:30] [PASSED] 47 VFs
[14:32:30] [PASSED] 48 VFs
[14:32:30] [PASSED] 49 VFs
[14:32:30] [PASSED] 50 VFs
[14:32:30] [PASSED] 51 VFs
[14:32:30] [PASSED] 52 VFs
[14:32:30] [PASSED] 53 VFs
[14:32:30] [PASSED] 54 VFs
[14:32:30] [PASSED] 55 VFs
[14:32:30] [PASSED] 56 VFs
[14:32:30] [PASSED] 57 VFs
[14:32:30] [PASSED] 58 VFs
[14:32:30] [PASSED] 59 VFs
[14:32:30] [PASSED] 60 VFs
[14:32:30] [PASSED] 61 VFs
[14:32:30] [PASSED] 62 VFs
[14:32:30] [PASSED] 63 VFs
[14:32:30] ================= [PASSED] fair_doorbells ==================
[14:32:30] ======================== fair_ggtt ========================
[14:32:30] [PASSED] 1 VF
[14:32:30] [PASSED] 2 VFs
[14:32:30] [PASSED] 3 VFs
[14:32:30] [PASSED] 4 VFs
[14:32:30] [PASSED] 5 VFs
[14:32:30] [PASSED] 6 VFs
[14:32:30] [PASSED] 7 VFs
[14:32:30] [PASSED] 8 VFs
[14:32:30] [PASSED] 9 VFs
[14:32:30] [PASSED] 10 VFs
[14:32:30] [PASSED] 11 VFs
[14:32:30] [PASSED] 12 VFs
[14:32:30] [PASSED] 13 VFs
[14:32:30] [PASSED] 14 VFs
[14:32:30] [PASSED] 15 VFs
[14:32:30] [PASSED] 16 VFs
[14:32:30] [PASSED] 17 VFs
[14:32:30] [PASSED] 18 VFs
[14:32:30] [PASSED] 19 VFs
[14:32:30] [PASSED] 20 VFs
[14:32:30] [PASSED] 21 VFs
[14:32:30] [PASSED] 22 VFs
[14:32:30] [PASSED] 23 VFs
[14:32:30] [PASSED] 24 VFs
[14:32:30] [PASSED] 25 VFs
[14:32:30] [PASSED] 26 VFs
[14:32:30] [PASSED] 27 VFs
[14:32:30] [PASSED] 28 VFs
[14:32:30] [PASSED] 29 VFs
[14:32:30] [PASSED] 30 VFs
[14:32:30] [PASSED] 31 VFs
[14:32:30] [PASSED] 32 VFs
[14:32:30] [PASSED] 33 VFs
[14:32:30] [PASSED] 34 VFs
[14:32:30] [PASSED] 35 VFs
[14:32:30] [PASSED] 36 VFs
[14:32:30] [PASSED] 37 VFs
[14:32:30] [PASSED] 38 VFs
[14:32:30] [PASSED] 39 VFs
[14:32:30] [PASSED] 40 VFs
[14:32:30] [PASSED] 41 VFs
[14:32:30] [PASSED] 42 VFs
[14:32:30] [PASSED] 43 VFs
[14:32:30] [PASSED] 44 VFs
[14:32:30] [PASSED] 45 VFs
[14:32:30] [PASSED] 46 VFs
[14:32:30] [PASSED] 47 VFs
[14:32:30] [PASSED] 48 VFs
[14:32:30] [PASSED] 49 VFs
[14:32:30] [PASSED] 50 VFs
[14:32:30] [PASSED] 51 VFs
[14:32:30] [PASSED] 52 VFs
[14:32:30] [PASSED] 53 VFs
[14:32:30] [PASSED] 54 VFs
[14:32:30] [PASSED] 55 VFs
[14:32:30] [PASSED] 56 VFs
[14:32:30] [PASSED] 57 VFs
[14:32:30] [PASSED] 58 VFs
[14:32:30] [PASSED] 59 VFs
[14:32:30] [PASSED] 60 VFs
[14:32:30] [PASSED] 61 VFs
[14:32:30] [PASSED] 62 VFs
[14:32:30] [PASSED] 63 VFs
[14:32:30] ==================== [PASSED] fair_ggtt ====================
[14:32:30] ================== [PASSED] pf_gt_config ===================
[14:32:30] ===================== lmtt (1 subtest) =====================
[14:32:30] ======================== test_ops =========================
[14:32:30] [PASSED] 2-level
[14:32:30] [PASSED] multi-level
[14:32:30] ==================== [PASSED] test_ops =====================
[14:32:30] ====================== [PASSED] lmtt =======================
[14:32:30] ================= pf_service (11 subtests) =================
[14:32:30] [PASSED] pf_negotiate_any
[14:32:30] [PASSED] pf_negotiate_base_match
[14:32:30] [PASSED] pf_negotiate_base_newer
[14:32:30] [PASSED] pf_negotiate_base_next
[14:32:30] [SKIPPED] pf_negotiate_base_older
[14:32:30] [PASSED] pf_negotiate_base_prev
[14:32:30] [PASSED] pf_negotiate_latest_match
[14:32:30] [PASSED] pf_negotiate_latest_newer
[14:32:30] [PASSED] pf_negotiate_latest_next
[14:32:30] [SKIPPED] pf_negotiate_latest_older
[14:32:30] [SKIPPED] pf_negotiate_latest_prev
[14:32:30] =================== [PASSED] pf_service ====================
[14:32:30] ================= xe_guc_g2g (2 subtests) ==================
[14:32:30] ============== xe_live_guc_g2g_kunit_default ==============
[14:32:30] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[14:32:30] ============== xe_live_guc_g2g_kunit_allmem ===============
[14:32:30] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[14:32:30] =================== [SKIPPED] xe_guc_g2g ===================
[14:32:30] =================== xe_mocs (2 subtests) ===================
[14:32:30] ================ xe_live_mocs_kernel_kunit ================
[14:32:30] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[14:32:30] ================ xe_live_mocs_reset_kunit =================
[14:32:30] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[14:32:30] ==================== [SKIPPED] xe_mocs =====================
[14:32:30] ================= xe_migrate (2 subtests) ==================
[14:32:30] ================= xe_migrate_sanity_kunit =================
[14:32:30] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[14:32:30] ================== xe_validate_ccs_kunit ==================
[14:32:30] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[14:32:30] =================== [SKIPPED] xe_migrate ===================
[14:32:30] ================== xe_dma_buf (1 subtest) ==================
[14:32:30] ==================== xe_dma_buf_kunit =====================
[14:32:30] ================ [SKIPPED] xe_dma_buf_kunit ================
[14:32:30] =================== [SKIPPED] xe_dma_buf ===================
[14:32:30] ================= xe_bo_shrink (1 subtest) =================
[14:32:30] =================== xe_bo_shrink_kunit ====================
[14:32:30] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[14:32:30] ================== [SKIPPED] xe_bo_shrink ==================
[14:32:30] ==================== xe_bo (2 subtests) ====================
[14:32:30] ================== xe_ccs_migrate_kunit ===================
[14:32:30] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[14:32:30] ==================== xe_bo_evict_kunit ====================
[14:32:30] =============== [SKIPPED] xe_bo_evict_kunit ================
[14:32:30] ===================== [SKIPPED] xe_bo ======================
[14:32:30] ==================== args (11 subtests) ====================
[14:32:30] [PASSED] count_args_test
[14:32:30] [PASSED] call_args_example
[14:32:30] [PASSED] call_args_test
[14:32:30] [PASSED] drop_first_arg_example
[14:32:30] [PASSED] drop_first_arg_test
[14:32:30] [PASSED] first_arg_example
[14:32:30] [PASSED] first_arg_test
[14:32:30] [PASSED] last_arg_example
[14:32:30] [PASSED] last_arg_test
[14:32:30] [PASSED] pick_arg_example
[14:32:30] [PASSED] sep_comma_example
[14:32:30] ====================== [PASSED] args =======================
[14:32:30] =================== xe_pci (3 subtests) ====================
[14:32:30] ==================== check_graphics_ip ====================
[14:32:30] [PASSED] 12.00 Xe_LP
[14:32:30] [PASSED] 12.10 Xe_LP+
[14:32:30] [PASSED] 12.55 Xe_HPG
[14:32:30] [PASSED] 12.60 Xe_HPC
[14:32:30] [PASSED] 12.70 Xe_LPG
[14:32:30] [PASSED] 12.71 Xe_LPG
[14:32:30] [PASSED] 12.74 Xe_LPG+
[14:32:30] [PASSED] 20.01 Xe2_HPG
[14:32:30] [PASSED] 20.02 Xe2_HPG
[14:32:30] [PASSED] 20.04 Xe2_LPG
[14:32:30] [PASSED] 30.00 Xe3_LPG
[14:32:30] [PASSED] 30.01 Xe3_LPG
[14:32:30] [PASSED] 30.03 Xe3_LPG
[14:32:30] [PASSED] 30.04 Xe3_LPG
[14:32:30] [PASSED] 30.05 Xe3_LPG
[14:32:30] [PASSED] 35.11 Xe3p_XPC
[14:32:30] ================ [PASSED] check_graphics_ip ================
[14:32:30] ===================== check_media_ip ======================
[14:32:30] [PASSED] 12.00 Xe_M
[14:32:30] [PASSED] 12.55 Xe_HPM
[14:32:30] [PASSED] 13.00 Xe_LPM+
[14:32:30] [PASSED] 13.01 Xe2_HPM
[14:32:30] [PASSED] 20.00 Xe2_LPM
[14:32:30] [PASSED] 30.00 Xe3_LPM
[14:32:30] [PASSED] 30.02 Xe3_LPM
[14:32:30] [PASSED] 35.00 Xe3p_LPM
[14:32:30] [PASSED] 35.03 Xe3p_HPM
[14:32:30] ================= [PASSED] check_media_ip ==================
[14:32:30] =================== check_platform_desc ===================
[14:32:30] [PASSED] 0x9A60 (TIGERLAKE)
[14:32:30] [PASSED] 0x9A68 (TIGERLAKE)
[14:32:30] [PASSED] 0x9A70 (TIGERLAKE)
[14:32:30] [PASSED] 0x9A40 (TIGERLAKE)
[14:32:30] [PASSED] 0x9A49 (TIGERLAKE)
[14:32:30] [PASSED] 0x9A59 (TIGERLAKE)
[14:32:30] [PASSED] 0x9A78 (TIGERLAKE)
[14:32:30] [PASSED] 0x9AC0 (TIGERLAKE)
[14:32:30] [PASSED] 0x9AC9 (TIGERLAKE)
[14:32:30] [PASSED] 0x9AD9 (TIGERLAKE)
[14:32:30] [PASSED] 0x9AF8 (TIGERLAKE)
[14:32:30] [PASSED] 0x4C80 (ROCKETLAKE)
[14:32:30] [PASSED] 0x4C8A (ROCKETLAKE)
[14:32:30] [PASSED] 0x4C8B (ROCKETLAKE)
[14:32:30] [PASSED] 0x4C8C (ROCKETLAKE)
[14:32:30] [PASSED] 0x4C90 (ROCKETLAKE)
[14:32:30] [PASSED] 0x4C9A (ROCKETLAKE)
[14:32:30] [PASSED] 0x4680 (ALDERLAKE_S)
[14:32:30] [PASSED] 0x4682 (ALDERLAKE_S)
[14:32:30] [PASSED] 0x4688 (ALDERLAKE_S)
[14:32:30] [PASSED] 0x468A (ALDERLAKE_S)
[14:32:30] [PASSED] 0x468B (ALDERLAKE_S)
[14:32:30] [PASSED] 0x4690 (ALDERLAKE_S)
[14:32:30] [PASSED] 0x4692 (ALDERLAKE_S)
[14:32:30] [PASSED] 0x4693 (ALDERLAKE_S)
[14:32:30] [PASSED] 0x46A0 (ALDERLAKE_P)
[14:32:30] [PASSED] 0x46A1 (ALDERLAKE_P)
[14:32:30] [PASSED] 0x46A2 (ALDERLAKE_P)
[14:32:30] [PASSED] 0x46A3 (ALDERLAKE_P)
[14:32:30] [PASSED] 0x46A6 (ALDERLAKE_P)
[14:32:30] [PASSED] 0x46A8 (ALDERLAKE_P)
[14:32:30] [PASSED] 0x46AA (ALDERLAKE_P)
[14:32:30] [PASSED] 0x462A (ALDERLAKE_P)
[14:32:30] [PASSED] 0x4626 (ALDERLAKE_P)
[14:32:30] [PASSED] 0x4628 (ALDERLAKE_P)
[14:32:30] [PASSED] 0x46B0 (ALDERLAKE_P)
stty: 'standard input': Inappropriate ioctl for device
[14:32:30] [PASSED] 0x46B1 (ALDERLAKE_P)
[14:32:30] [PASSED] 0x46B2 (ALDERLAKE_P)
[14:32:30] [PASSED] 0x46B3 (ALDERLAKE_P)
[14:32:30] [PASSED] 0x46C0 (ALDERLAKE_P)
[14:32:30] [PASSED] 0x46C1 (ALDERLAKE_P)
[14:32:30] [PASSED] 0x46C2 (ALDERLAKE_P)
[14:32:30] [PASSED] 0x46C3 (ALDERLAKE_P)
[14:32:30] [PASSED] 0x46D0 (ALDERLAKE_N)
[14:32:30] [PASSED] 0x46D1 (ALDERLAKE_N)
[14:32:30] [PASSED] 0x46D2 (ALDERLAKE_N)
[14:32:30] [PASSED] 0x46D3 (ALDERLAKE_N)
[14:32:30] [PASSED] 0x46D4 (ALDERLAKE_N)
[14:32:30] [PASSED] 0xA721 (ALDERLAKE_P)
[14:32:30] [PASSED] 0xA7A1 (ALDERLAKE_P)
[14:32:30] [PASSED] 0xA7A9 (ALDERLAKE_P)
[14:32:30] [PASSED] 0xA7AC (ALDERLAKE_P)
[14:32:30] [PASSED] 0xA7AD (ALDERLAKE_P)
[14:32:30] [PASSED] 0xA720 (ALDERLAKE_P)
[14:32:30] [PASSED] 0xA7A0 (ALDERLAKE_P)
[14:32:30] [PASSED] 0xA7A8 (ALDERLAKE_P)
[14:32:30] [PASSED] 0xA7AA (ALDERLAKE_P)
[14:32:30] [PASSED] 0xA7AB (ALDERLAKE_P)
[14:32:30] [PASSED] 0xA780 (ALDERLAKE_S)
[14:32:30] [PASSED] 0xA781 (ALDERLAKE_S)
[14:32:30] [PASSED] 0xA782 (ALDERLAKE_S)
[14:32:30] [PASSED] 0xA783 (ALDERLAKE_S)
[14:32:30] [PASSED] 0xA788 (ALDERLAKE_S)
[14:32:30] [PASSED] 0xA789 (ALDERLAKE_S)
[14:32:30] [PASSED] 0xA78A (ALDERLAKE_S)
[14:32:30] [PASSED] 0xA78B (ALDERLAKE_S)
[14:32:30] [PASSED] 0x4905 (DG1)
[14:32:30] [PASSED] 0x4906 (DG1)
[14:32:30] [PASSED] 0x4907 (DG1)
[14:32:30] [PASSED] 0x4908 (DG1)
[14:32:30] [PASSED] 0x4909 (DG1)
[14:32:30] [PASSED] 0x56C0 (DG2)
[14:32:30] [PASSED] 0x56C2 (DG2)
[14:32:30] [PASSED] 0x56C1 (DG2)
[14:32:30] [PASSED] 0x7D51 (METEORLAKE)
[14:32:30] [PASSED] 0x7DD1 (METEORLAKE)
[14:32:30] [PASSED] 0x7D41 (METEORLAKE)
[14:32:30] [PASSED] 0x7D67 (METEORLAKE)
[14:32:30] [PASSED] 0xB640 (METEORLAKE)
[14:32:30] [PASSED] 0x56A0 (DG2)
[14:32:30] [PASSED] 0x56A1 (DG2)
[14:32:30] [PASSED] 0x56A2 (DG2)
[14:32:30] [PASSED] 0x56BE (DG2)
[14:32:30] [PASSED] 0x56BF (DG2)
[14:32:30] [PASSED] 0x5690 (DG2)
[14:32:30] [PASSED] 0x5691 (DG2)
[14:32:30] [PASSED] 0x5692 (DG2)
[14:32:30] [PASSED] 0x56A5 (DG2)
[14:32:30] [PASSED] 0x56A6 (DG2)
[14:32:30] [PASSED] 0x56B0 (DG2)
[14:32:30] [PASSED] 0x56B1 (DG2)
[14:32:30] [PASSED] 0x56BA (DG2)
[14:32:30] [PASSED] 0x56BB (DG2)
[14:32:30] [PASSED] 0x56BC (DG2)
[14:32:30] [PASSED] 0x56BD (DG2)
[14:32:30] [PASSED] 0x5693 (DG2)
[14:32:30] [PASSED] 0x5694 (DG2)
[14:32:30] [PASSED] 0x5695 (DG2)
[14:32:30] [PASSED] 0x56A3 (DG2)
[14:32:30] [PASSED] 0x56A4 (DG2)
[14:32:30] [PASSED] 0x56B2 (DG2)
[14:32:30] [PASSED] 0x56B3 (DG2)
[14:32:30] [PASSED] 0x5696 (DG2)
[14:32:30] [PASSED] 0x5697 (DG2)
[14:32:30] [PASSED] 0xB69 (PVC)
[14:32:30] [PASSED] 0xB6E (PVC)
[14:32:30] [PASSED] 0xBD4 (PVC)
[14:32:30] [PASSED] 0xBD5 (PVC)
[14:32:30] [PASSED] 0xBD6 (PVC)
[14:32:30] [PASSED] 0xBD7 (PVC)
[14:32:30] [PASSED] 0xBD8 (PVC)
[14:32:30] [PASSED] 0xBD9 (PVC)
[14:32:30] [PASSED] 0xBDA (PVC)
[14:32:30] [PASSED] 0xBDB (PVC)
[14:32:30] [PASSED] 0xBE0 (PVC)
[14:32:30] [PASSED] 0xBE1 (PVC)
[14:32:30] [PASSED] 0xBE5 (PVC)
[14:32:30] [PASSED] 0x7D40 (METEORLAKE)
[14:32:30] [PASSED] 0x7D45 (METEORLAKE)
[14:32:30] [PASSED] 0x7D55 (METEORLAKE)
[14:32:30] [PASSED] 0x7D60 (METEORLAKE)
[14:32:30] [PASSED] 0x7DD5 (METEORLAKE)
[14:32:30] [PASSED] 0x6420 (LUNARLAKE)
[14:32:30] [PASSED] 0x64A0 (LUNARLAKE)
[14:32:30] [PASSED] 0x64B0 (LUNARLAKE)
[14:32:30] [PASSED] 0xE202 (BATTLEMAGE)
[14:32:30] [PASSED] 0xE209 (BATTLEMAGE)
[14:32:30] [PASSED] 0xE20B (BATTLEMAGE)
[14:32:30] [PASSED] 0xE20C (BATTLEMAGE)
[14:32:30] [PASSED] 0xE20D (BATTLEMAGE)
[14:32:30] [PASSED] 0xE210 (BATTLEMAGE)
[14:32:30] [PASSED] 0xE211 (BATTLEMAGE)
[14:32:30] [PASSED] 0xE212 (BATTLEMAGE)
[14:32:30] [PASSED] 0xE216 (BATTLEMAGE)
[14:32:30] [PASSED] 0xE220 (BATTLEMAGE)
[14:32:30] [PASSED] 0xE221 (BATTLEMAGE)
[14:32:30] [PASSED] 0xE222 (BATTLEMAGE)
[14:32:30] [PASSED] 0xE223 (BATTLEMAGE)
[14:32:30] [PASSED] 0xB080 (PANTHERLAKE)
[14:32:30] [PASSED] 0xB081 (PANTHERLAKE)
[14:32:30] [PASSED] 0xB082 (PANTHERLAKE)
[14:32:30] [PASSED] 0xB083 (PANTHERLAKE)
[14:32:30] [PASSED] 0xB084 (PANTHERLAKE)
[14:32:30] [PASSED] 0xB085 (PANTHERLAKE)
[14:32:30] [PASSED] 0xB086 (PANTHERLAKE)
[14:32:30] [PASSED] 0xB087 (PANTHERLAKE)
[14:32:30] [PASSED] 0xB08F (PANTHERLAKE)
[14:32:30] [PASSED] 0xB090 (PANTHERLAKE)
[14:32:30] [PASSED] 0xB0A0 (PANTHERLAKE)
[14:32:30] [PASSED] 0xB0B0 (PANTHERLAKE)
[14:32:30] [PASSED] 0xD740 (NOVALAKE_S)
[14:32:30] [PASSED] 0xD741 (NOVALAKE_S)
[14:32:30] [PASSED] 0xD742 (NOVALAKE_S)
[14:32:30] [PASSED] 0xD743 (NOVALAKE_S)
[14:32:30] [PASSED] 0xD744 (NOVALAKE_S)
[14:32:30] [PASSED] 0xD745 (NOVALAKE_S)
[14:32:30] [PASSED] 0x674C (CRESCENTISLAND)
[14:32:30] [PASSED] 0xFD80 (PANTHERLAKE)
[14:32:30] [PASSED] 0xFD81 (PANTHERLAKE)
[14:32:30] =============== [PASSED] check_platform_desc ===============
[14:32:30] ===================== [PASSED] xe_pci ======================
[14:32:30] =================== xe_rtp (2 subtests) ====================
[14:32:30] =============== xe_rtp_process_to_sr_tests ================
[14:32:30] [PASSED] coalesce-same-reg
[14:32:30] [PASSED] no-match-no-add
[14:32:30] [PASSED] match-or
[14:32:30] [PASSED] match-or-xfail
[14:32:30] [PASSED] no-match-no-add-multiple-rules
[14:32:30] [PASSED] two-regs-two-entries
[14:32:30] [PASSED] clr-one-set-other
[14:32:30] [PASSED] set-field
[14:32:30] [PASSED] conflict-duplicate
[14:32:30] [PASSED] conflict-not-disjoint
[14:32:30] [PASSED] conflict-reg-type
[14:32:30] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[14:32:30] ================== xe_rtp_process_tests ===================
[14:32:30] [PASSED] active1
[14:32:30] [PASSED] active2
[14:32:30] [PASSED] active-inactive
[14:32:30] [PASSED] inactive-active
[14:32:30] [PASSED] inactive-1st_or_active-inactive
[14:32:30] [PASSED] inactive-2nd_or_active-inactive
[14:32:30] [PASSED] inactive-last_or_active-inactive
[14:32:30] [PASSED] inactive-no_or_active-inactive
[14:32:30] ============== [PASSED] xe_rtp_process_tests ===============
[14:32:30] ===================== [PASSED] xe_rtp ======================
[14:32:30] ==================== xe_wa (1 subtest) =====================
[14:32:30] ======================== xe_wa_gt =========================
[14:32:30] [PASSED] TIGERLAKE B0
[14:32:30] [PASSED] DG1 A0
[14:32:30] [PASSED] DG1 B0
[14:32:30] [PASSED] ALDERLAKE_S A0
[14:32:30] [PASSED] ALDERLAKE_S B0
[14:32:30] [PASSED] ALDERLAKE_S C0
[14:32:30] [PASSED] ALDERLAKE_S D0
[14:32:30] [PASSED] ALDERLAKE_P A0
[14:32:30] [PASSED] ALDERLAKE_P B0
[14:32:30] [PASSED] ALDERLAKE_P C0
[14:32:30] [PASSED] ALDERLAKE_S RPLS D0
[14:32:30] [PASSED] ALDERLAKE_P RPLU E0
[14:32:30] [PASSED] DG2 G10 C0
[14:32:30] [PASSED] DG2 G11 B1
[14:32:30] [PASSED] DG2 G12 A1
[14:32:30] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[14:32:30] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[14:32:30] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[14:32:30] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[14:32:30] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[14:32:30] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[14:32:30] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[14:32:30] ==================== [PASSED] xe_wa_gt =====================
[14:32:30] ====================== [PASSED] xe_wa ======================
[14:32:30] ============================================================
[14:32:30] Testing complete. Ran 510 tests: passed: 492, skipped: 18
[14:32:30] Elapsed time: 35.793s total, 4.249s configuring, 31.028s building, 0.463s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[14:32:30] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[14:32:32] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[14:32:57] Starting KUnit Kernel (1/1)...
[14:32:57] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[14:32:57] ============ drm_test_pick_cmdline (2 subtests) ============
[14:32:57] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[14:32:57] =============== drm_test_pick_cmdline_named ===============
[14:32:57] [PASSED] NTSC
[14:32:57] [PASSED] NTSC-J
[14:32:57] [PASSED] PAL
[14:32:57] [PASSED] PAL-M
[14:32:57] =========== [PASSED] drm_test_pick_cmdline_named ===========
[14:32:57] ============== [PASSED] drm_test_pick_cmdline ==============
[14:32:57] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[14:32:57] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[14:32:57] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[14:32:57] =========== drm_validate_clone_mode (2 subtests) ===========
[14:32:57] ============== drm_test_check_in_clone_mode ===============
[14:32:57] [PASSED] in_clone_mode
[14:32:57] [PASSED] not_in_clone_mode
[14:32:57] ========== [PASSED] drm_test_check_in_clone_mode ===========
[14:32:57] =============== drm_test_check_valid_clones ===============
[14:32:57] [PASSED] not_in_clone_mode
[14:32:57] [PASSED] valid_clone
[14:32:57] [PASSED] invalid_clone
[14:32:57] =========== [PASSED] drm_test_check_valid_clones ===========
[14:32:57] ============= [PASSED] drm_validate_clone_mode =============
[14:32:57] ============= drm_validate_modeset (1 subtest) =============
[14:32:57] [PASSED] drm_test_check_connector_changed_modeset
[14:32:57] ============== [PASSED] drm_validate_modeset ===============
[14:32:57] ====== drm_test_bridge_get_current_state (2 subtests) ======
[14:32:57] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[14:32:57] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[14:32:57] ======== [PASSED] drm_test_bridge_get_current_state ========
[14:32:57] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[14:32:57] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[14:32:57] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[14:32:57] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[14:32:57] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[14:32:57] ============== drm_bridge_alloc (2 subtests) ===============
[14:32:57] [PASSED] drm_test_drm_bridge_alloc_basic
[14:32:57] [PASSED] drm_test_drm_bridge_alloc_get_put
[14:32:57] ================ [PASSED] drm_bridge_alloc =================
[14:32:57] ================== drm_buddy (8 subtests) ==================
[14:32:57] [PASSED] drm_test_buddy_alloc_limit
[14:32:57] [PASSED] drm_test_buddy_alloc_optimistic
[14:32:57] [PASSED] drm_test_buddy_alloc_pessimistic
[14:32:57] [PASSED] drm_test_buddy_alloc_pathological
[14:32:57] [PASSED] drm_test_buddy_alloc_contiguous
[14:32:57] [PASSED] drm_test_buddy_alloc_clear
[14:32:57] [PASSED] drm_test_buddy_alloc_range_bias
[14:32:58] [PASSED] drm_test_buddy_fragmentation_performance
[14:32:58] ==================== [PASSED] drm_buddy ====================
[14:32:58] ============= drm_cmdline_parser (40 subtests) =============
[14:32:58] [PASSED] drm_test_cmdline_force_d_only
[14:32:58] [PASSED] drm_test_cmdline_force_D_only_dvi
[14:32:58] [PASSED] drm_test_cmdline_force_D_only_hdmi
[14:32:58] [PASSED] drm_test_cmdline_force_D_only_not_digital
[14:32:58] [PASSED] drm_test_cmdline_force_e_only
[14:32:58] [PASSED] drm_test_cmdline_res
[14:32:58] [PASSED] drm_test_cmdline_res_vesa
[14:32:58] [PASSED] drm_test_cmdline_res_vesa_rblank
[14:32:58] [PASSED] drm_test_cmdline_res_rblank
[14:32:58] [PASSED] drm_test_cmdline_res_bpp
[14:32:58] [PASSED] drm_test_cmdline_res_refresh
[14:32:58] [PASSED] drm_test_cmdline_res_bpp_refresh
[14:32:58] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[14:32:58] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[14:32:58] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[14:32:58] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[14:32:58] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[14:32:58] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[14:32:58] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[14:32:58] [PASSED] drm_test_cmdline_res_margins_force_on
[14:32:58] [PASSED] drm_test_cmdline_res_vesa_margins
[14:32:58] [PASSED] drm_test_cmdline_name
[14:32:58] [PASSED] drm_test_cmdline_name_bpp
[14:32:58] [PASSED] drm_test_cmdline_name_option
[14:32:58] [PASSED] drm_test_cmdline_name_bpp_option
[14:32:58] [PASSED] drm_test_cmdline_rotate_0
[14:32:58] [PASSED] drm_test_cmdline_rotate_90
[14:32:58] [PASSED] drm_test_cmdline_rotate_180
[14:32:58] [PASSED] drm_test_cmdline_rotate_270
[14:32:58] [PASSED] drm_test_cmdline_hmirror
[14:32:58] [PASSED] drm_test_cmdline_vmirror
[14:32:58] [PASSED] drm_test_cmdline_margin_options
[14:32:58] [PASSED] drm_test_cmdline_multiple_options
[14:32:58] [PASSED] drm_test_cmdline_bpp_extra_and_option
[14:32:58] [PASSED] drm_test_cmdline_extra_and_option
[14:32:58] [PASSED] drm_test_cmdline_freestanding_options
[14:32:58] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[14:32:58] [PASSED] drm_test_cmdline_panel_orientation
[14:32:58] ================ drm_test_cmdline_invalid =================
[14:32:58] [PASSED] margin_only
[14:32:58] [PASSED] interlace_only
[14:32:58] [PASSED] res_missing_x
[14:32:58] [PASSED] res_missing_y
[14:32:58] [PASSED] res_bad_y
[14:32:58] [PASSED] res_missing_y_bpp
[14:32:58] [PASSED] res_bad_bpp
[14:32:58] [PASSED] res_bad_refresh
[14:32:58] [PASSED] res_bpp_refresh_force_on_off
[14:32:58] [PASSED] res_invalid_mode
[14:32:58] [PASSED] res_bpp_wrong_place_mode
[14:32:58] [PASSED] name_bpp_refresh
[14:32:58] [PASSED] name_refresh
[14:32:58] [PASSED] name_refresh_wrong_mode
[14:32:58] [PASSED] name_refresh_invalid_mode
[14:32:58] [PASSED] rotate_multiple
[14:32:58] [PASSED] rotate_invalid_val
[14:32:58] [PASSED] rotate_truncated
[14:32:58] [PASSED] invalid_option
[14:32:58] [PASSED] invalid_tv_option
[14:32:58] [PASSED] truncated_tv_option
[14:32:58] ============ [PASSED] drm_test_cmdline_invalid =============
[14:32:58] =============== drm_test_cmdline_tv_options ===============
[14:32:58] [PASSED] NTSC
[14:32:58] [PASSED] NTSC_443
[14:32:58] [PASSED] NTSC_J
[14:32:58] [PASSED] PAL
[14:32:58] [PASSED] PAL_M
[14:32:58] [PASSED] PAL_N
[14:32:58] [PASSED] SECAM
[14:32:58] [PASSED] MONO_525
[14:32:58] [PASSED] MONO_625
[14:32:58] =========== [PASSED] drm_test_cmdline_tv_options ===========
[14:32:58] =============== [PASSED] drm_cmdline_parser ================
[14:32:58] ========== drmm_connector_hdmi_init (20 subtests) ==========
[14:32:58] [PASSED] drm_test_connector_hdmi_init_valid
[14:32:58] [PASSED] drm_test_connector_hdmi_init_bpc_8
[14:32:58] [PASSED] drm_test_connector_hdmi_init_bpc_10
[14:32:58] [PASSED] drm_test_connector_hdmi_init_bpc_12
[14:32:58] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[14:32:58] [PASSED] drm_test_connector_hdmi_init_bpc_null
[14:32:58] [PASSED] drm_test_connector_hdmi_init_formats_empty
[14:32:58] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[14:32:58] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[14:32:58] [PASSED] supported_formats=0x9 yuv420_allowed=1
[14:32:58] [PASSED] supported_formats=0x9 yuv420_allowed=0
[14:32:58] [PASSED] supported_formats=0x3 yuv420_allowed=1
[14:32:58] [PASSED] supported_formats=0x3 yuv420_allowed=0
[14:32:58] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[14:32:58] [PASSED] drm_test_connector_hdmi_init_null_ddc
[14:32:58] [PASSED] drm_test_connector_hdmi_init_null_product
[14:32:58] [PASSED] drm_test_connector_hdmi_init_null_vendor
[14:32:58] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[14:32:58] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[14:32:58] [PASSED] drm_test_connector_hdmi_init_product_valid
[14:32:58] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[14:32:58] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[14:32:58] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[14:32:58] ========= drm_test_connector_hdmi_init_type_valid =========
[14:32:58] [PASSED] HDMI-A
[14:32:58] [PASSED] HDMI-B
[14:32:58] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[14:32:58] ======== drm_test_connector_hdmi_init_type_invalid ========
[14:32:58] [PASSED] Unknown
[14:32:58] [PASSED] VGA
[14:32:58] [PASSED] DVI-I
[14:32:58] [PASSED] DVI-D
[14:32:58] [PASSED] DVI-A
[14:32:58] [PASSED] Composite
[14:32:58] [PASSED] SVIDEO
[14:32:58] [PASSED] LVDS
[14:32:58] [PASSED] Component
[14:32:58] [PASSED] DIN
[14:32:58] [PASSED] DP
[14:32:58] [PASSED] TV
[14:32:58] [PASSED] eDP
[14:32:58] [PASSED] Virtual
[14:32:58] [PASSED] DSI
[14:32:58] [PASSED] DPI
[14:32:58] [PASSED] Writeback
[14:32:58] [PASSED] SPI
[14:32:58] [PASSED] USB
[14:32:58] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[14:32:58] ============ [PASSED] drmm_connector_hdmi_init =============
[14:32:58] ============= drmm_connector_init (3 subtests) =============
[14:32:58] [PASSED] drm_test_drmm_connector_init
[14:32:58] [PASSED] drm_test_drmm_connector_init_null_ddc
[14:32:58] ========= drm_test_drmm_connector_init_type_valid =========
[14:32:58] [PASSED] Unknown
[14:32:58] [PASSED] VGA
[14:32:58] [PASSED] DVI-I
[14:32:58] [PASSED] DVI-D
[14:32:58] [PASSED] DVI-A
[14:32:58] [PASSED] Composite
[14:32:58] [PASSED] SVIDEO
[14:32:58] [PASSED] LVDS
[14:32:58] [PASSED] Component
[14:32:58] [PASSED] DIN
[14:32:58] [PASSED] DP
[14:32:58] [PASSED] HDMI-A
[14:32:58] [PASSED] HDMI-B
[14:32:58] [PASSED] TV
[14:32:58] [PASSED] eDP
[14:32:58] [PASSED] Virtual
[14:32:58] [PASSED] DSI
[14:32:58] [PASSED] DPI
[14:32:58] [PASSED] Writeback
[14:32:58] [PASSED] SPI
[14:32:58] [PASSED] USB
[14:32:58] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[14:32:58] =============== [PASSED] drmm_connector_init ===============
[14:32:58] ========= drm_connector_dynamic_init (6 subtests) ==========
[14:32:58] [PASSED] drm_test_drm_connector_dynamic_init
[14:32:58] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[14:32:58] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[14:32:58] [PASSED] drm_test_drm_connector_dynamic_init_properties
[14:32:58] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[14:32:58] [PASSED] Unknown
[14:32:58] [PASSED] VGA
[14:32:58] [PASSED] DVI-I
[14:32:58] [PASSED] DVI-D
[14:32:58] [PASSED] DVI-A
[14:32:58] [PASSED] Composite
[14:32:58] [PASSED] SVIDEO
[14:32:58] [PASSED] LVDS
[14:32:58] [PASSED] Component
[14:32:58] [PASSED] DIN
[14:32:58] [PASSED] DP
[14:32:58] [PASSED] HDMI-A
[14:32:58] [PASSED] HDMI-B
[14:32:58] [PASSED] TV
[14:32:58] [PASSED] eDP
[14:32:58] [PASSED] Virtual
[14:32:58] [PASSED] DSI
[14:32:58] [PASSED] DPI
[14:32:58] [PASSED] Writeback
[14:32:58] [PASSED] SPI
[14:32:58] [PASSED] USB
[14:32:58] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[14:32:58] ======== drm_test_drm_connector_dynamic_init_name =========
[14:32:58] [PASSED] Unknown
[14:32:58] [PASSED] VGA
[14:32:58] [PASSED] DVI-I
[14:32:58] [PASSED] DVI-D
[14:32:58] [PASSED] DVI-A
[14:32:58] [PASSED] Composite
[14:32:58] [PASSED] SVIDEO
[14:32:58] [PASSED] LVDS
[14:32:58] [PASSED] Component
[14:32:58] [PASSED] DIN
[14:32:58] [PASSED] DP
[14:32:58] [PASSED] HDMI-A
[14:32:58] [PASSED] HDMI-B
[14:32:58] [PASSED] TV
[14:32:58] [PASSED] eDP
[14:32:58] [PASSED] Virtual
[14:32:58] [PASSED] DSI
[14:32:58] [PASSED] DPI
[14:32:58] [PASSED] Writeback
[14:32:58] [PASSED] SPI
[14:32:58] [PASSED] USB
[14:32:58] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[14:32:58] =========== [PASSED] drm_connector_dynamic_init ============
[14:32:58] ==== drm_connector_dynamic_register_early (4 subtests) =====
[14:32:58] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[14:32:58] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[14:32:58] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[14:32:58] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[14:32:58] ====== [PASSED] drm_connector_dynamic_register_early =======
[14:32:58] ======= drm_connector_dynamic_register (7 subtests) ========
[14:32:58] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[14:32:58] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[14:32:58] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[14:32:58] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[14:32:58] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[14:32:58] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[14:32:58] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[14:32:58] ========= [PASSED] drm_connector_dynamic_register ==========
[14:32:58] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[14:32:58] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[14:32:58] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[14:32:58] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[14:32:58] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[14:32:58] ========== drm_test_get_tv_mode_from_name_valid ===========
[14:32:58] [PASSED] NTSC
[14:32:58] [PASSED] NTSC-443
[14:32:58] [PASSED] NTSC-J
[14:32:58] [PASSED] PAL
[14:32:58] [PASSED] PAL-M
[14:32:58] [PASSED] PAL-N
[14:32:58] [PASSED] SECAM
[14:32:58] [PASSED] Mono
[14:32:58] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[14:32:58] [PASSED] drm_test_get_tv_mode_from_name_truncated
[14:32:58] ============ [PASSED] drm_get_tv_mode_from_name ============
[14:32:58] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[14:32:58] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[14:32:58] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[14:32:58] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[14:32:58] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[14:32:58] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[14:32:58] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[14:32:58] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[14:32:58] [PASSED] VIC 96
[14:32:58] [PASSED] VIC 97
[14:32:58] [PASSED] VIC 101
[14:32:58] [PASSED] VIC 102
[14:32:58] [PASSED] VIC 106
[14:32:58] [PASSED] VIC 107
[14:32:58] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[14:32:58] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[14:32:58] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[14:32:58] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[14:32:58] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[14:32:58] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[14:32:58] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[14:32:58] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[14:32:58] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[14:32:58] [PASSED] Automatic
[14:32:58] [PASSED] Full
[14:32:58] [PASSED] Limited 16:235
[14:32:58] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[14:32:58] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[14:32:58] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[14:32:58] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[14:32:58] === drm_test_drm_hdmi_connector_get_output_format_name ====
[14:32:58] [PASSED] RGB
[14:32:58] [PASSED] YUV 4:2:0
[14:32:58] [PASSED] YUV 4:2:2
[14:32:58] [PASSED] YUV 4:4:4
[14:32:58] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[14:32:58] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[14:32:58] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[14:32:58] ============= drm_damage_helper (21 subtests) ==============
[14:32:58] [PASSED] drm_test_damage_iter_no_damage
[14:32:58] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[14:32:58] [PASSED] drm_test_damage_iter_no_damage_src_moved
[14:32:58] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[14:32:58] [PASSED] drm_test_damage_iter_no_damage_not_visible
[14:32:58] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[14:32:58] [PASSED] drm_test_damage_iter_no_damage_no_fb
[14:32:58] [PASSED] drm_test_damage_iter_simple_damage
[14:32:58] [PASSED] drm_test_damage_iter_single_damage
[14:32:58] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[14:32:58] [PASSED] drm_test_damage_iter_single_damage_outside_src
[14:32:58] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[14:32:58] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[14:32:58] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[14:32:58] [PASSED] drm_test_damage_iter_single_damage_src_moved
[14:32:58] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[14:32:58] [PASSED] drm_test_damage_iter_damage
[14:32:58] [PASSED] drm_test_damage_iter_damage_one_intersect
[14:32:58] [PASSED] drm_test_damage_iter_damage_one_outside
[14:32:58] [PASSED] drm_test_damage_iter_damage_src_moved
[14:32:58] [PASSED] drm_test_damage_iter_damage_not_visible
[14:32:58] ================ [PASSED] drm_damage_helper ================
[14:32:58] ============== drm_dp_mst_helper (3 subtests) ==============
[14:32:58] ============== drm_test_dp_mst_calc_pbn_mode ==============
[14:32:58] [PASSED] Clock 154000 BPP 30 DSC disabled
[14:32:58] [PASSED] Clock 234000 BPP 30 DSC disabled
[14:32:58] [PASSED] Clock 297000 BPP 24 DSC disabled
[14:32:58] [PASSED] Clock 332880 BPP 24 DSC enabled
[14:32:58] [PASSED] Clock 324540 BPP 24 DSC enabled
[14:32:58] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[14:32:58] ============== drm_test_dp_mst_calc_pbn_div ===============
[14:32:58] [PASSED] Link rate 2000000 lane count 4
[14:32:58] [PASSED] Link rate 2000000 lane count 2
[14:32:58] [PASSED] Link rate 2000000 lane count 1
[14:32:58] [PASSED] Link rate 1350000 lane count 4
[14:32:58] [PASSED] Link rate 1350000 lane count 2
[14:32:58] [PASSED] Link rate 1350000 lane count 1
[14:32:58] [PASSED] Link rate 1000000 lane count 4
[14:32:58] [PASSED] Link rate 1000000 lane count 2
[14:32:58] [PASSED] Link rate 1000000 lane count 1
[14:32:58] [PASSED] Link rate 810000 lane count 4
[14:32:58] [PASSED] Link rate 810000 lane count 2
[14:32:58] [PASSED] Link rate 810000 lane count 1
[14:32:58] [PASSED] Link rate 540000 lane count 4
[14:32:58] [PASSED] Link rate 540000 lane count 2
[14:32:58] [PASSED] Link rate 540000 lane count 1
[14:32:58] [PASSED] Link rate 270000 lane count 4
[14:32:58] [PASSED] Link rate 270000 lane count 2
[14:32:58] [PASSED] Link rate 270000 lane count 1
[14:32:58] [PASSED] Link rate 162000 lane count 4
[14:32:58] [PASSED] Link rate 162000 lane count 2
[14:32:58] [PASSED] Link rate 162000 lane count 1
[14:32:58] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[14:32:58] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[14:32:58] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[14:32:58] [PASSED] DP_POWER_UP_PHY with port number
[14:32:58] [PASSED] DP_POWER_DOWN_PHY with port number
[14:32:58] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[14:32:58] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[14:32:58] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[14:32:58] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[14:32:58] [PASSED] DP_QUERY_PAYLOAD with port number
[14:32:58] [PASSED] DP_QUERY_PAYLOAD with VCPI
[14:32:58] [PASSED] DP_REMOTE_DPCD_READ with port number
[14:32:58] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[14:32:58] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[14:32:58] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[14:32:58] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[14:32:58] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[14:32:58] [PASSED] DP_REMOTE_I2C_READ with port number
[14:32:58] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[14:32:58] [PASSED] DP_REMOTE_I2C_READ with transactions array
[14:32:58] [PASSED] DP_REMOTE_I2C_WRITE with port number
[14:32:58] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[14:32:58] [PASSED] DP_REMOTE_I2C_WRITE with data array
[14:32:58] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[14:32:58] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[14:32:58] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[14:32:58] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[14:32:58] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[14:32:58] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[14:32:58] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[14:32:58] ================ [PASSED] drm_dp_mst_helper ================
[14:32:58] ================== drm_exec (7 subtests) ===================
[14:32:58] [PASSED] sanitycheck
[14:32:58] [PASSED] test_lock
[14:32:58] [PASSED] test_lock_unlock
[14:32:58] [PASSED] test_duplicates
[14:32:58] [PASSED] test_prepare
[14:32:58] [PASSED] test_prepare_array
[14:32:58] [PASSED] test_multiple_loops
[14:32:58] ==================== [PASSED] drm_exec =====================
[14:32:58] =========== drm_format_helper_test (17 subtests) ===========
[14:32:58] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[14:32:58] [PASSED] single_pixel_source_buffer
[14:32:58] [PASSED] single_pixel_clip_rectangle
[14:32:58] [PASSED] well_known_colors
[14:32:58] [PASSED] destination_pitch
[14:32:58] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[14:32:58] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[14:32:58] [PASSED] single_pixel_source_buffer
[14:32:58] [PASSED] single_pixel_clip_rectangle
[14:32:58] [PASSED] well_known_colors
[14:32:58] [PASSED] destination_pitch
[14:32:58] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[14:32:58] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[14:32:58] [PASSED] single_pixel_source_buffer
[14:32:58] [PASSED] single_pixel_clip_rectangle
[14:32:58] [PASSED] well_known_colors
[14:32:58] [PASSED] destination_pitch
[14:32:58] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[14:32:58] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[14:32:58] [PASSED] single_pixel_source_buffer
[14:32:58] [PASSED] single_pixel_clip_rectangle
[14:32:58] [PASSED] well_known_colors
[14:32:58] [PASSED] destination_pitch
[14:32:58] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[14:32:58] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[14:32:58] [PASSED] single_pixel_source_buffer
[14:32:58] [PASSED] single_pixel_clip_rectangle
[14:32:58] [PASSED] well_known_colors
[14:32:58] [PASSED] destination_pitch
[14:32:58] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[14:32:58] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[14:32:58] [PASSED] single_pixel_source_buffer
[14:32:58] [PASSED] single_pixel_clip_rectangle
[14:32:58] [PASSED] well_known_colors
[14:32:58] [PASSED] destination_pitch
[14:32:58] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[14:32:58] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[14:32:58] [PASSED] single_pixel_source_buffer
[14:32:58] [PASSED] single_pixel_clip_rectangle
[14:32:58] [PASSED] well_known_colors
[14:32:58] [PASSED] destination_pitch
[14:32:58] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[14:32:58] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[14:32:58] [PASSED] single_pixel_source_buffer
[14:32:58] [PASSED] single_pixel_clip_rectangle
[14:32:58] [PASSED] well_known_colors
[14:32:58] [PASSED] destination_pitch
[14:32:58] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[14:32:58] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[14:32:58] [PASSED] single_pixel_source_buffer
[14:32:58] [PASSED] single_pixel_clip_rectangle
[14:32:58] [PASSED] well_known_colors
[14:32:58] [PASSED] destination_pitch
[14:32:58] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[14:32:58] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[14:32:58] [PASSED] single_pixel_source_buffer
[14:32:58] [PASSED] single_pixel_clip_rectangle
[14:32:58] [PASSED] well_known_colors
[14:32:58] [PASSED] destination_pitch
[14:32:58] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[14:32:58] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[14:32:58] [PASSED] single_pixel_source_buffer
[14:32:58] [PASSED] single_pixel_clip_rectangle
[14:32:58] [PASSED] well_known_colors
[14:32:58] [PASSED] destination_pitch
[14:32:58] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[14:32:58] ============== drm_test_fb_xrgb8888_to_mono ===============
[14:32:58] [PASSED] single_pixel_source_buffer
[14:32:58] [PASSED] single_pixel_clip_rectangle
[14:32:58] [PASSED] well_known_colors
[14:32:58] [PASSED] destination_pitch
[14:32:58] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[14:32:58] ==================== drm_test_fb_swab =====================
[14:32:58] [PASSED] single_pixel_source_buffer
[14:32:58] [PASSED] single_pixel_clip_rectangle
[14:32:58] [PASSED] well_known_colors
[14:32:58] [PASSED] destination_pitch
[14:32:58] ================ [PASSED] drm_test_fb_swab =================
[14:32:58] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[14:32:58] [PASSED] single_pixel_source_buffer
[14:32:58] [PASSED] single_pixel_clip_rectangle
[14:32:58] [PASSED] well_known_colors
[14:32:58] [PASSED] destination_pitch
[14:32:58] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[14:32:58] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[14:32:58] [PASSED] single_pixel_source_buffer
[14:32:58] [PASSED] single_pixel_clip_rectangle
[14:32:58] [PASSED] well_known_colors
[14:32:58] [PASSED] destination_pitch
[14:32:58] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[14:32:58] ================= drm_test_fb_clip_offset =================
[14:32:58] [PASSED] pass through
[14:32:58] [PASSED] horizontal offset
[14:32:58] [PASSED] vertical offset
[14:32:58] [PASSED] horizontal and vertical offset
[14:32:58] [PASSED] horizontal offset (custom pitch)
[14:32:58] [PASSED] vertical offset (custom pitch)
[14:32:58] [PASSED] horizontal and vertical offset (custom pitch)
[14:32:58] ============= [PASSED] drm_test_fb_clip_offset =============
[14:32:58] =================== drm_test_fb_memcpy ====================
[14:32:58] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[14:32:58] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[14:32:58] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[14:32:58] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[14:32:58] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[14:32:58] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[14:32:58] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[14:32:58] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[14:32:58] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[14:32:58] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[14:32:58] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[14:32:58] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[14:32:58] =============== [PASSED] drm_test_fb_memcpy ================
[14:32:58] ============= [PASSED] drm_format_helper_test ==============
[14:32:58] ================= drm_format (18 subtests) =================
[14:32:58] [PASSED] drm_test_format_block_width_invalid
[14:32:58] [PASSED] drm_test_format_block_width_one_plane
[14:32:58] [PASSED] drm_test_format_block_width_two_plane
[14:32:58] [PASSED] drm_test_format_block_width_three_plane
[14:32:58] [PASSED] drm_test_format_block_width_tiled
[14:32:58] [PASSED] drm_test_format_block_height_invalid
[14:32:58] [PASSED] drm_test_format_block_height_one_plane
[14:32:58] [PASSED] drm_test_format_block_height_two_plane
[14:32:58] [PASSED] drm_test_format_block_height_three_plane
[14:32:58] [PASSED] drm_test_format_block_height_tiled
[14:32:58] [PASSED] drm_test_format_min_pitch_invalid
[14:32:58] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[14:32:58] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[14:32:58] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[14:32:58] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[14:32:58] [PASSED] drm_test_format_min_pitch_two_plane
[14:32:58] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[14:32:58] [PASSED] drm_test_format_min_pitch_tiled
[14:32:58] =================== [PASSED] drm_format ====================
[14:32:58] ============== drm_framebuffer (10 subtests) ===============
[14:32:58] ========== drm_test_framebuffer_check_src_coords ==========
[14:32:58] [PASSED] Success: source fits into fb
[14:32:58] [PASSED] Fail: overflowing fb with x-axis coordinate
[14:32:58] [PASSED] Fail: overflowing fb with y-axis coordinate
[14:32:58] [PASSED] Fail: overflowing fb with source width
[14:32:58] [PASSED] Fail: overflowing fb with source height
[14:32:58] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[14:32:58] [PASSED] drm_test_framebuffer_cleanup
[14:32:58] =============== drm_test_framebuffer_create ===============
[14:32:58] [PASSED] ABGR8888 normal sizes
[14:32:58] [PASSED] ABGR8888 max sizes
[14:32:58] [PASSED] ABGR8888 pitch greater than min required
[14:32:58] [PASSED] ABGR8888 pitch less than min required
[14:32:58] [PASSED] ABGR8888 Invalid width
[14:32:58] [PASSED] ABGR8888 Invalid buffer handle
[14:32:58] [PASSED] No pixel format
[14:32:58] [PASSED] ABGR8888 Width 0
[14:32:58] [PASSED] ABGR8888 Height 0
[14:32:58] [PASSED] ABGR8888 Out of bound height * pitch combination
[14:32:58] [PASSED] ABGR8888 Large buffer offset
[14:32:58] [PASSED] ABGR8888 Buffer offset for inexistent plane
[14:32:58] [PASSED] ABGR8888 Invalid flag
[14:32:58] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[14:32:58] [PASSED] ABGR8888 Valid buffer modifier
[14:32:58] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[14:32:58] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[14:32:58] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[14:32:58] [PASSED] NV12 Normal sizes
[14:32:58] [PASSED] NV12 Max sizes
[14:32:58] [PASSED] NV12 Invalid pitch
[14:32:58] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[14:32:58] [PASSED] NV12 different modifier per-plane
[14:32:58] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[14:32:58] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[14:32:58] [PASSED] NV12 Modifier for inexistent plane
[14:32:58] [PASSED] NV12 Handle for inexistent plane
[14:32:58] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[14:32:58] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[14:32:58] [PASSED] YVU420 Normal sizes
[14:32:58] [PASSED] YVU420 Max sizes
[14:32:58] [PASSED] YVU420 Invalid pitch
[14:32:58] [PASSED] YVU420 Different pitches
[14:32:58] [PASSED] YVU420 Different buffer offsets/pitches
[14:32:58] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[14:32:58] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[14:32:58] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[14:32:58] [PASSED] YVU420 Valid modifier
[14:32:58] [PASSED] YVU420 Different modifiers per plane
[14:32:58] [PASSED] YVU420 Modifier for inexistent plane
[14:32:58] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[14:32:58] [PASSED] X0L2 Normal sizes
[14:32:58] [PASSED] X0L2 Max sizes
[14:32:58] [PASSED] X0L2 Invalid pitch
[14:32:58] [PASSED] X0L2 Pitch greater than minimum required
[14:32:58] [PASSED] X0L2 Handle for inexistent plane
[14:32:58] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[14:32:58] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[14:32:58] [PASSED] X0L2 Valid modifier
[14:32:58] [PASSED] X0L2 Modifier for inexistent plane
[14:32:58] =========== [PASSED] drm_test_framebuffer_create ===========
[14:32:58] [PASSED] drm_test_framebuffer_free
[14:32:58] [PASSED] drm_test_framebuffer_init
[14:32:58] [PASSED] drm_test_framebuffer_init_bad_format
[14:32:58] [PASSED] drm_test_framebuffer_init_dev_mismatch
[14:32:58] [PASSED] drm_test_framebuffer_lookup
[14:32:58] [PASSED] drm_test_framebuffer_lookup_inexistent
[14:32:58] [PASSED] drm_test_framebuffer_modifiers_not_supported
[14:32:58] ================= [PASSED] drm_framebuffer =================
[14:32:58] ================ drm_gem_shmem (8 subtests) ================
[14:32:58] [PASSED] drm_gem_shmem_test_obj_create
[14:32:58] [PASSED] drm_gem_shmem_test_obj_create_private
[14:32:58] [PASSED] drm_gem_shmem_test_pin_pages
[14:32:58] [PASSED] drm_gem_shmem_test_vmap
[14:32:58] [PASSED] drm_gem_shmem_test_get_pages_sgt
[14:32:58] [PASSED] drm_gem_shmem_test_get_sg_table
[14:32:58] [PASSED] drm_gem_shmem_test_madvise
[14:32:58] [PASSED] drm_gem_shmem_test_purge
[14:32:58] ================== [PASSED] drm_gem_shmem ==================
[14:32:58] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[14:32:58] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[14:32:58] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[14:32:58] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[14:32:58] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[14:32:58] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[14:32:58] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[14:32:58] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[14:32:58] [PASSED] Automatic
[14:32:58] [PASSED] Full
[14:32:58] [PASSED] Limited 16:235
[14:32:58] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[14:32:58] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[14:32:58] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[14:32:58] [PASSED] drm_test_check_disable_connector
[14:32:58] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[14:32:58] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[14:32:58] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[14:32:58] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[14:32:58] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[14:32:58] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[14:32:58] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[14:32:58] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[14:32:58] [PASSED] drm_test_check_output_bpc_dvi
[14:32:58] [PASSED] drm_test_check_output_bpc_format_vic_1
[14:32:58] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[14:32:58] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[14:32:58] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[14:32:58] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[14:32:58] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[14:32:58] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[14:32:58] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[14:32:58] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[14:32:58] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[14:32:58] [PASSED] drm_test_check_broadcast_rgb_value
[14:32:58] [PASSED] drm_test_check_bpc_8_value
[14:32:58] [PASSED] drm_test_check_bpc_10_value
[14:32:58] [PASSED] drm_test_check_bpc_12_value
[14:32:58] [PASSED] drm_test_check_format_value
[14:32:58] [PASSED] drm_test_check_tmds_char_value
[14:32:58] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[14:32:58] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[14:32:58] [PASSED] drm_test_check_mode_valid
[14:32:58] [PASSED] drm_test_check_mode_valid_reject
[14:32:58] [PASSED] drm_test_check_mode_valid_reject_rate
[14:32:58] [PASSED] drm_test_check_mode_valid_reject_max_clock
[14:32:58] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[14:32:58] ================= drm_managed (2 subtests) =================
[14:32:58] [PASSED] drm_test_managed_release_action
[14:32:58] [PASSED] drm_test_managed_run_action
[14:32:58] =================== [PASSED] drm_managed ===================
[14:32:58] =================== drm_mm (6 subtests) ====================
[14:32:58] [PASSED] drm_test_mm_init
[14:32:58] [PASSED] drm_test_mm_debug
[14:32:58] [PASSED] drm_test_mm_align32
[14:32:58] [PASSED] drm_test_mm_align64
[14:32:58] [PASSED] drm_test_mm_lowest
[14:32:58] [PASSED] drm_test_mm_highest
[14:32:58] ===================== [PASSED] drm_mm ======================
[14:32:58] ============= drm_modes_analog_tv (5 subtests) =============
[14:32:58] [PASSED] drm_test_modes_analog_tv_mono_576i
[14:32:58] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[14:32:58] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[14:32:58] [PASSED] drm_test_modes_analog_tv_pal_576i
[14:32:58] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[14:32:58] =============== [PASSED] drm_modes_analog_tv ===============
[14:32:58] ============== drm_plane_helper (2 subtests) ===============
[14:32:58] =============== drm_test_check_plane_state ================
[14:32:58] [PASSED] clipping_simple
[14:32:58] [PASSED] clipping_rotate_reflect
[14:32:58] [PASSED] positioning_simple
[14:32:58] [PASSED] upscaling
[14:32:58] [PASSED] downscaling
[14:32:58] [PASSED] rounding1
[14:32:58] [PASSED] rounding2
[14:32:58] [PASSED] rounding3
[14:32:58] [PASSED] rounding4
[14:32:58] =========== [PASSED] drm_test_check_plane_state ============
[14:32:58] =========== drm_test_check_invalid_plane_state ============
[14:32:58] [PASSED] positioning_invalid
[14:32:58] [PASSED] upscaling_invalid
[14:32:58] [PASSED] downscaling_invalid
[14:32:58] ======= [PASSED] drm_test_check_invalid_plane_state ========
[14:32:58] ================ [PASSED] drm_plane_helper =================
[14:32:58] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[14:32:58] ====== drm_test_connector_helper_tv_get_modes_check =======
[14:32:58] [PASSED] None
[14:32:58] [PASSED] PAL
[14:32:58] [PASSED] NTSC
[14:32:58] [PASSED] Both, NTSC Default
[14:32:58] [PASSED] Both, PAL Default
[14:32:58] [PASSED] Both, NTSC Default, with PAL on command-line
[14:32:58] [PASSED] Both, PAL Default, with NTSC on command-line
[14:32:58] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[14:32:58] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[14:32:58] ================== drm_rect (9 subtests) ===================
[14:32:58] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[14:32:58] [PASSED] drm_test_rect_clip_scaled_not_clipped
[14:32:58] [PASSED] drm_test_rect_clip_scaled_clipped
[14:32:58] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[14:32:58] ================= drm_test_rect_intersect =================
[14:32:58] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[14:32:58] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[14:32:58] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[14:32:58] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[14:32:58] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[14:32:58] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[14:32:58] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[14:32:58] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[14:32:58] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[14:32:58] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[14:32:58] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[14:32:58] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[14:32:58] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[14:32:58] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[14:32:58] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[14:32:58] ============= [PASSED] drm_test_rect_intersect =============
[14:32:58] ================ drm_test_rect_calc_hscale ================
[14:32:58] [PASSED] normal use
[14:32:58] [PASSED] out of max range
[14:32:58] [PASSED] out of min range
[14:32:58] [PASSED] zero dst
[14:32:58] [PASSED] negative src
[14:32:58] [PASSED] negative dst
[14:32:58] ============ [PASSED] drm_test_rect_calc_hscale ============
[14:32:58] ================ drm_test_rect_calc_vscale ================
[14:32:58] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[14:32:58] [PASSED] out of max range
[14:32:58] [PASSED] out of min range
[14:32:58] [PASSED] zero dst
[14:32:58] [PASSED] negative src
[14:32:58] [PASSED] negative dst
[14:32:58] ============ [PASSED] drm_test_rect_calc_vscale ============
[14:32:58] ================== drm_test_rect_rotate ===================
[14:32:58] [PASSED] reflect-x
[14:32:58] [PASSED] reflect-y
[14:32:58] [PASSED] rotate-0
[14:32:58] [PASSED] rotate-90
[14:32:58] [PASSED] rotate-180
[14:32:58] [PASSED] rotate-270
[14:32:58] ============== [PASSED] drm_test_rect_rotate ===============
[14:32:58] ================ drm_test_rect_rotate_inv =================
[14:32:58] [PASSED] reflect-x
[14:32:58] [PASSED] reflect-y
[14:32:58] [PASSED] rotate-0
[14:32:58] [PASSED] rotate-90
[14:32:58] [PASSED] rotate-180
[14:32:58] [PASSED] rotate-270
[14:32:58] ============ [PASSED] drm_test_rect_rotate_inv =============
[14:32:58] ==================== [PASSED] drm_rect =====================
[14:32:58] ============ drm_sysfb_modeset_test (1 subtest) ============
[14:32:58] ============ drm_test_sysfb_build_fourcc_list =============
[14:32:58] [PASSED] no native formats
[14:32:58] [PASSED] XRGB8888 as native format
[14:32:58] [PASSED] remove duplicates
[14:32:58] [PASSED] convert alpha formats
[14:32:58] [PASSED] random formats
[14:32:58] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[14:32:58] ============= [PASSED] drm_sysfb_modeset_test ==============
[14:32:58] ============================================================
[14:32:58] Testing complete. Ran 622 tests: passed: 622
[14:32:58] Elapsed time: 27.409s total, 1.673s configuring, 25.318s building, 0.390s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[14:32:58] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[14:32:59] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[14:33:09] Starting KUnit Kernel (1/1)...
[14:33:09] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[14:33:09] ================= ttm_device (5 subtests) ==================
[14:33:09] [PASSED] ttm_device_init_basic
[14:33:09] [PASSED] ttm_device_init_multiple
[14:33:09] [PASSED] ttm_device_fini_basic
[14:33:09] [PASSED] ttm_device_init_no_vma_man
[14:33:09] ================== ttm_device_init_pools ==================
[14:33:09] [PASSED] No DMA allocations, no DMA32 required
[14:33:09] [PASSED] DMA allocations, DMA32 required
[14:33:09] [PASSED] No DMA allocations, DMA32 required
[14:33:09] [PASSED] DMA allocations, no DMA32 required
[14:33:09] ============== [PASSED] ttm_device_init_pools ==============
[14:33:09] =================== [PASSED] ttm_device ====================
[14:33:09] ================== ttm_pool (8 subtests) ===================
[14:33:09] ================== ttm_pool_alloc_basic ===================
[14:33:09] [PASSED] One page
[14:33:09] [PASSED] More than one page
[14:33:09] [PASSED] Above the allocation limit
[14:33:09] [PASSED] One page, with coherent DMA mappings enabled
[14:33:09] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[14:33:09] ============== [PASSED] ttm_pool_alloc_basic ===============
[14:33:09] ============== ttm_pool_alloc_basic_dma_addr ==============
[14:33:09] [PASSED] One page
[14:33:09] [PASSED] More than one page
[14:33:09] [PASSED] Above the allocation limit
[14:33:09] [PASSED] One page, with coherent DMA mappings enabled
[14:33:09] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[14:33:09] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[14:33:09] [PASSED] ttm_pool_alloc_order_caching_match
[14:33:09] [PASSED] ttm_pool_alloc_caching_mismatch
[14:33:09] [PASSED] ttm_pool_alloc_order_mismatch
[14:33:09] [PASSED] ttm_pool_free_dma_alloc
[14:33:09] [PASSED] ttm_pool_free_no_dma_alloc
[14:33:09] [PASSED] ttm_pool_fini_basic
[14:33:09] ==================== [PASSED] ttm_pool =====================
[14:33:09] ================ ttm_resource (8 subtests) =================
[14:33:09] ================= ttm_resource_init_basic =================
[14:33:09] [PASSED] Init resource in TTM_PL_SYSTEM
[14:33:09] [PASSED] Init resource in TTM_PL_VRAM
[14:33:09] [PASSED] Init resource in a private placement
[14:33:09] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[14:33:09] ============= [PASSED] ttm_resource_init_basic =============
[14:33:09] [PASSED] ttm_resource_init_pinned
[14:33:09] [PASSED] ttm_resource_fini_basic
[14:33:09] [PASSED] ttm_resource_manager_init_basic
[14:33:09] [PASSED] ttm_resource_manager_usage_basic
[14:33:09] [PASSED] ttm_resource_manager_set_used_basic
[14:33:09] [PASSED] ttm_sys_man_alloc_basic
[14:33:09] [PASSED] ttm_sys_man_free_basic
[14:33:09] ================== [PASSED] ttm_resource ===================
[14:33:09] =================== ttm_tt (15 subtests) ===================
[14:33:09] ==================== ttm_tt_init_basic ====================
[14:33:09] [PASSED] Page-aligned size
[14:33:09] [PASSED] Extra pages requested
[14:33:09] ================ [PASSED] ttm_tt_init_basic ================
[14:33:09] [PASSED] ttm_tt_init_misaligned
[14:33:09] [PASSED] ttm_tt_fini_basic
[14:33:09] [PASSED] ttm_tt_fini_sg
[14:33:09] [PASSED] ttm_tt_fini_shmem
[14:33:09] [PASSED] ttm_tt_create_basic
[14:33:09] [PASSED] ttm_tt_create_invalid_bo_type
[14:33:09] [PASSED] ttm_tt_create_ttm_exists
[14:33:09] [PASSED] ttm_tt_create_failed
[14:33:09] [PASSED] ttm_tt_destroy_basic
[14:33:09] [PASSED] ttm_tt_populate_null_ttm
[14:33:09] [PASSED] ttm_tt_populate_populated_ttm
[14:33:09] [PASSED] ttm_tt_unpopulate_basic
[14:33:09] [PASSED] ttm_tt_unpopulate_empty_ttm
[14:33:09] [PASSED] ttm_tt_swapin_basic
[14:33:09] ===================== [PASSED] ttm_tt ======================
[14:33:09] =================== ttm_bo (14 subtests) ===================
[14:33:09] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[14:33:09] [PASSED] Cannot be interrupted and sleeps
[14:33:09] [PASSED] Cannot be interrupted, locks straight away
[14:33:09] [PASSED] Can be interrupted, sleeps
[14:33:09] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[14:33:09] [PASSED] ttm_bo_reserve_locked_no_sleep
[14:33:09] [PASSED] ttm_bo_reserve_no_wait_ticket
[14:33:09] [PASSED] ttm_bo_reserve_double_resv
[14:33:09] [PASSED] ttm_bo_reserve_interrupted
[14:33:09] [PASSED] ttm_bo_reserve_deadlock
[14:33:09] [PASSED] ttm_bo_unreserve_basic
[14:33:09] [PASSED] ttm_bo_unreserve_pinned
[14:33:09] [PASSED] ttm_bo_unreserve_bulk
[14:33:09] [PASSED] ttm_bo_fini_basic
[14:33:09] [PASSED] ttm_bo_fini_shared_resv
[14:33:09] [PASSED] ttm_bo_pin_basic
[14:33:09] [PASSED] ttm_bo_pin_unpin_resource
[14:33:09] [PASSED] ttm_bo_multiple_pin_one_unpin
[14:33:09] ===================== [PASSED] ttm_bo ======================
[14:33:09] ============== ttm_bo_validate (21 subtests) ===============
[14:33:09] ============== ttm_bo_init_reserved_sys_man ===============
[14:33:09] [PASSED] Buffer object for userspace
[14:33:09] [PASSED] Kernel buffer object
[14:33:09] [PASSED] Shared buffer object
[14:33:09] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[14:33:09] ============== ttm_bo_init_reserved_mock_man ==============
[14:33:09] [PASSED] Buffer object for userspace
[14:33:09] [PASSED] Kernel buffer object
[14:33:09] [PASSED] Shared buffer object
[14:33:09] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[14:33:09] [PASSED] ttm_bo_init_reserved_resv
[14:33:09] ================== ttm_bo_validate_basic ==================
[14:33:09] [PASSED] Buffer object for userspace
[14:33:09] [PASSED] Kernel buffer object
[14:33:09] [PASSED] Shared buffer object
[14:33:09] ============== [PASSED] ttm_bo_validate_basic ==============
[14:33:09] [PASSED] ttm_bo_validate_invalid_placement
[14:33:09] ============= ttm_bo_validate_same_placement ==============
[14:33:09] [PASSED] System manager
[14:33:09] [PASSED] VRAM manager
[14:33:09] ========= [PASSED] ttm_bo_validate_same_placement ==========
[14:33:09] [PASSED] ttm_bo_validate_failed_alloc
[14:33:09] [PASSED] ttm_bo_validate_pinned
[14:33:09] [PASSED] ttm_bo_validate_busy_placement
[14:33:09] ================ ttm_bo_validate_multihop =================
[14:33:09] [PASSED] Buffer object for userspace
[14:33:09] [PASSED] Kernel buffer object
[14:33:09] [PASSED] Shared buffer object
[14:33:09] ============ [PASSED] ttm_bo_validate_multihop =============
[14:33:09] ========== ttm_bo_validate_no_placement_signaled ==========
[14:33:09] [PASSED] Buffer object in system domain, no page vector
[14:33:09] [PASSED] Buffer object in system domain with an existing page vector
[14:33:09] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[14:33:09] ======== ttm_bo_validate_no_placement_not_signaled ========
[14:33:09] [PASSED] Buffer object for userspace
[14:33:09] [PASSED] Kernel buffer object
[14:33:09] [PASSED] Shared buffer object
[14:33:09] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[14:33:09] [PASSED] ttm_bo_validate_move_fence_signaled
[14:33:09] ========= ttm_bo_validate_move_fence_not_signaled =========
[14:33:09] [PASSED] Waits for GPU
[14:33:09] [PASSED] Tries to lock straight away
[14:33:09] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[14:33:09] [PASSED] ttm_bo_validate_happy_evict
[14:33:09] [PASSED] ttm_bo_validate_all_pinned_evict
[14:33:09] [PASSED] ttm_bo_validate_allowed_only_evict
[14:33:09] [PASSED] ttm_bo_validate_deleted_evict
[14:33:09] [PASSED] ttm_bo_validate_busy_domain_evict
[14:33:09] [PASSED] ttm_bo_validate_evict_gutting
[14:33:09] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[14:33:09] ================= [PASSED] ttm_bo_validate =================
[14:33:09] ============================================================
[14:33:09] Testing complete. Ran 101 tests: passed: 101
[14:33:09] Elapsed time: 11.196s total, 1.671s configuring, 9.308s building, 0.171s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH v2 1/4] drm/ras: Introduce the DRM RAS infrastructure over generic netlink
2025-11-26 14:36 [PATCH v2 0/4] Introduce DRM_RAS using generic netlink for RAS Riana Tauro
2025-11-26 14:31 ` ✗ CI.checkpatch: warning for Introduce DRM_RAS using generic netlink for RAS (rev2) Patchwork
2025-11-26 14:33 ` ✓ CI.KUnit: success " Patchwork
@ 2025-11-26 14:36 ` Riana Tauro
2025-11-26 14:36 ` [PATCH v2 2/4] drm/xe/xe_drm_ras: Add support for drm ras Riana Tauro
` (2 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Riana Tauro @ 2025-11-26 14:36 UTC (permalink / raw)
To: intel-xe, dri-devel
Cc: aravind.iddamsetty, anshuman.gupta, rodrigo.vivi, joonas.lahtinen,
lukas, simona.vetter, airlied, lucas.demarchi, Zack McKevitt,
Lijo Lazar, Hawking Zhang, Jakub Kicinski, David S. Miller,
Paolo Abeni, Eric Dumazet, netdev, Riana Tauro
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Introduces the DRM RAS infrastructure over generic netlink.
The new interface allows drivers to expose RAS nodes and their
associated error counters to userspace in a structured and extensible
way. Each drm_ras node can register its own set of error counters, which
are then discoverable and queryable through netlink operations. This
lays the groundwork for reporting and managing hardware error states
in a unified manner across different DRM drivers.
Currently is only supports error-counter nodes. But it can be
extended later.
The registration is also no tied to any drm node, so it can be
used by accel devices as well.
It uses the new and mandatory YAML description format stored in
Documentation/netlink/specs/. This forces a single generic netlink
family namespace for the entire drm: "drm-ras".
But multiple-endpoints are supported within the single family.
Any modification to this API needs to be applied to
Documentation/netlink/specs/drm_ras.yaml before regenerating the
code:
$ tools/net/ynl/pyynl/ynl_gen_c.py --spec \
Documentation/netlink/specs/drm_ras.yaml --mode uapi --header \
> include/uapi/drm/drm_ras.h
$ tools/net/ynl/pyynl/ynl_gen_c.py --spec \
Documentation/netlink/specs/drm_ras.yaml --mode kernel --header \
> include/drm/drm_ras_nl.h
$ tools/net/ynl/pyynl/ynl_gen_c.py --spec \
Documentation/netlink/specs/drm_ras.yaml --mode kernel --source \
> drivers/gpu/drm/drm_ras_nl.c
Cc: Zack McKevitt <zachary.mckevitt@oss.qualcomm.com>
Cc: Lukas Wunner <lukas@wunner.de>
Cc: Lijo Lazar <lijo.lazar@amd.com>
Cc: Hawking Zhang <Hawking.Zhang@amd.com>
Cc: Jakub Kicinski <kuba@kernel.org>
Cc: David S. Miller <davem@davemloft.net>
Cc: Paolo Abeni <pabeni@redhat.com>
Cc: Eric Dumazet <edumazet@google.com>
Cc: netdev@vger.kernel.org
Co-developed-by: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Riana Tauro <riana.tauro@intel.com>
---
v2: fix doc and memory leak
use xe_for_each_start
use standard genlmsg_iput (Jakub Kicinski)
---
Documentation/gpu/drm-ras.rst | 107 +++++++
Documentation/netlink/specs/drm_ras.yaml | 130 +++++++++
drivers/gpu/drm/Kconfig | 9 +
drivers/gpu/drm/Makefile | 1 +
drivers/gpu/drm/drm_drv.c | 6 +
drivers/gpu/drm/drm_ras.c | 351 +++++++++++++++++++++++
drivers/gpu/drm/drm_ras_genl_family.c | 42 +++
drivers/gpu/drm/drm_ras_nl.c | 54 ++++
include/drm/drm_ras.h | 76 +++++
include/drm/drm_ras_genl_family.h | 17 ++
include/drm/drm_ras_nl.h | 24 ++
include/uapi/drm/drm_ras.h | 49 ++++
12 files changed, 866 insertions(+)
create mode 100644 Documentation/gpu/drm-ras.rst
create mode 100644 Documentation/netlink/specs/drm_ras.yaml
create mode 100644 drivers/gpu/drm/drm_ras.c
create mode 100644 drivers/gpu/drm/drm_ras_genl_family.c
create mode 100644 drivers/gpu/drm/drm_ras_nl.c
create mode 100644 include/drm/drm_ras.h
create mode 100644 include/drm/drm_ras_genl_family.h
create mode 100644 include/drm/drm_ras_nl.h
create mode 100644 include/uapi/drm/drm_ras.h
diff --git a/Documentation/gpu/drm-ras.rst b/Documentation/gpu/drm-ras.rst
new file mode 100644
index 000000000000..802b3797e6e2
--- /dev/null
+++ b/Documentation/gpu/drm-ras.rst
@@ -0,0 +1,107 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+============================
+DRM RAS over Generic Netlink
+============================
+
+The DRM RAS (Reliability, Availability, Serviceability) interface provides a
+standardized way for GPU/accelerator drivers to expose error counters and
+other reliability nodes to user space via Generic Netlink. This allows
+diagnostic tools, monitoring daemons, or test infrastructure to query hardware
+health in a uniform way across different DRM drivers.
+
+Key Goals:
+
+* Provide a standardized RAS solution for GPU and accelerator drivers, enabling
+ data center monitoring and reliability operations.
+* Implement a single drm-ras Generic Netlink family to meet modern Netlink YAML
+ specifications and centralize all RAS-related communication in one namespace.
+* Support a basic error counter interface, addressing the immediate, essential
+ monitoring needs.
+* Offer a flexible, future-proof interface that can be extended to support
+ additional types of RAS data in the future.
+* Allow multiple nodes per driver, enabling drivers to register separate
+ nodes for different IP blocks, sub-blocks, or other logical subdivisions
+ as applicable.
+
+Nodes
+=====
+
+Nodes are logical abstractions representing an error source or block within
+the device. Currently, only error counter nodes is supported.
+
+Drivers are responsible for registering and unregistering nodes via the
+`drm_ras_node_register()` and `drm_ras_node_unregister()` APIs.
+
+Node Management
+-------------------
+
+.. kernel-doc:: drivers/gpu/drm/drm_ras.c
+ :doc: DRM RAS Node Management
+.. kernel-doc:: drivers/gpu/drm/drm_ras.c
+ :internal:
+
+Generic Netlink Usage
+=====================
+
+The interface is implemented as a Generic Netlink family named ``drm-ras``.
+User space tools can:
+
+* List registered nodes with the ``get-nodes`` command.
+* List all error counters in an node with the ``get-error-counters`` command.
+* Query error counters using the ``query-error-counter`` command.
+
+YAML-based Interface
+--------------------
+
+The interface is described in a YAML specification:
+
+:ref:`Documentation/netlink/specs/drm_ras.yaml`
+
+This YAML is used to auto-generate user space bindings via
+``tools/net/ynl/pyynl/ynl_gen_c.py``, and drives the structure of netlink
+attributes and operations.
+
+Usage Notes
+-----------
+
+* User space must first enumerate nodes to obtain their IDs.
+* Node IDs are then used for all further queries, such as error counters.
+* The interface supports future extension by adding new node types and
+ additional attributes.
+
+Example: List nodes using ynl
+
+.. code-block:: bash
+
+ sudo ynl --family drm_ras --dump list-nodes
+ [{'device-name': '0000:03:00.0',
+ 'node-id': 0,
+ 'node-name': 'correctable-errors',
+ 'node-type': 'error-counter'},
+ {'device-name': '0000:03:00.0',
+ 'node-id': 1,
+ 'node-name': 'nonfatal-errors',
+ 'node-type': 'error-counter'},
+ {'device-name': '0000:03:00.0',
+ 'node-id': 2,
+ 'node-name': 'fatal-errors',
+ 'node-type': 'error-counter'}]
+
+Example: List all error counters using ynl
+
+.. code-block:: bash
+
+
+ sudo ynl --family drm_ras --dump get-error-counters --json '{"node-id":1}'
+ [{'error-id': 1, 'error-name': 'error_name_1', 'error-value': 0},
+ {'error-id': 2, 'error-name': 'error_name_2', 'error-value': 0}]
+
+
+Example: Query an error counter for a given node
+
+.. code-block:: bash
+
+ sudo ynl --family drm_ras --do query-error-counter --json '{"node-id":2, "error-id":1}'
+ {'error-id': 1, 'error-name': 'error_name_1', 'error-value': 0}
+
diff --git a/Documentation/netlink/specs/drm_ras.yaml b/Documentation/netlink/specs/drm_ras.yaml
new file mode 100644
index 000000000000..be0e379c5bc9
--- /dev/null
+++ b/Documentation/netlink/specs/drm_ras.yaml
@@ -0,0 +1,130 @@
+# SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
+---
+name: drm-ras
+protocol: genetlink
+uapi-header: drm/drm_ras.h
+
+doc: >-
+ DRM RAS (Reliability, Availability, Serviceability) over Generic Netlink.
+ Provides a standardized mechanism for DRM drivers to register "nodes"
+ representing hardware/software components capable of reporting error counters.
+ Userspace tools can query the list of nodes or individual error counters
+ via the Generic Netlink interface.
+
+definitions:
+ -
+ type: enum
+ name: node-type
+ value-start: 1
+ entries: [error-counter]
+ doc: >-
+ Type of the node. Currently, only error-counter nodes are
+ supported, which expose reliability counters for a hardware/software
+ component.
+
+attribute-sets:
+ -
+ name: node-attrs
+ attributes:
+ -
+ name: node-id
+ type: u32
+ doc: >-
+ Unique identifier for the node.
+ Assigned dynamically by the DRM RAS core upon registration.
+ -
+ name: device-name
+ type: string
+ doc: >-
+ Device name chosen by the driver at registration.
+ Can be a PCI BDF, UUID, or module name if unique.
+ -
+ name: node-name
+ type: string
+ doc: >-
+ Node name chosen by the driver at registration.
+ Can be an IP block name, or any name that identifies the
+ RAS node inside the device.
+ -
+ name: node-type
+ type: u32
+ doc: Type of this node, identifying its function.
+ enum: node-type
+ -
+ name: error-counter-attrs
+ attributes:
+ -
+ name: node-id
+ type: u32
+ doc: Node ID targeted by this error counter operation.
+ -
+ name: error-id
+ type: u32
+ doc: Unique identifier for a specific error counter within an node.
+ -
+ name: error-name
+ type: string
+ doc: Name of the error.
+ -
+ name: error-value
+ type: u32
+ doc: Current value of the requested error counter.
+
+operations:
+ list:
+ -
+ name: list-nodes
+ doc: >-
+ Retrieve the full list of currently registered DRM RAS nodes.
+ Each node includes its dynamically assigned ID, name, and type.
+ **Important:** User space must call this operation first to obtain
+ the node IDs. These IDs are required for all subsequent
+ operations on nodes, such as querying error counters.
+ attribute-set: node-attrs
+ flags: [admin-perm]
+ dump:
+ reply:
+ attributes:
+ - node-id
+ - device-name
+ - node-name
+ - node-type
+ -
+ name: get-error-counters
+ doc: >-
+ Retrieve the full list of error counters for a given node.
+ The response include the id, the name, and even the current
+ value of each counter.
+ attribute-set: error-counter-attrs
+ flags: [admin-perm]
+ dump:
+ request:
+ attributes:
+ - node-id
+ reply:
+ attributes:
+ - error-id
+ - error-name
+ - error-value
+ -
+ name: query-error-counter
+ doc: >-
+ Query the information of a specific error counter for a given node.
+ Users must provide the node ID and the error counter ID.
+ The response contains the id, the name, and the current value
+ of the counter.
+ attribute-set: error-counter-attrs
+ flags: [admin-perm]
+ do:
+ request:
+ attributes:
+ - node-id
+ - error-id
+ reply:
+ attributes:
+ - error-id
+ - error-name
+ - error-value
+
+kernel-family:
+ headers: ["drm/drm_ras_nl.h"]
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 7e6bc0b3a589..5cfb23b80441 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -130,6 +130,15 @@ config DRM_PANIC_SCREEN_QR_VERSION
Smaller QR code are easier to read, but will contain less debugging
data. Default is 40.
+config DRM_RAS
+ bool "DRM RAS support"
+ depends on DRM
+ help
+ Enables the DRM RAS (Reliability, Availability and Serviceability)
+ support for DRM drivers. This provides a Generic Netlink interface
+ for error reporting and queries.
+ If in doubt, say "N".
+
config DRM_DEBUG_DP_MST_TOPOLOGY_REFS
bool "Enable refcount backtrace history in the DP MST helpers"
depends on STACKTRACE_SUPPORT
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 7789f42027ff..1fab172f583d 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -93,6 +93,7 @@ drm-$(CONFIG_DRM_ACCEL) += ../../accel/drm_accel.o
drm-$(CONFIG_DRM_PANIC) += drm_panic.o
drm-$(CONFIG_DRM_DRAW) += drm_draw.o
drm-$(CONFIG_DRM_PANIC_SCREEN_QR_CODE) += drm_panic_qr.o
+drm-$(CONFIG_DRM_RAS) += drm_ras.o drm_ras_nl.o drm_ras_genl_family.o
obj-$(CONFIG_DRM) += drm.o
obj-$(CONFIG_DRM_PANEL_ORIENTATION_QUIRKS) += drm_panel_orientation_quirks.o
diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
index 8e3cb08241c8..96841b5c0b9d 100644
--- a/drivers/gpu/drm/drm_drv.c
+++ b/drivers/gpu/drm/drm_drv.c
@@ -53,6 +53,7 @@
#include <drm/drm_panic.h>
#include <drm/drm_print.h>
#include <drm/drm_privacy_screen_machine.h>
+#include <drm/drm_ras_genl_family.h>
#include "drm_crtc_internal.h"
#include "drm_internal.h"
@@ -1220,6 +1221,7 @@ static const struct file_operations drm_stub_fops = {
static void drm_core_exit(void)
{
+ drm_ras_genl_family_unregister();
drm_privacy_screen_lookup_exit();
drm_panic_exit();
accel_core_exit();
@@ -1258,6 +1260,10 @@ static int __init drm_core_init(void)
drm_privacy_screen_lookup_init();
+ ret = drm_ras_genl_family_register();
+ if (ret < 0)
+ goto error;
+
drm_core_init_complete = true;
DRM_DEBUG("Initialized\n");
diff --git a/drivers/gpu/drm/drm_ras.c b/drivers/gpu/drm/drm_ras.c
new file mode 100644
index 000000000000..32f3897ce580
--- /dev/null
+++ b/drivers/gpu/drm/drm_ras.c
@@ -0,0 +1,351 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/netdevice.h>
+#include <linux/xarray.h>
+#include <net/genetlink.h>
+
+#include <drm/drm_ras.h>
+
+/**
+ * DOC: DRM RAS Node Management
+ *
+ * This module provides the infrastructure to manage RAS (Reliability,
+ * Availability, and Serviceability) nodes for DRM drivers. Each
+ * DRM driver may register one or more RAS nodes, which represent
+ * logical components capable of reporting error counters and other
+ * reliability metrics.
+ *
+ * The nodes are stored in a global xarray `drm_ras_xa` to allow
+ * efficient lookup by ID. Nodes can be registered or unregistered
+ * dynamically at runtime.
+ *
+ * A Generic Netlink family `drm_ras` exposes two main operations to
+ * userspace:
+ *
+ * 1. LIST_NODES: Dump all currently registered RAS nodes.
+ * The user receives an array of node IDs, names, and types.
+ *
+ * 2. GET_ERROR_COUNTERS: Dump all error counters of a given node.
+ * The user receives an array of error IDs, names, and current value.
+ *
+ * 3. QUERY_ERROR_COUNTER: Query a specific error counter for a given node.
+ * Userspace must provide the node ID and the counter ID, and
+ * receives the ID, the error name, and its current value.
+ *
+ * Node registration:
+ * - drm_ras_node_register(): Registers a new node and assigns
+ * it a unique ID in the xarray.
+ * - drm_ras_node_unregister(): Removes a previously registered
+ * node from the xarray.
+ *
+ * Node type:
+ * - ERROR_COUNTER:
+ * + Currently, only error counters are supported.
+ * + The driver must implement the query_error_counter() callback to provide
+ * the name and the value of the error counter.
+ * + The driver must provide a error_counter_range.last value informing the
+ * last valid error ID.
+ * + The driver can provide a error_counter_range.first value informing the
+ * frst valid error ID.
+ * + The error counters in the driver doesn't need to be contiguous, but the
+ * driver must return -ENOENT to the query_error_counter as an indication
+ * that the ID should be skipped and not listed in the netlink API.
+ *
+ * Netlink handlers:
+ * - drm_ras_nl_list_nodes_dumpit(): Implements the LIST_NODES
+ * operation, iterating over the xarray.
+ * - drm_ras_nl_get_error_counters_dumpit(): Implements the GET_ERROR_COUNTERS
+ * operation, iterating over the know valid error_counter_range.
+ * - drm_ras_nl_query_error_counter_doit(): Implements the QUERY_ERROR_COUNTER
+ * operation, fetching a counter value from a specific node.
+ */
+
+static DEFINE_XARRAY_ALLOC(drm_ras_xa);
+
+/*
+ * The netlink callback context carries dump state across multiple dumpit calls
+ */
+struct drm_ras_ctx {
+ /* Which xarray id to restart the dump from */
+ unsigned long restart;
+};
+
+/**
+ * drm_ras_nl_list_nodes_dumpit() - Dump all registered RAS nodes
+ * @skb: Netlink message buffer
+ * @cb: Callback context for multi-part dumps
+ *
+ * Iterates over all registered RAS nodes in the global xarray and appends
+ * their attributes (ID, name, type) to the given netlink message buffer.
+ * Uses @cb->ctx to track progress in case the message buffer fills up, allowing
+ * multi-part dump support. On buffer overflow, updates the context to resume
+ * from the last node on the next invocation.
+ *
+ * Return: 0 if all nodes fit in @skb, number of bytes added to @skb if
+ * the buffer filled up (requires multi-part continuation), or
+ * a negative error code on failure.
+ */
+int drm_ras_nl_list_nodes_dumpit(struct sk_buff *skb,
+ struct netlink_callback *cb)
+{
+ const struct genl_info *info = genl_info_dump(cb);
+ struct drm_ras_ctx *ctx = (void *)cb->ctx;
+ struct drm_ras_node *node;
+ struct nlattr *hdr;
+ unsigned long id;
+ int ret;
+
+ xa_for_each_start(&drm_ras_xa, id, node, ctx->restart) {
+ hdr = genlmsg_iput(skb, info);
+ if (!hdr) {
+ ret = -EMSGSIZE;
+ break;
+ }
+
+ ret = nla_put_u32(skb, DRM_RAS_A_NODE_ATTRS_NODE_ID, node->id);
+ if (ret) {
+ genlmsg_cancel(skb, hdr);
+ break;
+ }
+
+ ret = nla_put_string(skb, DRM_RAS_A_NODE_ATTRS_DEVICE_NAME,
+ node->device_name);
+ if (ret) {
+ genlmsg_cancel(skb, hdr);
+ break;
+ }
+
+ ret = nla_put_string(skb, DRM_RAS_A_NODE_ATTRS_NODE_NAME,
+ node->node_name);
+ if (ret) {
+ genlmsg_cancel(skb, hdr);
+ break;
+ }
+
+ ret = nla_put_u32(skb, DRM_RAS_A_NODE_ATTRS_NODE_TYPE,
+ node->type);
+ if (ret) {
+ genlmsg_cancel(skb, hdr);
+ break;
+ }
+
+ genlmsg_end(skb, hdr);
+ }
+
+ if (ret == -EMSGSIZE)
+ ctx->restart = id;
+
+ return ret;
+}
+
+static int get_node_error_counter(u32 node_id, u32 error_id,
+ const char **name, u32 *value)
+{
+ struct drm_ras_node *node;
+
+ node = xa_load(&drm_ras_xa, node_id);
+ if (!node || !node->query_error_counter)
+ return -ENOENT;
+
+ if (error_id < node->error_counter_range.first ||
+ error_id > node->error_counter_range.last)
+ return -EINVAL;
+
+ return node->query_error_counter(node, error_id, name, value);
+}
+
+static int msg_reply_value(struct sk_buff *msg, u32 error_id,
+ const char *error_name, u32 value)
+{
+ int ret;
+
+ ret = nla_put_u32(msg, DRM_RAS_A_ERROR_COUNTER_ATTRS_ERROR_ID, error_id);
+ if (ret)
+ return ret;
+
+ ret = nla_put_string(msg, DRM_RAS_A_ERROR_COUNTER_ATTRS_ERROR_NAME,
+ error_name);
+ if (ret)
+ return ret;
+
+ return nla_put_u32(msg, DRM_RAS_A_ERROR_COUNTER_ATTRS_ERROR_VALUE,
+ value);
+}
+
+static int doit_reply_value(struct genl_info *info, u32 node_id,
+ u32 error_id)
+{
+ struct sk_buff *msg;
+ struct nlattr *hdr;
+ const char *error_name;
+ u32 value;
+ int ret;
+
+ msg = genlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL);
+ if (!msg)
+ return -ENOMEM;
+
+ hdr = genlmsg_iput(msg, info);
+ if (!hdr) {
+ nlmsg_free(msg);
+ return -EMSGSIZE;
+ }
+
+ ret = get_node_error_counter(node_id, error_id,
+ &error_name, &value);
+ if (ret)
+ return ret;
+
+ ret = msg_reply_value(msg, error_id, error_name, value);
+ if (ret) {
+ genlmsg_cancel(msg, hdr);
+ nlmsg_free(msg);
+ return ret;
+ }
+
+ genlmsg_end(msg, hdr);
+
+ return genlmsg_reply(msg, info);
+}
+
+/**
+ * drm_ras_nl_get_error_counters_dumpit() - Dump all Error Counters
+ * @skb: Netlink message buffer
+ * @cb: Callback context for multi-part dumps
+ *
+ * Iterates over all error counters in a given Node and appends
+ * their attributes (ID, name, value) to the given netlink message buffer.
+ * Uses @cb->ctx to track progress in case the message buffer fills up, allowing
+ * multi-part dump support. On buffer overflow, updates the context to resume
+ * from the last node on the next invocation.
+ *
+ * Return: 0 if all errors fit in @skb, number of bytes added to @skb if
+ * the buffer filled up (requires multi-part continuation), or
+ * a negative error code on failure.
+ */
+int drm_ras_nl_get_error_counters_dumpit(struct sk_buff *skb,
+ struct netlink_callback *cb)
+{
+ const struct genl_info *info = genl_info_dump(cb);
+ struct drm_ras_ctx *ctx = (void *)cb->ctx;
+ struct drm_ras_node *node;
+ struct nlattr *hdr;
+ const char *error_name;
+ u32 node_id, error_id, value;
+ int ret;
+
+ if (!info->attrs || !info->attrs[DRM_RAS_A_ERROR_COUNTER_ATTRS_NODE_ID])
+ return -EINVAL;
+
+ node_id = nla_get_u32(info->attrs[DRM_RAS_A_ERROR_COUNTER_ATTRS_NODE_ID]);
+
+ node = xa_load(&drm_ras_xa, node_id);
+ if (!node)
+ return -ENOENT;
+
+ for (error_id = max(node->error_counter_range.first, ctx->restart);
+ error_id <= node->error_counter_range.last;
+ error_id++) {
+ ret = get_node_error_counter(node_id, error_id,
+ &error_name, &value);
+ /*
+ * For non-contiguous range, driver return -ENOENT as indication
+ * to skip this ID when listing all errors.
+ */
+ if (ret == -ENOENT)
+ continue;
+ if (ret)
+ return ret;
+
+ hdr = genlmsg_iput(skb, info);
+
+ if (!hdr) {
+ ret = -EMSGSIZE;
+ break;
+ }
+
+ ret = msg_reply_value(skb, error_id, error_name, value);
+ if (ret) {
+ genlmsg_cancel(skb, hdr);
+ break;
+ }
+
+ genlmsg_end(skb, hdr);
+ }
+
+ if (ret == -EMSGSIZE)
+ ctx->restart = error_id;
+
+ return ret;
+}
+
+/**
+ * drm_ras_nl_query_error_counter_doit() - Query an error counter of an node
+ * @skb: Netlink message buffer
+ * @info: Generic Netlink info containing attributes of the request
+ *
+ * Extracts the node ID and error ID from the netlink attributes and
+ * retrieves the current value of the corresponding error counter. Sends the
+ * result back to the requesting user via the standard Genl reply.
+ *
+ * Return: 0 on success, or negative errno on failure.
+ */
+int drm_ras_nl_query_error_counter_doit(struct sk_buff *skb,
+ struct genl_info *info)
+{
+ u32 node_id, error_id;
+
+ if (!info->attrs ||
+ !info->attrs[DRM_RAS_A_ERROR_COUNTER_ATTRS_NODE_ID] ||
+ !info->attrs[DRM_RAS_A_ERROR_COUNTER_ATTRS_ERROR_ID])
+ return -EINVAL;
+
+ node_id = nla_get_u32(info->attrs[DRM_RAS_A_ERROR_COUNTER_ATTRS_NODE_ID]);
+ error_id = nla_get_u32(info->attrs[DRM_RAS_A_ERROR_COUNTER_ATTRS_ERROR_ID]);
+
+ return doit_reply_value(info, node_id, error_id);
+}
+
+/**
+ * drm_ras_node_register() - Register a new RAS node
+ * @node: Node structure to register
+ *
+ * Adds the given RAS node to the global node xarray and assigns it
+ * a unique ID. Both @node->name and @node->type must be valid.
+ *
+ * Return: 0 on success, or negative errno on failure:
+ */
+int drm_ras_node_register(struct drm_ras_node *node)
+{
+ if (!node->device_name || !node->node_name)
+ return -EINVAL;
+
+ /* Currently, only Error Counter Endpoinnts are supported */
+ if (node->type != DRM_RAS_NODE_TYPE_ERROR_COUNTER)
+ return -EINVAL;
+
+ /* Mandatorty entries for Error Counter Node */
+ if (node->type == DRM_RAS_NODE_TYPE_ERROR_COUNTER &&
+ (!node->error_counter_range.last || !node->query_error_counter))
+ return -EINVAL;
+
+ return xa_alloc(&drm_ras_xa, &node->id, node, xa_limit_32b, GFP_KERNEL);
+}
+EXPORT_SYMBOL(drm_ras_node_register);
+
+/**
+ * drm_ras_node_unregister() - Unregister a previously registered node
+ * @node: Node structure to unregister
+ *
+ * Removes the given node from the global node xarray using its ID.
+ */
+void drm_ras_node_unregister(struct drm_ras_node *node)
+{
+ xa_erase(&drm_ras_xa, node->id);
+}
+EXPORT_SYMBOL(drm_ras_node_unregister);
diff --git a/drivers/gpu/drm/drm_ras_genl_family.c b/drivers/gpu/drm/drm_ras_genl_family.c
new file mode 100644
index 000000000000..2d818b8c3808
--- /dev/null
+++ b/drivers/gpu/drm/drm_ras_genl_family.c
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#include <drm/drm_ras_genl_family.h>
+#include <drm/drm_ras_nl.h>
+
+/* Track family registration so the drm_exit can be called at any time */
+static bool registered;
+
+/**
+ * drm_ras_genl_family_register() - Register drm-ras genl family
+ *
+ * Only to be called one at drm_drv_init()
+ */
+int drm_ras_genl_family_register(void)
+{
+ int ret;
+
+ registered = false;
+
+ ret = genl_register_family(&drm_ras_nl_family);
+ if (ret)
+ return ret;
+
+ registered = true;
+ return 0;
+}
+
+/**
+ * drm_ras_genl_family_unregister() - Unregister drm-ras genl family
+ *
+ * To be called one at drm_drv_exit() at any moment, but only once.
+ */
+void drm_ras_genl_family_unregister(void)
+{
+ if (registered) {
+ genl_unregister_family(&drm_ras_nl_family);
+ registered = false;
+ }
+}
diff --git a/drivers/gpu/drm/drm_ras_nl.c b/drivers/gpu/drm/drm_ras_nl.c
new file mode 100644
index 000000000000..fcd1392410e4
--- /dev/null
+++ b/drivers/gpu/drm/drm_ras_nl.c
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
+/* Do not edit directly, auto-generated from: */
+/* Documentation/netlink/specs/drm_ras.yaml */
+/* YNL-GEN kernel source */
+
+#include <net/netlink.h>
+#include <net/genetlink.h>
+
+#include <uapi/drm/drm_ras.h>
+#include <drm/drm_ras_nl.h>
+
+/* DRM_RAS_CMD_GET_ERROR_COUNTERS - dump */
+static const struct nla_policy drm_ras_get_error_counters_nl_policy[DRM_RAS_A_ERROR_COUNTER_ATTRS_NODE_ID + 1] = {
+ [DRM_RAS_A_ERROR_COUNTER_ATTRS_NODE_ID] = { .type = NLA_U32, },
+};
+
+/* DRM_RAS_CMD_QUERY_ERROR_COUNTER - do */
+static const struct nla_policy drm_ras_query_error_counter_nl_policy[DRM_RAS_A_ERROR_COUNTER_ATTRS_ERROR_ID + 1] = {
+ [DRM_RAS_A_ERROR_COUNTER_ATTRS_NODE_ID] = { .type = NLA_U32, },
+ [DRM_RAS_A_ERROR_COUNTER_ATTRS_ERROR_ID] = { .type = NLA_U32, },
+};
+
+/* Ops table for drm_ras */
+static const struct genl_split_ops drm_ras_nl_ops[] = {
+ {
+ .cmd = DRM_RAS_CMD_LIST_NODES,
+ .dumpit = drm_ras_nl_list_nodes_dumpit,
+ .flags = GENL_ADMIN_PERM | GENL_CMD_CAP_DUMP,
+ },
+ {
+ .cmd = DRM_RAS_CMD_GET_ERROR_COUNTERS,
+ .dumpit = drm_ras_nl_get_error_counters_dumpit,
+ .policy = drm_ras_get_error_counters_nl_policy,
+ .maxattr = DRM_RAS_A_ERROR_COUNTER_ATTRS_NODE_ID,
+ .flags = GENL_ADMIN_PERM | GENL_CMD_CAP_DUMP,
+ },
+ {
+ .cmd = DRM_RAS_CMD_QUERY_ERROR_COUNTER,
+ .doit = drm_ras_nl_query_error_counter_doit,
+ .policy = drm_ras_query_error_counter_nl_policy,
+ .maxattr = DRM_RAS_A_ERROR_COUNTER_ATTRS_ERROR_ID,
+ .flags = GENL_ADMIN_PERM | GENL_CMD_CAP_DO,
+ },
+};
+
+struct genl_family drm_ras_nl_family __ro_after_init = {
+ .name = DRM_RAS_FAMILY_NAME,
+ .version = DRM_RAS_FAMILY_VERSION,
+ .netnsok = true,
+ .parallel_ops = true,
+ .module = THIS_MODULE,
+ .split_ops = drm_ras_nl_ops,
+ .n_split_ops = ARRAY_SIZE(drm_ras_nl_ops),
+};
diff --git a/include/drm/drm_ras.h b/include/drm/drm_ras.h
new file mode 100644
index 000000000000..bba47a282ef8
--- /dev/null
+++ b/include/drm/drm_ras.h
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef __DRM_RAS_H__
+#define __DRM_RAS_H__
+
+#include "drm_ras_nl.h"
+
+/**
+ * struct drm_ras_node - A DRM RAS Node
+ */
+struct drm_ras_node {
+ /** @id: Unique identifier for the node. Dynamically assigned. */
+ u32 id;
+ /**
+ * @device_name: Human-readable name of the device. Given by the driver.
+ */
+ const char *device_name;
+ /** @node_name: Human-readable name of the node. Given by the driver. */
+ const char *node_name;
+ /** @type: Type of the node (enum drm_ras_node_type). */
+ enum drm_ras_node_type type;
+
+ /* Error-Counter Related Callback and Variables */
+
+ /** @error_counter_range: Range of valid Error IDs for this node. */
+ struct {
+ /** @first: First valid Error ID. */
+ u32 first;
+ /** @last: Last valid Error ID. Mandatory entry. */
+ u32 last;
+ } error_counter_range;
+
+ /**
+ * @query_error_counter:
+ *
+ * This callback is used by drm-ras to query a specific error counter.
+ * counters supported by this node. Used for input check and to
+ * iterate in all counters.
+ *
+ * Driver should expect query_error_counters() to be called with
+ * error_id from `error_counter_range.first` to
+ * `error_counter_range.last`.
+ *
+ * The @query_error_counter is a mandatory callback for
+ * error_counter_node.
+ *
+ * Returns: 0 on success,
+ * -ENOENT when error_id is not supported as an indication that
+ * drm_ras should silently skip this entry. Used for
+ * supporting non-contiguous error ranges.
+ * Driver is responsible for maintaining the list of
+ * supported error IDs in the range of first to last.
+ * Other negative values on errors that should terminate the
+ * netlink query.
+ */
+ int (*query_error_counter)(struct drm_ras_node *ep, u32 error_id,
+ const char **name, u32 *val);
+
+ /** @priv: Driver private data */
+ void *priv;
+};
+
+struct drm_device;
+
+#if IS_ENABLED(CONFIG_DRM_RAS)
+int drm_ras_node_register(struct drm_ras_node *ep);
+void drm_ras_node_unregister(struct drm_ras_node *ep);
+#else
+static inline int drm_ras_node_register(struct drm_ras_node *ep) { return 0; }
+static inline void drm_ras_node_unregister(struct drm_ras_node *ep) { }
+#endif
+
+#endif
diff --git a/include/drm/drm_ras_genl_family.h b/include/drm/drm_ras_genl_family.h
new file mode 100644
index 000000000000..5931b53429f1
--- /dev/null
+++ b/include/drm/drm_ras_genl_family.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef __DRM_RAS_GENL_FAMILY_H__
+#define __DRM_RAS_GENL_FAMILY_H__
+
+#if IS_ENABLED(CONFIG_DRM_RAS)
+int drm_ras_genl_family_register(void);
+void drm_ras_genl_family_unregister(void);
+#else
+static inline int drm_ras_genl_family_register(void) { return 0; }
+static inline void drm_ras_genl_family_unregister(void) { }
+#endif
+
+#endif
diff --git a/include/drm/drm_ras_nl.h b/include/drm/drm_ras_nl.h
new file mode 100644
index 000000000000..9613b7d9ffdb
--- /dev/null
+++ b/include/drm/drm_ras_nl.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
+/* Do not edit directly, auto-generated from: */
+/* Documentation/netlink/specs/drm_ras.yaml */
+/* YNL-GEN kernel header */
+
+#ifndef _LINUX_DRM_RAS_GEN_H
+#define _LINUX_DRM_RAS_GEN_H
+
+#include <net/netlink.h>
+#include <net/genetlink.h>
+
+#include <uapi/drm/drm_ras.h>
+#include <drm/drm_ras_nl.h>
+
+int drm_ras_nl_list_nodes_dumpit(struct sk_buff *skb,
+ struct netlink_callback *cb);
+int drm_ras_nl_get_error_counters_dumpit(struct sk_buff *skb,
+ struct netlink_callback *cb);
+int drm_ras_nl_query_error_counter_doit(struct sk_buff *skb,
+ struct genl_info *info);
+
+extern struct genl_family drm_ras_nl_family;
+
+#endif /* _LINUX_DRM_RAS_GEN_H */
diff --git a/include/uapi/drm/drm_ras.h b/include/uapi/drm/drm_ras.h
new file mode 100644
index 000000000000..3415ba345ac8
--- /dev/null
+++ b/include/uapi/drm/drm_ras.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
+/* Do not edit directly, auto-generated from: */
+/* Documentation/netlink/specs/drm_ras.yaml */
+/* YNL-GEN uapi header */
+
+#ifndef _UAPI_LINUX_DRM_RAS_H
+#define _UAPI_LINUX_DRM_RAS_H
+
+#define DRM_RAS_FAMILY_NAME "drm-ras"
+#define DRM_RAS_FAMILY_VERSION 1
+
+/*
+ * Type of the node. Currently, only error-counter nodes are supported, which
+ * expose reliability counters for a hardware/software component.
+ */
+enum drm_ras_node_type {
+ DRM_RAS_NODE_TYPE_ERROR_COUNTER = 1,
+};
+
+enum {
+ DRM_RAS_A_NODE_ATTRS_NODE_ID = 1,
+ DRM_RAS_A_NODE_ATTRS_DEVICE_NAME,
+ DRM_RAS_A_NODE_ATTRS_NODE_NAME,
+ DRM_RAS_A_NODE_ATTRS_NODE_TYPE,
+
+ __DRM_RAS_A_NODE_ATTRS_MAX,
+ DRM_RAS_A_NODE_ATTRS_MAX = (__DRM_RAS_A_NODE_ATTRS_MAX - 1)
+};
+
+enum {
+ DRM_RAS_A_ERROR_COUNTER_ATTRS_NODE_ID = 1,
+ DRM_RAS_A_ERROR_COUNTER_ATTRS_ERROR_ID,
+ DRM_RAS_A_ERROR_COUNTER_ATTRS_ERROR_NAME,
+ DRM_RAS_A_ERROR_COUNTER_ATTRS_ERROR_VALUE,
+
+ __DRM_RAS_A_ERROR_COUNTER_ATTRS_MAX,
+ DRM_RAS_A_ERROR_COUNTER_ATTRS_MAX = (__DRM_RAS_A_ERROR_COUNTER_ATTRS_MAX - 1)
+};
+
+enum {
+ DRM_RAS_CMD_LIST_NODES = 1,
+ DRM_RAS_CMD_GET_ERROR_COUNTERS,
+ DRM_RAS_CMD_QUERY_ERROR_COUNTER,
+
+ __DRM_RAS_CMD_MAX,
+ DRM_RAS_CMD_MAX = (__DRM_RAS_CMD_MAX - 1)
+};
+
+#endif /* _UAPI_LINUX_DRM_RAS_H */
--
2.47.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v2 2/4] drm/xe/xe_drm_ras: Add support for drm ras
2025-11-26 14:36 [PATCH v2 0/4] Introduce DRM_RAS using generic netlink for RAS Riana Tauro
` (2 preceding siblings ...)
2025-11-26 14:36 ` [PATCH v2 1/4] drm/ras: Introduce the DRM RAS infrastructure over generic netlink Riana Tauro
@ 2025-11-26 14:36 ` Riana Tauro
2025-11-26 18:48 ` Rodrigo Vivi
2025-11-26 14:36 ` [PATCH v2 3/4] drm/xe/xe_hw_error: Add support for GT hardware errors Riana Tauro
2025-11-26 14:36 ` [PATCH v2 4/4] drm/xe/xe_hw_error: Add support for PVC SOC errors Riana Tauro
5 siblings, 1 reply; 10+ messages in thread
From: Riana Tauro @ 2025-11-26 14:36 UTC (permalink / raw)
To: intel-xe, dri-devel
Cc: aravind.iddamsetty, anshuman.gupta, rodrigo.vivi, joonas.lahtinen,
lukas, simona.vetter, airlied, lucas.demarchi, Riana Tauro
Allocate correctable, nonfatal and fatal nodes per xe device.
Each node contains error classes, counters and respective
query counter functions.
Add basic functionality to create and register drm nodes.
Signed-off-by: Riana Tauro <riana.tauro@intel.com>
---
drivers/gpu/drm/xe/Makefile | 1 +
drivers/gpu/drm/xe/xe_device_types.h | 4 +
drivers/gpu/drm/xe/xe_drm_ras.c | 221 ++++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_drm_ras.h | 12 ++
drivers/gpu/drm/xe/xe_drm_ras_types.h | 54 +++++++
drivers/gpu/drm/xe/xe_hw_error.c | 38 ++---
include/uapi/drm/xe_drm.h | 5 +
7 files changed, 313 insertions(+), 22 deletions(-)
create mode 100644 drivers/gpu/drm/xe/xe_drm_ras.c
create mode 100644 drivers/gpu/drm/xe/xe_drm_ras.h
create mode 100644 drivers/gpu/drm/xe/xe_drm_ras_types.h
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index b848da79a4e1..7bc805b33e12 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -41,6 +41,7 @@ xe-y += xe_bb.o \
xe_device_sysfs.o \
xe_dma_buf.o \
xe_drm_client.o \
+ xe_drm_ras.o \
xe_eu_stall.o \
xe_exec.o \
xe_exec_queue.o \
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 6ce3247d1bd8..69097e3b3995 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -13,6 +13,7 @@
#include <drm/ttm/ttm_device.h>
#include "xe_devcoredump_types.h"
+#include "xe_drm_ras_types.h"
#include "xe_heci_gsc.h"
#include "xe_late_bind_fw_types.h"
#include "xe_lmtt_types.h"
@@ -353,6 +354,9 @@ struct xe_device {
bool oob_initialized;
} wa_active;
+ /** @ras: ras structure for device */
+ struct xe_drm_ras ras;
+
/** @survivability: survivability information for device */
struct xe_survivability survivability;
diff --git a/drivers/gpu/drm/xe/xe_drm_ras.c b/drivers/gpu/drm/xe/xe_drm_ras.c
new file mode 100644
index 000000000000..5320e845e9d5
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_drm_ras.c
@@ -0,0 +1,221 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#include <drm/drm_managed.h>
+#include <drm/drm_ras.h>
+#include <drm/xe_drm.h>
+
+#include "xe_device.h"
+#include "xe_drm_ras.h"
+
+#define ERR_INFO(index, _name) \
+ [index] = { .name = _name, .counter = 0 }
+
+static struct xe_drm_ras_counter error_info[] = {
+ ERR_INFO(DRM_XE_GENL_CORE_COMPUTE, "GT Error"),
+};
+
+static int hw_query_error_counter(struct xe_drm_ras_counter *info,
+ u32 error_id, const char **name, u32 *val)
+{
+ *name = info[error_id].name;
+ *val = info[error_id].counter;
+
+ return 0;
+}
+
+static int query_non_fatal_error_counters(struct drm_ras_node *ep,
+ u32 error_id, const char **name,
+ u32 *val)
+{
+ struct xe_device *xe = ep->priv;
+ struct xe_drm_ras *ras = &xe->ras;
+ struct xe_drm_ras_counter *info = ras->info[HARDWARE_ERROR_NONFATAL];
+
+ if (error_id >= ARRAY_SIZE(error_info))
+ return -EINVAL;
+
+ if (!error_info[error_id].name)
+ return -ENOENT;
+
+ return hw_query_error_counter(info, error_id, name, val);
+}
+
+static int query_fatal_error_counters(struct drm_ras_node *ep,
+ u32 error_id, const char **name,
+ u32 *val)
+{
+ struct xe_device *xe = ep->priv;
+ struct xe_drm_ras *ras = &xe->ras;
+ struct xe_drm_ras_counter *info = ras->info[HARDWARE_ERROR_FATAL];
+
+ if (error_id >= ARRAY_SIZE(error_info))
+ return -EINVAL;
+
+ if (!error_info[error_id].name)
+ return -ENOENT;
+
+ return hw_query_error_counter(info, error_id, name, val);
+}
+
+static int query_correctable_error_counters(struct drm_ras_node *ep,
+ u32 error_id, const char **name,
+ u32 *val)
+{
+ struct xe_device *xe = ep->priv;
+ struct xe_drm_ras *ras = &xe->ras;
+ struct xe_drm_ras_counter *info = ras->info[HARDWARE_ERROR_CORRECTABLE];
+
+ if (error_id >= ARRAY_SIZE(error_info))
+ return -EINVAL;
+
+ if (!error_info[error_id].name)
+ return -ENOENT;
+
+ return hw_query_error_counter(info, error_id, name, val);
+}
+
+static struct xe_drm_ras_counter *allocate_and_copy_counters(struct xe_device *xe,
+ int count,
+ struct xe_drm_ras_counter *src)
+{
+ struct xe_drm_ras_counter *counter;
+
+ counter = drmm_kzalloc(&xe->drm, count * sizeof(struct xe_drm_ras_counter), GFP_KERNEL);
+ if (!counter)
+ return ERR_PTR(-ENOMEM);
+
+ memcpy(counter, src, count * sizeof(struct xe_drm_ras_counter));
+
+ return counter;
+}
+
+static int assign_node_params(struct xe_device *xe, struct drm_ras_node *node,
+ enum hardware_error hw_err)
+{
+ struct xe_drm_ras *ras = &xe->ras;
+ int count = 0, ret = 0;
+
+ count = ARRAY_SIZE(error_info);
+ node->error_counter_range.first = DRM_XE_GENL_CORE_COMPUTE;
+ node->error_counter_range.last = count - 1;
+
+ switch (hw_err) {
+ case HARDWARE_ERROR_CORRECTABLE:
+ ras->info[hw_err] = allocate_and_copy_counters(xe, count, error_info);
+ if (IS_ERR(ras->info[hw_err]))
+ return PTR_ERR(ras->info[hw_err]);
+ node->query_error_counter = query_correctable_error_counters;
+ break;
+ case HARDWARE_ERROR_NONFATAL:
+ ras->info[hw_err] = allocate_and_copy_counters(xe, count, error_info);
+ if (IS_ERR(ras->info[hw_err]))
+ return PTR_ERR(ras->info[hw_err]);
+ node->query_error_counter = query_non_fatal_error_counters;
+ break;
+ case HARDWARE_ERROR_FATAL:
+ ras->info[hw_err] = allocate_and_copy_counters(xe, count, error_info);
+ if (IS_ERR(ras->info[hw_err]))
+ return PTR_ERR(ras->info[hw_err]);
+ node->query_error_counter = query_fatal_error_counters;
+ break;
+ default:
+ break;
+ }
+
+ return ret;
+}
+
+static int register_nodes(struct xe_device *xe)
+{
+ struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
+ struct xe_drm_ras *ras = &xe->ras;
+ const char *device_name;
+ int i = 0, ret;
+
+ device_name = kasprintf(GFP_KERNEL, "%04x:%02x:%02x.%d",
+ pci_domain_nr(pdev->bus), pdev->bus->number,
+ PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
+
+ for (i = 0; i < HARDWARE_ERROR_MAX; i++) {
+ struct drm_ras_node *node = &ras->node[i];
+ const char *hw_err_str = hw_error_to_str(i);
+ const char *node_name;
+
+ node_name = kasprintf(GFP_KERNEL, "%s-errors", hw_err_str);
+
+ node->device_name = device_name;
+ node->node_name = node_name;
+ node->type = DRM_RAS_NODE_TYPE_ERROR_COUNTER;
+
+ ret = assign_node_params(xe, node, i);
+ if (ret) {
+ kfree(node->node_name);
+ return ret;
+ }
+
+ node->priv = xe;
+
+ ret = drm_ras_node_register(node);
+ if (ret) {
+ drm_err(&xe->drm, "Failed to register drm ras tile node\n");
+ kfree(node->node_name);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static void xe_drm_ras_unregister_nodes(void *arg)
+{
+ struct xe_device *xe = arg;
+ struct xe_drm_ras *ras = &xe->ras;
+ int i = 0;
+
+ for (i = 0; i < HARDWARE_ERROR_MAX; i++) {
+ struct drm_ras_node *node = &ras->node[i];
+
+ drm_ras_node_unregister(node);
+
+ kfree(node->node_name);
+ if (i == 0)
+ kfree(node->device_name);
+ }
+}
+
+/**
+ * xe_drm_ras_allocate_nodes - Allocate drm ras nodes
+ * @xe: xe device instance
+ *
+ * Allocate xe drm ras nodes for all errors in a tile
+ *
+ * Return: 0 on success, error code on failure
+ */
+int xe_drm_ras_allocate_nodes(struct xe_device *xe)
+{
+ struct drm_ras_node *node;
+ int err;
+
+ node = drmm_kzalloc(&xe->drm, HARDWARE_ERROR_MAX * sizeof(struct drm_ras_node), GFP_KERNEL);
+ if (!node)
+ return -ENOMEM;
+
+ xe->ras.node = node;
+
+ err = register_nodes(xe);
+ if (err) {
+ drm_err(&xe->drm, "Failed to register drm ras node\n");
+ return err;
+ }
+
+ err = devm_add_action_or_reset(xe->drm.dev, xe_drm_ras_unregister_nodes, xe);
+ if (err) {
+ drm_err(&xe->drm, "Failed to add action for xe drm_ras\n");
+ return err;
+ }
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/xe/xe_drm_ras.h b/drivers/gpu/drm/xe/xe_drm_ras.h
new file mode 100644
index 000000000000..6272b5da4e6d
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_drm_ras.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+#ifndef XE_DRM_RAS_H_
+#define XE_DRM_RAS_H_
+
+struct xe_device;
+
+int xe_drm_ras_allocate_nodes(struct xe_device *xe);
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_drm_ras_types.h b/drivers/gpu/drm/xe/xe_drm_ras_types.h
new file mode 100644
index 000000000000..452ff9a91510
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_drm_ras_types.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef _XE_DRM_RAS_TYPES_H_
+#define _XE_DRM_RAS_TYPES_H_
+
+#include <linux/limits.h>
+
+struct drm_ras_node;
+
+/* Error categories reported by hardware */
+enum hardware_error {
+ HARDWARE_ERROR_CORRECTABLE = 0,
+ HARDWARE_ERROR_NONFATAL = 1,
+ HARDWARE_ERROR_FATAL = 2,
+ HARDWARE_ERROR_MAX,
+};
+
+static inline const char *hw_error_to_str(const enum hardware_error hw_err)
+{
+ switch (hw_err) {
+ case HARDWARE_ERROR_CORRECTABLE:
+ return "correctable";
+ case HARDWARE_ERROR_NONFATAL:
+ return "nonfatal";
+ case HARDWARE_ERROR_FATAL:
+ return "fatal";
+ default:
+ return "UNKNOWN";
+ }
+}
+
+struct xe_drm_ras_counter {
+ const char *name;
+ int counter;
+};
+
+/**
+ * struct xe_drm_ras - xe drm ras structure
+ *
+ * This structure has details of error counters
+ */
+struct xe_drm_ras {
+ /** @node: DRM RAS node */
+ struct drm_ras_node *node;
+
+ /** @info: info array for all types of errors */
+ struct xe_drm_ras_counter *info[HARDWARE_ERROR_MAX];
+
+};
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
index 8c65291f36fc..2adc2e6540f6 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.c
+++ b/drivers/gpu/drm/xe/xe_hw_error.c
@@ -10,6 +10,7 @@
#include "regs/xe_irq_regs.h"
#include "xe_device.h"
+#include "xe_drm_ras.h"
#include "xe_hw_error.h"
#include "xe_mmio.h"
#include "xe_survivability_mode.h"
@@ -17,14 +18,6 @@
#define HEC_UNCORR_FW_ERR_BITS 4
extern struct fault_attr inject_csc_hw_error;
-/* Error categories reported by hardware */
-enum hardware_error {
- HARDWARE_ERROR_CORRECTABLE = 0,
- HARDWARE_ERROR_NONFATAL = 1,
- HARDWARE_ERROR_FATAL = 2,
- HARDWARE_ERROR_MAX,
-};
-
static const char * const hec_uncorrected_fw_errors[] = {
"Fatal",
"CSE Disabled",
@@ -32,20 +25,6 @@ static const char * const hec_uncorrected_fw_errors[] = {
"Data Corruption"
};
-static const char *hw_error_to_str(const enum hardware_error hw_err)
-{
- switch (hw_err) {
- case HARDWARE_ERROR_CORRECTABLE:
- return "CORRECTABLE";
- case HARDWARE_ERROR_NONFATAL:
- return "NONFATAL";
- case HARDWARE_ERROR_FATAL:
- return "FATAL";
- default:
- return "UNKNOWN";
- }
-}
-
static bool fault_inject_csc_hw_error(void)
{
return IS_ENABLED(CONFIG_DEBUG_FS) && should_fail(&inject_csc_hw_error, 1);
@@ -146,6 +125,20 @@ void xe_hw_error_irq_handler(struct xe_tile *tile, const u32 master_ctl)
hw_error_source_handler(tile, hw_err);
}
+static int hw_error_info_init(struct xe_device *xe)
+{
+ int ret;
+
+ if (xe->info.platform != XE_PVC)
+ return 0;
+
+ ret = xe_drm_ras_allocate_nodes(xe);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
/*
* Process hardware errors during boot
*/
@@ -178,5 +171,6 @@ void xe_hw_error_init(struct xe_device *xe)
INIT_WORK(&tile->csc_hw_error_work, csc_hw_error_work);
+ hw_error_info_init(xe);
process_hw_errors(xe);
}
diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
index 47853659a705..053cbe1aafbb 100644
--- a/include/uapi/drm/xe_drm.h
+++ b/include/uapi/drm/xe_drm.h
@@ -2273,6 +2273,11 @@ struct drm_xe_vm_query_mem_range_attr {
};
+/**
+ * RAS Counters
+ */
+#define DRM_XE_GENL_CORE_COMPUTE (1)
+
#if defined(__cplusplus)
}
#endif
--
2.47.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v2 2/4] drm/xe/xe_drm_ras: Add support for drm ras
2025-11-26 14:36 ` [PATCH v2 2/4] drm/xe/xe_drm_ras: Add support for drm ras Riana Tauro
@ 2025-11-26 18:48 ` Rodrigo Vivi
2025-12-02 3:27 ` Riana Tauro
0 siblings, 1 reply; 10+ messages in thread
From: Rodrigo Vivi @ 2025-11-26 18:48 UTC (permalink / raw)
To: Riana Tauro
Cc: intel-xe, dri-devel, aravind.iddamsetty, anshuman.gupta,
joonas.lahtinen, lukas, simona.vetter, airlied, lucas.demarchi
On Wed, Nov 26, 2025 at 08:06:45PM +0530, Riana Tauro wrote:
> Allocate correctable, nonfatal and fatal nodes per xe device.
> Each node contains error classes, counters and respective
> query counter functions.
>
> Add basic functionality to create and register drm nodes.
>
> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
> ---
> drivers/gpu/drm/xe/Makefile | 1 +
> drivers/gpu/drm/xe/xe_device_types.h | 4 +
> drivers/gpu/drm/xe/xe_drm_ras.c | 221 ++++++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_drm_ras.h | 12 ++
> drivers/gpu/drm/xe/xe_drm_ras_types.h | 54 +++++++
> drivers/gpu/drm/xe/xe_hw_error.c | 38 ++---
> include/uapi/drm/xe_drm.h | 5 +
> 7 files changed, 313 insertions(+), 22 deletions(-)
> create mode 100644 drivers/gpu/drm/xe/xe_drm_ras.c
> create mode 100644 drivers/gpu/drm/xe/xe_drm_ras.h
> create mode 100644 drivers/gpu/drm/xe/xe_drm_ras_types.h
>
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index b848da79a4e1..7bc805b33e12 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -41,6 +41,7 @@ xe-y += xe_bb.o \
> xe_device_sysfs.o \
> xe_dma_buf.o \
> xe_drm_client.o \
> + xe_drm_ras.o \
> xe_eu_stall.o \
> xe_exec.o \
> xe_exec_queue.o \
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index 6ce3247d1bd8..69097e3b3995 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -13,6 +13,7 @@
> #include <drm/ttm/ttm_device.h>
>
> #include "xe_devcoredump_types.h"
> +#include "xe_drm_ras_types.h"
> #include "xe_heci_gsc.h"
> #include "xe_late_bind_fw_types.h"
> #include "xe_lmtt_types.h"
> @@ -353,6 +354,9 @@ struct xe_device {
> bool oob_initialized;
> } wa_active;
>
> + /** @ras: ras structure for device */
> + struct xe_drm_ras ras;
> +
> /** @survivability: survivability information for device */
> struct xe_survivability survivability;
>
> diff --git a/drivers/gpu/drm/xe/xe_drm_ras.c b/drivers/gpu/drm/xe/xe_drm_ras.c
> new file mode 100644
> index 000000000000..5320e845e9d5
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_drm_ras.c
> @@ -0,0 +1,221 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#include <drm/drm_managed.h>
> +#include <drm/drm_ras.h>
> +#include <drm/xe_drm.h>
> +
> +#include "xe_device.h"
> +#include "xe_drm_ras.h"
> +
> +#define ERR_INFO(index, _name) \
> + [index] = { .name = _name, .counter = 0 }
> +
> +static struct xe_drm_ras_counter error_info[] = {
> + ERR_INFO(DRM_XE_GENL_CORE_COMPUTE, "GT Error"),
> +};
> +
> +static int hw_query_error_counter(struct xe_drm_ras_counter *info,
> + u32 error_id, const char **name, u32 *val)
> +{
> + *name = info[error_id].name;
> + *val = info[error_id].counter;
> +
> + return 0;
> +}
> +
> +static int query_non_fatal_error_counters(struct drm_ras_node *ep,
> + u32 error_id, const char **name,
> + u32 *val)
> +{
> + struct xe_device *xe = ep->priv;
> + struct xe_drm_ras *ras = &xe->ras;
> + struct xe_drm_ras_counter *info = ras->info[HARDWARE_ERROR_NONFATAL];
> +
> + if (error_id >= ARRAY_SIZE(error_info))
> + return -EINVAL;
> +
> + if (!error_info[error_id].name)
> + return -ENOENT;
> +
> + return hw_query_error_counter(info, error_id, name, val);
> +}
> +
> +static int query_fatal_error_counters(struct drm_ras_node *ep,
> + u32 error_id, const char **name,
> + u32 *val)
> +{
> + struct xe_device *xe = ep->priv;
> + struct xe_drm_ras *ras = &xe->ras;
> + struct xe_drm_ras_counter *info = ras->info[HARDWARE_ERROR_FATAL];
> +
> + if (error_id >= ARRAY_SIZE(error_info))
> + return -EINVAL;
> +
> + if (!error_info[error_id].name)
> + return -ENOENT;
> +
> + return hw_query_error_counter(info, error_id, name, val);
> +}
> +
> +static int query_correctable_error_counters(struct drm_ras_node *ep,
> + u32 error_id, const char **name,
> + u32 *val)
> +{
> + struct xe_device *xe = ep->priv;
> + struct xe_drm_ras *ras = &xe->ras;
> + struct xe_drm_ras_counter *info = ras->info[HARDWARE_ERROR_CORRECTABLE];
> +
> + if (error_id >= ARRAY_SIZE(error_info))
> + return -EINVAL;
> +
> + if (!error_info[error_id].name)
> + return -ENOENT;
> +
> + return hw_query_error_counter(info, error_id, name, val);
> +}
> +
> +static struct xe_drm_ras_counter *allocate_and_copy_counters(struct xe_device *xe,
> + int count,
> + struct xe_drm_ras_counter *src)
> +{
> + struct xe_drm_ras_counter *counter;
> +
> + counter = drmm_kzalloc(&xe->drm, count * sizeof(struct xe_drm_ras_counter), GFP_KERNEL);
> + if (!counter)
> + return ERR_PTR(-ENOMEM);
> +
> + memcpy(counter, src, count * sizeof(struct xe_drm_ras_counter));
> +
> + return counter;
> +}
> +
> +static int assign_node_params(struct xe_device *xe, struct drm_ras_node *node,
> + enum hardware_error hw_err)
> +{
> + struct xe_drm_ras *ras = &xe->ras;
> + int count = 0, ret = 0;
> +
> + count = ARRAY_SIZE(error_info);
> + node->error_counter_range.first = DRM_XE_GENL_CORE_COMPUTE;
> + node->error_counter_range.last = count - 1;
> +
> + switch (hw_err) {
> + case HARDWARE_ERROR_CORRECTABLE:
> + ras->info[hw_err] = allocate_and_copy_counters(xe, count, error_info);
> + if (IS_ERR(ras->info[hw_err]))
> + return PTR_ERR(ras->info[hw_err]);
> + node->query_error_counter = query_correctable_error_counters;
> + break;
> + case HARDWARE_ERROR_NONFATAL:
> + ras->info[hw_err] = allocate_and_copy_counters(xe, count, error_info);
> + if (IS_ERR(ras->info[hw_err]))
> + return PTR_ERR(ras->info[hw_err]);
> + node->query_error_counter = query_non_fatal_error_counters;
> + break;
> + case HARDWARE_ERROR_FATAL:
> + ras->info[hw_err] = allocate_and_copy_counters(xe, count, error_info);
> + if (IS_ERR(ras->info[hw_err]))
> + return PTR_ERR(ras->info[hw_err]);
> + node->query_error_counter = query_fatal_error_counters;
> + break;
> + default:
> + break;
> + }
> +
> + return ret;
> +}
> +
> +static int register_nodes(struct xe_device *xe)
> +{
> + struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
> + struct xe_drm_ras *ras = &xe->ras;
> + const char *device_name;
> + int i = 0, ret;
> +
> + device_name = kasprintf(GFP_KERNEL, "%04x:%02x:%02x.%d",
> + pci_domain_nr(pdev->bus), pdev->bus->number,
> + PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
> +
> + for (i = 0; i < HARDWARE_ERROR_MAX; i++) {
> + struct drm_ras_node *node = &ras->node[i];
> + const char *hw_err_str = hw_error_to_str(i);
> + const char *node_name;
> +
> + node_name = kasprintf(GFP_KERNEL, "%s-errors", hw_err_str);
> +
> + node->device_name = device_name;
> + node->node_name = node_name;
> + node->type = DRM_RAS_NODE_TYPE_ERROR_COUNTER;
> +
> + ret = assign_node_params(xe, node, i);
> + if (ret) {
> + kfree(node->node_name);
> + return ret;
> + }
> +
> + node->priv = xe;
> +
> + ret = drm_ras_node_register(node);
> + if (ret) {
> + drm_err(&xe->drm, "Failed to register drm ras tile node\n");
> + kfree(node->node_name);
> + return ret;
> + }
> + }
> +
> + return 0;
> +}
> +
> +static void xe_drm_ras_unregister_nodes(void *arg)
> +{
> + struct xe_device *xe = arg;
> + struct xe_drm_ras *ras = &xe->ras;
> + int i = 0;
> +
> + for (i = 0; i < HARDWARE_ERROR_MAX; i++) {
> + struct drm_ras_node *node = &ras->node[i];
> +
> + drm_ras_node_unregister(node);
> +
> + kfree(node->node_name);
> + if (i == 0)
> + kfree(node->device_name);
> + }
> +}
> +
> +/**
> + * xe_drm_ras_allocate_nodes - Allocate drm ras nodes
> + * @xe: xe device instance
> + *
> + * Allocate xe drm ras nodes for all errors in a tile
> + *
> + * Return: 0 on success, error code on failure
> + */
> +int xe_drm_ras_allocate_nodes(struct xe_device *xe)
> +{
> + struct drm_ras_node *node;
> + int err;
> +
> + node = drmm_kzalloc(&xe->drm, HARDWARE_ERROR_MAX * sizeof(struct drm_ras_node), GFP_KERNEL);
> + if (!node)
> + return -ENOMEM;
> +
> + xe->ras.node = node;
> +
> + err = register_nodes(xe);
> + if (err) {
> + drm_err(&xe->drm, "Failed to register drm ras node\n");
> + return err;
> + }
> +
> + err = devm_add_action_or_reset(xe->drm.dev, xe_drm_ras_unregister_nodes, xe);
> + if (err) {
> + drm_err(&xe->drm, "Failed to add action for xe drm_ras\n");
> + return err;
> + }
> +
> + return 0;
> +}
> diff --git a/drivers/gpu/drm/xe/xe_drm_ras.h b/drivers/gpu/drm/xe/xe_drm_ras.h
> new file mode 100644
> index 000000000000..6272b5da4e6d
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_drm_ras.h
> @@ -0,0 +1,12 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +#ifndef XE_DRM_RAS_H_
> +#define XE_DRM_RAS_H_
> +
> +struct xe_device;
> +
> +int xe_drm_ras_allocate_nodes(struct xe_device *xe);
> +
> +#endif
> diff --git a/drivers/gpu/drm/xe/xe_drm_ras_types.h b/drivers/gpu/drm/xe/xe_drm_ras_types.h
> new file mode 100644
> index 000000000000..452ff9a91510
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_drm_ras_types.h
> @@ -0,0 +1,54 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#ifndef _XE_DRM_RAS_TYPES_H_
> +#define _XE_DRM_RAS_TYPES_H_
> +
> +#include <linux/limits.h>
> +
> +struct drm_ras_node;
> +
> +/* Error categories reported by hardware */
> +enum hardware_error {
> + HARDWARE_ERROR_CORRECTABLE = 0,
> + HARDWARE_ERROR_NONFATAL = 1,
> + HARDWARE_ERROR_FATAL = 2,
> + HARDWARE_ERROR_MAX,
> +};
> +
> +static inline const char *hw_error_to_str(const enum hardware_error hw_err)
> +{
> + switch (hw_err) {
> + case HARDWARE_ERROR_CORRECTABLE:
> + return "correctable";
> + case HARDWARE_ERROR_NONFATAL:
> + return "nonfatal";
> + case HARDWARE_ERROR_FATAL:
> + return "fatal";
> + default:
> + return "UNKNOWN";
> + }
> +}
> +
> +struct xe_drm_ras_counter {
> + const char *name;
> + int counter;
> +};
> +
> +/**
> + * struct xe_drm_ras - xe drm ras structure
> + *
> + * This structure has details of error counters
> + */
> +struct xe_drm_ras {
> + /** @node: DRM RAS node */
> + struct drm_ras_node *node;
> +
> + /** @info: info array for all types of errors */
> + struct xe_drm_ras_counter *info[HARDWARE_ERROR_MAX];
> +
> +};
> +
> +#endif
> diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
> index 8c65291f36fc..2adc2e6540f6 100644
> --- a/drivers/gpu/drm/xe/xe_hw_error.c
> +++ b/drivers/gpu/drm/xe/xe_hw_error.c
> @@ -10,6 +10,7 @@
> #include "regs/xe_irq_regs.h"
>
> #include "xe_device.h"
> +#include "xe_drm_ras.h"
> #include "xe_hw_error.h"
> #include "xe_mmio.h"
> #include "xe_survivability_mode.h"
> @@ -17,14 +18,6 @@
> #define HEC_UNCORR_FW_ERR_BITS 4
> extern struct fault_attr inject_csc_hw_error;
>
> -/* Error categories reported by hardware */
> -enum hardware_error {
> - HARDWARE_ERROR_CORRECTABLE = 0,
> - HARDWARE_ERROR_NONFATAL = 1,
> - HARDWARE_ERROR_FATAL = 2,
> - HARDWARE_ERROR_MAX,
> -};
> -
> static const char * const hec_uncorrected_fw_errors[] = {
> "Fatal",
> "CSE Disabled",
> @@ -32,20 +25,6 @@ static const char * const hec_uncorrected_fw_errors[] = {
> "Data Corruption"
> };
>
> -static const char *hw_error_to_str(const enum hardware_error hw_err)
> -{
> - switch (hw_err) {
> - case HARDWARE_ERROR_CORRECTABLE:
> - return "CORRECTABLE";
> - case HARDWARE_ERROR_NONFATAL:
> - return "NONFATAL";
> - case HARDWARE_ERROR_FATAL:
> - return "FATAL";
> - default:
> - return "UNKNOWN";
> - }
> -}
> -
> static bool fault_inject_csc_hw_error(void)
> {
> return IS_ENABLED(CONFIG_DEBUG_FS) && should_fail(&inject_csc_hw_error, 1);
> @@ -146,6 +125,20 @@ void xe_hw_error_irq_handler(struct xe_tile *tile, const u32 master_ctl)
> hw_error_source_handler(tile, hw_err);
> }
>
> +static int hw_error_info_init(struct xe_device *xe)
> +{
> + int ret;
> +
> + if (xe->info.platform != XE_PVC)
> + return 0;
> +
> + ret = xe_drm_ras_allocate_nodes(xe);
> + if (ret)
> + return ret;
> +
> + return 0;
> +}
> +
> /*
> * Process hardware errors during boot
> */
> @@ -178,5 +171,6 @@ void xe_hw_error_init(struct xe_device *xe)
>
> INIT_WORK(&tile->csc_hw_error_work, csc_hw_error_work);
>
> + hw_error_info_init(xe);
> process_hw_errors(xe);
> }
> diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
> index 47853659a705..053cbe1aafbb 100644
> --- a/include/uapi/drm/xe_drm.h
> +++ b/include/uapi/drm/xe_drm.h
> @@ -2273,6 +2273,11 @@ struct drm_xe_vm_query_mem_range_attr {
>
> };
>
> +/**
> + * RAS Counters
> + */
> +#define DRM_XE_GENL_CORE_COMPUTE (1)
The feedback we got from Joonas is that we should also make the string name
an uAPI defined here in the header.
I'm afraid this series is missing that part for all the patches here.
Perhaps we should also mention this in the docs in the firs patch as well.
Other than that the series is great, thank you so much for picking that up!
> +
> #if defined(__cplusplus)
> }
> #endif
> --
> 2.47.1
>
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH v2 2/4] drm/xe/xe_drm_ras: Add support for drm ras
2025-11-26 18:48 ` Rodrigo Vivi
@ 2025-12-02 3:27 ` Riana Tauro
0 siblings, 0 replies; 10+ messages in thread
From: Riana Tauro @ 2025-12-02 3:27 UTC (permalink / raw)
To: Rodrigo Vivi
Cc: intel-xe, dri-devel, aravind.iddamsetty, anshuman.gupta,
joonas.lahtinen, lukas, simona.vetter, airlied, lucas.demarchi
On 11/27/2025 12:18 AM, Rodrigo Vivi wrote:
> On Wed, Nov 26, 2025 at 08:06:45PM +0530, Riana Tauro wrote:
>> Allocate correctable, nonfatal and fatal nodes per xe device.
>> Each node contains error classes, counters and respective
>> query counter functions.
>>
>> Add basic functionality to create and register drm nodes.
>>
>> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
>> ---
>> drivers/gpu/drm/xe/Makefile | 1 +
>> drivers/gpu/drm/xe/xe_device_types.h | 4 +
>> drivers/gpu/drm/xe/xe_drm_ras.c | 221 ++++++++++++++++++++++++++
>> drivers/gpu/drm/xe/xe_drm_ras.h | 12 ++
>> drivers/gpu/drm/xe/xe_drm_ras_types.h | 54 +++++++
>> drivers/gpu/drm/xe/xe_hw_error.c | 38 ++---
>> include/uapi/drm/xe_drm.h | 5 +
>> 7 files changed, 313 insertions(+), 22 deletions(-)
>> create mode 100644 drivers/gpu/drm/xe/xe_drm_ras.c
>> create mode 100644 drivers/gpu/drm/xe/xe_drm_ras.h
>> create mode 100644 drivers/gpu/drm/xe/xe_drm_ras_types.h
>>
>> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
>> index b848da79a4e1..7bc805b33e12 100644
>> --- a/drivers/gpu/drm/xe/Makefile
>> +++ b/drivers/gpu/drm/xe/Makefile
>> @@ -41,6 +41,7 @@ xe-y += xe_bb.o \
>> xe_device_sysfs.o \
>> xe_dma_buf.o \
>> xe_drm_client.o \
>> + xe_drm_ras.o \
>> xe_eu_stall.o \
>> xe_exec.o \
>> xe_exec_queue.o \
>> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
>> index 6ce3247d1bd8..69097e3b3995 100644
>> --- a/drivers/gpu/drm/xe/xe_device_types.h
>> +++ b/drivers/gpu/drm/xe/xe_device_types.h
>> @@ -13,6 +13,7 @@
>> #include <drm/ttm/ttm_device.h>
>>
>> #include "xe_devcoredump_types.h"
>> +#include "xe_drm_ras_types.h"
>> #include "xe_heci_gsc.h"
>> #include "xe_late_bind_fw_types.h"
>> #include "xe_lmtt_types.h"
>> @@ -353,6 +354,9 @@ struct xe_device {
>> bool oob_initialized;
>> } wa_active;
>>
>> + /** @ras: ras structure for device */
>> + struct xe_drm_ras ras;
>> +
>> /** @survivability: survivability information for device */
>> struct xe_survivability survivability;
>>
>> diff --git a/drivers/gpu/drm/xe/xe_drm_ras.c b/drivers/gpu/drm/xe/xe_drm_ras.c
>> new file mode 100644
>> index 000000000000..5320e845e9d5
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/xe_drm_ras.c
>> @@ -0,0 +1,221 @@
>> +// SPDX-License-Identifier: MIT
>> +/*
>> + * Copyright © 2025 Intel Corporation
>> + */
>> +
>> +#include <drm/drm_managed.h>
>> +#include <drm/drm_ras.h>
>> +#include <drm/xe_drm.h>
>> +
>> +#include "xe_device.h"
>> +#include "xe_drm_ras.h"
>> +
>> +#define ERR_INFO(index, _name) \
>> + [index] = { .name = _name, .counter = 0 }
>> +
>> +static struct xe_drm_ras_counter error_info[] = {
>> + ERR_INFO(DRM_XE_GENL_CORE_COMPUTE, "GT Error"),
>> +};
>> +
>> +static int hw_query_error_counter(struct xe_drm_ras_counter *info,
>> + u32 error_id, const char **name, u32 *val)
>> +{
>> + *name = info[error_id].name;
>> + *val = info[error_id].counter;
>> +
>> + return 0;
>> +}
>> +
>> +static int query_non_fatal_error_counters(struct drm_ras_node *ep,
>> + u32 error_id, const char **name,
>> + u32 *val)
>> +{
>> + struct xe_device *xe = ep->priv;
>> + struct xe_drm_ras *ras = &xe->ras;
>> + struct xe_drm_ras_counter *info = ras->info[HARDWARE_ERROR_NONFATAL];
>> +
>> + if (error_id >= ARRAY_SIZE(error_info))
>> + return -EINVAL;
>> +
>> + if (!error_info[error_id].name)
>> + return -ENOENT;
>> +
>> + return hw_query_error_counter(info, error_id, name, val);
>> +}
>> +
>> +static int query_fatal_error_counters(struct drm_ras_node *ep,
>> + u32 error_id, const char **name,
>> + u32 *val)
>> +{
>> + struct xe_device *xe = ep->priv;
>> + struct xe_drm_ras *ras = &xe->ras;
>> + struct xe_drm_ras_counter *info = ras->info[HARDWARE_ERROR_FATAL];
>> +
>> + if (error_id >= ARRAY_SIZE(error_info))
>> + return -EINVAL;
>> +
>> + if (!error_info[error_id].name)
>> + return -ENOENT;
>> +
>> + return hw_query_error_counter(info, error_id, name, val);
>> +}
>> +
>> +static int query_correctable_error_counters(struct drm_ras_node *ep,
>> + u32 error_id, const char **name,
>> + u32 *val)
>> +{
>> + struct xe_device *xe = ep->priv;
>> + struct xe_drm_ras *ras = &xe->ras;
>> + struct xe_drm_ras_counter *info = ras->info[HARDWARE_ERROR_CORRECTABLE];
>> +
>> + if (error_id >= ARRAY_SIZE(error_info))
>> + return -EINVAL;
>> +
>> + if (!error_info[error_id].name)
>> + return -ENOENT;
>> +
>> + return hw_query_error_counter(info, error_id, name, val);
>> +}
>> +
>> +static struct xe_drm_ras_counter *allocate_and_copy_counters(struct xe_device *xe,
>> + int count,
>> + struct xe_drm_ras_counter *src)
>> +{
>> + struct xe_drm_ras_counter *counter;
>> +
>> + counter = drmm_kzalloc(&xe->drm, count * sizeof(struct xe_drm_ras_counter), GFP_KERNEL);
>> + if (!counter)
>> + return ERR_PTR(-ENOMEM);
>> +
>> + memcpy(counter, src, count * sizeof(struct xe_drm_ras_counter));
>> +
>> + return counter;
>> +}
>> +
>> +static int assign_node_params(struct xe_device *xe, struct drm_ras_node *node,
>> + enum hardware_error hw_err)
>> +{
>> + struct xe_drm_ras *ras = &xe->ras;
>> + int count = 0, ret = 0;
>> +
>> + count = ARRAY_SIZE(error_info);
>> + node->error_counter_range.first = DRM_XE_GENL_CORE_COMPUTE;
>> + node->error_counter_range.last = count - 1;
>> +
>> + switch (hw_err) {
>> + case HARDWARE_ERROR_CORRECTABLE:
>> + ras->info[hw_err] = allocate_and_copy_counters(xe, count, error_info);
>> + if (IS_ERR(ras->info[hw_err]))
>> + return PTR_ERR(ras->info[hw_err]);
>> + node->query_error_counter = query_correctable_error_counters;
>> + break;
>> + case HARDWARE_ERROR_NONFATAL:
>> + ras->info[hw_err] = allocate_and_copy_counters(xe, count, error_info);
>> + if (IS_ERR(ras->info[hw_err]))
>> + return PTR_ERR(ras->info[hw_err]);
>> + node->query_error_counter = query_non_fatal_error_counters;
>> + break;
>> + case HARDWARE_ERROR_FATAL:
>> + ras->info[hw_err] = allocate_and_copy_counters(xe, count, error_info);
>> + if (IS_ERR(ras->info[hw_err]))
>> + return PTR_ERR(ras->info[hw_err]);
>> + node->query_error_counter = query_fatal_error_counters;
>> + break;
>> + default:
>> + break;
>> + }
>> +
>> + return ret;
>> +}
>> +
>> +static int register_nodes(struct xe_device *xe)
>> +{
>> + struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
>> + struct xe_drm_ras *ras = &xe->ras;
>> + const char *device_name;
>> + int i = 0, ret;
>> +
>> + device_name = kasprintf(GFP_KERNEL, "%04x:%02x:%02x.%d",
>> + pci_domain_nr(pdev->bus), pdev->bus->number,
>> + PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
>> +
>> + for (i = 0; i < HARDWARE_ERROR_MAX; i++) {
>> + struct drm_ras_node *node = &ras->node[i];
>> + const char *hw_err_str = hw_error_to_str(i);
>> + const char *node_name;
>> +
>> + node_name = kasprintf(GFP_KERNEL, "%s-errors", hw_err_str);
>> +
>> + node->device_name = device_name;
>> + node->node_name = node_name;
>> + node->type = DRM_RAS_NODE_TYPE_ERROR_COUNTER;
>> +
>> + ret = assign_node_params(xe, node, i);
>> + if (ret) {
>> + kfree(node->node_name);
>> + return ret;
>> + }
>> +
>> + node->priv = xe;
>> +
>> + ret = drm_ras_node_register(node);
>> + if (ret) {
>> + drm_err(&xe->drm, "Failed to register drm ras tile node\n");
>> + kfree(node->node_name);
>> + return ret;
>> + }
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static void xe_drm_ras_unregister_nodes(void *arg)
>> +{
>> + struct xe_device *xe = arg;
>> + struct xe_drm_ras *ras = &xe->ras;
>> + int i = 0;
>> +
>> + for (i = 0; i < HARDWARE_ERROR_MAX; i++) {
>> + struct drm_ras_node *node = &ras->node[i];
>> +
>> + drm_ras_node_unregister(node);
>> +
>> + kfree(node->node_name);
>> + if (i == 0)
>> + kfree(node->device_name);
>> + }
>> +}
>> +
>> +/**
>> + * xe_drm_ras_allocate_nodes - Allocate drm ras nodes
>> + * @xe: xe device instance
>> + *
>> + * Allocate xe drm ras nodes for all errors in a tile
>> + *
>> + * Return: 0 on success, error code on failure
>> + */
>> +int xe_drm_ras_allocate_nodes(struct xe_device *xe)
>> +{
>> + struct drm_ras_node *node;
>> + int err;
>> +
>> + node = drmm_kzalloc(&xe->drm, HARDWARE_ERROR_MAX * sizeof(struct drm_ras_node), GFP_KERNEL);
>> + if (!node)
>> + return -ENOMEM;
>> +
>> + xe->ras.node = node;
>> +
>> + err = register_nodes(xe);
>> + if (err) {
>> + drm_err(&xe->drm, "Failed to register drm ras node\n");
>> + return err;
>> + }
>> +
>> + err = devm_add_action_or_reset(xe->drm.dev, xe_drm_ras_unregister_nodes, xe);
>> + if (err) {
>> + drm_err(&xe->drm, "Failed to add action for xe drm_ras\n");
>> + return err;
>> + }
>> +
>> + return 0;
>> +}
>> diff --git a/drivers/gpu/drm/xe/xe_drm_ras.h b/drivers/gpu/drm/xe/xe_drm_ras.h
>> new file mode 100644
>> index 000000000000..6272b5da4e6d
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/xe_drm_ras.h
>> @@ -0,0 +1,12 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2025 Intel Corporation
>> + */
>> +#ifndef XE_DRM_RAS_H_
>> +#define XE_DRM_RAS_H_
>> +
>> +struct xe_device;
>> +
>> +int xe_drm_ras_allocate_nodes(struct xe_device *xe);
>> +
>> +#endif
>> diff --git a/drivers/gpu/drm/xe/xe_drm_ras_types.h b/drivers/gpu/drm/xe/xe_drm_ras_types.h
>> new file mode 100644
>> index 000000000000..452ff9a91510
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/xe_drm_ras_types.h
>> @@ -0,0 +1,54 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2025 Intel Corporation
>> + */
>> +
>> +#ifndef _XE_DRM_RAS_TYPES_H_
>> +#define _XE_DRM_RAS_TYPES_H_
>> +
>> +#include <linux/limits.h>
>> +
>> +struct drm_ras_node;
>> +
>> +/* Error categories reported by hardware */
>> +enum hardware_error {
>> + HARDWARE_ERROR_CORRECTABLE = 0,
>> + HARDWARE_ERROR_NONFATAL = 1,
>> + HARDWARE_ERROR_FATAL = 2,
>> + HARDWARE_ERROR_MAX,
>> +};
>> +
>> +static inline const char *hw_error_to_str(const enum hardware_error hw_err)
>> +{
>> + switch (hw_err) {
>> + case HARDWARE_ERROR_CORRECTABLE:
>> + return "correctable";
>> + case HARDWARE_ERROR_NONFATAL:
>> + return "nonfatal";
>> + case HARDWARE_ERROR_FATAL:
>> + return "fatal";
>> + default:
>> + return "UNKNOWN";
>> + }
>> +}
>> +
>> +struct xe_drm_ras_counter {
>> + const char *name;
>> + int counter;
>> +};
>> +
>> +/**
>> + * struct xe_drm_ras - xe drm ras structure
>> + *
>> + * This structure has details of error counters
>> + */
>> +struct xe_drm_ras {
>> + /** @node: DRM RAS node */
>> + struct drm_ras_node *node;
>> +
>> + /** @info: info array for all types of errors */
>> + struct xe_drm_ras_counter *info[HARDWARE_ERROR_MAX];
>> +
>> +};
>> +
>> +#endif
>> diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
>> index 8c65291f36fc..2adc2e6540f6 100644
>> --- a/drivers/gpu/drm/xe/xe_hw_error.c
>> +++ b/drivers/gpu/drm/xe/xe_hw_error.c
>> @@ -10,6 +10,7 @@
>> #include "regs/xe_irq_regs.h"
>>
>> #include "xe_device.h"
>> +#include "xe_drm_ras.h"
>> #include "xe_hw_error.h"
>> #include "xe_mmio.h"
>> #include "xe_survivability_mode.h"
>> @@ -17,14 +18,6 @@
>> #define HEC_UNCORR_FW_ERR_BITS 4
>> extern struct fault_attr inject_csc_hw_error;
>>
>> -/* Error categories reported by hardware */
>> -enum hardware_error {
>> - HARDWARE_ERROR_CORRECTABLE = 0,
>> - HARDWARE_ERROR_NONFATAL = 1,
>> - HARDWARE_ERROR_FATAL = 2,
>> - HARDWARE_ERROR_MAX,
>> -};
>> -
>> static const char * const hec_uncorrected_fw_errors[] = {
>> "Fatal",
>> "CSE Disabled",
>> @@ -32,20 +25,6 @@ static const char * const hec_uncorrected_fw_errors[] = {
>> "Data Corruption"
>> };
>>
>> -static const char *hw_error_to_str(const enum hardware_error hw_err)
>> -{
>> - switch (hw_err) {
>> - case HARDWARE_ERROR_CORRECTABLE:
>> - return "CORRECTABLE";
>> - case HARDWARE_ERROR_NONFATAL:
>> - return "NONFATAL";
>> - case HARDWARE_ERROR_FATAL:
>> - return "FATAL";
>> - default:
>> - return "UNKNOWN";
>> - }
>> -}
>> -
>> static bool fault_inject_csc_hw_error(void)
>> {
>> return IS_ENABLED(CONFIG_DEBUG_FS) && should_fail(&inject_csc_hw_error, 1);
>> @@ -146,6 +125,20 @@ void xe_hw_error_irq_handler(struct xe_tile *tile, const u32 master_ctl)
>> hw_error_source_handler(tile, hw_err);
>> }
>>
>> +static int hw_error_info_init(struct xe_device *xe)
>> +{
>> + int ret;
>> +
>> + if (xe->info.platform != XE_PVC)
>> + return 0;
>> +
>> + ret = xe_drm_ras_allocate_nodes(xe);
>> + if (ret)
>> + return ret;
>> +
>> + return 0;
>> +}
>> +
>> /*
>> * Process hardware errors during boot
>> */
>> @@ -178,5 +171,6 @@ void xe_hw_error_init(struct xe_device *xe)
>>
>> INIT_WORK(&tile->csc_hw_error_work, csc_hw_error_work);
>>
>> + hw_error_info_init(xe);
>> process_hw_errors(xe);
>> }
>> diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
>> index 47853659a705..053cbe1aafbb 100644
>> --- a/include/uapi/drm/xe_drm.h
>> +++ b/include/uapi/drm/xe_drm.h
>> @@ -2273,6 +2273,11 @@ struct drm_xe_vm_query_mem_range_attr {
>>
>> };
>>
>> +/**
>> + * RAS Counters
>> + */
>> +#define DRM_XE_GENL_CORE_COMPUTE (1)
>
> The feedback we got from Joonas is that we should also make the string name
> an uAPI defined here in the header.
> I'm afraid this series is missing that part for all the patches here.
> Perhaps we should also mention this in the docs in the firs patch as well
Sure will add this. We may need mapping for node_id and node_name as well
Thanks
Riana
>
> Other than that the series is great, thank you so much for picking that up!
>
>> +
>> #if defined(__cplusplus)
>> }
>> #endif
>> --
>> 2.47.1
>>
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 3/4] drm/xe/xe_hw_error: Add support for GT hardware errors
2025-11-26 14:36 [PATCH v2 0/4] Introduce DRM_RAS using generic netlink for RAS Riana Tauro
` (3 preceding siblings ...)
2025-11-26 14:36 ` [PATCH v2 2/4] drm/xe/xe_drm_ras: Add support for drm ras Riana Tauro
@ 2025-11-26 14:36 ` Riana Tauro
2025-11-27 5:28 ` kernel test robot
2025-11-26 14:36 ` [PATCH v2 4/4] drm/xe/xe_hw_error: Add support for PVC SOC errors Riana Tauro
5 siblings, 1 reply; 10+ messages in thread
From: Riana Tauro @ 2025-11-26 14:36 UTC (permalink / raw)
To: intel-xe, dri-devel
Cc: aravind.iddamsetty, anshuman.gupta, rodrigo.vivi, joonas.lahtinen,
lukas, simona.vetter, airlied, lucas.demarchi, Riana Tauro,
Himal Prasad Ghimiray
PVC supports GT error reporting via vector registers alongwith
error status register. Add support to report these errors and
update respective counters. Incase of Subslice error reported
by vector register, process the error status register
for applicable bits.
Incorporate the counter inside the driver itself and start
using the drm_ras generic netlink to report them.
Co-developed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Signed-off-by: Riana Tauro <riana.tauro@intel.com>
---
drivers/gpu/drm/xe/regs/xe_hw_error_regs.h | 44 ++++++
drivers/gpu/drm/xe/xe_hw_error.c | 175 ++++++++++++++++++++-
2 files changed, 215 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/xe/regs/xe_hw_error_regs.h b/drivers/gpu/drm/xe/regs/xe_hw_error_regs.h
index c146b9ef44eb..a9e829dac9a9 100644
--- a/drivers/gpu/drm/xe/regs/xe_hw_error_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_hw_error_regs.h
@@ -11,10 +11,54 @@
#define HEC_UNCORR_FW_ERR_DW0(base) XE_REG((base) + 0x124)
+#define ERR_STAT_GT_COR 0x100160
+#define ERR_STAT_GT_NONFATAL 0x100164
+#define ERR_STAT_GT_FATAL 0x100168
+#define ERR_STAT_GT_REG(x) XE_REG(_PICK_EVEN((x), \
+ ERR_STAT_GT_COR, \
+ ERR_STAT_GT_NONFATAL))
+
+#define GT_HW_ERROR_MAX_ERR_BITS 16
+#define EU_GRF_ERR (15)
+#define EU_IC_ERR (14)
+#define SLM_ERR (13)
+#define GUC_COR_ERR (1)
+
+#define GUC_FAT_ERR (6)
+#define FPU_FAT_ERR (3)
+
+#define PVC_COR_ERR_MASK (BIT(GUC_COR_ERR) | BIT(SLM_ERR) | \
+ BIT(EU_IC_ERR) | BIT(EU_GRF_ERR))
+
+#define PVC_FAT_ERR_MASK (BIT(FPU_FAT_ERR) | BIT(GUC_FAT_ERR) | \
+ BIT(EU_GRF_ERR) | BIT(SLM_ERR))
+
#define DEV_ERR_STAT_NONFATAL 0x100178
#define DEV_ERR_STAT_CORRECTABLE 0x10017c
#define DEV_ERR_STAT_REG(x) XE_REG(_PICK_EVEN((x), \
DEV_ERR_STAT_CORRECTABLE, \
DEV_ERR_STAT_NONFATAL))
+
#define XE_CSC_ERROR BIT(17)
+#define XE_GT_ERROR BIT(0)
+
+#define ERR_STAT_GT_FATAL_VECTOR_0 0x100260
+#define ERR_STAT_GT_FATAL_VECTOR_1 0x100264
+
+#define ERR_STAT_GT_FATAL_VECTOR_REG(x) XE_REG(_PICK_EVEN((x), \
+ ERR_STAT_GT_FATAL_VECTOR_0, \
+ ERR_STAT_GT_FATAL_VECTOR_1))
+
+#define ERR_STAT_GT_COR_VECTOR_LEN (4)
+#define ERR_STAT_GT_COR_VECTOR_0 0x1002a0
+#define ERR_STAT_GT_COR_VECTOR_1 0x1002a4
+
+#define ERR_STAT_GT_COR_VECTOR_REG(x) XE_REG(_PICK_EVEN((x), \
+ ERR_STAT_GT_COR_VECTOR_0,\
+ ERR_STAT_GT_COR_VECTOR_1))
+
+#define ERR_STAT_GT_VECTOR_REG(hw_err, x) (hw_err == HARDWARE_ERROR_CORRECTABLE ? \
+ ERR_STAT_GT_COR_VECTOR_REG(x) : \
+ ERR_STAT_GT_FATAL_VECTOR_REG(x))
+
#endif
diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
index 2adc2e6540f6..1bfda1b3bae4 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.c
+++ b/drivers/gpu/drm/xe/xe_hw_error.c
@@ -15,7 +15,9 @@
#include "xe_mmio.h"
#include "xe_survivability_mode.h"
+#define XE_RAS_REG_SIZE 32
#define HEC_UNCORR_FW_ERR_BITS 4
+
extern struct fault_attr inject_csc_hw_error;
static const char * const hec_uncorrected_fw_errors[] = {
@@ -25,6 +27,25 @@ static const char * const hec_uncorrected_fw_errors[] = {
"Data Corruption"
};
+#define ERR_INDEX(_bit, index) \
+ [__ffs(_bit)] = index
+
+static const unsigned long xe_hw_error_map[] = {
+ ERR_INDEX(XE_GT_ERROR, DRM_XE_GENL_CORE_COMPUTE),
+};
+
+enum gt_vector_regs {
+ ERR_STAT_GT_VECTOR0 = 0,
+ ERR_STAT_GT_VECTOR1,
+ ERR_STAT_GT_VECTOR2,
+ ERR_STAT_GT_VECTOR3,
+ ERR_STAT_GT_VECTOR4,
+ ERR_STAT_GT_VECTOR5,
+ ERR_STAT_GT_VECTOR6,
+ ERR_STAT_GT_VECTOR7,
+ ERR_STAT_GT_VECTOR_MAX,
+};
+
static bool fault_inject_csc_hw_error(void)
{
return IS_ENABLED(CONFIG_DEBUG_FS) && should_fail(&inject_csc_hw_error, 1);
@@ -76,14 +97,133 @@ static void csc_hw_error_handler(struct xe_tile *tile, const enum hardware_error
xe_mmio_write32(mmio, HEC_UNCORR_ERR_STATUS(base), err_src);
}
+static void log_hw_error(struct xe_tile *tile, const char *name, const enum hardware_error hw_err)
+{
+ const char *hw_err_str = hw_error_to_str(hw_err);
+ struct xe_device *xe = tile_to_xe(tile);
+
+ if (hw_err == HARDWARE_ERROR_FATAL)
+ drm_err_ratelimited(&xe->drm, "%s %s error detected\n", name, hw_err_str);
+ else
+ drm_warn(&xe->drm, "%s %s error detected\n", name, hw_err_str);
+}
+
+static void
+log_gt_err(struct xe_tile *tile, const char *name, int i, u32 err, const enum hardware_error hw_err)
+{
+ const char *hw_err_str = hw_error_to_str(hw_err);
+ struct xe_device *xe = tile_to_xe(tile);
+
+ if (hw_err == HARDWARE_ERROR_FATAL)
+ drm_err_ratelimited(&xe->drm, "%s %s error detected, ERROR_STAT_GT_VECTOR%d:0x%08x\n",
+ name, hw_err_str, i, err);
+ else
+ drm_warn(&xe->drm, "%s %s error detected, ERROR_STAT_GT_VECTOR%d:0x%08x\n",
+ name, hw_err_str, i, err);
+}
+
+static void gt_handle_errors(struct xe_tile *tile, const enum hardware_error hw_err, u32 err_bit)
+{
+ struct xe_device *xe = tile_to_xe(tile);
+ struct xe_drm_ras *ras = &xe->ras;
+ struct xe_drm_ras_counter *info = ras->info[hw_err];
+ struct xe_mmio *mmio = &tile->mmio;
+ u32 index;
+ int i;
+
+ if (xe->info.platform != XE_PVC)
+ return;
+
+ index = xe_hw_error_map[err_bit];
+
+ for (i = 0; i < ERR_STAT_GT_VECTOR_MAX; i++) {
+ u32 vector;
+ unsigned long err_stat;
+
+ if (hw_err == HARDWARE_ERROR_CORRECTABLE && i >= ERR_STAT_GT_COR_VECTOR_LEN)
+ break;
+
+ vector = xe_mmio_read32(mmio, ERR_STAT_GT_VECTOR_REG(hw_err, i));
+ if (!vector)
+ continue;
+
+ switch (i) {
+ case ERR_STAT_GT_VECTOR0:
+ case ERR_STAT_GT_VECTOR1:
+ u32 errbit;
+
+ info[index].counter += hweight32(vector);
+ log_gt_err(tile, "Subslice", i, vector, hw_err);
+
+ if (err_stat)
+ break;
+
+ err_stat = xe_mmio_read32(mmio, ERR_STAT_GT_REG(hw_err));
+ for_each_set_bit(errbit, &err_stat, GT_HW_ERROR_MAX_ERR_BITS) {
+ if (hw_err == HARDWARE_ERROR_CORRECTABLE &&
+ (BIT(errbit) & PVC_COR_ERR_MASK))
+ info[index].counter++;
+ if (hw_err == HARDWARE_ERROR_FATAL &&
+ (BIT(errbit) & PVC_FAT_ERR_MASK))
+ info[index].counter++;
+ }
+ if (err_stat)
+ xe_mmio_write32(mmio, ERR_STAT_GT_REG(hw_err), err_stat);
+ break;
+ case ERR_STAT_GT_VECTOR2:
+ case ERR_STAT_GT_VECTOR3:
+ info[index].counter += hweight32(vector);
+ log_gt_err(tile, "L3 BANK", i, vector, hw_err);
+ break;
+ case ERR_STAT_GT_VECTOR6:
+ info[index].counter += hweight32(vector);
+ log_gt_err(tile, "TLB", i, vector, hw_err);
+ break;
+ case ERR_STAT_GT_VECTOR7:
+ info[index].counter += hweight32(vector);
+ log_gt_err(tile, "L3 Fabric", i, vector, hw_err);
+ break;
+ default:
+ log_gt_err(tile, "Undefined", i, vector, hw_err);
+ }
+
+ xe_mmio_write32(mmio, ERR_STAT_GT_VECTOR_REG(hw_err, i), vector);
+ }
+}
+
+static void gt_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err, u32 err_bit)
+{
+ struct xe_device *xe = tile_to_xe(tile);
+ struct xe_drm_ras *ras = &xe->ras;
+ struct xe_drm_ras_counter *info = ras->info[hw_err];
+ u32 index = xe_hw_error_map[err_bit];
+
+ switch (hw_err) {
+ case HARDWARE_ERROR_CORRECTABLE:
+ gt_handle_errors(tile, hw_err, err_bit);
+ break;
+ case HARDWARE_ERROR_NONFATAL:
+ info[index].counter++;
+ log_hw_error(tile, "GT", hw_err);
+ break;
+ case HARDWARE_ERROR_FATAL:
+ gt_handle_errors(tile, hw_err, err_bit);
+ break;
+ default:
+ log_hw_error(tile, "Undefined", hw_err);
+ }
+}
+
static void hw_error_source_handler(struct xe_tile *tile, const enum hardware_error hw_err)
{
const char *hw_err_str = hw_error_to_str(hw_err);
struct xe_device *xe = tile_to_xe(tile);
- unsigned long flags;
- u32 err_src;
+ struct xe_drm_ras *ras = &xe->ras;
+ struct xe_drm_ras_counter *info = ras->info[hw_err];
+ unsigned long flags, err_src;
+ u32 err_bit;
- if (xe->info.platform != XE_BATTLEMAGE)
+ if (!IS_DGFX(xe))
return;
spin_lock_irqsave(&xe->irq.lock, flags);
@@ -94,9 +234,36 @@ static void hw_error_source_handler(struct xe_tile *tile, const enum hardware_er
goto unlock;
}
- if (err_src & XE_CSC_ERROR)
+ if (err_src & XE_CSC_ERROR) {
csc_hw_error_handler(tile, hw_err);
+ goto clear_reg;
+ }
+
+ if (!info) {
+ drm_err_ratelimited(&xe->drm, HW_ERR "Errors undefined\n");
+ goto clear_reg;
+ }
+
+ for_each_set_bit(err_bit, &err_src, XE_RAS_REG_SIZE) {
+ u32 index = xe_hw_error_map[err_bit];
+ const char *name = info[index].name;
+
+ if (hw_err == HARDWARE_ERROR_FATAL) {
+ drm_err_ratelimited(&xe->drm, HW_ERR
+ "TILE%d reported %s %s error, bit[%d] is set\n",
+ tile->id, name, hw_err_str, err_bit);
+ } else {
+ drm_warn(&xe->drm, HW_ERR
+ "TILE%d reported %s %s error, bit[%d] is set\n",
+ tile->id, name, hw_err_str, err_bit);
+ }
+
+
+ if (BIT(err_bit) & XE_GT_ERROR)
+ gt_hw_error_handler(tile, hw_err, err_bit);
+ }
+clear_reg:
xe_mmio_write32(&tile->mmio, DEV_ERR_STAT_REG(hw_err), err_src);
unlock:
--
2.47.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v2 3/4] drm/xe/xe_hw_error: Add support for GT hardware errors
2025-11-26 14:36 ` [PATCH v2 3/4] drm/xe/xe_hw_error: Add support for GT hardware errors Riana Tauro
@ 2025-11-27 5:28 ` kernel test robot
0 siblings, 0 replies; 10+ messages in thread
From: kernel test robot @ 2025-11-27 5:28 UTC (permalink / raw)
To: Riana Tauro, intel-xe, dri-devel
Cc: oe-kbuild-all, aravind.iddamsetty, anshuman.gupta, rodrigo.vivi,
joonas.lahtinen, lukas, simona.vetter, airlied, lucas.demarchi,
Riana Tauro, Himal Prasad Ghimiray
Hi Riana,
kernel test robot noticed the following build errors:
[auto build test ERROR on drm-xe/drm-xe-next]
[also build test ERROR on drm/drm-next drm-intel/for-linux-next drm-intel/for-linux-next-fixes drm-misc/drm-misc-next drm-tip/drm-tip linus/master drm-exynos/exynos-drm-next v6.18-rc7 next-20251127]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Riana-Tauro/drm-ras-Introduce-the-DRM-RAS-infrastructure-over-generic-netlink/20251126-220942
base: https://gitlab.freedesktop.org/drm/xe/kernel.git drm-xe-next
patch link: https://lore.kernel.org/r/20251126143652.2843242-9-riana.tauro%40intel.com
patch subject: [PATCH v2 3/4] drm/xe/xe_hw_error: Add support for GT hardware errors
config: riscv-randconfig-r061-20251127 (https://download.01.org/0day-ci/archive/20251127/202511271357.7pA8zqx0-lkp@intel.com/config)
compiler: riscv64-linux-gcc (GCC) 13.4.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251127/202511271357.7pA8zqx0-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202511271357.7pA8zqx0-lkp@intel.com/
All errors (new ones prefixed by >>):
In file included from arch/riscv/include/asm/bitops.h:19,
from include/linux/bitops.h:67,
from include/linux/thread_info.h:27,
from include/asm-generic/preempt.h:5,
from ./arch/riscv/include/generated/asm/preempt.h:1,
from include/linux/preempt.h:79,
from include/linux/spinlock.h:56,
from include/linux/kref.h:16,
from include/linux/configfs.h:25,
from include/linux/fault-inject.h:14,
from drivers/gpu/drm/xe/xe_hw_error.c:6:
>> include/asm-generic/bitops/__ffs.h:45:21: error: nonconstant array index in initializer
45 | #define __ffs(word) generic___ffs(word)
| ^~~~~~~~~~~~~
drivers/gpu/drm/xe/xe_hw_error.c:31:10: note: in expansion of macro '__ffs'
31 | [__ffs(_bit)] = index
| ^~~~~
drivers/gpu/drm/xe/xe_hw_error.c:34:9: note: in expansion of macro 'ERR_INDEX'
34 | ERR_INDEX(XE_GT_ERROR, DRM_XE_GENL_CORE_COMPUTE),
| ^~~~~~~~~
include/asm-generic/bitops/__ffs.h:45:21: note: (near initialization for 'xe_hw_error_map')
45 | #define __ffs(word) generic___ffs(word)
| ^~~~~~~~~~~~~
drivers/gpu/drm/xe/xe_hw_error.c:31:10: note: in expansion of macro '__ffs'
31 | [__ffs(_bit)] = index
| ^~~~~
drivers/gpu/drm/xe/xe_hw_error.c:34:9: note: in expansion of macro 'ERR_INDEX'
34 | ERR_INDEX(XE_GT_ERROR, DRM_XE_GENL_CORE_COMPUTE),
| ^~~~~~~~~
Kconfig warnings: (for reference only)
WARNING: unmet direct dependencies detected for ARCH_HAS_ELF_CORE_EFLAGS
Depends on [n]: BINFMT_ELF [=y] && ELF_CORE [=n]
Selected by [y]:
- RISCV [=y]
vim +45 include/asm-generic/bitops/__ffs.h
c1226a005ec400 Akinobu Mita 2006-03-26 43
cb4ede926134a6 Xiao Wang 2023-11-12 44 #ifndef __HAVE_ARCH___FFS
cb4ede926134a6 Xiao Wang 2023-11-12 @45 #define __ffs(word) generic___ffs(word)
cb4ede926134a6 Xiao Wang 2023-11-12 46 #endif
cb4ede926134a6 Xiao Wang 2023-11-12 47
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 4/4] drm/xe/xe_hw_error: Add support for PVC SOC errors
2025-11-26 14:36 [PATCH v2 0/4] Introduce DRM_RAS using generic netlink for RAS Riana Tauro
` (4 preceding siblings ...)
2025-11-26 14:36 ` [PATCH v2 3/4] drm/xe/xe_hw_error: Add support for GT hardware errors Riana Tauro
@ 2025-11-26 14:36 ` Riana Tauro
5 siblings, 0 replies; 10+ messages in thread
From: Riana Tauro @ 2025-11-26 14:36 UTC (permalink / raw)
To: intel-xe, dri-devel
Cc: aravind.iddamsetty, anshuman.gupta, rodrigo.vivi, joonas.lahtinen,
lukas, simona.vetter, airlied, lucas.demarchi, Riana Tauro,
Himal Prasad Ghimiray
Report the SOC nonfatal/fatal hardware error and update the counters.
Co-developed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Signed-off-by: Riana Tauro <riana.tauro@intel.com>
---
drivers/gpu/drm/xe/regs/xe_hw_error_regs.h | 24 +++
drivers/gpu/drm/xe/xe_drm_ras.c | 1 +
drivers/gpu/drm/xe/xe_hw_error.c | 202 ++++++++++++++++++++-
include/uapi/drm/xe_drm.h | 1 +
4 files changed, 227 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/regs/xe_hw_error_regs.h b/drivers/gpu/drm/xe/regs/xe_hw_error_regs.h
index a9e829dac9a9..771e101f7643 100644
--- a/drivers/gpu/drm/xe/regs/xe_hw_error_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_hw_error_regs.h
@@ -40,6 +40,7 @@
DEV_ERR_STAT_NONFATAL))
#define XE_CSC_ERROR BIT(17)
+#define XE_SOC_ERROR BIT(16)
#define XE_GT_ERROR BIT(0)
#define ERR_STAT_GT_FATAL_VECTOR_0 0x100260
@@ -61,4 +62,27 @@
ERR_STAT_GT_COR_VECTOR_REG(x) : \
ERR_STAT_GT_FATAL_VECTOR_REG(x))
+#define SOC_PVC_BASE 0x282000
+#define SOC_PVC_SLAVE_BASE 0x283000
+
+#define SOC_GCOERRSTS 0x200
+#define SOC_GNFERRSTS 0x210
+#define SOC_GLOBAL_ERR_STAT_REG(base, x) XE_REG(_PICK_EVEN((x), \
+ (base) + SOC_GCOERRSTS, \
+ (base) + SOC_GNFERRSTS))
+#define SOC_SLAVE_IEH BIT(1)
+#define SOC_IEH0_LOCAL_ERR_STATUS BIT(0)
+#define SOC_IEH1_LOCAL_ERR_STATUS BIT(0)
+
+#define SOC_GSYSEVTCTL 0x264
+#define SOC_GSYSEVTCTL_REG(base, slave_base, x) XE_REG(_PICK_EVEN((x), \
+ (base) + SOC_GSYSEVTCTL, \
+ slave_base + SOC_GSYSEVTCTL))
+
+#define SOC_LERRUNCSTS 0x280
+#define SOC_LERRCORSTS 0x294
+#define SOC_LOCAL_ERR_STAT_REG(base, x) XE_REG(x == HARDWARE_ERROR_CORRECTABLE ? \
+ (base) + SOC_LERRCORSTS : \
+ (base) + SOC_LERRUNCSTS)
+
#endif
diff --git a/drivers/gpu/drm/xe/xe_drm_ras.c b/drivers/gpu/drm/xe/xe_drm_ras.c
index 5320e845e9d5..dd83d798dd26 100644
--- a/drivers/gpu/drm/xe/xe_drm_ras.c
+++ b/drivers/gpu/drm/xe/xe_drm_ras.c
@@ -15,6 +15,7 @@
static struct xe_drm_ras_counter error_info[] = {
ERR_INFO(DRM_XE_GENL_CORE_COMPUTE, "GT Error"),
+ ERR_INFO(DRM_XE_GENL_SOC_INTERNAL, "SOC Error"),
};
static int hw_query_error_counter(struct xe_drm_ras_counter *info,
diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
index 1bfda1b3bae4..95181fc07cce 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.c
+++ b/drivers/gpu/drm/xe/xe_hw_error.c
@@ -16,7 +16,8 @@
#include "xe_survivability_mode.h"
#define XE_RAS_REG_SIZE 32
-#define HEC_UNCORR_FW_ERR_BITS 4
+#define XE_SOC_NUM_IEH 2
+#define HEC_UNCORR_FW_ERR_BITS 4
extern struct fault_attr inject_csc_hw_error;
@@ -32,6 +33,7 @@ static const char * const hec_uncorrected_fw_errors[] = {
static const unsigned long xe_hw_error_map[] = {
ERR_INDEX(XE_GT_ERROR, DRM_XE_GENL_CORE_COMPUTE),
+ ERR_INDEX(XE_SOC_ERROR, DRM_XE_GENL_SOC_INTERNAL),
};
enum gt_vector_regs {
@@ -46,6 +48,92 @@ enum gt_vector_regs {
ERR_STAT_GT_VECTOR_MAX,
};
+static const char * const pvc_slave_local_fatal_err_reg[] = {
+ [0] = "Local IEH internal: Malformed PCIe AER",
+ [1] = "Local IEH internal: Malformed PCIe ERR",
+ [2] = "Local IEH internal: UR conditions in IEH",
+ [3] = "Local IEH internal: From SERR Sources",
+ [4 ... 19] = "Undefined",
+ [20] = "Malformed MCA error packet (HBM/Punit)",
+ [21 ... 31] = "Undefined",
+};
+
+static const char * const pvc_slave_global_err_reg[] = {
+ [0] = "Undefined",
+ [1] = "HBM SS2: Channel0",
+ [2] = "HBM SS2: Channel1",
+ [3] = "HBM SS2: Channel2",
+ [4] = "HBM SS2: Channel3",
+ [5] = "HBM SS2: Channel4",
+ [6] = "HBM SS2: Channel5",
+ [7] = "HBM SS2: Channel6",
+ [8] = "HBM SS2: Channel7",
+ [9] = "HBM SS3: Channel0",
+ [10] = "HBM SS3: Channel1",
+ [11] = "HBM SS3: Channel2",
+ [12] = "HBM SS3: Channel3",
+ [13] = "HBM SS3: Channel4",
+ [14] = "HBM SS3: Channel5",
+ [15] = "HBM SS3: Channel6",
+ [16] = "HBM SS3: Channel7",
+ [17] = "Undefined",
+ [18] = "ANR MDFI",
+ [19 ... 31] = "Undefined",
+};
+
+static const char * const pvc_master_global_err_reg[] = {
+ [0 ... 1] = "Undefined",
+ [2] = "HBM SS0: Channel0",
+ [3] = "HBM SS0: Channel1",
+ [4] = "HBM SS0: Channel2",
+ [5] = "HBM SS0: Channel3",
+ [6] = "HBM SS0: Channel4",
+ [7] = "HBM SS0: Channel5",
+ [8] = "HBM SS0: Channel6",
+ [9] = "HBM SS0: Channel7",
+ [10] = "HBM SS1: Channel0",
+ [11] = "HBM SS1: Channel1",
+ [12] = "HBM SS1: Channel2",
+ [13] = "HBM SS1: Channel3",
+ [14] = "HBM SS1: Channel4",
+ [15] = "HBM SS1: Channel5",
+ [16] = "HBM SS1: Channel6",
+ [17] = "HBM SS1: Channel7",
+ [18 ... 31] = "Undefined",
+};
+
+static const char * const pvc_master_local_fatal_err_reg[] = {
+ [0] = "Local IEH internal: Malformed IOSF PCIe AER",
+ [1] = "Local IEH internal: Malformed IOSF PCIe ERR",
+ [2] = "Local IEH internal: IEH UR RESPONSE",
+ [3] = "Local IEH internal: From SERR SPI controller",
+ [4] = "Base Die MDFI T2T",
+ [5] = "Undefined",
+ [6] = "Base Die MDFI T2C",
+ [7] = "Undefined",
+ [8] = "Invalid CSC PSF Command Parity",
+ [9] = "Invalid CSC PSF Unexpected Completion",
+ [10] = "Invalid CSC PSF Unsupported Request",
+ [11] = "Invalid PCIe PSF Command Parity",
+ [12] = "PCIe PSF Unexpected Completion",
+ [13] = "PCIe PSF Unsupported Request",
+ [14 ... 19] = "Undefined",
+ [20] = "Malformed MCA error packet (HBM/Punit)",
+ [21 ... 31] = "Undefined",
+};
+
+static const char * const pvc_master_local_nonfatal_err_reg[] = {
+ [0 ... 3] = "Undefined",
+ [4] = "Base Die MDFI T2T",
+ [5] = "Undefined",
+ [6] = "Base Die MDFI T2C",
+ [7] = "Undefined",
+ [8] = "Invalid CSC PSF Command Parity",
+ [9] = "Invalid CSC PSF Unexpected Completion",
+ [10] = "Invalid PCIe PSF Command Parity",
+ [11 ... 31] = "Undefined",
+};
+
static bool fault_inject_csc_hw_error(void)
{
return IS_ENABLED(CONFIG_DEBUG_FS) && should_fail(&inject_csc_hw_error, 1);
@@ -191,6 +279,115 @@ static void gt_handle_errors(struct xe_tile *tile, const enum hardware_error hw_
}
}
+static void log_soc_error(struct xe_tile *tile, const char * const *reg_info,
+ const enum hardware_error hw_err, u32 err_bit, u32 index)
+{
+ const char *hw_err_str = hw_error_to_str(hw_err);
+ struct xe_device *xe = tile_to_xe(tile);
+ struct xe_drm_ras *ras = &xe->ras;
+ struct xe_drm_ras_counter *info = ras->info[hw_err];
+ const char *name;
+
+ name = reg_info[err_bit];
+
+ if (strcmp(name, "Undefined") != 0) {
+ drm_err_ratelimited(&xe->drm, "%s SOC %s error detected", name, hw_err_str);
+ info[index].counter += 1;
+ }
+}
+
+static void soc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err,
+ u32 err_bit)
+{
+ struct xe_device *xe = tile_to_xe(tile);
+ struct xe_mmio *mmio = &tile->mmio;
+ unsigned long master_global_errstat, slave_global_errstat;
+ unsigned long master_local_errstat, slave_local_errstat;
+ u32 base, slave_base, index, regbit;
+ int i;
+
+ if (xe->info.platform != XE_PVC)
+ return;
+
+ base = SOC_PVC_BASE;
+ slave_base = SOC_PVC_SLAVE_BASE;
+
+ index = xe_hw_error_map[err_bit];
+
+ /*
+ * Mask error type in GSYSEVTCTL so that no new errors of the type will be reported
+ */
+ for (i = 0; i < XE_SOC_NUM_IEH; i++)
+ xe_mmio_write32(mmio, SOC_GSYSEVTCTL_REG(base, slave_base, i), ~REG_BIT(hw_err));
+
+ if (hw_err == HARDWARE_ERROR_CORRECTABLE) {
+ xe_mmio_write32(mmio, SOC_GLOBAL_ERR_STAT_REG(base, hw_err), REG_GENMASK(31, 0));
+ xe_mmio_write32(mmio, SOC_LOCAL_ERR_STAT_REG(base, hw_err), REG_GENMASK(31, 0));
+ xe_mmio_write32(mmio, SOC_GLOBAL_ERR_STAT_REG(slave_base, hw_err),
+ REG_GENMASK(31, 0));
+ xe_mmio_write32(mmio, SOC_LOCAL_ERR_STAT_REG(slave_base, hw_err),
+ REG_GENMASK(31, 0));
+ goto unmask_gsysevtctl;
+ }
+
+ /*
+ * Read the master global IEH error register if
+ * BIT 1 is set then process the slave IEH first. If BIT 0 in
+ * global error register is set then process the corresponding
+ * Local error registers
+ */
+ master_global_errstat = xe_mmio_read32(mmio, SOC_GLOBAL_ERR_STAT_REG(base, hw_err));
+ if (master_global_errstat & SOC_SLAVE_IEH) {
+ slave_global_errstat = xe_mmio_read32(mmio,
+ SOC_GLOBAL_ERR_STAT_REG(slave_base, hw_err));
+ if (slave_global_errstat & SOC_IEH1_LOCAL_ERR_STATUS) {
+ slave_local_errstat = xe_mmio_read32(mmio,
+ SOC_LOCAL_ERR_STAT_REG(slave_base,
+ hw_err));
+
+ for_each_set_bit(regbit, &slave_local_errstat, XE_RAS_REG_SIZE) {
+ if (hw_err == HARDWARE_ERROR_FATAL)
+ log_soc_error(tile, pvc_slave_local_fatal_err_reg, hw_err,
+ regbit, index);
+ }
+
+ xe_mmio_write32(mmio, SOC_LOCAL_ERR_STAT_REG(slave_base, hw_err),
+ slave_local_errstat);
+ }
+
+ for_each_set_bit(regbit, &slave_global_errstat, XE_RAS_REG_SIZE)
+ log_soc_error(tile, pvc_slave_global_err_reg, hw_err, regbit, index);
+
+ xe_mmio_write32(mmio, SOC_GLOBAL_ERR_STAT_REG(slave_base, hw_err),
+ slave_global_errstat);
+ }
+
+ if (master_global_errstat & SOC_IEH0_LOCAL_ERR_STATUS) {
+ master_local_errstat = xe_mmio_read32(mmio, SOC_LOCAL_ERR_STAT_REG(base, hw_err));
+
+ for_each_set_bit(regbit, &master_local_errstat, XE_RAS_REG_SIZE) {
+ if (hw_err == HARDWARE_ERROR_FATAL)
+ log_soc_error(tile, pvc_master_local_fatal_err_reg, hw_err,
+ regbit, index);
+ if (hw_err == HARDWARE_ERROR_NONFATAL)
+ log_soc_error(tile, pvc_master_local_nonfatal_err_reg, hw_err,
+ regbit, index);
+ }
+
+ xe_mmio_write32(mmio, SOC_LOCAL_ERR_STAT_REG(base, hw_err), master_local_errstat);
+ }
+
+ for_each_set_bit(regbit, &master_global_errstat, XE_RAS_REG_SIZE)
+ log_soc_error(tile, pvc_master_global_err_reg, hw_err, regbit, index);
+
+ xe_mmio_write32(mmio, SOC_GLOBAL_ERR_STAT_REG(base, hw_err), master_global_errstat);
+
+unmask_gsysevtctl:
+ for (i = 0; i < XE_SOC_NUM_IEH; i++)
+ xe_mmio_write32(mmio, SOC_GSYSEVTCTL_REG(base, slave_base, i),
+ (HARDWARE_ERROR_MAX << 1) + 1);
+}
+
static void gt_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err, u32 err_bit)
{
struct xe_device *xe = tile_to_xe(tile);
@@ -261,6 +458,9 @@ static void hw_error_source_handler(struct xe_tile *tile, const enum hardware_er
if (BIT(err_bit) & XE_GT_ERROR)
gt_hw_error_handler(tile, hw_err, err_bit);
+
+ if (BIT(err_bit) == XE_SOC_ERROR)
+ soc_hw_error_handler(tile, hw_err, err_bit);
}
clear_reg:
diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
index 053cbe1aafbb..f0bf50ca659e 100644
--- a/include/uapi/drm/xe_drm.h
+++ b/include/uapi/drm/xe_drm.h
@@ -2277,6 +2277,7 @@ struct drm_xe_vm_query_mem_range_attr {
* RAS Counters
*/
#define DRM_XE_GENL_CORE_COMPUTE (1)
+#define DRM_XE_GENL_SOC_INTERNAL (2)
#if defined(__cplusplus)
}
--
2.47.1
^ permalink raw reply related [flat|nested] 10+ messages in thread