* [PATCH v5 00/10] Page Reclamation Support for Xe3p Platforms
@ 2025-12-10 1:45 Brian Nguyen
2025-12-10 1:45 ` [PATCH v5 01/10] drm/xe: Do not forward invalid TLB invalidation seqnos to upper layers Brian Nguyen
` (13 more replies)
0 siblings, 14 replies; 22+ messages in thread
From: Brian Nguyen @ 2025-12-10 1:45 UTC (permalink / raw)
To: intel-xe; +Cc: tejas.upadhyay, matthew.brost, shuicheng.lin, stuart.summers
This series introduces a hardware-assisted page reclamation support on Xe3p
platforms, integrating with the KMD's existing TLB invalidation workflow and
adding the ability to perform selective Private Physical Cache (PPC) flushing
rather than always forcing the default full PPC flush.
Currently as of Xe2, Xe TLB invalidations trigger a full Private Physical Cache
flush to guarantee non-coherent memory correctness. New HW (Xe3p and beyond)
supports a page reclamation feature, which we selectively enable on platforms
with a flag in device info.
The driver can provide a “Page Reclaim List” (PRL), tracking the physical pages
used that correspond to an unmap/unbind operation and let hardware perform selective
cache line eviction. If reclamation succeeds, we skip the full PPC flush entirely
otherwise we fall back to our current process of full PPC flush with the TLB
invalidation.
Thanks,
Brian
v2:
- General refactor to remove additional variables from
tlb fences (flush_cache and PRL ptr). (Matthew B)
- Removed lock from xe_tlb_inval_reset_timeout and moved
into xe_tlb_inval_done_handler. (Matthew B)
- Removed page reclaim variables out of tlb fences (Matthew B)
- Add FW check for page reclaim support. (Shuicheng, Matthew B)
- Moved PRL max entries overflow handling out from
generate_reclaim_entry to caller. (Shuicheng)
- Fix one off error with NULL terminated PRL.
- Add xe_page_reclaim_list_init for clarity. (Matthew B)
- Invalidate PRL on early abort page walks.
- Allocate PRL bo size to num_entries. (Matthew B)
- Move PRL bo allocation to tlb_inval run_job. (Matthew B)
- Modify debugfs to expose file only if page reclaim supported by
default instead of previous behavior to return an ENODEV
and thus no need to move xe_match_desc from configfs (Michal)
- Compacted warning checking, update commit message,
spelling, moved variables, etc. (Shuicheng, Matthew B, Michal)
- Remove unused function. (Shuicheng)
- Fix various missing kernel doc input.
v3:
- Removed MEDIA_IS_ON due to racy condition. (Matthew A)
- Move l3 policy access to xe_pat. (Matthew A)
- Add vm_dbg prints for PRL generation and invalidation. (Matthew B)
- Add comments for PRL tile handling and flush behavior with medai. (Matthew B)
- Modify reclaim_entry to QW and adjust bitfields accordingly. (Matthew B)
- Add missing shift of PTE for page address in reclaim entry. (Matthew B)
- Fix NULL pointer dereference check.
- s/ifence/fence for kernel doc.
- Squashed dependent patch.
- Update erroneous comments
v4:
- s/GEN_MASK/GEN_MASK_ULL, s/BIT/BIT_ULL for xe_guc_reclaim_entry (CI)
- Revised comments to current changes (Tejas)
- Moved PAT macros back to original place.
v5:
- Add a new xe_page_reclaim_list_is_new() function that will
indicate PRL has never been allocated. This is to avoid continuously
allocating new PRL if there are multiple failed unbinds. Once a PRL is
invalidated, the tlb inval range should fallback to default behavior
and not allocate on scratch.
- Add xe_page_reclaim_list_entries_put into xe_page_reclaim_list_invalidate.
Modify code accordingly to accomadate change.
- Use xe_page_reclaim_list_valid() helper for clarity. (Matthew B)
- Remove unnecessary null check on put in tlb inval job. (Matthew B)
Suggested-by: Matthew Brost <matthew.brost@intel.com>
Brian Nguyen (8):
drm/xe/xe_tlb_inval: Modify fence interface to support PPC flush
drm/xe/guc: Add page reclamation interface to GuC
drm/xe: Create page reclaim list on unbind
drm/xe: Suballocate BO for page reclaim
drm/xe: Prep page reclaim in tlb inval job
drm/xe: Append page reclamation action to tlb inval
drm/xe: Optimize flushing of L2$ by skipping unnecessary page reclaim
drm/xe: Add debugfs support for page reclamation
Matthew Brost (1):
drm/xe: Do not forward invalid TLB invalidation seqnos to upper layers
Oak Zeng (1):
drm/xe: Add page reclamation info to device info
drivers/gpu/drm/xe/Makefile | 1 +
drivers/gpu/drm/xe/abi/guc_actions_abi.h | 2 +
drivers/gpu/drm/xe/regs/xe_gtt_defs.h | 1 +
drivers/gpu/drm/xe/xe_debugfs.c | 41 +++++++
drivers/gpu/drm/xe/xe_device_types.h | 9 ++
drivers/gpu/drm/xe/xe_guc.c | 4 +
drivers/gpu/drm/xe/xe_guc_ct.c | 17 +++
drivers/gpu/drm/xe/xe_guc_fwif.h | 1 +
drivers/gpu/drm/xe/xe_guc_tlb_inval.c | 37 ++++--
drivers/gpu/drm/xe/xe_page_reclaim.c | 136 +++++++++++++++++++++++
drivers/gpu/drm/xe/xe_page_reclaim.h | 105 +++++++++++++++++
drivers/gpu/drm/xe/xe_pat.c | 8 ++
drivers/gpu/drm/xe/xe_pat.h | 10 ++
drivers/gpu/drm/xe/xe_pci.c | 1 +
drivers/gpu/drm/xe/xe_pci_types.h | 1 +
drivers/gpu/drm/xe/xe_pt.c | 135 +++++++++++++++++++++-
drivers/gpu/drm/xe/xe_pt_types.h | 5 +
drivers/gpu/drm/xe/xe_tile.c | 5 +
drivers/gpu/drm/xe/xe_tlb_inval.c | 27 ++++-
drivers/gpu/drm/xe/xe_tlb_inval.h | 2 +-
drivers/gpu/drm/xe/xe_tlb_inval_job.c | 36 +++++-
drivers/gpu/drm/xe/xe_tlb_inval_job.h | 4 +
drivers/gpu/drm/xe/xe_tlb_inval_types.h | 5 +-
drivers/gpu/drm/xe/xe_vm.c | 4 +-
24 files changed, 581 insertions(+), 16 deletions(-)
create mode 100644 drivers/gpu/drm/xe/xe_page_reclaim.c
create mode 100644 drivers/gpu/drm/xe/xe_page_reclaim.h
--
2.52.0
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v5 01/10] drm/xe: Do not forward invalid TLB invalidation seqnos to upper layers
2025-12-10 1:45 [PATCH v5 00/10] Page Reclamation Support for Xe3p Platforms Brian Nguyen
@ 2025-12-10 1:45 ` Brian Nguyen
2025-12-10 1:45 ` [PATCH v5 02/10] drm/xe/xe_tlb_inval: Modify fence interface to support PPC flush Brian Nguyen
` (12 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Brian Nguyen @ 2025-12-10 1:45 UTC (permalink / raw)
To: intel-xe; +Cc: tejas.upadhyay, matthew.brost, shuicheng.lin, stuart.summers
From: Matthew Brost <matthew.brost@intel.com>
Certain TLB invalidation operations send multiple H2G messages per seqno
with only the final H2G containing the valid seqno - the others carry an
invalid seqno. The G2H handler drops these invalid seqno to aovid
prematurely signaling a TLB invalidation fence.
With TLB_INVALIDATION_SEQNO_INVALID used to indicate in progress
multi-step TLB invalidations, reset tdr to ensure that timeout
won't prematurely trigger when G2H actions are still ongoing.
v2: Remove lock from xe_tlb_inval_reset_timeout. (Matthew B)
v3: Squash with dependent patch from Matthew Brost' series.
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Brian Nguyen <brian3.nguyen@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
---
drivers/gpu/drm/xe/xe_tlb_inval.c | 20 ++++++++++++++++++++
drivers/gpu/drm/xe/xe_tlb_inval_types.h | 1 +
2 files changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_tlb_inval.c b/drivers/gpu/drm/xe/xe_tlb_inval.c
index 918a59e686ea..a122fbb9fc4a 100644
--- a/drivers/gpu/drm/xe/xe_tlb_inval.c
+++ b/drivers/gpu/drm/xe/xe_tlb_inval.c
@@ -199,6 +199,20 @@ void xe_tlb_inval_reset(struct xe_tlb_inval *tlb_inval)
mutex_unlock(&tlb_inval->seqno_lock);
}
+/**
+ * xe_tlb_inval_reset_timeout() - Reset TLB inval fence timeout
+ * @tlb_inval: TLB invalidation client
+ *
+ * Reset the TLB invalidation timeout timer.
+ */
+static void xe_tlb_inval_reset_timeout(struct xe_tlb_inval *tlb_inval)
+{
+ lockdep_assert_held(&tlb_inval->pending_lock);
+
+ mod_delayed_work(system_wq, &tlb_inval->fence_tdr,
+ tlb_inval->ops->timeout_delay(tlb_inval));
+}
+
static bool xe_tlb_inval_seqno_past(struct xe_tlb_inval *tlb_inval, int seqno)
{
int seqno_recv = READ_ONCE(tlb_inval->seqno_recv);
@@ -360,6 +374,12 @@ void xe_tlb_inval_done_handler(struct xe_tlb_inval *tlb_inval, int seqno)
* process_g2h_msg().
*/
spin_lock_irqsave(&tlb_inval->pending_lock, flags);
+ if (seqno == TLB_INVALIDATION_SEQNO_INVALID) {
+ xe_tlb_inval_reset_timeout(tlb_inval);
+ spin_unlock_irqrestore(&tlb_inval->pending_lock, flags);
+ return;
+ }
+
if (xe_tlb_inval_seqno_past(tlb_inval, seqno)) {
spin_unlock_irqrestore(&tlb_inval->pending_lock, flags);
return;
diff --git a/drivers/gpu/drm/xe/xe_tlb_inval_types.h b/drivers/gpu/drm/xe/xe_tlb_inval_types.h
index 8f8b060e9005..7a6967ce3b76 100644
--- a/drivers/gpu/drm/xe/xe_tlb_inval_types.h
+++ b/drivers/gpu/drm/xe/xe_tlb_inval_types.h
@@ -80,6 +80,7 @@ struct xe_tlb_inval {
const struct xe_tlb_inval_ops *ops;
/** @tlb_inval.seqno: TLB invalidation seqno, protected by CT lock */
#define TLB_INVALIDATION_SEQNO_MAX 0x100000
+#define TLB_INVALIDATION_SEQNO_INVALID TLB_INVALIDATION_SEQNO_MAX
int seqno;
/** @tlb_invalidation.seqno_lock: protects @tlb_invalidation.seqno */
struct mutex seqno_lock;
--
2.52.0
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v5 02/10] drm/xe/xe_tlb_inval: Modify fence interface to support PPC flush
2025-12-10 1:45 [PATCH v5 00/10] Page Reclamation Support for Xe3p Platforms Brian Nguyen
2025-12-10 1:45 ` [PATCH v5 01/10] drm/xe: Do not forward invalid TLB invalidation seqnos to upper layers Brian Nguyen
@ 2025-12-10 1:45 ` Brian Nguyen
2025-12-10 5:32 ` Upadhyay, Tejas
2025-12-10 1:45 ` [PATCH v5 03/10] drm/xe: Add page reclamation info to device info Brian Nguyen
` (11 subsequent siblings)
13 siblings, 1 reply; 22+ messages in thread
From: Brian Nguyen @ 2025-12-10 1:45 UTC (permalink / raw)
To: intel-xe; +Cc: tejas.upadhyay, matthew.brost, shuicheng.lin, stuart.summers
Allow tlb_invalidation to control when driver wants to flush the
Private Physical Cache (PPC) as a process of the tlb invalidation
process.
Default behavior is still to always flush the PPC but driver now has the
option to disable it.
v2:
- Revise commit/kernel doc descriptions. (Shuicheng)
- Remove unused function. (Shuicheng)
- Remove bool flush_cache parameter from fence,
and various function inputs. (Matthew B)
Signed-off-by: Brian Nguyen <brian3.nguyen@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
Cc: Shuicheng Lin <shuicheng.lin@intel.com>
---
drivers/gpu/drm/xe/xe_guc_tlb_inval.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_guc_tlb_inval.c b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
index 848d3493df10..37ac943cb10f 100644
--- a/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
+++ b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
@@ -34,9 +34,12 @@ static int send_tlb_inval(struct xe_guc *guc, const u32 *action, int len)
G2H_LEN_DW_TLB_INVALIDATE, 1);
}
-#define MAKE_INVAL_OP(type) ((type << XE_GUC_TLB_INVAL_TYPE_SHIFT) | \
+#define MAKE_INVAL_OP_FLUSH(type, flush_cache) ((type << XE_GUC_TLB_INVAL_TYPE_SHIFT) | \
XE_GUC_TLB_INVAL_MODE_HEAVY << XE_GUC_TLB_INVAL_MODE_SHIFT | \
- XE_GUC_TLB_INVAL_FLUSH_CACHE)
+ (flush_cache ? \
+ XE_GUC_TLB_INVAL_FLUSH_CACHE : 0))
+
+#define MAKE_INVAL_OP(type) MAKE_INVAL_OP_FLUSH(type, true)
static int send_tlb_inval_all(struct xe_tlb_inval *tlb_inval, u32 seqno)
{
@@ -152,7 +155,7 @@ static int send_tlb_inval_ppgtt(struct xe_tlb_inval *tlb_inval, u32 seqno,
ilog2(SZ_2M) + 1)));
xe_gt_assert(gt, IS_ALIGNED(start, length));
- action[len++] = MAKE_INVAL_OP(XE_GUC_TLB_INVAL_PAGE_SELECTIVE);
+ action[len++] = MAKE_INVAL_OP_FLUSH(XE_GUC_TLB_INVAL_PAGE_SELECTIVE, true);
action[len++] = asid;
action[len++] = lower_32_bits(start);
action[len++] = upper_32_bits(start);
--
2.52.0
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v5 03/10] drm/xe: Add page reclamation info to device info
2025-12-10 1:45 [PATCH v5 00/10] Page Reclamation Support for Xe3p Platforms Brian Nguyen
2025-12-10 1:45 ` [PATCH v5 01/10] drm/xe: Do not forward invalid TLB invalidation seqnos to upper layers Brian Nguyen
2025-12-10 1:45 ` [PATCH v5 02/10] drm/xe/xe_tlb_inval: Modify fence interface to support PPC flush Brian Nguyen
@ 2025-12-10 1:45 ` Brian Nguyen
2025-12-10 1:45 ` [PATCH v5 04/10] drm/xe/guc: Add page reclamation interface to GuC Brian Nguyen
` (10 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Brian Nguyen @ 2025-12-10 1:45 UTC (permalink / raw)
To: intel-xe
Cc: tejas.upadhyay, matthew.brost, shuicheng.lin, stuart.summers,
Oak Zeng
From: Oak Zeng <oak.zeng@intel.com>
Starting from Xe3p, HW adds a feature assisting range based page
reclamation. Introduce a bit in device info to indicate whether
device has such capability.
Signed-off-by: Oak Zeng <oak.zeng@intel.com>
Signed-off-by: Brian Nguyen <brian3.nguyen@intel.com>
Reviewed-by: Shuicheng Lin <shuicheng.lin@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
---
drivers/gpu/drm/xe/xe_device_types.h | 2 ++
drivers/gpu/drm/xe/xe_pci.c | 1 +
drivers/gpu/drm/xe/xe_pci_types.h | 1 +
3 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 9de73353223f..3836c5ed1c72 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -315,6 +315,8 @@ struct xe_device {
u8 has_mem_copy_instr:1;
/** @info.has_mert: Device has standalone MERT */
u8 has_mert:1;
+ /** @info.has_page_reclaim_hw_assist: Device supports page reclamation feature */
+ u8 has_page_reclaim_hw_assist:1;
/** @info.has_pxp: Device has PXP support */
u8 has_pxp:1;
/** @info.has_range_tlb_inval: Has range based TLB invalidations */
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index aaea2044c86e..4de52b0a3db5 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -682,6 +682,7 @@ static int xe_info_init_early(struct xe_device *xe,
xe->info.has_late_bind = desc->has_late_bind;
xe->info.has_llc = desc->has_llc;
xe->info.has_mert = desc->has_mert;
+ xe->info.has_page_reclaim_hw_assist = desc->has_page_reclaim_hw_assist;
xe->info.has_pxp = desc->has_pxp;
xe->info.has_sriov = xe_configfs_primary_gt_allowed(to_pci_dev(xe->drm.dev)) &&
desc->has_sriov;
diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
index f19f35359696..96feae80b705 100644
--- a/drivers/gpu/drm/xe/xe_pci_types.h
+++ b/drivers/gpu/drm/xe/xe_pci_types.h
@@ -49,6 +49,7 @@ struct xe_device_desc {
u8 has_mbx_power_limits:1;
u8 has_mem_copy_instr:1;
u8 has_mert:1;
+ u8 has_page_reclaim_hw_assist:1;
u8 has_pxp:1;
u8 has_sriov:1;
u8 needs_scratch:1;
--
2.52.0
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v5 04/10] drm/xe/guc: Add page reclamation interface to GuC
2025-12-10 1:45 [PATCH v5 00/10] Page Reclamation Support for Xe3p Platforms Brian Nguyen
` (2 preceding siblings ...)
2025-12-10 1:45 ` [PATCH v5 03/10] drm/xe: Add page reclamation info to device info Brian Nguyen
@ 2025-12-10 1:45 ` Brian Nguyen
2025-12-10 1:45 ` [PATCH v5 05/10] drm/xe: Create page reclaim list on unbind Brian Nguyen
` (9 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Brian Nguyen @ 2025-12-10 1:45 UTC (permalink / raw)
To: intel-xe; +Cc: tejas.upadhyay, matthew.brost, shuicheng.lin, stuart.summers
Add page reclamation related changes to GuC interface, handlers, and
senders to support page reclamation.
Currently TLB invalidations will perform an entire PPC flush in order to
prevent stale memory access for noncoherent system memory. Page
reclamation is an extension of the typical TLB invalidation
workflow, allowing disabling of full PPC flush and enable selective PPC
flushing. Selective flushing will be decided by a list of pages whom's
address is passed to GuC at time of action.
Page reclamation interfaces require at least GuC FW ver 70.31.0.
v2:
- Moved send_page_reclaim to first patch usage.
- Add comments explaining shared done handler. (Matthew B)
- Add FW version fallback to disable page reclaim
on older versions. (Matthew B, Shuicheng)
Signed-off-by: Brian Nguyen <brian3.nguyen@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Shuicheng Lin <shuicheng.lin@intel.com>
---
drivers/gpu/drm/xe/abi/guc_actions_abi.h | 2 ++
drivers/gpu/drm/xe/xe_guc.c | 4 ++++
drivers/gpu/drm/xe/xe_guc_ct.c | 17 +++++++++++++++++
drivers/gpu/drm/xe/xe_guc_fwif.h | 1 +
4 files changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/xe/abi/guc_actions_abi.h b/drivers/gpu/drm/xe/abi/guc_actions_abi.h
index 47756e4674a1..11de3bdf69b5 100644
--- a/drivers/gpu/drm/xe/abi/guc_actions_abi.h
+++ b/drivers/gpu/drm/xe/abi/guc_actions_abi.h
@@ -151,6 +151,8 @@ enum xe_guc_action {
XE_GUC_ACTION_TLB_INVALIDATION = 0x7000,
XE_GUC_ACTION_TLB_INVALIDATION_DONE = 0x7001,
XE_GUC_ACTION_TLB_INVALIDATION_ALL = 0x7002,
+ XE_GUC_ACTION_PAGE_RECLAMATION = 0x7003,
+ XE_GUC_ACTION_PAGE_RECLAMATION_DONE = 0x7004,
XE_GUC_ACTION_STATE_CAPTURE_NOTIFICATION = 0x8002,
XE_GUC_ACTION_NOTIFY_FLUSH_LOG_BUFFER_TO_FILE = 0x8003,
XE_GUC_ACTION_NOTIFY_CRASH_DUMP_POSTED = 0x8004,
diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index f0407bab9a0c..7daae3294665 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -767,6 +767,10 @@ int xe_guc_init(struct xe_guc *guc)
if (!xe_uc_fw_is_enabled(&guc->fw))
return 0;
+ /* Disable page reclaim if GuC FW does not support */
+ if (GUC_FIRMWARE_VER(guc) < MAKE_GUC_VER(70, 31, 0))
+ xe->info.has_page_reclaim_hw_assist = false;
+
if (IS_SRIOV_VF(xe)) {
ret = xe_guc_ct_init(&guc->ct);
if (ret)
diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c b/drivers/gpu/drm/xe/xe_guc_ct.c
index 648f0f523abb..1c2acdec151a 100644
--- a/drivers/gpu/drm/xe/xe_guc_ct.c
+++ b/drivers/gpu/drm/xe/xe_guc_ct.c
@@ -1405,6 +1405,7 @@ static int parse_g2h_event(struct xe_guc_ct *ct, u32 *msg, u32 len)
case XE_GUC_ACTION_DEREGISTER_CONTEXT_DONE:
case XE_GUC_ACTION_SCHED_ENGINE_MODE_DONE:
case XE_GUC_ACTION_TLB_INVALIDATION_DONE:
+ case XE_GUC_ACTION_PAGE_RECLAMATION_DONE:
g2h_release_space(ct, len);
}
@@ -1591,6 +1592,15 @@ static int process_g2h_msg(struct xe_guc_ct *ct, u32 *msg, u32 len)
ret = xe_guc_pagefault_handler(guc, payload, adj_len);
break;
case XE_GUC_ACTION_TLB_INVALIDATION_DONE:
+ case XE_GUC_ACTION_PAGE_RECLAMATION_DONE:
+ /*
+ * Page reclamation is an extension of TLB invalidation. Both
+ * operations share the same seqno and fence. When either
+ * action completes, we need to signal the corresponding
+ * fence. Since the handling logic (lookup fence by seqno,
+ * fence signalling) is identical, we use the same handler
+ * for both G2H events.
+ */
ret = xe_guc_tlb_inval_done_handler(guc, payload, adj_len);
break;
case XE_GUC_ACTION_GUC2PF_RELAY_FROM_VF:
@@ -1756,6 +1766,7 @@ static int g2h_read(struct xe_guc_ct *ct, u32 *msg, bool fast_path)
switch (action) {
case XE_GUC_ACTION_REPORT_PAGE_FAULT_REQ_DESC:
case XE_GUC_ACTION_TLB_INVALIDATION_DONE:
+ case XE_GUC_ACTION_PAGE_RECLAMATION_DONE:
break; /* Process these in fast-path */
default:
return 0;
@@ -1792,6 +1803,12 @@ static void g2h_fast_path(struct xe_guc_ct *ct, u32 *msg, u32 len)
ret = xe_guc_pagefault_handler(guc, payload, adj_len);
break;
case XE_GUC_ACTION_TLB_INVALIDATION_DONE:
+ case XE_GUC_ACTION_PAGE_RECLAMATION_DONE:
+ /*
+ * Seqno and fence handling of page reclamation and TLB
+ * invalidation is identical, so we can use the same handler
+ * for both actions.
+ */
__g2h_release_space(ct, len);
ret = xe_guc_tlb_inval_done_handler(guc, payload, adj_len);
break;
diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h
index 7d93c2749485..5aa6fb249be9 100644
--- a/drivers/gpu/drm/xe/xe_guc_fwif.h
+++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
@@ -16,6 +16,7 @@
#define G2H_LEN_DW_DEREGISTER_CONTEXT 3
#define G2H_LEN_DW_TLB_INVALIDATE 3
#define G2H_LEN_DW_G2G_NOTIFY_MIN 3
+#define G2H_LEN_DW_PAGE_RECLAMATION 3
#define GUC_ID_MAX 65535
#define GUC_ID_UNKNOWN 0xffffffff
--
2.52.0
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v5 05/10] drm/xe: Create page reclaim list on unbind
2025-12-10 1:45 [PATCH v5 00/10] Page Reclamation Support for Xe3p Platforms Brian Nguyen
` (3 preceding siblings ...)
2025-12-10 1:45 ` [PATCH v5 04/10] drm/xe/guc: Add page reclamation interface to GuC Brian Nguyen
@ 2025-12-10 1:45 ` Brian Nguyen
2025-12-10 2:13 ` Matthew Brost
2025-12-10 1:45 ` [PATCH v5 06/10] drm/xe: Suballocate BO for page reclaim Brian Nguyen
` (8 subsequent siblings)
13 siblings, 1 reply; 22+ messages in thread
From: Brian Nguyen @ 2025-12-10 1:45 UTC (permalink / raw)
To: intel-xe; +Cc: tejas.upadhyay, matthew.brost, shuicheng.lin, stuart.summers
Page reclaim list (PRL) is preparation work for the page reclaim feature.
The PRL is firstly owned by pt_update_ops and all other page reclaim
operations will point back to this PRL. PRL generates its entries during
the unbind page walker, updating the PRL.
This PRL is restricted to a 4K page, so 512 page entries at most.
v2:
- Removed unused function. (Shuicheng)
- Compacted warning checking, update commit message,
spelling, etc. (Shuicheng, Matthew B)
- Fix kernel docs
- Moved PRL max entries overflow handling out from
generate_reclaim_entry to caller (Shuicheng)
- Add xe_page_reclaim_list_init for clarity. (Matthew B)
- Modify xe_guc_page_reclaim_entry to use macros
for greater flexbility. (Matthew B)
- Add fallback for PTE outside of page reclaim supported
4K, 64K, 2M pages (Matthew B)
- Invalidate PRL for early abort page walk.
- Removed page reclaim related variables from tlb fence
(Matthew Brost)
- Remove error handling in *alloc_entries failure. (Matthew B)
v3:
- Fix NULL pointer dereference check.
- Modify reclaim_entry to QW and bitfields accordingly. (Matthew B)
- Add vm_dbg prints for PRL generation and invalidation. (Matthew B)
v4:
- s/GENMASK/GENMASK_ULL && s/BIT/BIT_ULL (CI)
v5:
- Addition of xe_page_reclaim_list_is_new() to avoid continuous
allocation of PRL if consecutive VMAs cause a PRL invalidation.
- Add xe_page_reclaim_list_valid() helpers for clarity. (Matthew B)
- Move xe_page_reclaim_list_entries_put in
xe_page_reclaim_list_invalidate.
Signed-off-by: Brian Nguyen <brian3.nguyen@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Shuicheng Lin <shuicheng.lin@intel.com>
---
drivers/gpu/drm/xe/Makefile | 1 +
drivers/gpu/drm/xe/regs/xe_gtt_defs.h | 1 +
drivers/gpu/drm/xe/xe_page_reclaim.c | 65 ++++++++++++++
drivers/gpu/drm/xe/xe_page_reclaim.h | 96 ++++++++++++++++++++
drivers/gpu/drm/xe/xe_pt.c | 123 +++++++++++++++++++++++++-
drivers/gpu/drm/xe/xe_pt_types.h | 5 ++
6 files changed, 290 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/xe/xe_page_reclaim.c
create mode 100644 drivers/gpu/drm/xe/xe_page_reclaim.h
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 6ecba27d85f7..7f08b4cd91d6 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -95,6 +95,7 @@ xe-y += xe_bb.o \
xe_oa.o \
xe_observation.o \
xe_pagefault.o \
+ xe_page_reclaim.o \
xe_pat.o \
xe_pci.o \
xe_pcode.o \
diff --git a/drivers/gpu/drm/xe/regs/xe_gtt_defs.h b/drivers/gpu/drm/xe/regs/xe_gtt_defs.h
index 4389e5a76f89..4d83461e538b 100644
--- a/drivers/gpu/drm/xe/regs/xe_gtt_defs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gtt_defs.h
@@ -9,6 +9,7 @@
#define XELPG_GGTT_PTE_PAT0 BIT_ULL(52)
#define XELPG_GGTT_PTE_PAT1 BIT_ULL(53)
+#define XE_PTE_ADDR_MASK GENMASK_ULL(51, 12)
#define GGTT_PTE_VFID GENMASK_ULL(11, 2)
#define GUC_GGTT_TOP 0xFEE00000
diff --git a/drivers/gpu/drm/xe/xe_page_reclaim.c b/drivers/gpu/drm/xe/xe_page_reclaim.c
new file mode 100644
index 000000000000..018d546fcf50
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_page_reclaim.c
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#include <linux/bitfield.h>
+#include <linux/kref.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+
+#include "xe_page_reclaim.h"
+
+#include "regs/xe_gt_regs.h"
+#include "xe_assert.h"
+#include "xe_macros.h"
+
+/**
+ * xe_page_reclaim_list_invalidate() - Mark a PRL as invalid
+ * @prl: Page reclaim list to reset
+ *
+ * Clears the entries pointer and marks the list as invalid so
+ * future use knows PRL is unusable. It is expected that the entries
+ * have already been released.
+ */
+void xe_page_reclaim_list_invalidate(struct xe_page_reclaim_list *prl)
+{
+ xe_page_reclaim_entries_put(prl->entries);
+ prl->entries = NULL;
+ prl->num_entries = XE_PAGE_RECLAIM_INVALID_LIST;
+}
+
+/**
+ * xe_page_reclaim_list_init() - Initialize a page reclaim list
+ * @prl: Page reclaim list to initialize
+ *
+ * NULLs both values in list to prepare on initalization.
+ */
+void xe_page_reclaim_list_init(struct xe_page_reclaim_list *prl)
+{
+ // xe_page_reclaim_list_invalidate(prl);
+ prl->entries = NULL;
+ prl->num_entries = 0;
+}
+
+/**
+ * xe_page_reclaim_list_alloc_entries() - Allocate page reclaim list entries
+ * @prl: Page reclaim list to allocate entries for
+ *
+ * Allocate one 4K page for the PRL entries, otherwise assign prl->entries to NULL.
+ */
+int xe_page_reclaim_list_alloc_entries(struct xe_page_reclaim_list *prl)
+{
+ struct page *page;
+
+ if (XE_WARN_ON(prl->entries))
+ return 0;
+
+ page = alloc_page(GFP_KERNEL | __GFP_ZERO);
+ if (page) {
+ prl->entries = page_address(page);
+ prl->num_entries = 0;
+ }
+
+ return page ? 0 : -ENOMEM;
+}
diff --git a/drivers/gpu/drm/xe/xe_page_reclaim.h b/drivers/gpu/drm/xe/xe_page_reclaim.h
new file mode 100644
index 000000000000..93f19fe6d146
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_page_reclaim.h
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef _XE_PAGE_RECLAIM_H_
+#define _XE_PAGE_RECLAIM_H_
+
+#include <linux/kref.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+#include <linux/workqueue.h>
+#include <linux/bits.h>
+
+#define XE_PAGE_RECLAIM_MAX_ENTRIES 512
+#define XE_PAGE_RECLAIM_LIST_MAX_SIZE SZ_4K
+
+struct xe_guc_page_reclaim_entry {
+ u64 qw;
+/* valid reclaim entry bit */
+#define XE_PAGE_RECLAIM_VALID BIT_ULL(0)
+/*
+ * offset order of page size to be reclaimed
+ * page_size = 1 << (XE_PTE_SHIFT + reclamation_size)
+ */
+#define XE_PAGE_RECLAIM_SIZE GENMASK_ULL(6, 1)
+#define XE_PAGE_RECLAIM_RSVD_0 GENMASK_ULL(11, 7)
+/* lower 20 bits of the physical address */
+#define XE_PAGE_RECLAIM_ADDR_LO GENMASK_ULL(31, 12)
+/* upper 20 bits of the physical address */
+#define XE_PAGE_RECLAIM_ADDR_HI GENMASK_ULL(51, 32)
+#define XE_PAGE_RECLAIM_RSVD_1 GENMASK_ULL(63, 52)
+} __packed;
+
+struct xe_page_reclaim_list {
+ /** @entries: array of page reclaim entries, page allocated */
+ struct xe_guc_page_reclaim_entry *entries;
+ /** @num_entries: number of entries */
+ int num_entries;
+#define XE_PAGE_RECLAIM_INVALID_LIST -1
+};
+
+/**
+ * xe_page_reclaim_list_is_new() - Check if PRL is new allocation
+ * @prl: Pointer to page reclaim list
+ *
+ * PRL indicates it hasn't been allocated through both values being NULL
+ */
+static inline bool xe_page_reclaim_list_is_new(struct xe_page_reclaim_list *prl)
+{
+ return prl->entries == NULL && prl->num_entries == 0;
+}
+
+/**
+ * xe_page_reclaim_list_valid() - Check if the page reclaim list is valid
+ * @prl: Pointer to page reclaim list
+ *
+ * PRL uses the XE_PAGE_RECLAIM_INVALID_LIST to indicate that a PRL
+ * is unusable.
+ */
+static inline bool xe_page_reclaim_list_valid(struct xe_page_reclaim_list *prl)
+{
+ return !xe_page_reclaim_list_is_new(prl) &&
+ prl->num_entries != XE_PAGE_RECLAIM_INVALID_LIST;
+}
+
+void xe_page_reclaim_list_invalidate(struct xe_page_reclaim_list *prl);
+void xe_page_reclaim_list_init(struct xe_page_reclaim_list *prl);
+int xe_page_reclaim_list_alloc_entries(struct xe_page_reclaim_list *prl);
+/**
+ * xe_page_reclaim_entries_get() - Increment the reference count of page reclaim entries.
+ * @entries: Pointer to the array of page reclaim entries.
+ *
+ * This function increments the reference count of the backing page.
+ */
+static inline void xe_page_reclaim_entries_get(struct xe_guc_page_reclaim_entry *entries)
+{
+ if (entries)
+ get_page(virt_to_page(entries));
+}
+
+/**
+ * xe_page_reclaim_entries_put() - Decrement the reference count of page reclaim entries.
+ * @entries: Pointer to the array of page reclaim entries.
+ *
+ * This function decrements the reference count of the backing page
+ * and frees it if the count reaches zero.
+ */
+static inline void xe_page_reclaim_entries_put(struct xe_guc_page_reclaim_entry *entries)
+{
+ if (entries)
+ put_page(virt_to_page(entries));
+}
+
+#endif /* _XE_PAGE_RECLAIM_H_ */
diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c
index 884127b4d97d..89802cc16b47 100644
--- a/drivers/gpu/drm/xe/xe_pt.c
+++ b/drivers/gpu/drm/xe/xe_pt.c
@@ -12,6 +12,7 @@
#include "xe_exec_queue.h"
#include "xe_gt.h"
#include "xe_migrate.h"
+#include "xe_page_reclaim.h"
#include "xe_pt_types.h"
#include "xe_pt_walk.h"
#include "xe_res_cursor.h"
@@ -1535,6 +1536,9 @@ struct xe_pt_stage_unbind_walk {
/** @modified_end: Walk range start, modified like @modified_start. */
u64 modified_end;
+ /** @prl: Backing pointer to page reclaim list in pt_update_ops */
+ struct xe_page_reclaim_list *prl;
+
/* Output */
/* @wupd: Structure to track the page-table updates we're building */
struct xe_walk_update wupd;
@@ -1572,6 +1576,68 @@ static bool xe_pt_check_kill(u64 addr, u64 next, unsigned int level,
return false;
}
+/* Huge 2MB leaf lives directly in a level-1 table and has no children */
+static bool is_2m_pte(struct xe_pt *pte)
+{
+ return pte->level == 1 && !pte->base.children;
+}
+
+/* page_size = 2^(reclamation_size + XE_PTE_SHIFT) */
+#define COMPUTE_RECLAIM_ADDRESS_MASK(page_size) \
+({ \
+ BUILD_BUG_ON(!__builtin_constant_p(page_size)); \
+ ilog2(page_size) - XE_PTE_SHIFT; \
+})
+
+static int generate_reclaim_entry(struct xe_tile *tile,
+ struct xe_page_reclaim_list *prl,
+ u64 pte, struct xe_pt *xe_child)
+{
+ struct xe_guc_page_reclaim_entry *reclaim_entries = prl->entries;
+ u64 phys_page = (pte & XE_PTE_ADDR_MASK) >> XE_PTE_SHIFT;
+ int num_entries = prl->num_entries;
+ u32 reclamation_size;
+
+ xe_tile_assert(tile, xe_child->level <= MAX_HUGEPTE_LEVEL);
+ xe_tile_assert(tile, reclaim_entries);
+ xe_tile_assert(tile, num_entries < XE_PAGE_RECLAIM_MAX_ENTRIES - 1);
+
+ if (!xe_page_reclaim_list_valid(prl))
+ return -EINVAL;
+
+ /**
+ * reclamation_size indicates the size of the page to be
+ * invalidated and flushed from non-coherent cache.
+ * Page size is computed as 2^(reclamation_size + XE_PTE_SHIFT) bytes.
+ * Only 4K, 64K (level 0), and 2M pages are supported by hardware for page reclaim
+ */
+ if (xe_child->level == 0 && !(pte & XE_PTE_PS64)) {
+ reclamation_size = COMPUTE_RECLAIM_ADDRESS_MASK(SZ_4K); /* reclamation_size = 0 */
+ } else if (xe_child->level == 0) {
+ reclamation_size = COMPUTE_RECLAIM_ADDRESS_MASK(SZ_64K); /* reclamation_size = 4 */
+ } else if (is_2m_pte(xe_child)) {
+ reclamation_size = COMPUTE_RECLAIM_ADDRESS_MASK(SZ_2M); /* reclamation_size = 9 */
+ } else {
+ xe_page_reclaim_list_invalidate(prl);
+ vm_dbg(&tile_to_xe(tile)->drm,
+ "PRL invalidate: unsupported PTE level=%u pte=%#llx\n",
+ xe_child->level, pte);
+ return -EINVAL;
+ }
+
+ reclaim_entries[num_entries].qw =
+ FIELD_PREP(XE_PAGE_RECLAIM_VALID, 1) |
+ FIELD_PREP(XE_PAGE_RECLAIM_SIZE, reclamation_size) |
+ FIELD_PREP(XE_PAGE_RECLAIM_ADDR_LO, phys_page) |
+ FIELD_PREP(XE_PAGE_RECLAIM_ADDR_HI, phys_page >> 20);
+ prl->num_entries++;
+ vm_dbg(&tile_to_xe(tile)->drm,
+ "PRL add entry: level=%u pte=%#llx reclamation_size=%u prl_idx=%d\n",
+ xe_child->level, pte, reclamation_size, num_entries);
+
+ return 0;
+}
+
static int xe_pt_stage_unbind_entry(struct xe_ptw *parent, pgoff_t offset,
unsigned int level, u64 addr, u64 next,
struct xe_ptw **child,
@@ -1579,11 +1645,48 @@ static int xe_pt_stage_unbind_entry(struct xe_ptw *parent, pgoff_t offset,
struct xe_pt_walk *walk)
{
struct xe_pt *xe_child = container_of(*child, typeof(*xe_child), base);
+ struct xe_pt_stage_unbind_walk *xe_walk =
+ container_of(walk, typeof(*xe_walk), base);
+ struct xe_device *xe = tile_to_xe(xe_walk->tile);
XE_WARN_ON(!*child);
XE_WARN_ON(!level);
+ /* Check for leaf node */
+ if (xe_walk->prl && xe_page_reclaim_list_valid(xe_walk->prl) &&
+ !xe_child->base.children) {
+ struct iosys_map *leaf_map = &xe_child->bo->vmap;
+ pgoff_t first = xe_pt_offset(addr, 0, walk);
+ pgoff_t count = xe_pt_num_entries(addr, next, 0, walk);
+
+ for (pgoff_t i = 0; i < count; i++) {
+ u64 pte = xe_map_rd(xe, leaf_map, (first + i) * sizeof(u64), u64);
+ int ret;
+
+ /* Account for NULL terminated entry on end (-1) */
+ if (xe_walk->prl->num_entries < XE_PAGE_RECLAIM_MAX_ENTRIES - 1) {
+ ret = generate_reclaim_entry(xe_walk->tile, xe_walk->prl,
+ pte, xe_child);
+ if (ret)
+ break;
+ } else {
+ /* overflow, mark as invalid */
+ xe_page_reclaim_list_invalidate(xe_walk->prl);
+ vm_dbg(&xe->drm,
+ "PRL invalidate: overflow while adding pte=%#llx",
+ pte);
+ break;
+ }
+ }
+ }
- xe_pt_check_kill(addr, next, level - 1, xe_child, action, walk);
+ /* If aborting page walk early, invalidate PRL since PTE may be dropped from this abort */
+ if (xe_pt_check_kill(addr, next, level - 1, xe_child, action, walk) &&
+ xe_walk->prl && level > 1 && xe_child->base.children && xe_child->num_live != 0) {
+ xe_page_reclaim_list_invalidate(xe_walk->prl);
+ vm_dbg(&xe->drm,
+ "PRL invalidate: kill at level=%u addr=%#llx next=%#llx num_live=%u\n",
+ level, addr, next, xe_child->num_live);
+ }
return 0;
}
@@ -1654,6 +1757,8 @@ static unsigned int xe_pt_stage_unbind(struct xe_tile *tile,
{
u64 start = range ? xe_svm_range_start(range) : xe_vma_start(vma);
u64 end = range ? xe_svm_range_end(range) : xe_vma_end(vma);
+ struct xe_vm_pgtable_update_op *pt_update_op =
+ container_of(entries, struct xe_vm_pgtable_update_op, entries[0]);
struct xe_pt_stage_unbind_walk xe_walk = {
.base = {
.ops = &xe_pt_stage_unbind_ops,
@@ -1665,6 +1770,7 @@ static unsigned int xe_pt_stage_unbind(struct xe_tile *tile,
.modified_start = start,
.modified_end = end,
.wupd.entries = entries,
+ .prl = pt_update_op->prl,
};
struct xe_pt *pt = vm->pt_root[tile->id];
@@ -1897,6 +2003,7 @@ static int unbind_op_prepare(struct xe_tile *tile,
struct xe_vm_pgtable_update_ops *pt_update_ops,
struct xe_vma *vma)
{
+ struct xe_device *xe = tile_to_xe(tile);
u32 current_op = pt_update_ops->current_op;
struct xe_vm_pgtable_update_op *pt_op = &pt_update_ops->ops[current_op];
int err;
@@ -1914,6 +2021,16 @@ static int unbind_op_prepare(struct xe_tile *tile,
pt_op->vma = vma;
pt_op->bind = false;
pt_op->rebind = false;
+ /*
+ * Maintain one PRL located in pt_update_ops that all others in unbind op reference.
+ * Ensure that PRL is allocated only once, and if invalidated, remains an invalidated PRL.
+ */
+ if (xe->info.has_page_reclaim_hw_assist &&
+ xe_page_reclaim_list_is_new(&pt_update_ops->prl))
+ xe_page_reclaim_list_alloc_entries(&pt_update_ops->prl);
+
+ /* Page reclaim may not be needed due to other features, so skip the corresponding VMA */
+ pt_op->prl = (xe_page_reclaim_list_valid(&pt_update_ops->prl)) ? &pt_update_ops->prl : NULL;
err = vma_reserve_fences(tile_to_xe(tile), vma);
if (err)
@@ -1979,6 +2096,7 @@ static int unbind_range_prepare(struct xe_vm *vm,
pt_op->vma = XE_INVALID_VMA;
pt_op->bind = false;
pt_op->rebind = false;
+ pt_op->prl = NULL;
pt_op->num_entries = xe_pt_stage_unbind(tile, vm, NULL, range,
pt_op->entries);
@@ -2096,6 +2214,7 @@ xe_pt_update_ops_init(struct xe_vm_pgtable_update_ops *pt_update_ops)
init_llist_head(&pt_update_ops->deferred);
pt_update_ops->start = ~0x0ull;
pt_update_ops->last = 0x0ull;
+ xe_page_reclaim_list_init(&pt_update_ops->prl);
}
/**
@@ -2518,6 +2637,8 @@ void xe_pt_update_ops_fini(struct xe_tile *tile, struct xe_vma_ops *vops)
&vops->pt_update_ops[tile->id];
int i;
+ xe_page_reclaim_entries_put(pt_update_ops->prl.entries);
+
lockdep_assert_held(&vops->vm->lock);
xe_vm_assert_held(vops->vm);
diff --git a/drivers/gpu/drm/xe/xe_pt_types.h b/drivers/gpu/drm/xe/xe_pt_types.h
index 881f01e14db8..88fabf8e2655 100644
--- a/drivers/gpu/drm/xe/xe_pt_types.h
+++ b/drivers/gpu/drm/xe/xe_pt_types.h
@@ -8,6 +8,7 @@
#include <linux/types.h>
+#include "xe_page_reclaim.h"
#include "xe_pt_walk.h"
struct xe_bo;
@@ -79,6 +80,8 @@ struct xe_vm_pgtable_update_op {
struct xe_vm_pgtable_update entries[XE_VM_MAX_LEVEL * 2 + 1];
/** @vma: VMA for operation, operation not valid if NULL */
struct xe_vma *vma;
+ /** @prl: Backing pointer to page reclaim list of pt_update_ops */
+ struct xe_page_reclaim_list *prl;
/** @num_entries: number of entries for this update operation */
u32 num_entries;
/** @bind: is a bind */
@@ -95,6 +98,8 @@ struct xe_vm_pgtable_update_ops {
struct llist_head deferred;
/** @q: exec queue for PT operations */
struct xe_exec_queue *q;
+ /** @prl: embedded page reclaim list */
+ struct xe_page_reclaim_list prl;
/** @start: start address of ops */
u64 start;
/** @last: last address of ops */
--
2.52.0
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v5 06/10] drm/xe: Suballocate BO for page reclaim
2025-12-10 1:45 [PATCH v5 00/10] Page Reclamation Support for Xe3p Platforms Brian Nguyen
` (4 preceding siblings ...)
2025-12-10 1:45 ` [PATCH v5 05/10] drm/xe: Create page reclaim list on unbind Brian Nguyen
@ 2025-12-10 1:45 ` Brian Nguyen
2025-12-10 1:45 ` [PATCH v5 07/10] drm/xe: Prep page reclaim in tlb inval job Brian Nguyen
` (7 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Brian Nguyen @ 2025-12-10 1:45 UTC (permalink / raw)
To: intel-xe; +Cc: tejas.upadhyay, matthew.brost, shuicheng.lin, stuart.summers
Page reclamation feature needs the PRL to be suballocated into a
GGTT-mapped BO. On allocation failure, fallback to default tlb
invalidation with full PPC flush.
PRL's BO allocation is managed in separate pool to ensure 4K alignment
for proper GGTT address.
With BO, pass into TLB invalidation backend and modify fence to
accomadate accordingly.
v2:
- Removed page reclaim related variables from TLB fence. (Matthew B)
- Allocate PRL bo size to num_entries. (Matthew B)
- Move PRL bo allocation to tlb_inval run_job. (Matthew B)
v5:
- Use xe_page_reclaim_list_valid. (Matthew B)
Signed-off-by: Brian Nguyen <brian3.nguyen@intel.com>
Suggested-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
---
drivers/gpu/drm/xe/xe_device_types.h | 7 +++++
drivers/gpu/drm/xe/xe_page_reclaim.c | 39 +++++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_page_reclaim.h | 6 +++++
drivers/gpu/drm/xe/xe_tile.c | 5 ++++
drivers/gpu/drm/xe/xe_tlb_inval_job.c | 9 +++++++
5 files changed, 66 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 3836c5ed1c72..155ea0800f1b 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -184,6 +184,13 @@ struct xe_tile {
* Media GT shares a pool with its primary GT.
*/
struct xe_sa_manager *kernel_bb_pool;
+
+ /**
+ * @mem.reclaim_pool: Pool for PRLs allocated.
+ *
+ * Only main GT has page reclaim list allocations.
+ */
+ struct xe_sa_manager *reclaim_pool;
} mem;
/** @sriov: tile level virtualization data */
diff --git a/drivers/gpu/drm/xe/xe_page_reclaim.c b/drivers/gpu/drm/xe/xe_page_reclaim.c
index 018d546fcf50..0cce5ad2e33b 100644
--- a/drivers/gpu/drm/xe/xe_page_reclaim.c
+++ b/drivers/gpu/drm/xe/xe_page_reclaim.c
@@ -13,6 +13,45 @@
#include "regs/xe_gt_regs.h"
#include "xe_assert.h"
#include "xe_macros.h"
+#include "xe_sa.h"
+#include "xe_tlb_inval_types.h"
+
+/**
+ * xe_page_reclaim_create_prl_bo() - Back a PRL with a suballocated GGTT BO
+ * @tlb_inval: TLB invalidation frontend associated with the request
+ * @prl: page reclaim list data that bo will copy from
+ * @fence: tlb invalidation fence that page reclaim action is paired to
+ *
+ * Suballocates a 4K BO out of the tile reclaim pool, copies the PRL CPU
+ * copy into the BO and queues the buffer for release when @fence signals.
+ *
+ * Return: struct drm_suballoc pointer on success or ERR_PTR on failure.
+ */
+struct drm_suballoc *xe_page_reclaim_create_prl_bo(struct xe_tlb_inval *tlb_inval,
+ struct xe_page_reclaim_list *prl,
+ struct xe_tlb_inval_fence *fence)
+{
+ struct xe_gt *gt = container_of(tlb_inval, struct xe_gt, tlb_inval);
+ struct xe_tile *tile = gt_to_tile(gt);
+ /* (+1) for NULL page_reclaim_entry to indicate end of list */
+ int prl_size = min(prl->num_entries + 1, XE_PAGE_RECLAIM_MAX_ENTRIES) *
+ sizeof(struct xe_guc_page_reclaim_entry);
+ struct drm_suballoc *prl_sa;
+
+ /* Maximum size of PRL is 1 4K-page */
+ prl_sa = __xe_sa_bo_new(tile->mem.reclaim_pool,
+ prl_size, GFP_ATOMIC);
+ if (IS_ERR(prl_sa))
+ return prl_sa;
+
+ memcpy(xe_sa_bo_cpu_addr(prl_sa), prl->entries,
+ prl_size);
+ xe_sa_bo_flush_write(prl_sa);
+ /* Queue up sa_bo_free on tlb invalidation fence signal */
+ xe_sa_bo_free(prl_sa, &fence->base);
+
+ return prl_sa;
+}
/**
* xe_page_reclaim_list_invalidate() - Mark a PRL as invalid
diff --git a/drivers/gpu/drm/xe/xe_page_reclaim.h b/drivers/gpu/drm/xe/xe_page_reclaim.h
index 93f19fe6d146..f5f07e2e114f 100644
--- a/drivers/gpu/drm/xe/xe_page_reclaim.h
+++ b/drivers/gpu/drm/xe/xe_page_reclaim.h
@@ -16,6 +16,9 @@
#define XE_PAGE_RECLAIM_MAX_ENTRIES 512
#define XE_PAGE_RECLAIM_LIST_MAX_SIZE SZ_4K
+struct xe_tlb_inval;
+struct xe_tlb_inval_fence;
+
struct xe_guc_page_reclaim_entry {
u64 qw;
/* valid reclaim entry bit */
@@ -65,6 +68,9 @@ static inline bool xe_page_reclaim_list_valid(struct xe_page_reclaim_list *prl)
prl->num_entries != XE_PAGE_RECLAIM_INVALID_LIST;
}
+struct drm_suballoc *xe_page_reclaim_create_prl_bo(struct xe_tlb_inval *tlb_inval,
+ struct xe_page_reclaim_list *prl,
+ struct xe_tlb_inval_fence *fence);
void xe_page_reclaim_list_invalidate(struct xe_page_reclaim_list *prl);
void xe_page_reclaim_list_init(struct xe_page_reclaim_list *prl);
int xe_page_reclaim_list_alloc_entries(struct xe_page_reclaim_list *prl);
diff --git a/drivers/gpu/drm/xe/xe_tile.c b/drivers/gpu/drm/xe/xe_tile.c
index 4f4f9a5c43af..63c060c2ea5c 100644
--- a/drivers/gpu/drm/xe/xe_tile.c
+++ b/drivers/gpu/drm/xe/xe_tile.c
@@ -209,6 +209,11 @@ int xe_tile_init(struct xe_tile *tile)
if (IS_ERR(tile->mem.kernel_bb_pool))
return PTR_ERR(tile->mem.kernel_bb_pool);
+ /* Optimistically anticipate at most 256 TLB fences with PRL */
+ tile->mem.reclaim_pool = xe_sa_bo_manager_init(tile, SZ_1M, XE_PAGE_RECLAIM_LIST_MAX_SIZE);
+ if (IS_ERR(tile->mem.reclaim_pool))
+ return PTR_ERR(tile->mem.reclaim_pool);
+
return 0;
}
void xe_tile_migrate_wait(struct xe_tile *tile)
diff --git a/drivers/gpu/drm/xe/xe_tlb_inval_job.c b/drivers/gpu/drm/xe/xe_tlb_inval_job.c
index 1ae0dec2cf31..78e39a4fb264 100644
--- a/drivers/gpu/drm/xe/xe_tlb_inval_job.c
+++ b/drivers/gpu/drm/xe/xe_tlb_inval_job.c
@@ -24,6 +24,8 @@ struct xe_tlb_inval_job {
struct xe_exec_queue *q;
/** @vm: VM which TLB invalidation is being issued for */
struct xe_vm *vm;
+ /** @prl: Embedded copy of page reclaim list */
+ struct xe_page_reclaim_list prl;
/** @refcount: ref count of this job */
struct kref refcount;
/**
@@ -47,6 +49,13 @@ static struct dma_fence *xe_tlb_inval_job_run(struct xe_dep_job *dep_job)
container_of(dep_job, typeof(*job), dep);
struct xe_tlb_inval_fence *ifence =
container_of(job->fence, typeof(*ifence), base);
+ struct drm_suballoc *prl_sa = NULL;
+
+ if (xe_page_reclaim_list_valid(&job->prl)) {
+ prl_sa = xe_page_reclaim_create_prl_bo(job->tlb_inval, &job->prl, ifence);
+ if (IS_ERR(prl_sa))
+ prl_sa = NULL; /* Indicate fall back PPC flush with NULL */
+ }
xe_tlb_inval_range(job->tlb_inval, ifence, job->start,
job->end, job->vm->usm.asid);
--
2.52.0
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v5 07/10] drm/xe: Prep page reclaim in tlb inval job
2025-12-10 1:45 [PATCH v5 00/10] Page Reclamation Support for Xe3p Platforms Brian Nguyen
` (5 preceding siblings ...)
2025-12-10 1:45 ` [PATCH v5 06/10] drm/xe: Suballocate BO for page reclaim Brian Nguyen
@ 2025-12-10 1:45 ` Brian Nguyen
2025-12-10 2:15 ` Matthew Brost
2025-12-10 1:45 ` [PATCH v5 08/10] drm/xe: Append page reclamation action to tlb inval Brian Nguyen
` (6 subsequent siblings)
13 siblings, 1 reply; 22+ messages in thread
From: Brian Nguyen @ 2025-12-10 1:45 UTC (permalink / raw)
To: intel-xe
Cc: tejas.upadhyay, matthew.brost, shuicheng.lin, stuart.summers,
Michal Wajdeczko
Use page reclaim list as indicator if page reclaim action is desired and
pass it to tlb inval fence to handle.
Job will need to maintain its own embedded copy to ensure lifetime of
PRL exist until job has run.
v2:
- Use xe variant of WARN_ON (Michal)
v3:
- Add comments for PRL tile handling and flush behavior with media.
(Matthew Brost)
Signed-off-by: Brian Nguyen <brian3.nguyen@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
drivers/gpu/drm/xe/xe_pt.c | 11 +++++++++++
drivers/gpu/drm/xe/xe_tlb_inval_job.c | 25 +++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_tlb_inval_job.h | 4 ++++
3 files changed, 40 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c
index 89802cc16b47..78e2f037f8e1 100644
--- a/drivers/gpu/drm/xe/xe_pt.c
+++ b/drivers/gpu/drm/xe/xe_pt.c
@@ -2512,6 +2512,17 @@ xe_pt_update_ops_run(struct xe_tile *tile, struct xe_vma_ops *vops)
goto kill_vm_tile1;
}
update.ijob = ijob;
+ /*
+ * Only add page reclaim for the primary GT. Media GT does not have
+ * any PPC to flush, so enabling the PPC flush bit for media is
+ * effectively a NOP and provides no performance benefit nor
+ * interfere with primary GT.
+ */
+ if (xe_page_reclaim_list_valid(&pt_update_ops->prl)) {
+ xe_tlb_inval_job_add_page_reclaim(ijob, &pt_update_ops->prl);
+ /* Release ref from alloc, job will now handle it */
+ xe_page_reclaim_list_invalidate(&pt_update_ops->prl);
+ }
if (tile->media_gt) {
dep_scheduler = to_dep_scheduler(q, tile->media_gt);
diff --git a/drivers/gpu/drm/xe/xe_tlb_inval_job.c b/drivers/gpu/drm/xe/xe_tlb_inval_job.c
index 78e39a4fb264..fc5b4a32a32d 100644
--- a/drivers/gpu/drm/xe/xe_tlb_inval_job.c
+++ b/drivers/gpu/drm/xe/xe_tlb_inval_job.c
@@ -7,7 +7,9 @@
#include "xe_dep_job_types.h"
#include "xe_dep_scheduler.h"
#include "xe_exec_queue.h"
+#include "xe_gt_printk.h"
#include "xe_gt_types.h"
+#include "xe_page_reclaim.h"
#include "xe_tlb_inval.h"
#include "xe_tlb_inval_job.h"
#include "xe_migrate.h"
@@ -116,6 +118,7 @@ xe_tlb_inval_job_create(struct xe_exec_queue *q, struct xe_tlb_inval *tlb_inval,
job->start = start;
job->end = end;
job->fence_armed = false;
+ xe_page_reclaim_list_init(&job->prl);
job->dep.ops = &dep_job_ops;
job->type = type;
kref_init(&job->refcount);
@@ -149,6 +152,25 @@ xe_tlb_inval_job_create(struct xe_exec_queue *q, struct xe_tlb_inval *tlb_inval,
return ERR_PTR(err);
}
+/**
+ * xe_tlb_inval_job_add_page_reclaim() - Embed PRL into a TLB job
+ * @job: TLB invalidation job that may trigger reclamation
+ * @prl: Page reclaim list populated during unbind
+ *
+ * Copies @prl into the job and takes an extra reference to the entry page so
+ * ownership can transfer to the TLB fence when the job is pushed.
+ */
+void xe_tlb_inval_job_add_page_reclaim(struct xe_tlb_inval_job *job,
+ struct xe_page_reclaim_list *prl)
+{
+ struct xe_device *xe = gt_to_xe(job->q->gt);
+
+ xe_gt_WARN_ON(job->q->gt, !xe->info.has_page_reclaim_hw_assist);
+ job->prl = *prl;
+ /* Pair with put in job_destroy */
+ xe_page_reclaim_entries_get(job->prl.entries);
+}
+
static void xe_tlb_inval_job_destroy(struct kref *ref)
{
struct xe_tlb_inval_job *job = container_of(ref, typeof(*job),
@@ -159,6 +181,9 @@ static void xe_tlb_inval_job_destroy(struct kref *ref)
struct xe_device *xe = gt_to_xe(q->gt);
struct xe_vm *vm = job->vm;
+ /* BO creation retains a copy (if used), so no longer needed */
+ xe_page_reclaim_entries_put(job->prl.entries);
+
if (!job->fence_armed)
kfree(ifence);
else
diff --git a/drivers/gpu/drm/xe/xe_tlb_inval_job.h b/drivers/gpu/drm/xe/xe_tlb_inval_job.h
index 4d6df1a6c6ca..03d6e21cd611 100644
--- a/drivers/gpu/drm/xe/xe_tlb_inval_job.h
+++ b/drivers/gpu/drm/xe/xe_tlb_inval_job.h
@@ -12,6 +12,7 @@ struct dma_fence;
struct xe_dep_scheduler;
struct xe_exec_queue;
struct xe_migrate;
+struct xe_page_reclaim_list;
struct xe_tlb_inval;
struct xe_tlb_inval_job;
struct xe_vm;
@@ -21,6 +22,9 @@ xe_tlb_inval_job_create(struct xe_exec_queue *q, struct xe_tlb_inval *tlb_inval,
struct xe_dep_scheduler *dep_scheduler,
struct xe_vm *vm, u64 start, u64 end, int type);
+void xe_tlb_inval_job_add_page_reclaim(struct xe_tlb_inval_job *job,
+ struct xe_page_reclaim_list *prl);
+
int xe_tlb_inval_job_alloc_dep(struct xe_tlb_inval_job *job);
struct dma_fence *xe_tlb_inval_job_push(struct xe_tlb_inval_job *job,
--
2.52.0
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v5 08/10] drm/xe: Append page reclamation action to tlb inval
2025-12-10 1:45 [PATCH v5 00/10] Page Reclamation Support for Xe3p Platforms Brian Nguyen
` (6 preceding siblings ...)
2025-12-10 1:45 ` [PATCH v5 07/10] drm/xe: Prep page reclaim in tlb inval job Brian Nguyen
@ 2025-12-10 1:45 ` Brian Nguyen
2025-12-10 1:45 ` [PATCH v5 09/10] drm/xe: Optimize flushing of L2$ by skipping unnecessary page reclaim Brian Nguyen
` (5 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Brian Nguyen @ 2025-12-10 1:45 UTC (permalink / raw)
To: intel-xe; +Cc: tejas.upadhyay, matthew.brost, shuicheng.lin, stuart.summers
Add page reclamation action to tlb inval backend. The page reclamation
action is paired with range tlb invalidations so both are issued at the
same time.
Page reclamation will issue the TLB invalidation with an invalid seqno
and a H2G page reclamation action with the fence's corresponding seqno
and handle the fence accordingly on page reclaim action done handler.
If page reclamation fails, tlb timeout handler will be responsible for
signalling fence and cleaning up.
v2:
- add send_page_reclaim to patch.
- Remove flush_cache and use prl_sa pointer to determine PPC flush
instead of explicit bool. Add NULL as fallback for others. (Matthew B)
v3:
- Add comments for flush_cache with media.
Signed-off-by: Brian Nguyen <brian3.nguyen@intel.com>
Suggested-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
---
drivers/gpu/drm/xe/xe_guc_tlb_inval.c | 30 ++++++++++++++++++++-----
drivers/gpu/drm/xe/xe_tlb_inval.c | 7 +++---
drivers/gpu/drm/xe/xe_tlb_inval.h | 2 +-
drivers/gpu/drm/xe/xe_tlb_inval_job.c | 2 +-
drivers/gpu/drm/xe/xe_tlb_inval_types.h | 4 +++-
drivers/gpu/drm/xe/xe_vm.c | 4 ++--
6 files changed, 36 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_guc_tlb_inval.c b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
index 37ac943cb10f..6532a88d51e2 100644
--- a/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
+++ b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
@@ -13,6 +13,7 @@
#include "xe_guc_tlb_inval.h"
#include "xe_force_wake.h"
#include "xe_mmio.h"
+#include "xe_sa.h"
#include "xe_tlb_inval.h"
#include "regs/xe_guc_regs.h"
@@ -93,6 +94,20 @@ static int send_tlb_inval_ggtt(struct xe_tlb_inval *tlb_inval, u32 seqno)
return -ECANCELED;
}
+static int send_page_reclaim(struct xe_guc *guc, u32 seqno,
+ u64 gpu_addr)
+{
+ u32 action[] = {
+ XE_GUC_ACTION_PAGE_RECLAMATION,
+ seqno,
+ lower_32_bits(gpu_addr),
+ upper_32_bits(gpu_addr),
+ };
+
+ return xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action),
+ G2H_LEN_DW_PAGE_RECLAMATION, 1);
+}
+
/*
* Ensure that roundup_pow_of_two(length) doesn't overflow.
* Note that roundup_pow_of_two() operates on unsigned long,
@@ -101,20 +116,21 @@ static int send_tlb_inval_ggtt(struct xe_tlb_inval *tlb_inval, u32 seqno)
#define MAX_RANGE_TLB_INVALIDATION_LENGTH (rounddown_pow_of_two(ULONG_MAX))
static int send_tlb_inval_ppgtt(struct xe_tlb_inval *tlb_inval, u32 seqno,
- u64 start, u64 end, u32 asid)
+ u64 start, u64 end, u32 asid,
+ struct drm_suballoc *prl_sa)
{
#define MAX_TLB_INVALIDATION_LEN 7
struct xe_guc *guc = tlb_inval->private;
struct xe_gt *gt = guc_to_gt(guc);
u32 action[MAX_TLB_INVALIDATION_LEN];
u64 length = end - start;
- int len = 0;
+ int len = 0, err;
if (guc_to_xe(guc)->info.force_execlist)
return -ECANCELED;
action[len++] = XE_GUC_ACTION_TLB_INVALIDATION;
- action[len++] = seqno;
+ action[len++] = !prl_sa ? seqno : TLB_INVALIDATION_SEQNO_INVALID;
if (!gt_to_xe(gt)->info.has_range_tlb_inval ||
length > MAX_RANGE_TLB_INVALIDATION_LENGTH) {
action[len++] = MAKE_INVAL_OP(XE_GUC_TLB_INVAL_FULL);
@@ -155,7 +171,8 @@ static int send_tlb_inval_ppgtt(struct xe_tlb_inval *tlb_inval, u32 seqno,
ilog2(SZ_2M) + 1)));
xe_gt_assert(gt, IS_ALIGNED(start, length));
- action[len++] = MAKE_INVAL_OP_FLUSH(XE_GUC_TLB_INVAL_PAGE_SELECTIVE, true);
+ /* Flush on NULL case, Media is not required to modify flush due to no PPC so NOP */
+ action[len++] = MAKE_INVAL_OP_FLUSH(XE_GUC_TLB_INVAL_PAGE_SELECTIVE, !prl_sa);
action[len++] = asid;
action[len++] = lower_32_bits(start);
action[len++] = upper_32_bits(start);
@@ -164,7 +181,10 @@ static int send_tlb_inval_ppgtt(struct xe_tlb_inval *tlb_inval, u32 seqno,
xe_gt_assert(gt, len <= MAX_TLB_INVALIDATION_LEN);
- return send_tlb_inval(guc, action, len);
+ err = send_tlb_inval(guc, action, len);
+ if (!err && prl_sa)
+ err = send_page_reclaim(guc, seqno, xe_sa_bo_gpu_addr(prl_sa));
+ return err;
}
static bool tlb_inval_initialized(struct xe_tlb_inval *tlb_inval)
diff --git a/drivers/gpu/drm/xe/xe_tlb_inval.c b/drivers/gpu/drm/xe/xe_tlb_inval.c
index a122fbb9fc4a..dec042248164 100644
--- a/drivers/gpu/drm/xe/xe_tlb_inval.c
+++ b/drivers/gpu/drm/xe/xe_tlb_inval.c
@@ -313,6 +313,7 @@ int xe_tlb_inval_ggtt(struct xe_tlb_inval *tlb_inval)
* @start: start address
* @end: end address
* @asid: address space id
+ * @prl_sa: suballocation of page reclaim list if used, NULL indicates PPC flush
*
* Issue a range based TLB invalidation if supported, if not fallback to a full
* TLB invalidation. Completion of TLB is asynchronous and caller can use
@@ -322,10 +323,10 @@ int xe_tlb_inval_ggtt(struct xe_tlb_inval *tlb_inval)
*/
int xe_tlb_inval_range(struct xe_tlb_inval *tlb_inval,
struct xe_tlb_inval_fence *fence, u64 start, u64 end,
- u32 asid)
+ u32 asid, struct drm_suballoc *prl_sa)
{
return xe_tlb_inval_issue(tlb_inval, fence, tlb_inval->ops->ppgtt,
- start, end, asid);
+ start, end, asid, prl_sa);
}
/**
@@ -341,7 +342,7 @@ void xe_tlb_inval_vm(struct xe_tlb_inval *tlb_inval, struct xe_vm *vm)
u64 range = 1ull << vm->xe->info.va_bits;
xe_tlb_inval_fence_init(tlb_inval, &fence, true);
- xe_tlb_inval_range(tlb_inval, &fence, 0, range, vm->usm.asid);
+ xe_tlb_inval_range(tlb_inval, &fence, 0, range, vm->usm.asid, NULL);
xe_tlb_inval_fence_wait(&fence);
}
diff --git a/drivers/gpu/drm/xe/xe_tlb_inval.h b/drivers/gpu/drm/xe/xe_tlb_inval.h
index 05614915463a..858d0690f995 100644
--- a/drivers/gpu/drm/xe/xe_tlb_inval.h
+++ b/drivers/gpu/drm/xe/xe_tlb_inval.h
@@ -23,7 +23,7 @@ int xe_tlb_inval_ggtt(struct xe_tlb_inval *tlb_inval);
void xe_tlb_inval_vm(struct xe_tlb_inval *tlb_inval, struct xe_vm *vm);
int xe_tlb_inval_range(struct xe_tlb_inval *tlb_inval,
struct xe_tlb_inval_fence *fence,
- u64 start, u64 end, u32 asid);
+ u64 start, u64 end, u32 asid, struct drm_suballoc *prl_sa);
void xe_tlb_inval_fence_init(struct xe_tlb_inval *tlb_inval,
struct xe_tlb_inval_fence *fence,
diff --git a/drivers/gpu/drm/xe/xe_tlb_inval_job.c b/drivers/gpu/drm/xe/xe_tlb_inval_job.c
index fc5b4a32a32d..6a7bd6315797 100644
--- a/drivers/gpu/drm/xe/xe_tlb_inval_job.c
+++ b/drivers/gpu/drm/xe/xe_tlb_inval_job.c
@@ -60,7 +60,7 @@ static struct dma_fence *xe_tlb_inval_job_run(struct xe_dep_job *dep_job)
}
xe_tlb_inval_range(job->tlb_inval, ifence, job->start,
- job->end, job->vm->usm.asid);
+ job->end, job->vm->usm.asid, prl_sa);
return job->fence;
}
diff --git a/drivers/gpu/drm/xe/xe_tlb_inval_types.h b/drivers/gpu/drm/xe/xe_tlb_inval_types.h
index 7a6967ce3b76..48d1503e8460 100644
--- a/drivers/gpu/drm/xe/xe_tlb_inval_types.h
+++ b/drivers/gpu/drm/xe/xe_tlb_inval_types.h
@@ -9,6 +9,7 @@
#include <linux/workqueue.h>
#include <linux/dma-fence.h>
+struct drm_suballoc;
struct xe_tlb_inval;
/** struct xe_tlb_inval_ops - TLB invalidation ops (backend) */
@@ -40,12 +41,13 @@ struct xe_tlb_inval_ops {
* @start: Start address
* @end: End address
* @asid: Address space ID
+ * @prl_sa: Suballocation for page reclaim list
*
* Return 0 on success, -ECANCELED if backend is mid-reset, error on
* failure
*/
int (*ppgtt)(struct xe_tlb_inval *tlb_inval, u32 seqno, u64 start,
- u64 end, u32 asid);
+ u64 end, u32 asid, struct drm_suballoc *prl_sa);
/**
* @initialized: Backend is initialized
diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
index c2012d20faa6..bd787aae4248 100644
--- a/drivers/gpu/drm/xe/xe_vm.c
+++ b/drivers/gpu/drm/xe/xe_vm.c
@@ -3928,7 +3928,7 @@ int xe_vm_range_tilemask_tlb_inval(struct xe_vm *vm, u64 start,
err = xe_tlb_inval_range(&tile->primary_gt->tlb_inval,
&fence[fence_id], start, end,
- vm->usm.asid);
+ vm->usm.asid, NULL);
if (err)
goto wait;
++fence_id;
@@ -3941,7 +3941,7 @@ int xe_vm_range_tilemask_tlb_inval(struct xe_vm *vm, u64 start,
err = xe_tlb_inval_range(&tile->media_gt->tlb_inval,
&fence[fence_id], start, end,
- vm->usm.asid);
+ vm->usm.asid, NULL);
if (err)
goto wait;
++fence_id;
--
2.52.0
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v5 09/10] drm/xe: Optimize flushing of L2$ by skipping unnecessary page reclaim
2025-12-10 1:45 [PATCH v5 00/10] Page Reclamation Support for Xe3p Platforms Brian Nguyen
` (7 preceding siblings ...)
2025-12-10 1:45 ` [PATCH v5 08/10] drm/xe: Append page reclamation action to tlb inval Brian Nguyen
@ 2025-12-10 1:45 ` Brian Nguyen
2025-12-10 6:08 ` Upadhyay, Tejas
2025-12-10 1:45 ` [PATCH v5 10/10] drm/xe: Add debugfs support for page reclamation Brian Nguyen
` (4 subsequent siblings)
13 siblings, 1 reply; 22+ messages in thread
From: Brian Nguyen @ 2025-12-10 1:45 UTC (permalink / raw)
To: intel-xe
Cc: tejas.upadhyay, matthew.brost, shuicheng.lin, stuart.summers,
Matthew Auld
There are additional hardware managed L2$ flushing such as the
transient display. In those scenarios, page reclamation is
unnecessary resulting in redundant cacheline flushes, so skip
over those corresponding ranges.
v2:
- Elaborated on reasoning for page reclamation skip based on
Tejas's discussion. (Matthew A, Tejas)
v3:
- Removed MEDIA_IS_ON due to racy condition resulting in removal of
relevant registers and values. (Matthew A)
- Moved l3 policy access to xe_pat. (Matthew A)
v4:
- Updated comments based on previous change. (Tejas)
- Move back PAT index macros to xe_pat.c.
Signed-off-by: Brian Nguyen <brian3.nguyen@intel.com>
Cc: Tejas Upadhyay <tejas.upadhyay@intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/xe/xe_page_reclaim.c | 32 ++++++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_page_reclaim.h | 3 +++
drivers/gpu/drm/xe/xe_pat.c | 8 +++++++
drivers/gpu/drm/xe/xe_pat.h | 10 +++++++++
drivers/gpu/drm/xe/xe_pt.c | 3 ++-
5 files changed, 55 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/xe_page_reclaim.c b/drivers/gpu/drm/xe/xe_page_reclaim.c
index 0cce5ad2e33b..fd8c33761127 100644
--- a/drivers/gpu/drm/xe/xe_page_reclaim.c
+++ b/drivers/gpu/drm/xe/xe_page_reclaim.c
@@ -13,8 +13,40 @@
#include "regs/xe_gt_regs.h"
#include "xe_assert.h"
#include "xe_macros.h"
+#include "xe_mmio.h"
+#include "xe_pat.h"
#include "xe_sa.h"
#include "xe_tlb_inval_types.h"
+#include "xe_vm.h"
+
+/**
+ * xe_page_reclaim_skip() - Decide whether PRL should be skipped for a VMA
+ * @tile: Tile owning the VMA
+ * @vma: VMA under consideration
+ *
+ * PPC flushing may be handled by HW for specific PAT encodings.
+ * Skip PPC flushing/Page Reclaim for scenarios below due to redundant
+ * flushes.
+ * - pat_index is transient display (1)
+ *
+ * Return: true when page reclamation is unnecessary, false otherwise.
+ */
+bool xe_page_reclaim_skip(struct xe_tile *tile, struct xe_vma *vma)
+{
+ u8 l3_policy;
+
+ l3_policy = xe_pat_index_get_l3_policy(tile->xe, vma->attr.pat_index);
+
+ /*
+ * - l3_policy: 0=WB, 1=XD ("WB - Transient Display"), 3=UC
+ * Transient display flushes is taken care by HW, l3_policy = 1.
+ *
+ * HW will sequence these transient flushes at various sync points so
+ * any event of page reclamation will hit these sync points before
+ * page reclamation could execute.
+ */
+ return (l3_policy == XE_L3_POLICY_XD);
+}
/**
* xe_page_reclaim_create_prl_bo() - Back a PRL with a suballocated GGTT BO
diff --git a/drivers/gpu/drm/xe/xe_page_reclaim.h b/drivers/gpu/drm/xe/xe_page_reclaim.h
index f5f07e2e114f..0faea29f3964 100644
--- a/drivers/gpu/drm/xe/xe_page_reclaim.h
+++ b/drivers/gpu/drm/xe/xe_page_reclaim.h
@@ -18,6 +18,8 @@
struct xe_tlb_inval;
struct xe_tlb_inval_fence;
+struct xe_tile;
+struct xe_vma;
struct xe_guc_page_reclaim_entry {
u64 qw;
@@ -68,6 +70,7 @@ static inline bool xe_page_reclaim_list_valid(struct xe_page_reclaim_list *prl)
prl->num_entries != XE_PAGE_RECLAIM_INVALID_LIST;
}
+bool xe_page_reclaim_skip(struct xe_tile *tile, struct xe_vma *vma);
struct drm_suballoc *xe_page_reclaim_create_prl_bo(struct xe_tlb_inval *tlb_inval,
struct xe_page_reclaim_list *prl,
struct xe_tlb_inval_fence *fence);
diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c
index 6f48d34711a6..2c3375e0250b 100644
--- a/drivers/gpu/drm/xe/xe_pat.c
+++ b/drivers/gpu/drm/xe/xe_pat.c
@@ -9,6 +9,7 @@
#include <generated/xe_wa_oob.h>
+#include "regs/xe_gt_regs.h"
#include "regs/xe_reg_defs.h"
#include "xe_assert.h"
#include "xe_device.h"
@@ -231,6 +232,13 @@ bool xe_pat_index_get_comp_en(struct xe_device *xe, u16 pat_index)
return !!(xe->pat.table[pat_index].value & XE2_COMP_EN);
}
+u16 xe_pat_index_get_l3_policy(struct xe_device *xe, u16 pat_index)
+{
+ WARN_ON(pat_index >= xe->pat.n_entries);
+
+ return REG_FIELD_GET(XE2_L3_POLICY, xe->pat.table[pat_index].value);
+}
+
static void program_pat(struct xe_gt *gt, const struct xe_pat_table_entry table[],
int n_entries)
{
diff --git a/drivers/gpu/drm/xe/xe_pat.h b/drivers/gpu/drm/xe/xe_pat.h
index 5749a488d9a9..d5dadfb7f924 100644
--- a/drivers/gpu/drm/xe/xe_pat.h
+++ b/drivers/gpu/drm/xe/xe_pat.h
@@ -69,4 +69,14 @@ u16 xe_pat_index_get_coh_mode(struct xe_device *xe, u16 pat_index);
*/
bool xe_pat_index_get_comp_en(struct xe_device *xe, u16 pat_index);
+#define XE_L3_POLICY_WB 0 /* Write-back */
+#define XE_L3_POLICY_XD 1 /* WB - Transient Display */
+#define XE_L3_POLICY_UC 3 /* Uncached */
+/**
+ * xe_pat_index_get_l3_policy - Extract the L3 policy for the given pat_index.
+ * @xe: xe device
+ * @pat_index: The pat_index to query
+ */
+u16 xe_pat_index_get_l3_policy(struct xe_device *xe, u16 pat_index);
+
#endif
diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c
index 78e2f037f8e1..43426979b164 100644
--- a/drivers/gpu/drm/xe/xe_pt.c
+++ b/drivers/gpu/drm/xe/xe_pt.c
@@ -2030,7 +2030,8 @@ static int unbind_op_prepare(struct xe_tile *tile,
xe_page_reclaim_list_alloc_entries(&pt_update_ops->prl);
/* Page reclaim may not be needed due to other features, so skip the corresponding VMA */
- pt_op->prl = (xe_page_reclaim_list_valid(&pt_update_ops->prl)) ? &pt_update_ops->prl : NULL;
+ pt_op->prl = (xe_page_reclaim_list_valid(&pt_update_ops->prl) &&
+ !xe_page_reclaim_skip(tile, vma)) ? &pt_update_ops->prl : NULL;
err = vma_reserve_fences(tile_to_xe(tile), vma);
if (err)
--
2.52.0
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v5 10/10] drm/xe: Add debugfs support for page reclamation
2025-12-10 1:45 [PATCH v5 00/10] Page Reclamation Support for Xe3p Platforms Brian Nguyen
` (8 preceding siblings ...)
2025-12-10 1:45 ` [PATCH v5 09/10] drm/xe: Optimize flushing of L2$ by skipping unnecessary page reclaim Brian Nguyen
@ 2025-12-10 1:45 ` Brian Nguyen
2025-12-11 5:50 ` ✗ CI.checkpatch: warning for Page Reclamation Support for Xe3p Platforms (rev6) Patchwork
` (3 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Brian Nguyen @ 2025-12-10 1:45 UTC (permalink / raw)
To: intel-xe
Cc: tejas.upadhyay, matthew.brost, shuicheng.lin, stuart.summers,
Michal Wajdeczko
Allow for runtime modification to page reclamation feature through
debugfs configuration. This parameter will only take effect if the
platform supports the page reclamation feature by default.
v2:
- Minor comment tweaks. (Shuicheng)
- Convert to kstrtobool_from_user. (Michal)
- Only expose page reclaim file if page reclaim flag
initially supported and with that, remove
xe_match_desc usage. (Michal)
Signed-off-by: Brian Nguyen <brian3.nguyen@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Shuicheng Lin <shuicheng.lin@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
drivers/gpu/drm/xe/xe_debugfs.c | 41 +++++++++++++++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_debugfs.c b/drivers/gpu/drm/xe/xe_debugfs.c
index 0f8a96a05a8e..d24e5aca30ed 100644
--- a/drivers/gpu/drm/xe/xe_debugfs.c
+++ b/drivers/gpu/drm/xe/xe_debugfs.c
@@ -291,6 +291,39 @@ static const struct file_operations wedged_mode_fops = {
.write = wedged_mode_set,
};
+static ssize_t page_reclaim_hw_assist_show(struct file *f, char __user *ubuf,
+ size_t size, loff_t *pos)
+{
+ struct xe_device *xe = file_inode(f)->i_private;
+ char buf[8];
+ int len;
+
+ len = scnprintf(buf, sizeof(buf), "%d\n", xe->info.has_page_reclaim_hw_assist);
+ return simple_read_from_buffer(ubuf, size, pos, buf, len);
+}
+
+static ssize_t page_reclaim_hw_assist_set(struct file *f, const char __user *ubuf,
+ size_t size, loff_t *pos)
+{
+ struct xe_device *xe = file_inode(f)->i_private;
+ bool val;
+ ssize_t ret;
+
+ ret = kstrtobool_from_user(ubuf, size, &val);
+ if (ret)
+ return ret;
+
+ xe->info.has_page_reclaim_hw_assist = val;
+
+ return size;
+}
+
+static const struct file_operations page_reclaim_hw_assist_fops = {
+ .owner = THIS_MODULE,
+ .read = page_reclaim_hw_assist_show,
+ .write = page_reclaim_hw_assist_set,
+};
+
static ssize_t atomic_svm_timeslice_ms_show(struct file *f, char __user *ubuf,
size_t size, loff_t *pos)
{
@@ -396,6 +429,14 @@ void xe_debugfs_register(struct xe_device *xe)
debugfs_create_file("disable_late_binding", 0600, root, xe,
&disable_late_binding_fops);
+ /*
+ * Don't expose page reclaim configuration file if not supported by the
+ * hardware initially.
+ */
+ if (xe->info.has_page_reclaim_hw_assist)
+ debugfs_create_file("page_reclaim_hw_assist", 0600, root, xe,
+ &page_reclaim_hw_assist_fops);
+
man = ttm_manager_type(bdev, XE_PL_TT);
ttm_resource_manager_create_debugfs(man, root, "gtt_mm");
--
2.52.0
^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH v5 05/10] drm/xe: Create page reclaim list on unbind
2025-12-10 1:45 ` [PATCH v5 05/10] drm/xe: Create page reclaim list on unbind Brian Nguyen
@ 2025-12-10 2:13 ` Matthew Brost
0 siblings, 0 replies; 22+ messages in thread
From: Matthew Brost @ 2025-12-10 2:13 UTC (permalink / raw)
To: Brian Nguyen; +Cc: intel-xe, tejas.upadhyay, shuicheng.lin, stuart.summers
On Wed, Dec 10, 2025 at 09:45:23AM +0800, Brian Nguyen wrote:
> Page reclaim list (PRL) is preparation work for the page reclaim feature.
> The PRL is firstly owned by pt_update_ops and all other page reclaim
> operations will point back to this PRL. PRL generates its entries during
> the unbind page walker, updating the PRL.
>
> This PRL is restricted to a 4K page, so 512 page entries at most.
>
> v2:
> - Removed unused function. (Shuicheng)
> - Compacted warning checking, update commit message,
> spelling, etc. (Shuicheng, Matthew B)
> - Fix kernel docs
> - Moved PRL max entries overflow handling out from
> generate_reclaim_entry to caller (Shuicheng)
> - Add xe_page_reclaim_list_init for clarity. (Matthew B)
> - Modify xe_guc_page_reclaim_entry to use macros
> for greater flexbility. (Matthew B)
> - Add fallback for PTE outside of page reclaim supported
> 4K, 64K, 2M pages (Matthew B)
> - Invalidate PRL for early abort page walk.
> - Removed page reclaim related variables from tlb fence
> (Matthew Brost)
> - Remove error handling in *alloc_entries failure. (Matthew B)
>
> v3:
> - Fix NULL pointer dereference check.
> - Modify reclaim_entry to QW and bitfields accordingly. (Matthew B)
> - Add vm_dbg prints for PRL generation and invalidation. (Matthew B)
>
> v4:
> - s/GENMASK/GENMASK_ULL && s/BIT/BIT_ULL (CI)
>
> v5:
> - Addition of xe_page_reclaim_list_is_new() to avoid continuous
> allocation of PRL if consecutive VMAs cause a PRL invalidation.
> - Add xe_page_reclaim_list_valid() helpers for clarity. (Matthew B)
> - Move xe_page_reclaim_list_entries_put in
> xe_page_reclaim_list_invalidate.
>
The helpers looks much better, thanks!
> Signed-off-by: Brian Nguyen <brian3.nguyen@intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>
With that:
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
> Cc: Shuicheng Lin <shuicheng.lin@intel.com>
> ---
> drivers/gpu/drm/xe/Makefile | 1 +
> drivers/gpu/drm/xe/regs/xe_gtt_defs.h | 1 +
> drivers/gpu/drm/xe/xe_page_reclaim.c | 65 ++++++++++++++
> drivers/gpu/drm/xe/xe_page_reclaim.h | 96 ++++++++++++++++++++
> drivers/gpu/drm/xe/xe_pt.c | 123 +++++++++++++++++++++++++-
> drivers/gpu/drm/xe/xe_pt_types.h | 5 ++
> 6 files changed, 290 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/xe/xe_page_reclaim.c
> create mode 100644 drivers/gpu/drm/xe/xe_page_reclaim.h
>
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index 6ecba27d85f7..7f08b4cd91d6 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -95,6 +95,7 @@ xe-y += xe_bb.o \
> xe_oa.o \
> xe_observation.o \
> xe_pagefault.o \
> + xe_page_reclaim.o \
> xe_pat.o \
> xe_pci.o \
> xe_pcode.o \
> diff --git a/drivers/gpu/drm/xe/regs/xe_gtt_defs.h b/drivers/gpu/drm/xe/regs/xe_gtt_defs.h
> index 4389e5a76f89..4d83461e538b 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gtt_defs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gtt_defs.h
> @@ -9,6 +9,7 @@
> #define XELPG_GGTT_PTE_PAT0 BIT_ULL(52)
> #define XELPG_GGTT_PTE_PAT1 BIT_ULL(53)
>
> +#define XE_PTE_ADDR_MASK GENMASK_ULL(51, 12)
> #define GGTT_PTE_VFID GENMASK_ULL(11, 2)
>
> #define GUC_GGTT_TOP 0xFEE00000
> diff --git a/drivers/gpu/drm/xe/xe_page_reclaim.c b/drivers/gpu/drm/xe/xe_page_reclaim.c
> new file mode 100644
> index 000000000000..018d546fcf50
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_page_reclaim.c
> @@ -0,0 +1,65 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#include <linux/bitfield.h>
> +#include <linux/kref.h>
> +#include <linux/mm.h>
> +#include <linux/slab.h>
> +
> +#include "xe_page_reclaim.h"
> +
> +#include "regs/xe_gt_regs.h"
> +#include "xe_assert.h"
> +#include "xe_macros.h"
> +
> +/**
> + * xe_page_reclaim_list_invalidate() - Mark a PRL as invalid
> + * @prl: Page reclaim list to reset
> + *
> + * Clears the entries pointer and marks the list as invalid so
> + * future use knows PRL is unusable. It is expected that the entries
> + * have already been released.
> + */
> +void xe_page_reclaim_list_invalidate(struct xe_page_reclaim_list *prl)
> +{
> + xe_page_reclaim_entries_put(prl->entries);
> + prl->entries = NULL;
> + prl->num_entries = XE_PAGE_RECLAIM_INVALID_LIST;
> +}
> +
> +/**
> + * xe_page_reclaim_list_init() - Initialize a page reclaim list
> + * @prl: Page reclaim list to initialize
> + *
> + * NULLs both values in list to prepare on initalization.
> + */
> +void xe_page_reclaim_list_init(struct xe_page_reclaim_list *prl)
> +{
> + // xe_page_reclaim_list_invalidate(prl);
> + prl->entries = NULL;
> + prl->num_entries = 0;
> +}
> +
> +/**
> + * xe_page_reclaim_list_alloc_entries() - Allocate page reclaim list entries
> + * @prl: Page reclaim list to allocate entries for
> + *
> + * Allocate one 4K page for the PRL entries, otherwise assign prl->entries to NULL.
> + */
> +int xe_page_reclaim_list_alloc_entries(struct xe_page_reclaim_list *prl)
> +{
> + struct page *page;
> +
> + if (XE_WARN_ON(prl->entries))
> + return 0;
> +
> + page = alloc_page(GFP_KERNEL | __GFP_ZERO);
> + if (page) {
> + prl->entries = page_address(page);
> + prl->num_entries = 0;
> + }
> +
> + return page ? 0 : -ENOMEM;
> +}
> diff --git a/drivers/gpu/drm/xe/xe_page_reclaim.h b/drivers/gpu/drm/xe/xe_page_reclaim.h
> new file mode 100644
> index 000000000000..93f19fe6d146
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_page_reclaim.h
> @@ -0,0 +1,96 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#ifndef _XE_PAGE_RECLAIM_H_
> +#define _XE_PAGE_RECLAIM_H_
> +
> +#include <linux/kref.h>
> +#include <linux/mm.h>
> +#include <linux/slab.h>
> +#include <linux/types.h>
> +#include <linux/workqueue.h>
> +#include <linux/bits.h>
> +
> +#define XE_PAGE_RECLAIM_MAX_ENTRIES 512
> +#define XE_PAGE_RECLAIM_LIST_MAX_SIZE SZ_4K
> +
> +struct xe_guc_page_reclaim_entry {
> + u64 qw;
> +/* valid reclaim entry bit */
> +#define XE_PAGE_RECLAIM_VALID BIT_ULL(0)
> +/*
> + * offset order of page size to be reclaimed
> + * page_size = 1 << (XE_PTE_SHIFT + reclamation_size)
> + */
> +#define XE_PAGE_RECLAIM_SIZE GENMASK_ULL(6, 1)
> +#define XE_PAGE_RECLAIM_RSVD_0 GENMASK_ULL(11, 7)
> +/* lower 20 bits of the physical address */
> +#define XE_PAGE_RECLAIM_ADDR_LO GENMASK_ULL(31, 12)
> +/* upper 20 bits of the physical address */
> +#define XE_PAGE_RECLAIM_ADDR_HI GENMASK_ULL(51, 32)
> +#define XE_PAGE_RECLAIM_RSVD_1 GENMASK_ULL(63, 52)
> +} __packed;
> +
> +struct xe_page_reclaim_list {
> + /** @entries: array of page reclaim entries, page allocated */
> + struct xe_guc_page_reclaim_entry *entries;
> + /** @num_entries: number of entries */
> + int num_entries;
> +#define XE_PAGE_RECLAIM_INVALID_LIST -1
> +};
> +
> +/**
> + * xe_page_reclaim_list_is_new() - Check if PRL is new allocation
> + * @prl: Pointer to page reclaim list
> + *
> + * PRL indicates it hasn't been allocated through both values being NULL
> + */
> +static inline bool xe_page_reclaim_list_is_new(struct xe_page_reclaim_list *prl)
> +{
> + return prl->entries == NULL && prl->num_entries == 0;
> +}
> +
> +/**
> + * xe_page_reclaim_list_valid() - Check if the page reclaim list is valid
> + * @prl: Pointer to page reclaim list
> + *
> + * PRL uses the XE_PAGE_RECLAIM_INVALID_LIST to indicate that a PRL
> + * is unusable.
> + */
> +static inline bool xe_page_reclaim_list_valid(struct xe_page_reclaim_list *prl)
> +{
> + return !xe_page_reclaim_list_is_new(prl) &&
> + prl->num_entries != XE_PAGE_RECLAIM_INVALID_LIST;
> +}
> +
> +void xe_page_reclaim_list_invalidate(struct xe_page_reclaim_list *prl);
> +void xe_page_reclaim_list_init(struct xe_page_reclaim_list *prl);
> +int xe_page_reclaim_list_alloc_entries(struct xe_page_reclaim_list *prl);
> +/**
> + * xe_page_reclaim_entries_get() - Increment the reference count of page reclaim entries.
> + * @entries: Pointer to the array of page reclaim entries.
> + *
> + * This function increments the reference count of the backing page.
> + */
> +static inline void xe_page_reclaim_entries_get(struct xe_guc_page_reclaim_entry *entries)
> +{
> + if (entries)
> + get_page(virt_to_page(entries));
> +}
> +
> +/**
> + * xe_page_reclaim_entries_put() - Decrement the reference count of page reclaim entries.
> + * @entries: Pointer to the array of page reclaim entries.
> + *
> + * This function decrements the reference count of the backing page
> + * and frees it if the count reaches zero.
> + */
> +static inline void xe_page_reclaim_entries_put(struct xe_guc_page_reclaim_entry *entries)
> +{
> + if (entries)
> + put_page(virt_to_page(entries));
> +}
> +
> +#endif /* _XE_PAGE_RECLAIM_H_ */
> diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c
> index 884127b4d97d..89802cc16b47 100644
> --- a/drivers/gpu/drm/xe/xe_pt.c
> +++ b/drivers/gpu/drm/xe/xe_pt.c
> @@ -12,6 +12,7 @@
> #include "xe_exec_queue.h"
> #include "xe_gt.h"
> #include "xe_migrate.h"
> +#include "xe_page_reclaim.h"
> #include "xe_pt_types.h"
> #include "xe_pt_walk.h"
> #include "xe_res_cursor.h"
> @@ -1535,6 +1536,9 @@ struct xe_pt_stage_unbind_walk {
> /** @modified_end: Walk range start, modified like @modified_start. */
> u64 modified_end;
>
> + /** @prl: Backing pointer to page reclaim list in pt_update_ops */
> + struct xe_page_reclaim_list *prl;
> +
> /* Output */
> /* @wupd: Structure to track the page-table updates we're building */
> struct xe_walk_update wupd;
> @@ -1572,6 +1576,68 @@ static bool xe_pt_check_kill(u64 addr, u64 next, unsigned int level,
> return false;
> }
>
> +/* Huge 2MB leaf lives directly in a level-1 table and has no children */
> +static bool is_2m_pte(struct xe_pt *pte)
> +{
> + return pte->level == 1 && !pte->base.children;
> +}
> +
> +/* page_size = 2^(reclamation_size + XE_PTE_SHIFT) */
> +#define COMPUTE_RECLAIM_ADDRESS_MASK(page_size) \
> +({ \
> + BUILD_BUG_ON(!__builtin_constant_p(page_size)); \
> + ilog2(page_size) - XE_PTE_SHIFT; \
> +})
> +
> +static int generate_reclaim_entry(struct xe_tile *tile,
> + struct xe_page_reclaim_list *prl,
> + u64 pte, struct xe_pt *xe_child)
> +{
> + struct xe_guc_page_reclaim_entry *reclaim_entries = prl->entries;
> + u64 phys_page = (pte & XE_PTE_ADDR_MASK) >> XE_PTE_SHIFT;
> + int num_entries = prl->num_entries;
> + u32 reclamation_size;
> +
> + xe_tile_assert(tile, xe_child->level <= MAX_HUGEPTE_LEVEL);
> + xe_tile_assert(tile, reclaim_entries);
> + xe_tile_assert(tile, num_entries < XE_PAGE_RECLAIM_MAX_ENTRIES - 1);
> +
> + if (!xe_page_reclaim_list_valid(prl))
> + return -EINVAL;
> +
> + /**
> + * reclamation_size indicates the size of the page to be
> + * invalidated and flushed from non-coherent cache.
> + * Page size is computed as 2^(reclamation_size + XE_PTE_SHIFT) bytes.
> + * Only 4K, 64K (level 0), and 2M pages are supported by hardware for page reclaim
> + */
> + if (xe_child->level == 0 && !(pte & XE_PTE_PS64)) {
> + reclamation_size = COMPUTE_RECLAIM_ADDRESS_MASK(SZ_4K); /* reclamation_size = 0 */
> + } else if (xe_child->level == 0) {
> + reclamation_size = COMPUTE_RECLAIM_ADDRESS_MASK(SZ_64K); /* reclamation_size = 4 */
> + } else if (is_2m_pte(xe_child)) {
> + reclamation_size = COMPUTE_RECLAIM_ADDRESS_MASK(SZ_2M); /* reclamation_size = 9 */
> + } else {
> + xe_page_reclaim_list_invalidate(prl);
> + vm_dbg(&tile_to_xe(tile)->drm,
> + "PRL invalidate: unsupported PTE level=%u pte=%#llx\n",
> + xe_child->level, pte);
> + return -EINVAL;
> + }
> +
> + reclaim_entries[num_entries].qw =
> + FIELD_PREP(XE_PAGE_RECLAIM_VALID, 1) |
> + FIELD_PREP(XE_PAGE_RECLAIM_SIZE, reclamation_size) |
> + FIELD_PREP(XE_PAGE_RECLAIM_ADDR_LO, phys_page) |
> + FIELD_PREP(XE_PAGE_RECLAIM_ADDR_HI, phys_page >> 20);
> + prl->num_entries++;
> + vm_dbg(&tile_to_xe(tile)->drm,
> + "PRL add entry: level=%u pte=%#llx reclamation_size=%u prl_idx=%d\n",
> + xe_child->level, pte, reclamation_size, num_entries);
> +
> + return 0;
> +}
> +
> static int xe_pt_stage_unbind_entry(struct xe_ptw *parent, pgoff_t offset,
> unsigned int level, u64 addr, u64 next,
> struct xe_ptw **child,
> @@ -1579,11 +1645,48 @@ static int xe_pt_stage_unbind_entry(struct xe_ptw *parent, pgoff_t offset,
> struct xe_pt_walk *walk)
> {
> struct xe_pt *xe_child = container_of(*child, typeof(*xe_child), base);
> + struct xe_pt_stage_unbind_walk *xe_walk =
> + container_of(walk, typeof(*xe_walk), base);
> + struct xe_device *xe = tile_to_xe(xe_walk->tile);
>
> XE_WARN_ON(!*child);
> XE_WARN_ON(!level);
> + /* Check for leaf node */
> + if (xe_walk->prl && xe_page_reclaim_list_valid(xe_walk->prl) &&
> + !xe_child->base.children) {
> + struct iosys_map *leaf_map = &xe_child->bo->vmap;
> + pgoff_t first = xe_pt_offset(addr, 0, walk);
> + pgoff_t count = xe_pt_num_entries(addr, next, 0, walk);
> +
> + for (pgoff_t i = 0; i < count; i++) {
> + u64 pte = xe_map_rd(xe, leaf_map, (first + i) * sizeof(u64), u64);
> + int ret;
> +
> + /* Account for NULL terminated entry on end (-1) */
> + if (xe_walk->prl->num_entries < XE_PAGE_RECLAIM_MAX_ENTRIES - 1) {
> + ret = generate_reclaim_entry(xe_walk->tile, xe_walk->prl,
> + pte, xe_child);
> + if (ret)
> + break;
> + } else {
> + /* overflow, mark as invalid */
> + xe_page_reclaim_list_invalidate(xe_walk->prl);
> + vm_dbg(&xe->drm,
> + "PRL invalidate: overflow while adding pte=%#llx",
> + pte);
> + break;
> + }
> + }
> + }
>
> - xe_pt_check_kill(addr, next, level - 1, xe_child, action, walk);
> + /* If aborting page walk early, invalidate PRL since PTE may be dropped from this abort */
> + if (xe_pt_check_kill(addr, next, level - 1, xe_child, action, walk) &&
> + xe_walk->prl && level > 1 && xe_child->base.children && xe_child->num_live != 0) {
> + xe_page_reclaim_list_invalidate(xe_walk->prl);
> + vm_dbg(&xe->drm,
> + "PRL invalidate: kill at level=%u addr=%#llx next=%#llx num_live=%u\n",
> + level, addr, next, xe_child->num_live);
> + }
>
> return 0;
> }
> @@ -1654,6 +1757,8 @@ static unsigned int xe_pt_stage_unbind(struct xe_tile *tile,
> {
> u64 start = range ? xe_svm_range_start(range) : xe_vma_start(vma);
> u64 end = range ? xe_svm_range_end(range) : xe_vma_end(vma);
> + struct xe_vm_pgtable_update_op *pt_update_op =
> + container_of(entries, struct xe_vm_pgtable_update_op, entries[0]);
> struct xe_pt_stage_unbind_walk xe_walk = {
> .base = {
> .ops = &xe_pt_stage_unbind_ops,
> @@ -1665,6 +1770,7 @@ static unsigned int xe_pt_stage_unbind(struct xe_tile *tile,
> .modified_start = start,
> .modified_end = end,
> .wupd.entries = entries,
> + .prl = pt_update_op->prl,
> };
> struct xe_pt *pt = vm->pt_root[tile->id];
>
> @@ -1897,6 +2003,7 @@ static int unbind_op_prepare(struct xe_tile *tile,
> struct xe_vm_pgtable_update_ops *pt_update_ops,
> struct xe_vma *vma)
> {
> + struct xe_device *xe = tile_to_xe(tile);
> u32 current_op = pt_update_ops->current_op;
> struct xe_vm_pgtable_update_op *pt_op = &pt_update_ops->ops[current_op];
> int err;
> @@ -1914,6 +2021,16 @@ static int unbind_op_prepare(struct xe_tile *tile,
> pt_op->vma = vma;
> pt_op->bind = false;
> pt_op->rebind = false;
> + /*
> + * Maintain one PRL located in pt_update_ops that all others in unbind op reference.
> + * Ensure that PRL is allocated only once, and if invalidated, remains an invalidated PRL.
> + */
> + if (xe->info.has_page_reclaim_hw_assist &&
> + xe_page_reclaim_list_is_new(&pt_update_ops->prl))
> + xe_page_reclaim_list_alloc_entries(&pt_update_ops->prl);
> +
> + /* Page reclaim may not be needed due to other features, so skip the corresponding VMA */
> + pt_op->prl = (xe_page_reclaim_list_valid(&pt_update_ops->prl)) ? &pt_update_ops->prl : NULL;
>
> err = vma_reserve_fences(tile_to_xe(tile), vma);
> if (err)
> @@ -1979,6 +2096,7 @@ static int unbind_range_prepare(struct xe_vm *vm,
> pt_op->vma = XE_INVALID_VMA;
> pt_op->bind = false;
> pt_op->rebind = false;
> + pt_op->prl = NULL;
>
> pt_op->num_entries = xe_pt_stage_unbind(tile, vm, NULL, range,
> pt_op->entries);
> @@ -2096,6 +2214,7 @@ xe_pt_update_ops_init(struct xe_vm_pgtable_update_ops *pt_update_ops)
> init_llist_head(&pt_update_ops->deferred);
> pt_update_ops->start = ~0x0ull;
> pt_update_ops->last = 0x0ull;
> + xe_page_reclaim_list_init(&pt_update_ops->prl);
> }
>
> /**
> @@ -2518,6 +2637,8 @@ void xe_pt_update_ops_fini(struct xe_tile *tile, struct xe_vma_ops *vops)
> &vops->pt_update_ops[tile->id];
> int i;
>
> + xe_page_reclaim_entries_put(pt_update_ops->prl.entries);
> +
> lockdep_assert_held(&vops->vm->lock);
> xe_vm_assert_held(vops->vm);
>
> diff --git a/drivers/gpu/drm/xe/xe_pt_types.h b/drivers/gpu/drm/xe/xe_pt_types.h
> index 881f01e14db8..88fabf8e2655 100644
> --- a/drivers/gpu/drm/xe/xe_pt_types.h
> +++ b/drivers/gpu/drm/xe/xe_pt_types.h
> @@ -8,6 +8,7 @@
>
> #include <linux/types.h>
>
> +#include "xe_page_reclaim.h"
> #include "xe_pt_walk.h"
>
> struct xe_bo;
> @@ -79,6 +80,8 @@ struct xe_vm_pgtable_update_op {
> struct xe_vm_pgtable_update entries[XE_VM_MAX_LEVEL * 2 + 1];
> /** @vma: VMA for operation, operation not valid if NULL */
> struct xe_vma *vma;
> + /** @prl: Backing pointer to page reclaim list of pt_update_ops */
> + struct xe_page_reclaim_list *prl;
> /** @num_entries: number of entries for this update operation */
> u32 num_entries;
> /** @bind: is a bind */
> @@ -95,6 +98,8 @@ struct xe_vm_pgtable_update_ops {
> struct llist_head deferred;
> /** @q: exec queue for PT operations */
> struct xe_exec_queue *q;
> + /** @prl: embedded page reclaim list */
> + struct xe_page_reclaim_list prl;
> /** @start: start address of ops */
> u64 start;
> /** @last: last address of ops */
> --
> 2.52.0
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v5 07/10] drm/xe: Prep page reclaim in tlb inval job
2025-12-10 1:45 ` [PATCH v5 07/10] drm/xe: Prep page reclaim in tlb inval job Brian Nguyen
@ 2025-12-10 2:15 ` Matthew Brost
0 siblings, 0 replies; 22+ messages in thread
From: Matthew Brost @ 2025-12-10 2:15 UTC (permalink / raw)
To: Brian Nguyen
Cc: intel-xe, tejas.upadhyay, shuicheng.lin, stuart.summers,
Michal Wajdeczko
On Wed, Dec 10, 2025 at 09:45:25AM +0800, Brian Nguyen wrote:
> Use page reclaim list as indicator if page reclaim action is desired and
> pass it to tlb inval fence to handle.
>
> Job will need to maintain its own embedded copy to ensure lifetime of
> PRL exist until job has run.
>
> v2:
> - Use xe variant of WARN_ON (Michal)
>
> v3:
> - Add comments for PRL tile handling and flush behavior with media.
> (Matthew Brost)
>
> Signed-off-by: Brian Nguyen <brian3.nguyen@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
> ---
> drivers/gpu/drm/xe/xe_pt.c | 11 +++++++++++
> drivers/gpu/drm/xe/xe_tlb_inval_job.c | 25 +++++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_tlb_inval_job.h | 4 ++++
> 3 files changed, 40 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c
> index 89802cc16b47..78e2f037f8e1 100644
> --- a/drivers/gpu/drm/xe/xe_pt.c
> +++ b/drivers/gpu/drm/xe/xe_pt.c
> @@ -2512,6 +2512,17 @@ xe_pt_update_ops_run(struct xe_tile *tile, struct xe_vma_ops *vops)
> goto kill_vm_tile1;
> }
> update.ijob = ijob;
> + /*
> + * Only add page reclaim for the primary GT. Media GT does not have
> + * any PPC to flush, so enabling the PPC flush bit for media is
> + * effectively a NOP and provides no performance benefit nor
> + * interfere with primary GT.
> + */
> + if (xe_page_reclaim_list_valid(&pt_update_ops->prl)) {
> + xe_tlb_inval_job_add_page_reclaim(ijob, &pt_update_ops->prl);
> + /* Release ref from alloc, job will now handle it */
> + xe_page_reclaim_list_invalidate(&pt_update_ops->prl);
> + }
>
> if (tile->media_gt) {
> dep_scheduler = to_dep_scheduler(q, tile->media_gt);
> diff --git a/drivers/gpu/drm/xe/xe_tlb_inval_job.c b/drivers/gpu/drm/xe/xe_tlb_inval_job.c
> index 78e39a4fb264..fc5b4a32a32d 100644
> --- a/drivers/gpu/drm/xe/xe_tlb_inval_job.c
> +++ b/drivers/gpu/drm/xe/xe_tlb_inval_job.c
> @@ -7,7 +7,9 @@
> #include "xe_dep_job_types.h"
> #include "xe_dep_scheduler.h"
> #include "xe_exec_queue.h"
> +#include "xe_gt_printk.h"
> #include "xe_gt_types.h"
> +#include "xe_page_reclaim.h"
> #include "xe_tlb_inval.h"
> #include "xe_tlb_inval_job.h"
> #include "xe_migrate.h"
> @@ -116,6 +118,7 @@ xe_tlb_inval_job_create(struct xe_exec_queue *q, struct xe_tlb_inval *tlb_inval,
> job->start = start;
> job->end = end;
> job->fence_armed = false;
> + xe_page_reclaim_list_init(&job->prl);
> job->dep.ops = &dep_job_ops;
> job->type = type;
> kref_init(&job->refcount);
> @@ -149,6 +152,25 @@ xe_tlb_inval_job_create(struct xe_exec_queue *q, struct xe_tlb_inval *tlb_inval,
> return ERR_PTR(err);
> }
>
> +/**
> + * xe_tlb_inval_job_add_page_reclaim() - Embed PRL into a TLB job
> + * @job: TLB invalidation job that may trigger reclamation
> + * @prl: Page reclaim list populated during unbind
> + *
> + * Copies @prl into the job and takes an extra reference to the entry page so
> + * ownership can transfer to the TLB fence when the job is pushed.
> + */
> +void xe_tlb_inval_job_add_page_reclaim(struct xe_tlb_inval_job *job,
> + struct xe_page_reclaim_list *prl)
> +{
> + struct xe_device *xe = gt_to_xe(job->q->gt);
> +
> + xe_gt_WARN_ON(job->q->gt, !xe->info.has_page_reclaim_hw_assist);
> + job->prl = *prl;
> + /* Pair with put in job_destroy */
> + xe_page_reclaim_entries_get(job->prl.entries);
> +}
> +
> static void xe_tlb_inval_job_destroy(struct kref *ref)
> {
> struct xe_tlb_inval_job *job = container_of(ref, typeof(*job),
> @@ -159,6 +181,9 @@ static void xe_tlb_inval_job_destroy(struct kref *ref)
> struct xe_device *xe = gt_to_xe(q->gt);
> struct xe_vm *vm = job->vm;
>
> + /* BO creation retains a copy (if used), so no longer needed */
> + xe_page_reclaim_entries_put(job->prl.entries);
> +
> if (!job->fence_armed)
> kfree(ifence);
> else
> diff --git a/drivers/gpu/drm/xe/xe_tlb_inval_job.h b/drivers/gpu/drm/xe/xe_tlb_inval_job.h
> index 4d6df1a6c6ca..03d6e21cd611 100644
> --- a/drivers/gpu/drm/xe/xe_tlb_inval_job.h
> +++ b/drivers/gpu/drm/xe/xe_tlb_inval_job.h
> @@ -12,6 +12,7 @@ struct dma_fence;
> struct xe_dep_scheduler;
> struct xe_exec_queue;
> struct xe_migrate;
> +struct xe_page_reclaim_list;
> struct xe_tlb_inval;
> struct xe_tlb_inval_job;
> struct xe_vm;
> @@ -21,6 +22,9 @@ xe_tlb_inval_job_create(struct xe_exec_queue *q, struct xe_tlb_inval *tlb_inval,
> struct xe_dep_scheduler *dep_scheduler,
> struct xe_vm *vm, u64 start, u64 end, int type);
>
> +void xe_tlb_inval_job_add_page_reclaim(struct xe_tlb_inval_job *job,
> + struct xe_page_reclaim_list *prl);
> +
> int xe_tlb_inval_job_alloc_dep(struct xe_tlb_inval_job *job);
>
> struct dma_fence *xe_tlb_inval_job_push(struct xe_tlb_inval_job *job,
> --
> 2.52.0
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH v5 02/10] drm/xe/xe_tlb_inval: Modify fence interface to support PPC flush
2025-12-10 1:45 ` [PATCH v5 02/10] drm/xe/xe_tlb_inval: Modify fence interface to support PPC flush Brian Nguyen
@ 2025-12-10 5:32 ` Upadhyay, Tejas
0 siblings, 0 replies; 22+ messages in thread
From: Upadhyay, Tejas @ 2025-12-10 5:32 UTC (permalink / raw)
To: Nguyen, Brian3, intel-xe@lists.freedesktop.org
Cc: Brost, Matthew, Lin, Shuicheng, Summers, Stuart
> -----Original Message-----
> From: Nguyen, Brian3 <brian3.nguyen@intel.com>
> Sent: 10 December 2025 07:15
> To: intel-xe@lists.freedesktop.org
> Cc: Upadhyay, Tejas <tejas.upadhyay@intel.com>; Brost, Matthew
> <matthew.brost@intel.com>; Lin, Shuicheng <shuicheng.lin@intel.com>;
> Summers, Stuart <stuart.summers@intel.com>
> Subject: [PATCH v5 02/10] drm/xe/xe_tlb_inval: Modify fence interface to
> support PPC flush
>
> Allow tlb_invalidation to control when driver wants to flush the Private
> Physical Cache (PPC) as a process of the tlb invalidation process.
>
> Default behavior is still to always flush the PPC but driver now has the option
> to disable it.
>
> v2:
> - Revise commit/kernel doc descriptions. (Shuicheng)
> - Remove unused function. (Shuicheng)
> - Remove bool flush_cache parameter from fence,
> and various function inputs. (Matthew B)
>
> Signed-off-by: Brian Nguyen <brian3.nguyen@intel.com>
> Reviewed-by: Matthew Brost <matthew.brost@intel.com>
> Cc: Shuicheng Lin <shuicheng.lin@intel.com>
> ---
> drivers/gpu/drm/xe/xe_guc_tlb_inval.c | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> index 848d3493df10..37ac943cb10f 100644
> --- a/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> +++ b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> @@ -34,9 +34,12 @@ static int send_tlb_inval(struct xe_guc *guc, const u32
> *action, int len)
> G2H_LEN_DW_TLB_INVALIDATE, 1); }
>
> -#define MAKE_INVAL_OP(type) ((type <<
> XE_GUC_TLB_INVAL_TYPE_SHIFT) | \
> +#define MAKE_INVAL_OP_FLUSH(type, flush_cache) ((type <<
> XE_GUC_TLB_INVAL_TYPE_SHIFT) | \
> XE_GUC_TLB_INVAL_MODE_HEAVY <<
> XE_GUC_TLB_INVAL_MODE_SHIFT | \
> - XE_GUC_TLB_INVAL_FLUSH_CACHE)
> + (flush_cache ? \
> + XE_GUC_TLB_INVAL_FLUSH_CACHE : 0))
> +
LGTM,
Reviewed-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Tejas
> +#define MAKE_INVAL_OP(type) MAKE_INVAL_OP_FLUSH(type, true)
>
> static int send_tlb_inval_all(struct xe_tlb_inval *tlb_inval, u32 seqno) { @@ -
> 152,7 +155,7 @@ static int send_tlb_inval_ppgtt(struct xe_tlb_inval
> *tlb_inval, u32 seqno,
> ilog2(SZ_2M) + 1)));
> xe_gt_assert(gt, IS_ALIGNED(start, length));
>
> - action[len++] =
> MAKE_INVAL_OP(XE_GUC_TLB_INVAL_PAGE_SELECTIVE);
> + action[len++] =
> MAKE_INVAL_OP_FLUSH(XE_GUC_TLB_INVAL_PAGE_SELECTIVE,
> +true);
> action[len++] = asid;
> action[len++] = lower_32_bits(start);
> action[len++] = upper_32_bits(start);
> --
> 2.52.0
^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH v5 09/10] drm/xe: Optimize flushing of L2$ by skipping unnecessary page reclaim
2025-12-10 1:45 ` [PATCH v5 09/10] drm/xe: Optimize flushing of L2$ by skipping unnecessary page reclaim Brian Nguyen
@ 2025-12-10 6:08 ` Upadhyay, Tejas
2025-12-10 6:19 ` Matthew Brost
0 siblings, 1 reply; 22+ messages in thread
From: Upadhyay, Tejas @ 2025-12-10 6:08 UTC (permalink / raw)
To: Nguyen, Brian3, intel-xe@lists.freedesktop.org
Cc: Brost, Matthew, Lin, Shuicheng, Summers, Stuart, Auld, Matthew
> -----Original Message-----
> From: Nguyen, Brian3 <brian3.nguyen@intel.com>
> Sent: 10 December 2025 07:15
> To: intel-xe@lists.freedesktop.org
> Cc: Upadhyay, Tejas <tejas.upadhyay@intel.com>; Brost, Matthew
> <matthew.brost@intel.com>; Lin, Shuicheng <shuicheng.lin@intel.com>;
> Summers, Stuart <stuart.summers@intel.com>; Auld, Matthew
> <matthew.auld@intel.com>
> Subject: [PATCH v5 09/10] drm/xe: Optimize flushing of L2$ by skipping
> unnecessary page reclaim
>
> There are additional hardware managed L2$ flushing such as the transient
> display. In those scenarios, page reclamation is unnecessary resulting in
> redundant cacheline flushes, so skip over those corresponding ranges.
>
> v2:
> - Elaborated on reasoning for page reclamation skip based on
> Tejas's discussion. (Matthew A, Tejas)
>
> v3:
> - Removed MEDIA_IS_ON due to racy condition resulting in removal of
> relevant registers and values. (Matthew A)
> - Moved l3 policy access to xe_pat. (Matthew A)
>
> v4:
> - Updated comments based on previous change. (Tejas)
> - Move back PAT index macros to xe_pat.c.
>
> Signed-off-by: Brian Nguyen <brian3.nguyen@intel.com>
> Cc: Tejas Upadhyay <tejas.upadhyay@intel.com>
> Cc: Matthew Auld <matthew.auld@intel.com>
> ---
> drivers/gpu/drm/xe/xe_page_reclaim.c | 32
> ++++++++++++++++++++++++++++ drivers/gpu/drm/xe/xe_page_reclaim.h
> | 3 +++
> drivers/gpu/drm/xe/xe_pat.c | 8 +++++++
> drivers/gpu/drm/xe/xe_pat.h | 10 +++++++++
> drivers/gpu/drm/xe/xe_pt.c | 3 ++-
> 5 files changed, 55 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_page_reclaim.c
> b/drivers/gpu/drm/xe/xe_page_reclaim.c
> index 0cce5ad2e33b..fd8c33761127 100644
> --- a/drivers/gpu/drm/xe/xe_page_reclaim.c
> +++ b/drivers/gpu/drm/xe/xe_page_reclaim.c
> @@ -13,8 +13,40 @@
> #include "regs/xe_gt_regs.h"
> #include "xe_assert.h"
> #include "xe_macros.h"
> +#include "xe_mmio.h"
> +#include "xe_pat.h"
> #include "xe_sa.h"
> #include "xe_tlb_inval_types.h"
> +#include "xe_vm.h"
> +
> +/**
> + * xe_page_reclaim_skip() - Decide whether PRL should be skipped for a
> +VMA
> + * @tile: Tile owning the VMA
> + * @vma: VMA under consideration
> + *
> + * PPC flushing may be handled by HW for specific PAT encodings.
> + * Skip PPC flushing/Page Reclaim for scenarios below due to redundant
> + * flushes.
> + * - pat_index is transient display (1)
> + *
> + * Return: true when page reclamation is unnecessary, false otherwise.
> + */
> +bool xe_page_reclaim_skip(struct xe_tile *tile, struct xe_vma *vma) {
> + u8 l3_policy;
> +
> + l3_policy = xe_pat_index_get_l3_policy(tile->xe, vma->attr.pat_index);
> +
> + /*
> + * - l3_policy: 0=WB, 1=XD ("WB - Transient Display"), 3=UC
> + * Transient display flushes is taken care by HW, l3_policy = 1.
> + *
> + * HW will sequence these transient flushes at various sync points so
> + * any event of page reclamation will hit these sync points before
> + * page reclamation could execute.
> + */
> + return (l3_policy == XE_L3_POLICY_XD); }
I think you do not want to skip anything here as far current HW capabilities concerned on upstream. Though normal flow of transient display flush by KMD driver will flush, you cant be sure and you need to flush full at page reclamation. The idea of skipping came because of HW capability to flush which is not there in any of upstream platforms. Probably we can drop this patch itself!
Tejas
>
> /**
> * xe_page_reclaim_create_prl_bo() - Back a PRL with a suballocated GGTT BO
> diff --git a/drivers/gpu/drm/xe/xe_page_reclaim.h
> b/drivers/gpu/drm/xe/xe_page_reclaim.h
> index f5f07e2e114f..0faea29f3964 100644
> --- a/drivers/gpu/drm/xe/xe_page_reclaim.h
> +++ b/drivers/gpu/drm/xe/xe_page_reclaim.h
> @@ -18,6 +18,8 @@
>
> struct xe_tlb_inval;
> struct xe_tlb_inval_fence;
> +struct xe_tile;
> +struct xe_vma;
>
> struct xe_guc_page_reclaim_entry {
> u64 qw;
> @@ -68,6 +70,7 @@ static inline bool xe_page_reclaim_list_valid(struct
> xe_page_reclaim_list *prl)
> prl->num_entries != XE_PAGE_RECLAIM_INVALID_LIST; }
>
> +bool xe_page_reclaim_skip(struct xe_tile *tile, struct xe_vma *vma);
> struct drm_suballoc *xe_page_reclaim_create_prl_bo(struct xe_tlb_inval
> *tlb_inval,
> struct xe_page_reclaim_list
> *prl,
> struct xe_tlb_inval_fence
> *fence); diff --git a/drivers/gpu/drm/xe/xe_pat.c
> b/drivers/gpu/drm/xe/xe_pat.c index 6f48d34711a6..2c3375e0250b
> 100644
> --- a/drivers/gpu/drm/xe/xe_pat.c
> +++ b/drivers/gpu/drm/xe/xe_pat.c
> @@ -9,6 +9,7 @@
>
> #include <generated/xe_wa_oob.h>
>
> +#include "regs/xe_gt_regs.h"
> #include "regs/xe_reg_defs.h"
> #include "xe_assert.h"
> #include "xe_device.h"
> @@ -231,6 +232,13 @@ bool xe_pat_index_get_comp_en(struct xe_device
> *xe, u16 pat_index)
> return !!(xe->pat.table[pat_index].value & XE2_COMP_EN); }
>
> +u16 xe_pat_index_get_l3_policy(struct xe_device *xe, u16 pat_index) {
> + WARN_ON(pat_index >= xe->pat.n_entries);
> +
> + return REG_FIELD_GET(XE2_L3_POLICY, xe-
> >pat.table[pat_index].value); }
> +
> static void program_pat(struct xe_gt *gt, const struct xe_pat_table_entry
> table[],
> int n_entries)
> {
> diff --git a/drivers/gpu/drm/xe/xe_pat.h b/drivers/gpu/drm/xe/xe_pat.h
> index 5749a488d9a9..d5dadfb7f924 100644
> --- a/drivers/gpu/drm/xe/xe_pat.h
> +++ b/drivers/gpu/drm/xe/xe_pat.h
> @@ -69,4 +69,14 @@ u16 xe_pat_index_get_coh_mode(struct xe_device
> *xe, u16 pat_index);
> */
> bool xe_pat_index_get_comp_en(struct xe_device *xe, u16 pat_index);
>
> +#define XE_L3_POLICY_WB 0 /* Write-back */
> +#define XE_L3_POLICY_XD 1 /* WB - Transient Display */
> +#define XE_L3_POLICY_UC 3 /* Uncached */
> +/**
> + * xe_pat_index_get_l3_policy - Extract the L3 policy for the given pat_index.
> + * @xe: xe device
> + * @pat_index: The pat_index to query
> + */
> +u16 xe_pat_index_get_l3_policy(struct xe_device *xe, u16 pat_index);
> +
> #endif
> diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c index
> 78e2f037f8e1..43426979b164 100644
> --- a/drivers/gpu/drm/xe/xe_pt.c
> +++ b/drivers/gpu/drm/xe/xe_pt.c
> @@ -2030,7 +2030,8 @@ static int unbind_op_prepare(struct xe_tile *tile,
> xe_page_reclaim_list_alloc_entries(&pt_update_ops->prl);
>
> /* Page reclaim may not be needed due to other features, so skip the
> corresponding VMA */
> - pt_op->prl = (xe_page_reclaim_list_valid(&pt_update_ops->prl)) ?
> &pt_update_ops->prl : NULL;
> + pt_op->prl = (xe_page_reclaim_list_valid(&pt_update_ops->prl) &&
> + !xe_page_reclaim_skip(tile, vma)) ? &pt_update_ops->prl :
> NULL;
>
> err = vma_reserve_fences(tile_to_xe(tile), vma);
> if (err)
> --
> 2.52.0
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v5 09/10] drm/xe: Optimize flushing of L2$ by skipping unnecessary page reclaim
2025-12-10 6:08 ` Upadhyay, Tejas
@ 2025-12-10 6:19 ` Matthew Brost
2025-12-10 6:49 ` Upadhyay, Tejas
0 siblings, 1 reply; 22+ messages in thread
From: Matthew Brost @ 2025-12-10 6:19 UTC (permalink / raw)
To: Upadhyay, Tejas
Cc: Nguyen, Brian3, intel-xe@lists.freedesktop.org, Lin, Shuicheng,
Summers, Stuart, Auld, Matthew
On Tue, Dec 09, 2025 at 11:08:16PM -0700, Upadhyay, Tejas wrote:
>
>
> > -----Original Message-----
> > From: Nguyen, Brian3 <brian3.nguyen@intel.com>
> > Sent: 10 December 2025 07:15
> > To: intel-xe@lists.freedesktop.org
> > Cc: Upadhyay, Tejas <tejas.upadhyay@intel.com>; Brost, Matthew
> > <matthew.brost@intel.com>; Lin, Shuicheng <shuicheng.lin@intel.com>;
> > Summers, Stuart <stuart.summers@intel.com>; Auld, Matthew
> > <matthew.auld@intel.com>
> > Subject: [PATCH v5 09/10] drm/xe: Optimize flushing of L2$ by skipping
> > unnecessary page reclaim
> >
> > There are additional hardware managed L2$ flushing such as the transient
> > display. In those scenarios, page reclamation is unnecessary resulting in
> > redundant cacheline flushes, so skip over those corresponding ranges.
> >
> > v2:
> > - Elaborated on reasoning for page reclamation skip based on
> > Tejas's discussion. (Matthew A, Tejas)
> >
> > v3:
> > - Removed MEDIA_IS_ON due to racy condition resulting in removal of
> > relevant registers and values. (Matthew A)
> > - Moved l3 policy access to xe_pat. (Matthew A)
> >
> > v4:
> > - Updated comments based on previous change. (Tejas)
> > - Move back PAT index macros to xe_pat.c.
> >
> > Signed-off-by: Brian Nguyen <brian3.nguyen@intel.com>
> > Cc: Tejas Upadhyay <tejas.upadhyay@intel.com>
> > Cc: Matthew Auld <matthew.auld@intel.com>
> > ---
> > drivers/gpu/drm/xe/xe_page_reclaim.c | 32
> > ++++++++++++++++++++++++++++ drivers/gpu/drm/xe/xe_page_reclaim.h
> > | 3 +++
> > drivers/gpu/drm/xe/xe_pat.c | 8 +++++++
> > drivers/gpu/drm/xe/xe_pat.h | 10 +++++++++
> > drivers/gpu/drm/xe/xe_pt.c | 3 ++-
> > 5 files changed, 55 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/xe/xe_page_reclaim.c
> > b/drivers/gpu/drm/xe/xe_page_reclaim.c
> > index 0cce5ad2e33b..fd8c33761127 100644
> > --- a/drivers/gpu/drm/xe/xe_page_reclaim.c
> > +++ b/drivers/gpu/drm/xe/xe_page_reclaim.c
> > @@ -13,8 +13,40 @@
> > #include "regs/xe_gt_regs.h"
> > #include "xe_assert.h"
> > #include "xe_macros.h"
> > +#include "xe_mmio.h"
> > +#include "xe_pat.h"
> > #include "xe_sa.h"
> > #include "xe_tlb_inval_types.h"
> > +#include "xe_vm.h"
> > +
> > +/**
> > + * xe_page_reclaim_skip() - Decide whether PRL should be skipped for a
> > +VMA
> > + * @tile: Tile owning the VMA
> > + * @vma: VMA under consideration
> > + *
> > + * PPC flushing may be handled by HW for specific PAT encodings.
> > + * Skip PPC flushing/Page Reclaim for scenarios below due to redundant
> > + * flushes.
> > + * - pat_index is transient display (1)
> > + *
> > + * Return: true when page reclamation is unnecessary, false otherwise.
> > + */
> > +bool xe_page_reclaim_skip(struct xe_tile *tile, struct xe_vma *vma) {
> > + u8 l3_policy;
> > +
> > + l3_policy = xe_pat_index_get_l3_policy(tile->xe, vma->attr.pat_index);
> > +
> > + /*
> > + * - l3_policy: 0=WB, 1=XD ("WB - Transient Display"), 3=UC
> > + * Transient display flushes is taken care by HW, l3_policy = 1.
> > + *
> > + * HW will sequence these transient flushes at various sync points so
> > + * any event of page reclamation will hit these sync points before
> > + * page reclamation could execute.
> > + */
> > + return (l3_policy == XE_L3_POLICY_XD); }
>
> I think you do not want to skip anything here as far current HW capabilities concerned on upstream. Though normal flow of transient display flush by KMD driver will flush, you cant be sure and you need to flush full at page reclamation. The idea of skipping came because of HW capability to flush which is not there in any of upstream platforms. Probably we can drop this patch itself!
Well maybe (?) - tbh I haven't the spec on this skipping.
But if any upstream platform correctly reports a cap, future platforms
report the different cap, completely reasonable to merge now.
Hoe about a bspec link in the commit...
e.g.
Bspec: <number>
So we can all get on the same page.
Matt
>
> Tejas
> >
> > /**
> > * xe_page_reclaim_create_prl_bo() - Back a PRL with a suballocated GGTT BO
> > diff --git a/drivers/gpu/drm/xe/xe_page_reclaim.h
> > b/drivers/gpu/drm/xe/xe_page_reclaim.h
> > index f5f07e2e114f..0faea29f3964 100644
> > --- a/drivers/gpu/drm/xe/xe_page_reclaim.h
> > +++ b/drivers/gpu/drm/xe/xe_page_reclaim.h
> > @@ -18,6 +18,8 @@
> >
> > struct xe_tlb_inval;
> > struct xe_tlb_inval_fence;
> > +struct xe_tile;
> > +struct xe_vma;
> >
> > struct xe_guc_page_reclaim_entry {
> > u64 qw;
> > @@ -68,6 +70,7 @@ static inline bool xe_page_reclaim_list_valid(struct
> > xe_page_reclaim_list *prl)
> > prl->num_entries != XE_PAGE_RECLAIM_INVALID_LIST; }
> >
> > +bool xe_page_reclaim_skip(struct xe_tile *tile, struct xe_vma *vma);
> > struct drm_suballoc *xe_page_reclaim_create_prl_bo(struct xe_tlb_inval
> > *tlb_inval,
> > struct xe_page_reclaim_list
> > *prl,
> > struct xe_tlb_inval_fence
> > *fence); diff --git a/drivers/gpu/drm/xe/xe_pat.c
> > b/drivers/gpu/drm/xe/xe_pat.c index 6f48d34711a6..2c3375e0250b
> > 100644
> > --- a/drivers/gpu/drm/xe/xe_pat.c
> > +++ b/drivers/gpu/drm/xe/xe_pat.c
> > @@ -9,6 +9,7 @@
> >
> > #include <generated/xe_wa_oob.h>
> >
> > +#include "regs/xe_gt_regs.h"
> > #include "regs/xe_reg_defs.h"
> > #include "xe_assert.h"
> > #include "xe_device.h"
> > @@ -231,6 +232,13 @@ bool xe_pat_index_get_comp_en(struct xe_device
> > *xe, u16 pat_index)
> > return !!(xe->pat.table[pat_index].value & XE2_COMP_EN); }
> >
> > +u16 xe_pat_index_get_l3_policy(struct xe_device *xe, u16 pat_index) {
> > + WARN_ON(pat_index >= xe->pat.n_entries);
> > +
> > + return REG_FIELD_GET(XE2_L3_POLICY, xe-
> > >pat.table[pat_index].value); }
> > +
> > static void program_pat(struct xe_gt *gt, const struct xe_pat_table_entry
> > table[],
> > int n_entries)
> > {
> > diff --git a/drivers/gpu/drm/xe/xe_pat.h b/drivers/gpu/drm/xe/xe_pat.h
> > index 5749a488d9a9..d5dadfb7f924 100644
> > --- a/drivers/gpu/drm/xe/xe_pat.h
> > +++ b/drivers/gpu/drm/xe/xe_pat.h
> > @@ -69,4 +69,14 @@ u16 xe_pat_index_get_coh_mode(struct xe_device
> > *xe, u16 pat_index);
> > */
> > bool xe_pat_index_get_comp_en(struct xe_device *xe, u16 pat_index);
> >
> > +#define XE_L3_POLICY_WB 0 /* Write-back */
> > +#define XE_L3_POLICY_XD 1 /* WB - Transient Display */
> > +#define XE_L3_POLICY_UC 3 /* Uncached */
> > +/**
> > + * xe_pat_index_get_l3_policy - Extract the L3 policy for the given pat_index.
> > + * @xe: xe device
> > + * @pat_index: The pat_index to query
> > + */
> > +u16 xe_pat_index_get_l3_policy(struct xe_device *xe, u16 pat_index);
> > +
> > #endif
> > diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c index
> > 78e2f037f8e1..43426979b164 100644
> > --- a/drivers/gpu/drm/xe/xe_pt.c
> > +++ b/drivers/gpu/drm/xe/xe_pt.c
> > @@ -2030,7 +2030,8 @@ static int unbind_op_prepare(struct xe_tile *tile,
> > xe_page_reclaim_list_alloc_entries(&pt_update_ops->prl);
> >
> > /* Page reclaim may not be needed due to other features, so skip the
> > corresponding VMA */
> > - pt_op->prl = (xe_page_reclaim_list_valid(&pt_update_ops->prl)) ?
> > &pt_update_ops->prl : NULL;
> > + pt_op->prl = (xe_page_reclaim_list_valid(&pt_update_ops->prl) &&
> > + !xe_page_reclaim_skip(tile, vma)) ? &pt_update_ops->prl :
> > NULL;
> >
> > err = vma_reserve_fences(tile_to_xe(tile), vma);
> > if (err)
> > --
> > 2.52.0
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH v5 09/10] drm/xe: Optimize flushing of L2$ by skipping unnecessary page reclaim
2025-12-10 6:19 ` Matthew Brost
@ 2025-12-10 6:49 ` Upadhyay, Tejas
0 siblings, 0 replies; 22+ messages in thread
From: Upadhyay, Tejas @ 2025-12-10 6:49 UTC (permalink / raw)
To: Brost, Matthew
Cc: Nguyen, Brian3, intel-xe@lists.freedesktop.org, Lin, Shuicheng,
Summers, Stuart, Auld, Matthew
> -----Original Message-----
> From: Brost, Matthew <matthew.brost@intel.com>
> Sent: 10 December 2025 11:49
> To: Upadhyay, Tejas <tejas.upadhyay@intel.com>
> Cc: Nguyen, Brian3 <brian3.nguyen@intel.com>; intel-
> xe@lists.freedesktop.org; Lin, Shuicheng <shuicheng.lin@intel.com>;
> Summers, Stuart <stuart.summers@intel.com>; Auld, Matthew
> <matthew.auld@intel.com>
> Subject: Re: [PATCH v5 09/10] drm/xe: Optimize flushing of L2$ by skipping
> unnecessary page reclaim
>
> On Tue, Dec 09, 2025 at 11:08:16PM -0700, Upadhyay, Tejas wrote:
> >
> >
> > > -----Original Message-----
> > > From: Nguyen, Brian3 <brian3.nguyen@intel.com>
> > > Sent: 10 December 2025 07:15
> > > To: intel-xe@lists.freedesktop.org
> > > Cc: Upadhyay, Tejas <tejas.upadhyay@intel.com>; Brost, Matthew
> > > <matthew.brost@intel.com>; Lin, Shuicheng <shuicheng.lin@intel.com>;
> > > Summers, Stuart <stuart.summers@intel.com>; Auld, Matthew
> > > <matthew.auld@intel.com>
> > > Subject: [PATCH v5 09/10] drm/xe: Optimize flushing of L2$ by
> > > skipping unnecessary page reclaim
> > >
> > > There are additional hardware managed L2$ flushing such as the
> > > transient display. In those scenarios, page reclamation is
> > > unnecessary resulting in redundant cacheline flushes, so skip over those
> corresponding ranges.
> > >
> > > v2:
> > > - Elaborated on reasoning for page reclamation skip based on
> > > Tejas's discussion. (Matthew A, Tejas)
> > >
> > > v3:
> > > - Removed MEDIA_IS_ON due to racy condition resulting in removal of
> > > relevant registers and values. (Matthew A)
> > > - Moved l3 policy access to xe_pat. (Matthew A)
> > >
> > > v4:
> > > - Updated comments based on previous change. (Tejas)
> > > - Move back PAT index macros to xe_pat.c.
> > >
> > > Signed-off-by: Brian Nguyen <brian3.nguyen@intel.com>
> > > Cc: Tejas Upadhyay <tejas.upadhyay@intel.com>
> > > Cc: Matthew Auld <matthew.auld@intel.com>
> > > ---
> > > drivers/gpu/drm/xe/xe_page_reclaim.c | 32
> > > ++++++++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_page_reclaim.h
> > > | 3 +++
> > > drivers/gpu/drm/xe/xe_pat.c | 8 +++++++
> > > drivers/gpu/drm/xe/xe_pat.h | 10 +++++++++
> > > drivers/gpu/drm/xe/xe_pt.c | 3 ++-
> > > 5 files changed, 55 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/xe/xe_page_reclaim.c
> > > b/drivers/gpu/drm/xe/xe_page_reclaim.c
> > > index 0cce5ad2e33b..fd8c33761127 100644
> > > --- a/drivers/gpu/drm/xe/xe_page_reclaim.c
> > > +++ b/drivers/gpu/drm/xe/xe_page_reclaim.c
> > > @@ -13,8 +13,40 @@
> > > #include "regs/xe_gt_regs.h"
> > > #include "xe_assert.h"
> > > #include "xe_macros.h"
> > > +#include "xe_mmio.h"
> > > +#include "xe_pat.h"
> > > #include "xe_sa.h"
> > > #include "xe_tlb_inval_types.h"
> > > +#include "xe_vm.h"
> > > +
> > > +/**
> > > + * xe_page_reclaim_skip() - Decide whether PRL should be skipped
> > > +for a VMA
> > > + * @tile: Tile owning the VMA
> > > + * @vma: VMA under consideration
> > > + *
> > > + * PPC flushing may be handled by HW for specific PAT encodings.
> > > + * Skip PPC flushing/Page Reclaim for scenarios below due to
> > > +redundant
> > > + * flushes.
> > > + * - pat_index is transient display (1)
> > > + *
> > > + * Return: true when page reclamation is unnecessary, false otherwise.
> > > + */
> > > +bool xe_page_reclaim_skip(struct xe_tile *tile, struct xe_vma *vma) {
> > > + u8 l3_policy;
> > > +
> > > + l3_policy = xe_pat_index_get_l3_policy(tile->xe,
> > > +vma->attr.pat_index);
> > > +
> > > + /*
> > > + * - l3_policy: 0=WB, 1=XD ("WB - Transient Display"), 3=UC
> > > + * Transient display flushes is taken care by HW, l3_policy = 1.
> > > + *
> > > + * HW will sequence these transient flushes at various sync points so
> > > + * any event of page reclamation will hit these sync points before
> > > + * page reclamation could execute.
> > > + */
> > > + return (l3_policy == XE_L3_POLICY_XD); }
> >
> > I think you do not want to skip anything here as far current HW capabilities
> concerned on upstream. Though normal flow of transient display flush by
> KMD driver will flush, you cant be sure and you need to flush full at page
> reclamation. The idea of skipping came because of HW capability to flush
> which is not there in any of upstream platforms. Probably we can drop this
> patch itself!
I just rethought, I think this will be executed only when has_hw_page_reclamantion is true. And when page_reclamation turns true indirectly transient display flush will be take care by HW.
So it should be good to go, with that :
Reviewed-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Tejas
>
> Well maybe (?) - tbh I haven't the spec on this skipping.
>
> But if any upstream platform correctly reports a cap, future platforms report
> the different cap, completely reasonable to merge now.
>
> Hoe about a bspec link in the commit...
>
> e.g.
>
> Bspec: <number>
>
> So we can all get on the same page.
>
> Matt
>
> >
> > Tejas
> > >
> > > /**
> > > * xe_page_reclaim_create_prl_bo() - Back a PRL with a suballocated
> > > GGTT BO diff --git a/drivers/gpu/drm/xe/xe_page_reclaim.h
> > > b/drivers/gpu/drm/xe/xe_page_reclaim.h
> > > index f5f07e2e114f..0faea29f3964 100644
> > > --- a/drivers/gpu/drm/xe/xe_page_reclaim.h
> > > +++ b/drivers/gpu/drm/xe/xe_page_reclaim.h
> > > @@ -18,6 +18,8 @@
> > >
> > > struct xe_tlb_inval;
> > > struct xe_tlb_inval_fence;
> > > +struct xe_tile;
> > > +struct xe_vma;
> > >
> > > struct xe_guc_page_reclaim_entry {
> > > u64 qw;
> > > @@ -68,6 +70,7 @@ static inline bool
> > > xe_page_reclaim_list_valid(struct xe_page_reclaim_list *prl)
> > > prl->num_entries != XE_PAGE_RECLAIM_INVALID_LIST; }
> > >
> > > +bool xe_page_reclaim_skip(struct xe_tile *tile, struct xe_vma
> > > +*vma);
> > > struct drm_suballoc *xe_page_reclaim_create_prl_bo(struct
> > > xe_tlb_inval *tlb_inval,
> > > struct xe_page_reclaim_list
> *prl,
> > > struct xe_tlb_inval_fence
> > > *fence); diff --git a/drivers/gpu/drm/xe/xe_pat.c
> > > b/drivers/gpu/drm/xe/xe_pat.c index 6f48d34711a6..2c3375e0250b
> > > 100644
> > > --- a/drivers/gpu/drm/xe/xe_pat.c
> > > +++ b/drivers/gpu/drm/xe/xe_pat.c
> > > @@ -9,6 +9,7 @@
> > >
> > > #include <generated/xe_wa_oob.h>
> > >
> > > +#include "regs/xe_gt_regs.h"
> > > #include "regs/xe_reg_defs.h"
> > > #include "xe_assert.h"
> > > #include "xe_device.h"
> > > @@ -231,6 +232,13 @@ bool xe_pat_index_get_comp_en(struct
> xe_device
> > > *xe, u16 pat_index)
> > > return !!(xe->pat.table[pat_index].value & XE2_COMP_EN); }
> > >
> > > +u16 xe_pat_index_get_l3_policy(struct xe_device *xe, u16 pat_index) {
> > > + WARN_ON(pat_index >= xe->pat.n_entries);
> > > +
> > > + return REG_FIELD_GET(XE2_L3_POLICY, xe-
> > > >pat.table[pat_index].value); }
> > > +
> > > static void program_pat(struct xe_gt *gt, const struct
> > > xe_pat_table_entry table[],
> > > int n_entries)
> > > {
> > > diff --git a/drivers/gpu/drm/xe/xe_pat.h
> > > b/drivers/gpu/drm/xe/xe_pat.h index 5749a488d9a9..d5dadfb7f924
> > > 100644
> > > --- a/drivers/gpu/drm/xe/xe_pat.h
> > > +++ b/drivers/gpu/drm/xe/xe_pat.h
> > > @@ -69,4 +69,14 @@ u16 xe_pat_index_get_coh_mode(struct xe_device
> > > *xe, u16 pat_index);
> > > */
> > > bool xe_pat_index_get_comp_en(struct xe_device *xe, u16 pat_index);
> > >
> > > +#define XE_L3_POLICY_WB 0 /* Write-back */
> > > +#define XE_L3_POLICY_XD 1 /* WB - Transient Display */
> > > +#define XE_L3_POLICY_UC 3 /* Uncached */
> > > +/**
> > > + * xe_pat_index_get_l3_policy - Extract the L3 policy for the given
> pat_index.
> > > + * @xe: xe device
> > > + * @pat_index: The pat_index to query */
> > > +u16 xe_pat_index_get_l3_policy(struct xe_device *xe, u16
> > > +pat_index);
> > > +
> > > #endif
> > > diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c
> > > index
> > > 78e2f037f8e1..43426979b164 100644
> > > --- a/drivers/gpu/drm/xe/xe_pt.c
> > > +++ b/drivers/gpu/drm/xe/xe_pt.c
> > > @@ -2030,7 +2030,8 @@ static int unbind_op_prepare(struct xe_tile
> *tile,
> > > xe_page_reclaim_list_alloc_entries(&pt_update_ops->prl);
> > >
> > > /* Page reclaim may not be needed due to other features, so skip
> > > the corresponding VMA */
> > > - pt_op->prl = (xe_page_reclaim_list_valid(&pt_update_ops->prl)) ?
> > > &pt_update_ops->prl : NULL;
> > > + pt_op->prl = (xe_page_reclaim_list_valid(&pt_update_ops->prl) &&
> > > + !xe_page_reclaim_skip(tile, vma)) ? &pt_update_ops->prl :
> > > NULL;
> > >
> > > err = vma_reserve_fences(tile_to_xe(tile), vma);
> > > if (err)
> > > --
> > > 2.52.0
> >
^ permalink raw reply [flat|nested] 22+ messages in thread
* ✗ CI.checkpatch: warning for Page Reclamation Support for Xe3p Platforms (rev6)
2025-12-10 1:45 [PATCH v5 00/10] Page Reclamation Support for Xe3p Platforms Brian Nguyen
` (9 preceding siblings ...)
2025-12-10 1:45 ` [PATCH v5 10/10] drm/xe: Add debugfs support for page reclamation Brian Nguyen
@ 2025-12-11 5:50 ` Patchwork
2025-12-11 5:52 ` ✓ CI.KUnit: success " Patchwork
` (2 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2025-12-11 5:50 UTC (permalink / raw)
To: Brian Nguyen; +Cc: intel-xe
== Series Details ==
Series: Page Reclamation Support for Xe3p Platforms (rev6)
URL : https://patchwork.freedesktop.org/series/157698/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
8f50e69d0ce3656564bbdf8b3e213d61470d463f
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit d4cb4d9a2f705d421a448a8029bbd722ee34345d
Author: Brian Nguyen <brian3.nguyen@intel.com>
Date: Wed Dec 10 09:45:28 2025 +0800
drm/xe: Add debugfs support for page reclamation
Allow for runtime modification to page reclamation feature through
debugfs configuration. This parameter will only take effect if the
platform supports the page reclamation feature by default.
v2:
- Minor comment tweaks. (Shuicheng)
- Convert to kstrtobool_from_user. (Michal)
- Only expose page reclaim file if page reclaim flag
initially supported and with that, remove
xe_match_desc usage. (Michal)
Signed-off-by: Brian Nguyen <brian3.nguyen@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Shuicheng Lin <shuicheng.lin@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
+ /mt/dim checkpatch 3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b drm-intel
57717484771c drm/xe: Do not forward invalid TLB invalidation seqnos to upper layers
02f792639caf drm/xe/xe_tlb_inval: Modify fence interface to support PPC flush
454b1176fa94 drm/xe: Add page reclamation info to device info
154443b2c366 drm/xe/guc: Add page reclamation interface to GuC
9cfe9c3d8afd drm/xe: Create page reclaim list on unbind
-:75: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#75:
new file mode 100644
-:202: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "!prl->entries"
#202: FILE: drivers/gpu/drm/xe/xe_page_reclaim.h:52:
+ return prl->entries == NULL && prl->num_entries == 0;
-:287: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#287: FILE: drivers/gpu/drm/xe/xe_pt.c:1593:
+static int generate_reclaim_entry(struct xe_tile *tile,
+ struct xe_page_reclaim_list *prl,
total: 0 errors, 1 warnings, 2 checks, 391 lines checked
281f1dd4ef2b drm/xe: Suballocate BO for page reclaim
875b1ccecd72 drm/xe: Prep page reclaim in tlb inval job
3662f1de45a8 drm/xe: Append page reclamation action to tlb inval
325cb5168fd5 drm/xe: Optimize flushing of L2$ by skipping unnecessary page reclaim
d4cb4d9a2f70 drm/xe: Add debugfs support for page reclamation
^ permalink raw reply [flat|nested] 22+ messages in thread
* ✓ CI.KUnit: success for Page Reclamation Support for Xe3p Platforms (rev6)
2025-12-10 1:45 [PATCH v5 00/10] Page Reclamation Support for Xe3p Platforms Brian Nguyen
` (10 preceding siblings ...)
2025-12-11 5:50 ` ✗ CI.checkpatch: warning for Page Reclamation Support for Xe3p Platforms (rev6) Patchwork
@ 2025-12-11 5:52 ` Patchwork
2025-12-11 7:17 ` ✓ Xe.CI.BAT: " Patchwork
2025-12-11 14:04 ` ✗ Xe.CI.Full: failure " Patchwork
13 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2025-12-11 5:52 UTC (permalink / raw)
To: Brian Nguyen; +Cc: intel-xe
== Series Details ==
Series: Page Reclamation Support for Xe3p Platforms (rev6)
URL : https://patchwork.freedesktop.org/series/157698/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[05:50:01] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[05:50:08] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[05:51:08] Starting KUnit Kernel (1/1)...
[05:51:08] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[05:51:09] ================== guc_buf (11 subtests) ===================
[05:51:09] [PASSED] test_smallest
[05:51:09] [PASSED] test_largest
[05:51:09] [PASSED] test_granular
[05:51:09] [PASSED] test_unique
[05:51:09] [PASSED] test_overlap
[05:51:09] [PASSED] test_reusable
[05:51:09] [PASSED] test_too_big
[05:51:09] [PASSED] test_flush
[05:51:09] [PASSED] test_lookup
[05:51:09] [PASSED] test_data
[05:51:09] [PASSED] test_class
[05:51:09] ===================== [PASSED] guc_buf =====================
[05:51:09] =================== guc_dbm (7 subtests) ===================
[05:51:09] [PASSED] test_empty
[05:51:09] [PASSED] test_default
[05:51:09] ======================== test_size ========================
[05:51:09] [PASSED] 4
[05:51:09] [PASSED] 8
[05:51:09] [PASSED] 32
[05:51:09] [PASSED] 256
[05:51:09] ==================== [PASSED] test_size ====================
[05:51:09] ======================= test_reuse ========================
[05:51:09] [PASSED] 4
[05:51:09] [PASSED] 8
[05:51:09] [PASSED] 32
[05:51:09] [PASSED] 256
[05:51:09] =================== [PASSED] test_reuse ====================
[05:51:09] =================== test_range_overlap ====================
[05:51:09] [PASSED] 4
[05:51:09] [PASSED] 8
[05:51:09] [PASSED] 32
[05:51:09] [PASSED] 256
[05:51:09] =============== [PASSED] test_range_overlap ================
[05:51:09] =================== test_range_compact ====================
[05:51:09] [PASSED] 4
[05:51:09] [PASSED] 8
[05:51:09] [PASSED] 32
[05:51:09] [PASSED] 256
[05:51:09] =============== [PASSED] test_range_compact ================
[05:51:09] ==================== test_range_spare =====================
[05:51:09] [PASSED] 4
[05:51:09] [PASSED] 8
[05:51:09] [PASSED] 32
[05:51:09] [PASSED] 256
[05:51:09] ================ [PASSED] test_range_spare =================
[05:51:09] ===================== [PASSED] guc_dbm =====================
[05:51:09] =================== guc_idm (6 subtests) ===================
[05:51:09] [PASSED] bad_init
[05:51:09] [PASSED] no_init
[05:51:09] [PASSED] init_fini
[05:51:09] [PASSED] check_used
[05:51:09] [PASSED] check_quota
[05:51:09] [PASSED] check_all
[05:51:09] ===================== [PASSED] guc_idm =====================
[05:51:09] ================== no_relay (3 subtests) ===================
[05:51:09] [PASSED] xe_drops_guc2pf_if_not_ready
[05:51:09] [PASSED] xe_drops_guc2vf_if_not_ready
[05:51:09] [PASSED] xe_rejects_send_if_not_ready
[05:51:09] ==================== [PASSED] no_relay =====================
[05:51:09] ================== pf_relay (14 subtests) ==================
[05:51:09] [PASSED] pf_rejects_guc2pf_too_short
[05:51:09] [PASSED] pf_rejects_guc2pf_too_long
[05:51:09] [PASSED] pf_rejects_guc2pf_no_payload
[05:51:09] [PASSED] pf_fails_no_payload
[05:51:09] [PASSED] pf_fails_bad_origin
[05:51:09] [PASSED] pf_fails_bad_type
[05:51:09] [PASSED] pf_txn_reports_error
[05:51:09] [PASSED] pf_txn_sends_pf2guc
[05:51:09] [PASSED] pf_sends_pf2guc
[05:51:09] [SKIPPED] pf_loopback_nop
[05:51:09] [SKIPPED] pf_loopback_echo
[05:51:09] [SKIPPED] pf_loopback_fail
[05:51:09] [SKIPPED] pf_loopback_busy
[05:51:09] [SKIPPED] pf_loopback_retry
[05:51:09] ==================== [PASSED] pf_relay =====================
[05:51:09] ================== vf_relay (3 subtests) ===================
[05:51:09] [PASSED] vf_rejects_guc2vf_too_short
[05:51:09] [PASSED] vf_rejects_guc2vf_too_long
[05:51:09] [PASSED] vf_rejects_guc2vf_no_payload
[05:51:09] ==================== [PASSED] vf_relay =====================
[05:51:09] ================ pf_gt_config (6 subtests) =================
[05:51:09] [PASSED] fair_contexts_1vf
[05:51:09] [PASSED] fair_doorbells_1vf
[05:51:09] [PASSED] fair_ggtt_1vf
[05:51:09] ====================== fair_contexts ======================
[05:51:09] [PASSED] 1 VF
[05:51:09] [PASSED] 2 VFs
[05:51:09] [PASSED] 3 VFs
[05:51:09] [PASSED] 4 VFs
[05:51:09] [PASSED] 5 VFs
[05:51:09] [PASSED] 6 VFs
[05:51:09] [PASSED] 7 VFs
[05:51:09] [PASSED] 8 VFs
[05:51:09] [PASSED] 9 VFs
[05:51:09] [PASSED] 10 VFs
[05:51:09] [PASSED] 11 VFs
[05:51:09] [PASSED] 12 VFs
[05:51:09] [PASSED] 13 VFs
[05:51:09] [PASSED] 14 VFs
[05:51:09] [PASSED] 15 VFs
[05:51:09] [PASSED] 16 VFs
[05:51:09] [PASSED] 17 VFs
[05:51:09] [PASSED] 18 VFs
[05:51:09] [PASSED] 19 VFs
[05:51:09] [PASSED] 20 VFs
[05:51:09] [PASSED] 21 VFs
[05:51:09] [PASSED] 22 VFs
[05:51:09] [PASSED] 23 VFs
[05:51:09] [PASSED] 24 VFs
[05:51:09] [PASSED] 25 VFs
[05:51:09] [PASSED] 26 VFs
[05:51:09] [PASSED] 27 VFs
[05:51:09] [PASSED] 28 VFs
[05:51:09] [PASSED] 29 VFs
[05:51:09] [PASSED] 30 VFs
[05:51:09] [PASSED] 31 VFs
[05:51:09] [PASSED] 32 VFs
[05:51:09] [PASSED] 33 VFs
[05:51:09] [PASSED] 34 VFs
[05:51:09] [PASSED] 35 VFs
[05:51:09] [PASSED] 36 VFs
[05:51:09] [PASSED] 37 VFs
[05:51:09] [PASSED] 38 VFs
[05:51:09] [PASSED] 39 VFs
[05:51:09] [PASSED] 40 VFs
[05:51:09] [PASSED] 41 VFs
[05:51:09] [PASSED] 42 VFs
[05:51:09] [PASSED] 43 VFs
[05:51:09] [PASSED] 44 VFs
[05:51:09] [PASSED] 45 VFs
[05:51:09] [PASSED] 46 VFs
[05:51:09] [PASSED] 47 VFs
[05:51:09] [PASSED] 48 VFs
[05:51:09] [PASSED] 49 VFs
[05:51:09] [PASSED] 50 VFs
[05:51:09] [PASSED] 51 VFs
[05:51:09] [PASSED] 52 VFs
[05:51:09] [PASSED] 53 VFs
[05:51:09] [PASSED] 54 VFs
[05:51:09] [PASSED] 55 VFs
[05:51:09] [PASSED] 56 VFs
[05:51:09] [PASSED] 57 VFs
[05:51:09] [PASSED] 58 VFs
[05:51:09] [PASSED] 59 VFs
[05:51:09] [PASSED] 60 VFs
[05:51:09] [PASSED] 61 VFs
[05:51:09] [PASSED] 62 VFs
[05:51:09] [PASSED] 63 VFs
[05:51:09] ================== [PASSED] fair_contexts ==================
[05:51:09] ===================== fair_doorbells ======================
[05:51:09] [PASSED] 1 VF
[05:51:09] [PASSED] 2 VFs
[05:51:09] [PASSED] 3 VFs
[05:51:09] [PASSED] 4 VFs
[05:51:09] [PASSED] 5 VFs
[05:51:09] [PASSED] 6 VFs
[05:51:09] [PASSED] 7 VFs
[05:51:09] [PASSED] 8 VFs
[05:51:09] [PASSED] 9 VFs
[05:51:09] [PASSED] 10 VFs
[05:51:09] [PASSED] 11 VFs
[05:51:09] [PASSED] 12 VFs
[05:51:09] [PASSED] 13 VFs
[05:51:09] [PASSED] 14 VFs
[05:51:09] [PASSED] 15 VFs
[05:51:09] [PASSED] 16 VFs
[05:51:09] [PASSED] 17 VFs
[05:51:09] [PASSED] 18 VFs
[05:51:09] [PASSED] 19 VFs
[05:51:09] [PASSED] 20 VFs
[05:51:09] [PASSED] 21 VFs
[05:51:09] [PASSED] 22 VFs
[05:51:09] [PASSED] 23 VFs
[05:51:09] [PASSED] 24 VFs
[05:51:09] [PASSED] 25 VFs
[05:51:09] [PASSED] 26 VFs
[05:51:09] [PASSED] 27 VFs
[05:51:09] [PASSED] 28 VFs
[05:51:09] [PASSED] 29 VFs
[05:51:09] [PASSED] 30 VFs
[05:51:09] [PASSED] 31 VFs
[05:51:09] [PASSED] 32 VFs
[05:51:09] [PASSED] 33 VFs
[05:51:09] [PASSED] 34 VFs
[05:51:09] [PASSED] 35 VFs
[05:51:09] [PASSED] 36 VFs
[05:51:09] [PASSED] 37 VFs
[05:51:09] [PASSED] 38 VFs
[05:51:09] [PASSED] 39 VFs
[05:51:09] [PASSED] 40 VFs
[05:51:09] [PASSED] 41 VFs
[05:51:09] [PASSED] 42 VFs
[05:51:09] [PASSED] 43 VFs
[05:51:09] [PASSED] 44 VFs
[05:51:09] [PASSED] 45 VFs
[05:51:09] [PASSED] 46 VFs
[05:51:09] [PASSED] 47 VFs
[05:51:09] [PASSED] 48 VFs
[05:51:09] [PASSED] 49 VFs
[05:51:09] [PASSED] 50 VFs
[05:51:09] [PASSED] 51 VFs
[05:51:09] [PASSED] 52 VFs
[05:51:09] [PASSED] 53 VFs
[05:51:09] [PASSED] 54 VFs
[05:51:09] [PASSED] 55 VFs
[05:51:09] [PASSED] 56 VFs
[05:51:09] [PASSED] 57 VFs
[05:51:09] [PASSED] 58 VFs
[05:51:09] [PASSED] 59 VFs
[05:51:09] [PASSED] 60 VFs
[05:51:09] [PASSED] 61 VFs
[05:51:09] [PASSED] 62 VFs
[05:51:09] [PASSED] 63 VFs
[05:51:09] ================= [PASSED] fair_doorbells ==================
[05:51:09] ======================== fair_ggtt ========================
[05:51:09] [PASSED] 1 VF
[05:51:09] [PASSED] 2 VFs
[05:51:09] [PASSED] 3 VFs
[05:51:09] [PASSED] 4 VFs
[05:51:09] [PASSED] 5 VFs
[05:51:09] [PASSED] 6 VFs
[05:51:09] [PASSED] 7 VFs
[05:51:09] [PASSED] 8 VFs
[05:51:09] [PASSED] 9 VFs
[05:51:09] [PASSED] 10 VFs
[05:51:09] [PASSED] 11 VFs
[05:51:09] [PASSED] 12 VFs
[05:51:09] [PASSED] 13 VFs
[05:51:09] [PASSED] 14 VFs
[05:51:09] [PASSED] 15 VFs
[05:51:09] [PASSED] 16 VFs
[05:51:09] [PASSED] 17 VFs
[05:51:09] [PASSED] 18 VFs
[05:51:09] [PASSED] 19 VFs
[05:51:09] [PASSED] 20 VFs
[05:51:09] [PASSED] 21 VFs
[05:51:09] [PASSED] 22 VFs
[05:51:09] [PASSED] 23 VFs
[05:51:09] [PASSED] 24 VFs
[05:51:09] [PASSED] 25 VFs
[05:51:09] [PASSED] 26 VFs
[05:51:09] [PASSED] 27 VFs
[05:51:09] [PASSED] 28 VFs
[05:51:09] [PASSED] 29 VFs
[05:51:09] [PASSED] 30 VFs
[05:51:09] [PASSED] 31 VFs
[05:51:09] [PASSED] 32 VFs
[05:51:09] [PASSED] 33 VFs
[05:51:09] [PASSED] 34 VFs
[05:51:09] [PASSED] 35 VFs
[05:51:09] [PASSED] 36 VFs
[05:51:09] [PASSED] 37 VFs
[05:51:09] [PASSED] 38 VFs
[05:51:09] [PASSED] 39 VFs
[05:51:09] [PASSED] 40 VFs
[05:51:09] [PASSED] 41 VFs
[05:51:09] [PASSED] 42 VFs
[05:51:09] [PASSED] 43 VFs
[05:51:09] [PASSED] 44 VFs
[05:51:09] [PASSED] 45 VFs
[05:51:09] [PASSED] 46 VFs
[05:51:09] [PASSED] 47 VFs
[05:51:09] [PASSED] 48 VFs
[05:51:09] [PASSED] 49 VFs
[05:51:09] [PASSED] 50 VFs
[05:51:09] [PASSED] 51 VFs
[05:51:09] [PASSED] 52 VFs
[05:51:09] [PASSED] 53 VFs
[05:51:09] [PASSED] 54 VFs
[05:51:09] [PASSED] 55 VFs
[05:51:09] [PASSED] 56 VFs
[05:51:09] [PASSED] 57 VFs
[05:51:09] [PASSED] 58 VFs
[05:51:09] [PASSED] 59 VFs
[05:51:09] [PASSED] 60 VFs
[05:51:09] [PASSED] 61 VFs
[05:51:09] [PASSED] 62 VFs
[05:51:09] [PASSED] 63 VFs
[05:51:09] ==================== [PASSED] fair_ggtt ====================
[05:51:09] ================== [PASSED] pf_gt_config ===================
[05:51:09] ===================== lmtt (1 subtest) =====================
[05:51:09] ======================== test_ops =========================
[05:51:09] [PASSED] 2-level
[05:51:09] [PASSED] multi-level
[05:51:09] ==================== [PASSED] test_ops =====================
[05:51:09] ====================== [PASSED] lmtt =======================
[05:51:09] ================= pf_service (11 subtests) =================
[05:51:09] [PASSED] pf_negotiate_any
[05:51:09] [PASSED] pf_negotiate_base_match
[05:51:09] [PASSED] pf_negotiate_base_newer
[05:51:09] [PASSED] pf_negotiate_base_next
[05:51:09] [SKIPPED] pf_negotiate_base_older
[05:51:09] [PASSED] pf_negotiate_base_prev
[05:51:09] [PASSED] pf_negotiate_latest_match
[05:51:09] [PASSED] pf_negotiate_latest_newer
[05:51:09] [PASSED] pf_negotiate_latest_next
[05:51:09] [SKIPPED] pf_negotiate_latest_older
[05:51:09] [SKIPPED] pf_negotiate_latest_prev
[05:51:09] =================== [PASSED] pf_service ====================
[05:51:09] ================= xe_guc_g2g (2 subtests) ==================
[05:51:09] ============== xe_live_guc_g2g_kunit_default ==============
[05:51:09] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[05:51:09] ============== xe_live_guc_g2g_kunit_allmem ===============
[05:51:09] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[05:51:09] =================== [SKIPPED] xe_guc_g2g ===================
[05:51:09] =================== xe_mocs (2 subtests) ===================
[05:51:09] ================ xe_live_mocs_kernel_kunit ================
[05:51:09] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[05:51:09] ================ xe_live_mocs_reset_kunit =================
[05:51:09] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[05:51:09] ==================== [SKIPPED] xe_mocs =====================
[05:51:09] ================= xe_migrate (2 subtests) ==================
[05:51:09] ================= xe_migrate_sanity_kunit =================
[05:51:09] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[05:51:09] ================== xe_validate_ccs_kunit ==================
[05:51:09] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[05:51:09] =================== [SKIPPED] xe_migrate ===================
[05:51:09] ================== xe_dma_buf (1 subtest) ==================
[05:51:09] ==================== xe_dma_buf_kunit =====================
[05:51:09] ================ [SKIPPED] xe_dma_buf_kunit ================
[05:51:09] =================== [SKIPPED] xe_dma_buf ===================
[05:51:09] ================= xe_bo_shrink (1 subtest) =================
[05:51:09] =================== xe_bo_shrink_kunit ====================
[05:51:09] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[05:51:09] ================== [SKIPPED] xe_bo_shrink ==================
[05:51:09] ==================== xe_bo (2 subtests) ====================
[05:51:09] ================== xe_ccs_migrate_kunit ===================
[05:51:09] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[05:51:09] ==================== xe_bo_evict_kunit ====================
[05:51:09] =============== [SKIPPED] xe_bo_evict_kunit ================
[05:51:09] ===================== [SKIPPED] xe_bo ======================
[05:51:09] ==================== args (11 subtests) ====================
[05:51:09] [PASSED] count_args_test
[05:51:09] [PASSED] call_args_example
[05:51:09] [PASSED] call_args_test
[05:51:09] [PASSED] drop_first_arg_example
[05:51:09] [PASSED] drop_first_arg_test
[05:51:09] [PASSED] first_arg_example
[05:51:09] [PASSED] first_arg_test
[05:51:09] [PASSED] last_arg_example
[05:51:09] [PASSED] last_arg_test
[05:51:09] [PASSED] pick_arg_example
[05:51:09] [PASSED] sep_comma_example
[05:51:09] ====================== [PASSED] args =======================
[05:51:09] =================== xe_pci (3 subtests) ====================
[05:51:09] ==================== check_graphics_ip ====================
[05:51:09] [PASSED] 12.00 Xe_LP
[05:51:09] [PASSED] 12.10 Xe_LP+
[05:51:09] [PASSED] 12.55 Xe_HPG
[05:51:09] [PASSED] 12.60 Xe_HPC
[05:51:09] [PASSED] 12.70 Xe_LPG
[05:51:09] [PASSED] 12.71 Xe_LPG
[05:51:09] [PASSED] 12.74 Xe_LPG+
[05:51:09] [PASSED] 20.01 Xe2_HPG
[05:51:09] [PASSED] 20.02 Xe2_HPG
[05:51:09] [PASSED] 20.04 Xe2_LPG
[05:51:09] [PASSED] 30.00 Xe3_LPG
[05:51:09] [PASSED] 30.01 Xe3_LPG
[05:51:09] [PASSED] 30.03 Xe3_LPG
[05:51:09] [PASSED] 30.04 Xe3_LPG
[05:51:09] [PASSED] 30.05 Xe3_LPG
[05:51:09] [PASSED] 35.11 Xe3p_XPC
[05:51:09] ================ [PASSED] check_graphics_ip ================
[05:51:09] ===================== check_media_ip ======================
[05:51:09] [PASSED] 12.00 Xe_M
[05:51:09] [PASSED] 12.55 Xe_HPM
[05:51:09] [PASSED] 13.00 Xe_LPM+
[05:51:09] [PASSED] 13.01 Xe2_HPM
[05:51:09] [PASSED] 20.00 Xe2_LPM
[05:51:09] [PASSED] 30.00 Xe3_LPM
[05:51:09] [PASSED] 30.02 Xe3_LPM
[05:51:09] [PASSED] 35.00 Xe3p_LPM
[05:51:09] [PASSED] 35.03 Xe3p_HPM
[05:51:09] ================= [PASSED] check_media_ip ==================
[05:51:09] =================== check_platform_desc ===================
[05:51:09] [PASSED] 0x9A60 (TIGERLAKE)
[05:51:09] [PASSED] 0x9A68 (TIGERLAKE)
[05:51:09] [PASSED] 0x9A70 (TIGERLAKE)
[05:51:09] [PASSED] 0x9A40 (TIGERLAKE)
[05:51:09] [PASSED] 0x9A49 (TIGERLAKE)
[05:51:09] [PASSED] 0x9A59 (TIGERLAKE)
[05:51:09] [PASSED] 0x9A78 (TIGERLAKE)
[05:51:09] [PASSED] 0x9AC0 (TIGERLAKE)
[05:51:09] [PASSED] 0x9AC9 (TIGERLAKE)
[05:51:09] [PASSED] 0x9AD9 (TIGERLAKE)
[05:51:09] [PASSED] 0x9AF8 (TIGERLAKE)
[05:51:09] [PASSED] 0x4C80 (ROCKETLAKE)
[05:51:09] [PASSED] 0x4C8A (ROCKETLAKE)
[05:51:09] [PASSED] 0x4C8B (ROCKETLAKE)
[05:51:09] [PASSED] 0x4C8C (ROCKETLAKE)
[05:51:09] [PASSED] 0x4C90 (ROCKETLAKE)
[05:51:09] [PASSED] 0x4C9A (ROCKETLAKE)
[05:51:09] [PASSED] 0x4680 (ALDERLAKE_S)
[05:51:09] [PASSED] 0x4682 (ALDERLAKE_S)
[05:51:09] [PASSED] 0x4688 (ALDERLAKE_S)
[05:51:09] [PASSED] 0x468A (ALDERLAKE_S)
[05:51:09] [PASSED] 0x468B (ALDERLAKE_S)
[05:51:09] [PASSED] 0x4690 (ALDERLAKE_S)
[05:51:09] [PASSED] 0x4692 (ALDERLAKE_S)
[05:51:09] [PASSED] 0x4693 (ALDERLAKE_S)
[05:51:09] [PASSED] 0x46A0 (ALDERLAKE_P)
[05:51:09] [PASSED] 0x46A1 (ALDERLAKE_P)
[05:51:09] [PASSED] 0x46A2 (ALDERLAKE_P)
[05:51:09] [PASSED] 0x46A3 (ALDERLAKE_P)
[05:51:09] [PASSED] 0x46A6 (ALDERLAKE_P)
[05:51:09] [PASSED] 0x46A8 (ALDERLAKE_P)
[05:51:09] [PASSED] 0x46AA (ALDERLAKE_P)
[05:51:09] [PASSED] 0x462A (ALDERLAKE_P)
[05:51:09] [PASSED] 0x4626 (ALDERLAKE_P)
[05:51:09] [PASSED] 0x4628 (ALDERLAKE_P)
[05:51:09] [PASSED] 0x46B0 (ALDERLAKE_P)
stty: 'standard input': Inappropriate ioctl for device
[05:51:09] [PASSED] 0x46B1 (ALDERLAKE_P)
[05:51:09] [PASSED] 0x46B2 (ALDERLAKE_P)
[05:51:09] [PASSED] 0x46B3 (ALDERLAKE_P)
[05:51:09] [PASSED] 0x46C0 (ALDERLAKE_P)
[05:51:09] [PASSED] 0x46C1 (ALDERLAKE_P)
[05:51:09] [PASSED] 0x46C2 (ALDERLAKE_P)
[05:51:09] [PASSED] 0x46C3 (ALDERLAKE_P)
[05:51:09] [PASSED] 0x46D0 (ALDERLAKE_N)
[05:51:09] [PASSED] 0x46D1 (ALDERLAKE_N)
[05:51:09] [PASSED] 0x46D2 (ALDERLAKE_N)
[05:51:09] [PASSED] 0x46D3 (ALDERLAKE_N)
[05:51:09] [PASSED] 0x46D4 (ALDERLAKE_N)
[05:51:09] [PASSED] 0xA721 (ALDERLAKE_P)
[05:51:09] [PASSED] 0xA7A1 (ALDERLAKE_P)
[05:51:09] [PASSED] 0xA7A9 (ALDERLAKE_P)
[05:51:09] [PASSED] 0xA7AC (ALDERLAKE_P)
[05:51:09] [PASSED] 0xA7AD (ALDERLAKE_P)
[05:51:09] [PASSED] 0xA720 (ALDERLAKE_P)
[05:51:09] [PASSED] 0xA7A0 (ALDERLAKE_P)
[05:51:09] [PASSED] 0xA7A8 (ALDERLAKE_P)
[05:51:09] [PASSED] 0xA7AA (ALDERLAKE_P)
[05:51:09] [PASSED] 0xA7AB (ALDERLAKE_P)
[05:51:09] [PASSED] 0xA780 (ALDERLAKE_S)
[05:51:09] [PASSED] 0xA781 (ALDERLAKE_S)
[05:51:09] [PASSED] 0xA782 (ALDERLAKE_S)
[05:51:09] [PASSED] 0xA783 (ALDERLAKE_S)
[05:51:09] [PASSED] 0xA788 (ALDERLAKE_S)
[05:51:09] [PASSED] 0xA789 (ALDERLAKE_S)
[05:51:09] [PASSED] 0xA78A (ALDERLAKE_S)
[05:51:09] [PASSED] 0xA78B (ALDERLAKE_S)
[05:51:09] [PASSED] 0x4905 (DG1)
[05:51:09] [PASSED] 0x4906 (DG1)
[05:51:09] [PASSED] 0x4907 (DG1)
[05:51:09] [PASSED] 0x4908 (DG1)
[05:51:09] [PASSED] 0x4909 (DG1)
[05:51:09] [PASSED] 0x56C0 (DG2)
[05:51:09] [PASSED] 0x56C2 (DG2)
[05:51:09] [PASSED] 0x56C1 (DG2)
[05:51:09] [PASSED] 0x7D51 (METEORLAKE)
[05:51:09] [PASSED] 0x7DD1 (METEORLAKE)
[05:51:09] [PASSED] 0x7D41 (METEORLAKE)
[05:51:09] [PASSED] 0x7D67 (METEORLAKE)
[05:51:09] [PASSED] 0xB640 (METEORLAKE)
[05:51:09] [PASSED] 0x56A0 (DG2)
[05:51:09] [PASSED] 0x56A1 (DG2)
[05:51:09] [PASSED] 0x56A2 (DG2)
[05:51:09] [PASSED] 0x56BE (DG2)
[05:51:09] [PASSED] 0x56BF (DG2)
[05:51:09] [PASSED] 0x5690 (DG2)
[05:51:09] [PASSED] 0x5691 (DG2)
[05:51:09] [PASSED] 0x5692 (DG2)
[05:51:09] [PASSED] 0x56A5 (DG2)
[05:51:09] [PASSED] 0x56A6 (DG2)
[05:51:09] [PASSED] 0x56B0 (DG2)
[05:51:09] [PASSED] 0x56B1 (DG2)
[05:51:09] [PASSED] 0x56BA (DG2)
[05:51:09] [PASSED] 0x56BB (DG2)
[05:51:09] [PASSED] 0x56BC (DG2)
[05:51:09] [PASSED] 0x56BD (DG2)
[05:51:09] [PASSED] 0x5693 (DG2)
[05:51:09] [PASSED] 0x5694 (DG2)
[05:51:09] [PASSED] 0x5695 (DG2)
[05:51:09] [PASSED] 0x56A3 (DG2)
[05:51:09] [PASSED] 0x56A4 (DG2)
[05:51:09] [PASSED] 0x56B2 (DG2)
[05:51:09] [PASSED] 0x56B3 (DG2)
[05:51:09] [PASSED] 0x5696 (DG2)
[05:51:09] [PASSED] 0x5697 (DG2)
[05:51:09] [PASSED] 0xB69 (PVC)
[05:51:09] [PASSED] 0xB6E (PVC)
[05:51:09] [PASSED] 0xBD4 (PVC)
[05:51:09] [PASSED] 0xBD5 (PVC)
[05:51:09] [PASSED] 0xBD6 (PVC)
[05:51:09] [PASSED] 0xBD7 (PVC)
[05:51:09] [PASSED] 0xBD8 (PVC)
[05:51:09] [PASSED] 0xBD9 (PVC)
[05:51:09] [PASSED] 0xBDA (PVC)
[05:51:09] [PASSED] 0xBDB (PVC)
[05:51:09] [PASSED] 0xBE0 (PVC)
[05:51:09] [PASSED] 0xBE1 (PVC)
[05:51:09] [PASSED] 0xBE5 (PVC)
[05:51:09] [PASSED] 0x7D40 (METEORLAKE)
[05:51:09] [PASSED] 0x7D45 (METEORLAKE)
[05:51:09] [PASSED] 0x7D55 (METEORLAKE)
[05:51:09] [PASSED] 0x7D60 (METEORLAKE)
[05:51:09] [PASSED] 0x7DD5 (METEORLAKE)
[05:51:09] [PASSED] 0x6420 (LUNARLAKE)
[05:51:09] [PASSED] 0x64A0 (LUNARLAKE)
[05:51:09] [PASSED] 0x64B0 (LUNARLAKE)
[05:51:09] [PASSED] 0xE202 (BATTLEMAGE)
[05:51:09] [PASSED] 0xE209 (BATTLEMAGE)
[05:51:09] [PASSED] 0xE20B (BATTLEMAGE)
[05:51:09] [PASSED] 0xE20C (BATTLEMAGE)
[05:51:09] [PASSED] 0xE20D (BATTLEMAGE)
[05:51:09] [PASSED] 0xE210 (BATTLEMAGE)
[05:51:09] [PASSED] 0xE211 (BATTLEMAGE)
[05:51:09] [PASSED] 0xE212 (BATTLEMAGE)
[05:51:09] [PASSED] 0xE216 (BATTLEMAGE)
[05:51:09] [PASSED] 0xE220 (BATTLEMAGE)
[05:51:09] [PASSED] 0xE221 (BATTLEMAGE)
[05:51:09] [PASSED] 0xE222 (BATTLEMAGE)
[05:51:09] [PASSED] 0xE223 (BATTLEMAGE)
[05:51:09] [PASSED] 0xB080 (PANTHERLAKE)
[05:51:09] [PASSED] 0xB081 (PANTHERLAKE)
[05:51:09] [PASSED] 0xB082 (PANTHERLAKE)
[05:51:09] [PASSED] 0xB083 (PANTHERLAKE)
[05:51:09] [PASSED] 0xB084 (PANTHERLAKE)
[05:51:09] [PASSED] 0xB085 (PANTHERLAKE)
[05:51:09] [PASSED] 0xB086 (PANTHERLAKE)
[05:51:09] [PASSED] 0xB087 (PANTHERLAKE)
[05:51:09] [PASSED] 0xB08F (PANTHERLAKE)
[05:51:09] [PASSED] 0xB090 (PANTHERLAKE)
[05:51:09] [PASSED] 0xB0A0 (PANTHERLAKE)
[05:51:09] [PASSED] 0xB0B0 (PANTHERLAKE)
[05:51:09] [PASSED] 0xD740 (NOVALAKE_S)
[05:51:09] [PASSED] 0xD741 (NOVALAKE_S)
[05:51:09] [PASSED] 0xD742 (NOVALAKE_S)
[05:51:09] [PASSED] 0xD743 (NOVALAKE_S)
[05:51:09] [PASSED] 0xD744 (NOVALAKE_S)
[05:51:09] [PASSED] 0xD745 (NOVALAKE_S)
[05:51:09] [PASSED] 0x674C (CRESCENTISLAND)
[05:51:09] [PASSED] 0xFD80 (PANTHERLAKE)
[05:51:09] [PASSED] 0xFD81 (PANTHERLAKE)
[05:51:09] =============== [PASSED] check_platform_desc ===============
[05:51:09] ===================== [PASSED] xe_pci ======================
[05:51:09] =================== xe_rtp (2 subtests) ====================
[05:51:09] =============== xe_rtp_process_to_sr_tests ================
[05:51:09] [PASSED] coalesce-same-reg
[05:51:09] [PASSED] no-match-no-add
[05:51:09] [PASSED] match-or
[05:51:09] [PASSED] match-or-xfail
[05:51:09] [PASSED] no-match-no-add-multiple-rules
[05:51:09] [PASSED] two-regs-two-entries
[05:51:09] [PASSED] clr-one-set-other
[05:51:09] [PASSED] set-field
[05:51:09] [PASSED] conflict-duplicate
[05:51:09] [PASSED] conflict-not-disjoint
[05:51:09] [PASSED] conflict-reg-type
[05:51:09] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[05:51:09] ================== xe_rtp_process_tests ===================
[05:51:09] [PASSED] active1
[05:51:09] [PASSED] active2
[05:51:09] [PASSED] active-inactive
[05:51:09] [PASSED] inactive-active
[05:51:09] [PASSED] inactive-1st_or_active-inactive
[05:51:09] [PASSED] inactive-2nd_or_active-inactive
[05:51:09] [PASSED] inactive-last_or_active-inactive
[05:51:09] [PASSED] inactive-no_or_active-inactive
[05:51:09] ============== [PASSED] xe_rtp_process_tests ===============
[05:51:09] ===================== [PASSED] xe_rtp ======================
[05:51:09] ==================== xe_wa (1 subtest) =====================
[05:51:09] ======================== xe_wa_gt =========================
[05:51:09] [PASSED] TIGERLAKE B0
[05:51:09] [PASSED] DG1 A0
[05:51:09] [PASSED] DG1 B0
[05:51:09] [PASSED] ALDERLAKE_S A0
[05:51:09] [PASSED] ALDERLAKE_S B0
[05:51:09] [PASSED] ALDERLAKE_S C0
[05:51:09] [PASSED] ALDERLAKE_S D0
[05:51:09] [PASSED] ALDERLAKE_P A0
[05:51:09] [PASSED] ALDERLAKE_P B0
[05:51:09] [PASSED] ALDERLAKE_P C0
[05:51:09] [PASSED] ALDERLAKE_S RPLS D0
[05:51:09] [PASSED] ALDERLAKE_P RPLU E0
[05:51:09] [PASSED] DG2 G10 C0
[05:51:09] [PASSED] DG2 G11 B1
[05:51:09] [PASSED] DG2 G12 A1
[05:51:09] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[05:51:09] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[05:51:09] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[05:51:09] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[05:51:09] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[05:51:09] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[05:51:09] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[05:51:09] ==================== [PASSED] xe_wa_gt =====================
[05:51:09] ====================== [PASSED] xe_wa ======================
[05:51:09] ============================================================
[05:51:09] Testing complete. Ran 510 tests: passed: 492, skipped: 18
[05:51:09] Elapsed time: 68.147s total, 7.225s configuring, 60.146s building, 0.747s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[05:51:09] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[05:51:12] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[05:52:01] Starting KUnit Kernel (1/1)...
[05:52:01] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[05:52:01] ============ drm_test_pick_cmdline (2 subtests) ============
[05:52:01] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[05:52:01] =============== drm_test_pick_cmdline_named ===============
[05:52:01] [PASSED] NTSC
[05:52:01] [PASSED] NTSC-J
[05:52:01] [PASSED] PAL
[05:52:01] [PASSED] PAL-M
[05:52:01] =========== [PASSED] drm_test_pick_cmdline_named ===========
[05:52:01] ============== [PASSED] drm_test_pick_cmdline ==============
[05:52:01] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[05:52:01] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[05:52:01] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[05:52:01] =========== drm_validate_clone_mode (2 subtests) ===========
[05:52:01] ============== drm_test_check_in_clone_mode ===============
[05:52:01] [PASSED] in_clone_mode
[05:52:01] [PASSED] not_in_clone_mode
[05:52:01] ========== [PASSED] drm_test_check_in_clone_mode ===========
[05:52:01] =============== drm_test_check_valid_clones ===============
[05:52:01] [PASSED] not_in_clone_mode
[05:52:01] [PASSED] valid_clone
[05:52:01] [PASSED] invalid_clone
[05:52:01] =========== [PASSED] drm_test_check_valid_clones ===========
[05:52:01] ============= [PASSED] drm_validate_clone_mode =============
[05:52:01] ============= drm_validate_modeset (1 subtest) =============
[05:52:01] [PASSED] drm_test_check_connector_changed_modeset
[05:52:01] ============== [PASSED] drm_validate_modeset ===============
[05:52:01] ====== drm_test_bridge_get_current_state (2 subtests) ======
[05:52:01] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[05:52:01] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[05:52:01] ======== [PASSED] drm_test_bridge_get_current_state ========
[05:52:01] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[05:52:01] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[05:52:01] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[05:52:01] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[05:52:01] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[05:52:01] ============== drm_bridge_alloc (2 subtests) ===============
[05:52:01] [PASSED] drm_test_drm_bridge_alloc_basic
[05:52:01] [PASSED] drm_test_drm_bridge_alloc_get_put
[05:52:01] ================ [PASSED] drm_bridge_alloc =================
[05:52:01] ================== drm_buddy (8 subtests) ==================
[05:52:01] [PASSED] drm_test_buddy_alloc_limit
[05:52:01] [PASSED] drm_test_buddy_alloc_optimistic
[05:52:01] [PASSED] drm_test_buddy_alloc_pessimistic
[05:52:01] [PASSED] drm_test_buddy_alloc_pathological
[05:52:01] [PASSED] drm_test_buddy_alloc_contiguous
[05:52:01] [PASSED] drm_test_buddy_alloc_clear
[05:52:01] [PASSED] drm_test_buddy_alloc_range_bias
[05:52:01] [PASSED] drm_test_buddy_fragmentation_performance
[05:52:01] ==================== [PASSED] drm_buddy ====================
[05:52:01] ============= drm_cmdline_parser (40 subtests) =============
[05:52:01] [PASSED] drm_test_cmdline_force_d_only
[05:52:01] [PASSED] drm_test_cmdline_force_D_only_dvi
[05:52:01] [PASSED] drm_test_cmdline_force_D_only_hdmi
[05:52:01] [PASSED] drm_test_cmdline_force_D_only_not_digital
[05:52:01] [PASSED] drm_test_cmdline_force_e_only
[05:52:01] [PASSED] drm_test_cmdline_res
[05:52:01] [PASSED] drm_test_cmdline_res_vesa
[05:52:01] [PASSED] drm_test_cmdline_res_vesa_rblank
[05:52:01] [PASSED] drm_test_cmdline_res_rblank
[05:52:01] [PASSED] drm_test_cmdline_res_bpp
[05:52:01] [PASSED] drm_test_cmdline_res_refresh
[05:52:01] [PASSED] drm_test_cmdline_res_bpp_refresh
[05:52:01] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[05:52:01] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[05:52:01] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[05:52:01] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[05:52:01] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[05:52:01] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[05:52:01] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[05:52:01] [PASSED] drm_test_cmdline_res_margins_force_on
[05:52:01] [PASSED] drm_test_cmdline_res_vesa_margins
[05:52:01] [PASSED] drm_test_cmdline_name
[05:52:01] [PASSED] drm_test_cmdline_name_bpp
[05:52:01] [PASSED] drm_test_cmdline_name_option
[05:52:01] [PASSED] drm_test_cmdline_name_bpp_option
[05:52:01] [PASSED] drm_test_cmdline_rotate_0
[05:52:01] [PASSED] drm_test_cmdline_rotate_90
[05:52:01] [PASSED] drm_test_cmdline_rotate_180
[05:52:01] [PASSED] drm_test_cmdline_rotate_270
[05:52:01] [PASSED] drm_test_cmdline_hmirror
[05:52:01] [PASSED] drm_test_cmdline_vmirror
[05:52:01] [PASSED] drm_test_cmdline_margin_options
[05:52:01] [PASSED] drm_test_cmdline_multiple_options
[05:52:01] [PASSED] drm_test_cmdline_bpp_extra_and_option
[05:52:01] [PASSED] drm_test_cmdline_extra_and_option
[05:52:01] [PASSED] drm_test_cmdline_freestanding_options
[05:52:01] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[05:52:01] [PASSED] drm_test_cmdline_panel_orientation
[05:52:01] ================ drm_test_cmdline_invalid =================
[05:52:01] [PASSED] margin_only
[05:52:01] [PASSED] interlace_only
[05:52:01] [PASSED] res_missing_x
[05:52:01] [PASSED] res_missing_y
[05:52:01] [PASSED] res_bad_y
[05:52:01] [PASSED] res_missing_y_bpp
[05:52:01] [PASSED] res_bad_bpp
[05:52:01] [PASSED] res_bad_refresh
[05:52:01] [PASSED] res_bpp_refresh_force_on_off
[05:52:01] [PASSED] res_invalid_mode
[05:52:01] [PASSED] res_bpp_wrong_place_mode
[05:52:01] [PASSED] name_bpp_refresh
[05:52:01] [PASSED] name_refresh
[05:52:01] [PASSED] name_refresh_wrong_mode
[05:52:01] [PASSED] name_refresh_invalid_mode
[05:52:01] [PASSED] rotate_multiple
[05:52:01] [PASSED] rotate_invalid_val
[05:52:01] [PASSED] rotate_truncated
[05:52:01] [PASSED] invalid_option
[05:52:01] [PASSED] invalid_tv_option
[05:52:01] [PASSED] truncated_tv_option
[05:52:01] ============ [PASSED] drm_test_cmdline_invalid =============
[05:52:01] =============== drm_test_cmdline_tv_options ===============
[05:52:01] [PASSED] NTSC
[05:52:01] [PASSED] NTSC_443
[05:52:01] [PASSED] NTSC_J
[05:52:01] [PASSED] PAL
[05:52:01] [PASSED] PAL_M
[05:52:01] [PASSED] PAL_N
[05:52:01] [PASSED] SECAM
[05:52:01] [PASSED] MONO_525
[05:52:01] [PASSED] MONO_625
[05:52:01] =========== [PASSED] drm_test_cmdline_tv_options ===========
[05:52:01] =============== [PASSED] drm_cmdline_parser ================
[05:52:01] ========== drmm_connector_hdmi_init (20 subtests) ==========
[05:52:01] [PASSED] drm_test_connector_hdmi_init_valid
[05:52:01] [PASSED] drm_test_connector_hdmi_init_bpc_8
[05:52:01] [PASSED] drm_test_connector_hdmi_init_bpc_10
[05:52:01] [PASSED] drm_test_connector_hdmi_init_bpc_12
[05:52:01] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[05:52:01] [PASSED] drm_test_connector_hdmi_init_bpc_null
[05:52:01] [PASSED] drm_test_connector_hdmi_init_formats_empty
[05:52:01] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[05:52:01] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[05:52:01] [PASSED] supported_formats=0x9 yuv420_allowed=1
[05:52:01] [PASSED] supported_formats=0x9 yuv420_allowed=0
[05:52:01] [PASSED] supported_formats=0x3 yuv420_allowed=1
[05:52:01] [PASSED] supported_formats=0x3 yuv420_allowed=0
[05:52:01] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[05:52:01] [PASSED] drm_test_connector_hdmi_init_null_ddc
[05:52:01] [PASSED] drm_test_connector_hdmi_init_null_product
[05:52:01] [PASSED] drm_test_connector_hdmi_init_null_vendor
[05:52:01] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[05:52:01] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[05:52:01] [PASSED] drm_test_connector_hdmi_init_product_valid
[05:52:01] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[05:52:01] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[05:52:01] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[05:52:01] ========= drm_test_connector_hdmi_init_type_valid =========
[05:52:01] [PASSED] HDMI-A
[05:52:01] [PASSED] HDMI-B
[05:52:01] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[05:52:01] ======== drm_test_connector_hdmi_init_type_invalid ========
[05:52:01] [PASSED] Unknown
[05:52:01] [PASSED] VGA
[05:52:01] [PASSED] DVI-I
[05:52:01] [PASSED] DVI-D
[05:52:01] [PASSED] DVI-A
[05:52:01] [PASSED] Composite
[05:52:01] [PASSED] SVIDEO
[05:52:01] [PASSED] LVDS
[05:52:01] [PASSED] Component
[05:52:01] [PASSED] DIN
[05:52:01] [PASSED] DP
[05:52:01] [PASSED] TV
[05:52:01] [PASSED] eDP
[05:52:01] [PASSED] Virtual
[05:52:01] [PASSED] DSI
[05:52:01] [PASSED] DPI
[05:52:01] [PASSED] Writeback
[05:52:01] [PASSED] SPI
[05:52:01] [PASSED] USB
[05:52:01] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[05:52:01] ============ [PASSED] drmm_connector_hdmi_init =============
[05:52:01] ============= drmm_connector_init (3 subtests) =============
[05:52:01] [PASSED] drm_test_drmm_connector_init
[05:52:01] [PASSED] drm_test_drmm_connector_init_null_ddc
[05:52:01] ========= drm_test_drmm_connector_init_type_valid =========
[05:52:01] [PASSED] Unknown
[05:52:01] [PASSED] VGA
[05:52:01] [PASSED] DVI-I
[05:52:01] [PASSED] DVI-D
[05:52:01] [PASSED] DVI-A
[05:52:01] [PASSED] Composite
[05:52:01] [PASSED] SVIDEO
[05:52:01] [PASSED] LVDS
[05:52:01] [PASSED] Component
[05:52:01] [PASSED] DIN
[05:52:01] [PASSED] DP
[05:52:01] [PASSED] HDMI-A
[05:52:01] [PASSED] HDMI-B
[05:52:01] [PASSED] TV
[05:52:01] [PASSED] eDP
[05:52:01] [PASSED] Virtual
[05:52:01] [PASSED] DSI
[05:52:01] [PASSED] DPI
[05:52:01] [PASSED] Writeback
[05:52:01] [PASSED] SPI
[05:52:01] [PASSED] USB
[05:52:01] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[05:52:01] =============== [PASSED] drmm_connector_init ===============
[05:52:01] ========= drm_connector_dynamic_init (6 subtests) ==========
[05:52:01] [PASSED] drm_test_drm_connector_dynamic_init
[05:52:01] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[05:52:01] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[05:52:01] [PASSED] drm_test_drm_connector_dynamic_init_properties
[05:52:01] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[05:52:01] [PASSED] Unknown
[05:52:01] [PASSED] VGA
[05:52:01] [PASSED] DVI-I
[05:52:01] [PASSED] DVI-D
[05:52:01] [PASSED] DVI-A
[05:52:01] [PASSED] Composite
[05:52:01] [PASSED] SVIDEO
[05:52:01] [PASSED] LVDS
[05:52:01] [PASSED] Component
[05:52:01] [PASSED] DIN
[05:52:01] [PASSED] DP
[05:52:01] [PASSED] HDMI-A
[05:52:01] [PASSED] HDMI-B
[05:52:01] [PASSED] TV
[05:52:01] [PASSED] eDP
[05:52:01] [PASSED] Virtual
[05:52:01] [PASSED] DSI
[05:52:01] [PASSED] DPI
[05:52:01] [PASSED] Writeback
[05:52:01] [PASSED] SPI
[05:52:01] [PASSED] USB
[05:52:01] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[05:52:01] ======== drm_test_drm_connector_dynamic_init_name =========
[05:52:01] [PASSED] Unknown
[05:52:01] [PASSED] VGA
[05:52:01] [PASSED] DVI-I
[05:52:01] [PASSED] DVI-D
[05:52:01] [PASSED] DVI-A
[05:52:01] [PASSED] Composite
[05:52:01] [PASSED] SVIDEO
[05:52:01] [PASSED] LVDS
[05:52:01] [PASSED] Component
[05:52:01] [PASSED] DIN
[05:52:01] [PASSED] DP
[05:52:01] [PASSED] HDMI-A
[05:52:01] [PASSED] HDMI-B
[05:52:01] [PASSED] TV
[05:52:01] [PASSED] eDP
[05:52:01] [PASSED] Virtual
[05:52:01] [PASSED] DSI
[05:52:01] [PASSED] DPI
[05:52:01] [PASSED] Writeback
[05:52:01] [PASSED] SPI
[05:52:01] [PASSED] USB
[05:52:01] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[05:52:01] =========== [PASSED] drm_connector_dynamic_init ============
[05:52:01] ==== drm_connector_dynamic_register_early (4 subtests) =====
[05:52:01] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[05:52:01] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[05:52:01] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[05:52:01] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[05:52:01] ====== [PASSED] drm_connector_dynamic_register_early =======
[05:52:01] ======= drm_connector_dynamic_register (7 subtests) ========
[05:52:01] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[05:52:01] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[05:52:01] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[05:52:01] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[05:52:01] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[05:52:01] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[05:52:01] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[05:52:01] ========= [PASSED] drm_connector_dynamic_register ==========
[05:52:01] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[05:52:01] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[05:52:01] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[05:52:01] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[05:52:01] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[05:52:01] ========== drm_test_get_tv_mode_from_name_valid ===========
[05:52:01] [PASSED] NTSC
[05:52:01] [PASSED] NTSC-443
[05:52:01] [PASSED] NTSC-J
[05:52:01] [PASSED] PAL
[05:52:01] [PASSED] PAL-M
[05:52:01] [PASSED] PAL-N
[05:52:01] [PASSED] SECAM
[05:52:01] [PASSED] Mono
[05:52:01] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[05:52:01] [PASSED] drm_test_get_tv_mode_from_name_truncated
[05:52:01] ============ [PASSED] drm_get_tv_mode_from_name ============
[05:52:01] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[05:52:01] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[05:52:01] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[05:52:01] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[05:52:01] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[05:52:01] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[05:52:01] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[05:52:01] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[05:52:01] [PASSED] VIC 96
[05:52:01] [PASSED] VIC 97
[05:52:01] [PASSED] VIC 101
[05:52:01] [PASSED] VIC 102
[05:52:01] [PASSED] VIC 106
[05:52:01] [PASSED] VIC 107
[05:52:01] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[05:52:01] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[05:52:01] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[05:52:01] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[05:52:01] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[05:52:01] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[05:52:01] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[05:52:01] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[05:52:01] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[05:52:01] [PASSED] Automatic
[05:52:01] [PASSED] Full
[05:52:01] [PASSED] Limited 16:235
[05:52:01] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[05:52:01] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[05:52:01] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[05:52:01] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[05:52:01] === drm_test_drm_hdmi_connector_get_output_format_name ====
[05:52:01] [PASSED] RGB
[05:52:01] [PASSED] YUV 4:2:0
[05:52:01] [PASSED] YUV 4:2:2
[05:52:01] [PASSED] YUV 4:4:4
[05:52:01] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[05:52:01] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[05:52:01] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[05:52:01] ============= drm_damage_helper (21 subtests) ==============
[05:52:01] [PASSED] drm_test_damage_iter_no_damage
[05:52:01] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[05:52:01] [PASSED] drm_test_damage_iter_no_damage_src_moved
[05:52:01] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[05:52:01] [PASSED] drm_test_damage_iter_no_damage_not_visible
[05:52:01] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[05:52:01] [PASSED] drm_test_damage_iter_no_damage_no_fb
[05:52:01] [PASSED] drm_test_damage_iter_simple_damage
[05:52:01] [PASSED] drm_test_damage_iter_single_damage
[05:52:01] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[05:52:01] [PASSED] drm_test_damage_iter_single_damage_outside_src
[05:52:01] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[05:52:01] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[05:52:01] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[05:52:01] [PASSED] drm_test_damage_iter_single_damage_src_moved
[05:52:01] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[05:52:01] [PASSED] drm_test_damage_iter_damage
[05:52:01] [PASSED] drm_test_damage_iter_damage_one_intersect
[05:52:01] [PASSED] drm_test_damage_iter_damage_one_outside
[05:52:01] [PASSED] drm_test_damage_iter_damage_src_moved
[05:52:01] [PASSED] drm_test_damage_iter_damage_not_visible
[05:52:01] ================ [PASSED] drm_damage_helper ================
[05:52:01] ============== drm_dp_mst_helper (3 subtests) ==============
[05:52:01] ============== drm_test_dp_mst_calc_pbn_mode ==============
[05:52:01] [PASSED] Clock 154000 BPP 30 DSC disabled
[05:52:01] [PASSED] Clock 234000 BPP 30 DSC disabled
[05:52:01] [PASSED] Clock 297000 BPP 24 DSC disabled
[05:52:01] [PASSED] Clock 332880 BPP 24 DSC enabled
[05:52:01] [PASSED] Clock 324540 BPP 24 DSC enabled
[05:52:01] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[05:52:01] ============== drm_test_dp_mst_calc_pbn_div ===============
[05:52:01] [PASSED] Link rate 2000000 lane count 4
[05:52:01] [PASSED] Link rate 2000000 lane count 2
[05:52:01] [PASSED] Link rate 2000000 lane count 1
[05:52:01] [PASSED] Link rate 1350000 lane count 4
[05:52:01] [PASSED] Link rate 1350000 lane count 2
[05:52:01] [PASSED] Link rate 1350000 lane count 1
[05:52:01] [PASSED] Link rate 1000000 lane count 4
[05:52:01] [PASSED] Link rate 1000000 lane count 2
[05:52:01] [PASSED] Link rate 1000000 lane count 1
[05:52:01] [PASSED] Link rate 810000 lane count 4
[05:52:01] [PASSED] Link rate 810000 lane count 2
[05:52:01] [PASSED] Link rate 810000 lane count 1
[05:52:01] [PASSED] Link rate 540000 lane count 4
[05:52:01] [PASSED] Link rate 540000 lane count 2
[05:52:01] [PASSED] Link rate 540000 lane count 1
[05:52:01] [PASSED] Link rate 270000 lane count 4
[05:52:01] [PASSED] Link rate 270000 lane count 2
[05:52:01] [PASSED] Link rate 270000 lane count 1
[05:52:01] [PASSED] Link rate 162000 lane count 4
[05:52:01] [PASSED] Link rate 162000 lane count 2
[05:52:01] [PASSED] Link rate 162000 lane count 1
[05:52:01] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[05:52:01] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[05:52:01] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[05:52:01] [PASSED] DP_POWER_UP_PHY with port number
[05:52:01] [PASSED] DP_POWER_DOWN_PHY with port number
[05:52:01] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[05:52:01] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[05:52:01] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[05:52:01] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[05:52:01] [PASSED] DP_QUERY_PAYLOAD with port number
[05:52:01] [PASSED] DP_QUERY_PAYLOAD with VCPI
[05:52:01] [PASSED] DP_REMOTE_DPCD_READ with port number
[05:52:01] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[05:52:01] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[05:52:01] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[05:52:01] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[05:52:01] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[05:52:01] [PASSED] DP_REMOTE_I2C_READ with port number
[05:52:01] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[05:52:01] [PASSED] DP_REMOTE_I2C_READ with transactions array
[05:52:01] [PASSED] DP_REMOTE_I2C_WRITE with port number
[05:52:01] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[05:52:01] [PASSED] DP_REMOTE_I2C_WRITE with data array
[05:52:01] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[05:52:01] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[05:52:01] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[05:52:01] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[05:52:01] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[05:52:01] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[05:52:01] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[05:52:01] ================ [PASSED] drm_dp_mst_helper ================
[05:52:01] ================== drm_exec (7 subtests) ===================
[05:52:01] [PASSED] sanitycheck
[05:52:01] [PASSED] test_lock
[05:52:01] [PASSED] test_lock_unlock
[05:52:01] [PASSED] test_duplicates
[05:52:01] [PASSED] test_prepare
[05:52:01] [PASSED] test_prepare_array
[05:52:01] [PASSED] test_multiple_loops
[05:52:01] ==================== [PASSED] drm_exec =====================
[05:52:01] =========== drm_format_helper_test (17 subtests) ===========
[05:52:01] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[05:52:01] [PASSED] single_pixel_source_buffer
[05:52:01] [PASSED] single_pixel_clip_rectangle
[05:52:01] [PASSED] well_known_colors
[05:52:01] [PASSED] destination_pitch
[05:52:01] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[05:52:01] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[05:52:01] [PASSED] single_pixel_source_buffer
[05:52:01] [PASSED] single_pixel_clip_rectangle
[05:52:01] [PASSED] well_known_colors
[05:52:01] [PASSED] destination_pitch
[05:52:01] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[05:52:01] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[05:52:01] [PASSED] single_pixel_source_buffer
[05:52:01] [PASSED] single_pixel_clip_rectangle
[05:52:01] [PASSED] well_known_colors
[05:52:01] [PASSED] destination_pitch
[05:52:01] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[05:52:01] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[05:52:01] [PASSED] single_pixel_source_buffer
[05:52:01] [PASSED] single_pixel_clip_rectangle
[05:52:01] [PASSED] well_known_colors
[05:52:01] [PASSED] destination_pitch
[05:52:01] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[05:52:01] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[05:52:01] [PASSED] single_pixel_source_buffer
[05:52:01] [PASSED] single_pixel_clip_rectangle
[05:52:01] [PASSED] well_known_colors
[05:52:01] [PASSED] destination_pitch
[05:52:01] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[05:52:01] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[05:52:01] [PASSED] single_pixel_source_buffer
[05:52:01] [PASSED] single_pixel_clip_rectangle
[05:52:01] [PASSED] well_known_colors
[05:52:01] [PASSED] destination_pitch
[05:52:01] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[05:52:01] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[05:52:01] [PASSED] single_pixel_source_buffer
[05:52:01] [PASSED] single_pixel_clip_rectangle
[05:52:01] [PASSED] well_known_colors
[05:52:01] [PASSED] destination_pitch
[05:52:01] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[05:52:01] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[05:52:01] [PASSED] single_pixel_source_buffer
[05:52:01] [PASSED] single_pixel_clip_rectangle
[05:52:01] [PASSED] well_known_colors
[05:52:01] [PASSED] destination_pitch
[05:52:01] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[05:52:01] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[05:52:01] [PASSED] single_pixel_source_buffer
[05:52:01] [PASSED] single_pixel_clip_rectangle
[05:52:01] [PASSED] well_known_colors
[05:52:01] [PASSED] destination_pitch
[05:52:01] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[05:52:01] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[05:52:01] [PASSED] single_pixel_source_buffer
[05:52:01] [PASSED] single_pixel_clip_rectangle
[05:52:01] [PASSED] well_known_colors
[05:52:01] [PASSED] destination_pitch
[05:52:01] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[05:52:01] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[05:52:01] [PASSED] single_pixel_source_buffer
[05:52:01] [PASSED] single_pixel_clip_rectangle
[05:52:01] [PASSED] well_known_colors
[05:52:01] [PASSED] destination_pitch
[05:52:01] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[05:52:01] ============== drm_test_fb_xrgb8888_to_mono ===============
[05:52:01] [PASSED] single_pixel_source_buffer
[05:52:01] [PASSED] single_pixel_clip_rectangle
[05:52:01] [PASSED] well_known_colors
[05:52:01] [PASSED] destination_pitch
[05:52:01] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[05:52:01] ==================== drm_test_fb_swab =====================
[05:52:01] [PASSED] single_pixel_source_buffer
[05:52:01] [PASSED] single_pixel_clip_rectangle
[05:52:01] [PASSED] well_known_colors
[05:52:01] [PASSED] destination_pitch
[05:52:01] ================ [PASSED] drm_test_fb_swab =================
[05:52:01] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[05:52:01] [PASSED] single_pixel_source_buffer
[05:52:01] [PASSED] single_pixel_clip_rectangle
[05:52:01] [PASSED] well_known_colors
[05:52:01] [PASSED] destination_pitch
[05:52:01] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[05:52:01] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[05:52:01] [PASSED] single_pixel_source_buffer
[05:52:01] [PASSED] single_pixel_clip_rectangle
[05:52:01] [PASSED] well_known_colors
[05:52:01] [PASSED] destination_pitch
[05:52:01] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[05:52:01] ================= drm_test_fb_clip_offset =================
[05:52:01] [PASSED] pass through
[05:52:01] [PASSED] horizontal offset
[05:52:01] [PASSED] vertical offset
[05:52:01] [PASSED] horizontal and vertical offset
[05:52:01] [PASSED] horizontal offset (custom pitch)
[05:52:01] [PASSED] vertical offset (custom pitch)
[05:52:01] [PASSED] horizontal and vertical offset (custom pitch)
[05:52:01] ============= [PASSED] drm_test_fb_clip_offset =============
[05:52:01] =================== drm_test_fb_memcpy ====================
[05:52:01] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[05:52:01] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[05:52:01] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[05:52:01] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[05:52:01] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[05:52:01] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[05:52:01] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[05:52:01] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[05:52:01] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[05:52:01] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[05:52:01] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[05:52:01] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[05:52:01] =============== [PASSED] drm_test_fb_memcpy ================
[05:52:01] ============= [PASSED] drm_format_helper_test ==============
[05:52:01] ================= drm_format (18 subtests) =================
[05:52:01] [PASSED] drm_test_format_block_width_invalid
[05:52:01] [PASSED] drm_test_format_block_width_one_plane
[05:52:01] [PASSED] drm_test_format_block_width_two_plane
[05:52:01] [PASSED] drm_test_format_block_width_three_plane
[05:52:01] [PASSED] drm_test_format_block_width_tiled
[05:52:01] [PASSED] drm_test_format_block_height_invalid
[05:52:01] [PASSED] drm_test_format_block_height_one_plane
[05:52:01] [PASSED] drm_test_format_block_height_two_plane
[05:52:01] [PASSED] drm_test_format_block_height_three_plane
[05:52:01] [PASSED] drm_test_format_block_height_tiled
[05:52:01] [PASSED] drm_test_format_min_pitch_invalid
[05:52:01] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[05:52:01] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[05:52:01] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[05:52:01] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[05:52:01] [PASSED] drm_test_format_min_pitch_two_plane
[05:52:01] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[05:52:01] [PASSED] drm_test_format_min_pitch_tiled
[05:52:01] =================== [PASSED] drm_format ====================
[05:52:01] ============== drm_framebuffer (10 subtests) ===============
[05:52:01] ========== drm_test_framebuffer_check_src_coords ==========
[05:52:01] [PASSED] Success: source fits into fb
[05:52:01] [PASSED] Fail: overflowing fb with x-axis coordinate
[05:52:01] [PASSED] Fail: overflowing fb with y-axis coordinate
[05:52:01] [PASSED] Fail: overflowing fb with source width
[05:52:01] [PASSED] Fail: overflowing fb with source height
[05:52:01] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[05:52:01] [PASSED] drm_test_framebuffer_cleanup
[05:52:01] =============== drm_test_framebuffer_create ===============
[05:52:01] [PASSED] ABGR8888 normal sizes
[05:52:01] [PASSED] ABGR8888 max sizes
[05:52:01] [PASSED] ABGR8888 pitch greater than min required
[05:52:01] [PASSED] ABGR8888 pitch less than min required
[05:52:01] [PASSED] ABGR8888 Invalid width
[05:52:01] [PASSED] ABGR8888 Invalid buffer handle
[05:52:01] [PASSED] No pixel format
[05:52:01] [PASSED] ABGR8888 Width 0
[05:52:01] [PASSED] ABGR8888 Height 0
[05:52:01] [PASSED] ABGR8888 Out of bound height * pitch combination
[05:52:01] [PASSED] ABGR8888 Large buffer offset
[05:52:01] [PASSED] ABGR8888 Buffer offset for inexistent plane
[05:52:01] [PASSED] ABGR8888 Invalid flag
[05:52:01] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[05:52:01] [PASSED] ABGR8888 Valid buffer modifier
[05:52:01] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[05:52:01] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[05:52:01] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[05:52:01] [PASSED] NV12 Normal sizes
[05:52:01] [PASSED] NV12 Max sizes
[05:52:01] [PASSED] NV12 Invalid pitch
[05:52:01] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[05:52:01] [PASSED] NV12 different modifier per-plane
[05:52:01] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[05:52:01] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[05:52:01] [PASSED] NV12 Modifier for inexistent plane
[05:52:01] [PASSED] NV12 Handle for inexistent plane
[05:52:01] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[05:52:01] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[05:52:01] [PASSED] YVU420 Normal sizes
[05:52:01] [PASSED] YVU420 Max sizes
[05:52:01] [PASSED] YVU420 Invalid pitch
[05:52:01] [PASSED] YVU420 Different pitches
[05:52:01] [PASSED] YVU420 Different buffer offsets/pitches
[05:52:01] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[05:52:01] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[05:52:01] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[05:52:01] [PASSED] YVU420 Valid modifier
[05:52:01] [PASSED] YVU420 Different modifiers per plane
[05:52:01] [PASSED] YVU420 Modifier for inexistent plane
[05:52:01] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[05:52:01] [PASSED] X0L2 Normal sizes
[05:52:01] [PASSED] X0L2 Max sizes
[05:52:01] [PASSED] X0L2 Invalid pitch
[05:52:01] [PASSED] X0L2 Pitch greater than minimum required
[05:52:01] [PASSED] X0L2 Handle for inexistent plane
[05:52:01] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[05:52:01] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[05:52:01] [PASSED] X0L2 Valid modifier
[05:52:01] [PASSED] X0L2 Modifier for inexistent plane
[05:52:01] =========== [PASSED] drm_test_framebuffer_create ===========
[05:52:01] [PASSED] drm_test_framebuffer_free
[05:52:01] [PASSED] drm_test_framebuffer_init
[05:52:01] [PASSED] drm_test_framebuffer_init_bad_format
[05:52:01] [PASSED] drm_test_framebuffer_init_dev_mismatch
[05:52:01] [PASSED] drm_test_framebuffer_lookup
[05:52:01] [PASSED] drm_test_framebuffer_lookup_inexistent
[05:52:01] [PASSED] drm_test_framebuffer_modifiers_not_supported
[05:52:01] ================= [PASSED] drm_framebuffer =================
[05:52:01] ================ drm_gem_shmem (8 subtests) ================
[05:52:01] [PASSED] drm_gem_shmem_test_obj_create
[05:52:01] [PASSED] drm_gem_shmem_test_obj_create_private
[05:52:01] [PASSED] drm_gem_shmem_test_pin_pages
[05:52:01] [PASSED] drm_gem_shmem_test_vmap
[05:52:01] [PASSED] drm_gem_shmem_test_get_pages_sgt
[05:52:01] [PASSED] drm_gem_shmem_test_get_sg_table
[05:52:01] [PASSED] drm_gem_shmem_test_madvise
[05:52:01] [PASSED] drm_gem_shmem_test_purge
[05:52:01] ================== [PASSED] drm_gem_shmem ==================
[05:52:01] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[05:52:01] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[05:52:01] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[05:52:01] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[05:52:01] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[05:52:01] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[05:52:01] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[05:52:01] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[05:52:01] [PASSED] Automatic
[05:52:01] [PASSED] Full
[05:52:01] [PASSED] Limited 16:235
[05:52:01] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[05:52:01] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[05:52:01] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[05:52:01] [PASSED] drm_test_check_disable_connector
[05:52:01] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[05:52:01] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[05:52:01] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[05:52:01] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[05:52:01] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[05:52:01] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[05:52:01] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[05:52:01] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[05:52:01] [PASSED] drm_test_check_output_bpc_dvi
[05:52:01] [PASSED] drm_test_check_output_bpc_format_vic_1
[05:52:01] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[05:52:01] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[05:52:01] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[05:52:01] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[05:52:01] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[05:52:01] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[05:52:01] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[05:52:01] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[05:52:01] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[05:52:01] [PASSED] drm_test_check_broadcast_rgb_value
[05:52:01] [PASSED] drm_test_check_bpc_8_value
[05:52:01] [PASSED] drm_test_check_bpc_10_value
[05:52:01] [PASSED] drm_test_check_bpc_12_value
[05:52:01] [PASSED] drm_test_check_format_value
[05:52:01] [PASSED] drm_test_check_tmds_char_value
[05:52:01] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[05:52:01] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[05:52:01] [PASSED] drm_test_check_mode_valid
[05:52:01] [PASSED] drm_test_check_mode_valid_reject
[05:52:01] [PASSED] drm_test_check_mode_valid_reject_rate
[05:52:01] [PASSED] drm_test_check_mode_valid_reject_max_clock
[05:52:01] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[05:52:01] ================= drm_managed (2 subtests) =================
[05:52:01] [PASSED] drm_test_managed_release_action
[05:52:01] [PASSED] drm_test_managed_run_action
[05:52:01] =================== [PASSED] drm_managed ===================
[05:52:01] =================== drm_mm (6 subtests) ====================
[05:52:01] [PASSED] drm_test_mm_init
[05:52:01] [PASSED] drm_test_mm_debug
[05:52:01] [PASSED] drm_test_mm_align32
[05:52:01] [PASSED] drm_test_mm_align64
[05:52:01] [PASSED] drm_test_mm_lowest
[05:52:01] [PASSED] drm_test_mm_highest
[05:52:01] ===================== [PASSED] drm_mm ======================
[05:52:01] ============= drm_modes_analog_tv (5 subtests) =============
[05:52:01] [PASSED] drm_test_modes_analog_tv_mono_576i
[05:52:01] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[05:52:01] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[05:52:01] [PASSED] drm_test_modes_analog_tv_pal_576i
[05:52:01] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[05:52:01] =============== [PASSED] drm_modes_analog_tv ===============
[05:52:01] ============== drm_plane_helper (2 subtests) ===============
[05:52:01] =============== drm_test_check_plane_state ================
[05:52:01] [PASSED] clipping_simple
[05:52:01] [PASSED] clipping_rotate_reflect
[05:52:01] [PASSED] positioning_simple
[05:52:01] [PASSED] upscaling
[05:52:01] [PASSED] downscaling
[05:52:01] [PASSED] rounding1
[05:52:01] [PASSED] rounding2
[05:52:01] [PASSED] rounding3
[05:52:01] [PASSED] rounding4
[05:52:01] =========== [PASSED] drm_test_check_plane_state ============
[05:52:01] =========== drm_test_check_invalid_plane_state ============
[05:52:01] [PASSED] positioning_invalid
[05:52:01] [PASSED] upscaling_invalid
[05:52:01] [PASSED] downscaling_invalid
[05:52:01] ======= [PASSED] drm_test_check_invalid_plane_state ========
[05:52:01] ================ [PASSED] drm_plane_helper =================
[05:52:01] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[05:52:01] ====== drm_test_connector_helper_tv_get_modes_check =======
[05:52:01] [PASSED] None
[05:52:01] [PASSED] PAL
[05:52:01] [PASSED] NTSC
[05:52:01] [PASSED] Both, NTSC Default
[05:52:01] [PASSED] Both, PAL Default
[05:52:01] [PASSED] Both, NTSC Default, with PAL on command-line
[05:52:01] [PASSED] Both, PAL Default, with NTSC on command-line
[05:52:01] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[05:52:01] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[05:52:01] ================== drm_rect (9 subtests) ===================
[05:52:01] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[05:52:01] [PASSED] drm_test_rect_clip_scaled_not_clipped
[05:52:01] [PASSED] drm_test_rect_clip_scaled_clipped
[05:52:01] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[05:52:01] ================= drm_test_rect_intersect =================
[05:52:01] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[05:52:01] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[05:52:01] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[05:52:01] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[05:52:01] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[05:52:01] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[05:52:01] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[05:52:01] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[05:52:01] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[05:52:01] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[05:52:01] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[05:52:01] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[05:52:01] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[05:52:01] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[05:52:01] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[05:52:01] ============= [PASSED] drm_test_rect_intersect =============
[05:52:01] ================ drm_test_rect_calc_hscale ================
[05:52:01] [PASSED] normal use
[05:52:01] [PASSED] out of max range
[05:52:01] [PASSED] out of min range
[05:52:01] [PASSED] zero dst
[05:52:01] [PASSED] negative src
[05:52:01] [PASSED] negative dst
[05:52:01] ============ [PASSED] drm_test_rect_calc_hscale ============
[05:52:01] ================ drm_test_rect_calc_vscale ================
[05:52:01] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[05:52:01] [PASSED] out of max range
[05:52:01] [PASSED] out of min range
[05:52:01] [PASSED] zero dst
[05:52:01] [PASSED] negative src
[05:52:01] [PASSED] negative dst
[05:52:01] ============ [PASSED] drm_test_rect_calc_vscale ============
[05:52:01] ================== drm_test_rect_rotate ===================
[05:52:01] [PASSED] reflect-x
[05:52:01] [PASSED] reflect-y
[05:52:01] [PASSED] rotate-0
[05:52:01] [PASSED] rotate-90
[05:52:01] [PASSED] rotate-180
[05:52:01] [PASSED] rotate-270
[05:52:01] ============== [PASSED] drm_test_rect_rotate ===============
[05:52:01] ================ drm_test_rect_rotate_inv =================
[05:52:01] [PASSED] reflect-x
[05:52:01] [PASSED] reflect-y
[05:52:01] [PASSED] rotate-0
[05:52:01] [PASSED] rotate-90
[05:52:01] [PASSED] rotate-180
[05:52:01] [PASSED] rotate-270
[05:52:01] ============ [PASSED] drm_test_rect_rotate_inv =============
[05:52:01] ==================== [PASSED] drm_rect =====================
[05:52:01] ============ drm_sysfb_modeset_test (1 subtest) ============
[05:52:01] ============ drm_test_sysfb_build_fourcc_list =============
[05:52:01] [PASSED] no native formats
[05:52:01] [PASSED] XRGB8888 as native format
[05:52:01] [PASSED] remove duplicates
[05:52:01] [PASSED] convert alpha formats
[05:52:01] [PASSED] random formats
[05:52:01] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[05:52:01] ============= [PASSED] drm_sysfb_modeset_test ==============
[05:52:01] ================== drm_fixp (2 subtests) ===================
[05:52:01] [PASSED] drm_test_int2fixp
[05:52:01] [PASSED] drm_test_sm2fixp
[05:52:01] ==================== [PASSED] drm_fixp =====================
[05:52:01] ============================================================
[05:52:01] Testing complete. Ran 624 tests: passed: 624
[05:52:01] Elapsed time: 51.911s total, 2.604s configuring, 48.582s building, 0.693s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[05:52:01] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[05:52:04] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[05:52:20] Starting KUnit Kernel (1/1)...
[05:52:20] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[05:52:20] ================= ttm_device (5 subtests) ==================
[05:52:20] [PASSED] ttm_device_init_basic
[05:52:20] [PASSED] ttm_device_init_multiple
[05:52:20] [PASSED] ttm_device_fini_basic
[05:52:20] [PASSED] ttm_device_init_no_vma_man
[05:52:20] ================== ttm_device_init_pools ==================
[05:52:20] [PASSED] No DMA allocations, no DMA32 required
[05:52:20] [PASSED] DMA allocations, DMA32 required
[05:52:20] [PASSED] No DMA allocations, DMA32 required
[05:52:20] [PASSED] DMA allocations, no DMA32 required
[05:52:20] ============== [PASSED] ttm_device_init_pools ==============
[05:52:20] =================== [PASSED] ttm_device ====================
[05:52:20] ================== ttm_pool (8 subtests) ===================
[05:52:20] ================== ttm_pool_alloc_basic ===================
[05:52:20] [PASSED] One page
[05:52:20] [PASSED] More than one page
[05:52:20] [PASSED] Above the allocation limit
[05:52:20] [PASSED] One page, with coherent DMA mappings enabled
[05:52:20] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[05:52:20] ============== [PASSED] ttm_pool_alloc_basic ===============
[05:52:20] ============== ttm_pool_alloc_basic_dma_addr ==============
[05:52:20] [PASSED] One page
[05:52:20] [PASSED] More than one page
[05:52:20] [PASSED] Above the allocation limit
[05:52:20] [PASSED] One page, with coherent DMA mappings enabled
[05:52:20] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[05:52:20] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[05:52:20] [PASSED] ttm_pool_alloc_order_caching_match
[05:52:20] [PASSED] ttm_pool_alloc_caching_mismatch
[05:52:20] [PASSED] ttm_pool_alloc_order_mismatch
[05:52:20] [PASSED] ttm_pool_free_dma_alloc
[05:52:20] [PASSED] ttm_pool_free_no_dma_alloc
[05:52:20] [PASSED] ttm_pool_fini_basic
[05:52:20] ==================== [PASSED] ttm_pool =====================
[05:52:20] ================ ttm_resource (8 subtests) =================
[05:52:20] ================= ttm_resource_init_basic =================
[05:52:20] [PASSED] Init resource in TTM_PL_SYSTEM
[05:52:20] [PASSED] Init resource in TTM_PL_VRAM
[05:52:20] [PASSED] Init resource in a private placement
[05:52:20] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[05:52:20] ============= [PASSED] ttm_resource_init_basic =============
[05:52:20] [PASSED] ttm_resource_init_pinned
[05:52:20] [PASSED] ttm_resource_fini_basic
[05:52:20] [PASSED] ttm_resource_manager_init_basic
[05:52:20] [PASSED] ttm_resource_manager_usage_basic
[05:52:20] [PASSED] ttm_resource_manager_set_used_basic
[05:52:20] [PASSED] ttm_sys_man_alloc_basic
[05:52:20] [PASSED] ttm_sys_man_free_basic
[05:52:20] ================== [PASSED] ttm_resource ===================
[05:52:20] =================== ttm_tt (15 subtests) ===================
[05:52:20] ==================== ttm_tt_init_basic ====================
[05:52:20] [PASSED] Page-aligned size
[05:52:20] [PASSED] Extra pages requested
[05:52:20] ================ [PASSED] ttm_tt_init_basic ================
[05:52:20] [PASSED] ttm_tt_init_misaligned
[05:52:20] [PASSED] ttm_tt_fini_basic
[05:52:20] [PASSED] ttm_tt_fini_sg
[05:52:20] [PASSED] ttm_tt_fini_shmem
[05:52:20] [PASSED] ttm_tt_create_basic
[05:52:20] [PASSED] ttm_tt_create_invalid_bo_type
[05:52:20] [PASSED] ttm_tt_create_ttm_exists
[05:52:20] [PASSED] ttm_tt_create_failed
[05:52:20] [PASSED] ttm_tt_destroy_basic
[05:52:20] [PASSED] ttm_tt_populate_null_ttm
[05:52:20] [PASSED] ttm_tt_populate_populated_ttm
[05:52:20] [PASSED] ttm_tt_unpopulate_basic
[05:52:20] [PASSED] ttm_tt_unpopulate_empty_ttm
[05:52:20] [PASSED] ttm_tt_swapin_basic
[05:52:20] ===================== [PASSED] ttm_tt ======================
[05:52:20] =================== ttm_bo (14 subtests) ===================
[05:52:20] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[05:52:20] [PASSED] Cannot be interrupted and sleeps
[05:52:20] [PASSED] Cannot be interrupted, locks straight away
[05:52:20] [PASSED] Can be interrupted, sleeps
[05:52:20] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[05:52:20] [PASSED] ttm_bo_reserve_locked_no_sleep
[05:52:20] [PASSED] ttm_bo_reserve_no_wait_ticket
[05:52:21] [PASSED] ttm_bo_reserve_double_resv
[05:52:21] [PASSED] ttm_bo_reserve_interrupted
[05:52:21] [PASSED] ttm_bo_reserve_deadlock
[05:52:21] [PASSED] ttm_bo_unreserve_basic
[05:52:21] [PASSED] ttm_bo_unreserve_pinned
[05:52:21] [PASSED] ttm_bo_unreserve_bulk
[05:52:21] [PASSED] ttm_bo_fini_basic
[05:52:21] [PASSED] ttm_bo_fini_shared_resv
[05:52:21] [PASSED] ttm_bo_pin_basic
[05:52:21] [PASSED] ttm_bo_pin_unpin_resource
[05:52:21] [PASSED] ttm_bo_multiple_pin_one_unpin
[05:52:21] ===================== [PASSED] ttm_bo ======================
[05:52:21] ============== ttm_bo_validate (21 subtests) ===============
[05:52:21] ============== ttm_bo_init_reserved_sys_man ===============
[05:52:21] [PASSED] Buffer object for userspace
[05:52:21] [PASSED] Kernel buffer object
[05:52:21] [PASSED] Shared buffer object
[05:52:21] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[05:52:21] ============== ttm_bo_init_reserved_mock_man ==============
[05:52:21] [PASSED] Buffer object for userspace
[05:52:21] [PASSED] Kernel buffer object
[05:52:21] [PASSED] Shared buffer object
[05:52:21] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[05:52:21] [PASSED] ttm_bo_init_reserved_resv
[05:52:21] ================== ttm_bo_validate_basic ==================
[05:52:21] [PASSED] Buffer object for userspace
[05:52:21] [PASSED] Kernel buffer object
[05:52:21] [PASSED] Shared buffer object
[05:52:21] ============== [PASSED] ttm_bo_validate_basic ==============
[05:52:21] [PASSED] ttm_bo_validate_invalid_placement
[05:52:21] ============= ttm_bo_validate_same_placement ==============
[05:52:21] [PASSED] System manager
[05:52:21] [PASSED] VRAM manager
[05:52:21] ========= [PASSED] ttm_bo_validate_same_placement ==========
[05:52:21] [PASSED] ttm_bo_validate_failed_alloc
[05:52:21] [PASSED] ttm_bo_validate_pinned
[05:52:21] [PASSED] ttm_bo_validate_busy_placement
[05:52:21] ================ ttm_bo_validate_multihop =================
[05:52:21] [PASSED] Buffer object for userspace
[05:52:21] [PASSED] Kernel buffer object
[05:52:21] [PASSED] Shared buffer object
[05:52:21] ============ [PASSED] ttm_bo_validate_multihop =============
[05:52:21] ========== ttm_bo_validate_no_placement_signaled ==========
[05:52:21] [PASSED] Buffer object in system domain, no page vector
[05:52:21] [PASSED] Buffer object in system domain with an existing page vector
[05:52:21] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[05:52:21] ======== ttm_bo_validate_no_placement_not_signaled ========
[05:52:21] [PASSED] Buffer object for userspace
[05:52:21] [PASSED] Kernel buffer object
[05:52:21] [PASSED] Shared buffer object
[05:52:21] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[05:52:21] [PASSED] ttm_bo_validate_move_fence_signaled
[05:52:21] ========= ttm_bo_validate_move_fence_not_signaled =========
[05:52:21] [PASSED] Waits for GPU
[05:52:21] [PASSED] Tries to lock straight away
[05:52:21] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[05:52:21] [PASSED] ttm_bo_validate_happy_evict
[05:52:21] [PASSED] ttm_bo_validate_all_pinned_evict
[05:52:21] [PASSED] ttm_bo_validate_allowed_only_evict
[05:52:21] [PASSED] ttm_bo_validate_deleted_evict
[05:52:21] [PASSED] ttm_bo_validate_busy_domain_evict
[05:52:21] [PASSED] ttm_bo_validate_evict_gutting
[05:52:21] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[05:52:21] ================= [PASSED] ttm_bo_validate =================
[05:52:21] ============================================================
[05:52:21] Testing complete. Ran 101 tests: passed: 101
[05:52:21] Elapsed time: 19.216s total, 2.564s configuring, 16.380s building, 0.217s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 22+ messages in thread
* ✓ Xe.CI.BAT: success for Page Reclamation Support for Xe3p Platforms (rev6)
2025-12-10 1:45 [PATCH v5 00/10] Page Reclamation Support for Xe3p Platforms Brian Nguyen
` (11 preceding siblings ...)
2025-12-11 5:52 ` ✓ CI.KUnit: success " Patchwork
@ 2025-12-11 7:17 ` Patchwork
2025-12-11 14:04 ` ✗ Xe.CI.Full: failure " Patchwork
13 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2025-12-11 7:17 UTC (permalink / raw)
To: Brian Nguyen; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 1102 bytes --]
== Series Details ==
Series: Page Reclamation Support for Xe3p Platforms (rev6)
URL : https://patchwork.freedesktop.org/series/157698/
State : success
== Summary ==
CI Bug Log - changes from xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b_BAT -> xe-pw-157698v6_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (12 -> 12)
------------------------------
No changes in participating hosts
Changes
-------
No changes found
Build changes
-------------
* IGT: IGT_8663 -> IGT_8664
* Linux: xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b -> xe-pw-157698v6
IGT_8663: aca02d1cc9804e5f1868b0ebfba6426e2d1244fc @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
IGT_8664: 28cc709ad89c0ef569569f19f4772d4cca354963 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b: 3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b
xe-pw-157698v6: 157698v6
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/index.html
[-- Attachment #2: Type: text/html, Size: 1664 bytes --]
^ permalink raw reply [flat|nested] 22+ messages in thread
* ✗ Xe.CI.Full: failure for Page Reclamation Support for Xe3p Platforms (rev6)
2025-12-10 1:45 [PATCH v5 00/10] Page Reclamation Support for Xe3p Platforms Brian Nguyen
` (12 preceding siblings ...)
2025-12-11 7:17 ` ✓ Xe.CI.BAT: " Patchwork
@ 2025-12-11 14:04 ` Patchwork
2025-12-11 19:50 ` Nguyen, Brian3
13 siblings, 1 reply; 22+ messages in thread
From: Patchwork @ 2025-12-11 14:04 UTC (permalink / raw)
To: Brian Nguyen; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 38627 bytes --]
== Series Details ==
Series: Page Reclamation Support for Xe3p Platforms (rev6)
URL : https://patchwork.freedesktop.org/series/157698/
State : failure
== Summary ==
CI Bug Log - changes from xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b_FULL -> xe-pw-157698v6_FULL
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-157698v6_FULL absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-157698v6_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (2 -> 2)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-157698v6_FULL:
### IGT changes ###
#### Possible regressions ####
* igt@kms_cursor_legacy@cursorb-vs-flipa-legacy:
- shard-bmg: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b/shard-bmg-2/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-3/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html
Known issues
------------
Here are the changes found in xe-pw-157698v6_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_async_flips@alternate-sync-async-flip:
- shard-bmg: [PASS][3] -> [FAIL][4] ([Intel XE#3718] / [Intel XE#6078])
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b/shard-bmg-5/igt@kms_async_flips@alternate-sync-async-flip.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-5/igt@kms_async_flips@alternate-sync-async-flip.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-a-dp-2:
- shard-bmg: [PASS][5] -> [FAIL][6] ([Intel XE#6078])
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b/shard-bmg-5/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-dp-2.html
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-5/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-dp-2.html
* igt@kms_big_fb@linear-8bpp-rotate-270:
- shard-bmg: NOTRUN -> [SKIP][7] ([Intel XE#2327]) +1 other test skip
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-2/igt@kms_big_fb@linear-8bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180:
- shard-bmg: NOTRUN -> [SKIP][8] ([Intel XE#1124]) +10 other tests skip
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-4/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-90:
- shard-lnl: NOTRUN -> [SKIP][9] ([Intel XE#1124]) +1 other test skip
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-lnl-3/igt@kms_big_fb@yf-tiled-64bpp-rotate-90.html
* igt@kms_bw@connected-linear-tiling-1-displays-2560x1440p:
- shard-bmg: [PASS][10] -> [SKIP][11] ([Intel XE#367])
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b/shard-bmg-8/igt@kms_bw@connected-linear-tiling-1-displays-2560x1440p.html
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-6/igt@kms_bw@connected-linear-tiling-1-displays-2560x1440p.html
* igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p:
- shard-lnl: NOTRUN -> [SKIP][12] ([Intel XE#2191])
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-lnl-5/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html
* igt@kms_bw@linear-tiling-2-displays-2160x1440p:
- shard-bmg: NOTRUN -> [SKIP][13] ([Intel XE#367]) +1 other test skip
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-5/igt@kms_bw@linear-tiling-2-displays-2160x1440p.html
* igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-mc-ccs:
- shard-lnl: NOTRUN -> [SKIP][14] ([Intel XE#2887]) +1 other test skip
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-lnl-8/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-mc-ccs.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs@pipe-c-dp-2:
- shard-bmg: NOTRUN -> [SKIP][15] ([Intel XE#2652] / [Intel XE#787]) +8 other tests skip
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-6/igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs@pipe-c-dp-2.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc:
- shard-lnl: NOTRUN -> [SKIP][16] ([Intel XE#3432])
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-lnl-8/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc:
- shard-bmg: NOTRUN -> [SKIP][17] ([Intel XE#2887]) +7 other tests skip
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-3/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc.html
* igt@kms_cdclk@mode-transition-all-outputs:
- shard-bmg: NOTRUN -> [SKIP][18] ([Intel XE#2724])
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-8/igt@kms_cdclk@mode-transition-all-outputs.html
* igt@kms_chamelium_color@ctm-negative:
- shard-lnl: NOTRUN -> [SKIP][19] ([Intel XE#306])
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-lnl-1/igt@kms_chamelium_color@ctm-negative.html
* igt@kms_chamelium_color@ctm-red-to-blue:
- shard-bmg: NOTRUN -> [SKIP][20] ([Intel XE#2325])
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-3/igt@kms_chamelium_color@ctm-red-to-blue.html
* igt@kms_chamelium_frames@hdmi-crc-single:
- shard-bmg: NOTRUN -> [SKIP][21] ([Intel XE#2252]) +3 other tests skip
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-6/igt@kms_chamelium_frames@hdmi-crc-single.html
* igt@kms_chamelium_hpd@dp-hpd-enable-disable-mode:
- shard-lnl: NOTRUN -> [SKIP][22] ([Intel XE#373]) +1 other test skip
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-lnl-1/igt@kms_chamelium_hpd@dp-hpd-enable-disable-mode.html
* igt@kms_content_protection@uevent:
- shard-bmg: NOTRUN -> [FAIL][23] ([Intel XE#6707]) +1 other test fail
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-4/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@cursor-offscreen-32x32:
- shard-bmg: NOTRUN -> [SKIP][24] ([Intel XE#2320]) +3 other tests skip
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-5/igt@kms_cursor_crc@cursor-offscreen-32x32.html
* igt@kms_cursor_crc@cursor-random-256x85:
- shard-lnl: NOTRUN -> [SKIP][25] ([Intel XE#1424]) +2 other tests skip
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-lnl-1/igt@kms_cursor_crc@cursor-random-256x85.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x512:
- shard-lnl: NOTRUN -> [SKIP][26] ([Intel XE#2321])
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-lnl-3/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
- shard-lnl: NOTRUN -> [SKIP][27] ([Intel XE#309])
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-lnl-4/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-3:
- shard-bmg: NOTRUN -> [SKIP][28] ([Intel XE#1340])
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-5/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-3.html
* igt@kms_dsc@dsc-with-output-formats:
- shard-bmg: NOTRUN -> [SKIP][29] ([Intel XE#2244]) +1 other test skip
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-2/igt@kms_dsc@dsc-with-output-formats.html
* igt@kms_flip@2x-flip-vs-expired-vblank@ac-dp2-hdmi-a3:
- shard-bmg: [PASS][30] -> [FAIL][31] ([Intel XE#3321]) +1 other test fail
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b/shard-bmg-8/igt@kms_flip@2x-flip-vs-expired-vblank@ac-dp2-hdmi-a3.html
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-8/igt@kms_flip@2x-flip-vs-expired-vblank@ac-dp2-hdmi-a3.html
* igt@kms_flip@flip-vs-expired-vblank@b-edp1:
- shard-lnl: [PASS][32] -> [FAIL][33] ([Intel XE#301]) +1 other test fail
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling:
- shard-lnl: NOTRUN -> [SKIP][34] ([Intel XE#1401] / [Intel XE#1745])
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-lnl-5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling@pipe-a-default-mode:
- shard-lnl: NOTRUN -> [SKIP][35] ([Intel XE#1401])
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-lnl-5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling:
- shard-bmg: NOTRUN -> [SKIP][36] ([Intel XE#2293] / [Intel XE#2380]) +1 other test skip
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode:
- shard-bmg: NOTRUN -> [SKIP][37] ([Intel XE#2293]) +1 other test skip
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-5/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode.html
* igt@kms_force_connector_basic@force-connector-state:
- shard-lnl: NOTRUN -> [SKIP][38] ([Intel XE#352])
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-lnl-5/igt@kms_force_connector_basic@force-connector-state.html
* igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-mmap-wc:
- shard-lnl: NOTRUN -> [SKIP][39] ([Intel XE#651]) +1 other test skip
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-lnl-5/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-render:
- shard-bmg: NOTRUN -> [SKIP][40] ([Intel XE#2311]) +14 other tests skip
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-lnl: NOTRUN -> [SKIP][41] ([Intel XE#656]) +9 other tests skip
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-lnl-8/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-tiling-linear:
- shard-bmg: NOTRUN -> [SKIP][42] ([Intel XE#4141]) +9 other tests skip
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-tiling-linear.html
* igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-shrfb-draw-render:
- shard-lnl: NOTRUN -> [SKIP][43] ([Intel XE#6312])
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-lnl-5/igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-pgflip-blt:
- shard-bmg: NOTRUN -> [SKIP][44] ([Intel XE#2313]) +19 other tests skip
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-pgflip-blt.html
* igt@kms_hdr@bpc-switch@pipe-a-dp-2:
- shard-bmg: [PASS][45] -> [ABORT][46] ([Intel XE#6740]) +3 other tests abort
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b/shard-bmg-2/igt@kms_hdr@bpc-switch@pipe-a-dp-2.html
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-8/igt@kms_hdr@bpc-switch@pipe-a-dp-2.html
* igt@kms_hdr@static-toggle:
- shard-lnl: NOTRUN -> [SKIP][47] ([Intel XE#1503])
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-lnl-5/igt@kms_hdr@static-toggle.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-lnl: NOTRUN -> [SKIP][48] ([Intel XE#356])
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-lnl-1/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_plane@pixel-format-source-clamping@pipe-b-plane-0:
- shard-lnl: NOTRUN -> [FAIL][49] ([Intel XE#5195]) +2 other tests fail
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-lnl-8/igt@kms_plane@pixel-format-source-clamping@pipe-b-plane-0.html
* igt@kms_plane_multiple@2x-tiling-yf:
- shard-bmg: NOTRUN -> [SKIP][50] ([Intel XE#5021])
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-2/igt@kms_plane_multiple@2x-tiling-yf.html
* igt@kms_pm_backlight@bad-brightness:
- shard-bmg: NOTRUN -> [SKIP][51] ([Intel XE#870])
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-2/igt@kms_pm_backlight@bad-brightness.html
* igt@kms_pm_dc@dc3co-vpb-simulation:
- shard-bmg: NOTRUN -> [SKIP][52] ([Intel XE#2391])
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-2/igt@kms_pm_dc@dc3co-vpb-simulation.html
* igt@kms_pm_dc@dc6-psr:
- shard-bmg: NOTRUN -> [SKIP][53] ([Intel XE#2392])
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-2/igt@kms_pm_dc@dc6-psr.html
* igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf:
- shard-lnl: NOTRUN -> [SKIP][54] ([Intel XE#1406] / [Intel XE#2893] / [Intel XE#4608])
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-lnl-2/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf@pipe-b-edp-1:
- shard-lnl: NOTRUN -> [SKIP][55] ([Intel XE#1406] / [Intel XE#4608]) +1 other test skip
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-lnl-2/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf@pipe-b-edp-1.html
* igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area-big-fb:
- shard-bmg: NOTRUN -> [SKIP][56] ([Intel XE#1406] / [Intel XE#1489]) +4 other tests skip
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-4/igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area-big-fb.html
* igt@kms_psr@pr-dpms:
- shard-lnl: NOTRUN -> [SKIP][57] ([Intel XE#1406])
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-lnl-5/igt@kms_psr@pr-dpms.html
* igt@kms_psr@psr2-no-drrs:
- shard-bmg: NOTRUN -> [SKIP][58] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +5 other tests skip
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-3/igt@kms_psr@psr2-no-drrs.html
* igt@kms_psr@psr2-primary-render:
- shard-bmg: NOTRUN -> [SKIP][59] ([Intel XE#1406] / [Intel XE#2234])
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-2/igt@kms_psr@psr2-primary-render.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
- shard-lnl: NOTRUN -> [SKIP][60] ([Intel XE#3414] / [Intel XE#3904])
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-lnl-5/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
* igt@kms_rotation_crc@sprite-rotation-90:
- shard-bmg: NOTRUN -> [SKIP][61] ([Intel XE#3414] / [Intel XE#3904]) +1 other test skip
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-8/igt@kms_rotation_crc@sprite-rotation-90.html
* igt@kms_sharpness_filter@invalid-filter-with-scaler:
- shard-bmg: NOTRUN -> [SKIP][62] ([Intel XE#6503]) +1 other test skip
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-2/igt@kms_sharpness_filter@invalid-filter-with-scaler.html
* igt@xe_compute_preempt@compute-preempt-many-vram:
- shard-lnl: NOTRUN -> [SKIP][63] ([Intel XE#5191])
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-lnl-2/igt@xe_compute_preempt@compute-preempt-many-vram.html
* igt@xe_eudebug@discovery-empty-clients:
- shard-lnl: NOTRUN -> [SKIP][64] ([Intel XE#4837])
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-lnl-2/igt@xe_eudebug@discovery-empty-clients.html
* igt@xe_eudebug@vma-ufence:
- shard-bmg: NOTRUN -> [SKIP][65] ([Intel XE#4837]) +4 other tests skip
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-3/igt@xe_eudebug@vma-ufence.html
* igt@xe_eudebug_online@pagefault-one-of-many:
- shard-bmg: NOTRUN -> [SKIP][66] ([Intel XE#6665])
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-4/igt@xe_eudebug_online@pagefault-one-of-many.html
* igt@xe_eudebug_online@resume-dss:
- shard-lnl: NOTRUN -> [SKIP][67] ([Intel XE#4837] / [Intel XE#6665]) +1 other test skip
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-lnl-8/igt@xe_eudebug_online@resume-dss.html
* igt@xe_eudebug_online@single-step-one:
- shard-bmg: NOTRUN -> [SKIP][68] ([Intel XE#4837] / [Intel XE#6665]) +2 other tests skip
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-3/igt@xe_eudebug_online@single-step-one.html
* igt@xe_evict@evict-beng-cm-threads-large-multi-vm:
- shard-lnl: NOTRUN -> [SKIP][69] ([Intel XE#688]) +1 other test skip
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-lnl-3/igt@xe_evict@evict-beng-cm-threads-large-multi-vm.html
* igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate-race:
- shard-lnl: NOTRUN -> [SKIP][70] ([Intel XE#1392]) +1 other test skip
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-lnl-5/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate-race.html
* igt@xe_exec_basic@multigpu-once-userptr-rebind:
- shard-bmg: NOTRUN -> [SKIP][71] ([Intel XE#2322]) +4 other tests skip
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-4/igt@xe_exec_basic@multigpu-once-userptr-rebind.html
* igt@xe_exec_system_allocator@many-64k-mmap-free-huge:
- shard-bmg: NOTRUN -> [SKIP][72] ([Intel XE#5007])
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-3/igt@xe_exec_system_allocator@many-64k-mmap-free-huge.html
* igt@xe_exec_system_allocator@process-many-large-execqueues-mmap-new-huge:
- shard-bmg: NOTRUN -> [SKIP][73] ([Intel XE#4943]) +13 other tests skip
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-6/igt@xe_exec_system_allocator@process-many-large-execqueues-mmap-new-huge.html
* igt@xe_exec_system_allocator@threads-shared-vm-many-large-mmap-new-huge-nomemset:
- shard-lnl: NOTRUN -> [SKIP][74] ([Intel XE#4943]) +3 other tests skip
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-lnl-5/igt@xe_exec_system_allocator@threads-shared-vm-many-large-mmap-new-huge-nomemset.html
* igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv:
- shard-bmg: NOTRUN -> [ABORT][75] ([Intel XE#5466] / [Intel XE#5530])
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-6/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
* igt@xe_module_load@load:
- shard-bmg: ([PASS][76], [PASS][77], [PASS][78], [PASS][79], [PASS][80], [PASS][81], [PASS][82], [PASS][83], [PASS][84], [PASS][85], [PASS][86], [PASS][87], [PASS][88], [PASS][89], [PASS][90], [PASS][91], [PASS][92], [PASS][93], [PASS][94], [PASS][95], [PASS][96], [PASS][97], [PASS][98], [PASS][99], [PASS][100]) -> ([PASS][101], [PASS][102], [PASS][103], [PASS][104], [PASS][105], [PASS][106], [SKIP][107], [PASS][108], [PASS][109], [PASS][110], [PASS][111], [PASS][112], [PASS][113], [PASS][114], [PASS][115], [PASS][116], [PASS][117], [PASS][118], [PASS][119], [PASS][120], [PASS][121], [PASS][122], [PASS][123], [PASS][124]) ([Intel XE#2457])
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b/shard-bmg-6/igt@xe_module_load@load.html
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b/shard-bmg-1/igt@xe_module_load@load.html
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b/shard-bmg-3/igt@xe_module_load@load.html
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b/shard-bmg-4/igt@xe_module_load@load.html
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b/shard-bmg-5/igt@xe_module_load@load.html
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b/shard-bmg-5/igt@xe_module_load@load.html
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b/shard-bmg-5/igt@xe_module_load@load.html
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b/shard-bmg-3/igt@xe_module_load@load.html
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b/shard-bmg-3/igt@xe_module_load@load.html
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b/shard-bmg-3/igt@xe_module_load@load.html
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b/shard-bmg-4/igt@xe_module_load@load.html
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b/shard-bmg-2/igt@xe_module_load@load.html
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b/shard-bmg-8/igt@xe_module_load@load.html
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b/shard-bmg-8/igt@xe_module_load@load.html
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b/shard-bmg-2/igt@xe_module_load@load.html
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b/shard-bmg-4/igt@xe_module_load@load.html
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b/shard-bmg-8/igt@xe_module_load@load.html
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b/shard-bmg-8/igt@xe_module_load@load.html
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b/shard-bmg-1/igt@xe_module_load@load.html
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b/shard-bmg-1/igt@xe_module_load@load.html
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b/shard-bmg-2/igt@xe_module_load@load.html
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b/shard-bmg-5/igt@xe_module_load@load.html
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b/shard-bmg-6/igt@xe_module_load@load.html
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b/shard-bmg-6/igt@xe_module_load@load.html
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b/shard-bmg-6/igt@xe_module_load@load.html
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-5/igt@xe_module_load@load.html
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-2/igt@xe_module_load@load.html
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-2/igt@xe_module_load@load.html
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-1/igt@xe_module_load@load.html
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-1/igt@xe_module_load@load.html
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-1/igt@xe_module_load@load.html
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-2/igt@xe_module_load@load.html
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-6/igt@xe_module_load@load.html
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-4/igt@xe_module_load@load.html
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-4/igt@xe_module_load@load.html
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-5/igt@xe_module_load@load.html
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-3/igt@xe_module_load@load.html
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-2/igt@xe_module_load@load.html
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-2/igt@xe_module_load@load.html
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-8/igt@xe_module_load@load.html
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-8/igt@xe_module_load@load.html
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-8/igt@xe_module_load@load.html
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-6/igt@xe_module_load@load.html
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-3/igt@xe_module_load@load.html
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-5/igt@xe_module_load@load.html
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-6/igt@xe_module_load@load.html
[122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-3/igt@xe_module_load@load.html
[123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-4/igt@xe_module_load@load.html
[124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-4/igt@xe_module_load@load.html
* igt@xe_pat@pat-index-xelp:
- shard-lnl: NOTRUN -> [SKIP][125] ([Intel XE#977])
[125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-lnl-8/igt@xe_pat@pat-index-xelp.html
* igt@xe_pm@s2idle-d3cold-basic-exec:
- shard-bmg: NOTRUN -> [SKIP][126] ([Intel XE#2284]) +1 other test skip
[126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-1/igt@xe_pm@s2idle-d3cold-basic-exec.html
* igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_copy0:
- shard-lnl: [PASS][127] -> [FAIL][128] ([Intel XE#6251])
[127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b/shard-lnl-2/igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_copy0.html
[128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-lnl-3/igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_copy0.html
* igt@xe_pxp@display-pxp-fb:
- shard-bmg: NOTRUN -> [SKIP][129] ([Intel XE#4733]) +3 other tests skip
[129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-2/igt@xe_pxp@display-pxp-fb.html
* igt@xe_query@multigpu-query-gt-list:
- shard-lnl: NOTRUN -> [SKIP][130] ([Intel XE#944]) +1 other test skip
[130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-lnl-3/igt@xe_query@multigpu-query-gt-list.html
* igt@xe_query@multigpu-query-topology-l3-bank-mask:
- shard-bmg: NOTRUN -> [SKIP][131] ([Intel XE#944]) +1 other test skip
[131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-3/igt@xe_query@multigpu-query-topology-l3-bank-mask.html
#### Possible fixes ####
* igt@kms_async_flips@async-flip-with-page-flip-events-linear-atomic@pipe-c-edp-1:
- shard-lnl: [FAIL][132] ([Intel XE#6054]) -> [PASS][133]
[132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b/shard-lnl-1/igt@kms_async_flips@async-flip-with-page-flip-events-linear-atomic@pipe-c-edp-1.html
[133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-lnl-8/igt@kms_async_flips@async-flip-with-page-flip-events-linear-atomic@pipe-c-edp-1.html
* igt@kms_cursor_edge_walk@256x256-top-edge@pipe-d-dp-2:
- shard-bmg: [FAIL][134] -> [PASS][135] +2 other tests pass
[134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b/shard-bmg-2/igt@kms_cursor_edge_walk@256x256-top-edge@pipe-d-dp-2.html
[135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-1/igt@kms_cursor_edge_walk@256x256-top-edge@pipe-d-dp-2.html
* igt@kms_flip@flip-vs-suspend@c-hdmi-a3:
- shard-bmg: [INCOMPLETE][136] ([Intel XE#2049] / [Intel XE#2597]) -> [PASS][137] +1 other test pass
[136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b/shard-bmg-2/igt@kms_flip@flip-vs-suspend@c-hdmi-a3.html
[137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-3/igt@kms_flip@flip-vs-suspend@c-hdmi-a3.html
* igt@kms_flip@modeset-vs-vblank-race@d-dp2:
- shard-bmg: [FAIL][138] ([Intel XE#3650]) -> [PASS][139] +6 other tests pass
[138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b/shard-bmg-6/igt@kms_flip@modeset-vs-vblank-race@d-dp2.html
[139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-4/igt@kms_flip@modeset-vs-vblank-race@d-dp2.html
* igt@xe_pmu@engine-activity-accuracy-50:
- shard-lnl: [FAIL][140] ([Intel XE#6251]) -> [PASS][141] +1 other test pass
[140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b/shard-lnl-5/igt@xe_pmu@engine-activity-accuracy-50.html
[141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-lnl-3/igt@xe_pmu@engine-activity-accuracy-50.html
#### Warnings ####
* igt@kms_async_flips@async-flip-with-page-flip-events-linear-atomic:
- shard-lnl: [FAIL][142] ([Intel XE#6054] / [Intel XE#6676]) -> [FAIL][143] ([Intel XE#6676])
[142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b/shard-lnl-1/igt@kms_async_flips@async-flip-with-page-flip-events-linear-atomic.html
[143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-lnl-8/igt@kms_async_flips@async-flip-with-page-flip-events-linear-atomic.html
* igt@kms_hdr@brightness-with-hdr:
- shard-bmg: [SKIP][144] ([Intel XE#3374] / [Intel XE#3544]) -> [SKIP][145] ([Intel XE#3544])
[144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b/shard-bmg-5/igt@kms_hdr@brightness-with-hdr.html
[145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-4/igt@kms_hdr@brightness-with-hdr.html
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1340]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1340
[Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
[Intel XE#1401]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1401
[Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
[Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
[Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
[Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
[Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
[Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
[Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
[Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
[Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
[Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
[Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
[Intel XE#2391]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2391
[Intel XE#2392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2392
[Intel XE#2457]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2457
[Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
[Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
[Intel XE#2724]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2724
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
[Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
[Intel XE#3321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3321
[Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
[Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
[Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
[Intel XE#352]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/352
[Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
[Intel XE#356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/356
[Intel XE#3650]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3650
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#3718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3718
[Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
[Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
[Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
[Intel XE#4608]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4608
[Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
[Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
[Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
[Intel XE#5007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5007
[Intel XE#5021]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5021
[Intel XE#5191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5191
[Intel XE#5195]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5195
[Intel XE#5466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5466
[Intel XE#5530]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5530
[Intel XE#6054]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6054
[Intel XE#6078]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6078
[Intel XE#6251]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6251
[Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
[Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
[Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
[Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
[Intel XE#6665]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6665
[Intel XE#6676]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6676
[Intel XE#6707]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6707
[Intel XE#6740]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6740
[Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
[Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
[Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
[Intel XE#977]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/977
Build changes
-------------
* IGT: IGT_8663 -> IGT_8664
* Linux: xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b -> xe-pw-157698v6
IGT_8663: aca02d1cc9804e5f1868b0ebfba6426e2d1244fc @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
IGT_8664: 28cc709ad89c0ef569569f19f4772d4cca354963 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b: 3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b
xe-pw-157698v6: 157698v6
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/index.html
[-- Attachment #2: Type: text/html, Size: 43287 bytes --]
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: ✗ Xe.CI.Full: failure for Page Reclamation Support for Xe3p Platforms (rev6)
2025-12-11 14:04 ` ✗ Xe.CI.Full: failure " Patchwork
@ 2025-12-11 19:50 ` Nguyen, Brian3
0 siblings, 0 replies; 22+ messages in thread
From: Nguyen, Brian3 @ 2025-12-11 19:50 UTC (permalink / raw)
To: intel-xe
On 12/11/2025 6:04 AM, Patchwork wrote:
> *Patch Details*
> *Series:* Page Reclamation Support for Xe3p Platforms (rev6)
> *URL:* https://patchwork.freedesktop.org/series/157698/ <https://patchwork.freedesktop.org/series/157698/>
> *State:* failure
> *Details:* https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/index.html <https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/index.html>
>
>
> CI Bug Log - changes from xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b_FULL -> xe-pw-157698v6_FULL
>
>
> Summary
>
> *FAILURE*
>
> Serious unknown changes coming with xe-pw-157698v6_FULL absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in xe-pw-157698v6_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
>
> Participating hosts (2 -> 2)
>
> No changes in participating hosts
>
>
> Possible new issues
>
> Here are the unknown changes that may have been introduced in xe-pw-157698v6_FULL:
>
>
> IGT changes
>
>
> Possible regressions
>
> * igt@kms_cursor_legacy@cursorb-vs-flipa-legacy:
> o shard-bmg: PASS <https://intel-gfx-ci.01.org/tree/intel-xe/xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b/shard-bmg-2/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html> -> INCOMPLETE <https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157698v6/shard-bmg-3/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html>
>
Should be a random failure in test case. Unrelated to changes made in patchset.
Brian
> Build changes
>
> * IGT: IGT_8663 -> IGT_8664
> * Linux: xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b -> xe-pw-157698v6
>
> IGT_8663: aca02d1cc9804e5f1868b0ebfba6426e2d1244fc @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> IGT_8664: 28cc709ad89c0ef569569f19f4772d4cca354963 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> xe-4220-3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b: 3adb3f4aa5a8563ee9c1f6e137827b740e3ab40b
> xe-pw-157698v6: 157698v6
>
^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2025-12-11 19:51 UTC | newest]
Thread overview: 22+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-12-10 1:45 [PATCH v5 00/10] Page Reclamation Support for Xe3p Platforms Brian Nguyen
2025-12-10 1:45 ` [PATCH v5 01/10] drm/xe: Do not forward invalid TLB invalidation seqnos to upper layers Brian Nguyen
2025-12-10 1:45 ` [PATCH v5 02/10] drm/xe/xe_tlb_inval: Modify fence interface to support PPC flush Brian Nguyen
2025-12-10 5:32 ` Upadhyay, Tejas
2025-12-10 1:45 ` [PATCH v5 03/10] drm/xe: Add page reclamation info to device info Brian Nguyen
2025-12-10 1:45 ` [PATCH v5 04/10] drm/xe/guc: Add page reclamation interface to GuC Brian Nguyen
2025-12-10 1:45 ` [PATCH v5 05/10] drm/xe: Create page reclaim list on unbind Brian Nguyen
2025-12-10 2:13 ` Matthew Brost
2025-12-10 1:45 ` [PATCH v5 06/10] drm/xe: Suballocate BO for page reclaim Brian Nguyen
2025-12-10 1:45 ` [PATCH v5 07/10] drm/xe: Prep page reclaim in tlb inval job Brian Nguyen
2025-12-10 2:15 ` Matthew Brost
2025-12-10 1:45 ` [PATCH v5 08/10] drm/xe: Append page reclamation action to tlb inval Brian Nguyen
2025-12-10 1:45 ` [PATCH v5 09/10] drm/xe: Optimize flushing of L2$ by skipping unnecessary page reclaim Brian Nguyen
2025-12-10 6:08 ` Upadhyay, Tejas
2025-12-10 6:19 ` Matthew Brost
2025-12-10 6:49 ` Upadhyay, Tejas
2025-12-10 1:45 ` [PATCH v5 10/10] drm/xe: Add debugfs support for page reclamation Brian Nguyen
2025-12-11 5:50 ` ✗ CI.checkpatch: warning for Page Reclamation Support for Xe3p Platforms (rev6) Patchwork
2025-12-11 5:52 ` ✓ CI.KUnit: success " Patchwork
2025-12-11 7:17 ` ✓ Xe.CI.BAT: " Patchwork
2025-12-11 14:04 ` ✗ Xe.CI.Full: failure " Patchwork
2025-12-11 19:50 ` Nguyen, Brian3
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