Re: [PATCH] drm/xe/nvm: enable cri platform

[Raag Jadav <raag.jadav@intel.com>]

On Mon, Dec 15, 2025 at 02:59:28PM +0200, Alexander Usyskin wrote:
> Mark CRI as one that have CSC NVM device.
> Update the writable override flow to take the
> information from survivability register for CRI.

Quite a bit of trailing space, please use it.

> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_nvm.c | 35 ++++++++++++++++++++++++-----------
>  drivers/gpu/drm/xe/xe_pci.c |  1 +
>  2 files changed, 25 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_nvm.c b/drivers/gpu/drm/xe/xe_nvm.c
> index 33f4ac82fc80..87b7b0120f7c 100644
> --- a/drivers/gpu/drm/xe/xe_nvm.c
> +++ b/drivers/gpu/drm/xe/xe_nvm.c
> @@ -10,6 +10,7 @@
>  #include "xe_device_types.h"
>  #include "xe_mmio.h"
>  #include "xe_nvm.h"
> +#include "xe_pcode_api.h"
>  #include "regs/xe_gsc_regs.h"
>  #include "xe_sriov.h"
>  
> @@ -45,39 +46,51 @@ static bool xe_nvm_non_posted_erase(struct xe_device *xe)
>  {
>  	struct xe_mmio *mmio = xe_root_tile_mmio(xe);
>  
> -	if (xe->info.platform != XE_BATTLEMAGE)
> +	switch (xe->info.platform) {
> +	case XE_CRESCENTISLAND:
> +		fallthrough;

Is standalone fallthrough a thing?

Raag

> +	case XE_BATTLEMAGE:
> +		return !(xe_mmio_read32(mmio, XE_REG(GEN12_CNTL_PROTECTED_NVM_REG)) &
> +			 NVM_NON_POSTED_ERASE_CHICKEN_BIT);
> +	default:
>  		return false;
> -	return !(xe_mmio_read32(mmio, XE_REG(GEN12_CNTL_PROTECTED_NVM_REG)) &
> -		 NVM_NON_POSTED_ERASE_CHICKEN_BIT);
> +	}
>  }