[PATCH v3 0/4] drm/xe/hwmon: Expose new temperature attributes

[PATCH v3 0/4] drm/xe/hwmon: Expose new temperature attributes

[Karthik Poosa]

Expose tempX_emergency and tempX_crit for package and vram,
representing shutdown and critical temperature thresholds.
These values are read via pcode thermal mailbox commands.

These are read using pcode thermal mailbox commands

v2: 
 - Expose memory controller, pcie and individual vram
   temperatures also.
 - Addressed some of review comments of v1 from KVP.

v3:
 - Combine patches 1,2,3 into patch 1.
 - Combine patches 4,5 to patch 2.
 - Addressed review comments from v2.
 - Update kernel version in Xe hwmon documentation.

Karthik Poosa (4):
  drm/xe/hwmon: Expose temperature limits
  drm/xe/hwmon: Expose memory controller temperature
  drm/xe/hwmon: Expose GPU pcie temperature
  drm/xe/hwmon: Expose individual vram temperature

 .../ABI/testing/sysfs-driver-intel-xe-hwmon   | 112 +++++++
 drivers/gpu/drm/xe/regs/xe_pcode_regs.h       |   2 +
 drivers/gpu/drm/xe/xe_device_types.h          |   3 +
 drivers/gpu/drm/xe/xe_hwmon.c                 | 295 +++++++++++++++++-
 drivers/gpu/drm/xe/xe_pci.c                   |   5 +
 drivers/gpu/drm/xe/xe_pci_types.h             |   1 +
 drivers/gpu/drm/xe/xe_pcode_api.h             |   7 +
 7 files changed, 415 insertions(+), 10 deletions(-)

-- 
2.25.1

[PATCH v3 1/4] drm/xe/hwmon: Expose temperature limits

[Karthik Poosa]

Read temperature limits using pcode mailbox and
expose shutdown temperature limit as tempX_emergency,
critical temperature limit of as tempX_crit and
GPU average temperature limit as tempX_max.

Update Xe hwmon documentation for these entries.

Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
---
 .../ABI/testing/sysfs-driver-intel-xe-hwmon   |  40 ++++++
 drivers/gpu/drm/xe/xe_device_types.h          |   3 +
 drivers/gpu/drm/xe/xe_hwmon.c                 | 116 +++++++++++++++++-
 drivers/gpu/drm/xe/xe_pci.c                   |   5 +
 drivers/gpu/drm/xe/xe_pci_types.h             |   1 +
 drivers/gpu/drm/xe/xe_pcode_api.h             |   3 +
 6 files changed, 164 insertions(+), 4 deletions(-)

diff --git a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
index d9e2b17c6872..c8f211c336be 100644
--- a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
+++ b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
@@ -196,3 +196,43 @@ Description:	RW. Package burst power limit interval (Tau in PL2/Tau) in
 		milliseconds over which sustained power is averaged.
 
 		Only supported for particular Intel Xe graphics platforms.
+
+What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp2_emergency
+Date:		December 2025
+KernelVersion:	6.19
+Contact:	intel-xe@lists.freedesktop.org
+Description:	RO. Package shutdown temperature in millidegree Celsius.
+
+		Only supported for particular Intel Xe graphics platforms.
+
+What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp2_crit
+Date:		December 2025
+KernelVersion:	6.19
+Contact:	intel-xe@lists.freedesktop.org
+Description:	RO. Package critical temperature in millidegree Celsius.
+
+		Only supported for particular Intel Xe graphics platforms.
+
+What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp2_max
+Date:		December 2025
+KernelVersion:	6.19
+Contact:	intel-xe@lists.freedesktop.org
+Description:	RO. Package average temperature limit in millidegree Celsius.
+
+		Only supported for particular Intel Xe graphics platforms.
+
+What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp3_emergency
+Date:		December 2025
+KernelVersion:	6.19
+Contact:	intel-xe@lists.freedesktop.org
+Description:	RO. VRAM shutdown temperature in millidegree Celsius.
+
+		Only supported for particular Intel Xe graphics platforms.
+
+What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp3_crit
+Date:		December 2025
+KernelVersion:	6.19
+Contact:	intel-xe@lists.freedesktop.org
+Description:	RO. VRAM critical temperature in millidegree Celsius.
+
+		Only supported for particular Intel Xe graphics platforms.
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 413ba4c8b62e..8e6dd2665596 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -321,6 +321,9 @@ struct xe_device {
 		 * pcode mailbox commands.
 		 */
 		u8 has_mbx_power_limits:1;
+		/** @info.has_mbx_thermal_info: Device has support for thermal mailbox commands.
+		 */
+		u8 has_mbx_thermal_info:1;
 		/** @info.has_mem_copy_instr: Device supports MEM_COPY instruction */
 		u8 has_mem_copy_instr:1;
 		/** @info.has_mert: Device has standalone MERT */
diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index ff2aea52ef75..66a8c3e40027 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -53,6 +53,14 @@ enum xe_fan_channel {
 	FAN_MAX,
 };
 
+enum xe_temp_limit {
+	TEMP_LIMIT_PKG_SHUTDOWN,
+	TEMP_LIMIT_PKG_TJMAX,
+	TEMP_LIMIT_MEM_SHUTDOWN,
+	TEMP_LIMIT_PKG_CRIT,
+	TEMP_LIMIT_MEM_TJMAX,
+};
+
 /* Attribute index for powerX_xxx_interval sysfs entries */
 enum sensor_attr_power {
 	SENSOR_INDEX_PSYS_PL1,
@@ -111,6 +119,18 @@ struct xe_hwmon_fan_info {
 	u64 time_prev;
 };
 
+/**
+ * struct xe_hwmon_thermal_info - to store temperature data
+ */
+struct xe_hwmon_thermal_info {
+	union {
+		/** @limits: temperatures limits */
+		u8 limit[8];
+		/** @data: temperature limits in dwords */
+		u32 data[2];
+	};
+};
+
 /**
  * struct xe_hwmon - xe hwmon data structure
  */
@@ -137,7 +157,8 @@ struct xe_hwmon {
 	u32 pl1_on_boot[CHANNEL_MAX];
 	/** @pl2_on_boot: power limit PL2 on boot */
 	u32 pl2_on_boot[CHANNEL_MAX];
-
+	/** @temp: Temperature info */
+	struct xe_hwmon_thermal_info temp;
 };
 
 static int xe_hwmon_pcode_read_power_limit(const struct xe_hwmon *hwmon, u32 attr, int channel,
@@ -677,8 +698,11 @@ static const struct attribute_group *hwmon_groups[] = {
 };
 
 static const struct hwmon_channel_info * const hwmon_info[] = {
-	HWMON_CHANNEL_INFO(temp, HWMON_T_LABEL, HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_INPUT | HWMON_T_LABEL),
+	HWMON_CHANNEL_INFO(temp,
+			   HWMON_T_LABEL,
+			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT |
+			   HWMON_T_MAX,
+			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT),
 	HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_LABEL | HWMON_P_CRIT |
 			   HWMON_P_CAP,
 			   HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_LABEL | HWMON_P_CAP),
@@ -689,6 +713,23 @@ static const struct hwmon_channel_info * const hwmon_info[] = {
 	NULL
 };
 
+static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
+{
+	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
+	int ret = 0;
+
+	if (!hwmon->xe->info.has_mbx_power_limits)
+		return -EOPNOTSUPP;
+
+	/* Read thermal info */
+	ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_LIMITS, 0),
+			    &hwmon->temp.data[0], &hwmon->temp.data[1]);
+	drm_dbg(&hwmon->xe->drm, "thermal info read ret %d, val 0x%x val1 0x%x\n", ret,
+		hwmon->temp.data[0], hwmon->temp.data[1]);
+
+	return ret;
+}
+
 /* I1 is exposed as power_crit or as curr_crit depending on bit 31 */
 static int xe_hwmon_pcode_read_i1(const struct xe_hwmon *hwmon, u32 *uval)
 {
@@ -787,6 +828,34 @@ static umode_t
 xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 {
 	switch (attr) {
+	case hwmon_temp_emergency:
+		switch (channel) {
+		case CHANNEL_PKG:
+			return hwmon->temp.limit[TEMP_LIMIT_PKG_SHUTDOWN] ? 0444 : 0;
+		case CHANNEL_VRAM:
+			return hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN] ? 0444 : 0;
+		default:
+			return 0;
+		}
+		break;
+	case hwmon_temp_crit:
+		switch (channel) {
+		case CHANNEL_PKG:
+			return hwmon->temp.limit[TEMP_LIMIT_PKG_TJMAX] ? 0444 : 0;
+		case CHANNEL_VRAM:
+			return hwmon->temp.limit[TEMP_LIMIT_MEM_TJMAX] ? 0444 : 0;
+		default:
+			return 0;
+		}
+		break;
+	case hwmon_temp_max:
+		switch (channel) {
+		case CHANNEL_PKG:
+			return hwmon->temp.limit[TEMP_LIMIT_PKG_CRIT] ? 0444 : 0;
+		default:
+			return 0;
+		}
+		break;
 	case hwmon_temp_input:
 	case hwmon_temp_label:
 		return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_TEMP, channel)) ? 0444 : 0;
@@ -807,10 +876,46 @@ xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
 
 		/* HW register value is in degrees Celsius, convert to millidegrees. */
 		*val = REG_FIELD_GET(TEMP_MASK, reg_val) * MILLIDEGREE_PER_DEGREE;
-		return 0;
+		break;
+	case hwmon_temp_emergency:
+		switch (channel) {
+		case CHANNEL_PKG:
+			*val = hwmon->temp.limit[TEMP_LIMIT_PKG_SHUTDOWN] * MILLIDEGREE_PER_DEGREE;
+			break;
+		case CHANNEL_VRAM:
+			*val = hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN] * MILLIDEGREE_PER_DEGREE;
+			break;
+		default:
+			*val = 0;
+			return -EOPNOTSUPP;
+		}
+		break;
+	case hwmon_temp_crit:
+		switch (channel) {
+		case CHANNEL_PKG:
+			*val = hwmon->temp.limit[TEMP_LIMIT_PKG_TJMAX] * MILLIDEGREE_PER_DEGREE;
+			break;
+		case CHANNEL_VRAM:
+			*val = hwmon->temp.limit[TEMP_LIMIT_MEM_TJMAX] * MILLIDEGREE_PER_DEGREE;
+			break;
+		default:
+			*val = 0;
+			return -EOPNOTSUPP;
+		}
+		break;
+	case hwmon_temp_max:
+		switch (channel) {
+		case CHANNEL_PKG:
+			*val = hwmon->temp.limit[TEMP_LIMIT_PKG_CRIT] * MILLIDEGREE_PER_DEGREE;
+			break;
+		default:
+			return 0;
+		}
+		break;
 	default:
 		return -EOPNOTSUPP;
 	}
+	return 0;
 }
 
 static umode_t
@@ -1263,6 +1368,9 @@ xe_hwmon_get_preregistration_info(struct xe_hwmon *hwmon)
 	for (channel = 0; channel < FAN_MAX; channel++)
 		if (xe_hwmon_is_visible(hwmon, hwmon_fan, hwmon_fan_input, channel))
 			xe_hwmon_fan_input_read(hwmon, channel, &fan_speed);
+
+	if (xe_hwmon_pcode_read_thermal_info(hwmon))
+		drm_dbg(&hwmon->xe->drm, "Thermal mailbox support not present in firmware\n");
 }
 
 int xe_hwmon_register(struct xe_device *xe)
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 673761c8623e..a47637900e84 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -311,6 +311,7 @@ static const struct xe_device_desc dg2_desc = {
 	.has_display = true,
 	.has_fan_control = true,
 	.has_mbx_power_limits = false,
+	.has_mbx_thermal_info = false,
 };
 
 static const __maybe_unused struct xe_device_desc pvc_desc = {
@@ -328,6 +329,7 @@ static const __maybe_unused struct xe_device_desc pvc_desc = {
 	.vm_max_level = 4,
 	.vram_flags = XE_VRAM_FLAGS_NEED64K,
 	.has_mbx_power_limits = false,
+	.has_mbx_thermal_info = false,
 };
 
 static const struct xe_device_desc mtl_desc = {
@@ -365,6 +367,7 @@ static const struct xe_device_desc bmg_desc = {
 	.has_fan_control = true,
 	.has_flat_ccs = 1,
 	.has_mbx_power_limits = true,
+	.has_mbx_thermal_info = true,
 	.has_gsc_nvm = 1,
 	.has_heci_cscfi = 1,
 	.has_i2c = true,
@@ -418,6 +421,7 @@ static const struct xe_device_desc cri_desc = {
 	.has_flat_ccs = false,
 	.has_i2c = true,
 	.has_mbx_power_limits = true,
+	.has_mbx_thermal_info = true,
 	.has_mert = true,
 	.has_pre_prod_wa = 1,
 	.has_sriov = true,
@@ -681,6 +685,7 @@ static int xe_info_init_early(struct xe_device *xe,
 	/* runtime fusing may force flat_ccs to disabled later */
 	xe->info.has_flat_ccs = desc->has_flat_ccs;
 	xe->info.has_mbx_power_limits = desc->has_mbx_power_limits;
+	xe->info.has_mbx_thermal_info = desc->has_mbx_thermal_info;
 	xe->info.has_gsc_nvm = desc->has_gsc_nvm;
 	xe->info.has_heci_gscfi = desc->has_heci_gscfi;
 	xe->info.has_heci_cscfi = desc->has_heci_cscfi;
diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
index 3bb51d155951..34d2b66188e4 100644
--- a/drivers/gpu/drm/xe/xe_pci_types.h
+++ b/drivers/gpu/drm/xe/xe_pci_types.h
@@ -48,6 +48,7 @@ struct xe_device_desc {
 	u8 has_late_bind:1;
 	u8 has_llc:1;
 	u8 has_mbx_power_limits:1;
+	u8 has_mbx_thermal_info:1;
 	u8 has_mem_copy_instr:1;
 	u8 has_mert:1;
 	u8 has_pre_prod_wa:1;
diff --git a/drivers/gpu/drm/xe/xe_pcode_api.h b/drivers/gpu/drm/xe/xe_pcode_api.h
index 975892d6b230..a3bff76a074d 100644
--- a/drivers/gpu/drm/xe/xe_pcode_api.h
+++ b/drivers/gpu/drm/xe/xe_pcode_api.h
@@ -65,6 +65,9 @@
 #define       FAN_TABLE				1
 #define       VR_CONFIG				2
 
+#define	PCODE_THERMAL_INFO			0x25
+#define	READ_THERMAL_LIMITS			0x0
+
 #define   PCODE_FREQUENCY_CONFIG		0x6e
 /* Frequency Config Sub Commands (param1) */
 #define     PCODE_MBOX_FC_SC_READ_FUSED_P0	0x0
-- 
2.25.1

Re: [PATCH v3 1/4] drm/xe/hwmon: Expose temperature limits

[Raag Jadav]

On Tue, Dec 16, 2025 at 05:10:27PM +0530, Karthik Poosa wrote:
> Read temperature limits using pcode mailbox and
> expose shutdown temperature limit as tempX_emergency,
> critical temperature limit of as tempX_crit and
> GPU average temperature limit as tempX_max.
> 
> Update Xe hwmon documentation for these entries.
> 
> Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
> ---
>  .../ABI/testing/sysfs-driver-intel-xe-hwmon   |  40 ++++++
>  drivers/gpu/drm/xe/xe_device_types.h          |   3 +
>  drivers/gpu/drm/xe/xe_hwmon.c                 | 116 +++++++++++++++++-
>  drivers/gpu/drm/xe/xe_pci.c                   |   5 +
>  drivers/gpu/drm/xe/xe_pci_types.h             |   1 +
>  drivers/gpu/drm/xe/xe_pcode_api.h             |   3 +
>  6 files changed, 164 insertions(+), 4 deletions(-)
> 
> diff --git a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> index d9e2b17c6872..c8f211c336be 100644
> --- a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> +++ b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> @@ -196,3 +196,43 @@ Description:	RW. Package burst power limit interval (Tau in PL2/Tau) in
>  		milliseconds over which sustained power is averaged.
>  
>  		Only supported for particular Intel Xe graphics platforms.
> +
> +What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp2_emergency
> +Date:		December 2025
> +KernelVersion:	6.19
> +Contact:	intel-xe@lists.freedesktop.org
> +Description:	RO. Package shutdown temperature in millidegree Celsius.
> +
> +		Only supported for particular Intel Xe graphics platforms.
> +
> +What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp2_crit
> +Date:		December 2025
> +KernelVersion:	6.19
> +Contact:	intel-xe@lists.freedesktop.org
> +Description:	RO. Package critical temperature in millidegree Celsius.
> +
> +		Only supported for particular Intel Xe graphics platforms.
> +
> +What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp2_max
> +Date:		December 2025
> +KernelVersion:	6.19
> +Contact:	intel-xe@lists.freedesktop.org
> +Description:	RO. Package average temperature limit in millidegree Celsius.
> +
> +		Only supported for particular Intel Xe graphics platforms.
> +
> +What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp3_emergency
> +Date:		December 2025
> +KernelVersion:	6.19
> +Contact:	intel-xe@lists.freedesktop.org
> +Description:	RO. VRAM shutdown temperature in millidegree Celsius.
> +
> +		Only supported for particular Intel Xe graphics platforms.
> +
> +What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp3_crit
> +Date:		December 2025
> +KernelVersion:	6.19
> +Contact:	intel-xe@lists.freedesktop.org
> +Description:	RO. VRAM critical temperature in millidegree Celsius.
> +
> +		Only supported for particular Intel Xe graphics platforms.

As per hwmon documentation all these attributes are RW so they don't
match with ABI expectations.

> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index 413ba4c8b62e..8e6dd2665596 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -321,6 +321,9 @@ struct xe_device {
>  		 * pcode mailbox commands.
>  		 */
>  		u8 has_mbx_power_limits:1;
> +		/** @info.has_mbx_thermal_info: Device has support for thermal mailbox commands.
> +		 */

Can be one line.

> +		u8 has_mbx_thermal_info:1;
>  		/** @info.has_mem_copy_instr: Device supports MEM_COPY instruction */
>  		u8 has_mem_copy_instr:1;
>  		/** @info.has_mert: Device has standalone MERT */
> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index ff2aea52ef75..66a8c3e40027 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> @@ -53,6 +53,14 @@ enum xe_fan_channel {
>  	FAN_MAX,
>  };
>  
> +enum xe_temp_limit {
> +	TEMP_LIMIT_PKG_SHUTDOWN,
> +	TEMP_LIMIT_PKG_TJMAX,
> +	TEMP_LIMIT_MEM_SHUTDOWN,
> +	TEMP_LIMIT_PKG_CRIT,
> +	TEMP_LIMIT_MEM_TJMAX,
> +};
> +
>  /* Attribute index for powerX_xxx_interval sysfs entries */
>  enum sensor_attr_power {
>  	SENSOR_INDEX_PSYS_PL1,
> @@ -111,6 +119,18 @@ struct xe_hwmon_fan_info {
>  	u64 time_prev;
>  };
>  
> +/**
> + * struct xe_hwmon_thermal_info - to store temperature data
> + */
> +struct xe_hwmon_thermal_info {
> +	union {
> +		/** @limits: temperatures limits */
> +		u8 limit[8];

What are the magic numbers? Can we have proper defines?

> +		/** @data: temperature limits in dwords */
> +		u32 data[2];
> +	};
> +};
> +
>  /**
>   * struct xe_hwmon - xe hwmon data structure
>   */
> @@ -137,7 +157,8 @@ struct xe_hwmon {
>  	u32 pl1_on_boot[CHANNEL_MAX];
>  	/** @pl2_on_boot: power limit PL2 on boot */
>  	u32 pl2_on_boot[CHANNEL_MAX];
> -
> +	/** @temp: Temperature info */
> +	struct xe_hwmon_thermal_info temp;
>  };
>  
>  static int xe_hwmon_pcode_read_power_limit(const struct xe_hwmon *hwmon, u32 attr, int channel,
> @@ -677,8 +698,11 @@ static const struct attribute_group *hwmon_groups[] = {
>  };
>  
>  static const struct hwmon_channel_info * const hwmon_info[] = {
> -	HWMON_CHANNEL_INFO(temp, HWMON_T_LABEL, HWMON_T_INPUT | HWMON_T_LABEL,
> -			   HWMON_T_INPUT | HWMON_T_LABEL),
> +	HWMON_CHANNEL_INFO(temp,
> +			   HWMON_T_LABEL,
> +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT |
> +			   HWMON_T_MAX,
> +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT),
>  	HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_LABEL | HWMON_P_CRIT |
>  			   HWMON_P_CAP,
>  			   HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_LABEL | HWMON_P_CAP),
> @@ -689,6 +713,23 @@ static const struct hwmon_channel_info * const hwmon_info[] = {
>  	NULL
>  };
>  
> +static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
> +{
> +	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
> +	int ret = 0;
> +
> +	if (!hwmon->xe->info.has_mbx_power_limits)
> +		return -EOPNOTSUPP;
> +
> +	/* Read thermal info */
> +	ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_LIMITS, 0),
> +			    &hwmon->temp.data[0], &hwmon->temp.data[1]);
> +	drm_dbg(&hwmon->xe->drm, "thermal info read ret %d, val 0x%x val1 0x%x\n", ret,
> +		hwmon->temp.data[0], hwmon->temp.data[1]);
> +
> +	return ret;
> +}
> +
>  /* I1 is exposed as power_crit or as curr_crit depending on bit 31 */
>  static int xe_hwmon_pcode_read_i1(const struct xe_hwmon *hwmon, u32 *uval)
>  {
> @@ -787,6 +828,34 @@ static umode_t
>  xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
>  {
>  	switch (attr) {
> +	case hwmon_temp_emergency:
> +		switch (channel) {
> +		case CHANNEL_PKG:
> +			return hwmon->temp.limit[TEMP_LIMIT_PKG_SHUTDOWN] ? 0444 : 0;
> +		case CHANNEL_VRAM:
> +			return hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN] ? 0444 : 0;
> +		default:
> +			return 0;
> +		}
> +		break;
> +	case hwmon_temp_crit:
> +		switch (channel) {
> +		case CHANNEL_PKG:
> +			return hwmon->temp.limit[TEMP_LIMIT_PKG_TJMAX] ? 0444 : 0;
> +		case CHANNEL_VRAM:
> +			return hwmon->temp.limit[TEMP_LIMIT_MEM_TJMAX] ? 0444 : 0;
> +		default:
> +			return 0;
> +		}
> +		break;
> +	case hwmon_temp_max:
> +		switch (channel) {
> +		case CHANNEL_PKG:
> +			return hwmon->temp.limit[TEMP_LIMIT_PKG_CRIT] ? 0444 : 0;
> +		default:
> +			return 0;
> +		}
> +		break;
>  	case hwmon_temp_input:
>  	case hwmon_temp_label:
>  		return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_TEMP, channel)) ? 0444 : 0;
> @@ -807,10 +876,46 @@ xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
>  
>  		/* HW register value is in degrees Celsius, convert to millidegrees. */
>  		*val = REG_FIELD_GET(TEMP_MASK, reg_val) * MILLIDEGREE_PER_DEGREE;
> -		return 0;
> +		break;
> +	case hwmon_temp_emergency:
> +		switch (channel) {
> +		case CHANNEL_PKG:
> +			*val = hwmon->temp.limit[TEMP_LIMIT_PKG_SHUTDOWN] * MILLIDEGREE_PER_DEGREE;
> +			break;
> +		case CHANNEL_VRAM:
> +			*val = hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN] * MILLIDEGREE_PER_DEGREE;
> +			break;
> +		default:
> +			*val = 0;

Do you need this?

> +			return -EOPNOTSUPP;
> +		}
> +		break;
> +	case hwmon_temp_crit:
> +		switch (channel) {
> +		case CHANNEL_PKG:
> +			*val = hwmon->temp.limit[TEMP_LIMIT_PKG_TJMAX] * MILLIDEGREE_PER_DEGREE;
> +			break;
> +		case CHANNEL_VRAM:
> +			*val = hwmon->temp.limit[TEMP_LIMIT_MEM_TJMAX] * MILLIDEGREE_PER_DEGREE;
> +			break;
> +		default:
> +			*val = 0;

Ditto.

> +			return -EOPNOTSUPP;
> +		}
> +		break;
> +	case hwmon_temp_max:
> +		switch (channel) {
> +		case CHANNEL_PKG:
> +			*val = hwmon->temp.limit[TEMP_LIMIT_PKG_CRIT] * MILLIDEGREE_PER_DEGREE;
> +			break;
> +		default:
> +			return 0;
> +		}
> +		break;
>  	default:
>  		return -EOPNOTSUPP;
>  	}
> +	return 0;
>  }
>  
>  static umode_t
> @@ -1263,6 +1368,9 @@ xe_hwmon_get_preregistration_info(struct xe_hwmon *hwmon)
>  	for (channel = 0; channel < FAN_MAX; channel++)
>  		if (xe_hwmon_is_visible(hwmon, hwmon_fan, hwmon_fan_input, channel))
>  			xe_hwmon_fan_input_read(hwmon, channel, &fan_speed);
> +
> +	if (xe_hwmon_pcode_read_thermal_info(hwmon))
> +		drm_dbg(&hwmon->xe->drm, "Thermal mailbox support not present in firmware\n");
>  }
>  
>  int xe_hwmon_register(struct xe_device *xe)
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index 673761c8623e..a47637900e84 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -311,6 +311,7 @@ static const struct xe_device_desc dg2_desc = {
>  	.has_display = true,
>  	.has_fan_control = true,
>  	.has_mbx_power_limits = false,
> +	.has_mbx_thermal_info = false,

Why?

>  };
>  
>  static const __maybe_unused struct xe_device_desc pvc_desc = {
> @@ -328,6 +329,7 @@ static const __maybe_unused struct xe_device_desc pvc_desc = {
>  	.vm_max_level = 4,
>  	.vram_flags = XE_VRAM_FLAGS_NEED64K,
>  	.has_mbx_power_limits = false,
> +	.has_mbx_thermal_info = false,

Ditto.

>  };
>  
>  static const struct xe_device_desc mtl_desc = {
> @@ -365,6 +367,7 @@ static const struct xe_device_desc bmg_desc = {
>  	.has_fan_control = true,
>  	.has_flat_ccs = 1,
>  	.has_mbx_power_limits = true,
> +	.has_mbx_thermal_info = true,
>  	.has_gsc_nvm = 1,
>  	.has_heci_cscfi = 1,
>  	.has_i2c = true,
> @@ -418,6 +421,7 @@ static const struct xe_device_desc cri_desc = {
>  	.has_flat_ccs = false,
>  	.has_i2c = true,
>  	.has_mbx_power_limits = true,
> +	.has_mbx_thermal_info = true,
>  	.has_mert = true,
>  	.has_pre_prod_wa = 1,
>  	.has_sriov = true,
> @@ -681,6 +685,7 @@ static int xe_info_init_early(struct xe_device *xe,
>  	/* runtime fusing may force flat_ccs to disabled later */
>  	xe->info.has_flat_ccs = desc->has_flat_ccs;
>  	xe->info.has_mbx_power_limits = desc->has_mbx_power_limits;
> +	xe->info.has_mbx_thermal_info = desc->has_mbx_thermal_info;
>  	xe->info.has_gsc_nvm = desc->has_gsc_nvm;
>  	xe->info.has_heci_gscfi = desc->has_heci_gscfi;
>  	xe->info.has_heci_cscfi = desc->has_heci_cscfi;
> diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
> index 3bb51d155951..34d2b66188e4 100644
> --- a/drivers/gpu/drm/xe/xe_pci_types.h
> +++ b/drivers/gpu/drm/xe/xe_pci_types.h
> @@ -48,6 +48,7 @@ struct xe_device_desc {
>  	u8 has_late_bind:1;
>  	u8 has_llc:1;
>  	u8 has_mbx_power_limits:1;
> +	u8 has_mbx_thermal_info:1;
>  	u8 has_mem_copy_instr:1;
>  	u8 has_mert:1;
>  	u8 has_pre_prod_wa:1;
> diff --git a/drivers/gpu/drm/xe/xe_pcode_api.h b/drivers/gpu/drm/xe/xe_pcode_api.h
> index 975892d6b230..a3bff76a074d 100644
> --- a/drivers/gpu/drm/xe/xe_pcode_api.h
> +++ b/drivers/gpu/drm/xe/xe_pcode_api.h
> @@ -65,6 +65,9 @@
>  #define       FAN_TABLE				1
>  #define       VR_CONFIG				2
>  
> +#define	PCODE_THERMAL_INFO			0x25
> +#define	READ_THERMAL_LIMITS			0x0

Does this match with spacing convention and ordering?

Raag

>  #define   PCODE_FREQUENCY_CONFIG		0x6e
>  /* Frequency Config Sub Commands (param1) */
>  #define     PCODE_MBOX_FC_SC_READ_FUSED_P0	0x0
> -- 
> 2.25.1
> 

Re: [PATCH v3 1/4] drm/xe/hwmon: Expose temperature limits

[Poosa, Karthik]

On 17-12-2025 22:35, Raag Jadav wrote:
> On Tue, Dec 16, 2025 at 05:10:27PM +0530, Karthik Poosa wrote:
>> Read temperature limits using pcode mailbox and
>> expose shutdown temperature limit as tempX_emergency,
>> critical temperature limit of as tempX_crit and
>> GPU average temperature limit as tempX_max.
>>
>> Update Xe hwmon documentation for these entries.
>>
>> Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
>> ---
>>   .../ABI/testing/sysfs-driver-intel-xe-hwmon   |  40 ++++++
>>   drivers/gpu/drm/xe/xe_device_types.h          |   3 +
>>   drivers/gpu/drm/xe/xe_hwmon.c                 | 116 +++++++++++++++++-
>>   drivers/gpu/drm/xe/xe_pci.c                   |   5 +
>>   drivers/gpu/drm/xe/xe_pci_types.h             |   1 +
>>   drivers/gpu/drm/xe/xe_pcode_api.h             |   3 +
>>   6 files changed, 164 insertions(+), 4 deletions(-)
>>
>> diff --git a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
>> index d9e2b17c6872..c8f211c336be 100644
>> --- a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
>> +++ b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
>> @@ -196,3 +196,43 @@ Description:	RW. Package burst power limit interval (Tau in PL2/Tau) in
>>   		milliseconds over which sustained power is averaged.
>>   
>>   		Only supported for particular Intel Xe graphics platforms.
>> +
>> +What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp2_emergency
>> +Date:		December 2025
>> +KernelVersion:	6.19
>> +Contact:	intel-xe@lists.freedesktop.org
>> +Description:	RO. Package shutdown temperature in millidegree Celsius.
>> +
>> +		Only supported for particular Intel Xe graphics platforms.
>> +
>> +What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp2_crit
>> +Date:		December 2025
>> +KernelVersion:	6.19
>> +Contact:	intel-xe@lists.freedesktop.org
>> +Description:	RO. Package critical temperature in millidegree Celsius.
>> +
>> +		Only supported for particular Intel Xe graphics platforms.
>> +
>> +What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp2_max
>> +Date:		December 2025
>> +KernelVersion:	6.19
>> +Contact:	intel-xe@lists.freedesktop.org
>> +Description:	RO. Package average temperature limit in millidegree Celsius.
>> +
>> +		Only supported for particular Intel Xe graphics platforms.
>> +
>> +What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp3_emergency
>> +Date:		December 2025
>> +KernelVersion:	6.19
>> +Contact:	intel-xe@lists.freedesktop.org
>> +Description:	RO. VRAM shutdown temperature in millidegree Celsius.
>> +
>> +		Only supported for particular Intel Xe graphics platforms.
>> +
>> +What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp3_crit
>> +Date:		December 2025
>> +KernelVersion:	6.19
>> +Contact:	intel-xe@lists.freedesktop.org
>> +Description:	RO. VRAM critical temperature in millidegree Celsius.
>> +
>> +		Only supported for particular Intel Xe graphics platforms.
> As per hwmon documentation all these attributes are RW so they don't
> match with ABI expectations.

1. These are read only values for our hardware, write is not supported.

2. Couple of other drivers are also supporting readonly for temp_crit.

Ex:

a) drivers/net/ethernet/broadcom/bnxt/bnxt_hwmon.c - bnxt_hwmon_is_visible

75 static umode_t bnxt_hwmon_is_visible(const void *_data, enum 
hwmon_sensor_types type,
  76                                      u32 attr, int channel)
  77 { 82
  83         switch (attr) {
  86         case hwmon_temp_max:
  87         case hwmon_temp_crit:
  88         case hwmon_temp_emergency:
  89         case hwmon_temp_max_alarm:
  90         case hwmon_temp_crit_alarm:
  91         case hwmon_temp_emergency_alarm:
  92                 if (!(bp->fw_cap & 
BNXT_FW_CAP_THRESHOLD_TEMP_SUPPORTED))
  93                         return 0;
  94                 return 0444;

b) . drivers/hwmon/intel-m10-bmc-hwmon.c -

static const struct hwmon_ops m10bmc_hwmon_ops = {
         .visible = 0444,
         .read = m10bmc_hwmon_read,

3. hwmon also doesn't report any violation for 0444 return from 
xe_hwmon_temp_is_visible.

>> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
>> index 413ba4c8b62e..8e6dd2665596 100644
>> --- a/drivers/gpu/drm/xe/xe_device_types.h
>> +++ b/drivers/gpu/drm/xe/xe_device_types.h
>> @@ -321,6 +321,9 @@ struct xe_device {
>>   		 * pcode mailbox commands.
>>   		 */
>>   		u8 has_mbx_power_limits:1;
>> +		/** @info.has_mbx_thermal_info: Device has support for thermal mailbox commands.
>> +		 */
> Can be one line.
>
>> +		u8 has_mbx_thermal_info:1;
>>   		/** @info.has_mem_copy_instr: Device supports MEM_COPY instruction */
>>   		u8 has_mem_copy_instr:1;
>>   		/** @info.has_mert: Device has standalone MERT */
>> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
>> index ff2aea52ef75..66a8c3e40027 100644
>> --- a/drivers/gpu/drm/xe/xe_hwmon.c
>> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
>> @@ -53,6 +53,14 @@ enum xe_fan_channel {
>>   	FAN_MAX,
>>   };
>>   
>> +enum xe_temp_limit {
>> +	TEMP_LIMIT_PKG_SHUTDOWN,
>> +	TEMP_LIMIT_PKG_TJMAX,
>> +	TEMP_LIMIT_MEM_SHUTDOWN,
>> +	TEMP_LIMIT_PKG_CRIT,
>> +	TEMP_LIMIT_MEM_TJMAX,
>> +};
>> +
>>   /* Attribute index for powerX_xxx_interval sysfs entries */
>>   enum sensor_attr_power {
>>   	SENSOR_INDEX_PSYS_PL1,
>> @@ -111,6 +119,18 @@ struct xe_hwmon_fan_info {
>>   	u64 time_prev;
>>   };
>>   
>> +/**
>> + * struct xe_hwmon_thermal_info - to store temperature data
>> + */
>> +struct xe_hwmon_thermal_info {
>> +	union {
>> +		/** @limits: temperatures limits */
>> +		u8 limit[8];
> What are the magic numbers? Can we have proper defines?

We can use xe_temp_limit max value and keep remaining bytes as reserved.

>
>> +		/** @data: temperature limits in dwords */
>> +		u32 data[2];
>> +	};
>> +};
>> +
>>   /**
>>    * struct xe_hwmon - xe hwmon data structure
>>    */
>> @@ -137,7 +157,8 @@ struct xe_hwmon {
>>   	u32 pl1_on_boot[CHANNEL_MAX];
>>   	/** @pl2_on_boot: power limit PL2 on boot */
>>   	u32 pl2_on_boot[CHANNEL_MAX];
>> -
>> +	/** @temp: Temperature info */
>> +	struct xe_hwmon_thermal_info temp;
>>   };
>>   
>>   static int xe_hwmon_pcode_read_power_limit(const struct xe_hwmon *hwmon, u32 attr, int channel,
>> @@ -677,8 +698,11 @@ static const struct attribute_group *hwmon_groups[] = {
>>   };
>>   
>>   static const struct hwmon_channel_info * const hwmon_info[] = {
>> -	HWMON_CHANNEL_INFO(temp, HWMON_T_LABEL, HWMON_T_INPUT | HWMON_T_LABEL,
>> -			   HWMON_T_INPUT | HWMON_T_LABEL),
>> +	HWMON_CHANNEL_INFO(temp,
>> +			   HWMON_T_LABEL,
>> +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT |
>> +			   HWMON_T_MAX,
>> +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT),
>>   	HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_LABEL | HWMON_P_CRIT |
>>   			   HWMON_P_CAP,
>>   			   HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_LABEL | HWMON_P_CAP),
>> @@ -689,6 +713,23 @@ static const struct hwmon_channel_info * const hwmon_info[] = {
>>   	NULL
>>   };
>>   
>> +static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
>> +{
>> +	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
>> +	int ret = 0;
>> +
>> +	if (!hwmon->xe->info.has_mbx_power_limits)
>> +		return -EOPNOTSUPP;
>> +
>> +	/* Read thermal info */
>> +	ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_LIMITS, 0),
>> +			    &hwmon->temp.data[0], &hwmon->temp.data[1]);
>> +	drm_dbg(&hwmon->xe->drm, "thermal info read ret %d, val 0x%x val1 0x%x\n", ret,
>> +		hwmon->temp.data[0], hwmon->temp.data[1]);
>> +
>> +	return ret;
>> +}
>> +
>>   /* I1 is exposed as power_crit or as curr_crit depending on bit 31 */
>>   static int xe_hwmon_pcode_read_i1(const struct xe_hwmon *hwmon, u32 *uval)
>>   {
>> @@ -787,6 +828,34 @@ static umode_t
>>   xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
>>   {
>>   	switch (attr) {
>> +	case hwmon_temp_emergency:
>> +		switch (channel) {
>> +		case CHANNEL_PKG:
>> +			return hwmon->temp.limit[TEMP_LIMIT_PKG_SHUTDOWN] ? 0444 : 0;
>> +		case CHANNEL_VRAM:
>> +			return hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN] ? 0444 : 0;
>> +		default:
>> +			return 0;
>> +		}
>> +		break;
>> +	case hwmon_temp_crit:
>> +		switch (channel) {
>> +		case CHANNEL_PKG:
>> +			return hwmon->temp.limit[TEMP_LIMIT_PKG_TJMAX] ? 0444 : 0;
>> +		case CHANNEL_VRAM:
>> +			return hwmon->temp.limit[TEMP_LIMIT_MEM_TJMAX] ? 0444 : 0;
>> +		default:
>> +			return 0;
>> +		}
>> +		break;
>> +	case hwmon_temp_max:
>> +		switch (channel) {
>> +		case CHANNEL_PKG:
>> +			return hwmon->temp.limit[TEMP_LIMIT_PKG_CRIT] ? 0444 : 0;
>> +		default:
>> +			return 0;
>> +		}
>> +		break;
>>   	case hwmon_temp_input:
>>   	case hwmon_temp_label:
>>   		return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_TEMP, channel)) ? 0444 : 0;
>> @@ -807,10 +876,46 @@ xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
>>   
>>   		/* HW register value is in degrees Celsius, convert to millidegrees. */
>>   		*val = REG_FIELD_GET(TEMP_MASK, reg_val) * MILLIDEGREE_PER_DEGREE;
>> -		return 0;
>> +		break;
>> +	case hwmon_temp_emergency:
>> +		switch (channel) {
>> +		case CHANNEL_PKG:
>> +			*val = hwmon->temp.limit[TEMP_LIMIT_PKG_SHUTDOWN] * MILLIDEGREE_PER_DEGREE;
>> +			break;
>> +		case CHANNEL_VRAM:
>> +			*val = hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN] * MILLIDEGREE_PER_DEGREE;
>> +			break;
>> +		default:
>> +			*val = 0;
> Do you need this?
>
>> +			return -EOPNOTSUPP;
>> +		}
>> +		break;
>> +	case hwmon_temp_crit:
>> +		switch (channel) {
>> +		case CHANNEL_PKG:
>> +			*val = hwmon->temp.limit[TEMP_LIMIT_PKG_TJMAX] * MILLIDEGREE_PER_DEGREE;
>> +			break;
>> +		case CHANNEL_VRAM:
>> +			*val = hwmon->temp.limit[TEMP_LIMIT_MEM_TJMAX] * MILLIDEGREE_PER_DEGREE;
>> +			break;
>> +		default:
>> +			*val = 0;
> Ditto.
>
>> +			return -EOPNOTSUPP;
>> +		}
>> +		break;
>> +	case hwmon_temp_max:
>> +		switch (channel) {
>> +		case CHANNEL_PKG:
>> +			*val = hwmon->temp.limit[TEMP_LIMIT_PKG_CRIT] * MILLIDEGREE_PER_DEGREE;
>> +			break;
>> +		default:
>> +			return 0;
>> +		}
>> +		break;
>>   	default:
>>   		return -EOPNOTSUPP;
>>   	}
>> +	return 0;
>>   }
>>   
>>   static umode_t
>> @@ -1263,6 +1368,9 @@ xe_hwmon_get_preregistration_info(struct xe_hwmon *hwmon)
>>   	for (channel = 0; channel < FAN_MAX; channel++)
>>   		if (xe_hwmon_is_visible(hwmon, hwmon_fan, hwmon_fan_input, channel))
>>   			xe_hwmon_fan_input_read(hwmon, channel, &fan_speed);
>> +
>> +	if (xe_hwmon_pcode_read_thermal_info(hwmon))
>> +		drm_dbg(&hwmon->xe->drm, "Thermal mailbox support not present in firmware\n");
>>   }
>>   
>>   int xe_hwmon_register(struct xe_device *xe)
>> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
>> index 673761c8623e..a47637900e84 100644
>> --- a/drivers/gpu/drm/xe/xe_pci.c
>> +++ b/drivers/gpu/drm/xe/xe_pci.c
>> @@ -311,6 +311,7 @@ static const struct xe_device_desc dg2_desc = {
>>   	.has_display = true,
>>   	.has_fan_control = true,
>>   	.has_mbx_power_limits = false,
>> +	.has_mbx_thermal_info = false,
> Why?
>
>>   };
>>   
>>   static const __maybe_unused struct xe_device_desc pvc_desc = {
>> @@ -328,6 +329,7 @@ static const __maybe_unused struct xe_device_desc pvc_desc = {
>>   	.vm_max_level = 4,
>>   	.vram_flags = XE_VRAM_FLAGS_NEED64K,
>>   	.has_mbx_power_limits = false,
>> +	.has_mbx_thermal_info = false,
> Ditto.
>
>>   };
>>   
>>   static const struct xe_device_desc mtl_desc = {
>> @@ -365,6 +367,7 @@ static const struct xe_device_desc bmg_desc = {
>>   	.has_fan_control = true,
>>   	.has_flat_ccs = 1,
>>   	.has_mbx_power_limits = true,
>> +	.has_mbx_thermal_info = true,
>>   	.has_gsc_nvm = 1,
>>   	.has_heci_cscfi = 1,
>>   	.has_i2c = true,
>> @@ -418,6 +421,7 @@ static const struct xe_device_desc cri_desc = {
>>   	.has_flat_ccs = false,
>>   	.has_i2c = true,
>>   	.has_mbx_power_limits = true,
>> +	.has_mbx_thermal_info = true,
>>   	.has_mert = true,
>>   	.has_pre_prod_wa = 1,
>>   	.has_sriov = true,
>> @@ -681,6 +685,7 @@ static int xe_info_init_early(struct xe_device *xe,
>>   	/* runtime fusing may force flat_ccs to disabled later */
>>   	xe->info.has_flat_ccs = desc->has_flat_ccs;
>>   	xe->info.has_mbx_power_limits = desc->has_mbx_power_limits;
>> +	xe->info.has_mbx_thermal_info = desc->has_mbx_thermal_info;
>>   	xe->info.has_gsc_nvm = desc->has_gsc_nvm;
>>   	xe->info.has_heci_gscfi = desc->has_heci_gscfi;
>>   	xe->info.has_heci_cscfi = desc->has_heci_cscfi;
>> diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
>> index 3bb51d155951..34d2b66188e4 100644
>> --- a/drivers/gpu/drm/xe/xe_pci_types.h
>> +++ b/drivers/gpu/drm/xe/xe_pci_types.h
>> @@ -48,6 +48,7 @@ struct xe_device_desc {
>>   	u8 has_late_bind:1;
>>   	u8 has_llc:1;
>>   	u8 has_mbx_power_limits:1;
>> +	u8 has_mbx_thermal_info:1;
>>   	u8 has_mem_copy_instr:1;
>>   	u8 has_mert:1;
>>   	u8 has_pre_prod_wa:1;
>> diff --git a/drivers/gpu/drm/xe/xe_pcode_api.h b/drivers/gpu/drm/xe/xe_pcode_api.h
>> index 975892d6b230..a3bff76a074d 100644
>> --- a/drivers/gpu/drm/xe/xe_pcode_api.h
>> +++ b/drivers/gpu/drm/xe/xe_pcode_api.h
>> @@ -65,6 +65,9 @@
>>   #define       FAN_TABLE				1
>>   #define       VR_CONFIG				2
>>   
>> +#define	PCODE_THERMAL_INFO			0x25
>> +#define	READ_THERMAL_LIMITS			0x0
> Does this match with spacing convention and ordering?
>
> Raag
>
>>   #define   PCODE_FREQUENCY_CONFIG		0x6e
>>   /* Frequency Config Sub Commands (param1) */
>>   #define     PCODE_MBOX_FC_SC_READ_FUSED_P0	0x0
>> -- 
>> 2.25.1
>>

Re: [PATCH v3 1/4] drm/xe/hwmon: Expose temperature limits

[Raag Jadav]

On Thu, Dec 18, 2025 at 01:07:57PM +0530, Poosa, Karthik wrote:
> On 17-12-2025 22:35, Raag Jadav wrote:
> > On Tue, Dec 16, 2025 at 05:10:27PM +0530, Karthik Poosa wrote:
> > > Read temperature limits using pcode mailbox and
> > > expose shutdown temperature limit as tempX_emergency,
> > > critical temperature limit of as tempX_crit and
> > > GPU average temperature limit as tempX_max.
> > > 
> > > Update Xe hwmon documentation for these entries.
> > > 
> > > Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
> > > ---
> > >   .../ABI/testing/sysfs-driver-intel-xe-hwmon   |  40 ++++++
> > >   drivers/gpu/drm/xe/xe_device_types.h          |   3 +
> > >   drivers/gpu/drm/xe/xe_hwmon.c                 | 116 +++++++++++++++++-
> > >   drivers/gpu/drm/xe/xe_pci.c                   |   5 +
> > >   drivers/gpu/drm/xe/xe_pci_types.h             |   1 +
> > >   drivers/gpu/drm/xe/xe_pcode_api.h             |   3 +
> > >   6 files changed, 164 insertions(+), 4 deletions(-)
> > > 
> > > diff --git a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> > > index d9e2b17c6872..c8f211c336be 100644
> > > --- a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> > > +++ b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> > > @@ -196,3 +196,43 @@ Description:	RW. Package burst power limit interval (Tau in PL2/Tau) in
> > >   		milliseconds over which sustained power is averaged.
> > >   		Only supported for particular Intel Xe graphics platforms.
> > > +
> > > +What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp2_emergency
> > > +Date:		December 2025
> > > +KernelVersion:	6.19
> > > +Contact:	intel-xe@lists.freedesktop.org
> > > +Description:	RO. Package shutdown temperature in millidegree Celsius.
> > > +
> > > +		Only supported for particular Intel Xe graphics platforms.
> > > +
> > > +What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp2_crit
> > > +Date:		December 2025
> > > +KernelVersion:	6.19
> > > +Contact:	intel-xe@lists.freedesktop.org
> > > +Description:	RO. Package critical temperature in millidegree Celsius.
> > > +
> > > +		Only supported for particular Intel Xe graphics platforms.
> > > +
> > > +What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp2_max
> > > +Date:		December 2025
> > > +KernelVersion:	6.19
> > > +Contact:	intel-xe@lists.freedesktop.org
> > > +Description:	RO. Package average temperature limit in millidegree Celsius.
> > > +
> > > +		Only supported for particular Intel Xe graphics platforms.
> > > +
> > > +What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp3_emergency
> > > +Date:		December 2025
> > > +KernelVersion:	6.19
> > > +Contact:	intel-xe@lists.freedesktop.org
> > > +Description:	RO. VRAM shutdown temperature in millidegree Celsius.
> > > +
> > > +		Only supported for particular Intel Xe graphics platforms.
> > > +
> > > +What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp3_crit
> > > +Date:		December 2025
> > > +KernelVersion:	6.19
> > > +Contact:	intel-xe@lists.freedesktop.org
> > > +Description:	RO. VRAM critical temperature in millidegree Celsius.
> > > +
> > > +		Only supported for particular Intel Xe graphics platforms.
> > As per hwmon documentation all these attributes are RW so they don't
> > match with ABI expectations.
> 
> 1. These are read only values for our hardware, write is not supported.
> 
> 2. Couple of other drivers are also supporting readonly for temp_crit.
> 
> Ex:
> 
> a) drivers/net/ethernet/broadcom/bnxt/bnxt_hwmon.c - bnxt_hwmon_is_visible
> 
> 75 static umode_t bnxt_hwmon_is_visible(const void *_data, enum
> hwmon_sensor_types type,
>  76                                      u32 attr, int channel)
>  77 { 82
>  83         switch (attr) {
>  86         case hwmon_temp_max:
>  87         case hwmon_temp_crit:
>  88         case hwmon_temp_emergency:
>  89         case hwmon_temp_max_alarm:
>  90         case hwmon_temp_crit_alarm:
>  91         case hwmon_temp_emergency_alarm:
>  92                 if (!(bp->fw_cap &
> BNXT_FW_CAP_THRESHOLD_TEMP_SUPPORTED))
>  93                         return 0;
>  94                 return 0444;
> 
> b) . drivers/hwmon/intel-m10-bmc-hwmon.c -
> 
> static const struct hwmon_ops m10bmc_hwmon_ops = {
>         .visible = 0444,
>         .read = m10bmc_hwmon_read,
> 
> 3. hwmon also doesn't report any violation for 0444 return from
> xe_hwmon_temp_is_visible.

Sure, but since this is a pre-defined ABI which we don't control I'll let
the maintainers have the final call on this.

Raag

> > > diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> > > index 413ba4c8b62e..8e6dd2665596 100644
> > > --- a/drivers/gpu/drm/xe/xe_device_types.h
> > > +++ b/drivers/gpu/drm/xe/xe_device_types.h
> > > @@ -321,6 +321,9 @@ struct xe_device {
> > >   		 * pcode mailbox commands.
> > >   		 */
> > >   		u8 has_mbx_power_limits:1;
> > > +		/** @info.has_mbx_thermal_info: Device has support for thermal mailbox commands.
> > > +		 */
> > Can be one line.
> > 
> > > +		u8 has_mbx_thermal_info:1;
> > >   		/** @info.has_mem_copy_instr: Device supports MEM_COPY instruction */
> > >   		u8 has_mem_copy_instr:1;
> > >   		/** @info.has_mert: Device has standalone MERT */
> > > diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> > > index ff2aea52ef75..66a8c3e40027 100644
> > > --- a/drivers/gpu/drm/xe/xe_hwmon.c
> > > +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> > > @@ -53,6 +53,14 @@ enum xe_fan_channel {
> > >   	FAN_MAX,
> > >   };
> > > +enum xe_temp_limit {
> > > +	TEMP_LIMIT_PKG_SHUTDOWN,
> > > +	TEMP_LIMIT_PKG_TJMAX,
> > > +	TEMP_LIMIT_MEM_SHUTDOWN,
> > > +	TEMP_LIMIT_PKG_CRIT,
> > > +	TEMP_LIMIT_MEM_TJMAX,
> > > +};
> > > +
> > >   /* Attribute index for powerX_xxx_interval sysfs entries */
> > >   enum sensor_attr_power {
> > >   	SENSOR_INDEX_PSYS_PL1,
> > > @@ -111,6 +119,18 @@ struct xe_hwmon_fan_info {
> > >   	u64 time_prev;
> > >   };
> > > +/**
> > > + * struct xe_hwmon_thermal_info - to store temperature data
> > > + */
> > > +struct xe_hwmon_thermal_info {
> > > +	union {
> > > +		/** @limits: temperatures limits */
> > > +		u8 limit[8];
> > What are the magic numbers? Can we have proper defines?
> 
> We can use xe_temp_limit max value and keep remaining bytes as reserved.
> 
> > 
> > > +		/** @data: temperature limits in dwords */
> > > +		u32 data[2];
> > > +	};
> > > +};
> > > +
> > >   /**
> > >    * struct xe_hwmon - xe hwmon data structure
> > >    */
> > > @@ -137,7 +157,8 @@ struct xe_hwmon {
> > >   	u32 pl1_on_boot[CHANNEL_MAX];
> > >   	/** @pl2_on_boot: power limit PL2 on boot */
> > >   	u32 pl2_on_boot[CHANNEL_MAX];
> > > -
> > > +	/** @temp: Temperature info */
> > > +	struct xe_hwmon_thermal_info temp;
> > >   };
> > >   static int xe_hwmon_pcode_read_power_limit(const struct xe_hwmon *hwmon, u32 attr, int channel,
> > > @@ -677,8 +698,11 @@ static const struct attribute_group *hwmon_groups[] = {
> > >   };
> > >   static const struct hwmon_channel_info * const hwmon_info[] = {
> > > -	HWMON_CHANNEL_INFO(temp, HWMON_T_LABEL, HWMON_T_INPUT | HWMON_T_LABEL,
> > > -			   HWMON_T_INPUT | HWMON_T_LABEL),
> > > +	HWMON_CHANNEL_INFO(temp,
> > > +			   HWMON_T_LABEL,
> > > +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT |
> > > +			   HWMON_T_MAX,
> > > +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT),
> > >   	HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_LABEL | HWMON_P_CRIT |
> > >   			   HWMON_P_CAP,
> > >   			   HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_LABEL | HWMON_P_CAP),
> > > @@ -689,6 +713,23 @@ static const struct hwmon_channel_info * const hwmon_info[] = {
> > >   	NULL
> > >   };
> > > +static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
> > > +{
> > > +	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
> > > +	int ret = 0;
> > > +
> > > +	if (!hwmon->xe->info.has_mbx_power_limits)
> > > +		return -EOPNOTSUPP;
> > > +
> > > +	/* Read thermal info */
> > > +	ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_LIMITS, 0),
> > > +			    &hwmon->temp.data[0], &hwmon->temp.data[1]);
> > > +	drm_dbg(&hwmon->xe->drm, "thermal info read ret %d, val 0x%x val1 0x%x\n", ret,
> > > +		hwmon->temp.data[0], hwmon->temp.data[1]);
> > > +
> > > +	return ret;
> > > +}
> > > +
> > >   /* I1 is exposed as power_crit or as curr_crit depending on bit 31 */
> > >   static int xe_hwmon_pcode_read_i1(const struct xe_hwmon *hwmon, u32 *uval)
> > >   {
> > > @@ -787,6 +828,34 @@ static umode_t
> > >   xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
> > >   {
> > >   	switch (attr) {
> > > +	case hwmon_temp_emergency:
> > > +		switch (channel) {
> > > +		case CHANNEL_PKG:
> > > +			return hwmon->temp.limit[TEMP_LIMIT_PKG_SHUTDOWN] ? 0444 : 0;
> > > +		case CHANNEL_VRAM:
> > > +			return hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN] ? 0444 : 0;
> > > +		default:
> > > +			return 0;
> > > +		}
> > > +		break;
> > > +	case hwmon_temp_crit:
> > > +		switch (channel) {
> > > +		case CHANNEL_PKG:
> > > +			return hwmon->temp.limit[TEMP_LIMIT_PKG_TJMAX] ? 0444 : 0;
> > > +		case CHANNEL_VRAM:
> > > +			return hwmon->temp.limit[TEMP_LIMIT_MEM_TJMAX] ? 0444 : 0;
> > > +		default:
> > > +			return 0;
> > > +		}
> > > +		break;
> > > +	case hwmon_temp_max:
> > > +		switch (channel) {
> > > +		case CHANNEL_PKG:
> > > +			return hwmon->temp.limit[TEMP_LIMIT_PKG_CRIT] ? 0444 : 0;
> > > +		default:
> > > +			return 0;
> > > +		}
> > > +		break;
> > >   	case hwmon_temp_input:
> > >   	case hwmon_temp_label:
> > >   		return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_TEMP, channel)) ? 0444 : 0;
> > > @@ -807,10 +876,46 @@ xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
> > >   		/* HW register value is in degrees Celsius, convert to millidegrees. */
> > >   		*val = REG_FIELD_GET(TEMP_MASK, reg_val) * MILLIDEGREE_PER_DEGREE;
> > > -		return 0;
> > > +		break;
> > > +	case hwmon_temp_emergency:
> > > +		switch (channel) {
> > > +		case CHANNEL_PKG:
> > > +			*val = hwmon->temp.limit[TEMP_LIMIT_PKG_SHUTDOWN] * MILLIDEGREE_PER_DEGREE;
> > > +			break;
> > > +		case CHANNEL_VRAM:
> > > +			*val = hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN] * MILLIDEGREE_PER_DEGREE;
> > > +			break;
> > > +		default:
> > > +			*val = 0;
> > Do you need this?
> > 
> > > +			return -EOPNOTSUPP;
> > > +		}
> > > +		break;
> > > +	case hwmon_temp_crit:
> > > +		switch (channel) {
> > > +		case CHANNEL_PKG:
> > > +			*val = hwmon->temp.limit[TEMP_LIMIT_PKG_TJMAX] * MILLIDEGREE_PER_DEGREE;
> > > +			break;
> > > +		case CHANNEL_VRAM:
> > > +			*val = hwmon->temp.limit[TEMP_LIMIT_MEM_TJMAX] * MILLIDEGREE_PER_DEGREE;
> > > +			break;
> > > +		default:
> > > +			*val = 0;
> > Ditto.
> > 
> > > +			return -EOPNOTSUPP;
> > > +		}
> > > +		break;
> > > +	case hwmon_temp_max:
> > > +		switch (channel) {
> > > +		case CHANNEL_PKG:
> > > +			*val = hwmon->temp.limit[TEMP_LIMIT_PKG_CRIT] * MILLIDEGREE_PER_DEGREE;
> > > +			break;
> > > +		default:
> > > +			return 0;
> > > +		}
> > > +		break;
> > >   	default:
> > >   		return -EOPNOTSUPP;
> > >   	}
> > > +	return 0;
> > >   }
> > >   static umode_t
> > > @@ -1263,6 +1368,9 @@ xe_hwmon_get_preregistration_info(struct xe_hwmon *hwmon)
> > >   	for (channel = 0; channel < FAN_MAX; channel++)
> > >   		if (xe_hwmon_is_visible(hwmon, hwmon_fan, hwmon_fan_input, channel))
> > >   			xe_hwmon_fan_input_read(hwmon, channel, &fan_speed);
> > > +
> > > +	if (xe_hwmon_pcode_read_thermal_info(hwmon))
> > > +		drm_dbg(&hwmon->xe->drm, "Thermal mailbox support not present in firmware\n");
> > >   }
> > >   int xe_hwmon_register(struct xe_device *xe)
> > > diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> > > index 673761c8623e..a47637900e84 100644
> > > --- a/drivers/gpu/drm/xe/xe_pci.c
> > > +++ b/drivers/gpu/drm/xe/xe_pci.c
> > > @@ -311,6 +311,7 @@ static const struct xe_device_desc dg2_desc = {
> > >   	.has_display = true,
> > >   	.has_fan_control = true,
> > >   	.has_mbx_power_limits = false,
> > > +	.has_mbx_thermal_info = false,
> > Why?
> > 
> > >   };
> > >   static const __maybe_unused struct xe_device_desc pvc_desc = {
> > > @@ -328,6 +329,7 @@ static const __maybe_unused struct xe_device_desc pvc_desc = {
> > >   	.vm_max_level = 4,
> > >   	.vram_flags = XE_VRAM_FLAGS_NEED64K,
> > >   	.has_mbx_power_limits = false,
> > > +	.has_mbx_thermal_info = false,
> > Ditto.
> > 
> > >   };
> > >   static const struct xe_device_desc mtl_desc = {
> > > @@ -365,6 +367,7 @@ static const struct xe_device_desc bmg_desc = {
> > >   	.has_fan_control = true,
> > >   	.has_flat_ccs = 1,
> > >   	.has_mbx_power_limits = true,
> > > +	.has_mbx_thermal_info = true,
> > >   	.has_gsc_nvm = 1,
> > >   	.has_heci_cscfi = 1,
> > >   	.has_i2c = true,
> > > @@ -418,6 +421,7 @@ static const struct xe_device_desc cri_desc = {
> > >   	.has_flat_ccs = false,
> > >   	.has_i2c = true,
> > >   	.has_mbx_power_limits = true,
> > > +	.has_mbx_thermal_info = true,
> > >   	.has_mert = true,
> > >   	.has_pre_prod_wa = 1,
> > >   	.has_sriov = true,
> > > @@ -681,6 +685,7 @@ static int xe_info_init_early(struct xe_device *xe,
> > >   	/* runtime fusing may force flat_ccs to disabled later */
> > >   	xe->info.has_flat_ccs = desc->has_flat_ccs;
> > >   	xe->info.has_mbx_power_limits = desc->has_mbx_power_limits;
> > > +	xe->info.has_mbx_thermal_info = desc->has_mbx_thermal_info;
> > >   	xe->info.has_gsc_nvm = desc->has_gsc_nvm;
> > >   	xe->info.has_heci_gscfi = desc->has_heci_gscfi;
> > >   	xe->info.has_heci_cscfi = desc->has_heci_cscfi;
> > > diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
> > > index 3bb51d155951..34d2b66188e4 100644
> > > --- a/drivers/gpu/drm/xe/xe_pci_types.h
> > > +++ b/drivers/gpu/drm/xe/xe_pci_types.h
> > > @@ -48,6 +48,7 @@ struct xe_device_desc {
> > >   	u8 has_late_bind:1;
> > >   	u8 has_llc:1;
> > >   	u8 has_mbx_power_limits:1;
> > > +	u8 has_mbx_thermal_info:1;
> > >   	u8 has_mem_copy_instr:1;
> > >   	u8 has_mert:1;
> > >   	u8 has_pre_prod_wa:1;
> > > diff --git a/drivers/gpu/drm/xe/xe_pcode_api.h b/drivers/gpu/drm/xe/xe_pcode_api.h
> > > index 975892d6b230..a3bff76a074d 100644
> > > --- a/drivers/gpu/drm/xe/xe_pcode_api.h
> > > +++ b/drivers/gpu/drm/xe/xe_pcode_api.h
> > > @@ -65,6 +65,9 @@
> > >   #define       FAN_TABLE				1
> > >   #define       VR_CONFIG				2
> > > +#define	PCODE_THERMAL_INFO			0x25
> > > +#define	READ_THERMAL_LIMITS			0x0
> > Does this match with spacing convention and ordering?
> > 
> > Raag
> > 
> > >   #define   PCODE_FREQUENCY_CONFIG		0x6e
> > >   /* Frequency Config Sub Commands (param1) */
> > >   #define     PCODE_MBOX_FC_SC_READ_FUSED_P0	0x0
> > > -- 
> > > 2.25.1
> > > 

Re: [PATCH v3 1/4] drm/xe/hwmon: Expose temperature limits

[Nilawar, Badal]

Hi Guenter,

On 18-12-2025 16:45, Raag Jadav wrote:
> On Thu, Dec 18, 2025 at 01:07:57PM +0530, Poosa, Karthik wrote:
>> On 17-12-2025 22:35, Raag Jadav wrote:
>>> On Tue, Dec 16, 2025 at 05:10:27PM +0530, Karthik Poosa wrote:
>>>> Read temperature limits using pcode mailbox and
>>>> expose shutdown temperature limit as tempX_emergency,
>>>> critical temperature limit of as tempX_crit and
>>>> GPU average temperature limit as tempX_max.
>>>>
>>>> Update Xe hwmon documentation for these entries.
>>>>
>>>> Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
>>>> ---
>>>>    .../ABI/testing/sysfs-driver-intel-xe-hwmon   |  40 ++++++
>>>>    drivers/gpu/drm/xe/xe_device_types.h          |   3 +
>>>>    drivers/gpu/drm/xe/xe_hwmon.c                 | 116 +++++++++++++++++-
>>>>    drivers/gpu/drm/xe/xe_pci.c                   |   5 +
>>>>    drivers/gpu/drm/xe/xe_pci_types.h             |   1 +
>>>>    drivers/gpu/drm/xe/xe_pcode_api.h             |   3 +
>>>>    6 files changed, 164 insertions(+), 4 deletions(-)
>>>>
>>>> diff --git a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
>>>> index d9e2b17c6872..c8f211c336be 100644
>>>> --- a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
>>>> +++ b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
>>>> @@ -196,3 +196,43 @@ Description:	RW. Package burst power limit interval (Tau in PL2/Tau) in
>>>>    		milliseconds over which sustained power is averaged.
>>>>    		Only supported for particular Intel Xe graphics platforms.
>>>> +
>>>> +What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp2_emergency
>>>> +Date:		December 2025
>>>> +KernelVersion:	6.19
>>>> +Contact:	intel-xe@lists.freedesktop.org
>>>> +Description:	RO. Package shutdown temperature in millidegree Celsius.
>>>> +
>>>> +		Only supported for particular Intel Xe graphics platforms.
>>>> +
>>>> +What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp2_crit
>>>> +Date:		December 2025
>>>> +KernelVersion:	6.19
>>>> +Contact:	intel-xe@lists.freedesktop.org
>>>> +Description:	RO. Package critical temperature in millidegree Celsius.
>>>> +
>>>> +		Only supported for particular Intel Xe graphics platforms.
>>>> +
>>>> +What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp2_max
>>>> +Date:		December 2025
>>>> +KernelVersion:	6.19
>>>> +Contact:	intel-xe@lists.freedesktop.org
>>>> +Description:	RO. Package average temperature limit in millidegree Celsius.
>>>> +
>>>> +		Only supported for particular Intel Xe graphics platforms.
>>>> +
>>>> +What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp3_emergency
>>>> +Date:		December 2025
>>>> +KernelVersion:	6.19
>>>> +Contact:	intel-xe@lists.freedesktop.org
>>>> +Description:	RO. VRAM shutdown temperature in millidegree Celsius.
>>>> +
>>>> +		Only supported for particular Intel Xe graphics platforms.
>>>> +
>>>> +What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp3_crit
>>>> +Date:		December 2025
>>>> +KernelVersion:	6.19
>>>> +Contact:	intel-xe@lists.freedesktop.org
>>>> +Description:	RO. VRAM critical temperature in millidegree Celsius.
>>>> +
>>>> +		Only supported for particular Intel Xe graphics platforms.
>>> As per hwmon documentation all these attributes are RW so they don't
>>> match with ABI expectations.
>> 1. These are read only values for our hardware, write is not supported.
>>
>> 2. Couple of other drivers are also supporting readonly for temp_crit.
>>
>> Ex:
>>
>> a) drivers/net/ethernet/broadcom/bnxt/bnxt_hwmon.c - bnxt_hwmon_is_visible
>>
>> 75 static umode_t bnxt_hwmon_is_visible(const void *_data, enum
>> hwmon_sensor_types type,
>>   76                                      u32 attr, int channel)
>>   77 { 82
>>   83         switch (attr) {
>>   86         case hwmon_temp_max:
>>   87         case hwmon_temp_crit:
>>   88         case hwmon_temp_emergency:
>>   89         case hwmon_temp_max_alarm:
>>   90         case hwmon_temp_crit_alarm:
>>   91         case hwmon_temp_emergency_alarm:
>>   92                 if (!(bp->fw_cap &
>> BNXT_FW_CAP_THRESHOLD_TEMP_SUPPORTED))
>>   93                         return 0;
>>   94                 return 0444;
>>
>> b) . drivers/hwmon/intel-m10-bmc-hwmon.c -
>>
>> static const struct hwmon_ops m10bmc_hwmon_ops = {
>>          .visible = 0444,
>>          .read = m10bmc_hwmon_read,
>>
>> 3. hwmon also doesn't report any violation for 0444 return from
>> xe_hwmon_temp_is_visible.
> Sure, but since this is a pre-defined ABI which we don't control I'll let
> the maintainers have the final call on this.

Could you please share your thoughts on this? Temperature limits are 
kept RO as hardware doesn't allow to write.

Thanks,
Badal

>
> Raag
>
>>>> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
>>>> index 413ba4c8b62e..8e6dd2665596 100644
>>>> --- a/drivers/gpu/drm/xe/xe_device_types.h
>>>> +++ b/drivers/gpu/drm/xe/xe_device_types.h
>>>> @@ -321,6 +321,9 @@ struct xe_device {
>>>>    		 * pcode mailbox commands.
>>>>    		 */
>>>>    		u8 has_mbx_power_limits:1;
>>>> +		/** @info.has_mbx_thermal_info: Device has support for thermal mailbox commands.
>>>> +		 */
>>> Can be one line.
>>>
>>>> +		u8 has_mbx_thermal_info:1;
>>>>    		/** @info.has_mem_copy_instr: Device supports MEM_COPY instruction */
>>>>    		u8 has_mem_copy_instr:1;
>>>>    		/** @info.has_mert: Device has standalone MERT */
>>>> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
>>>> index ff2aea52ef75..66a8c3e40027 100644
>>>> --- a/drivers/gpu/drm/xe/xe_hwmon.c
>>>> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
>>>> @@ -53,6 +53,14 @@ enum xe_fan_channel {
>>>>    	FAN_MAX,
>>>>    };
>>>> +enum xe_temp_limit {
>>>> +	TEMP_LIMIT_PKG_SHUTDOWN,
>>>> +	TEMP_LIMIT_PKG_TJMAX,
>>>> +	TEMP_LIMIT_MEM_SHUTDOWN,
>>>> +	TEMP_LIMIT_PKG_CRIT,
>>>> +	TEMP_LIMIT_MEM_TJMAX,
>>>> +};
>>>> +
>>>>    /* Attribute index for powerX_xxx_interval sysfs entries */
>>>>    enum sensor_attr_power {
>>>>    	SENSOR_INDEX_PSYS_PL1,
>>>> @@ -111,6 +119,18 @@ struct xe_hwmon_fan_info {
>>>>    	u64 time_prev;
>>>>    };
>>>> +/**
>>>> + * struct xe_hwmon_thermal_info - to store temperature data
>>>> + */
>>>> +struct xe_hwmon_thermal_info {
>>>> +	union {
>>>> +		/** @limits: temperatures limits */
>>>> +		u8 limit[8];
>>> What are the magic numbers? Can we have proper defines?
>> We can use xe_temp_limit max value and keep remaining bytes as reserved.
>>
>>>> +		/** @data: temperature limits in dwords */
>>>> +		u32 data[2];
>>>> +	};
>>>> +};
>>>> +
>>>>    /**
>>>>     * struct xe_hwmon - xe hwmon data structure
>>>>     */
>>>> @@ -137,7 +157,8 @@ struct xe_hwmon {
>>>>    	u32 pl1_on_boot[CHANNEL_MAX];
>>>>    	/** @pl2_on_boot: power limit PL2 on boot */
>>>>    	u32 pl2_on_boot[CHANNEL_MAX];
>>>> -
>>>> +	/** @temp: Temperature info */
>>>> +	struct xe_hwmon_thermal_info temp;
>>>>    };
>>>>    static int xe_hwmon_pcode_read_power_limit(const struct xe_hwmon *hwmon, u32 attr, int channel,
>>>> @@ -677,8 +698,11 @@ static const struct attribute_group *hwmon_groups[] = {
>>>>    };
>>>>    static const struct hwmon_channel_info * const hwmon_info[] = {
>>>> -	HWMON_CHANNEL_INFO(temp, HWMON_T_LABEL, HWMON_T_INPUT | HWMON_T_LABEL,
>>>> -			   HWMON_T_INPUT | HWMON_T_LABEL),
>>>> +	HWMON_CHANNEL_INFO(temp,
>>>> +			   HWMON_T_LABEL,
>>>> +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT |
>>>> +			   HWMON_T_MAX,
>>>> +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT),
>>>>    	HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_LABEL | HWMON_P_CRIT |
>>>>    			   HWMON_P_CAP,
>>>>    			   HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_LABEL | HWMON_P_CAP),
>>>> @@ -689,6 +713,23 @@ static const struct hwmon_channel_info * const hwmon_info[] = {
>>>>    	NULL
>>>>    };
>>>> +static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
>>>> +{
>>>> +	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
>>>> +	int ret = 0;
>>>> +
>>>> +	if (!hwmon->xe->info.has_mbx_power_limits)
>>>> +		return -EOPNOTSUPP;
>>>> +
>>>> +	/* Read thermal info */
>>>> +	ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_LIMITS, 0),
>>>> +			    &hwmon->temp.data[0], &hwmon->temp.data[1]);
>>>> +	drm_dbg(&hwmon->xe->drm, "thermal info read ret %d, val 0x%x val1 0x%x\n", ret,
>>>> +		hwmon->temp.data[0], hwmon->temp.data[1]);
>>>> +
>>>> +	return ret;
>>>> +}
>>>> +
>>>>    /* I1 is exposed as power_crit or as curr_crit depending on bit 31 */
>>>>    static int xe_hwmon_pcode_read_i1(const struct xe_hwmon *hwmon, u32 *uval)
>>>>    {
>>>> @@ -787,6 +828,34 @@ static umode_t
>>>>    xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
>>>>    {
>>>>    	switch (attr) {
>>>> +	case hwmon_temp_emergency:
>>>> +		switch (channel) {
>>>> +		case CHANNEL_PKG:
>>>> +			return hwmon->temp.limit[TEMP_LIMIT_PKG_SHUTDOWN] ? 0444 : 0;
>>>> +		case CHANNEL_VRAM:
>>>> +			return hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN] ? 0444 : 0;
>>>> +		default:
>>>> +			return 0;
>>>> +		}
>>>> +		break;
>>>> +	case hwmon_temp_crit:
>>>> +		switch (channel) {
>>>> +		case CHANNEL_PKG:
>>>> +			return hwmon->temp.limit[TEMP_LIMIT_PKG_TJMAX] ? 0444 : 0;
>>>> +		case CHANNEL_VRAM:
>>>> +			return hwmon->temp.limit[TEMP_LIMIT_MEM_TJMAX] ? 0444 : 0;
>>>> +		default:
>>>> +			return 0;
>>>> +		}
>>>> +		break;
>>>> +	case hwmon_temp_max:
>>>> +		switch (channel) {
>>>> +		case CHANNEL_PKG:
>>>> +			return hwmon->temp.limit[TEMP_LIMIT_PKG_CRIT] ? 0444 : 0;
>>>> +		default:
>>>> +			return 0;
>>>> +		}
>>>> +		break;
>>>>    	case hwmon_temp_input:
>>>>    	case hwmon_temp_label:
>>>>    		return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_TEMP, channel)) ? 0444 : 0;
>>>> @@ -807,10 +876,46 @@ xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
>>>>    		/* HW register value is in degrees Celsius, convert to millidegrees. */
>>>>    		*val = REG_FIELD_GET(TEMP_MASK, reg_val) * MILLIDEGREE_PER_DEGREE;
>>>> -		return 0;
>>>> +		break;
>>>> +	case hwmon_temp_emergency:
>>>> +		switch (channel) {
>>>> +		case CHANNEL_PKG:
>>>> +			*val = hwmon->temp.limit[TEMP_LIMIT_PKG_SHUTDOWN] * MILLIDEGREE_PER_DEGREE;
>>>> +			break;
>>>> +		case CHANNEL_VRAM:
>>>> +			*val = hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN] * MILLIDEGREE_PER_DEGREE;
>>>> +			break;
>>>> +		default:
>>>> +			*val = 0;
>>> Do you need this?
>>>
>>>> +			return -EOPNOTSUPP;
>>>> +		}
>>>> +		break;
>>>> +	case hwmon_temp_crit:
>>>> +		switch (channel) {
>>>> +		case CHANNEL_PKG:
>>>> +			*val = hwmon->temp.limit[TEMP_LIMIT_PKG_TJMAX] * MILLIDEGREE_PER_DEGREE;
>>>> +			break;
>>>> +		case CHANNEL_VRAM:
>>>> +			*val = hwmon->temp.limit[TEMP_LIMIT_MEM_TJMAX] * MILLIDEGREE_PER_DEGREE;
>>>> +			break;
>>>> +		default:
>>>> +			*val = 0;
>>> Ditto.
>>>
>>>> +			return -EOPNOTSUPP;
>>>> +		}
>>>> +		break;
>>>> +	case hwmon_temp_max:
>>>> +		switch (channel) {
>>>> +		case CHANNEL_PKG:
>>>> +			*val = hwmon->temp.limit[TEMP_LIMIT_PKG_CRIT] * MILLIDEGREE_PER_DEGREE;
>>>> +			break;
>>>> +		default:
>>>> +			return 0;
>>>> +		}
>>>> +		break;
>>>>    	default:
>>>>    		return -EOPNOTSUPP;
>>>>    	}
>>>> +	return 0;
>>>>    }
>>>>    static umode_t
>>>> @@ -1263,6 +1368,9 @@ xe_hwmon_get_preregistration_info(struct xe_hwmon *hwmon)
>>>>    	for (channel = 0; channel < FAN_MAX; channel++)
>>>>    		if (xe_hwmon_is_visible(hwmon, hwmon_fan, hwmon_fan_input, channel))
>>>>    			xe_hwmon_fan_input_read(hwmon, channel, &fan_speed);
>>>> +
>>>> +	if (xe_hwmon_pcode_read_thermal_info(hwmon))
>>>> +		drm_dbg(&hwmon->xe->drm, "Thermal mailbox support not present in firmware\n");
>>>>    }
>>>>    int xe_hwmon_register(struct xe_device *xe)
>>>> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
>>>> index 673761c8623e..a47637900e84 100644
>>>> --- a/drivers/gpu/drm/xe/xe_pci.c
>>>> +++ b/drivers/gpu/drm/xe/xe_pci.c
>>>> @@ -311,6 +311,7 @@ static const struct xe_device_desc dg2_desc = {
>>>>    	.has_display = true,
>>>>    	.has_fan_control = true,
>>>>    	.has_mbx_power_limits = false,
>>>> +	.has_mbx_thermal_info = false,
>>> Why?
>>>
>>>>    };
>>>>    static const __maybe_unused struct xe_device_desc pvc_desc = {
>>>> @@ -328,6 +329,7 @@ static const __maybe_unused struct xe_device_desc pvc_desc = {
>>>>    	.vm_max_level = 4,
>>>>    	.vram_flags = XE_VRAM_FLAGS_NEED64K,
>>>>    	.has_mbx_power_limits = false,
>>>> +	.has_mbx_thermal_info = false,
>>> Ditto.
>>>
>>>>    };
>>>>    static const struct xe_device_desc mtl_desc = {
>>>> @@ -365,6 +367,7 @@ static const struct xe_device_desc bmg_desc = {
>>>>    	.has_fan_control = true,
>>>>    	.has_flat_ccs = 1,
>>>>    	.has_mbx_power_limits = true,
>>>> +	.has_mbx_thermal_info = true,
>>>>    	.has_gsc_nvm = 1,
>>>>    	.has_heci_cscfi = 1,
>>>>    	.has_i2c = true,
>>>> @@ -418,6 +421,7 @@ static const struct xe_device_desc cri_desc = {
>>>>    	.has_flat_ccs = false,
>>>>    	.has_i2c = true,
>>>>    	.has_mbx_power_limits = true,
>>>> +	.has_mbx_thermal_info = true,
>>>>    	.has_mert = true,
>>>>    	.has_pre_prod_wa = 1,
>>>>    	.has_sriov = true,
>>>> @@ -681,6 +685,7 @@ static int xe_info_init_early(struct xe_device *xe,
>>>>    	/* runtime fusing may force flat_ccs to disabled later */
>>>>    	xe->info.has_flat_ccs = desc->has_flat_ccs;
>>>>    	xe->info.has_mbx_power_limits = desc->has_mbx_power_limits;
>>>> +	xe->info.has_mbx_thermal_info = desc->has_mbx_thermal_info;
>>>>    	xe->info.has_gsc_nvm = desc->has_gsc_nvm;
>>>>    	xe->info.has_heci_gscfi = desc->has_heci_gscfi;
>>>>    	xe->info.has_heci_cscfi = desc->has_heci_cscfi;
>>>> diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
>>>> index 3bb51d155951..34d2b66188e4 100644
>>>> --- a/drivers/gpu/drm/xe/xe_pci_types.h
>>>> +++ b/drivers/gpu/drm/xe/xe_pci_types.h
>>>> @@ -48,6 +48,7 @@ struct xe_device_desc {
>>>>    	u8 has_late_bind:1;
>>>>    	u8 has_llc:1;
>>>>    	u8 has_mbx_power_limits:1;
>>>> +	u8 has_mbx_thermal_info:1;
>>>>    	u8 has_mem_copy_instr:1;
>>>>    	u8 has_mert:1;
>>>>    	u8 has_pre_prod_wa:1;
>>>> diff --git a/drivers/gpu/drm/xe/xe_pcode_api.h b/drivers/gpu/drm/xe/xe_pcode_api.h
>>>> index 975892d6b230..a3bff76a074d 100644
>>>> --- a/drivers/gpu/drm/xe/xe_pcode_api.h
>>>> +++ b/drivers/gpu/drm/xe/xe_pcode_api.h
>>>> @@ -65,6 +65,9 @@
>>>>    #define       FAN_TABLE				1
>>>>    #define       VR_CONFIG				2
>>>> +#define	PCODE_THERMAL_INFO			0x25
>>>> +#define	READ_THERMAL_LIMITS			0x0
>>> Does this match with spacing convention and ordering?
>>>
>>> Raag
>>>
>>>>    #define   PCODE_FREQUENCY_CONFIG		0x6e
>>>>    /* Frequency Config Sub Commands (param1) */
>>>>    #define     PCODE_MBOX_FC_SC_READ_FUSED_P0	0x0
>>>> -- 
>>>> 2.25.1
>>>>

Re: [PATCH v3 1/4] drm/xe/hwmon: Expose temperature limits

[Guenter Roeck]

On 12/19/25 00:37, Nilawar, Badal wrote:
> Hi Guenter,
> 
...
>>>>> +
>>>>> +        Only supported for particular Intel Xe graphics platforms.
>>>> As per hwmon documentation all these attributes are RW so they don't
>>>> match with ABI expectations.
>>> 1. These are read only values for our hardware, write is not supported.
>>>
>>> 2. Couple of other drivers are also supporting readonly for temp_crit.
>>>
>>> Ex:
>>>
>>> a) drivers/net/ethernet/broadcom/bnxt/bnxt_hwmon.c - bnxt_hwmon_is_visible
>>>
>>> 75 static umode_t bnxt_hwmon_is_visible(const void *_data, enum
>>> hwmon_sensor_types type,
>>>   76                                      u32 attr, int channel)
>>>   77 { 82
>>>   83         switch (attr) {
>>>   86         case hwmon_temp_max:
>>>   87         case hwmon_temp_crit:
>>>   88         case hwmon_temp_emergency:
>>>   89         case hwmon_temp_max_alarm:
>>>   90         case hwmon_temp_crit_alarm:
>>>   91         case hwmon_temp_emergency_alarm:
>>>   92                 if (!(bp->fw_cap &
>>> BNXT_FW_CAP_THRESHOLD_TEMP_SUPPORTED))
>>>   93                         return 0;
>>>   94                 return 0444;
>>>
>>> b) . drivers/hwmon/intel-m10-bmc-hwmon.c -
>>>
>>> static const struct hwmon_ops m10bmc_hwmon_ops = {
>>>          .visible = 0444,
>>>          .read = m10bmc_hwmon_read,
>>>
>>> 3. hwmon also doesn't report any violation for 0444 return from
>>> xe_hwmon_temp_is_visible.
>> Sure, but since this is a pre-defined ABI which we don't control I'll let
>> the maintainers have the final call on this.
> 
> Could you please share your thoughts on this? Temperature limits are kept RO as hardware doesn't allow to write.
> 

One of the developers involved in the drm hardware monitoring code once
told me that I have no clue what hardware monitoring is about, so why
do you ask me ? Apparently they know better.

If the driver was in drivers/hwmon, this would not be an issue. Of course
it does not make sense to have an attribute as writable if the value it
controls can not be modified. I can not tell you the rules for this driver
because it does not reside in drivers/hwmon and, again, the above.

Sorry for the rude reply, but, please, do not ask me for advice on any
hwmon code in the drm subdirectory. They make their own rules.

Guenter

Re: [PATCH v3 1/4] drm/xe/hwmon: Expose temperature limits

[Rodrigo Vivi]

On Thu, Dec 18, 2025 at 12:15:41PM +0100, Raag Jadav wrote:
> On Thu, Dec 18, 2025 at 01:07:57PM +0530, Poosa, Karthik wrote:
> > On 17-12-2025 22:35, Raag Jadav wrote:
> > > On Tue, Dec 16, 2025 at 05:10:27PM +0530, Karthik Poosa wrote:
> > > > Read temperature limits using pcode mailbox and
> > > > expose shutdown temperature limit as tempX_emergency,
> > > > critical temperature limit of as tempX_crit and
> > > > GPU average temperature limit as tempX_max.
> > > > 
> > > > Update Xe hwmon documentation for these entries.
> > > > 
> > > > Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
> > > > ---
> > > >   .../ABI/testing/sysfs-driver-intel-xe-hwmon   |  40 ++++++
> > > >   drivers/gpu/drm/xe/xe_device_types.h          |   3 +
> > > >   drivers/gpu/drm/xe/xe_hwmon.c                 | 116 +++++++++++++++++-
> > > >   drivers/gpu/drm/xe/xe_pci.c                   |   5 +
> > > >   drivers/gpu/drm/xe/xe_pci_types.h             |   1 +
> > > >   drivers/gpu/drm/xe/xe_pcode_api.h             |   3 +
> > > >   6 files changed, 164 insertions(+), 4 deletions(-)
> > > > 
> > > > diff --git a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> > > > index d9e2b17c6872..c8f211c336be 100644
> > > > --- a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> > > > +++ b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> > > > @@ -196,3 +196,43 @@ Description:	RW. Package burst power limit interval (Tau in PL2/Tau) in
> > > >   		milliseconds over which sustained power is averaged.
> > > >   		Only supported for particular Intel Xe graphics platforms.
> > > > +
> > > > +What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp2_emergency
> > > > +Date:		December 2025
> > > > +KernelVersion:	6.19
> > > > +Contact:	intel-xe@lists.freedesktop.org
> > > > +Description:	RO. Package shutdown temperature in millidegree Celsius.
> > > > +
> > > > +		Only supported for particular Intel Xe graphics platforms.
> > > > +
> > > > +What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp2_crit
> > > > +Date:		December 2025
> > > > +KernelVersion:	6.19
> > > > +Contact:	intel-xe@lists.freedesktop.org
> > > > +Description:	RO. Package critical temperature in millidegree Celsius.
> > > > +
> > > > +		Only supported for particular Intel Xe graphics platforms.
> > > > +
> > > > +What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp2_max
> > > > +Date:		December 2025
> > > > +KernelVersion:	6.19
> > > > +Contact:	intel-xe@lists.freedesktop.org
> > > > +Description:	RO. Package average temperature limit in millidegree Celsius.
> > > > +
> > > > +		Only supported for particular Intel Xe graphics platforms.
> > > > +
> > > > +What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp3_emergency
> > > > +Date:		December 2025
> > > > +KernelVersion:	6.19
> > > > +Contact:	intel-xe@lists.freedesktop.org
> > > > +Description:	RO. VRAM shutdown temperature in millidegree Celsius.
> > > > +
> > > > +		Only supported for particular Intel Xe graphics platforms.
> > > > +
> > > > +What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp3_crit
> > > > +Date:		December 2025
> > > > +KernelVersion:	6.19
> > > > +Contact:	intel-xe@lists.freedesktop.org
> > > > +Description:	RO. VRAM critical temperature in millidegree Celsius.
> > > > +
> > > > +		Only supported for particular Intel Xe graphics platforms.
> > > As per hwmon documentation all these attributes are RW so they don't
> > > match with ABI expectations.
> > 
> > 1. These are read only values for our hardware, write is not supported.
> > 
> > 2. Couple of other drivers are also supporting readonly for temp_crit.
> > 
> > Ex:
> > 
> > a) drivers/net/ethernet/broadcom/bnxt/bnxt_hwmon.c - bnxt_hwmon_is_visible
> > 
> > 75 static umode_t bnxt_hwmon_is_visible(const void *_data, enum
> > hwmon_sensor_types type,
> >  76                                      u32 attr, int channel)
> >  77 { 82
> >  83         switch (attr) {
> >  86         case hwmon_temp_max:
> >  87         case hwmon_temp_crit:
> >  88         case hwmon_temp_emergency:
> >  89         case hwmon_temp_max_alarm:
> >  90         case hwmon_temp_crit_alarm:
> >  91         case hwmon_temp_emergency_alarm:
> >  92                 if (!(bp->fw_cap &
> > BNXT_FW_CAP_THRESHOLD_TEMP_SUPPORTED))
> >  93                         return 0;
> >  94                 return 0444;
> > 
> > b) . drivers/hwmon/intel-m10-bmc-hwmon.c -
> > 
> > static const struct hwmon_ops m10bmc_hwmon_ops = {
> >         .visible = 0444,
> >         .read = m10bmc_hwmon_read,
> > 
> > 3. hwmon also doesn't report any violation for 0444 return from
> > xe_hwmon_temp_is_visible.
> 
> Sure, but since this is a pre-defined ABI which we don't control I'll let
> the maintainers have the final call on this.

Not needed. It is properly documented:

"""
Read/write values may be read-only for some chips, depending on the
hardware implementation.
"""

in Documentation/hwmon/sysfs-interface.rst

> 
> Raag
> 
> > > > diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> > > > index 413ba4c8b62e..8e6dd2665596 100644
> > > > --- a/drivers/gpu/drm/xe/xe_device_types.h
> > > > +++ b/drivers/gpu/drm/xe/xe_device_types.h
> > > > @@ -321,6 +321,9 @@ struct xe_device {
> > > >   		 * pcode mailbox commands.
> > > >   		 */
> > > >   		u8 has_mbx_power_limits:1;
> > > > +		/** @info.has_mbx_thermal_info: Device has support for thermal mailbox commands.
> > > > +		 */
> > > Can be one line.
> > > 
> > > > +		u8 has_mbx_thermal_info:1;
> > > >   		/** @info.has_mem_copy_instr: Device supports MEM_COPY instruction */
> > > >   		u8 has_mem_copy_instr:1;
> > > >   		/** @info.has_mert: Device has standalone MERT */
> > > > diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> > > > index ff2aea52ef75..66a8c3e40027 100644
> > > > --- a/drivers/gpu/drm/xe/xe_hwmon.c
> > > > +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> > > > @@ -53,6 +53,14 @@ enum xe_fan_channel {
> > > >   	FAN_MAX,
> > > >   };
> > > > +enum xe_temp_limit {
> > > > +	TEMP_LIMIT_PKG_SHUTDOWN,
> > > > +	TEMP_LIMIT_PKG_TJMAX,
> > > > +	TEMP_LIMIT_MEM_SHUTDOWN,
> > > > +	TEMP_LIMIT_PKG_CRIT,
> > > > +	TEMP_LIMIT_MEM_TJMAX,
> > > > +};
> > > > +
> > > >   /* Attribute index for powerX_xxx_interval sysfs entries */
> > > >   enum sensor_attr_power {
> > > >   	SENSOR_INDEX_PSYS_PL1,
> > > > @@ -111,6 +119,18 @@ struct xe_hwmon_fan_info {
> > > >   	u64 time_prev;
> > > >   };
> > > > +/**
> > > > + * struct xe_hwmon_thermal_info - to store temperature data
> > > > + */
> > > > +struct xe_hwmon_thermal_info {
> > > > +	union {
> > > > +		/** @limits: temperatures limits */
> > > > +		u8 limit[8];
> > > What are the magic numbers? Can we have proper defines?
> > 
> > We can use xe_temp_limit max value and keep remaining bytes as reserved.
> > 
> > > 
> > > > +		/** @data: temperature limits in dwords */
> > > > +		u32 data[2];
> > > > +	};
> > > > +};
> > > > +
> > > >   /**
> > > >    * struct xe_hwmon - xe hwmon data structure
> > > >    */
> > > > @@ -137,7 +157,8 @@ struct xe_hwmon {
> > > >   	u32 pl1_on_boot[CHANNEL_MAX];
> > > >   	/** @pl2_on_boot: power limit PL2 on boot */
> > > >   	u32 pl2_on_boot[CHANNEL_MAX];
> > > > -
> > > > +	/** @temp: Temperature info */
> > > > +	struct xe_hwmon_thermal_info temp;
> > > >   };
> > > >   static int xe_hwmon_pcode_read_power_limit(const struct xe_hwmon *hwmon, u32 attr, int channel,
> > > > @@ -677,8 +698,11 @@ static const struct attribute_group *hwmon_groups[] = {
> > > >   };
> > > >   static const struct hwmon_channel_info * const hwmon_info[] = {
> > > > -	HWMON_CHANNEL_INFO(temp, HWMON_T_LABEL, HWMON_T_INPUT | HWMON_T_LABEL,
> > > > -			   HWMON_T_INPUT | HWMON_T_LABEL),
> > > > +	HWMON_CHANNEL_INFO(temp,
> > > > +			   HWMON_T_LABEL,
> > > > +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT |
> > > > +			   HWMON_T_MAX,
> > > > +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT),
> > > >   	HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_LABEL | HWMON_P_CRIT |
> > > >   			   HWMON_P_CAP,
> > > >   			   HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_LABEL | HWMON_P_CAP),
> > > > @@ -689,6 +713,23 @@ static const struct hwmon_channel_info * const hwmon_info[] = {
> > > >   	NULL
> > > >   };
> > > > +static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
> > > > +{
> > > > +	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
> > > > +	int ret = 0;
> > > > +
> > > > +	if (!hwmon->xe->info.has_mbx_power_limits)
> > > > +		return -EOPNOTSUPP;
> > > > +
> > > > +	/* Read thermal info */
> > > > +	ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_LIMITS, 0),
> > > > +			    &hwmon->temp.data[0], &hwmon->temp.data[1]);
> > > > +	drm_dbg(&hwmon->xe->drm, "thermal info read ret %d, val 0x%x val1 0x%x\n", ret,
> > > > +		hwmon->temp.data[0], hwmon->temp.data[1]);
> > > > +
> > > > +	return ret;
> > > > +}
> > > > +
> > > >   /* I1 is exposed as power_crit or as curr_crit depending on bit 31 */
> > > >   static int xe_hwmon_pcode_read_i1(const struct xe_hwmon *hwmon, u32 *uval)
> > > >   {
> > > > @@ -787,6 +828,34 @@ static umode_t
> > > >   xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
> > > >   {
> > > >   	switch (attr) {
> > > > +	case hwmon_temp_emergency:
> > > > +		switch (channel) {
> > > > +		case CHANNEL_PKG:
> > > > +			return hwmon->temp.limit[TEMP_LIMIT_PKG_SHUTDOWN] ? 0444 : 0;
> > > > +		case CHANNEL_VRAM:
> > > > +			return hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN] ? 0444 : 0;
> > > > +		default:
> > > > +			return 0;
> > > > +		}
> > > > +		break;
> > > > +	case hwmon_temp_crit:
> > > > +		switch (channel) {
> > > > +		case CHANNEL_PKG:
> > > > +			return hwmon->temp.limit[TEMP_LIMIT_PKG_TJMAX] ? 0444 : 0;
> > > > +		case CHANNEL_VRAM:
> > > > +			return hwmon->temp.limit[TEMP_LIMIT_MEM_TJMAX] ? 0444 : 0;
> > > > +		default:
> > > > +			return 0;
> > > > +		}
> > > > +		break;
> > > > +	case hwmon_temp_max:
> > > > +		switch (channel) {
> > > > +		case CHANNEL_PKG:
> > > > +			return hwmon->temp.limit[TEMP_LIMIT_PKG_CRIT] ? 0444 : 0;
> > > > +		default:
> > > > +			return 0;
> > > > +		}
> > > > +		break;
> > > >   	case hwmon_temp_input:
> > > >   	case hwmon_temp_label:
> > > >   		return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_TEMP, channel)) ? 0444 : 0;
> > > > @@ -807,10 +876,46 @@ xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
> > > >   		/* HW register value is in degrees Celsius, convert to millidegrees. */
> > > >   		*val = REG_FIELD_GET(TEMP_MASK, reg_val) * MILLIDEGREE_PER_DEGREE;
> > > > -		return 0;
> > > > +		break;
> > > > +	case hwmon_temp_emergency:
> > > > +		switch (channel) {
> > > > +		case CHANNEL_PKG:
> > > > +			*val = hwmon->temp.limit[TEMP_LIMIT_PKG_SHUTDOWN] * MILLIDEGREE_PER_DEGREE;
> > > > +			break;
> > > > +		case CHANNEL_VRAM:
> > > > +			*val = hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN] * MILLIDEGREE_PER_DEGREE;
> > > > +			break;
> > > > +		default:
> > > > +			*val = 0;
> > > Do you need this?
> > > 
> > > > +			return -EOPNOTSUPP;
> > > > +		}
> > > > +		break;
> > > > +	case hwmon_temp_crit:
> > > > +		switch (channel) {
> > > > +		case CHANNEL_PKG:
> > > > +			*val = hwmon->temp.limit[TEMP_LIMIT_PKG_TJMAX] * MILLIDEGREE_PER_DEGREE;
> > > > +			break;
> > > > +		case CHANNEL_VRAM:
> > > > +			*val = hwmon->temp.limit[TEMP_LIMIT_MEM_TJMAX] * MILLIDEGREE_PER_DEGREE;
> > > > +			break;
> > > > +		default:
> > > > +			*val = 0;
> > > Ditto.
> > > 
> > > > +			return -EOPNOTSUPP;
> > > > +		}
> > > > +		break;
> > > > +	case hwmon_temp_max:
> > > > +		switch (channel) {
> > > > +		case CHANNEL_PKG:
> > > > +			*val = hwmon->temp.limit[TEMP_LIMIT_PKG_CRIT] * MILLIDEGREE_PER_DEGREE;
> > > > +			break;
> > > > +		default:
> > > > +			return 0;
> > > > +		}
> > > > +		break;
> > > >   	default:
> > > >   		return -EOPNOTSUPP;
> > > >   	}
> > > > +	return 0;
> > > >   }
> > > >   static umode_t
> > > > @@ -1263,6 +1368,9 @@ xe_hwmon_get_preregistration_info(struct xe_hwmon *hwmon)
> > > >   	for (channel = 0; channel < FAN_MAX; channel++)
> > > >   		if (xe_hwmon_is_visible(hwmon, hwmon_fan, hwmon_fan_input, channel))
> > > >   			xe_hwmon_fan_input_read(hwmon, channel, &fan_speed);
> > > > +
> > > > +	if (xe_hwmon_pcode_read_thermal_info(hwmon))
> > > > +		drm_dbg(&hwmon->xe->drm, "Thermal mailbox support not present in firmware\n");
> > > >   }
> > > >   int xe_hwmon_register(struct xe_device *xe)
> > > > diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> > > > index 673761c8623e..a47637900e84 100644
> > > > --- a/drivers/gpu/drm/xe/xe_pci.c
> > > > +++ b/drivers/gpu/drm/xe/xe_pci.c
> > > > @@ -311,6 +311,7 @@ static const struct xe_device_desc dg2_desc = {
> > > >   	.has_display = true,
> > > >   	.has_fan_control = true,
> > > >   	.has_mbx_power_limits = false,
> > > > +	.has_mbx_thermal_info = false,
> > > Why?
> > > 
> > > >   };
> > > >   static const __maybe_unused struct xe_device_desc pvc_desc = {
> > > > @@ -328,6 +329,7 @@ static const __maybe_unused struct xe_device_desc pvc_desc = {
> > > >   	.vm_max_level = 4,
> > > >   	.vram_flags = XE_VRAM_FLAGS_NEED64K,
> > > >   	.has_mbx_power_limits = false,
> > > > +	.has_mbx_thermal_info = false,
> > > Ditto.
> > > 
> > > >   };
> > > >   static const struct xe_device_desc mtl_desc = {
> > > > @@ -365,6 +367,7 @@ static const struct xe_device_desc bmg_desc = {
> > > >   	.has_fan_control = true,
> > > >   	.has_flat_ccs = 1,
> > > >   	.has_mbx_power_limits = true,
> > > > +	.has_mbx_thermal_info = true,
> > > >   	.has_gsc_nvm = 1,
> > > >   	.has_heci_cscfi = 1,
> > > >   	.has_i2c = true,
> > > > @@ -418,6 +421,7 @@ static const struct xe_device_desc cri_desc = {
> > > >   	.has_flat_ccs = false,
> > > >   	.has_i2c = true,
> > > >   	.has_mbx_power_limits = true,
> > > > +	.has_mbx_thermal_info = true,
> > > >   	.has_mert = true,
> > > >   	.has_pre_prod_wa = 1,
> > > >   	.has_sriov = true,
> > > > @@ -681,6 +685,7 @@ static int xe_info_init_early(struct xe_device *xe,
> > > >   	/* runtime fusing may force flat_ccs to disabled later */
> > > >   	xe->info.has_flat_ccs = desc->has_flat_ccs;
> > > >   	xe->info.has_mbx_power_limits = desc->has_mbx_power_limits;
> > > > +	xe->info.has_mbx_thermal_info = desc->has_mbx_thermal_info;
> > > >   	xe->info.has_gsc_nvm = desc->has_gsc_nvm;
> > > >   	xe->info.has_heci_gscfi = desc->has_heci_gscfi;
> > > >   	xe->info.has_heci_cscfi = desc->has_heci_cscfi;
> > > > diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
> > > > index 3bb51d155951..34d2b66188e4 100644
> > > > --- a/drivers/gpu/drm/xe/xe_pci_types.h
> > > > +++ b/drivers/gpu/drm/xe/xe_pci_types.h
> > > > @@ -48,6 +48,7 @@ struct xe_device_desc {
> > > >   	u8 has_late_bind:1;
> > > >   	u8 has_llc:1;
> > > >   	u8 has_mbx_power_limits:1;
> > > > +	u8 has_mbx_thermal_info:1;
> > > >   	u8 has_mem_copy_instr:1;
> > > >   	u8 has_mert:1;
> > > >   	u8 has_pre_prod_wa:1;
> > > > diff --git a/drivers/gpu/drm/xe/xe_pcode_api.h b/drivers/gpu/drm/xe/xe_pcode_api.h
> > > > index 975892d6b230..a3bff76a074d 100644
> > > > --- a/drivers/gpu/drm/xe/xe_pcode_api.h
> > > > +++ b/drivers/gpu/drm/xe/xe_pcode_api.h
> > > > @@ -65,6 +65,9 @@
> > > >   #define       FAN_TABLE				1
> > > >   #define       VR_CONFIG				2
> > > > +#define	PCODE_THERMAL_INFO			0x25
> > > > +#define	READ_THERMAL_LIMITS			0x0
> > > Does this match with spacing convention and ordering?
> > > 
> > > Raag
> > > 
> > > >   #define   PCODE_FREQUENCY_CONFIG		0x6e
> > > >   /* Frequency Config Sub Commands (param1) */
> > > >   #define     PCODE_MBOX_FC_SC_READ_FUSED_P0	0x0
> > > > -- 
> > > > 2.25.1
> > > > 

[PATCH v3 2/4] drm/xe/hwmon: Expose memory controller temperature

[Karthik Poosa]

Expose GPU memory controller average temperature and its limits
under temp4_xxx.
Update Xe hwmon documentation for this.

v2:
 - Rephrase commit message. (Badal)
 - Update kernel version in Xe hwmon documentation. (Raag)

Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
---
 .../ABI/testing/sysfs-driver-intel-xe-hwmon   | 24 +++++
 drivers/gpu/drm/xe/xe_hwmon.c                 | 94 ++++++++++++++++++-
 drivers/gpu/drm/xe/xe_pcode_api.h             |  4 +
 3 files changed, 118 insertions(+), 4 deletions(-)

diff --git a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
index c8f211c336be..81f9b5d58850 100644
--- a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
+++ b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
@@ -236,3 +236,27 @@ Contact:	intel-xe@lists.freedesktop.org
 Description:	RO. VRAM critical temperature in millidegree Celsius.
 
 		Only supported for particular Intel Xe graphics platforms.
+
+What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp4_input
+Date:		December 2025
+KernelVersion:	6.19
+Contact:	intel-xe@lists.freedesktop.org
+Description:	RO. Memory controller average temperature in millidegree Celsius.
+
+		Only supported for particular Intel Xe graphics platforms.
+
+What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp4_emergency
+Date:		December 2025
+KernelVersion:	6.19
+Contact:	intel-xe@lists.freedesktop.org
+Description:	RO. Memory controller shutdown temperature in millidegree Celsius.
+
+		Only supported for particular Intel Xe graphics platforms.
+
+What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp4_crit
+Date:		December 2025
+KernelVersion:	6.19
+Contact:	intel-xe@lists.freedesktop.org
+Description:	RO. Memory controller critical temperature in millidegree Celsius.
+
+		Only supported for particular Intel Xe graphics platforms.
diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index 66a8c3e40027..6d31ad74cd0e 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -43,6 +43,7 @@ enum xe_hwmon_channel {
 	CHANNEL_CARD,
 	CHANNEL_PKG,
 	CHANNEL_VRAM,
+	CHANNEL_MCTRL,
 	CHANNEL_MAX,
 };
 
@@ -99,6 +100,11 @@ enum sensor_attr_power {
  */
 #define PL_WRITE_MBX_TIMEOUT_MS	(1)
 
+/*
+ * Number of thermal sensors.
+ */
+#define MAX_THERMAL_SENSORS    (255)
+
 /**
  * struct xe_hwmon_energy_info - to accumulate energy
  */
@@ -129,6 +135,10 @@ struct xe_hwmon_thermal_info {
 		/** @data: temperature limits in dwords */
 		u32 data[2];
 	};
+	/** @count: no of temperature sensors */
+	u8 count;
+	/** @value: value from each sensors S1.7 format. */
+	u8 value[MAX_THERMAL_SENSORS];
 };
 
 /**
@@ -702,6 +712,7 @@ static const struct hwmon_channel_info * const hwmon_info[] = {
 			   HWMON_T_LABEL,
 			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT |
 			   HWMON_T_MAX,
+			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
 			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT),
 	HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_LABEL | HWMON_P_CRIT |
 			   HWMON_P_CAP,
@@ -717,6 +728,7 @@ static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
 {
 	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
 	int ret = 0;
+	u32 val = 0;
 
 	if (!hwmon->xe->info.has_mbx_power_limits)
 		return -EOPNOTSUPP;
@@ -727,9 +739,54 @@ static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
 	drm_dbg(&hwmon->xe->drm, "thermal info read ret %d, val 0x%x val1 0x%x\n", ret,
 		hwmon->temp.data[0], hwmon->temp.data[1]);
 
+	/* Read thermal config */
+	ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_CONFIG, 0),
+			    &val, NULL);
+	drm_dbg(&hwmon->xe->drm, "thermal config read ret %d, count %d\n", ret, val);
+	if (ret)
+		return ret;
+
+	hwmon->temp.count = val & TEMP_MASK;
+	if (hwmon->temp.count > MAX_THERMAL_SENSORS) {
+		drm_warn(&hwmon->xe->drm, "thermal config count %d exceeds supported limit %d\n",
+			 hwmon->temp.count, MAX_THERMAL_SENSORS);
+		ret = -ENOMEM;
+	}
 	return ret;
 }
 
+static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
+{
+	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
+	int ret = 0, i = 0;
+
+	for (i = 0; i < (hwmon->temp.count / 4); i++) {
+		/* Read thermal data */
+		ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_DATA, i),
+				    (uint32_t *)&hwmon->temp.value[i * 4], NULL);
+		drm_dbg(&hwmon->xe->drm, "thermal data for group %d ret %d, val 0x%x\n", i, ret,
+			(u32)hwmon->temp.value[i * 4]);
+		if (ret)
+			return ret;
+	}
+	if (hwmon->temp.count % 4) {
+		ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_DATA, i),
+				    (uint32_t *)&hwmon->temp.value[i * 4], NULL);
+		drm_dbg(&hwmon->xe->drm, "thermal data for group %d ret %d, val 0x%x\n", i, ret,
+			(u32)hwmon->temp.value[i * 4]);
+		if (ret)
+			return ret;
+	}
+
+	*val = 0;
+	for (i = TEMP_INDEX_MCTRL; i < hwmon->temp.count; i++) {
+		*val += (hwmon->temp.value[i] & TEMP_MASK_MAILBOX) *
+			((hwmon->temp.value[i] & 0x80) ? -1 : 1);
+	}
+	*val = (*val / hwmon->temp.count) * MILLIDEGREE_PER_DEGREE;
+	return 0;
+}
+
 /* I1 is exposed as power_crit or as curr_crit depending on bit 31 */
 static int xe_hwmon_pcode_read_i1(const struct xe_hwmon *hwmon, u32 *uval)
 {
@@ -827,6 +884,8 @@ static void xe_hwmon_get_voltage(struct xe_hwmon *hwmon, int channel, long *valu
 static umode_t
 xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 {
+	long val = 0;
+
 	switch (attr) {
 	case hwmon_temp_emergency:
 		switch (channel) {
@@ -834,6 +893,8 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 			return hwmon->temp.limit[TEMP_LIMIT_PKG_SHUTDOWN] ? 0444 : 0;
 		case CHANNEL_VRAM:
 			return hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN] ? 0444 : 0;
+		case CHANNEL_MCTRL:
+			return (!get_mc_temp(hwmon, &val)) ? 0444 : 0;
 		default:
 			return 0;
 		}
@@ -844,6 +905,8 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 			return hwmon->temp.limit[TEMP_LIMIT_PKG_TJMAX] ? 0444 : 0;
 		case CHANNEL_VRAM:
 			return hwmon->temp.limit[TEMP_LIMIT_MEM_TJMAX] ? 0444 : 0;
+		case CHANNEL_MCTRL:
+			return (!get_mc_temp(hwmon, &val)) ? 0444 : 0;
 		default:
 			return 0;
 		}
@@ -858,7 +921,16 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 		break;
 	case hwmon_temp_input:
 	case hwmon_temp_label:
-		return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_TEMP, channel)) ? 0444 : 0;
+		switch (channel) {
+		case CHANNEL_PKG:
+		case CHANNEL_VRAM:
+			return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_TEMP,
+					       channel)) ? 0444 : 0;
+		case CHANNEL_MCTRL:
+			return (!get_mc_temp(hwmon, &val)) ? 0444 : 0;
+		default:
+			return 0;
+		}
 	default:
 		return 0;
 	}
@@ -872,10 +944,20 @@ xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
 
 	switch (attr) {
 	case hwmon_temp_input:
-		reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_TEMP, channel));
+		switch (channel) {
+		case CHANNEL_PKG:
+		case CHANNEL_VRAM:
+			reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_TEMP, channel));
 
-		/* HW register value is in degrees Celsius, convert to millidegrees. */
-		*val = REG_FIELD_GET(TEMP_MASK, reg_val) * MILLIDEGREE_PER_DEGREE;
+			/* HW register value is in degrees Celsius, convert to millidegrees. */
+			*val = REG_FIELD_GET(TEMP_MASK, reg_val) * MILLIDEGREE_PER_DEGREE;
+			break;
+		case CHANNEL_MCTRL:
+			return get_mc_temp(hwmon, val);
+		default:
+			*val = 0;
+			return -EOPNOTSUPP;
+		}
 		break;
 	case hwmon_temp_emergency:
 		switch (channel) {
@@ -883,6 +965,7 @@ xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
 			*val = hwmon->temp.limit[TEMP_LIMIT_PKG_SHUTDOWN] * MILLIDEGREE_PER_DEGREE;
 			break;
 		case CHANNEL_VRAM:
+		case CHANNEL_MCTRL:
 			*val = hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN] * MILLIDEGREE_PER_DEGREE;
 			break;
 		default:
@@ -896,6 +979,7 @@ xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
 			*val = hwmon->temp.limit[TEMP_LIMIT_PKG_TJMAX] * MILLIDEGREE_PER_DEGREE;
 			break;
 		case CHANNEL_VRAM:
+		case CHANNEL_MCTRL:
 			*val = hwmon->temp.limit[TEMP_LIMIT_MEM_TJMAX] * MILLIDEGREE_PER_DEGREE;
 			break;
 		default:
@@ -1274,6 +1358,8 @@ static int xe_hwmon_read_label(struct device *dev,
 			*str = "pkg";
 		else if (channel == CHANNEL_VRAM)
 			*str = "vram";
+		else if (channel == CHANNEL_MCTRL)
+			*str = "mctrl_avg";
 		return 0;
 	case hwmon_power:
 	case hwmon_energy:
diff --git a/drivers/gpu/drm/xe/xe_pcode_api.h b/drivers/gpu/drm/xe/xe_pcode_api.h
index a3bff76a074d..91e232834482 100644
--- a/drivers/gpu/drm/xe/xe_pcode_api.h
+++ b/drivers/gpu/drm/xe/xe_pcode_api.h
@@ -67,6 +67,10 @@
 
 #define	PCODE_THERMAL_INFO			0x25
 #define	READ_THERMAL_LIMITS			0x0
+#define	READ_THERMAL_CONFIG			0x1
+#define	READ_THERMAL_DATA			0x2
+#define TEMP_MASK_MAILBOX			REG_GENMASK8(6, 0)
+#define TEMP_INDEX_MCTRL			0x2
 
 #define   PCODE_FREQUENCY_CONFIG		0x6e
 /* Frequency Config Sub Commands (param1) */
-- 
2.25.1

Re: [PATCH v3 2/4] drm/xe/hwmon: Expose memory controller temperature

[Raag Jadav]

On Tue, Dec 16, 2025 at 05:10:28PM +0530, Karthik Poosa wrote:
> Expose GPU memory controller average temperature and its limits
> under temp4_xxx.
> Update Xe hwmon documentation for this.
> 
> v2:
>  - Rephrase commit message. (Badal)
>  - Update kernel version in Xe hwmon documentation. (Raag)
> 
> Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
> ---
>  .../ABI/testing/sysfs-driver-intel-xe-hwmon   | 24 +++++
>  drivers/gpu/drm/xe/xe_hwmon.c                 | 94 ++++++++++++++++++-
>  drivers/gpu/drm/xe/xe_pcode_api.h             |  4 +
>  3 files changed, 118 insertions(+), 4 deletions(-)
> 
> diff --git a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> index c8f211c336be..81f9b5d58850 100644
> --- a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> +++ b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> @@ -236,3 +236,27 @@ Contact:	intel-xe@lists.freedesktop.org
>  Description:	RO. VRAM critical temperature in millidegree Celsius.
>  
>  		Only supported for particular Intel Xe graphics platforms.
> +
> +What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp4_input
> +Date:		December 2025
> +KernelVersion:	6.19
> +Contact:	intel-xe@lists.freedesktop.org
> +Description:	RO. Memory controller average temperature in millidegree Celsius.
> +
> +		Only supported for particular Intel Xe graphics platforms.
> +
> +What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp4_emergency
> +Date:		December 2025
> +KernelVersion:	6.19
> +Contact:	intel-xe@lists.freedesktop.org
> +Description:	RO. Memory controller shutdown temperature in millidegree Celsius.
> +
> +		Only supported for particular Intel Xe graphics platforms.
> +
> +What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp4_crit
> +Date:		December 2025
> +KernelVersion:	6.19
> +Contact:	intel-xe@lists.freedesktop.org
> +Description:	RO. Memory controller critical temperature in millidegree Celsius.
> +
> +		Only supported for particular Intel Xe graphics platforms.

Same as patch 1. These attributes defer from ABI definition so not my call.

> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index 66a8c3e40027..6d31ad74cd0e 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> @@ -43,6 +43,7 @@ enum xe_hwmon_channel {
>  	CHANNEL_CARD,
>  	CHANNEL_PKG,
>  	CHANNEL_VRAM,
> +	CHANNEL_MCTRL,
>  	CHANNEL_MAX,
>  };
>  
> @@ -99,6 +100,11 @@ enum sensor_attr_power {
>   */
>  #define PL_WRITE_MBX_TIMEOUT_MS	(1)
>  
> +/*
> + * Number of thermal sensors.
> + */
> +#define MAX_THERMAL_SENSORS    (255)
> +
>  /**
>   * struct xe_hwmon_energy_info - to accumulate energy
>   */
> @@ -129,6 +135,10 @@ struct xe_hwmon_thermal_info {
>  		/** @data: temperature limits in dwords */
>  		u32 data[2];
>  	};
> +	/** @count: no of temperature sensors */
> +	u8 count;
> +	/** @value: value from each sensors S1.7 format. */
> +	u8 value[MAX_THERMAL_SENSORS];
>  };
>  
>  /**
> @@ -702,6 +712,7 @@ static const struct hwmon_channel_info * const hwmon_info[] = {
>  			   HWMON_T_LABEL,
>  			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT |
>  			   HWMON_T_MAX,
> +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
>  			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT),
>  	HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_LABEL | HWMON_P_CRIT |
>  			   HWMON_P_CAP,
> @@ -717,6 +728,7 @@ static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
>  {
>  	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
>  	int ret = 0;
> +	u32 val = 0;
>  
>  	if (!hwmon->xe->info.has_mbx_power_limits)
>  		return -EOPNOTSUPP;
> @@ -727,9 +739,54 @@ static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
>  	drm_dbg(&hwmon->xe->drm, "thermal info read ret %d, val 0x%x val1 0x%x\n", ret,
>  		hwmon->temp.data[0], hwmon->temp.data[1]);
>  
> +	/* Read thermal config */

Comments are usually helpful for something that's not obvious from the code,
so no need for tautology (and also in all other places where applicable).

> +	ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_CONFIG, 0),
> +			    &val, NULL);
> +	drm_dbg(&hwmon->xe->drm, "thermal config read ret %d, count %d\n", ret, val);

This is redundant in error cases because the pcode helper already prints the
error code and count won't be present.

> +	if (ret)
> +		return ret;
> +
> +	hwmon->temp.count = val & TEMP_MASK;
> +	if (hwmon->temp.count > MAX_THERMAL_SENSORS) {

How does a u8 variable exceed the value of 255? ...

> +		drm_warn(&hwmon->xe->drm, "thermal config count %d exceeds supported limit %d\n",
> +			 hwmon->temp.count, MAX_THERMAL_SENSORS);
> +		ret = -ENOMEM;

... and how does it translate to 'out of memory'?

> +	}
>  	return ret;
>  }
>  
> +static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
> +{
> +	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
> +	int ret = 0, i = 0;
> +
> +	for (i = 0; i < (hwmon->temp.count / 4); i++) {

Magic 4.

> +		/* Read thermal data */
> +		ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_DATA, i),
> +				    (uint32_t *)&hwmon->temp.value[i * 4], NULL);

Let's not solve a problem that doesn't exist and try to work without
a cast.

> +		drm_dbg(&hwmon->xe->drm, "thermal data for group %d ret %d, val 0x%x\n", i, ret,
> +			(u32)hwmon->temp.value[i * 4]);

Ditto. And you're using both uint32_t and u32, make it consistent.

> +		if (ret)
> +			return ret;
> +	}
> +	if (hwmon->temp.count % 4) {
> +		ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_DATA, i),
> +				    (uint32_t *)&hwmon->temp.value[i * 4], NULL);

Ditto.

> +		drm_dbg(&hwmon->xe->drm, "thermal data for group %d ret %d, val 0x%x\n", i, ret,
> +			(u32)hwmon->temp.value[i * 4]);

Ditto.

> +		if (ret)
> +			return ret;
> +	}
> +
> +	*val = 0;
> +	for (i = TEMP_INDEX_MCTRL; i < hwmon->temp.count; i++) {
> +		*val += (hwmon->temp.value[i] & TEMP_MASK_MAILBOX) *
> +			((hwmon->temp.value[i] & 0x80) ? -1 : 1);

Now, this is something that needs an explanation but doesn't have it ...

> +	}
> +	*val = (*val / hwmon->temp.count) * MILLIDEGREE_PER_DEGREE;

... and the math is independent of the assignment so let's do them
separately.

> +	return 0;
> +}
> +
>  /* I1 is exposed as power_crit or as curr_crit depending on bit 31 */
>  static int xe_hwmon_pcode_read_i1(const struct xe_hwmon *hwmon, u32 *uval)
>  {
> @@ -827,6 +884,8 @@ static void xe_hwmon_get_voltage(struct xe_hwmon *hwmon, int channel, long *valu
>  static umode_t
>  xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
>  {
> +	long val = 0;
> +
>  	switch (attr) {
>  	case hwmon_temp_emergency:
>  		switch (channel) {
> @@ -834,6 +893,8 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
>  			return hwmon->temp.limit[TEMP_LIMIT_PKG_SHUTDOWN] ? 0444 : 0;
>  		case CHANNEL_VRAM:
>  			return hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN] ? 0444 : 0;
> +		case CHANNEL_MCTRL:
> +			return (!get_mc_temp(hwmon, &val)) ? 0444 : 0;

Do we really need to read it all here?

>  		default:
>  			return 0;
>  		}
> @@ -844,6 +905,8 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
>  			return hwmon->temp.limit[TEMP_LIMIT_PKG_TJMAX] ? 0444 : 0;
>  		case CHANNEL_VRAM:
>  			return hwmon->temp.limit[TEMP_LIMIT_MEM_TJMAX] ? 0444 : 0;
> +		case CHANNEL_MCTRL:
> +			return (!get_mc_temp(hwmon, &val)) ? 0444 : 0;

Ditto.

>  		default:
>  			return 0;
>  		}
> @@ -858,7 +921,16 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
>  		break;
>  	case hwmon_temp_input:
>  	case hwmon_temp_label:
> -		return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_TEMP, channel)) ? 0444 : 0;
> +		switch (channel) {
> +		case CHANNEL_PKG:
> +		case CHANNEL_VRAM:
> +			return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_TEMP,
> +					       channel)) ? 0444 : 0;
> +		case CHANNEL_MCTRL:
> +			return (!get_mc_temp(hwmon, &val)) ? 0444 : 0;

Ditto.

> +		default:
> +			return 0;
> +		}
>  	default:
>  		return 0;
>  	}
> @@ -872,10 +944,20 @@ xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
>  
>  	switch (attr) {
>  	case hwmon_temp_input:
> -		reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_TEMP, channel));
> +		switch (channel) {
> +		case CHANNEL_PKG:
> +		case CHANNEL_VRAM:
> +			reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_TEMP, channel));
>  
> -		/* HW register value is in degrees Celsius, convert to millidegrees. */
> -		*val = REG_FIELD_GET(TEMP_MASK, reg_val) * MILLIDEGREE_PER_DEGREE;
> +			/* HW register value is in degrees Celsius, convert to millidegrees. */
> +			*val = REG_FIELD_GET(TEMP_MASK, reg_val) * MILLIDEGREE_PER_DEGREE;
> +			break;
> +		case CHANNEL_MCTRL:
> +			return get_mc_temp(hwmon, val);
> +		default:
> +			*val = 0;

Do you need this?

> +			return -EOPNOTSUPP;
> +		}
>  		break;
>  	case hwmon_temp_emergency:
>  		switch (channel) {
> @@ -883,6 +965,7 @@ xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
>  			*val = hwmon->temp.limit[TEMP_LIMIT_PKG_SHUTDOWN] * MILLIDEGREE_PER_DEGREE;
>  			break;
>  		case CHANNEL_VRAM:
> +		case CHANNEL_MCTRL:
>  			*val = hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN] * MILLIDEGREE_PER_DEGREE;
>  			break;
>  		default:
> @@ -896,6 +979,7 @@ xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
>  			*val = hwmon->temp.limit[TEMP_LIMIT_PKG_TJMAX] * MILLIDEGREE_PER_DEGREE;
>  			break;
>  		case CHANNEL_VRAM:
> +		case CHANNEL_MCTRL:
>  			*val = hwmon->temp.limit[TEMP_LIMIT_MEM_TJMAX] * MILLIDEGREE_PER_DEGREE;
>  			break;
>  		default:
> @@ -1274,6 +1358,8 @@ static int xe_hwmon_read_label(struct device *dev,
>  			*str = "pkg";
>  		else if (channel == CHANNEL_VRAM)
>  			*str = "vram";
> +		else if (channel == CHANNEL_MCTRL)
> +			*str = "mctrl_avg";

The rest of the channels also signify the average so no need to spell
it out.

Raag

>  		return 0;
>  	case hwmon_power:
>  	case hwmon_energy:
> diff --git a/drivers/gpu/drm/xe/xe_pcode_api.h b/drivers/gpu/drm/xe/xe_pcode_api.h
> index a3bff76a074d..91e232834482 100644
> --- a/drivers/gpu/drm/xe/xe_pcode_api.h
> +++ b/drivers/gpu/drm/xe/xe_pcode_api.h
> @@ -67,6 +67,10 @@
>  
>  #define	PCODE_THERMAL_INFO			0x25
>  #define	READ_THERMAL_LIMITS			0x0
> +#define	READ_THERMAL_CONFIG			0x1
> +#define	READ_THERMAL_DATA			0x2
> +#define TEMP_MASK_MAILBOX			REG_GENMASK8(6, 0)
> +#define TEMP_INDEX_MCTRL			0x2
>  
>  #define   PCODE_FREQUENCY_CONFIG		0x6e
>  /* Frequency Config Sub Commands (param1) */
> -- 
> 2.25.1
> 

Re: [PATCH v3 2/4] drm/xe/hwmon: Expose memory controller temperature

[Poosa, Karthik]

On 19-12-2025 13:25, Raag Jadav wrote:
> On Tue, Dec 16, 2025 at 05:10:28PM +0530, Karthik Poosa wrote:
>> Expose GPU memory controller average temperature and its limits
>> under temp4_xxx.
>> Update Xe hwmon documentation for this.
>>
>> v2:
>>   - Rephrase commit message. (Badal)
>>   - Update kernel version in Xe hwmon documentation. (Raag)
>>
>> Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
>> ---
>>   .../ABI/testing/sysfs-driver-intel-xe-hwmon   | 24 +++++
>>   drivers/gpu/drm/xe/xe_hwmon.c                 | 94 ++++++++++++++++++-
>>   drivers/gpu/drm/xe/xe_pcode_api.h             |  4 +
>>   3 files changed, 118 insertions(+), 4 deletions(-)
>>
>> diff --git a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
>> index c8f211c336be..81f9b5d58850 100644
>> --- a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
>> +++ b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
>> @@ -236,3 +236,27 @@ Contact:	intel-xe@lists.freedesktop.org
>>   Description:	RO. VRAM critical temperature in millidegree Celsius.
>>   
>>   		Only supported for particular Intel Xe graphics platforms.
>> +
>> +What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp4_input
>> +Date:		December 2025
>> +KernelVersion:	6.19
>> +Contact:	intel-xe@lists.freedesktop.org
>> +Description:	RO. Memory controller average temperature in millidegree Celsius.
>> +
>> +		Only supported for particular Intel Xe graphics platforms.
>> +
>> +What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp4_emergency
>> +Date:		December 2025
>> +KernelVersion:	6.19
>> +Contact:	intel-xe@lists.freedesktop.org
>> +Description:	RO. Memory controller shutdown temperature in millidegree Celsius.
>> +
>> +		Only supported for particular Intel Xe graphics platforms.
>> +
>> +What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp4_crit
>> +Date:		December 2025
>> +KernelVersion:	6.19
>> +Contact:	intel-xe@lists.freedesktop.org
>> +Description:	RO. Memory controller critical temperature in millidegree Celsius.
>> +
>> +		Only supported for particular Intel Xe graphics platforms.
> Same as patch 1. These attributes defer from ABI definition so not my call.
>
>> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
>> index 66a8c3e40027..6d31ad74cd0e 100644
>> --- a/drivers/gpu/drm/xe/xe_hwmon.c
>> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
>> @@ -43,6 +43,7 @@ enum xe_hwmon_channel {
>>   	CHANNEL_CARD,
>>   	CHANNEL_PKG,
>>   	CHANNEL_VRAM,
>> +	CHANNEL_MCTRL,
>>   	CHANNEL_MAX,
>>   };
>>   
>> @@ -99,6 +100,11 @@ enum sensor_attr_power {
>>    */
>>   #define PL_WRITE_MBX_TIMEOUT_MS	(1)
>>   
>> +/*
>> + * Number of thermal sensors.
>> + */
>> +#define MAX_THERMAL_SENSORS    (255)
>> +
>>   /**
>>    * struct xe_hwmon_energy_info - to accumulate energy
>>    */
>> @@ -129,6 +135,10 @@ struct xe_hwmon_thermal_info {
>>   		/** @data: temperature limits in dwords */
>>   		u32 data[2];
>>   	};
>> +	/** @count: no of temperature sensors */
>> +	u8 count;
>> +	/** @value: value from each sensors S1.7 format. */
>> +	u8 value[MAX_THERMAL_SENSORS];
>>   };
>>   
>>   /**
>> @@ -702,6 +712,7 @@ static const struct hwmon_channel_info * const hwmon_info[] = {
>>   			   HWMON_T_LABEL,
>>   			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT |
>>   			   HWMON_T_MAX,
>> +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
>>   			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT),
>>   	HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_LABEL | HWMON_P_CRIT |
>>   			   HWMON_P_CAP,
>> @@ -717,6 +728,7 @@ static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
>>   {
>>   	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
>>   	int ret = 0;
>> +	u32 val = 0;
>>   
>>   	if (!hwmon->xe->info.has_mbx_power_limits)
>>   		return -EOPNOTSUPP;
>> @@ -727,9 +739,54 @@ static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
>>   	drm_dbg(&hwmon->xe->drm, "thermal info read ret %d, val 0x%x val1 0x%x\n", ret,
>>   		hwmon->temp.data[0], hwmon->temp.data[1]);
>>   
>> +	/* Read thermal config */
> Comments are usually helpful for something that's not obvious from the code,
> so no need for tautology (and also in all other places where applicable).
will remove this
>
>> +	ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_CONFIG, 0),
>> +			    &val, NULL);
>> +	drm_dbg(&hwmon->xe->drm, "thermal config read ret %d, count %d\n", ret, val);
> This is redundant in error cases because the pcode helper already prints the
> error code and count won't be present.
it will be helpful to know the count during debug
>
>> +	if (ret)
>> +		return ret;
>> +
>> +	hwmon->temp.count = val & TEMP_MASK;
>> +	if (hwmon->temp.count > MAX_THERMAL_SENSORS) {
> How does a u8 variable exceed the value of 255? ...
it is not needed, this can be removed
>
>> +		drm_warn(&hwmon->xe->drm, "thermal config count %d exceeds supported limit %d\n",
>> +			 hwmon->temp.count, MAX_THERMAL_SENSORS);
>> +		ret = -ENOMEM;
> ... and how does it translate to 'out of memory'?

Earlier patch we have allocated memory only for 11 sensors, so we had 
this check,

it is not needed now as we are storing memory for MAX_THERMAL_SENSORS

>
>> +	}
>>   	return ret;
>>   }
>>   
>> +static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
>> +{
>> +	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
>> +	int ret = 0, i = 0;
>> +
>> +	for (i = 0; i < (hwmon->temp.count / 4); i++) {
> Magic 4.
sizeof(u32), will change this
>
>> +		/* Read thermal data */
>> +		ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_DATA, i),
>> +				    (uint32_t *)&hwmon->temp.value[i * 4], NULL);
> Let's not solve a problem that doesn't exist and try to work without
> a cast.
>
>> +		drm_dbg(&hwmon->xe->drm, "thermal data for group %d ret %d, val 0x%x\n", i, ret,
>> +			(u32)hwmon->temp.value[i * 4]);
> Ditto. And you're using both uint32_t and u32, make it consistent.
ok
>
>> +		if (ret)
>> +			return ret;
>> +	}
>> +	if (hwmon->temp.count % 4) {
>> +		ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_DATA, i),
>> +				    (uint32_t *)&hwmon->temp.value[i * 4], NULL);
> Ditto.
>
>> +		drm_dbg(&hwmon->xe->drm, "thermal data for group %d ret %d, val 0x%x\n", i, ret,
>> +			(u32)hwmon->temp.value[i * 4]);
> Ditto.
>
>> +		if (ret)
>> +			return ret;
>> +	}
>> +
>> +	*val = 0;
>> +	for (i = TEMP_INDEX_MCTRL; i < hwmon->temp.count; i++) {
>> +		*val += (hwmon->temp.value[i] & TEMP_MASK_MAILBOX) *
>> +			((hwmon->temp.value[i] & 0x80) ? -1 : 1);
> Now, this is something that needs an explanation but doesn't have it ...
Signed for S1.7, bit 7 for sign, 6:0 for value, adding comment in next 
revision
>
>> +	}
>> +	*val = (*val / hwmon->temp.count) * MILLIDEGREE_PER_DEGREE;
> ... and the math is independent of the assignment so let's do them
> separately.
okay
>
>> +	return 0;
>> +}
>> +
>>   /* I1 is exposed as power_crit or as curr_crit depending on bit 31 */
>>   static int xe_hwmon_pcode_read_i1(const struct xe_hwmon *hwmon, u32 *uval)
>>   {
>> @@ -827,6 +884,8 @@ static void xe_hwmon_get_voltage(struct xe_hwmon *hwmon, int channel, long *valu
>>   static umode_t
>>   xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
>>   {
>> +	long val = 0;
>> +
>>   	switch (attr) {
>>   	case hwmon_temp_emergency:
>>   		switch (channel) {
>> @@ -834,6 +893,8 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
>>   			return hwmon->temp.limit[TEMP_LIMIT_PKG_SHUTDOWN] ? 0444 : 0;
>>   		case CHANNEL_VRAM:
>>   			return hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN] ? 0444 : 0;
>> +		case CHANNEL_MCTRL:
>> +			return (!get_mc_temp(hwmon, &val)) ? 0444 : 0;
> Do we really need to read it all here?
we can make visible based on hwmon->temp.count > 0
>
>>   		default:
>>   			return 0;
>>   		}
>> @@ -844,6 +905,8 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
>>   			return hwmon->temp.limit[TEMP_LIMIT_PKG_TJMAX] ? 0444 : 0;
>>   		case CHANNEL_VRAM:
>>   			return hwmon->temp.limit[TEMP_LIMIT_MEM_TJMAX] ? 0444 : 0;
>> +		case CHANNEL_MCTRL:
>> +			return (!get_mc_temp(hwmon, &val)) ? 0444 : 0;
> Ditto.
>
>>   		default:
>>   			return 0;
>>   		}
>> @@ -858,7 +921,16 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
>>   		break;
>>   	case hwmon_temp_input:
>>   	case hwmon_temp_label:
>> -		return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_TEMP, channel)) ? 0444 : 0;
>> +		switch (channel) {
>> +		case CHANNEL_PKG:
>> +		case CHANNEL_VRAM:
>> +			return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_TEMP,
>> +					       channel)) ? 0444 : 0;
>> +		case CHANNEL_MCTRL:
>> +			return (!get_mc_temp(hwmon, &val)) ? 0444 : 0;
> Ditto.
>
>> +		default:
>> +			return 0;
>> +		}
>>   	default:
>>   		return 0;
>>   	}
>> @@ -872,10 +944,20 @@ xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
>>   
>>   	switch (attr) {
>>   	case hwmon_temp_input:
>> -		reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_TEMP, channel));
>> +		switch (channel) {
>> +		case CHANNEL_PKG:
>> +		case CHANNEL_VRAM:
>> +			reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_TEMP, channel));
>>   
>> -		/* HW register value is in degrees Celsius, convert to millidegrees. */
>> -		*val = REG_FIELD_GET(TEMP_MASK, reg_val) * MILLIDEGREE_PER_DEGREE;
>> +			/* HW register value is in degrees Celsius, convert to millidegrees. */
>> +			*val = REG_FIELD_GET(TEMP_MASK, reg_val) * MILLIDEGREE_PER_DEGREE;
>> +			break;
>> +		case CHANNEL_MCTRL:
>> +			return get_mc_temp(hwmon, val);
>> +		default:
>> +			*val = 0;
> Do you need this?
incase *val is garbage this shall make this 0
>
>> +			return -EOPNOTSUPP;
>> +		}
>>   		break;
>>   	case hwmon_temp_emergency:
>>   		switch (channel) {
>> @@ -883,6 +965,7 @@ xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
>>   			*val = hwmon->temp.limit[TEMP_LIMIT_PKG_SHUTDOWN] * MILLIDEGREE_PER_DEGREE;
>>   			break;
>>   		case CHANNEL_VRAM:
>> +		case CHANNEL_MCTRL:
>>   			*val = hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN] * MILLIDEGREE_PER_DEGREE;
>>   			break;
>>   		default:
>> @@ -896,6 +979,7 @@ xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
>>   			*val = hwmon->temp.limit[TEMP_LIMIT_PKG_TJMAX] * MILLIDEGREE_PER_DEGREE;
>>   			break;
>>   		case CHANNEL_VRAM:
>> +		case CHANNEL_MCTRL:
>>   			*val = hwmon->temp.limit[TEMP_LIMIT_MEM_TJMAX] * MILLIDEGREE_PER_DEGREE;
>>   			break;
>>   		default:
>> @@ -1274,6 +1358,8 @@ static int xe_hwmon_read_label(struct device *dev,
>>   			*str = "pkg";
>>   		else if (channel == CHANNEL_VRAM)
>>   			*str = "vram";
>> +		else if (channel == CHANNEL_MCTRL)
>> +			*str = "mctrl_avg";
> The rest of the channels also signify the average so no need to spell
> it out.
>
> Raag
ok
>
>>   		return 0;
>>   	case hwmon_power:
>>   	case hwmon_energy:
>> diff --git a/drivers/gpu/drm/xe/xe_pcode_api.h b/drivers/gpu/drm/xe/xe_pcode_api.h
>> index a3bff76a074d..91e232834482 100644
>> --- a/drivers/gpu/drm/xe/xe_pcode_api.h
>> +++ b/drivers/gpu/drm/xe/xe_pcode_api.h
>> @@ -67,6 +67,10 @@
>>   
>>   #define	PCODE_THERMAL_INFO			0x25
>>   #define	READ_THERMAL_LIMITS			0x0
>> +#define	READ_THERMAL_CONFIG			0x1
>> +#define	READ_THERMAL_DATA			0x2
>> +#define TEMP_MASK_MAILBOX			REG_GENMASK8(6, 0)
>> +#define TEMP_INDEX_MCTRL			0x2
>>   
>>   #define   PCODE_FREQUENCY_CONFIG		0x6e
>>   /* Frequency Config Sub Commands (param1) */
>> -- 
>> 2.25.1
>>

Re: [PATCH v3 2/4] drm/xe/hwmon: Expose memory controller temperature

[Poosa, Karthik]

On 19-12-2025 13:25, Raag Jadav wrote:
> On Tue, Dec 16, 2025 at 05:10:28PM +0530, Karthik Poosa wrote:
>> Expose GPU memory controller average temperature and its limits
>> under temp4_xxx.
>> Update Xe hwmon documentation for this.
>>
>> v2:
>>   - Rephrase commit message. (Badal)
>>   - Update kernel version in Xe hwmon documentation. (Raag)
>>
>> Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
>> ---
>>   .../ABI/testing/sysfs-driver-intel-xe-hwmon   | 24 +++++
>>   drivers/gpu/drm/xe/xe_hwmon.c                 | 94 ++++++++++++++++++-
>>   drivers/gpu/drm/xe/xe_pcode_api.h             |  4 +
>>   3 files changed, 118 insertions(+), 4 deletions(-)
>>
>> diff --git a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
>> index c8f211c336be..81f9b5d58850 100644
>> --- a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
>> +++ b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
>> @@ -236,3 +236,27 @@ Contact:	intel-xe@lists.freedesktop.org
>>   Description:	RO. VRAM critical temperature in millidegree Celsius.
>>   
>>   		Only supported for particular Intel Xe graphics platforms.
>> +
>> +What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp4_input
>> +Date:		December 2025
>> +KernelVersion:	6.19
>> +Contact:	intel-xe@lists.freedesktop.org
>> +Description:	RO. Memory controller average temperature in millidegree Celsius.
>> +
>> +		Only supported for particular Intel Xe graphics platforms.
>> +
>> +What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp4_emergency
>> +Date:		December 2025
>> +KernelVersion:	6.19
>> +Contact:	intel-xe@lists.freedesktop.org
>> +Description:	RO. Memory controller shutdown temperature in millidegree Celsius.
>> +
>> +		Only supported for particular Intel Xe graphics platforms.
>> +
>> +What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp4_crit
>> +Date:		December 2025
>> +KernelVersion:	6.19
>> +Contact:	intel-xe@lists.freedesktop.org
>> +Description:	RO. Memory controller critical temperature in millidegree Celsius.
>> +
>> +		Only supported for particular Intel Xe graphics platforms.
> Same as patch 1. These attributes defer from ABI definition so not my call.
>
>> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
>> index 66a8c3e40027..6d31ad74cd0e 100644
>> --- a/drivers/gpu/drm/xe/xe_hwmon.c
>> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
>> @@ -43,6 +43,7 @@ enum xe_hwmon_channel {
>>   	CHANNEL_CARD,
>>   	CHANNEL_PKG,
>>   	CHANNEL_VRAM,
>> +	CHANNEL_MCTRL,
>>   	CHANNEL_MAX,
>>   };
>>   
>> @@ -99,6 +100,11 @@ enum sensor_attr_power {
>>    */
>>   #define PL_WRITE_MBX_TIMEOUT_MS	(1)
>>   
>> +/*
>> + * Number of thermal sensors.
>> + */
>> +#define MAX_THERMAL_SENSORS    (255)
>> +
>>   /**
>>    * struct xe_hwmon_energy_info - to accumulate energy
>>    */
>> @@ -129,6 +135,10 @@ struct xe_hwmon_thermal_info {
>>   		/** @data: temperature limits in dwords */
>>   		u32 data[2];
>>   	};
>> +	/** @count: no of temperature sensors */
>> +	u8 count;
>> +	/** @value: value from each sensors S1.7 format. */
>> +	u8 value[MAX_THERMAL_SENSORS];
>>   };
>>   
>>   /**
>> @@ -702,6 +712,7 @@ static const struct hwmon_channel_info * const hwmon_info[] = {
>>   			   HWMON_T_LABEL,
>>   			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT |
>>   			   HWMON_T_MAX,
>> +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
>>   			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT),
>>   	HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_LABEL | HWMON_P_CRIT |
>>   			   HWMON_P_CAP,
>> @@ -717,6 +728,7 @@ static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
>>   {
>>   	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
>>   	int ret = 0;
>> +	u32 val = 0;
>>   
>>   	if (!hwmon->xe->info.has_mbx_power_limits)
>>   		return -EOPNOTSUPP;
>> @@ -727,9 +739,54 @@ static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
>>   	drm_dbg(&hwmon->xe->drm, "thermal info read ret %d, val 0x%x val1 0x%x\n", ret,
>>   		hwmon->temp.data[0], hwmon->temp.data[1]);
>>   
>> +	/* Read thermal config */
> Comments are usually helpful for something that's not obvious from the code,
> so no need for tautology (and also in all other places where applicable).
will remove this
>
>> +	ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_CONFIG, 0),
>> +			    &val, NULL);
>> +	drm_dbg(&hwmon->xe->drm, "thermal config read ret %d, count %d\n", ret, val);
> This is redundant in error cases because the pcode helper already prints the
> error code and count won't be present.
it will be helpful to know the count during debug
>
>> +	if (ret)
>> +		return ret;
>> +
>> +	hwmon->temp.count = val & TEMP_MASK;
>> +	if (hwmon->temp.count > MAX_THERMAL_SENSORS) {
> How does a u8 variable exceed the value of 255? ...
it is not needed, this can be removed
>
>> +		drm_warn(&hwmon->xe->drm, "thermal config count %d exceeds supported limit %d\n",
>> +			 hwmon->temp.count, MAX_THERMAL_SENSORS);
>> +		ret = -ENOMEM;
> ... and how does it translate to 'out of memory'?

Earlier patch we have allocated memory only for 11 sensors, so we had 
this check,

it is not needed now as we are storing memory for MAX_THERMAL_SENSORS

>
>> +	}
>>   	return ret;
>>   }
>>   
>> +static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
>> +{
>> +	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
>> +	int ret = 0, i = 0;
>> +
>> +	for (i = 0; i < (hwmon->temp.count / 4); i++) {
> Magic 4.
sizeof(u32), will change this
>
>> +		/* Read thermal data */
>> +		ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_DATA, i),
>> +				    (uint32_t *)&hwmon->temp.value[i * 4], NULL);
> Let's not solve a problem that doesn't exist and try to work without
> a cast.
>
>> +		drm_dbg(&hwmon->xe->drm, "thermal data for group %d ret %d, val 0x%x\n", i, ret,
>> +			(u32)hwmon->temp.value[i * 4]);
> Ditto. And you're using both uint32_t and u32, make it consistent.
ok
>
>> +		if (ret)
>> +			return ret;
>> +	}
>> +	if (hwmon->temp.count % 4) {
>> +		ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_DATA, i),
>> +				    (uint32_t *)&hwmon->temp.value[i * 4], NULL);
> Ditto.
>
>> +		drm_dbg(&hwmon->xe->drm, "thermal data for group %d ret %d, val 0x%x\n", i, ret,
>> +			(u32)hwmon->temp.value[i * 4]);
> Ditto.
>
>> +		if (ret)
>> +			return ret;
>> +	}
>> +
>> +	*val = 0;
>> +	for (i = TEMP_INDEX_MCTRL; i < hwmon->temp.count; i++) {
>> +		*val += (hwmon->temp.value[i] & TEMP_MASK_MAILBOX) *
>> +			((hwmon->temp.value[i] & 0x80) ? -1 : 1);
> Now, this is something that needs an explanation but doesn't have it ...
Signed for S1.7, bit 7 for sign, 6:0 for value, adding comment in next 
revision
>
>> +	}
>> +	*val = (*val / hwmon->temp.count) * MILLIDEGREE_PER_DEGREE;
> ... and the math is independent of the assignment so let's do them
> separately.
okay
>
>> +	return 0;
>> +}
>> +
>>   /* I1 is exposed as power_crit or as curr_crit depending on bit 31 */
>>   static int xe_hwmon_pcode_read_i1(const struct xe_hwmon *hwmon, u32 *uval)
>>   {
>> @@ -827,6 +884,8 @@ static void xe_hwmon_get_voltage(struct xe_hwmon *hwmon, int channel, long *valu
>>   static umode_t
>>   xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
>>   {
>> +	long val = 0;
>> +
>>   	switch (attr) {
>>   	case hwmon_temp_emergency:
>>   		switch (channel) {
>> @@ -834,6 +893,8 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
>>   			return hwmon->temp.limit[TEMP_LIMIT_PKG_SHUTDOWN] ? 0444 : 0;
>>   		case CHANNEL_VRAM:
>>   			return hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN] ? 0444 : 0;
>> +		case CHANNEL_MCTRL:
>> +			return (!get_mc_temp(hwmon, &val)) ? 0444 : 0;
> Do we really need to read it all here?
we can make visible based on hwmon->temp.count > 0
>
>>   		default:
>>   			return 0;
>>   		}
>> @@ -844,6 +905,8 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
>>   			return hwmon->temp.limit[TEMP_LIMIT_PKG_TJMAX] ? 0444 : 0;
>>   		case CHANNEL_VRAM:
>>   			return hwmon->temp.limit[TEMP_LIMIT_MEM_TJMAX] ? 0444 : 0;
>> +		case CHANNEL_MCTRL:
>> +			return (!get_mc_temp(hwmon, &val)) ? 0444 : 0;
> Ditto.
>
>>   		default:
>>   			return 0;
>>   		}
>> @@ -858,7 +921,16 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
>>   		break;
>>   	case hwmon_temp_input:
>>   	case hwmon_temp_label:
>> -		return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_TEMP, channel)) ? 0444 : 0;
>> +		switch (channel) {
>> +		case CHANNEL_PKG:
>> +		case CHANNEL_VRAM:
>> +			return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_TEMP,
>> +					       channel)) ? 0444 : 0;
>> +		case CHANNEL_MCTRL:
>> +			return (!get_mc_temp(hwmon, &val)) ? 0444 : 0;
> Ditto.
>
>> +		default:
>> +			return 0;
>> +		}
>>   	default:
>>   		return 0;
>>   	}
>> @@ -872,10 +944,20 @@ xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
>>   
>>   	switch (attr) {
>>   	case hwmon_temp_input:
>> -		reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_TEMP, channel));
>> +		switch (channel) {
>> +		case CHANNEL_PKG:
>> +		case CHANNEL_VRAM:
>> +			reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_TEMP, channel));
>>   
>> -		/* HW register value is in degrees Celsius, convert to millidegrees. */
>> -		*val = REG_FIELD_GET(TEMP_MASK, reg_val) * MILLIDEGREE_PER_DEGREE;
>> +			/* HW register value is in degrees Celsius, convert to millidegrees. */
>> +			*val = REG_FIELD_GET(TEMP_MASK, reg_val) * MILLIDEGREE_PER_DEGREE;
>> +			break;
>> +		case CHANNEL_MCTRL:
>> +			return get_mc_temp(hwmon, val);
>> +		default:
>> +			*val = 0;
> Do you need this?
incase *val is garbage this shall make this 0
>
>> +			return -EOPNOTSUPP;
>> +		}
>>   		break;
>>   	case hwmon_temp_emergency:
>>   		switch (channel) {
>> @@ -883,6 +965,7 @@ xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
>>   			*val = hwmon->temp.limit[TEMP_LIMIT_PKG_SHUTDOWN] * MILLIDEGREE_PER_DEGREE;
>>   			break;
>>   		case CHANNEL_VRAM:
>> +		case CHANNEL_MCTRL:
>>   			*val = hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN] * MILLIDEGREE_PER_DEGREE;
>>   			break;
>>   		default:
>> @@ -896,6 +979,7 @@ xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
>>   			*val = hwmon->temp.limit[TEMP_LIMIT_PKG_TJMAX] * MILLIDEGREE_PER_DEGREE;
>>   			break;
>>   		case CHANNEL_VRAM:
>> +		case CHANNEL_MCTRL:
>>   			*val = hwmon->temp.limit[TEMP_LIMIT_MEM_TJMAX] * MILLIDEGREE_PER_DEGREE;
>>   			break;
>>   		default:
>> @@ -1274,6 +1358,8 @@ static int xe_hwmon_read_label(struct device *dev,
>>   			*str = "pkg";
>>   		else if (channel == CHANNEL_VRAM)
>>   			*str = "vram";
>> +		else if (channel == CHANNEL_MCTRL)
>> +			*str = "mctrl_avg";
> The rest of the channels also signify the average so no need to spell
> it out.
>
> Raag
ok
>
>>   		return 0;
>>   	case hwmon_power:
>>   	case hwmon_energy:
>> diff --git a/drivers/gpu/drm/xe/xe_pcode_api.h b/drivers/gpu/drm/xe/xe_pcode_api.h
>> index a3bff76a074d..91e232834482 100644
>> --- a/drivers/gpu/drm/xe/xe_pcode_api.h
>> +++ b/drivers/gpu/drm/xe/xe_pcode_api.h
>> @@ -67,6 +67,10 @@
>>   
>>   #define	PCODE_THERMAL_INFO			0x25
>>   #define	READ_THERMAL_LIMITS			0x0
>> +#define	READ_THERMAL_CONFIG			0x1
>> +#define	READ_THERMAL_DATA			0x2
>> +#define TEMP_MASK_MAILBOX			REG_GENMASK8(6, 0)
>> +#define TEMP_INDEX_MCTRL			0x2
>>   
>>   #define   PCODE_FREQUENCY_CONFIG		0x6e
>>   /* Frequency Config Sub Commands (param1) */
>> -- 
>> 2.25.1
>>

[PATCH v3 3/4] drm/xe/hwmon: Expose GPU pcie temperature

[Karthik Poosa]

Expose GPU PCIe average temperature and its limits via hwmon
sysfs temp5_xxx.
Update Xe hwmon sysfs documentation for this.

v2: Update kernel version in Xe hwmon documentation. (Raag)

Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
---
 .../ABI/testing/sysfs-driver-intel-xe-hwmon   | 24 +++++++++++++
 drivers/gpu/drm/xe/xe_hwmon.c                 | 36 +++++++++++++++++++
 2 files changed, 60 insertions(+)

diff --git a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
index 81f9b5d58850..51a35fcfb393 100644
--- a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
+++ b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
@@ -260,3 +260,27 @@ Contact:	intel-xe@lists.freedesktop.org
 Description:	RO. Memory controller critical temperature in millidegree Celsius.
 
 		Only supported for particular Intel Xe graphics platforms.
+
+What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp5_input
+Date:		December 2025
+KernelVersion:	6.19
+Contact:	intel-xe@lists.freedesktop.org
+Description:	RO. GPU PCIe temperature in millidegree Celsius.
+
+		Only supported for particular Intel Xe graphics platforms.
+
+What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp5_emergency
+Date:		December 2025
+KernelVersion:	6.19
+Contact:	intel-xe@lists.freedesktop.org
+Description:	RO. GPU PCIe shutdown temperature in millidegree Celsius.
+
+		Only supported for particular Intel Xe graphics platforms.
+
+What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp5_crit
+Date:		December 2025
+KernelVersion:	6.19
+Contact:	intel-xe@lists.freedesktop.org
+Description:	RO. GPU PCIe critical temperature in millidegree Celsius.
+
+		Only supported for particular Intel Xe graphics platforms.
diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index 6d31ad74cd0e..b8519c734b4e 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -44,6 +44,7 @@ enum xe_hwmon_channel {
 	CHANNEL_PKG,
 	CHANNEL_VRAM,
 	CHANNEL_MCTRL,
+	CHANNEL_PCIE,
 	CHANNEL_MAX,
 };
 
@@ -713,6 +714,7 @@ static const struct hwmon_channel_info * const hwmon_info[] = {
 			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT |
 			   HWMON_T_MAX,
 			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
+			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
 			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT),
 	HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_LABEL | HWMON_P_CRIT |
 			   HWMON_P_CAP,
@@ -787,6 +789,28 @@ static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
 	return 0;
 }
 
+static int get_pcie_temp(struct xe_hwmon *hwmon, long *val)
+{
+	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
+	int ret = 0;
+	u32 data = 0;
+
+	ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_DATA, 2),
+			    &data, NULL);
+	drm_dbg(&hwmon->xe->drm, "thermal data for pcie ret %d, val 0x%x\n", ret, data);
+	if (ret)
+		return ret;
+
+	if (hwmon->xe->info.subplatform != XE_SUBPLATFORM_BATTLEMAGE_G21)
+		data >>= 8;
+	*val = (data & TEMP_MASK_MAILBOX) * MILLIDEGREE_PER_DEGREE;
+
+	if (data & 0x80)
+		*val = *val * -1;
+
+	return 0;
+}
+
 /* I1 is exposed as power_crit or as curr_crit depending on bit 31 */
 static int xe_hwmon_pcode_read_i1(const struct xe_hwmon *hwmon, u32 *uval)
 {
@@ -895,6 +919,8 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 			return hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN] ? 0444 : 0;
 		case CHANNEL_MCTRL:
 			return (!get_mc_temp(hwmon, &val)) ? 0444 : 0;
+		case CHANNEL_PCIE:
+			return (!get_pcie_temp(hwmon, &val)) ? 0444 : 0;
 		default:
 			return 0;
 		}
@@ -907,6 +933,8 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 			return hwmon->temp.limit[TEMP_LIMIT_MEM_TJMAX] ? 0444 : 0;
 		case CHANNEL_MCTRL:
 			return (!get_mc_temp(hwmon, &val)) ? 0444 : 0;
+		case CHANNEL_PCIE:
+			return (!get_pcie_temp(hwmon, &val)) ? 0444 : 0;
 		default:
 			return 0;
 		}
@@ -928,6 +956,8 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 					       channel)) ? 0444 : 0;
 		case CHANNEL_MCTRL:
 			return (!get_mc_temp(hwmon, &val)) ? 0444 : 0;
+		case CHANNEL_PCIE:
+			return (!get_pcie_temp(hwmon, &val)) ? 0444 : 0;
 		default:
 			return 0;
 		}
@@ -954,6 +984,8 @@ xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
 			break;
 		case CHANNEL_MCTRL:
 			return get_mc_temp(hwmon, val);
+		case CHANNEL_PCIE:
+			return get_pcie_temp(hwmon, val);
 		default:
 			*val = 0;
 			return -EOPNOTSUPP;
@@ -962,6 +994,7 @@ xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
 	case hwmon_temp_emergency:
 		switch (channel) {
 		case CHANNEL_PKG:
+		case CHANNEL_PCIE:
 			*val = hwmon->temp.limit[TEMP_LIMIT_PKG_SHUTDOWN] * MILLIDEGREE_PER_DEGREE;
 			break;
 		case CHANNEL_VRAM:
@@ -976,6 +1009,7 @@ xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
 	case hwmon_temp_crit:
 		switch (channel) {
 		case CHANNEL_PKG:
+		case CHANNEL_PCIE:
 			*val = hwmon->temp.limit[TEMP_LIMIT_PKG_TJMAX] * MILLIDEGREE_PER_DEGREE;
 			break;
 		case CHANNEL_VRAM:
@@ -1360,6 +1394,8 @@ static int xe_hwmon_read_label(struct device *dev,
 			*str = "vram";
 		else if (channel == CHANNEL_MCTRL)
 			*str = "mctrl_avg";
+		else if (channel == CHANNEL_PCIE)
+			*str = "pcie";
 		return 0;
 	case hwmon_power:
 	case hwmon_energy:
-- 
2.25.1

Re: [PATCH v3 3/4] drm/xe/hwmon: Expose GPU pcie temperature

[Raag Jadav]

On Tue, Dec 16, 2025 at 05:10:29PM +0530, Karthik Poosa wrote:
> Expose GPU PCIe average temperature and its limits via hwmon

Use consistent upper/lower cases in subject.

> sysfs temp5_xxx.
> Update Xe hwmon sysfs documentation for this.
> 
> v2: Update kernel version in Xe hwmon documentation. (Raag)
> 
> Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
> ---
>  .../ABI/testing/sysfs-driver-intel-xe-hwmon   | 24 +++++++++++++
>  drivers/gpu/drm/xe/xe_hwmon.c                 | 36 +++++++++++++++++++
>  2 files changed, 60 insertions(+)
> 
> diff --git a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> index 81f9b5d58850..51a35fcfb393 100644
> --- a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> +++ b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> @@ -260,3 +260,27 @@ Contact:	intel-xe@lists.freedesktop.org
>  Description:	RO. Memory controller critical temperature in millidegree Celsius.
>  
>  		Only supported for particular Intel Xe graphics platforms.
> +
> +What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp5_input
> +Date:		December 2025
> +KernelVersion:	6.19
> +Contact:	intel-xe@lists.freedesktop.org
> +Description:	RO. GPU PCIe temperature in millidegree Celsius.
> +
> +		Only supported for particular Intel Xe graphics platforms.
> +
> +What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp5_emergency
> +Date:		December 2025
> +KernelVersion:	6.19
> +Contact:	intel-xe@lists.freedesktop.org
> +Description:	RO. GPU PCIe shutdown temperature in millidegree Celsius.
> +
> +		Only supported for particular Intel Xe graphics platforms.
> +
> +What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp5_crit
> +Date:		December 2025
> +KernelVersion:	6.19
> +Contact:	intel-xe@lists.freedesktop.org
> +Description:	RO. GPU PCIe critical temperature in millidegree Celsius.
> +
> +		Only supported for particular Intel Xe graphics platforms.

Same as patch 1. These attributes defer from ABI definition so not my call.

> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index 6d31ad74cd0e..b8519c734b4e 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> @@ -44,6 +44,7 @@ enum xe_hwmon_channel {
>  	CHANNEL_PKG,
>  	CHANNEL_VRAM,
>  	CHANNEL_MCTRL,
> +	CHANNEL_PCIE,
>  	CHANNEL_MAX,
>  };
>  
> @@ -713,6 +714,7 @@ static const struct hwmon_channel_info * const hwmon_info[] = {
>  			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT |
>  			   HWMON_T_MAX,
>  			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
> +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
>  			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT),
>  	HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_LABEL | HWMON_P_CRIT |
>  			   HWMON_P_CAP,
> @@ -787,6 +789,28 @@ static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
>  	return 0;
>  }
>  
> +static int get_pcie_temp(struct xe_hwmon *hwmon, long *val)
> +{
> +	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
> +	int ret = 0;
> +	u32 data = 0;
> +
> +	ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_DATA, 2),
> +			    &data, NULL);
> +	drm_dbg(&hwmon->xe->drm, "thermal data for pcie ret %d, val 0x%x\n", ret, data);

Same comments as last patch (and also in all other places where applicable).

> +	if (ret)
> +		return ret;
> +
> +	if (hwmon->xe->info.subplatform != XE_SUBPLATFORM_BATTLEMAGE_G21)
> +		data >>= 8;

I'm a bit lost here. How is data format different per subplatform?
Shouldn't this be a pcode bug?

> +	*val = (data & TEMP_MASK_MAILBOX) * MILLIDEGREE_PER_DEGREE;
> +
> +	if (data & 0x80)
> +		*val = *val * -1;
> +
> +	return 0;
> +}
> +
>  /* I1 is exposed as power_crit or as curr_crit depending on bit 31 */
>  static int xe_hwmon_pcode_read_i1(const struct xe_hwmon *hwmon, u32 *uval)
>  {
> @@ -895,6 +919,8 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
>  			return hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN] ? 0444 : 0;
>  		case CHANNEL_MCTRL:
>  			return (!get_mc_temp(hwmon, &val)) ? 0444 : 0;
> +		case CHANNEL_PCIE:
> +			return (!get_pcie_temp(hwmon, &val)) ? 0444 : 0;

Same comments as last patch.

>  		default:
>  			return 0;
>  		}
> @@ -907,6 +933,8 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
>  			return hwmon->temp.limit[TEMP_LIMIT_MEM_TJMAX] ? 0444 : 0;
>  		case CHANNEL_MCTRL:
>  			return (!get_mc_temp(hwmon, &val)) ? 0444 : 0;
> +		case CHANNEL_PCIE:
> +			return (!get_pcie_temp(hwmon, &val)) ? 0444 : 0;

Ditto.

>  		default:
>  			return 0;
>  		}
> @@ -928,6 +956,8 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
>  					       channel)) ? 0444 : 0;
>  		case CHANNEL_MCTRL:
>  			return (!get_mc_temp(hwmon, &val)) ? 0444 : 0;
> +		case CHANNEL_PCIE:
> +			return (!get_pcie_temp(hwmon, &val)) ? 0444 : 0;

Ditto.

Raag

>  		default:
>  			return 0;
>  		}
> @@ -954,6 +984,8 @@ xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
>  			break;
>  		case CHANNEL_MCTRL:
>  			return get_mc_temp(hwmon, val);
> +		case CHANNEL_PCIE:
> +			return get_pcie_temp(hwmon, val);
>  		default:
>  			*val = 0;
>  			return -EOPNOTSUPP;
> @@ -962,6 +994,7 @@ xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
>  	case hwmon_temp_emergency:
>  		switch (channel) {
>  		case CHANNEL_PKG:
> +		case CHANNEL_PCIE:
>  			*val = hwmon->temp.limit[TEMP_LIMIT_PKG_SHUTDOWN] * MILLIDEGREE_PER_DEGREE;
>  			break;
>  		case CHANNEL_VRAM:
> @@ -976,6 +1009,7 @@ xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
>  	case hwmon_temp_crit:
>  		switch (channel) {
>  		case CHANNEL_PKG:
> +		case CHANNEL_PCIE:
>  			*val = hwmon->temp.limit[TEMP_LIMIT_PKG_TJMAX] * MILLIDEGREE_PER_DEGREE;
>  			break;
>  		case CHANNEL_VRAM:
> @@ -1360,6 +1394,8 @@ static int xe_hwmon_read_label(struct device *dev,
>  			*str = "vram";
>  		else if (channel == CHANNEL_MCTRL)
>  			*str = "mctrl_avg";
> +		else if (channel == CHANNEL_PCIE)
> +			*str = "pcie";
>  		return 0;
>  	case hwmon_power:
>  	case hwmon_energy:
> -- 
> 2.25.1
> 

Re: [PATCH v3 3/4] drm/xe/hwmon: Expose GPU pcie temperature

[Poosa, Karthik]

On 19-12-2025 13:53, Raag Jadav wrote:
> On Tue, Dec 16, 2025 at 05:10:29PM +0530, Karthik Poosa wrote:
>> Expose GPU PCIe average temperature and its limits via hwmon
> Use consistent upper/lower cases in subject.
ok
>
>> sysfs temp5_xxx.
>> Update Xe hwmon sysfs documentation for this.
>>
>> v2: Update kernel version in Xe hwmon documentation. (Raag)
>>
>> Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
>> ---
>>   .../ABI/testing/sysfs-driver-intel-xe-hwmon   | 24 +++++++++++++
>>   drivers/gpu/drm/xe/xe_hwmon.c                 | 36 +++++++++++++++++++
>>   2 files changed, 60 insertions(+)
>>
>> diff --git a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
>> index 81f9b5d58850..51a35fcfb393 100644
>> --- a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
>> +++ b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
>> @@ -260,3 +260,27 @@ Contact:	intel-xe@lists.freedesktop.org
>>   Description:	RO. Memory controller critical temperature in millidegree Celsius.
>>   
>>   		Only supported for particular Intel Xe graphics platforms.
>> +
>> +What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp5_input
>> +Date:		December 2025
>> +KernelVersion:	6.19
>> +Contact:	intel-xe@lists.freedesktop.org
>> +Description:	RO. GPU PCIe temperature in millidegree Celsius.
>> +
>> +		Only supported for particular Intel Xe graphics platforms.
>> +
>> +What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp5_emergency
>> +Date:		December 2025
>> +KernelVersion:	6.19
>> +Contact:	intel-xe@lists.freedesktop.org
>> +Description:	RO. GPU PCIe shutdown temperature in millidegree Celsius.
>> +
>> +		Only supported for particular Intel Xe graphics platforms.
>> +
>> +What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp5_crit
>> +Date:		December 2025
>> +KernelVersion:	6.19
>> +Contact:	intel-xe@lists.freedesktop.org
>> +Description:	RO. GPU PCIe critical temperature in millidegree Celsius.
>> +
>> +		Only supported for particular Intel Xe graphics platforms.
> Same as patch 1. These attributes defer from ABI definition so not my call.
>
>> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
>> index 6d31ad74cd0e..b8519c734b4e 100644
>> --- a/drivers/gpu/drm/xe/xe_hwmon.c
>> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
>> @@ -44,6 +44,7 @@ enum xe_hwmon_channel {
>>   	CHANNEL_PKG,
>>   	CHANNEL_VRAM,
>>   	CHANNEL_MCTRL,
>> +	CHANNEL_PCIE,
>>   	CHANNEL_MAX,
>>   };
>>   
>> @@ -713,6 +714,7 @@ static const struct hwmon_channel_info * const hwmon_info[] = {
>>   			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT |
>>   			   HWMON_T_MAX,
>>   			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
>> +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
>>   			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT),
>>   	HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_LABEL | HWMON_P_CRIT |
>>   			   HWMON_P_CAP,
>> @@ -787,6 +789,28 @@ static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
>>   	return 0;
>>   }
>>   
>> +static int get_pcie_temp(struct xe_hwmon *hwmon, long *val)
>> +{
>> +	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
>> +	int ret = 0;
>> +	u32 data = 0;
>> +
>> +	ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_DATA, 2),
>> +			    &data, NULL);
>> +	drm_dbg(&hwmon->xe->drm, "thermal data for pcie ret %d, val 0x%x\n", ret, data);
> Same comments as last patch (and also in all other places where applicable).
we can remove this.
>
>> +	if (ret)
>> +		return ret;
>> +
>> +	if (hwmon->xe->info.subplatform != XE_SUBPLATFORM_BATTLEMAGE_G21)
>> +		data >>= 8;
> I'm a bit lost here. How is data format different per subplatform?
> Shouldn't this be a pcode bug?

Format is same, only offset of sensor is different for G21 is different 
as it has less sensors.

>
>> +	*val = (data & TEMP_MASK_MAILBOX) * MILLIDEGREE_PER_DEGREE;
>> +
>> +	if (data & 0x80)
>> +		*val = *val * -1;
>> +
>> +	return 0;
>> +}
>> +
>>   /* I1 is exposed as power_crit or as curr_crit depending on bit 31 */
>>   static int xe_hwmon_pcode_read_i1(const struct xe_hwmon *hwmon, u32 *uval)
>>   {
>> @@ -895,6 +919,8 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
>>   			return hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN] ? 0444 : 0;
>>   		case CHANNEL_MCTRL:
>>   			return (!get_mc_temp(hwmon, &val)) ? 0444 : 0;
>> +		case CHANNEL_PCIE:
>> +			return (!get_pcie_temp(hwmon, &val)) ? 0444 : 0;
> Same comments as last patch.
>
>>   		default:
>>   			return 0;
>>   		}
>> @@ -907,6 +933,8 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
>>   			return hwmon->temp.limit[TEMP_LIMIT_MEM_TJMAX] ? 0444 : 0;
>>   		case CHANNEL_MCTRL:
>>   			return (!get_mc_temp(hwmon, &val)) ? 0444 : 0;
>> +		case CHANNEL_PCIE:
>> +			return (!get_pcie_temp(hwmon, &val)) ? 0444 : 0;
> Ditto.
>
>>   		default:
>>   			return 0;
>>   		}
>> @@ -928,6 +956,8 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
>>   					       channel)) ? 0444 : 0;
>>   		case CHANNEL_MCTRL:
>>   			return (!get_mc_temp(hwmon, &val)) ? 0444 : 0;
>> +		case CHANNEL_PCIE:
>> +			return (!get_pcie_temp(hwmon, &val)) ? 0444 : 0;
> Ditto.
>
> Raag
>
>>   		default:
>>   			return 0;
>>   		}
>> @@ -954,6 +984,8 @@ xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
>>   			break;
>>   		case CHANNEL_MCTRL:
>>   			return get_mc_temp(hwmon, val);
>> +		case CHANNEL_PCIE:
>> +			return get_pcie_temp(hwmon, val);
>>   		default:
>>   			*val = 0;
>>   			return -EOPNOTSUPP;
>> @@ -962,6 +994,7 @@ xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
>>   	case hwmon_temp_emergency:
>>   		switch (channel) {
>>   		case CHANNEL_PKG:
>> +		case CHANNEL_PCIE:
>>   			*val = hwmon->temp.limit[TEMP_LIMIT_PKG_SHUTDOWN] * MILLIDEGREE_PER_DEGREE;
>>   			break;
>>   		case CHANNEL_VRAM:
>> @@ -976,6 +1009,7 @@ xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
>>   	case hwmon_temp_crit:
>>   		switch (channel) {
>>   		case CHANNEL_PKG:
>> +		case CHANNEL_PCIE:
>>   			*val = hwmon->temp.limit[TEMP_LIMIT_PKG_TJMAX] * MILLIDEGREE_PER_DEGREE;
>>   			break;
>>   		case CHANNEL_VRAM:
>> @@ -1360,6 +1394,8 @@ static int xe_hwmon_read_label(struct device *dev,
>>   			*str = "vram";
>>   		else if (channel == CHANNEL_MCTRL)
>>   			*str = "mctrl_avg";
>> +		else if (channel == CHANNEL_PCIE)
>> +			*str = "pcie";
>>   		return 0;
>>   	case hwmon_power:
>>   	case hwmon_energy:
>> -- 
>> 2.25.1
>>

[PATCH v3 4/4] drm/xe/hwmon: Expose individual vram temperature

[Karthik Poosa]

Expose individual VRAM temperature attributes.
Update Xe hwmon documentation for this entry.

v2:
 - Avoid using default switch case for VRAM individual temperatures.
 - Append labels with vram number.
 - Update kernel version in Xe hwmon documentation.

Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
---
 .../ABI/testing/sysfs-driver-intel-xe-hwmon   | 24 ++++++++++
 drivers/gpu/drm/xe/regs/xe_pcode_regs.h       |  2 +
 drivers/gpu/drm/xe/xe_hwmon.c                 | 47 ++++++++++++++++++-
 3 files changed, 72 insertions(+), 1 deletion(-)

diff --git a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
index 51a35fcfb393..b58a96b1857d 100644
--- a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
+++ b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
@@ -284,3 +284,27 @@ Contact:	intel-xe@lists.freedesktop.org
 Description:	RO. GPU PCIe critical temperature in millidegree Celsius.
 
 		Only supported for particular Intel Xe graphics platforms.
+
+What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp6-21_input
+Date:		December 2025
+KernelVersion:	6.19
+Contact:	intel-xe@lists.freedesktop.org
+Description:	RO. Individual VRAM temperature in millidegree Celsius.
+
+		Only supported for particular Intel Xe graphics platforms.
+
+What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp6-21_emergency
+Date:		December 2025
+KernelVersion:	6.19
+Contact:	intel-xe@lists.freedesktop.org
+Description:	RO. Individual VRAM shutdown temperature in millidegree Celsius.
+
+		Only supported for particular Intel Xe graphics platforms.
+
+What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp6-21_crit
+Date:		December 2025
+KernelVersion:	6.19
+Contact:	intel-xe@lists.freedesktop.org
+Description:	RO. Individual VRAM critical temperature in millidegree Celsius.
+
+		Only supported for particular Intel Xe graphics platforms.
diff --git a/drivers/gpu/drm/xe/regs/xe_pcode_regs.h b/drivers/gpu/drm/xe/regs/xe_pcode_regs.h
index fb097607b86c..7c35e2605d2f 100644
--- a/drivers/gpu/drm/xe/regs/xe_pcode_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_pcode_regs.h
@@ -23,5 +23,7 @@
 #define BMG_FAN_3_SPEED				XE_REG(0x1381a0)
 #define BMG_VRAM_TEMPERATURE			XE_REG(0x1382c0)
 #define BMG_PACKAGE_TEMPERATURE			XE_REG(0x138434)
+#define BMG_VRAM_TEMPERATURE_N(n)		XE_REG(0x138260 + (n))
+#define TEMP_MASK_VRAM_N			REG_GENMASK(31, 8)
 
 #endif /* _XE_PCODE_REGS_H_ */
diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index b8519c734b4e..8eb1dd8f4b2f 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -39,12 +39,16 @@ enum xe_hwmon_reg_operation {
 	REG_READ64,
 };
 
+#define MAX_VRAM_CHANNELS      (16)
+
 enum xe_hwmon_channel {
 	CHANNEL_CARD,
 	CHANNEL_PKG,
 	CHANNEL_VRAM,
 	CHANNEL_MCTRL,
 	CHANNEL_PCIE,
+	CHANNEL_VRAM_N,
+	CHANNEL_VRAM_N_MAX = CHANNEL_VRAM_N + MAX_VRAM_CHANNELS,
 	CHANNEL_MAX,
 };
 
@@ -256,6 +260,8 @@ static struct xe_reg xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg
 				return BMG_PACKAGE_TEMPERATURE;
 			else if (channel == CHANNEL_VRAM)
 				return BMG_VRAM_TEMPERATURE;
+			else if (channel >= CHANNEL_VRAM_N && channel <= CHANNEL_VRAM_N_MAX)
+				return BMG_VRAM_TEMPERATURE_N(((channel % CHANNEL_VRAM_N) * 4));
 		} else if (xe->info.platform == XE_DG2) {
 			if (channel == CHANNEL_PKG)
 				return PCU_CR_PACKAGE_TEMPERATURE;
@@ -715,6 +721,22 @@ static const struct hwmon_channel_info * const hwmon_info[] = {
 			   HWMON_T_MAX,
 			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
 			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
+			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
+			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
+			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
+			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
+			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
+			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
+			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
+			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
+			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
+			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
+			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
+			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
+			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
+			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
+			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
+			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
 			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT),
 	HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_LABEL | HWMON_P_CRIT |
 			   HWMON_P_CAP,
@@ -921,6 +943,9 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 			return (!get_mc_temp(hwmon, &val)) ? 0444 : 0;
 		case CHANNEL_PCIE:
 			return (!get_pcie_temp(hwmon, &val)) ? 0444 : 0;
+		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
+			return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_TEMP,
+					       channel)) ? 0444 : 0;
 		default:
 			return 0;
 		}
@@ -935,6 +960,9 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 			return (!get_mc_temp(hwmon, &val)) ? 0444 : 0;
 		case CHANNEL_PCIE:
 			return (!get_pcie_temp(hwmon, &val)) ? 0444 : 0;
+		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
+			return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_TEMP,
+					       channel)) ? 0444 : 0;
 		default:
 			return 0;
 		}
@@ -958,6 +986,9 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 			return (!get_mc_temp(hwmon, &val)) ? 0444 : 0;
 		case CHANNEL_PCIE:
 			return (!get_pcie_temp(hwmon, &val)) ? 0444 : 0;
+		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
+			return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_TEMP,
+					       channel)) ? 0444 : 0;
 		default:
 			return 0;
 		}
@@ -986,6 +1017,12 @@ xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
 			return get_mc_temp(hwmon, val);
 		case CHANNEL_PCIE:
 			return get_pcie_temp(hwmon, val);
+		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
+			reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_TEMP, channel));
+			/* Temperature format here is S 31.23.8 */
+			*val = REG_FIELD_GET(TEMP_MASK_VRAM_N, reg_val) *
+					     ((reg_val >> 31) ? -1 : 1) * MILLIDEGREE_PER_DEGREE;
+			break;
 		default:
 			*val = 0;
 			return -EOPNOTSUPP;
@@ -999,6 +1036,7 @@ xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
 			break;
 		case CHANNEL_VRAM:
 		case CHANNEL_MCTRL:
+		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
 			*val = hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN] * MILLIDEGREE_PER_DEGREE;
 			break;
 		default:
@@ -1014,6 +1052,7 @@ xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
 			break;
 		case CHANNEL_VRAM:
 		case CHANNEL_MCTRL:
+		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
 			*val = hwmon->temp.limit[TEMP_LIMIT_MEM_TJMAX] * MILLIDEGREE_PER_DEGREE;
 			break;
 		default:
@@ -1386,16 +1425,22 @@ static int xe_hwmon_read_label(struct device *dev,
 			       enum hwmon_sensor_types type,
 			       u32 attr, int channel, const char **str)
 {
+	char temp[16] = {0};
+
 	switch (type) {
 	case hwmon_temp:
 		if (channel == CHANNEL_PKG)
 			*str = "pkg";
 		else if (channel == CHANNEL_VRAM)
-			*str = "vram";
+			*str = "vram_avg";
 		else if (channel == CHANNEL_MCTRL)
 			*str = "mctrl_avg";
 		else if (channel == CHANNEL_PCIE)
 			*str = "pcie";
+		else if (channel >= CHANNEL_VRAM_N && channel <= CHANNEL_VRAM_N_MAX) {
+			sprintf(temp, "vram_%d", (channel - CHANNEL_VRAM_N));
+			*str = temp;
+		}
 		return 0;
 	case hwmon_power:
 	case hwmon_energy:
-- 
2.25.1

Re: [PATCH v3 4/4] drm/xe/hwmon: Expose individual vram temperature

[Raag Jadav]

On Tue, Dec 16, 2025 at 05:10:30PM +0530, Karthik Poosa wrote:
> Expose individual VRAM temperature attributes.
> Update Xe hwmon documentation for this entry.
> 
> v2:
>  - Avoid using default switch case for VRAM individual temperatures.
>  - Append labels with vram number.
>  - Update kernel version in Xe hwmon documentation.
> 
> Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
> ---
>  .../ABI/testing/sysfs-driver-intel-xe-hwmon   | 24 ++++++++++
>  drivers/gpu/drm/xe/regs/xe_pcode_regs.h       |  2 +
>  drivers/gpu/drm/xe/xe_hwmon.c                 | 47 ++++++++++++++++++-
>  3 files changed, 72 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> index 51a35fcfb393..b58a96b1857d 100644
> --- a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> +++ b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> @@ -284,3 +284,27 @@ Contact:	intel-xe@lists.freedesktop.org
>  Description:	RO. GPU PCIe critical temperature in millidegree Celsius.
>  
>  		Only supported for particular Intel Xe graphics platforms.
> +
> +What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp6-21_input

Brace around channel range with '[]'.

> +Date:		December 2025
> +KernelVersion:	6.19
> +Contact:	intel-xe@lists.freedesktop.org
> +Description:	RO. Individual VRAM temperature in millidegree Celsius.
> +
> +		Only supported for particular Intel Xe graphics platforms.
> +
> +What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp6-21_emergency

Ditto.

> +Date:		December 2025
> +KernelVersion:	6.19
> +Contact:	intel-xe@lists.freedesktop.org
> +Description:	RO. Individual VRAM shutdown temperature in millidegree Celsius.
> +
> +		Only supported for particular Intel Xe graphics platforms.
> +
> +What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp6-21_crit

Ditto.

> +Date:		December 2025
> +KernelVersion:	6.19
> +Contact:	intel-xe@lists.freedesktop.org
> +Description:	RO. Individual VRAM critical temperature in millidegree Celsius.
> +
> +		Only supported for particular Intel Xe graphics platforms.
> diff --git a/drivers/gpu/drm/xe/regs/xe_pcode_regs.h b/drivers/gpu/drm/xe/regs/xe_pcode_regs.h
> index fb097607b86c..7c35e2605d2f 100644
> --- a/drivers/gpu/drm/xe/regs/xe_pcode_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_pcode_regs.h
> @@ -23,5 +23,7 @@
>  #define BMG_FAN_3_SPEED				XE_REG(0x1381a0)
>  #define BMG_VRAM_TEMPERATURE			XE_REG(0x1382c0)
>  #define BMG_PACKAGE_TEMPERATURE			XE_REG(0x138434)
> +#define BMG_VRAM_TEMPERATURE_N(n)		XE_REG(0x138260 + (n))

Is this the correct ordering?

> +#define TEMP_MASK_VRAM_N			REG_GENMASK(31, 8)

We usually have spacing for masks and bitfields. Please refer to
xe_mchbar_regs.h.

>  #endif /* _XE_PCODE_REGS_H_ */
> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index b8519c734b4e..8eb1dd8f4b2f 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> @@ -39,12 +39,16 @@ enum xe_hwmon_reg_operation {
>  	REG_READ64,
>  };
>  
> +#define MAX_VRAM_CHANNELS      (16)
> +
>  enum xe_hwmon_channel {
>  	CHANNEL_CARD,
>  	CHANNEL_PKG,
>  	CHANNEL_VRAM,
>  	CHANNEL_MCTRL,
>  	CHANNEL_PCIE,
> +	CHANNEL_VRAM_N,
> +	CHANNEL_VRAM_N_MAX = CHANNEL_VRAM_N + MAX_VRAM_CHANNELS,

Please consider the future prospects (or risks) of this approach. We're
writing ourselves into a corner here, because now any new component will
be id'ed after CHANNEL_VRAM_N_MAX and with that we can potentially hit
scaling problem with MAX_VRAM_CHANNELS.

I have already mentioned it once[1] but again, not my call.

[1] https://lore.kernel.org/intel-xe/Z5SPWwiB15ptK4hR@black.fi.intel.com/


>  	CHANNEL_MAX,
>  };
>  
> @@ -256,6 +260,8 @@ static struct xe_reg xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg
>  				return BMG_PACKAGE_TEMPERATURE;
>  			else if (channel == CHANNEL_VRAM)
>  				return BMG_VRAM_TEMPERATURE;
> +			else if (channel >= CHANNEL_VRAM_N && channel <= CHANNEL_VRAM_N_MAX)
> +				return BMG_VRAM_TEMPERATURE_N(((channel % CHANNEL_VRAM_N) * 4));
>  		} else if (xe->info.platform == XE_DG2) {
>  			if (channel == CHANNEL_PKG)
>  				return PCU_CR_PACKAGE_TEMPERATURE;
> @@ -715,6 +721,22 @@ static const struct hwmon_channel_info * const hwmon_info[] = {
>  			   HWMON_T_MAX,
>  			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
>  			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
> +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
> +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
> +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
> +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
> +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
> +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
> +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
> +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
> +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
> +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
> +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
> +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
> +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
> +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
> +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
> +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
>  			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT),
>  	HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_LABEL | HWMON_P_CRIT |
>  			   HWMON_P_CAP,
> @@ -921,6 +943,9 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
>  			return (!get_mc_temp(hwmon, &val)) ? 0444 : 0;
>  		case CHANNEL_PCIE:
>  			return (!get_pcie_temp(hwmon, &val)) ? 0444 : 0;
> +		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:

So this means we're exposing them all but do we really have 16 VRAMs?

> +			return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_TEMP,
> +					       channel)) ? 0444 : 0;
>  		default:
>  			return 0;
>  		}
> @@ -935,6 +960,9 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
>  			return (!get_mc_temp(hwmon, &val)) ? 0444 : 0;
>  		case CHANNEL_PCIE:
>  			return (!get_pcie_temp(hwmon, &val)) ? 0444 : 0;
> +		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:

Ditto.

> +			return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_TEMP,
> +					       channel)) ? 0444 : 0;
>  		default:
>  			return 0;
>  		}
> @@ -958,6 +986,9 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
>  			return (!get_mc_temp(hwmon, &val)) ? 0444 : 0;
>  		case CHANNEL_PCIE:
>  			return (!get_pcie_temp(hwmon, &val)) ? 0444 : 0;
> +		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:

Ditto.

> +			return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_TEMP,
> +					       channel)) ? 0444 : 0;
>  		default:
>  			return 0;
>  		}
> @@ -986,6 +1017,12 @@ xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
>  			return get_mc_temp(hwmon, val);
>  		case CHANNEL_PCIE:
>  			return get_pcie_temp(hwmon, val);
> +		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
> +			reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_TEMP, channel));
> +			/* Temperature format here is S 31.23.8 */

I'm not confident if this is translatable to human beings, could you
please elaborate?

> +			*val = REG_FIELD_GET(TEMP_MASK_VRAM_N, reg_val) *
> +					     ((reg_val >> 31) ? -1 : 1) * MILLIDEGREE_PER_DEGREE;
> +			break;
>  		default:
>  			*val = 0;
>  			return -EOPNOTSUPP;
> @@ -999,6 +1036,7 @@ xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
>  			break;
>  		case CHANNEL_VRAM:
>  		case CHANNEL_MCTRL:
> +		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
>  			*val = hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN] * MILLIDEGREE_PER_DEGREE;
>  			break;
>  		default:
> @@ -1014,6 +1052,7 @@ xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
>  			break;
>  		case CHANNEL_VRAM:
>  		case CHANNEL_MCTRL:
> +		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
>  			*val = hwmon->temp.limit[TEMP_LIMIT_MEM_TJMAX] * MILLIDEGREE_PER_DEGREE;
>  			break;
>  		default:
> @@ -1386,16 +1425,22 @@ static int xe_hwmon_read_label(struct device *dev,
>  			       enum hwmon_sensor_types type,
>  			       u32 attr, int channel, const char **str)
>  {
> +	char temp[16] = {0};
> +
>  	switch (type) {
>  	case hwmon_temp:
>  		if (channel == CHANNEL_PKG)
>  			*str = "pkg";
>  		else if (channel == CHANNEL_VRAM)
> -			*str = "vram";
> +			*str = "vram_avg";
>  		else if (channel == CHANNEL_MCTRL)
>  			*str = "mctrl_avg";
>  		else if (channel == CHANNEL_PCIE)
>  			*str = "pcie";
> +		else if (channel >= CHANNEL_VRAM_N && channel <= CHANNEL_VRAM_N_MAX) {
> +			sprintf(temp, "vram_%d", (channel - CHANNEL_VRAM_N));
> +			*str = temp;

Can this be done without temp?

Raag

> +		}
>  		return 0;
>  	case hwmon_power:
>  	case hwmon_energy:
> -- 
> 2.25.1
> 

Re: [PATCH v3 4/4] drm/xe/hwmon: Expose individual vram temperature

[Poosa, Karthik]

[-- Attachment #1: Type: text/plain, Size: 10211 bytes --]


On 22-12-2025 00:22, Raag Jadav wrote:
> On Tue, Dec 16, 2025 at 05:10:30PM +0530, Karthik Poosa wrote:
>> Expose individual VRAM temperature attributes.
>> Update Xe hwmon documentation for this entry.
>>
>> v2:
>>   - Avoid using default switch case for VRAM individual temperatures.
>>   - Append labels with vram number.
>>   - Update kernel version in Xe hwmon documentation.
>>
>> Signed-off-by: Karthik Poosa<karthik.poosa@intel.com>
>> ---
>>   .../ABI/testing/sysfs-driver-intel-xe-hwmon   | 24 ++++++++++
>>   drivers/gpu/drm/xe/regs/xe_pcode_regs.h       |  2 +
>>   drivers/gpu/drm/xe/xe_hwmon.c                 | 47 ++++++++++++++++++-
>>   3 files changed, 72 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
>> index 51a35fcfb393..b58a96b1857d 100644
>> --- a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
>> +++ b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
>> @@ -284,3 +284,27 @@ Contact:	intel-xe@lists.freedesktop.org
>>   Description:	RO. GPU PCIe critical temperature in millidegree Celsius.
>>   
>>   		Only supported for particular Intel Xe graphics platforms.
>> +
>> +What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp6-21_input
> Brace around channel range with '[]'.
ok
>
>> +Date:		December 2025
>> +KernelVersion:	6.19
>> +Contact:	intel-xe@lists.freedesktop.org
>> +Description:	RO. Individual VRAM temperature in millidegree Celsius.
>> +
>> +		Only supported for particular Intel Xe graphics platforms.
>> +
>> +What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp6-21_emergency
> Ditto.
>
>> +Date:		December 2025
>> +KernelVersion:	6.19
>> +Contact:	intel-xe@lists.freedesktop.org
>> +Description:	RO. Individual VRAM shutdown temperature in millidegree Celsius.
>> +
>> +		Only supported for particular Intel Xe graphics platforms.
>> +
>> +What:		/sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp6-21_crit
> Ditto.
>
>> +Date:		December 2025
>> +KernelVersion:	6.19
>> +Contact:	intel-xe@lists.freedesktop.org
>> +Description:	RO. Individual VRAM critical temperature in millidegree Celsius.
>> +
>> +		Only supported for particular Intel Xe graphics platforms.
>> diff --git a/drivers/gpu/drm/xe/regs/xe_pcode_regs.h b/drivers/gpu/drm/xe/regs/xe_pcode_regs.h
>> index fb097607b86c..7c35e2605d2f 100644
>> --- a/drivers/gpu/drm/xe/regs/xe_pcode_regs.h
>> +++ b/drivers/gpu/drm/xe/regs/xe_pcode_regs.h
>> @@ -23,5 +23,7 @@
>>   #define BMG_FAN_3_SPEED				XE_REG(0x1381a0)
>>   #define BMG_VRAM_TEMPERATURE			XE_REG(0x1382c0)
>>   #define BMG_PACKAGE_TEMPERATURE			XE_REG(0x138434)
>> +#define BMG_VRAM_TEMPERATURE_N(n)		XE_REG(0x138260 + (n))
> Is this the correct ordering?
We can move this after BMG_VRAM_TEMPERATURE
>
>> +#define TEMP_MASK_VRAM_N			REG_GENMASK(31, 8)
> We usually have spacing for masks and bitfields. Please refer to
> xe_mchbar_regs.h.
>
>>   #endif /* _XE_PCODE_REGS_H_ */
>> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
>> index b8519c734b4e..8eb1dd8f4b2f 100644
>> --- a/drivers/gpu/drm/xe/xe_hwmon.c
>> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
>> @@ -39,12 +39,16 @@ enum xe_hwmon_reg_operation {
>>   	REG_READ64,
>>   };
>>   
>> +#define MAX_VRAM_CHANNELS      (16)
>> +
>>   enum xe_hwmon_channel {
>>   	CHANNEL_CARD,
>>   	CHANNEL_PKG,
>>   	CHANNEL_VRAM,
>>   	CHANNEL_MCTRL,
>>   	CHANNEL_PCIE,
>> +	CHANNEL_VRAM_N,
>> +	CHANNEL_VRAM_N_MAX = CHANNEL_VRAM_N + MAX_VRAM_CHANNELS,
> Please consider the future prospects (or risks) of this approach. We're
> writing ourselves into a corner here, because now any new component will
> be id'ed after CHANNEL_VRAM_N_MAX and with that we can potentially hit
> scaling problem with MAX_VRAM_CHANNELS.
>
> I have already mentioned it once[1] but again, not my call.
>
> [1]https://lore.kernel.org/intel-xe/Z5SPWwiB15ptK4hR@black.fi.intel.com/

what is your suggestion here ? to have separate channel enum for each 
sensor type ?

>
>>   	CHANNEL_MAX,
>>   };
>>   
>> @@ -256,6 +260,8 @@ static struct xe_reg xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg
>>   				return BMG_PACKAGE_TEMPERATURE;
>>   			else if (channel == CHANNEL_VRAM)
>>   				return BMG_VRAM_TEMPERATURE;
>> +			else if (channel >= CHANNEL_VRAM_N && channel <= CHANNEL_VRAM_N_MAX)
>> +				return BMG_VRAM_TEMPERATURE_N(((channel % CHANNEL_VRAM_N) * 4));
>>   		} else if (xe->info.platform == XE_DG2) {
>>   			if (channel == CHANNEL_PKG)
>>   				return PCU_CR_PACKAGE_TEMPERATURE;
>> @@ -715,6 +721,22 @@ static const struct hwmon_channel_info * const hwmon_info[] = {
>>   			   HWMON_T_MAX,
>>   			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
>>   			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
>> +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
>> +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
>> +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
>> +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
>> +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
>> +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
>> +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
>> +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
>> +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
>> +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
>> +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
>> +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
>> +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
>> +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
>> +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
>> +			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT,
>>   			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_EMERGENCY | HWMON_T_CRIT),
>>   	HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_LABEL | HWMON_P_CRIT |
>>   			   HWMON_P_CAP,
>> @@ -921,6 +943,9 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
>>   			return (!get_mc_temp(hwmon, &val)) ? 0444 : 0;
>>   		case CHANNEL_PCIE:
>>   			return (!get_pcie_temp(hwmon, &val)) ? 0444 : 0;
>> +		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
> So this means we're exposing them all but do we really have 16 VRAMs?

we have support for maximum of 16, we don't have mechanism to detect 
VRAM if it is present,

we could check returned temperature is non-zero, but if temp is 0 C, it 
would be valid.

>
>> +			return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_TEMP,
>> +					       channel)) ? 0444 : 0;
>>   		default:
>>   			return 0;
>>   		}
>> @@ -935,6 +960,9 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
>>   			return (!get_mc_temp(hwmon, &val)) ? 0444 : 0;
>>   		case CHANNEL_PCIE:
>>   			return (!get_pcie_temp(hwmon, &val)) ? 0444 : 0;
>> +		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
> Ditto.
>
>> +			return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_TEMP,
>> +					       channel)) ? 0444 : 0;
>>   		default:
>>   			return 0;
>>   		}
>> @@ -958,6 +986,9 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
>>   			return (!get_mc_temp(hwmon, &val)) ? 0444 : 0;
>>   		case CHANNEL_PCIE:
>>   			return (!get_pcie_temp(hwmon, &val)) ? 0444 : 0;
>> +		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
> Ditto.
>
>> +			return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_TEMP,
>> +					       channel)) ? 0444 : 0;
>>   		default:
>>   			return 0;
>>   		}
>> @@ -986,6 +1017,12 @@ xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
>>   			return get_mc_temp(hwmon, val);
>>   		case CHANNEL_PCIE:
>>   			return get_pcie_temp(hwmon, val);
>> +		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
>> +			reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_TEMP, channel));
>> +			/* Temperature format here is S 31.23.8 */
> I'm not confident if this is translatable to human beings, could you
> please elaborate?

This is signed format, 31 bit for sign, 23 bits for whole number part 
and 8 bits for fraction.

I shall add a comment about this next revision.

>
>> +			*val = REG_FIELD_GET(TEMP_MASK_VRAM_N, reg_val) *
>> +					     ((reg_val >> 31) ? -1 : 1) * MILLIDEGREE_PER_DEGREE;
>> +			break;
>>   		default:
>>   			*val = 0;
>>   			return -EOPNOTSUPP;
>> @@ -999,6 +1036,7 @@ xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
>>   			break;
>>   		case CHANNEL_VRAM:
>>   		case CHANNEL_MCTRL:
>> +		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
>>   			*val = hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN] * MILLIDEGREE_PER_DEGREE;
>>   			break;
>>   		default:
>> @@ -1014,6 +1052,7 @@ xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
>>   			break;
>>   		case CHANNEL_VRAM:
>>   		case CHANNEL_MCTRL:
>> +		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
>>   			*val = hwmon->temp.limit[TEMP_LIMIT_MEM_TJMAX] * MILLIDEGREE_PER_DEGREE;
>>   			break;
>>   		default:
>> @@ -1386,16 +1425,22 @@ static int xe_hwmon_read_label(struct device *dev,
>>   			       enum hwmon_sensor_types type,
>>   			       u32 attr, int channel, const char **str)
>>   {
>> +	char temp[16] = {0};
>> +
>>   	switch (type) {
>>   	case hwmon_temp:
>>   		if (channel == CHANNEL_PKG)
>>   			*str = "pkg";
>>   		else if (channel == CHANNEL_VRAM)
>> -			*str = "vram";
>> +			*str = "vram_avg";
>>   		else if (channel == CHANNEL_MCTRL)
>>   			*str = "mctrl_avg";
>>   		else if (channel == CHANNEL_PCIE)
>>   			*str = "pcie";
>> +		else if (channel >= CHANNEL_VRAM_N && channel <= CHANNEL_VRAM_N_MAX) {
>> +			sprintf(temp, "vram_%d", (channel - CHANNEL_VRAM_N));
>> +			*str = temp;
> Can this be done without temp?
>
> Raag
I experimented with different methods; this one compiles without warnings.
Do you have any suggestions ?

>
>> +		}
>>   		return 0;
>>   	case hwmon_power:
>>   	case hwmon_energy:
>> -- 
>> 2.25.1
>>

[-- Attachment #2: Type: text/html, Size: 13932 bytes --]

✓ CI.KUnit: success for drm/xe/hwmon: Expose new temperature attributes (rev4)

[Patchwork]

== Series Details ==

Series: drm/xe/hwmon: Expose new temperature attributes (rev4)
URL   : https://patchwork.freedesktop.org/series/158384/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[19:26:45] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[19:26:49] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[19:27:21] Starting KUnit Kernel (1/1)...
[19:27:21] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[19:27:21] ================== guc_buf (11 subtests) ===================
[19:27:21] [PASSED] test_smallest
[19:27:21] [PASSED] test_largest
[19:27:21] [PASSED] test_granular
[19:27:21] [PASSED] test_unique
[19:27:21] [PASSED] test_overlap
[19:27:21] [PASSED] test_reusable
[19:27:21] [PASSED] test_too_big
[19:27:21] [PASSED] test_flush
[19:27:21] [PASSED] test_lookup
[19:27:21] [PASSED] test_data
[19:27:21] [PASSED] test_class
[19:27:21] ===================== [PASSED] guc_buf =====================
[19:27:21] =================== guc_dbm (7 subtests) ===================
[19:27:21] [PASSED] test_empty
[19:27:21] [PASSED] test_default
[19:27:21] ======================== test_size  ========================
[19:27:21] [PASSED] 4
[19:27:21] [PASSED] 8
[19:27:21] [PASSED] 32
[19:27:21] [PASSED] 256
[19:27:21] ==================== [PASSED] test_size ====================
[19:27:21] ======================= test_reuse  ========================
[19:27:21] [PASSED] 4
[19:27:21] [PASSED] 8
[19:27:21] [PASSED] 32
[19:27:21] [PASSED] 256
[19:27:21] =================== [PASSED] test_reuse ====================
[19:27:21] =================== test_range_overlap  ====================
[19:27:21] [PASSED] 4
[19:27:21] [PASSED] 8
[19:27:21] [PASSED] 32
[19:27:21] [PASSED] 256
[19:27:21] =============== [PASSED] test_range_overlap ================
[19:27:21] =================== test_range_compact  ====================
[19:27:21] [PASSED] 4
[19:27:21] [PASSED] 8
[19:27:21] [PASSED] 32
[19:27:21] [PASSED] 256
[19:27:21] =============== [PASSED] test_range_compact ================
[19:27:21] ==================== test_range_spare  =====================
[19:27:21] [PASSED] 4
[19:27:21] [PASSED] 8
[19:27:21] [PASSED] 32
[19:27:21] [PASSED] 256
[19:27:21] ================ [PASSED] test_range_spare =================
[19:27:21] ===================== [PASSED] guc_dbm =====================
[19:27:21] =================== guc_idm (6 subtests) ===================
[19:27:21] [PASSED] bad_init
[19:27:21] [PASSED] no_init
[19:27:21] [PASSED] init_fini
[19:27:21] [PASSED] check_used
[19:27:21] [PASSED] check_quota
[19:27:21] [PASSED] check_all
[19:27:21] ===================== [PASSED] guc_idm =====================
[19:27:21] ================== no_relay (3 subtests) ===================
[19:27:21] [PASSED] xe_drops_guc2pf_if_not_ready
[19:27:21] [PASSED] xe_drops_guc2vf_if_not_ready
[19:27:21] [PASSED] xe_rejects_send_if_not_ready
[19:27:21] ==================== [PASSED] no_relay =====================
[19:27:21] ================== pf_relay (14 subtests) ==================
[19:27:21] [PASSED] pf_rejects_guc2pf_too_short
[19:27:21] [PASSED] pf_rejects_guc2pf_too_long
[19:27:21] [PASSED] pf_rejects_guc2pf_no_payload
[19:27:21] [PASSED] pf_fails_no_payload
[19:27:21] [PASSED] pf_fails_bad_origin
[19:27:21] [PASSED] pf_fails_bad_type
[19:27:21] [PASSED] pf_txn_reports_error
[19:27:21] [PASSED] pf_txn_sends_pf2guc
[19:27:21] [PASSED] pf_sends_pf2guc
[19:27:21] [SKIPPED] pf_loopback_nop
[19:27:21] [SKIPPED] pf_loopback_echo
[19:27:21] [SKIPPED] pf_loopback_fail
[19:27:21] [SKIPPED] pf_loopback_busy
[19:27:21] [SKIPPED] pf_loopback_retry
[19:27:21] ==================== [PASSED] pf_relay =====================
[19:27:21] ================== vf_relay (3 subtests) ===================
[19:27:21] [PASSED] vf_rejects_guc2vf_too_short
[19:27:21] [PASSED] vf_rejects_guc2vf_too_long
[19:27:21] [PASSED] vf_rejects_guc2vf_no_payload
[19:27:21] ==================== [PASSED] vf_relay =====================
[19:27:21] ================ pf_gt_config (6 subtests) =================
[19:27:21] [PASSED] fair_contexts_1vf
[19:27:21] [PASSED] fair_doorbells_1vf
[19:27:21] [PASSED] fair_ggtt_1vf
[19:27:21] ====================== fair_contexts  ======================
[19:27:21] [PASSED] 1 VF
[19:27:21] [PASSED] 2 VFs
[19:27:21] [PASSED] 3 VFs
[19:27:21] [PASSED] 4 VFs
[19:27:21] [PASSED] 5 VFs
[19:27:21] [PASSED] 6 VFs
[19:27:21] [PASSED] 7 VFs
[19:27:21] [PASSED] 8 VFs
[19:27:21] [PASSED] 9 VFs
[19:27:21] [PASSED] 10 VFs
[19:27:21] [PASSED] 11 VFs
[19:27:21] [PASSED] 12 VFs
[19:27:21] [PASSED] 13 VFs
[19:27:21] [PASSED] 14 VFs
[19:27:21] [PASSED] 15 VFs
[19:27:21] [PASSED] 16 VFs
[19:27:21] [PASSED] 17 VFs
[19:27:21] [PASSED] 18 VFs
[19:27:21] [PASSED] 19 VFs
[19:27:21] [PASSED] 20 VFs
[19:27:21] [PASSED] 21 VFs
[19:27:21] [PASSED] 22 VFs
[19:27:21] [PASSED] 23 VFs
[19:27:21] [PASSED] 24 VFs
[19:27:21] [PASSED] 25 VFs
[19:27:21] [PASSED] 26 VFs
[19:27:21] [PASSED] 27 VFs
[19:27:21] [PASSED] 28 VFs
[19:27:21] [PASSED] 29 VFs
[19:27:21] [PASSED] 30 VFs
[19:27:21] [PASSED] 31 VFs
[19:27:21] [PASSED] 32 VFs
[19:27:21] [PASSED] 33 VFs
[19:27:21] [PASSED] 34 VFs
[19:27:21] [PASSED] 35 VFs
[19:27:21] [PASSED] 36 VFs
[19:27:21] [PASSED] 37 VFs
[19:27:21] [PASSED] 38 VFs
[19:27:21] [PASSED] 39 VFs
[19:27:21] [PASSED] 40 VFs
[19:27:21] [PASSED] 41 VFs
[19:27:21] [PASSED] 42 VFs
[19:27:21] [PASSED] 43 VFs
[19:27:21] [PASSED] 44 VFs
[19:27:21] [PASSED] 45 VFs
[19:27:21] [PASSED] 46 VFs
[19:27:21] [PASSED] 47 VFs
[19:27:21] [PASSED] 48 VFs
[19:27:21] [PASSED] 49 VFs
[19:27:21] [PASSED] 50 VFs
[19:27:21] [PASSED] 51 VFs
[19:27:21] [PASSED] 52 VFs
[19:27:21] [PASSED] 53 VFs
[19:27:21] [PASSED] 54 VFs
[19:27:21] [PASSED] 55 VFs
[19:27:21] [PASSED] 56 VFs
[19:27:21] [PASSED] 57 VFs
[19:27:21] [PASSED] 58 VFs
[19:27:21] [PASSED] 59 VFs
[19:27:21] [PASSED] 60 VFs
[19:27:21] [PASSED] 61 VFs
[19:27:21] [PASSED] 62 VFs
[19:27:21] [PASSED] 63 VFs
[19:27:21] ================== [PASSED] fair_contexts ==================
[19:27:21] ===================== fair_doorbells  ======================
[19:27:21] [PASSED] 1 VF
[19:27:21] [PASSED] 2 VFs
[19:27:21] [PASSED] 3 VFs
[19:27:21] [PASSED] 4 VFs
[19:27:21] [PASSED] 5 VFs
[19:27:21] [PASSED] 6 VFs
[19:27:21] [PASSED] 7 VFs
[19:27:21] [PASSED] 8 VFs
[19:27:21] [PASSED] 9 VFs
[19:27:21] [PASSED] 10 VFs
[19:27:21] [PASSED] 11 VFs
[19:27:21] [PASSED] 12 VFs
[19:27:21] [PASSED] 13 VFs
[19:27:21] [PASSED] 14 VFs
[19:27:21] [PASSED] 15 VFs
[19:27:21] [PASSED] 16 VFs
[19:27:21] [PASSED] 17 VFs
[19:27:21] [PASSED] 18 VFs
[19:27:21] [PASSED] 19 VFs
[19:27:21] [PASSED] 20 VFs
[19:27:21] [PASSED] 21 VFs
[19:27:21] [PASSED] 22 VFs
[19:27:21] [PASSED] 23 VFs
[19:27:21] [PASSED] 24 VFs
[19:27:21] [PASSED] 25 VFs
[19:27:21] [PASSED] 26 VFs
[19:27:21] [PASSED] 27 VFs
[19:27:21] [PASSED] 28 VFs
[19:27:21] [PASSED] 29 VFs
[19:27:21] [PASSED] 30 VFs
[19:27:21] [PASSED] 31 VFs
[19:27:21] [PASSED] 32 VFs
[19:27:21] [PASSED] 33 VFs
[19:27:21] [PASSED] 34 VFs
[19:27:21] [PASSED] 35 VFs
[19:27:21] [PASSED] 36 VFs
[19:27:21] [PASSED] 37 VFs
[19:27:21] [PASSED] 38 VFs
[19:27:21] [PASSED] 39 VFs
[19:27:21] [PASSED] 40 VFs
[19:27:21] [PASSED] 41 VFs
[19:27:21] [PASSED] 42 VFs
[19:27:21] [PASSED] 43 VFs
[19:27:21] [PASSED] 44 VFs
[19:27:21] [PASSED] 45 VFs
[19:27:21] [PASSED] 46 VFs
[19:27:21] [PASSED] 47 VFs
[19:27:21] [PASSED] 48 VFs
[19:27:21] [PASSED] 49 VFs
[19:27:21] [PASSED] 50 VFs
[19:27:21] [PASSED] 51 VFs
[19:27:21] [PASSED] 52 VFs
[19:27:21] [PASSED] 53 VFs
[19:27:21] [PASSED] 54 VFs
[19:27:21] [PASSED] 55 VFs
[19:27:21] [PASSED] 56 VFs
[19:27:21] [PASSED] 57 VFs
[19:27:21] [PASSED] 58 VFs
[19:27:21] [PASSED] 59 VFs
[19:27:21] [PASSED] 60 VFs
[19:27:21] [PASSED] 61 VFs
[19:27:21] [PASSED] 62 VFs
[19:27:21] [PASSED] 63 VFs
[19:27:21] ================= [PASSED] fair_doorbells ==================
[19:27:21] ======================== fair_ggtt  ========================
[19:27:21] [PASSED] 1 VF
[19:27:21] [PASSED] 2 VFs
[19:27:21] [PASSED] 3 VFs
[19:27:21] [PASSED] 4 VFs
[19:27:21] [PASSED] 5 VFs
[19:27:21] [PASSED] 6 VFs
[19:27:21] [PASSED] 7 VFs
[19:27:21] [PASSED] 8 VFs
[19:27:21] [PASSED] 9 VFs
[19:27:21] [PASSED] 10 VFs
[19:27:21] [PASSED] 11 VFs
[19:27:21] [PASSED] 12 VFs
[19:27:21] [PASSED] 13 VFs
[19:27:21] [PASSED] 14 VFs
[19:27:21] [PASSED] 15 VFs
[19:27:21] [PASSED] 16 VFs
[19:27:21] [PASSED] 17 VFs
[19:27:21] [PASSED] 18 VFs
[19:27:21] [PASSED] 19 VFs
[19:27:21] [PASSED] 20 VFs
[19:27:21] [PASSED] 21 VFs
[19:27:21] [PASSED] 22 VFs
[19:27:21] [PASSED] 23 VFs
[19:27:21] [PASSED] 24 VFs
[19:27:21] [PASSED] 25 VFs
[19:27:21] [PASSED] 26 VFs
[19:27:21] [PASSED] 27 VFs
[19:27:21] [PASSED] 28 VFs
[19:27:21] [PASSED] 29 VFs
[19:27:21] [PASSED] 30 VFs
[19:27:21] [PASSED] 31 VFs
[19:27:21] [PASSED] 32 VFs
[19:27:21] [PASSED] 33 VFs
[19:27:21] [PASSED] 34 VFs
[19:27:21] [PASSED] 35 VFs
[19:27:21] [PASSED] 36 VFs
[19:27:21] [PASSED] 37 VFs
[19:27:21] [PASSED] 38 VFs
[19:27:21] [PASSED] 39 VFs
[19:27:21] [PASSED] 40 VFs
[19:27:21] [PASSED] 41 VFs
[19:27:21] [PASSED] 42 VFs
[19:27:21] [PASSED] 43 VFs
[19:27:21] [PASSED] 44 VFs
[19:27:21] [PASSED] 45 VFs
[19:27:21] [PASSED] 46 VFs
[19:27:21] [PASSED] 47 VFs
[19:27:21] [PASSED] 48 VFs
[19:27:21] [PASSED] 49 VFs
[19:27:21] [PASSED] 50 VFs
[19:27:21] [PASSED] 51 VFs
[19:27:21] [PASSED] 52 VFs
[19:27:21] [PASSED] 53 VFs
[19:27:21] [PASSED] 54 VFs
[19:27:21] [PASSED] 55 VFs
[19:27:21] [PASSED] 56 VFs
[19:27:21] [PASSED] 57 VFs
[19:27:21] [PASSED] 58 VFs
[19:27:21] [PASSED] 59 VFs
[19:27:21] [PASSED] 60 VFs
[19:27:21] [PASSED] 61 VFs
[19:27:21] [PASSED] 62 VFs
[19:27:21] [PASSED] 63 VFs
[19:27:21] ==================== [PASSED] fair_ggtt ====================
[19:27:21] ================== [PASSED] pf_gt_config ===================
[19:27:21] ===================== lmtt (1 subtest) =====================
[19:27:21] ======================== test_ops  =========================
[19:27:21] [PASSED] 2-level
[19:27:21] [PASSED] multi-level
[19:27:21] ==================== [PASSED] test_ops =====================
[19:27:21] ====================== [PASSED] lmtt =======================
[19:27:21] ================= pf_service (11 subtests) =================
[19:27:21] [PASSED] pf_negotiate_any
[19:27:21] [PASSED] pf_negotiate_base_match
[19:27:21] [PASSED] pf_negotiate_base_newer
[19:27:21] [PASSED] pf_negotiate_base_next
[19:27:21] [SKIPPED] pf_negotiate_base_older
[19:27:21] [PASSED] pf_negotiate_base_prev
[19:27:21] [PASSED] pf_negotiate_latest_match
[19:27:21] [PASSED] pf_negotiate_latest_newer
[19:27:21] [PASSED] pf_negotiate_latest_next
[19:27:21] [SKIPPED] pf_negotiate_latest_older
[19:27:21] [SKIPPED] pf_negotiate_latest_prev
[19:27:21] =================== [PASSED] pf_service ====================
[19:27:21] ================= xe_guc_g2g (2 subtests) ==================
[19:27:21] ============== xe_live_guc_g2g_kunit_default  ==============
[19:27:21] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[19:27:21] ============== xe_live_guc_g2g_kunit_allmem  ===============
[19:27:21] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[19:27:21] =================== [SKIPPED] xe_guc_g2g ===================
[19:27:21] =================== xe_mocs (2 subtests) ===================
[19:27:21] ================ xe_live_mocs_kernel_kunit  ================
[19:27:21] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[19:27:21] ================ xe_live_mocs_reset_kunit  =================
[19:27:21] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[19:27:21] ==================== [SKIPPED] xe_mocs =====================
[19:27:21] ================= xe_migrate (2 subtests) ==================
[19:27:21] ================= xe_migrate_sanity_kunit  =================
[19:27:21] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[19:27:21] ================== xe_validate_ccs_kunit  ==================
[19:27:21] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[19:27:21] =================== [SKIPPED] xe_migrate ===================
[19:27:21] ================== xe_dma_buf (1 subtest) ==================
[19:27:21] ==================== xe_dma_buf_kunit  =====================
[19:27:21] ================ [SKIPPED] xe_dma_buf_kunit ================
[19:27:21] =================== [SKIPPED] xe_dma_buf ===================
[19:27:21] ================= xe_bo_shrink (1 subtest) =================
[19:27:21] =================== xe_bo_shrink_kunit  ====================
[19:27:21] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[19:27:21] ================== [SKIPPED] xe_bo_shrink ==================
[19:27:21] ==================== xe_bo (2 subtests) ====================
[19:27:21] ================== xe_ccs_migrate_kunit  ===================
[19:27:21] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[19:27:21] ==================== xe_bo_evict_kunit  ====================
[19:27:21] =============== [SKIPPED] xe_bo_evict_kunit ================
[19:27:21] ===================== [SKIPPED] xe_bo ======================
[19:27:21] ==================== args (11 subtests) ====================
[19:27:21] [PASSED] count_args_test
[19:27:21] [PASSED] call_args_example
[19:27:21] [PASSED] call_args_test
[19:27:21] [PASSED] drop_first_arg_example
[19:27:21] [PASSED] drop_first_arg_test
[19:27:21] [PASSED] first_arg_example
[19:27:21] [PASSED] first_arg_test
[19:27:21] [PASSED] last_arg_example
[19:27:21] [PASSED] last_arg_test
[19:27:21] [PASSED] pick_arg_example
[19:27:21] [PASSED] sep_comma_example
[19:27:21] ====================== [PASSED] args =======================
[19:27:21] =================== xe_pci (3 subtests) ====================
[19:27:21] ==================== check_graphics_ip  ====================
[19:27:21] [PASSED] 12.00 Xe_LP
[19:27:21] [PASSED] 12.10 Xe_LP+
[19:27:21] [PASSED] 12.55 Xe_HPG
[19:27:21] [PASSED] 12.60 Xe_HPC
[19:27:21] [PASSED] 12.70 Xe_LPG
[19:27:21] [PASSED] 12.71 Xe_LPG
[19:27:21] [PASSED] 12.74 Xe_LPG+
[19:27:21] [PASSED] 20.01 Xe2_HPG
[19:27:21] [PASSED] 20.02 Xe2_HPG
[19:27:21] [PASSED] 20.04 Xe2_LPG
[19:27:21] [PASSED] 30.00 Xe3_LPG
[19:27:21] [PASSED] 30.01 Xe3_LPG
[19:27:21] [PASSED] 30.03 Xe3_LPG
[19:27:21] [PASSED] 30.04 Xe3_LPG
[19:27:21] [PASSED] 30.05 Xe3_LPG
[19:27:21] [PASSED] 35.11 Xe3p_XPC
[19:27:21] ================ [PASSED] check_graphics_ip ================
[19:27:21] ===================== check_media_ip  ======================
[19:27:21] [PASSED] 12.00 Xe_M
[19:27:21] [PASSED] 12.55 Xe_HPM
[19:27:21] [PASSED] 13.00 Xe_LPM+
[19:27:21] [PASSED] 13.01 Xe2_HPM
[19:27:21] [PASSED] 20.00 Xe2_LPM
[19:27:21] [PASSED] 30.00 Xe3_LPM
[19:27:21] [PASSED] 30.02 Xe3_LPM
[19:27:21] [PASSED] 35.00 Xe3p_LPM
[19:27:21] [PASSED] 35.03 Xe3p_HPM
[19:27:21] ================= [PASSED] check_media_ip ==================
[19:27:21] =================== check_platform_desc  ===================
[19:27:21] [PASSED] 0x9A60 (TIGERLAKE)
[19:27:21] [PASSED] 0x9A68 (TIGERLAKE)
[19:27:21] [PASSED] 0x9A70 (TIGERLAKE)
[19:27:21] [PASSED] 0x9A40 (TIGERLAKE)
[19:27:21] [PASSED] 0x9A49 (TIGERLAKE)
[19:27:21] [PASSED] 0x9A59 (TIGERLAKE)
[19:27:21] [PASSED] 0x9A78 (TIGERLAKE)
[19:27:21] [PASSED] 0x9AC0 (TIGERLAKE)
[19:27:21] [PASSED] 0x9AC9 (TIGERLAKE)
[19:27:21] [PASSED] 0x9AD9 (TIGERLAKE)
[19:27:21] [PASSED] 0x9AF8 (TIGERLAKE)
[19:27:21] [PASSED] 0x4C80 (ROCKETLAKE)
[19:27:21] [PASSED] 0x4C8A (ROCKETLAKE)
[19:27:21] [PASSED] 0x4C8B (ROCKETLAKE)
[19:27:21] [PASSED] 0x4C8C (ROCKETLAKE)
[19:27:21] [PASSED] 0x4C90 (ROCKETLAKE)
[19:27:21] [PASSED] 0x4C9A (ROCKETLAKE)
[19:27:21] [PASSED] 0x4680 (ALDERLAKE_S)
[19:27:21] [PASSED] 0x4682 (ALDERLAKE_S)
[19:27:21] [PASSED] 0x4688 (ALDERLAKE_S)
[19:27:21] [PASSED] 0x468A (ALDERLAKE_S)
[19:27:21] [PASSED] 0x468B (ALDERLAKE_S)
[19:27:21] [PASSED] 0x4690 (ALDERLAKE_S)
[19:27:21] [PASSED] 0x4692 (ALDERLAKE_S)
[19:27:21] [PASSED] 0x4693 (ALDERLAKE_S)
[19:27:21] [PASSED] 0x46A0 (ALDERLAKE_P)
[19:27:21] [PASSED] 0x46A1 (ALDERLAKE_P)
[19:27:21] [PASSED] 0x46A2 (ALDERLAKE_P)
[19:27:21] [PASSED] 0x46A3 (ALDERLAKE_P)
[19:27:21] [PASSED] 0x46A6 (ALDERLAKE_P)
[19:27:21] [PASSED] 0x46A8 (ALDERLAKE_P)
[19:27:21] [PASSED] 0x46AA (ALDERLAKE_P)
[19:27:21] [PASSED] 0x462A (ALDERLAKE_P)
[19:27:21] [PASSED] 0x4626 (ALDERLAKE_P)
[19:27:21] [PASSED] 0x4628 (ALDERLAKE_P)
[19:27:21] [PASSED] 0x46B0 (ALDERLAKE_P)
stty: 'standard input': Inappropriate ioctl for device
[19:27:21] [PASSED] 0x46B1 (ALDERLAKE_P)
[19:27:21] [PASSED] 0x46B2 (ALDERLAKE_P)
[19:27:21] [PASSED] 0x46B3 (ALDERLAKE_P)
[19:27:21] [PASSED] 0x46C0 (ALDERLAKE_P)
[19:27:21] [PASSED] 0x46C1 (ALDERLAKE_P)
[19:27:21] [PASSED] 0x46C2 (ALDERLAKE_P)
[19:27:21] [PASSED] 0x46C3 (ALDERLAKE_P)
[19:27:21] [PASSED] 0x46D0 (ALDERLAKE_N)
[19:27:21] [PASSED] 0x46D1 (ALDERLAKE_N)
[19:27:21] [PASSED] 0x46D2 (ALDERLAKE_N)
[19:27:21] [PASSED] 0x46D3 (ALDERLAKE_N)
[19:27:21] [PASSED] 0x46D4 (ALDERLAKE_N)
[19:27:21] [PASSED] 0xA721 (ALDERLAKE_P)
[19:27:21] [PASSED] 0xA7A1 (ALDERLAKE_P)
[19:27:21] [PASSED] 0xA7A9 (ALDERLAKE_P)
[19:27:21] [PASSED] 0xA7AC (ALDERLAKE_P)
[19:27:21] [PASSED] 0xA7AD (ALDERLAKE_P)
[19:27:21] [PASSED] 0xA720 (ALDERLAKE_P)
[19:27:21] [PASSED] 0xA7A0 (ALDERLAKE_P)
[19:27:21] [PASSED] 0xA7A8 (ALDERLAKE_P)
[19:27:21] [PASSED] 0xA7AA (ALDERLAKE_P)
[19:27:21] [PASSED] 0xA7AB (ALDERLAKE_P)
[19:27:21] [PASSED] 0xA780 (ALDERLAKE_S)
[19:27:21] [PASSED] 0xA781 (ALDERLAKE_S)
[19:27:21] [PASSED] 0xA782 (ALDERLAKE_S)
[19:27:21] [PASSED] 0xA783 (ALDERLAKE_S)
[19:27:21] [PASSED] 0xA788 (ALDERLAKE_S)
[19:27:21] [PASSED] 0xA789 (ALDERLAKE_S)
[19:27:21] [PASSED] 0xA78A (ALDERLAKE_S)
[19:27:21] [PASSED] 0xA78B (ALDERLAKE_S)
[19:27:21] [PASSED] 0x4905 (DG1)
[19:27:21] [PASSED] 0x4906 (DG1)
[19:27:21] [PASSED] 0x4907 (DG1)
[19:27:21] [PASSED] 0x4908 (DG1)
[19:27:21] [PASSED] 0x4909 (DG1)
[19:27:21] [PASSED] 0x56C0 (DG2)
[19:27:21] [PASSED] 0x56C2 (DG2)
[19:27:21] [PASSED] 0x56C1 (DG2)
[19:27:21] [PASSED] 0x7D51 (METEORLAKE)
[19:27:21] [PASSED] 0x7DD1 (METEORLAKE)
[19:27:21] [PASSED] 0x7D41 (METEORLAKE)
[19:27:21] [PASSED] 0x7D67 (METEORLAKE)
[19:27:21] [PASSED] 0xB640 (METEORLAKE)
[19:27:21] [PASSED] 0x56A0 (DG2)
[19:27:21] [PASSED] 0x56A1 (DG2)
[19:27:21] [PASSED] 0x56A2 (DG2)
[19:27:21] [PASSED] 0x56BE (DG2)
[19:27:21] [PASSED] 0x56BF (DG2)
[19:27:21] [PASSED] 0x5690 (DG2)
[19:27:21] [PASSED] 0x5691 (DG2)
[19:27:21] [PASSED] 0x5692 (DG2)
[19:27:21] [PASSED] 0x56A5 (DG2)
[19:27:21] [PASSED] 0x56A6 (DG2)
[19:27:21] [PASSED] 0x56B0 (DG2)
[19:27:21] [PASSED] 0x56B1 (DG2)
[19:27:21] [PASSED] 0x56BA (DG2)
[19:27:21] [PASSED] 0x56BB (DG2)
[19:27:21] [PASSED] 0x56BC (DG2)
[19:27:21] [PASSED] 0x56BD (DG2)
[19:27:21] [PASSED] 0x5693 (DG2)
[19:27:21] [PASSED] 0x5694 (DG2)
[19:27:21] [PASSED] 0x5695 (DG2)
[19:27:21] [PASSED] 0x56A3 (DG2)
[19:27:21] [PASSED] 0x56A4 (DG2)
[19:27:21] [PASSED] 0x56B2 (DG2)
[19:27:21] [PASSED] 0x56B3 (DG2)
[19:27:21] [PASSED] 0x5696 (DG2)
[19:27:21] [PASSED] 0x5697 (DG2)
[19:27:21] [PASSED] 0xB69 (PVC)
[19:27:21] [PASSED] 0xB6E (PVC)
[19:27:21] [PASSED] 0xBD4 (PVC)
[19:27:21] [PASSED] 0xBD5 (PVC)
[19:27:21] [PASSED] 0xBD6 (PVC)
[19:27:21] [PASSED] 0xBD7 (PVC)
[19:27:21] [PASSED] 0xBD8 (PVC)
[19:27:21] [PASSED] 0xBD9 (PVC)
[19:27:21] [PASSED] 0xBDA (PVC)
[19:27:21] [PASSED] 0xBDB (PVC)
[19:27:21] [PASSED] 0xBE0 (PVC)
[19:27:21] [PASSED] 0xBE1 (PVC)
[19:27:21] [PASSED] 0xBE5 (PVC)
[19:27:21] [PASSED] 0x7D40 (METEORLAKE)
[19:27:21] [PASSED] 0x7D45 (METEORLAKE)
[19:27:21] [PASSED] 0x7D55 (METEORLAKE)
[19:27:21] [PASSED] 0x7D60 (METEORLAKE)
[19:27:21] [PASSED] 0x7DD5 (METEORLAKE)
[19:27:21] [PASSED] 0x6420 (LUNARLAKE)
[19:27:21] [PASSED] 0x64A0 (LUNARLAKE)
[19:27:21] [PASSED] 0x64B0 (LUNARLAKE)
[19:27:21] [PASSED] 0xE202 (BATTLEMAGE)
[19:27:21] [PASSED] 0xE209 (BATTLEMAGE)
[19:27:21] [PASSED] 0xE20B (BATTLEMAGE)
[19:27:21] [PASSED] 0xE20C (BATTLEMAGE)
[19:27:21] [PASSED] 0xE20D (BATTLEMAGE)
[19:27:21] [PASSED] 0xE210 (BATTLEMAGE)
[19:27:21] [PASSED] 0xE211 (BATTLEMAGE)
[19:27:21] [PASSED] 0xE212 (BATTLEMAGE)
[19:27:21] [PASSED] 0xE216 (BATTLEMAGE)
[19:27:21] [PASSED] 0xE220 (BATTLEMAGE)
[19:27:21] [PASSED] 0xE221 (BATTLEMAGE)
[19:27:21] [PASSED] 0xE222 (BATTLEMAGE)
[19:27:21] [PASSED] 0xE223 (BATTLEMAGE)
[19:27:21] [PASSED] 0xB080 (PANTHERLAKE)
[19:27:21] [PASSED] 0xB081 (PANTHERLAKE)
[19:27:21] [PASSED] 0xB082 (PANTHERLAKE)
[19:27:21] [PASSED] 0xB083 (PANTHERLAKE)
[19:27:21] [PASSED] 0xB084 (PANTHERLAKE)
[19:27:21] [PASSED] 0xB085 (PANTHERLAKE)
[19:27:21] [PASSED] 0xB086 (PANTHERLAKE)
[19:27:21] [PASSED] 0xB087 (PANTHERLAKE)
[19:27:21] [PASSED] 0xB08F (PANTHERLAKE)
[19:27:21] [PASSED] 0xB090 (PANTHERLAKE)
[19:27:21] [PASSED] 0xB0A0 (PANTHERLAKE)
[19:27:21] [PASSED] 0xB0B0 (PANTHERLAKE)
[19:27:21] [PASSED] 0xFD80 (PANTHERLAKE)
[19:27:21] [PASSED] 0xFD81 (PANTHERLAKE)
[19:27:21] [PASSED] 0xD740 (NOVALAKE_S)
[19:27:21] [PASSED] 0xD741 (NOVALAKE_S)
[19:27:21] [PASSED] 0xD742 (NOVALAKE_S)
[19:27:21] [PASSED] 0xD743 (NOVALAKE_S)
[19:27:21] [PASSED] 0xD744 (NOVALAKE_S)
[19:27:21] [PASSED] 0xD745 (NOVALAKE_S)
[19:27:21] [PASSED] 0x674C (CRESCENTISLAND)
[19:27:21] =============== [PASSED] check_platform_desc ===============
[19:27:21] ===================== [PASSED] xe_pci ======================
[19:27:21] =================== xe_rtp (2 subtests) ====================
[19:27:21] =============== xe_rtp_process_to_sr_tests  ================
[19:27:21] [PASSED] coalesce-same-reg
[19:27:21] [PASSED] no-match-no-add
[19:27:21] [PASSED] match-or
[19:27:21] [PASSED] match-or-xfail
[19:27:21] [PASSED] no-match-no-add-multiple-rules
[19:27:21] [PASSED] two-regs-two-entries
[19:27:21] [PASSED] clr-one-set-other
[19:27:21] [PASSED] set-field
[19:27:21] [PASSED] conflict-duplicate
[19:27:21] [PASSED] conflict-not-disjoint
[19:27:21] [PASSED] conflict-reg-type
[19:27:21] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[19:27:21] ================== xe_rtp_process_tests  ===================
[19:27:21] [PASSED] active1
[19:27:21] [PASSED] active2
[19:27:21] [PASSED] active-inactive
[19:27:21] [PASSED] inactive-active
[19:27:21] [PASSED] inactive-1st_or_active-inactive
[19:27:21] [PASSED] inactive-2nd_or_active-inactive
[19:27:21] [PASSED] inactive-last_or_active-inactive
[19:27:21] [PASSED] inactive-no_or_active-inactive
[19:27:21] ============== [PASSED] xe_rtp_process_tests ===============
[19:27:21] ===================== [PASSED] xe_rtp ======================
[19:27:21] ==================== xe_wa (1 subtest) =====================
[19:27:21] ======================== xe_wa_gt  =========================
[19:27:21] [PASSED] TIGERLAKE B0
[19:27:21] [PASSED] DG1 A0
[19:27:21] [PASSED] DG1 B0
[19:27:21] [PASSED] ALDERLAKE_S A0
[19:27:21] [PASSED] ALDERLAKE_S B0
[19:27:21] [PASSED] ALDERLAKE_S C0
[19:27:21] [PASSED] ALDERLAKE_S D0
[19:27:21] [PASSED] ALDERLAKE_P A0
[19:27:21] [PASSED] ALDERLAKE_P B0
[19:27:21] [PASSED] ALDERLAKE_P C0
[19:27:21] [PASSED] ALDERLAKE_S RPLS D0
[19:27:21] [PASSED] ALDERLAKE_P RPLU E0
[19:27:21] [PASSED] DG2 G10 C0
[19:27:21] [PASSED] DG2 G11 B1
[19:27:21] [PASSED] DG2 G12 A1
[19:27:21] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[19:27:21] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[19:27:21] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[19:27:21] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[19:27:21] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[19:27:21] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[19:27:21] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[19:27:21] ==================== [PASSED] xe_wa_gt =====================
[19:27:21] ====================== [PASSED] xe_wa ======================
[19:27:21] ============================================================
[19:27:21] Testing complete. Ran 510 tests: passed: 492, skipped: 18
[19:27:21] Elapsed time: 36.150s total, 4.176s configuring, 31.458s building, 0.463s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[19:27:21] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[19:27:23] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[19:27:48] Starting KUnit Kernel (1/1)...
[19:27:48] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[19:27:48] ============ drm_test_pick_cmdline (2 subtests) ============
[19:27:48] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[19:27:48] =============== drm_test_pick_cmdline_named  ===============
[19:27:48] [PASSED] NTSC
[19:27:48] [PASSED] NTSC-J
[19:27:48] [PASSED] PAL
[19:27:48] [PASSED] PAL-M
[19:27:48] =========== [PASSED] drm_test_pick_cmdline_named ===========
[19:27:48] ============== [PASSED] drm_test_pick_cmdline ==============
[19:27:48] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[19:27:48] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[19:27:48] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[19:27:48] =========== drm_validate_clone_mode (2 subtests) ===========
[19:27:48] ============== drm_test_check_in_clone_mode  ===============
[19:27:48] [PASSED] in_clone_mode
[19:27:48] [PASSED] not_in_clone_mode
[19:27:48] ========== [PASSED] drm_test_check_in_clone_mode ===========
[19:27:48] =============== drm_test_check_valid_clones  ===============
[19:27:48] [PASSED] not_in_clone_mode
[19:27:48] [PASSED] valid_clone
[19:27:48] [PASSED] invalid_clone
[19:27:48] =========== [PASSED] drm_test_check_valid_clones ===========
[19:27:48] ============= [PASSED] drm_validate_clone_mode =============
[19:27:48] ============= drm_validate_modeset (1 subtest) =============
[19:27:48] [PASSED] drm_test_check_connector_changed_modeset
[19:27:48] ============== [PASSED] drm_validate_modeset ===============
[19:27:48] ====== drm_test_bridge_get_current_state (2 subtests) ======
[19:27:48] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[19:27:48] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[19:27:48] ======== [PASSED] drm_test_bridge_get_current_state ========
[19:27:48] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[19:27:48] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[19:27:48] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[19:27:48] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[19:27:48] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[19:27:48] ============== drm_bridge_alloc (2 subtests) ===============
[19:27:48] [PASSED] drm_test_drm_bridge_alloc_basic
[19:27:48] [PASSED] drm_test_drm_bridge_alloc_get_put
[19:27:48] ================ [PASSED] drm_bridge_alloc =================
[19:27:48] ================== drm_buddy (8 subtests) ==================
[19:27:48] [PASSED] drm_test_buddy_alloc_limit
[19:27:48] [PASSED] drm_test_buddy_alloc_optimistic
[19:27:48] [PASSED] drm_test_buddy_alloc_pessimistic
[19:27:48] [PASSED] drm_test_buddy_alloc_pathological
[19:27:48] [PASSED] drm_test_buddy_alloc_contiguous
[19:27:48] [PASSED] drm_test_buddy_alloc_clear
[19:27:48] [PASSED] drm_test_buddy_alloc_range_bias
[19:27:48] [PASSED] drm_test_buddy_fragmentation_performance
[19:27:48] ==================== [PASSED] drm_buddy ====================
[19:27:48] ============= drm_cmdline_parser (40 subtests) =============
[19:27:48] [PASSED] drm_test_cmdline_force_d_only
[19:27:48] [PASSED] drm_test_cmdline_force_D_only_dvi
[19:27:48] [PASSED] drm_test_cmdline_force_D_only_hdmi
[19:27:48] [PASSED] drm_test_cmdline_force_D_only_not_digital
[19:27:48] [PASSED] drm_test_cmdline_force_e_only
[19:27:48] [PASSED] drm_test_cmdline_res
[19:27:48] [PASSED] drm_test_cmdline_res_vesa
[19:27:48] [PASSED] drm_test_cmdline_res_vesa_rblank
[19:27:48] [PASSED] drm_test_cmdline_res_rblank
[19:27:48] [PASSED] drm_test_cmdline_res_bpp
[19:27:48] [PASSED] drm_test_cmdline_res_refresh
[19:27:48] [PASSED] drm_test_cmdline_res_bpp_refresh
[19:27:48] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[19:27:48] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[19:27:48] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[19:27:48] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[19:27:48] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[19:27:48] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[19:27:48] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[19:27:48] [PASSED] drm_test_cmdline_res_margins_force_on
[19:27:48] [PASSED] drm_test_cmdline_res_vesa_margins
[19:27:48] [PASSED] drm_test_cmdline_name
[19:27:48] [PASSED] drm_test_cmdline_name_bpp
[19:27:48] [PASSED] drm_test_cmdline_name_option
[19:27:48] [PASSED] drm_test_cmdline_name_bpp_option
[19:27:48] [PASSED] drm_test_cmdline_rotate_0
[19:27:48] [PASSED] drm_test_cmdline_rotate_90
[19:27:48] [PASSED] drm_test_cmdline_rotate_180
[19:27:48] [PASSED] drm_test_cmdline_rotate_270
[19:27:48] [PASSED] drm_test_cmdline_hmirror
[19:27:48] [PASSED] drm_test_cmdline_vmirror
[19:27:48] [PASSED] drm_test_cmdline_margin_options
[19:27:48] [PASSED] drm_test_cmdline_multiple_options
[19:27:48] [PASSED] drm_test_cmdline_bpp_extra_and_option
[19:27:48] [PASSED] drm_test_cmdline_extra_and_option
[19:27:48] [PASSED] drm_test_cmdline_freestanding_options
[19:27:48] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[19:27:48] [PASSED] drm_test_cmdline_panel_orientation
[19:27:48] ================ drm_test_cmdline_invalid  =================
[19:27:48] [PASSED] margin_only
[19:27:48] [PASSED] interlace_only
[19:27:48] [PASSED] res_missing_x
[19:27:48] [PASSED] res_missing_y
[19:27:48] [PASSED] res_bad_y
[19:27:48] [PASSED] res_missing_y_bpp
[19:27:48] [PASSED] res_bad_bpp
[19:27:48] [PASSED] res_bad_refresh
[19:27:48] [PASSED] res_bpp_refresh_force_on_off
[19:27:48] [PASSED] res_invalid_mode
[19:27:48] [PASSED] res_bpp_wrong_place_mode
[19:27:48] [PASSED] name_bpp_refresh
[19:27:48] [PASSED] name_refresh
[19:27:48] [PASSED] name_refresh_wrong_mode
[19:27:48] [PASSED] name_refresh_invalid_mode
[19:27:48] [PASSED] rotate_multiple
[19:27:48] [PASSED] rotate_invalid_val
[19:27:48] [PASSED] rotate_truncated
[19:27:48] [PASSED] invalid_option
[19:27:48] [PASSED] invalid_tv_option
[19:27:48] [PASSED] truncated_tv_option
[19:27:48] ============ [PASSED] drm_test_cmdline_invalid =============
[19:27:48] =============== drm_test_cmdline_tv_options  ===============
[19:27:48] [PASSED] NTSC
[19:27:48] [PASSED] NTSC_443
[19:27:48] [PASSED] NTSC_J
[19:27:48] [PASSED] PAL
[19:27:48] [PASSED] PAL_M
[19:27:48] [PASSED] PAL_N
[19:27:48] [PASSED] SECAM
[19:27:48] [PASSED] MONO_525
[19:27:48] [PASSED] MONO_625
[19:27:48] =========== [PASSED] drm_test_cmdline_tv_options ===========
[19:27:48] =============== [PASSED] drm_cmdline_parser ================
[19:27:48] ========== drmm_connector_hdmi_init (20 subtests) ==========
[19:27:48] [PASSED] drm_test_connector_hdmi_init_valid
[19:27:48] [PASSED] drm_test_connector_hdmi_init_bpc_8
[19:27:48] [PASSED] drm_test_connector_hdmi_init_bpc_10
[19:27:48] [PASSED] drm_test_connector_hdmi_init_bpc_12
[19:27:48] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[19:27:48] [PASSED] drm_test_connector_hdmi_init_bpc_null
[19:27:48] [PASSED] drm_test_connector_hdmi_init_formats_empty
[19:27:48] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[19:27:48] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[19:27:48] [PASSED] supported_formats=0x9 yuv420_allowed=1
[19:27:48] [PASSED] supported_formats=0x9 yuv420_allowed=0
[19:27:48] [PASSED] supported_formats=0x3 yuv420_allowed=1
[19:27:48] [PASSED] supported_formats=0x3 yuv420_allowed=0
[19:27:48] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[19:27:48] [PASSED] drm_test_connector_hdmi_init_null_ddc
[19:27:48] [PASSED] drm_test_connector_hdmi_init_null_product
[19:27:48] [PASSED] drm_test_connector_hdmi_init_null_vendor
[19:27:48] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[19:27:48] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[19:27:48] [PASSED] drm_test_connector_hdmi_init_product_valid
[19:27:48] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[19:27:48] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[19:27:48] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[19:27:48] ========= drm_test_connector_hdmi_init_type_valid  =========
[19:27:48] [PASSED] HDMI-A
[19:27:48] [PASSED] HDMI-B
[19:27:48] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[19:27:48] ======== drm_test_connector_hdmi_init_type_invalid  ========
[19:27:48] [PASSED] Unknown
[19:27:48] [PASSED] VGA
[19:27:48] [PASSED] DVI-I
[19:27:48] [PASSED] DVI-D
[19:27:48] [PASSED] DVI-A
[19:27:48] [PASSED] Composite
[19:27:48] [PASSED] SVIDEO
[19:27:48] [PASSED] LVDS
[19:27:48] [PASSED] Component
[19:27:48] [PASSED] DIN
[19:27:48] [PASSED] DP
[19:27:48] [PASSED] TV
[19:27:48] [PASSED] eDP
[19:27:48] [PASSED] Virtual
[19:27:48] [PASSED] DSI
[19:27:48] [PASSED] DPI
[19:27:48] [PASSED] Writeback
[19:27:48] [PASSED] SPI
[19:27:48] [PASSED] USB
[19:27:48] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[19:27:48] ============ [PASSED] drmm_connector_hdmi_init =============
[19:27:48] ============= drmm_connector_init (3 subtests) =============
[19:27:48] [PASSED] drm_test_drmm_connector_init
[19:27:48] [PASSED] drm_test_drmm_connector_init_null_ddc
[19:27:48] ========= drm_test_drmm_connector_init_type_valid  =========
[19:27:48] [PASSED] Unknown
[19:27:48] [PASSED] VGA
[19:27:48] [PASSED] DVI-I
[19:27:48] [PASSED] DVI-D
[19:27:48] [PASSED] DVI-A
[19:27:48] [PASSED] Composite
[19:27:48] [PASSED] SVIDEO
[19:27:48] [PASSED] LVDS
[19:27:48] [PASSED] Component
[19:27:48] [PASSED] DIN
[19:27:48] [PASSED] DP
[19:27:48] [PASSED] HDMI-A
[19:27:48] [PASSED] HDMI-B
[19:27:48] [PASSED] TV
[19:27:48] [PASSED] eDP
[19:27:48] [PASSED] Virtual
[19:27:48] [PASSED] DSI
[19:27:48] [PASSED] DPI
[19:27:48] [PASSED] Writeback
[19:27:48] [PASSED] SPI
[19:27:48] [PASSED] USB
[19:27:48] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[19:27:48] =============== [PASSED] drmm_connector_init ===============
[19:27:48] ========= drm_connector_dynamic_init (6 subtests) ==========
[19:27:48] [PASSED] drm_test_drm_connector_dynamic_init
[19:27:48] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[19:27:48] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[19:27:48] [PASSED] drm_test_drm_connector_dynamic_init_properties
[19:27:48] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[19:27:48] [PASSED] Unknown
[19:27:48] [PASSED] VGA
[19:27:48] [PASSED] DVI-I
[19:27:48] [PASSED] DVI-D
[19:27:48] [PASSED] DVI-A
[19:27:48] [PASSED] Composite
[19:27:48] [PASSED] SVIDEO
[19:27:48] [PASSED] LVDS
[19:27:48] [PASSED] Component
[19:27:48] [PASSED] DIN
[19:27:48] [PASSED] DP
[19:27:48] [PASSED] HDMI-A
[19:27:48] [PASSED] HDMI-B
[19:27:48] [PASSED] TV
[19:27:48] [PASSED] eDP
[19:27:48] [PASSED] Virtual
[19:27:48] [PASSED] DSI
[19:27:48] [PASSED] DPI
[19:27:48] [PASSED] Writeback
[19:27:48] [PASSED] SPI
[19:27:48] [PASSED] USB
[19:27:48] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[19:27:48] ======== drm_test_drm_connector_dynamic_init_name  =========
[19:27:48] [PASSED] Unknown
[19:27:48] [PASSED] VGA
[19:27:48] [PASSED] DVI-I
[19:27:48] [PASSED] DVI-D
[19:27:48] [PASSED] DVI-A
[19:27:48] [PASSED] Composite
[19:27:48] [PASSED] SVIDEO
[19:27:48] [PASSED] LVDS
[19:27:48] [PASSED] Component
[19:27:48] [PASSED] DIN
[19:27:48] [PASSED] DP
[19:27:48] [PASSED] HDMI-A
[19:27:48] [PASSED] HDMI-B
[19:27:48] [PASSED] TV
[19:27:48] [PASSED] eDP
[19:27:48] [PASSED] Virtual
[19:27:48] [PASSED] DSI
[19:27:48] [PASSED] DPI
[19:27:48] [PASSED] Writeback
[19:27:48] [PASSED] SPI
[19:27:48] [PASSED] USB
[19:27:48] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[19:27:48] =========== [PASSED] drm_connector_dynamic_init ============
[19:27:48] ==== drm_connector_dynamic_register_early (4 subtests) =====
[19:27:48] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[19:27:48] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[19:27:48] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[19:27:48] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[19:27:48] ====== [PASSED] drm_connector_dynamic_register_early =======
[19:27:48] ======= drm_connector_dynamic_register (7 subtests) ========
[19:27:48] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[19:27:48] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[19:27:48] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[19:27:48] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[19:27:48] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[19:27:48] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[19:27:48] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[19:27:48] ========= [PASSED] drm_connector_dynamic_register ==========
[19:27:48] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[19:27:48] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[19:27:48] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[19:27:48] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[19:27:48] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[19:27:48] ========== drm_test_get_tv_mode_from_name_valid  ===========
[19:27:48] [PASSED] NTSC
[19:27:48] [PASSED] NTSC-443
[19:27:48] [PASSED] NTSC-J
[19:27:48] [PASSED] PAL
[19:27:48] [PASSED] PAL-M
[19:27:48] [PASSED] PAL-N
[19:27:48] [PASSED] SECAM
[19:27:48] [PASSED] Mono
[19:27:48] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[19:27:48] [PASSED] drm_test_get_tv_mode_from_name_truncated
[19:27:48] ============ [PASSED] drm_get_tv_mode_from_name ============
[19:27:48] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[19:27:48] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[19:27:48] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[19:27:48] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[19:27:48] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[19:27:48] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[19:27:48] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[19:27:48] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[19:27:48] [PASSED] VIC 96
[19:27:48] [PASSED] VIC 97
[19:27:48] [PASSED] VIC 101
[19:27:48] [PASSED] VIC 102
[19:27:48] [PASSED] VIC 106
[19:27:48] [PASSED] VIC 107
[19:27:48] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[19:27:48] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[19:27:48] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[19:27:48] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[19:27:48] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[19:27:48] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[19:27:48] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[19:27:48] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[19:27:48] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[19:27:48] [PASSED] Automatic
[19:27:48] [PASSED] Full
[19:27:48] [PASSED] Limited 16:235
[19:27:48] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[19:27:48] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[19:27:48] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[19:27:48] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[19:27:48] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[19:27:48] [PASSED] RGB
[19:27:48] [PASSED] YUV 4:2:0
[19:27:48] [PASSED] YUV 4:2:2
[19:27:48] [PASSED] YUV 4:4:4
[19:27:48] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[19:27:48] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[19:27:48] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[19:27:48] ============= drm_damage_helper (21 subtests) ==============
[19:27:48] [PASSED] drm_test_damage_iter_no_damage
[19:27:48] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[19:27:48] [PASSED] drm_test_damage_iter_no_damage_src_moved
[19:27:48] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[19:27:48] [PASSED] drm_test_damage_iter_no_damage_not_visible
[19:27:48] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[19:27:48] [PASSED] drm_test_damage_iter_no_damage_no_fb
[19:27:48] [PASSED] drm_test_damage_iter_simple_damage
[19:27:48] [PASSED] drm_test_damage_iter_single_damage
[19:27:48] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[19:27:48] [PASSED] drm_test_damage_iter_single_damage_outside_src
[19:27:48] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[19:27:48] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[19:27:48] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[19:27:48] [PASSED] drm_test_damage_iter_single_damage_src_moved
[19:27:48] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[19:27:48] [PASSED] drm_test_damage_iter_damage
[19:27:48] [PASSED] drm_test_damage_iter_damage_one_intersect
[19:27:48] [PASSED] drm_test_damage_iter_damage_one_outside
[19:27:48] [PASSED] drm_test_damage_iter_damage_src_moved
[19:27:48] [PASSED] drm_test_damage_iter_damage_not_visible
[19:27:48] ================ [PASSED] drm_damage_helper ================
[19:27:48] ============== drm_dp_mst_helper (3 subtests) ==============
[19:27:48] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[19:27:48] [PASSED] Clock 154000 BPP 30 DSC disabled
[19:27:48] [PASSED] Clock 234000 BPP 30 DSC disabled
[19:27:48] [PASSED] Clock 297000 BPP 24 DSC disabled
[19:27:48] [PASSED] Clock 332880 BPP 24 DSC enabled
[19:27:48] [PASSED] Clock 324540 BPP 24 DSC enabled
[19:27:48] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[19:27:48] ============== drm_test_dp_mst_calc_pbn_div  ===============
[19:27:48] [PASSED] Link rate 2000000 lane count 4
[19:27:48] [PASSED] Link rate 2000000 lane count 2
[19:27:48] [PASSED] Link rate 2000000 lane count 1
[19:27:48] [PASSED] Link rate 1350000 lane count 4
[19:27:48] [PASSED] Link rate 1350000 lane count 2
[19:27:48] [PASSED] Link rate 1350000 lane count 1
[19:27:48] [PASSED] Link rate 1000000 lane count 4
[19:27:48] [PASSED] Link rate 1000000 lane count 2
[19:27:48] [PASSED] Link rate 1000000 lane count 1
[19:27:48] [PASSED] Link rate 810000 lane count 4
[19:27:48] [PASSED] Link rate 810000 lane count 2
[19:27:48] [PASSED] Link rate 810000 lane count 1
[19:27:48] [PASSED] Link rate 540000 lane count 4
[19:27:48] [PASSED] Link rate 540000 lane count 2
[19:27:48] [PASSED] Link rate 540000 lane count 1
[19:27:48] [PASSED] Link rate 270000 lane count 4
[19:27:48] [PASSED] Link rate 270000 lane count 2
[19:27:48] [PASSED] Link rate 270000 lane count 1
[19:27:48] [PASSED] Link rate 162000 lane count 4
[19:27:48] [PASSED] Link rate 162000 lane count 2
[19:27:48] [PASSED] Link rate 162000 lane count 1
[19:27:48] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[19:27:48] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[19:27:48] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[19:27:48] [PASSED] DP_POWER_UP_PHY with port number
[19:27:48] [PASSED] DP_POWER_DOWN_PHY with port number
[19:27:48] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[19:27:48] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[19:27:48] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[19:27:48] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[19:27:48] [PASSED] DP_QUERY_PAYLOAD with port number
[19:27:48] [PASSED] DP_QUERY_PAYLOAD with VCPI
[19:27:48] [PASSED] DP_REMOTE_DPCD_READ with port number
[19:27:48] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[19:27:48] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[19:27:48] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[19:27:48] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[19:27:48] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[19:27:48] [PASSED] DP_REMOTE_I2C_READ with port number
[19:27:48] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[19:27:48] [PASSED] DP_REMOTE_I2C_READ with transactions array
[19:27:48] [PASSED] DP_REMOTE_I2C_WRITE with port number
[19:27:48] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[19:27:48] [PASSED] DP_REMOTE_I2C_WRITE with data array
[19:27:48] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[19:27:48] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[19:27:48] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[19:27:48] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[19:27:48] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[19:27:48] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[19:27:48] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[19:27:48] ================ [PASSED] drm_dp_mst_helper ================
[19:27:48] ================== drm_exec (7 subtests) ===================
[19:27:48] [PASSED] sanitycheck
[19:27:48] [PASSED] test_lock
[19:27:48] [PASSED] test_lock_unlock
[19:27:48] [PASSED] test_duplicates
[19:27:48] [PASSED] test_prepare
[19:27:48] [PASSED] test_prepare_array
[19:27:48] [PASSED] test_multiple_loops
[19:27:48] ==================== [PASSED] drm_exec =====================
[19:27:48] =========== drm_format_helper_test (17 subtests) ===========
[19:27:48] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[19:27:48] [PASSED] single_pixel_source_buffer
[19:27:48] [PASSED] single_pixel_clip_rectangle
[19:27:48] [PASSED] well_known_colors
[19:27:48] [PASSED] destination_pitch
[19:27:48] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[19:27:48] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[19:27:48] [PASSED] single_pixel_source_buffer
[19:27:48] [PASSED] single_pixel_clip_rectangle
[19:27:48] [PASSED] well_known_colors
[19:27:48] [PASSED] destination_pitch
[19:27:48] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[19:27:48] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[19:27:48] [PASSED] single_pixel_source_buffer
[19:27:48] [PASSED] single_pixel_clip_rectangle
[19:27:48] [PASSED] well_known_colors
[19:27:48] [PASSED] destination_pitch
[19:27:48] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[19:27:48] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[19:27:48] [PASSED] single_pixel_source_buffer
[19:27:48] [PASSED] single_pixel_clip_rectangle
[19:27:48] [PASSED] well_known_colors
[19:27:48] [PASSED] destination_pitch
[19:27:48] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[19:27:48] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[19:27:48] [PASSED] single_pixel_source_buffer
[19:27:48] [PASSED] single_pixel_clip_rectangle
[19:27:48] [PASSED] well_known_colors
[19:27:48] [PASSED] destination_pitch
[19:27:48] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[19:27:48] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[19:27:48] [PASSED] single_pixel_source_buffer
[19:27:48] [PASSED] single_pixel_clip_rectangle
[19:27:48] [PASSED] well_known_colors
[19:27:48] [PASSED] destination_pitch
[19:27:48] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[19:27:48] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[19:27:48] [PASSED] single_pixel_source_buffer
[19:27:48] [PASSED] single_pixel_clip_rectangle
[19:27:48] [PASSED] well_known_colors
[19:27:48] [PASSED] destination_pitch
[19:27:48] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[19:27:48] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[19:27:48] [PASSED] single_pixel_source_buffer
[19:27:48] [PASSED] single_pixel_clip_rectangle
[19:27:48] [PASSED] well_known_colors
[19:27:48] [PASSED] destination_pitch
[19:27:48] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[19:27:48] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[19:27:48] [PASSED] single_pixel_source_buffer
[19:27:48] [PASSED] single_pixel_clip_rectangle
[19:27:48] [PASSED] well_known_colors
[19:27:48] [PASSED] destination_pitch
[19:27:48] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[19:27:48] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[19:27:48] [PASSED] single_pixel_source_buffer
[19:27:48] [PASSED] single_pixel_clip_rectangle
[19:27:48] [PASSED] well_known_colors
[19:27:48] [PASSED] destination_pitch
[19:27:48] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[19:27:48] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[19:27:48] [PASSED] single_pixel_source_buffer
[19:27:48] [PASSED] single_pixel_clip_rectangle
[19:27:48] [PASSED] well_known_colors
[19:27:48] [PASSED] destination_pitch
[19:27:48] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[19:27:48] ============== drm_test_fb_xrgb8888_to_mono  ===============
[19:27:48] [PASSED] single_pixel_source_buffer
[19:27:48] [PASSED] single_pixel_clip_rectangle
[19:27:48] [PASSED] well_known_colors
[19:27:48] [PASSED] destination_pitch
[19:27:48] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[19:27:48] ==================== drm_test_fb_swab  =====================
[19:27:48] [PASSED] single_pixel_source_buffer
[19:27:48] [PASSED] single_pixel_clip_rectangle
[19:27:48] [PASSED] well_known_colors
[19:27:48] [PASSED] destination_pitch
[19:27:48] ================ [PASSED] drm_test_fb_swab =================
[19:27:48] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[19:27:48] [PASSED] single_pixel_source_buffer
[19:27:48] [PASSED] single_pixel_clip_rectangle
[19:27:48] [PASSED] well_known_colors
[19:27:48] [PASSED] destination_pitch
[19:27:48] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[19:27:48] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[19:27:48] [PASSED] single_pixel_source_buffer
[19:27:48] [PASSED] single_pixel_clip_rectangle
[19:27:48] [PASSED] well_known_colors
[19:27:48] [PASSED] destination_pitch
[19:27:48] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[19:27:48] ================= drm_test_fb_clip_offset  =================
[19:27:48] [PASSED] pass through
[19:27:48] [PASSED] horizontal offset
[19:27:48] [PASSED] vertical offset
[19:27:48] [PASSED] horizontal and vertical offset
[19:27:48] [PASSED] horizontal offset (custom pitch)
[19:27:48] [PASSED] vertical offset (custom pitch)
[19:27:48] [PASSED] horizontal and vertical offset (custom pitch)
[19:27:48] ============= [PASSED] drm_test_fb_clip_offset =============
[19:27:48] =================== drm_test_fb_memcpy  ====================
[19:27:48] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[19:27:48] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[19:27:48] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[19:27:48] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[19:27:48] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[19:27:48] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[19:27:48] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[19:27:48] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[19:27:48] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[19:27:48] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[19:27:48] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[19:27:48] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[19:27:48] =============== [PASSED] drm_test_fb_memcpy ================
[19:27:48] ============= [PASSED] drm_format_helper_test ==============
[19:27:48] ================= drm_format (18 subtests) =================
[19:27:48] [PASSED] drm_test_format_block_width_invalid
[19:27:48] [PASSED] drm_test_format_block_width_one_plane
[19:27:48] [PASSED] drm_test_format_block_width_two_plane
[19:27:48] [PASSED] drm_test_format_block_width_three_plane
[19:27:48] [PASSED] drm_test_format_block_width_tiled
[19:27:48] [PASSED] drm_test_format_block_height_invalid
[19:27:48] [PASSED] drm_test_format_block_height_one_plane
[19:27:48] [PASSED] drm_test_format_block_height_two_plane
[19:27:48] [PASSED] drm_test_format_block_height_three_plane
[19:27:48] [PASSED] drm_test_format_block_height_tiled
[19:27:48] [PASSED] drm_test_format_min_pitch_invalid
[19:27:48] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[19:27:48] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[19:27:48] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[19:27:48] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[19:27:48] [PASSED] drm_test_format_min_pitch_two_plane
[19:27:48] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[19:27:48] [PASSED] drm_test_format_min_pitch_tiled
[19:27:48] =================== [PASSED] drm_format ====================
[19:27:48] ============== drm_framebuffer (10 subtests) ===============
[19:27:48] ========== drm_test_framebuffer_check_src_coords  ==========
[19:27:48] [PASSED] Success: source fits into fb
[19:27:48] [PASSED] Fail: overflowing fb with x-axis coordinate
[19:27:48] [PASSED] Fail: overflowing fb with y-axis coordinate
[19:27:48] [PASSED] Fail: overflowing fb with source width
[19:27:48] [PASSED] Fail: overflowing fb with source height
[19:27:48] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[19:27:48] [PASSED] drm_test_framebuffer_cleanup
[19:27:48] =============== drm_test_framebuffer_create  ===============
[19:27:48] [PASSED] ABGR8888 normal sizes
[19:27:48] [PASSED] ABGR8888 max sizes
[19:27:48] [PASSED] ABGR8888 pitch greater than min required
[19:27:48] [PASSED] ABGR8888 pitch less than min required
[19:27:48] [PASSED] ABGR8888 Invalid width
[19:27:48] [PASSED] ABGR8888 Invalid buffer handle
[19:27:48] [PASSED] No pixel format
[19:27:48] [PASSED] ABGR8888 Width 0
[19:27:48] [PASSED] ABGR8888 Height 0
[19:27:48] [PASSED] ABGR8888 Out of bound height * pitch combination
[19:27:48] [PASSED] ABGR8888 Large buffer offset
[19:27:48] [PASSED] ABGR8888 Buffer offset for inexistent plane
[19:27:48] [PASSED] ABGR8888 Invalid flag
[19:27:48] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[19:27:48] [PASSED] ABGR8888 Valid buffer modifier
[19:27:48] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[19:27:48] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[19:27:48] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[19:27:48] [PASSED] NV12 Normal sizes
[19:27:48] [PASSED] NV12 Max sizes
[19:27:48] [PASSED] NV12 Invalid pitch
[19:27:48] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[19:27:48] [PASSED] NV12 different  modifier per-plane
[19:27:48] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[19:27:48] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[19:27:48] [PASSED] NV12 Modifier for inexistent plane
[19:27:48] [PASSED] NV12 Handle for inexistent plane
[19:27:48] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[19:27:48] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[19:27:48] [PASSED] YVU420 Normal sizes
[19:27:48] [PASSED] YVU420 Max sizes
[19:27:48] [PASSED] YVU420 Invalid pitch
[19:27:48] [PASSED] YVU420 Different pitches
[19:27:48] [PASSED] YVU420 Different buffer offsets/pitches
[19:27:48] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[19:27:48] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[19:27:48] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[19:27:48] [PASSED] YVU420 Valid modifier
[19:27:48] [PASSED] YVU420 Different modifiers per plane
[19:27:48] [PASSED] YVU420 Modifier for inexistent plane
[19:27:48] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[19:27:48] [PASSED] X0L2 Normal sizes
[19:27:48] [PASSED] X0L2 Max sizes
[19:27:48] [PASSED] X0L2 Invalid pitch
[19:27:48] [PASSED] X0L2 Pitch greater than minimum required
[19:27:48] [PASSED] X0L2 Handle for inexistent plane
[19:27:48] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[19:27:48] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[19:27:48] [PASSED] X0L2 Valid modifier
[19:27:48] [PASSED] X0L2 Modifier for inexistent plane
[19:27:48] =========== [PASSED] drm_test_framebuffer_create ===========
[19:27:48] [PASSED] drm_test_framebuffer_free
[19:27:48] [PASSED] drm_test_framebuffer_init
[19:27:48] [PASSED] drm_test_framebuffer_init_bad_format
[19:27:48] [PASSED] drm_test_framebuffer_init_dev_mismatch
[19:27:48] [PASSED] drm_test_framebuffer_lookup
[19:27:48] [PASSED] drm_test_framebuffer_lookup_inexistent
[19:27:48] [PASSED] drm_test_framebuffer_modifiers_not_supported
[19:27:48] ================= [PASSED] drm_framebuffer =================
[19:27:48] ================ drm_gem_shmem (8 subtests) ================
[19:27:48] [PASSED] drm_gem_shmem_test_obj_create
[19:27:48] [PASSED] drm_gem_shmem_test_obj_create_private
[19:27:48] [PASSED] drm_gem_shmem_test_pin_pages
[19:27:48] [PASSED] drm_gem_shmem_test_vmap
[19:27:48] [PASSED] drm_gem_shmem_test_get_pages_sgt
[19:27:48] [PASSED] drm_gem_shmem_test_get_sg_table
[19:27:48] [PASSED] drm_gem_shmem_test_madvise
[19:27:48] [PASSED] drm_gem_shmem_test_purge
[19:27:48] ================== [PASSED] drm_gem_shmem ==================
[19:27:48] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[19:27:48] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[19:27:48] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[19:27:48] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[19:27:48] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[19:27:48] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[19:27:48] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[19:27:48] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[19:27:48] [PASSED] Automatic
[19:27:48] [PASSED] Full
[19:27:48] [PASSED] Limited 16:235
[19:27:48] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[19:27:48] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[19:27:48] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[19:27:48] [PASSED] drm_test_check_disable_connector
[19:27:48] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[19:27:48] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[19:27:48] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[19:27:48] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[19:27:48] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[19:27:48] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[19:27:48] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[19:27:48] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[19:27:48] [PASSED] drm_test_check_output_bpc_dvi
[19:27:48] [PASSED] drm_test_check_output_bpc_format_vic_1
[19:27:48] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[19:27:48] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[19:27:48] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[19:27:48] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[19:27:48] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[19:27:48] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[19:27:48] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[19:27:48] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[19:27:48] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[19:27:48] [PASSED] drm_test_check_broadcast_rgb_value
[19:27:48] [PASSED] drm_test_check_bpc_8_value
[19:27:48] [PASSED] drm_test_check_bpc_10_value
[19:27:48] [PASSED] drm_test_check_bpc_12_value
[19:27:48] [PASSED] drm_test_check_format_value
[19:27:48] [PASSED] drm_test_check_tmds_char_value
[19:27:48] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[19:27:48] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[19:27:48] [PASSED] drm_test_check_mode_valid
[19:27:48] [PASSED] drm_test_check_mode_valid_reject
[19:27:48] [PASSED] drm_test_check_mode_valid_reject_rate
[19:27:48] [PASSED] drm_test_check_mode_valid_reject_max_clock
[19:27:48] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[19:27:48] ================= drm_managed (2 subtests) =================
[19:27:48] [PASSED] drm_test_managed_release_action
[19:27:48] [PASSED] drm_test_managed_run_action
[19:27:48] =================== [PASSED] drm_managed ===================
[19:27:48] =================== drm_mm (6 subtests) ====================
[19:27:48] [PASSED] drm_test_mm_init
[19:27:48] [PASSED] drm_test_mm_debug
[19:27:48] [PASSED] drm_test_mm_align32
[19:27:48] [PASSED] drm_test_mm_align64
[19:27:48] [PASSED] drm_test_mm_lowest
[19:27:48] [PASSED] drm_test_mm_highest
[19:27:48] ===================== [PASSED] drm_mm ======================
[19:27:48] ============= drm_modes_analog_tv (5 subtests) =============
[19:27:48] [PASSED] drm_test_modes_analog_tv_mono_576i
[19:27:48] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[19:27:48] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[19:27:48] [PASSED] drm_test_modes_analog_tv_pal_576i
[19:27:48] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[19:27:48] =============== [PASSED] drm_modes_analog_tv ===============
[19:27:48] ============== drm_plane_helper (2 subtests) ===============
[19:27:48] =============== drm_test_check_plane_state  ================
[19:27:48] [PASSED] clipping_simple
[19:27:48] [PASSED] clipping_rotate_reflect
[19:27:48] [PASSED] positioning_simple
[19:27:48] [PASSED] upscaling
[19:27:48] [PASSED] downscaling
[19:27:48] [PASSED] rounding1
[19:27:48] [PASSED] rounding2
[19:27:48] [PASSED] rounding3
[19:27:48] [PASSED] rounding4
[19:27:48] =========== [PASSED] drm_test_check_plane_state ============
[19:27:48] =========== drm_test_check_invalid_plane_state  ============
[19:27:48] [PASSED] positioning_invalid
[19:27:48] [PASSED] upscaling_invalid
[19:27:48] [PASSED] downscaling_invalid
[19:27:48] ======= [PASSED] drm_test_check_invalid_plane_state ========
[19:27:48] ================ [PASSED] drm_plane_helper =================
[19:27:48] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[19:27:48] ====== drm_test_connector_helper_tv_get_modes_check  =======
[19:27:48] [PASSED] None
[19:27:48] [PASSED] PAL
[19:27:48] [PASSED] NTSC
[19:27:48] [PASSED] Both, NTSC Default
[19:27:48] [PASSED] Both, PAL Default
[19:27:48] [PASSED] Both, NTSC Default, with PAL on command-line
[19:27:48] [PASSED] Both, PAL Default, with NTSC on command-line
[19:27:48] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[19:27:48] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[19:27:48] ================== drm_rect (9 subtests) ===================
[19:27:48] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[19:27:48] [PASSED] drm_test_rect_clip_scaled_not_clipped
[19:27:48] [PASSED] drm_test_rect_clip_scaled_clipped
[19:27:48] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[19:27:48] ================= drm_test_rect_intersect  =================
[19:27:48] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[19:27:48] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[19:27:48] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[19:27:48] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[19:27:48] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[19:27:48] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[19:27:48] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[19:27:48] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[19:27:48] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[19:27:48] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[19:27:48] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[19:27:48] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[19:27:48] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[19:27:48] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[19:27:48] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[19:27:48] ============= [PASSED] drm_test_rect_intersect =============
[19:27:48] ================ drm_test_rect_calc_hscale  ================
[19:27:48] [PASSED] normal use
[19:27:48] [PASSED] out of max range
[19:27:48] [PASSED] out of min range
[19:27:48] [PASSED] zero dst
[19:27:48] [PASSED] negative src
[19:27:48] [PASSED] negative dst
[19:27:48] ============ [PASSED] drm_test_rect_calc_hscale ============
[19:27:48] ================ drm_test_rect_calc_vscale  ================
[19:27:48] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[19:27:48] [PASSED] out of max range
[19:27:48] [PASSED] out of min range
[19:27:48] [PASSED] zero dst
[19:27:48] [PASSED] negative src
[19:27:48] [PASSED] negative dst
[19:27:48] ============ [PASSED] drm_test_rect_calc_vscale ============
[19:27:48] ================== drm_test_rect_rotate  ===================
[19:27:48] [PASSED] reflect-x
[19:27:48] [PASSED] reflect-y
[19:27:48] [PASSED] rotate-0
[19:27:48] [PASSED] rotate-90
[19:27:48] [PASSED] rotate-180
[19:27:48] [PASSED] rotate-270
[19:27:48] ============== [PASSED] drm_test_rect_rotate ===============
[19:27:48] ================ drm_test_rect_rotate_inv  =================
[19:27:48] [PASSED] reflect-x
[19:27:48] [PASSED] reflect-y
[19:27:48] [PASSED] rotate-0
[19:27:48] [PASSED] rotate-90
[19:27:48] [PASSED] rotate-180
[19:27:48] [PASSED] rotate-270
[19:27:48] ============ [PASSED] drm_test_rect_rotate_inv =============
[19:27:48] ==================== [PASSED] drm_rect =====================
[19:27:48] ============ drm_sysfb_modeset_test (1 subtest) ============
[19:27:48] ============ drm_test_sysfb_build_fourcc_list  =============
[19:27:48] [PASSED] no native formats
[19:27:48] [PASSED] XRGB8888 as native format
[19:27:48] [PASSED] remove duplicates
[19:27:48] [PASSED] convert alpha formats
[19:27:48] [PASSED] random formats
[19:27:48] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[19:27:48] ============= [PASSED] drm_sysfb_modeset_test ==============
[19:27:48] ================== drm_fixp (2 subtests) ===================
[19:27:48] [PASSED] drm_test_int2fixp
[19:27:48] [PASSED] drm_test_sm2fixp
[19:27:48] ==================== [PASSED] drm_fixp =====================
[19:27:48] ============================================================
[19:27:48] Testing complete. Ran 624 tests: passed: 624
[19:27:48] Elapsed time: 27.233s total, 1.665s configuring, 25.148s building, 0.382s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[19:27:49] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[19:27:50] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[19:28:00] Starting KUnit Kernel (1/1)...
[19:28:00] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[19:28:00] ================= ttm_device (5 subtests) ==================
[19:28:00] [PASSED] ttm_device_init_basic
[19:28:00] [PASSED] ttm_device_init_multiple
[19:28:00] [PASSED] ttm_device_fini_basic
[19:28:00] [PASSED] ttm_device_init_no_vma_man
[19:28:00] ================== ttm_device_init_pools  ==================
[19:28:00] [PASSED] No DMA allocations, no DMA32 required
[19:28:00] [PASSED] DMA allocations, DMA32 required
[19:28:00] [PASSED] No DMA allocations, DMA32 required
[19:28:00] [PASSED] DMA allocations, no DMA32 required
[19:28:00] ============== [PASSED] ttm_device_init_pools ==============
[19:28:00] =================== [PASSED] ttm_device ====================
[19:28:00] ================== ttm_pool (8 subtests) ===================
[19:28:00] ================== ttm_pool_alloc_basic  ===================
[19:28:00] [PASSED] One page
[19:28:00] [PASSED] More than one page
[19:28:00] [PASSED] Above the allocation limit
[19:28:00] [PASSED] One page, with coherent DMA mappings enabled
[19:28:00] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[19:28:00] ============== [PASSED] ttm_pool_alloc_basic ===============
[19:28:00] ============== ttm_pool_alloc_basic_dma_addr  ==============
[19:28:00] [PASSED] One page
[19:28:00] [PASSED] More than one page
[19:28:00] [PASSED] Above the allocation limit
[19:28:00] [PASSED] One page, with coherent DMA mappings enabled
[19:28:00] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[19:28:00] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[19:28:00] [PASSED] ttm_pool_alloc_order_caching_match
[19:28:00] [PASSED] ttm_pool_alloc_caching_mismatch
[19:28:00] [PASSED] ttm_pool_alloc_order_mismatch
[19:28:00] [PASSED] ttm_pool_free_dma_alloc
[19:28:00] [PASSED] ttm_pool_free_no_dma_alloc
[19:28:00] [PASSED] ttm_pool_fini_basic
[19:28:00] ==================== [PASSED] ttm_pool =====================
[19:28:00] ================ ttm_resource (8 subtests) =================
[19:28:00] ================= ttm_resource_init_basic  =================
[19:28:00] [PASSED] Init resource in TTM_PL_SYSTEM
[19:28:00] [PASSED] Init resource in TTM_PL_VRAM
[19:28:00] [PASSED] Init resource in a private placement
[19:28:00] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[19:28:00] ============= [PASSED] ttm_resource_init_basic =============
[19:28:00] [PASSED] ttm_resource_init_pinned
[19:28:00] [PASSED] ttm_resource_fini_basic
[19:28:00] [PASSED] ttm_resource_manager_init_basic
[19:28:00] [PASSED] ttm_resource_manager_usage_basic
[19:28:00] [PASSED] ttm_resource_manager_set_used_basic
[19:28:00] [PASSED] ttm_sys_man_alloc_basic
[19:28:00] [PASSED] ttm_sys_man_free_basic
[19:28:00] ================== [PASSED] ttm_resource ===================
[19:28:00] =================== ttm_tt (15 subtests) ===================
[19:28:00] ==================== ttm_tt_init_basic  ====================
[19:28:00] [PASSED] Page-aligned size
[19:28:00] [PASSED] Extra pages requested
[19:28:00] ================ [PASSED] ttm_tt_init_basic ================
[19:28:00] [PASSED] ttm_tt_init_misaligned
[19:28:00] [PASSED] ttm_tt_fini_basic
[19:28:00] [PASSED] ttm_tt_fini_sg
[19:28:00] [PASSED] ttm_tt_fini_shmem
[19:28:00] [PASSED] ttm_tt_create_basic
[19:28:00] [PASSED] ttm_tt_create_invalid_bo_type
[19:28:00] [PASSED] ttm_tt_create_ttm_exists
[19:28:00] [PASSED] ttm_tt_create_failed
[19:28:00] [PASSED] ttm_tt_destroy_basic
[19:28:00] [PASSED] ttm_tt_populate_null_ttm
[19:28:00] [PASSED] ttm_tt_populate_populated_ttm
[19:28:00] [PASSED] ttm_tt_unpopulate_basic
[19:28:00] [PASSED] ttm_tt_unpopulate_empty_ttm
[19:28:00] [PASSED] ttm_tt_swapin_basic
[19:28:00] ===================== [PASSED] ttm_tt ======================
[19:28:00] =================== ttm_bo (14 subtests) ===================
[19:28:00] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[19:28:00] [PASSED] Cannot be interrupted and sleeps
[19:28:00] [PASSED] Cannot be interrupted, locks straight away
[19:28:00] [PASSED] Can be interrupted, sleeps
[19:28:00] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[19:28:00] [PASSED] ttm_bo_reserve_locked_no_sleep
[19:28:00] [PASSED] ttm_bo_reserve_no_wait_ticket
[19:28:00] [PASSED] ttm_bo_reserve_double_resv
[19:28:00] [PASSED] ttm_bo_reserve_interrupted
[19:28:00] [PASSED] ttm_bo_reserve_deadlock
[19:28:00] [PASSED] ttm_bo_unreserve_basic
[19:28:00] [PASSED] ttm_bo_unreserve_pinned
[19:28:00] [PASSED] ttm_bo_unreserve_bulk
[19:28:00] [PASSED] ttm_bo_fini_basic
[19:28:00] [PASSED] ttm_bo_fini_shared_resv
[19:28:00] [PASSED] ttm_bo_pin_basic
[19:28:00] [PASSED] ttm_bo_pin_unpin_resource
[19:28:00] [PASSED] ttm_bo_multiple_pin_one_unpin
[19:28:00] ===================== [PASSED] ttm_bo ======================
[19:28:00] ============== ttm_bo_validate (21 subtests) ===============
[19:28:00] ============== ttm_bo_init_reserved_sys_man  ===============
[19:28:00] [PASSED] Buffer object for userspace
[19:28:00] [PASSED] Kernel buffer object
[19:28:00] [PASSED] Shared buffer object
[19:28:00] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[19:28:00] ============== ttm_bo_init_reserved_mock_man  ==============
[19:28:00] [PASSED] Buffer object for userspace
[19:28:00] [PASSED] Kernel buffer object
[19:28:00] [PASSED] Shared buffer object
[19:28:00] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[19:28:00] [PASSED] ttm_bo_init_reserved_resv
[19:28:00] ================== ttm_bo_validate_basic  ==================
[19:28:00] [PASSED] Buffer object for userspace
[19:28:00] [PASSED] Kernel buffer object
[19:28:00] [PASSED] Shared buffer object
[19:28:00] ============== [PASSED] ttm_bo_validate_basic ==============
[19:28:00] [PASSED] ttm_bo_validate_invalid_placement
[19:28:00] ============= ttm_bo_validate_same_placement  ==============
[19:28:00] [PASSED] System manager
[19:28:00] [PASSED] VRAM manager
[19:28:00] ========= [PASSED] ttm_bo_validate_same_placement ==========
[19:28:00] [PASSED] ttm_bo_validate_failed_alloc
[19:28:00] [PASSED] ttm_bo_validate_pinned
[19:28:00] [PASSED] ttm_bo_validate_busy_placement
[19:28:00] ================ ttm_bo_validate_multihop  =================
[19:28:00] [PASSED] Buffer object for userspace
[19:28:00] [PASSED] Kernel buffer object
[19:28:00] [PASSED] Shared buffer object
[19:28:00] ============ [PASSED] ttm_bo_validate_multihop =============
[19:28:00] ========== ttm_bo_validate_no_placement_signaled  ==========
[19:28:00] [PASSED] Buffer object in system domain, no page vector
[19:28:00] [PASSED] Buffer object in system domain with an existing page vector
[19:28:00] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[19:28:00] ======== ttm_bo_validate_no_placement_not_signaled  ========
[19:28:00] [PASSED] Buffer object for userspace
[19:28:00] [PASSED] Kernel buffer object
[19:28:00] [PASSED] Shared buffer object
[19:28:00] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[19:28:00] [PASSED] ttm_bo_validate_move_fence_signaled
[19:28:00] ========= ttm_bo_validate_move_fence_not_signaled  =========
[19:28:00] [PASSED] Waits for GPU
[19:28:00] [PASSED] Tries to lock straight away
[19:28:00] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[19:28:00] [PASSED] ttm_bo_validate_happy_evict
[19:28:00] [PASSED] ttm_bo_validate_all_pinned_evict
[19:28:00] [PASSED] ttm_bo_validate_allowed_only_evict
[19:28:00] [PASSED] ttm_bo_validate_deleted_evict
[19:28:00] [PASSED] ttm_bo_validate_busy_domain_evict
[19:28:00] [PASSED] ttm_bo_validate_evict_gutting
[19:28:00] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[19:28:00] ================= [PASSED] ttm_bo_validate =================
[19:28:00] ============================================================
[19:28:00] Testing complete. Ran 101 tests: passed: 101
[19:28:00] Elapsed time: 11.240s total, 1.606s configuring, 9.418s building, 0.184s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for drm/xe/hwmon: Expose new temperature attributes (rev4)

[Patchwork]

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== Series Details ==

Series: drm/xe/hwmon: Expose new temperature attributes (rev4)
URL   : https://patchwork.freedesktop.org/series/158384/
State : success

== Summary ==

CI Bug Log - changes from xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41_BAT -> xe-pw-158384v4_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (12 -> 12)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * Linux: xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41 -> xe-pw-158384v4

  IGT_8668: 906681747a312ef11ef9af8ab1fa6eff28b4cbd0 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41: 72428bdb20b6c86beaeddb9d69bf698d0697aa41
  xe-pw-158384v4: 158384v4

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/index.html

[-- Attachment #2: Type: text/html, Size: 1516 bytes --]

✗ Xe.CI.Full: failure for drm/xe/hwmon: Expose new temperature attributes (rev4)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 85042 bytes --]

== Series Details ==

Series: drm/xe/hwmon: Expose new temperature attributes (rev4)
URL   : https://patchwork.freedesktop.org/series/158384/
State : failure

== Summary ==

CI Bug Log - changes from xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41_FULL -> xe-pw-158384v4_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-158384v4_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-158384v4_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-158384v4_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@core_setmaster@master-drop-set-shared-fd:
    - shard-bmg:          [PASS][1] -> [SKIP][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-7/igt@core_setmaster@master-drop-set-shared-fd.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@core_setmaster@master-drop-set-shared-fd.html

  * igt@kms_plane_cursor@overlay@pipe-d-hdmi-a-3-size-256:
    - shard-bmg:          [PASS][3] -> [FAIL][4] +1 other test fail
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-2/igt@kms_plane_cursor@overlay@pipe-d-hdmi-a-3-size-256.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-2/igt@kms_plane_cursor@overlay@pipe-d-hdmi-a-3-size-256.html

  
Known issues
------------

  Here are the changes found in xe-pw-158384v4_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_hotunplug@hotrebind-lateclose:
    - shard-bmg:          [PASS][5] -> [SKIP][6] ([Intel XE#6779])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-1/igt@core_hotunplug@hotrebind-lateclose.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@core_hotunplug@hotrebind-lateclose.html

  * igt@core_hotunplug@unbind-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][7] ([Intel XE#6779])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@core_hotunplug@unbind-rebind.html

  * igt@fbdev@eof:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#2134])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@fbdev@eof.html

  * igt@intel_hwmon@hwmon-read:
    - shard-bmg:          [PASS][9] -> [SKIP][10] ([Intel XE#5177] / [Intel XE#6703])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-3/igt@intel_hwmon@hwmon-read.html
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@intel_hwmon@hwmon-read.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-270:
    - shard-bmg:          NOTRUN -> [SKIP][11] ([Intel XE#2327])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-3/igt@kms_big_fb@4-tiled-32bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-addfb-size-overflow:
    - shard-bmg:          NOTRUN -> [SKIP][12] ([Intel XE#610])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-3/igt@kms_big_fb@y-tiled-addfb-size-overflow.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180:
    - shard-bmg:          NOTRUN -> [SKIP][13] ([Intel XE#1124]) +4 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-3/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180.html

  * igt@kms_bw@linear-tiling-4-displays-2560x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][14] ([Intel XE#367])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-3/igt@kms_bw@linear-tiling-4-displays-2560x1440p.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs@pipe-c-dp-2:
    - shard-bmg:          NOTRUN -> [SKIP][15] ([Intel XE#2652] / [Intel XE#787]) +8 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-3/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs@pipe-c-dp-2.html

  * igt@kms_ccs@bad-rotation-90-y-tiled-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][16] ([Intel XE#2887]) +4 other tests skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-2/igt@kms_ccs@bad-rotation-90-y-tiled-ccs.html

  * igt@kms_chamelium_color@degamma:
    - shard-bmg:          NOTRUN -> [SKIP][17] ([Intel XE#2325])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-3/igt@kms_chamelium_color@degamma.html

  * igt@kms_chamelium_edid@hdmi-edid-read:
    - shard-bmg:          NOTRUN -> [SKIP][18] ([Intel XE#2252]) +3 other tests skip
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-3/igt@kms_chamelium_edid@hdmi-edid-read.html

  * igt@kms_cursor_crc@cursor-random-32x10:
    - shard-bmg:          NOTRUN -> [SKIP][19] ([Intel XE#2320])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-3/igt@kms_cursor_crc@cursor-random-32x10.html

  * igt@kms_cursor_crc@cursor-rapid-movement-512x512:
    - shard-bmg:          NOTRUN -> [SKIP][20] ([Intel XE#2321])
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-3/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions:
    - shard-bmg:          [PASS][21] -> [SKIP][22] ([Intel XE#2291])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-8/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions.html
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-2/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions.html

  * igt@kms_fbcon_fbt@fbc:
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#4156])
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-3/igt@kms_fbcon_fbt@fbc.html

  * igt@kms_flip@2x-modeset-vs-vblank-race-interruptible:
    - shard-bmg:          [PASS][24] -> [SKIP][25] ([Intel XE#2316]) +1 other test skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-8/igt@kms_flip@2x-modeset-vs-vblank-race-interruptible.html
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-2/igt@kms_flip@2x-modeset-vs-vblank-race-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
    - shard-lnl:          [PASS][26] -> [FAIL][27] ([Intel XE#301]) +1 other test fail
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling:
    - shard-bmg:          NOTRUN -> [SKIP][28] ([Intel XE#2293] / [Intel XE#2380]) +1 other test skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-3/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling@pipe-a-valid-mode:
    - shard-bmg:          NOTRUN -> [SKIP][29] ([Intel XE#2293]) +5 other tests skip
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-8/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-shrfb-pgflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][30] ([Intel XE#2311]) +9 other tests skip
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-3/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][31] ([Intel XE#2312]) +1 other test skip
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][32] ([Intel XE#4141]) +3 other tests skip
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][33] ([Intel XE#6703]) +203 other tests skip
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][34] ([Intel XE#6557] / [Intel XE#6703]) +2 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcdrrs-suspend.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][35] ([Intel XE#2313]) +12 other tests skip
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt.html

  * igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [ABORT][36] ([Intel XE#6740]) +1 other test abort
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-3/igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-2.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-b:
    - shard-bmg:          NOTRUN -> [SKIP][37] ([Intel XE#6886]) +3 other tests skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-7/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-b.html

  * igt@kms_pm_rpm@system-suspend-modeset:
    - shard-bmg:          [PASS][38] -> [SKIP][39] ([Intel XE#6693]) +2 other tests skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-7/igt@kms_pm_rpm@system-suspend-modeset.html
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_pm_rpm@system-suspend-modeset.html

  * igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-fully-sf:
    - shard-bmg:          NOTRUN -> [SKIP][40] ([Intel XE#1406] / [Intel XE#1489]) +3 other tests skip
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-3/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr@pr-no-drrs:
    - shard-bmg:          NOTRUN -> [SKIP][41] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +2 other tests skip
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-3/igt@kms_psr@pr-no-drrs.html

  * igt@kms_psr@psr-basic:
    - shard-bmg:          NOTRUN -> [SKIP][42] ([Intel XE#1406] / [Intel XE#6703]) +4 other tests skip
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_psr@psr-basic.html

  * igt@kms_psr@psr2-primary-render:
    - shard-bmg:          NOTRUN -> [SKIP][43] ([Intel XE#1406] / [Intel XE#2234])
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-3/igt@kms_psr@psr2-primary-render.html

  * igt@kms_setmode@invalid-clone-single-crtc-stealing:
    - shard-bmg:          [PASS][44] -> [SKIP][45] ([Intel XE#1435])
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-8/igt@kms_setmode@invalid-clone-single-crtc-stealing.html
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-2/igt@kms_setmode@invalid-clone-single-crtc-stealing.html

  * igt@kms_sharpness_filter@filter-scaler-downscale:
    - shard-bmg:          NOTRUN -> [SKIP][46] ([Intel XE#6503])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-3/igt@kms_sharpness_filter@filter-scaler-downscale.html

  * igt@kms_vrr@flip-basic-fastset:
    - shard-bmg:          NOTRUN -> [SKIP][47] ([Intel XE#1499])
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-2/igt@kms_vrr@flip-basic-fastset.html

  * igt@kms_vrr@lobf:
    - shard-bmg:          NOTRUN -> [SKIP][48] ([Intel XE#2168])
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-3/igt@kms_vrr@lobf.html

  * igt@xe_create@invalid-pad:
    - shard-bmg:          [PASS][49] -> [SKIP][50] ([Intel XE#6557] / [Intel XE#6703]) +7 other tests skip
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-3/igt@xe_create@invalid-pad.html
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@xe_create@invalid-pad.html

  * igt@xe_eudebug@basic-vm-access-parameters:
    - shard-bmg:          NOTRUN -> [SKIP][51] ([Intel XE#4837]) +1 other test skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-3/igt@xe_eudebug@basic-vm-access-parameters.html

  * igt@xe_eudebug_online@resume-one:
    - shard-bmg:          NOTRUN -> [SKIP][52] ([Intel XE#4837] / [Intel XE#6665])
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-3/igt@xe_eudebug_online@resume-one.html

  * igt@xe_eudebug_sriov@deny-sriov:
    - shard-bmg:          NOTRUN -> [SKIP][53] ([Intel XE#5793])
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-3/igt@xe_eudebug_sriov@deny-sriov.html

  * igt@xe_exec_basic@many-bindexecqueue-rebind:
    - shard-bmg:          [PASS][54] -> [SKIP][55] ([Intel XE#6703]) +575 other tests skip
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-1/igt@xe_exec_basic@many-bindexecqueue-rebind.html
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@xe_exec_basic@many-bindexecqueue-rebind.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][56] ([Intel XE#2322]) +4 other tests skip
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-2/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-rebind.html

  * igt@xe_exec_multi_queue@max-queues-basic:
    - shard-bmg:          NOTRUN -> [SKIP][57] ([Intel XE#6874]) +9 other tests skip
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-3/igt@xe_exec_multi_queue@max-queues-basic.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-mmap-free-huge-nomemset:
    - shard-bmg:          NOTRUN -> [SKIP][58] ([Intel XE#4943]) +5 other tests skip
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-3/igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-mmap-free-huge-nomemset.html

  * igt@xe_live_ktest@xe_bo:
    - shard-bmg:          [PASS][59] -> [SKIP][60] ([Intel XE#2229]) +2 other tests skip
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-3/igt@xe_live_ktest@xe_bo.html
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@xe_live_ktest@xe_bo.html

  * igt@xe_oa@oa-tlb-invalidate:
    - shard-bmg:          NOTRUN -> [SKIP][61] ([Intel XE#2248])
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-3/igt@xe_oa@oa-tlb-invalidate.html

  * igt@xe_pm@vram-d3cold-threshold:
    - shard-bmg:          NOTRUN -> [SKIP][62] ([Intel XE#579])
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-3/igt@xe_pm@vram-d3cold-threshold.html

  * igt@xe_pmu@engine-activity-accuracy-50:
    - shard-lnl:          [PASS][63] -> [FAIL][64] ([Intel XE#6251]) +3 other tests fail
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-lnl-7/igt@xe_pmu@engine-activity-accuracy-50.html
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-lnl-1/igt@xe_pmu@engine-activity-accuracy-50.html

  * igt@xe_pxp@pxp-termination-key-update-post-termination-irq:
    - shard-bmg:          NOTRUN -> [SKIP][65] ([Intel XE#4733])
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-3/igt@xe_pxp@pxp-termination-key-update-post-termination-irq.html

  * igt@xe_query@multigpu-query-topology-l3-bank-mask:
    - shard-bmg:          NOTRUN -> [SKIP][66] ([Intel XE#944])
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-3/igt@xe_query@multigpu-query-topology-l3-bank-mask.html

  
#### Possible fixes ####

  * igt@core_hotunplug@hotreplug:
    - shard-bmg:          [SKIP][67] ([Intel XE#6779]) -> [PASS][68] +1 other test pass
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@core_hotunplug@hotreplug.html
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-8/igt@core_hotunplug@hotreplug.html

  * igt@core_setmaster@master-drop-set-user:
    - shard-bmg:          [FAIL][69] ([Intel XE#4674]) -> [PASS][70]
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@core_setmaster@master-drop-set-user.html
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-8/igt@core_setmaster@master-drop-set-user.html

  * igt@fbdev@read:
    - shard-bmg:          [SKIP][71] ([Intel XE#2134]) -> [PASS][72]
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@fbdev@read.html
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-7/igt@fbdev@read.html

  * igt@intel_hwmon@hwmon-write:
    - shard-bmg:          [SKIP][73] ([Intel XE#5177] / [Intel XE#6703]) -> [PASS][74]
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-2/igt@intel_hwmon@hwmon-write.html
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-7/igt@intel_hwmon@hwmon-write.html

  * igt@kms_async_flips@alternate-sync-async-flip:
    - shard-lnl:          [FAIL][75] ([Intel XE#3718]) -> [PASS][76] +1 other test pass
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-lnl-8/igt@kms_async_flips@alternate-sync-async-flip.html
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-lnl-5/igt@kms_async_flips@alternate-sync-async-flip.html

  * igt@kms_color@ctm-0-75:
    - shard-bmg:          [DMESG-FAIL][77] ([Intel XE#5545]) -> [PASS][78] +1 other test pass
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-2/igt@kms_color@ctm-0-75.html
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-7/igt@kms_color@ctm-0-75.html

  * igt@kms_color@ctm-0-75@pipe-d-hdmi-a-3:
    - shard-bmg:          [CRASH][79] -> [PASS][80] +2 other tests pass
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-2/igt@kms_color@ctm-0-75@pipe-d-hdmi-a-3.html
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-7/igt@kms_color@ctm-0-75@pipe-d-hdmi-a-3.html

  * igt@kms_feature_discovery@display-1x:
    - shard-bmg:          [SKIP][81] ([Intel XE#6557] / [Intel XE#6703]) -> [PASS][82] +9 other tests pass
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@kms_feature_discovery@display-1x.html
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-8/igt@kms_feature_discovery@display-1x.html

  * igt@kms_flip@2x-flip-vs-dpms-on-nop:
    - shard-bmg:          [SKIP][83] ([Intel XE#2316]) -> [PASS][84] +1 other test pass
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-2/igt@kms_flip@2x-flip-vs-dpms-on-nop.html
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-7/igt@kms_flip@2x-flip-vs-dpms-on-nop.html

  * igt@kms_flip@flip-vs-expired-vblank@c-edp1:
    - shard-lnl:          [FAIL][85] ([Intel XE#301] / [Intel XE#3149]) -> [PASS][86] +1 other test pass
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html

  * igt@kms_flip@wf_vblank-ts-check:
    - shard-bmg:          [SKIP][87] ([Intel XE#6703]) -> [PASS][88] +572 other tests pass
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@kms_flip@wf_vblank-ts-check.html
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-8/igt@kms_flip@wf_vblank-ts-check.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-bmg:          [ABORT][89] ([Intel XE#6740]) -> [PASS][90]
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-8/igt@kms_hdr@bpc-switch-suspend.html
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-2/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_pm_rpm@universal-planes-dpms:
    - shard-bmg:          [SKIP][91] ([Intel XE#6693]) -> [PASS][92] +3 other tests pass
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@kms_pm_rpm@universal-planes-dpms.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-8/igt@kms_pm_rpm@universal-planes-dpms.html

  * igt@xe_module_load@many-reload:
    - shard-bmg:          [FAIL][93] -> [PASS][94]
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@xe_module_load@many-reload.html
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-8/igt@xe_module_load@many-reload.html

  * igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_compute0:
    - shard-lnl:          [FAIL][95] ([Intel XE#6251]) -> [PASS][96] +1 other test pass
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-lnl-2/igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_compute0.html
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-lnl-8/igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_compute0.html

  
#### Warnings ####

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - shard-bmg:          [SKIP][97] ([Intel XE#2233]) -> [SKIP][98] ([Intel XE#6703])
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-3/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_big_fb@linear-32bpp-rotate-270:
    - shard-bmg:          [SKIP][99] ([Intel XE#6703]) -> [SKIP][100] ([Intel XE#2327]) +3 other tests skip
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@kms_big_fb@linear-32bpp-rotate-270.html
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-8/igt@kms_big_fb@linear-32bpp-rotate-270.html

  * igt@kms_big_fb@x-tiled-64bpp-rotate-90:
    - shard-bmg:          [SKIP][101] ([Intel XE#2327]) -> [SKIP][102] ([Intel XE#6703]) +1 other test skip
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-1/igt@kms_big_fb@x-tiled-64bpp-rotate-90.html
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_big_fb@x-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-64bpp-rotate-90:
    - shard-bmg:          [SKIP][103] ([Intel XE#6703]) -> [SKIP][104] ([Intel XE#1124]) +8 other tests skip
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-8/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
    - shard-bmg:          [SKIP][105] ([Intel XE#6703]) -> [SKIP][106] ([Intel XE#607])
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-8/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@yf-tiled-32bpp-rotate-0:
    - shard-bmg:          [SKIP][107] ([Intel XE#1124]) -> [SKIP][108] ([Intel XE#6703]) +10 other tests skip
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-1/igt@kms_big_fb@yf-tiled-32bpp-rotate-0.html
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_big_fb@yf-tiled-32bpp-rotate-0.html

  * igt@kms_big_fb@yf-tiled-addfb-size-overflow:
    - shard-bmg:          [SKIP][109] ([Intel XE#6703]) -> [SKIP][110] ([Intel XE#610])
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-7/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html

  * igt@kms_bw@connected-linear-tiling-3-displays-2560x1440p:
    - shard-bmg:          [SKIP][111] ([Intel XE#6703]) -> [SKIP][112] ([Intel XE#2314] / [Intel XE#2894]) +1 other test skip
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@kms_bw@connected-linear-tiling-3-displays-2560x1440p.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-8/igt@kms_bw@connected-linear-tiling-3-displays-2560x1440p.html

  * igt@kms_bw@connected-linear-tiling-4-displays-3840x2160p:
    - shard-bmg:          [SKIP][113] ([Intel XE#2314] / [Intel XE#2894]) -> [SKIP][114] ([Intel XE#6703])
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-3/igt@kms_bw@connected-linear-tiling-4-displays-3840x2160p.html
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_bw@connected-linear-tiling-4-displays-3840x2160p.html

  * igt@kms_bw@linear-tiling-1-displays-2160x1440p:
    - shard-bmg:          [SKIP][115] ([Intel XE#6703]) -> [SKIP][116] ([Intel XE#367]) +1 other test skip
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@kms_bw@linear-tiling-1-displays-2160x1440p.html
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-8/igt@kms_bw@linear-tiling-1-displays-2160x1440p.html

  * igt@kms_bw@linear-tiling-2-displays-2160x1440p:
    - shard-bmg:          [SKIP][117] ([Intel XE#367]) -> [SKIP][118] ([Intel XE#6703]) +1 other test skip
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-7/igt@kms_bw@linear-tiling-2-displays-2160x1440p.html
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_bw@linear-tiling-2-displays-2160x1440p.html

  * igt@kms_ccs@bad-aux-stride-4-tiled-mtl-mc-ccs:
    - shard-bmg:          [SKIP][119] ([Intel XE#6557] / [Intel XE#6703]) -> [SKIP][120] ([Intel XE#2887])
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-mc-ccs.html
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-7/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-mc-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs:
    - shard-bmg:          [SKIP][121] ([Intel XE#3432]) -> [SKIP][122] ([Intel XE#6703]) +1 other test skip
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-3/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs:
    - shard-bmg:          [SKIP][123] ([Intel XE#2652] / [Intel XE#787]) -> [SKIP][124] ([Intel XE#6703])
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-3/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs:
    - shard-bmg:          [SKIP][125] ([Intel XE#6703]) -> [SKIP][126] ([Intel XE#3432]) +3 other tests skip
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-8/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc:
    - shard-bmg:          [SKIP][127] ([Intel XE#6703]) -> [SKIP][128] ([Intel XE#2887]) +11 other tests skip
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-2/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc.html
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-7/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
    - shard-bmg:          [SKIP][129] ([Intel XE#2887]) -> [SKIP][130] ([Intel XE#6703]) +13 other tests skip
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-3/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html

  * igt@kms_chamelium_color@ctm-blue-to-red:
    - shard-bmg:          [SKIP][131] ([Intel XE#2325]) -> [SKIP][132] ([Intel XE#6703]) +1 other test skip
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-7/igt@kms_chamelium_color@ctm-blue-to-red.html
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_chamelium_color@ctm-blue-to-red.html

  * igt@kms_chamelium_color@ctm-negative:
    - shard-bmg:          [SKIP][133] ([Intel XE#6703]) -> [SKIP][134] ([Intel XE#2325])
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@kms_chamelium_color@ctm-negative.html
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-7/igt@kms_chamelium_color@ctm-negative.html

  * igt@kms_chamelium_edid@dp-edid-change-during-hibernate:
    - shard-bmg:          [SKIP][135] ([Intel XE#2252]) -> [SKIP][136] ([Intel XE#6703]) +9 other tests skip
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-1/igt@kms_chamelium_edid@dp-edid-change-during-hibernate.html
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_chamelium_edid@dp-edid-change-during-hibernate.html

  * igt@kms_chamelium_hpd@dp-hpd-with-enabled-mode:
    - shard-bmg:          [SKIP][137] ([Intel XE#6703]) -> [SKIP][138] ([Intel XE#2252]) +11 other tests skip
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@kms_chamelium_hpd@dp-hpd-with-enabled-mode.html
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-7/igt@kms_chamelium_hpd@dp-hpd-with-enabled-mode.html

  * igt@kms_content_protection@content-type-change:
    - shard-bmg:          [SKIP][139] ([Intel XE#6703]) -> [SKIP][140] ([Intel XE#2341]) +1 other test skip
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@kms_content_protection@content-type-change.html
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-7/igt@kms_content_protection@content-type-change.html

  * igt@kms_content_protection@dp-mst-lic-type-0:
    - shard-bmg:          [SKIP][141] ([Intel XE#6703]) -> [SKIP][142] ([Intel XE#2390])
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@kms_content_protection@dp-mst-lic-type-0.html
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-8/igt@kms_content_protection@dp-mst-lic-type-0.html

  * igt@kms_content_protection@dp-mst-suspend-resume:
    - shard-bmg:          [SKIP][143] ([Intel XE#6743]) -> [SKIP][144] ([Intel XE#6703])
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-3/igt@kms_content_protection@dp-mst-suspend-resume.html
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_content_protection@dp-mst-suspend-resume.html

  * igt@kms_content_protection@lic-type-1:
    - shard-bmg:          [SKIP][145] ([Intel XE#2341]) -> [SKIP][146] ([Intel XE#6703])
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-1/igt@kms_content_protection@lic-type-1.html
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_content_protection@lic-type-1.html

  * igt@kms_content_protection@uevent:
    - shard-bmg:          [FAIL][147] ([Intel XE#6707]) -> [SKIP][148] ([Intel XE#6703])
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-3/igt@kms_content_protection@uevent.html
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_content_protection@uevent.html

  * igt@kms_cursor_crc@cursor-offscreen-128x42:
    - shard-bmg:          [SKIP][149] ([Intel XE#6703]) -> [SKIP][150] ([Intel XE#2320]) +4 other tests skip
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@kms_cursor_crc@cursor-offscreen-128x42.html
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-7/igt@kms_cursor_crc@cursor-offscreen-128x42.html

  * igt@kms_cursor_crc@cursor-random-32x32:
    - shard-bmg:          [SKIP][151] ([Intel XE#2320]) -> [SKIP][152] ([Intel XE#6703]) +6 other tests skip
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-7/igt@kms_cursor_crc@cursor-random-32x32.html
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_cursor_crc@cursor-random-32x32.html

  * igt@kms_cursor_crc@cursor-random-512x170:
    - shard-bmg:          [SKIP][153] ([Intel XE#6703]) -> [SKIP][154] ([Intel XE#2321])
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@kms_cursor_crc@cursor-random-512x170.html
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-8/igt@kms_cursor_crc@cursor-random-512x170.html

  * igt@kms_cursor_crc@cursor-rapid-movement-256x85:
    - shard-bmg:          [SKIP][155] ([Intel XE#6557] / [Intel XE#6703]) -> [SKIP][156] ([Intel XE#2320])
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@kms_cursor_crc@cursor-rapid-movement-256x85.html
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-8/igt@kms_cursor_crc@cursor-rapid-movement-256x85.html

  * igt@kms_cursor_crc@cursor-sliding-512x170:
    - shard-bmg:          [SKIP][157] ([Intel XE#2321]) -> [SKIP][158] ([Intel XE#6703])
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-3/igt@kms_cursor_crc@cursor-sliding-512x170.html
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_cursor_crc@cursor-sliding-512x170.html

  * igt@kms_dirtyfb@psr-dirtyfb-ioctl:
    - shard-bmg:          [SKIP][159] ([Intel XE#1508]) -> [SKIP][160] ([Intel XE#6703]) +1 other test skip
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-1/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html

  * igt@kms_dp_link_training@non-uhbr-mst:
    - shard-bmg:          [SKIP][161] ([Intel XE#4354]) -> [SKIP][162] ([Intel XE#6703])
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-3/igt@kms_dp_link_training@non-uhbr-mst.html
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_dp_link_training@non-uhbr-mst.html

  * igt@kms_dsc@dsc-with-bpc:
    - shard-bmg:          [SKIP][163] ([Intel XE#6703]) -> [SKIP][164] ([Intel XE#2244]) +1 other test skip
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@kms_dsc@dsc-with-bpc.html
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-7/igt@kms_dsc@dsc-with-bpc.html

  * igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area:
    - shard-bmg:          [SKIP][165] ([Intel XE#4422]) -> [SKIP][166] ([Intel XE#6703])
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-1/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area.html
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area.html

  * igt@kms_feature_discovery@display-4x:
    - shard-bmg:          [SKIP][167] ([Intel XE#1138]) -> [SKIP][168] ([Intel XE#6703])
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-7/igt@kms_feature_discovery@display-4x.html
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_feature_discovery@display-4x.html

  * igt@kms_feature_discovery@dp-mst:
    - shard-bmg:          [SKIP][169] ([Intel XE#2375]) -> [SKIP][170] ([Intel XE#6703])
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-3/igt@kms_feature_discovery@dp-mst.html
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_feature_discovery@dp-mst.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling:
    - shard-bmg:          [SKIP][171] ([Intel XE#2293] / [Intel XE#2380]) -> [SKIP][172] ([Intel XE#6703]) +5 other tests skip
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-3/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling:
    - shard-bmg:          [SKIP][173] ([Intel XE#6703]) -> [SKIP][174] ([Intel XE#2293] / [Intel XE#2380]) +3 other tests skip
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-8/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-pri-indfb-draw-render:
    - shard-bmg:          [SKIP][175] ([Intel XE#6703]) -> [SKIP][176] ([Intel XE#2311]) +26 other tests skip
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-pri-indfb-draw-render.html
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-8/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][177] ([Intel XE#6557] / [Intel XE#6703]) -> [SKIP][178] ([Intel XE#2311]) +1 other test skip
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-pri-shrfb-draw-mmap-wc.html
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-7/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@drrs-rgb565-draw-render:
    - shard-bmg:          [SKIP][179] ([Intel XE#2311]) -> [SKIP][180] ([Intel XE#6703]) +29 other tests skip
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-3/igt@kms_frontbuffer_tracking@drrs-rgb565-draw-render.html
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-rgb565-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-shrfb-draw-blt:
    - shard-bmg:          [SKIP][181] ([Intel XE#6703]) -> [SKIP][182] ([Intel XE#4141]) +12 other tests skip
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-shrfb-draw-blt.html
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-msflip-blt:
    - shard-bmg:          [SKIP][183] ([Intel XE#2312]) -> [SKIP][184] ([Intel XE#4141])
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-msflip-blt.html
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-msflip-blt:
    - shard-bmg:          [SKIP][185] ([Intel XE#4141]) -> [SKIP][186] ([Intel XE#6703]) +11 other tests skip
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-msflip-blt.html
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-render:
    - shard-bmg:          [SKIP][187] ([Intel XE#2311]) -> [SKIP][188] ([Intel XE#2312]) +2 other tests skip
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-render.html
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-tiling-y:
    - shard-bmg:          [SKIP][189] ([Intel XE#6703]) -> [SKIP][190] ([Intel XE#2352])
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcdrrs-tiling-y.html
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcdrrs-tiling-y.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-msflip-blt:
    - shard-bmg:          [SKIP][191] ([Intel XE#2312]) -> [SKIP][192] ([Intel XE#2313]) +3 other tests skip
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-msflip-blt.html
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-y:
    - shard-bmg:          [SKIP][193] ([Intel XE#2352]) -> [SKIP][194] ([Intel XE#6703])
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][195] ([Intel XE#2313]) -> [SKIP][196] ([Intel XE#6557] / [Intel XE#6703])
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc.html
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt:
    - shard-bmg:          [SKIP][197] ([Intel XE#6703]) -> [SKIP][198] ([Intel XE#2313]) +28 other tests skip
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-8/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][199] ([Intel XE#2313]) -> [SKIP][200] ([Intel XE#2312]) +2 other tests skip
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-8/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc.html
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-2/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][201] ([Intel XE#2313]) -> [SKIP][202] ([Intel XE#6703]) +27 other tests skip
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-1/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-wc.html
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-bmg:          [SKIP][203] ([Intel XE#3374] / [Intel XE#3544]) -> [SKIP][204] ([Intel XE#6703])
   [203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-1/igt@kms_hdr@brightness-with-hdr.html
   [204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_joiner@invalid-modeset-force-ultra-joiner:
    - shard-bmg:          [SKIP][205] ([Intel XE#2934] / [Intel XE#6590]) -> [SKIP][206] ([Intel XE#6703])
   [205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-3/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html
   [206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html

  * igt@kms_joiner@invalid-modeset-ultra-joiner:
    - shard-bmg:          [SKIP][207] ([Intel XE#2927] / [Intel XE#6590]) -> [SKIP][208] ([Intel XE#6703])
   [207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-3/igt@kms_joiner@invalid-modeset-ultra-joiner.html
   [208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_joiner@invalid-modeset-ultra-joiner.html

  * igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner:
    - shard-bmg:          [SKIP][209] ([Intel XE#4090] / [Intel XE#6590]) -> [SKIP][210] ([Intel XE#6703])
   [209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-3/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html
   [210]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html

  * igt@kms_pipe_stress@stress-xrgb8888-yftiled:
    - shard-bmg:          [SKIP][211] ([Intel XE#5624]) -> [SKIP][212] ([Intel XE#6703])
   [211]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-3/igt@kms_pipe_stress@stress-xrgb8888-yftiled.html
   [212]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_pipe_stress@stress-xrgb8888-yftiled.html

  * igt@kms_plane_multiple@2x-tiling-y:
    - shard-bmg:          [SKIP][213] ([Intel XE#6703]) -> [SKIP][214] ([Intel XE#5021])
   [213]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@kms_plane_multiple@2x-tiling-y.html
   [214]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-7/igt@kms_plane_multiple@2x-tiling-y.html

  * igt@kms_plane_multiple@tiling-y:
    - shard-bmg:          [SKIP][215] ([Intel XE#5020]) -> [SKIP][216] ([Intel XE#6703])
   [215]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-7/igt@kms_plane_multiple@tiling-y.html
   [216]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_plane_multiple@tiling-y.html

  * igt@kms_plane_multiple@tiling-yf:
    - shard-bmg:          [SKIP][217] ([Intel XE#6703]) -> [SKIP][218] ([Intel XE#5020])
   [217]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@kms_plane_multiple@tiling-yf.html
   [218]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-8/igt@kms_plane_multiple@tiling-yf.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5:
    - shard-bmg:          [SKIP][219] ([Intel XE#6886]) -> [SKIP][220] ([Intel XE#6703]) +1 other test skip
   [219]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-1/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5.html
   [220]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75:
    - shard-bmg:          [SKIP][221] ([Intel XE#6703]) -> [SKIP][222] ([Intel XE#6886])
   [221]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75.html
   [222]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-7/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75.html

  * igt@kms_pm_backlight@brightness-with-dpms:
    - shard-bmg:          [SKIP][223] ([Intel XE#6703]) -> [SKIP][224] ([Intel XE#2938])
   [223]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-2/igt@kms_pm_backlight@brightness-with-dpms.html
   [224]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-7/igt@kms_pm_backlight@brightness-with-dpms.html

  * igt@kms_pm_dc@dc5-psr:
    - shard-bmg:          [SKIP][225] ([Intel XE#2392]) -> [SKIP][226] ([Intel XE#6703])
   [225]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-3/igt@kms_pm_dc@dc5-psr.html
   [226]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_pm_dc@dc5-psr.html

  * igt@kms_pm_dc@dc5-retention-flops:
    - shard-bmg:          [SKIP][227] ([Intel XE#3309]) -> [SKIP][228] ([Intel XE#6703])
   [227]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-3/igt@kms_pm_dc@dc5-retention-flops.html
   [228]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_pm_dc@dc5-retention-flops.html

  * igt@kms_pm_lpsp@kms-lpsp:
    - shard-bmg:          [SKIP][229] ([Intel XE#6703]) -> [SKIP][230] ([Intel XE#2499])
   [229]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@kms_pm_lpsp@kms-lpsp.html
   [230]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-8/igt@kms_pm_lpsp@kms-lpsp.html

  * igt@kms_pm_rpm@dpms-mode-unset-lpsp:
    - shard-bmg:          [SKIP][231] ([Intel XE#1439] / [Intel XE#836]) -> [SKIP][232] ([Intel XE#6693])
   [231]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-3/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html
   [232]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html

  * igt@kms_psr2_sf@pr-overlay-plane-move-continuous-sf:
    - shard-bmg:          [SKIP][233] ([Intel XE#1406] / [Intel XE#1489]) -> [SKIP][234] ([Intel XE#1406] / [Intel XE#6703]) +6 other tests skip
   [233]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-1/igt@kms_psr2_sf@pr-overlay-plane-move-continuous-sf.html
   [234]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_psr2_sf@pr-overlay-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-sf:
    - shard-bmg:          [SKIP][235] ([Intel XE#1406] / [Intel XE#6703]) -> [SKIP][236] ([Intel XE#1406] / [Intel XE#1489]) +8 other tests skip
   [235]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-sf.html
   [236]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-7/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_su@frontbuffer-xrgb8888:
    - shard-bmg:          [SKIP][237] ([Intel XE#1406] / [Intel XE#2387]) -> [SKIP][238] ([Intel XE#1406] / [Intel XE#6703]) +1 other test skip
   [237]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-3/igt@kms_psr2_su@frontbuffer-xrgb8888.html
   [238]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_psr2_su@frontbuffer-xrgb8888.html

  * igt@kms_psr@psr2-no-drrs:
    - shard-bmg:          [SKIP][239] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) -> [SKIP][240] ([Intel XE#1406] / [Intel XE#6703]) +11 other tests skip
   [239]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-3/igt@kms_psr@psr2-no-drrs.html
   [240]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_psr@psr2-no-drrs.html

  * igt@kms_psr@psr2-sprite-blt:
    - shard-bmg:          [SKIP][241] ([Intel XE#1406] / [Intel XE#6703]) -> [SKIP][242] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +10 other tests skip
   [241]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@kms_psr@psr2-sprite-blt.html
   [242]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-7/igt@kms_psr@psr2-sprite-blt.html

  * igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
    - shard-bmg:          [SKIP][243] ([Intel XE#1406] / [Intel XE#6703]) -> [SKIP][244] ([Intel XE#1406] / [Intel XE#2414])
   [243]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-2/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
   [244]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-7/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html

  * igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
    - shard-bmg:          [SKIP][245] ([Intel XE#1406] / [Intel XE#2414]) -> [SKIP][246] ([Intel XE#1406] / [Intel XE#6703])
   [245]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-3/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
   [246]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-180:
    - shard-bmg:          [SKIP][247] ([Intel XE#6703]) -> [SKIP][248] ([Intel XE#2330]) +1 other test skip
   [247]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-2/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html
   [248]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-7/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
    - shard-bmg:          [SKIP][249] ([Intel XE#3414] / [Intel XE#3904]) -> [SKIP][250] ([Intel XE#6703])
   [249]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-3/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
   [250]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html

  * igt@kms_rotation_crc@sprite-rotation-90:
    - shard-bmg:          [SKIP][251] ([Intel XE#6703]) -> [SKIP][252] ([Intel XE#3414] / [Intel XE#3904]) +1 other test skip
   [251]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@kms_rotation_crc@sprite-rotation-90.html
   [252]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-7/igt@kms_rotation_crc@sprite-rotation-90.html

  * igt@kms_sharpness_filter@filter-basic:
    - shard-bmg:          [SKIP][253] ([Intel XE#6703]) -> [SKIP][254] ([Intel XE#6503]) +3 other tests skip
   [253]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@kms_sharpness_filter@filter-basic.html
   [254]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-7/igt@kms_sharpness_filter@filter-basic.html

  * igt@kms_sharpness_filter@invalid-filter-with-scaler:
    - shard-bmg:          [SKIP][255] ([Intel XE#6503]) -> [SKIP][256] ([Intel XE#6703]) +1 other test skip
   [255]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-1/igt@kms_sharpness_filter@invalid-filter-with-scaler.html
   [256]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_sharpness_filter@invalid-filter-with-scaler.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          [SKIP][257] ([Intel XE#2426]) -> [SKIP][258] ([Intel XE#6703])
   [257]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-1/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [258]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@kms_vrr@cmrr:
    - shard-bmg:          [SKIP][259] ([Intel XE#6703]) -> [SKIP][260] ([Intel XE#2168])
   [259]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@kms_vrr@cmrr.html
   [260]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-8/igt@kms_vrr@cmrr.html

  * igt@kms_vrr@seamless-rr-switch-drrs:
    - shard-bmg:          [SKIP][261] ([Intel XE#6703]) -> [SKIP][262] ([Intel XE#1499])
   [261]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@kms_vrr@seamless-rr-switch-drrs.html
   [262]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-8/igt@kms_vrr@seamless-rr-switch-drrs.html

  * igt@xe_compute@ccs-mode-compute-kernel:
    - shard-bmg:          [SKIP][263] ([Intel XE#6703]) -> [SKIP][264] ([Intel XE#6599])
   [263]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@xe_compute@ccs-mode-compute-kernel.html
   [264]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-7/igt@xe_compute@ccs-mode-compute-kernel.html

  * igt@xe_eudebug@basic-vm-bind-metadata-discovery:
    - shard-bmg:          [SKIP][265] ([Intel XE#6703]) -> [SKIP][266] ([Intel XE#4837]) +7 other tests skip
   [265]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-2/igt@xe_eudebug@basic-vm-bind-metadata-discovery.html
   [266]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-7/igt@xe_eudebug@basic-vm-bind-metadata-discovery.html

  * igt@xe_eudebug@connect-user:
    - shard-bmg:          [SKIP][267] ([Intel XE#4837]) -> [SKIP][268] ([Intel XE#6703]) +6 other tests skip
   [267]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-1/igt@xe_eudebug@connect-user.html
   [268]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@xe_eudebug@connect-user.html

  * igt@xe_eudebug_online@breakpoint-many-sessions-single-tile:
    - shard-bmg:          [SKIP][269] ([Intel XE#6703]) -> [SKIP][270] ([Intel XE#4837] / [Intel XE#6665]) +5 other tests skip
   [269]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@xe_eudebug_online@breakpoint-many-sessions-single-tile.html
   [270]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-8/igt@xe_eudebug_online@breakpoint-many-sessions-single-tile.html

  * igt@xe_eudebug_online@set-breakpoint-faultable:
    - shard-bmg:          [SKIP][271] ([Intel XE#4837] / [Intel XE#6665]) -> [SKIP][272] ([Intel XE#6703]) +5 other tests skip
   [271]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-1/igt@xe_eudebug_online@set-breakpoint-faultable.html
   [272]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@xe_eudebug_online@set-breakpoint-faultable.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr:
    - shard-bmg:          [SKIP][273] ([Intel XE#2322]) -> [SKIP][274] ([Intel XE#6703]) +10 other tests skip
   [273]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-3/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr.html
   [274]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-invalidate:
    - shard-bmg:          [SKIP][275] ([Intel XE#6703]) -> [SKIP][276] ([Intel XE#2322]) +6 other tests skip
   [275]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-invalidate.html
   [276]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-7/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-invalidate.html

  * igt@xe_exec_multi_queue@few-execs-preempt-mode-userptr-invalidate:
    - shard-bmg:          [SKIP][277] ([Intel XE#6874]) -> [SKIP][278] ([Intel XE#6703]) +28 other tests skip
   [277]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-3/igt@xe_exec_multi_queue@few-execs-preempt-mode-userptr-invalidate.html
   [278]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@xe_exec_multi_queue@few-execs-preempt-mode-userptr-invalidate.html

  * igt@xe_exec_multi_queue@many-queues-basic-smem:
    - shard-bmg:          [SKIP][279] ([Intel XE#6703]) -> [SKIP][280] ([Intel XE#6874]) +28 other tests skip
   [279]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@xe_exec_multi_queue@many-queues-basic-smem.html
   [280]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-8/igt@xe_exec_multi_queue@many-queues-basic-smem.html

  * igt@xe_exec_system_allocator@many-64k-mmap-huge-nomemset:
    - shard-bmg:          [SKIP][281] ([Intel XE#5007]) -> [SKIP][282] ([Intel XE#6703])
   [281]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-1/igt@xe_exec_system_allocator@many-64k-mmap-huge-nomemset.html
   [282]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@xe_exec_system_allocator@many-64k-mmap-huge-nomemset.html

  * igt@xe_exec_system_allocator@many-64k-mmap-new-huge:
    - shard-bmg:          [SKIP][283] ([Intel XE#6703]) -> [SKIP][284] ([Intel XE#5007]) +1 other test skip
   [283]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-2/igt@xe_exec_system_allocator@many-64k-mmap-new-huge.html
   [284]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-7/igt@xe_exec_system_allocator@many-64k-mmap-new-huge.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-execqueues-mmap-new-huge:
    - shard-bmg:          [SKIP][285] ([Intel XE#4943]) -> [SKIP][286] ([Intel XE#6703]) +21 other tests skip
   [285]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-1/igt@xe_exec_system_allocator@threads-shared-vm-many-execqueues-mmap-new-huge.html
   [286]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@xe_exec_system_allocator@threads-shared-vm-many-execqueues-mmap-new-huge.html

  * igt@xe_exec_system_allocator@twice-mmap-free-huge:
    - shard-bmg:          [SKIP][287] ([Intel XE#6703]) -> [SKIP][288] ([Intel XE#4943]) +15 other tests skip
   [287]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@xe_exec_system_allocator@twice-mmap-free-huge.html
   [288]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-7/igt@xe_exec_system_allocator@twice-mmap-free-huge.html

  * igt@xe_media_fill@media-fill:
    - shard-bmg:          [SKIP][289] ([Intel XE#6703]) -> [SKIP][290] ([Intel XE#2459] / [Intel XE#2596])
   [289]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@xe_media_fill@media-fill.html
   [290]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-8/igt@xe_media_fill@media-fill.html

  * igt@xe_module_load@load:
    - shard-bmg:          ([PASS][291], [PASS][292], [PASS][293], [PASS][294], [PASS][295], [PASS][296], [PASS][297], [PASS][298], [PASS][299], [PASS][300], [ABORT][301], [ABORT][302], [ABORT][303], [ABORT][304], [PASS][305], [PASS][306], [PASS][307], [PASS][308], [PASS][309], [PASS][310], [PASS][311], [PASS][312], [PASS][313], [PASS][314]) ([Intel XE#6887]) -> ([ABORT][315], [PASS][316], [PASS][317], [PASS][318], [PASS][319], [PASS][320], [PASS][321], [PASS][322], [PASS][323], [PASS][324], [PASS][325], [PASS][326], [PASS][327], [PASS][328], [SKIP][329], [PASS][330], [PASS][331], [PASS][332], [PASS][333], [PASS][334], [PASS][335], [ABORT][336], [PASS][337], [PASS][338]) ([Intel XE#2457] / [Intel XE#6887])
   [291]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@xe_module_load@load.html
   [292]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@xe_module_load@load.html
   [293]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-8/igt@xe_module_load@load.html
   [294]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-8/igt@xe_module_load@load.html
   [295]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@xe_module_load@load.html
   [296]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-7/igt@xe_module_load@load.html
   [297]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-4/igt@xe_module_load@load.html
   [298]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-3/igt@xe_module_load@load.html
   [299]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-2/igt@xe_module_load@load.html
   [300]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-2/igt@xe_module_load@load.html
   [301]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-6/igt@xe_module_load@load.html
   [302]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-6/igt@xe_module_load@load.html
   [303]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-6/igt@xe_module_load@load.html
   [304]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-6/igt@xe_module_load@load.html
   [305]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-2/igt@xe_module_load@load.html
   [306]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-1/igt@xe_module_load@load.html
   [307]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-1/igt@xe_module_load@load.html
   [308]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-1/igt@xe_module_load@load.html
   [309]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-3/igt@xe_module_load@load.html
   [310]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@xe_module_load@load.html
   [311]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@xe_module_load@load.html
   [312]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-4/igt@xe_module_load@load.html
   [313]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-7/igt@xe_module_load@load.html
   [314]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-3/igt@xe_module_load@load.html
   [315]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-6/igt@xe_module_load@load.html
   [316]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-1/igt@xe_module_load@load.html
   [317]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-1/igt@xe_module_load@load.html
   [318]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@xe_module_load@load.html
   [319]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@xe_module_load@load.html
   [320]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@xe_module_load@load.html
   [321]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-7/igt@xe_module_load@load.html
   [322]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-3/igt@xe_module_load@load.html
   [323]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-3/igt@xe_module_load@load.html
   [324]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-3/igt@xe_module_load@load.html
   [325]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@xe_module_load@load.html
   [326]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@xe_module_load@load.html
   [327]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-4/igt@xe_module_load@load.html
   [328]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-4/igt@xe_module_load@load.html
   [329]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-3/igt@xe_module_load@load.html
   [330]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-8/igt@xe_module_load@load.html
   [331]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-8/igt@xe_module_load@load.html
   [332]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-8/igt@xe_module_load@load.html
   [333]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-7/igt@xe_module_load@load.html
   [334]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-2/igt@xe_module_load@load.html
   [335]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@xe_module_load@load.html
   [336]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-6/igt@xe_module_load@load.html
   [337]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-7/igt@xe_module_load@load.html
   [338]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-2/igt@xe_module_load@load.html

  * igt@xe_pm@d3cold-basic:
    - shard-bmg:          [SKIP][339] ([Intel XE#6703]) -> [SKIP][340] ([Intel XE#2284])
   [339]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-2/igt@xe_pm@d3cold-basic.html
   [340]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-7/igt@xe_pm@d3cold-basic.html

  * igt@xe_pm@d3cold-i2c:
    - shard-bmg:          [SKIP][341] ([Intel XE#5694]) -> [SKIP][342] ([Intel XE#6703])
   [341]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-3/igt@xe_pm@d3cold-i2c.html
   [342]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@xe_pm@d3cold-i2c.html

  * igt@xe_pm@d3cold-multiple-execs:
    - shard-bmg:          [SKIP][343] ([Intel XE#2284]) -> [SKIP][344] ([Intel XE#6703]) +2 other tests skip
   [343]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-7/igt@xe_pm@d3cold-multiple-execs.html
   [344]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@xe_pm@d3cold-multiple-execs.html

  * igt@xe_pxp@pxp-stale-bo-bind-post-termination-irq:
    - shard-bmg:          [SKIP][345] ([Intel XE#4733]) -> [SKIP][346] ([Intel XE#6703]) +3 other tests skip
   [345]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-3/igt@xe_pxp@pxp-stale-bo-bind-post-termination-irq.html
   [346]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@xe_pxp@pxp-stale-bo-bind-post-termination-irq.html

  * igt@xe_pxp@pxp-termination-key-update-post-suspend:
    - shard-bmg:          [SKIP][347] ([Intel XE#6703]) -> [SKIP][348] ([Intel XE#4733]) +3 other tests skip
   [347]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-2/igt@xe_pxp@pxp-termination-key-update-post-suspend.html
   [348]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-7/igt@xe_pxp@pxp-termination-key-update-post-suspend.html

  * igt@xe_query@multigpu-query-mem-usage:
    - shard-bmg:          [SKIP][349] ([Intel XE#944]) -> [SKIP][350] ([Intel XE#6703]) +2 other tests skip
   [349]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-3/igt@xe_query@multigpu-query-mem-usage.html
   [350]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-5/igt@xe_query@multigpu-query-mem-usage.html

  * igt@xe_query@multigpu-query-oa-units:
    - shard-bmg:          [SKIP][351] ([Intel XE#6703]) -> [SKIP][352] ([Intel XE#944])
   [351]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41/shard-bmg-5/igt@xe_query@multigpu-query-oa-units.html
   [352]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/shard-bmg-7/igt@xe_query@multigpu-query-oa-units.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1138
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
  [Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1508]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1508
  [Intel XE#2134]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2134
  [Intel XE#2168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2168
  [Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229
  [Intel XE#2233]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2233
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
  [Intel XE#2248]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2248
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2330
  [Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
  [Intel XE#2352]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2352
  [Intel XE#2375]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2375
  [Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
  [Intel XE#2387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2387
  [Intel XE#2390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2390
  [Intel XE#2392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2392
  [Intel XE#2414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2414
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2457]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2457
  [Intel XE#2459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2459
  [Intel XE#2499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2499
  [Intel XE#2596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2596
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
  [Intel XE#2927]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2927
  [Intel XE#2934]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2934
  [Intel XE#2938]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2938
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#3309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3309
  [Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#3718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3718
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4090]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4090
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4156]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4156
  [Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
  [Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
  [Intel XE#4674]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4674
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
  [Intel XE#5007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5007
  [Intel XE#5020]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5020
  [Intel XE#5021]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5021
  [Intel XE#5177]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5177
  [Intel XE#5545]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5545
  [Intel XE#5624]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5624
  [Intel XE#5694]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5694
  [Intel XE#579]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/579
  [Intel XE#5793]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5793
  [Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
  [Intel XE#610]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/610
  [Intel XE#6251]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6251
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#6557]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6557
  [Intel XE#6590]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6590
  [Intel XE#6599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6599
  [Intel XE#6665]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6665
  [Intel XE#6693]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6693
  [Intel XE#6703]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6703
  [Intel XE#6707]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6707
  [Intel XE#6740]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6740
  [Intel XE#6743]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6743
  [Intel XE#6779]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6779
  [Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
  [Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
  [Intel XE#6887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6887
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41 -> xe-pw-158384v4

  IGT_8668: 906681747a312ef11ef9af8ab1fa6eff28b4cbd0 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4254-72428bdb20b6c86beaeddb9d69bf698d0697aa41: 72428bdb20b6c86beaeddb9d69bf698d0697aa41
  xe-pw-158384v4: 158384v4

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158384v4/index.html

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