Re: [PATCH] drm/xe: Do not preempt fence signaling CS instructions

[Matthew Brost <matthew.brost@intel.com>]

On Tue, Jan 20, 2026 at 01:10:20PM -0800, Daniele Ceraolo Spurio wrote:
> 
> 
> On 1/19/2026 4:01 AM, Zbigniew Kempczyński wrote:
> > On Fri, Jan 16, 2026 at 01:05:01PM -0800, Matthew Brost wrote:
> > > On Fri, Jan 16, 2026 at 10:45:39AM +0100, Zbigniew Kempczyński wrote:
> > > > On Wed, Jan 14, 2026 at 04:45:46PM -0800, Matthew Brost wrote:
> > > > > If a batch buffer is complete, it makes little sense to preempt the
> > > > > fence signaling instructions in the ring, as the largest portion of the
> > > > > work (the batch buffer) is already done and fence signaling consists of
> > > > > only a few instructions. If these instructions are preempted, the GuC
> > > > > would need to perform a context switch just to signal the fence, which
> > > > > is costly and delays fence signaling. Avoid this scenario by disabling
> > > > > preemption immediately after the BB start instruction and re-enabling it
> > > > > after executing the fence signaling instructions.
> > > > > 
> > > > > Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver for Intel GPUs")
> > > > > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> > > > > Cc: Carlos Santa <carlos.santa@intel.com>
> > > > > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > > > > ---
> > > > >   drivers/gpu/drm/xe/xe_ring_ops.c | 9 +++++++++
> > > > >   1 file changed, 9 insertions(+)
> > > > > 
> > > > > diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
> > > > > index a1fd99f2d539..cd645ee400b9 100644
> > > > > --- a/drivers/gpu/drm/xe/xe_ring_ops.c
> > > > > +++ b/drivers/gpu/drm/xe/xe_ring_ops.c
> > > > > @@ -282,6 +282,9 @@ static void __emit_job_gen12_simple(struct xe_sched_job *job, struct xe_lrc *lrc
> > > > >   	i = emit_bb_start(batch_addr, ppgtt_flag, dw, i);
> > > > > +	/* Don't preempt fence signaling */
> > > > > +	dw[i++] = MI_ARB_ON_OFF | MI_ARB_DISABLE;
> > > > > +
> > > > >   	if (job->user_fence.used) {
> > > > >   		i = emit_flush_dw(dw, i);
> > > > >   		i = emit_store_imm_ppgtt_posted(job->user_fence.addr,
> > > > > @@ -347,6 +350,9 @@ static void __emit_job_gen12_video(struct xe_sched_job *job, struct xe_lrc *lrc,
> > > > >   	i = emit_bb_start(batch_addr, ppgtt_flag, dw, i);
> > > > > +	/* Don't preempt fence signaling */
> > > > > +	dw[i++] = MI_ARB_ON_OFF | MI_ARB_DISABLE;
> > > > > +
> > > > >   	if (job->user_fence.used) {
> > > > >   		i = emit_flush_dw(dw, i);
> > > > >   		i = emit_store_imm_ppgtt_posted(job->user_fence.addr,
> > > > > @@ -399,6 +405,9 @@ static void __emit_job_gen12_render_compute(struct xe_sched_job *job,
> > > > >   	i = emit_bb_start(batch_addr, ppgtt_flag, dw, i);
> > > > > +	/* Don't preempt fence signaling */
> > > > > +	dw[i++] = MI_ARB_ON_OFF | MI_ARB_DISABLE;
> > > > > +
> > > > IGT tests which calls compute-walker, then bbe are asynchronous (don't
> > > > wait for completion, pipe-control is necessary to wait on
> > > > compute-walker).
> > > > 
> > > This asynchronous behavior may explain things. Is this a common use
> > > case?
> > Compute runtime if I'm not wrong uses pipe-control explicitely. IGT are
> > not doing this relying on kmd.
> > 
> > > Also do you know if render engines have similar asynchronous behaviors
> > > or is this specific to compute engines?
> > I don't know, I think Mesa folks may know the answer.
> > 
> > > Lastly, the i915 disables preemption on both render / compute engines
> > > immediately after the BB before emitting the pipe control. Is this async
> > > behavior a new few feature in Xe2 parts which only the Xe driver
> > > supports? This might explain why the i915 works and Xe does not.
> > Test exercises WMTP and this is supported starting at Xe2+. Probably
> > what test is doing has a meaning in this case. First compute-walker
> > submits kernel which loops until it will observe some memory write.
> > Second job executes compute-walker with kernel which does some quick job.
> > But first occupies all EU's so second job can be preempted only when
> > preemption occurs and SIP will be executed. So if we disable preemption
> > immediately we submit compute-walker I think we have no change to enter
> > SIP and switch. Even if I add pipe-control to batch level according
> > to Daniele comment job it is still preemptable and we move pipe-control
> > location from kmd -> batch level..
> 
> So basically the test requires a preemption but does not put any preemption
> points within the batch? I'd argue that the fact that the test works at all
> is by chance, because the kernel just happens to add a preemption point
> after the BB and the batch doesn't wait for the results before completing.
> IMO it should be ok to go ahead with this patch and rework the test, but we
> probably need an ack from a maintainer because something that worked before

So my reply to Zbigniew. I'd like to know if this test works with pipe
controls in the batch.

Then I believe we need to confirm:

 - Compute runtime inserts pipe controls in the batch
 - Get extensive CI runs of compute runtime, Mesa, and application 

As long as we haven't regressed anything, we should be good to merge
this behavior change.

If not, then we stuck with the existing behavior but perhaps could add
an opt-in exec queue flag to create the behavior.

Matt

> (even if just by chance) is not going to work anymore.
> 
> Daniele
> 
> > 
> > --
> > Zbigniew
> > 
> > > Matt
> > > 
> > > > May you try to put arb disable after emit_render_cache_flush?
> > > > 
> > > > --
> > > > Zbigniew
> > > > 
> > > > >   	i = emit_render_cache_flush(job, dw, i);
> > > > >   	if (job->user_fence.used)
> > > > > -- 
> > > > > 2.34.1
> > > > > 
>