From: Matthew Brost <matthew.brost@intel.com>
To: "Summers, Stuart" <stuart.summers@intel.com>
Cc: "Kempczynski, Zbigniew" <zbigniew.kempczynski@intel.com>,
"Ceraolo Spurio, Daniele" <daniele.ceraolospurio@intel.com>,
"Dugast, Francois" <francois.dugast@intel.com>,
"intel-xe@lists.freedesktop.org" <intel-xe@lists.freedesktop.org>,
"Santa, Carlos" <carlos.santa@intel.com>
Subject: Re: [PATCH] drm/xe: Do not preempt fence signaling CS instructions
Date: Fri, 16 Jan 2026 12:44:42 -0800 [thread overview]
Message-ID: <aWqjOp2yaIIxI287@lstrano-desk.jf.intel.com> (raw)
In-Reply-To: <7379f92d177312e90ff27df2a088897a1da920cc.camel@intel.com>
On Fri, Jan 16, 2026 at 12:51:46PM -0700, Summers, Stuart wrote:
> On Fri, 2026-01-16 at 08:43 -0800, Daniele Ceraolo Spurio wrote:
> >
> >
> > On 1/16/2026 2:12 AM, Francois Dugast wrote:
> > > On Fri, Jan 16, 2026 at 10:45:39AM +0100, Zbigniew Kempczyński
> > > wrote:
> > > > On Wed, Jan 14, 2026 at 04:45:46PM -0800, Matthew Brost wrote:
> > > > > If a batch buffer is complete, it makes little sense to preempt
> > > > > the
> > > > > fence signaling instructions in the ring, as the largest
> > > > > portion of the
> > > > > work (the batch buffer) is already done and fence signaling
> > > > > consists of
> > > > > only a few instructions. If these instructions are preempted,
> > > > > the GuC
> > > > > would need to perform a context switch just to signal the
> > > > > fence, which
> > > > > is costly and delays fence signaling. Avoid this scenario by
> > > > > disabling
> > > > > preemption immediately after the BB start instruction and re-
> > > > > enabling it
> > > > > after executing the fence signaling instructions.
> > > > >
> > > > > Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver for
> > > > > Intel GPUs")
> > > > > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> > > > > Cc: Carlos Santa <carlos.santa@intel.com>
> > > > > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > > > > ---
> > > > > drivers/gpu/drm/xe/xe_ring_ops.c | 9 +++++++++
> > > > > 1 file changed, 9 insertions(+)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c
> > > > > b/drivers/gpu/drm/xe/xe_ring_ops.c
> > > > > index a1fd99f2d539..cd645ee400b9 100644
> > > > > --- a/drivers/gpu/drm/xe/xe_ring_ops.c
> > > > > +++ b/drivers/gpu/drm/xe/xe_ring_ops.c
> > > > > @@ -282,6 +282,9 @@ static void __emit_job_gen12_simple(struct
> > > > > xe_sched_job *job, struct xe_lrc *lrc
> > > > >
> > > > > i = emit_bb_start(batch_addr, ppgtt_flag, dw, i);
> > > > >
> > > > > + /* Don't preempt fence signaling */
> > > > > + dw[i++] = MI_ARB_ON_OFF | MI_ARB_DISABLE;
> > > > > +
> > > > > if (job->user_fence.used) {
> > > > > i = emit_flush_dw(dw, i);
> > > > > i = emit_store_imm_ppgtt_posted(job-
> > > > > >user_fence.addr,
> > > > > @@ -347,6 +350,9 @@ static void __emit_job_gen12_video(struct
> > > > > xe_sched_job *job, struct xe_lrc *lrc,
> > > > >
> > > > > i = emit_bb_start(batch_addr, ppgtt_flag, dw, i);
> > > > >
> > > > > + /* Don't preempt fence signaling */
> > > > > + dw[i++] = MI_ARB_ON_OFF | MI_ARB_DISABLE;
> > > > > +
> > > > > if (job->user_fence.used) {
> > > > > i = emit_flush_dw(dw, i);
> > > > > i = emit_store_imm_ppgtt_posted(job-
> > > > > >user_fence.addr,
> > > > > @@ -399,6 +405,9 @@ static void
> > > > > __emit_job_gen12_render_compute(struct xe_sched_job *job,
> > > > >
> > > > > i = emit_bb_start(batch_addr, ppgtt_flag, dw, i);
> > > > >
> > > > > + /* Don't preempt fence signaling */
> > > > > + dw[i++] = MI_ARB_ON_OFF | MI_ARB_DISABLE;
> > > > > +
> > > > IGT tests which calls compute-walker, then bbe are asynchronous
> > > > (don't
> > > > wait for completion, pipe-control is necessary to wait on
> > > > compute-walker).
> > > >
> > > > May you try to put arb disable after emit_render_cache_flush?
> > > Thanks Zbigniew, xe_compute_preempt tests do pass with this change:
> > >
> > > diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c
> > > b/drivers/gpu/drm/xe/xe_ring_ops.c
> > > index cd645ee400b9..d8cceab97fa8 100644
> > > --- a/drivers/gpu/drm/xe/xe_ring_ops.c
> > > +++ b/drivers/gpu/drm/xe/xe_ring_ops.c
> > > @@ -405,11 +405,11 @@ static void
> > > __emit_job_gen12_render_compute(struct xe_sched_job *job,
> > >
> > > i = emit_bb_start(batch_addr, ppgtt_flag, dw, i);
> > >
> > > + i = emit_render_cache_flush(job, dw, i);
> > > +
Yes, I also confirmed that emit_render_cache_flush() is the problematic
instruction that hangs when preemption is disabled.
> >
> > The pipe control in emit_render_cache_flush is preemptable, so having
> > that before the arb off switch invalidates what the patch is trying
> > to
> > do (i.e., no preemption points after the bb completes until we signal
> > the fence).
Yes, disabling preemption after emit_render_cache_flush() makes the
render/compute engine change in this series useless, as
emit_render_cache_flush() is preemptable and the goal of the series is
to avoid preempting if the BB is done in the fence signaling
instructions.
> >
> > Why does disabling arbitration cause this specific pipe control to
> > hang?
This is what we need to figure out. I looked at i915, and they have
preemption disabled around sections very similar to
emit_render_cache_flush().
I ’m raising this up the management chain to see if we can find an owner
to debug it, and perhaps even get an SV trace to figure out what is
going on. I believe this series, if working, would make our stack perform
better, so it would be good to get something functional here.
>
> Are we enabling/disabling preemption from the batch too? It seems like
We are not disabling preemption in the batch, only in the fence
signaling.
> the batch preemption control should be owned by the user and not rely
> on the ring configuration here (which might have other intention as
> seen here).
>
> Also would be interesting to know if the compute/render UMD compliance
> tests are passing with this change.
>
Agree.
Matt
> Thanks,
> Stuart
>
> >
> > Daniele
> >
> > > /* Don't preempt fence signaling */
> > > dw[i++] = MI_ARB_ON_OFF | MI_ARB_DISABLE;
> > >
> > > - i = emit_render_cache_flush(job, dw, i);
> > > -
> > > if (job->user_fence.used)
> > > i = emit_store_imm_ppgtt_posted(job-
> > > >user_fence.addr,
> > > job-
> > > >user_fence.value,
> > >
> > >
> > > Francois
> > >
> > > > --
> > > > Zbigniew
> > > >
> > > > > i = emit_render_cache_flush(job, dw, i);
> > > > >
> > > > > if (job->user_fence.used)
> > > > > --
> > > > > 2.34.1
> > > > >
> >
>
next prev parent reply other threads:[~2026-01-16 20:44 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-15 0:45 [PATCH] drm/xe: Do not preempt fence signaling CS instructions Matthew Brost
2026-01-15 0:52 ` ✓ CI.KUnit: success for " Patchwork
2026-01-15 1:35 ` ✓ Xe.CI.BAT: " Patchwork
2026-01-15 6:13 ` ✗ Xe.CI.Full: failure " Patchwork
2026-01-16 9:45 ` [PATCH] " Zbigniew Kempczyński
2026-01-16 10:12 ` Francois Dugast
2026-01-16 16:43 ` Daniele Ceraolo Spurio
2026-01-16 19:51 ` Summers, Stuart
2026-01-16 20:44 ` Matthew Brost [this message]
2026-01-16 21:07 ` Summers, Stuart
2026-01-16 21:19 ` Matthew Brost
2026-01-16 21:05 ` Matthew Brost
2026-01-19 12:01 ` Zbigniew Kempczyński
2026-01-20 21:10 ` Daniele Ceraolo Spurio
2026-01-20 21:26 ` Matthew Brost
2026-01-20 21:27 ` Matthew Brost
2026-01-22 9:22 ` Zbigniew Kempczyński
2026-01-22 17:47 ` Daniele Ceraolo Spurio
2026-01-27 20:14 ` Matthew Brost
2026-01-20 21:11 ` Matthew Brost
2026-01-22 8:44 ` Zbigniew Kempczyński
2026-01-27 7:20 ` Zbigniew Kempczyński
2026-01-27 20:15 ` Matthew Brost
2026-02-26 17:35 ` Matthew Brost
2026-02-26 17:49 ` Daniele Ceraolo Spurio
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