Re: [PATCH v2 0/3] Fix Cx0 Suspend Resume issue

[Rodrigo Vivi <rodrigo.vivi@intel.com>]

On Wed, Jan 14, 2026 at 09:12:56AM +0530, Suraj Kandpal wrote:
> CX0 PHY currently has two issues which cause a hang when we try
> to suspend resume machine with a delay of 15mins and 1+ hour.
> This happens due to two reasons:
> 1) We do not follow the Enablement sequence where we need to
> enable our clock after PPS Enablement cycle
> 2) We do not make sure response ready and error bit are cleared
> in P2M_MSGBUS_STATUS before writing the transaction pending bit.
> This series aims to solve this.

Is there any Fixes: tag that we should add to any of the commits
in this series?

Also, next time, consider a fix as the first patch for easy backport
and the refactor on top.

Thanks,
Rodrigo.

> 
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> 
> Mika Kahola (1):
>   drm/i915/cx0: Split PLL enabling/disabling in two parts
> 
> Suraj Kandpal (2):
>   drm/i915/cx0: Clear response ready & error bit
>   drm/i915/cx0: Rename intel_clear_response_ready flag
> 
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 134 +++++++++++-------
>  drivers/gpu/drm/i915/display/intel_cx0_phy.h  |   4 +-
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c |   7 +-
>  drivers/gpu/drm/i915/display/intel_lt_phy.c   |   2 +-
>  4 files changed, 92 insertions(+), 55 deletions(-)
> 
> -- 
> 2.34.1
>