[PATCH v2 0/3] Fix Cx0 Suspend Resume issue

[PATCH v2 0/3] Fix Cx0 Suspend Resume issue

[Suraj Kandpal]

CX0 PHY currently has two issues which cause a hang when we try
to suspend resume machine with a delay of 15mins and 1+ hour.
This happens due to two reasons:
1) We do not follow the Enablement sequence where we need to
enable our clock after PPS Enablement cycle
2) We do not make sure response ready and error bit are cleared
in P2M_MSGBUS_STATUS before writing the transaction pending bit.
This series aims to solve this.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>

Mika Kahola (1):
  drm/i915/cx0: Split PLL enabling/disabling in two parts

Suraj Kandpal (2):
  drm/i915/cx0: Clear response ready & error bit
  drm/i915/cx0: Rename intel_clear_response_ready flag

 drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 134 +++++++++++-------
 drivers/gpu/drm/i915/display/intel_cx0_phy.h  |   4 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |   7 +-
 drivers/gpu/drm/i915/display/intel_lt_phy.c   |   2 +-
 4 files changed, 92 insertions(+), 55 deletions(-)

-- 
2.34.1

[PATCH v2 1/3] drm/i915/cx0: Split PLL enabling/disabling in two parts

[Suraj Kandpal]

From: Mika Kahola <mika.kahola@intel.com>

Split PLL enabling/disabling in two parts - one for pll setting
pll dividers and second one to enable/disable pll clock. PLL
clock enabling/disbling happens via encoder->enable_clock/disable_clock
function hook.

PLL state verification happens now earlier than the clock is enabled
which causes a drm warn to be thrown. Silence this warning by
allowing this check for only earlier platforms than MeteorLake.

While at it also add the necessary argument to cx0_enable_clock
so that we can move step 12 of the enable sequence.

v2:
- Move state verification to enable_clock() function for
MTL+ platforms
- Squash patch 1 & 2 (Gustavo)
- Use correct Bspec references (Gustavo)
- Fix build error (Michal)

Bspec: 65448, 68849
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Michał Grzelak <michal.grzelak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 120 +++++++++++-------
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |   7 +-
 2 files changed, 80 insertions(+), 47 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 7288065d2461..3418a3ed28fd 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -3225,11 +3225,8 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
 {
 	int port_clock = pll_state->use_c10 ? pll_state->c10.clock : pll_state->c20.clock;
 	struct intel_display *display = to_intel_display(encoder);
-	enum phy phy = intel_encoder_to_phy(encoder);
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	bool lane_reversal = dig_port->lane_reversal;
-	u8 maxpclk_lane = lane_reversal ? INTEL_CX0_LANE1 :
-					  INTEL_CX0_LANE0;
 	struct ref_tracker *wakeref = intel_cx0_phy_transaction_begin(encoder);
 
 	/*
@@ -3284,42 +3281,6 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
 	 */
 	intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), port_clock);
 
-	/*
-	 * 9. Set PORT_CLOCK_CTL register PCLK PLL Request
-	 * LN<Lane for maxPCLK> to "1" to enable PLL.
-	 */
-	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
-		     intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES),
-		     intel_cx0_get_pclk_pll_request(maxpclk_lane));
-
-	/* 10. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK> == "1". */
-	if (intel_de_wait_us(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
-			     intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES),
-			     intel_cx0_get_pclk_pll_ack(maxpclk_lane),
-			     XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US, NULL))
-		drm_warn(display->drm, "Port %c PLL not locked\n",
-			 phy_name(phy));
-
-	/*
-	 * 11. Follow the Display Voltage Frequency Switching Sequence After
-	 * Frequency Change. We handle this step in bxt_set_cdclk().
-	 */
-
-	/*
-	 * 12. Toggle powerdown if HDMI is enabled on C10 PHY.
-	 *
-	 * Wa_13013502646:
-	 * Fixes: HDMI lane to lane skew violations on C10 display PHYs.
-	 * Workaround: Toggle powerdown value by setting first to P0 and then to P2, for both
-	 * PHY lanes.
-	 */
-	if (!cx0pll_state_is_dp(pll_state) && pll_state->use_c10) {
-		intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES,
-						    XELPDP_P0_STATE_ACTIVE);
-		intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES,
-						    XELPDP_P2_STATE_READY);
-	}
-
 	intel_cx0_phy_transaction_end(encoder, wakeref);
 }
 
@@ -3403,6 +3364,56 @@ static int intel_mtl_tbt_clock_select(struct intel_display *display,
 	}
 }
 
+static void intel_cx0pll_enable_clock(struct intel_encoder *encoder,
+				      const struct intel_cx0pll_state *pll_state)
+{
+	struct intel_display *display = to_intel_display(encoder);
+	enum phy phy = intel_encoder_to_phy(encoder);
+	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+	bool lane_reversal = dig_port->lane_reversal;
+	u8 maxpclk_lane = lane_reversal ? INTEL_CX0_LANE1 :
+					  INTEL_CX0_LANE0;
+	struct ref_tracker *wakeref = intel_cx0_phy_transaction_begin(encoder);
+
+	/*
+	 * 9. Set PORT_CLOCK_CTL register PCLK PLL Request
+	 * LN<Lane for maxPCLK> to "1" to enable PLL.
+	 */
+	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
+		     intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES),
+		     intel_cx0_get_pclk_pll_request(maxpclk_lane));
+
+	/* 10. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK> == "1". */
+	if (intel_de_wait_us(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
+			     intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES),
+			     intel_cx0_get_pclk_pll_ack(maxpclk_lane),
+			     XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US, NULL))
+		drm_warn(display->drm, "Port %c PLL not locked\n",
+			 phy_name(phy));
+
+	/*
+	 * 11. Follow the Display Voltage Frequency Switching Sequence After
+	 * Frequency Change. We handle this step in bxt_set_cdclk().
+	 */
+
+	/*
+	 * 12. Toggle powerdown if HDMI is enabled on C10 PHY.
+	 *
+	 * Wa_13013502646:
+	 * Fixes: HDMI lane to lane skew violations on C10 display PHYs.
+	 * Workaround: Toggle powerdown value by setting first to P0 and then to P2, for both
+	 * PHY lanes.
+	 */
+	if (!cx0pll_state_is_dp(pll_state) && pll_state->use_c10) {
+		intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES,
+						    XELPDP_P0_STATE_ACTIVE);
+		intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES,
+						    XELPDP_P2_STATE_READY);
+	}
+
+	intel_cx0_phy_transaction_end(encoder, wakeref);
+}
+
 void intel_mtl_tbt_pll_enable_clock(struct intel_encoder *encoder, int port_clock)
 {
 	struct intel_display *display = to_intel_display(encoder);
@@ -3468,10 +3479,16 @@ void intel_mtl_pll_enable(struct intel_encoder *encoder,
 void intel_mtl_pll_enable_clock(struct intel_encoder *encoder,
 				const struct intel_crtc_state *crtc_state)
 {
+	struct intel_display *display = to_intel_display(encoder);
+	struct intel_dpll *pll = crtc_state->intel_dpll;
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 
 	if (intel_tc_port_in_tbt_alt_mode(dig_port))
 		intel_mtl_tbt_pll_enable_clock(encoder, crtc_state->port_clock);
+	else
+		intel_cx0pll_enable_clock(encoder, &crtc_state->dpll_hw_state.cx0pll);
+
+	assert_dpll_enabled(display, pll);
 }
 
 /*
@@ -3567,12 +3584,6 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder)
 	 * Frequency Change. We handle this step in bxt_set_cdclk().
 	 */
 
-	/* 7. Program PORT_CLOCK_CTL register to disable and gate clocks. */
-	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
-		     XELPDP_DDI_CLOCK_SELECT_MASK(display), 0);
-	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
-		     XELPDP_FORWARD_CLOCK_UNGATE, 0);
-
 	intel_cx0_phy_transaction_end(encoder, wakeref);
 }
 
@@ -3586,6 +3597,20 @@ static bool intel_cx0_pll_is_enabled(struct intel_encoder *encoder)
 			     intel_cx0_get_pclk_pll_request(lane);
 }
 
+static void intel_cx0pll_disable_clock(struct intel_encoder *encoder)
+{
+	struct intel_display *display = to_intel_display(encoder);
+	struct ref_tracker *wakeref = intel_cx0_phy_transaction_begin(encoder);
+
+	/* 7. Program PORT_CLOCK_CTL register to disable and gate clocks. */
+	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
+		     XELPDP_DDI_CLOCK_SELECT_MASK(display), 0);
+	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
+		     XELPDP_FORWARD_CLOCK_UNGATE, 0);
+
+	intel_cx0_phy_transaction_end(encoder, wakeref);
+}
+
 void intel_mtl_tbt_pll_disable_clock(struct intel_encoder *encoder)
 {
 	struct intel_display *display = to_intel_display(encoder);
@@ -3635,6 +3660,9 @@ void intel_mtl_pll_disable_clock(struct intel_encoder *encoder)
 
 	if (intel_tc_port_in_tbt_alt_mode(dig_port))
 		intel_mtl_tbt_pll_disable_clock(encoder);
+	else
+		intel_cx0pll_disable_clock(encoder);
+
 }
 
 enum icl_port_dpll_id
@@ -3783,6 +3811,8 @@ void intel_cx0_pll_power_save_wa(struct intel_display *display)
 			    encoder->base.base.id, encoder->base.name);
 
 		intel_cx0pll_enable(encoder, &pll_state);
+		intel_cx0pll_enable_clock(encoder, &pll_state);
 		intel_cx0pll_disable(encoder);
+		intel_cx0pll_disable_clock(encoder);
 	}
 }
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 9aa84a430f09..040c97d81302 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -298,7 +298,8 @@ void intel_dpll_enable(const struct intel_crtc_state *crtc_state)
 
 	if (old_mask) {
 		drm_WARN_ON(display->drm, !pll->on);
-		assert_dpll_enabled(display, pll);
+		if (DISPLAY_VER(display) < 14)
+			assert_dpll_enabled(display, pll);
 		goto out;
 	}
 	drm_WARN_ON(display->drm, pll->on);
@@ -342,7 +343,9 @@ void intel_dpll_disable(const struct intel_crtc_state *crtc_state)
 		    pll->info->name, pll->active_mask, pll->on,
 		    crtc->base.base.id, crtc->base.name);
 
-	assert_dpll_enabled(display, pll);
+	if (DISPLAY_VER(display) < 14)
+		assert_dpll_enabled(display, pll);
+
 	drm_WARN_ON(display->drm, !pll->on);
 
 	pll->active_mask &= ~pipe_mask;
-- 
2.34.1

Re: [PATCH v2 1/3] drm/i915/cx0: Split PLL enabling/disabling in two parts

[Imre Deak]

On Wed, Jan 14, 2026 at 09:12:57AM +0530, Suraj Kandpal wrote:
> From: Mika Kahola <mika.kahola@intel.com>
> 
> Split PLL enabling/disabling in two parts - one for pll setting
> pll dividers and second one to enable/disable pll clock. PLL
> clock enabling/disbling happens via encoder->enable_clock/disable_clock
> function hook.

This is missing the rationale for the change. As I understand it
appeares to fix a PLL enabling/disabling timeout, if so that should be
described here in the commit log and also explain how the change fixes
the timeout, IOW wrt. what are the enabling/disabling steps gets
reordered?

Also, what about CMTG? It may require an output/DDI's PLL for another
ouput/DDI even if the former output/DDI is disabled.

Also, there is an ordering issue in the change, see below.

> PLL state verification happens now earlier than the clock is enabled
> which causes a drm warn to be thrown. Silence this warning by
> allowing this check for only earlier platforms than MeteorLake.
> 
> While at it also add the necessary argument to cx0_enable_clock
> so that we can move step 12 of the enable sequence.
> 
> v2:
> - Move state verification to enable_clock() function for
> MTL+ platforms
> - Squash patch 1 & 2 (Gustavo)
> - Use correct Bspec references (Gustavo)
> - Fix build error (Michal)
> 
> Bspec: 65448, 68849
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> Reviewed-by: Michał Grzelak <michal.grzelak@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 120 +++++++++++-------
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c |   7 +-
>  2 files changed, 80 insertions(+), 47 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 7288065d2461..3418a3ed28fd 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -3225,11 +3225,8 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
>  {
>  	int port_clock = pll_state->use_c10 ? pll_state->c10.clock : pll_state->c20.clock;
>  	struct intel_display *display = to_intel_display(encoder);
> -	enum phy phy = intel_encoder_to_phy(encoder);
>  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>  	bool lane_reversal = dig_port->lane_reversal;
> -	u8 maxpclk_lane = lane_reversal ? INTEL_CX0_LANE1 :
> -					  INTEL_CX0_LANE0;
>  	struct ref_tracker *wakeref = intel_cx0_phy_transaction_begin(encoder);
>  
>  	/*
> @@ -3284,42 +3281,6 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
>  	 */
>  	intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), port_clock);
>  
> -	/*
> -	 * 9. Set PORT_CLOCK_CTL register PCLK PLL Request
> -	 * LN<Lane for maxPCLK> to "1" to enable PLL.
> -	 */
> -	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
> -		     intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES),
> -		     intel_cx0_get_pclk_pll_request(maxpclk_lane));
> -
> -	/* 10. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK> == "1". */
> -	if (intel_de_wait_us(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
> -			     intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES),
> -			     intel_cx0_get_pclk_pll_ack(maxpclk_lane),
> -			     XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US, NULL))
> -		drm_warn(display->drm, "Port %c PLL not locked\n",
> -			 phy_name(phy));
> -
> -	/*
> -	 * 11. Follow the Display Voltage Frequency Switching Sequence After
> -	 * Frequency Change. We handle this step in bxt_set_cdclk().
> -	 */
> -
> -	/*
> -	 * 12. Toggle powerdown if HDMI is enabled on C10 PHY.
> -	 *
> -	 * Wa_13013502646:
> -	 * Fixes: HDMI lane to lane skew violations on C10 display PHYs.
> -	 * Workaround: Toggle powerdown value by setting first to P0 and then to P2, for both
> -	 * PHY lanes.
> -	 */
> -	if (!cx0pll_state_is_dp(pll_state) && pll_state->use_c10) {
> -		intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES,
> -						    XELPDP_P0_STATE_ACTIVE);
> -		intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES,
> -						    XELPDP_P2_STATE_READY);
> -	}
> -
>  	intel_cx0_phy_transaction_end(encoder, wakeref);
>  }
>  
> @@ -3403,6 +3364,56 @@ static int intel_mtl_tbt_clock_select(struct intel_display *display,
>  	}
>  }
>  
> +static void intel_cx0pll_enable_clock(struct intel_encoder *encoder,
> +				      const struct intel_cx0pll_state *pll_state)
> +{
> +	struct intel_display *display = to_intel_display(encoder);
> +	enum phy phy = intel_encoder_to_phy(encoder);
> +	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> +	bool lane_reversal = dig_port->lane_reversal;
> +	u8 maxpclk_lane = lane_reversal ? INTEL_CX0_LANE1 :
> +					  INTEL_CX0_LANE0;
> +	struct ref_tracker *wakeref = intel_cx0_phy_transaction_begin(encoder);
> +
> +	/*
> +	 * 9. Set PORT_CLOCK_CTL register PCLK PLL Request
> +	 * LN<Lane for maxPCLK> to "1" to enable PLL.
> +	 */
> +	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
> +		     intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES),
> +		     intel_cx0_get_pclk_pll_request(maxpclk_lane));
> +
> +	/* 10. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK> == "1". */
> +	if (intel_de_wait_us(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
> +			     intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES),
> +			     intel_cx0_get_pclk_pll_ack(maxpclk_lane),
> +			     XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US, NULL))
> +		drm_warn(display->drm, "Port %c PLL not locked\n",
> +			 phy_name(phy));
> +
> +	/*
> +	 * 11. Follow the Display Voltage Frequency Switching Sequence After
> +	 * Frequency Change. We handle this step in bxt_set_cdclk().
> +	 */
> +
> +	/*
> +	 * 12. Toggle powerdown if HDMI is enabled on C10 PHY.
> +	 *
> +	 * Wa_13013502646:
> +	 * Fixes: HDMI lane to lane skew violations on C10 display PHYs.
> +	 * Workaround: Toggle powerdown value by setting first to P0 and then to P2, for both
> +	 * PHY lanes.
> +	 */
> +	if (!cx0pll_state_is_dp(pll_state) && pll_state->use_c10) {
> +		intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES,
> +						    XELPDP_P0_STATE_ACTIVE);
> +		intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES,
> +						    XELPDP_P2_STATE_READY);
> +	}
> +
> +	intel_cx0_phy_transaction_end(encoder, wakeref);
> +}
> +
>  void intel_mtl_tbt_pll_enable_clock(struct intel_encoder *encoder, int port_clock)
>  {
>  	struct intel_display *display = to_intel_display(encoder);
> @@ -3468,10 +3479,16 @@ void intel_mtl_pll_enable(struct intel_encoder *encoder,
>  void intel_mtl_pll_enable_clock(struct intel_encoder *encoder,
>  				const struct intel_crtc_state *crtc_state)
>  {
> +	struct intel_display *display = to_intel_display(encoder);
> +	struct intel_dpll *pll = crtc_state->intel_dpll;
>  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>  
>  	if (intel_tc_port_in_tbt_alt_mode(dig_port))
>  		intel_mtl_tbt_pll_enable_clock(encoder, crtc_state->port_clock);
> +	else
> +		intel_cx0pll_enable_clock(encoder, &crtc_state->dpll_hw_state.cx0pll);
> +
> +	assert_dpll_enabled(display, pll);
>  }
>  
>  /*
> @@ -3567,12 +3584,6 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder)
>  	 * Frequency Change. We handle this step in bxt_set_cdclk().
>  	 */
>  
> -	/* 7. Program PORT_CLOCK_CTL register to disable and gate clocks. */
> -	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
> -		     XELPDP_DDI_CLOCK_SELECT_MASK(display), 0);
> -	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
> -		     XELPDP_FORWARD_CLOCK_UNGATE, 0);
> -
>  	intel_cx0_phy_transaction_end(encoder, wakeref);
>  }
>  
> @@ -3586,6 +3597,20 @@ static bool intel_cx0_pll_is_enabled(struct intel_encoder *encoder)
>  			     intel_cx0_get_pclk_pll_request(lane);
>  }
>  
> +static void intel_cx0pll_disable_clock(struct intel_encoder *encoder)
> +{
> +	struct intel_display *display = to_intel_display(encoder);
> +	struct ref_tracker *wakeref = intel_cx0_phy_transaction_begin(encoder);
> +
> +	/* 7. Program PORT_CLOCK_CTL register to disable and gate clocks. */
> +	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
> +		     XELPDP_DDI_CLOCK_SELECT_MASK(display), 0);
> +	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
> +		     XELPDP_FORWARD_CLOCK_UNGATE, 0);
> +
> +	intel_cx0_phy_transaction_end(encoder, wakeref);

During a modeset disable sequence encoder::disable_clock() is called
first and only afterwards intel_dpll_funcs::disable() is called. So the
above will incorrectly reorder the clearing of the clock-select and
forward-clock-ungate flags wrt. the rest of the steps
intel_cx0pll_disable(), i.e. not matching now bspec at all.

> +}
> +
>  void intel_mtl_tbt_pll_disable_clock(struct intel_encoder *encoder)
>  {
>  	struct intel_display *display = to_intel_display(encoder);
> @@ -3635,6 +3660,9 @@ void intel_mtl_pll_disable_clock(struct intel_encoder *encoder)
>  
>  	if (intel_tc_port_in_tbt_alt_mode(dig_port))
>  		intel_mtl_tbt_pll_disable_clock(encoder);
> +	else
> +		intel_cx0pll_disable_clock(encoder);
> +
>  }
>  
>  enum icl_port_dpll_id
> @@ -3783,6 +3811,8 @@ void intel_cx0_pll_power_save_wa(struct intel_display *display)
>  			    encoder->base.base.id, encoder->base.name);
>  
>  		intel_cx0pll_enable(encoder, &pll_state);
> +		intel_cx0pll_enable_clock(encoder, &pll_state);
>  		intel_cx0pll_disable(encoder);
> +		intel_cx0pll_disable_clock(encoder);
>  	}
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 9aa84a430f09..040c97d81302 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -298,7 +298,8 @@ void intel_dpll_enable(const struct intel_crtc_state *crtc_state)
>  
>  	if (old_mask) {
>  		drm_WARN_ON(display->drm, !pll->on);
> -		assert_dpll_enabled(display, pll);
> +		if (DISPLAY_VER(display) < 14)
> +			assert_dpll_enabled(display, pll);
>  		goto out;
>  	}
>  	drm_WARN_ON(display->drm, pll->on);
> @@ -342,7 +343,9 @@ void intel_dpll_disable(const struct intel_crtc_state *crtc_state)
>  		    pll->info->name, pll->active_mask, pll->on,
>  		    crtc->base.base.id, crtc->base.name);
>  
> -	assert_dpll_enabled(display, pll);
> +	if (DISPLAY_VER(display) < 14)
> +		assert_dpll_enabled(display, pll);
> +
>  	drm_WARN_ON(display->drm, !pll->on);
>  
>  	pll->active_mask &= ~pipe_mask;
> -- 
> 2.34.1
> 

[PATCH v2 2/3] drm/i915/cx0: Clear response ready & error bit

[Suraj Kandpal]

Clear the response ready and error bit of PORT_P2M_MESSAGE_BUS_STATUS
before writing the transaction pending bit of
PORT_M2P_MSGBUS_CTL as that is a hard requirement. If not done
we find that the PHY hangs since it ends up in a weird state if left
idle for more than 1 hour.

Bspec: 65101
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Reviewed-by: Michał Grzelak <michal.grzelak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 3418a3ed28fd..00c7fa9040ee 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -222,6 +222,8 @@ static int __intel_cx0_read_once(struct intel_encoder *encoder,
 		return -ETIMEDOUT;
 	}
 
+	intel_clear_response_ready_flag(encoder, lane);
+
 	intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
 		       XELPDP_PORT_M2P_TRANSACTION_PENDING |
 		       XELPDP_PORT_M2P_COMMAND_READ |
@@ -293,6 +295,8 @@ static int __intel_cx0_write_once(struct intel_encoder *encoder,
 		return -ETIMEDOUT;
 	}
 
+	intel_clear_response_ready_flag(encoder, lane);
+
 	intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
 		       XELPDP_PORT_M2P_TRANSACTION_PENDING |
 		       (committed ? XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED :
-- 
2.34.1

[PATCH v2 3/3] drm/i915/cx0: Rename intel_clear_response_ready flag

[Suraj Kandpal]

Rename the non static intel_clear_response_ready_flag to
intel_cx0_clear_response_ready_flag so that we follow the
naming standards of non static function.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 14 +++++++-------
 drivers/gpu/drm/i915/display/intel_cx0_phy.h |  4 ++--
 drivers/gpu/drm/i915/display/intel_lt_phy.c  |  2 +-
 3 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 00c7fa9040ee..716b5108b4c4 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -127,8 +127,8 @@ static void intel_cx0_phy_transaction_end(struct intel_encoder *encoder, struct
 	intel_display_power_put(display, POWER_DOMAIN_DC_OFF, wakeref);
 }
 
-void intel_clear_response_ready_flag(struct intel_encoder *encoder,
-				     int lane)
+void intel_cx0_clear_response_ready_flag(struct intel_encoder *encoder,
+					 int lane)
 {
 	struct intel_display *display = to_intel_display(encoder);
 
@@ -155,7 +155,7 @@ void intel_cx0_bus_reset(struct intel_encoder *encoder, int lane)
 		return;
 	}
 
-	intel_clear_response_ready_flag(encoder, lane);
+	intel_cx0_clear_response_ready_flag(encoder, lane);
 }
 
 int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
@@ -222,7 +222,7 @@ static int __intel_cx0_read_once(struct intel_encoder *encoder,
 		return -ETIMEDOUT;
 	}
 
-	intel_clear_response_ready_flag(encoder, lane);
+	intel_cx0_clear_response_ready_flag(encoder, lane);
 
 	intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
 		       XELPDP_PORT_M2P_TRANSACTION_PENDING |
@@ -233,7 +233,7 @@ static int __intel_cx0_read_once(struct intel_encoder *encoder,
 	if (ack < 0)
 		return ack;
 
-	intel_clear_response_ready_flag(encoder, lane);
+	intel_cx0_clear_response_ready_flag(encoder, lane);
 
 	/*
 	 * FIXME: Workaround to let HW to settle
@@ -295,7 +295,7 @@ static int __intel_cx0_write_once(struct intel_encoder *encoder,
 		return -ETIMEDOUT;
 	}
 
-	intel_clear_response_ready_flag(encoder, lane);
+	intel_cx0_clear_response_ready_flag(encoder, lane);
 
 	intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
 		       XELPDP_PORT_M2P_TRANSACTION_PENDING |
@@ -325,7 +325,7 @@ static int __intel_cx0_write_once(struct intel_encoder *encoder,
 		return -EINVAL;
 	}
 
-	intel_clear_response_ready_flag(encoder, lane);
+	intel_cx0_clear_response_ready_flag(encoder, lane);
 
 	/*
 	 * FIXME: Workaround to let HW to settle
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index ae98ac23ea22..87d3bdaca3ec 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -25,8 +25,8 @@ struct intel_dpll_hw_state;
 struct intel_encoder;
 struct intel_hdmi;
 
-void intel_clear_response_ready_flag(struct intel_encoder *encoder,
-				     int lane);
+void intel_cx0_clear_response_ready_flag(struct intel_encoder *encoder,
+					 int lane);
 bool intel_encoder_is_c10phy(struct intel_encoder *encoder);
 void intel_mtl_pll_enable(struct intel_encoder *encoder,
 			  struct intel_dpll *pll,
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 6cdae03ee172..e174ca011d50 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -1106,7 +1106,7 @@ static int __intel_lt_phy_p2p_write_once(struct intel_encoder *encoder,
 	 * This is the time PHY takes to settle down after programming the PHY.
 	 */
 	udelay(150);
-	intel_clear_response_ready_flag(encoder, lane);
+	intel_cx0_clear_response_ready_flag(encoder, lane);
 	intel_lt_phy_clear_status_p2p(encoder, lane);
 
 	return 0;
-- 
2.34.1

RE: [PATCH v2 3/3] drm/i915/cx0: Rename intel_clear_response_ready flag

[Garg, Nemesa]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Suraj
> Kandpal
> Sent: Wednesday, January 14, 2026 9:13 AM
> To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Kandpal, Suraj
> <suraj.kandpal@intel.com>
> Subject: [PATCH v2 3/3] drm/i915/cx0: Rename intel_clear_response_ready
> flag
> 
> Rename the non static intel_clear_response_ready_flag to
> intel_cx0_clear_response_ready_flag so that we follow the naming standards
> of non static function.
> 
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 14 +++++++-------
> drivers/gpu/drm/i915/display/intel_cx0_phy.h |  4 ++--
> drivers/gpu/drm/i915/display/intel_lt_phy.c  |  2 +-
>  3 files changed, 10 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 00c7fa9040ee..716b5108b4c4 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -127,8 +127,8 @@ static void intel_cx0_phy_transaction_end(struct
> intel_encoder *encoder, struct
>  	intel_display_power_put(display, POWER_DOMAIN_DC_OFF,
> wakeref);  }
> 
> -void intel_clear_response_ready_flag(struct intel_encoder *encoder,
> -				     int lane)
> +void intel_cx0_clear_response_ready_flag(struct intel_encoder *encoder,
> +					 int lane)
>  {
>  	struct intel_display *display = to_intel_display(encoder);
> 
> @@ -155,7 +155,7 @@ void intel_cx0_bus_reset(struct intel_encoder
> *encoder, int lane)
>  		return;
>  	}
> 
> -	intel_clear_response_ready_flag(encoder, lane);
> +	intel_cx0_clear_response_ready_flag(encoder, lane);
>  }
> 
>  int intel_cx0_wait_for_ack(struct intel_encoder *encoder, @@ -222,7 +222,7
> @@ static int __intel_cx0_read_once(struct intel_encoder *encoder,
>  		return -ETIMEDOUT;
>  	}
> 
> -	intel_clear_response_ready_flag(encoder, lane);
> +	intel_cx0_clear_response_ready_flag(encoder, lane);
> 
>  	intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display,
> port, lane),
>  		       XELPDP_PORT_M2P_TRANSACTION_PENDING | @@ -
> 233,7 +233,7 @@ static int __intel_cx0_read_once(struct intel_encoder
> *encoder,
>  	if (ack < 0)
>  		return ack;
> 
> -	intel_clear_response_ready_flag(encoder, lane);
> +	intel_cx0_clear_response_ready_flag(encoder, lane);
> 
>  	/*
>  	 * FIXME: Workaround to let HW to settle @@ -295,7 +295,7 @@
> static int __intel_cx0_write_once(struct intel_encoder *encoder,
>  		return -ETIMEDOUT;
>  	}
> 
> -	intel_clear_response_ready_flag(encoder, lane);
> +	intel_cx0_clear_response_ready_flag(encoder, lane);
> 
>  	intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display,
> port, lane),
>  		       XELPDP_PORT_M2P_TRANSACTION_PENDING | @@ -
> 325,7 +325,7 @@ static int __intel_cx0_write_once(struct intel_encoder
> *encoder,
>  		return -EINVAL;
>  	}
> 
> -	intel_clear_response_ready_flag(encoder, lane);
> +	intel_cx0_clear_response_ready_flag(encoder, lane);
> 
>  	/*
>  	 * FIXME: Workaround to let HW to settle diff --git
> a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> index ae98ac23ea22..87d3bdaca3ec 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> @@ -25,8 +25,8 @@ struct intel_dpll_hw_state;  struct intel_encoder;  struct
> intel_hdmi;
> 
> -void intel_clear_response_ready_flag(struct intel_encoder *encoder,
> -				     int lane);
> +void intel_cx0_clear_response_ready_flag(struct intel_encoder *encoder,
> +					 int lane);
>  bool intel_encoder_is_c10phy(struct intel_encoder *encoder);  void
> intel_mtl_pll_enable(struct intel_encoder *encoder,
>  			  struct intel_dpll *pll,
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 6cdae03ee172..e174ca011d50 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -1106,7 +1106,7 @@ static int __intel_lt_phy_p2p_write_once(struct
> intel_encoder *encoder,
>  	 * This is the time PHY takes to settle down after programming the
> PHY.
>  	 */
>  	udelay(150);
> -	intel_clear_response_ready_flag(encoder, lane);
> +	intel_cx0_clear_response_ready_flag(encoder, lane);
>  	intel_lt_phy_clear_status_p2p(encoder, lane);
> 
>  	return 0;
> --
LGTM,
Reviewed-by: Nemesa Garg <nemesa.garg@intel.com>
> 2.34.1

✓ CI.KUnit: success for Fix Cx0 Suspend Resume issue (rev2)

[Patchwork]

== Series Details ==

Series: Fix Cx0 Suspend Resume issue (rev2)
URL   : https://patchwork.freedesktop.org/series/159539/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[04:34:14] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[04:34:19] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[04:34:50] Starting KUnit Kernel (1/1)...
[04:34:50] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[04:34:50] ================== guc_buf (11 subtests) ===================
[04:34:50] [PASSED] test_smallest
[04:34:50] [PASSED] test_largest
[04:34:50] [PASSED] test_granular
[04:34:50] [PASSED] test_unique
[04:34:50] [PASSED] test_overlap
[04:34:50] [PASSED] test_reusable
[04:34:50] [PASSED] test_too_big
[04:34:50] [PASSED] test_flush
[04:34:50] [PASSED] test_lookup
[04:34:50] [PASSED] test_data
[04:34:50] [PASSED] test_class
[04:34:50] ===================== [PASSED] guc_buf =====================
[04:34:50] =================== guc_dbm (7 subtests) ===================
[04:34:50] [PASSED] test_empty
[04:34:50] [PASSED] test_default
[04:34:50] ======================== test_size  ========================
[04:34:50] [PASSED] 4
[04:34:50] [PASSED] 8
[04:34:50] [PASSED] 32
[04:34:50] [PASSED] 256
[04:34:50] ==================== [PASSED] test_size ====================
[04:34:50] ======================= test_reuse  ========================
[04:34:50] [PASSED] 4
[04:34:50] [PASSED] 8
[04:34:50] [PASSED] 32
[04:34:50] [PASSED] 256
[04:34:50] =================== [PASSED] test_reuse ====================
[04:34:50] =================== test_range_overlap  ====================
[04:34:50] [PASSED] 4
[04:34:50] [PASSED] 8
[04:34:50] [PASSED] 32
[04:34:50] [PASSED] 256
[04:34:50] =============== [PASSED] test_range_overlap ================
[04:34:50] =================== test_range_compact  ====================
[04:34:50] [PASSED] 4
[04:34:50] [PASSED] 8
[04:34:50] [PASSED] 32
[04:34:50] [PASSED] 256
[04:34:50] =============== [PASSED] test_range_compact ================
[04:34:50] ==================== test_range_spare  =====================
[04:34:50] [PASSED] 4
[04:34:50] [PASSED] 8
[04:34:50] [PASSED] 32
[04:34:50] [PASSED] 256
[04:34:50] ================ [PASSED] test_range_spare =================
[04:34:50] ===================== [PASSED] guc_dbm =====================
[04:34:50] =================== guc_idm (6 subtests) ===================
[04:34:50] [PASSED] bad_init
[04:34:50] [PASSED] no_init
[04:34:50] [PASSED] init_fini
[04:34:50] [PASSED] check_used
[04:34:51] [PASSED] check_quota
[04:34:51] [PASSED] check_all
[04:34:51] ===================== [PASSED] guc_idm =====================
[04:34:51] ================== no_relay (3 subtests) ===================
[04:34:51] [PASSED] xe_drops_guc2pf_if_not_ready
[04:34:51] [PASSED] xe_drops_guc2vf_if_not_ready
[04:34:51] [PASSED] xe_rejects_send_if_not_ready
[04:34:51] ==================== [PASSED] no_relay =====================
[04:34:51] ================== pf_relay (14 subtests) ==================
[04:34:51] [PASSED] pf_rejects_guc2pf_too_short
[04:34:51] [PASSED] pf_rejects_guc2pf_too_long
[04:34:51] [PASSED] pf_rejects_guc2pf_no_payload
[04:34:51] [PASSED] pf_fails_no_payload
[04:34:51] [PASSED] pf_fails_bad_origin
[04:34:51] [PASSED] pf_fails_bad_type
[04:34:51] [PASSED] pf_txn_reports_error
[04:34:51] [PASSED] pf_txn_sends_pf2guc
[04:34:51] [PASSED] pf_sends_pf2guc
[04:34:51] [SKIPPED] pf_loopback_nop
[04:34:51] [SKIPPED] pf_loopback_echo
[04:34:51] [SKIPPED] pf_loopback_fail
[04:34:51] [SKIPPED] pf_loopback_busy
[04:34:51] [SKIPPED] pf_loopback_retry
[04:34:51] ==================== [PASSED] pf_relay =====================
[04:34:51] ================== vf_relay (3 subtests) ===================
[04:34:51] [PASSED] vf_rejects_guc2vf_too_short
[04:34:51] [PASSED] vf_rejects_guc2vf_too_long
[04:34:51] [PASSED] vf_rejects_guc2vf_no_payload
[04:34:51] ==================== [PASSED] vf_relay =====================
[04:34:51] ================ pf_gt_config (6 subtests) =================
[04:34:51] [PASSED] fair_contexts_1vf
[04:34:51] [PASSED] fair_doorbells_1vf
[04:34:51] [PASSED] fair_ggtt_1vf
[04:34:51] ====================== fair_contexts  ======================
[04:34:51] [PASSED] 1 VF
[04:34:51] [PASSED] 2 VFs
[04:34:51] [PASSED] 3 VFs
[04:34:51] [PASSED] 4 VFs
[04:34:51] [PASSED] 5 VFs
[04:34:51] [PASSED] 6 VFs
[04:34:51] [PASSED] 7 VFs
[04:34:51] [PASSED] 8 VFs
[04:34:51] [PASSED] 9 VFs
[04:34:51] [PASSED] 10 VFs
[04:34:51] [PASSED] 11 VFs
[04:34:51] [PASSED] 12 VFs
[04:34:51] [PASSED] 13 VFs
[04:34:51] [PASSED] 14 VFs
[04:34:51] [PASSED] 15 VFs
[04:34:51] [PASSED] 16 VFs
[04:34:51] [PASSED] 17 VFs
[04:34:51] [PASSED] 18 VFs
[04:34:51] [PASSED] 19 VFs
[04:34:51] [PASSED] 20 VFs
[04:34:51] [PASSED] 21 VFs
[04:34:51] [PASSED] 22 VFs
[04:34:51] [PASSED] 23 VFs
[04:34:51] [PASSED] 24 VFs
[04:34:51] [PASSED] 25 VFs
[04:34:51] [PASSED] 26 VFs
[04:34:51] [PASSED] 27 VFs
[04:34:51] [PASSED] 28 VFs
[04:34:51] [PASSED] 29 VFs
[04:34:51] [PASSED] 30 VFs
[04:34:51] [PASSED] 31 VFs
[04:34:51] [PASSED] 32 VFs
[04:34:51] [PASSED] 33 VFs
[04:34:51] [PASSED] 34 VFs
[04:34:51] [PASSED] 35 VFs
[04:34:51] [PASSED] 36 VFs
[04:34:51] [PASSED] 37 VFs
[04:34:51] [PASSED] 38 VFs
[04:34:51] [PASSED] 39 VFs
[04:34:51] [PASSED] 40 VFs
[04:34:51] [PASSED] 41 VFs
[04:34:51] [PASSED] 42 VFs
[04:34:51] [PASSED] 43 VFs
[04:34:51] [PASSED] 44 VFs
[04:34:51] [PASSED] 45 VFs
[04:34:51] [PASSED] 46 VFs
[04:34:51] [PASSED] 47 VFs
[04:34:51] [PASSED] 48 VFs
[04:34:51] [PASSED] 49 VFs
[04:34:51] [PASSED] 50 VFs
[04:34:51] [PASSED] 51 VFs
[04:34:51] [PASSED] 52 VFs
[04:34:51] [PASSED] 53 VFs
[04:34:51] [PASSED] 54 VFs
[04:34:51] [PASSED] 55 VFs
[04:34:51] [PASSED] 56 VFs
[04:34:51] [PASSED] 57 VFs
[04:34:51] [PASSED] 58 VFs
[04:34:51] [PASSED] 59 VFs
[04:34:51] [PASSED] 60 VFs
[04:34:51] [PASSED] 61 VFs
[04:34:51] [PASSED] 62 VFs
[04:34:51] [PASSED] 63 VFs
[04:34:51] ================== [PASSED] fair_contexts ==================
[04:34:51] ===================== fair_doorbells  ======================
[04:34:51] [PASSED] 1 VF
[04:34:51] [PASSED] 2 VFs
[04:34:51] [PASSED] 3 VFs
[04:34:51] [PASSED] 4 VFs
[04:34:51] [PASSED] 5 VFs
[04:34:51] [PASSED] 6 VFs
[04:34:51] [PASSED] 7 VFs
[04:34:51] [PASSED] 8 VFs
[04:34:51] [PASSED] 9 VFs
[04:34:51] [PASSED] 10 VFs
[04:34:51] [PASSED] 11 VFs
[04:34:51] [PASSED] 12 VFs
[04:34:51] [PASSED] 13 VFs
[04:34:51] [PASSED] 14 VFs
[04:34:51] [PASSED] 15 VFs
[04:34:51] [PASSED] 16 VFs
[04:34:51] [PASSED] 17 VFs
[04:34:51] [PASSED] 18 VFs
[04:34:51] [PASSED] 19 VFs
[04:34:51] [PASSED] 20 VFs
[04:34:51] [PASSED] 21 VFs
[04:34:51] [PASSED] 22 VFs
[04:34:51] [PASSED] 23 VFs
[04:34:51] [PASSED] 24 VFs
[04:34:51] [PASSED] 25 VFs
[04:34:51] [PASSED] 26 VFs
[04:34:51] [PASSED] 27 VFs
[04:34:51] [PASSED] 28 VFs
[04:34:51] [PASSED] 29 VFs
[04:34:51] [PASSED] 30 VFs
[04:34:51] [PASSED] 31 VFs
[04:34:51] [PASSED] 32 VFs
[04:34:51] [PASSED] 33 VFs
[04:34:51] [PASSED] 34 VFs
[04:34:51] [PASSED] 35 VFs
[04:34:51] [PASSED] 36 VFs
[04:34:51] [PASSED] 37 VFs
[04:34:51] [PASSED] 38 VFs
[04:34:51] [PASSED] 39 VFs
[04:34:51] [PASSED] 40 VFs
[04:34:51] [PASSED] 41 VFs
[04:34:51] [PASSED] 42 VFs
[04:34:51] [PASSED] 43 VFs
[04:34:51] [PASSED] 44 VFs
[04:34:51] [PASSED] 45 VFs
[04:34:51] [PASSED] 46 VFs
[04:34:51] [PASSED] 47 VFs
[04:34:51] [PASSED] 48 VFs
[04:34:51] [PASSED] 49 VFs
[04:34:51] [PASSED] 50 VFs
[04:34:51] [PASSED] 51 VFs
[04:34:51] [PASSED] 52 VFs
[04:34:51] [PASSED] 53 VFs
[04:34:51] [PASSED] 54 VFs
[04:34:51] [PASSED] 55 VFs
[04:34:51] [PASSED] 56 VFs
[04:34:51] [PASSED] 57 VFs
[04:34:51] [PASSED] 58 VFs
[04:34:51] [PASSED] 59 VFs
[04:34:51] [PASSED] 60 VFs
[04:34:51] [PASSED] 61 VFs
[04:34:51] [PASSED] 62 VFs
[04:34:51] [PASSED] 63 VFs
[04:34:51] ================= [PASSED] fair_doorbells ==================
[04:34:51] ======================== fair_ggtt  ========================
[04:34:51] [PASSED] 1 VF
[04:34:51] [PASSED] 2 VFs
[04:34:51] [PASSED] 3 VFs
[04:34:51] [PASSED] 4 VFs
[04:34:51] [PASSED] 5 VFs
[04:34:51] [PASSED] 6 VFs
[04:34:51] [PASSED] 7 VFs
[04:34:51] [PASSED] 8 VFs
[04:34:51] [PASSED] 9 VFs
[04:34:51] [PASSED] 10 VFs
[04:34:51] [PASSED] 11 VFs
[04:34:51] [PASSED] 12 VFs
[04:34:51] [PASSED] 13 VFs
[04:34:51] [PASSED] 14 VFs
[04:34:51] [PASSED] 15 VFs
[04:34:51] [PASSED] 16 VFs
[04:34:51] [PASSED] 17 VFs
[04:34:51] [PASSED] 18 VFs
[04:34:51] [PASSED] 19 VFs
[04:34:51] [PASSED] 20 VFs
[04:34:51] [PASSED] 21 VFs
[04:34:51] [PASSED] 22 VFs
[04:34:51] [PASSED] 23 VFs
[04:34:51] [PASSED] 24 VFs
[04:34:51] [PASSED] 25 VFs
[04:34:51] [PASSED] 26 VFs
[04:34:51] [PASSED] 27 VFs
[04:34:51] [PASSED] 28 VFs
[04:34:51] [PASSED] 29 VFs
[04:34:51] [PASSED] 30 VFs
[04:34:51] [PASSED] 31 VFs
[04:34:51] [PASSED] 32 VFs
[04:34:51] [PASSED] 33 VFs
[04:34:51] [PASSED] 34 VFs
[04:34:51] [PASSED] 35 VFs
[04:34:51] [PASSED] 36 VFs
[04:34:51] [PASSED] 37 VFs
[04:34:51] [PASSED] 38 VFs
[04:34:51] [PASSED] 39 VFs
[04:34:51] [PASSED] 40 VFs
[04:34:51] [PASSED] 41 VFs
[04:34:51] [PASSED] 42 VFs
[04:34:51] [PASSED] 43 VFs
[04:34:51] [PASSED] 44 VFs
[04:34:51] [PASSED] 45 VFs
[04:34:51] [PASSED] 46 VFs
[04:34:51] [PASSED] 47 VFs
[04:34:51] [PASSED] 48 VFs
[04:34:51] [PASSED] 49 VFs
[04:34:51] [PASSED] 50 VFs
[04:34:51] [PASSED] 51 VFs
[04:34:51] [PASSED] 52 VFs
[04:34:51] [PASSED] 53 VFs
[04:34:51] [PASSED] 54 VFs
[04:34:51] [PASSED] 55 VFs
[04:34:51] [PASSED] 56 VFs
[04:34:51] [PASSED] 57 VFs
[04:34:51] [PASSED] 58 VFs
[04:34:51] [PASSED] 59 VFs
[04:34:51] [PASSED] 60 VFs
[04:34:51] [PASSED] 61 VFs
[04:34:51] [PASSED] 62 VFs
[04:34:51] [PASSED] 63 VFs
[04:34:51] ==================== [PASSED] fair_ggtt ====================
[04:34:51] ================== [PASSED] pf_gt_config ===================
[04:34:51] ===================== lmtt (1 subtest) =====================
[04:34:51] ======================== test_ops  =========================
[04:34:51] [PASSED] 2-level
[04:34:51] [PASSED] multi-level
[04:34:51] ==================== [PASSED] test_ops =====================
[04:34:51] ====================== [PASSED] lmtt =======================
[04:34:51] ================= pf_service (11 subtests) =================
[04:34:51] [PASSED] pf_negotiate_any
[04:34:51] [PASSED] pf_negotiate_base_match
[04:34:51] [PASSED] pf_negotiate_base_newer
[04:34:51] [PASSED] pf_negotiate_base_next
[04:34:51] [SKIPPED] pf_negotiate_base_older
[04:34:51] [PASSED] pf_negotiate_base_prev
[04:34:51] [PASSED] pf_negotiate_latest_match
[04:34:51] [PASSED] pf_negotiate_latest_newer
[04:34:51] [PASSED] pf_negotiate_latest_next
[04:34:51] [SKIPPED] pf_negotiate_latest_older
[04:34:51] [SKIPPED] pf_negotiate_latest_prev
[04:34:51] =================== [PASSED] pf_service ====================
[04:34:51] ================= xe_guc_g2g (2 subtests) ==================
[04:34:51] ============== xe_live_guc_g2g_kunit_default  ==============
[04:34:51] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[04:34:51] ============== xe_live_guc_g2g_kunit_allmem  ===============
[04:34:51] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[04:34:51] =================== [SKIPPED] xe_guc_g2g ===================
[04:34:51] =================== xe_mocs (2 subtests) ===================
[04:34:51] ================ xe_live_mocs_kernel_kunit  ================
[04:34:51] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[04:34:51] ================ xe_live_mocs_reset_kunit  =================
[04:34:51] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[04:34:51] ==================== [SKIPPED] xe_mocs =====================
[04:34:51] ================= xe_migrate (2 subtests) ==================
[04:34:51] ================= xe_migrate_sanity_kunit  =================
[04:34:51] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[04:34:51] ================== xe_validate_ccs_kunit  ==================
[04:34:51] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[04:34:51] =================== [SKIPPED] xe_migrate ===================
[04:34:51] ================== xe_dma_buf (1 subtest) ==================
[04:34:51] ==================== xe_dma_buf_kunit  =====================
[04:34:51] ================ [SKIPPED] xe_dma_buf_kunit ================
[04:34:51] =================== [SKIPPED] xe_dma_buf ===================
[04:34:51] ================= xe_bo_shrink (1 subtest) =================
[04:34:51] =================== xe_bo_shrink_kunit  ====================
[04:34:51] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[04:34:51] ================== [SKIPPED] xe_bo_shrink ==================
[04:34:51] ==================== xe_bo (2 subtests) ====================
[04:34:51] ================== xe_ccs_migrate_kunit  ===================
[04:34:51] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[04:34:51] ==================== xe_bo_evict_kunit  ====================
[04:34:51] =============== [SKIPPED] xe_bo_evict_kunit ================
[04:34:51] ===================== [SKIPPED] xe_bo ======================
[04:34:51] ==================== args (13 subtests) ====================
[04:34:51] [PASSED] count_args_test
[04:34:51] [PASSED] call_args_example
[04:34:51] [PASSED] call_args_test
[04:34:51] [PASSED] drop_first_arg_example
[04:34:51] [PASSED] drop_first_arg_test
[04:34:51] [PASSED] first_arg_example
[04:34:51] [PASSED] first_arg_test
[04:34:51] [PASSED] last_arg_example
[04:34:51] [PASSED] last_arg_test
[04:34:51] [PASSED] pick_arg_example
[04:34:51] [PASSED] if_args_example
[04:34:51] [PASSED] if_args_test
[04:34:51] [PASSED] sep_comma_example
[04:34:51] ====================== [PASSED] args =======================
[04:34:51] =================== xe_pci (3 subtests) ====================
[04:34:51] ==================== check_graphics_ip  ====================
[04:34:51] [PASSED] 12.00 Xe_LP
[04:34:51] [PASSED] 12.10 Xe_LP+
[04:34:51] [PASSED] 12.55 Xe_HPG
[04:34:51] [PASSED] 12.60 Xe_HPC
[04:34:51] [PASSED] 12.70 Xe_LPG
[04:34:51] [PASSED] 12.71 Xe_LPG
[04:34:51] [PASSED] 12.74 Xe_LPG+
[04:34:51] [PASSED] 20.01 Xe2_HPG
[04:34:51] [PASSED] 20.02 Xe2_HPG
[04:34:51] [PASSED] 20.04 Xe2_LPG
[04:34:51] [PASSED] 30.00 Xe3_LPG
[04:34:51] [PASSED] 30.01 Xe3_LPG
[04:34:51] [PASSED] 30.03 Xe3_LPG
[04:34:51] [PASSED] 30.04 Xe3_LPG
[04:34:51] [PASSED] 30.05 Xe3_LPG
[04:34:51] [PASSED] 35.11 Xe3p_XPC
[04:34:51] ================ [PASSED] check_graphics_ip ================
[04:34:51] ===================== check_media_ip  ======================
[04:34:51] [PASSED] 12.00 Xe_M
[04:34:51] [PASSED] 12.55 Xe_HPM
[04:34:51] [PASSED] 13.00 Xe_LPM+
[04:34:51] [PASSED] 13.01 Xe2_HPM
[04:34:51] [PASSED] 20.00 Xe2_LPM
[04:34:51] [PASSED] 30.00 Xe3_LPM
[04:34:51] [PASSED] 30.02 Xe3_LPM
[04:34:51] [PASSED] 35.00 Xe3p_LPM
[04:34:51] [PASSED] 35.03 Xe3p_HPM
[04:34:51] ================= [PASSED] check_media_ip ==================
[04:34:51] =================== check_platform_desc  ===================
[04:34:51] [PASSED] 0x9A60 (TIGERLAKE)
[04:34:51] [PASSED] 0x9A68 (TIGERLAKE)
[04:34:51] [PASSED] 0x9A70 (TIGERLAKE)
[04:34:51] [PASSED] 0x9A40 (TIGERLAKE)
[04:34:51] [PASSED] 0x9A49 (TIGERLAKE)
[04:34:51] [PASSED] 0x9A59 (TIGERLAKE)
[04:34:51] [PASSED] 0x9A78 (TIGERLAKE)
[04:34:51] [PASSED] 0x9AC0 (TIGERLAKE)
[04:34:51] [PASSED] 0x9AC9 (TIGERLAKE)
[04:34:51] [PASSED] 0x9AD9 (TIGERLAKE)
[04:34:51] [PASSED] 0x9AF8 (TIGERLAKE)
[04:34:51] [PASSED] 0x4C80 (ROCKETLAKE)
[04:34:51] [PASSED] 0x4C8A (ROCKETLAKE)
[04:34:51] [PASSED] 0x4C8B (ROCKETLAKE)
[04:34:51] [PASSED] 0x4C8C (ROCKETLAKE)
[04:34:51] [PASSED] 0x4C90 (ROCKETLAKE)
[04:34:51] [PASSED] 0x4C9A (ROCKETLAKE)
[04:34:51] [PASSED] 0x4680 (ALDERLAKE_S)
[04:34:51] [PASSED] 0x4682 (ALDERLAKE_S)
[04:34:51] [PASSED] 0x4688 (ALDERLAKE_S)
[04:34:51] [PASSED] 0x468A (ALDERLAKE_S)
[04:34:51] [PASSED] 0x468B (ALDERLAKE_S)
[04:34:51] [PASSED] 0x4690 (ALDERLAKE_S)
[04:34:51] [PASSED] 0x4692 (ALDERLAKE_S)
[04:34:51] [PASSED] 0x4693 (ALDERLAKE_S)
[04:34:51] [PASSED] 0x46A0 (ALDERLAKE_P)
[04:34:51] [PASSED] 0x46A1 (ALDERLAKE_P)
[04:34:51] [PASSED] 0x46A2 (ALDERLAKE_P)
[04:34:51] [PASSED] 0x46A3 (ALDERLAKE_P)
[04:34:51] [PASSED] 0x46A6 (ALDERLAKE_P)
[04:34:51] [PASSED] 0x46A8 (ALDERLAKE_P)
[04:34:51] [PASSED] 0x46AA (ALDERLAKE_P)
[04:34:51] [PASSED] 0x462A (ALDERLAKE_P)
[04:34:51] [PASSED] 0x4626 (ALDERLAKE_P)
[04:34:51] [PASSED] 0x4628 (ALDERLAKE_P)
stty: 'standard input': Inappropriate ioctl for device
[04:34:51] [PASSED] 0x46B0 (ALDERLAKE_P)
[04:34:51] [PASSED] 0x46B1 (ALDERLAKE_P)
[04:34:51] [PASSED] 0x46B2 (ALDERLAKE_P)
[04:34:51] [PASSED] 0x46B3 (ALDERLAKE_P)
[04:34:51] [PASSED] 0x46C0 (ALDERLAKE_P)
[04:34:51] [PASSED] 0x46C1 (ALDERLAKE_P)
[04:34:51] [PASSED] 0x46C2 (ALDERLAKE_P)
[04:34:51] [PASSED] 0x46C3 (ALDERLAKE_P)
[04:34:51] [PASSED] 0x46D0 (ALDERLAKE_N)
[04:34:51] [PASSED] 0x46D1 (ALDERLAKE_N)
[04:34:51] [PASSED] 0x46D2 (ALDERLAKE_N)
[04:34:51] [PASSED] 0x46D3 (ALDERLAKE_N)
[04:34:51] [PASSED] 0x46D4 (ALDERLAKE_N)
[04:34:51] [PASSED] 0xA721 (ALDERLAKE_P)
[04:34:51] [PASSED] 0xA7A1 (ALDERLAKE_P)
[04:34:51] [PASSED] 0xA7A9 (ALDERLAKE_P)
[04:34:51] [PASSED] 0xA7AC (ALDERLAKE_P)
[04:34:51] [PASSED] 0xA7AD (ALDERLAKE_P)
[04:34:51] [PASSED] 0xA720 (ALDERLAKE_P)
[04:34:51] [PASSED] 0xA7A0 (ALDERLAKE_P)
[04:34:51] [PASSED] 0xA7A8 (ALDERLAKE_P)
[04:34:51] [PASSED] 0xA7AA (ALDERLAKE_P)
[04:34:51] [PASSED] 0xA7AB (ALDERLAKE_P)
[04:34:51] [PASSED] 0xA780 (ALDERLAKE_S)
[04:34:51] [PASSED] 0xA781 (ALDERLAKE_S)
[04:34:51] [PASSED] 0xA782 (ALDERLAKE_S)
[04:34:51] [PASSED] 0xA783 (ALDERLAKE_S)
[04:34:51] [PASSED] 0xA788 (ALDERLAKE_S)
[04:34:51] [PASSED] 0xA789 (ALDERLAKE_S)
[04:34:51] [PASSED] 0xA78A (ALDERLAKE_S)
[04:34:51] [PASSED] 0xA78B (ALDERLAKE_S)
[04:34:51] [PASSED] 0x4905 (DG1)
[04:34:51] [PASSED] 0x4906 (DG1)
[04:34:51] [PASSED] 0x4907 (DG1)
[04:34:51] [PASSED] 0x4908 (DG1)
[04:34:51] [PASSED] 0x4909 (DG1)
[04:34:51] [PASSED] 0x56C0 (DG2)
[04:34:51] [PASSED] 0x56C2 (DG2)
[04:34:51] [PASSED] 0x56C1 (DG2)
[04:34:51] [PASSED] 0x7D51 (METEORLAKE)
[04:34:51] [PASSED] 0x7DD1 (METEORLAKE)
[04:34:51] [PASSED] 0x7D41 (METEORLAKE)
[04:34:51] [PASSED] 0x7D67 (METEORLAKE)
[04:34:51] [PASSED] 0xB640 (METEORLAKE)
[04:34:51] [PASSED] 0x56A0 (DG2)
[04:34:51] [PASSED] 0x56A1 (DG2)
[04:34:51] [PASSED] 0x56A2 (DG2)
[04:34:51] [PASSED] 0x56BE (DG2)
[04:34:51] [PASSED] 0x56BF (DG2)
[04:34:51] [PASSED] 0x5690 (DG2)
[04:34:51] [PASSED] 0x5691 (DG2)
[04:34:51] [PASSED] 0x5692 (DG2)
[04:34:51] [PASSED] 0x56A5 (DG2)
[04:34:51] [PASSED] 0x56A6 (DG2)
[04:34:51] [PASSED] 0x56B0 (DG2)
[04:34:51] [PASSED] 0x56B1 (DG2)
[04:34:51] [PASSED] 0x56BA (DG2)
[04:34:51] [PASSED] 0x56BB (DG2)
[04:34:51] [PASSED] 0x56BC (DG2)
[04:34:51] [PASSED] 0x56BD (DG2)
[04:34:51] [PASSED] 0x5693 (DG2)
[04:34:51] [PASSED] 0x5694 (DG2)
[04:34:51] [PASSED] 0x5695 (DG2)
[04:34:51] [PASSED] 0x56A3 (DG2)
[04:34:51] [PASSED] 0x56A4 (DG2)
[04:34:51] [PASSED] 0x56B2 (DG2)
[04:34:51] [PASSED] 0x56B3 (DG2)
[04:34:51] [PASSED] 0x5696 (DG2)
[04:34:51] [PASSED] 0x5697 (DG2)
[04:34:51] [PASSED] 0xB69 (PVC)
[04:34:51] [PASSED] 0xB6E (PVC)
[04:34:51] [PASSED] 0xBD4 (PVC)
[04:34:51] [PASSED] 0xBD5 (PVC)
[04:34:51] [PASSED] 0xBD6 (PVC)
[04:34:51] [PASSED] 0xBD7 (PVC)
[04:34:51] [PASSED] 0xBD8 (PVC)
[04:34:51] [PASSED] 0xBD9 (PVC)
[04:34:51] [PASSED] 0xBDA (PVC)
[04:34:51] [PASSED] 0xBDB (PVC)
[04:34:51] [PASSED] 0xBE0 (PVC)
[04:34:51] [PASSED] 0xBE1 (PVC)
[04:34:51] [PASSED] 0xBE5 (PVC)
[04:34:51] [PASSED] 0x7D40 (METEORLAKE)
[04:34:51] [PASSED] 0x7D45 (METEORLAKE)
[04:34:51] [PASSED] 0x7D55 (METEORLAKE)
[04:34:51] [PASSED] 0x7D60 (METEORLAKE)
[04:34:51] [PASSED] 0x7DD5 (METEORLAKE)
[04:34:51] [PASSED] 0x6420 (LUNARLAKE)
[04:34:51] [PASSED] 0x64A0 (LUNARLAKE)
[04:34:51] [PASSED] 0x64B0 (LUNARLAKE)
[04:34:51] [PASSED] 0xE202 (BATTLEMAGE)
[04:34:51] [PASSED] 0xE209 (BATTLEMAGE)
[04:34:51] [PASSED] 0xE20B (BATTLEMAGE)
[04:34:51] [PASSED] 0xE20C (BATTLEMAGE)
[04:34:51] [PASSED] 0xE20D (BATTLEMAGE)
[04:34:51] [PASSED] 0xE210 (BATTLEMAGE)
[04:34:51] [PASSED] 0xE211 (BATTLEMAGE)
[04:34:51] [PASSED] 0xE212 (BATTLEMAGE)
[04:34:51] [PASSED] 0xE216 (BATTLEMAGE)
[04:34:51] [PASSED] 0xE220 (BATTLEMAGE)
[04:34:51] [PASSED] 0xE221 (BATTLEMAGE)
[04:34:51] [PASSED] 0xE222 (BATTLEMAGE)
[04:34:51] [PASSED] 0xE223 (BATTLEMAGE)
[04:34:51] [PASSED] 0xB080 (PANTHERLAKE)
[04:34:51] [PASSED] 0xB081 (PANTHERLAKE)
[04:34:51] [PASSED] 0xB082 (PANTHERLAKE)
[04:34:51] [PASSED] 0xB083 (PANTHERLAKE)
[04:34:51] [PASSED] 0xB084 (PANTHERLAKE)
[04:34:51] [PASSED] 0xB085 (PANTHERLAKE)
[04:34:51] [PASSED] 0xB086 (PANTHERLAKE)
[04:34:51] [PASSED] 0xB087 (PANTHERLAKE)
[04:34:51] [PASSED] 0xB08F (PANTHERLAKE)
[04:34:51] [PASSED] 0xB090 (PANTHERLAKE)
[04:34:51] [PASSED] 0xB0A0 (PANTHERLAKE)
[04:34:51] [PASSED] 0xB0B0 (PANTHERLAKE)
[04:34:51] [PASSED] 0xFD80 (PANTHERLAKE)
[04:34:51] [PASSED] 0xFD81 (PANTHERLAKE)
[04:34:51] [PASSED] 0xD740 (NOVALAKE_S)
[04:34:51] [PASSED] 0xD741 (NOVALAKE_S)
[04:34:51] [PASSED] 0xD742 (NOVALAKE_S)
[04:34:51] [PASSED] 0xD743 (NOVALAKE_S)
[04:34:51] [PASSED] 0xD744 (NOVALAKE_S)
[04:34:51] [PASSED] 0xD745 (NOVALAKE_S)
[04:34:51] [PASSED] 0x674C (CRESCENTISLAND)
[04:34:51] =============== [PASSED] check_platform_desc ===============
[04:34:51] ===================== [PASSED] xe_pci ======================
[04:34:51] =================== xe_rtp (2 subtests) ====================
[04:34:51] =============== xe_rtp_process_to_sr_tests  ================
[04:34:51] [PASSED] coalesce-same-reg
[04:34:51] [PASSED] no-match-no-add
[04:34:51] [PASSED] match-or
[04:34:51] [PASSED] match-or-xfail
[04:34:51] [PASSED] no-match-no-add-multiple-rules
[04:34:51] [PASSED] two-regs-two-entries
[04:34:51] [PASSED] clr-one-set-other
[04:34:51] [PASSED] set-field
[04:34:51] [PASSED] conflict-duplicate
[04:34:51] [PASSED] conflict-not-disjoint
[04:34:51] [PASSED] conflict-reg-type
[04:34:51] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[04:34:51] ================== xe_rtp_process_tests  ===================
[04:34:51] [PASSED] active1
[04:34:51] [PASSED] active2
[04:34:51] [PASSED] active-inactive
[04:34:51] [PASSED] inactive-active
[04:34:51] [PASSED] inactive-1st_or_active-inactive
[04:34:51] [PASSED] inactive-2nd_or_active-inactive
[04:34:51] [PASSED] inactive-last_or_active-inactive
[04:34:51] [PASSED] inactive-no_or_active-inactive
[04:34:51] ============== [PASSED] xe_rtp_process_tests ===============
[04:34:51] ===================== [PASSED] xe_rtp ======================
[04:34:51] ==================== xe_wa (1 subtest) =====================
[04:34:51] ======================== xe_wa_gt  =========================
[04:34:51] [PASSED] TIGERLAKE B0
[04:34:51] [PASSED] DG1 A0
[04:34:51] [PASSED] DG1 B0
[04:34:51] [PASSED] ALDERLAKE_S A0
[04:34:51] [PASSED] ALDERLAKE_S B0
[04:34:51] [PASSED] ALDERLAKE_S C0
[04:34:51] [PASSED] ALDERLAKE_S D0
[04:34:51] [PASSED] ALDERLAKE_P A0
[04:34:51] [PASSED] ALDERLAKE_P B0
[04:34:51] [PASSED] ALDERLAKE_P C0
[04:34:51] [PASSED] ALDERLAKE_S RPLS D0
[04:34:51] [PASSED] ALDERLAKE_P RPLU E0
[04:34:51] [PASSED] DG2 G10 C0
[04:34:51] [PASSED] DG2 G11 B1
[04:34:51] [PASSED] DG2 G12 A1
[04:34:51] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[04:34:51] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[04:34:51] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[04:34:51] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[04:34:51] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[04:34:51] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[04:34:51] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[04:34:51] ==================== [PASSED] xe_wa_gt =====================
[04:34:51] ====================== [PASSED] xe_wa ======================
[04:34:51] ============================================================
[04:34:51] Testing complete. Ran 512 tests: passed: 494, skipped: 18
[04:34:51] Elapsed time: 36.369s total, 4.162s configuring, 31.691s building, 0.464s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[04:34:51] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[04:34:53] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[04:35:18] Starting KUnit Kernel (1/1)...
[04:35:18] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[04:35:18] ============ drm_test_pick_cmdline (2 subtests) ============
[04:35:18] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[04:35:18] =============== drm_test_pick_cmdline_named  ===============
[04:35:18] [PASSED] NTSC
[04:35:18] [PASSED] NTSC-J
[04:35:18] [PASSED] PAL
[04:35:18] [PASSED] PAL-M
[04:35:18] =========== [PASSED] drm_test_pick_cmdline_named ===========
[04:35:18] ============== [PASSED] drm_test_pick_cmdline ==============
[04:35:18] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[04:35:18] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[04:35:18] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[04:35:18] =========== drm_validate_clone_mode (2 subtests) ===========
[04:35:18] ============== drm_test_check_in_clone_mode  ===============
[04:35:18] [PASSED] in_clone_mode
[04:35:18] [PASSED] not_in_clone_mode
[04:35:18] ========== [PASSED] drm_test_check_in_clone_mode ===========
[04:35:18] =============== drm_test_check_valid_clones  ===============
[04:35:18] [PASSED] not_in_clone_mode
[04:35:18] [PASSED] valid_clone
[04:35:18] [PASSED] invalid_clone
[04:35:18] =========== [PASSED] drm_test_check_valid_clones ===========
[04:35:18] ============= [PASSED] drm_validate_clone_mode =============
[04:35:18] ============= drm_validate_modeset (1 subtest) =============
[04:35:18] [PASSED] drm_test_check_connector_changed_modeset
[04:35:18] ============== [PASSED] drm_validate_modeset ===============
[04:35:18] ====== drm_test_bridge_get_current_state (2 subtests) ======
[04:35:18] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[04:35:18] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[04:35:18] ======== [PASSED] drm_test_bridge_get_current_state ========
[04:35:18] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[04:35:18] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[04:35:18] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[04:35:18] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[04:35:18] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[04:35:18] ============== drm_bridge_alloc (2 subtests) ===============
[04:35:18] [PASSED] drm_test_drm_bridge_alloc_basic
[04:35:18] [PASSED] drm_test_drm_bridge_alloc_get_put
[04:35:18] ================ [PASSED] drm_bridge_alloc =================
[04:35:18] ================== drm_buddy (8 subtests) ==================
[04:35:18] [PASSED] drm_test_buddy_alloc_limit
[04:35:18] [PASSED] drm_test_buddy_alloc_optimistic
[04:35:18] [PASSED] drm_test_buddy_alloc_pessimistic
[04:35:18] [PASSED] drm_test_buddy_alloc_pathological
[04:35:18] [PASSED] drm_test_buddy_alloc_contiguous
[04:35:18] [PASSED] drm_test_buddy_alloc_clear
[04:35:18] [PASSED] drm_test_buddy_alloc_range_bias
[04:35:18] [PASSED] drm_test_buddy_fragmentation_performance
[04:35:18] ==================== [PASSED] drm_buddy ====================
[04:35:18] ============= drm_cmdline_parser (40 subtests) =============
[04:35:18] [PASSED] drm_test_cmdline_force_d_only
[04:35:18] [PASSED] drm_test_cmdline_force_D_only_dvi
[04:35:18] [PASSED] drm_test_cmdline_force_D_only_hdmi
[04:35:18] [PASSED] drm_test_cmdline_force_D_only_not_digital
[04:35:18] [PASSED] drm_test_cmdline_force_e_only
[04:35:18] [PASSED] drm_test_cmdline_res
[04:35:18] [PASSED] drm_test_cmdline_res_vesa
[04:35:18] [PASSED] drm_test_cmdline_res_vesa_rblank
[04:35:18] [PASSED] drm_test_cmdline_res_rblank
[04:35:18] [PASSED] drm_test_cmdline_res_bpp
[04:35:18] [PASSED] drm_test_cmdline_res_refresh
[04:35:18] [PASSED] drm_test_cmdline_res_bpp_refresh
[04:35:18] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[04:35:18] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[04:35:18] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[04:35:18] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[04:35:18] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[04:35:18] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[04:35:18] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[04:35:18] [PASSED] drm_test_cmdline_res_margins_force_on
[04:35:18] [PASSED] drm_test_cmdline_res_vesa_margins
[04:35:18] [PASSED] drm_test_cmdline_name
[04:35:18] [PASSED] drm_test_cmdline_name_bpp
[04:35:18] [PASSED] drm_test_cmdline_name_option
[04:35:18] [PASSED] drm_test_cmdline_name_bpp_option
[04:35:18] [PASSED] drm_test_cmdline_rotate_0
[04:35:18] [PASSED] drm_test_cmdline_rotate_90
[04:35:18] [PASSED] drm_test_cmdline_rotate_180
[04:35:18] [PASSED] drm_test_cmdline_rotate_270
[04:35:18] [PASSED] drm_test_cmdline_hmirror
[04:35:18] [PASSED] drm_test_cmdline_vmirror
[04:35:18] [PASSED] drm_test_cmdline_margin_options
[04:35:18] [PASSED] drm_test_cmdline_multiple_options
[04:35:18] [PASSED] drm_test_cmdline_bpp_extra_and_option
[04:35:18] [PASSED] drm_test_cmdline_extra_and_option
[04:35:18] [PASSED] drm_test_cmdline_freestanding_options
[04:35:18] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[04:35:18] [PASSED] drm_test_cmdline_panel_orientation
[04:35:18] ================ drm_test_cmdline_invalid  =================
[04:35:18] [PASSED] margin_only
[04:35:18] [PASSED] interlace_only
[04:35:18] [PASSED] res_missing_x
[04:35:18] [PASSED] res_missing_y
[04:35:18] [PASSED] res_bad_y
[04:35:18] [PASSED] res_missing_y_bpp
[04:35:18] [PASSED] res_bad_bpp
[04:35:18] [PASSED] res_bad_refresh
[04:35:18] [PASSED] res_bpp_refresh_force_on_off
[04:35:18] [PASSED] res_invalid_mode
[04:35:18] [PASSED] res_bpp_wrong_place_mode
[04:35:18] [PASSED] name_bpp_refresh
[04:35:18] [PASSED] name_refresh
[04:35:18] [PASSED] name_refresh_wrong_mode
[04:35:18] [PASSED] name_refresh_invalid_mode
[04:35:18] [PASSED] rotate_multiple
[04:35:18] [PASSED] rotate_invalid_val
[04:35:18] [PASSED] rotate_truncated
[04:35:18] [PASSED] invalid_option
[04:35:18] [PASSED] invalid_tv_option
[04:35:18] [PASSED] truncated_tv_option
[04:35:18] ============ [PASSED] drm_test_cmdline_invalid =============
[04:35:18] =============== drm_test_cmdline_tv_options  ===============
[04:35:18] [PASSED] NTSC
[04:35:18] [PASSED] NTSC_443
[04:35:18] [PASSED] NTSC_J
[04:35:18] [PASSED] PAL
[04:35:18] [PASSED] PAL_M
[04:35:18] [PASSED] PAL_N
[04:35:18] [PASSED] SECAM
[04:35:18] [PASSED] MONO_525
[04:35:18] [PASSED] MONO_625
[04:35:18] =========== [PASSED] drm_test_cmdline_tv_options ===========
[04:35:18] =============== [PASSED] drm_cmdline_parser ================
[04:35:18] ========== drmm_connector_hdmi_init (20 subtests) ==========
[04:35:18] [PASSED] drm_test_connector_hdmi_init_valid
[04:35:18] [PASSED] drm_test_connector_hdmi_init_bpc_8
[04:35:18] [PASSED] drm_test_connector_hdmi_init_bpc_10
[04:35:18] [PASSED] drm_test_connector_hdmi_init_bpc_12
[04:35:18] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[04:35:18] [PASSED] drm_test_connector_hdmi_init_bpc_null
[04:35:18] [PASSED] drm_test_connector_hdmi_init_formats_empty
[04:35:18] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[04:35:18] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[04:35:18] [PASSED] supported_formats=0x9 yuv420_allowed=1
[04:35:18] [PASSED] supported_formats=0x9 yuv420_allowed=0
[04:35:18] [PASSED] supported_formats=0x3 yuv420_allowed=1
[04:35:18] [PASSED] supported_formats=0x3 yuv420_allowed=0
[04:35:18] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[04:35:18] [PASSED] drm_test_connector_hdmi_init_null_ddc
[04:35:18] [PASSED] drm_test_connector_hdmi_init_null_product
[04:35:18] [PASSED] drm_test_connector_hdmi_init_null_vendor
[04:35:18] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[04:35:18] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[04:35:18] [PASSED] drm_test_connector_hdmi_init_product_valid
[04:35:18] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[04:35:18] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[04:35:18] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[04:35:18] ========= drm_test_connector_hdmi_init_type_valid  =========
[04:35:18] [PASSED] HDMI-A
[04:35:18] [PASSED] HDMI-B
[04:35:18] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[04:35:18] ======== drm_test_connector_hdmi_init_type_invalid  ========
[04:35:18] [PASSED] Unknown
[04:35:18] [PASSED] VGA
[04:35:18] [PASSED] DVI-I
[04:35:18] [PASSED] DVI-D
[04:35:18] [PASSED] DVI-A
[04:35:18] [PASSED] Composite
[04:35:18] [PASSED] SVIDEO
[04:35:18] [PASSED] LVDS
[04:35:18] [PASSED] Component
[04:35:18] [PASSED] DIN
[04:35:18] [PASSED] DP
[04:35:18] [PASSED] TV
[04:35:18] [PASSED] eDP
[04:35:18] [PASSED] Virtual
[04:35:18] [PASSED] DSI
[04:35:18] [PASSED] DPI
[04:35:18] [PASSED] Writeback
[04:35:18] [PASSED] SPI
[04:35:18] [PASSED] USB
[04:35:18] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[04:35:18] ============ [PASSED] drmm_connector_hdmi_init =============
[04:35:18] ============= drmm_connector_init (3 subtests) =============
[04:35:18] [PASSED] drm_test_drmm_connector_init
[04:35:18] [PASSED] drm_test_drmm_connector_init_null_ddc
[04:35:18] ========= drm_test_drmm_connector_init_type_valid  =========
[04:35:18] [PASSED] Unknown
[04:35:18] [PASSED] VGA
[04:35:18] [PASSED] DVI-I
[04:35:18] [PASSED] DVI-D
[04:35:18] [PASSED] DVI-A
[04:35:18] [PASSED] Composite
[04:35:18] [PASSED] SVIDEO
[04:35:18] [PASSED] LVDS
[04:35:18] [PASSED] Component
[04:35:18] [PASSED] DIN
[04:35:18] [PASSED] DP
[04:35:18] [PASSED] HDMI-A
[04:35:18] [PASSED] HDMI-B
[04:35:18] [PASSED] TV
[04:35:18] [PASSED] eDP
[04:35:18] [PASSED] Virtual
[04:35:18] [PASSED] DSI
[04:35:18] [PASSED] DPI
[04:35:18] [PASSED] Writeback
[04:35:18] [PASSED] SPI
[04:35:18] [PASSED] USB
[04:35:18] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[04:35:18] =============== [PASSED] drmm_connector_init ===============
[04:35:18] ========= drm_connector_dynamic_init (6 subtests) ==========
[04:35:18] [PASSED] drm_test_drm_connector_dynamic_init
[04:35:18] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[04:35:18] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[04:35:18] [PASSED] drm_test_drm_connector_dynamic_init_properties
[04:35:18] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[04:35:18] [PASSED] Unknown
[04:35:18] [PASSED] VGA
[04:35:18] [PASSED] DVI-I
[04:35:18] [PASSED] DVI-D
[04:35:18] [PASSED] DVI-A
[04:35:18] [PASSED] Composite
[04:35:18] [PASSED] SVIDEO
[04:35:18] [PASSED] LVDS
[04:35:18] [PASSED] Component
[04:35:18] [PASSED] DIN
[04:35:18] [PASSED] DP
[04:35:18] [PASSED] HDMI-A
[04:35:18] [PASSED] HDMI-B
[04:35:18] [PASSED] TV
[04:35:18] [PASSED] eDP
[04:35:18] [PASSED] Virtual
[04:35:18] [PASSED] DSI
[04:35:18] [PASSED] DPI
[04:35:18] [PASSED] Writeback
[04:35:18] [PASSED] SPI
[04:35:18] [PASSED] USB
[04:35:18] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[04:35:18] ======== drm_test_drm_connector_dynamic_init_name  =========
[04:35:18] [PASSED] Unknown
[04:35:18] [PASSED] VGA
[04:35:18] [PASSED] DVI-I
[04:35:18] [PASSED] DVI-D
[04:35:18] [PASSED] DVI-A
[04:35:18] [PASSED] Composite
[04:35:18] [PASSED] SVIDEO
[04:35:18] [PASSED] LVDS
[04:35:18] [PASSED] Component
[04:35:18] [PASSED] DIN
[04:35:18] [PASSED] DP
[04:35:18] [PASSED] HDMI-A
[04:35:18] [PASSED] HDMI-B
[04:35:18] [PASSED] TV
[04:35:18] [PASSED] eDP
[04:35:18] [PASSED] Virtual
[04:35:18] [PASSED] DSI
[04:35:18] [PASSED] DPI
[04:35:18] [PASSED] Writeback
[04:35:18] [PASSED] SPI
[04:35:18] [PASSED] USB
[04:35:18] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[04:35:18] =========== [PASSED] drm_connector_dynamic_init ============
[04:35:18] ==== drm_connector_dynamic_register_early (4 subtests) =====
[04:35:18] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[04:35:18] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[04:35:18] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[04:35:18] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[04:35:18] ====== [PASSED] drm_connector_dynamic_register_early =======
[04:35:18] ======= drm_connector_dynamic_register (7 subtests) ========
[04:35:18] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[04:35:18] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[04:35:18] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[04:35:18] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[04:35:18] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[04:35:18] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[04:35:18] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[04:35:18] ========= [PASSED] drm_connector_dynamic_register ==========
[04:35:18] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[04:35:18] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[04:35:18] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[04:35:18] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[04:35:18] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[04:35:18] ========== drm_test_get_tv_mode_from_name_valid  ===========
[04:35:18] [PASSED] NTSC
[04:35:18] [PASSED] NTSC-443
[04:35:18] [PASSED] NTSC-J
[04:35:18] [PASSED] PAL
[04:35:18] [PASSED] PAL-M
[04:35:18] [PASSED] PAL-N
[04:35:18] [PASSED] SECAM
[04:35:18] [PASSED] Mono
[04:35:18] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[04:35:18] [PASSED] drm_test_get_tv_mode_from_name_truncated
[04:35:18] ============ [PASSED] drm_get_tv_mode_from_name ============
[04:35:18] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[04:35:18] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[04:35:18] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[04:35:18] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[04:35:18] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[04:35:18] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[04:35:18] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[04:35:18] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[04:35:18] [PASSED] VIC 96
[04:35:18] [PASSED] VIC 97
[04:35:18] [PASSED] VIC 101
[04:35:18] [PASSED] VIC 102
[04:35:18] [PASSED] VIC 106
[04:35:18] [PASSED] VIC 107
[04:35:18] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[04:35:18] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[04:35:18] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[04:35:18] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[04:35:18] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[04:35:18] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[04:35:18] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[04:35:18] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[04:35:18] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[04:35:18] [PASSED] Automatic
[04:35:18] [PASSED] Full
[04:35:18] [PASSED] Limited 16:235
[04:35:18] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[04:35:18] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[04:35:18] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[04:35:18] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[04:35:18] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[04:35:18] [PASSED] RGB
[04:35:18] [PASSED] YUV 4:2:0
[04:35:18] [PASSED] YUV 4:2:2
[04:35:18] [PASSED] YUV 4:4:4
[04:35:18] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[04:35:18] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[04:35:18] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[04:35:18] ============= drm_damage_helper (21 subtests) ==============
[04:35:18] [PASSED] drm_test_damage_iter_no_damage
[04:35:18] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[04:35:18] [PASSED] drm_test_damage_iter_no_damage_src_moved
[04:35:18] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[04:35:18] [PASSED] drm_test_damage_iter_no_damage_not_visible
[04:35:18] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[04:35:18] [PASSED] drm_test_damage_iter_no_damage_no_fb
[04:35:18] [PASSED] drm_test_damage_iter_simple_damage
[04:35:18] [PASSED] drm_test_damage_iter_single_damage
[04:35:18] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[04:35:18] [PASSED] drm_test_damage_iter_single_damage_outside_src
[04:35:18] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[04:35:18] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[04:35:18] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[04:35:18] [PASSED] drm_test_damage_iter_single_damage_src_moved
[04:35:18] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[04:35:18] [PASSED] drm_test_damage_iter_damage
[04:35:18] [PASSED] drm_test_damage_iter_damage_one_intersect
[04:35:18] [PASSED] drm_test_damage_iter_damage_one_outside
[04:35:18] [PASSED] drm_test_damage_iter_damage_src_moved
[04:35:18] [PASSED] drm_test_damage_iter_damage_not_visible
[04:35:18] ================ [PASSED] drm_damage_helper ================
[04:35:18] ============== drm_dp_mst_helper (3 subtests) ==============
[04:35:18] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[04:35:18] [PASSED] Clock 154000 BPP 30 DSC disabled
[04:35:18] [PASSED] Clock 234000 BPP 30 DSC disabled
[04:35:18] [PASSED] Clock 297000 BPP 24 DSC disabled
[04:35:18] [PASSED] Clock 332880 BPP 24 DSC enabled
[04:35:18] [PASSED] Clock 324540 BPP 24 DSC enabled
[04:35:18] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[04:35:18] ============== drm_test_dp_mst_calc_pbn_div  ===============
[04:35:18] [PASSED] Link rate 2000000 lane count 4
[04:35:18] [PASSED] Link rate 2000000 lane count 2
[04:35:18] [PASSED] Link rate 2000000 lane count 1
[04:35:18] [PASSED] Link rate 1350000 lane count 4
[04:35:18] [PASSED] Link rate 1350000 lane count 2
[04:35:18] [PASSED] Link rate 1350000 lane count 1
[04:35:18] [PASSED] Link rate 1000000 lane count 4
[04:35:18] [PASSED] Link rate 1000000 lane count 2
[04:35:18] [PASSED] Link rate 1000000 lane count 1
[04:35:18] [PASSED] Link rate 810000 lane count 4
[04:35:18] [PASSED] Link rate 810000 lane count 2
[04:35:18] [PASSED] Link rate 810000 lane count 1
[04:35:18] [PASSED] Link rate 540000 lane count 4
[04:35:18] [PASSED] Link rate 540000 lane count 2
[04:35:18] [PASSED] Link rate 540000 lane count 1
[04:35:18] [PASSED] Link rate 270000 lane count 4
[04:35:18] [PASSED] Link rate 270000 lane count 2
[04:35:18] [PASSED] Link rate 270000 lane count 1
[04:35:18] [PASSED] Link rate 162000 lane count 4
[04:35:18] [PASSED] Link rate 162000 lane count 2
[04:35:18] [PASSED] Link rate 162000 lane count 1
[04:35:18] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[04:35:18] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[04:35:18] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[04:35:18] [PASSED] DP_POWER_UP_PHY with port number
[04:35:18] [PASSED] DP_POWER_DOWN_PHY with port number
[04:35:18] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[04:35:18] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[04:35:18] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[04:35:18] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[04:35:18] [PASSED] DP_QUERY_PAYLOAD with port number
[04:35:18] [PASSED] DP_QUERY_PAYLOAD with VCPI
[04:35:18] [PASSED] DP_REMOTE_DPCD_READ with port number
[04:35:18] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[04:35:18] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[04:35:18] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[04:35:18] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[04:35:18] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[04:35:18] [PASSED] DP_REMOTE_I2C_READ with port number
[04:35:18] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[04:35:18] [PASSED] DP_REMOTE_I2C_READ with transactions array
[04:35:18] [PASSED] DP_REMOTE_I2C_WRITE with port number
[04:35:18] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[04:35:18] [PASSED] DP_REMOTE_I2C_WRITE with data array
[04:35:18] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[04:35:18] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[04:35:18] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[04:35:18] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[04:35:18] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[04:35:18] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[04:35:18] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[04:35:18] ================ [PASSED] drm_dp_mst_helper ================
[04:35:18] ================== drm_exec (7 subtests) ===================
[04:35:18] [PASSED] sanitycheck
[04:35:18] [PASSED] test_lock
[04:35:18] [PASSED] test_lock_unlock
[04:35:18] [PASSED] test_duplicates
[04:35:18] [PASSED] test_prepare
[04:35:18] [PASSED] test_prepare_array
[04:35:18] [PASSED] test_multiple_loops
[04:35:18] ==================== [PASSED] drm_exec =====================
[04:35:18] =========== drm_format_helper_test (17 subtests) ===========
[04:35:18] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[04:35:18] [PASSED] single_pixel_source_buffer
[04:35:18] [PASSED] single_pixel_clip_rectangle
[04:35:18] [PASSED] well_known_colors
[04:35:18] [PASSED] destination_pitch
[04:35:18] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[04:35:18] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[04:35:18] [PASSED] single_pixel_source_buffer
[04:35:18] [PASSED] single_pixel_clip_rectangle
[04:35:18] [PASSED] well_known_colors
[04:35:18] [PASSED] destination_pitch
[04:35:18] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[04:35:18] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[04:35:18] [PASSED] single_pixel_source_buffer
[04:35:18] [PASSED] single_pixel_clip_rectangle
[04:35:18] [PASSED] well_known_colors
[04:35:18] [PASSED] destination_pitch
[04:35:18] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[04:35:18] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[04:35:18] [PASSED] single_pixel_source_buffer
[04:35:18] [PASSED] single_pixel_clip_rectangle
[04:35:18] [PASSED] well_known_colors
[04:35:18] [PASSED] destination_pitch
[04:35:18] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[04:35:18] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[04:35:18] [PASSED] single_pixel_source_buffer
[04:35:18] [PASSED] single_pixel_clip_rectangle
[04:35:18] [PASSED] well_known_colors
[04:35:18] [PASSED] destination_pitch
[04:35:18] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[04:35:18] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[04:35:18] [PASSED] single_pixel_source_buffer
[04:35:18] [PASSED] single_pixel_clip_rectangle
[04:35:18] [PASSED] well_known_colors
[04:35:18] [PASSED] destination_pitch
[04:35:18] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[04:35:18] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[04:35:18] [PASSED] single_pixel_source_buffer
[04:35:18] [PASSED] single_pixel_clip_rectangle
[04:35:18] [PASSED] well_known_colors
[04:35:18] [PASSED] destination_pitch
[04:35:18] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[04:35:18] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[04:35:18] [PASSED] single_pixel_source_buffer
[04:35:18] [PASSED] single_pixel_clip_rectangle
[04:35:18] [PASSED] well_known_colors
[04:35:18] [PASSED] destination_pitch
[04:35:18] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[04:35:18] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[04:35:18] [PASSED] single_pixel_source_buffer
[04:35:18] [PASSED] single_pixel_clip_rectangle
[04:35:18] [PASSED] well_known_colors
[04:35:18] [PASSED] destination_pitch
[04:35:18] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[04:35:18] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[04:35:18] [PASSED] single_pixel_source_buffer
[04:35:18] [PASSED] single_pixel_clip_rectangle
[04:35:18] [PASSED] well_known_colors
[04:35:18] [PASSED] destination_pitch
[04:35:18] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[04:35:18] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[04:35:18] [PASSED] single_pixel_source_buffer
[04:35:18] [PASSED] single_pixel_clip_rectangle
[04:35:18] [PASSED] well_known_colors
[04:35:18] [PASSED] destination_pitch
[04:35:18] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[04:35:18] ============== drm_test_fb_xrgb8888_to_mono  ===============
[04:35:18] [PASSED] single_pixel_source_buffer
[04:35:18] [PASSED] single_pixel_clip_rectangle
[04:35:18] [PASSED] well_known_colors
[04:35:18] [PASSED] destination_pitch
[04:35:18] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[04:35:18] ==================== drm_test_fb_swab  =====================
[04:35:18] [PASSED] single_pixel_source_buffer
[04:35:18] [PASSED] single_pixel_clip_rectangle
[04:35:18] [PASSED] well_known_colors
[04:35:18] [PASSED] destination_pitch
[04:35:18] ================ [PASSED] drm_test_fb_swab =================
[04:35:18] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[04:35:18] [PASSED] single_pixel_source_buffer
[04:35:18] [PASSED] single_pixel_clip_rectangle
[04:35:18] [PASSED] well_known_colors
[04:35:18] [PASSED] destination_pitch
[04:35:18] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[04:35:18] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[04:35:18] [PASSED] single_pixel_source_buffer
[04:35:18] [PASSED] single_pixel_clip_rectangle
[04:35:18] [PASSED] well_known_colors
[04:35:18] [PASSED] destination_pitch
[04:35:18] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[04:35:18] ================= drm_test_fb_clip_offset  =================
[04:35:18] [PASSED] pass through
[04:35:18] [PASSED] horizontal offset
[04:35:18] [PASSED] vertical offset
[04:35:18] [PASSED] horizontal and vertical offset
[04:35:18] [PASSED] horizontal offset (custom pitch)
[04:35:18] [PASSED] vertical offset (custom pitch)
[04:35:18] [PASSED] horizontal and vertical offset (custom pitch)
[04:35:18] ============= [PASSED] drm_test_fb_clip_offset =============
[04:35:18] =================== drm_test_fb_memcpy  ====================
[04:35:18] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[04:35:18] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[04:35:18] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[04:35:18] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[04:35:18] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[04:35:18] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[04:35:18] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[04:35:18] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[04:35:18] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[04:35:18] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[04:35:18] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[04:35:18] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[04:35:18] =============== [PASSED] drm_test_fb_memcpy ================
[04:35:18] ============= [PASSED] drm_format_helper_test ==============
[04:35:18] ================= drm_format (18 subtests) =================
[04:35:18] [PASSED] drm_test_format_block_width_invalid
[04:35:18] [PASSED] drm_test_format_block_width_one_plane
[04:35:18] [PASSED] drm_test_format_block_width_two_plane
[04:35:18] [PASSED] drm_test_format_block_width_three_plane
[04:35:18] [PASSED] drm_test_format_block_width_tiled
[04:35:18] [PASSED] drm_test_format_block_height_invalid
[04:35:18] [PASSED] drm_test_format_block_height_one_plane
[04:35:18] [PASSED] drm_test_format_block_height_two_plane
[04:35:18] [PASSED] drm_test_format_block_height_three_plane
[04:35:18] [PASSED] drm_test_format_block_height_tiled
[04:35:18] [PASSED] drm_test_format_min_pitch_invalid
[04:35:18] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[04:35:18] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[04:35:18] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[04:35:18] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[04:35:18] [PASSED] drm_test_format_min_pitch_two_plane
[04:35:18] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[04:35:18] [PASSED] drm_test_format_min_pitch_tiled
[04:35:18] =================== [PASSED] drm_format ====================
[04:35:18] ============== drm_framebuffer (10 subtests) ===============
[04:35:18] ========== drm_test_framebuffer_check_src_coords  ==========
[04:35:18] [PASSED] Success: source fits into fb
[04:35:18] [PASSED] Fail: overflowing fb with x-axis coordinate
[04:35:18] [PASSED] Fail: overflowing fb with y-axis coordinate
[04:35:18] [PASSED] Fail: overflowing fb with source width
[04:35:18] [PASSED] Fail: overflowing fb with source height
[04:35:18] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[04:35:18] [PASSED] drm_test_framebuffer_cleanup
[04:35:18] =============== drm_test_framebuffer_create  ===============
[04:35:18] [PASSED] ABGR8888 normal sizes
[04:35:18] [PASSED] ABGR8888 max sizes
[04:35:18] [PASSED] ABGR8888 pitch greater than min required
[04:35:18] [PASSED] ABGR8888 pitch less than min required
[04:35:18] [PASSED] ABGR8888 Invalid width
[04:35:18] [PASSED] ABGR8888 Invalid buffer handle
[04:35:18] [PASSED] No pixel format
[04:35:18] [PASSED] ABGR8888 Width 0
[04:35:18] [PASSED] ABGR8888 Height 0
[04:35:18] [PASSED] ABGR8888 Out of bound height * pitch combination
[04:35:18] [PASSED] ABGR8888 Large buffer offset
[04:35:18] [PASSED] ABGR8888 Buffer offset for inexistent plane
[04:35:18] [PASSED] ABGR8888 Invalid flag
[04:35:18] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[04:35:18] [PASSED] ABGR8888 Valid buffer modifier
[04:35:18] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[04:35:18] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[04:35:18] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[04:35:18] [PASSED] NV12 Normal sizes
[04:35:18] [PASSED] NV12 Max sizes
[04:35:18] [PASSED] NV12 Invalid pitch
[04:35:18] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[04:35:18] [PASSED] NV12 different  modifier per-plane
[04:35:18] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[04:35:18] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[04:35:18] [PASSED] NV12 Modifier for inexistent plane
[04:35:18] [PASSED] NV12 Handle for inexistent plane
[04:35:18] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[04:35:18] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[04:35:18] [PASSED] YVU420 Normal sizes
[04:35:18] [PASSED] YVU420 Max sizes
[04:35:18] [PASSED] YVU420 Invalid pitch
[04:35:18] [PASSED] YVU420 Different pitches
[04:35:18] [PASSED] YVU420 Different buffer offsets/pitches
[04:35:18] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[04:35:18] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[04:35:18] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[04:35:18] [PASSED] YVU420 Valid modifier
[04:35:18] [PASSED] YVU420 Different modifiers per plane
[04:35:18] [PASSED] YVU420 Modifier for inexistent plane
[04:35:18] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[04:35:18] [PASSED] X0L2 Normal sizes
[04:35:18] [PASSED] X0L2 Max sizes
[04:35:18] [PASSED] X0L2 Invalid pitch
[04:35:18] [PASSED] X0L2 Pitch greater than minimum required
[04:35:18] [PASSED] X0L2 Handle for inexistent plane
[04:35:18] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[04:35:18] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[04:35:18] [PASSED] X0L2 Valid modifier
[04:35:18] [PASSED] X0L2 Modifier for inexistent plane
[04:35:18] =========== [PASSED] drm_test_framebuffer_create ===========
[04:35:18] [PASSED] drm_test_framebuffer_free
[04:35:18] [PASSED] drm_test_framebuffer_init
[04:35:18] [PASSED] drm_test_framebuffer_init_bad_format
[04:35:18] [PASSED] drm_test_framebuffer_init_dev_mismatch
[04:35:18] [PASSED] drm_test_framebuffer_lookup
[04:35:18] [PASSED] drm_test_framebuffer_lookup_inexistent
[04:35:18] [PASSED] drm_test_framebuffer_modifiers_not_supported
[04:35:18] ================= [PASSED] drm_framebuffer =================
[04:35:18] ================ drm_gem_shmem (8 subtests) ================
[04:35:18] [PASSED] drm_gem_shmem_test_obj_create
[04:35:18] [PASSED] drm_gem_shmem_test_obj_create_private
[04:35:18] [PASSED] drm_gem_shmem_test_pin_pages
[04:35:18] [PASSED] drm_gem_shmem_test_vmap
[04:35:18] [PASSED] drm_gem_shmem_test_get_sg_table
[04:35:18] [PASSED] drm_gem_shmem_test_get_pages_sgt
[04:35:18] [PASSED] drm_gem_shmem_test_madvise
[04:35:18] [PASSED] drm_gem_shmem_test_purge
[04:35:18] ================== [PASSED] drm_gem_shmem ==================
[04:35:18] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[04:35:18] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[04:35:18] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[04:35:18] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[04:35:18] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[04:35:18] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[04:35:18] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[04:35:18] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[04:35:18] [PASSED] Automatic
[04:35:18] [PASSED] Full
[04:35:18] [PASSED] Limited 16:235
[04:35:18] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[04:35:18] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[04:35:18] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[04:35:18] [PASSED] drm_test_check_disable_connector
[04:35:18] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[04:35:18] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[04:35:18] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[04:35:18] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[04:35:18] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[04:35:18] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[04:35:18] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[04:35:18] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[04:35:18] [PASSED] drm_test_check_output_bpc_dvi
[04:35:18] [PASSED] drm_test_check_output_bpc_format_vic_1
[04:35:18] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[04:35:18] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[04:35:18] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[04:35:18] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[04:35:18] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[04:35:18] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[04:35:18] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[04:35:18] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[04:35:18] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[04:35:18] [PASSED] drm_test_check_broadcast_rgb_value
[04:35:18] [PASSED] drm_test_check_bpc_8_value
[04:35:18] [PASSED] drm_test_check_bpc_10_value
[04:35:18] [PASSED] drm_test_check_bpc_12_value
[04:35:18] [PASSED] drm_test_check_format_value
[04:35:18] [PASSED] drm_test_check_tmds_char_value
[04:35:18] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[04:35:18] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[04:35:18] [PASSED] drm_test_check_mode_valid
[04:35:18] [PASSED] drm_test_check_mode_valid_reject
[04:35:18] [PASSED] drm_test_check_mode_valid_reject_rate
[04:35:18] [PASSED] drm_test_check_mode_valid_reject_max_clock
[04:35:18] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[04:35:18] ================= drm_managed (2 subtests) =================
[04:35:18] [PASSED] drm_test_managed_release_action
[04:35:18] [PASSED] drm_test_managed_run_action
[04:35:18] =================== [PASSED] drm_managed ===================
[04:35:18] =================== drm_mm (6 subtests) ====================
[04:35:18] [PASSED] drm_test_mm_init
[04:35:18] [PASSED] drm_test_mm_debug
[04:35:18] [PASSED] drm_test_mm_align32
[04:35:18] [PASSED] drm_test_mm_align64
[04:35:18] [PASSED] drm_test_mm_lowest
[04:35:18] [PASSED] drm_test_mm_highest
[04:35:18] ===================== [PASSED] drm_mm ======================
[04:35:18] ============= drm_modes_analog_tv (5 subtests) =============
[04:35:18] [PASSED] drm_test_modes_analog_tv_mono_576i
[04:35:18] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[04:35:18] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[04:35:18] [PASSED] drm_test_modes_analog_tv_pal_576i
[04:35:18] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[04:35:18] =============== [PASSED] drm_modes_analog_tv ===============
[04:35:18] ============== drm_plane_helper (2 subtests) ===============
[04:35:18] =============== drm_test_check_plane_state  ================
[04:35:18] [PASSED] clipping_simple
[04:35:18] [PASSED] clipping_rotate_reflect
[04:35:18] [PASSED] positioning_simple
[04:35:18] [PASSED] upscaling
[04:35:18] [PASSED] downscaling
[04:35:18] [PASSED] rounding1
[04:35:18] [PASSED] rounding2
[04:35:18] [PASSED] rounding3
[04:35:18] [PASSED] rounding4
[04:35:18] =========== [PASSED] drm_test_check_plane_state ============
[04:35:18] =========== drm_test_check_invalid_plane_state  ============
[04:35:18] [PASSED] positioning_invalid
[04:35:18] [PASSED] upscaling_invalid
[04:35:18] [PASSED] downscaling_invalid
[04:35:18] ======= [PASSED] drm_test_check_invalid_plane_state ========
[04:35:18] ================ [PASSED] drm_plane_helper =================
[04:35:18] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[04:35:18] ====== drm_test_connector_helper_tv_get_modes_check  =======
[04:35:18] [PASSED] None
[04:35:18] [PASSED] PAL
[04:35:18] [PASSED] NTSC
[04:35:18] [PASSED] Both, NTSC Default
[04:35:18] [PASSED] Both, PAL Default
[04:35:18] [PASSED] Both, NTSC Default, with PAL on command-line
[04:35:18] [PASSED] Both, PAL Default, with NTSC on command-line
[04:35:18] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[04:35:18] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[04:35:18] ================== drm_rect (9 subtests) ===================
[04:35:18] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[04:35:18] [PASSED] drm_test_rect_clip_scaled_not_clipped
[04:35:18] [PASSED] drm_test_rect_clip_scaled_clipped
[04:35:18] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[04:35:18] ================= drm_test_rect_intersect  =================
[04:35:18] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[04:35:18] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[04:35:18] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[04:35:18] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[04:35:18] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[04:35:18] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[04:35:18] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[04:35:18] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[04:35:18] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[04:35:18] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[04:35:18] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[04:35:18] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[04:35:18] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[04:35:18] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[04:35:18] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[04:35:18] ============= [PASSED] drm_test_rect_intersect =============
[04:35:18] ================ drm_test_rect_calc_hscale  ================
[04:35:18] [PASSED] normal use
[04:35:18] [PASSED] out of max range
[04:35:18] [PASSED] out of min range
[04:35:18] [PASSED] zero dst
[04:35:18] [PASSED] negative src
[04:35:18] [PASSED] negative dst
[04:35:18] ============ [PASSED] drm_test_rect_calc_hscale ============
[04:35:18] ================ drm_test_rect_calc_vscale  ================
[04:35:18] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[04:35:18] [PASSED] out of max range
[04:35:18] [PASSED] out of min range
[04:35:18] [PASSED] zero dst
[04:35:18] [PASSED] negative src
[04:35:18] [PASSED] negative dst
[04:35:18] ============ [PASSED] drm_test_rect_calc_vscale ============
[04:35:18] ================== drm_test_rect_rotate  ===================
[04:35:18] [PASSED] reflect-x
[04:35:18] [PASSED] reflect-y
[04:35:18] [PASSED] rotate-0
[04:35:18] [PASSED] rotate-90
[04:35:18] [PASSED] rotate-180
[04:35:18] [PASSED] rotate-270
[04:35:18] ============== [PASSED] drm_test_rect_rotate ===============
[04:35:18] ================ drm_test_rect_rotate_inv  =================
[04:35:18] [PASSED] reflect-x
[04:35:18] [PASSED] reflect-y
[04:35:18] [PASSED] rotate-0
[04:35:18] [PASSED] rotate-90
[04:35:18] [PASSED] rotate-180
[04:35:18] [PASSED] rotate-270
[04:35:18] ============ [PASSED] drm_test_rect_rotate_inv =============
[04:35:18] ==================== [PASSED] drm_rect =====================
[04:35:18] ============ drm_sysfb_modeset_test (1 subtest) ============
[04:35:18] ============ drm_test_sysfb_build_fourcc_list  =============
[04:35:18] [PASSED] no native formats
[04:35:18] [PASSED] XRGB8888 as native format
[04:35:18] [PASSED] remove duplicates
[04:35:18] [PASSED] convert alpha formats
[04:35:18] [PASSED] random formats
[04:35:18] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[04:35:18] ============= [PASSED] drm_sysfb_modeset_test ==============
[04:35:18] ================== drm_fixp (2 subtests) ===================
[04:35:18] [PASSED] drm_test_int2fixp
[04:35:18] [PASSED] drm_test_sm2fixp
[04:35:18] ==================== [PASSED] drm_fixp =====================
[04:35:18] ============================================================
[04:35:18] Testing complete. Ran 624 tests: passed: 624
[04:35:18] Elapsed time: 27.354s total, 1.682s configuring, 25.254s building, 0.374s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[04:35:18] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[04:35:20] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[04:35:29] Starting KUnit Kernel (1/1)...
[04:35:29] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[04:35:30] ================= ttm_device (5 subtests) ==================
[04:35:30] [PASSED] ttm_device_init_basic
[04:35:30] [PASSED] ttm_device_init_multiple
[04:35:30] [PASSED] ttm_device_fini_basic
[04:35:30] [PASSED] ttm_device_init_no_vma_man
[04:35:30] ================== ttm_device_init_pools  ==================
[04:35:30] [PASSED] No DMA allocations, no DMA32 required
[04:35:30] [PASSED] DMA allocations, DMA32 required
[04:35:30] [PASSED] No DMA allocations, DMA32 required
[04:35:30] [PASSED] DMA allocations, no DMA32 required
[04:35:30] ============== [PASSED] ttm_device_init_pools ==============
[04:35:30] =================== [PASSED] ttm_device ====================
[04:35:30] ================== ttm_pool (8 subtests) ===================
[04:35:30] ================== ttm_pool_alloc_basic  ===================
[04:35:30] [PASSED] One page
[04:35:30] [PASSED] More than one page
[04:35:30] [PASSED] Above the allocation limit
[04:35:30] [PASSED] One page, with coherent DMA mappings enabled
[04:35:30] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[04:35:30] ============== [PASSED] ttm_pool_alloc_basic ===============
[04:35:30] ============== ttm_pool_alloc_basic_dma_addr  ==============
[04:35:30] [PASSED] One page
[04:35:30] [PASSED] More than one page
[04:35:30] [PASSED] Above the allocation limit
[04:35:30] [PASSED] One page, with coherent DMA mappings enabled
[04:35:30] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[04:35:30] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[04:35:30] [PASSED] ttm_pool_alloc_order_caching_match
[04:35:30] [PASSED] ttm_pool_alloc_caching_mismatch
[04:35:30] [PASSED] ttm_pool_alloc_order_mismatch
[04:35:30] [PASSED] ttm_pool_free_dma_alloc
[04:35:30] [PASSED] ttm_pool_free_no_dma_alloc
[04:35:30] [PASSED] ttm_pool_fini_basic
[04:35:30] ==================== [PASSED] ttm_pool =====================
[04:35:30] ================ ttm_resource (8 subtests) =================
[04:35:30] ================= ttm_resource_init_basic  =================
[04:35:30] [PASSED] Init resource in TTM_PL_SYSTEM
[04:35:30] [PASSED] Init resource in TTM_PL_VRAM
[04:35:30] [PASSED] Init resource in a private placement
[04:35:30] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[04:35:30] ============= [PASSED] ttm_resource_init_basic =============
[04:35:30] [PASSED] ttm_resource_init_pinned
[04:35:30] [PASSED] ttm_resource_fini_basic
[04:35:30] [PASSED] ttm_resource_manager_init_basic
[04:35:30] [PASSED] ttm_resource_manager_usage_basic
[04:35:30] [PASSED] ttm_resource_manager_set_used_basic
[04:35:30] [PASSED] ttm_sys_man_alloc_basic
[04:35:30] [PASSED] ttm_sys_man_free_basic
[04:35:30] ================== [PASSED] ttm_resource ===================
[04:35:30] =================== ttm_tt (15 subtests) ===================
[04:35:30] ==================== ttm_tt_init_basic  ====================
[04:35:30] [PASSED] Page-aligned size
[04:35:30] [PASSED] Extra pages requested
[04:35:30] ================ [PASSED] ttm_tt_init_basic ================
[04:35:30] [PASSED] ttm_tt_init_misaligned
[04:35:30] [PASSED] ttm_tt_fini_basic
[04:35:30] [PASSED] ttm_tt_fini_sg
[04:35:30] [PASSED] ttm_tt_fini_shmem
[04:35:30] [PASSED] ttm_tt_create_basic
[04:35:30] [PASSED] ttm_tt_create_invalid_bo_type
[04:35:30] [PASSED] ttm_tt_create_ttm_exists
[04:35:30] [PASSED] ttm_tt_create_failed
[04:35:30] [PASSED] ttm_tt_destroy_basic
[04:35:30] [PASSED] ttm_tt_populate_null_ttm
[04:35:30] [PASSED] ttm_tt_populate_populated_ttm
[04:35:30] [PASSED] ttm_tt_unpopulate_basic
[04:35:30] [PASSED] ttm_tt_unpopulate_empty_ttm
[04:35:30] [PASSED] ttm_tt_swapin_basic
[04:35:30] ===================== [PASSED] ttm_tt ======================
[04:35:30] =================== ttm_bo (14 subtests) ===================
[04:35:30] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[04:35:30] [PASSED] Cannot be interrupted and sleeps
[04:35:30] [PASSED] Cannot be interrupted, locks straight away
[04:35:30] [PASSED] Can be interrupted, sleeps
[04:35:30] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[04:35:30] [PASSED] ttm_bo_reserve_locked_no_sleep
[04:35:30] [PASSED] ttm_bo_reserve_no_wait_ticket
[04:35:30] [PASSED] ttm_bo_reserve_double_resv
[04:35:30] [PASSED] ttm_bo_reserve_interrupted
[04:35:30] [PASSED] ttm_bo_reserve_deadlock
[04:35:30] [PASSED] ttm_bo_unreserve_basic
[04:35:30] [PASSED] ttm_bo_unreserve_pinned
[04:35:30] [PASSED] ttm_bo_unreserve_bulk
[04:35:30] [PASSED] ttm_bo_fini_basic
[04:35:30] [PASSED] ttm_bo_fini_shared_resv
[04:35:30] [PASSED] ttm_bo_pin_basic
[04:35:30] [PASSED] ttm_bo_pin_unpin_resource
[04:35:30] [PASSED] ttm_bo_multiple_pin_one_unpin
[04:35:30] ===================== [PASSED] ttm_bo ======================
[04:35:30] ============== ttm_bo_validate (21 subtests) ===============
[04:35:30] ============== ttm_bo_init_reserved_sys_man  ===============
[04:35:30] [PASSED] Buffer object for userspace
[04:35:30] [PASSED] Kernel buffer object
[04:35:30] [PASSED] Shared buffer object
[04:35:30] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[04:35:30] ============== ttm_bo_init_reserved_mock_man  ==============
[04:35:30] [PASSED] Buffer object for userspace
[04:35:30] [PASSED] Kernel buffer object
[04:35:30] [PASSED] Shared buffer object
[04:35:30] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[04:35:30] [PASSED] ttm_bo_init_reserved_resv
[04:35:30] ================== ttm_bo_validate_basic  ==================
[04:35:30] [PASSED] Buffer object for userspace
[04:35:30] [PASSED] Kernel buffer object
[04:35:30] [PASSED] Shared buffer object
[04:35:30] ============== [PASSED] ttm_bo_validate_basic ==============
[04:35:30] [PASSED] ttm_bo_validate_invalid_placement
[04:35:30] ============= ttm_bo_validate_same_placement  ==============
[04:35:30] [PASSED] System manager
[04:35:30] [PASSED] VRAM manager
[04:35:30] ========= [PASSED] ttm_bo_validate_same_placement ==========
[04:35:30] [PASSED] ttm_bo_validate_failed_alloc
[04:35:30] [PASSED] ttm_bo_validate_pinned
[04:35:30] [PASSED] ttm_bo_validate_busy_placement
[04:35:30] ================ ttm_bo_validate_multihop  =================
[04:35:30] [PASSED] Buffer object for userspace
[04:35:30] [PASSED] Kernel buffer object
[04:35:30] [PASSED] Shared buffer object
[04:35:30] ============ [PASSED] ttm_bo_validate_multihop =============
[04:35:30] ========== ttm_bo_validate_no_placement_signaled  ==========
[04:35:30] [PASSED] Buffer object in system domain, no page vector
[04:35:30] [PASSED] Buffer object in system domain with an existing page vector
[04:35:30] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[04:35:30] ======== ttm_bo_validate_no_placement_not_signaled  ========
[04:35:30] [PASSED] Buffer object for userspace
[04:35:30] [PASSED] Kernel buffer object
[04:35:30] [PASSED] Shared buffer object
[04:35:30] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[04:35:30] [PASSED] ttm_bo_validate_move_fence_signaled
[04:35:30] ========= ttm_bo_validate_move_fence_not_signaled  =========
[04:35:30] [PASSED] Waits for GPU
[04:35:30] [PASSED] Tries to lock straight away
[04:35:30] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[04:35:30] [PASSED] ttm_bo_validate_happy_evict
[04:35:30] [PASSED] ttm_bo_validate_all_pinned_evict
[04:35:30] [PASSED] ttm_bo_validate_allowed_only_evict
[04:35:30] [PASSED] ttm_bo_validate_deleted_evict
[04:35:30] [PASSED] ttm_bo_validate_busy_domain_evict
[04:35:30] [PASSED] ttm_bo_validate_evict_gutting
[04:35:30] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[04:35:30] ================= [PASSED] ttm_bo_validate =================
[04:35:30] ============================================================
[04:35:30] Testing complete. Ran 101 tests: passed: 101
[04:35:30] Elapsed time: 11.401s total, 1.663s configuring, 9.471s building, 0.229s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✗ Xe.CI.BAT: failure for Fix Cx0 Suspend Resume issue (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 4177 bytes --]

== Series Details ==

Series: Fix Cx0 Suspend Resume issue (rev2)
URL   : https://patchwork.freedesktop.org/series/159539/
State : failure

== Summary ==

CI Bug Log - changes from xe-4380-1580579412915ac76344699e53124b580060302d_BAT -> xe-pw-159539v2_BAT
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-159539v2_BAT absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-159539v2_BAT, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (12 -> 12)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-159539v2_BAT:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size:
    - bat-lnl-1:          [PASS][1] -> [DMESG-WARN][2] +57 other tests dmesg-warn
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/bat-lnl-1/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/bat-lnl-1/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html

  * igt@kms_force_connector_basic@force-connector-state:
    - bat-bmg-2:          [PASS][3] -> [DMESG-WARN][4] +1 other test dmesg-warn
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/bat-bmg-2/igt@kms_force_connector_basic@force-connector-state.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/bat-bmg-2/igt@kms_force_connector_basic@force-connector-state.html

  * igt@kms_hdmi_inject@inject-audio:
    - bat-ptl-1:          [PASS][5] -> [DMESG-WARN][6] +1 other test dmesg-warn
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/bat-ptl-1/igt@kms_hdmi_inject@inject-audio.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/bat-ptl-1/igt@kms_hdmi_inject@inject-audio.html

  * igt@kms_pipe_crc_basic@hang-read-crc@pipe-c-edp-1:
    - bat-ptl-2:          [PASS][7] -> [DMESG-WARN][8] +72 other tests dmesg-warn
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/bat-ptl-2/igt@kms_pipe_crc_basic@hang-read-crc@pipe-c-edp-1.html
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/bat-ptl-2/igt@kms_pipe_crc_basic@hang-read-crc@pipe-c-edp-1.html

  * igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-hdmi-a-3:
    - bat-bmg-1:          [PASS][9] -> [DMESG-WARN][10] +64 other tests dmesg-warn
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/bat-bmg-1/igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-hdmi-a-3.html
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/bat-bmg-1/igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-hdmi-a-3.html

  
Known issues
------------

  Here are the changes found in xe-pw-159539v2_BAT that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@xe_waitfence@engine:
    - bat-dg2-oem2:       [FAIL][11] ([Intel XE#6519]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/bat-dg2-oem2/igt@xe_waitfence@engine.html
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/bat-dg2-oem2/igt@xe_waitfence@engine.html

  
  [Intel XE#6519]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6519


Build changes
-------------

  * Linux: xe-4380-1580579412915ac76344699e53124b580060302d -> xe-pw-159539v2

  IGT_8699: 0b67ab25f2eb58b296872c8c34474b79353727d5 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4380-1580579412915ac76344699e53124b580060302d: 1580579412915ac76344699e53124b580060302d
  xe-pw-159539v2: 159539v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/index.html

[-- Attachment #2: Type: text/html, Size: 4914 bytes --]

✗ Xe.CI.Full: failure for Fix Cx0 Suspend Resume issue (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 15608 bytes --]

== Series Details ==

Series: Fix Cx0 Suspend Resume issue (rev2)
URL   : https://patchwork.freedesktop.org/series/159539/
State : failure

== Summary ==

CI Bug Log - changes from xe-4380-1580579412915ac76344699e53124b580060302d_FULL -> xe-pw-159539v2_FULL
====================================================

Summary
-------

  **WARNING**

  Minor unknown changes coming with xe-pw-159539v2_FULL need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-159539v2_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-159539v2_FULL:

### IGT changes ###

#### Warnings ####

  * igt@xe_module_load@load:
    - shard-lnl:          ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [SKIP][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26]) ([Intel XE#378]) -> ([DMESG-WARN][27], [DMESG-WARN][28], [DMESG-WARN][29], [DMESG-WARN][30], [DMESG-WARN][31], [DMESG-WARN][32], [DMESG-WARN][33], [DMESG-WARN][34], [DMESG-WARN][35], [DMESG-WARN][36], [DMESG-WARN][37], [DMESG-WARN][38], [DMESG-WARN][39], [DMESG-WARN][40], [DMESG-WARN][41], [DMESG-WARN][42], [DMESG-WARN][43], [DMESG-WARN][44], [DMESG-WARN][45], [DMESG-WARN][46], [DMESG-WARN][47], [DMESG-WARN][48], [DMESG-WARN][49], [DMESG-WARN][50], [DMESG-WARN][51])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-lnl-7/igt@xe_module_load@load.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-lnl-2/igt@xe_module_load@load.html
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-lnl-3/igt@xe_module_load@load.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-lnl-1/igt@xe_module_load@load.html
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-lnl-1/igt@xe_module_load@load.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-lnl-3/igt@xe_module_load@load.html
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-lnl-3/igt@xe_module_load@load.html
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-lnl-3/igt@xe_module_load@load.html
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-lnl-4/igt@xe_module_load@load.html
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-lnl-4/igt@xe_module_load@load.html
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-lnl-4/igt@xe_module_load@load.html
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-lnl-5/igt@xe_module_load@load.html
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-lnl-7/igt@xe_module_load@load.html
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-lnl-2/igt@xe_module_load@load.html
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-lnl-2/igt@xe_module_load@load.html
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-lnl-4/igt@xe_module_load@load.html
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-lnl-1/igt@xe_module_load@load.html
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-lnl-5/igt@xe_module_load@load.html
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-lnl-5/igt@xe_module_load@load.html
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-lnl-1/igt@xe_module_load@load.html
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-lnl-8/igt@xe_module_load@load.html
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-lnl-8/igt@xe_module_load@load.html
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-lnl-8/igt@xe_module_load@load.html
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-lnl-2/igt@xe_module_load@load.html
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-lnl-8/igt@xe_module_load@load.html
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-lnl-7/igt@xe_module_load@load.html
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-lnl-1/igt@xe_module_load@load.html
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-lnl-1/igt@xe_module_load@load.html
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-lnl-1/igt@xe_module_load@load.html
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-lnl-8/igt@xe_module_load@load.html
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-lnl-8/igt@xe_module_load@load.html
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-lnl-8/igt@xe_module_load@load.html
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-lnl-4/igt@xe_module_load@load.html
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-lnl-4/igt@xe_module_load@load.html
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-lnl-4/igt@xe_module_load@load.html
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-lnl-4/igt@xe_module_load@load.html
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-lnl-3/igt@xe_module_load@load.html
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-lnl-3/igt@xe_module_load@load.html
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-lnl-3/igt@xe_module_load@load.html
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-lnl-3/igt@xe_module_load@load.html
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-lnl-2/igt@xe_module_load@load.html
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-lnl-2/igt@xe_module_load@load.html
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-lnl-7/igt@xe_module_load@load.html
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-lnl-7/igt@xe_module_load@load.html
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-lnl-7/igt@xe_module_load@load.html
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-lnl-7/igt@xe_module_load@load.html
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-lnl-7/igt@xe_module_load@load.html
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-lnl-5/igt@xe_module_load@load.html
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-lnl-5/igt@xe_module_load@load.html
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-lnl-5/igt@xe_module_load@load.html
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-lnl-5/igt@xe_module_load@load.html
    - shard-bmg:          ([PASS][52], [PASS][53], [PASS][54], [SKIP][55], [PASS][56], [PASS][57], [PASS][58], [PASS][59], [PASS][60], [PASS][61], [PASS][62], [PASS][63], [PASS][64], [PASS][65], [PASS][66], [PASS][67], [PASS][68], [PASS][69], [PASS][70], [PASS][71], [PASS][72], [PASS][73], [PASS][74], [PASS][75], [PASS][76]) ([Intel XE#2457]) -> ([ABORT][77], [DMESG-WARN][78], [DMESG-WARN][79], [DMESG-WARN][80], [DMESG-WARN][81], [DMESG-WARN][82], [DMESG-WARN][83], [DMESG-WARN][84], [DMESG-WARN][85], [DMESG-WARN][86], [DMESG-WARN][87], [DMESG-WARN][88], [DMESG-WARN][89], [DMESG-WARN][90], [DMESG-WARN][91], [DMESG-WARN][92], [DMESG-WARN][93], [DMESG-WARN][94], [DMESG-WARN][95], [DMESG-WARN][96], [DMESG-WARN][97], [DMESG-WARN][98], [DMESG-WARN][99], [DMESG-WARN][100])
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-bmg-1/igt@xe_module_load@load.html
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-bmg-8/igt@xe_module_load@load.html
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-bmg-8/igt@xe_module_load@load.html
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-bmg-8/igt@xe_module_load@load.html
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-bmg-10/igt@xe_module_load@load.html
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-bmg-10/igt@xe_module_load@load.html
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-bmg-8/igt@xe_module_load@load.html
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-bmg-3/igt@xe_module_load@load.html
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-bmg-2/igt@xe_module_load@load.html
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-bmg-2/igt@xe_module_load@load.html
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-bmg-10/igt@xe_module_load@load.html
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-bmg-9/igt@xe_module_load@load.html
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-bmg-9/igt@xe_module_load@load.html
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-bmg-9/igt@xe_module_load@load.html
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-bmg-1/igt@xe_module_load@load.html
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-bmg-3/igt@xe_module_load@load.html
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-bmg-3/igt@xe_module_load@load.html
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-bmg-1/igt@xe_module_load@load.html
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-bmg-7/igt@xe_module_load@load.html
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-bmg-7/igt@xe_module_load@load.html
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-bmg-7/igt@xe_module_load@load.html
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-bmg-7/igt@xe_module_load@load.html
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-bmg-6/igt@xe_module_load@load.html
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-bmg-6/igt@xe_module_load@load.html
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4380-1580579412915ac76344699e53124b580060302d/shard-bmg-6/igt@xe_module_load@load.html
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-bmg-4/igt@xe_module_load@load.html
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-bmg-8/igt@xe_module_load@load.html
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-bmg-8/igt@xe_module_load@load.html
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-bmg-10/igt@xe_module_load@load.html
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-bmg-10/igt@xe_module_load@load.html
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-bmg-10/igt@xe_module_load@load.html
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-bmg-10/igt@xe_module_load@load.html
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-bmg-1/igt@xe_module_load@load.html
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-bmg-1/igt@xe_module_load@load.html
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-bmg-1/igt@xe_module_load@load.html
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-bmg-7/igt@xe_module_load@load.html
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-bmg-7/igt@xe_module_load@load.html
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-bmg-9/igt@xe_module_load@load.html
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-bmg-9/igt@xe_module_load@load.html
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-bmg-9/igt@xe_module_load@load.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-bmg-2/igt@xe_module_load@load.html
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-bmg-2/igt@xe_module_load@load.html
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-bmg-2/igt@xe_module_load@load.html
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-bmg-2/igt@xe_module_load@load.html
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-bmg-6/igt@xe_module_load@load.html
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-bmg-3/igt@xe_module_load@load.html
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-bmg-3/igt@xe_module_load@load.html
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-bmg-3/igt@xe_module_load@load.html
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/shard-bmg-3/igt@xe_module_load@load.html

  
  [Intel XE#2457]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2457
  [Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378


Build changes
-------------

  * Linux: xe-4380-1580579412915ac76344699e53124b580060302d -> xe-pw-159539v2

  IGT_8699: 0b67ab25f2eb58b296872c8c34474b79353727d5 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4380-1580579412915ac76344699e53124b580060302d: 1580579412915ac76344699e53124b580060302d
  xe-pw-159539v2: 159539v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v2/index.html

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Re: [PATCH v2 0/3] Fix Cx0 Suspend Resume issue

[Rodrigo Vivi]

On Wed, Jan 14, 2026 at 09:12:56AM +0530, Suraj Kandpal wrote:
> CX0 PHY currently has two issues which cause a hang when we try
> to suspend resume machine with a delay of 15mins and 1+ hour.
> This happens due to two reasons:
> 1) We do not follow the Enablement sequence where we need to
> enable our clock after PPS Enablement cycle
> 2) We do not make sure response ready and error bit are cleared
> in P2M_MSGBUS_STATUS before writing the transaction pending bit.
> This series aims to solve this.

Is there any Fixes: tag that we should add to any of the commits
in this series?

Also, next time, consider a fix as the first patch for easy backport
and the refactor on top.

Thanks,
Rodrigo.

> 
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> 
> Mika Kahola (1):
>   drm/i915/cx0: Split PLL enabling/disabling in two parts
> 
> Suraj Kandpal (2):
>   drm/i915/cx0: Clear response ready & error bit
>   drm/i915/cx0: Rename intel_clear_response_ready flag
> 
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 134 +++++++++++-------
>  drivers/gpu/drm/i915/display/intel_cx0_phy.h  |   4 +-
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c |   7 +-
>  drivers/gpu/drm/i915/display/intel_lt_phy.c   |   2 +-
>  4 files changed, 92 insertions(+), 55 deletions(-)
> 
> -- 
> 2.34.1
> 

RE: [PATCH v2 0/3] Fix Cx0 Suspend Resume issue

[Saarinen, Jani]

Hi, 
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of
> Rodrigo Vivi
> Sent: Wednesday, 14 January 2026 17.10
> To: Kandpal, Suraj <suraj.kandpal@intel.com>
> Cc: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org; Nautiyal,
> Ankit K <ankit.k.nautiyal@intel.com>
> Subject: Re: [PATCH v2 0/3] Fix Cx0 Suspend Resume issue
> 
> On Wed, Jan 14, 2026 at 09:12:56AM +0530, Suraj Kandpal wrote:
> > CX0 PHY currently has two issues which cause a hang when we try to
> > suspend resume machine with a delay of 15mins and 1+ hour.
> > This happens due to two reasons:
> > 1) We do not follow the Enablement sequence where we need to enable
> > our clock after PPS Enablement cycle
> > 2) We do not make sure response ready and error bit are cleared in
> > P2M_MSGBUS_STATUS before writing the transaction pending bit.
> > This series aims to solve this.
> 
> Is there any Fixes: tag that we should add to any of the commits in this series?
> 
> Also, next time, consider a fix as the first patch for easy backport and the
> refactor on top.
Looking at both i915 and xe CI results this is not really ready as is. 

Br,
Jani
> 
> Thanks,
> Rodrigo.
> 
> >
> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> >
> > Mika Kahola (1):
> >   drm/i915/cx0: Split PLL enabling/disabling in two parts
> >
> > Suraj Kandpal (2):
> >   drm/i915/cx0: Clear response ready & error bit
> >   drm/i915/cx0: Rename intel_clear_response_ready flag
> >
> >  drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 134 +++++++++++-------
> >  drivers/gpu/drm/i915/display/intel_cx0_phy.h  |   4 +-
> >  drivers/gpu/drm/i915/display/intel_dpll_mgr.c |   7 +-
> >  drivers/gpu/drm/i915/display/intel_lt_phy.c   |   2 +-
> >  4 files changed, 92 insertions(+), 55 deletions(-)
> >
> > --
> > 2.34.1
> >