* [PATCH v1 1/4] drm/xe/sysctrl: Add System Controller
2026-01-16 9:33 [PATCH v1 0/4] Introduce Xe Correctable Error Handling Raag Jadav
@ 2026-01-16 9:33 ` Raag Jadav
2026-01-16 9:33 ` [PATCH v1 2/4] drm/xe/sysctrl: Add system controller interrupt handler Raag Jadav
` (6 subsequent siblings)
7 siblings, 0 replies; 17+ messages in thread
From: Raag Jadav @ 2026-01-16 9:33 UTC (permalink / raw)
To: intel-xe
Cc: rodrigo.vivi, riana.tauro, michal.wajdeczko, matthew.d.roper,
umesh.nerlige.ramappa, soham.purkait, anoop.c.vijay, Raag Jadav
From: Anoop Vijay <anoop.c.vijay@intel.com>
Do not review, CI only.
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
---
drivers/gpu/drm/xe/Makefile | 2 +
drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h | 44 ++
drivers/gpu/drm/xe/xe_device.c | 5 +
drivers/gpu/drm/xe/xe_device_types.h | 6 +
drivers/gpu/drm/xe/xe_pci.c | 2 +
drivers/gpu/drm/xe/xe_pci_types.h | 1 +
drivers/gpu/drm/xe/xe_sysctrl.c | 70 +++
drivers/gpu/drm/xe/xe_sysctrl.h | 13 +
drivers/gpu/drm/xe/xe_sysctrl_mailbox.c | 429 ++++++++++++++++++
drivers/gpu/drm/xe/xe_sysctrl_mailbox.h | 35 ++
drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h | 36 ++
drivers/gpu/drm/xe/xe_sysctrl_types.h | 23 +
12 files changed, 666 insertions(+)
create mode 100644 drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h
create mode 100644 drivers/gpu/drm/xe/xe_sysctrl.c
create mode 100644 drivers/gpu/drm/xe/xe_sysctrl.h
create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_mailbox.c
create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_types.h
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 3a6a707638b5..ff567fa58119 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -121,6 +121,8 @@ xe-y += xe_bb.o \
xe_step.o \
xe_survivability_mode.o \
xe_sync.o \
+ xe_sysctrl.o \
+ xe_sysctrl_mailbox.o \
xe_tile.o \
xe_tile_sysfs.o \
xe_tlb_inval.o \
diff --git a/drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h b/drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h
new file mode 100644
index 000000000000..e0b630654fe3
--- /dev/null
+++ b/drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_SYSCTRL_REGS_H_
+#define _XE_SYSCTRL_REGS_H_
+
+#include "xe_regs.h"
+
+#define SYSCTRL_BASE_OFFSET 0xDB000
+#define SYSCTRL_BASE (SOC_BASE + SYSCTRL_BASE_OFFSET)
+#define SYSCTRL_MAILBOX_INDEX 0x03
+#define SYSCTRL_BAR_LENGTH 0x1000
+
+#define SYSCTRL_MB_CTRL XE_REG(SYSCTRL_BASE + 0x10)
+#define SYSCTRL_MB_CTRL_RUN_BUSY REG_BIT(31)
+#define SYSCTRL_MB_CTRL_IRQ REG_BIT(30)
+#define SYSCTRL_MB_CTRL_RUN_BUSY_OUT REG_BIT(29)
+#define SYSCTRL_MB_CTRL_PARAM3_MASK REG_GENMASK(28, 24)
+#define SYSCTRL_MB_CTRL_PARAM2_MASK REG_GENMASK(23, 16)
+#define SYSCTRL_MB_CTRL_PARAM1_MASK REG_GENMASK(15, 8)
+#define SYSCTRL_MB_CTRL_COMMAND_MASK REG_GENMASK(7, 0)
+
+#define SYSCTRL_MB_DATA0 XE_REG(SYSCTRL_BASE + 0x14)
+#define SYSCTRL_MB_DATA1 XE_REG(SYSCTRL_BASE + 0x18)
+#define SYSCTRL_MB_DATA2 XE_REG(SYSCTRL_BASE + 0x1C)
+#define SYSCTRL_MB_DATA3 XE_REG(SYSCTRL_BASE + 0x20)
+
+#define MKHI_FRAME_PHASE REG_BIT(24)
+#define MKHI_FRAME_CURRENT_MASK REG_GENMASK(21, 16)
+#define MKHI_FRAME_TOTAL_MASK REG_GENMASK(13, 8)
+#define MKHI_FRAME_COMMAND_MASK REG_GENMASK(7, 0)
+
+#define SYSCTRL_MB_FRAME_SIZE 16
+#define SYSCTRL_MB_MAX_FRAMES 64
+#define SYSCTRL_MB_MAX_MESSAGE_SIZE (SYSCTRL_MB_FRAME_SIZE * SYSCTRL_MB_MAX_FRAMES)
+#define SYSCTRL_MKHI_COMMAND 5
+
+#define SYSCTRL_MB_DEFAULT_TIMEOUT_MS 500
+#define SYSCTRL_MB_RETRY_TIMEOUT_MS 20
+#define SYSCTRL_MB_POLL_INTERVAL_US 100
+
+#endif /* _XE_SYSCTRL_REGS_H_ */
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index 495310a624b5..b45048803531 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -64,6 +64,7 @@
#include "xe_survivability_mode.h"
#include "xe_sriov.h"
#include "xe_svm.h"
+#include "xe_sysctrl.h"
#include "xe_tile.h"
#include "xe_ttm_stolen_mgr.h"
#include "xe_ttm_sys_mgr.h"
@@ -988,6 +989,10 @@ int xe_device_probe(struct xe_device *xe)
if (err)
goto err_unregister_display;
+ err = xe_sysctrl_init(xe);
+ if (err)
+ goto err_unregister_display;
+
err = xe_device_sysfs_init(xe);
if (err)
goto err_unregister_display;
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index f689766adcb1..4cb2a2c427cd 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -29,6 +29,7 @@
#include "xe_sriov_vf_ccs_types.h"
#include "xe_step_types.h"
#include "xe_survivability_mode_types.h"
+#include "xe_sysctrl_types.h"
#include "xe_tile_sriov_vf_types.h"
#include "xe_validation.h"
@@ -361,6 +362,8 @@ struct xe_device {
u8 has_soc_remapper_telem:1;
/** @info.has_sriov: Supports SR-IOV */
u8 has_sriov:1;
+ /** @info.has_sysctrl: Supports System Controller */
+ u8 has_sysctrl:1;
/** @info.has_usm: Device has unified shared memory support */
u8 has_usm:1;
/** @info.has_64bit_timestamp: Device supports 64-bit timestamps */
@@ -627,6 +630,9 @@ struct xe_device {
/** @heci_gsc: graphics security controller */
struct xe_heci_gsc heci_gsc;
+ /** @sc: System Controller */
+ struct xe_sysctrl sc;
+
/** @nvm: discrete graphics non-volatile memory */
struct intel_dg_nvm_dev *nvm;
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 09189ff3da44..26b3ede9657b 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -428,6 +428,7 @@ static const struct xe_device_desc cri_desc = {
.has_soc_remapper_sysctrl = true,
.has_soc_remapper_telem = true,
.has_sriov = true,
+ .has_sysctrl = true,
.max_gt_per_tile = 2,
.require_force_probe = true,
.va_bits = 57,
@@ -703,6 +704,7 @@ static int xe_info_init_early(struct xe_device *xe,
xe->info.has_soc_remapper_telem = desc->has_soc_remapper_telem;
xe->info.has_sriov = xe_configfs_primary_gt_allowed(to_pci_dev(xe->drm.dev)) &&
desc->has_sriov;
+ xe->info.has_sysctrl = desc->has_sysctrl;
xe->info.has_mem_copy_instr = desc->has_mem_copy_instr;
xe->info.skip_guc_pc = desc->skip_guc_pc;
xe->info.skip_mtcfg = desc->skip_mtcfg;
diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
index 20acc5349ee6..0027024072b1 100644
--- a/drivers/gpu/drm/xe/xe_pci_types.h
+++ b/drivers/gpu/drm/xe/xe_pci_types.h
@@ -57,6 +57,7 @@ struct xe_device_desc {
u8 has_soc_remapper_sysctrl:1;
u8 has_soc_remapper_telem:1;
u8 has_sriov:1;
+ u8 has_sysctrl:1;
u8 needs_scratch:1;
u8 skip_guc_pc:1;
u8 skip_mtcfg:1;
diff --git a/drivers/gpu/drm/xe/xe_sysctrl.c b/drivers/gpu/drm/xe/xe_sysctrl.c
new file mode 100644
index 000000000000..8daab7703247
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl.c
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#include <drm/drm_managed.h>
+#include <linux/device.h>
+#include <linux/mutex.h>
+
+#include "regs/xe_sysctrl_regs.h"
+#include "xe_device.h"
+#include "xe_printk.h"
+#include "xe_soc_remapper.h"
+#include "xe_sysctrl.h"
+#include "xe_sysctrl_mailbox.h"
+#include "xe_sysctrl_types.h"
+
+/**
+ * DOC: System Controller (sysctrl)
+ *
+ * The System Controller (sysctrl) is an embedded microcontroller in Intel GPUs
+ * responsible for managing various low-level platform functions. Communication
+ * between the driver and the System Controller occurs via a mailbox interface,
+ * enabling the exchange of commands and responses.
+ *
+ * This module provides initialization routines and helper functions to interact
+ * with the System Controller through the mailbox.
+ */
+
+static void xe_sysctrl_fini(void *arg)
+{
+ struct xe_device *xe = arg;
+
+ xe->soc_remapper.set_sysctrl_region(xe, 0);
+}
+
+/**
+ * xe_sysctrl_init - Initialize System Controller subsystem
+ * @xe: xe device instance
+ *
+ * Entry point for System Controller initialization, called from xe_device_probe.
+ * This function checks platform support and initializes the system controller.
+ *
+ * Return: 0 on success, error code on failure
+ */
+int xe_sysctrl_init(struct xe_device *xe)
+{
+ struct xe_sysctrl *sc = &xe->sc;
+ int ret;
+
+ if (!xe->info.has_sysctrl)
+ return 0;
+
+ if (!xe->soc_remapper.set_sysctrl_region)
+ return -ENODEV;
+
+ xe->soc_remapper.set_sysctrl_region(xe, SYSCTRL_MAILBOX_INDEX);
+
+ ret = devm_add_action_or_reset(xe->drm.dev, xe_sysctrl_fini, xe);
+ if (ret)
+ return ret;
+
+ ret = drmm_mutex_init(&xe->drm, &sc->cmd_lock);
+ if (ret)
+ return ret;
+
+ xe_sysctrl_mailbox_init(sc);
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/xe/xe_sysctrl.h b/drivers/gpu/drm/xe/xe_sysctrl.h
new file mode 100644
index 000000000000..ee7826fe4c98
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_SYSCTRL_H_
+#define _XE_SYSCTRL_H_
+
+struct xe_device;
+
+int xe_sysctrl_init(struct xe_device *xe);
+
+#endif /* _XE_SYSCTRL_H_ */
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.c b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.c
new file mode 100644
index 000000000000..97fe3498fcc7
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.c
@@ -0,0 +1,429 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#include <linux/bitfield.h>
+#include <linux/container_of.h>
+#include <linux/errno.h>
+#include <linux/minmax.h>
+#include <linux/mutex.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/types.h>
+
+#include "regs/xe_sysctrl_regs.h"
+#include "xe_device.h"
+#include "xe_device_types.h"
+#include "xe_mmio.h"
+#include "xe_pm.h"
+#include "xe_printk.h"
+#include "xe_sysctrl.h"
+#include "xe_sysctrl_mailbox.h"
+#include "xe_sysctrl_mailbox_types.h"
+#include "xe_sysctrl_types.h"
+
+#define MKHI_HDR_GROUP_ID_MASK GENMASK(7, 0)
+#define MKHI_HDR_COMMAND_MASK GENMASK(14, 8)
+#define MKHI_HDR_IS_RESPONSE BIT(15)
+#define MKHI_HDR_RESERVED_MASK GENMASK(23, 16)
+#define MKHI_HDR_RESULT_MASK GENMASK(31, 24)
+
+#define XE_SYSCTRL_MKHI_HDR_GROUP_ID(hdr) \
+ FIELD_GET(MKHI_HDR_GROUP_ID_MASK, le32_to_cpu((hdr)->data))
+
+#define XE_SYSCTRL_MKHI_HDR_COMMAND(hdr) \
+ FIELD_GET(MKHI_HDR_COMMAND_MASK, le32_to_cpu((hdr)->data))
+
+#define XE_SYSCTRL_MKHI_HDR_IS_RESPONSE(hdr) \
+ FIELD_GET(MKHI_HDR_IS_RESPONSE, le32_to_cpu((hdr)->data))
+
+#define XE_SYSCTRL_MKHI_HDR_RESULT(hdr) \
+ FIELD_GET(MKHI_HDR_RESULT_MASK, le32_to_cpu((hdr)->data))
+
+static struct xe_device *sc_to_xe(struct xe_sysctrl *sc)
+{
+ return container_of(sc, struct xe_device, sc);
+}
+
+static bool xe_sysctrl_mailbox_wait_bit_clear(struct xe_device *xe, u32 bit_mask,
+ unsigned int timeout_ms)
+{
+ struct xe_mmio *mmio = xe_root_tile_mmio(xe);
+ int ret;
+
+ ret = xe_mmio_wait32_not(mmio, SYSCTRL_MB_CTRL, bit_mask, bit_mask,
+ timeout_ms * 1000, NULL, false);
+
+ return ret == 0;
+}
+
+static bool xe_sysctrl_mailbox_wait_bit_set(struct xe_device *xe, u32 bit_mask,
+ unsigned int timeout_ms)
+{
+ struct xe_mmio *mmio = xe_root_tile_mmio(xe);
+ int ret;
+
+ ret = xe_mmio_wait32(mmio, SYSCTRL_MB_CTRL, bit_mask, bit_mask,
+ timeout_ms * 1000, NULL, false);
+
+ return ret == 0;
+}
+
+static int xe_sysctrl_mailbox_write_frame(struct xe_device *xe, const void *frame,
+ size_t len)
+{
+ static const struct xe_reg regs[] = {
+ SYSCTRL_MB_DATA0, SYSCTRL_MB_DATA1, SYSCTRL_MB_DATA2, SYSCTRL_MB_DATA3
+ };
+ u32 val[SYSCTRL_MB_FRAME_SIZE / sizeof(u32)] = {0};
+ struct xe_mmio *mmio = xe_root_tile_mmio(xe);
+ u32 dw = DIV_ROUND_UP(len, sizeof(u32));
+ u32 i;
+
+ memcpy(val, frame, len);
+
+ for (i = 0; i < dw; i++)
+ xe_mmio_write32(mmio, regs[i], val[i]);
+
+ return 0;
+}
+
+static int xe_sysctrl_mailbox_read_frame(struct xe_device *xe, void *frame,
+ size_t len)
+{
+ static const struct xe_reg regs[] = {
+ SYSCTRL_MB_DATA0, SYSCTRL_MB_DATA1, SYSCTRL_MB_DATA2, SYSCTRL_MB_DATA3
+ };
+ u32 val[SYSCTRL_MB_FRAME_SIZE / sizeof(u32)] = {0};
+ struct xe_mmio *mmio = xe_root_tile_mmio(xe);
+ u32 dw = DIV_ROUND_UP(len, sizeof(u32));
+ u32 i;
+
+ for (i = 0; i < dw; i++)
+ val[i] = xe_mmio_read32(mmio, regs[i]);
+
+ memcpy(frame, val, len);
+
+ return 0;
+}
+
+static void xe_sysctrl_mailbox_clear_response(struct xe_device *xe)
+{
+ struct xe_mmio *mmio = xe_root_tile_mmio(xe);
+
+ xe_mmio_rmw32(mmio, SYSCTRL_MB_CTRL, SYSCTRL_MB_CTRL_RUN_BUSY_OUT, 0);
+}
+
+static int xe_sysctrl_mailbox_prepare_command(struct xe_device *xe,
+ u8 group_id, u8 command,
+ const void *data_in, size_t data_in_len,
+ u8 **mbox_cmd, size_t *cmd_size)
+{
+ struct xe_sysctrl_mailbox_mkhi_msg_hdr *mkhi_hdr;
+ size_t size;
+ u8 *buffer;
+
+ size = sizeof(*mkhi_hdr) + data_in_len;
+ if (size > SYSCTRL_MB_MAX_MESSAGE_SIZE) {
+ xe_err(xe, "sysctrl: Message too large: %zu bytes\n", size);
+ return -EINVAL;
+ }
+
+ buffer = kmalloc(size, GFP_KERNEL);
+ if (!buffer)
+ return -ENOMEM;
+
+ mkhi_hdr = (struct xe_sysctrl_mailbox_mkhi_msg_hdr *)buffer;
+ mkhi_hdr->data = cpu_to_le32(FIELD_PREP(MKHI_HDR_GROUP_ID_MASK, group_id) |
+ FIELD_PREP(MKHI_HDR_COMMAND_MASK, command & 0x7F) |
+ FIELD_PREP(MKHI_HDR_IS_RESPONSE, 0) |
+ FIELD_PREP(MKHI_HDR_RESERVED_MASK, 0) |
+ FIELD_PREP(MKHI_HDR_RESULT_MASK, 0));
+
+ if (data_in && data_in_len)
+ memcpy(buffer + sizeof(*mkhi_hdr), data_in, data_in_len);
+
+ *mbox_cmd = buffer;
+ *cmd_size = size;
+
+ return 0;
+}
+
+static int xe_sysctrl_mailbox_send_frames(struct xe_device *xe,
+ const u8 *mbox_cmd,
+ size_t cmd_size, unsigned int timeout_ms)
+{
+ struct xe_mmio *mmio = xe_root_tile_mmio(xe);
+ u32 ctrl_reg, total_frames, frame;
+ struct xe_sysctrl *sc = &xe->sc;
+ size_t bytes_sent, frame_size;
+
+ total_frames = DIV_ROUND_UP(cmd_size, SYSCTRL_MB_FRAME_SIZE);
+
+ if (!xe_sysctrl_mailbox_wait_bit_clear(xe, SYSCTRL_MB_CTRL_RUN_BUSY, timeout_ms)) {
+ xe_err(xe, "sysctrl: Mailbox busy\n");
+ return -EBUSY;
+ }
+
+ sc->phase_bit ^= 1;
+ bytes_sent = 0;
+
+ for (frame = 0; frame < total_frames; frame++) {
+ frame_size = min(cmd_size - bytes_sent, (size_t)SYSCTRL_MB_FRAME_SIZE);
+
+ if (xe_sysctrl_mailbox_write_frame(xe, mbox_cmd + bytes_sent, frame_size)) {
+ xe_err(xe, "sysctrl: Failed to write frame %u\n", frame);
+ sc->phase_bit ^= 1;
+ return -EIO;
+ }
+
+ ctrl_reg = SYSCTRL_MB_CTRL_RUN_BUSY |
+ FIELD_PREP(MKHI_FRAME_CURRENT_MASK, frame) |
+ FIELD_PREP(MKHI_FRAME_TOTAL_MASK, total_frames - 1) |
+ FIELD_PREP(MKHI_FRAME_COMMAND_MASK, SYSCTRL_MKHI_COMMAND) |
+ (sc->phase_bit ? MKHI_FRAME_PHASE : 0);
+
+ xe_mmio_write32(mmio, SYSCTRL_MB_CTRL, ctrl_reg);
+
+ if (!xe_sysctrl_mailbox_wait_bit_clear(xe, SYSCTRL_MB_CTRL_RUN_BUSY, timeout_ms)) {
+ xe_err(xe, "sysctrl: Frame %u acknowledgment timeout\n", frame);
+ return -ETIMEDOUT;
+ }
+
+ bytes_sent += frame_size;
+ }
+
+ return 0;
+}
+
+static int xe_sysctrl_mailbox_process_first_frame(struct xe_device *xe,
+ const struct xe_sysctrl_mailbox_mkhi_msg_hdr *req,
+ void *out,
+ size_t frame_size,
+ size_t *payload_bytes)
+{
+ struct xe_sysctrl_mailbox_mkhi_msg_hdr *resp_hdr;
+ size_t hdr_size = sizeof(*resp_hdr);
+ size_t payload_size;
+ u32 frame_data[SYSCTRL_MB_FRAME_SIZE / sizeof(u32)];
+ int ret;
+
+ ret = xe_sysctrl_mailbox_read_frame(xe, frame_data, frame_size);
+ if (ret)
+ return ret;
+
+ resp_hdr = (struct xe_sysctrl_mailbox_mkhi_msg_hdr *)frame_data;
+
+ if (!XE_SYSCTRL_MKHI_HDR_IS_RESPONSE(resp_hdr) ||
+ XE_SYSCTRL_MKHI_HDR_GROUP_ID(resp_hdr) != XE_SYSCTRL_MKHI_HDR_GROUP_ID(req) ||
+ XE_SYSCTRL_MKHI_HDR_COMMAND(resp_hdr) != XE_SYSCTRL_MKHI_HDR_COMMAND(req)) {
+ xe_err(xe, "SC: Response header mismatch\n");
+ return -EPROTO;
+ }
+
+ if (XE_SYSCTRL_MKHI_HDR_RESULT(resp_hdr) != 0) {
+ xe_err(xe, "SC: Firmware error: 0x%02lx\n",
+ XE_SYSCTRL_MKHI_HDR_RESULT(resp_hdr));
+ return -EIO;
+ }
+
+ payload_size = frame_size - hdr_size;
+ if (payload_size > 0)
+ memcpy(out, (u8 *)frame_data + hdr_size, payload_size);
+
+ *payload_bytes = payload_size;
+
+ xe_sysctrl_mailbox_clear_response(xe);
+
+ return 0;
+}
+
+static int xe_sysctrl_mailbox_process_frame(struct xe_device *xe,
+ void *out, size_t frame_size,
+ unsigned int timeout_ms)
+{
+ int ret;
+
+ if (!xe_sysctrl_mailbox_wait_bit_set(xe, SYSCTRL_MB_CTRL_RUN_BUSY_OUT, timeout_ms)) {
+ xe_err(xe, "sysctrl: Response frame timeout\n");
+ return -ETIMEDOUT;
+ }
+
+ ret = xe_sysctrl_mailbox_read_frame(xe, out, frame_size);
+ if (ret)
+ return ret;
+
+ xe_sysctrl_mailbox_clear_response(xe);
+
+ return 0;
+}
+
+static int xe_sysctrl_mailbox_receive_frames(struct xe_device *xe,
+ const struct xe_sysctrl_mailbox_mkhi_msg_hdr *req,
+ void *data_out, size_t data_out_len,
+ size_t *rdata_len, unsigned int timeout_ms)
+{
+ struct xe_sysctrl_mailbox_mkhi_msg_hdr *mkhi_hdr;
+ struct xe_mmio *mmio = xe_root_tile_mmio(xe);
+ size_t hdr_size = sizeof(*mkhi_hdr);
+ u32 ctrl_reg, total_frames, frame;
+ size_t received = 0;
+ u8 *out = data_out;
+ size_t frame_size;
+ int ret = 0;
+
+ if (!xe_sysctrl_mailbox_wait_bit_set(xe, SYSCTRL_MB_CTRL_RUN_BUSY_OUT, timeout_ms)) {
+ xe_err(xe, "sysctrl: Response frame 0 timeout\n");
+ return -ETIMEDOUT;
+ }
+
+ ctrl_reg = xe_mmio_read32(mmio, SYSCTRL_MB_CTRL);
+ total_frames = FIELD_GET(MKHI_FRAME_TOTAL_MASK, ctrl_reg) + 1;
+
+ if (total_frames == 1)
+ frame_size = min(hdr_size + data_out_len, (size_t)SYSCTRL_MB_FRAME_SIZE);
+ else
+ frame_size = SYSCTRL_MB_FRAME_SIZE;
+
+ ret = xe_sysctrl_mailbox_process_first_frame(xe, req, out, frame_size, &received);
+ if (ret)
+ return ret;
+
+ out += received;
+
+ for (frame = 1; frame < total_frames; frame++) {
+ size_t remaining = data_out_len - received;
+
+ frame_size = min_t(size_t, remaining, SYSCTRL_MB_FRAME_SIZE);
+
+ ret = xe_sysctrl_mailbox_process_frame(xe, out, frame_size, timeout_ms);
+ if (ret)
+ break;
+
+ received += frame_size;
+ out += frame_size;
+ }
+
+ *rdata_len = received;
+
+ return ret;
+}
+
+static int xe_sysctrl_mailbox_send_command(struct xe_device *xe,
+ const u8 *mbox_cmd, size_t cmd_size,
+ void *data_out, size_t data_out_len,
+ size_t *rdata_len, unsigned int timeout_ms)
+{
+ const struct xe_sysctrl_mailbox_mkhi_msg_hdr *mkhi_hdr;
+ size_t received;
+ int ret;
+
+ ret = xe_sysctrl_mailbox_send_frames(xe, mbox_cmd, cmd_size, timeout_ms);
+ if (ret)
+ return ret;
+
+ if (!data_out || !rdata_len)
+ return 0;
+
+ mkhi_hdr = (const struct xe_sysctrl_mailbox_mkhi_msg_hdr *)mbox_cmd;
+
+ ret = xe_sysctrl_mailbox_receive_frames(xe, mkhi_hdr, data_out, data_out_len,
+ &received, timeout_ms);
+ if (ret)
+ return ret;
+
+ *rdata_len = received;
+
+ return 0;
+}
+
+/**
+ * xe_sysctrl_mailbox_init - Initialize System Controller mailbox interface
+ * @sc: System controller structure
+ *
+ * Initialize system controller mailbox interface for communication.
+ */
+void xe_sysctrl_mailbox_init(struct xe_sysctrl *sc)
+{
+ struct xe_device *xe = sc_to_xe(sc);
+ struct xe_mmio *mmio = xe_root_tile_mmio(xe);
+ u32 ctrl_reg;
+
+ ctrl_reg = xe_mmio_read32(mmio, SYSCTRL_MB_CTRL);
+ sc->phase_bit = (ctrl_reg & MKHI_FRAME_PHASE) ? 1 : 0;
+
+ xe_mmio_rmw32(mmio, SYSCTRL_MB_CTRL, MKHI_FRAME_PHASE, 0);
+}
+
+/**
+ * xe_sysctrl_send_command - Send command to System Controller via mailbox
+ * @xe: XE device instance
+ * @cmd: Pointer to xe_sysctrl_mailbox_command structure
+ * @rdata_len: Pointer to store actual response data size (can be NULL)
+ *
+ * Send a command to the System Controller using MKHI protocol. Handles
+ * command preparation, fragmentation, transmission, and response reception.
+ *
+ * Return: 0 on success, negative error code on failure
+ */
+int xe_sysctrl_send_command(struct xe_device *xe,
+ struct xe_sysctrl_mailbox_command *cmd,
+ size_t *rdata_len)
+{
+ struct xe_sysctrl *sc = &xe->sc;
+ u8 group_id, command_code;
+ u8 *mbox_cmd = NULL;
+ size_t cmd_size = 0;
+ int ret = 0;
+
+ if (!xe) {
+ pr_err("sysctrl: Invalid device handle\n");
+ return -EINVAL;
+ }
+
+ if (!cmd) {
+ xe_err(xe, "sysctrl: Invalid command buffer\n");
+ return -EINVAL;
+ }
+
+ if (!xe->info.has_sysctrl)
+ return -ENODEV;
+
+ group_id = XE_SYSCTRL_APP_HDR_GROUP_ID(&cmd->header);
+ command_code = XE_SYSCTRL_APP_HDR_COMMAND(&cmd->header);
+
+ if (!cmd->data_in && cmd->data_in_len) {
+ xe_err(xe, "sysctrl: Invalid input parameters\n");
+ return -EINVAL;
+ }
+
+ if (!cmd->data_out && cmd->data_out_len) {
+ xe_err(xe, "sysctrl: Invalid output parameters\n");
+ return -EINVAL;
+ }
+
+ might_sleep();
+
+ ret = xe_sysctrl_mailbox_prepare_command(xe, group_id, command_code,
+ cmd->data_in, cmd->data_in_len,
+ &mbox_cmd, &cmd_size);
+ if (ret) {
+ xe_err(xe, "sysctrl: Failed to prepare command: %d\n", ret);
+ return ret;
+ }
+
+ guard(xe_pm_runtime)(xe);
+
+ guard(mutex)(&sc->cmd_lock);
+
+ ret = xe_sysctrl_mailbox_send_command(xe, mbox_cmd, cmd_size,
+ cmd->data_out, cmd->data_out_len, rdata_len,
+ SYSCTRL_MB_DEFAULT_TIMEOUT_MS);
+ if (ret)
+ xe_err(xe, "sysctrl: Mailbox command failed: %d\n", ret);
+
+ kfree(mbox_cmd);
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
new file mode 100644
index 000000000000..750b7528bab2
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef __XE_SYSCTRL_MAILBOX_H__
+#define __XE_SYSCTRL_MAILBOX_H__
+
+#include <linux/bitfield.h>
+#include <linux/types.h>
+
+struct xe_sysctrl;
+struct xe_device;
+struct xe_sysctrl_mailbox_command;
+
+#define APP_HDR_GROUP_ID_MASK GENMASK(7, 0)
+#define APP_HDR_COMMAND_MASK GENMASK(15, 8)
+#define APP_HDR_VERSION_MASK GENMASK(23, 16)
+#define APP_HDR_RESERVED_MASK GENMASK(31, 24)
+
+#define XE_SYSCTRL_APP_HDR_GROUP_ID(hdr) \
+ FIELD_GET(APP_HDR_GROUP_ID_MASK, le32_to_cpu((hdr)->data))
+
+#define XE_SYSCTRL_APP_HDR_COMMAND(hdr) \
+ FIELD_GET(APP_HDR_COMMAND_MASK, le32_to_cpu((hdr)->data))
+
+#define XE_SYSCTRL_APP_HDR_VERSION(hdr) \
+ FIELD_GET(APP_HDR_VERSION_MASK, le32_to_cpu((hdr)->data))
+
+void xe_sysctrl_mailbox_init(struct xe_sysctrl *sc);
+int xe_sysctrl_send_command(struct xe_device *xe,
+ struct xe_sysctrl_mailbox_command *cmd,
+ size_t *rdata_len);
+
+#endif /* __XE_SYSCTRL_MAILBOX_H__ */
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
new file mode 100644
index 000000000000..1f315ad1b996
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef __XE_SYSCTRL_MAILBOX_TYPES_H__
+#define __XE_SYSCTRL_MAILBOX_TYPES_H__
+
+#include <linux/types.h>
+
+struct xe_sysctrl_mailbox_mkhi_msg_hdr {
+ __le32 data;
+} __packed;
+
+struct xe_sysctrl_mailbox_app_msg_hdr {
+ __le32 data;
+} __packed;
+
+struct xe_sysctrl_mailbox_command {
+ /** @header: Application message header containing command information */
+ struct xe_sysctrl_mailbox_app_msg_hdr header;
+
+ /** @data_in: Pointer to input payload data (can be NULL if no input data) */
+ void *data_in;
+
+ /** @data_in_len: Size of input payload in bytes (0 if no input data) */
+ size_t data_in_len;
+
+ /** @data_out: Pointer to output buffer for response data (can be NULL if no response) */
+ void *data_out;
+
+ /** @data_out_len: Size of output buffer in bytes (0 if no response expected) */
+ size_t data_out_len;
+};
+
+#endif /* __XE_SYSCTRL_MAILBOX_TYPES_H__ */
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_types.h b/drivers/gpu/drm/xe/xe_sysctrl_types.h
new file mode 100644
index 000000000000..88a34967688b
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl_types.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_SYSCTRL_TYPES_H_
+#define _XE_SYSCTRL_TYPES_H_
+
+#include <linux/mutex.h>
+#include <linux/types.h>
+
+/**
+ * struct xe_sysctrl - System Controller driver context
+ */
+struct xe_sysctrl {
+ /** @cmd_lock: Mutex protecting mailbox command operations */
+ struct mutex cmd_lock;
+
+ /** @phase_bit: MKHI message boundary phase toggle bit */
+ u32 phase_bit;
+};
+
+#endif /* _XE_SYSCTRL_TYPES_H_ */
--
2.43.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v1 2/4] drm/xe/sysctrl: Add system controller interrupt handler
2026-01-16 9:33 [PATCH v1 0/4] Introduce Xe Correctable Error Handling Raag Jadav
2026-01-16 9:33 ` [PATCH v1 1/4] drm/xe/sysctrl: Add System Controller Raag Jadav
@ 2026-01-16 9:33 ` Raag Jadav
2026-01-16 21:30 ` Matthew Brost
2026-01-20 8:30 ` [v1,2/4] " Mallesh, Koujalagi
2026-01-16 9:33 ` [PATCH v1 3/4] drm/xe/sysctrl: Add system controller event support Raag Jadav
` (5 subsequent siblings)
7 siblings, 2 replies; 17+ messages in thread
From: Raag Jadav @ 2026-01-16 9:33 UTC (permalink / raw)
To: intel-xe
Cc: rodrigo.vivi, riana.tauro, michal.wajdeczko, matthew.d.roper,
umesh.nerlige.ramappa, soham.purkait, anoop.c.vijay, Raag Jadav
Add system controller interrupt handler which is denoted by 11th bit in
GFX master interrupt register. While at it, add ordered workqueue for
scheduling system controller work.
Co-developed-by: Soham Purkait <soham.purkait@intel.com>
Signed-off-by: Soham Purkait <soham.purkait@intel.com>
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
---
drivers/gpu/drm/xe/regs/xe_irq_regs.h | 1 +
drivers/gpu/drm/xe/xe_irq.c | 2 ++
drivers/gpu/drm/xe/xe_sysctrl.c | 39 +++++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_sysctrl.h | 3 +++
drivers/gpu/drm/xe/xe_sysctrl_types.h | 7 +++++
5 files changed, 52 insertions(+)
diff --git a/drivers/gpu/drm/xe/regs/xe_irq_regs.h b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
index 9d74f454d3ff..1d6b976c4de0 100644
--- a/drivers/gpu/drm/xe/regs/xe_irq_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
@@ -22,6 +22,7 @@
#define DISPLAY_IRQ REG_BIT(16)
#define SOC_H2DMEMINT_IRQ REG_BIT(13)
#define I2C_IRQ REG_BIT(12)
+#define SYSCTRL_IRQ REG_BIT(11)
#define GT_DW_IRQ(x) REG_BIT(x)
/*
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index 7560a45f7f64..9e49e2241da4 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -24,6 +24,7 @@
#include "xe_mmio.h"
#include "xe_pxp.h"
#include "xe_sriov.h"
+#include "xe_sysctrl.h"
#include "xe_tile.h"
/*
@@ -525,6 +526,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
xe_heci_csc_irq_handler(xe, master_ctl);
xe_display_irq_handler(xe, master_ctl);
xe_i2c_irq_handler(xe, master_ctl);
+ xe_sysctrl_irq_handler(xe, master_ctl);
xe_mert_irq_handler(xe, master_ctl);
gu_misc_iir = gu_misc_irq_ack(xe, master_ctl);
}
diff --git a/drivers/gpu/drm/xe/xe_sysctrl.c b/drivers/gpu/drm/xe/xe_sysctrl.c
index 8daab7703247..1d78916dd6ad 100644
--- a/drivers/gpu/drm/xe/xe_sysctrl.c
+++ b/drivers/gpu/drm/xe/xe_sysctrl.c
@@ -7,6 +7,7 @@
#include <linux/device.h>
#include <linux/mutex.h>
+#include "regs/xe_irq_regs.h"
#include "regs/xe_sysctrl_regs.h"
#include "xe_device.h"
#include "xe_printk.h"
@@ -27,9 +28,17 @@
* with the System Controller through the mailbox.
*/
+static void xe_sysctrl_work(struct work_struct *work)
+{
+}
+
static void xe_sysctrl_fini(void *arg)
{
struct xe_device *xe = arg;
+ struct xe_sysctrl *sc = &xe->sc;
+
+ cancel_work_sync(&sc->work);
+ destroy_workqueue(sc->wq);
xe->soc_remapper.set_sysctrl_region(xe, 0);
}
@@ -56,6 +65,14 @@ int xe_sysctrl_init(struct xe_device *xe)
xe->soc_remapper.set_sysctrl_region(xe, SYSCTRL_MAILBOX_INDEX);
+ INIT_WORK(&sc->work, xe_sysctrl_work);
+
+ sc->wq = alloc_ordered_workqueue("sysctrl-ordered-wq", 0);
+ if (!sc->wq) {
+ ret = -ENOMEM;
+ goto err_sysctrl_fini;
+ }
+
ret = devm_add_action_or_reset(xe->drm.dev, xe_sysctrl_fini, xe);
if (ret)
return ret;
@@ -67,4 +84,26 @@ int xe_sysctrl_init(struct xe_device *xe)
xe_sysctrl_mailbox_init(sc);
return 0;
+
+err_sysctrl_fini:
+ xe_sysctrl_fini(xe);
+ return ret;
+}
+
+/**
+ * xe_sysctrl_irq_handler: Handler for System Controller interrupts
+ * @xe: xe device instance
+ * @master_ctl: interrupt register
+ *
+ * Handle interrupts generated by System Controller.
+ */
+void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl)
+{
+ struct xe_sysctrl *sc = &xe->sc;
+
+ if (!xe->info.has_sysctrl)
+ return;
+
+ if (master_ctl & SYSCTRL_IRQ)
+ queue_work(sc->wq, &sc->work);
}
diff --git a/drivers/gpu/drm/xe/xe_sysctrl.h b/drivers/gpu/drm/xe/xe_sysctrl.h
index ee7826fe4c98..5919310b9db9 100644
--- a/drivers/gpu/drm/xe/xe_sysctrl.h
+++ b/drivers/gpu/drm/xe/xe_sysctrl.h
@@ -6,8 +6,11 @@
#ifndef _XE_SYSCTRL_H_
#define _XE_SYSCTRL_H_
+#include <linux/types.h>
+
struct xe_device;
int xe_sysctrl_init(struct xe_device *xe);
+void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl);
#endif /* _XE_SYSCTRL_H_ */
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_types.h b/drivers/gpu/drm/xe/xe_sysctrl_types.h
index 88a34967688b..14fc80dfee6e 100644
--- a/drivers/gpu/drm/xe/xe_sysctrl_types.h
+++ b/drivers/gpu/drm/xe/xe_sysctrl_types.h
@@ -8,6 +8,7 @@
#include <linux/mutex.h>
#include <linux/types.h>
+#include <linux/workqueue_types.h>
/**
* struct xe_sysctrl - System Controller driver context
@@ -18,6 +19,12 @@ struct xe_sysctrl {
/** @phase_bit: MKHI message boundary phase toggle bit */
u32 phase_bit;
+
+ /** @wq: Queue for sysctrl work */
+ struct workqueue_struct *wq;
+
+ /** @work: Worker for pending events */
+ struct work_struct work;
};
#endif /* _XE_SYSCTRL_TYPES_H_ */
--
2.43.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH v1 2/4] drm/xe/sysctrl: Add system controller interrupt handler
2026-01-16 9:33 ` [PATCH v1 2/4] drm/xe/sysctrl: Add system controller interrupt handler Raag Jadav
@ 2026-01-16 21:30 ` Matthew Brost
2026-01-17 7:13 ` Raag Jadav
2026-01-20 8:30 ` [v1,2/4] " Mallesh, Koujalagi
1 sibling, 1 reply; 17+ messages in thread
From: Matthew Brost @ 2026-01-16 21:30 UTC (permalink / raw)
To: Raag Jadav
Cc: intel-xe, rodrigo.vivi, riana.tauro, michal.wajdeczko,
matthew.d.roper, umesh.nerlige.ramappa, soham.purkait,
anoop.c.vijay
On Fri, Jan 16, 2026 at 03:03:31PM +0530, Raag Jadav wrote:
> Add system controller interrupt handler which is denoted by 11th bit in
> GFX master interrupt register. While at it, add ordered workqueue for
> scheduling system controller work.
>
> Co-developed-by: Soham Purkait <soham.purkait@intel.com>
> Signed-off-by: Soham Purkait <soham.purkait@intel.com>
> Signed-off-by: Raag Jadav <raag.jadav@intel.com>
> ---
> drivers/gpu/drm/xe/regs/xe_irq_regs.h | 1 +
> drivers/gpu/drm/xe/xe_irq.c | 2 ++
> drivers/gpu/drm/xe/xe_sysctrl.c | 39 +++++++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_sysctrl.h | 3 +++
> drivers/gpu/drm/xe/xe_sysctrl_types.h | 7 +++++
> 5 files changed, 52 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_irq_regs.h b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> index 9d74f454d3ff..1d6b976c4de0 100644
> --- a/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> @@ -22,6 +22,7 @@
> #define DISPLAY_IRQ REG_BIT(16)
> #define SOC_H2DMEMINT_IRQ REG_BIT(13)
> #define I2C_IRQ REG_BIT(12)
> +#define SYSCTRL_IRQ REG_BIT(11)
> #define GT_DW_IRQ(x) REG_BIT(x)
>
> /*
> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> index 7560a45f7f64..9e49e2241da4 100644
> --- a/drivers/gpu/drm/xe/xe_irq.c
> +++ b/drivers/gpu/drm/xe/xe_irq.c
> @@ -24,6 +24,7 @@
> #include "xe_mmio.h"
> #include "xe_pxp.h"
> #include "xe_sriov.h"
> +#include "xe_sysctrl.h"
> #include "xe_tile.h"
>
> /*
> @@ -525,6 +526,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
> xe_heci_csc_irq_handler(xe, master_ctl);
> xe_display_irq_handler(xe, master_ctl);
> xe_i2c_irq_handler(xe, master_ctl);
> + xe_sysctrl_irq_handler(xe, master_ctl);
> xe_mert_irq_handler(xe, master_ctl);
> gu_misc_iir = gu_misc_irq_ack(xe, master_ctl);
> }
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl.c b/drivers/gpu/drm/xe/xe_sysctrl.c
> index 8daab7703247..1d78916dd6ad 100644
> --- a/drivers/gpu/drm/xe/xe_sysctrl.c
> +++ b/drivers/gpu/drm/xe/xe_sysctrl.c
> @@ -7,6 +7,7 @@
> #include <linux/device.h>
> #include <linux/mutex.h>
>
> +#include "regs/xe_irq_regs.h"
> #include "regs/xe_sysctrl_regs.h"
> #include "xe_device.h"
> #include "xe_printk.h"
> @@ -27,9 +28,17 @@
> * with the System Controller through the mailbox.
> */
>
> +static void xe_sysctrl_work(struct work_struct *work)
> +{
> +}
> +
> static void xe_sysctrl_fini(void *arg)
> {
> struct xe_device *xe = arg;
> + struct xe_sysctrl *sc = &xe->sc;
> +
> + cancel_work_sync(&sc->work);
> + destroy_workqueue(sc->wq);
>
> xe->soc_remapper.set_sysctrl_region(xe, 0);
> }
> @@ -56,6 +65,14 @@ int xe_sysctrl_init(struct xe_device *xe)
>
> xe->soc_remapper.set_sysctrl_region(xe, SYSCTRL_MAILBOX_INDEX);
>
> + INIT_WORK(&sc->work, xe_sysctrl_work);
> +
> + sc->wq = alloc_ordered_workqueue("sysctrl-ordered-wq", 0);
We do have drmm_alloc_ordered_workqueue, so you don’t need to manually
clean up the WQ. We don’t use it as widely as we should in Xe, as it was
added after we merged, but we should use that helper going forward.
I do have a question—does this require a dedicated WQ though? i.e.,
would a system WQ work here? We allocate a lot of WQs in Xe, but
typically that’s done when we really care about ordering. For example,
we may have multiple work_items scheduled on a WQ but want only one of
them executing at any given time, so we schedule them on a single
dedicated WQ. Here you only have one work_item, so I believe you can
probably just use one of the system WQs.
Matt
> + if (!sc->wq) {
> + ret = -ENOMEM;
> + goto err_sysctrl_fini;
> + }
> +
> ret = devm_add_action_or_reset(xe->drm.dev, xe_sysctrl_fini, xe);
> if (ret)
> return ret;
> @@ -67,4 +84,26 @@ int xe_sysctrl_init(struct xe_device *xe)
> xe_sysctrl_mailbox_init(sc);
>
> return 0;
> +
> +err_sysctrl_fini:
> + xe_sysctrl_fini(xe);
> + return ret;
> +}
> +
> +/**
> + * xe_sysctrl_irq_handler: Handler for System Controller interrupts
> + * @xe: xe device instance
> + * @master_ctl: interrupt register
> + *
> + * Handle interrupts generated by System Controller.
> + */
> +void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl)
> +{
> + struct xe_sysctrl *sc = &xe->sc;
> +
> + if (!xe->info.has_sysctrl)
> + return;
> +
> + if (master_ctl & SYSCTRL_IRQ)
> + queue_work(sc->wq, &sc->work);
> }
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl.h b/drivers/gpu/drm/xe/xe_sysctrl.h
> index ee7826fe4c98..5919310b9db9 100644
> --- a/drivers/gpu/drm/xe/xe_sysctrl.h
> +++ b/drivers/gpu/drm/xe/xe_sysctrl.h
> @@ -6,8 +6,11 @@
> #ifndef _XE_SYSCTRL_H_
> #define _XE_SYSCTRL_H_
>
> +#include <linux/types.h>
> +
> struct xe_device;
>
> int xe_sysctrl_init(struct xe_device *xe);
> +void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl);
>
> #endif /* _XE_SYSCTRL_H_ */
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl_types.h b/drivers/gpu/drm/xe/xe_sysctrl_types.h
> index 88a34967688b..14fc80dfee6e 100644
> --- a/drivers/gpu/drm/xe/xe_sysctrl_types.h
> +++ b/drivers/gpu/drm/xe/xe_sysctrl_types.h
> @@ -8,6 +8,7 @@
>
> #include <linux/mutex.h>
> #include <linux/types.h>
> +#include <linux/workqueue_types.h>
>
> /**
> * struct xe_sysctrl - System Controller driver context
> @@ -18,6 +19,12 @@ struct xe_sysctrl {
>
> /** @phase_bit: MKHI message boundary phase toggle bit */
> u32 phase_bit;
> +
> + /** @wq: Queue for sysctrl work */
> + struct workqueue_struct *wq;
> +
> + /** @work: Worker for pending events */
> + struct work_struct work;
> };
>
> #endif /* _XE_SYSCTRL_TYPES_H_ */
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH v1 2/4] drm/xe/sysctrl: Add system controller interrupt handler
2026-01-16 21:30 ` Matthew Brost
@ 2026-01-17 7:13 ` Raag Jadav
0 siblings, 0 replies; 17+ messages in thread
From: Raag Jadav @ 2026-01-17 7:13 UTC (permalink / raw)
To: Matthew Brost
Cc: intel-xe, rodrigo.vivi, riana.tauro, michal.wajdeczko,
matthew.d.roper, umesh.nerlige.ramappa, soham.purkait,
anoop.c.vijay
On Fri, Jan 16, 2026 at 01:30:34PM -0800, Matthew Brost wrote:
> On Fri, Jan 16, 2026 at 03:03:31PM +0530, Raag Jadav wrote:
> > Add system controller interrupt handler which is denoted by 11th bit in
> > GFX master interrupt register. While at it, add ordered workqueue for
> > scheduling system controller work.
> >
> > Co-developed-by: Soham Purkait <soham.purkait@intel.com>
> > Signed-off-by: Soham Purkait <soham.purkait@intel.com>
> > Signed-off-by: Raag Jadav <raag.jadav@intel.com>
> > ---
> > drivers/gpu/drm/xe/regs/xe_irq_regs.h | 1 +
> > drivers/gpu/drm/xe/xe_irq.c | 2 ++
> > drivers/gpu/drm/xe/xe_sysctrl.c | 39 +++++++++++++++++++++++++++
> > drivers/gpu/drm/xe/xe_sysctrl.h | 3 +++
> > drivers/gpu/drm/xe/xe_sysctrl_types.h | 7 +++++
> > 5 files changed, 52 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/xe/regs/xe_irq_regs.h b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> > index 9d74f454d3ff..1d6b976c4de0 100644
> > --- a/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> > +++ b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> > @@ -22,6 +22,7 @@
> > #define DISPLAY_IRQ REG_BIT(16)
> > #define SOC_H2DMEMINT_IRQ REG_BIT(13)
> > #define I2C_IRQ REG_BIT(12)
> > +#define SYSCTRL_IRQ REG_BIT(11)
> > #define GT_DW_IRQ(x) REG_BIT(x)
> >
> > /*
> > diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> > index 7560a45f7f64..9e49e2241da4 100644
> > --- a/drivers/gpu/drm/xe/xe_irq.c
> > +++ b/drivers/gpu/drm/xe/xe_irq.c
> > @@ -24,6 +24,7 @@
> > #include "xe_mmio.h"
> > #include "xe_pxp.h"
> > #include "xe_sriov.h"
> > +#include "xe_sysctrl.h"
> > #include "xe_tile.h"
> >
> > /*
> > @@ -525,6 +526,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
> > xe_heci_csc_irq_handler(xe, master_ctl);
> > xe_display_irq_handler(xe, master_ctl);
> > xe_i2c_irq_handler(xe, master_ctl);
> > + xe_sysctrl_irq_handler(xe, master_ctl);
> > xe_mert_irq_handler(xe, master_ctl);
> > gu_misc_iir = gu_misc_irq_ack(xe, master_ctl);
> > }
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl.c b/drivers/gpu/drm/xe/xe_sysctrl.c
> > index 8daab7703247..1d78916dd6ad 100644
> > --- a/drivers/gpu/drm/xe/xe_sysctrl.c
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl.c
> > @@ -7,6 +7,7 @@
> > #include <linux/device.h>
> > #include <linux/mutex.h>
> >
> > +#include "regs/xe_irq_regs.h"
> > #include "regs/xe_sysctrl_regs.h"
> > #include "xe_device.h"
> > #include "xe_printk.h"
> > @@ -27,9 +28,17 @@
> > * with the System Controller through the mailbox.
> > */
> >
> > +static void xe_sysctrl_work(struct work_struct *work)
> > +{
> > +}
> > +
> > static void xe_sysctrl_fini(void *arg)
> > {
> > struct xe_device *xe = arg;
> > + struct xe_sysctrl *sc = &xe->sc;
> > +
> > + cancel_work_sync(&sc->work);
> > + destroy_workqueue(sc->wq);
> >
> > xe->soc_remapper.set_sysctrl_region(xe, 0);
> > }
> > @@ -56,6 +65,14 @@ int xe_sysctrl_init(struct xe_device *xe)
> >
> > xe->soc_remapper.set_sysctrl_region(xe, SYSCTRL_MAILBOX_INDEX);
> >
> > + INIT_WORK(&sc->work, xe_sysctrl_work);
> > +
> > + sc->wq = alloc_ordered_workqueue("sysctrl-ordered-wq", 0);
>
> We do have drmm_alloc_ordered_workqueue, so you don’t need to manually
> clean up the WQ. We don’t use it as widely as we should in Xe, as it was
> added after we merged, but we should use that helper going forward.
Yes, but xe_sysctrl_fini() is setup as devm action and not drmm, so just
trying to keep the unwind consistent. Is it a good practice to mix/match
between managed APIs? My understanding is that it usually leads to resource
races due to inconsistent unwind.
> I do have a question—does this require a dedicated WQ though? i.e.,
> would a system WQ work here? We allocate a lot of WQs in Xe, but
> typically that’s done when we really care about ordering. For example,
> we may have multiple work_items scheduled on a WQ but want only one of
> them executing at any given time, so we schedule them on a single
> dedicated WQ. Here you only have one work_item, so I believe you can
> probably just use one of the system WQs.
For something as critical as error handling, should we rely on system WQ?
Raag
> > + if (!sc->wq) {
> > + ret = -ENOMEM;
> > + goto err_sysctrl_fini;
> > + }
> > +
> > ret = devm_add_action_or_reset(xe->drm.dev, xe_sysctrl_fini, xe);
> > if (ret)
> > return ret;
> > @@ -67,4 +84,26 @@ int xe_sysctrl_init(struct xe_device *xe)
> > xe_sysctrl_mailbox_init(sc);
> >
> > return 0;
> > +
> > +err_sysctrl_fini:
> > + xe_sysctrl_fini(xe);
> > + return ret;
> > +}
> > +
> > +/**
> > + * xe_sysctrl_irq_handler: Handler for System Controller interrupts
> > + * @xe: xe device instance
> > + * @master_ctl: interrupt register
> > + *
> > + * Handle interrupts generated by System Controller.
> > + */
> > +void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl)
> > +{
> > + struct xe_sysctrl *sc = &xe->sc;
> > +
> > + if (!xe->info.has_sysctrl)
> > + return;
> > +
> > + if (master_ctl & SYSCTRL_IRQ)
> > + queue_work(sc->wq, &sc->work);
> > }
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl.h b/drivers/gpu/drm/xe/xe_sysctrl.h
> > index ee7826fe4c98..5919310b9db9 100644
> > --- a/drivers/gpu/drm/xe/xe_sysctrl.h
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl.h
> > @@ -6,8 +6,11 @@
> > #ifndef _XE_SYSCTRL_H_
> > #define _XE_SYSCTRL_H_
> >
> > +#include <linux/types.h>
> > +
> > struct xe_device;
> >
> > int xe_sysctrl_init(struct xe_device *xe);
> > +void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl);
> >
> > #endif /* _XE_SYSCTRL_H_ */
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl_types.h b/drivers/gpu/drm/xe/xe_sysctrl_types.h
> > index 88a34967688b..14fc80dfee6e 100644
> > --- a/drivers/gpu/drm/xe/xe_sysctrl_types.h
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl_types.h
> > @@ -8,6 +8,7 @@
> >
> > #include <linux/mutex.h>
> > #include <linux/types.h>
> > +#include <linux/workqueue_types.h>
> >
> > /**
> > * struct xe_sysctrl - System Controller driver context
> > @@ -18,6 +19,12 @@ struct xe_sysctrl {
> >
> > /** @phase_bit: MKHI message boundary phase toggle bit */
> > u32 phase_bit;
> > +
> > + /** @wq: Queue for sysctrl work */
> > + struct workqueue_struct *wq;
> > +
> > + /** @work: Worker for pending events */
> > + struct work_struct work;
> > };
> >
> > #endif /* _XE_SYSCTRL_TYPES_H_ */
> > --
> > 2.43.0
> >
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [v1,2/4] drm/xe/sysctrl: Add system controller interrupt handler
2026-01-16 9:33 ` [PATCH v1 2/4] drm/xe/sysctrl: Add system controller interrupt handler Raag Jadav
2026-01-16 21:30 ` Matthew Brost
@ 2026-01-20 8:30 ` Mallesh, Koujalagi
2026-01-20 12:05 ` Raag Jadav
1 sibling, 1 reply; 17+ messages in thread
From: Mallesh, Koujalagi @ 2026-01-20 8:30 UTC (permalink / raw)
To: Raag Jadav, intel-xe
Cc: rodrigo.vivi, riana.tauro, michal.wajdeczko, matthew.d.roper,
umesh.nerlige.ramappa, soham.purkait, anoop.c.vijay
Hi Raag,
On 16-01-2026 03:03 pm, Raag Jadav wrote:
> Add system controller interrupt handler which is denoted by 11th bit in
> GFX master interrupt register. While at it, add ordered workqueue for
> scheduling system controller work.
>
> Co-developed-by: Soham Purkait <soham.purkait@intel.com>
> Signed-off-by: Soham Purkait <soham.purkait@intel.com>
> Signed-off-by: Raag Jadav <raag.jadav@intel.com>
> ---
> drivers/gpu/drm/xe/regs/xe_irq_regs.h | 1 +
> drivers/gpu/drm/xe/xe_irq.c | 2 ++
> drivers/gpu/drm/xe/xe_sysctrl.c | 39 +++++++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_sysctrl.h | 3 +++
> drivers/gpu/drm/xe/xe_sysctrl_types.h | 7 +++++
> 5 files changed, 52 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_irq_regs.h b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> index 9d74f454d3ff..1d6b976c4de0 100644
> --- a/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> @@ -22,6 +22,7 @@
> #define DISPLAY_IRQ REG_BIT(16)
> #define SOC_H2DMEMINT_IRQ REG_BIT(13)
> #define I2C_IRQ REG_BIT(12)
> +#define SYSCTRL_IRQ REG_BIT(11)
> #define GT_DW_IRQ(x) REG_BIT(x)
>
> /*
> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> index 7560a45f7f64..9e49e2241da4 100644
> --- a/drivers/gpu/drm/xe/xe_irq.c
> +++ b/drivers/gpu/drm/xe/xe_irq.c
> @@ -24,6 +24,7 @@
> #include "xe_mmio.h"
> #include "xe_pxp.h"
> #include "xe_sriov.h"
> +#include "xe_sysctrl.h"
> #include "xe_tile.h"
>
> /*
> @@ -525,6 +526,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
> xe_heci_csc_irq_handler(xe, master_ctl);
> xe_display_irq_handler(xe, master_ctl);
> xe_i2c_irq_handler(xe, master_ctl);
> + xe_sysctrl_irq_handler(xe, master_ctl);
> xe_mert_irq_handler(xe, master_ctl);
> gu_misc_iir = gu_misc_irq_ack(xe, master_ctl);
> }
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl.c b/drivers/gpu/drm/xe/xe_sysctrl.c
> index 8daab7703247..1d78916dd6ad 100644
> --- a/drivers/gpu/drm/xe/xe_sysctrl.c
> +++ b/drivers/gpu/drm/xe/xe_sysctrl.c
> @@ -7,6 +7,7 @@
> #include <linux/device.h>
> #include <linux/mutex.h>
>
> +#include "regs/xe_irq_regs.h"
> #include "regs/xe_sysctrl_regs.h"
> #include "xe_device.h"
> #include "xe_printk.h"
> @@ -27,9 +28,17 @@
> * with the System Controller through the mailbox.
> */
>
> +static void xe_sysctrl_work(struct work_struct *work)
> +{
> +}
> +
> static void xe_sysctrl_fini(void *arg)
> {
> struct xe_device *xe = arg;
> + struct xe_sysctrl *sc = &xe->sc;
> +
> + cancel_work_sync(&sc->work);
> + destroy_workqueue(sc->wq);
>
> xe->soc_remapper.set_sysctrl_region(xe, 0);
> }
> @@ -56,6 +65,14 @@ int xe_sysctrl_init(struct xe_device *xe)
>
> xe->soc_remapper.set_sysctrl_region(xe, SYSCTRL_MAILBOX_INDEX);
>
> + INIT_WORK(&sc->work, xe_sysctrl_work);
> +
> + sc->wq = alloc_ordered_workqueue("sysctrl-ordered-wq", 0);
> + if (!sc->wq) {
> + ret = -ENOMEM;
> + goto err_sysctrl_fini;
> + }
> +
> ret = devm_add_action_or_reset(xe->drm.dev, xe_sysctrl_fini, xe);
> if (ret)
> return ret;
> @@ -67,4 +84,26 @@ int xe_sysctrl_init(struct xe_device *xe)
> xe_sysctrl_mailbox_init(sc);
>
> return 0;
> +
> +err_sysctrl_fini:
> + xe_sysctrl_fini(xe);
> + return ret;
> +}
> +
> +/**
> + * xe_sysctrl_irq_handler: Handler for System Controller interrupts
> + * @xe: xe device instance
> + * @master_ctl: interrupt register
> + *
> + * Handle interrupts generated by System Controller.
> + */
> +void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl)
> +{
> + struct xe_sysctrl *sc = &xe->sc;
> +
> + if (!xe->info.has_sysctrl)
> + return;
> +
> + if (master_ctl & SYSCTRL_IRQ)
> + queue_work(sc->wq, &sc->work);
> }
The interrupt handler could be called before initialization completes
which cause a null pointer deference when we access sc->wq.
Thanks
-/Mallesh
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl.h b/drivers/gpu/drm/xe/xe_sysctrl.h
> index ee7826fe4c98..5919310b9db9 100644
> --- a/drivers/gpu/drm/xe/xe_sysctrl.h
> +++ b/drivers/gpu/drm/xe/xe_sysctrl.h
> @@ -6,8 +6,11 @@
> #ifndef _XE_SYSCTRL_H_
> #define _XE_SYSCTRL_H_
>
> +#include <linux/types.h>
> +
> struct xe_device;
>
> int xe_sysctrl_init(struct xe_device *xe);
> +void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl);
>
> #endif /* _XE_SYSCTRL_H_ */
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl_types.h b/drivers/gpu/drm/xe/xe_sysctrl_types.h
> index 88a34967688b..14fc80dfee6e 100644
> --- a/drivers/gpu/drm/xe/xe_sysctrl_types.h
> +++ b/drivers/gpu/drm/xe/xe_sysctrl_types.h
> @@ -8,6 +8,7 @@
>
> #include <linux/mutex.h>
> #include <linux/types.h>
> +#include <linux/workqueue_types.h>
>
> /**
> * struct xe_sysctrl - System Controller driver context
> @@ -18,6 +19,12 @@ struct xe_sysctrl {
>
> /** @phase_bit: MKHI message boundary phase toggle bit */
> u32 phase_bit;
> +
> + /** @wq: Queue for sysctrl work */
> + struct workqueue_struct *wq;
> +
> + /** @work: Worker for pending events */
> + struct work_struct work;
> };
>
> #endif /* _XE_SYSCTRL_TYPES_H_ */
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [v1,2/4] drm/xe/sysctrl: Add system controller interrupt handler
2026-01-20 8:30 ` [v1,2/4] " Mallesh, Koujalagi
@ 2026-01-20 12:05 ` Raag Jadav
0 siblings, 0 replies; 17+ messages in thread
From: Raag Jadav @ 2026-01-20 12:05 UTC (permalink / raw)
To: Mallesh, Koujalagi
Cc: intel-xe, rodrigo.vivi, riana.tauro, michal.wajdeczko,
matthew.d.roper, umesh.nerlige.ramappa, soham.purkait,
anoop.c.vijay
On Tue, Jan 20, 2026 at 02:00:17PM +0530, Mallesh, Koujalagi wrote:
> On 16-01-2026 03:03 pm, Raag Jadav wrote:
> > Add system controller interrupt handler which is denoted by 11th bit in
> > GFX master interrupt register. While at it, add ordered workqueue for
> > scheduling system controller work.
> >
> > Co-developed-by: Soham Purkait <soham.purkait@intel.com>
> > Signed-off-by: Soham Purkait <soham.purkait@intel.com>
> > Signed-off-by: Raag Jadav <raag.jadav@intel.com>
> > ---
> > drivers/gpu/drm/xe/regs/xe_irq_regs.h | 1 +
> > drivers/gpu/drm/xe/xe_irq.c | 2 ++
> > drivers/gpu/drm/xe/xe_sysctrl.c | 39 +++++++++++++++++++++++++++
> > drivers/gpu/drm/xe/xe_sysctrl.h | 3 +++
> > drivers/gpu/drm/xe/xe_sysctrl_types.h | 7 +++++
> > 5 files changed, 52 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/xe/regs/xe_irq_regs.h b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> > index 9d74f454d3ff..1d6b976c4de0 100644
> > --- a/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> > +++ b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> > @@ -22,6 +22,7 @@
> > #define DISPLAY_IRQ REG_BIT(16)
> > #define SOC_H2DMEMINT_IRQ REG_BIT(13)
> > #define I2C_IRQ REG_BIT(12)
> > +#define SYSCTRL_IRQ REG_BIT(11)
> > #define GT_DW_IRQ(x) REG_BIT(x)
> > /*
> > diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> > index 7560a45f7f64..9e49e2241da4 100644
> > --- a/drivers/gpu/drm/xe/xe_irq.c
> > +++ b/drivers/gpu/drm/xe/xe_irq.c
> > @@ -24,6 +24,7 @@
> > #include "xe_mmio.h"
> > #include "xe_pxp.h"
> > #include "xe_sriov.h"
> > +#include "xe_sysctrl.h"
> > #include "xe_tile.h"
> > /*
> > @@ -525,6 +526,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
> > xe_heci_csc_irq_handler(xe, master_ctl);
> > xe_display_irq_handler(xe, master_ctl);
> > xe_i2c_irq_handler(xe, master_ctl);
> > + xe_sysctrl_irq_handler(xe, master_ctl);
> > xe_mert_irq_handler(xe, master_ctl);
> > gu_misc_iir = gu_misc_irq_ack(xe, master_ctl);
> > }
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl.c b/drivers/gpu/drm/xe/xe_sysctrl.c
> > index 8daab7703247..1d78916dd6ad 100644
> > --- a/drivers/gpu/drm/xe/xe_sysctrl.c
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl.c
> > @@ -7,6 +7,7 @@
> > #include <linux/device.h>
> > #include <linux/mutex.h>
> > +#include "regs/xe_irq_regs.h"
> > #include "regs/xe_sysctrl_regs.h"
> > #include "xe_device.h"
> > #include "xe_printk.h"
> > @@ -27,9 +28,17 @@
> > * with the System Controller through the mailbox.
> > */
> > +static void xe_sysctrl_work(struct work_struct *work)
> > +{
> > +}
> > +
> > static void xe_sysctrl_fini(void *arg)
> > {
> > struct xe_device *xe = arg;
> > + struct xe_sysctrl *sc = &xe->sc;
> > +
> > + cancel_work_sync(&sc->work);
> > + destroy_workqueue(sc->wq);
> > xe->soc_remapper.set_sysctrl_region(xe, 0);
> > }
> > @@ -56,6 +65,14 @@ int xe_sysctrl_init(struct xe_device *xe)
> > xe->soc_remapper.set_sysctrl_region(xe, SYSCTRL_MAILBOX_INDEX);
> > + INIT_WORK(&sc->work, xe_sysctrl_work);
> > +
> > + sc->wq = alloc_ordered_workqueue("sysctrl-ordered-wq", 0);
> > + if (!sc->wq) {
> > + ret = -ENOMEM;
> > + goto err_sysctrl_fini;
> > + }
> > +
> > ret = devm_add_action_or_reset(xe->drm.dev, xe_sysctrl_fini, xe);
> > if (ret)
> > return ret;
> > @@ -67,4 +84,26 @@ int xe_sysctrl_init(struct xe_device *xe)
> > xe_sysctrl_mailbox_init(sc);
> > return 0;
> > +
> > +err_sysctrl_fini:
> > + xe_sysctrl_fini(xe);
> > + return ret;
> > +}
> > +
> > +/**
> > + * xe_sysctrl_irq_handler: Handler for System Controller interrupts
> > + * @xe: xe device instance
> > + * @master_ctl: interrupt register
> > + *
> > + * Handle interrupts generated by System Controller.
> > + */
> > +void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl)
> > +{
> > + struct xe_sysctrl *sc = &xe->sc;
> > +
> > + if (!xe->info.has_sysctrl)
> > + return;
> > +
> > + if (master_ctl & SYSCTRL_IRQ)
> > + queue_work(sc->wq, &sc->work);
> > }
>
> The interrupt handler could be called before initialization completes which
> cause a null pointer deference when we access sc->wq.
Hm, it could be true for other components as well. Let me dive into irq
code to confirm the sequence.
Raag
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl.h b/drivers/gpu/drm/xe/xe_sysctrl.h
> > index ee7826fe4c98..5919310b9db9 100644
> > --- a/drivers/gpu/drm/xe/xe_sysctrl.h
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl.h
> > @@ -6,8 +6,11 @@
> > #ifndef _XE_SYSCTRL_H_
> > #define _XE_SYSCTRL_H_
> > +#include <linux/types.h>
> > +
> > struct xe_device;
> > int xe_sysctrl_init(struct xe_device *xe);
> > +void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl);
> > #endif /* _XE_SYSCTRL_H_ */
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl_types.h b/drivers/gpu/drm/xe/xe_sysctrl_types.h
> > index 88a34967688b..14fc80dfee6e 100644
> > --- a/drivers/gpu/drm/xe/xe_sysctrl_types.h
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl_types.h
> > @@ -8,6 +8,7 @@
> > #include <linux/mutex.h>
> > #include <linux/types.h>
> > +#include <linux/workqueue_types.h>
> > /**
> > * struct xe_sysctrl - System Controller driver context
> > @@ -18,6 +19,12 @@ struct xe_sysctrl {
> > /** @phase_bit: MKHI message boundary phase toggle bit */
> > u32 phase_bit;
> > +
> > + /** @wq: Queue for sysctrl work */
> > + struct workqueue_struct *wq;
> > +
> > + /** @work: Worker for pending events */
> > + struct work_struct work;
> > };
> > #endif /* _XE_SYSCTRL_TYPES_H_ */
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v1 3/4] drm/xe/sysctrl: Add system controller event support
2026-01-16 9:33 [PATCH v1 0/4] Introduce Xe Correctable Error Handling Raag Jadav
2026-01-16 9:33 ` [PATCH v1 1/4] drm/xe/sysctrl: Add System Controller Raag Jadav
2026-01-16 9:33 ` [PATCH v1 2/4] drm/xe/sysctrl: Add system controller interrupt handler Raag Jadav
@ 2026-01-16 9:33 ` Raag Jadav
2026-01-20 8:46 ` [v1,3/4] " Mallesh, Koujalagi
2026-01-16 9:33 ` [PATCH v1 4/4] drm/xe/ras: Introduce correctable error handling Raag Jadav
` (4 subsequent siblings)
7 siblings, 1 reply; 17+ messages in thread
From: Raag Jadav @ 2026-01-16 9:33 UTC (permalink / raw)
To: intel-xe
Cc: rodrigo.vivi, riana.tauro, michal.wajdeczko, matthew.d.roper,
umesh.nerlige.ramappa, soham.purkait, anoop.c.vijay, Raag Jadav
System controller reports different types of events to GFX endpoint for
different usecases, add initial support for them. This will be further
extended to service those usecases.
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
---
drivers/gpu/drm/xe/Makefile | 1 +
drivers/gpu/drm/xe/xe_sysctrl.c | 7 ++
drivers/gpu/drm/xe/xe_sysctrl.h | 1 +
drivers/gpu/drm/xe/xe_sysctrl_event.c | 77 +++++++++++++++++++++
drivers/gpu/drm/xe/xe_sysctrl_event_types.h | 49 +++++++++++++
drivers/gpu/drm/xe/xe_sysctrl_mailbox.h | 10 +++
6 files changed, 145 insertions(+)
create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_event.c
create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_event_types.h
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index ff567fa58119..16e28cab8464 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -122,6 +122,7 @@ xe-y += xe_bb.o \
xe_survivability_mode.o \
xe_sync.o \
xe_sysctrl.o \
+ xe_sysctrl_event.o \
xe_sysctrl_mailbox.o \
xe_tile.o \
xe_tile_sysfs.o \
diff --git a/drivers/gpu/drm/xe/xe_sysctrl.c b/drivers/gpu/drm/xe/xe_sysctrl.c
index 1d78916dd6ad..b5a57e2dc0d8 100644
--- a/drivers/gpu/drm/xe/xe_sysctrl.c
+++ b/drivers/gpu/drm/xe/xe_sysctrl.c
@@ -10,6 +10,7 @@
#include "regs/xe_irq_regs.h"
#include "regs/xe_sysctrl_regs.h"
#include "xe_device.h"
+#include "xe_pm.h"
#include "xe_printk.h"
#include "xe_soc_remapper.h"
#include "xe_sysctrl.h"
@@ -30,6 +31,12 @@
static void xe_sysctrl_work(struct work_struct *work)
{
+ struct xe_sysctrl *sc = container_of(work, struct xe_sysctrl, work);
+ struct xe_device *xe = container_of(sc, struct xe_device, sc);
+
+ xe_pm_runtime_get(xe);
+ xe_sysctrl_event(xe);
+ xe_pm_runtime_put(xe);
}
static void xe_sysctrl_fini(void *arg)
diff --git a/drivers/gpu/drm/xe/xe_sysctrl.h b/drivers/gpu/drm/xe/xe_sysctrl.h
index 5919310b9db9..bd9acf575d14 100644
--- a/drivers/gpu/drm/xe/xe_sysctrl.h
+++ b/drivers/gpu/drm/xe/xe_sysctrl.h
@@ -12,5 +12,6 @@ struct xe_device;
int xe_sysctrl_init(struct xe_device *xe);
void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl);
+void xe_sysctrl_event(struct xe_device *xe);
#endif /* _XE_SYSCTRL_H_ */
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event.c b/drivers/gpu/drm/xe/xe_sysctrl_event.c
new file mode 100644
index 000000000000..3a860bc34db0
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl_event.c
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#include "xe_assert.h"
+#include "xe_device.h"
+#include "xe_irq.h"
+#include "xe_pm.h"
+#include "xe_printk.h"
+#include "xe_sysctrl.h"
+#include "xe_sysctrl_event_types.h"
+#include "xe_sysctrl_mailbox.h"
+#include "xe_sysctrl_mailbox_types.h"
+
+static void xe_sysctrl_get_pending_event(struct xe_device *xe,
+ struct xe_sysctrl_mailbox_command *command)
+{
+ struct xe_sysctrl_event_response response;
+ size_t len;
+ int ret;
+
+ command->data_out = &response;
+ command->data_out_len = sizeof(response);
+
+ do {
+ memset(&response, 0, sizeof(response));
+
+ ret = xe_sysctrl_send_command(xe, command, &len);
+ if (ret || !len)
+ return;
+
+ if (len != sizeof(response))
+ xe_err(xe, "Unexpected response length %ld\n", len);
+
+ if (response.event == XE_SYSCTRL_EVENT_THRESHOLD_CROSSED)
+ xe_warn(xe, "Counter threshold crossed\n");
+ else
+ xe_err(xe, "Unexpected event %#x\n", response.event);
+
+ } while (response.count);
+}
+
+static void xe_sysctrl_event_request_prep(struct xe_device *xe,
+ struct xe_sysctrl_mailbox_app_msg_hdr *header,
+ struct xe_sysctrl_event_request *request)
+{
+ struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
+ struct xe_sysctrl_event_request req_data;
+ u32 req_hdr;
+
+ req_hdr = REG_FIELD_PREP(APP_HDR_GROUP_ID_MASK, XE_SYSCTRL_GROUP_GFSP) |
+ REG_FIELD_PREP(APP_HDR_GROUP_ID_MASK, XE_SYSCTRL_CMD_GET_PENDING_EVENT);
+
+ req_data.vector = xe_device_has_msix(xe) ? XE_IRQ_DEFAULT_MSIX : 0;
+ req_data.fn = PCI_FUNC(pdev->devfn);
+
+ header->data = req_hdr;
+ *request = req_data;
+}
+
+void xe_sysctrl_event(struct xe_device *xe)
+{
+ struct xe_sysctrl_mailbox_app_msg_hdr header = {};
+ struct xe_sysctrl_mailbox_command command = {};
+ struct xe_sysctrl_event_request request;
+
+ xe_assert(xe, !xe_pm_runtime_suspended(xe));
+
+ xe_sysctrl_event_request_prep(xe, &header, &request);
+
+ command.header = header;
+ command.data_in = &request;
+ command.data_in_len = sizeof(request);
+
+ xe_sysctrl_get_pending_event(xe, &command);
+}
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event_types.h b/drivers/gpu/drm/xe/xe_sysctrl_event_types.h
new file mode 100644
index 000000000000..9c5fb95c58f7
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl_event_types.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_SYSCTRL_EVENT_TYPES_H_
+#define _XE_SYSCTRL_EVENT_TYPES_H_
+
+#include <linux/types.h>
+
+#define XE_SYSCTRL_EVENT_DATA_LEN 68
+
+enum xe_sysctrl_event {
+ XE_SYSCTRL_EVENT_THRESHOLD_CROSSED = 0x01,
+};
+
+/**
+ * struct xe_sysctrl_event_request - Request structure for pending event
+ */
+struct xe_sysctrl_event_request {
+ /** @vector: MSI-X vector that was triggered */
+ u32 vector;
+ /** @fn: Function index (0-7) of PCIe device */
+ u8 fn;
+ /** @reserved: Reserved for future use */
+ u16 reserved;
+ /** @reserved2: Reserved for future use */
+ u32 reserved2[2];
+} __packed;
+
+/**
+ * struct xe_sysctrl_event_response - Response structure for pending event
+ */
+struct xe_sysctrl_event_response {
+ /** @count: Number of pending events */
+ u32 count;
+ /** @event: Pending event */
+ enum xe_sysctrl_event event;
+ /** @timestamp: Timestamp of most recent event */
+ u64 timestamp;
+ /** @extended: Event has extended payload */
+ u8 extended:1;
+ /** @reserved: Reserved for future use */
+ u32 reserved:23;
+ /** @data: Generic event data */
+ u32 data[XE_SYSCTRL_EVENT_DATA_LEN];
+} __packed;
+
+#endif /* _XE_SYSCTRL_EVENT_TYPES_H_ */
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
index 750b7528bab2..c6208a611c9e 100644
--- a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
+++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
@@ -27,6 +27,16 @@ struct xe_sysctrl_mailbox_command;
#define XE_SYSCTRL_APP_HDR_VERSION(hdr) \
FIELD_GET(APP_HDR_VERSION_MASK, le32_to_cpu((hdr)->data))
+/* Command groups */
+enum xe_sysctrl_group {
+ XE_SYSCTRL_GROUP_GFSP = 0x01,
+};
+
+/* Commands supported by GFSP group */
+enum xe_sysctrl_gfsp_cmd {
+ XE_SYSCTRL_CMD_GET_PENDING_EVENT = 0x07,
+};
+
void xe_sysctrl_mailbox_init(struct xe_sysctrl *sc);
int xe_sysctrl_send_command(struct xe_device *xe,
struct xe_sysctrl_mailbox_command *cmd,
--
2.43.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [v1,3/4] drm/xe/sysctrl: Add system controller event support
2026-01-16 9:33 ` [PATCH v1 3/4] drm/xe/sysctrl: Add system controller event support Raag Jadav
@ 2026-01-20 8:46 ` Mallesh, Koujalagi
2026-01-20 12:10 ` Raag Jadav
0 siblings, 1 reply; 17+ messages in thread
From: Mallesh, Koujalagi @ 2026-01-20 8:46 UTC (permalink / raw)
To: Raag Jadav, intel-xe
Cc: rodrigo.vivi, riana.tauro, michal.wajdeczko, matthew.d.roper,
umesh.nerlige.ramappa, soham.purkait, anoop.c.vijay
Hi Raag,
On 16-01-2026 03:03 pm, Raag Jadav wrote:
> System controller reports different types of events to GFX endpoint for
> different usecases, add initial support for them. This will be further
> extended to service those usecases.
>
> Signed-off-by: Raag Jadav <raag.jadav@intel.com>
> ---
> drivers/gpu/drm/xe/Makefile | 1 +
> drivers/gpu/drm/xe/xe_sysctrl.c | 7 ++
> drivers/gpu/drm/xe/xe_sysctrl.h | 1 +
> drivers/gpu/drm/xe/xe_sysctrl_event.c | 77 +++++++++++++++++++++
> drivers/gpu/drm/xe/xe_sysctrl_event_types.h | 49 +++++++++++++
> drivers/gpu/drm/xe/xe_sysctrl_mailbox.h | 10 +++
> 6 files changed, 145 insertions(+)
> create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_event.c
> create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_event_types.h
>
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index ff567fa58119..16e28cab8464 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -122,6 +122,7 @@ xe-y += xe_bb.o \
> xe_survivability_mode.o \
> xe_sync.o \
> xe_sysctrl.o \
> + xe_sysctrl_event.o \
> xe_sysctrl_mailbox.o \
> xe_tile.o \
> xe_tile_sysfs.o \
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl.c b/drivers/gpu/drm/xe/xe_sysctrl.c
> index 1d78916dd6ad..b5a57e2dc0d8 100644
> --- a/drivers/gpu/drm/xe/xe_sysctrl.c
> +++ b/drivers/gpu/drm/xe/xe_sysctrl.c
> @@ -10,6 +10,7 @@
> #include "regs/xe_irq_regs.h"
> #include "regs/xe_sysctrl_regs.h"
> #include "xe_device.h"
> +#include "xe_pm.h"
> #include "xe_printk.h"
> #include "xe_soc_remapper.h"
> #include "xe_sysctrl.h"
> @@ -30,6 +31,12 @@
>
> static void xe_sysctrl_work(struct work_struct *work)
> {
> + struct xe_sysctrl *sc = container_of(work, struct xe_sysctrl, work);
> + struct xe_device *xe = container_of(sc, struct xe_device, sc);
> +
> + xe_pm_runtime_get(xe);
> + xe_sysctrl_event(xe);
> + xe_pm_runtime_put(xe);
> }
>
> static void xe_sysctrl_fini(void *arg)
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl.h b/drivers/gpu/drm/xe/xe_sysctrl.h
> index 5919310b9db9..bd9acf575d14 100644
> --- a/drivers/gpu/drm/xe/xe_sysctrl.h
> +++ b/drivers/gpu/drm/xe/xe_sysctrl.h
> @@ -12,5 +12,6 @@ struct xe_device;
>
> int xe_sysctrl_init(struct xe_device *xe);
> void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl);
> +void xe_sysctrl_event(struct xe_device *xe);
>
> #endif /* _XE_SYSCTRL_H_ */
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event.c b/drivers/gpu/drm/xe/xe_sysctrl_event.c
> new file mode 100644
> index 000000000000..3a860bc34db0
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_sysctrl_event.c
> @@ -0,0 +1,77 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#include "xe_assert.h"
> +#include "xe_device.h"
> +#include "xe_irq.h"
> +#include "xe_pm.h"
> +#include "xe_printk.h"
> +#include "xe_sysctrl.h"
> +#include "xe_sysctrl_event_types.h"
> +#include "xe_sysctrl_mailbox.h"
> +#include "xe_sysctrl_mailbox_types.h"
> +
> +static void xe_sysctrl_get_pending_event(struct xe_device *xe,
> + struct xe_sysctrl_mailbox_command *command)
> +{
> + struct xe_sysctrl_event_response response;
> + size_t len;
> + int ret;
> +
> + command->data_out = &response;
> + command->data_out_len = sizeof(response);
> +
> + do {
> + memset(&response, 0, sizeof(response));
> +
> + ret = xe_sysctrl_send_command(xe, command, &len);
> + if (ret || !len)
> + return;
> +
> + if (len != sizeof(response))
> + xe_err(xe, "Unexpected response length %ld\n", len);
If we see response structure is mismatched, should either return or
handle gracefully.
> +
> + if (response.event == XE_SYSCTRL_EVENT_THRESHOLD_CROSSED)
> + xe_warn(xe, "Counter threshold crossed\n");
> + else
> + xe_err(xe, "Unexpected event %#x\n", response.event);
> +
> + } while (response.count);
> +}
> +
> +static void xe_sysctrl_event_request_prep(struct xe_device *xe,
> + struct xe_sysctrl_mailbox_app_msg_hdr *header,
> + struct xe_sysctrl_event_request *request)
> +{
> + struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
> + struct xe_sysctrl_event_request req_data;
> + u32 req_hdr;
> +
> + req_hdr = REG_FIELD_PREP(APP_HDR_GROUP_ID_MASK, XE_SYSCTRL_GROUP_GFSP) |
> + REG_FIELD_PREP(APP_HDR_GROUP_ID_MASK, XE_SYSCTRL_CMD_GET_PENDING_EVENT);
We need use APP_HDR_COMMAND_MASK right?
Thanks
-/Mallesh
> +
> + req_data.vector = xe_device_has_msix(xe) ? XE_IRQ_DEFAULT_MSIX : 0;
> + req_data.fn = PCI_FUNC(pdev->devfn);
> +
> + header->data = req_hdr;
> + *request = req_data;
> +}
> +
> +void xe_sysctrl_event(struct xe_device *xe)
> +{
> + struct xe_sysctrl_mailbox_app_msg_hdr header = {};
> + struct xe_sysctrl_mailbox_command command = {};
> + struct xe_sysctrl_event_request request;
> +
> + xe_assert(xe, !xe_pm_runtime_suspended(xe));
> +
> + xe_sysctrl_event_request_prep(xe, &header, &request);
> +
> + command.header = header;
> + command.data_in = &request;
> + command.data_in_len = sizeof(request);
> +
> + xe_sysctrl_get_pending_event(xe, &command);
> +}
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event_types.h b/drivers/gpu/drm/xe/xe_sysctrl_event_types.h
> new file mode 100644
> index 000000000000..9c5fb95c58f7
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_sysctrl_event_types.h
> @@ -0,0 +1,49 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#ifndef _XE_SYSCTRL_EVENT_TYPES_H_
> +#define _XE_SYSCTRL_EVENT_TYPES_H_
> +
> +#include <linux/types.h>
> +
> +#define XE_SYSCTRL_EVENT_DATA_LEN 68
> +
> +enum xe_sysctrl_event {
> + XE_SYSCTRL_EVENT_THRESHOLD_CROSSED = 0x01,
> +};
> +
> +/**
> + * struct xe_sysctrl_event_request - Request structure for pending event
> + */
> +struct xe_sysctrl_event_request {
> + /** @vector: MSI-X vector that was triggered */
> + u32 vector;
> + /** @fn: Function index (0-7) of PCIe device */
> + u8 fn;
> + /** @reserved: Reserved for future use */
> + u16 reserved;
> + /** @reserved2: Reserved for future use */
> + u32 reserved2[2];
> +} __packed;
> +
> +/**
> + * struct xe_sysctrl_event_response - Response structure for pending event
> + */
> +struct xe_sysctrl_event_response {
> + /** @count: Number of pending events */
> + u32 count;
> + /** @event: Pending event */
> + enum xe_sysctrl_event event;
> + /** @timestamp: Timestamp of most recent event */
> + u64 timestamp;
> + /** @extended: Event has extended payload */
> + u8 extended:1;
> + /** @reserved: Reserved for future use */
> + u32 reserved:23;
> + /** @data: Generic event data */
> + u32 data[XE_SYSCTRL_EVENT_DATA_LEN];
> +} __packed;
> +
> +#endif /* _XE_SYSCTRL_EVENT_TYPES_H_ */
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
> index 750b7528bab2..c6208a611c9e 100644
> --- a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
> +++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
> @@ -27,6 +27,16 @@ struct xe_sysctrl_mailbox_command;
> #define XE_SYSCTRL_APP_HDR_VERSION(hdr) \
> FIELD_GET(APP_HDR_VERSION_MASK, le32_to_cpu((hdr)->data))
>
> +/* Command groups */
> +enum xe_sysctrl_group {
> + XE_SYSCTRL_GROUP_GFSP = 0x01,
> +};
> +
> +/* Commands supported by GFSP group */
> +enum xe_sysctrl_gfsp_cmd {
> + XE_SYSCTRL_CMD_GET_PENDING_EVENT = 0x07,
> +};
> +
> void xe_sysctrl_mailbox_init(struct xe_sysctrl *sc);
> int xe_sysctrl_send_command(struct xe_device *xe,
> struct xe_sysctrl_mailbox_command *cmd,
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [v1,3/4] drm/xe/sysctrl: Add system controller event support
2026-01-20 8:46 ` [v1,3/4] " Mallesh, Koujalagi
@ 2026-01-20 12:10 ` Raag Jadav
0 siblings, 0 replies; 17+ messages in thread
From: Raag Jadav @ 2026-01-20 12:10 UTC (permalink / raw)
To: Mallesh, Koujalagi
Cc: intel-xe, rodrigo.vivi, riana.tauro, michal.wajdeczko,
matthew.d.roper, umesh.nerlige.ramappa, soham.purkait,
anoop.c.vijay
On Tue, Jan 20, 2026 at 02:16:23PM +0530, Mallesh, Koujalagi wrote:
> Hi Raag,
>
> On 16-01-2026 03:03 pm, Raag Jadav wrote:
> > System controller reports different types of events to GFX endpoint for
> > different usecases, add initial support for them. This will be further
> > extended to service those usecases.
> >
> > Signed-off-by: Raag Jadav <raag.jadav@intel.com>
> > ---
> > drivers/gpu/drm/xe/Makefile | 1 +
> > drivers/gpu/drm/xe/xe_sysctrl.c | 7 ++
> > drivers/gpu/drm/xe/xe_sysctrl.h | 1 +
> > drivers/gpu/drm/xe/xe_sysctrl_event.c | 77 +++++++++++++++++++++
> > drivers/gpu/drm/xe/xe_sysctrl_event_types.h | 49 +++++++++++++
> > drivers/gpu/drm/xe/xe_sysctrl_mailbox.h | 10 +++
> > 6 files changed, 145 insertions(+)
> > create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_event.c
> > create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_event_types.h
> >
> > diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> > index ff567fa58119..16e28cab8464 100644
> > --- a/drivers/gpu/drm/xe/Makefile
> > +++ b/drivers/gpu/drm/xe/Makefile
> > @@ -122,6 +122,7 @@ xe-y += xe_bb.o \
> > xe_survivability_mode.o \
> > xe_sync.o \
> > xe_sysctrl.o \
> > + xe_sysctrl_event.o \
> > xe_sysctrl_mailbox.o \
> > xe_tile.o \
> > xe_tile_sysfs.o \
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl.c b/drivers/gpu/drm/xe/xe_sysctrl.c
> > index 1d78916dd6ad..b5a57e2dc0d8 100644
> > --- a/drivers/gpu/drm/xe/xe_sysctrl.c
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl.c
> > @@ -10,6 +10,7 @@
> > #include "regs/xe_irq_regs.h"
> > #include "regs/xe_sysctrl_regs.h"
> > #include "xe_device.h"
> > +#include "xe_pm.h"
> > #include "xe_printk.h"
> > #include "xe_soc_remapper.h"
> > #include "xe_sysctrl.h"
> > @@ -30,6 +31,12 @@
> > static void xe_sysctrl_work(struct work_struct *work)
> > {
> > + struct xe_sysctrl *sc = container_of(work, struct xe_sysctrl, work);
> > + struct xe_device *xe = container_of(sc, struct xe_device, sc);
> > +
> > + xe_pm_runtime_get(xe);
> > + xe_sysctrl_event(xe);
> > + xe_pm_runtime_put(xe);
> > }
> > static void xe_sysctrl_fini(void *arg)
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl.h b/drivers/gpu/drm/xe/xe_sysctrl.h
> > index 5919310b9db9..bd9acf575d14 100644
> > --- a/drivers/gpu/drm/xe/xe_sysctrl.h
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl.h
> > @@ -12,5 +12,6 @@ struct xe_device;
> > int xe_sysctrl_init(struct xe_device *xe);
> > void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl);
> > +void xe_sysctrl_event(struct xe_device *xe);
> > #endif /* _XE_SYSCTRL_H_ */
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event.c b/drivers/gpu/drm/xe/xe_sysctrl_event.c
> > new file mode 100644
> > index 000000000000..3a860bc34db0
> > --- /dev/null
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl_event.c
> > @@ -0,0 +1,77 @@
> > +// SPDX-License-Identifier: MIT
> > +/*
> > + * Copyright © 2026 Intel Corporation
> > + */
> > +
> > +#include "xe_assert.h"
> > +#include "xe_device.h"
> > +#include "xe_irq.h"
> > +#include "xe_pm.h"
> > +#include "xe_printk.h"
> > +#include "xe_sysctrl.h"
> > +#include "xe_sysctrl_event_types.h"
> > +#include "xe_sysctrl_mailbox.h"
> > +#include "xe_sysctrl_mailbox_types.h"
> > +
> > +static void xe_sysctrl_get_pending_event(struct xe_device *xe,
> > + struct xe_sysctrl_mailbox_command *command)
> > +{
> > + struct xe_sysctrl_event_response response;
> > + size_t len;
> > + int ret;
> > +
> > + command->data_out = &response;
> > + command->data_out_len = sizeof(response);
> > +
> > + do {
> > + memset(&response, 0, sizeof(response));
> > +
> > + ret = xe_sysctrl_send_command(xe, command, &len);
> > + if (ret || !len)
> > + return;
> > +
> > + if (len != sizeof(response))
> > + xe_err(xe, "Unexpected response length %ld\n", len);
> If we see response structure is mismatched, should either return or handle
> gracefully.
Good point. My understanding was to move forward anyway in case the error
is so critical that not handling it results in graver consequences. Let's
confirm this with arch.
Raag
> > + if (response.event == XE_SYSCTRL_EVENT_THRESHOLD_CROSSED)
> > + xe_warn(xe, "Counter threshold crossed\n");
> > + else
> > + xe_err(xe, "Unexpected event %#x\n", response.event);
> > +
> > + } while (response.count);
> > +}
> > +
> > +static void xe_sysctrl_event_request_prep(struct xe_device *xe,
> > + struct xe_sysctrl_mailbox_app_msg_hdr *header,
> > + struct xe_sysctrl_event_request *request)
> > +{
> > + struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
> > + struct xe_sysctrl_event_request req_data;
> > + u32 req_hdr;
> > +
> > + req_hdr = REG_FIELD_PREP(APP_HDR_GROUP_ID_MASK, XE_SYSCTRL_GROUP_GFSP) |
> > + REG_FIELD_PREP(APP_HDR_GROUP_ID_MASK, XE_SYSCTRL_CMD_GET_PENDING_EVENT);
>
> We need use APP_HDR_COMMAND_MASK right?
Yep, missed it. Thanks.
Raag
> > +
> > + req_data.vector = xe_device_has_msix(xe) ? XE_IRQ_DEFAULT_MSIX : 0;
> > + req_data.fn = PCI_FUNC(pdev->devfn);
> > +
> > + header->data = req_hdr;
> > + *request = req_data;
> > +}
> > +
> > +void xe_sysctrl_event(struct xe_device *xe)
> > +{
> > + struct xe_sysctrl_mailbox_app_msg_hdr header = {};
> > + struct xe_sysctrl_mailbox_command command = {};
> > + struct xe_sysctrl_event_request request;
> > +
> > + xe_assert(xe, !xe_pm_runtime_suspended(xe));
> > +
> > + xe_sysctrl_event_request_prep(xe, &header, &request);
> > +
> > + command.header = header;
> > + command.data_in = &request;
> > + command.data_in_len = sizeof(request);
> > +
> > + xe_sysctrl_get_pending_event(xe, &command);
> > +}
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event_types.h b/drivers/gpu/drm/xe/xe_sysctrl_event_types.h
> > new file mode 100644
> > index 000000000000..9c5fb95c58f7
> > --- /dev/null
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl_event_types.h
> > @@ -0,0 +1,49 @@
> > +/* SPDX-License-Identifier: MIT */
> > +/*
> > + * Copyright © 2026 Intel Corporation
> > + */
> > +
> > +#ifndef _XE_SYSCTRL_EVENT_TYPES_H_
> > +#define _XE_SYSCTRL_EVENT_TYPES_H_
> > +
> > +#include <linux/types.h>
> > +
> > +#define XE_SYSCTRL_EVENT_DATA_LEN 68
> > +
> > +enum xe_sysctrl_event {
> > + XE_SYSCTRL_EVENT_THRESHOLD_CROSSED = 0x01,
> > +};
> > +
> > +/**
> > + * struct xe_sysctrl_event_request - Request structure for pending event
> > + */
> > +struct xe_sysctrl_event_request {
> > + /** @vector: MSI-X vector that was triggered */
> > + u32 vector;
> > + /** @fn: Function index (0-7) of PCIe device */
> > + u8 fn;
> > + /** @reserved: Reserved for future use */
> > + u16 reserved;
> > + /** @reserved2: Reserved for future use */
> > + u32 reserved2[2];
> > +} __packed;
> > +
> > +/**
> > + * struct xe_sysctrl_event_response - Response structure for pending event
> > + */
> > +struct xe_sysctrl_event_response {
> > + /** @count: Number of pending events */
> > + u32 count;
> > + /** @event: Pending event */
> > + enum xe_sysctrl_event event;
> > + /** @timestamp: Timestamp of most recent event */
> > + u64 timestamp;
> > + /** @extended: Event has extended payload */
> > + u8 extended:1;
> > + /** @reserved: Reserved for future use */
> > + u32 reserved:23;
> > + /** @data: Generic event data */
> > + u32 data[XE_SYSCTRL_EVENT_DATA_LEN];
> > +} __packed;
> > +
> > +#endif /* _XE_SYSCTRL_EVENT_TYPES_H_ */
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
> > index 750b7528bab2..c6208a611c9e 100644
> > --- a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
> > @@ -27,6 +27,16 @@ struct xe_sysctrl_mailbox_command;
> > #define XE_SYSCTRL_APP_HDR_VERSION(hdr) \
> > FIELD_GET(APP_HDR_VERSION_MASK, le32_to_cpu((hdr)->data))
> > +/* Command groups */
> > +enum xe_sysctrl_group {
> > + XE_SYSCTRL_GROUP_GFSP = 0x01,
> > +};
> > +
> > +/* Commands supported by GFSP group */
> > +enum xe_sysctrl_gfsp_cmd {
> > + XE_SYSCTRL_CMD_GET_PENDING_EVENT = 0x07,
> > +};
> > +
> > void xe_sysctrl_mailbox_init(struct xe_sysctrl *sc);
> > int xe_sysctrl_send_command(struct xe_device *xe,
> > struct xe_sysctrl_mailbox_command *cmd,
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v1 4/4] drm/xe/ras: Introduce correctable error handling
2026-01-16 9:33 [PATCH v1 0/4] Introduce Xe Correctable Error Handling Raag Jadav
` (2 preceding siblings ...)
2026-01-16 9:33 ` [PATCH v1 3/4] drm/xe/sysctrl: Add system controller event support Raag Jadav
@ 2026-01-16 9:33 ` Raag Jadav
2026-01-20 8:51 ` [v1,4/4] " Mallesh, Koujalagi
2026-01-16 10:08 ` ✗ CI.checkpatch: warning for Introduce Xe Correctable Error Handling Patchwork
` (3 subsequent siblings)
7 siblings, 1 reply; 17+ messages in thread
From: Raag Jadav @ 2026-01-16 9:33 UTC (permalink / raw)
To: intel-xe
Cc: rodrigo.vivi, riana.tauro, michal.wajdeczko, matthew.d.roper,
umesh.nerlige.ramappa, soham.purkait, anoop.c.vijay, Raag Jadav
Add initial support for correctable error handling which is serviced
using system controller event. Currently we only log the errors in
dmesg but this serves as a foundation for RAS infrastructure and will
be further extended to facilitate other RAS features.
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
---
drivers/gpu/drm/xe/Makefile | 1 +
drivers/gpu/drm/xe/xe_ras.c | 86 +++++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_ras.h | 14 +++++
drivers/gpu/drm/xe/xe_ras_types.h | 79 ++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_sysctrl_event.c | 3 +-
5 files changed, 182 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/xe/xe_ras.c
create mode 100644 drivers/gpu/drm/xe/xe_ras.h
create mode 100644 drivers/gpu/drm/xe/xe_ras_types.h
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 16e28cab8464..8cc060a64c90 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -110,6 +110,7 @@ xe-y += xe_bb.o \
xe_pxp_submit.o \
xe_query.o \
xe_range_fence.o \
+ xe_ras.o \
xe_reg_sr.o \
xe_reg_whitelist.o \
xe_ring_ops.o \
diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
new file mode 100644
index 000000000000..6fea009c991a
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_ras.c
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#include "xe_assert.h"
+#include "xe_printk.h"
+#include "xe_ras.h"
+#include "xe_ras_types.h"
+#include "xe_sysctrl_event_types.h"
+
+/* Severity of detected errors */
+enum xe_ras_severity {
+ XE_RAS_SEV_NOT_SUPPORTED = 0x00,
+ XE_RAS_SEV_CORRECTABLE = 0x01,
+ XE_RAS_SEV_UNCORRECTABLE = 0x02,
+ XE_RAS_SEV_INFORMATIONAL = 0x03,
+ XE_RAS_SEV_MAX
+};
+
+/* Major IP blocks/components where errors can originate */
+enum xe_ras_component {
+ XE_RAS_COMP_NOT_SUPPORTED = 0x00,
+ XE_RAS_COMP_MEMORY = 0x01,
+ XE_RAS_COMP_GT = 0x02,
+ XE_RAS_COMP_RESERVED = 0x03,
+ XE_RAS_COMP_PCIE = 0x04,
+ XE_RAS_COMP_FABRIC = 0x05,
+ XE_RAS_COMP_SOC = 0x06,
+ XE_RAS_COMP_MAX
+};
+
+static const char *xe_ras_severities[] = {
+ [XE_RAS_SEV_NOT_SUPPORTED] = "Not Supported",
+ [XE_RAS_SEV_CORRECTABLE] = "Correctable",
+ [XE_RAS_SEV_UNCORRECTABLE] = "Uncorrectable",
+ [XE_RAS_SEV_INFORMATIONAL] = "Informational",
+};
+static_assert(ARRAY_SIZE(xe_ras_severities) == XE_RAS_SEV_MAX);
+
+static const char *xe_ras_components[] = {
+ [XE_RAS_COMP_NOT_SUPPORTED] = "Not Supported",
+ [XE_RAS_COMP_MEMORY] = "Memory",
+ [XE_RAS_COMP_GT] = "GT",
+ [XE_RAS_COMP_RESERVED] = "Reserved",
+ [XE_RAS_COMP_PCIE] = "PCIe",
+ [XE_RAS_COMP_FABRIC] = "Fabric",
+ [XE_RAS_COMP_SOC] = "SoC",
+};
+static_assert(ARRAY_SIZE(xe_ras_components) == XE_RAS_COMP_MAX);
+
+static inline const char *sev_to_str(struct xe_device *xe, u32 sev)
+{
+ xe_assert(xe, sev < XE_RAS_SEV_MAX);
+
+ return xe_ras_severities[sev];
+}
+
+static inline const char *comp_to_str(struct xe_device *xe, u32 comp)
+{
+ xe_assert(xe, comp < XE_RAS_COMP_MAX);
+
+ return xe_ras_components[comp];
+}
+
+void xe_ras_event_log(struct xe_device *xe, struct xe_sysctrl_event_response *response)
+{
+ struct xe_ras_event_threshold_crossed *pending = (void *)&response->data;
+ struct xe_ras_error *errors = pending->counters;
+ u32 cid, sev, comp, inst, cause;
+ u8 tile;
+
+ xe_assert(xe, pending->ncounters < XE_RAS_NUM_COUNTERS);
+
+ for (cid = 0; cid < pending->ncounters; cid++) {
+ sev = errors[cid].common.severity;
+ comp = errors[cid].common.component;
+
+ tile = errors[cid].product.unit.tile;
+ inst = errors[cid].product.unit.instance;
+ cause = errors[cid].product.cause.cause;
+
+ xe_warn(xe, "[RAS]: Error:%s Tile:%u Component:%s Instance:%u Cause:%#x\n",
+ sev_to_str(xe, sev), tile, comp_to_str(xe, comp), inst, cause);
+ }
+}
diff --git a/drivers/gpu/drm/xe/xe_ras.h b/drivers/gpu/drm/xe/xe_ras.h
new file mode 100644
index 000000000000..fdefe0e2fe98
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_ras.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_RAS_H_
+#define _XE_RAS_H_
+
+struct xe_device;
+struct xe_sysctrl_event_response;
+
+void xe_ras_event_log(struct xe_device *xe, struct xe_sysctrl_event_response *response);
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_ras_types.h b/drivers/gpu/drm/xe/xe_ras_types.h
new file mode 100644
index 000000000000..348ba520d676
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_ras_types.h
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_RAS_TYPES_H_
+#define _XE_RAS_TYPES_H_
+
+#include <linux/types.h>
+
+#define XE_RAS_NUM_COUNTERS 21
+
+/**
+ * struct xe_ras_error_common - Error fields that are common across all products
+ */
+struct xe_ras_error_common {
+ /** @severity: Error severity */
+ u8 severity;
+ /** @component: IP block where error originated */
+ u8 component;
+} __packed;
+
+/**
+ * struct xe_ras_error_unit - Error unit information
+ */
+struct xe_ras_error_unit {
+ /** @tile: Tile identifier */
+ u8 tile;
+ /** @instance: Instance identifier specific to IP */
+ u32 instance;
+} __packed;
+
+/**
+ * struct xe_ras_error_cause - Error cause information
+ */
+struct xe_ras_error_cause {
+ /** @cause: Cause/checker */
+ u32 cause;
+ /** @reserved: For future use */
+ u8 reserved;
+} __packed;
+
+/**
+ * struct xe_ras_error_product - Error fields that are specific to the product
+ */
+struct xe_ras_error_product {
+ /** @unit: Unit within IP block */
+ struct xe_ras_error_unit unit;
+ /** @cause: Cause/checker */
+ struct xe_ras_error_cause cause;
+} __packed;
+
+/**
+ * struct xe_ras_error - Combines common and product-specific parts
+ */
+struct xe_ras_error {
+ /** @common: Common error type and component */
+ struct xe_ras_error_common common;
+ /** @product: Product-specific unit and cause */
+ struct xe_ras_error_product product;
+} __packed;
+
+/**
+ * struct xe_ras_event_threshold_crossed - Event data for counter threshold crossed event
+ */
+struct xe_ras_event_threshold_crossed {
+ /** @ncounters: Number of counters that crossed thresholds */
+ u32 ncounters;
+ /** @ts_high: Upper 32 bits of event timestamp */
+ u32 ts_high;
+ /** @ts_low: Lower 32 bits of event timestamp */
+ u32 ts_low;
+ /** @reason: Threshold cross reason */
+ u32 reason;
+ /** @counters: Array of error counters that crossed threshold */
+ struct xe_ras_error counters[XE_RAS_NUM_COUNTERS];
+} __packed;
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event.c b/drivers/gpu/drm/xe/xe_sysctrl_event.c
index 3a860bc34db0..d70bef72764f 100644
--- a/drivers/gpu/drm/xe/xe_sysctrl_event.c
+++ b/drivers/gpu/drm/xe/xe_sysctrl_event.c
@@ -8,6 +8,7 @@
#include "xe_irq.h"
#include "xe_pm.h"
#include "xe_printk.h"
+#include "xe_ras.h"
#include "xe_sysctrl.h"
#include "xe_sysctrl_event_types.h"
#include "xe_sysctrl_mailbox.h"
@@ -34,7 +35,7 @@ static void xe_sysctrl_get_pending_event(struct xe_device *xe,
xe_err(xe, "Unexpected response length %ld\n", len);
if (response.event == XE_SYSCTRL_EVENT_THRESHOLD_CROSSED)
- xe_warn(xe, "Counter threshold crossed\n");
+ xe_ras_event_log(xe, &response);
else
xe_err(xe, "Unexpected event %#x\n", response.event);
--
2.43.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [v1,4/4] drm/xe/ras: Introduce correctable error handling
2026-01-16 9:33 ` [PATCH v1 4/4] drm/xe/ras: Introduce correctable error handling Raag Jadav
@ 2026-01-20 8:51 ` Mallesh, Koujalagi
2026-01-20 12:17 ` Raag Jadav
0 siblings, 1 reply; 17+ messages in thread
From: Mallesh, Koujalagi @ 2026-01-20 8:51 UTC (permalink / raw)
To: Raag Jadav, intel-xe
Cc: rodrigo.vivi, riana.tauro, michal.wajdeczko, matthew.d.roper,
umesh.nerlige.ramappa, soham.purkait, anoop.c.vijay
Hi Raag,
On 16-01-2026 03:03 pm, Raag Jadav wrote:
> Add initial support for correctable error handling which is serviced
> using system controller event. Currently we only log the errors in
> dmesg but this serves as a foundation for RAS infrastructure and will
> be further extended to facilitate other RAS features.
>
> Signed-off-by: Raag Jadav <raag.jadav@intel.com>
> ---
> drivers/gpu/drm/xe/Makefile | 1 +
> drivers/gpu/drm/xe/xe_ras.c | 86 +++++++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_ras.h | 14 +++++
> drivers/gpu/drm/xe/xe_ras_types.h | 79 ++++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_sysctrl_event.c | 3 +-
> 5 files changed, 182 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/xe/xe_ras.c
> create mode 100644 drivers/gpu/drm/xe/xe_ras.h
> create mode 100644 drivers/gpu/drm/xe/xe_ras_types.h
>
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index 16e28cab8464..8cc060a64c90 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -110,6 +110,7 @@ xe-y += xe_bb.o \
> xe_pxp_submit.o \
> xe_query.o \
> xe_range_fence.o \
> + xe_ras.o \
> xe_reg_sr.o \
> xe_reg_whitelist.o \
> xe_ring_ops.o \
> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> new file mode 100644
> index 000000000000..6fea009c991a
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_ras.c
> @@ -0,0 +1,86 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#include "xe_assert.h"
> +#include "xe_printk.h"
> +#include "xe_ras.h"
> +#include "xe_ras_types.h"
> +#include "xe_sysctrl_event_types.h"
> +
> +/* Severity of detected errors */
> +enum xe_ras_severity {
> + XE_RAS_SEV_NOT_SUPPORTED = 0x00,
> + XE_RAS_SEV_CORRECTABLE = 0x01,
> + XE_RAS_SEV_UNCORRECTABLE = 0x02,
> + XE_RAS_SEV_INFORMATIONAL = 0x03,
> + XE_RAS_SEV_MAX
> +};
> +
> +/* Major IP blocks/components where errors can originate */
> +enum xe_ras_component {
> + XE_RAS_COMP_NOT_SUPPORTED = 0x00,
> + XE_RAS_COMP_MEMORY = 0x01,
> + XE_RAS_COMP_GT = 0x02,
> + XE_RAS_COMP_RESERVED = 0x03,
> + XE_RAS_COMP_PCIE = 0x04,
> + XE_RAS_COMP_FABRIC = 0x05,
> + XE_RAS_COMP_SOC = 0x06,
> + XE_RAS_COMP_MAX
> +};
> +
> +static const char *xe_ras_severities[] = {
> + [XE_RAS_SEV_NOT_SUPPORTED] = "Not Supported",
> + [XE_RAS_SEV_CORRECTABLE] = "Correctable",
> + [XE_RAS_SEV_UNCORRECTABLE] = "Uncorrectable",
> + [XE_RAS_SEV_INFORMATIONAL] = "Informational",
> +};
> +static_assert(ARRAY_SIZE(xe_ras_severities) == XE_RAS_SEV_MAX);
> +
> +static const char *xe_ras_components[] = {
> + [XE_RAS_COMP_NOT_SUPPORTED] = "Not Supported",
> + [XE_RAS_COMP_MEMORY] = "Memory",
> + [XE_RAS_COMP_GT] = "GT",
> + [XE_RAS_COMP_RESERVED] = "Reserved",
> + [XE_RAS_COMP_PCIE] = "PCIe",
> + [XE_RAS_COMP_FABRIC] = "Fabric",
> + [XE_RAS_COMP_SOC] = "SoC",
> +};
> +static_assert(ARRAY_SIZE(xe_ras_components) == XE_RAS_COMP_MAX);
> +
> +static inline const char *sev_to_str(struct xe_device *xe, u32 sev)
> +{
> + xe_assert(xe, sev < XE_RAS_SEV_MAX);
> +
> + return xe_ras_severities[sev];
> +}
> +
> +static inline const char *comp_to_str(struct xe_device *xe, u32 comp)
> +{
> + xe_assert(xe, comp < XE_RAS_COMP_MAX);
> +
> + return xe_ras_components[comp];
> +}
> +
> +void xe_ras_event_log(struct xe_device *xe, struct xe_sysctrl_event_response *response)
> +{
> + struct xe_ras_event_threshold_crossed *pending = (void *)&response->data;
> + struct xe_ras_error *errors = pending->counters;
> + u32 cid, sev, comp, inst, cause;
> + u8 tile;
> +
> + xe_assert(xe, pending->ncounters < XE_RAS_NUM_COUNTERS);
> +
> + for (cid = 0; cid < pending->ncounters; cid++) {
> + sev = errors[cid].common.severity;
> + comp = errors[cid].common.component;
> +
> + tile = errors[cid].product.unit.tile;
> + inst = errors[cid].product.unit.instance;
> + cause = errors[cid].product.cause.cause;
> +
> + xe_warn(xe, "[RAS]: Error:%s Tile:%u Component:%s Instance:%u Cause:%#x\n",
> + sev_to_str(xe, sev), tile, comp_to_str(xe, comp), inst, cause);
Please add Error timestamp and Threshold reason.
Thanks
-/Mallesh
> + }
> +}
> diff --git a/drivers/gpu/drm/xe/xe_ras.h b/drivers/gpu/drm/xe/xe_ras.h
> new file mode 100644
> index 000000000000..fdefe0e2fe98
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_ras.h
> @@ -0,0 +1,14 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#ifndef _XE_RAS_H_
> +#define _XE_RAS_H_
> +
> +struct xe_device;
> +struct xe_sysctrl_event_response;
> +
> +void xe_ras_event_log(struct xe_device *xe, struct xe_sysctrl_event_response *response);
> +
> +#endif
> diff --git a/drivers/gpu/drm/xe/xe_ras_types.h b/drivers/gpu/drm/xe/xe_ras_types.h
> new file mode 100644
> index 000000000000..348ba520d676
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_ras_types.h
> @@ -0,0 +1,79 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#ifndef _XE_RAS_TYPES_H_
> +#define _XE_RAS_TYPES_H_
> +
> +#include <linux/types.h>
> +
> +#define XE_RAS_NUM_COUNTERS 21
> +
> +/**
> + * struct xe_ras_error_common - Error fields that are common across all products
> + */
> +struct xe_ras_error_common {
> + /** @severity: Error severity */
> + u8 severity;
> + /** @component: IP block where error originated */
> + u8 component;
> +} __packed;
> +
> +/**
> + * struct xe_ras_error_unit - Error unit information
> + */
> +struct xe_ras_error_unit {
> + /** @tile: Tile identifier */
> + u8 tile;
> + /** @instance: Instance identifier specific to IP */
> + u32 instance;
> +} __packed;
> +
> +/**
> + * struct xe_ras_error_cause - Error cause information
> + */
> +struct xe_ras_error_cause {
> + /** @cause: Cause/checker */
> + u32 cause;
> + /** @reserved: For future use */
> + u8 reserved;
> +} __packed;
> +
> +/**
> + * struct xe_ras_error_product - Error fields that are specific to the product
> + */
> +struct xe_ras_error_product {
> + /** @unit: Unit within IP block */
> + struct xe_ras_error_unit unit;
> + /** @cause: Cause/checker */
> + struct xe_ras_error_cause cause;
> +} __packed;
> +
> +/**
> + * struct xe_ras_error - Combines common and product-specific parts
> + */
> +struct xe_ras_error {
> + /** @common: Common error type and component */
> + struct xe_ras_error_common common;
> + /** @product: Product-specific unit and cause */
> + struct xe_ras_error_product product;
> +} __packed;
> +
> +/**
> + * struct xe_ras_event_threshold_crossed - Event data for counter threshold crossed event
> + */
> +struct xe_ras_event_threshold_crossed {
> + /** @ncounters: Number of counters that crossed thresholds */
> + u32 ncounters;
> + /** @ts_high: Upper 32 bits of event timestamp */
> + u32 ts_high;
> + /** @ts_low: Lower 32 bits of event timestamp */
> + u32 ts_low;
> + /** @reason: Threshold cross reason */
> + u32 reason;
> + /** @counters: Array of error counters that crossed threshold */
> + struct xe_ras_error counters[XE_RAS_NUM_COUNTERS];
> +} __packed;
> +
> +#endif
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event.c b/drivers/gpu/drm/xe/xe_sysctrl_event.c
> index 3a860bc34db0..d70bef72764f 100644
> --- a/drivers/gpu/drm/xe/xe_sysctrl_event.c
> +++ b/drivers/gpu/drm/xe/xe_sysctrl_event.c
> @@ -8,6 +8,7 @@
> #include "xe_irq.h"
> #include "xe_pm.h"
> #include "xe_printk.h"
> +#include "xe_ras.h"
> #include "xe_sysctrl.h"
> #include "xe_sysctrl_event_types.h"
> #include "xe_sysctrl_mailbox.h"
> @@ -34,7 +35,7 @@ static void xe_sysctrl_get_pending_event(struct xe_device *xe,
> xe_err(xe, "Unexpected response length %ld\n", len);
>
> if (response.event == XE_SYSCTRL_EVENT_THRESHOLD_CROSSED)
> - xe_warn(xe, "Counter threshold crossed\n");
> + xe_ras_event_log(xe, &response);
> else
> xe_err(xe, "Unexpected event %#x\n", response.event);
>
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [v1,4/4] drm/xe/ras: Introduce correctable error handling
2026-01-20 8:51 ` [v1,4/4] " Mallesh, Koujalagi
@ 2026-01-20 12:17 ` Raag Jadav
0 siblings, 0 replies; 17+ messages in thread
From: Raag Jadav @ 2026-01-20 12:17 UTC (permalink / raw)
To: Mallesh, Koujalagi
Cc: intel-xe, rodrigo.vivi, riana.tauro, michal.wajdeczko,
matthew.d.roper, umesh.nerlige.ramappa, soham.purkait,
anoop.c.vijay
On Tue, Jan 20, 2026 at 02:21:55PM +0530, Mallesh, Koujalagi wrote:
> Hi Raag,
>
> On 16-01-2026 03:03 pm, Raag Jadav wrote:
> > Add initial support for correctable error handling which is serviced
> > using system controller event. Currently we only log the errors in
> > dmesg but this serves as a foundation for RAS infrastructure and will
> > be further extended to facilitate other RAS features.
> >
> > Signed-off-by: Raag Jadav <raag.jadav@intel.com>
> > ---
> > drivers/gpu/drm/xe/Makefile | 1 +
> > drivers/gpu/drm/xe/xe_ras.c | 86 +++++++++++++++++++++++++++
> > drivers/gpu/drm/xe/xe_ras.h | 14 +++++
> > drivers/gpu/drm/xe/xe_ras_types.h | 79 ++++++++++++++++++++++++
> > drivers/gpu/drm/xe/xe_sysctrl_event.c | 3 +-
> > 5 files changed, 182 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/gpu/drm/xe/xe_ras.c
> > create mode 100644 drivers/gpu/drm/xe/xe_ras.h
> > create mode 100644 drivers/gpu/drm/xe/xe_ras_types.h
> >
> > diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> > index 16e28cab8464..8cc060a64c90 100644
> > --- a/drivers/gpu/drm/xe/Makefile
> > +++ b/drivers/gpu/drm/xe/Makefile
> > @@ -110,6 +110,7 @@ xe-y += xe_bb.o \
> > xe_pxp_submit.o \
> > xe_query.o \
> > xe_range_fence.o \
> > + xe_ras.o \
> > xe_reg_sr.o \
> > xe_reg_whitelist.o \
> > xe_ring_ops.o \
> > diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> > new file mode 100644
> > index 000000000000..6fea009c991a
> > --- /dev/null
> > +++ b/drivers/gpu/drm/xe/xe_ras.c
> > @@ -0,0 +1,86 @@
> > +// SPDX-License-Identifier: MIT
> > +/*
> > + * Copyright © 2026 Intel Corporation
> > + */
> > +
> > +#include "xe_assert.h"
> > +#include "xe_printk.h"
> > +#include "xe_ras.h"
> > +#include "xe_ras_types.h"
> > +#include "xe_sysctrl_event_types.h"
> > +
> > +/* Severity of detected errors */
> > +enum xe_ras_severity {
> > + XE_RAS_SEV_NOT_SUPPORTED = 0x00,
> > + XE_RAS_SEV_CORRECTABLE = 0x01,
> > + XE_RAS_SEV_UNCORRECTABLE = 0x02,
> > + XE_RAS_SEV_INFORMATIONAL = 0x03,
> > + XE_RAS_SEV_MAX
> > +};
> > +
> > +/* Major IP blocks/components where errors can originate */
> > +enum xe_ras_component {
> > + XE_RAS_COMP_NOT_SUPPORTED = 0x00,
> > + XE_RAS_COMP_MEMORY = 0x01,
> > + XE_RAS_COMP_GT = 0x02,
> > + XE_RAS_COMP_RESERVED = 0x03,
> > + XE_RAS_COMP_PCIE = 0x04,
> > + XE_RAS_COMP_FABRIC = 0x05,
> > + XE_RAS_COMP_SOC = 0x06,
> > + XE_RAS_COMP_MAX
> > +};
> > +
> > +static const char *xe_ras_severities[] = {
> > + [XE_RAS_SEV_NOT_SUPPORTED] = "Not Supported",
> > + [XE_RAS_SEV_CORRECTABLE] = "Correctable",
> > + [XE_RAS_SEV_UNCORRECTABLE] = "Uncorrectable",
> > + [XE_RAS_SEV_INFORMATIONAL] = "Informational",
> > +};
> > +static_assert(ARRAY_SIZE(xe_ras_severities) == XE_RAS_SEV_MAX);
> > +
> > +static const char *xe_ras_components[] = {
> > + [XE_RAS_COMP_NOT_SUPPORTED] = "Not Supported",
> > + [XE_RAS_COMP_MEMORY] = "Memory",
> > + [XE_RAS_COMP_GT] = "GT",
> > + [XE_RAS_COMP_RESERVED] = "Reserved",
> > + [XE_RAS_COMP_PCIE] = "PCIe",
> > + [XE_RAS_COMP_FABRIC] = "Fabric",
> > + [XE_RAS_COMP_SOC] = "SoC",
> > +};
> > +static_assert(ARRAY_SIZE(xe_ras_components) == XE_RAS_COMP_MAX);
> > +
> > +static inline const char *sev_to_str(struct xe_device *xe, u32 sev)
> > +{
> > + xe_assert(xe, sev < XE_RAS_SEV_MAX);
> > +
> > + return xe_ras_severities[sev];
> > +}
> > +
> > +static inline const char *comp_to_str(struct xe_device *xe, u32 comp)
> > +{
> > + xe_assert(xe, comp < XE_RAS_COMP_MAX);
> > +
> > + return xe_ras_components[comp];
> > +}
> > +
> > +void xe_ras_event_log(struct xe_device *xe, struct xe_sysctrl_event_response *response)
> > +{
> > + struct xe_ras_event_threshold_crossed *pending = (void *)&response->data;
> > + struct xe_ras_error *errors = pending->counters;
> > + u32 cid, sev, comp, inst, cause;
> > + u8 tile;
> > +
> > + xe_assert(xe, pending->ncounters < XE_RAS_NUM_COUNTERS);
> > +
> > + for (cid = 0; cid < pending->ncounters; cid++) {
> > + sev = errors[cid].common.severity;
> > + comp = errors[cid].common.component;
> > +
> > + tile = errors[cid].product.unit.tile;
> > + inst = errors[cid].product.unit.instance;
> > + cause = errors[cid].product.cause.cause;
> > +
> > + xe_warn(xe, "[RAS]: Error:%s Tile:%u Component:%s Instance:%u Cause:%#x\n",
> > + sev_to_str(xe, sev), tile, comp_to_str(xe, comp), inst, cause);
>
> Please add Error timestamp and Threshold reason.
Sure. The timestamp will be per event so we'll probably need to log it
before we land here.
Raag
> > + }
> > +}
> > diff --git a/drivers/gpu/drm/xe/xe_ras.h b/drivers/gpu/drm/xe/xe_ras.h
> > new file mode 100644
> > index 000000000000..fdefe0e2fe98
> > --- /dev/null
> > +++ b/drivers/gpu/drm/xe/xe_ras.h
> > @@ -0,0 +1,14 @@
> > +/* SPDX-License-Identifier: MIT */
> > +/*
> > + * Copyright © 2026 Intel Corporation
> > + */
> > +
> > +#ifndef _XE_RAS_H_
> > +#define _XE_RAS_H_
> > +
> > +struct xe_device;
> > +struct xe_sysctrl_event_response;
> > +
> > +void xe_ras_event_log(struct xe_device *xe, struct xe_sysctrl_event_response *response);
> > +
> > +#endif
> > diff --git a/drivers/gpu/drm/xe/xe_ras_types.h b/drivers/gpu/drm/xe/xe_ras_types.h
> > new file mode 100644
> > index 000000000000..348ba520d676
> > --- /dev/null
> > +++ b/drivers/gpu/drm/xe/xe_ras_types.h
> > @@ -0,0 +1,79 @@
> > +/* SPDX-License-Identifier: MIT */
> > +/*
> > + * Copyright © 2026 Intel Corporation
> > + */
> > +
> > +#ifndef _XE_RAS_TYPES_H_
> > +#define _XE_RAS_TYPES_H_
> > +
> > +#include <linux/types.h>
> > +
> > +#define XE_RAS_NUM_COUNTERS 21
> > +
> > +/**
> > + * struct xe_ras_error_common - Error fields that are common across all products
> > + */
> > +struct xe_ras_error_common {
> > + /** @severity: Error severity */
> > + u8 severity;
> > + /** @component: IP block where error originated */
> > + u8 component;
> > +} __packed;
> > +
> > +/**
> > + * struct xe_ras_error_unit - Error unit information
> > + */
> > +struct xe_ras_error_unit {
> > + /** @tile: Tile identifier */
> > + u8 tile;
> > + /** @instance: Instance identifier specific to IP */
> > + u32 instance;
> > +} __packed;
> > +
> > +/**
> > + * struct xe_ras_error_cause - Error cause information
> > + */
> > +struct xe_ras_error_cause {
> > + /** @cause: Cause/checker */
> > + u32 cause;
> > + /** @reserved: For future use */
> > + u8 reserved;
> > +} __packed;
> > +
> > +/**
> > + * struct xe_ras_error_product - Error fields that are specific to the product
> > + */
> > +struct xe_ras_error_product {
> > + /** @unit: Unit within IP block */
> > + struct xe_ras_error_unit unit;
> > + /** @cause: Cause/checker */
> > + struct xe_ras_error_cause cause;
> > +} __packed;
> > +
> > +/**
> > + * struct xe_ras_error - Combines common and product-specific parts
> > + */
> > +struct xe_ras_error {
> > + /** @common: Common error type and component */
> > + struct xe_ras_error_common common;
> > + /** @product: Product-specific unit and cause */
> > + struct xe_ras_error_product product;
> > +} __packed;
> > +
> > +/**
> > + * struct xe_ras_event_threshold_crossed - Event data for counter threshold crossed event
> > + */
> > +struct xe_ras_event_threshold_crossed {
> > + /** @ncounters: Number of counters that crossed thresholds */
> > + u32 ncounters;
> > + /** @ts_high: Upper 32 bits of event timestamp */
> > + u32 ts_high;
> > + /** @ts_low: Lower 32 bits of event timestamp */
> > + u32 ts_low;
> > + /** @reason: Threshold cross reason */
> > + u32 reason;
> > + /** @counters: Array of error counters that crossed threshold */
> > + struct xe_ras_error counters[XE_RAS_NUM_COUNTERS];
> > +} __packed;
> > +
> > +#endif
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event.c b/drivers/gpu/drm/xe/xe_sysctrl_event.c
> > index 3a860bc34db0..d70bef72764f 100644
> > --- a/drivers/gpu/drm/xe/xe_sysctrl_event.c
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl_event.c
> > @@ -8,6 +8,7 @@
> > #include "xe_irq.h"
> > #include "xe_pm.h"
> > #include "xe_printk.h"
> > +#include "xe_ras.h"
> > #include "xe_sysctrl.h"
> > #include "xe_sysctrl_event_types.h"
> > #include "xe_sysctrl_mailbox.h"
> > @@ -34,7 +35,7 @@ static void xe_sysctrl_get_pending_event(struct xe_device *xe,
> > xe_err(xe, "Unexpected response length %ld\n", len);
> > if (response.event == XE_SYSCTRL_EVENT_THRESHOLD_CROSSED)
> > - xe_warn(xe, "Counter threshold crossed\n");
> > + xe_ras_event_log(xe, &response);
> > else
> > xe_err(xe, "Unexpected event %#x\n", response.event);
^ permalink raw reply [flat|nested] 17+ messages in thread
* ✗ CI.checkpatch: warning for Introduce Xe Correctable Error Handling
2026-01-16 9:33 [PATCH v1 0/4] Introduce Xe Correctable Error Handling Raag Jadav
` (3 preceding siblings ...)
2026-01-16 9:33 ` [PATCH v1 4/4] drm/xe/ras: Introduce correctable error handling Raag Jadav
@ 2026-01-16 10:08 ` Patchwork
2026-01-16 10:09 ` ✓ CI.KUnit: success " Patchwork
` (2 subsequent siblings)
7 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2026-01-16 10:08 UTC (permalink / raw)
To: Raag Jadav; +Cc: intel-xe
== Series Details ==
Series: Introduce Xe Correctable Error Handling
URL : https://patchwork.freedesktop.org/series/160184/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
ee83616c430ce70bd254bd2774d143a5733c8666
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 72fb0963b3aff4366f6f0ac5e3d7ca1791511023
Author: Raag Jadav <raag.jadav@intel.com>
Date: Fri Jan 16 15:03:33 2026 +0530
drm/xe/ras: Introduce correctable error handling
Add initial support for correctable error handling which is serviced
using system controller event. Currently we only log the errors in
dmesg but this serves as a foundation for RAS infrastructure and will
be further extended to facilitate other RAS features.
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
+ /mt/dim checkpatch 2c3e2b14be8eda5fb69764bb077663809afa183c drm-intel
e57b7efcecce drm/xe/sysctrl: Add System Controller
-:24: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#24:
new file mode 100644
-:800: ERROR:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Anoop Vijay <anoop.c.vijay@intel.com>'
total: 1 errors, 1 warnings, 0 checks, 720 lines checked
c722682db1af drm/xe/sysctrl: Add system controller interrupt handler
26fa4a379607 drm/xe/sysctrl: Add system controller event support
-:61: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#61:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 174 lines checked
72fb0963b3af drm/xe/ras: Introduce correctable error handling
-:26: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#26:
new file mode 100644
-:63: WARNING:STATIC_CONST_CHAR_ARRAY: static const char * array should probably be static const char * const
#63: FILE: drivers/gpu/drm/xe/xe_ras.c:33:
+static const char *xe_ras_severities[] = {
-:69: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#69: FILE: drivers/gpu/drm/xe/xe_ras.c:39:
+};
+static_assert(ARRAY_SIZE(xe_ras_severities) == XE_RAS_SEV_MAX);
-:71: WARNING:STATIC_CONST_CHAR_ARRAY: static const char * array should probably be static const char * const
#71: FILE: drivers/gpu/drm/xe/xe_ras.c:41:
+static const char *xe_ras_components[] = {
-:80: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#80: FILE: drivers/gpu/drm/xe/xe_ras.c:50:
+};
+static_assert(ARRAY_SIZE(xe_ras_components) == XE_RAS_COMP_MAX);
total: 0 errors, 3 warnings, 2 checks, 201 lines checked
^ permalink raw reply [flat|nested] 17+ messages in thread* ✓ CI.KUnit: success for Introduce Xe Correctable Error Handling
2026-01-16 9:33 [PATCH v1 0/4] Introduce Xe Correctable Error Handling Raag Jadav
` (4 preceding siblings ...)
2026-01-16 10:08 ` ✗ CI.checkpatch: warning for Introduce Xe Correctable Error Handling Patchwork
@ 2026-01-16 10:09 ` Patchwork
2026-01-16 11:02 ` ✓ Xe.CI.BAT: " Patchwork
2026-01-16 14:25 ` ✓ Xe.CI.Full: " Patchwork
7 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2026-01-16 10:09 UTC (permalink / raw)
To: Raag Jadav; +Cc: intel-xe
== Series Details ==
Series: Introduce Xe Correctable Error Handling
URL : https://patchwork.freedesktop.org/series/160184/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[10:08:03] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:08:08] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[10:08:47] Starting KUnit Kernel (1/1)...
[10:08:47] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:08:47] ================== guc_buf (11 subtests) ===================
[10:08:47] [PASSED] test_smallest
[10:08:47] [PASSED] test_largest
[10:08:47] [PASSED] test_granular
[10:08:47] [PASSED] test_unique
[10:08:47] [PASSED] test_overlap
[10:08:47] [PASSED] test_reusable
[10:08:47] [PASSED] test_too_big
[10:08:47] [PASSED] test_flush
[10:08:47] [PASSED] test_lookup
[10:08:47] [PASSED] test_data
[10:08:47] [PASSED] test_class
[10:08:47] ===================== [PASSED] guc_buf =====================
[10:08:47] =================== guc_dbm (7 subtests) ===================
[10:08:47] [PASSED] test_empty
[10:08:47] [PASSED] test_default
[10:08:47] ======================== test_size ========================
[10:08:47] [PASSED] 4
[10:08:47] [PASSED] 8
[10:08:47] [PASSED] 32
[10:08:47] [PASSED] 256
[10:08:47] ==================== [PASSED] test_size ====================
[10:08:47] ======================= test_reuse ========================
[10:08:47] [PASSED] 4
[10:08:47] [PASSED] 8
[10:08:47] [PASSED] 32
[10:08:47] [PASSED] 256
[10:08:47] =================== [PASSED] test_reuse ====================
[10:08:47] =================== test_range_overlap ====================
[10:08:47] [PASSED] 4
[10:08:47] [PASSED] 8
[10:08:47] [PASSED] 32
[10:08:47] [PASSED] 256
[10:08:47] =============== [PASSED] test_range_overlap ================
[10:08:47] =================== test_range_compact ====================
[10:08:47] [PASSED] 4
[10:08:47] [PASSED] 8
[10:08:47] [PASSED] 32
[10:08:47] [PASSED] 256
[10:08:47] =============== [PASSED] test_range_compact ================
[10:08:47] ==================== test_range_spare =====================
[10:08:47] [PASSED] 4
[10:08:47] [PASSED] 8
[10:08:47] [PASSED] 32
[10:08:47] [PASSED] 256
[10:08:47] ================ [PASSED] test_range_spare =================
[10:08:47] ===================== [PASSED] guc_dbm =====================
[10:08:47] =================== guc_idm (6 subtests) ===================
[10:08:47] [PASSED] bad_init
[10:08:47] [PASSED] no_init
[10:08:47] [PASSED] init_fini
[10:08:47] [PASSED] check_used
[10:08:47] [PASSED] check_quota
[10:08:47] [PASSED] check_all
[10:08:47] ===================== [PASSED] guc_idm =====================
[10:08:47] ================== no_relay (3 subtests) ===================
[10:08:47] [PASSED] xe_drops_guc2pf_if_not_ready
[10:08:47] [PASSED] xe_drops_guc2vf_if_not_ready
[10:08:47] [PASSED] xe_rejects_send_if_not_ready
[10:08:47] ==================== [PASSED] no_relay =====================
[10:08:47] ================== pf_relay (14 subtests) ==================
[10:08:47] [PASSED] pf_rejects_guc2pf_too_short
[10:08:47] [PASSED] pf_rejects_guc2pf_too_long
[10:08:47] [PASSED] pf_rejects_guc2pf_no_payload
[10:08:47] [PASSED] pf_fails_no_payload
[10:08:47] [PASSED] pf_fails_bad_origin
[10:08:47] [PASSED] pf_fails_bad_type
[10:08:47] [PASSED] pf_txn_reports_error
[10:08:47] [PASSED] pf_txn_sends_pf2guc
[10:08:47] [PASSED] pf_sends_pf2guc
[10:08:47] [SKIPPED] pf_loopback_nop
[10:08:47] [SKIPPED] pf_loopback_echo
[10:08:47] [SKIPPED] pf_loopback_fail
[10:08:47] [SKIPPED] pf_loopback_busy
[10:08:47] [SKIPPED] pf_loopback_retry
[10:08:47] ==================== [PASSED] pf_relay =====================
[10:08:47] ================== vf_relay (3 subtests) ===================
[10:08:47] [PASSED] vf_rejects_guc2vf_too_short
[10:08:47] [PASSED] vf_rejects_guc2vf_too_long
[10:08:47] [PASSED] vf_rejects_guc2vf_no_payload
[10:08:47] ==================== [PASSED] vf_relay =====================
[10:08:47] ================ pf_gt_config (6 subtests) =================
[10:08:47] [PASSED] fair_contexts_1vf
[10:08:47] [PASSED] fair_doorbells_1vf
[10:08:47] [PASSED] fair_ggtt_1vf
[10:08:47] ====================== fair_contexts ======================
[10:08:47] [PASSED] 1 VF
[10:08:47] [PASSED] 2 VFs
[10:08:47] [PASSED] 3 VFs
[10:08:47] [PASSED] 4 VFs
[10:08:47] [PASSED] 5 VFs
[10:08:47] [PASSED] 6 VFs
[10:08:47] [PASSED] 7 VFs
[10:08:47] [PASSED] 8 VFs
[10:08:47] [PASSED] 9 VFs
[10:08:47] [PASSED] 10 VFs
[10:08:47] [PASSED] 11 VFs
[10:08:47] [PASSED] 12 VFs
[10:08:47] [PASSED] 13 VFs
[10:08:47] [PASSED] 14 VFs
[10:08:47] [PASSED] 15 VFs
[10:08:47] [PASSED] 16 VFs
[10:08:47] [PASSED] 17 VFs
[10:08:47] [PASSED] 18 VFs
[10:08:47] [PASSED] 19 VFs
[10:08:47] [PASSED] 20 VFs
[10:08:47] [PASSED] 21 VFs
[10:08:47] [PASSED] 22 VFs
[10:08:47] [PASSED] 23 VFs
[10:08:47] [PASSED] 24 VFs
[10:08:47] [PASSED] 25 VFs
[10:08:47] [PASSED] 26 VFs
[10:08:47] [PASSED] 27 VFs
[10:08:47] [PASSED] 28 VFs
[10:08:47] [PASSED] 29 VFs
[10:08:47] [PASSED] 30 VFs
[10:08:47] [PASSED] 31 VFs
[10:08:47] [PASSED] 32 VFs
[10:08:47] [PASSED] 33 VFs
[10:08:47] [PASSED] 34 VFs
[10:08:47] [PASSED] 35 VFs
[10:08:47] [PASSED] 36 VFs
[10:08:47] [PASSED] 37 VFs
[10:08:47] [PASSED] 38 VFs
[10:08:47] [PASSED] 39 VFs
[10:08:47] [PASSED] 40 VFs
[10:08:47] [PASSED] 41 VFs
[10:08:47] [PASSED] 42 VFs
[10:08:47] [PASSED] 43 VFs
[10:08:47] [PASSED] 44 VFs
[10:08:47] [PASSED] 45 VFs
[10:08:47] [PASSED] 46 VFs
[10:08:47] [PASSED] 47 VFs
[10:08:47] [PASSED] 48 VFs
[10:08:47] [PASSED] 49 VFs
[10:08:47] [PASSED] 50 VFs
[10:08:47] [PASSED] 51 VFs
[10:08:47] [PASSED] 52 VFs
[10:08:47] [PASSED] 53 VFs
[10:08:47] [PASSED] 54 VFs
[10:08:47] [PASSED] 55 VFs
[10:08:47] [PASSED] 56 VFs
[10:08:47] [PASSED] 57 VFs
[10:08:47] [PASSED] 58 VFs
[10:08:47] [PASSED] 59 VFs
[10:08:47] [PASSED] 60 VFs
[10:08:47] [PASSED] 61 VFs
[10:08:47] [PASSED] 62 VFs
[10:08:47] [PASSED] 63 VFs
[10:08:47] ================== [PASSED] fair_contexts ==================
[10:08:47] ===================== fair_doorbells ======================
[10:08:47] [PASSED] 1 VF
[10:08:47] [PASSED] 2 VFs
[10:08:47] [PASSED] 3 VFs
[10:08:47] [PASSED] 4 VFs
[10:08:47] [PASSED] 5 VFs
[10:08:47] [PASSED] 6 VFs
[10:08:47] [PASSED] 7 VFs
[10:08:47] [PASSED] 8 VFs
[10:08:47] [PASSED] 9 VFs
[10:08:47] [PASSED] 10 VFs
[10:08:47] [PASSED] 11 VFs
[10:08:47] [PASSED] 12 VFs
[10:08:47] [PASSED] 13 VFs
[10:08:47] [PASSED] 14 VFs
[10:08:47] [PASSED] 15 VFs
[10:08:47] [PASSED] 16 VFs
[10:08:47] [PASSED] 17 VFs
[10:08:47] [PASSED] 18 VFs
[10:08:47] [PASSED] 19 VFs
[10:08:47] [PASSED] 20 VFs
[10:08:47] [PASSED] 21 VFs
[10:08:47] [PASSED] 22 VFs
[10:08:47] [PASSED] 23 VFs
[10:08:47] [PASSED] 24 VFs
[10:08:47] [PASSED] 25 VFs
[10:08:47] [PASSED] 26 VFs
[10:08:47] [PASSED] 27 VFs
[10:08:47] [PASSED] 28 VFs
[10:08:47] [PASSED] 29 VFs
[10:08:47] [PASSED] 30 VFs
[10:08:47] [PASSED] 31 VFs
[10:08:47] [PASSED] 32 VFs
[10:08:47] [PASSED] 33 VFs
[10:08:47] [PASSED] 34 VFs
[10:08:47] [PASSED] 35 VFs
[10:08:47] [PASSED] 36 VFs
[10:08:47] [PASSED] 37 VFs
[10:08:47] [PASSED] 38 VFs
[10:08:47] [PASSED] 39 VFs
[10:08:47] [PASSED] 40 VFs
[10:08:47] [PASSED] 41 VFs
[10:08:47] [PASSED] 42 VFs
[10:08:47] [PASSED] 43 VFs
[10:08:47] [PASSED] 44 VFs
[10:08:47] [PASSED] 45 VFs
[10:08:47] [PASSED] 46 VFs
[10:08:47] [PASSED] 47 VFs
[10:08:47] [PASSED] 48 VFs
[10:08:47] [PASSED] 49 VFs
[10:08:47] [PASSED] 50 VFs
[10:08:47] [PASSED] 51 VFs
[10:08:47] [PASSED] 52 VFs
[10:08:47] [PASSED] 53 VFs
[10:08:47] [PASSED] 54 VFs
[10:08:47] [PASSED] 55 VFs
[10:08:47] [PASSED] 56 VFs
[10:08:47] [PASSED] 57 VFs
[10:08:47] [PASSED] 58 VFs
[10:08:47] [PASSED] 59 VFs
[10:08:47] [PASSED] 60 VFs
[10:08:47] [PASSED] 61 VFs
[10:08:47] [PASSED] 62 VFs
[10:08:47] [PASSED] 63 VFs
[10:08:47] ================= [PASSED] fair_doorbells ==================
[10:08:47] ======================== fair_ggtt ========================
[10:08:47] [PASSED] 1 VF
[10:08:47] [PASSED] 2 VFs
[10:08:47] [PASSED] 3 VFs
[10:08:47] [PASSED] 4 VFs
[10:08:47] [PASSED] 5 VFs
[10:08:47] [PASSED] 6 VFs
[10:08:47] [PASSED] 7 VFs
[10:08:47] [PASSED] 8 VFs
[10:08:47] [PASSED] 9 VFs
[10:08:47] [PASSED] 10 VFs
[10:08:47] [PASSED] 11 VFs
[10:08:47] [PASSED] 12 VFs
[10:08:47] [PASSED] 13 VFs
[10:08:47] [PASSED] 14 VFs
[10:08:47] [PASSED] 15 VFs
[10:08:47] [PASSED] 16 VFs
[10:08:47] [PASSED] 17 VFs
[10:08:47] [PASSED] 18 VFs
[10:08:47] [PASSED] 19 VFs
[10:08:47] [PASSED] 20 VFs
[10:08:47] [PASSED] 21 VFs
[10:08:47] [PASSED] 22 VFs
[10:08:47] [PASSED] 23 VFs
[10:08:47] [PASSED] 24 VFs
[10:08:47] [PASSED] 25 VFs
[10:08:47] [PASSED] 26 VFs
[10:08:47] [PASSED] 27 VFs
[10:08:47] [PASSED] 28 VFs
[10:08:47] [PASSED] 29 VFs
[10:08:47] [PASSED] 30 VFs
[10:08:47] [PASSED] 31 VFs
[10:08:47] [PASSED] 32 VFs
[10:08:47] [PASSED] 33 VFs
[10:08:47] [PASSED] 34 VFs
[10:08:47] [PASSED] 35 VFs
[10:08:47] [PASSED] 36 VFs
[10:08:47] [PASSED] 37 VFs
[10:08:47] [PASSED] 38 VFs
[10:08:47] [PASSED] 39 VFs
[10:08:47] [PASSED] 40 VFs
[10:08:47] [PASSED] 41 VFs
[10:08:47] [PASSED] 42 VFs
[10:08:47] [PASSED] 43 VFs
[10:08:47] [PASSED] 44 VFs
[10:08:47] [PASSED] 45 VFs
[10:08:47] [PASSED] 46 VFs
[10:08:47] [PASSED] 47 VFs
[10:08:47] [PASSED] 48 VFs
[10:08:47] [PASSED] 49 VFs
[10:08:47] [PASSED] 50 VFs
[10:08:47] [PASSED] 51 VFs
[10:08:47] [PASSED] 52 VFs
[10:08:47] [PASSED] 53 VFs
[10:08:47] [PASSED] 54 VFs
[10:08:47] [PASSED] 55 VFs
[10:08:47] [PASSED] 56 VFs
[10:08:47] [PASSED] 57 VFs
[10:08:47] [PASSED] 58 VFs
[10:08:47] [PASSED] 59 VFs
[10:08:47] [PASSED] 60 VFs
[10:08:47] [PASSED] 61 VFs
[10:08:47] [PASSED] 62 VFs
[10:08:47] [PASSED] 63 VFs
[10:08:47] ==================== [PASSED] fair_ggtt ====================
[10:08:47] ================== [PASSED] pf_gt_config ===================
[10:08:47] ===================== lmtt (1 subtest) =====================
[10:08:47] ======================== test_ops =========================
[10:08:47] [PASSED] 2-level
[10:08:47] [PASSED] multi-level
[10:08:47] ==================== [PASSED] test_ops =====================
[10:08:47] ====================== [PASSED] lmtt =======================
[10:08:47] ================= pf_service (11 subtests) =================
[10:08:47] [PASSED] pf_negotiate_any
[10:08:47] [PASSED] pf_negotiate_base_match
[10:08:47] [PASSED] pf_negotiate_base_newer
[10:08:47] [PASSED] pf_negotiate_base_next
[10:08:47] [SKIPPED] pf_negotiate_base_older
[10:08:47] [PASSED] pf_negotiate_base_prev
[10:08:47] [PASSED] pf_negotiate_latest_match
[10:08:47] [PASSED] pf_negotiate_latest_newer
[10:08:47] [PASSED] pf_negotiate_latest_next
[10:08:47] [SKIPPED] pf_negotiate_latest_older
[10:08:47] [SKIPPED] pf_negotiate_latest_prev
[10:08:47] =================== [PASSED] pf_service ====================
[10:08:47] ================= xe_guc_g2g (2 subtests) ==================
[10:08:47] ============== xe_live_guc_g2g_kunit_default ==============
[10:08:47] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[10:08:47] ============== xe_live_guc_g2g_kunit_allmem ===============
[10:08:47] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[10:08:47] =================== [SKIPPED] xe_guc_g2g ===================
[10:08:47] =================== xe_mocs (2 subtests) ===================
[10:08:47] ================ xe_live_mocs_kernel_kunit ================
[10:08:47] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[10:08:47] ================ xe_live_mocs_reset_kunit =================
[10:08:47] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[10:08:47] ==================== [SKIPPED] xe_mocs =====================
[10:08:47] ================= xe_migrate (2 subtests) ==================
[10:08:47] ================= xe_migrate_sanity_kunit =================
[10:08:47] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[10:08:47] ================== xe_validate_ccs_kunit ==================
[10:08:47] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[10:08:47] =================== [SKIPPED] xe_migrate ===================
[10:08:47] ================== xe_dma_buf (1 subtest) ==================
[10:08:47] ==================== xe_dma_buf_kunit =====================
[10:08:47] ================ [SKIPPED] xe_dma_buf_kunit ================
[10:08:47] =================== [SKIPPED] xe_dma_buf ===================
[10:08:47] ================= xe_bo_shrink (1 subtest) =================
[10:08:47] =================== xe_bo_shrink_kunit ====================
[10:08:47] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[10:08:47] ================== [SKIPPED] xe_bo_shrink ==================
[10:08:47] ==================== xe_bo (2 subtests) ====================
[10:08:47] ================== xe_ccs_migrate_kunit ===================
[10:08:47] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[10:08:47] ==================== xe_bo_evict_kunit ====================
[10:08:47] =============== [SKIPPED] xe_bo_evict_kunit ================
[10:08:47] ===================== [SKIPPED] xe_bo ======================
[10:08:47] ==================== args (13 subtests) ====================
[10:08:47] [PASSED] count_args_test
[10:08:47] [PASSED] call_args_example
[10:08:47] [PASSED] call_args_test
[10:08:47] [PASSED] drop_first_arg_example
[10:08:47] [PASSED] drop_first_arg_test
[10:08:47] [PASSED] first_arg_example
[10:08:47] [PASSED] first_arg_test
[10:08:47] [PASSED] last_arg_example
[10:08:47] [PASSED] last_arg_test
[10:08:47] [PASSED] pick_arg_example
[10:08:47] [PASSED] if_args_example
[10:08:47] [PASSED] if_args_test
[10:08:47] [PASSED] sep_comma_example
[10:08:47] ====================== [PASSED] args =======================
[10:08:47] =================== xe_pci (3 subtests) ====================
[10:08:47] ==================== check_graphics_ip ====================
[10:08:47] [PASSED] 12.00 Xe_LP
[10:08:47] [PASSED] 12.10 Xe_LP+
[10:08:47] [PASSED] 12.55 Xe_HPG
[10:08:47] [PASSED] 12.60 Xe_HPC
[10:08:47] [PASSED] 12.70 Xe_LPG
[10:08:47] [PASSED] 12.71 Xe_LPG
[10:08:47] [PASSED] 12.74 Xe_LPG+
[10:08:47] [PASSED] 20.01 Xe2_HPG
[10:08:47] [PASSED] 20.02 Xe2_HPG
[10:08:47] [PASSED] 20.04 Xe2_LPG
[10:08:47] [PASSED] 30.00 Xe3_LPG
[10:08:47] [PASSED] 30.01 Xe3_LPG
[10:08:47] [PASSED] 30.03 Xe3_LPG
[10:08:47] [PASSED] 30.04 Xe3_LPG
[10:08:47] [PASSED] 30.05 Xe3_LPG
[10:08:47] [PASSED] 35.11 Xe3p_XPC
[10:08:47] ================ [PASSED] check_graphics_ip ================
[10:08:47] ===================== check_media_ip ======================
[10:08:47] [PASSED] 12.00 Xe_M
[10:08:47] [PASSED] 12.55 Xe_HPM
[10:08:47] [PASSED] 13.00 Xe_LPM+
[10:08:47] [PASSED] 13.01 Xe2_HPM
[10:08:47] [PASSED] 20.00 Xe2_LPM
[10:08:47] [PASSED] 30.00 Xe3_LPM
[10:08:47] [PASSED] 30.02 Xe3_LPM
[10:08:47] [PASSED] 35.00 Xe3p_LPM
[10:08:47] [PASSED] 35.03 Xe3p_HPM
[10:08:47] ================= [PASSED] check_media_ip ==================
[10:08:47] =================== check_platform_desc ===================
[10:08:47] [PASSED] 0x9A60 (TIGERLAKE)
[10:08:47] [PASSED] 0x9A68 (TIGERLAKE)
[10:08:47] [PASSED] 0x9A70 (TIGERLAKE)
[10:08:47] [PASSED] 0x9A40 (TIGERLAKE)
[10:08:47] [PASSED] 0x9A49 (TIGERLAKE)
[10:08:47] [PASSED] 0x9A59 (TIGERLAKE)
[10:08:47] [PASSED] 0x9A78 (TIGERLAKE)
[10:08:47] [PASSED] 0x9AC0 (TIGERLAKE)
[10:08:47] [PASSED] 0x9AC9 (TIGERLAKE)
[10:08:47] [PASSED] 0x9AD9 (TIGERLAKE)
[10:08:47] [PASSED] 0x9AF8 (TIGERLAKE)
[10:08:47] [PASSED] 0x4C80 (ROCKETLAKE)
[10:08:47] [PASSED] 0x4C8A (ROCKETLAKE)
[10:08:47] [PASSED] 0x4C8B (ROCKETLAKE)
[10:08:47] [PASSED] 0x4C8C (ROCKETLAKE)
[10:08:47] [PASSED] 0x4C90 (ROCKETLAKE)
[10:08:47] [PASSED] 0x4C9A (ROCKETLAKE)
[10:08:47] [PASSED] 0x4680 (ALDERLAKE_S)
[10:08:47] [PASSED] 0x4682 (ALDERLAKE_S)
[10:08:47] [PASSED] 0x4688 (ALDERLAKE_S)
[10:08:47] [PASSED] 0x468A (ALDERLAKE_S)
[10:08:47] [PASSED] 0x468B (ALDERLAKE_S)
[10:08:47] [PASSED] 0x4690 (ALDERLAKE_S)
[10:08:47] [PASSED] 0x4692 (ALDERLAKE_S)
[10:08:47] [PASSED] 0x4693 (ALDERLAKE_S)
[10:08:47] [PASSED] 0x46A0 (ALDERLAKE_P)
[10:08:47] [PASSED] 0x46A1 (ALDERLAKE_P)
[10:08:47] [PASSED] 0x46A2 (ALDERLAKE_P)
[10:08:47] [PASSED] 0x46A3 (ALDERLAKE_P)
[10:08:47] [PASSED] 0x46A6 (ALDERLAKE_P)
[10:08:47] [PASSED] 0x46A8 (ALDERLAKE_P)
[10:08:47] [PASSED] 0x46AA (ALDERLAKE_P)
[10:08:47] [PASSED] 0x462A (ALDERLAKE_P)
[10:08:47] [PASSED] 0x4626 (ALDERLAKE_P)
[10:08:47] [PASSED] 0x4628 (ALDERLAKE_P)
stty: 'standard input': Inappropriate ioctl for device
[10:08:47] [PASSED] 0x46B0 (ALDERLAKE_P)
[10:08:47] [PASSED] 0x46B1 (ALDERLAKE_P)
[10:08:47] [PASSED] 0x46B2 (ALDERLAKE_P)
[10:08:47] [PASSED] 0x46B3 (ALDERLAKE_P)
[10:08:47] [PASSED] 0x46C0 (ALDERLAKE_P)
[10:08:47] [PASSED] 0x46C1 (ALDERLAKE_P)
[10:08:47] [PASSED] 0x46C2 (ALDERLAKE_P)
[10:08:47] [PASSED] 0x46C3 (ALDERLAKE_P)
[10:08:47] [PASSED] 0x46D0 (ALDERLAKE_N)
[10:08:47] [PASSED] 0x46D1 (ALDERLAKE_N)
[10:08:47] [PASSED] 0x46D2 (ALDERLAKE_N)
[10:08:47] [PASSED] 0x46D3 (ALDERLAKE_N)
[10:08:47] [PASSED] 0x46D4 (ALDERLAKE_N)
[10:08:47] [PASSED] 0xA721 (ALDERLAKE_P)
[10:08:47] [PASSED] 0xA7A1 (ALDERLAKE_P)
[10:08:47] [PASSED] 0xA7A9 (ALDERLAKE_P)
[10:08:47] [PASSED] 0xA7AC (ALDERLAKE_P)
[10:08:47] [PASSED] 0xA7AD (ALDERLAKE_P)
[10:08:47] [PASSED] 0xA720 (ALDERLAKE_P)
[10:08:47] [PASSED] 0xA7A0 (ALDERLAKE_P)
[10:08:47] [PASSED] 0xA7A8 (ALDERLAKE_P)
[10:08:47] [PASSED] 0xA7AA (ALDERLAKE_P)
[10:08:47] [PASSED] 0xA7AB (ALDERLAKE_P)
[10:08:47] [PASSED] 0xA780 (ALDERLAKE_S)
[10:08:47] [PASSED] 0xA781 (ALDERLAKE_S)
[10:08:47] [PASSED] 0xA782 (ALDERLAKE_S)
[10:08:47] [PASSED] 0xA783 (ALDERLAKE_S)
[10:08:47] [PASSED] 0xA788 (ALDERLAKE_S)
[10:08:47] [PASSED] 0xA789 (ALDERLAKE_S)
[10:08:47] [PASSED] 0xA78A (ALDERLAKE_S)
[10:08:47] [PASSED] 0xA78B (ALDERLAKE_S)
[10:08:47] [PASSED] 0x4905 (DG1)
[10:08:47] [PASSED] 0x4906 (DG1)
[10:08:47] [PASSED] 0x4907 (DG1)
[10:08:47] [PASSED] 0x4908 (DG1)
[10:08:47] [PASSED] 0x4909 (DG1)
[10:08:47] [PASSED] 0x56C0 (DG2)
[10:08:47] [PASSED] 0x56C2 (DG2)
[10:08:47] [PASSED] 0x56C1 (DG2)
[10:08:47] [PASSED] 0x7D51 (METEORLAKE)
[10:08:47] [PASSED] 0x7DD1 (METEORLAKE)
[10:08:47] [PASSED] 0x7D41 (METEORLAKE)
[10:08:47] [PASSED] 0x7D67 (METEORLAKE)
[10:08:47] [PASSED] 0xB640 (METEORLAKE)
[10:08:47] [PASSED] 0x56A0 (DG2)
[10:08:47] [PASSED] 0x56A1 (DG2)
[10:08:47] [PASSED] 0x56A2 (DG2)
[10:08:47] [PASSED] 0x56BE (DG2)
[10:08:47] [PASSED] 0x56BF (DG2)
[10:08:47] [PASSED] 0x5690 (DG2)
[10:08:47] [PASSED] 0x5691 (DG2)
[10:08:47] [PASSED] 0x5692 (DG2)
[10:08:47] [PASSED] 0x56A5 (DG2)
[10:08:47] [PASSED] 0x56A6 (DG2)
[10:08:47] [PASSED] 0x56B0 (DG2)
[10:08:47] [PASSED] 0x56B1 (DG2)
[10:08:47] [PASSED] 0x56BA (DG2)
[10:08:47] [PASSED] 0x56BB (DG2)
[10:08:47] [PASSED] 0x56BC (DG2)
[10:08:47] [PASSED] 0x56BD (DG2)
[10:08:47] [PASSED] 0x5693 (DG2)
[10:08:47] [PASSED] 0x5694 (DG2)
[10:08:47] [PASSED] 0x5695 (DG2)
[10:08:47] [PASSED] 0x56A3 (DG2)
[10:08:47] [PASSED] 0x56A4 (DG2)
[10:08:47] [PASSED] 0x56B2 (DG2)
[10:08:47] [PASSED] 0x56B3 (DG2)
[10:08:47] [PASSED] 0x5696 (DG2)
[10:08:47] [PASSED] 0x5697 (DG2)
[10:08:47] [PASSED] 0xB69 (PVC)
[10:08:47] [PASSED] 0xB6E (PVC)
[10:08:47] [PASSED] 0xBD4 (PVC)
[10:08:47] [PASSED] 0xBD5 (PVC)
[10:08:47] [PASSED] 0xBD6 (PVC)
[10:08:47] [PASSED] 0xBD7 (PVC)
[10:08:47] [PASSED] 0xBD8 (PVC)
[10:08:47] [PASSED] 0xBD9 (PVC)
[10:08:47] [PASSED] 0xBDA (PVC)
[10:08:47] [PASSED] 0xBDB (PVC)
[10:08:47] [PASSED] 0xBE0 (PVC)
[10:08:47] [PASSED] 0xBE1 (PVC)
[10:08:47] [PASSED] 0xBE5 (PVC)
[10:08:47] [PASSED] 0x7D40 (METEORLAKE)
[10:08:47] [PASSED] 0x7D45 (METEORLAKE)
[10:08:47] [PASSED] 0x7D55 (METEORLAKE)
[10:08:47] [PASSED] 0x7D60 (METEORLAKE)
[10:08:47] [PASSED] 0x7DD5 (METEORLAKE)
[10:08:47] [PASSED] 0x6420 (LUNARLAKE)
[10:08:47] [PASSED] 0x64A0 (LUNARLAKE)
[10:08:47] [PASSED] 0x64B0 (LUNARLAKE)
[10:08:47] [PASSED] 0xE202 (BATTLEMAGE)
[10:08:47] [PASSED] 0xE209 (BATTLEMAGE)
[10:08:47] [PASSED] 0xE20B (BATTLEMAGE)
[10:08:47] [PASSED] 0xE20C (BATTLEMAGE)
[10:08:47] [PASSED] 0xE20D (BATTLEMAGE)
[10:08:47] [PASSED] 0xE210 (BATTLEMAGE)
[10:08:47] [PASSED] 0xE211 (BATTLEMAGE)
[10:08:47] [PASSED] 0xE212 (BATTLEMAGE)
[10:08:47] [PASSED] 0xE216 (BATTLEMAGE)
[10:08:47] [PASSED] 0xE220 (BATTLEMAGE)
[10:08:47] [PASSED] 0xE221 (BATTLEMAGE)
[10:08:47] [PASSED] 0xE222 (BATTLEMAGE)
[10:08:47] [PASSED] 0xE223 (BATTLEMAGE)
[10:08:47] [PASSED] 0xB080 (PANTHERLAKE)
[10:08:47] [PASSED] 0xB081 (PANTHERLAKE)
[10:08:47] [PASSED] 0xB082 (PANTHERLAKE)
[10:08:47] [PASSED] 0xB083 (PANTHERLAKE)
[10:08:47] [PASSED] 0xB084 (PANTHERLAKE)
[10:08:47] [PASSED] 0xB085 (PANTHERLAKE)
[10:08:47] [PASSED] 0xB086 (PANTHERLAKE)
[10:08:47] [PASSED] 0xB087 (PANTHERLAKE)
[10:08:47] [PASSED] 0xB08F (PANTHERLAKE)
[10:08:47] [PASSED] 0xB090 (PANTHERLAKE)
[10:08:47] [PASSED] 0xB0A0 (PANTHERLAKE)
[10:08:47] [PASSED] 0xB0B0 (PANTHERLAKE)
[10:08:47] [PASSED] 0xFD80 (PANTHERLAKE)
[10:08:47] [PASSED] 0xFD81 (PANTHERLAKE)
[10:08:47] [PASSED] 0xD740 (NOVALAKE_S)
[10:08:47] [PASSED] 0xD741 (NOVALAKE_S)
[10:08:47] [PASSED] 0xD742 (NOVALAKE_S)
[10:08:47] [PASSED] 0xD743 (NOVALAKE_S)
[10:08:47] [PASSED] 0xD744 (NOVALAKE_S)
[10:08:47] [PASSED] 0xD745 (NOVALAKE_S)
[10:08:47] [PASSED] 0x674C (CRESCENTISLAND)
[10:08:47] =============== [PASSED] check_platform_desc ===============
[10:08:47] ===================== [PASSED] xe_pci ======================
[10:08:47] =================== xe_rtp (2 subtests) ====================
[10:08:47] =============== xe_rtp_process_to_sr_tests ================
[10:08:47] [PASSED] coalesce-same-reg
[10:08:47] [PASSED] no-match-no-add
[10:08:47] [PASSED] match-or
[10:08:47] [PASSED] match-or-xfail
[10:08:47] [PASSED] no-match-no-add-multiple-rules
[10:08:47] [PASSED] two-regs-two-entries
[10:08:47] [PASSED] clr-one-set-other
[10:08:47] [PASSED] set-field
[10:08:47] [PASSED] conflict-duplicate
[10:08:47] [PASSED] conflict-not-disjoint
[10:08:47] [PASSED] conflict-reg-type
[10:08:47] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[10:08:47] ================== xe_rtp_process_tests ===================
[10:08:47] [PASSED] active1
[10:08:47] [PASSED] active2
[10:08:47] [PASSED] active-inactive
[10:08:47] [PASSED] inactive-active
[10:08:47] [PASSED] inactive-1st_or_active-inactive
[10:08:47] [PASSED] inactive-2nd_or_active-inactive
[10:08:47] [PASSED] inactive-last_or_active-inactive
[10:08:47] [PASSED] inactive-no_or_active-inactive
[10:08:47] ============== [PASSED] xe_rtp_process_tests ===============
[10:08:47] ===================== [PASSED] xe_rtp ======================
[10:08:47] ==================== xe_wa (1 subtest) =====================
[10:08:47] ======================== xe_wa_gt =========================
[10:08:47] [PASSED] TIGERLAKE B0
[10:08:47] [PASSED] DG1 A0
[10:08:47] [PASSED] DG1 B0
[10:08:47] [PASSED] ALDERLAKE_S A0
[10:08:47] [PASSED] ALDERLAKE_S B0
[10:08:47] [PASSED] ALDERLAKE_S C0
[10:08:47] [PASSED] ALDERLAKE_S D0
[10:08:47] [PASSED] ALDERLAKE_P A0
[10:08:47] [PASSED] ALDERLAKE_P B0
[10:08:47] [PASSED] ALDERLAKE_P C0
[10:08:47] [PASSED] ALDERLAKE_S RPLS D0
[10:08:47] [PASSED] ALDERLAKE_P RPLU E0
[10:08:47] [PASSED] DG2 G10 C0
[10:08:47] [PASSED] DG2 G11 B1
[10:08:47] [PASSED] DG2 G12 A1
[10:08:47] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[10:08:47] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[10:08:47] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[10:08:47] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[10:08:47] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[10:08:47] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[10:08:47] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[10:08:47] ==================== [PASSED] xe_wa_gt =====================
[10:08:47] ====================== [PASSED] xe_wa ======================
[10:08:47] ============================================================
[10:08:47] Testing complete. Ran 512 tests: passed: 494, skipped: 18
[10:08:47] Elapsed time: 44.288s total, 4.705s configuring, 39.066s building, 0.484s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[10:08:48] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:08:49] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[10:09:20] Starting KUnit Kernel (1/1)...
[10:09:20] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:09:20] ============ drm_test_pick_cmdline (2 subtests) ============
[10:09:20] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[10:09:20] =============== drm_test_pick_cmdline_named ===============
[10:09:20] [PASSED] NTSC
[10:09:20] [PASSED] NTSC-J
[10:09:20] [PASSED] PAL
[10:09:20] [PASSED] PAL-M
[10:09:20] =========== [PASSED] drm_test_pick_cmdline_named ===========
[10:09:20] ============== [PASSED] drm_test_pick_cmdline ==============
[10:09:20] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[10:09:20] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[10:09:20] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[10:09:20] =========== drm_validate_clone_mode (2 subtests) ===========
[10:09:20] ============== drm_test_check_in_clone_mode ===============
[10:09:20] [PASSED] in_clone_mode
[10:09:20] [PASSED] not_in_clone_mode
[10:09:20] ========== [PASSED] drm_test_check_in_clone_mode ===========
[10:09:20] =============== drm_test_check_valid_clones ===============
[10:09:20] [PASSED] not_in_clone_mode
[10:09:20] [PASSED] valid_clone
[10:09:20] [PASSED] invalid_clone
[10:09:20] =========== [PASSED] drm_test_check_valid_clones ===========
[10:09:20] ============= [PASSED] drm_validate_clone_mode =============
[10:09:20] ============= drm_validate_modeset (1 subtest) =============
[10:09:20] [PASSED] drm_test_check_connector_changed_modeset
[10:09:20] ============== [PASSED] drm_validate_modeset ===============
[10:09:20] ====== drm_test_bridge_get_current_state (2 subtests) ======
[10:09:20] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[10:09:20] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[10:09:20] ======== [PASSED] drm_test_bridge_get_current_state ========
[10:09:20] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[10:09:20] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[10:09:20] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[10:09:20] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[10:09:20] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[10:09:20] ============== drm_bridge_alloc (2 subtests) ===============
[10:09:20] [PASSED] drm_test_drm_bridge_alloc_basic
[10:09:20] [PASSED] drm_test_drm_bridge_alloc_get_put
[10:09:20] ================ [PASSED] drm_bridge_alloc =================
[10:09:20] ================== drm_buddy (8 subtests) ==================
[10:09:20] [PASSED] drm_test_buddy_alloc_limit
[10:09:20] [PASSED] drm_test_buddy_alloc_optimistic
[10:09:20] [PASSED] drm_test_buddy_alloc_pessimistic
[10:09:20] [PASSED] drm_test_buddy_alloc_pathological
[10:09:20] [PASSED] drm_test_buddy_alloc_contiguous
[10:09:20] [PASSED] drm_test_buddy_alloc_clear
[10:09:20] [PASSED] drm_test_buddy_alloc_range_bias
[10:09:20] [PASSED] drm_test_buddy_fragmentation_performance
[10:09:20] ==================== [PASSED] drm_buddy ====================
[10:09:20] ============= drm_cmdline_parser (40 subtests) =============
[10:09:20] [PASSED] drm_test_cmdline_force_d_only
[10:09:20] [PASSED] drm_test_cmdline_force_D_only_dvi
[10:09:20] [PASSED] drm_test_cmdline_force_D_only_hdmi
[10:09:20] [PASSED] drm_test_cmdline_force_D_only_not_digital
[10:09:20] [PASSED] drm_test_cmdline_force_e_only
[10:09:20] [PASSED] drm_test_cmdline_res
[10:09:20] [PASSED] drm_test_cmdline_res_vesa
[10:09:20] [PASSED] drm_test_cmdline_res_vesa_rblank
[10:09:20] [PASSED] drm_test_cmdline_res_rblank
[10:09:20] [PASSED] drm_test_cmdline_res_bpp
[10:09:20] [PASSED] drm_test_cmdline_res_refresh
[10:09:20] [PASSED] drm_test_cmdline_res_bpp_refresh
[10:09:20] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[10:09:20] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[10:09:20] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[10:09:20] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[10:09:20] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[10:09:20] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[10:09:20] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[10:09:20] [PASSED] drm_test_cmdline_res_margins_force_on
[10:09:20] [PASSED] drm_test_cmdline_res_vesa_margins
[10:09:20] [PASSED] drm_test_cmdline_name
[10:09:20] [PASSED] drm_test_cmdline_name_bpp
[10:09:20] [PASSED] drm_test_cmdline_name_option
[10:09:20] [PASSED] drm_test_cmdline_name_bpp_option
[10:09:20] [PASSED] drm_test_cmdline_rotate_0
[10:09:20] [PASSED] drm_test_cmdline_rotate_90
[10:09:20] [PASSED] drm_test_cmdline_rotate_180
[10:09:20] [PASSED] drm_test_cmdline_rotate_270
[10:09:20] [PASSED] drm_test_cmdline_hmirror
[10:09:20] [PASSED] drm_test_cmdline_vmirror
[10:09:20] [PASSED] drm_test_cmdline_margin_options
[10:09:20] [PASSED] drm_test_cmdline_multiple_options
[10:09:20] [PASSED] drm_test_cmdline_bpp_extra_and_option
[10:09:20] [PASSED] drm_test_cmdline_extra_and_option
[10:09:20] [PASSED] drm_test_cmdline_freestanding_options
[10:09:20] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[10:09:20] [PASSED] drm_test_cmdline_panel_orientation
[10:09:20] ================ drm_test_cmdline_invalid =================
[10:09:20] [PASSED] margin_only
[10:09:20] [PASSED] interlace_only
[10:09:20] [PASSED] res_missing_x
[10:09:20] [PASSED] res_missing_y
[10:09:20] [PASSED] res_bad_y
[10:09:20] [PASSED] res_missing_y_bpp
[10:09:20] [PASSED] res_bad_bpp
[10:09:20] [PASSED] res_bad_refresh
[10:09:20] [PASSED] res_bpp_refresh_force_on_off
[10:09:20] [PASSED] res_invalid_mode
[10:09:20] [PASSED] res_bpp_wrong_place_mode
[10:09:20] [PASSED] name_bpp_refresh
[10:09:20] [PASSED] name_refresh
[10:09:20] [PASSED] name_refresh_wrong_mode
[10:09:20] [PASSED] name_refresh_invalid_mode
[10:09:20] [PASSED] rotate_multiple
[10:09:20] [PASSED] rotate_invalid_val
[10:09:20] [PASSED] rotate_truncated
[10:09:20] [PASSED] invalid_option
[10:09:20] [PASSED] invalid_tv_option
[10:09:20] [PASSED] truncated_tv_option
[10:09:20] ============ [PASSED] drm_test_cmdline_invalid =============
[10:09:20] =============== drm_test_cmdline_tv_options ===============
[10:09:20] [PASSED] NTSC
[10:09:20] [PASSED] NTSC_443
[10:09:20] [PASSED] NTSC_J
[10:09:20] [PASSED] PAL
[10:09:20] [PASSED] PAL_M
[10:09:20] [PASSED] PAL_N
[10:09:20] [PASSED] SECAM
[10:09:20] [PASSED] MONO_525
[10:09:20] [PASSED] MONO_625
[10:09:20] =========== [PASSED] drm_test_cmdline_tv_options ===========
[10:09:20] =============== [PASSED] drm_cmdline_parser ================
[10:09:20] ========== drmm_connector_hdmi_init (20 subtests) ==========
[10:09:20] [PASSED] drm_test_connector_hdmi_init_valid
[10:09:20] [PASSED] drm_test_connector_hdmi_init_bpc_8
[10:09:20] [PASSED] drm_test_connector_hdmi_init_bpc_10
[10:09:20] [PASSED] drm_test_connector_hdmi_init_bpc_12
[10:09:20] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[10:09:20] [PASSED] drm_test_connector_hdmi_init_bpc_null
[10:09:20] [PASSED] drm_test_connector_hdmi_init_formats_empty
[10:09:20] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[10:09:20] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[10:09:20] [PASSED] supported_formats=0x9 yuv420_allowed=1
[10:09:20] [PASSED] supported_formats=0x9 yuv420_allowed=0
[10:09:20] [PASSED] supported_formats=0x3 yuv420_allowed=1
[10:09:20] [PASSED] supported_formats=0x3 yuv420_allowed=0
[10:09:20] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[10:09:20] [PASSED] drm_test_connector_hdmi_init_null_ddc
[10:09:20] [PASSED] drm_test_connector_hdmi_init_null_product
[10:09:20] [PASSED] drm_test_connector_hdmi_init_null_vendor
[10:09:20] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[10:09:20] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[10:09:20] [PASSED] drm_test_connector_hdmi_init_product_valid
[10:09:20] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[10:09:20] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[10:09:20] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[10:09:20] ========= drm_test_connector_hdmi_init_type_valid =========
[10:09:20] [PASSED] HDMI-A
[10:09:20] [PASSED] HDMI-B
[10:09:20] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[10:09:20] ======== drm_test_connector_hdmi_init_type_invalid ========
[10:09:20] [PASSED] Unknown
[10:09:20] [PASSED] VGA
[10:09:20] [PASSED] DVI-I
[10:09:20] [PASSED] DVI-D
[10:09:20] [PASSED] DVI-A
[10:09:20] [PASSED] Composite
[10:09:20] [PASSED] SVIDEO
[10:09:20] [PASSED] LVDS
[10:09:20] [PASSED] Component
[10:09:20] [PASSED] DIN
[10:09:20] [PASSED] DP
[10:09:20] [PASSED] TV
[10:09:20] [PASSED] eDP
[10:09:20] [PASSED] Virtual
[10:09:20] [PASSED] DSI
[10:09:20] [PASSED] DPI
[10:09:20] [PASSED] Writeback
[10:09:20] [PASSED] SPI
[10:09:20] [PASSED] USB
[10:09:20] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[10:09:20] ============ [PASSED] drmm_connector_hdmi_init =============
[10:09:20] ============= drmm_connector_init (3 subtests) =============
[10:09:20] [PASSED] drm_test_drmm_connector_init
[10:09:20] [PASSED] drm_test_drmm_connector_init_null_ddc
[10:09:20] ========= drm_test_drmm_connector_init_type_valid =========
[10:09:20] [PASSED] Unknown
[10:09:20] [PASSED] VGA
[10:09:20] [PASSED] DVI-I
[10:09:20] [PASSED] DVI-D
[10:09:20] [PASSED] DVI-A
[10:09:20] [PASSED] Composite
[10:09:20] [PASSED] SVIDEO
[10:09:20] [PASSED] LVDS
[10:09:20] [PASSED] Component
[10:09:20] [PASSED] DIN
[10:09:20] [PASSED] DP
[10:09:20] [PASSED] HDMI-A
[10:09:20] [PASSED] HDMI-B
[10:09:20] [PASSED] TV
[10:09:20] [PASSED] eDP
[10:09:20] [PASSED] Virtual
[10:09:20] [PASSED] DSI
[10:09:20] [PASSED] DPI
[10:09:20] [PASSED] Writeback
[10:09:20] [PASSED] SPI
[10:09:20] [PASSED] USB
[10:09:20] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[10:09:20] =============== [PASSED] drmm_connector_init ===============
[10:09:20] ========= drm_connector_dynamic_init (6 subtests) ==========
[10:09:20] [PASSED] drm_test_drm_connector_dynamic_init
[10:09:20] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[10:09:20] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[10:09:20] [PASSED] drm_test_drm_connector_dynamic_init_properties
[10:09:20] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[10:09:20] [PASSED] Unknown
[10:09:20] [PASSED] VGA
[10:09:20] [PASSED] DVI-I
[10:09:20] [PASSED] DVI-D
[10:09:20] [PASSED] DVI-A
[10:09:20] [PASSED] Composite
[10:09:20] [PASSED] SVIDEO
[10:09:20] [PASSED] LVDS
[10:09:20] [PASSED] Component
[10:09:20] [PASSED] DIN
[10:09:20] [PASSED] DP
[10:09:20] [PASSED] HDMI-A
[10:09:20] [PASSED] HDMI-B
[10:09:20] [PASSED] TV
[10:09:20] [PASSED] eDP
[10:09:20] [PASSED] Virtual
[10:09:20] [PASSED] DSI
[10:09:20] [PASSED] DPI
[10:09:20] [PASSED] Writeback
[10:09:20] [PASSED] SPI
[10:09:20] [PASSED] USB
[10:09:20] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[10:09:20] ======== drm_test_drm_connector_dynamic_init_name =========
[10:09:20] [PASSED] Unknown
[10:09:20] [PASSED] VGA
[10:09:20] [PASSED] DVI-I
[10:09:20] [PASSED] DVI-D
[10:09:20] [PASSED] DVI-A
[10:09:20] [PASSED] Composite
[10:09:20] [PASSED] SVIDEO
[10:09:20] [PASSED] LVDS
[10:09:20] [PASSED] Component
[10:09:20] [PASSED] DIN
[10:09:20] [PASSED] DP
[10:09:20] [PASSED] HDMI-A
[10:09:20] [PASSED] HDMI-B
[10:09:20] [PASSED] TV
[10:09:20] [PASSED] eDP
[10:09:20] [PASSED] Virtual
[10:09:20] [PASSED] DSI
[10:09:20] [PASSED] DPI
[10:09:20] [PASSED] Writeback
[10:09:20] [PASSED] SPI
[10:09:20] [PASSED] USB
[10:09:20] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[10:09:20] =========== [PASSED] drm_connector_dynamic_init ============
[10:09:20] ==== drm_connector_dynamic_register_early (4 subtests) =====
[10:09:20] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[10:09:20] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[10:09:20] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[10:09:20] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[10:09:20] ====== [PASSED] drm_connector_dynamic_register_early =======
[10:09:20] ======= drm_connector_dynamic_register (7 subtests) ========
[10:09:20] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[10:09:20] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[10:09:20] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[10:09:20] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[10:09:20] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[10:09:20] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[10:09:20] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[10:09:20] ========= [PASSED] drm_connector_dynamic_register ==========
[10:09:20] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[10:09:20] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[10:09:20] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[10:09:20] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[10:09:20] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[10:09:20] ========== drm_test_get_tv_mode_from_name_valid ===========
[10:09:20] [PASSED] NTSC
[10:09:20] [PASSED] NTSC-443
[10:09:20] [PASSED] NTSC-J
[10:09:20] [PASSED] PAL
[10:09:20] [PASSED] PAL-M
[10:09:20] [PASSED] PAL-N
[10:09:20] [PASSED] SECAM
[10:09:20] [PASSED] Mono
[10:09:20] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[10:09:20] [PASSED] drm_test_get_tv_mode_from_name_truncated
[10:09:20] ============ [PASSED] drm_get_tv_mode_from_name ============
[10:09:20] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[10:09:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[10:09:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[10:09:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[10:09:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[10:09:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[10:09:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[10:09:20] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[10:09:20] [PASSED] VIC 96
[10:09:20] [PASSED] VIC 97
[10:09:20] [PASSED] VIC 101
[10:09:20] [PASSED] VIC 102
[10:09:20] [PASSED] VIC 106
[10:09:20] [PASSED] VIC 107
[10:09:20] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[10:09:20] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[10:09:20] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[10:09:20] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[10:09:20] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[10:09:20] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[10:09:20] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[10:09:20] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[10:09:20] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[10:09:20] [PASSED] Automatic
[10:09:20] [PASSED] Full
[10:09:20] [PASSED] Limited 16:235
[10:09:20] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[10:09:20] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[10:09:20] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[10:09:20] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[10:09:20] === drm_test_drm_hdmi_connector_get_output_format_name ====
[10:09:20] [PASSED] RGB
[10:09:20] [PASSED] YUV 4:2:0
[10:09:20] [PASSED] YUV 4:2:2
[10:09:20] [PASSED] YUV 4:4:4
[10:09:20] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[10:09:20] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[10:09:20] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[10:09:20] ============= drm_damage_helper (21 subtests) ==============
[10:09:20] [PASSED] drm_test_damage_iter_no_damage
[10:09:20] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[10:09:20] [PASSED] drm_test_damage_iter_no_damage_src_moved
[10:09:20] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[10:09:20] [PASSED] drm_test_damage_iter_no_damage_not_visible
[10:09:20] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[10:09:20] [PASSED] drm_test_damage_iter_no_damage_no_fb
[10:09:20] [PASSED] drm_test_damage_iter_simple_damage
[10:09:20] [PASSED] drm_test_damage_iter_single_damage
[10:09:20] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[10:09:20] [PASSED] drm_test_damage_iter_single_damage_outside_src
[10:09:20] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[10:09:20] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[10:09:20] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[10:09:20] [PASSED] drm_test_damage_iter_single_damage_src_moved
[10:09:20] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[10:09:20] [PASSED] drm_test_damage_iter_damage
[10:09:20] [PASSED] drm_test_damage_iter_damage_one_intersect
[10:09:20] [PASSED] drm_test_damage_iter_damage_one_outside
[10:09:20] [PASSED] drm_test_damage_iter_damage_src_moved
[10:09:20] [PASSED] drm_test_damage_iter_damage_not_visible
[10:09:20] ================ [PASSED] drm_damage_helper ================
[10:09:20] ============== drm_dp_mst_helper (3 subtests) ==============
[10:09:20] ============== drm_test_dp_mst_calc_pbn_mode ==============
[10:09:20] [PASSED] Clock 154000 BPP 30 DSC disabled
[10:09:20] [PASSED] Clock 234000 BPP 30 DSC disabled
[10:09:20] [PASSED] Clock 297000 BPP 24 DSC disabled
[10:09:20] [PASSED] Clock 332880 BPP 24 DSC enabled
[10:09:20] [PASSED] Clock 324540 BPP 24 DSC enabled
[10:09:20] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[10:09:20] ============== drm_test_dp_mst_calc_pbn_div ===============
[10:09:20] [PASSED] Link rate 2000000 lane count 4
[10:09:20] [PASSED] Link rate 2000000 lane count 2
[10:09:20] [PASSED] Link rate 2000000 lane count 1
[10:09:20] [PASSED] Link rate 1350000 lane count 4
[10:09:20] [PASSED] Link rate 1350000 lane count 2
[10:09:20] [PASSED] Link rate 1350000 lane count 1
[10:09:20] [PASSED] Link rate 1000000 lane count 4
[10:09:20] [PASSED] Link rate 1000000 lane count 2
[10:09:20] [PASSED] Link rate 1000000 lane count 1
[10:09:20] [PASSED] Link rate 810000 lane count 4
[10:09:20] [PASSED] Link rate 810000 lane count 2
[10:09:20] [PASSED] Link rate 810000 lane count 1
[10:09:20] [PASSED] Link rate 540000 lane count 4
[10:09:20] [PASSED] Link rate 540000 lane count 2
[10:09:20] [PASSED] Link rate 540000 lane count 1
[10:09:20] [PASSED] Link rate 270000 lane count 4
[10:09:20] [PASSED] Link rate 270000 lane count 2
[10:09:20] [PASSED] Link rate 270000 lane count 1
[10:09:20] [PASSED] Link rate 162000 lane count 4
[10:09:20] [PASSED] Link rate 162000 lane count 2
[10:09:20] [PASSED] Link rate 162000 lane count 1
[10:09:20] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[10:09:20] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[10:09:20] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[10:09:20] [PASSED] DP_POWER_UP_PHY with port number
[10:09:20] [PASSED] DP_POWER_DOWN_PHY with port number
[10:09:20] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[10:09:20] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[10:09:20] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[10:09:20] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[10:09:20] [PASSED] DP_QUERY_PAYLOAD with port number
[10:09:20] [PASSED] DP_QUERY_PAYLOAD with VCPI
[10:09:20] [PASSED] DP_REMOTE_DPCD_READ with port number
[10:09:20] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[10:09:20] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[10:09:20] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[10:09:20] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[10:09:20] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[10:09:20] [PASSED] DP_REMOTE_I2C_READ with port number
[10:09:20] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[10:09:20] [PASSED] DP_REMOTE_I2C_READ with transactions array
[10:09:20] [PASSED] DP_REMOTE_I2C_WRITE with port number
[10:09:20] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[10:09:20] [PASSED] DP_REMOTE_I2C_WRITE with data array
[10:09:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[10:09:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[10:09:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[10:09:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[10:09:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[10:09:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[10:09:20] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[10:09:20] ================ [PASSED] drm_dp_mst_helper ================
[10:09:20] ================== drm_exec (7 subtests) ===================
[10:09:20] [PASSED] sanitycheck
[10:09:20] [PASSED] test_lock
[10:09:20] [PASSED] test_lock_unlock
[10:09:20] [PASSED] test_duplicates
[10:09:20] [PASSED] test_prepare
[10:09:20] [PASSED] test_prepare_array
[10:09:20] [PASSED] test_multiple_loops
[10:09:20] ==================== [PASSED] drm_exec =====================
[10:09:20] =========== drm_format_helper_test (17 subtests) ===========
[10:09:20] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[10:09:20] [PASSED] single_pixel_source_buffer
[10:09:20] [PASSED] single_pixel_clip_rectangle
[10:09:20] [PASSED] well_known_colors
[10:09:20] [PASSED] destination_pitch
[10:09:20] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[10:09:20] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[10:09:20] [PASSED] single_pixel_source_buffer
[10:09:20] [PASSED] single_pixel_clip_rectangle
[10:09:20] [PASSED] well_known_colors
[10:09:20] [PASSED] destination_pitch
[10:09:20] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[10:09:20] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[10:09:20] [PASSED] single_pixel_source_buffer
[10:09:20] [PASSED] single_pixel_clip_rectangle
[10:09:20] [PASSED] well_known_colors
[10:09:20] [PASSED] destination_pitch
[10:09:20] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[10:09:20] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[10:09:20] [PASSED] single_pixel_source_buffer
[10:09:20] [PASSED] single_pixel_clip_rectangle
[10:09:20] [PASSED] well_known_colors
[10:09:20] [PASSED] destination_pitch
[10:09:20] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[10:09:20] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[10:09:20] [PASSED] single_pixel_source_buffer
[10:09:20] [PASSED] single_pixel_clip_rectangle
[10:09:20] [PASSED] well_known_colors
[10:09:20] [PASSED] destination_pitch
[10:09:20] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[10:09:20] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[10:09:20] [PASSED] single_pixel_source_buffer
[10:09:20] [PASSED] single_pixel_clip_rectangle
[10:09:20] [PASSED] well_known_colors
[10:09:20] [PASSED] destination_pitch
[10:09:20] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[10:09:20] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[10:09:20] [PASSED] single_pixel_source_buffer
[10:09:20] [PASSED] single_pixel_clip_rectangle
[10:09:20] [PASSED] well_known_colors
[10:09:20] [PASSED] destination_pitch
[10:09:20] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[10:09:20] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[10:09:20] [PASSED] single_pixel_source_buffer
[10:09:20] [PASSED] single_pixel_clip_rectangle
[10:09:20] [PASSED] well_known_colors
[10:09:20] [PASSED] destination_pitch
[10:09:20] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[10:09:20] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[10:09:20] [PASSED] single_pixel_source_buffer
[10:09:20] [PASSED] single_pixel_clip_rectangle
[10:09:20] [PASSED] well_known_colors
[10:09:20] [PASSED] destination_pitch
[10:09:20] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[10:09:20] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[10:09:20] [PASSED] single_pixel_source_buffer
[10:09:20] [PASSED] single_pixel_clip_rectangle
[10:09:20] [PASSED] well_known_colors
[10:09:20] [PASSED] destination_pitch
[10:09:20] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[10:09:20] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[10:09:20] [PASSED] single_pixel_source_buffer
[10:09:20] [PASSED] single_pixel_clip_rectangle
[10:09:20] [PASSED] well_known_colors
[10:09:20] [PASSED] destination_pitch
[10:09:20] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[10:09:20] ============== drm_test_fb_xrgb8888_to_mono ===============
[10:09:20] [PASSED] single_pixel_source_buffer
[10:09:20] [PASSED] single_pixel_clip_rectangle
[10:09:20] [PASSED] well_known_colors
[10:09:20] [PASSED] destination_pitch
[10:09:20] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[10:09:20] ==================== drm_test_fb_swab =====================
[10:09:20] [PASSED] single_pixel_source_buffer
[10:09:20] [PASSED] single_pixel_clip_rectangle
[10:09:20] [PASSED] well_known_colors
[10:09:20] [PASSED] destination_pitch
[10:09:20] ================ [PASSED] drm_test_fb_swab =================
[10:09:20] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[10:09:20] [PASSED] single_pixel_source_buffer
[10:09:20] [PASSED] single_pixel_clip_rectangle
[10:09:20] [PASSED] well_known_colors
[10:09:20] [PASSED] destination_pitch
[10:09:20] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[10:09:20] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[10:09:20] [PASSED] single_pixel_source_buffer
[10:09:20] [PASSED] single_pixel_clip_rectangle
[10:09:20] [PASSED] well_known_colors
[10:09:20] [PASSED] destination_pitch
[10:09:20] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[10:09:20] ================= drm_test_fb_clip_offset =================
[10:09:20] [PASSED] pass through
[10:09:20] [PASSED] horizontal offset
[10:09:20] [PASSED] vertical offset
[10:09:20] [PASSED] horizontal and vertical offset
[10:09:20] [PASSED] horizontal offset (custom pitch)
[10:09:20] [PASSED] vertical offset (custom pitch)
[10:09:20] [PASSED] horizontal and vertical offset (custom pitch)
[10:09:20] ============= [PASSED] drm_test_fb_clip_offset =============
[10:09:20] =================== drm_test_fb_memcpy ====================
[10:09:20] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[10:09:20] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[10:09:20] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[10:09:20] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[10:09:20] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[10:09:20] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[10:09:20] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[10:09:20] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[10:09:20] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[10:09:20] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[10:09:20] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[10:09:20] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[10:09:20] =============== [PASSED] drm_test_fb_memcpy ================
[10:09:20] ============= [PASSED] drm_format_helper_test ==============
[10:09:20] ================= drm_format (18 subtests) =================
[10:09:20] [PASSED] drm_test_format_block_width_invalid
[10:09:20] [PASSED] drm_test_format_block_width_one_plane
[10:09:20] [PASSED] drm_test_format_block_width_two_plane
[10:09:20] [PASSED] drm_test_format_block_width_three_plane
[10:09:20] [PASSED] drm_test_format_block_width_tiled
[10:09:20] [PASSED] drm_test_format_block_height_invalid
[10:09:20] [PASSED] drm_test_format_block_height_one_plane
[10:09:20] [PASSED] drm_test_format_block_height_two_plane
[10:09:20] [PASSED] drm_test_format_block_height_three_plane
[10:09:20] [PASSED] drm_test_format_block_height_tiled
[10:09:20] [PASSED] drm_test_format_min_pitch_invalid
[10:09:20] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[10:09:20] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[10:09:20] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[10:09:20] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[10:09:20] [PASSED] drm_test_format_min_pitch_two_plane
[10:09:20] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[10:09:20] [PASSED] drm_test_format_min_pitch_tiled
[10:09:20] =================== [PASSED] drm_format ====================
[10:09:20] ============== drm_framebuffer (10 subtests) ===============
[10:09:20] ========== drm_test_framebuffer_check_src_coords ==========
[10:09:20] [PASSED] Success: source fits into fb
[10:09:20] [PASSED] Fail: overflowing fb with x-axis coordinate
[10:09:20] [PASSED] Fail: overflowing fb with y-axis coordinate
[10:09:20] [PASSED] Fail: overflowing fb with source width
[10:09:20] [PASSED] Fail: overflowing fb with source height
[10:09:20] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[10:09:20] [PASSED] drm_test_framebuffer_cleanup
[10:09:20] =============== drm_test_framebuffer_create ===============
[10:09:20] [PASSED] ABGR8888 normal sizes
[10:09:20] [PASSED] ABGR8888 max sizes
[10:09:20] [PASSED] ABGR8888 pitch greater than min required
[10:09:20] [PASSED] ABGR8888 pitch less than min required
[10:09:20] [PASSED] ABGR8888 Invalid width
[10:09:20] [PASSED] ABGR8888 Invalid buffer handle
[10:09:20] [PASSED] No pixel format
[10:09:20] [PASSED] ABGR8888 Width 0
[10:09:20] [PASSED] ABGR8888 Height 0
[10:09:20] [PASSED] ABGR8888 Out of bound height * pitch combination
[10:09:20] [PASSED] ABGR8888 Large buffer offset
[10:09:20] [PASSED] ABGR8888 Buffer offset for inexistent plane
[10:09:20] [PASSED] ABGR8888 Invalid flag
[10:09:20] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[10:09:20] [PASSED] ABGR8888 Valid buffer modifier
[10:09:20] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[10:09:20] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[10:09:20] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[10:09:20] [PASSED] NV12 Normal sizes
[10:09:20] [PASSED] NV12 Max sizes
[10:09:20] [PASSED] NV12 Invalid pitch
[10:09:20] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[10:09:20] [PASSED] NV12 different modifier per-plane
[10:09:20] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[10:09:20] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[10:09:20] [PASSED] NV12 Modifier for inexistent plane
[10:09:20] [PASSED] NV12 Handle for inexistent plane
[10:09:20] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[10:09:20] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[10:09:20] [PASSED] YVU420 Normal sizes
[10:09:20] [PASSED] YVU420 Max sizes
[10:09:20] [PASSED] YVU420 Invalid pitch
[10:09:20] [PASSED] YVU420 Different pitches
[10:09:20] [PASSED] YVU420 Different buffer offsets/pitches
[10:09:20] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[10:09:20] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[10:09:20] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[10:09:20] [PASSED] YVU420 Valid modifier
[10:09:20] [PASSED] YVU420 Different modifiers per plane
[10:09:20] [PASSED] YVU420 Modifier for inexistent plane
[10:09:20] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[10:09:20] [PASSED] X0L2 Normal sizes
[10:09:20] [PASSED] X0L2 Max sizes
[10:09:20] [PASSED] X0L2 Invalid pitch
[10:09:20] [PASSED] X0L2 Pitch greater than minimum required
[10:09:20] [PASSED] X0L2 Handle for inexistent plane
[10:09:20] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[10:09:20] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[10:09:20] [PASSED] X0L2 Valid modifier
[10:09:20] [PASSED] X0L2 Modifier for inexistent plane
[10:09:20] =========== [PASSED] drm_test_framebuffer_create ===========
[10:09:20] [PASSED] drm_test_framebuffer_free
[10:09:20] [PASSED] drm_test_framebuffer_init
[10:09:20] [PASSED] drm_test_framebuffer_init_bad_format
[10:09:20] [PASSED] drm_test_framebuffer_init_dev_mismatch
[10:09:20] [PASSED] drm_test_framebuffer_lookup
[10:09:20] [PASSED] drm_test_framebuffer_lookup_inexistent
[10:09:20] [PASSED] drm_test_framebuffer_modifiers_not_supported
[10:09:20] ================= [PASSED] drm_framebuffer =================
[10:09:20] ================ drm_gem_shmem (8 subtests) ================
[10:09:20] [PASSED] drm_gem_shmem_test_obj_create
[10:09:20] [PASSED] drm_gem_shmem_test_obj_create_private
[10:09:20] [PASSED] drm_gem_shmem_test_pin_pages
[10:09:20] [PASSED] drm_gem_shmem_test_vmap
[10:09:20] [PASSED] drm_gem_shmem_test_get_sg_table
[10:09:20] [PASSED] drm_gem_shmem_test_get_pages_sgt
[10:09:20] [PASSED] drm_gem_shmem_test_madvise
[10:09:20] [PASSED] drm_gem_shmem_test_purge
[10:09:20] ================== [PASSED] drm_gem_shmem ==================
[10:09:20] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[10:09:20] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[10:09:20] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[10:09:20] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[10:09:20] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[10:09:20] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[10:09:20] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[10:09:20] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[10:09:20] [PASSED] Automatic
[10:09:20] [PASSED] Full
[10:09:20] [PASSED] Limited 16:235
[10:09:20] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[10:09:20] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[10:09:20] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[10:09:20] [PASSED] drm_test_check_disable_connector
[10:09:20] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[10:09:20] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[10:09:20] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[10:09:20] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[10:09:20] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[10:09:20] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[10:09:20] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[10:09:20] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[10:09:20] [PASSED] drm_test_check_output_bpc_dvi
[10:09:20] [PASSED] drm_test_check_output_bpc_format_vic_1
[10:09:20] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[10:09:20] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[10:09:20] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[10:09:20] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[10:09:20] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[10:09:20] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[10:09:20] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[10:09:20] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[10:09:20] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[10:09:20] [PASSED] drm_test_check_broadcast_rgb_value
[10:09:20] [PASSED] drm_test_check_bpc_8_value
[10:09:20] [PASSED] drm_test_check_bpc_10_value
[10:09:20] [PASSED] drm_test_check_bpc_12_value
[10:09:20] [PASSED] drm_test_check_format_value
[10:09:20] [PASSED] drm_test_check_tmds_char_value
[10:09:20] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[10:09:20] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[10:09:20] [PASSED] drm_test_check_mode_valid
[10:09:20] [PASSED] drm_test_check_mode_valid_reject
[10:09:20] [PASSED] drm_test_check_mode_valid_reject_rate
[10:09:20] [PASSED] drm_test_check_mode_valid_reject_max_clock
[10:09:20] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[10:09:20] ================= drm_managed (2 subtests) =================
[10:09:20] [PASSED] drm_test_managed_release_action
[10:09:20] [PASSED] drm_test_managed_run_action
[10:09:20] =================== [PASSED] drm_managed ===================
[10:09:20] =================== drm_mm (6 subtests) ====================
[10:09:20] [PASSED] drm_test_mm_init
[10:09:20] [PASSED] drm_test_mm_debug
[10:09:20] [PASSED] drm_test_mm_align32
[10:09:20] [PASSED] drm_test_mm_align64
[10:09:20] [PASSED] drm_test_mm_lowest
[10:09:20] [PASSED] drm_test_mm_highest
[10:09:20] ===================== [PASSED] drm_mm ======================
[10:09:20] ============= drm_modes_analog_tv (5 subtests) =============
[10:09:20] [PASSED] drm_test_modes_analog_tv_mono_576i
[10:09:20] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[10:09:20] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[10:09:20] [PASSED] drm_test_modes_analog_tv_pal_576i
[10:09:20] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[10:09:20] =============== [PASSED] drm_modes_analog_tv ===============
[10:09:20] ============== drm_plane_helper (2 subtests) ===============
[10:09:20] =============== drm_test_check_plane_state ================
[10:09:20] [PASSED] clipping_simple
[10:09:20] [PASSED] clipping_rotate_reflect
[10:09:20] [PASSED] positioning_simple
[10:09:20] [PASSED] upscaling
[10:09:20] [PASSED] downscaling
[10:09:20] [PASSED] rounding1
[10:09:20] [PASSED] rounding2
[10:09:20] [PASSED] rounding3
[10:09:20] [PASSED] rounding4
[10:09:20] =========== [PASSED] drm_test_check_plane_state ============
[10:09:20] =========== drm_test_check_invalid_plane_state ============
[10:09:20] [PASSED] positioning_invalid
[10:09:20] [PASSED] upscaling_invalid
[10:09:20] [PASSED] downscaling_invalid
[10:09:20] ======= [PASSED] drm_test_check_invalid_plane_state ========
[10:09:20] ================ [PASSED] drm_plane_helper =================
[10:09:20] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[10:09:20] ====== drm_test_connector_helper_tv_get_modes_check =======
[10:09:20] [PASSED] None
[10:09:20] [PASSED] PAL
[10:09:20] [PASSED] NTSC
[10:09:20] [PASSED] Both, NTSC Default
[10:09:20] [PASSED] Both, PAL Default
[10:09:20] [PASSED] Both, NTSC Default, with PAL on command-line
[10:09:20] [PASSED] Both, PAL Default, with NTSC on command-line
[10:09:20] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[10:09:20] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[10:09:20] ================== drm_rect (9 subtests) ===================
[10:09:20] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[10:09:20] [PASSED] drm_test_rect_clip_scaled_not_clipped
[10:09:20] [PASSED] drm_test_rect_clip_scaled_clipped
[10:09:20] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[10:09:20] ================= drm_test_rect_intersect =================
[10:09:20] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[10:09:20] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[10:09:20] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[10:09:20] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[10:09:20] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[10:09:20] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[10:09:20] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[10:09:20] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[10:09:20] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[10:09:20] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[10:09:20] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[10:09:20] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[10:09:20] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[10:09:20] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[10:09:20] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[10:09:20] ============= [PASSED] drm_test_rect_intersect =============
[10:09:20] ================ drm_test_rect_calc_hscale ================
[10:09:20] [PASSED] normal use
[10:09:20] [PASSED] out of max range
[10:09:20] [PASSED] out of min range
[10:09:20] [PASSED] zero dst
[10:09:20] [PASSED] negative src
[10:09:20] [PASSED] negative dst
[10:09:20] ============ [PASSED] drm_test_rect_calc_hscale ============
[10:09:20] ================ drm_test_rect_calc_vscale ================
[10:09:20] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[10:09:20] [PASSED] out of max range
[10:09:20] [PASSED] out of min range
[10:09:20] [PASSED] zero dst
[10:09:20] [PASSED] negative src
[10:09:20] [PASSED] negative dst
[10:09:20] ============ [PASSED] drm_test_rect_calc_vscale ============
[10:09:20] ================== drm_test_rect_rotate ===================
[10:09:20] [PASSED] reflect-x
[10:09:20] [PASSED] reflect-y
[10:09:20] [PASSED] rotate-0
[10:09:20] [PASSED] rotate-90
[10:09:20] [PASSED] rotate-180
[10:09:20] [PASSED] rotate-270
[10:09:20] ============== [PASSED] drm_test_rect_rotate ===============
[10:09:20] ================ drm_test_rect_rotate_inv =================
[10:09:20] [PASSED] reflect-x
[10:09:20] [PASSED] reflect-y
[10:09:20] [PASSED] rotate-0
[10:09:20] [PASSED] rotate-90
[10:09:20] [PASSED] rotate-180
[10:09:20] [PASSED] rotate-270
[10:09:20] ============ [PASSED] drm_test_rect_rotate_inv =============
[10:09:20] ==================== [PASSED] drm_rect =====================
[10:09:20] ============ drm_sysfb_modeset_test (1 subtest) ============
[10:09:20] ============ drm_test_sysfb_build_fourcc_list =============
[10:09:20] [PASSED] no native formats
[10:09:20] [PASSED] XRGB8888 as native format
[10:09:20] [PASSED] remove duplicates
[10:09:20] [PASSED] convert alpha formats
[10:09:20] [PASSED] random formats
[10:09:20] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[10:09:20] ============= [PASSED] drm_sysfb_modeset_test ==============
[10:09:20] ================== drm_fixp (2 subtests) ===================
[10:09:20] [PASSED] drm_test_int2fixp
[10:09:20] [PASSED] drm_test_sm2fixp
[10:09:20] ==================== [PASSED] drm_fixp =====================
[10:09:20] ============================================================
[10:09:20] Testing complete. Ran 624 tests: passed: 624
[10:09:20] Elapsed time: 32.655s total, 1.647s configuring, 30.541s building, 0.408s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[10:09:20] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:09:22] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[10:09:31] Starting KUnit Kernel (1/1)...
[10:09:31] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:09:31] ================= ttm_device (5 subtests) ==================
[10:09:31] [PASSED] ttm_device_init_basic
[10:09:31] [PASSED] ttm_device_init_multiple
[10:09:31] [PASSED] ttm_device_fini_basic
[10:09:31] [PASSED] ttm_device_init_no_vma_man
[10:09:31] ================== ttm_device_init_pools ==================
[10:09:31] [PASSED] No DMA allocations, no DMA32 required
[10:09:31] [PASSED] DMA allocations, DMA32 required
[10:09:31] [PASSED] No DMA allocations, DMA32 required
[10:09:31] [PASSED] DMA allocations, no DMA32 required
[10:09:31] ============== [PASSED] ttm_device_init_pools ==============
[10:09:31] =================== [PASSED] ttm_device ====================
[10:09:31] ================== ttm_pool (8 subtests) ===================
[10:09:31] ================== ttm_pool_alloc_basic ===================
[10:09:31] [PASSED] One page
[10:09:31] [PASSED] More than one page
[10:09:31] [PASSED] Above the allocation limit
[10:09:31] [PASSED] One page, with coherent DMA mappings enabled
[10:09:31] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[10:09:31] ============== [PASSED] ttm_pool_alloc_basic ===============
[10:09:31] ============== ttm_pool_alloc_basic_dma_addr ==============
[10:09:31] [PASSED] One page
[10:09:31] [PASSED] More than one page
[10:09:31] [PASSED] Above the allocation limit
[10:09:31] [PASSED] One page, with coherent DMA mappings enabled
[10:09:31] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[10:09:31] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[10:09:31] [PASSED] ttm_pool_alloc_order_caching_match
[10:09:31] [PASSED] ttm_pool_alloc_caching_mismatch
[10:09:31] [PASSED] ttm_pool_alloc_order_mismatch
[10:09:31] [PASSED] ttm_pool_free_dma_alloc
[10:09:31] [PASSED] ttm_pool_free_no_dma_alloc
[10:09:31] [PASSED] ttm_pool_fini_basic
[10:09:31] ==================== [PASSED] ttm_pool =====================
[10:09:31] ================ ttm_resource (8 subtests) =================
[10:09:31] ================= ttm_resource_init_basic =================
[10:09:31] [PASSED] Init resource in TTM_PL_SYSTEM
[10:09:31] [PASSED] Init resource in TTM_PL_VRAM
[10:09:31] [PASSED] Init resource in a private placement
[10:09:31] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[10:09:31] ============= [PASSED] ttm_resource_init_basic =============
[10:09:31] [PASSED] ttm_resource_init_pinned
[10:09:31] [PASSED] ttm_resource_fini_basic
[10:09:31] [PASSED] ttm_resource_manager_init_basic
[10:09:31] [PASSED] ttm_resource_manager_usage_basic
[10:09:31] [PASSED] ttm_resource_manager_set_used_basic
[10:09:31] [PASSED] ttm_sys_man_alloc_basic
[10:09:31] [PASSED] ttm_sys_man_free_basic
[10:09:31] ================== [PASSED] ttm_resource ===================
[10:09:31] =================== ttm_tt (15 subtests) ===================
[10:09:31] ==================== ttm_tt_init_basic ====================
[10:09:31] [PASSED] Page-aligned size
[10:09:31] [PASSED] Extra pages requested
[10:09:31] ================ [PASSED] ttm_tt_init_basic ================
[10:09:31] [PASSED] ttm_tt_init_misaligned
[10:09:31] [PASSED] ttm_tt_fini_basic
[10:09:31] [PASSED] ttm_tt_fini_sg
[10:09:31] [PASSED] ttm_tt_fini_shmem
[10:09:31] [PASSED] ttm_tt_create_basic
[10:09:31] [PASSED] ttm_tt_create_invalid_bo_type
[10:09:31] [PASSED] ttm_tt_create_ttm_exists
[10:09:31] [PASSED] ttm_tt_create_failed
[10:09:31] [PASSED] ttm_tt_destroy_basic
[10:09:31] [PASSED] ttm_tt_populate_null_ttm
[10:09:31] [PASSED] ttm_tt_populate_populated_ttm
[10:09:31] [PASSED] ttm_tt_unpopulate_basic
[10:09:31] [PASSED] ttm_tt_unpopulate_empty_ttm
[10:09:31] [PASSED] ttm_tt_swapin_basic
[10:09:31] ===================== [PASSED] ttm_tt ======================
[10:09:31] =================== ttm_bo (14 subtests) ===================
[10:09:31] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[10:09:31] [PASSED] Cannot be interrupted and sleeps
[10:09:31] [PASSED] Cannot be interrupted, locks straight away
[10:09:31] [PASSED] Can be interrupted, sleeps
[10:09:31] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[10:09:31] [PASSED] ttm_bo_reserve_locked_no_sleep
[10:09:31] [PASSED] ttm_bo_reserve_no_wait_ticket
[10:09:31] [PASSED] ttm_bo_reserve_double_resv
[10:09:31] [PASSED] ttm_bo_reserve_interrupted
[10:09:31] [PASSED] ttm_bo_reserve_deadlock
[10:09:31] [PASSED] ttm_bo_unreserve_basic
[10:09:31] [PASSED] ttm_bo_unreserve_pinned
[10:09:31] [PASSED] ttm_bo_unreserve_bulk
[10:09:31] [PASSED] ttm_bo_fini_basic
[10:09:31] [PASSED] ttm_bo_fini_shared_resv
[10:09:31] [PASSED] ttm_bo_pin_basic
[10:09:31] [PASSED] ttm_bo_pin_unpin_resource
[10:09:31] [PASSED] ttm_bo_multiple_pin_one_unpin
[10:09:31] ===================== [PASSED] ttm_bo ======================
[10:09:31] ============== ttm_bo_validate (21 subtests) ===============
[10:09:31] ============== ttm_bo_init_reserved_sys_man ===============
[10:09:31] [PASSED] Buffer object for userspace
[10:09:31] [PASSED] Kernel buffer object
[10:09:31] [PASSED] Shared buffer object
[10:09:31] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[10:09:31] ============== ttm_bo_init_reserved_mock_man ==============
[10:09:31] [PASSED] Buffer object for userspace
[10:09:31] [PASSED] Kernel buffer object
[10:09:31] [PASSED] Shared buffer object
[10:09:31] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[10:09:31] [PASSED] ttm_bo_init_reserved_resv
[10:09:31] ================== ttm_bo_validate_basic ==================
[10:09:31] [PASSED] Buffer object for userspace
[10:09:31] [PASSED] Kernel buffer object
[10:09:31] [PASSED] Shared buffer object
[10:09:31] ============== [PASSED] ttm_bo_validate_basic ==============
[10:09:31] [PASSED] ttm_bo_validate_invalid_placement
[10:09:31] ============= ttm_bo_validate_same_placement ==============
[10:09:31] [PASSED] System manager
[10:09:31] [PASSED] VRAM manager
[10:09:31] ========= [PASSED] ttm_bo_validate_same_placement ==========
[10:09:31] [PASSED] ttm_bo_validate_failed_alloc
[10:09:31] [PASSED] ttm_bo_validate_pinned
[10:09:31] [PASSED] ttm_bo_validate_busy_placement
[10:09:31] ================ ttm_bo_validate_multihop =================
[10:09:31] [PASSED] Buffer object for userspace
[10:09:31] [PASSED] Kernel buffer object
[10:09:31] [PASSED] Shared buffer object
[10:09:31] ============ [PASSED] ttm_bo_validate_multihop =============
[10:09:31] ========== ttm_bo_validate_no_placement_signaled ==========
[10:09:31] [PASSED] Buffer object in system domain, no page vector
[10:09:31] [PASSED] Buffer object in system domain with an existing page vector
[10:09:31] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[10:09:31] ======== ttm_bo_validate_no_placement_not_signaled ========
[10:09:31] [PASSED] Buffer object for userspace
[10:09:31] [PASSED] Kernel buffer object
[10:09:31] [PASSED] Shared buffer object
[10:09:31] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[10:09:31] [PASSED] ttm_bo_validate_move_fence_signaled
[10:09:31] ========= ttm_bo_validate_move_fence_not_signaled =========
[10:09:31] [PASSED] Waits for GPU
[10:09:31] [PASSED] Tries to lock straight away
[10:09:31] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[10:09:31] [PASSED] ttm_bo_validate_happy_evict
[10:09:31] [PASSED] ttm_bo_validate_all_pinned_evict
[10:09:31] [PASSED] ttm_bo_validate_allowed_only_evict
[10:09:31] [PASSED] ttm_bo_validate_deleted_evict
[10:09:31] [PASSED] ttm_bo_validate_busy_domain_evict
[10:09:31] [PASSED] ttm_bo_validate_evict_gutting
[10:09:31] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[10:09:31] ================= [PASSED] ttm_bo_validate =================
[10:09:31] ============================================================
[10:09:31] Testing complete. Ran 101 tests: passed: 101
[10:09:31] Elapsed time: 11.144s total, 1.638s configuring, 9.290s building, 0.185s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 17+ messages in thread* ✓ Xe.CI.BAT: success for Introduce Xe Correctable Error Handling
2026-01-16 9:33 [PATCH v1 0/4] Introduce Xe Correctable Error Handling Raag Jadav
` (5 preceding siblings ...)
2026-01-16 10:09 ` ✓ CI.KUnit: success " Patchwork
@ 2026-01-16 11:02 ` Patchwork
2026-01-16 14:25 ` ✓ Xe.CI.Full: " Patchwork
7 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2026-01-16 11:02 UTC (permalink / raw)
To: Raag Jadav; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 1328 bytes --]
== Series Details ==
Series: Introduce Xe Correctable Error Handling
URL : https://patchwork.freedesktop.org/series/160184/
State : success
== Summary ==
CI Bug Log - changes from xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c_BAT -> xe-pw-160184v1_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (10 -> 11)
------------------------------
Additional (1): bat-bmg-3
Known issues
------------
Here are the changes found in xe-pw-160184v1_BAT that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@xe_peer2peer@read@read-gpua-vram01-gpub-system-p2p:
- bat-bmg-3: NOTRUN -> [SKIP][1] ([Intel XE#6566]) +3 other tests skip
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/bat-bmg-3/igt@xe_peer2peer@read@read-gpua-vram01-gpub-system-p2p.html
[Intel XE#6566]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6566
Build changes
-------------
* Linux: xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c -> xe-pw-160184v1
IGT_8704: 8704
xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c: 2c3e2b14be8eda5fb69764bb077663809afa183c
xe-pw-160184v1: 160184v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/index.html
[-- Attachment #2: Type: text/html, Size: 1892 bytes --]
^ permalink raw reply [flat|nested] 17+ messages in thread* ✓ Xe.CI.Full: success for Introduce Xe Correctable Error Handling
2026-01-16 9:33 [PATCH v1 0/4] Introduce Xe Correctable Error Handling Raag Jadav
` (6 preceding siblings ...)
2026-01-16 11:02 ` ✓ Xe.CI.BAT: " Patchwork
@ 2026-01-16 14:25 ` Patchwork
7 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2026-01-16 14:25 UTC (permalink / raw)
To: Raag Jadav; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 38330 bytes --]
== Series Details ==
Series: Introduce Xe Correctable Error Handling
URL : https://patchwork.freedesktop.org/series/160184/
State : success
== Summary ==
CI Bug Log - changes from xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c_FULL -> xe-pw-160184v1_FULL
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (2 -> 2)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in xe-pw-160184v1_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_atomic_transition@plane-all-modeset-transition:
- shard-lnl: NOTRUN -> [SKIP][1] ([Intel XE#3279])
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-lnl-7/igt@kms_atomic_transition@plane-all-modeset-transition.html
* igt@kms_big_fb@linear-8bpp-rotate-90:
- shard-bmg: NOTRUN -> [SKIP][2] ([Intel XE#2327]) +2 other tests skip
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-7/igt@kms_big_fb@linear-8bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-180:
- shard-lnl: NOTRUN -> [SKIP][3] ([Intel XE#1124]) +1 other test skip
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-lnl-7/igt@kms_big_fb@yf-tiled-16bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-270:
- shard-bmg: NOTRUN -> [SKIP][4] ([Intel XE#1124]) +1 other test skip
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-10/igt@kms_big_fb@yf-tiled-64bpp-rotate-270.html
* igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p:
- shard-lnl: NOTRUN -> [SKIP][5] ([Intel XE#2191])
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-lnl-2/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html
* igt@kms_bw@linear-tiling-1-displays-1920x1080p:
- shard-bmg: NOTRUN -> [SKIP][6] ([Intel XE#367])
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-10/igt@kms_bw@linear-tiling-1-displays-1920x1080p.html
* igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs:
- shard-lnl: NOTRUN -> [SKIP][7] ([Intel XE#2887]) +3 other tests skip
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-lnl-7/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs.html
* igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc:
- shard-bmg: NOTRUN -> [SKIP][8] ([Intel XE#2887]) +6 other tests skip
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-10/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc:
- shard-lnl: NOTRUN -> [SKIP][9] ([Intel XE#3432]) +1 other test skip
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-lnl-2/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc.html
* igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs:
- shard-bmg: NOTRUN -> [SKIP][10] ([Intel XE#3432])
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-10/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs.html
* igt@kms_chamelium_color@ctm-blue-to-red:
- shard-bmg: NOTRUN -> [SKIP][11] ([Intel XE#2325])
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-10/igt@kms_chamelium_color@ctm-blue-to-red.html
* igt@kms_chamelium_frames@hdmi-crc-fast:
- shard-lnl: NOTRUN -> [SKIP][12] ([Intel XE#373])
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-lnl-7/igt@kms_chamelium_frames@hdmi-crc-fast.html
* igt@kms_chamelium_hpd@dp-hpd-storm:
- shard-bmg: NOTRUN -> [SKIP][13] ([Intel XE#2252]) +1 other test skip
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-10/igt@kms_chamelium_hpd@dp-hpd-storm.html
* igt@kms_content_protection@dp-mst-type-0-hdcp14:
- shard-bmg: NOTRUN -> [SKIP][14] ([Intel XE#6974])
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-9/igt@kms_content_protection@dp-mst-type-0-hdcp14.html
* igt@kms_content_protection@dp-mst-type-1:
- shard-bmg: NOTRUN -> [SKIP][15] ([Intel XE#2390] / [Intel XE#6974])
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-7/igt@kms_content_protection@dp-mst-type-1.html
* igt@kms_content_protection@lic-type-1:
- shard-bmg: NOTRUN -> [SKIP][16] ([Intel XE#2341])
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-10/igt@kms_content_protection@lic-type-1.html
* igt@kms_cursor_crc@cursor-random-32x10:
- shard-lnl: NOTRUN -> [SKIP][17] ([Intel XE#1424])
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-lnl-7/igt@kms_cursor_crc@cursor-random-32x10.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x512:
- shard-bmg: NOTRUN -> [SKIP][18] ([Intel XE#2321])
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-9/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html
* igt@kms_cursor_crc@cursor-rapid-movement-64x21:
- shard-bmg: NOTRUN -> [SKIP][19] ([Intel XE#2320])
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-10/igt@kms_cursor_crc@cursor-rapid-movement-64x21.html
* igt@kms_cursor_edge_walk@256x256-top-edge@pipe-d-dp-2:
- shard-bmg: [PASS][20] -> [DMESG-FAIL][21] ([Intel XE#1727]) +1 other test dmesg-fail
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c/shard-bmg-10/igt@kms_cursor_edge_walk@256x256-top-edge@pipe-d-dp-2.html
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-3/igt@kms_cursor_edge_walk@256x256-top-edge@pipe-d-dp-2.html
* igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions:
- shard-lnl: NOTRUN -> [SKIP][22] ([Intel XE#309])
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-lnl-2/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions.html
* igt@kms_dirtyfb@psr-dirtyfb-ioctl:
- shard-bmg: NOTRUN -> [SKIP][23] ([Intel XE#1508])
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-7/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html
* igt@kms_dsc@dsc-fractional-bpp:
- shard-lnl: NOTRUN -> [SKIP][24] ([Intel XE#2244])
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-lnl-2/igt@kms_dsc@dsc-fractional-bpp.html
* igt@kms_fbcon_fbt@psr:
- shard-bmg: NOTRUN -> [SKIP][25] ([Intel XE#776])
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-10/igt@kms_fbcon_fbt@psr.html
* igt@kms_feature_discovery@chamelium:
- shard-bmg: NOTRUN -> [SKIP][26] ([Intel XE#2372])
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-10/igt@kms_feature_discovery@chamelium.html
* igt@kms_flip@2x-flip-vs-wf_vblank:
- shard-lnl: NOTRUN -> [SKIP][27] ([Intel XE#1421])
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-lnl-2/igt@kms_flip@2x-flip-vs-wf_vblank.html
* igt@kms_flip@2x-wf_vblank-ts-check:
- shard-bmg: [PASS][28] -> [FAIL][29] ([Intel XE#3098]) +1 other test fail
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c/shard-bmg-2/igt@kms_flip@2x-wf_vblank-ts-check.html
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-1/igt@kms_flip@2x-wf_vblank-ts-check.html
* igt@kms_flip@flip-vs-expired-vblank@b-edp1:
- shard-lnl: [PASS][30] -> [FAIL][31] ([Intel XE#301]) +2 other tests fail
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-yuv-linear-to-32bpp-yuv-linear-reflect-x:
- shard-bmg: NOTRUN -> [SKIP][32] ([Intel XE#7064] / [Intel XE#7081])
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-7/igt@kms_flip_scaled_crc@flip-32bpp-yuv-linear-to-32bpp-yuv-linear-reflect-x.html
* igt@kms_flip_scaled_crc@flip-32bpp-yuv-linear-to-32bpp-yuv-linear-reflect-x@pipe-a-valid-mode:
- shard-bmg: NOTRUN -> [SKIP][33] ([Intel XE#7064])
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-7/igt@kms_flip_scaled_crc@flip-32bpp-yuv-linear-to-32bpp-yuv-linear-reflect-x@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling:
- shard-lnl: NOTRUN -> [SKIP][34] ([Intel XE#1397] / [Intel XE#1745])
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-lnl-7/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling@pipe-a-default-mode:
- shard-lnl: NOTRUN -> [SKIP][35] ([Intel XE#1397])
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-lnl-7/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling:
- shard-bmg: NOTRUN -> [SKIP][36] ([Intel XE#2293] / [Intel XE#2380]) +1 other test skip
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-10/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode:
- shard-bmg: NOTRUN -> [SKIP][37] ([Intel XE#2293]) +1 other test skip
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-10/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@drrs-modesetfrombusy:
- shard-lnl: NOTRUN -> [SKIP][38] ([Intel XE#651]) +2 other tests skip
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-lnl-7/igt@kms_frontbuffer_tracking@drrs-modesetfrombusy.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc:
- shard-bmg: NOTRUN -> [SKIP][39] ([Intel XE#4141]) +3 other tests skip
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-9/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-render:
- shard-lnl: NOTRUN -> [SKIP][40] ([Intel XE#7061])
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-lnl-2/igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-argb161616f-draw-blt:
- shard-bmg: NOTRUN -> [SKIP][41] ([Intel XE#7061]) +2 other tests skip
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-10/igt@kms_frontbuffer_tracking@fbc-argb161616f-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-shrfb-plflip-blt:
- shard-bmg: NOTRUN -> [SKIP][42] ([Intel XE#2311]) +9 other tests skip
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-10/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-blt:
- shard-lnl: NOTRUN -> [SKIP][43] ([Intel XE#656]) +2 other tests skip
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-lnl-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-render:
- shard-bmg: NOTRUN -> [SKIP][44] ([Intel XE#2313]) +8 other tests skip
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-10/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-render.html
* igt@kms_hdr@static-swap:
- shard-lnl: NOTRUN -> [SKIP][45] ([Intel XE#1503])
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-lnl-2/igt@kms_hdr@static-swap.html
* igt@kms_panel_fitting@legacy:
- shard-bmg: NOTRUN -> [SKIP][46] ([Intel XE#2486])
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-7/igt@kms_panel_fitting@legacy.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling:
- shard-lnl: NOTRUN -> [SKIP][47] ([Intel XE#6886]) +3 other tests skip
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-lnl-7/igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling.html
* igt@kms_pm_dc@dc5-psr:
- shard-bmg: NOTRUN -> [SKIP][48] ([Intel XE#2392])
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-10/igt@kms_pm_dc@dc5-psr.html
* igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-fully-sf:
- shard-bmg: NOTRUN -> [SKIP][49] ([Intel XE#1406] / [Intel XE#1489]) +2 other tests skip
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-10/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf:
- shard-lnl: NOTRUN -> [SKIP][50] ([Intel XE#1406] / [Intel XE#2893] / [Intel XE#4608])
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-lnl-7/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf@pipe-b-edp-1:
- shard-lnl: NOTRUN -> [SKIP][51] ([Intel XE#1406] / [Intel XE#4608])
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-lnl-7/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf@pipe-b-edp-1.html
* igt@kms_psr2_sf@pr-overlay-plane-move-continuous-sf:
- shard-lnl: NOTRUN -> [SKIP][52] ([Intel XE#1406] / [Intel XE#2893])
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-lnl-2/igt@kms_psr2_sf@pr-overlay-plane-move-continuous-sf.html
* igt@kms_psr@fbc-pr-cursor-plane-move:
- shard-lnl: NOTRUN -> [SKIP][53] ([Intel XE#1406])
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-lnl-2/igt@kms_psr@fbc-pr-cursor-plane-move.html
* igt@kms_psr@pr-no-drrs:
- shard-bmg: NOTRUN -> [SKIP][54] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +3 other tests skip
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-7/igt@kms_psr@pr-no-drrs.html
* igt@kms_scaling_modes@scaling-mode-full:
- shard-bmg: NOTRUN -> [SKIP][55] ([Intel XE#2413])
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-9/igt@kms_scaling_modes@scaling-mode-full.html
* igt@kms_sharpness_filter@filter-dpms:
- shard-bmg: NOTRUN -> [SKIP][56] ([Intel XE#6503])
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-10/igt@kms_sharpness_filter@filter-dpms.html
* igt@testdisplay:
- shard-bmg: [PASS][57] -> [ABORT][58] ([Intel XE#6740] / [Intel XE#6976])
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c/shard-bmg-10/igt@testdisplay.html
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-9/igt@testdisplay.html
* igt@xe_compute@ccs-mode-basic:
- shard-lnl: NOTRUN -> [SKIP][59] ([Intel XE#1447])
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-lnl-2/igt@xe_compute@ccs-mode-basic.html
* igt@xe_eudebug@basic-vm-bind-metadata-discovery:
- shard-bmg: NOTRUN -> [SKIP][60] ([Intel XE#4837]) +3 other tests skip
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-10/igt@xe_eudebug@basic-vm-bind-metadata-discovery.html
* igt@xe_eudebug@multiple-sessions:
- shard-lnl: NOTRUN -> [SKIP][61] ([Intel XE#4837])
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-lnl-2/igt@xe_eudebug@multiple-sessions.html
* igt@xe_eudebug_online@pagefault-one-of-many:
- shard-bmg: NOTRUN -> [SKIP][62] ([Intel XE#6665])
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-10/igt@xe_eudebug_online@pagefault-one-of-many.html
* igt@xe_eudebug_online@writes-caching-vram-bb-vram-target-vram:
- shard-bmg: NOTRUN -> [SKIP][63] ([Intel XE#4837] / [Intel XE#6665])
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-10/igt@xe_eudebug_online@writes-caching-vram-bb-vram-target-vram.html
* igt@xe_evict@evict-beng-cm-threads-small:
- shard-lnl: NOTRUN -> [SKIP][64] ([Intel XE#688])
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-lnl-7/igt@xe_evict@evict-beng-cm-threads-small.html
* igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate:
- shard-bmg: NOTRUN -> [SKIP][65] ([Intel XE#2322]) +2 other tests skip
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-9/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate.html
* igt@xe_exec_basic@multigpu-once-bindexecqueue:
- shard-lnl: NOTRUN -> [SKIP][66] ([Intel XE#1392])
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-lnl-2/igt@xe_exec_basic@multigpu-once-bindexecqueue.html
* igt@xe_exec_multi_queue@many-execs-priority:
- shard-lnl: NOTRUN -> [SKIP][67] ([Intel XE#6874]) +7 other tests skip
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-lnl-7/igt@xe_exec_multi_queue@many-execs-priority.html
* igt@xe_exec_multi_queue@many-queues-preempt-mode-dyn-priority-smem:
- shard-bmg: NOTRUN -> [SKIP][68] ([Intel XE#6874]) +9 other tests skip
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-10/igt@xe_exec_multi_queue@many-queues-preempt-mode-dyn-priority-smem.html
* igt@xe_exec_store@basic-all@engine-drm_xe_engine_class_copy-instance-0-tile-0:
- shard-lnl: [PASS][69] -> [DMESG-WARN][70] ([Intel XE#7063])
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c/shard-lnl-4/igt@xe_exec_store@basic-all@engine-drm_xe_engine_class_copy-instance-0-tile-0.html
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-lnl-4/igt@xe_exec_store@basic-all@engine-drm_xe_engine_class_copy-instance-0-tile-0.html
* igt@xe_exec_system_allocator@process-many-execqueues-mmap-remap-ro:
- shard-bmg: [PASS][71] -> [ABORT][72] ([Intel XE#5545])
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c/shard-bmg-9/igt@xe_exec_system_allocator@process-many-execqueues-mmap-remap-ro.html
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-2/igt@xe_exec_system_allocator@process-many-execqueues-mmap-remap-ro.html
* igt@xe_exec_system_allocator@threads-many-large-mmap-huge-nomemset:
- shard-bmg: NOTRUN -> [SKIP][73] ([Intel XE#4943]) +7 other tests skip
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-7/igt@xe_exec_system_allocator@threads-many-large-mmap-huge-nomemset.html
* igt@xe_exec_system_allocator@threads-shared-vm-many-large-mmap-new-huge-nomemset:
- shard-lnl: NOTRUN -> [SKIP][74] ([Intel XE#4943]) +5 other tests skip
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-lnl-2/igt@xe_exec_system_allocator@threads-shared-vm-many-large-mmap-new-huge-nomemset.html
* igt@xe_mmap@small-bar:
- shard-bmg: NOTRUN -> [SKIP][75] ([Intel XE#586])
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-9/igt@xe_mmap@small-bar.html
* igt@xe_multigpu_svm@mgpu-pagefault-basic:
- shard-bmg: NOTRUN -> [SKIP][76] ([Intel XE#6964])
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-10/igt@xe_multigpu_svm@mgpu-pagefault-basic.html
* igt@xe_query@multigpu-query-invalid-size:
- shard-lnl: NOTRUN -> [SKIP][77] ([Intel XE#944])
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-lnl-2/igt@xe_query@multigpu-query-invalid-size.html
* igt@xe_sriov_auto_provisioning@selfconfig-reprovision-increase-numvfs:
- shard-lnl: NOTRUN -> [SKIP][78] ([Intel XE#4130])
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-lnl-7/igt@xe_sriov_auto_provisioning@selfconfig-reprovision-increase-numvfs.html
#### Possible fixes ####
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
- shard-lnl: [FAIL][79] ([Intel XE#301] / [Intel XE#3149]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
* igt@kms_hdr@bpc-switch@pipe-a-dp-2:
- shard-bmg: [ABORT][81] ([Intel XE#6740]) -> [PASS][82] +1 other test pass
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c/shard-bmg-7/igt@kms_hdr@bpc-switch@pipe-a-dp-2.html
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-10/igt@kms_hdr@bpc-switch@pipe-a-dp-2.html
* igt@kms_plane_lowres@tiling-none:
- shard-bmg: [DMESG-WARN][83] ([Intel XE#5681]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c/shard-bmg-2/igt@kms_plane_lowres@tiling-none.html
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-7/igt@kms_plane_lowres@tiling-none.html
* igt@kms_plane_lowres@tiling-none@pipe-d-hdmi-a-3:
- shard-bmg: [DMESG-WARN][85] ([Intel XE#6959]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c/shard-bmg-2/igt@kms_plane_lowres@tiling-none@pipe-d-hdmi-a-3.html
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-7/igt@kms_plane_lowres@tiling-none@pipe-d-hdmi-a-3.html
* {igt@xe_exec_basic@no-exec-bindexecqueue-userptr-invalidate@rcs0}:
- shard-lnl: [DMESG-WARN][87] ([Intel XE#7063]) -> [PASS][88] +1 other test pass
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c/shard-lnl-4/igt@xe_exec_basic@no-exec-bindexecqueue-userptr-invalidate@rcs0.html
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-lnl-4/igt@xe_exec_basic@no-exec-bindexecqueue-userptr-invalidate@rcs0.html
* igt@xe_exec_reset@gt-reset-stress:
- shard-lnl: [DMESG-WARN][89] ([Intel XE#7023]) -> [PASS][90]
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c/shard-lnl-8/igt@xe_exec_reset@gt-reset-stress.html
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-lnl-5/igt@xe_exec_reset@gt-reset-stress.html
* igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma:
- shard-lnl: [FAIL][91] ([Intel XE#5625]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c/shard-lnl-8/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma.html
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-lnl-5/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma.html
#### Warnings ####
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-lnl: [FAIL][93] ([Intel XE#301] / [Intel XE#3149]) -> [FAIL][94] ([Intel XE#301])
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-sf:
- shard-lnl: [DMESG-WARN][95] ([Intel XE#4537] / [Intel XE#7063]) -> [DMESG-WARN][96] ([Intel XE#7063]) +1 other test dmesg-warn
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c/shard-lnl-3/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-sf.html
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-lnl-1/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-sf.html
* igt@xe_module_load@load:
- shard-bmg: ([PASS][97], [PASS][98], [PASS][99], [PASS][100], [PASS][101], [PASS][102], [PASS][103], [PASS][104], [PASS][105], [PASS][106], [PASS][107], [PASS][108], [PASS][109], [PASS][110], [PASS][111], [PASS][112], [PASS][113], [PASS][114], [PASS][115], [PASS][116], [PASS][117], [PASS][118], [PASS][119], [PASS][120], [SKIP][121], [PASS][122]) ([Intel XE#2457]) -> ([PASS][123], [PASS][124], [PASS][125], [PASS][126], [PASS][127], [PASS][128], [PASS][129], [PASS][130], [PASS][131], [PASS][132], [PASS][133], [PASS][134], [PASS][135], [PASS][136], [ABORT][137], [ABORT][138], [SKIP][139], [ABORT][140], [PASS][141], [PASS][142], [PASS][143], [PASS][144], [PASS][145], [PASS][146]) ([Intel XE#2457] / [Intel XE#7083])
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c/shard-bmg-3/igt@xe_module_load@load.html
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c/shard-bmg-3/igt@xe_module_load@load.html
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c/shard-bmg-8/igt@xe_module_load@load.html
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c/shard-bmg-8/igt@xe_module_load@load.html
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c/shard-bmg-8/igt@xe_module_load@load.html
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c/shard-bmg-8/igt@xe_module_load@load.html
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c/shard-bmg-1/igt@xe_module_load@load.html
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c/shard-bmg-1/igt@xe_module_load@load.html
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c/shard-bmg-9/igt@xe_module_load@load.html
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c/shard-bmg-9/igt@xe_module_load@load.html
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c/shard-bmg-7/igt@xe_module_load@load.html
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c/shard-bmg-1/igt@xe_module_load@load.html
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c/shard-bmg-7/igt@xe_module_load@load.html
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c/shard-bmg-10/igt@xe_module_load@load.html
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c/shard-bmg-9/igt@xe_module_load@load.html
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c/shard-bmg-9/igt@xe_module_load@load.html
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c/shard-bmg-3/igt@xe_module_load@load.html
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c/shard-bmg-7/igt@xe_module_load@load.html
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c/shard-bmg-10/igt@xe_module_load@load.html
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c/shard-bmg-2/igt@xe_module_load@load.html
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c/shard-bmg-2/igt@xe_module_load@load.html
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c/shard-bmg-2/igt@xe_module_load@load.html
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c/shard-bmg-7/igt@xe_module_load@load.html
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c/shard-bmg-10/igt@xe_module_load@load.html
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c/shard-bmg-2/igt@xe_module_load@load.html
[122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c/shard-bmg-2/igt@xe_module_load@load.html
[123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-10/igt@xe_module_load@load.html
[124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-1/igt@xe_module_load@load.html
[125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-3/igt@xe_module_load@load.html
[126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-1/igt@xe_module_load@load.html
[127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-7/igt@xe_module_load@load.html
[128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-7/igt@xe_module_load@load.html
[129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-9/igt@xe_module_load@load.html
[130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-7/igt@xe_module_load@load.html
[131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-8/igt@xe_module_load@load.html
[132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-2/igt@xe_module_load@load.html
[133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-2/igt@xe_module_load@load.html
[134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-2/igt@xe_module_load@load.html
[135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-1/igt@xe_module_load@load.html
[136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-10/igt@xe_module_load@load.html
[137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-6/igt@xe_module_load@load.html
[138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-6/igt@xe_module_load@load.html
[139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-10/igt@xe_module_load@load.html
[140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-6/igt@xe_module_load@load.html
[141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-3/igt@xe_module_load@load.html
[142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-10/igt@xe_module_load@load.html
[143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-9/igt@xe_module_load@load.html
[144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-8/igt@xe_module_load@load.html
[145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-9/igt@xe_module_load@load.html
[146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-bmg-2/igt@xe_module_load@load.html
* igt@xe_pat@pat-sanity:
- shard-lnl: [DMESG-WARN][147] ([Intel XE#7063]) -> [DMESG-WARN][148] ([Intel XE#4537] / [Intel XE#7063])
[147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c/shard-lnl-4/igt@xe_pat@pat-sanity.html
[148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/shard-lnl-4/igt@xe_pat@pat-sanity.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
[Intel XE#1397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1397
[Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
[Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
[Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
[Intel XE#1447]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1447
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
[Intel XE#1508]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1508
[Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
[Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
[Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
[Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
[Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
[Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
[Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
[Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
[Intel XE#2372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2372
[Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
[Intel XE#2390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2390
[Intel XE#2392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2392
[Intel XE#2413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2413
[Intel XE#2457]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2457
[Intel XE#2486]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2486
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
[Intel XE#3098]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3098
[Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
[Intel XE#3279]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3279
[Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
[Intel XE#4130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4130
[Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
[Intel XE#4537]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4537
[Intel XE#4608]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4608
[Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
[Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
[Intel XE#5545]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5545
[Intel XE#5625]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5625
[Intel XE#5681]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5681
[Intel XE#586]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/586
[Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
[Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
[Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
[Intel XE#6665]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6665
[Intel XE#6740]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6740
[Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
[Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
[Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
[Intel XE#6959]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6959
[Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
[Intel XE#6974]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6974
[Intel XE#6976]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6976
[Intel XE#7023]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7023
[Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
[Intel XE#7063]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7063
[Intel XE#7064]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7064
[Intel XE#7081]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7081
[Intel XE#7083]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7083
[Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
Build changes
-------------
* Linux: xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c -> xe-pw-160184v1
IGT_8704: 8704
xe-4394-2c3e2b14be8eda5fb69764bb077663809afa183c: 2c3e2b14be8eda5fb69764bb077663809afa183c
xe-pw-160184v1: 160184v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v1/index.html
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