[PATCH v3] drm/i915/display: fix the pixel normalization handling for xe3p_lpd

[PATCH v3] drm/i915/display: fix the pixel normalization handling for xe3p_lpd

[Vinod Govindapillai]

Pixel normalizer is enabled with normalization factor as 1.0 for
FP16 formats in order to support FBC for those formats in xe3p_lpd.
Previously pixel normalizer gets disabled during the plane disable
routine. But there could be plane format settings without explicitly
calling the plane disable in-between and we could endup keeping the
pixel normalizer enabled for formats which we don't require that.
This is causing crc mismatches in yuv formats and FIFO underruns in
planar formats like NV12.

Fix this by updating the pixel normalizer configuration based on the
pixel formats explicitly during the plane settings arm calls itself
- enable it for FP16 and disable it for other formats in HDR capable
planes. To avoid redundancies in these updates, normalization factor
between old and new plane states are compared before the update. The
function to check validity of the fp16 formats for fbc is now updated
to return the normalization factor as 1.0 in case of fp16 formats and
0 in other cases.

v2: avoid redundant pixel normalization setting updates

v3: moved the normalization factor definition to intel_fbc.c and some
    updates to comments

Fixes: 5298eea7ed20 ("drm/i915/xe3p_lpd: use pixel normalizer for fp16 formats for FBC")
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
---
 .../drm/i915/display/intel_display_device.h   |  1 +
 .../drm/i915/display/intel_display_types.h    |  8 ++
 drivers/gpu/drm/i915/display/intel_fbc.c      | 19 ++++-
 drivers/gpu/drm/i915/display/intel_fbc.h      |  4 +-
 .../drm/i915/display/skl_universal_plane.c    | 82 +++++++++++++++----
 .../i915/display/skl_universal_plane_regs.h   |  1 -
 6 files changed, 92 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index 6c74d6b0cc48..126aa1eeeb6d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -175,6 +175,7 @@ struct intel_display_platforms {
 #define HAS_DSC_MST(__display)		(DISPLAY_VER(__display) >= 12 && HAS_DSC(__display))
 #define HAS_FBC(__display)		(DISPLAY_RUNTIME_INFO(__display)->fbc_mask != 0)
 #define HAS_FBC_DIRTY_RECT(__display)	(DISPLAY_VER(__display) >= 30)
+#define HAS_FBC_FP16_FORMATS(__display)	(DISPLAY_VER(__display) >= 35)
 #define HAS_FBC_SYS_CACHE(__display)	(DISPLAY_VER(__display) >= 35 && !(__display)->platform.dgfx)
 #define HAS_FPGA_DBG_UNCLAIMED(__display)	(DISPLAY_INFO(__display)->has_fpga_dbg)
 #define HAS_FW_BLC(__display)		(DISPLAY_VER(__display) >= 3)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index e6298279dc89..92bce232b2c5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -686,6 +686,14 @@ struct intel_plane_state {
 	unsigned long flags;
 #define PLANE_HAS_FENCE BIT(0)
 
+	/* xe3p_lpd+ */
+	struct {
+		/* In half-precision floating-point format. 0x3c00 (1.0) for fp16 formats */
+		unsigned int factor;
+		/* update is needed if factor differs between old and new plane states */
+		bool needs_update;
+	} pixel_normalizer;
+
 	struct intel_fb_view view;
 
 	/* for legacy cursor fb unpin */
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 1f3f5237a1c2..f9474e7741c8 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -71,6 +71,9 @@
 
 #define FBC_SYS_CACHE_ID_NONE	I915_MAX_FBCS
 
+/* Pixel normalization factor 1.0 in half-precision floating-point format */
+#define NORM_FACTOR_1_0_IN_HALF_PRECISION_FP		0x3c00
+
 struct intel_fbc_funcs {
 	void (*activate)(struct intel_fbc *fbc);
 	void (*deactivate)(struct intel_fbc *fbc);
@@ -1215,13 +1218,21 @@ static bool xe3p_lpd_fbc_pixel_format_is_valid(const struct intel_plane_state *p
 	}
 }
 
-bool
-intel_fbc_is_enable_pixel_normalizer(const struct intel_plane_state *plane_state)
+unsigned int
+intel_fbc_normalization_factor(const struct intel_plane_state *plane_state)
 {
 	struct intel_display *display = to_intel_display(plane_state);
 
-	return DISPLAY_VER(display) >= 35 &&
-	       xe3p_lpd_fbc_fp16_format_is_valid(plane_state);
+	/*
+	 * In order to have FBC for fp16 formats pixel normalizer block must be
+	 * active. For FP16 formats, use normalization factor as 1.0 and enable
+	 * the block.
+	 */
+	if (HAS_FBC_FP16_FORMATS(display) &&
+	    xe3p_lpd_fbc_fp16_format_is_valid(plane_state))
+		return NORM_FACTOR_1_0_IN_HALF_PRECISION_FP;
+
+	return 0;
 }
 
 static bool pixel_format_is_valid(const struct intel_plane_state *plane_state)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h
index f0255ddae2b6..b5888e98a659 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.h
+++ b/drivers/gpu/drm/i915/display/intel_fbc.h
@@ -56,7 +56,7 @@ void intel_fbc_prepare_dirty_rect(struct intel_atomic_state *state,
 				  struct intel_crtc *crtc);
 void intel_fbc_dirty_rect_update_noarm(struct intel_dsb *dsb,
 				       struct intel_plane *plane);
-bool
-intel_fbc_is_enable_pixel_normalizer(const struct intel_plane_state *plane_state);
+unsigned int
+intel_fbc_normalization_factor(const struct intel_plane_state *plane_state);
 
 #endif /* __INTEL_FBC_H__ */
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index b3d41705448a..05c227913b8d 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -891,20 +891,49 @@ static void icl_plane_disable_sel_fetch_arm(struct intel_dsb *dsb,
 	intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_CTL(pipe, plane->id), 0);
 }
 
-static void x3p_lpd_plane_update_pixel_normalizer(struct intel_dsb *dsb,
-						  struct intel_plane *plane,
-						  bool enable)
+static void xe3p_lpd_plane_disable_pixel_normalizer(struct intel_dsb *dsb,
+						    struct intel_plane *plane)
 {
 	struct intel_display *display = to_intel_display(plane);
 	enum intel_fbc_id fbc_id = skl_fbc_id_for_pipe(plane->pipe);
-	u32 val;
+	const struct intel_plane_state *plane_state =
+		to_intel_plane_state(plane->base.state);
+
+	if (!HAS_FBC_FP16_FORMATS(display))
+		return;
+
+	if (!skl_plane_has_fbc(display, fbc_id, plane->id))
+		return;
+
+	if (!plane_state->pixel_normalizer.factor)
+		return;
+
+	intel_de_write_dsb(display, dsb,
+			   PLANE_PIXEL_NORMALIZE(plane->pipe, plane->id), 0);
+}
+
+static void xe3p_lpd_plane_update_pixel_normalizer(struct intel_dsb *dsb,
+						   struct intel_plane *plane)
+{
+	struct intel_display *display = to_intel_display(plane);
+	enum intel_fbc_id fbc_id = skl_fbc_id_for_pipe(plane->pipe);
+	const struct intel_plane_state *plane_state =
+		to_intel_plane_state(plane->base.state);
+	u32 val = 0;
+
+	if (!HAS_FBC_FP16_FORMATS(display))
+		return;
 
-	/* Only HDR planes have pixel normalizer and don't matter if no FBC */
+	/* Only HDR planes have pixel normalizer and don't matter if FBC is fused off */
 	if (!skl_plane_has_fbc(display, fbc_id, plane->id))
 		return;
 
-	val = enable ? PLANE_PIXEL_NORMALIZE_NORM_FACTOR(PLANE_PIXEL_NORMALIZE_NORM_FACTOR_1_0) |
-		       PLANE_PIXEL_NORMALIZE_ENABLE : 0;
+	if (!plane_state->pixel_normalizer.needs_update)
+		return;
+
+	if (plane_state->pixel_normalizer.factor)
+		val = PLANE_PIXEL_NORMALIZE_NORM_FACTOR(plane_state->pixel_normalizer.factor) |
+		      PLANE_PIXEL_NORMALIZE_ENABLE;
 
 	intel_de_write_dsb(display, dsb,
 			   PLANE_PIXEL_NORMALIZE(plane->pipe, plane->id), val);
@@ -926,8 +955,7 @@ icl_plane_disable_arm(struct intel_dsb *dsb,
 
 	icl_plane_disable_sel_fetch_arm(dsb, plane, crtc_state);
 
-	if (DISPLAY_VER(display) >= 35)
-		x3p_lpd_plane_update_pixel_normalizer(dsb, plane, false);
+	xe3p_lpd_plane_disable_pixel_normalizer(dsb, plane);
 
 	intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id), 0);
 	intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id), 0);
@@ -1674,13 +1702,7 @@ icl_plane_update_arm(struct intel_dsb *dsb,
 
 	intel_color_plane_commit_arm(dsb, plane_state);
 
-	/*
-	 * In order to have FBC for fp16 formats pixel normalizer block must be
-	 * active. Check if pixel normalizer block need to be enabled for FBC.
-	 * If needed, use normalization factor as 1.0 and enable the block.
-	 */
-	if (intel_fbc_is_enable_pixel_normalizer(plane_state))
-		x3p_lpd_plane_update_pixel_normalizer(dsb, plane, true);
+	xe3p_lpd_plane_update_pixel_normalizer(dsb, plane);
 
 	/*
 	 * The control register self-arms if the plane was previously
@@ -2350,6 +2372,32 @@ static void clip_damage(struct intel_plane_state *plane_state)
 	drm_rect_intersect(damage, &src);
 }
 
+static void check_pixel_normalizer(struct intel_plane_state *plane_state)
+{
+	struct intel_display *display = to_intel_display(plane_state);
+	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
+	struct intel_atomic_state *state =
+		to_intel_atomic_state(plane_state->uapi.state);
+	const struct intel_plane_state *old_plane_state =
+		intel_atomic_get_old_plane_state(state, plane);
+
+	if (!HAS_FBC_FP16_FORMATS(display))
+		return;
+
+	plane_state->pixel_normalizer.factor =
+		intel_fbc_normalization_factor(plane_state);
+
+	/*
+	 * In case of no old state to compare, better to force update the pixel
+	 * normalizer settings.
+	 */
+	plane_state->pixel_normalizer.needs_update = true;
+	if (old_plane_state && old_plane_state->hw.fb)
+		plane_state->pixel_normalizer.needs_update =
+			plane_state->pixel_normalizer.factor !=
+			intel_fbc_normalization_factor(old_plane_state);
+}
+
 static int skl_plane_check(struct intel_crtc_state *crtc_state,
 			   struct intel_plane_state *plane_state)
 {
@@ -2400,6 +2448,8 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
 
 	check_protection(plane_state);
 
+	check_pixel_normalizer(plane_state);
+
 	/* HW only has 8 bits pixel precision, disable plane if invisible */
 	if (!(plane_state->hw.alpha >> 8)) {
 		plane_state->uapi.visible = false;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
index 6fd4da9f63cf..651f3557b576 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
@@ -580,6 +580,5 @@
 #define   PLANE_PIXEL_NORMALIZE_ENABLE			REG_BIT(31)
 #define   PLANE_PIXEL_NORMALIZE_NORM_FACTOR_MASK	REG_GENMASK(15, 0)
 #define   PLANE_PIXEL_NORMALIZE_NORM_FACTOR(val)	REG_FIELD_PREP(PLANE_PIXEL_NORMALIZE_NORM_FACTOR_MASK, (val))
-#define   PLANE_PIXEL_NORMALIZE_NORM_FACTOR_1_0		0x3c00
 
 #endif /* __SKL_UNIVERSAL_PLANE_REGS_H__ */
-- 
2.43.0

Re: [PATCH v3] drm/i915/display: fix the pixel normalization handling for xe3p_lpd

[Ville Syrjälä]

On Tue, Jan 27, 2026 at 01:13:45PM +0200, Vinod Govindapillai wrote:
> Pixel normalizer is enabled with normalization factor as 1.0 for
> FP16 formats in order to support FBC for those formats in xe3p_lpd.
> Previously pixel normalizer gets disabled during the plane disable
> routine. But there could be plane format settings without explicitly
> calling the plane disable in-between and we could endup keeping the
> pixel normalizer enabled for formats which we don't require that.
> This is causing crc mismatches in yuv formats and FIFO underruns in
> planar formats like NV12.
> 
> Fix this by updating the pixel normalizer configuration based on the
> pixel formats explicitly during the plane settings arm calls itself
> - enable it for FP16 and disable it for other formats in HDR capable
> planes. To avoid redundancies in these updates, normalization factor
> between old and new plane states are compared before the update. The
> function to check validity of the fp16 formats for fbc is now updated
> to return the normalization factor as 1.0 in case of fp16 formats and
> 0 in other cases.

This looks incredibly complex for just writing a single register.
I think it should be just somehting like:

static u32 pixel_normalizer_val()
{
	if (!need_pixel_normalizer())
		return 0;

	return ENABLE | FACTOR;
}

plane_update(..)
{
	...
	if (HAS_PIXEL_NORMALIZER())
		write(PIXEL_NOFMRALIZER, pixel_normalizer_val())
	...
}

plane_disable()
{
	...
	// do we even need to disable it for disabled planes?
	if (HAS_PIXEL_NORMALIZER())
		write(PIXEL_NORMALIZER, 0);
	...
}

> 
> v2: avoid redundant pixel normalization setting updates
> 
> v3: moved the normalization factor definition to intel_fbc.c and some
>     updates to comments
> 
> Fixes: 5298eea7ed20 ("drm/i915/xe3p_lpd: use pixel normalizer for fp16 formats for FBC")
> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> ---
>  .../drm/i915/display/intel_display_device.h   |  1 +
>  .../drm/i915/display/intel_display_types.h    |  8 ++
>  drivers/gpu/drm/i915/display/intel_fbc.c      | 19 ++++-
>  drivers/gpu/drm/i915/display/intel_fbc.h      |  4 +-
>  .../drm/i915/display/skl_universal_plane.c    | 82 +++++++++++++++----
>  .../i915/display/skl_universal_plane_regs.h   |  1 -
>  6 files changed, 92 insertions(+), 23 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
> index 6c74d6b0cc48..126aa1eeeb6d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -175,6 +175,7 @@ struct intel_display_platforms {
>  #define HAS_DSC_MST(__display)		(DISPLAY_VER(__display) >= 12 && HAS_DSC(__display))
>  #define HAS_FBC(__display)		(DISPLAY_RUNTIME_INFO(__display)->fbc_mask != 0)
>  #define HAS_FBC_DIRTY_RECT(__display)	(DISPLAY_VER(__display) >= 30)
> +#define HAS_FBC_FP16_FORMATS(__display)	(DISPLAY_VER(__display) >= 35)
>  #define HAS_FBC_SYS_CACHE(__display)	(DISPLAY_VER(__display) >= 35 && !(__display)->platform.dgfx)
>  #define HAS_FPGA_DBG_UNCLAIMED(__display)	(DISPLAY_INFO(__display)->has_fpga_dbg)
>  #define HAS_FW_BLC(__display)		(DISPLAY_VER(__display) >= 3)
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index e6298279dc89..92bce232b2c5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -686,6 +686,14 @@ struct intel_plane_state {
>  	unsigned long flags;
>  #define PLANE_HAS_FENCE BIT(0)
>  
> +	/* xe3p_lpd+ */
> +	struct {
> +		/* In half-precision floating-point format. 0x3c00 (1.0) for fp16 formats */
> +		unsigned int factor;
> +		/* update is needed if factor differs between old and new plane states */
> +		bool needs_update;
> +	} pixel_normalizer;
> +
>  	struct intel_fb_view view;
>  
>  	/* for legacy cursor fb unpin */
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 1f3f5237a1c2..f9474e7741c8 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -71,6 +71,9 @@
>  
>  #define FBC_SYS_CACHE_ID_NONE	I915_MAX_FBCS
>  
> +/* Pixel normalization factor 1.0 in half-precision floating-point format */
> +#define NORM_FACTOR_1_0_IN_HALF_PRECISION_FP		0x3c00
> +
>  struct intel_fbc_funcs {
>  	void (*activate)(struct intel_fbc *fbc);
>  	void (*deactivate)(struct intel_fbc *fbc);
> @@ -1215,13 +1218,21 @@ static bool xe3p_lpd_fbc_pixel_format_is_valid(const struct intel_plane_state *p
>  	}
>  }
>  
> -bool
> -intel_fbc_is_enable_pixel_normalizer(const struct intel_plane_state *plane_state)
> +unsigned int
> +intel_fbc_normalization_factor(const struct intel_plane_state *plane_state)
>  {
>  	struct intel_display *display = to_intel_display(plane_state);
>  
> -	return DISPLAY_VER(display) >= 35 &&
> -	       xe3p_lpd_fbc_fp16_format_is_valid(plane_state);
> +	/*
> +	 * In order to have FBC for fp16 formats pixel normalizer block must be
> +	 * active. For FP16 formats, use normalization factor as 1.0 and enable
> +	 * the block.
> +	 */
> +	if (HAS_FBC_FP16_FORMATS(display) &&
> +	    xe3p_lpd_fbc_fp16_format_is_valid(plane_state))
> +		return NORM_FACTOR_1_0_IN_HALF_PRECISION_FP;
> +
> +	return 0;
>  }
>  
>  static bool pixel_format_is_valid(const struct intel_plane_state *plane_state)
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h
> index f0255ddae2b6..b5888e98a659 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.h
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.h
> @@ -56,7 +56,7 @@ void intel_fbc_prepare_dirty_rect(struct intel_atomic_state *state,
>  				  struct intel_crtc *crtc);
>  void intel_fbc_dirty_rect_update_noarm(struct intel_dsb *dsb,
>  				       struct intel_plane *plane);
> -bool
> -intel_fbc_is_enable_pixel_normalizer(const struct intel_plane_state *plane_state);
> +unsigned int
> +intel_fbc_normalization_factor(const struct intel_plane_state *plane_state);
>  
>  #endif /* __INTEL_FBC_H__ */
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index b3d41705448a..05c227913b8d 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -891,20 +891,49 @@ static void icl_plane_disable_sel_fetch_arm(struct intel_dsb *dsb,
>  	intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_CTL(pipe, plane->id), 0);
>  }
>  
> -static void x3p_lpd_plane_update_pixel_normalizer(struct intel_dsb *dsb,
> -						  struct intel_plane *plane,
> -						  bool enable)
> +static void xe3p_lpd_plane_disable_pixel_normalizer(struct intel_dsb *dsb,
> +						    struct intel_plane *plane)
>  {
>  	struct intel_display *display = to_intel_display(plane);
>  	enum intel_fbc_id fbc_id = skl_fbc_id_for_pipe(plane->pipe);
> -	u32 val;
> +	const struct intel_plane_state *plane_state =
> +		to_intel_plane_state(plane->base.state);
> +
> +	if (!HAS_FBC_FP16_FORMATS(display))
> +		return;
> +
> +	if (!skl_plane_has_fbc(display, fbc_id, plane->id))
> +		return;
> +
> +	if (!plane_state->pixel_normalizer.factor)
> +		return;
> +
> +	intel_de_write_dsb(display, dsb,
> +			   PLANE_PIXEL_NORMALIZE(plane->pipe, plane->id), 0);
> +}
> +
> +static void xe3p_lpd_plane_update_pixel_normalizer(struct intel_dsb *dsb,
> +						   struct intel_plane *plane)
> +{
> +	struct intel_display *display = to_intel_display(plane);
> +	enum intel_fbc_id fbc_id = skl_fbc_id_for_pipe(plane->pipe);
> +	const struct intel_plane_state *plane_state =
> +		to_intel_plane_state(plane->base.state);
> +	u32 val = 0;
> +
> +	if (!HAS_FBC_FP16_FORMATS(display))
> +		return;
>  
> -	/* Only HDR planes have pixel normalizer and don't matter if no FBC */
> +	/* Only HDR planes have pixel normalizer and don't matter if FBC is fused off */
>  	if (!skl_plane_has_fbc(display, fbc_id, plane->id))
>  		return;
>  
> -	val = enable ? PLANE_PIXEL_NORMALIZE_NORM_FACTOR(PLANE_PIXEL_NORMALIZE_NORM_FACTOR_1_0) |
> -		       PLANE_PIXEL_NORMALIZE_ENABLE : 0;
> +	if (!plane_state->pixel_normalizer.needs_update)
> +		return;
> +
> +	if (plane_state->pixel_normalizer.factor)
> +		val = PLANE_PIXEL_NORMALIZE_NORM_FACTOR(plane_state->pixel_normalizer.factor) |
> +		      PLANE_PIXEL_NORMALIZE_ENABLE;
>  
>  	intel_de_write_dsb(display, dsb,
>  			   PLANE_PIXEL_NORMALIZE(plane->pipe, plane->id), val);
> @@ -926,8 +955,7 @@ icl_plane_disable_arm(struct intel_dsb *dsb,
>  
>  	icl_plane_disable_sel_fetch_arm(dsb, plane, crtc_state);
>  
> -	if (DISPLAY_VER(display) >= 35)
> -		x3p_lpd_plane_update_pixel_normalizer(dsb, plane, false);
> +	xe3p_lpd_plane_disable_pixel_normalizer(dsb, plane);
>  
>  	intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id), 0);
>  	intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id), 0);
> @@ -1674,13 +1702,7 @@ icl_plane_update_arm(struct intel_dsb *dsb,
>  
>  	intel_color_plane_commit_arm(dsb, plane_state);
>  
> -	/*
> -	 * In order to have FBC for fp16 formats pixel normalizer block must be
> -	 * active. Check if pixel normalizer block need to be enabled for FBC.
> -	 * If needed, use normalization factor as 1.0 and enable the block.
> -	 */
> -	if (intel_fbc_is_enable_pixel_normalizer(plane_state))
> -		x3p_lpd_plane_update_pixel_normalizer(dsb, plane, true);
> +	xe3p_lpd_plane_update_pixel_normalizer(dsb, plane);
>  
>  	/*
>  	 * The control register self-arms if the plane was previously
> @@ -2350,6 +2372,32 @@ static void clip_damage(struct intel_plane_state *plane_state)
>  	drm_rect_intersect(damage, &src);
>  }
>  
> +static void check_pixel_normalizer(struct intel_plane_state *plane_state)
> +{
> +	struct intel_display *display = to_intel_display(plane_state);
> +	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> +	struct intel_atomic_state *state =
> +		to_intel_atomic_state(plane_state->uapi.state);
> +	const struct intel_plane_state *old_plane_state =
> +		intel_atomic_get_old_plane_state(state, plane);
> +
> +	if (!HAS_FBC_FP16_FORMATS(display))
> +		return;
> +
> +	plane_state->pixel_normalizer.factor =
> +		intel_fbc_normalization_factor(plane_state);
> +
> +	/*
> +	 * In case of no old state to compare, better to force update the pixel
> +	 * normalizer settings.
> +	 */
> +	plane_state->pixel_normalizer.needs_update = true;
> +	if (old_plane_state && old_plane_state->hw.fb)
> +		plane_state->pixel_normalizer.needs_update =
> +			plane_state->pixel_normalizer.factor !=
> +			intel_fbc_normalization_factor(old_plane_state);
> +}
> +
>  static int skl_plane_check(struct intel_crtc_state *crtc_state,
>  			   struct intel_plane_state *plane_state)
>  {
> @@ -2400,6 +2448,8 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
>  
>  	check_protection(plane_state);
>  
> +	check_pixel_normalizer(plane_state);
> +
>  	/* HW only has 8 bits pixel precision, disable plane if invisible */
>  	if (!(plane_state->hw.alpha >> 8)) {
>  		plane_state->uapi.visible = false;
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> index 6fd4da9f63cf..651f3557b576 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> @@ -580,6 +580,5 @@
>  #define   PLANE_PIXEL_NORMALIZE_ENABLE			REG_BIT(31)
>  #define   PLANE_PIXEL_NORMALIZE_NORM_FACTOR_MASK	REG_GENMASK(15, 0)
>  #define   PLANE_PIXEL_NORMALIZE_NORM_FACTOR(val)	REG_FIELD_PREP(PLANE_PIXEL_NORMALIZE_NORM_FACTOR_MASK, (val))
> -#define   PLANE_PIXEL_NORMALIZE_NORM_FACTOR_1_0		0x3c00
>  
>  #endif /* __SKL_UNIVERSAL_PLANE_REGS_H__ */
> -- 
> 2.43.0

-- 
Ville Syrjälä
Intel

RE: [PATCH v3] drm/i915/display: fix the pixel normalization handling for xe3p_lpd

[Shankar, Uma]

> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Tuesday, January 27, 2026 5:48 PM
> To: Govindapillai, Vinod <vinod.govindapillai@intel.com>
> Cc: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org; Shankar, Uma
> <uma.shankar@intel.com>; Heikkila, Juha-pekka <juha-
> pekka.heikkila@intel.com>
> Subject: Re: [PATCH v3] drm/i915/display: fix the pixel normalization handling for
> xe3p_lpd
> 
> On Tue, Jan 27, 2026 at 01:13:45PM +0200, Vinod Govindapillai wrote:
> > Pixel normalizer is enabled with normalization factor as 1.0 for
> > FP16 formats in order to support FBC for those formats in xe3p_lpd.
> > Previously pixel normalizer gets disabled during the plane disable
> > routine. But there could be plane format settings without explicitly
> > calling the plane disable in-between and we could endup keeping the
> > pixel normalizer enabled for formats which we don't require that.
> > This is causing crc mismatches in yuv formats and FIFO underruns in
> > planar formats like NV12.
> >
> > Fix this by updating the pixel normalizer configuration based on the
> > pixel formats explicitly during the plane settings arm calls itself
> > - enable it for FP16 and disable it for other formats in HDR capable
> > planes. To avoid redundancies in these updates, normalization factor
> > between old and new plane states are compared before the update. The
> > function to check validity of the fp16 formats for fbc is now updated
> > to return the normalization factor as 1.0 in case of fp16 formats and
> > 0 in other cases.
> 
> This looks incredibly complex for just writing a single register.
> I think it should be just somehting like:
> 
> static u32 pixel_normalizer_val()
> {
> 	if (!need_pixel_normalizer())
> 		return 0;
> 
> 	return ENABLE | FACTOR;
> }
> 
> plane_update(..)
> {
> 	...
> 	if (HAS_PIXEL_NORMALIZER())
> 		write(PIXEL_NOFMRALIZER, pixel_normalizer_val())
> 	...
> }
> 
> plane_disable()
> {
> 	...
> 	// do we even need to disable it for disabled planes?
> 	if (HAS_PIXEL_NORMALIZER())
> 		write(PIXEL_NORMALIZER, 0);
> 	...
> }

I think we should enable pixel normalizer only when FP16 is being enabled and disable it
in case frame buffer format is switched from FP16 to any other format.

The "need_pixel_normalizer" should check that, in patch this is done by "check_pixel_normalizer".
I am not sure if disable case whether we need to explicitly disable it, but good to have it.

Regards,
Uma Shankar

> >
> > v2: avoid redundant pixel normalization setting updates
> >
> > v3: moved the normalization factor definition to intel_fbc.c and some
> >     updates to comments
> >
> > Fixes: 5298eea7ed20 ("drm/i915/xe3p_lpd: use pixel normalizer for fp16
> > formats for FBC")
> > Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> > ---
> >  .../drm/i915/display/intel_display_device.h   |  1 +
> >  .../drm/i915/display/intel_display_types.h    |  8 ++
> >  drivers/gpu/drm/i915/display/intel_fbc.c      | 19 ++++-
> >  drivers/gpu/drm/i915/display/intel_fbc.h      |  4 +-
> >  .../drm/i915/display/skl_universal_plane.c    | 82 +++++++++++++++----
> >  .../i915/display/skl_universal_plane_regs.h   |  1 -
> >  6 files changed, 92 insertions(+), 23 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
> > b/drivers/gpu/drm/i915/display/intel_display_device.h
> > index 6c74d6b0cc48..126aa1eeeb6d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> > @@ -175,6 +175,7 @@ struct intel_display_platforms {
> >  #define HAS_DSC_MST(__display)		(DISPLAY_VER(__display) >= 12
> && HAS_DSC(__display))
> >  #define HAS_FBC(__display)		(DISPLAY_RUNTIME_INFO(__display)-
> >fbc_mask != 0)
> >  #define HAS_FBC_DIRTY_RECT(__display)	(DISPLAY_VER(__display) >= 30)
> > +#define HAS_FBC_FP16_FORMATS(__display)
> 	(DISPLAY_VER(__display) >= 35)
> >  #define HAS_FBC_SYS_CACHE(__display)	(DISPLAY_VER(__display) >= 35
> && !(__display)->platform.dgfx)
> >  #define HAS_FPGA_DBG_UNCLAIMED(__display)
> 	(DISPLAY_INFO(__display)->has_fpga_dbg)
> >  #define HAS_FW_BLC(__display)		(DISPLAY_VER(__display) >= 3)
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index e6298279dc89..92bce232b2c5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -686,6 +686,14 @@ struct intel_plane_state {
> >  	unsigned long flags;
> >  #define PLANE_HAS_FENCE BIT(0)
> >
> > +	/* xe3p_lpd+ */
> > +	struct {
> > +		/* In half-precision floating-point format. 0x3c00 (1.0) for fp16
> formats */
> > +		unsigned int factor;
> > +		/* update is needed if factor differs between old and new plane
> states */
> > +		bool needs_update;
> > +	} pixel_normalizer;
> > +
> >  	struct intel_fb_view view;
> >
> >  	/* for legacy cursor fb unpin */
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > index 1f3f5237a1c2..f9474e7741c8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > @@ -71,6 +71,9 @@
> >
> >  #define FBC_SYS_CACHE_ID_NONE	I915_MAX_FBCS
> >
> > +/* Pixel normalization factor 1.0 in half-precision floating-point format */
> > +#define NORM_FACTOR_1_0_IN_HALF_PRECISION_FP		0x3c00
> > +
> >  struct intel_fbc_funcs {
> >  	void (*activate)(struct intel_fbc *fbc);
> >  	void (*deactivate)(struct intel_fbc *fbc); @@ -1215,13 +1218,21 @@
> > static bool xe3p_lpd_fbc_pixel_format_is_valid(const struct intel_plane_state *p
> >  	}
> >  }
> >
> > -bool
> > -intel_fbc_is_enable_pixel_normalizer(const struct intel_plane_state
> > *plane_state)
> > +unsigned int
> > +intel_fbc_normalization_factor(const struct intel_plane_state
> > +*plane_state)
> >  {
> >  	struct intel_display *display = to_intel_display(plane_state);
> >
> > -	return DISPLAY_VER(display) >= 35 &&
> > -	       xe3p_lpd_fbc_fp16_format_is_valid(plane_state);
> > +	/*
> > +	 * In order to have FBC for fp16 formats pixel normalizer block must be
> > +	 * active. For FP16 formats, use normalization factor as 1.0 and enable
> > +	 * the block.
> > +	 */
> > +	if (HAS_FBC_FP16_FORMATS(display) &&
> > +	    xe3p_lpd_fbc_fp16_format_is_valid(plane_state))
> > +		return NORM_FACTOR_1_0_IN_HALF_PRECISION_FP;
> > +
> > +	return 0;
> >  }
> >
> >  static bool pixel_format_is_valid(const struct intel_plane_state
> > *plane_state) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h
> > b/drivers/gpu/drm/i915/display/intel_fbc.h
> > index f0255ddae2b6..b5888e98a659 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.h
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.h
> > @@ -56,7 +56,7 @@ void intel_fbc_prepare_dirty_rect(struct
> intel_atomic_state *state,
> >  				  struct intel_crtc *crtc);
> >  void intel_fbc_dirty_rect_update_noarm(struct intel_dsb *dsb,
> >  				       struct intel_plane *plane); -bool
> > -intel_fbc_is_enable_pixel_normalizer(const struct intel_plane_state
> > *plane_state);
> > +unsigned int
> > +intel_fbc_normalization_factor(const struct intel_plane_state
> > +*plane_state);
> >
> >  #endif /* __INTEL_FBC_H__ */
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > index b3d41705448a..05c227913b8d 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > @@ -891,20 +891,49 @@ static void icl_plane_disable_sel_fetch_arm(struct
> intel_dsb *dsb,
> >  	intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_CTL(pipe,
> > plane->id), 0);  }
> >
> > -static void x3p_lpd_plane_update_pixel_normalizer(struct intel_dsb *dsb,
> > -						  struct intel_plane *plane,
> > -						  bool enable)
> > +static void xe3p_lpd_plane_disable_pixel_normalizer(struct intel_dsb *dsb,
> > +						    struct intel_plane *plane)
> >  {
> >  	struct intel_display *display = to_intel_display(plane);
> >  	enum intel_fbc_id fbc_id = skl_fbc_id_for_pipe(plane->pipe);
> > -	u32 val;
> > +	const struct intel_plane_state *plane_state =
> > +		to_intel_plane_state(plane->base.state);
> > +
> > +	if (!HAS_FBC_FP16_FORMATS(display))
> > +		return;
> > +
> > +	if (!skl_plane_has_fbc(display, fbc_id, plane->id))
> > +		return;
> > +
> > +	if (!plane_state->pixel_normalizer.factor)
> > +		return;
> > +
> > +	intel_de_write_dsb(display, dsb,
> > +			   PLANE_PIXEL_NORMALIZE(plane->pipe, plane->id),
> 0); }
> > +
> > +static void xe3p_lpd_plane_update_pixel_normalizer(struct intel_dsb *dsb,
> > +						   struct intel_plane *plane)
> > +{
> > +	struct intel_display *display = to_intel_display(plane);
> > +	enum intel_fbc_id fbc_id = skl_fbc_id_for_pipe(plane->pipe);
> > +	const struct intel_plane_state *plane_state =
> > +		to_intel_plane_state(plane->base.state);
> > +	u32 val = 0;
> > +
> > +	if (!HAS_FBC_FP16_FORMATS(display))
> > +		return;
> >
> > -	/* Only HDR planes have pixel normalizer and don't matter if no FBC */
> > +	/* Only HDR planes have pixel normalizer and don't matter if FBC is
> > +fused off */
> >  	if (!skl_plane_has_fbc(display, fbc_id, plane->id))
> >  		return;
> >
> > -	val = enable ?
> PLANE_PIXEL_NORMALIZE_NORM_FACTOR(PLANE_PIXEL_NORMALIZE_NO
> RM_FACTOR_1_0) |
> > -		       PLANE_PIXEL_NORMALIZE_ENABLE : 0;
> > +	if (!plane_state->pixel_normalizer.needs_update)
> > +		return;
> > +
> > +	if (plane_state->pixel_normalizer.factor)
> > +		val = PLANE_PIXEL_NORMALIZE_NORM_FACTOR(plane_state-
> >pixel_normalizer.factor) |
> > +		      PLANE_PIXEL_NORMALIZE_ENABLE;
> >
> >  	intel_de_write_dsb(display, dsb,
> >  			   PLANE_PIXEL_NORMALIZE(plane->pipe, plane->id),
> val); @@ -926,8
> > +955,7 @@ icl_plane_disable_arm(struct intel_dsb *dsb,
> >
> >  	icl_plane_disable_sel_fetch_arm(dsb, plane, crtc_state);
> >
> > -	if (DISPLAY_VER(display) >= 35)
> > -		x3p_lpd_plane_update_pixel_normalizer(dsb, plane, false);
> > +	xe3p_lpd_plane_disable_pixel_normalizer(dsb, plane);
> >
> >  	intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id), 0);
> >  	intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id), 0); @@
> > -1674,13 +1702,7 @@ icl_plane_update_arm(struct intel_dsb *dsb,
> >
> >  	intel_color_plane_commit_arm(dsb, plane_state);
> >
> > -	/*
> > -	 * In order to have FBC for fp16 formats pixel normalizer block must be
> > -	 * active. Check if pixel normalizer block need to be enabled for FBC.
> > -	 * If needed, use normalization factor as 1.0 and enable the block.
> > -	 */
> > -	if (intel_fbc_is_enable_pixel_normalizer(plane_state))
> > -		x3p_lpd_plane_update_pixel_normalizer(dsb, plane, true);
> > +	xe3p_lpd_plane_update_pixel_normalizer(dsb, plane);
> >
> >  	/*
> >  	 * The control register self-arms if the plane was previously @@
> > -2350,6 +2372,32 @@ static void clip_damage(struct intel_plane_state
> *plane_state)
> >  	drm_rect_intersect(damage, &src);
> >  }
> >
> > +static void check_pixel_normalizer(struct intel_plane_state
> > +*plane_state) {
> > +	struct intel_display *display = to_intel_display(plane_state);
> > +	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> > +	struct intel_atomic_state *state =
> > +		to_intel_atomic_state(plane_state->uapi.state);
> > +	const struct intel_plane_state *old_plane_state =
> > +		intel_atomic_get_old_plane_state(state, plane);
> > +
> > +	if (!HAS_FBC_FP16_FORMATS(display))
> > +		return;
> > +
> > +	plane_state->pixel_normalizer.factor =
> > +		intel_fbc_normalization_factor(plane_state);
> > +
> > +	/*
> > +	 * In case of no old state to compare, better to force update the pixel
> > +	 * normalizer settings.
> > +	 */
> > +	plane_state->pixel_normalizer.needs_update = true;
> > +	if (old_plane_state && old_plane_state->hw.fb)
> > +		plane_state->pixel_normalizer.needs_update =
> > +			plane_state->pixel_normalizer.factor !=
> > +			intel_fbc_normalization_factor(old_plane_state);
> > +}
> > +
> >  static int skl_plane_check(struct intel_crtc_state *crtc_state,
> >  			   struct intel_plane_state *plane_state)  { @@ -2400,6
> +2448,8 @@
> > static int skl_plane_check(struct intel_crtc_state *crtc_state,
> >
> >  	check_protection(plane_state);
> >
> > +	check_pixel_normalizer(plane_state);
> > +
> >  	/* HW only has 8 bits pixel precision, disable plane if invisible */
> >  	if (!(plane_state->hw.alpha >> 8)) {
> >  		plane_state->uapi.visible = false;
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> > b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> > index 6fd4da9f63cf..651f3557b576 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> > @@ -580,6 +580,5 @@
> >  #define   PLANE_PIXEL_NORMALIZE_ENABLE
> 	REG_BIT(31)
> >  #define   PLANE_PIXEL_NORMALIZE_NORM_FACTOR_MASK
> 	REG_GENMASK(15, 0)
> >  #define   PLANE_PIXEL_NORMALIZE_NORM_FACTOR(val)
> 	REG_FIELD_PREP(PLANE_PIXEL_NORMALIZE_NORM_FACTOR_MAS
> K, (val))
> > -#define   PLANE_PIXEL_NORMALIZE_NORM_FACTOR_1_0
> 	0x3c00
> >
> >  #endif /* __SKL_UNIVERSAL_PLANE_REGS_H__ */
> > --
> > 2.43.0
> 
> --
> Ville Syrjälä
> Intel

Re: [PATCH v3] drm/i915/display: fix the pixel normalization handling for xe3p_lpd

[Govindapillai, Vinod]

On Tue, 2026-01-27 at 14:18 +0200, Ville Syrjälä wrote:
> On Tue, Jan 27, 2026 at 01:13:45PM +0200, Vinod Govindapillai wrote:
> > Pixel normalizer is enabled with normalization factor as 1.0 for
> > FP16 formats in order to support FBC for those formats in xe3p_lpd.
> > Previously pixel normalizer gets disabled during the plane disable
> > routine. But there could be plane format settings without
> > explicitly
> > calling the plane disable in-between and we could endup keeping the
> > pixel normalizer enabled for formats which we don't require that.
> > This is causing crc mismatches in yuv formats and FIFO underruns in
> > planar formats like NV12.
> > 
> > Fix this by updating the pixel normalizer configuration based on
> > the
> > pixel formats explicitly during the plane settings arm calls itself
> > - enable it for FP16 and disable it for other formats in HDR
> > capable
> > planes. To avoid redundancies in these updates, normalization
> > factor
> > between old and new plane states are compared before the update.
> > The
> > function to check validity of the fp16 formats for fbc is now
> > updated
> > to return the normalization factor as 1.0 in case of fp16 formats
> > and
> > 0 in other cases.
> 
> This looks incredibly complex for just writing a single register.
> I think it should be just somehting like:
> 
> static u32 pixel_normalizer_val()
> {
> 	if (!need_pixel_normalizer())
> 		return 0;
> 
> 	return ENABLE | FACTOR;
> }
> 
> plane_update(..)
> {
> 	...
> 	if (HAS_PIXEL_NORMALIZER())
> 		write(PIXEL_NOFMRALIZER, pixel_normalizer_val())
> 	...
> }
> 
> plane_disable()
> {
> 	...
> 	// do we even need to disable it for disabled planes?
> 	if (HAS_PIXEL_NORMALIZER())
> 		write(PIXEL_NORMALIZER, 0);
> 	...
> }


Okay. Thanks for the suggestion. This is basically similar to the
revision 1 of this patch!

But before sending another revision, I would like to clarify about
HAS_PIXEL_NORMALIZER(). Pixel normalizer is there even in earlier
versions. We are using this mainly for the FP16 case. So do you agree
to use HAS_FP16_FORMATS instead of HAS_PIXEL_NORMALIZER?

Also normalizer is available for the HDR planes, so will have to use 

if (HAS_FP16_FORMATS(display) && skl_plane_has_fbc(display, fbc_id,
plane->id))
	write(PIXEL_NORMALIZER, val / 0)


BR
Vinod

> 
> > 
> > v2: avoid redundant pixel normalization setting updates
> > 
> > v3: moved the normalization factor definition to intel_fbc.c and
> > some
> >     updates to comments
> > 
> > Fixes: 5298eea7ed20 ("drm/i915/xe3p_lpd: use pixel normalizer for
> > fp16 formats for FBC")
> > Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> > ---
> >  .../drm/i915/display/intel_display_device.h   |  1 +
> >  .../drm/i915/display/intel_display_types.h    |  8 ++
> >  drivers/gpu/drm/i915/display/intel_fbc.c      | 19 ++++-
> >  drivers/gpu/drm/i915/display/intel_fbc.h      |  4 +-
> >  .../drm/i915/display/skl_universal_plane.c    | 82
> > +++++++++++++++----
> >  .../i915/display/skl_universal_plane_regs.h   |  1 -
> >  6 files changed, 92 insertions(+), 23 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
> > b/drivers/gpu/drm/i915/display/intel_display_device.h
> > index 6c74d6b0cc48..126aa1eeeb6d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> > @@ -175,6 +175,7 @@ struct intel_display_platforms {
> >  #define HAS_DSC_MST(__display)		(DISPLAY_VER(__display) >=
> > 12 && HAS_DSC(__display))
> >  #define
> > HAS_FBC(__display)		(DISPLAY_RUNTIME_INFO(__display)->fbc_mask != 0)
> >  #define HAS_FBC_DIRTY_RECT(__display)	(DISPLAY_VER(__display) >=
> > 30)
> > +#define
> > HAS_FBC_FP16_FORMATS(__display)	(DISPLAY_VER(__display) >= 35)
> >  #define HAS_FBC_SYS_CACHE(__display)	(DISPLAY_VER(__display) >=
> > 35 && !(__display)->platform.dgfx)
> >  #define
> > HAS_FPGA_DBG_UNCLAIMED(__display)	(DISPLAY_INFO(__display)->has_fpga_dbg)
> >  #define HAS_FW_BLC(__display)		(DISPLAY_VER(__display) >=
> > 3)
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index e6298279dc89..92bce232b2c5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -686,6 +686,14 @@ struct intel_plane_state {
> >  	unsigned long flags;
> >  #define PLANE_HAS_FENCE BIT(0)
> >  
> > +	/* xe3p_lpd+ */
> > +	struct {
> > +		/* In half-precision floating-point format. 0x3c00
> > (1.0) for fp16 formats */
> > +		unsigned int factor;
> > +		/* update is needed if factor differs between old
> > and new plane states */
> > +		bool needs_update;
> > +	} pixel_normalizer;
> > +
> >  	struct intel_fb_view view;
> >  
> >  	/* for legacy cursor fb unpin */
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > index 1f3f5237a1c2..f9474e7741c8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > @@ -71,6 +71,9 @@
> >  
> >  #define FBC_SYS_CACHE_ID_NONE	I915_MAX_FBCS
> >  
> > +/* Pixel normalization factor 1.0 in half-precision floating-point
> > format */
> > +#define NORM_FACTOR_1_0_IN_HALF_PRECISION_FP		0x3c00
> > +
> >  struct intel_fbc_funcs {
> >  	void (*activate)(struct intel_fbc *fbc);
> >  	void (*deactivate)(struct intel_fbc *fbc);
> > @@ -1215,13 +1218,21 @@ static bool
> > xe3p_lpd_fbc_pixel_format_is_valid(const struct intel_plane_state
> > *p
> >  	}
> >  }
> >  
> > -bool
> > -intel_fbc_is_enable_pixel_normalizer(const struct
> > intel_plane_state *plane_state)
> > +unsigned int
> > +intel_fbc_normalization_factor(const struct intel_plane_state
> > *plane_state)
> >  {
> >  	struct intel_display *display =
> > to_intel_display(plane_state);
> >  
> > -	return DISPLAY_VER(display) >= 35 &&
> > -	       xe3p_lpd_fbc_fp16_format_is_valid(plane_state);
> > +	/*
> > +	 * In order to have FBC for fp16 formats pixel normalizer
> > block must be
> > +	 * active. For FP16 formats, use normalization factor as
> > 1.0 and enable
> > +	 * the block.
> > +	 */
> > +	if (HAS_FBC_FP16_FORMATS(display) &&
> > +	    xe3p_lpd_fbc_fp16_format_is_valid(plane_state))
> > +		return NORM_FACTOR_1_0_IN_HALF_PRECISION_FP;
> > +
> > +	return 0;
> >  }
> >  
> >  static bool pixel_format_is_valid(const struct intel_plane_state
> > *plane_state)
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h
> > b/drivers/gpu/drm/i915/display/intel_fbc.h
> > index f0255ddae2b6..b5888e98a659 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.h
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.h
> > @@ -56,7 +56,7 @@ void intel_fbc_prepare_dirty_rect(struct
> > intel_atomic_state *state,
> >  				  struct intel_crtc *crtc);
> >  void intel_fbc_dirty_rect_update_noarm(struct intel_dsb *dsb,
> >  				       struct intel_plane *plane);
> > -bool
> > -intel_fbc_is_enable_pixel_normalizer(const struct
> > intel_plane_state *plane_state);
> > +unsigned int
> > +intel_fbc_normalization_factor(const struct intel_plane_state
> > *plane_state);
> >  
> >  #endif /* __INTEL_FBC_H__ */
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > index b3d41705448a..05c227913b8d 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > @@ -891,20 +891,49 @@ static void
> > icl_plane_disable_sel_fetch_arm(struct intel_dsb *dsb,
> >  	intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_CTL(pipe,
> > plane->id), 0);
> >  }
> >  
> > -static void x3p_lpd_plane_update_pixel_normalizer(struct intel_dsb
> > *dsb,
> > -						  struct
> > intel_plane *plane,
> > -						  bool enable)
> > +static void xe3p_lpd_plane_disable_pixel_normalizer(struct
> > intel_dsb *dsb,
> > +						    struct
> > intel_plane *plane)
> >  {
> >  	struct intel_display *display = to_intel_display(plane);
> >  	enum intel_fbc_id fbc_id = skl_fbc_id_for_pipe(plane-
> > >pipe);
> > -	u32 val;
> > +	const struct intel_plane_state *plane_state =
> > +		to_intel_plane_state(plane->base.state);
> > +
> > +	if (!HAS_FBC_FP16_FORMATS(display))
> > +		return;
> > +
> > +	if (!skl_plane_has_fbc(display, fbc_id, plane->id))
> > +		return;
> > +
> > +	if (!plane_state->pixel_normalizer.factor)
> > +		return;
> > +
> > +	intel_de_write_dsb(display, dsb,
> > +			   PLANE_PIXEL_NORMALIZE(plane->pipe,
> > plane->id), 0);
> > +}
> > +
> > +static void xe3p_lpd_plane_update_pixel_normalizer(struct
> > intel_dsb *dsb,
> > +						   struct
> > intel_plane *plane)
> > +{
> > +	struct intel_display *display = to_intel_display(plane);
> > +	enum intel_fbc_id fbc_id = skl_fbc_id_for_pipe(plane-
> > >pipe);
> > +	const struct intel_plane_state *plane_state =
> > +		to_intel_plane_state(plane->base.state);
> > +	u32 val = 0;
> > +
> > +	if (!HAS_FBC_FP16_FORMATS(display))
> > +		return;
> >  
> > -	/* Only HDR planes have pixel normalizer and don't matter
> > if no FBC */
> > +	/* Only HDR planes have pixel normalizer and don't matter
> > if FBC is fused off */
> >  	if (!skl_plane_has_fbc(display, fbc_id, plane->id))
> >  		return;
> >  
> > -	val = enable ?
> > PLANE_PIXEL_NORMALIZE_NORM_FACTOR(PLANE_PIXEL_NORMALIZE_NORM_FACTOR
> > _1_0) |
> > -		       PLANE_PIXEL_NORMALIZE_ENABLE : 0;
> > +	if (!plane_state->pixel_normalizer.needs_update)
> > +		return;
> > +
> > +	if (plane_state->pixel_normalizer.factor)
> > +		val =
> > PLANE_PIXEL_NORMALIZE_NORM_FACTOR(plane_state-
> > >pixel_normalizer.factor) |
> > +		      PLANE_PIXEL_NORMALIZE_ENABLE;
> >  
> >  	intel_de_write_dsb(display, dsb,
> >  			   PLANE_PIXEL_NORMALIZE(plane->pipe,
> > plane->id), val);
> > @@ -926,8 +955,7 @@ icl_plane_disable_arm(struct intel_dsb *dsb,
> >  
> >  	icl_plane_disable_sel_fetch_arm(dsb, plane, crtc_state);
> >  
> > -	if (DISPLAY_VER(display) >= 35)
> > -		x3p_lpd_plane_update_pixel_normalizer(dsb, plane,
> > false);
> > +	xe3p_lpd_plane_disable_pixel_normalizer(dsb, plane);
> >  
> >  	intel_de_write_dsb(display, dsb, PLANE_CTL(pipe,
> > plane_id), 0);
> >  	intel_de_write_dsb(display, dsb, PLANE_SURF(pipe,
> > plane_id), 0);
> > @@ -1674,13 +1702,7 @@ icl_plane_update_arm(struct intel_dsb *dsb,
> >  
> >  	intel_color_plane_commit_arm(dsb, plane_state);
> >  
> > -	/*
> > -	 * In order to have FBC for fp16 formats pixel normalizer
> > block must be
> > -	 * active. Check if pixel normalizer block need to be
> > enabled for FBC.
> > -	 * If needed, use normalization factor as 1.0 and enable
> > the block.
> > -	 */
> > -	if (intel_fbc_is_enable_pixel_normalizer(plane_state))
> > -		x3p_lpd_plane_update_pixel_normalizer(dsb, plane,
> > true);
> > +	xe3p_lpd_plane_update_pixel_normalizer(dsb, plane);
> >  
> >  	/*
> >  	 * The control register self-arms if the plane was
> > previously
> > @@ -2350,6 +2372,32 @@ static void clip_damage(struct
> > intel_plane_state *plane_state)
> >  	drm_rect_intersect(damage, &src);
> >  }
> >  
> > +static void check_pixel_normalizer(struct intel_plane_state
> > *plane_state)
> > +{
> > +	struct intel_display *display =
> > to_intel_display(plane_state);
> > +	struct intel_plane *plane = to_intel_plane(plane_state-
> > >uapi.plane);
> > +	struct intel_atomic_state *state =
> > +		to_intel_atomic_state(plane_state->uapi.state);
> > +	const struct intel_plane_state *old_plane_state =
> > +		intel_atomic_get_old_plane_state(state, plane);
> > +
> > +	if (!HAS_FBC_FP16_FORMATS(display))
> > +		return;
> > +
> > +	plane_state->pixel_normalizer.factor =
> > +		intel_fbc_normalization_factor(plane_state);
> > +
> > +	/*
> > +	 * In case of no old state to compare, better to force
> > update the pixel
> > +	 * normalizer settings.
> > +	 */
> > +	plane_state->pixel_normalizer.needs_update = true;
> > +	if (old_plane_state && old_plane_state->hw.fb)
> > +		plane_state->pixel_normalizer.needs_update =
> > +			plane_state->pixel_normalizer.factor !=
> > +			intel_fbc_normalization_factor(old_plane_s
> > tate);
> > +}
> > +
> >  static int skl_plane_check(struct intel_crtc_state *crtc_state,
> >  			   struct intel_plane_state *plane_state)
> >  {
> > @@ -2400,6 +2448,8 @@ static int skl_plane_check(struct
> > intel_crtc_state *crtc_state,
> >  
> >  	check_protection(plane_state);
> >  
> > +	check_pixel_normalizer(plane_state);
> > +
> >  	/* HW only has 8 bits pixel precision, disable plane if
> > invisible */
> >  	if (!(plane_state->hw.alpha >> 8)) {
> >  		plane_state->uapi.visible = false;
> > diff --git
> > a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> > b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> > index 6fd4da9f63cf..651f3557b576 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> > @@ -580,6 +580,5 @@
> >  #define  
> > PLANE_PIXEL_NORMALIZE_ENABLE			REG_BIT(31)
> >  #define  
> > PLANE_PIXEL_NORMALIZE_NORM_FACTOR_MASK	REG_GENMASK(15, 0)
> >  #define  
> > PLANE_PIXEL_NORMALIZE_NORM_FACTOR(val)	REG_FIELD_PREP(PLANE_PIXEL_NORMALIZE_NORM_FACTOR_MASK,(val))
> > -#define  
> > PLANE_PIXEL_NORMALIZE_NORM_FACTOR_1_0		0x3c00
> >  
> >  #endif /* __SKL_UNIVERSAL_PLANE_REGS_H__ */
> > -- 
> > 2.43.0
> 

Re: [PATCH v3] drm/i915/display: fix the pixel normalization handling for xe3p_lpd

[Ville Syrjälä]

On Wed, Jan 28, 2026 at 07:38:48AM +0000, Govindapillai, Vinod wrote:
> On Tue, 2026-01-27 at 14:18 +0200, Ville Syrjälä wrote:
> > On Tue, Jan 27, 2026 at 01:13:45PM +0200, Vinod Govindapillai wrote:
> > > Pixel normalizer is enabled with normalization factor as 1.0 for
> > > FP16 formats in order to support FBC for those formats in xe3p_lpd.
> > > Previously pixel normalizer gets disabled during the plane disable
> > > routine. But there could be plane format settings without
> > > explicitly
> > > calling the plane disable in-between and we could endup keeping the
> > > pixel normalizer enabled for formats which we don't require that.
> > > This is causing crc mismatches in yuv formats and FIFO underruns in
> > > planar formats like NV12.
> > > 
> > > Fix this by updating the pixel normalizer configuration based on
> > > the
> > > pixel formats explicitly during the plane settings arm calls itself
> > > - enable it for FP16 and disable it for other formats in HDR
> > > capable
> > > planes. To avoid redundancies in these updates, normalization
> > > factor
> > > between old and new plane states are compared before the update.
> > > The
> > > function to check validity of the fp16 formats for fbc is now
> > > updated
> > > to return the normalization factor as 1.0 in case of fp16 formats
> > > and
> > > 0 in other cases.
> > 
> > This looks incredibly complex for just writing a single register.
> > I think it should be just somehting like:
> > 
> > static u32 pixel_normalizer_val()
> > {
> > 	if (!need_pixel_normalizer())
> > 		return 0;
> > 
> > 	return ENABLE | FACTOR;
> > }
> > 
> > plane_update(..)
> > {
> > 	...
> > 	if (HAS_PIXEL_NORMALIZER())
> > 		write(PIXEL_NOFMRALIZER, pixel_normalizer_val())
> > 	...
> > }
> > 
> > plane_disable()
> > {
> > 	...
> > 	// do we even need to disable it for disabled planes?
> > 	if (HAS_PIXEL_NORMALIZER())
> > 		write(PIXEL_NORMALIZER, 0);
> > 	...
> > }
> 
> 
> Okay. Thanks for the suggestion. This is basically similar to the
> revision 1 of this patch!
> 
> But before sending another revision, I would like to clarify about
> HAS_PIXEL_NORMALIZER(). Pixel normalizer is there even in earlier
> versions. We are using this mainly for the FP16 case. So do you agree
> to use HAS_FP16_FORMATS instead of HAS_PIXEL_NORMALIZER?

If the normalizer is there then we want to program it.

> 
> Also normalizer is available for the HDR planes, so will have to use 
> 
> if (HAS_FP16_FORMATS(display) && skl_plane_has_fbc(display, fbc_id,
> plane->id))

plane_has_pixel_normalizer()
{
	return HAS_PIXEL_NORMALIZER() && plane_is_hdr();
}

> 	write(PIXEL_NORMALIZER, val / 0)
> 
> 
> BR
> Vinod
> 
> > 
> > > 
> > > v2: avoid redundant pixel normalization setting updates
> > > 
> > > v3: moved the normalization factor definition to intel_fbc.c and
> > > some
> > >     updates to comments
> > > 
> > > Fixes: 5298eea7ed20 ("drm/i915/xe3p_lpd: use pixel normalizer for
> > > fp16 formats for FBC")
> > > Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> > > ---
> > >  .../drm/i915/display/intel_display_device.h   |  1 +
> > >  .../drm/i915/display/intel_display_types.h    |  8 ++
> > >  drivers/gpu/drm/i915/display/intel_fbc.c      | 19 ++++-
> > >  drivers/gpu/drm/i915/display/intel_fbc.h      |  4 +-
> > >  .../drm/i915/display/skl_universal_plane.c    | 82
> > > +++++++++++++++----
> > >  .../i915/display/skl_universal_plane_regs.h   |  1 -
> > >  6 files changed, 92 insertions(+), 23 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
> > > b/drivers/gpu/drm/i915/display/intel_display_device.h
> > > index 6c74d6b0cc48..126aa1eeeb6d 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> > > @@ -175,6 +175,7 @@ struct intel_display_platforms {
> > >  #define HAS_DSC_MST(__display)		(DISPLAY_VER(__display) >=
> > > 12 && HAS_DSC(__display))
> > >  #define
> > > HAS_FBC(__display)		(DISPLAY_RUNTIME_INFO(__display)->fbc_mask != 0)
> > >  #define HAS_FBC_DIRTY_RECT(__display)	(DISPLAY_VER(__display) >=
> > > 30)
> > > +#define
> > > HAS_FBC_FP16_FORMATS(__display)	(DISPLAY_VER(__display) >= 35)
> > >  #define HAS_FBC_SYS_CACHE(__display)	(DISPLAY_VER(__display) >=
> > > 35 && !(__display)->platform.dgfx)
> > >  #define
> > > HAS_FPGA_DBG_UNCLAIMED(__display)	(DISPLAY_INFO(__display)->has_fpga_dbg)
> > >  #define HAS_FW_BLC(__display)		(DISPLAY_VER(__display) >=
> > > 3)
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index e6298279dc89..92bce232b2c5 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -686,6 +686,14 @@ struct intel_plane_state {
> > >  	unsigned long flags;
> > >  #define PLANE_HAS_FENCE BIT(0)
> > >  
> > > +	/* xe3p_lpd+ */
> > > +	struct {
> > > +		/* In half-precision floating-point format. 0x3c00
> > > (1.0) for fp16 formats */
> > > +		unsigned int factor;
> > > +		/* update is needed if factor differs between old
> > > and new plane states */
> > > +		bool needs_update;
> > > +	} pixel_normalizer;
> > > +
> > >  	struct intel_fb_view view;
> > >  
> > >  	/* for legacy cursor fb unpin */
> > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > index 1f3f5237a1c2..f9474e7741c8 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > @@ -71,6 +71,9 @@
> > >  
> > >  #define FBC_SYS_CACHE_ID_NONE	I915_MAX_FBCS
> > >  
> > > +/* Pixel normalization factor 1.0 in half-precision floating-point
> > > format */
> > > +#define NORM_FACTOR_1_0_IN_HALF_PRECISION_FP		0x3c00
> > > +
> > >  struct intel_fbc_funcs {
> > >  	void (*activate)(struct intel_fbc *fbc);
> > >  	void (*deactivate)(struct intel_fbc *fbc);
> > > @@ -1215,13 +1218,21 @@ static bool
> > > xe3p_lpd_fbc_pixel_format_is_valid(const struct intel_plane_state
> > > *p
> > >  	}
> > >  }
> > >  
> > > -bool
> > > -intel_fbc_is_enable_pixel_normalizer(const struct
> > > intel_plane_state *plane_state)
> > > +unsigned int
> > > +intel_fbc_normalization_factor(const struct intel_plane_state
> > > *plane_state)
> > >  {
> > >  	struct intel_display *display =
> > > to_intel_display(plane_state);
> > >  
> > > -	return DISPLAY_VER(display) >= 35 &&
> > > -	       xe3p_lpd_fbc_fp16_format_is_valid(plane_state);
> > > +	/*
> > > +	 * In order to have FBC for fp16 formats pixel normalizer
> > > block must be
> > > +	 * active. For FP16 formats, use normalization factor as
> > > 1.0 and enable
> > > +	 * the block.
> > > +	 */
> > > +	if (HAS_FBC_FP16_FORMATS(display) &&
> > > +	    xe3p_lpd_fbc_fp16_format_is_valid(plane_state))
> > > +		return NORM_FACTOR_1_0_IN_HALF_PRECISION_FP;
> > > +
> > > +	return 0;
> > >  }
> > >  
> > >  static bool pixel_format_is_valid(const struct intel_plane_state
> > > *plane_state)
> > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h
> > > b/drivers/gpu/drm/i915/display/intel_fbc.h
> > > index f0255ddae2b6..b5888e98a659 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_fbc.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.h
> > > @@ -56,7 +56,7 @@ void intel_fbc_prepare_dirty_rect(struct
> > > intel_atomic_state *state,
> > >  				  struct intel_crtc *crtc);
> > >  void intel_fbc_dirty_rect_update_noarm(struct intel_dsb *dsb,
> > >  				       struct intel_plane *plane);
> > > -bool
> > > -intel_fbc_is_enable_pixel_normalizer(const struct
> > > intel_plane_state *plane_state);
> > > +unsigned int
> > > +intel_fbc_normalization_factor(const struct intel_plane_state
> > > *plane_state);
> > >  
> > >  #endif /* __INTEL_FBC_H__ */
> > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > index b3d41705448a..05c227913b8d 100644
> > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > @@ -891,20 +891,49 @@ static void
> > > icl_plane_disable_sel_fetch_arm(struct intel_dsb *dsb,
> > >  	intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_CTL(pipe,
> > > plane->id), 0);
> > >  }
> > >  
> > > -static void x3p_lpd_plane_update_pixel_normalizer(struct intel_dsb
> > > *dsb,
> > > -						  struct
> > > intel_plane *plane,
> > > -						  bool enable)
> > > +static void xe3p_lpd_plane_disable_pixel_normalizer(struct
> > > intel_dsb *dsb,
> > > +						    struct
> > > intel_plane *plane)
> > >  {
> > >  	struct intel_display *display = to_intel_display(plane);
> > >  	enum intel_fbc_id fbc_id = skl_fbc_id_for_pipe(plane-
> > > >pipe);
> > > -	u32 val;
> > > +	const struct intel_plane_state *plane_state =
> > > +		to_intel_plane_state(plane->base.state);
> > > +
> > > +	if (!HAS_FBC_FP16_FORMATS(display))
> > > +		return;
> > > +
> > > +	if (!skl_plane_has_fbc(display, fbc_id, plane->id))
> > > +		return;
> > > +
> > > +	if (!plane_state->pixel_normalizer.factor)
> > > +		return;
> > > +
> > > +	intel_de_write_dsb(display, dsb,
> > > +			   PLANE_PIXEL_NORMALIZE(plane->pipe,
> > > plane->id), 0);
> > > +}
> > > +
> > > +static void xe3p_lpd_plane_update_pixel_normalizer(struct
> > > intel_dsb *dsb,
> > > +						   struct
> > > intel_plane *plane)
> > > +{
> > > +	struct intel_display *display = to_intel_display(plane);
> > > +	enum intel_fbc_id fbc_id = skl_fbc_id_for_pipe(plane-
> > > >pipe);
> > > +	const struct intel_plane_state *plane_state =
> > > +		to_intel_plane_state(plane->base.state);
> > > +	u32 val = 0;
> > > +
> > > +	if (!HAS_FBC_FP16_FORMATS(display))
> > > +		return;
> > >  
> > > -	/* Only HDR planes have pixel normalizer and don't matter
> > > if no FBC */
> > > +	/* Only HDR planes have pixel normalizer and don't matter
> > > if FBC is fused off */
> > >  	if (!skl_plane_has_fbc(display, fbc_id, plane->id))
> > >  		return;
> > >  
> > > -	val = enable ?
> > > PLANE_PIXEL_NORMALIZE_NORM_FACTOR(PLANE_PIXEL_NORMALIZE_NORM_FACTOR
> > > _1_0) |
> > > -		       PLANE_PIXEL_NORMALIZE_ENABLE : 0;
> > > +	if (!plane_state->pixel_normalizer.needs_update)
> > > +		return;
> > > +
> > > +	if (plane_state->pixel_normalizer.factor)
> > > +		val =
> > > PLANE_PIXEL_NORMALIZE_NORM_FACTOR(plane_state-
> > > >pixel_normalizer.factor) |
> > > +		      PLANE_PIXEL_NORMALIZE_ENABLE;
> > >  
> > >  	intel_de_write_dsb(display, dsb,
> > >  			   PLANE_PIXEL_NORMALIZE(plane->pipe,
> > > plane->id), val);
> > > @@ -926,8 +955,7 @@ icl_plane_disable_arm(struct intel_dsb *dsb,
> > >  
> > >  	icl_plane_disable_sel_fetch_arm(dsb, plane, crtc_state);
> > >  
> > > -	if (DISPLAY_VER(display) >= 35)
> > > -		x3p_lpd_plane_update_pixel_normalizer(dsb, plane,
> > > false);
> > > +	xe3p_lpd_plane_disable_pixel_normalizer(dsb, plane);
> > >  
> > >  	intel_de_write_dsb(display, dsb, PLANE_CTL(pipe,
> > > plane_id), 0);
> > >  	intel_de_write_dsb(display, dsb, PLANE_SURF(pipe,
> > > plane_id), 0);
> > > @@ -1674,13 +1702,7 @@ icl_plane_update_arm(struct intel_dsb *dsb,
> > >  
> > >  	intel_color_plane_commit_arm(dsb, plane_state);
> > >  
> > > -	/*
> > > -	 * In order to have FBC for fp16 formats pixel normalizer
> > > block must be
> > > -	 * active. Check if pixel normalizer block need to be
> > > enabled for FBC.
> > > -	 * If needed, use normalization factor as 1.0 and enable
> > > the block.
> > > -	 */
> > > -	if (intel_fbc_is_enable_pixel_normalizer(plane_state))
> > > -		x3p_lpd_plane_update_pixel_normalizer(dsb, plane,
> > > true);
> > > +	xe3p_lpd_plane_update_pixel_normalizer(dsb, plane);
> > >  
> > >  	/*
> > >  	 * The control register self-arms if the plane was
> > > previously
> > > @@ -2350,6 +2372,32 @@ static void clip_damage(struct
> > > intel_plane_state *plane_state)
> > >  	drm_rect_intersect(damage, &src);
> > >  }
> > >  
> > > +static void check_pixel_normalizer(struct intel_plane_state
> > > *plane_state)
> > > +{
> > > +	struct intel_display *display =
> > > to_intel_display(plane_state);
> > > +	struct intel_plane *plane = to_intel_plane(plane_state-
> > > >uapi.plane);
> > > +	struct intel_atomic_state *state =
> > > +		to_intel_atomic_state(plane_state->uapi.state);
> > > +	const struct intel_plane_state *old_plane_state =
> > > +		intel_atomic_get_old_plane_state(state, plane);
> > > +
> > > +	if (!HAS_FBC_FP16_FORMATS(display))
> > > +		return;
> > > +
> > > +	plane_state->pixel_normalizer.factor =
> > > +		intel_fbc_normalization_factor(plane_state);
> > > +
> > > +	/*
> > > +	 * In case of no old state to compare, better to force
> > > update the pixel
> > > +	 * normalizer settings.
> > > +	 */
> > > +	plane_state->pixel_normalizer.needs_update = true;
> > > +	if (old_plane_state && old_plane_state->hw.fb)
> > > +		plane_state->pixel_normalizer.needs_update =
> > > +			plane_state->pixel_normalizer.factor !=
> > > +			intel_fbc_normalization_factor(old_plane_s
> > > tate);
> > > +}
> > > +
> > >  static int skl_plane_check(struct intel_crtc_state *crtc_state,
> > >  			   struct intel_plane_state *plane_state)
> > >  {
> > > @@ -2400,6 +2448,8 @@ static int skl_plane_check(struct
> > > intel_crtc_state *crtc_state,
> > >  
> > >  	check_protection(plane_state);
> > >  
> > > +	check_pixel_normalizer(plane_state);
> > > +
> > >  	/* HW only has 8 bits pixel precision, disable plane if
> > > invisible */
> > >  	if (!(plane_state->hw.alpha >> 8)) {
> > >  		plane_state->uapi.visible = false;
> > > diff --git
> > > a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> > > b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> > > index 6fd4da9f63cf..651f3557b576 100644
> > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> > > @@ -580,6 +580,5 @@
> > >  #define  
> > > PLANE_PIXEL_NORMALIZE_ENABLE			REG_BIT(31)
> > >  #define  
> > > PLANE_PIXEL_NORMALIZE_NORM_FACTOR_MASK	REG_GENMASK(15, 0)
> > >  #define  
> > > PLANE_PIXEL_NORMALIZE_NORM_FACTOR(val)	REG_FIELD_PREP(PLANE_PIXEL_NORMALIZE_NORM_FACTOR_MASK,(val))
> > > -#define  
> > > PLANE_PIXEL_NORMALIZE_NORM_FACTOR_1_0		0x3c00
> > >  
> > >  #endif /* __SKL_UNIVERSAL_PLANE_REGS_H__ */
> > > -- 
> > > 2.43.0
> > 
> 

-- 
Ville Syrjälä
Intel

✓ CI.KUnit: success for drm/i915/display: fix the pixel normalization handling for xe3p_lpd (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/display: fix the pixel normalization handling for xe3p_lpd (rev3)
URL   : https://patchwork.freedesktop.org/series/160254/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[10:59:02] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:59:07] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[10:59:46] Starting KUnit Kernel (1/1)...
[10:59:46] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:59:46] ================== guc_buf (11 subtests) ===================
[10:59:46] [PASSED] test_smallest
[10:59:46] [PASSED] test_largest
[10:59:46] [PASSED] test_granular
[10:59:46] [PASSED] test_unique
[10:59:46] [PASSED] test_overlap
[10:59:46] [PASSED] test_reusable
[10:59:46] [PASSED] test_too_big
[10:59:46] [PASSED] test_flush
[10:59:46] [PASSED] test_lookup
[10:59:46] [PASSED] test_data
[10:59:46] [PASSED] test_class
[10:59:46] ===================== [PASSED] guc_buf =====================
[10:59:46] =================== guc_dbm (7 subtests) ===================
[10:59:46] [PASSED] test_empty
[10:59:46] [PASSED] test_default
[10:59:46] ======================== test_size  ========================
[10:59:46] [PASSED] 4
[10:59:46] [PASSED] 8
[10:59:46] [PASSED] 32
[10:59:46] [PASSED] 256
[10:59:46] ==================== [PASSED] test_size ====================
[10:59:46] ======================= test_reuse  ========================
[10:59:46] [PASSED] 4
[10:59:46] [PASSED] 8
[10:59:46] [PASSED] 32
[10:59:46] [PASSED] 256
[10:59:46] =================== [PASSED] test_reuse ====================
[10:59:46] =================== test_range_overlap  ====================
[10:59:46] [PASSED] 4
[10:59:46] [PASSED] 8
[10:59:46] [PASSED] 32
[10:59:46] [PASSED] 256
[10:59:46] =============== [PASSED] test_range_overlap ================
[10:59:46] =================== test_range_compact  ====================
[10:59:46] [PASSED] 4
[10:59:46] [PASSED] 8
[10:59:46] [PASSED] 32
[10:59:46] [PASSED] 256
[10:59:46] =============== [PASSED] test_range_compact ================
[10:59:46] ==================== test_range_spare  =====================
[10:59:46] [PASSED] 4
[10:59:46] [PASSED] 8
[10:59:46] [PASSED] 32
[10:59:46] [PASSED] 256
[10:59:46] ================ [PASSED] test_range_spare =================
[10:59:46] ===================== [PASSED] guc_dbm =====================
[10:59:46] =================== guc_idm (6 subtests) ===================
[10:59:46] [PASSED] bad_init
[10:59:46] [PASSED] no_init
[10:59:46] [PASSED] init_fini
[10:59:46] [PASSED] check_used
[10:59:46] [PASSED] check_quota
[10:59:46] [PASSED] check_all
[10:59:46] ===================== [PASSED] guc_idm =====================
[10:59:46] ================== no_relay (3 subtests) ===================
[10:59:46] [PASSED] xe_drops_guc2pf_if_not_ready
[10:59:46] [PASSED] xe_drops_guc2vf_if_not_ready
[10:59:46] [PASSED] xe_rejects_send_if_not_ready
[10:59:46] ==================== [PASSED] no_relay =====================
[10:59:46] ================== pf_relay (14 subtests) ==================
[10:59:46] [PASSED] pf_rejects_guc2pf_too_short
[10:59:46] [PASSED] pf_rejects_guc2pf_too_long
[10:59:46] [PASSED] pf_rejects_guc2pf_no_payload
[10:59:46] [PASSED] pf_fails_no_payload
[10:59:46] [PASSED] pf_fails_bad_origin
[10:59:46] [PASSED] pf_fails_bad_type
[10:59:46] [PASSED] pf_txn_reports_error
[10:59:46] [PASSED] pf_txn_sends_pf2guc
[10:59:46] [PASSED] pf_sends_pf2guc
[10:59:46] [SKIPPED] pf_loopback_nop
[10:59:46] [SKIPPED] pf_loopback_echo
[10:59:46] [SKIPPED] pf_loopback_fail
[10:59:46] [SKIPPED] pf_loopback_busy
[10:59:46] [SKIPPED] pf_loopback_retry
[10:59:46] ==================== [PASSED] pf_relay =====================
[10:59:46] ================== vf_relay (3 subtests) ===================
[10:59:46] [PASSED] vf_rejects_guc2vf_too_short
[10:59:46] [PASSED] vf_rejects_guc2vf_too_long
[10:59:46] [PASSED] vf_rejects_guc2vf_no_payload
[10:59:46] ==================== [PASSED] vf_relay =====================
[10:59:46] ================ pf_gt_config (6 subtests) =================
[10:59:46] [PASSED] fair_contexts_1vf
[10:59:46] [PASSED] fair_doorbells_1vf
[10:59:46] [PASSED] fair_ggtt_1vf
[10:59:46] ====================== fair_contexts  ======================
[10:59:46] [PASSED] 1 VF
[10:59:46] [PASSED] 2 VFs
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[10:59:46] [PASSED] 63 VFs
[10:59:46] ================== [PASSED] fair_contexts ==================
[10:59:46] ===================== fair_doorbells  ======================
[10:59:46] [PASSED] 1 VF
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[10:59:46] [PASSED] 62 VFs
[10:59:46] [PASSED] 63 VFs
[10:59:46] ================= [PASSED] fair_doorbells ==================
[10:59:46] ======================== fair_ggtt  ========================
[10:59:46] [PASSED] 1 VF
[10:59:46] [PASSED] 2 VFs
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[10:59:46] [PASSED] 62 VFs
[10:59:46] [PASSED] 63 VFs
[10:59:46] ==================== [PASSED] fair_ggtt ====================
[10:59:46] ================== [PASSED] pf_gt_config ===================
[10:59:46] ===================== lmtt (1 subtest) =====================
[10:59:46] ======================== test_ops  =========================
[10:59:46] [PASSED] 2-level
[10:59:46] [PASSED] multi-level
[10:59:46] ==================== [PASSED] test_ops =====================
[10:59:46] ====================== [PASSED] lmtt =======================
[10:59:46] ================= pf_service (11 subtests) =================
[10:59:46] [PASSED] pf_negotiate_any
[10:59:46] [PASSED] pf_negotiate_base_match
[10:59:46] [PASSED] pf_negotiate_base_newer
[10:59:46] [PASSED] pf_negotiate_base_next
[10:59:46] [SKIPPED] pf_negotiate_base_older
[10:59:46] [PASSED] pf_negotiate_base_prev
[10:59:46] [PASSED] pf_negotiate_latest_match
[10:59:46] [PASSED] pf_negotiate_latest_newer
[10:59:46] [PASSED] pf_negotiate_latest_next
[10:59:46] [SKIPPED] pf_negotiate_latest_older
[10:59:46] [SKIPPED] pf_negotiate_latest_prev
[10:59:46] =================== [PASSED] pf_service ====================
[10:59:46] ================= xe_guc_g2g (2 subtests) ==================
[10:59:46] ============== xe_live_guc_g2g_kunit_default  ==============
[10:59:46] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[10:59:46] ============== xe_live_guc_g2g_kunit_allmem  ===============
[10:59:46] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[10:59:46] =================== [SKIPPED] xe_guc_g2g ===================
[10:59:46] =================== xe_mocs (2 subtests) ===================
[10:59:46] ================ xe_live_mocs_kernel_kunit  ================
[10:59:46] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[10:59:46] ================ xe_live_mocs_reset_kunit  =================
[10:59:46] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[10:59:46] ==================== [SKIPPED] xe_mocs =====================
[10:59:46] ================= xe_migrate (2 subtests) ==================
[10:59:46] ================= xe_migrate_sanity_kunit  =================
[10:59:46] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[10:59:46] ================== xe_validate_ccs_kunit  ==================
[10:59:46] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[10:59:46] =================== [SKIPPED] xe_migrate ===================
[10:59:46] ================== xe_dma_buf (1 subtest) ==================
[10:59:46] ==================== xe_dma_buf_kunit  =====================
[10:59:46] ================ [SKIPPED] xe_dma_buf_kunit ================
[10:59:46] =================== [SKIPPED] xe_dma_buf ===================
[10:59:46] ================= xe_bo_shrink (1 subtest) =================
[10:59:46] =================== xe_bo_shrink_kunit  ====================
[10:59:46] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[10:59:46] ================== [SKIPPED] xe_bo_shrink ==================
[10:59:46] ==================== xe_bo (2 subtests) ====================
[10:59:46] ================== xe_ccs_migrate_kunit  ===================
[10:59:46] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[10:59:46] ==================== xe_bo_evict_kunit  ====================
[10:59:46] =============== [SKIPPED] xe_bo_evict_kunit ================
[10:59:46] ===================== [SKIPPED] xe_bo ======================
[10:59:46] ==================== args (13 subtests) ====================
[10:59:46] [PASSED] count_args_test
[10:59:46] [PASSED] call_args_example
[10:59:46] [PASSED] call_args_test
[10:59:46] [PASSED] drop_first_arg_example
[10:59:46] [PASSED] drop_first_arg_test
[10:59:46] [PASSED] first_arg_example
[10:59:46] [PASSED] first_arg_test
[10:59:46] [PASSED] last_arg_example
[10:59:46] [PASSED] last_arg_test
[10:59:46] [PASSED] pick_arg_example
[10:59:46] [PASSED] if_args_example
[10:59:46] [PASSED] if_args_test
[10:59:46] [PASSED] sep_comma_example
[10:59:46] ====================== [PASSED] args =======================
[10:59:46] =================== xe_pci (3 subtests) ====================
[10:59:46] ==================== check_graphics_ip  ====================
[10:59:46] [PASSED] 12.00 Xe_LP
[10:59:46] [PASSED] 12.10 Xe_LP+
[10:59:46] [PASSED] 12.55 Xe_HPG
[10:59:46] [PASSED] 12.60 Xe_HPC
[10:59:46] [PASSED] 12.70 Xe_LPG
[10:59:46] [PASSED] 12.71 Xe_LPG
[10:59:46] [PASSED] 12.74 Xe_LPG+
[10:59:46] [PASSED] 20.01 Xe2_HPG
[10:59:46] [PASSED] 20.02 Xe2_HPG
[10:59:46] [PASSED] 20.04 Xe2_LPG
[10:59:46] [PASSED] 30.00 Xe3_LPG
[10:59:46] [PASSED] 30.01 Xe3_LPG
[10:59:46] [PASSED] 30.03 Xe3_LPG
[10:59:46] [PASSED] 30.04 Xe3_LPG
[10:59:46] [PASSED] 30.05 Xe3_LPG
[10:59:46] [PASSED] 35.11 Xe3p_XPC
[10:59:46] ================ [PASSED] check_graphics_ip ================
[10:59:46] ===================== check_media_ip  ======================
[10:59:46] [PASSED] 12.00 Xe_M
[10:59:46] [PASSED] 12.55 Xe_HPM
[10:59:46] [PASSED] 13.00 Xe_LPM+
[10:59:46] [PASSED] 13.01 Xe2_HPM
[10:59:46] [PASSED] 20.00 Xe2_LPM
[10:59:46] [PASSED] 30.00 Xe3_LPM
[10:59:46] [PASSED] 30.02 Xe3_LPM
[10:59:46] [PASSED] 35.00 Xe3p_LPM
[10:59:46] [PASSED] 35.03 Xe3p_HPM
[10:59:46] ================= [PASSED] check_media_ip ==================
[10:59:46] =================== check_platform_desc  ===================
[10:59:46] [PASSED] 0x9A60 (TIGERLAKE)
[10:59:46] [PASSED] 0x9A68 (TIGERLAKE)
[10:59:46] [PASSED] 0x9A70 (TIGERLAKE)
[10:59:46] [PASSED] 0x9A40 (TIGERLAKE)
[10:59:46] [PASSED] 0x9A49 (TIGERLAKE)
[10:59:46] [PASSED] 0x9A59 (TIGERLAKE)
[10:59:46] [PASSED] 0x9A78 (TIGERLAKE)
[10:59:46] [PASSED] 0x9AC0 (TIGERLAKE)
[10:59:46] [PASSED] 0x9AC9 (TIGERLAKE)
[10:59:46] [PASSED] 0x9AD9 (TIGERLAKE)
[10:59:46] [PASSED] 0x9AF8 (TIGERLAKE)
[10:59:46] [PASSED] 0x4C80 (ROCKETLAKE)
[10:59:46] [PASSED] 0x4C8A (ROCKETLAKE)
[10:59:46] [PASSED] 0x4C8B (ROCKETLAKE)
[10:59:46] [PASSED] 0x4C8C (ROCKETLAKE)
[10:59:46] [PASSED] 0x4C90 (ROCKETLAKE)
[10:59:46] [PASSED] 0x4C9A (ROCKETLAKE)
[10:59:46] [PASSED] 0x4680 (ALDERLAKE_S)
[10:59:46] [PASSED] 0x4682 (ALDERLAKE_S)
[10:59:46] [PASSED] 0x4688 (ALDERLAKE_S)
[10:59:46] [PASSED] 0x468A (ALDERLAKE_S)
[10:59:46] [PASSED] 0x468B (ALDERLAKE_S)
[10:59:46] [PASSED] 0x4690 (ALDERLAKE_S)
[10:59:46] [PASSED] 0x4692 (ALDERLAKE_S)
[10:59:46] [PASSED] 0x4693 (ALDERLAKE_S)
[10:59:46] [PASSED] 0x46A0 (ALDERLAKE_P)
[10:59:46] [PASSED] 0x46A1 (ALDERLAKE_P)
[10:59:46] [PASSED] 0x46A2 (ALDERLAKE_P)
[10:59:46] [PASSED] 0x46A3 (ALDERLAKE_P)
[10:59:46] [PASSED] 0x46A6 (ALDERLAKE_P)
[10:59:46] [PASSED] 0x46A8 (ALDERLAKE_P)
[10:59:46] [PASSED] 0x46AA (ALDERLAKE_P)
[10:59:46] [PASSED] 0x462A (ALDERLAKE_P)
[10:59:46] [PASSED] 0x4626 (ALDERLAKE_P)
[10:59:46] [PASSED] 0x4628 (ALDERLAKE_P)
stty: 'standard input': Inappropriate ioctl for device
[10:59:46] [PASSED] 0x46B0 (ALDERLAKE_P)
[10:59:46] [PASSED] 0x46B1 (ALDERLAKE_P)
[10:59:46] [PASSED] 0x46B2 (ALDERLAKE_P)
[10:59:46] [PASSED] 0x46B3 (ALDERLAKE_P)
[10:59:46] [PASSED] 0x46C0 (ALDERLAKE_P)
[10:59:46] [PASSED] 0x46C1 (ALDERLAKE_P)
[10:59:46] [PASSED] 0x46C2 (ALDERLAKE_P)
[10:59:46] [PASSED] 0x46C3 (ALDERLAKE_P)
[10:59:46] [PASSED] 0x46D0 (ALDERLAKE_N)
[10:59:46] [PASSED] 0x46D1 (ALDERLAKE_N)
[10:59:46] [PASSED] 0x46D2 (ALDERLAKE_N)
[10:59:46] [PASSED] 0x46D3 (ALDERLAKE_N)
[10:59:46] [PASSED] 0x46D4 (ALDERLAKE_N)
[10:59:46] [PASSED] 0xA721 (ALDERLAKE_P)
[10:59:46] [PASSED] 0xA7A1 (ALDERLAKE_P)
[10:59:46] [PASSED] 0xA7A9 (ALDERLAKE_P)
[10:59:46] [PASSED] 0xA7AC (ALDERLAKE_P)
[10:59:46] [PASSED] 0xA7AD (ALDERLAKE_P)
[10:59:46] [PASSED] 0xA720 (ALDERLAKE_P)
[10:59:46] [PASSED] 0xA7A0 (ALDERLAKE_P)
[10:59:46] [PASSED] 0xA7A8 (ALDERLAKE_P)
[10:59:46] [PASSED] 0xA7AA (ALDERLAKE_P)
[10:59:46] [PASSED] 0xA7AB (ALDERLAKE_P)
[10:59:46] [PASSED] 0xA780 (ALDERLAKE_S)
[10:59:46] [PASSED] 0xA781 (ALDERLAKE_S)
[10:59:46] [PASSED] 0xA782 (ALDERLAKE_S)
[10:59:46] [PASSED] 0xA783 (ALDERLAKE_S)
[10:59:46] [PASSED] 0xA788 (ALDERLAKE_S)
[10:59:46] [PASSED] 0xA789 (ALDERLAKE_S)
[10:59:46] [PASSED] 0xA78A (ALDERLAKE_S)
[10:59:46] [PASSED] 0xA78B (ALDERLAKE_S)
[10:59:46] [PASSED] 0x4905 (DG1)
[10:59:46] [PASSED] 0x4906 (DG1)
[10:59:46] [PASSED] 0x4907 (DG1)
[10:59:46] [PASSED] 0x4908 (DG1)
[10:59:46] [PASSED] 0x4909 (DG1)
[10:59:46] [PASSED] 0x56C0 (DG2)
[10:59:46] [PASSED] 0x56C2 (DG2)
[10:59:46] [PASSED] 0x56C1 (DG2)
[10:59:46] [PASSED] 0x7D51 (METEORLAKE)
[10:59:46] [PASSED] 0x7DD1 (METEORLAKE)
[10:59:46] [PASSED] 0x7D41 (METEORLAKE)
[10:59:46] [PASSED] 0x7D67 (METEORLAKE)
[10:59:46] [PASSED] 0xB640 (METEORLAKE)
[10:59:46] [PASSED] 0x56A0 (DG2)
[10:59:46] [PASSED] 0x56A1 (DG2)
[10:59:46] [PASSED] 0x56A2 (DG2)
[10:59:46] [PASSED] 0x56BE (DG2)
[10:59:46] [PASSED] 0x56BF (DG2)
[10:59:46] [PASSED] 0x5690 (DG2)
[10:59:46] [PASSED] 0x5691 (DG2)
[10:59:46] [PASSED] 0x5692 (DG2)
[10:59:46] [PASSED] 0x56A5 (DG2)
[10:59:46] [PASSED] 0x56A6 (DG2)
[10:59:46] [PASSED] 0x56B0 (DG2)
[10:59:46] [PASSED] 0x56B1 (DG2)
[10:59:46] [PASSED] 0x56BA (DG2)
[10:59:46] [PASSED] 0x56BB (DG2)
[10:59:46] [PASSED] 0x56BC (DG2)
[10:59:46] [PASSED] 0x56BD (DG2)
[10:59:46] [PASSED] 0x5693 (DG2)
[10:59:46] [PASSED] 0x5694 (DG2)
[10:59:46] [PASSED] 0x5695 (DG2)
[10:59:46] [PASSED] 0x56A3 (DG2)
[10:59:46] [PASSED] 0x56A4 (DG2)
[10:59:46] [PASSED] 0x56B2 (DG2)
[10:59:46] [PASSED] 0x56B3 (DG2)
[10:59:46] [PASSED] 0x5696 (DG2)
[10:59:46] [PASSED] 0x5697 (DG2)
[10:59:46] [PASSED] 0xB69 (PVC)
[10:59:46] [PASSED] 0xB6E (PVC)
[10:59:46] [PASSED] 0xBD4 (PVC)
[10:59:46] [PASSED] 0xBD5 (PVC)
[10:59:46] [PASSED] 0xBD6 (PVC)
[10:59:46] [PASSED] 0xBD7 (PVC)
[10:59:46] [PASSED] 0xBD8 (PVC)
[10:59:46] [PASSED] 0xBD9 (PVC)
[10:59:46] [PASSED] 0xBDA (PVC)
[10:59:46] [PASSED] 0xBDB (PVC)
[10:59:46] [PASSED] 0xBE0 (PVC)
[10:59:46] [PASSED] 0xBE1 (PVC)
[10:59:46] [PASSED] 0xBE5 (PVC)
[10:59:46] [PASSED] 0x7D40 (METEORLAKE)
[10:59:46] [PASSED] 0x7D45 (METEORLAKE)
[10:59:46] [PASSED] 0x7D55 (METEORLAKE)
[10:59:46] [PASSED] 0x7D60 (METEORLAKE)
[10:59:46] [PASSED] 0x7DD5 (METEORLAKE)
[10:59:46] [PASSED] 0x6420 (LUNARLAKE)
[10:59:46] [PASSED] 0x64A0 (LUNARLAKE)
[10:59:46] [PASSED] 0x64B0 (LUNARLAKE)
[10:59:46] [PASSED] 0xE202 (BATTLEMAGE)
[10:59:46] [PASSED] 0xE209 (BATTLEMAGE)
[10:59:46] [PASSED] 0xE20B (BATTLEMAGE)
[10:59:46] [PASSED] 0xE20C (BATTLEMAGE)
[10:59:46] [PASSED] 0xE20D (BATTLEMAGE)
[10:59:46] [PASSED] 0xE210 (BATTLEMAGE)
[10:59:46] [PASSED] 0xE211 (BATTLEMAGE)
[10:59:46] [PASSED] 0xE212 (BATTLEMAGE)
[10:59:46] [PASSED] 0xE216 (BATTLEMAGE)
[10:59:46] [PASSED] 0xE220 (BATTLEMAGE)
[10:59:46] [PASSED] 0xE221 (BATTLEMAGE)
[10:59:46] [PASSED] 0xE222 (BATTLEMAGE)
[10:59:46] [PASSED] 0xE223 (BATTLEMAGE)
[10:59:46] [PASSED] 0xB080 (PANTHERLAKE)
[10:59:46] [PASSED] 0xB081 (PANTHERLAKE)
[10:59:46] [PASSED] 0xB082 (PANTHERLAKE)
[10:59:46] [PASSED] 0xB083 (PANTHERLAKE)
[10:59:46] [PASSED] 0xB084 (PANTHERLAKE)
[10:59:46] [PASSED] 0xB085 (PANTHERLAKE)
[10:59:46] [PASSED] 0xB086 (PANTHERLAKE)
[10:59:46] [PASSED] 0xB087 (PANTHERLAKE)
[10:59:46] [PASSED] 0xB08F (PANTHERLAKE)
[10:59:46] [PASSED] 0xB090 (PANTHERLAKE)
[10:59:46] [PASSED] 0xB0A0 (PANTHERLAKE)
[10:59:46] [PASSED] 0xB0B0 (PANTHERLAKE)
[10:59:46] [PASSED] 0xFD80 (PANTHERLAKE)
[10:59:46] [PASSED] 0xFD81 (PANTHERLAKE)
[10:59:46] [PASSED] 0xD740 (NOVALAKE_S)
[10:59:46] [PASSED] 0xD741 (NOVALAKE_S)
[10:59:46] [PASSED] 0xD742 (NOVALAKE_S)
[10:59:46] [PASSED] 0xD743 (NOVALAKE_S)
[10:59:46] [PASSED] 0xD744 (NOVALAKE_S)
[10:59:46] [PASSED] 0xD745 (NOVALAKE_S)
[10:59:46] [PASSED] 0x674C (CRESCENTISLAND)
[10:59:46] =============== [PASSED] check_platform_desc ===============
[10:59:46] ===================== [PASSED] xe_pci ======================
[10:59:46] =================== xe_rtp (2 subtests) ====================
[10:59:46] =============== xe_rtp_process_to_sr_tests  ================
[10:59:46] [PASSED] coalesce-same-reg
[10:59:46] [PASSED] no-match-no-add
[10:59:46] [PASSED] match-or
[10:59:46] [PASSED] match-or-xfail
[10:59:46] [PASSED] no-match-no-add-multiple-rules
[10:59:46] [PASSED] two-regs-two-entries
[10:59:46] [PASSED] clr-one-set-other
[10:59:46] [PASSED] set-field
[10:59:46] [PASSED] conflict-duplicate
[10:59:46] [PASSED] conflict-not-disjoint
[10:59:46] [PASSED] conflict-reg-type
[10:59:46] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[10:59:46] ================== xe_rtp_process_tests  ===================
[10:59:46] [PASSED] active1
[10:59:46] [PASSED] active2
[10:59:46] [PASSED] active-inactive
[10:59:46] [PASSED] inactive-active
[10:59:46] [PASSED] inactive-1st_or_active-inactive
[10:59:46] [PASSED] inactive-2nd_or_active-inactive
[10:59:46] [PASSED] inactive-last_or_active-inactive
[10:59:46] [PASSED] inactive-no_or_active-inactive
[10:59:46] ============== [PASSED] xe_rtp_process_tests ===============
[10:59:46] ===================== [PASSED] xe_rtp ======================
[10:59:46] ==================== xe_wa (1 subtest) =====================
[10:59:46] ======================== xe_wa_gt  =========================
[10:59:46] [PASSED] TIGERLAKE B0
[10:59:46] [PASSED] DG1 A0
[10:59:46] [PASSED] DG1 B0
[10:59:46] [PASSED] ALDERLAKE_S A0
[10:59:46] [PASSED] ALDERLAKE_S B0
[10:59:46] [PASSED] ALDERLAKE_S C0
[10:59:46] [PASSED] ALDERLAKE_S D0
[10:59:46] [PASSED] ALDERLAKE_P A0
[10:59:46] [PASSED] ALDERLAKE_P B0
[10:59:46] [PASSED] ALDERLAKE_P C0
[10:59:46] [PASSED] ALDERLAKE_S RPLS D0
[10:59:46] [PASSED] ALDERLAKE_P RPLU E0
[10:59:46] [PASSED] DG2 G10 C0
[10:59:46] [PASSED] DG2 G11 B1
[10:59:46] [PASSED] DG2 G12 A1
[10:59:46] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[10:59:46] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[10:59:46] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[10:59:46] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[10:59:46] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[10:59:46] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[10:59:46] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[10:59:46] ==================== [PASSED] xe_wa_gt =====================
[10:59:46] ====================== [PASSED] xe_wa ======================
[10:59:46] ============================================================
[10:59:46] Testing complete. Ran 512 tests: passed: 494, skipped: 18
[10:59:46] Elapsed time: 43.919s total, 4.272s configuring, 39.129s building, 0.499s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[10:59:46] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:59:48] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[11:00:20] Starting KUnit Kernel (1/1)...
[11:00:20] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:00:20] ============ drm_test_pick_cmdline (2 subtests) ============
[11:00:20] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[11:00:20] =============== drm_test_pick_cmdline_named  ===============
[11:00:20] [PASSED] NTSC
[11:00:20] [PASSED] NTSC-J
[11:00:20] [PASSED] PAL
[11:00:20] [PASSED] PAL-M
[11:00:20] =========== [PASSED] drm_test_pick_cmdline_named ===========
[11:00:20] ============== [PASSED] drm_test_pick_cmdline ==============
[11:00:20] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[11:00:20] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[11:00:20] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[11:00:20] =========== drm_validate_clone_mode (2 subtests) ===========
[11:00:20] ============== drm_test_check_in_clone_mode  ===============
[11:00:20] [PASSED] in_clone_mode
[11:00:20] [PASSED] not_in_clone_mode
[11:00:20] ========== [PASSED] drm_test_check_in_clone_mode ===========
[11:00:20] =============== drm_test_check_valid_clones  ===============
[11:00:20] [PASSED] not_in_clone_mode
[11:00:20] [PASSED] valid_clone
[11:00:20] [PASSED] invalid_clone
[11:00:20] =========== [PASSED] drm_test_check_valid_clones ===========
[11:00:20] ============= [PASSED] drm_validate_clone_mode =============
[11:00:20] ============= drm_validate_modeset (1 subtest) =============
[11:00:20] [PASSED] drm_test_check_connector_changed_modeset
[11:00:20] ============== [PASSED] drm_validate_modeset ===============
[11:00:20] ====== drm_test_bridge_get_current_state (2 subtests) ======
[11:00:20] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[11:00:20] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[11:00:20] ======== [PASSED] drm_test_bridge_get_current_state ========
[11:00:20] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[11:00:20] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[11:00:20] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[11:00:20] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[11:00:20] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[11:00:20] ============== drm_bridge_alloc (2 subtests) ===============
[11:00:20] [PASSED] drm_test_drm_bridge_alloc_basic
[11:00:20] [PASSED] drm_test_drm_bridge_alloc_get_put
[11:00:20] ================ [PASSED] drm_bridge_alloc =================
[11:00:20] ================== drm_buddy (9 subtests) ==================
[11:00:20] [PASSED] drm_test_buddy_alloc_limit
[11:00:20] [PASSED] drm_test_buddy_alloc_optimistic
[11:00:20] [PASSED] drm_test_buddy_alloc_pessimistic
[11:00:20] [PASSED] drm_test_buddy_alloc_pathological
[11:00:20] [PASSED] drm_test_buddy_alloc_contiguous
[11:00:20] [PASSED] drm_test_buddy_alloc_clear
[11:00:20] [PASSED] drm_test_buddy_alloc_range_bias
[11:00:20] [PASSED] drm_test_buddy_fragmentation_performance
[11:00:20] [PASSED] drm_test_buddy_alloc_exceeds_max_order
[11:00:20] ==================== [PASSED] drm_buddy ====================
[11:00:20] ============= drm_cmdline_parser (40 subtests) =============
[11:00:20] [PASSED] drm_test_cmdline_force_d_only
[11:00:20] [PASSED] drm_test_cmdline_force_D_only_dvi
[11:00:20] [PASSED] drm_test_cmdline_force_D_only_hdmi
[11:00:20] [PASSED] drm_test_cmdline_force_D_only_not_digital
[11:00:20] [PASSED] drm_test_cmdline_force_e_only
[11:00:20] [PASSED] drm_test_cmdline_res
[11:00:20] [PASSED] drm_test_cmdline_res_vesa
[11:00:20] [PASSED] drm_test_cmdline_res_vesa_rblank
[11:00:20] [PASSED] drm_test_cmdline_res_rblank
[11:00:20] [PASSED] drm_test_cmdline_res_bpp
[11:00:20] [PASSED] drm_test_cmdline_res_refresh
[11:00:20] [PASSED] drm_test_cmdline_res_bpp_refresh
[11:00:20] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[11:00:20] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[11:00:20] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[11:00:20] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[11:00:20] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[11:00:20] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[11:00:20] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[11:00:20] [PASSED] drm_test_cmdline_res_margins_force_on
[11:00:20] [PASSED] drm_test_cmdline_res_vesa_margins
[11:00:20] [PASSED] drm_test_cmdline_name
[11:00:20] [PASSED] drm_test_cmdline_name_bpp
[11:00:20] [PASSED] drm_test_cmdline_name_option
[11:00:20] [PASSED] drm_test_cmdline_name_bpp_option
[11:00:20] [PASSED] drm_test_cmdline_rotate_0
[11:00:20] [PASSED] drm_test_cmdline_rotate_90
[11:00:20] [PASSED] drm_test_cmdline_rotate_180
[11:00:20] [PASSED] drm_test_cmdline_rotate_270
[11:00:20] [PASSED] drm_test_cmdline_hmirror
[11:00:20] [PASSED] drm_test_cmdline_vmirror
[11:00:20] [PASSED] drm_test_cmdline_margin_options
[11:00:20] [PASSED] drm_test_cmdline_multiple_options
[11:00:20] [PASSED] drm_test_cmdline_bpp_extra_and_option
[11:00:20] [PASSED] drm_test_cmdline_extra_and_option
[11:00:20] [PASSED] drm_test_cmdline_freestanding_options
[11:00:20] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[11:00:20] [PASSED] drm_test_cmdline_panel_orientation
[11:00:20] ================ drm_test_cmdline_invalid  =================
[11:00:20] [PASSED] margin_only
[11:00:20] [PASSED] interlace_only
[11:00:20] [PASSED] res_missing_x
[11:00:20] [PASSED] res_missing_y
[11:00:20] [PASSED] res_bad_y
[11:00:20] [PASSED] res_missing_y_bpp
[11:00:20] [PASSED] res_bad_bpp
[11:00:20] [PASSED] res_bad_refresh
[11:00:20] [PASSED] res_bpp_refresh_force_on_off
[11:00:20] [PASSED] res_invalid_mode
[11:00:20] [PASSED] res_bpp_wrong_place_mode
[11:00:20] [PASSED] name_bpp_refresh
[11:00:20] [PASSED] name_refresh
[11:00:20] [PASSED] name_refresh_wrong_mode
[11:00:20] [PASSED] name_refresh_invalid_mode
[11:00:20] [PASSED] rotate_multiple
[11:00:20] [PASSED] rotate_invalid_val
[11:00:20] [PASSED] rotate_truncated
[11:00:20] [PASSED] invalid_option
[11:00:20] [PASSED] invalid_tv_option
[11:00:20] [PASSED] truncated_tv_option
[11:00:20] ============ [PASSED] drm_test_cmdline_invalid =============
[11:00:20] =============== drm_test_cmdline_tv_options  ===============
[11:00:20] [PASSED] NTSC
[11:00:20] [PASSED] NTSC_443
[11:00:20] [PASSED] NTSC_J
[11:00:20] [PASSED] PAL
[11:00:20] [PASSED] PAL_M
[11:00:20] [PASSED] PAL_N
[11:00:20] [PASSED] SECAM
[11:00:20] [PASSED] MONO_525
[11:00:20] [PASSED] MONO_625
[11:00:20] =========== [PASSED] drm_test_cmdline_tv_options ===========
[11:00:20] =============== [PASSED] drm_cmdline_parser ================
[11:00:20] ========== drmm_connector_hdmi_init (20 subtests) ==========
[11:00:20] [PASSED] drm_test_connector_hdmi_init_valid
[11:00:20] [PASSED] drm_test_connector_hdmi_init_bpc_8
[11:00:20] [PASSED] drm_test_connector_hdmi_init_bpc_10
[11:00:20] [PASSED] drm_test_connector_hdmi_init_bpc_12
[11:00:20] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[11:00:20] [PASSED] drm_test_connector_hdmi_init_bpc_null
[11:00:20] [PASSED] drm_test_connector_hdmi_init_formats_empty
[11:00:20] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[11:00:20] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[11:00:20] [PASSED] supported_formats=0x9 yuv420_allowed=1
[11:00:20] [PASSED] supported_formats=0x9 yuv420_allowed=0
[11:00:20] [PASSED] supported_formats=0x3 yuv420_allowed=1
[11:00:20] [PASSED] supported_formats=0x3 yuv420_allowed=0
[11:00:20] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[11:00:20] [PASSED] drm_test_connector_hdmi_init_null_ddc
[11:00:20] [PASSED] drm_test_connector_hdmi_init_null_product
[11:00:20] [PASSED] drm_test_connector_hdmi_init_null_vendor
[11:00:20] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[11:00:20] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[11:00:20] [PASSED] drm_test_connector_hdmi_init_product_valid
[11:00:20] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[11:00:20] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[11:00:20] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[11:00:20] ========= drm_test_connector_hdmi_init_type_valid  =========
[11:00:20] [PASSED] HDMI-A
[11:00:20] [PASSED] HDMI-B
[11:00:20] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[11:00:20] ======== drm_test_connector_hdmi_init_type_invalid  ========
[11:00:20] [PASSED] Unknown
[11:00:20] [PASSED] VGA
[11:00:20] [PASSED] DVI-I
[11:00:20] [PASSED] DVI-D
[11:00:20] [PASSED] DVI-A
[11:00:20] [PASSED] Composite
[11:00:20] [PASSED] SVIDEO
[11:00:20] [PASSED] LVDS
[11:00:20] [PASSED] Component
[11:00:20] [PASSED] DIN
[11:00:20] [PASSED] DP
[11:00:20] [PASSED] TV
[11:00:20] [PASSED] eDP
[11:00:20] [PASSED] Virtual
[11:00:20] [PASSED] DSI
[11:00:20] [PASSED] DPI
[11:00:20] [PASSED] Writeback
[11:00:20] [PASSED] SPI
[11:00:20] [PASSED] USB
[11:00:20] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[11:00:20] ============ [PASSED] drmm_connector_hdmi_init =============
[11:00:20] ============= drmm_connector_init (3 subtests) =============
[11:00:20] [PASSED] drm_test_drmm_connector_init
[11:00:20] [PASSED] drm_test_drmm_connector_init_null_ddc
[11:00:20] ========= drm_test_drmm_connector_init_type_valid  =========
[11:00:20] [PASSED] Unknown
[11:00:20] [PASSED] VGA
[11:00:20] [PASSED] DVI-I
[11:00:20] [PASSED] DVI-D
[11:00:20] [PASSED] DVI-A
[11:00:20] [PASSED] Composite
[11:00:20] [PASSED] SVIDEO
[11:00:20] [PASSED] LVDS
[11:00:20] [PASSED] Component
[11:00:20] [PASSED] DIN
[11:00:20] [PASSED] DP
[11:00:20] [PASSED] HDMI-A
[11:00:20] [PASSED] HDMI-B
[11:00:20] [PASSED] TV
[11:00:20] [PASSED] eDP
[11:00:20] [PASSED] Virtual
[11:00:20] [PASSED] DSI
[11:00:20] [PASSED] DPI
[11:00:20] [PASSED] Writeback
[11:00:20] [PASSED] SPI
[11:00:20] [PASSED] USB
[11:00:20] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[11:00:20] =============== [PASSED] drmm_connector_init ===============
[11:00:20] ========= drm_connector_dynamic_init (6 subtests) ==========
[11:00:20] [PASSED] drm_test_drm_connector_dynamic_init
[11:00:20] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[11:00:20] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[11:00:20] [PASSED] drm_test_drm_connector_dynamic_init_properties
[11:00:20] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[11:00:20] [PASSED] Unknown
[11:00:20] [PASSED] VGA
[11:00:20] [PASSED] DVI-I
[11:00:20] [PASSED] DVI-D
[11:00:20] [PASSED] DVI-A
[11:00:20] [PASSED] Composite
[11:00:20] [PASSED] SVIDEO
[11:00:20] [PASSED] LVDS
[11:00:20] [PASSED] Component
[11:00:20] [PASSED] DIN
[11:00:20] [PASSED] DP
[11:00:20] [PASSED] HDMI-A
[11:00:20] [PASSED] HDMI-B
[11:00:20] [PASSED] TV
[11:00:20] [PASSED] eDP
[11:00:20] [PASSED] Virtual
[11:00:20] [PASSED] DSI
[11:00:20] [PASSED] DPI
[11:00:20] [PASSED] Writeback
[11:00:20] [PASSED] SPI
[11:00:20] [PASSED] USB
[11:00:20] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[11:00:20] ======== drm_test_drm_connector_dynamic_init_name  =========
[11:00:20] [PASSED] Unknown
[11:00:20] [PASSED] VGA
[11:00:20] [PASSED] DVI-I
[11:00:20] [PASSED] DVI-D
[11:00:20] [PASSED] DVI-A
[11:00:20] [PASSED] Composite
[11:00:20] [PASSED] SVIDEO
[11:00:20] [PASSED] LVDS
[11:00:20] [PASSED] Component
[11:00:20] [PASSED] DIN
[11:00:20] [PASSED] DP
[11:00:20] [PASSED] HDMI-A
[11:00:20] [PASSED] HDMI-B
[11:00:20] [PASSED] TV
[11:00:20] [PASSED] eDP
[11:00:20] [PASSED] Virtual
[11:00:20] [PASSED] DSI
[11:00:20] [PASSED] DPI
[11:00:20] [PASSED] Writeback
[11:00:20] [PASSED] SPI
[11:00:20] [PASSED] USB
[11:00:20] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[11:00:20] =========== [PASSED] drm_connector_dynamic_init ============
[11:00:20] ==== drm_connector_dynamic_register_early (4 subtests) =====
[11:00:20] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[11:00:20] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[11:00:20] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[11:00:20] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[11:00:20] ====== [PASSED] drm_connector_dynamic_register_early =======
[11:00:20] ======= drm_connector_dynamic_register (7 subtests) ========
[11:00:20] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[11:00:20] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[11:00:20] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[11:00:20] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[11:00:20] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[11:00:20] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[11:00:20] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[11:00:20] ========= [PASSED] drm_connector_dynamic_register ==========
[11:00:20] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[11:00:20] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[11:00:20] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[11:00:20] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[11:00:20] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[11:00:20] ========== drm_test_get_tv_mode_from_name_valid  ===========
[11:00:20] [PASSED] NTSC
[11:00:20] [PASSED] NTSC-443
[11:00:20] [PASSED] NTSC-J
[11:00:20] [PASSED] PAL
[11:00:20] [PASSED] PAL-M
[11:00:20] [PASSED] PAL-N
[11:00:20] [PASSED] SECAM
[11:00:20] [PASSED] Mono
[11:00:20] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[11:00:20] [PASSED] drm_test_get_tv_mode_from_name_truncated
[11:00:20] ============ [PASSED] drm_get_tv_mode_from_name ============
[11:00:20] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[11:00:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[11:00:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[11:00:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[11:00:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[11:00:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[11:00:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[11:00:20] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[11:00:20] [PASSED] VIC 96
[11:00:20] [PASSED] VIC 97
[11:00:20] [PASSED] VIC 101
[11:00:20] [PASSED] VIC 102
[11:00:20] [PASSED] VIC 106
[11:00:20] [PASSED] VIC 107
[11:00:20] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[11:00:20] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[11:00:20] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[11:00:20] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[11:00:20] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[11:00:20] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[11:00:20] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[11:00:20] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[11:00:20] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[11:00:20] [PASSED] Automatic
[11:00:20] [PASSED] Full
[11:00:20] [PASSED] Limited 16:235
[11:00:20] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[11:00:20] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[11:00:20] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[11:00:20] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[11:00:20] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[11:00:20] [PASSED] RGB
[11:00:20] [PASSED] YUV 4:2:0
[11:00:20] [PASSED] YUV 4:2:2
[11:00:20] [PASSED] YUV 4:4:4
[11:00:20] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[11:00:20] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[11:00:20] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[11:00:20] ============= drm_damage_helper (21 subtests) ==============
[11:00:20] [PASSED] drm_test_damage_iter_no_damage
[11:00:20] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[11:00:20] [PASSED] drm_test_damage_iter_no_damage_src_moved
[11:00:20] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[11:00:20] [PASSED] drm_test_damage_iter_no_damage_not_visible
[11:00:20] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[11:00:20] [PASSED] drm_test_damage_iter_no_damage_no_fb
[11:00:20] [PASSED] drm_test_damage_iter_simple_damage
[11:00:20] [PASSED] drm_test_damage_iter_single_damage
[11:00:20] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[11:00:20] [PASSED] drm_test_damage_iter_single_damage_outside_src
[11:00:20] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[11:00:20] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[11:00:20] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[11:00:20] [PASSED] drm_test_damage_iter_single_damage_src_moved
[11:00:20] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[11:00:20] [PASSED] drm_test_damage_iter_damage
[11:00:20] [PASSED] drm_test_damage_iter_damage_one_intersect
[11:00:20] [PASSED] drm_test_damage_iter_damage_one_outside
[11:00:20] [PASSED] drm_test_damage_iter_damage_src_moved
[11:00:20] [PASSED] drm_test_damage_iter_damage_not_visible
[11:00:20] ================ [PASSED] drm_damage_helper ================
[11:00:20] ============== drm_dp_mst_helper (3 subtests) ==============
[11:00:20] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[11:00:20] [PASSED] Clock 154000 BPP 30 DSC disabled
[11:00:20] [PASSED] Clock 234000 BPP 30 DSC disabled
[11:00:20] [PASSED] Clock 297000 BPP 24 DSC disabled
[11:00:20] [PASSED] Clock 332880 BPP 24 DSC enabled
[11:00:20] [PASSED] Clock 324540 BPP 24 DSC enabled
[11:00:20] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[11:00:20] ============== drm_test_dp_mst_calc_pbn_div  ===============
[11:00:20] [PASSED] Link rate 2000000 lane count 4
[11:00:20] [PASSED] Link rate 2000000 lane count 2
[11:00:20] [PASSED] Link rate 2000000 lane count 1
[11:00:20] [PASSED] Link rate 1350000 lane count 4
[11:00:20] [PASSED] Link rate 1350000 lane count 2
[11:00:20] [PASSED] Link rate 1350000 lane count 1
[11:00:20] [PASSED] Link rate 1000000 lane count 4
[11:00:20] [PASSED] Link rate 1000000 lane count 2
[11:00:20] [PASSED] Link rate 1000000 lane count 1
[11:00:20] [PASSED] Link rate 810000 lane count 4
[11:00:20] [PASSED] Link rate 810000 lane count 2
[11:00:20] [PASSED] Link rate 810000 lane count 1
[11:00:20] [PASSED] Link rate 540000 lane count 4
[11:00:20] [PASSED] Link rate 540000 lane count 2
[11:00:20] [PASSED] Link rate 540000 lane count 1
[11:00:20] [PASSED] Link rate 270000 lane count 4
[11:00:20] [PASSED] Link rate 270000 lane count 2
[11:00:20] [PASSED] Link rate 270000 lane count 1
[11:00:20] [PASSED] Link rate 162000 lane count 4
[11:00:20] [PASSED] Link rate 162000 lane count 2
[11:00:20] [PASSED] Link rate 162000 lane count 1
[11:00:20] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[11:00:20] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[11:00:20] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[11:00:20] [PASSED] DP_POWER_UP_PHY with port number
[11:00:20] [PASSED] DP_POWER_DOWN_PHY with port number
[11:00:20] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[11:00:20] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[11:00:20] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[11:00:20] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[11:00:20] [PASSED] DP_QUERY_PAYLOAD with port number
[11:00:20] [PASSED] DP_QUERY_PAYLOAD with VCPI
[11:00:20] [PASSED] DP_REMOTE_DPCD_READ with port number
[11:00:20] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[11:00:20] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[11:00:20] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[11:00:20] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[11:00:20] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[11:00:20] [PASSED] DP_REMOTE_I2C_READ with port number
[11:00:20] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[11:00:20] [PASSED] DP_REMOTE_I2C_READ with transactions array
[11:00:20] [PASSED] DP_REMOTE_I2C_WRITE with port number
[11:00:20] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[11:00:20] [PASSED] DP_REMOTE_I2C_WRITE with data array
[11:00:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[11:00:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[11:00:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[11:00:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[11:00:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[11:00:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[11:00:20] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[11:00:20] ================ [PASSED] drm_dp_mst_helper ================
[11:00:20] ================== drm_exec (7 subtests) ===================
[11:00:20] [PASSED] sanitycheck
[11:00:20] [PASSED] test_lock
[11:00:20] [PASSED] test_lock_unlock
[11:00:20] [PASSED] test_duplicates
[11:00:20] [PASSED] test_prepare
[11:00:20] [PASSED] test_prepare_array
[11:00:20] [PASSED] test_multiple_loops
[11:00:20] ==================== [PASSED] drm_exec =====================
[11:00:20] =========== drm_format_helper_test (17 subtests) ===========
[11:00:20] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[11:00:20] [PASSED] single_pixel_source_buffer
[11:00:20] [PASSED] single_pixel_clip_rectangle
[11:00:20] [PASSED] well_known_colors
[11:00:20] [PASSED] destination_pitch
[11:00:20] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[11:00:20] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[11:00:20] [PASSED] single_pixel_source_buffer
[11:00:20] [PASSED] single_pixel_clip_rectangle
[11:00:20] [PASSED] well_known_colors
[11:00:20] [PASSED] destination_pitch
[11:00:20] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[11:00:20] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[11:00:20] [PASSED] single_pixel_source_buffer
[11:00:20] [PASSED] single_pixel_clip_rectangle
[11:00:20] [PASSED] well_known_colors
[11:00:20] [PASSED] destination_pitch
[11:00:20] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[11:00:20] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[11:00:20] [PASSED] single_pixel_source_buffer
[11:00:20] [PASSED] single_pixel_clip_rectangle
[11:00:20] [PASSED] well_known_colors
[11:00:20] [PASSED] destination_pitch
[11:00:20] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[11:00:20] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[11:00:20] [PASSED] single_pixel_source_buffer
[11:00:20] [PASSED] single_pixel_clip_rectangle
[11:00:20] [PASSED] well_known_colors
[11:00:20] [PASSED] destination_pitch
[11:00:20] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[11:00:20] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[11:00:20] [PASSED] single_pixel_source_buffer
[11:00:20] [PASSED] single_pixel_clip_rectangle
[11:00:20] [PASSED] well_known_colors
[11:00:20] [PASSED] destination_pitch
[11:00:20] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[11:00:20] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[11:00:20] [PASSED] single_pixel_source_buffer
[11:00:20] [PASSED] single_pixel_clip_rectangle
[11:00:20] [PASSED] well_known_colors
[11:00:20] [PASSED] destination_pitch
[11:00:20] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[11:00:20] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[11:00:20] [PASSED] single_pixel_source_buffer
[11:00:20] [PASSED] single_pixel_clip_rectangle
[11:00:20] [PASSED] well_known_colors
[11:00:20] [PASSED] destination_pitch
[11:00:20] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[11:00:20] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[11:00:20] [PASSED] single_pixel_source_buffer
[11:00:20] [PASSED] single_pixel_clip_rectangle
[11:00:20] [PASSED] well_known_colors
[11:00:20] [PASSED] destination_pitch
[11:00:20] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[11:00:20] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[11:00:20] [PASSED] single_pixel_source_buffer
[11:00:20] [PASSED] single_pixel_clip_rectangle
[11:00:20] [PASSED] well_known_colors
[11:00:20] [PASSED] destination_pitch
[11:00:20] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[11:00:20] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[11:00:20] [PASSED] single_pixel_source_buffer
[11:00:20] [PASSED] single_pixel_clip_rectangle
[11:00:20] [PASSED] well_known_colors
[11:00:20] [PASSED] destination_pitch
[11:00:20] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[11:00:20] ============== drm_test_fb_xrgb8888_to_mono  ===============
[11:00:20] [PASSED] single_pixel_source_buffer
[11:00:20] [PASSED] single_pixel_clip_rectangle
[11:00:20] [PASSED] well_known_colors
[11:00:20] [PASSED] destination_pitch
[11:00:20] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[11:00:20] ==================== drm_test_fb_swab  =====================
[11:00:20] [PASSED] single_pixel_source_buffer
[11:00:20] [PASSED] single_pixel_clip_rectangle
[11:00:20] [PASSED] well_known_colors
[11:00:20] [PASSED] destination_pitch
[11:00:20] ================ [PASSED] drm_test_fb_swab =================
[11:00:20] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[11:00:20] [PASSED] single_pixel_source_buffer
[11:00:20] [PASSED] single_pixel_clip_rectangle
[11:00:20] [PASSED] well_known_colors
[11:00:20] [PASSED] destination_pitch
[11:00:20] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[11:00:20] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[11:00:20] [PASSED] single_pixel_source_buffer
[11:00:20] [PASSED] single_pixel_clip_rectangle
[11:00:20] [PASSED] well_known_colors
[11:00:20] [PASSED] destination_pitch
[11:00:20] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[11:00:20] ================= drm_test_fb_clip_offset  =================
[11:00:20] [PASSED] pass through
[11:00:20] [PASSED] horizontal offset
[11:00:20] [PASSED] vertical offset
[11:00:20] [PASSED] horizontal and vertical offset
[11:00:20] [PASSED] horizontal offset (custom pitch)
[11:00:20] [PASSED] vertical offset (custom pitch)
[11:00:20] [PASSED] horizontal and vertical offset (custom pitch)
[11:00:20] ============= [PASSED] drm_test_fb_clip_offset =============
[11:00:20] =================== drm_test_fb_memcpy  ====================
[11:00:20] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[11:00:20] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[11:00:20] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[11:00:20] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[11:00:20] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[11:00:20] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[11:00:20] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[11:00:20] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[11:00:20] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[11:00:20] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[11:00:20] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[11:00:20] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[11:00:20] =============== [PASSED] drm_test_fb_memcpy ================
[11:00:20] ============= [PASSED] drm_format_helper_test ==============
[11:00:20] ================= drm_format (18 subtests) =================
[11:00:20] [PASSED] drm_test_format_block_width_invalid
[11:00:20] [PASSED] drm_test_format_block_width_one_plane
[11:00:20] [PASSED] drm_test_format_block_width_two_plane
[11:00:20] [PASSED] drm_test_format_block_width_three_plane
[11:00:20] [PASSED] drm_test_format_block_width_tiled
[11:00:20] [PASSED] drm_test_format_block_height_invalid
[11:00:20] [PASSED] drm_test_format_block_height_one_plane
[11:00:20] [PASSED] drm_test_format_block_height_two_plane
[11:00:20] [PASSED] drm_test_format_block_height_three_plane
[11:00:20] [PASSED] drm_test_format_block_height_tiled
[11:00:20] [PASSED] drm_test_format_min_pitch_invalid
[11:00:20] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[11:00:20] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[11:00:20] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[11:00:20] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[11:00:20] [PASSED] drm_test_format_min_pitch_two_plane
[11:00:20] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[11:00:20] [PASSED] drm_test_format_min_pitch_tiled
[11:00:20] =================== [PASSED] drm_format ====================
[11:00:20] ============== drm_framebuffer (10 subtests) ===============
[11:00:20] ========== drm_test_framebuffer_check_src_coords  ==========
[11:00:20] [PASSED] Success: source fits into fb
[11:00:20] [PASSED] Fail: overflowing fb with x-axis coordinate
[11:00:20] [PASSED] Fail: overflowing fb with y-axis coordinate
[11:00:20] [PASSED] Fail: overflowing fb with source width
[11:00:20] [PASSED] Fail: overflowing fb with source height
[11:00:20] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[11:00:20] [PASSED] drm_test_framebuffer_cleanup
[11:00:20] =============== drm_test_framebuffer_create  ===============
[11:00:20] [PASSED] ABGR8888 normal sizes
[11:00:20] [PASSED] ABGR8888 max sizes
[11:00:20] [PASSED] ABGR8888 pitch greater than min required
[11:00:20] [PASSED] ABGR8888 pitch less than min required
[11:00:20] [PASSED] ABGR8888 Invalid width
[11:00:20] [PASSED] ABGR8888 Invalid buffer handle
[11:00:20] [PASSED] No pixel format
[11:00:20] [PASSED] ABGR8888 Width 0
[11:00:20] [PASSED] ABGR8888 Height 0
[11:00:20] [PASSED] ABGR8888 Out of bound height * pitch combination
[11:00:20] [PASSED] ABGR8888 Large buffer offset
[11:00:20] [PASSED] ABGR8888 Buffer offset for inexistent plane
[11:00:20] [PASSED] ABGR8888 Invalid flag
[11:00:20] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[11:00:20] [PASSED] ABGR8888 Valid buffer modifier
[11:00:20] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[11:00:20] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[11:00:20] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[11:00:20] [PASSED] NV12 Normal sizes
[11:00:20] [PASSED] NV12 Max sizes
[11:00:20] [PASSED] NV12 Invalid pitch
[11:00:20] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[11:00:20] [PASSED] NV12 different  modifier per-plane
[11:00:20] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[11:00:20] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[11:00:20] [PASSED] NV12 Modifier for inexistent plane
[11:00:20] [PASSED] NV12 Handle for inexistent plane
[11:00:20] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[11:00:20] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[11:00:20] [PASSED] YVU420 Normal sizes
[11:00:20] [PASSED] YVU420 Max sizes
[11:00:20] [PASSED] YVU420 Invalid pitch
[11:00:20] [PASSED] YVU420 Different pitches
[11:00:20] [PASSED] YVU420 Different buffer offsets/pitches
[11:00:20] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[11:00:20] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[11:00:20] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[11:00:20] [PASSED] YVU420 Valid modifier
[11:00:20] [PASSED] YVU420 Different modifiers per plane
[11:00:20] [PASSED] YVU420 Modifier for inexistent plane
[11:00:20] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[11:00:20] [PASSED] X0L2 Normal sizes
[11:00:20] [PASSED] X0L2 Max sizes
[11:00:20] [PASSED] X0L2 Invalid pitch
[11:00:20] [PASSED] X0L2 Pitch greater than minimum required
[11:00:20] [PASSED] X0L2 Handle for inexistent plane
[11:00:20] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[11:00:20] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[11:00:20] [PASSED] X0L2 Valid modifier
[11:00:20] [PASSED] X0L2 Modifier for inexistent plane
[11:00:20] =========== [PASSED] drm_test_framebuffer_create ===========
[11:00:20] [PASSED] drm_test_framebuffer_free
[11:00:20] [PASSED] drm_test_framebuffer_init
[11:00:20] [PASSED] drm_test_framebuffer_init_bad_format
[11:00:20] [PASSED] drm_test_framebuffer_init_dev_mismatch
[11:00:20] [PASSED] drm_test_framebuffer_lookup
[11:00:20] [PASSED] drm_test_framebuffer_lookup_inexistent
[11:00:20] [PASSED] drm_test_framebuffer_modifiers_not_supported
[11:00:20] ================= [PASSED] drm_framebuffer =================
[11:00:20] ================ drm_gem_shmem (8 subtests) ================
[11:00:20] [PASSED] drm_gem_shmem_test_obj_create
[11:00:20] [PASSED] drm_gem_shmem_test_obj_create_private
[11:00:20] [PASSED] drm_gem_shmem_test_pin_pages
[11:00:20] [PASSED] drm_gem_shmem_test_vmap
[11:00:20] [PASSED] drm_gem_shmem_test_get_sg_table
[11:00:20] [PASSED] drm_gem_shmem_test_get_pages_sgt
[11:00:20] [PASSED] drm_gem_shmem_test_madvise
[11:00:20] [PASSED] drm_gem_shmem_test_purge
[11:00:20] ================== [PASSED] drm_gem_shmem ==================
[11:00:20] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[11:00:20] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[11:00:20] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[11:00:20] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[11:00:20] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[11:00:20] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[11:00:20] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[11:00:20] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[11:00:20] [PASSED] Automatic
[11:00:20] [PASSED] Full
[11:00:20] [PASSED] Limited 16:235
[11:00:20] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[11:00:20] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[11:00:20] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[11:00:20] [PASSED] drm_test_check_disable_connector
[11:00:20] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[11:00:20] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[11:00:20] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[11:00:20] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[11:00:20] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[11:00:20] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[11:00:20] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[11:00:20] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[11:00:20] [PASSED] drm_test_check_output_bpc_dvi
[11:00:20] [PASSED] drm_test_check_output_bpc_format_vic_1
[11:00:20] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[11:00:20] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[11:00:20] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[11:00:20] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[11:00:20] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[11:00:20] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[11:00:20] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[11:00:20] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[11:00:20] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[11:00:20] [PASSED] drm_test_check_broadcast_rgb_value
[11:00:20] [PASSED] drm_test_check_bpc_8_value
[11:00:20] [PASSED] drm_test_check_bpc_10_value
[11:00:20] [PASSED] drm_test_check_bpc_12_value
[11:00:20] [PASSED] drm_test_check_format_value
[11:00:20] [PASSED] drm_test_check_tmds_char_value
[11:00:20] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[11:00:20] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[11:00:20] [PASSED] drm_test_check_mode_valid
[11:00:20] [PASSED] drm_test_check_mode_valid_reject
[11:00:20] [PASSED] drm_test_check_mode_valid_reject_rate
[11:00:20] [PASSED] drm_test_check_mode_valid_reject_max_clock
[11:00:20] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[11:00:20] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[11:00:20] [PASSED] drm_test_check_infoframes
[11:00:20] [PASSED] drm_test_check_reject_avi_infoframe
[11:00:20] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[11:00:20] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[11:00:20] [PASSED] drm_test_check_reject_audio_infoframe
[11:00:20] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[11:00:20] ================= drm_managed (2 subtests) =================
[11:00:20] [PASSED] drm_test_managed_release_action
[11:00:20] [PASSED] drm_test_managed_run_action
[11:00:20] =================== [PASSED] drm_managed ===================
[11:00:20] =================== drm_mm (6 subtests) ====================
[11:00:20] [PASSED] drm_test_mm_init
[11:00:20] [PASSED] drm_test_mm_debug
[11:00:20] [PASSED] drm_test_mm_align32
[11:00:20] [PASSED] drm_test_mm_align64
[11:00:20] [PASSED] drm_test_mm_lowest
[11:00:20] [PASSED] drm_test_mm_highest
[11:00:20] ===================== [PASSED] drm_mm ======================
[11:00:20] ============= drm_modes_analog_tv (5 subtests) =============
[11:00:20] [PASSED] drm_test_modes_analog_tv_mono_576i
[11:00:20] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[11:00:20] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[11:00:20] [PASSED] drm_test_modes_analog_tv_pal_576i
[11:00:20] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[11:00:20] =============== [PASSED] drm_modes_analog_tv ===============
[11:00:20] ============== drm_plane_helper (2 subtests) ===============
[11:00:20] =============== drm_test_check_plane_state  ================
[11:00:20] [PASSED] clipping_simple
[11:00:20] [PASSED] clipping_rotate_reflect
[11:00:20] [PASSED] positioning_simple
[11:00:20] [PASSED] upscaling
[11:00:20] [PASSED] downscaling
[11:00:20] [PASSED] rounding1
[11:00:20] [PASSED] rounding2
[11:00:20] [PASSED] rounding3
[11:00:20] [PASSED] rounding4
[11:00:20] =========== [PASSED] drm_test_check_plane_state ============
[11:00:20] =========== drm_test_check_invalid_plane_state  ============
[11:00:20] [PASSED] positioning_invalid
[11:00:20] [PASSED] upscaling_invalid
[11:00:20] [PASSED] downscaling_invalid
[11:00:20] ======= [PASSED] drm_test_check_invalid_plane_state ========
[11:00:20] ================ [PASSED] drm_plane_helper =================
[11:00:20] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[11:00:20] ====== drm_test_connector_helper_tv_get_modes_check  =======
[11:00:20] [PASSED] None
[11:00:20] [PASSED] PAL
[11:00:20] [PASSED] NTSC
[11:00:20] [PASSED] Both, NTSC Default
[11:00:20] [PASSED] Both, PAL Default
[11:00:20] [PASSED] Both, NTSC Default, with PAL on command-line
[11:00:20] [PASSED] Both, PAL Default, with NTSC on command-line
[11:00:20] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[11:00:20] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[11:00:20] ================== drm_rect (9 subtests) ===================
[11:00:20] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[11:00:20] [PASSED] drm_test_rect_clip_scaled_not_clipped
[11:00:20] [PASSED] drm_test_rect_clip_scaled_clipped
[11:00:20] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[11:00:20] ================= drm_test_rect_intersect  =================
[11:00:20] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[11:00:20] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[11:00:20] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[11:00:20] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[11:00:20] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[11:00:20] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[11:00:20] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[11:00:20] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[11:00:20] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[11:00:20] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[11:00:20] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[11:00:20] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[11:00:20] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[11:00:20] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[11:00:20] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
stty: 'standard input': Inappropriate ioctl for device
[11:00:20] ============= [PASSED] drm_test_rect_intersect =============
[11:00:20] ================ drm_test_rect_calc_hscale  ================
[11:00:20] [PASSED] normal use
[11:00:20] [PASSED] out of max range
[11:00:20] [PASSED] out of min range
[11:00:20] [PASSED] zero dst
[11:00:20] [PASSED] negative src
[11:00:20] [PASSED] negative dst
[11:00:20] ============ [PASSED] drm_test_rect_calc_hscale ============
[11:00:20] ================ drm_test_rect_calc_vscale  ================
[11:00:20] [PASSED] normal use
[11:00:20] [PASSED] out of max range
[11:00:20] [PASSED] out of min range
[11:00:20] [PASSED] zero dst
[11:00:20] [PASSED] negative src
[11:00:20] [PASSED] negative dst
[11:00:20] ============ [PASSED] drm_test_rect_calc_vscale ============
[11:00:20] ================== drm_test_rect_rotate  ===================
[11:00:20] [PASSED] reflect-x
[11:00:20] [PASSED] reflect-y
[11:00:20] [PASSED] rotate-0
[11:00:20] [PASSED] rotate-90
[11:00:20] [PASSED] rotate-180
[11:00:20] [PASSED] rotate-270
[11:00:20] ============== [PASSED] drm_test_rect_rotate ===============
[11:00:20] ================ drm_test_rect_rotate_inv  =================
[11:00:20] [PASSED] reflect-x
[11:00:20] [PASSED] reflect-y
[11:00:20] [PASSED] rotate-0
[11:00:20] [PASSED] rotate-90
[11:00:20] [PASSED] rotate-180
[11:00:20] [PASSED] rotate-270
[11:00:20] ============ [PASSED] drm_test_rect_rotate_inv =============
[11:00:20] ==================== [PASSED] drm_rect =====================
[11:00:20] ============ drm_sysfb_modeset_test (1 subtest) ============
[11:00:20] ============ drm_test_sysfb_build_fourcc_list  =============
[11:00:20] [PASSED] no native formats
[11:00:20] [PASSED] XRGB8888 as native format
[11:00:20] [PASSED] remove duplicates
[11:00:20] [PASSED] convert alpha formats
[11:00:20] [PASSED] random formats
[11:00:20] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[11:00:20] ============= [PASSED] drm_sysfb_modeset_test ==============
[11:00:20] ================== drm_fixp (2 subtests) ===================
[11:00:20] [PASSED] drm_test_int2fixp
[11:00:20] [PASSED] drm_test_sm2fixp
[11:00:20] ==================== [PASSED] drm_fixp =====================
[11:00:20] ============================================================
[11:00:20] Testing complete. Ran 630 tests: passed: 630
[11:00:20] Elapsed time: 33.693s total, 1.639s configuring, 31.587s building, 0.448s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[11:00:20] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:00:22] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[11:00:32] Starting KUnit Kernel (1/1)...
[11:00:32] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:00:32] ================= ttm_device (5 subtests) ==================
[11:00:32] [PASSED] ttm_device_init_basic
[11:00:32] [PASSED] ttm_device_init_multiple
[11:00:32] [PASSED] ttm_device_fini_basic
[11:00:32] [PASSED] ttm_device_init_no_vma_man
[11:00:32] ================== ttm_device_init_pools  ==================
[11:00:32] [PASSED] No DMA allocations, no DMA32 required
[11:00:32] [PASSED] DMA allocations, DMA32 required
[11:00:32] [PASSED] No DMA allocations, DMA32 required
[11:00:32] [PASSED] DMA allocations, no DMA32 required
[11:00:32] ============== [PASSED] ttm_device_init_pools ==============
[11:00:32] =================== [PASSED] ttm_device ====================
[11:00:32] ================== ttm_pool (8 subtests) ===================
[11:00:32] ================== ttm_pool_alloc_basic  ===================
[11:00:32] [PASSED] One page
[11:00:32] [PASSED] More than one page
[11:00:32] [PASSED] Above the allocation limit
[11:00:32] [PASSED] One page, with coherent DMA mappings enabled
[11:00:32] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[11:00:32] ============== [PASSED] ttm_pool_alloc_basic ===============
[11:00:32] ============== ttm_pool_alloc_basic_dma_addr  ==============
[11:00:32] [PASSED] One page
[11:00:32] [PASSED] More than one page
[11:00:32] [PASSED] Above the allocation limit
[11:00:32] [PASSED] One page, with coherent DMA mappings enabled
[11:00:32] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[11:00:32] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[11:00:32] [PASSED] ttm_pool_alloc_order_caching_match
[11:00:32] [PASSED] ttm_pool_alloc_caching_mismatch
[11:00:32] [PASSED] ttm_pool_alloc_order_mismatch
[11:00:32] [PASSED] ttm_pool_free_dma_alloc
[11:00:32] [PASSED] ttm_pool_free_no_dma_alloc
[11:00:32] [PASSED] ttm_pool_fini_basic
[11:00:32] ==================== [PASSED] ttm_pool =====================
[11:00:32] ================ ttm_resource (8 subtests) =================
[11:00:32] ================= ttm_resource_init_basic  =================
[11:00:32] [PASSED] Init resource in TTM_PL_SYSTEM
[11:00:32] [PASSED] Init resource in TTM_PL_VRAM
[11:00:32] [PASSED] Init resource in a private placement
[11:00:32] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[11:00:32] ============= [PASSED] ttm_resource_init_basic =============
[11:00:32] [PASSED] ttm_resource_init_pinned
[11:00:32] [PASSED] ttm_resource_fini_basic
[11:00:32] [PASSED] ttm_resource_manager_init_basic
[11:00:32] [PASSED] ttm_resource_manager_usage_basic
[11:00:32] [PASSED] ttm_resource_manager_set_used_basic
[11:00:32] [PASSED] ttm_sys_man_alloc_basic
[11:00:32] [PASSED] ttm_sys_man_free_basic
[11:00:32] ================== [PASSED] ttm_resource ===================
[11:00:32] =================== ttm_tt (15 subtests) ===================
[11:00:32] ==================== ttm_tt_init_basic  ====================
[11:00:32] [PASSED] Page-aligned size
[11:00:32] [PASSED] Extra pages requested
[11:00:32] ================ [PASSED] ttm_tt_init_basic ================
[11:00:32] [PASSED] ttm_tt_init_misaligned
[11:00:32] [PASSED] ttm_tt_fini_basic
[11:00:32] [PASSED] ttm_tt_fini_sg
[11:00:32] [PASSED] ttm_tt_fini_shmem
[11:00:32] [PASSED] ttm_tt_create_basic
[11:00:32] [PASSED] ttm_tt_create_invalid_bo_type
[11:00:32] [PASSED] ttm_tt_create_ttm_exists
[11:00:32] [PASSED] ttm_tt_create_failed
[11:00:32] [PASSED] ttm_tt_destroy_basic
[11:00:32] [PASSED] ttm_tt_populate_null_ttm
[11:00:32] [PASSED] ttm_tt_populate_populated_ttm
[11:00:32] [PASSED] ttm_tt_unpopulate_basic
[11:00:32] [PASSED] ttm_tt_unpopulate_empty_ttm
[11:00:32] [PASSED] ttm_tt_swapin_basic
[11:00:32] ===================== [PASSED] ttm_tt ======================
[11:00:32] =================== ttm_bo (14 subtests) ===================
[11:00:32] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[11:00:32] [PASSED] Cannot be interrupted and sleeps
[11:00:32] [PASSED] Cannot be interrupted, locks straight away
[11:00:32] [PASSED] Can be interrupted, sleeps
[11:00:32] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[11:00:32] [PASSED] ttm_bo_reserve_locked_no_sleep
[11:00:32] [PASSED] ttm_bo_reserve_no_wait_ticket
[11:00:32] [PASSED] ttm_bo_reserve_double_resv
[11:00:32] [PASSED] ttm_bo_reserve_interrupted
[11:00:32] [PASSED] ttm_bo_reserve_deadlock
[11:00:32] [PASSED] ttm_bo_unreserve_basic
[11:00:32] [PASSED] ttm_bo_unreserve_pinned
[11:00:32] [PASSED] ttm_bo_unreserve_bulk
[11:00:32] [PASSED] ttm_bo_fini_basic
[11:00:32] [PASSED] ttm_bo_fini_shared_resv
[11:00:32] [PASSED] ttm_bo_pin_basic
[11:00:32] [PASSED] ttm_bo_pin_unpin_resource
[11:00:32] [PASSED] ttm_bo_multiple_pin_one_unpin
[11:00:32] ===================== [PASSED] ttm_bo ======================
[11:00:32] ============== ttm_bo_validate (21 subtests) ===============
[11:00:32] ============== ttm_bo_init_reserved_sys_man  ===============
[11:00:32] [PASSED] Buffer object for userspace
[11:00:32] [PASSED] Kernel buffer object
[11:00:32] [PASSED] Shared buffer object
[11:00:32] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[11:00:32] ============== ttm_bo_init_reserved_mock_man  ==============
[11:00:32] [PASSED] Buffer object for userspace
[11:00:32] [PASSED] Kernel buffer object
[11:00:32] [PASSED] Shared buffer object
[11:00:32] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[11:00:32] [PASSED] ttm_bo_init_reserved_resv
[11:00:32] ================== ttm_bo_validate_basic  ==================
[11:00:32] [PASSED] Buffer object for userspace
[11:00:32] [PASSED] Kernel buffer object
[11:00:32] [PASSED] Shared buffer object
[11:00:32] ============== [PASSED] ttm_bo_validate_basic ==============
[11:00:32] [PASSED] ttm_bo_validate_invalid_placement
[11:00:32] ============= ttm_bo_validate_same_placement  ==============
[11:00:32] [PASSED] System manager
[11:00:32] [PASSED] VRAM manager
[11:00:32] ========= [PASSED] ttm_bo_validate_same_placement ==========
[11:00:32] [PASSED] ttm_bo_validate_failed_alloc
[11:00:32] [PASSED] ttm_bo_validate_pinned
[11:00:32] [PASSED] ttm_bo_validate_busy_placement
[11:00:32] ================ ttm_bo_validate_multihop  =================
[11:00:32] [PASSED] Buffer object for userspace
[11:00:32] [PASSED] Kernel buffer object
[11:00:32] [PASSED] Shared buffer object
[11:00:32] ============ [PASSED] ttm_bo_validate_multihop =============
[11:00:32] ========== ttm_bo_validate_no_placement_signaled  ==========
[11:00:32] [PASSED] Buffer object in system domain, no page vector
[11:00:32] [PASSED] Buffer object in system domain with an existing page vector
[11:00:32] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[11:00:32] ======== ttm_bo_validate_no_placement_not_signaled  ========
[11:00:32] [PASSED] Buffer object for userspace
[11:00:32] [PASSED] Kernel buffer object
[11:00:32] [PASSED] Shared buffer object
[11:00:32] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[11:00:32] [PASSED] ttm_bo_validate_move_fence_signaled
[11:00:32] ========= ttm_bo_validate_move_fence_not_signaled  =========
[11:00:32] [PASSED] Waits for GPU
[11:00:32] [PASSED] Tries to lock straight away
[11:00:32] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[11:00:32] [PASSED] ttm_bo_validate_happy_evict
[11:00:32] [PASSED] ttm_bo_validate_all_pinned_evict
[11:00:32] [PASSED] ttm_bo_validate_allowed_only_evict
[11:00:32] [PASSED] ttm_bo_validate_deleted_evict
[11:00:32] [PASSED] ttm_bo_validate_busy_domain_evict
[11:00:32] [PASSED] ttm_bo_validate_evict_gutting
[11:00:32] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[11:00:32] ================= [PASSED] ttm_bo_validate =================
[11:00:32] ============================================================
[11:00:32] Testing complete. Ran 101 tests: passed: 101
[11:00:32] Elapsed time: 11.850s total, 1.747s configuring, 9.786s building, 0.293s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for drm/i915/display: fix the pixel normalization handling for xe3p_lpd (rev3)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 988 bytes --]

== Series Details ==

Series: drm/i915/display: fix the pixel normalization handling for xe3p_lpd (rev3)
URL   : https://patchwork.freedesktop.org/series/160254/
State : success

== Summary ==

CI Bug Log - changes from xe-4464-23ebb43006b887363bd6653fbc4a327fd3072226_BAT -> xe-pw-160254v3_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (12 -> 12)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * Linux: xe-4464-23ebb43006b887363bd6653fbc4a327fd3072226 -> xe-pw-160254v3

  IGT_8721: 3707bb4267de22a18d61b232c4ab5fbaf61db90c @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4464-23ebb43006b887363bd6653fbc4a327fd3072226: 23ebb43006b887363bd6653fbc4a327fd3072226
  xe-pw-160254v3: 160254v3

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160254v3/index.html

[-- Attachment #2: Type: text/html, Size: 1536 bytes --]

✓ Xe.CI.BAT: success for drm/i915/display: fix the pixel normalization handling for xe3p_lpd (rev3)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 988 bytes --]

== Series Details ==

Series: drm/i915/display: fix the pixel normalization handling for xe3p_lpd (rev3)
URL   : https://patchwork.freedesktop.org/series/160254/
State : success

== Summary ==

CI Bug Log - changes from xe-4464-23ebb43006b887363bd6653fbc4a327fd3072226_BAT -> xe-pw-160254v3_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (12 -> 12)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * Linux: xe-4464-23ebb43006b887363bd6653fbc4a327fd3072226 -> xe-pw-160254v3

  IGT_8721: 3707bb4267de22a18d61b232c4ab5fbaf61db90c @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4464-23ebb43006b887363bd6653fbc4a327fd3072226: 23ebb43006b887363bd6653fbc4a327fd3072226
  xe-pw-160254v3: 160254v3

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160254v3/index.html

[-- Attachment #2: Type: text/html, Size: 1536 bytes --]