* [PATCH] drm/i915/vrr: Configure VRR timings after enabling TRANS_DDI_FUNC_CTL
@ 2026-03-03 9:54 Ville Syrjala
2026-03-03 9:59 ` ✗ CI.checkpatch: warning for " Patchwork
` (3 more replies)
0 siblings, 4 replies; 6+ messages in thread
From: Ville Syrjala @ 2026-03-03 9:54 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe, stable, Ankit Nautiyal, Benjamin Tissoires
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Apparently ICL may hang with an MCE if we write TRANS_VRR_VMAX/FLIPLINE
before enabling TRANS_DDI_FUNC_CTL.
Personally I was only able to reproduce a hang (on an Dell XPS 7390
2-in-1) with an external display connected via a dock using a dodgy
type-C cable that made the link training fail. After the failed
link training the machine would hang. TGL seemed immune to the
problem for whatever reason.
BSpec does tell us to configure VRR after enabling TRANS_DDI_FUNC_CTL
as well. The DMC firmware also does the VRR restore in two stages:
- first stage seems to be unconditional and includes TRANS_VRR_CTL
and a few other VRR registers, among other things
- second stage is conditional on the DDI being enabled,
and includes TRANS_DDI_FUNC_CTL and TRANS_VRR_VMAX/VMIN/FLIPLINE,
among other things
So let's reorder the steps to match to avoid the hang, and
toss in an extra WARN to make sure we don't screw this up later.
BSpec: 22243
Cc: stable@vger.kernel.org
Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reported-by: Benjamin Tissoires <bentiss@kernel.org>
Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15777
Tested-by: Benjamin Tissoires <bentiss@kernel.org>
Fixes: dda7dcd9da73 ("drm/i915/vrr: Use fixed timings for platforms that support VRR")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 1 -
drivers/gpu/drm/i915/display/intel_vrr.c | 14 ++++++++++++++
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 27354585ba92..138ee7dd1977 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1637,7 +1637,6 @@ static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta
}
intel_set_transcoder_timings(crtc_state);
- intel_vrr_set_transcoder_timings(crtc_state);
if (cpu_transcoder != TRANSCODER_EDP)
intel_de_write(display, TRANS_MULT(display, cpu_transcoder),
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 00ca76dbdd6c..8a957804cb97 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -599,6 +599,18 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
if (!HAS_VRR(display))
return;
+ /*
+ * Bspec says:
+ * "(note: VRR needs to be programmed after
+ * TRANS_DDI_FUNC_CTL and before TRANS_CONF)."
+ *
+ * In practice it turns out that ICL can hang if
+ * TRANS_VRR_VMAX/FLIPLINE are written before
+ * enabling TRANS_DDI_FUNC_CTL.
+ */
+ drm_WARN_ON(display->drm,
+ !(intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & TRANS_DDI_FUNC_ENABLE));
+
/*
* This bit seems to have two meanings depending on the platform:
* TGL: generate VRR "safe window" for DSB vblank waits
@@ -961,6 +973,8 @@ void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
+ intel_vrr_set_transcoder_timings(crtc_state);
+
if (!intel_vrr_possible(crtc_state))
return;
--
2.52.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* ✗ CI.checkpatch: warning for drm/i915/vrr: Configure VRR timings after enabling TRANS_DDI_FUNC_CTL
2026-03-03 9:54 [PATCH] drm/i915/vrr: Configure VRR timings after enabling TRANS_DDI_FUNC_CTL Ville Syrjala
@ 2026-03-03 9:59 ` Patchwork
2026-03-03 10:01 ` ✓ CI.KUnit: success " Patchwork
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2026-03-03 9:59 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-xe
== Series Details ==
Series: drm/i915/vrr: Configure VRR timings after enabling TRANS_DDI_FUNC_CTL
URL : https://patchwork.freedesktop.org/series/162481/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
1f57ba1afceae32108bd24770069f764d940a0e4
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 009b71af5fade302588435dbc544c6b105471a84
Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
Date: Tue Mar 3 11:54:14 2026 +0200
drm/i915/vrr: Configure VRR timings after enabling TRANS_DDI_FUNC_CTL
Apparently ICL may hang with an MCE if we write TRANS_VRR_VMAX/FLIPLINE
before enabling TRANS_DDI_FUNC_CTL.
Personally I was only able to reproduce a hang (on an Dell XPS 7390
2-in-1) with an external display connected via a dock using a dodgy
type-C cable that made the link training fail. After the failed
link training the machine would hang. TGL seemed immune to the
problem for whatever reason.
BSpec does tell us to configure VRR after enabling TRANS_DDI_FUNC_CTL
as well. The DMC firmware also does the VRR restore in two stages:
- first stage seems to be unconditional and includes TRANS_VRR_CTL
and a few other VRR registers, among other things
- second stage is conditional on the DDI being enabled,
and includes TRANS_DDI_FUNC_CTL and TRANS_VRR_VMAX/VMIN/FLIPLINE,
among other things
So let's reorder the steps to match to avoid the hang, and
toss in an extra WARN to make sure we don't screw this up later.
BSpec: 22243
Cc: stable@vger.kernel.org
Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reported-by: Benjamin Tissoires <bentiss@kernel.org>
Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15777
Tested-by: Benjamin Tissoires <bentiss@kernel.org>
Fixes: dda7dcd9da73 ("drm/i915/vrr: Use fixed timings for platforms that support VRR")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+ /mt/dim checkpatch 17ea88b18f33a355595d94c8ee60269cc7ac7f1d drm-intel
009b71af5fad drm/i915/vrr: Configure VRR timings after enabling TRANS_DDI_FUNC_CTL
-:69: WARNING:LONG_LINE: line length of 116 exceeds 100 columns
#69: FILE: drivers/gpu/drm/i915/display/intel_vrr.c:612:
+ !(intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & TRANS_DDI_FUNC_ENABLE));
total: 0 errors, 1 warnings, 0 checks, 33 lines checked
^ permalink raw reply [flat|nested] 6+ messages in thread
* ✓ CI.KUnit: success for drm/i915/vrr: Configure VRR timings after enabling TRANS_DDI_FUNC_CTL
2026-03-03 9:54 [PATCH] drm/i915/vrr: Configure VRR timings after enabling TRANS_DDI_FUNC_CTL Ville Syrjala
2026-03-03 9:59 ` ✗ CI.checkpatch: warning for " Patchwork
@ 2026-03-03 10:01 ` Patchwork
2026-03-03 10:55 ` ✓ Xe.CI.BAT: " Patchwork
2026-03-04 6:06 ` [PATCH] " Nautiyal, Ankit K
3 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2026-03-03 10:01 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-xe
== Series Details ==
Series: drm/i915/vrr: Configure VRR timings after enabling TRANS_DDI_FUNC_CTL
URL : https://patchwork.freedesktop.org/series/162481/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[09:59:54] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[09:59:58] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[10:00:29] Starting KUnit Kernel (1/1)...
[10:00:29] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:00:29] ================== guc_buf (11 subtests) ===================
[10:00:29] [PASSED] test_smallest
[10:00:29] [PASSED] test_largest
[10:00:29] [PASSED] test_granular
[10:00:29] [PASSED] test_unique
[10:00:29] [PASSED] test_overlap
[10:00:29] [PASSED] test_reusable
[10:00:29] [PASSED] test_too_big
[10:00:29] [PASSED] test_flush
[10:00:29] [PASSED] test_lookup
[10:00:29] [PASSED] test_data
[10:00:29] [PASSED] test_class
[10:00:29] ===================== [PASSED] guc_buf =====================
[10:00:29] =================== guc_dbm (7 subtests) ===================
[10:00:29] [PASSED] test_empty
[10:00:29] [PASSED] test_default
[10:00:29] ======================== test_size ========================
[10:00:29] [PASSED] 4
[10:00:29] [PASSED] 8
[10:00:29] [PASSED] 32
[10:00:29] [PASSED] 256
[10:00:29] ==================== [PASSED] test_size ====================
[10:00:29] ======================= test_reuse ========================
[10:00:29] [PASSED] 4
[10:00:29] [PASSED] 8
[10:00:29] [PASSED] 32
[10:00:29] [PASSED] 256
[10:00:29] =================== [PASSED] test_reuse ====================
[10:00:29] =================== test_range_overlap ====================
[10:00:29] [PASSED] 4
[10:00:29] [PASSED] 8
[10:00:29] [PASSED] 32
[10:00:29] [PASSED] 256
[10:00:29] =============== [PASSED] test_range_overlap ================
[10:00:29] =================== test_range_compact ====================
[10:00:29] [PASSED] 4
[10:00:29] [PASSED] 8
[10:00:29] [PASSED] 32
[10:00:29] [PASSED] 256
[10:00:29] =============== [PASSED] test_range_compact ================
[10:00:29] ==================== test_range_spare =====================
[10:00:29] [PASSED] 4
[10:00:29] [PASSED] 8
[10:00:29] [PASSED] 32
[10:00:29] [PASSED] 256
[10:00:29] ================ [PASSED] test_range_spare =================
[10:00:29] ===================== [PASSED] guc_dbm =====================
[10:00:29] =================== guc_idm (6 subtests) ===================
[10:00:29] [PASSED] bad_init
[10:00:29] [PASSED] no_init
[10:00:29] [PASSED] init_fini
[10:00:29] [PASSED] check_used
[10:00:29] [PASSED] check_quota
[10:00:29] [PASSED] check_all
[10:00:29] ===================== [PASSED] guc_idm =====================
[10:00:29] ================== no_relay (3 subtests) ===================
[10:00:29] [PASSED] xe_drops_guc2pf_if_not_ready
[10:00:29] [PASSED] xe_drops_guc2vf_if_not_ready
[10:00:29] [PASSED] xe_rejects_send_if_not_ready
[10:00:29] ==================== [PASSED] no_relay =====================
[10:00:29] ================== pf_relay (14 subtests) ==================
[10:00:29] [PASSED] pf_rejects_guc2pf_too_short
[10:00:29] [PASSED] pf_rejects_guc2pf_too_long
[10:00:29] [PASSED] pf_rejects_guc2pf_no_payload
[10:00:29] [PASSED] pf_fails_no_payload
[10:00:29] [PASSED] pf_fails_bad_origin
[10:00:29] [PASSED] pf_fails_bad_type
[10:00:29] [PASSED] pf_txn_reports_error
[10:00:29] [PASSED] pf_txn_sends_pf2guc
[10:00:29] [PASSED] pf_sends_pf2guc
[10:00:29] [SKIPPED] pf_loopback_nop
[10:00:29] [SKIPPED] pf_loopback_echo
[10:00:29] [SKIPPED] pf_loopback_fail
[10:00:29] [SKIPPED] pf_loopback_busy
[10:00:29] [SKIPPED] pf_loopback_retry
[10:00:29] ==================== [PASSED] pf_relay =====================
[10:00:29] ================== vf_relay (3 subtests) ===================
[10:00:29] [PASSED] vf_rejects_guc2vf_too_short
[10:00:29] [PASSED] vf_rejects_guc2vf_too_long
[10:00:29] [PASSED] vf_rejects_guc2vf_no_payload
[10:00:29] ==================== [PASSED] vf_relay =====================
[10:00:29] ================ pf_gt_config (9 subtests) =================
[10:00:29] [PASSED] fair_contexts_1vf
[10:00:29] [PASSED] fair_doorbells_1vf
[10:00:29] [PASSED] fair_ggtt_1vf
[10:00:29] ====================== fair_vram_1vf ======================
[10:00:29] [PASSED] 3.50 GiB
[10:00:29] [PASSED] 11.5 GiB
[10:00:29] [PASSED] 15.5 GiB
[10:00:29] [PASSED] 31.5 GiB
[10:00:29] [PASSED] 63.5 GiB
[10:00:29] [PASSED] 13.9 GiB
[10:00:29] ================== [PASSED] fair_vram_1vf ==================
[10:00:29] ================ fair_vram_1vf_admin_only =================
[10:00:29] [PASSED] 3.50 GiB
[10:00:29] [PASSED] 11.5 GiB
[10:00:29] [PASSED] 15.5 GiB
[10:00:29] [PASSED] 31.5 GiB
[10:00:29] [PASSED] 63.5 GiB
[10:00:29] [PASSED] 13.9 GiB
[10:00:29] ============ [PASSED] fair_vram_1vf_admin_only =============
[10:00:29] ====================== fair_contexts ======================
[10:00:29] [PASSED] 1 VF
[10:00:29] [PASSED] 2 VFs
[10:00:29] [PASSED] 3 VFs
[10:00:29] [PASSED] 4 VFs
[10:00:29] [PASSED] 5 VFs
[10:00:29] [PASSED] 6 VFs
[10:00:29] [PASSED] 7 VFs
[10:00:29] [PASSED] 8 VFs
[10:00:29] [PASSED] 9 VFs
[10:00:29] [PASSED] 10 VFs
[10:00:29] [PASSED] 11 VFs
[10:00:29] [PASSED] 12 VFs
[10:00:29] [PASSED] 13 VFs
[10:00:29] [PASSED] 14 VFs
[10:00:29] [PASSED] 15 VFs
[10:00:29] [PASSED] 16 VFs
[10:00:29] [PASSED] 17 VFs
[10:00:29] [PASSED] 18 VFs
[10:00:29] [PASSED] 19 VFs
[10:00:29] [PASSED] 20 VFs
[10:00:29] [PASSED] 21 VFs
[10:00:29] [PASSED] 22 VFs
[10:00:29] [PASSED] 23 VFs
[10:00:29] [PASSED] 24 VFs
[10:00:29] [PASSED] 25 VFs
[10:00:29] [PASSED] 26 VFs
[10:00:29] [PASSED] 27 VFs
[10:00:29] [PASSED] 28 VFs
[10:00:29] [PASSED] 29 VFs
[10:00:29] [PASSED] 30 VFs
[10:00:29] [PASSED] 31 VFs
[10:00:29] [PASSED] 32 VFs
[10:00:29] [PASSED] 33 VFs
[10:00:29] [PASSED] 34 VFs
[10:00:29] [PASSED] 35 VFs
[10:00:29] [PASSED] 36 VFs
[10:00:29] [PASSED] 37 VFs
[10:00:29] [PASSED] 38 VFs
[10:00:29] [PASSED] 39 VFs
[10:00:29] [PASSED] 40 VFs
[10:00:29] [PASSED] 41 VFs
[10:00:29] [PASSED] 42 VFs
[10:00:29] [PASSED] 43 VFs
[10:00:29] [PASSED] 44 VFs
[10:00:29] [PASSED] 45 VFs
[10:00:29] [PASSED] 46 VFs
[10:00:29] [PASSED] 47 VFs
[10:00:29] [PASSED] 48 VFs
[10:00:29] [PASSED] 49 VFs
[10:00:29] [PASSED] 50 VFs
[10:00:29] [PASSED] 51 VFs
[10:00:29] [PASSED] 52 VFs
[10:00:29] [PASSED] 53 VFs
[10:00:29] [PASSED] 54 VFs
[10:00:29] [PASSED] 55 VFs
[10:00:29] [PASSED] 56 VFs
[10:00:29] [PASSED] 57 VFs
[10:00:29] [PASSED] 58 VFs
[10:00:29] [PASSED] 59 VFs
[10:00:29] [PASSED] 60 VFs
[10:00:29] [PASSED] 61 VFs
[10:00:29] [PASSED] 62 VFs
[10:00:29] [PASSED] 63 VFs
[10:00:29] ================== [PASSED] fair_contexts ==================
[10:00:29] ===================== fair_doorbells ======================
[10:00:29] [PASSED] 1 VF
[10:00:29] [PASSED] 2 VFs
[10:00:29] [PASSED] 3 VFs
[10:00:29] [PASSED] 4 VFs
[10:00:29] [PASSED] 5 VFs
[10:00:29] [PASSED] 6 VFs
[10:00:29] [PASSED] 7 VFs
[10:00:29] [PASSED] 8 VFs
[10:00:29] [PASSED] 9 VFs
[10:00:29] [PASSED] 10 VFs
[10:00:29] [PASSED] 11 VFs
[10:00:29] [PASSED] 12 VFs
[10:00:29] [PASSED] 13 VFs
[10:00:29] [PASSED] 14 VFs
[10:00:29] [PASSED] 15 VFs
[10:00:29] [PASSED] 16 VFs
[10:00:29] [PASSED] 17 VFs
[10:00:29] [PASSED] 18 VFs
[10:00:29] [PASSED] 19 VFs
[10:00:29] [PASSED] 20 VFs
[10:00:29] [PASSED] 21 VFs
[10:00:29] [PASSED] 22 VFs
[10:00:29] [PASSED] 23 VFs
[10:00:29] [PASSED] 24 VFs
[10:00:29] [PASSED] 25 VFs
[10:00:29] [PASSED] 26 VFs
[10:00:29] [PASSED] 27 VFs
[10:00:29] [PASSED] 28 VFs
[10:00:29] [PASSED] 29 VFs
[10:00:29] [PASSED] 30 VFs
[10:00:29] [PASSED] 31 VFs
[10:00:29] [PASSED] 32 VFs
[10:00:29] [PASSED] 33 VFs
[10:00:29] [PASSED] 34 VFs
[10:00:29] [PASSED] 35 VFs
[10:00:29] [PASSED] 36 VFs
[10:00:29] [PASSED] 37 VFs
[10:00:29] [PASSED] 38 VFs
[10:00:29] [PASSED] 39 VFs
[10:00:29] [PASSED] 40 VFs
[10:00:29] [PASSED] 41 VFs
[10:00:29] [PASSED] 42 VFs
[10:00:29] [PASSED] 43 VFs
[10:00:29] [PASSED] 44 VFs
[10:00:29] [PASSED] 45 VFs
[10:00:29] [PASSED] 46 VFs
[10:00:29] [PASSED] 47 VFs
[10:00:29] [PASSED] 48 VFs
[10:00:29] [PASSED] 49 VFs
[10:00:29] [PASSED] 50 VFs
[10:00:29] [PASSED] 51 VFs
[10:00:29] [PASSED] 52 VFs
[10:00:29] [PASSED] 53 VFs
[10:00:29] [PASSED] 54 VFs
[10:00:29] [PASSED] 55 VFs
[10:00:29] [PASSED] 56 VFs
[10:00:29] [PASSED] 57 VFs
[10:00:29] [PASSED] 58 VFs
[10:00:29] [PASSED] 59 VFs
[10:00:29] [PASSED] 60 VFs
[10:00:29] [PASSED] 61 VFs
[10:00:29] [PASSED] 62 VFs
[10:00:29] [PASSED] 63 VFs
[10:00:29] ================= [PASSED] fair_doorbells ==================
[10:00:29] ======================== fair_ggtt ========================
[10:00:29] [PASSED] 1 VF
[10:00:29] [PASSED] 2 VFs
[10:00:29] [PASSED] 3 VFs
[10:00:29] [PASSED] 4 VFs
[10:00:29] [PASSED] 5 VFs
[10:00:29] [PASSED] 6 VFs
[10:00:29] [PASSED] 7 VFs
[10:00:29] [PASSED] 8 VFs
[10:00:29] [PASSED] 9 VFs
[10:00:29] [PASSED] 10 VFs
[10:00:29] [PASSED] 11 VFs
[10:00:29] [PASSED] 12 VFs
[10:00:29] [PASSED] 13 VFs
[10:00:29] [PASSED] 14 VFs
[10:00:29] [PASSED] 15 VFs
[10:00:29] [PASSED] 16 VFs
[10:00:29] [PASSED] 17 VFs
[10:00:29] [PASSED] 18 VFs
[10:00:29] [PASSED] 19 VFs
[10:00:29] [PASSED] 20 VFs
[10:00:29] [PASSED] 21 VFs
[10:00:29] [PASSED] 22 VFs
[10:00:29] [PASSED] 23 VFs
[10:00:29] [PASSED] 24 VFs
[10:00:29] [PASSED] 25 VFs
[10:00:29] [PASSED] 26 VFs
[10:00:29] [PASSED] 27 VFs
[10:00:29] [PASSED] 28 VFs
[10:00:29] [PASSED] 29 VFs
[10:00:29] [PASSED] 30 VFs
[10:00:29] [PASSED] 31 VFs
[10:00:29] [PASSED] 32 VFs
[10:00:29] [PASSED] 33 VFs
[10:00:29] [PASSED] 34 VFs
[10:00:29] [PASSED] 35 VFs
[10:00:29] [PASSED] 36 VFs
[10:00:29] [PASSED] 37 VFs
[10:00:29] [PASSED] 38 VFs
[10:00:29] [PASSED] 39 VFs
[10:00:29] [PASSED] 40 VFs
[10:00:29] [PASSED] 41 VFs
[10:00:29] [PASSED] 42 VFs
[10:00:29] [PASSED] 43 VFs
[10:00:29] [PASSED] 44 VFs
[10:00:29] [PASSED] 45 VFs
[10:00:29] [PASSED] 46 VFs
[10:00:29] [PASSED] 47 VFs
[10:00:29] [PASSED] 48 VFs
[10:00:29] [PASSED] 49 VFs
[10:00:29] [PASSED] 50 VFs
[10:00:29] [PASSED] 51 VFs
[10:00:29] [PASSED] 52 VFs
[10:00:29] [PASSED] 53 VFs
[10:00:29] [PASSED] 54 VFs
[10:00:29] [PASSED] 55 VFs
[10:00:29] [PASSED] 56 VFs
[10:00:29] [PASSED] 57 VFs
[10:00:29] [PASSED] 58 VFs
[10:00:29] [PASSED] 59 VFs
[10:00:29] [PASSED] 60 VFs
[10:00:29] [PASSED] 61 VFs
[10:00:29] [PASSED] 62 VFs
[10:00:29] [PASSED] 63 VFs
[10:00:29] ==================== [PASSED] fair_ggtt ====================
[10:00:29] ======================== fair_vram ========================
[10:00:29] [PASSED] 1 VF
[10:00:29] [PASSED] 2 VFs
[10:00:29] [PASSED] 3 VFs
[10:00:29] [PASSED] 4 VFs
[10:00:29] [PASSED] 5 VFs
[10:00:29] [PASSED] 6 VFs
[10:00:29] [PASSED] 7 VFs
[10:00:29] [PASSED] 8 VFs
[10:00:29] [PASSED] 9 VFs
[10:00:29] [PASSED] 10 VFs
[10:00:29] [PASSED] 11 VFs
[10:00:29] [PASSED] 12 VFs
[10:00:29] [PASSED] 13 VFs
[10:00:29] [PASSED] 14 VFs
[10:00:29] [PASSED] 15 VFs
[10:00:29] [PASSED] 16 VFs
[10:00:29] [PASSED] 17 VFs
[10:00:29] [PASSED] 18 VFs
[10:00:29] [PASSED] 19 VFs
[10:00:29] [PASSED] 20 VFs
[10:00:29] [PASSED] 21 VFs
[10:00:29] [PASSED] 22 VFs
[10:00:29] [PASSED] 23 VFs
[10:00:29] [PASSED] 24 VFs
[10:00:29] [PASSED] 25 VFs
[10:00:29] [PASSED] 26 VFs
[10:00:29] [PASSED] 27 VFs
[10:00:29] [PASSED] 28 VFs
[10:00:29] [PASSED] 29 VFs
[10:00:29] [PASSED] 30 VFs
[10:00:29] [PASSED] 31 VFs
[10:00:29] [PASSED] 32 VFs
[10:00:29] [PASSED] 33 VFs
[10:00:29] [PASSED] 34 VFs
[10:00:29] [PASSED] 35 VFs
[10:00:29] [PASSED] 36 VFs
[10:00:29] [PASSED] 37 VFs
[10:00:29] [PASSED] 38 VFs
[10:00:29] [PASSED] 39 VFs
[10:00:29] [PASSED] 40 VFs
[10:00:29] [PASSED] 41 VFs
[10:00:29] [PASSED] 42 VFs
[10:00:29] [PASSED] 43 VFs
[10:00:29] [PASSED] 44 VFs
[10:00:29] [PASSED] 45 VFs
[10:00:29] [PASSED] 46 VFs
[10:00:29] [PASSED] 47 VFs
[10:00:29] [PASSED] 48 VFs
[10:00:29] [PASSED] 49 VFs
[10:00:29] [PASSED] 50 VFs
[10:00:29] [PASSED] 51 VFs
[10:00:29] [PASSED] 52 VFs
[10:00:29] [PASSED] 53 VFs
[10:00:29] [PASSED] 54 VFs
[10:00:29] [PASSED] 55 VFs
[10:00:29] [PASSED] 56 VFs
[10:00:29] [PASSED] 57 VFs
[10:00:29] [PASSED] 58 VFs
[10:00:29] [PASSED] 59 VFs
[10:00:29] [PASSED] 60 VFs
[10:00:29] [PASSED] 61 VFs
[10:00:29] [PASSED] 62 VFs
[10:00:29] [PASSED] 63 VFs
[10:00:29] ==================== [PASSED] fair_vram ====================
[10:00:29] ================== [PASSED] pf_gt_config ===================
[10:00:29] ===================== lmtt (1 subtest) =====================
[10:00:29] ======================== test_ops =========================
[10:00:29] [PASSED] 2-level
[10:00:29] [PASSED] multi-level
[10:00:29] ==================== [PASSED] test_ops =====================
[10:00:29] ====================== [PASSED] lmtt =======================
[10:00:29] ================= pf_service (11 subtests) =================
[10:00:29] [PASSED] pf_negotiate_any
[10:00:29] [PASSED] pf_negotiate_base_match
[10:00:29] [PASSED] pf_negotiate_base_newer
[10:00:29] [PASSED] pf_negotiate_base_next
[10:00:29] [SKIPPED] pf_negotiate_base_older
[10:00:29] [PASSED] pf_negotiate_base_prev
[10:00:29] [PASSED] pf_negotiate_latest_match
[10:00:29] [PASSED] pf_negotiate_latest_newer
[10:00:29] [PASSED] pf_negotiate_latest_next
[10:00:29] [SKIPPED] pf_negotiate_latest_older
[10:00:29] [SKIPPED] pf_negotiate_latest_prev
[10:00:29] =================== [PASSED] pf_service ====================
[10:00:29] ================= xe_guc_g2g (2 subtests) ==================
[10:00:29] ============== xe_live_guc_g2g_kunit_default ==============
[10:00:29] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[10:00:29] ============== xe_live_guc_g2g_kunit_allmem ===============
[10:00:29] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[10:00:29] =================== [SKIPPED] xe_guc_g2g ===================
[10:00:29] =================== xe_mocs (2 subtests) ===================
[10:00:29] ================ xe_live_mocs_kernel_kunit ================
[10:00:29] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[10:00:29] ================ xe_live_mocs_reset_kunit =================
[10:00:29] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[10:00:29] ==================== [SKIPPED] xe_mocs =====================
[10:00:29] ================= xe_migrate (2 subtests) ==================
[10:00:29] ================= xe_migrate_sanity_kunit =================
[10:00:29] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[10:00:29] ================== xe_validate_ccs_kunit ==================
[10:00:29] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[10:00:29] =================== [SKIPPED] xe_migrate ===================
[10:00:29] ================== xe_dma_buf (1 subtest) ==================
[10:00:29] ==================== xe_dma_buf_kunit =====================
[10:00:29] ================ [SKIPPED] xe_dma_buf_kunit ================
[10:00:29] =================== [SKIPPED] xe_dma_buf ===================
[10:00:29] ================= xe_bo_shrink (1 subtest) =================
[10:00:29] =================== xe_bo_shrink_kunit ====================
[10:00:29] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[10:00:29] ================== [SKIPPED] xe_bo_shrink ==================
[10:00:29] ==================== xe_bo (2 subtests) ====================
[10:00:29] ================== xe_ccs_migrate_kunit ===================
[10:00:29] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[10:00:29] ==================== xe_bo_evict_kunit ====================
[10:00:29] =============== [SKIPPED] xe_bo_evict_kunit ================
[10:00:29] ===================== [SKIPPED] xe_bo ======================
[10:00:29] ==================== args (13 subtests) ====================
[10:00:29] [PASSED] count_args_test
[10:00:29] [PASSED] call_args_example
[10:00:29] [PASSED] call_args_test
[10:00:29] [PASSED] drop_first_arg_example
[10:00:29] [PASSED] drop_first_arg_test
[10:00:29] [PASSED] first_arg_example
[10:00:29] [PASSED] first_arg_test
[10:00:29] [PASSED] last_arg_example
[10:00:29] [PASSED] last_arg_test
[10:00:29] [PASSED] pick_arg_example
[10:00:29] [PASSED] if_args_example
[10:00:29] [PASSED] if_args_test
[10:00:29] [PASSED] sep_comma_example
[10:00:29] ====================== [PASSED] args =======================
[10:00:29] =================== xe_pci (3 subtests) ====================
[10:00:29] ==================== check_graphics_ip ====================
[10:00:29] [PASSED] 12.00 Xe_LP
[10:00:29] [PASSED] 12.10 Xe_LP+
[10:00:29] [PASSED] 12.55 Xe_HPG
[10:00:29] [PASSED] 12.60 Xe_HPC
[10:00:29] [PASSED] 12.70 Xe_LPG
[10:00:29] [PASSED] 12.71 Xe_LPG
[10:00:29] [PASSED] 12.74 Xe_LPG+
[10:00:29] [PASSED] 20.01 Xe2_HPG
[10:00:29] [PASSED] 20.02 Xe2_HPG
[10:00:29] [PASSED] 20.04 Xe2_LPG
[10:00:29] [PASSED] 30.00 Xe3_LPG
[10:00:29] [PASSED] 30.01 Xe3_LPG
[10:00:29] [PASSED] 30.03 Xe3_LPG
[10:00:29] [PASSED] 30.04 Xe3_LPG
[10:00:29] [PASSED] 30.05 Xe3_LPG
[10:00:29] [PASSED] 35.10 Xe3p_LPG
[10:00:29] [PASSED] 35.11 Xe3p_XPC
[10:00:29] ================ [PASSED] check_graphics_ip ================
[10:00:29] ===================== check_media_ip ======================
[10:00:29] [PASSED] 12.00 Xe_M
[10:00:29] [PASSED] 12.55 Xe_HPM
[10:00:29] [PASSED] 13.00 Xe_LPM+
[10:00:29] [PASSED] 13.01 Xe2_HPM
[10:00:29] [PASSED] 20.00 Xe2_LPM
[10:00:29] [PASSED] 30.00 Xe3_LPM
[10:00:29] [PASSED] 30.02 Xe3_LPM
[10:00:29] [PASSED] 35.00 Xe3p_LPM
[10:00:29] [PASSED] 35.03 Xe3p_HPM
[10:00:29] ================= [PASSED] check_media_ip ==================
[10:00:29] =================== check_platform_desc ===================
[10:00:29] [PASSED] 0x9A60 (TIGERLAKE)
[10:00:29] [PASSED] 0x9A68 (TIGERLAKE)
[10:00:29] [PASSED] 0x9A70 (TIGERLAKE)
[10:00:29] [PASSED] 0x9A40 (TIGERLAKE)
[10:00:29] [PASSED] 0x9A49 (TIGERLAKE)
[10:00:29] [PASSED] 0x9A59 (TIGERLAKE)
[10:00:29] [PASSED] 0x9A78 (TIGERLAKE)
[10:00:29] [PASSED] 0x9AC0 (TIGERLAKE)
[10:00:29] [PASSED] 0x9AC9 (TIGERLAKE)
[10:00:29] [PASSED] 0x9AD9 (TIGERLAKE)
[10:00:29] [PASSED] 0x9AF8 (TIGERLAKE)
[10:00:29] [PASSED] 0x4C80 (ROCKETLAKE)
[10:00:29] [PASSED] 0x4C8A (ROCKETLAKE)
[10:00:29] [PASSED] 0x4C8B (ROCKETLAKE)
[10:00:29] [PASSED] 0x4C8C (ROCKETLAKE)
[10:00:29] [PASSED] 0x4C90 (ROCKETLAKE)
[10:00:29] [PASSED] 0x4C9A (ROCKETLAKE)
[10:00:29] [PASSED] 0x4680 (ALDERLAKE_S)
[10:00:29] [PASSED] 0x4682 (ALDERLAKE_S)
[10:00:29] [PASSED] 0x4688 (ALDERLAKE_S)
[10:00:29] [PASSED] 0x468A (ALDERLAKE_S)
[10:00:29] [PASSED] 0x468B (ALDERLAKE_S)
[10:00:29] [PASSED] 0x4690 (ALDERLAKE_S)
[10:00:29] [PASSED] 0x4692 (ALDERLAKE_S)
[10:00:29] [PASSED] 0x4693 (ALDERLAKE_S)
[10:00:29] [PASSED] 0x46A0 (ALDERLAKE_P)
[10:00:29] [PASSED] 0x46A1 (ALDERLAKE_P)
[10:00:29] [PASSED] 0x46A2 (ALDERLAKE_P)
[10:00:29] [PASSED] 0x46A3 (ALDERLAKE_P)
[10:00:29] [PASSED] 0x46A6 (ALDERLAKE_P)
[10:00:29] [PASSED] 0x46A8 (ALDERLAKE_P)
[10:00:29] [PASSED] 0x46AA (ALDERLAKE_P)
[10:00:29] [PASSED] 0x462A (ALDERLAKE_P)
[10:00:29] [PASSED] 0x4626 (ALDERLAKE_P)
[10:00:29] [PASSED] 0x4628 (ALDERLAKE_P)
[10:00:29] [PASSED] 0x46B0 (ALDERLAKE_P)
[10:00:29] [PASSED] 0x46B1 (ALDERLAKE_P)
[10:00:29] [PASSED] 0x46B2 (ALDERLAKE_P)
[10:00:29] [PASSED] 0x46B3 (ALDERLAKE_P)
[10:00:29] [PASSED] 0x46C0 (ALDERLAKE_P)
[10:00:29] [PASSED] 0x46C1 (ALDERLAKE_P)
[10:00:29] [PASSED] 0x46C2 (ALDERLAKE_P)
[10:00:29] [PASSED] 0x46C3 (ALDERLAKE_P)
[10:00:29] [PASSED] 0x46D0 (ALDERLAKE_N)
[10:00:29] [PASSED] 0x46D1 (ALDERLAKE_N)
[10:00:29] [PASSED] 0x46D2 (ALDERLAKE_N)
[10:00:29] [PASSED] 0x46D3 (ALDERLAKE_N)
[10:00:29] [PASSED] 0x46D4 (ALDERLAKE_N)
[10:00:29] [PASSED] 0xA721 (ALDERLAKE_P)
[10:00:29] [PASSED] 0xA7A1 (ALDERLAKE_P)
[10:00:29] [PASSED] 0xA7A9 (ALDERLAKE_P)
[10:00:29] [PASSED] 0xA7AC (ALDERLAKE_P)
[10:00:29] [PASSED] 0xA7AD (ALDERLAKE_P)
[10:00:29] [PASSED] 0xA720 (ALDERLAKE_P)
[10:00:29] [PASSED] 0xA7A0 (ALDERLAKE_P)
[10:00:29] [PASSED] 0xA7A8 (ALDERLAKE_P)
[10:00:29] [PASSED] 0xA7AA (ALDERLAKE_P)
[10:00:29] [PASSED] 0xA7AB (ALDERLAKE_P)
[10:00:29] [PASSED] 0xA780 (ALDERLAKE_S)
[10:00:29] [PASSED] 0xA781 (ALDERLAKE_S)
[10:00:29] [PASSED] 0xA782 (ALDERLAKE_S)
[10:00:29] [PASSED] 0xA783 (ALDERLAKE_S)
[10:00:29] [PASSED] 0xA788 (ALDERLAKE_S)
[10:00:29] [PASSED] 0xA789 (ALDERLAKE_S)
[10:00:29] [PASSED] 0xA78A (ALDERLAKE_S)
[10:00:29] [PASSED] 0xA78B (ALDERLAKE_S)
[10:00:29] [PASSED] 0x4905 (DG1)
[10:00:29] [PASSED] 0x4906 (DG1)
[10:00:29] [PASSED] 0x4907 (DG1)
[10:00:29] [PASSED] 0x4908 (DG1)
[10:00:29] [PASSED] 0x4909 (DG1)
[10:00:29] [PASSED] 0x56C0 (DG2)
[10:00:29] [PASSED] 0x56C2 (DG2)
[10:00:29] [PASSED] 0x56C1 (DG2)
[10:00:29] [PASSED] 0x7D51 (METEORLAKE)
[10:00:29] [PASSED] 0x7DD1 (METEORLAKE)
[10:00:29] [PASSED] 0x7D41 (METEORLAKE)
[10:00:29] [PASSED] 0x7D67 (METEORLAKE)
[10:00:29] [PASSED] 0xB640 (METEORLAKE)
[10:00:29] [PASSED] 0x56A0 (DG2)
[10:00:29] [PASSED] 0x56A1 (DG2)
[10:00:29] [PASSED] 0x56A2 (DG2)
[10:00:29] [PASSED] 0x56BE (DG2)
[10:00:29] [PASSED] 0x56BF (DG2)
[10:00:29] [PASSED] 0x5690 (DG2)
[10:00:29] [PASSED] 0x5691 (DG2)
[10:00:29] [PASSED] 0x5692 (DG2)
[10:00:29] [PASSED] 0x56A5 (DG2)
[10:00:29] [PASSED] 0x56A6 (DG2)
[10:00:29] [PASSED] 0x56B0 (DG2)
[10:00:29] [PASSED] 0x56B1 (DG2)
[10:00:29] [PASSED] 0x56BA (DG2)
[10:00:29] [PASSED] 0x56BB (DG2)
[10:00:29] [PASSED] 0x56BC (DG2)
[10:00:29] [PASSED] 0x56BD (DG2)
[10:00:29] [PASSED] 0x5693 (DG2)
[10:00:29] [PASSED] 0x5694 (DG2)
[10:00:29] [PASSED] 0x5695 (DG2)
[10:00:29] [PASSED] 0x56A3 (DG2)
[10:00:29] [PASSED] 0x56A4 (DG2)
[10:00:29] [PASSED] 0x56B2 (DG2)
[10:00:29] [PASSED] 0x56B3 (DG2)
[10:00:29] [PASSED] 0x5696 (DG2)
[10:00:29] [PASSED] 0x5697 (DG2)
[10:00:29] [PASSED] 0xB69 (PVC)
[10:00:29] [PASSED] 0xB6E (PVC)
[10:00:29] [PASSED] 0xBD4 (PVC)
[10:00:29] [PASSED] 0xBD5 (PVC)
[10:00:29] [PASSED] 0xBD6 (PVC)
[10:00:29] [PASSED] 0xBD7 (PVC)
[10:00:29] [PASSED] 0xBD8 (PVC)
[10:00:29] [PASSED] 0xBD9 (PVC)
[10:00:29] [PASSED] 0xBDA (PVC)
[10:00:29] [PASSED] 0xBDB (PVC)
[10:00:29] [PASSED] 0xBE0 (PVC)
[10:00:29] [PASSED] 0xBE1 (PVC)
[10:00:29] [PASSED] 0xBE5 (PVC)
[10:00:29] [PASSED] 0x7D40 (METEORLAKE)
[10:00:29] [PASSED] 0x7D45 (METEORLAKE)
[10:00:29] [PASSED] 0x7D55 (METEORLAKE)
[10:00:29] [PASSED] 0x7D60 (METEORLAKE)
[10:00:29] [PASSED] 0x7DD5 (METEORLAKE)
[10:00:29] [PASSED] 0x6420 (LUNARLAKE)
[10:00:29] [PASSED] 0x64A0 (LUNARLAKE)
[10:00:29] [PASSED] 0x64B0 (LUNARLAKE)
[10:00:29] [PASSED] 0xE202 (BATTLEMAGE)
[10:00:29] [PASSED] 0xE209 (BATTLEMAGE)
[10:00:29] [PASSED] 0xE20B (BATTLEMAGE)
[10:00:29] [PASSED] 0xE20C (BATTLEMAGE)
[10:00:29] [PASSED] 0xE20D (BATTLEMAGE)
[10:00:29] [PASSED] 0xE210 (BATTLEMAGE)
[10:00:29] [PASSED] 0xE211 (BATTLEMAGE)
[10:00:29] [PASSED] 0xE212 (BATTLEMAGE)
[10:00:29] [PASSED] 0xE216 (BATTLEMAGE)
[10:00:29] [PASSED] 0xE220 (BATTLEMAGE)
[10:00:29] [PASSED] 0xE221 (BATTLEMAGE)
[10:00:29] [PASSED] 0xE222 (BATTLEMAGE)
[10:00:29] [PASSED] 0xE223 (BATTLEMAGE)
[10:00:29] [PASSED] 0xB080 (PANTHERLAKE)
[10:00:29] [PASSED] 0xB081 (PANTHERLAKE)
[10:00:29] [PASSED] 0xB082 (PANTHERLAKE)
[10:00:29] [PASSED] 0xB083 (PANTHERLAKE)
[10:00:29] [PASSED] 0xB084 (PANTHERLAKE)
[10:00:29] [PASSED] 0xB085 (PANTHERLAKE)
[10:00:29] [PASSED] 0xB086 (PANTHERLAKE)
[10:00:29] [PASSED] 0xB087 (PANTHERLAKE)
[10:00:29] [PASSED] 0xB08F (PANTHERLAKE)
[10:00:29] [PASSED] 0xB090 (PANTHERLAKE)
[10:00:29] [PASSED] 0xB0A0 (PANTHERLAKE)
[10:00:29] [PASSED] 0xB0B0 (PANTHERLAKE)
[10:00:29] [PASSED] 0xFD80 (PANTHERLAKE)
[10:00:29] [PASSED] 0xFD81 (PANTHERLAKE)
[10:00:29] [PASSED] 0xD740 (NOVALAKE_S)
[10:00:29] [PASSED] 0xD741 (NOVALAKE_S)
[10:00:29] [PASSED] 0xD742 (NOVALAKE_S)
[10:00:29] [PASSED] 0xD743 (NOVALAKE_S)
[10:00:29] [PASSED] 0xD744 (NOVALAKE_S)
[10:00:29] [PASSED] 0xD745 (NOVALAKE_S)
[10:00:29] [PASSED] 0x674C (CRESCENTISLAND)
[10:00:29] [PASSED] 0xD750 (NOVALAKE_P)
[10:00:29] [PASSED] 0xD751 (NOVALAKE_P)
[10:00:29] [PASSED] 0xD752 (NOVALAKE_P)
[10:00:29] [PASSED] 0xD753 (NOVALAKE_P)
[10:00:29] [PASSED] 0xD754 (NOVALAKE_P)
[10:00:29] [PASSED] 0xD755 (NOVALAKE_P)
[10:00:29] [PASSED] 0xD756 (NOVALAKE_P)
[10:00:29] [PASSED] 0xD757 (NOVALAKE_P)
[10:00:29] [PASSED] 0xD75F (NOVALAKE_P)
[10:00:29] =============== [PASSED] check_platform_desc ===============
[10:00:29] ===================== [PASSED] xe_pci ======================
[10:00:29] =================== xe_rtp (2 subtests) ====================
[10:00:29] =============== xe_rtp_process_to_sr_tests ================
[10:00:29] [PASSED] coalesce-same-reg
[10:00:29] [PASSED] no-match-no-add
[10:00:29] [PASSED] match-or
[10:00:29] [PASSED] match-or-xfail
[10:00:29] [PASSED] no-match-no-add-multiple-rules
[10:00:29] [PASSED] two-regs-two-entries
[10:00:29] [PASSED] clr-one-set-other
[10:00:29] [PASSED] set-field
[10:00:29] [PASSED] conflict-duplicate
stty: 'standard input': Inappropriate ioctl for device
[10:00:29] [PASSED] conflict-not-disjoint
[10:00:29] [PASSED] conflict-reg-type
[10:00:29] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[10:00:29] ================== xe_rtp_process_tests ===================
[10:00:29] [PASSED] active1
[10:00:29] [PASSED] active2
[10:00:29] [PASSED] active-inactive
[10:00:29] [PASSED] inactive-active
[10:00:29] [PASSED] inactive-1st_or_active-inactive
[10:00:29] [PASSED] inactive-2nd_or_active-inactive
[10:00:29] [PASSED] inactive-last_or_active-inactive
[10:00:29] [PASSED] inactive-no_or_active-inactive
[10:00:29] ============== [PASSED] xe_rtp_process_tests ===============
[10:00:29] ===================== [PASSED] xe_rtp ======================
[10:00:29] ==================== xe_wa (1 subtest) =====================
[10:00:29] ======================== xe_wa_gt =========================
[10:00:29] [PASSED] TIGERLAKE B0
[10:00:29] [PASSED] DG1 A0
[10:00:29] [PASSED] DG1 B0
[10:00:29] [PASSED] ALDERLAKE_S A0
[10:00:29] [PASSED] ALDERLAKE_S B0
[10:00:29] [PASSED] ALDERLAKE_S C0
[10:00:29] [PASSED] ALDERLAKE_S D0
[10:00:29] [PASSED] ALDERLAKE_P A0
[10:00:29] [PASSED] ALDERLAKE_P B0
[10:00:29] [PASSED] ALDERLAKE_P C0
[10:00:29] [PASSED] ALDERLAKE_S RPLS D0
[10:00:29] [PASSED] ALDERLAKE_P RPLU E0
[10:00:29] [PASSED] DG2 G10 C0
[10:00:29] [PASSED] DG2 G11 B1
[10:00:29] [PASSED] DG2 G12 A1
[10:00:29] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[10:00:29] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[10:00:29] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[10:00:29] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[10:00:29] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[10:00:29] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[10:00:29] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[10:00:29] ==================== [PASSED] xe_wa_gt =====================
[10:00:29] ====================== [PASSED] xe_wa ======================
[10:00:29] ============================================================
[10:00:29] Testing complete. Ran 597 tests: passed: 579, skipped: 18
[10:00:29] Elapsed time: 35.496s total, 4.231s configuring, 30.598s building, 0.616s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[10:00:29] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:00:31] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[10:00:55] Starting KUnit Kernel (1/1)...
[10:00:55] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:00:55] ============ drm_test_pick_cmdline (2 subtests) ============
[10:00:55] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[10:00:55] =============== drm_test_pick_cmdline_named ===============
[10:00:55] [PASSED] NTSC
[10:00:55] [PASSED] NTSC-J
[10:00:55] [PASSED] PAL
[10:00:55] [PASSED] PAL-M
[10:00:55] =========== [PASSED] drm_test_pick_cmdline_named ===========
[10:00:55] ============== [PASSED] drm_test_pick_cmdline ==============
[10:00:55] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[10:00:55] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[10:00:55] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[10:00:55] =========== drm_validate_clone_mode (2 subtests) ===========
[10:00:55] ============== drm_test_check_in_clone_mode ===============
[10:00:55] [PASSED] in_clone_mode
[10:00:55] [PASSED] not_in_clone_mode
[10:00:55] ========== [PASSED] drm_test_check_in_clone_mode ===========
[10:00:55] =============== drm_test_check_valid_clones ===============
[10:00:55] [PASSED] not_in_clone_mode
[10:00:55] [PASSED] valid_clone
[10:00:55] [PASSED] invalid_clone
[10:00:55] =========== [PASSED] drm_test_check_valid_clones ===========
[10:00:55] ============= [PASSED] drm_validate_clone_mode =============
[10:00:55] ============= drm_validate_modeset (1 subtest) =============
[10:00:55] [PASSED] drm_test_check_connector_changed_modeset
[10:00:55] ============== [PASSED] drm_validate_modeset ===============
[10:00:55] ====== drm_test_bridge_get_current_state (2 subtests) ======
[10:00:55] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[10:00:55] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[10:00:55] ======== [PASSED] drm_test_bridge_get_current_state ========
[10:00:55] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[10:00:55] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[10:00:55] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[10:00:55] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[10:00:55] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[10:00:55] ============== drm_bridge_alloc (2 subtests) ===============
[10:00:55] [PASSED] drm_test_drm_bridge_alloc_basic
[10:00:55] [PASSED] drm_test_drm_bridge_alloc_get_put
[10:00:55] ================ [PASSED] drm_bridge_alloc =================
[10:00:55] ============= drm_cmdline_parser (40 subtests) =============
[10:00:55] [PASSED] drm_test_cmdline_force_d_only
[10:00:55] [PASSED] drm_test_cmdline_force_D_only_dvi
[10:00:55] [PASSED] drm_test_cmdline_force_D_only_hdmi
[10:00:55] [PASSED] drm_test_cmdline_force_D_only_not_digital
[10:00:55] [PASSED] drm_test_cmdline_force_e_only
[10:00:55] [PASSED] drm_test_cmdline_res
[10:00:55] [PASSED] drm_test_cmdline_res_vesa
[10:00:55] [PASSED] drm_test_cmdline_res_vesa_rblank
[10:00:55] [PASSED] drm_test_cmdline_res_rblank
[10:00:55] [PASSED] drm_test_cmdline_res_bpp
[10:00:55] [PASSED] drm_test_cmdline_res_refresh
[10:00:55] [PASSED] drm_test_cmdline_res_bpp_refresh
[10:00:55] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[10:00:55] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[10:00:55] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[10:00:55] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[10:00:55] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[10:00:55] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[10:00:55] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[10:00:55] [PASSED] drm_test_cmdline_res_margins_force_on
[10:00:55] [PASSED] drm_test_cmdline_res_vesa_margins
[10:00:55] [PASSED] drm_test_cmdline_name
[10:00:55] [PASSED] drm_test_cmdline_name_bpp
[10:00:55] [PASSED] drm_test_cmdline_name_option
[10:00:55] [PASSED] drm_test_cmdline_name_bpp_option
[10:00:55] [PASSED] drm_test_cmdline_rotate_0
[10:00:55] [PASSED] drm_test_cmdline_rotate_90
[10:00:55] [PASSED] drm_test_cmdline_rotate_180
[10:00:55] [PASSED] drm_test_cmdline_rotate_270
[10:00:55] [PASSED] drm_test_cmdline_hmirror
[10:00:55] [PASSED] drm_test_cmdline_vmirror
[10:00:55] [PASSED] drm_test_cmdline_margin_options
[10:00:55] [PASSED] drm_test_cmdline_multiple_options
[10:00:55] [PASSED] drm_test_cmdline_bpp_extra_and_option
[10:00:55] [PASSED] drm_test_cmdline_extra_and_option
[10:00:55] [PASSED] drm_test_cmdline_freestanding_options
[10:00:55] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[10:00:55] [PASSED] drm_test_cmdline_panel_orientation
[10:00:55] ================ drm_test_cmdline_invalid =================
[10:00:55] [PASSED] margin_only
[10:00:55] [PASSED] interlace_only
[10:00:55] [PASSED] res_missing_x
[10:00:55] [PASSED] res_missing_y
[10:00:55] [PASSED] res_bad_y
[10:00:55] [PASSED] res_missing_y_bpp
[10:00:55] [PASSED] res_bad_bpp
[10:00:55] [PASSED] res_bad_refresh
[10:00:55] [PASSED] res_bpp_refresh_force_on_off
[10:00:55] [PASSED] res_invalid_mode
[10:00:55] [PASSED] res_bpp_wrong_place_mode
[10:00:55] [PASSED] name_bpp_refresh
[10:00:55] [PASSED] name_refresh
[10:00:55] [PASSED] name_refresh_wrong_mode
[10:00:55] [PASSED] name_refresh_invalid_mode
[10:00:55] [PASSED] rotate_multiple
[10:00:55] [PASSED] rotate_invalid_val
[10:00:55] [PASSED] rotate_truncated
[10:00:55] [PASSED] invalid_option
[10:00:55] [PASSED] invalid_tv_option
[10:00:55] [PASSED] truncated_tv_option
[10:00:55] ============ [PASSED] drm_test_cmdline_invalid =============
[10:00:55] =============== drm_test_cmdline_tv_options ===============
[10:00:55] [PASSED] NTSC
[10:00:55] [PASSED] NTSC_443
[10:00:55] [PASSED] NTSC_J
[10:00:55] [PASSED] PAL
[10:00:55] [PASSED] PAL_M
[10:00:55] [PASSED] PAL_N
[10:00:55] [PASSED] SECAM
[10:00:55] [PASSED] MONO_525
[10:00:55] [PASSED] MONO_625
[10:00:55] =========== [PASSED] drm_test_cmdline_tv_options ===========
[10:00:55] =============== [PASSED] drm_cmdline_parser ================
[10:00:55] ========== drmm_connector_hdmi_init (20 subtests) ==========
[10:00:55] [PASSED] drm_test_connector_hdmi_init_valid
[10:00:55] [PASSED] drm_test_connector_hdmi_init_bpc_8
[10:00:55] [PASSED] drm_test_connector_hdmi_init_bpc_10
[10:00:55] [PASSED] drm_test_connector_hdmi_init_bpc_12
[10:00:55] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[10:00:55] [PASSED] drm_test_connector_hdmi_init_bpc_null
[10:00:55] [PASSED] drm_test_connector_hdmi_init_formats_empty
[10:00:55] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[10:00:55] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[10:00:55] [PASSED] supported_formats=0x9 yuv420_allowed=1
[10:00:55] [PASSED] supported_formats=0x9 yuv420_allowed=0
[10:00:55] [PASSED] supported_formats=0x3 yuv420_allowed=1
[10:00:55] [PASSED] supported_formats=0x3 yuv420_allowed=0
[10:00:55] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[10:00:55] [PASSED] drm_test_connector_hdmi_init_null_ddc
[10:00:55] [PASSED] drm_test_connector_hdmi_init_null_product
[10:00:55] [PASSED] drm_test_connector_hdmi_init_null_vendor
[10:00:55] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[10:00:55] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[10:00:55] [PASSED] drm_test_connector_hdmi_init_product_valid
[10:00:55] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[10:00:55] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[10:00:55] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[10:00:55] ========= drm_test_connector_hdmi_init_type_valid =========
[10:00:55] [PASSED] HDMI-A
[10:00:55] [PASSED] HDMI-B
[10:00:55] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[10:00:55] ======== drm_test_connector_hdmi_init_type_invalid ========
[10:00:55] [PASSED] Unknown
[10:00:55] [PASSED] VGA
[10:00:55] [PASSED] DVI-I
[10:00:55] [PASSED] DVI-D
[10:00:55] [PASSED] DVI-A
[10:00:55] [PASSED] Composite
[10:00:55] [PASSED] SVIDEO
[10:00:55] [PASSED] LVDS
[10:00:55] [PASSED] Component
[10:00:55] [PASSED] DIN
[10:00:55] [PASSED] DP
[10:00:55] [PASSED] TV
[10:00:55] [PASSED] eDP
[10:00:55] [PASSED] Virtual
[10:00:55] [PASSED] DSI
[10:00:55] [PASSED] DPI
[10:00:55] [PASSED] Writeback
[10:00:55] [PASSED] SPI
[10:00:55] [PASSED] USB
[10:00:55] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[10:00:55] ============ [PASSED] drmm_connector_hdmi_init =============
[10:00:55] ============= drmm_connector_init (3 subtests) =============
[10:00:55] [PASSED] drm_test_drmm_connector_init
[10:00:55] [PASSED] drm_test_drmm_connector_init_null_ddc
[10:00:55] ========= drm_test_drmm_connector_init_type_valid =========
[10:00:55] [PASSED] Unknown
[10:00:55] [PASSED] VGA
[10:00:55] [PASSED] DVI-I
[10:00:55] [PASSED] DVI-D
[10:00:55] [PASSED] DVI-A
[10:00:55] [PASSED] Composite
[10:00:55] [PASSED] SVIDEO
[10:00:55] [PASSED] LVDS
[10:00:55] [PASSED] Component
[10:00:55] [PASSED] DIN
[10:00:55] [PASSED] DP
[10:00:55] [PASSED] HDMI-A
[10:00:55] [PASSED] HDMI-B
[10:00:55] [PASSED] TV
[10:00:55] [PASSED] eDP
[10:00:55] [PASSED] Virtual
[10:00:55] [PASSED] DSI
[10:00:55] [PASSED] DPI
[10:00:55] [PASSED] Writeback
[10:00:55] [PASSED] SPI
[10:00:55] [PASSED] USB
[10:00:55] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[10:00:55] =============== [PASSED] drmm_connector_init ===============
[10:00:55] ========= drm_connector_dynamic_init (6 subtests) ==========
[10:00:55] [PASSED] drm_test_drm_connector_dynamic_init
[10:00:55] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[10:00:55] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[10:00:55] [PASSED] drm_test_drm_connector_dynamic_init_properties
[10:00:55] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[10:00:55] [PASSED] Unknown
[10:00:55] [PASSED] VGA
[10:00:55] [PASSED] DVI-I
[10:00:55] [PASSED] DVI-D
[10:00:55] [PASSED] DVI-A
[10:00:55] [PASSED] Composite
[10:00:55] [PASSED] SVIDEO
[10:00:55] [PASSED] LVDS
[10:00:55] [PASSED] Component
[10:00:55] [PASSED] DIN
[10:00:55] [PASSED] DP
[10:00:55] [PASSED] HDMI-A
[10:00:55] [PASSED] HDMI-B
[10:00:55] [PASSED] TV
[10:00:55] [PASSED] eDP
[10:00:55] [PASSED] Virtual
[10:00:55] [PASSED] DSI
[10:00:55] [PASSED] DPI
[10:00:55] [PASSED] Writeback
[10:00:55] [PASSED] SPI
[10:00:55] [PASSED] USB
[10:00:55] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[10:00:55] ======== drm_test_drm_connector_dynamic_init_name =========
[10:00:55] [PASSED] Unknown
[10:00:55] [PASSED] VGA
[10:00:55] [PASSED] DVI-I
[10:00:55] [PASSED] DVI-D
[10:00:55] [PASSED] DVI-A
[10:00:55] [PASSED] Composite
[10:00:55] [PASSED] SVIDEO
[10:00:55] [PASSED] LVDS
[10:00:55] [PASSED] Component
[10:00:55] [PASSED] DIN
[10:00:55] [PASSED] DP
[10:00:55] [PASSED] HDMI-A
[10:00:55] [PASSED] HDMI-B
[10:00:55] [PASSED] TV
[10:00:55] [PASSED] eDP
[10:00:55] [PASSED] Virtual
[10:00:55] [PASSED] DSI
[10:00:55] [PASSED] DPI
[10:00:55] [PASSED] Writeback
[10:00:55] [PASSED] SPI
[10:00:55] [PASSED] USB
[10:00:55] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[10:00:55] =========== [PASSED] drm_connector_dynamic_init ============
[10:00:55] ==== drm_connector_dynamic_register_early (4 subtests) =====
[10:00:55] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[10:00:55] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[10:00:55] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[10:00:55] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[10:00:55] ====== [PASSED] drm_connector_dynamic_register_early =======
[10:00:55] ======= drm_connector_dynamic_register (7 subtests) ========
[10:00:55] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[10:00:55] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[10:00:55] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[10:00:55] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[10:00:55] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[10:00:55] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[10:00:55] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[10:00:55] ========= [PASSED] drm_connector_dynamic_register ==========
[10:00:55] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[10:00:55] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[10:00:55] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[10:00:55] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[10:00:55] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[10:00:55] ========== drm_test_get_tv_mode_from_name_valid ===========
[10:00:55] [PASSED] NTSC
[10:00:55] [PASSED] NTSC-443
[10:00:55] [PASSED] NTSC-J
[10:00:55] [PASSED] PAL
[10:00:55] [PASSED] PAL-M
[10:00:55] [PASSED] PAL-N
[10:00:55] [PASSED] SECAM
[10:00:55] [PASSED] Mono
[10:00:55] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[10:00:55] [PASSED] drm_test_get_tv_mode_from_name_truncated
[10:00:55] ============ [PASSED] drm_get_tv_mode_from_name ============
[10:00:55] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[10:00:55] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[10:00:55] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[10:00:55] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[10:00:55] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[10:00:55] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[10:00:55] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[10:00:55] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[10:00:55] [PASSED] VIC 96
[10:00:55] [PASSED] VIC 97
[10:00:55] [PASSED] VIC 101
[10:00:55] [PASSED] VIC 102
[10:00:55] [PASSED] VIC 106
[10:00:55] [PASSED] VIC 107
[10:00:55] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[10:00:55] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[10:00:55] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[10:00:55] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[10:00:55] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[10:00:55] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[10:00:55] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[10:00:55] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[10:00:55] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[10:00:55] [PASSED] Automatic
[10:00:55] [PASSED] Full
[10:00:55] [PASSED] Limited 16:235
[10:00:55] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[10:00:55] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[10:00:55] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[10:00:55] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[10:00:55] === drm_test_drm_hdmi_connector_get_output_format_name ====
[10:00:55] [PASSED] RGB
[10:00:55] [PASSED] YUV 4:2:0
[10:00:55] [PASSED] YUV 4:2:2
[10:00:55] [PASSED] YUV 4:4:4
[10:00:55] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[10:00:55] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[10:00:55] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[10:00:55] ============= drm_damage_helper (21 subtests) ==============
[10:00:55] [PASSED] drm_test_damage_iter_no_damage
[10:00:55] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[10:00:55] [PASSED] drm_test_damage_iter_no_damage_src_moved
[10:00:55] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[10:00:55] [PASSED] drm_test_damage_iter_no_damage_not_visible
[10:00:55] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[10:00:55] [PASSED] drm_test_damage_iter_no_damage_no_fb
[10:00:55] [PASSED] drm_test_damage_iter_simple_damage
[10:00:55] [PASSED] drm_test_damage_iter_single_damage
[10:00:55] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[10:00:55] [PASSED] drm_test_damage_iter_single_damage_outside_src
[10:00:55] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[10:00:55] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[10:00:55] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[10:00:55] [PASSED] drm_test_damage_iter_single_damage_src_moved
[10:00:55] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[10:00:55] [PASSED] drm_test_damage_iter_damage
[10:00:55] [PASSED] drm_test_damage_iter_damage_one_intersect
[10:00:55] [PASSED] drm_test_damage_iter_damage_one_outside
[10:00:55] [PASSED] drm_test_damage_iter_damage_src_moved
[10:00:55] [PASSED] drm_test_damage_iter_damage_not_visible
[10:00:55] ================ [PASSED] drm_damage_helper ================
[10:00:55] ============== drm_dp_mst_helper (3 subtests) ==============
[10:00:55] ============== drm_test_dp_mst_calc_pbn_mode ==============
[10:00:55] [PASSED] Clock 154000 BPP 30 DSC disabled
[10:00:55] [PASSED] Clock 234000 BPP 30 DSC disabled
[10:00:55] [PASSED] Clock 297000 BPP 24 DSC disabled
[10:00:55] [PASSED] Clock 332880 BPP 24 DSC enabled
[10:00:55] [PASSED] Clock 324540 BPP 24 DSC enabled
[10:00:55] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[10:00:55] ============== drm_test_dp_mst_calc_pbn_div ===============
[10:00:55] [PASSED] Link rate 2000000 lane count 4
[10:00:55] [PASSED] Link rate 2000000 lane count 2
[10:00:55] [PASSED] Link rate 2000000 lane count 1
[10:00:55] [PASSED] Link rate 1350000 lane count 4
[10:00:55] [PASSED] Link rate 1350000 lane count 2
[10:00:55] [PASSED] Link rate 1350000 lane count 1
[10:00:55] [PASSED] Link rate 1000000 lane count 4
[10:00:55] [PASSED] Link rate 1000000 lane count 2
[10:00:55] [PASSED] Link rate 1000000 lane count 1
[10:00:55] [PASSED] Link rate 810000 lane count 4
[10:00:55] [PASSED] Link rate 810000 lane count 2
[10:00:55] [PASSED] Link rate 810000 lane count 1
[10:00:55] [PASSED] Link rate 540000 lane count 4
[10:00:55] [PASSED] Link rate 540000 lane count 2
[10:00:55] [PASSED] Link rate 540000 lane count 1
[10:00:55] [PASSED] Link rate 270000 lane count 4
[10:00:55] [PASSED] Link rate 270000 lane count 2
[10:00:55] [PASSED] Link rate 270000 lane count 1
[10:00:55] [PASSED] Link rate 162000 lane count 4
[10:00:55] [PASSED] Link rate 162000 lane count 2
[10:00:55] [PASSED] Link rate 162000 lane count 1
[10:00:55] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[10:00:55] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[10:00:55] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[10:00:55] [PASSED] DP_POWER_UP_PHY with port number
[10:00:55] [PASSED] DP_POWER_DOWN_PHY with port number
[10:00:55] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[10:00:55] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[10:00:55] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[10:00:55] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[10:00:55] [PASSED] DP_QUERY_PAYLOAD with port number
[10:00:55] [PASSED] DP_QUERY_PAYLOAD with VCPI
[10:00:55] [PASSED] DP_REMOTE_DPCD_READ with port number
[10:00:55] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[10:00:55] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[10:00:55] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[10:00:55] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[10:00:55] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[10:00:55] [PASSED] DP_REMOTE_I2C_READ with port number
[10:00:55] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[10:00:55] [PASSED] DP_REMOTE_I2C_READ with transactions array
[10:00:55] [PASSED] DP_REMOTE_I2C_WRITE with port number
[10:00:55] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[10:00:55] [PASSED] DP_REMOTE_I2C_WRITE with data array
[10:00:55] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[10:00:55] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[10:00:55] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[10:00:55] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[10:00:55] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[10:00:55] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[10:00:55] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[10:00:55] ================ [PASSED] drm_dp_mst_helper ================
[10:00:55] ================== drm_exec (7 subtests) ===================
[10:00:55] [PASSED] sanitycheck
[10:00:55] [PASSED] test_lock
[10:00:55] [PASSED] test_lock_unlock
[10:00:55] [PASSED] test_duplicates
[10:00:55] [PASSED] test_prepare
[10:00:55] [PASSED] test_prepare_array
[10:00:55] [PASSED] test_multiple_loops
[10:00:55] ==================== [PASSED] drm_exec =====================
[10:00:55] =========== drm_format_helper_test (17 subtests) ===========
[10:00:55] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[10:00:55] [PASSED] single_pixel_source_buffer
[10:00:55] [PASSED] single_pixel_clip_rectangle
[10:00:55] [PASSED] well_known_colors
[10:00:55] [PASSED] destination_pitch
[10:00:55] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[10:00:55] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[10:00:55] [PASSED] single_pixel_source_buffer
[10:00:55] [PASSED] single_pixel_clip_rectangle
[10:00:55] [PASSED] well_known_colors
[10:00:55] [PASSED] destination_pitch
[10:00:55] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[10:00:55] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[10:00:55] [PASSED] single_pixel_source_buffer
[10:00:55] [PASSED] single_pixel_clip_rectangle
[10:00:55] [PASSED] well_known_colors
[10:00:55] [PASSED] destination_pitch
[10:00:55] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[10:00:55] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[10:00:55] [PASSED] single_pixel_source_buffer
[10:00:55] [PASSED] single_pixel_clip_rectangle
[10:00:55] [PASSED] well_known_colors
[10:00:55] [PASSED] destination_pitch
[10:00:55] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[10:00:55] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[10:00:55] [PASSED] single_pixel_source_buffer
[10:00:55] [PASSED] single_pixel_clip_rectangle
[10:00:55] [PASSED] well_known_colors
[10:00:55] [PASSED] destination_pitch
[10:00:55] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[10:00:55] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[10:00:55] [PASSED] single_pixel_source_buffer
[10:00:55] [PASSED] single_pixel_clip_rectangle
[10:00:55] [PASSED] well_known_colors
[10:00:55] [PASSED] destination_pitch
[10:00:55] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[10:00:55] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[10:00:55] [PASSED] single_pixel_source_buffer
[10:00:55] [PASSED] single_pixel_clip_rectangle
[10:00:55] [PASSED] well_known_colors
[10:00:55] [PASSED] destination_pitch
[10:00:55] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[10:00:55] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[10:00:55] [PASSED] single_pixel_source_buffer
[10:00:55] [PASSED] single_pixel_clip_rectangle
[10:00:55] [PASSED] well_known_colors
[10:00:55] [PASSED] destination_pitch
[10:00:55] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[10:00:55] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[10:00:55] [PASSED] single_pixel_source_buffer
[10:00:55] [PASSED] single_pixel_clip_rectangle
[10:00:55] [PASSED] well_known_colors
[10:00:55] [PASSED] destination_pitch
[10:00:55] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[10:00:55] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[10:00:55] [PASSED] single_pixel_source_buffer
[10:00:55] [PASSED] single_pixel_clip_rectangle
[10:00:55] [PASSED] well_known_colors
[10:00:55] [PASSED] destination_pitch
[10:00:55] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[10:00:55] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[10:00:55] [PASSED] single_pixel_source_buffer
[10:00:55] [PASSED] single_pixel_clip_rectangle
[10:00:55] [PASSED] well_known_colors
[10:00:55] [PASSED] destination_pitch
[10:00:55] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[10:00:55] ============== drm_test_fb_xrgb8888_to_mono ===============
[10:00:55] [PASSED] single_pixel_source_buffer
[10:00:55] [PASSED] single_pixel_clip_rectangle
[10:00:55] [PASSED] well_known_colors
[10:00:55] [PASSED] destination_pitch
[10:00:55] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[10:00:55] ==================== drm_test_fb_swab =====================
[10:00:55] [PASSED] single_pixel_source_buffer
[10:00:55] [PASSED] single_pixel_clip_rectangle
[10:00:55] [PASSED] well_known_colors
[10:00:55] [PASSED] destination_pitch
[10:00:55] ================ [PASSED] drm_test_fb_swab =================
[10:00:55] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[10:00:55] [PASSED] single_pixel_source_buffer
[10:00:55] [PASSED] single_pixel_clip_rectangle
[10:00:55] [PASSED] well_known_colors
[10:00:55] [PASSED] destination_pitch
[10:00:55] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[10:00:55] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[10:00:55] [PASSED] single_pixel_source_buffer
[10:00:55] [PASSED] single_pixel_clip_rectangle
[10:00:55] [PASSED] well_known_colors
[10:00:55] [PASSED] destination_pitch
[10:00:55] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[10:00:55] ================= drm_test_fb_clip_offset =================
[10:00:55] [PASSED] pass through
[10:00:55] [PASSED] horizontal offset
[10:00:55] [PASSED] vertical offset
[10:00:55] [PASSED] horizontal and vertical offset
[10:00:55] [PASSED] horizontal offset (custom pitch)
[10:00:55] [PASSED] vertical offset (custom pitch)
[10:00:55] [PASSED] horizontal and vertical offset (custom pitch)
[10:00:55] ============= [PASSED] drm_test_fb_clip_offset =============
[10:00:55] =================== drm_test_fb_memcpy ====================
[10:00:55] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[10:00:55] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[10:00:55] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[10:00:55] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[10:00:55] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[10:00:55] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[10:00:55] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[10:00:55] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[10:00:55] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[10:00:55] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[10:00:55] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[10:00:55] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[10:00:55] =============== [PASSED] drm_test_fb_memcpy ================
[10:00:55] ============= [PASSED] drm_format_helper_test ==============
[10:00:55] ================= drm_format (18 subtests) =================
[10:00:55] [PASSED] drm_test_format_block_width_invalid
[10:00:55] [PASSED] drm_test_format_block_width_one_plane
[10:00:55] [PASSED] drm_test_format_block_width_two_plane
[10:00:55] [PASSED] drm_test_format_block_width_three_plane
[10:00:55] [PASSED] drm_test_format_block_width_tiled
[10:00:55] [PASSED] drm_test_format_block_height_invalid
[10:00:55] [PASSED] drm_test_format_block_height_one_plane
[10:00:55] [PASSED] drm_test_format_block_height_two_plane
[10:00:55] [PASSED] drm_test_format_block_height_three_plane
[10:00:55] [PASSED] drm_test_format_block_height_tiled
[10:00:55] [PASSED] drm_test_format_min_pitch_invalid
[10:00:55] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[10:00:55] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[10:00:55] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[10:00:55] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[10:00:55] [PASSED] drm_test_format_min_pitch_two_plane
[10:00:55] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[10:00:55] [PASSED] drm_test_format_min_pitch_tiled
[10:00:55] =================== [PASSED] drm_format ====================
[10:00:55] ============== drm_framebuffer (10 subtests) ===============
[10:00:55] ========== drm_test_framebuffer_check_src_coords ==========
[10:00:55] [PASSED] Success: source fits into fb
[10:00:55] [PASSED] Fail: overflowing fb with x-axis coordinate
[10:00:55] [PASSED] Fail: overflowing fb with y-axis coordinate
[10:00:55] [PASSED] Fail: overflowing fb with source width
[10:00:55] [PASSED] Fail: overflowing fb with source height
[10:00:55] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[10:00:55] [PASSED] drm_test_framebuffer_cleanup
[10:00:55] =============== drm_test_framebuffer_create ===============
[10:00:55] [PASSED] ABGR8888 normal sizes
[10:00:55] [PASSED] ABGR8888 max sizes
[10:00:55] [PASSED] ABGR8888 pitch greater than min required
[10:00:55] [PASSED] ABGR8888 pitch less than min required
[10:00:55] [PASSED] ABGR8888 Invalid width
[10:00:55] [PASSED] ABGR8888 Invalid buffer handle
[10:00:55] [PASSED] No pixel format
[10:00:55] [PASSED] ABGR8888 Width 0
[10:00:55] [PASSED] ABGR8888 Height 0
[10:00:55] [PASSED] ABGR8888 Out of bound height * pitch combination
[10:00:55] [PASSED] ABGR8888 Large buffer offset
[10:00:55] [PASSED] ABGR8888 Buffer offset for inexistent plane
[10:00:55] [PASSED] ABGR8888 Invalid flag
[10:00:55] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[10:00:55] [PASSED] ABGR8888 Valid buffer modifier
[10:00:55] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[10:00:55] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[10:00:55] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[10:00:55] [PASSED] NV12 Normal sizes
[10:00:55] [PASSED] NV12 Max sizes
[10:00:55] [PASSED] NV12 Invalid pitch
[10:00:55] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[10:00:55] [PASSED] NV12 different modifier per-plane
[10:00:55] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[10:00:55] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[10:00:55] [PASSED] NV12 Modifier for inexistent plane
[10:00:55] [PASSED] NV12 Handle for inexistent plane
[10:00:55] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[10:00:55] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[10:00:55] [PASSED] YVU420 Normal sizes
[10:00:55] [PASSED] YVU420 Max sizes
[10:00:55] [PASSED] YVU420 Invalid pitch
[10:00:55] [PASSED] YVU420 Different pitches
[10:00:55] [PASSED] YVU420 Different buffer offsets/pitches
[10:00:55] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[10:00:55] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[10:00:55] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[10:00:55] [PASSED] YVU420 Valid modifier
[10:00:55] [PASSED] YVU420 Different modifiers per plane
[10:00:55] [PASSED] YVU420 Modifier for inexistent plane
[10:00:55] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[10:00:55] [PASSED] X0L2 Normal sizes
[10:00:55] [PASSED] X0L2 Max sizes
[10:00:55] [PASSED] X0L2 Invalid pitch
[10:00:55] [PASSED] X0L2 Pitch greater than minimum required
[10:00:55] [PASSED] X0L2 Handle for inexistent plane
[10:00:55] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[10:00:55] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[10:00:55] [PASSED] X0L2 Valid modifier
[10:00:55] [PASSED] X0L2 Modifier for inexistent plane
[10:00:55] =========== [PASSED] drm_test_framebuffer_create ===========
[10:00:55] [PASSED] drm_test_framebuffer_free
[10:00:55] [PASSED] drm_test_framebuffer_init
[10:00:55] [PASSED] drm_test_framebuffer_init_bad_format
[10:00:55] [PASSED] drm_test_framebuffer_init_dev_mismatch
[10:00:55] [PASSED] drm_test_framebuffer_lookup
[10:00:55] [PASSED] drm_test_framebuffer_lookup_inexistent
[10:00:55] [PASSED] drm_test_framebuffer_modifiers_not_supported
[10:00:55] ================= [PASSED] drm_framebuffer =================
[10:00:55] ================ drm_gem_shmem (8 subtests) ================
[10:00:55] [PASSED] drm_gem_shmem_test_obj_create
[10:00:55] [PASSED] drm_gem_shmem_test_obj_create_private
[10:00:55] [PASSED] drm_gem_shmem_test_pin_pages
[10:00:55] [PASSED] drm_gem_shmem_test_vmap
[10:00:55] [PASSED] drm_gem_shmem_test_get_sg_table
[10:00:55] [PASSED] drm_gem_shmem_test_get_pages_sgt
[10:00:55] [PASSED] drm_gem_shmem_test_madvise
[10:00:55] [PASSED] drm_gem_shmem_test_purge
[10:00:55] ================== [PASSED] drm_gem_shmem ==================
[10:00:55] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[10:00:55] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[10:00:55] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[10:00:55] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[10:00:55] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[10:00:55] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[10:00:55] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[10:00:55] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[10:00:55] [PASSED] Automatic
[10:00:55] [PASSED] Full
[10:00:55] [PASSED] Limited 16:235
[10:00:55] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[10:00:55] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[10:00:55] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[10:00:55] [PASSED] drm_test_check_disable_connector
[10:00:55] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[10:00:55] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[10:00:55] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[10:00:55] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[10:00:55] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[10:00:55] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[10:00:55] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[10:00:55] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[10:00:55] [PASSED] drm_test_check_output_bpc_dvi
[10:00:55] [PASSED] drm_test_check_output_bpc_format_vic_1
[10:00:55] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[10:00:55] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[10:00:55] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[10:00:55] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[10:00:55] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[10:00:55] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[10:00:55] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[10:00:55] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[10:00:55] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[10:00:55] [PASSED] drm_test_check_broadcast_rgb_value
[10:00:55] [PASSED] drm_test_check_bpc_8_value
[10:00:55] [PASSED] drm_test_check_bpc_10_value
[10:00:55] [PASSED] drm_test_check_bpc_12_value
[10:00:55] [PASSED] drm_test_check_format_value
[10:00:55] [PASSED] drm_test_check_tmds_char_value
[10:00:55] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[10:00:55] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[10:00:55] [PASSED] drm_test_check_mode_valid
[10:00:55] [PASSED] drm_test_check_mode_valid_reject
[10:00:55] [PASSED] drm_test_check_mode_valid_reject_rate
[10:00:55] [PASSED] drm_test_check_mode_valid_reject_max_clock
[10:00:55] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[10:00:55] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[10:00:55] [PASSED] drm_test_check_infoframes
[10:00:55] [PASSED] drm_test_check_reject_avi_infoframe
[10:00:55] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[10:00:55] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[10:00:55] [PASSED] drm_test_check_reject_audio_infoframe
[10:00:55] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[10:00:55] ================= drm_managed (2 subtests) =================
[10:00:55] [PASSED] drm_test_managed_release_action
[10:00:55] [PASSED] drm_test_managed_run_action
[10:00:55] =================== [PASSED] drm_managed ===================
[10:00:55] =================== drm_mm (6 subtests) ====================
[10:00:55] [PASSED] drm_test_mm_init
[10:00:55] [PASSED] drm_test_mm_debug
[10:00:55] [PASSED] drm_test_mm_align32
[10:00:55] [PASSED] drm_test_mm_align64
[10:00:55] [PASSED] drm_test_mm_lowest
[10:00:55] [PASSED] drm_test_mm_highest
[10:00:55] ===================== [PASSED] drm_mm ======================
[10:00:55] ============= drm_modes_analog_tv (5 subtests) =============
[10:00:55] [PASSED] drm_test_modes_analog_tv_mono_576i
[10:00:55] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[10:00:55] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[10:00:55] [PASSED] drm_test_modes_analog_tv_pal_576i
[10:00:55] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[10:00:55] =============== [PASSED] drm_modes_analog_tv ===============
[10:00:55] ============== drm_plane_helper (2 subtests) ===============
[10:00:55] =============== drm_test_check_plane_state ================
[10:00:55] [PASSED] clipping_simple
[10:00:55] [PASSED] clipping_rotate_reflect
[10:00:55] [PASSED] positioning_simple
[10:00:55] [PASSED] upscaling
[10:00:55] [PASSED] downscaling
[10:00:55] [PASSED] rounding1
[10:00:55] [PASSED] rounding2
[10:00:55] [PASSED] rounding3
[10:00:55] [PASSED] rounding4
[10:00:55] =========== [PASSED] drm_test_check_plane_state ============
[10:00:55] =========== drm_test_check_invalid_plane_state ============
[10:00:55] [PASSED] positioning_invalid
[10:00:55] [PASSED] upscaling_invalid
[10:00:55] [PASSED] downscaling_invalid
[10:00:55] ======= [PASSED] drm_test_check_invalid_plane_state ========
[10:00:55] ================ [PASSED] drm_plane_helper =================
[10:00:55] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[10:00:55] ====== drm_test_connector_helper_tv_get_modes_check =======
[10:00:55] [PASSED] None
[10:00:55] [PASSED] PAL
[10:00:55] [PASSED] NTSC
[10:00:55] [PASSED] Both, NTSC Default
[10:00:55] [PASSED] Both, PAL Default
[10:00:55] [PASSED] Both, NTSC Default, with PAL on command-line
[10:00:55] [PASSED] Both, PAL Default, with NTSC on command-line
[10:00:55] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[10:00:55] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[10:00:55] ================== drm_rect (9 subtests) ===================
[10:00:55] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[10:00:55] [PASSED] drm_test_rect_clip_scaled_not_clipped
[10:00:55] [PASSED] drm_test_rect_clip_scaled_clipped
[10:00:55] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[10:00:55] ================= drm_test_rect_intersect =================
[10:00:55] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[10:00:55] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[10:00:55] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[10:00:55] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[10:00:55] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[10:00:55] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[10:00:55] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[10:00:55] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[10:00:55] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[10:00:55] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[10:00:55] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[10:00:55] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[10:00:55] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[10:00:55] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[10:00:55] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[10:00:55] ============= [PASSED] drm_test_rect_intersect =============
[10:00:55] ================ drm_test_rect_calc_hscale ================
[10:00:55] [PASSED] normal use
[10:00:55] [PASSED] out of max range
[10:00:55] [PASSED] out of min range
[10:00:55] [PASSED] zero dst
[10:00:55] [PASSED] negative src
[10:00:55] [PASSED] negative dst
[10:00:55] ============ [PASSED] drm_test_rect_calc_hscale ============
[10:00:55] ================ drm_test_rect_calc_vscale ================
[10:00:55] [PASSED] normal use
[10:00:55] [PASSED] out of max range
[10:00:55] [PASSED] out of min range
[10:00:55] [PASSED] zero dst
[10:00:55] [PASSED] negative src
[10:00:55] [PASSED] negative dst
stty: 'standard input': Inappropriate ioctl for device
[10:00:55] ============ [PASSED] drm_test_rect_calc_vscale ============
[10:00:55] ================== drm_test_rect_rotate ===================
[10:00:55] [PASSED] reflect-x
[10:00:55] [PASSED] reflect-y
[10:00:55] [PASSED] rotate-0
[10:00:55] [PASSED] rotate-90
[10:00:55] [PASSED] rotate-180
[10:00:55] [PASSED] rotate-270
[10:00:55] ============== [PASSED] drm_test_rect_rotate ===============
[10:00:55] ================ drm_test_rect_rotate_inv =================
[10:00:55] [PASSED] reflect-x
[10:00:55] [PASSED] reflect-y
[10:00:55] [PASSED] rotate-0
[10:00:55] [PASSED] rotate-90
[10:00:55] [PASSED] rotate-180
[10:00:55] [PASSED] rotate-270
[10:00:55] ============ [PASSED] drm_test_rect_rotate_inv =============
[10:00:55] ==================== [PASSED] drm_rect =====================
[10:00:55] ============ drm_sysfb_modeset_test (1 subtest) ============
[10:00:55] ============ drm_test_sysfb_build_fourcc_list =============
[10:00:55] [PASSED] no native formats
[10:00:55] [PASSED] XRGB8888 as native format
[10:00:55] [PASSED] remove duplicates
[10:00:55] [PASSED] convert alpha formats
[10:00:55] [PASSED] random formats
[10:00:55] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[10:00:55] ============= [PASSED] drm_sysfb_modeset_test ==============
[10:00:55] ================== drm_fixp (2 subtests) ===================
[10:00:55] [PASSED] drm_test_int2fixp
[10:00:55] [PASSED] drm_test_sm2fixp
[10:00:55] ==================== [PASSED] drm_fixp =====================
[10:00:55] ============================================================
[10:00:55] Testing complete. Ran 621 tests: passed: 621
[10:00:56] Elapsed time: 26.126s total, 1.710s configuring, 24.198s building, 0.168s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[10:00:56] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:00:57] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[10:01:07] Starting KUnit Kernel (1/1)...
[10:01:07] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:01:07] ================= ttm_device (5 subtests) ==================
[10:01:07] [PASSED] ttm_device_init_basic
[10:01:07] [PASSED] ttm_device_init_multiple
[10:01:07] [PASSED] ttm_device_fini_basic
[10:01:07] [PASSED] ttm_device_init_no_vma_man
[10:01:07] ================== ttm_device_init_pools ==================
[10:01:07] [PASSED] No DMA allocations, no DMA32 required
[10:01:07] [PASSED] DMA allocations, DMA32 required
[10:01:07] [PASSED] No DMA allocations, DMA32 required
[10:01:07] [PASSED] DMA allocations, no DMA32 required
[10:01:07] ============== [PASSED] ttm_device_init_pools ==============
[10:01:07] =================== [PASSED] ttm_device ====================
[10:01:07] ================== ttm_pool (8 subtests) ===================
[10:01:07] ================== ttm_pool_alloc_basic ===================
[10:01:07] [PASSED] One page
[10:01:07] [PASSED] More than one page
[10:01:07] [PASSED] Above the allocation limit
[10:01:07] [PASSED] One page, with coherent DMA mappings enabled
[10:01:07] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[10:01:07] ============== [PASSED] ttm_pool_alloc_basic ===============
[10:01:07] ============== ttm_pool_alloc_basic_dma_addr ==============
[10:01:07] [PASSED] One page
[10:01:07] [PASSED] More than one page
[10:01:07] [PASSED] Above the allocation limit
[10:01:07] [PASSED] One page, with coherent DMA mappings enabled
[10:01:07] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[10:01:07] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[10:01:07] [PASSED] ttm_pool_alloc_order_caching_match
[10:01:07] [PASSED] ttm_pool_alloc_caching_mismatch
[10:01:07] [PASSED] ttm_pool_alloc_order_mismatch
[10:01:07] [PASSED] ttm_pool_free_dma_alloc
[10:01:07] [PASSED] ttm_pool_free_no_dma_alloc
[10:01:07] [PASSED] ttm_pool_fini_basic
[10:01:07] ==================== [PASSED] ttm_pool =====================
[10:01:07] ================ ttm_resource (8 subtests) =================
[10:01:07] ================= ttm_resource_init_basic =================
[10:01:07] [PASSED] Init resource in TTM_PL_SYSTEM
[10:01:07] [PASSED] Init resource in TTM_PL_VRAM
[10:01:07] [PASSED] Init resource in a private placement
[10:01:07] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[10:01:07] ============= [PASSED] ttm_resource_init_basic =============
[10:01:07] [PASSED] ttm_resource_init_pinned
[10:01:07] [PASSED] ttm_resource_fini_basic
[10:01:07] [PASSED] ttm_resource_manager_init_basic
[10:01:07] [PASSED] ttm_resource_manager_usage_basic
[10:01:07] [PASSED] ttm_resource_manager_set_used_basic
[10:01:07] [PASSED] ttm_sys_man_alloc_basic
[10:01:07] [PASSED] ttm_sys_man_free_basic
[10:01:07] ================== [PASSED] ttm_resource ===================
[10:01:07] =================== ttm_tt (15 subtests) ===================
[10:01:07] ==================== ttm_tt_init_basic ====================
[10:01:07] [PASSED] Page-aligned size
[10:01:07] [PASSED] Extra pages requested
[10:01:07] ================ [PASSED] ttm_tt_init_basic ================
[10:01:07] [PASSED] ttm_tt_init_misaligned
[10:01:07] [PASSED] ttm_tt_fini_basic
[10:01:07] [PASSED] ttm_tt_fini_sg
[10:01:07] [PASSED] ttm_tt_fini_shmem
[10:01:07] [PASSED] ttm_tt_create_basic
[10:01:07] [PASSED] ttm_tt_create_invalid_bo_type
[10:01:07] [PASSED] ttm_tt_create_ttm_exists
[10:01:07] [PASSED] ttm_tt_create_failed
[10:01:07] [PASSED] ttm_tt_destroy_basic
[10:01:07] [PASSED] ttm_tt_populate_null_ttm
[10:01:07] [PASSED] ttm_tt_populate_populated_ttm
[10:01:07] [PASSED] ttm_tt_unpopulate_basic
[10:01:07] [PASSED] ttm_tt_unpopulate_empty_ttm
[10:01:07] [PASSED] ttm_tt_swapin_basic
[10:01:07] ===================== [PASSED] ttm_tt ======================
[10:01:07] =================== ttm_bo (14 subtests) ===================
[10:01:07] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[10:01:07] [PASSED] Cannot be interrupted and sleeps
[10:01:07] [PASSED] Cannot be interrupted, locks straight away
[10:01:07] [PASSED] Can be interrupted, sleeps
[10:01:07] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[10:01:07] [PASSED] ttm_bo_reserve_locked_no_sleep
[10:01:07] [PASSED] ttm_bo_reserve_no_wait_ticket
[10:01:07] [PASSED] ttm_bo_reserve_double_resv
[10:01:07] [PASSED] ttm_bo_reserve_interrupted
[10:01:07] [PASSED] ttm_bo_reserve_deadlock
[10:01:07] [PASSED] ttm_bo_unreserve_basic
[10:01:07] [PASSED] ttm_bo_unreserve_pinned
[10:01:07] [PASSED] ttm_bo_unreserve_bulk
[10:01:07] [PASSED] ttm_bo_fini_basic
[10:01:07] [PASSED] ttm_bo_fini_shared_resv
[10:01:07] [PASSED] ttm_bo_pin_basic
[10:01:07] [PASSED] ttm_bo_pin_unpin_resource
[10:01:07] [PASSED] ttm_bo_multiple_pin_one_unpin
[10:01:07] ===================== [PASSED] ttm_bo ======================
[10:01:07] ============== ttm_bo_validate (21 subtests) ===============
[10:01:07] ============== ttm_bo_init_reserved_sys_man ===============
[10:01:07] [PASSED] Buffer object for userspace
[10:01:07] [PASSED] Kernel buffer object
[10:01:07] [PASSED] Shared buffer object
[10:01:07] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[10:01:07] ============== ttm_bo_init_reserved_mock_man ==============
[10:01:07] [PASSED] Buffer object for userspace
[10:01:07] [PASSED] Kernel buffer object
[10:01:07] [PASSED] Shared buffer object
[10:01:07] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[10:01:07] [PASSED] ttm_bo_init_reserved_resv
[10:01:07] ================== ttm_bo_validate_basic ==================
[10:01:07] [PASSED] Buffer object for userspace
[10:01:07] [PASSED] Kernel buffer object
[10:01:07] [PASSED] Shared buffer object
[10:01:07] ============== [PASSED] ttm_bo_validate_basic ==============
[10:01:07] [PASSED] ttm_bo_validate_invalid_placement
[10:01:07] ============= ttm_bo_validate_same_placement ==============
[10:01:07] [PASSED] System manager
[10:01:07] [PASSED] VRAM manager
[10:01:07] ========= [PASSED] ttm_bo_validate_same_placement ==========
[10:01:07] [PASSED] ttm_bo_validate_failed_alloc
[10:01:07] [PASSED] ttm_bo_validate_pinned
[10:01:07] [PASSED] ttm_bo_validate_busy_placement
[10:01:07] ================ ttm_bo_validate_multihop =================
[10:01:07] [PASSED] Buffer object for userspace
[10:01:07] [PASSED] Kernel buffer object
[10:01:07] [PASSED] Shared buffer object
[10:01:07] ============ [PASSED] ttm_bo_validate_multihop =============
[10:01:07] ========== ttm_bo_validate_no_placement_signaled ==========
[10:01:07] [PASSED] Buffer object in system domain, no page vector
[10:01:07] [PASSED] Buffer object in system domain with an existing page vector
[10:01:07] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[10:01:07] ======== ttm_bo_validate_no_placement_not_signaled ========
[10:01:07] [PASSED] Buffer object for userspace
[10:01:07] [PASSED] Kernel buffer object
[10:01:07] [PASSED] Shared buffer object
[10:01:07] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[10:01:07] [PASSED] ttm_bo_validate_move_fence_signaled
[10:01:07] ========= ttm_bo_validate_move_fence_not_signaled =========
[10:01:07] [PASSED] Waits for GPU
[10:01:07] [PASSED] Tries to lock straight away
[10:01:07] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[10:01:07] [PASSED] ttm_bo_validate_happy_evict
[10:01:07] [PASSED] ttm_bo_validate_all_pinned_evict
[10:01:07] [PASSED] ttm_bo_validate_allowed_only_evict
[10:01:07] [PASSED] ttm_bo_validate_deleted_evict
[10:01:07] [PASSED] ttm_bo_validate_busy_domain_evict
[10:01:07] [PASSED] ttm_bo_validate_evict_gutting
[10:01:07] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[10:01:07] ================= [PASSED] ttm_bo_validate =================
[10:01:07] ============================================================
[10:01:07] Testing complete. Ran 101 tests: passed: 101
[10:01:07] Elapsed time: 11.516s total, 1.705s configuring, 9.545s building, 0.226s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 6+ messages in thread
* ✓ Xe.CI.BAT: success for drm/i915/vrr: Configure VRR timings after enabling TRANS_DDI_FUNC_CTL
2026-03-03 9:54 [PATCH] drm/i915/vrr: Configure VRR timings after enabling TRANS_DDI_FUNC_CTL Ville Syrjala
2026-03-03 9:59 ` ✗ CI.checkpatch: warning for " Patchwork
2026-03-03 10:01 ` ✓ CI.KUnit: success " Patchwork
@ 2026-03-03 10:55 ` Patchwork
2026-03-04 6:06 ` [PATCH] " Nautiyal, Ankit K
3 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2026-03-03 10:55 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 990 bytes --]
== Series Details ==
Series: drm/i915/vrr: Configure VRR timings after enabling TRANS_DDI_FUNC_CTL
URL : https://patchwork.freedesktop.org/series/162481/
State : success
== Summary ==
CI Bug Log - changes from xe-4648-a0812623719f56a50fb9dd57003b9d9abd61c093_BAT -> xe-pw-162481v1_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (14 -> 12)
------------------------------
Missing (2): bat-dg2-oem2 bat-atsm-2
Changes
-------
No changes found
Build changes
-------------
* Linux: xe-4648-a0812623719f56a50fb9dd57003b9d9abd61c093 -> xe-pw-162481v1
IGT_8777: a50285a68dbef0fe11140adef4016a756f57b324 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-4648-a0812623719f56a50fb9dd57003b9d9abd61c093: a0812623719f56a50fb9dd57003b9d9abd61c093
xe-pw-162481v1: 162481v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162481v1/index.html
[-- Attachment #2: Type: text/html, Size: 1538 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915/vrr: Configure VRR timings after enabling TRANS_DDI_FUNC_CTL
2026-03-03 9:54 [PATCH] drm/i915/vrr: Configure VRR timings after enabling TRANS_DDI_FUNC_CTL Ville Syrjala
` (2 preceding siblings ...)
2026-03-03 10:55 ` ✓ Xe.CI.BAT: " Patchwork
@ 2026-03-04 6:06 ` Nautiyal, Ankit K
2026-03-04 13:52 ` Ville Syrjälä
3 siblings, 1 reply; 6+ messages in thread
From: Nautiyal, Ankit K @ 2026-03-04 6:06 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: intel-xe, stable, Benjamin Tissoires
On 3/3/2026 3:24 PM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Apparently ICL may hang with an MCE if we write TRANS_VRR_VMAX/FLIPLINE
> before enabling TRANS_DDI_FUNC_CTL.
>
> Personally I was only able to reproduce a hang (on an Dell XPS 7390
> 2-in-1) with an external display connected via a dock using a dodgy
> type-C cable that made the link training fail. After the failed
> link training the machine would hang. TGL seemed immune to the
> problem for whatever reason.
>
> BSpec does tell us to configure VRR after enabling TRANS_DDI_FUNC_CTL
> as well. The DMC firmware also does the VRR restore in two stages:
> - first stage seems to be unconditional and includes TRANS_VRR_CTL
> and a few other VRR registers, among other things
> - second stage is conditional on the DDI being enabled,
> and includes TRANS_DDI_FUNC_CTL and TRANS_VRR_VMAX/VMIN/FLIPLINE,
> among other things
>
> So let's reorder the steps to match to avoid the hang, and
> toss in an extra WARN to make sure we don't screw this up later.
>
> BSpec: 22243
> Cc: stable@vger.kernel.org
> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Reported-by: Benjamin Tissoires <bentiss@kernel.org>
> Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15777
> Tested-by: Benjamin Tissoires <bentiss@kernel.org>
> Fixes: dda7dcd9da73 ("drm/i915/vrr: Use fixed timings for platforms that support VRR")
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
You are right. VRR timing registers are indeed supposed to be programmed
after TRANS_DDI_FUNC_CTL.
Thanks for catching this, Ville, and thanks Benjamin for the bisection.
Change looks good to me.
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 1 -
> drivers/gpu/drm/i915/display/intel_vrr.c | 14 ++++++++++++++
> 2 files changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 27354585ba92..138ee7dd1977 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1637,7 +1637,6 @@ static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta
> }
>
> intel_set_transcoder_timings(crtc_state);
> - intel_vrr_set_transcoder_timings(crtc_state);
>
> if (cpu_transcoder != TRANSCODER_EDP)
> intel_de_write(display, TRANS_MULT(display, cpu_transcoder),
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 00ca76dbdd6c..8a957804cb97 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -599,6 +599,18 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
> if (!HAS_VRR(display))
> return;
>
> + /*
> + * Bspec says:
> + * "(note: VRR needs to be programmed after
> + * TRANS_DDI_FUNC_CTL and before TRANS_CONF)."
> + *
> + * In practice it turns out that ICL can hang if
> + * TRANS_VRR_VMAX/FLIPLINE are written before
> + * enabling TRANS_DDI_FUNC_CTL.
> + */
> + drm_WARN_ON(display->drm,
> + !(intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & TRANS_DDI_FUNC_ENABLE));
> +
> /*
> * This bit seems to have two meanings depending on the platform:
> * TGL: generate VRR "safe window" for DSB vblank waits
> @@ -961,6 +973,8 @@ void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
>
> + intel_vrr_set_transcoder_timings(crtc_state);
> +
> if (!intel_vrr_possible(crtc_state))
> return;
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915/vrr: Configure VRR timings after enabling TRANS_DDI_FUNC_CTL
2026-03-04 6:06 ` [PATCH] " Nautiyal, Ankit K
@ 2026-03-04 13:52 ` Ville Syrjälä
0 siblings, 0 replies; 6+ messages in thread
From: Ville Syrjälä @ 2026-03-04 13:52 UTC (permalink / raw)
To: Nautiyal, Ankit K; +Cc: intel-gfx, intel-xe, stable, Benjamin Tissoires
On Wed, Mar 04, 2026 at 11:36:12AM +0530, Nautiyal, Ankit K wrote:
>
> On 3/3/2026 3:24 PM, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Apparently ICL may hang with an MCE if we write TRANS_VRR_VMAX/FLIPLINE
> > before enabling TRANS_DDI_FUNC_CTL.
> >
> > Personally I was only able to reproduce a hang (on an Dell XPS 7390
> > 2-in-1) with an external display connected via a dock using a dodgy
> > type-C cable that made the link training fail. After the failed
> > link training the machine would hang. TGL seemed immune to the
> > problem for whatever reason.
> >
> > BSpec does tell us to configure VRR after enabling TRANS_DDI_FUNC_CTL
> > as well. The DMC firmware also does the VRR restore in two stages:
> > - first stage seems to be unconditional and includes TRANS_VRR_CTL
> > and a few other VRR registers, among other things
> > - second stage is conditional on the DDI being enabled,
> > and includes TRANS_DDI_FUNC_CTL and TRANS_VRR_VMAX/VMIN/FLIPLINE,
> > among other things
> >
> > So let's reorder the steps to match to avoid the hang, and
> > toss in an extra WARN to make sure we don't screw this up later.
> >
> > BSpec: 22243
> > Cc: stable@vger.kernel.org
> > Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > Reported-by: Benjamin Tissoires <bentiss@kernel.org>
> > Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15777
> > Tested-by: Benjamin Tissoires <bentiss@kernel.org>
> > Fixes: dda7dcd9da73 ("drm/i915/vrr: Use fixed timings for platforms that support VRR")
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> You are right. VRR timing registers are indeed supposed to be programmed
> after TRANS_DDI_FUNC_CTL.
>
> Thanks for catching this, Ville, and thanks Benjamin for the bisection.
>
> Change looks good to me.
>
> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Pushed.
Thanks for the review, and the bug report.
>
>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 1 -
> > drivers/gpu/drm/i915/display/intel_vrr.c | 14 ++++++++++++++
> > 2 files changed, 14 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index 27354585ba92..138ee7dd1977 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -1637,7 +1637,6 @@ static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta
> > }
> >
> > intel_set_transcoder_timings(crtc_state);
> > - intel_vrr_set_transcoder_timings(crtc_state);
> >
> > if (cpu_transcoder != TRANSCODER_EDP)
> > intel_de_write(display, TRANS_MULT(display, cpu_transcoder),
> > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> > index 00ca76dbdd6c..8a957804cb97 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> > @@ -599,6 +599,18 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
> > if (!HAS_VRR(display))
> > return;
> >
> > + /*
> > + * Bspec says:
> > + * "(note: VRR needs to be programmed after
> > + * TRANS_DDI_FUNC_CTL and before TRANS_CONF)."
> > + *
> > + * In practice it turns out that ICL can hang if
> > + * TRANS_VRR_VMAX/FLIPLINE are written before
> > + * enabling TRANS_DDI_FUNC_CTL.
> > + */
> > + drm_WARN_ON(display->drm,
> > + !(intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & TRANS_DDI_FUNC_ENABLE));
> > +
> > /*
> > * This bit seems to have two meanings depending on the platform:
> > * TGL: generate VRR "safe window" for DSB vblank waits
> > @@ -961,6 +973,8 @@ void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state)
> > {
> > struct intel_display *display = to_intel_display(crtc_state);
> >
> > + intel_vrr_set_transcoder_timings(crtc_state);
> > +
> > if (!intel_vrr_possible(crtc_state))
> > return;
> >
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2026-03-04 13:52 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-03-03 9:54 [PATCH] drm/i915/vrr: Configure VRR timings after enabling TRANS_DDI_FUNC_CTL Ville Syrjala
2026-03-03 9:59 ` ✗ CI.checkpatch: warning for " Patchwork
2026-03-03 10:01 ` ✓ CI.KUnit: success " Patchwork
2026-03-03 10:55 ` ✓ Xe.CI.BAT: " Patchwork
2026-03-04 6:06 ` [PATCH] " Nautiyal, Ankit K
2026-03-04 13:52 ` Ville Syrjälä
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox